1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
16 #include "X86ISelLowering.h"
18 #include "X86InstrBuilder.h"
19 #include "X86TargetMachine.h"
20 #include "X86TargetObjectFile.h"
21 #include "Utils/X86ShuffleDecode.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/GlobalAlias.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/Function.h"
28 #include "llvm/Instructions.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/LLVMContext.h"
31 #include "llvm/CodeGen/IntrinsicLowering.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineFunction.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineJumpTableInfo.h"
36 #include "llvm/CodeGen/MachineModuleInfo.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/MC/MCAsmInfo.h"
39 #include "llvm/MC/MCContext.h"
40 #include "llvm/MC/MCExpr.h"
41 #include "llvm/MC/MCSymbol.h"
42 #include "llvm/ADT/SmallSet.h"
43 #include "llvm/ADT/Statistic.h"
44 #include "llvm/ADT/StringExtras.h"
45 #include "llvm/ADT/VariadicFunction.h"
46 #include "llvm/Support/CallSite.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/MathExtras.h"
50 #include "llvm/Target/TargetOptions.h"
54 STATISTIC(NumTailCalls, "Number of tail calls");
56 // Forward declarations.
57 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
60 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
61 /// sets things up to match to an AVX VEXTRACTF128 instruction or a
62 /// simple subregister reference. Idx is an index in the 128 bits we
63 /// want. It need not be aligned to a 128-bit bounday. That makes
64 /// lowering EXTRACT_VECTOR_ELT operations easier.
65 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
66 SelectionDAG &DAG, DebugLoc dl) {
67 EVT VT = Vec.getValueType();
68 assert(VT.getSizeInBits() == 256 && "Unexpected vector size!");
69 EVT ElVT = VT.getVectorElementType();
70 unsigned Factor = VT.getSizeInBits()/128;
71 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
72 VT.getVectorNumElements()/Factor);
74 // Extract from UNDEF is UNDEF.
75 if (Vec.getOpcode() == ISD::UNDEF)
76 return DAG.getUNDEF(ResultVT);
78 // Extract the relevant 128 bits. Generate an EXTRACT_SUBVECTOR
79 // we can match to VEXTRACTF128.
80 unsigned ElemsPerChunk = 128 / ElVT.getSizeInBits();
82 // This is the index of the first element of the 128-bit chunk
84 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / 128)
87 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
88 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
94 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
95 /// sets things up to match to an AVX VINSERTF128 instruction or a
96 /// simple superregister reference. Idx is an index in the 128 bits
97 /// we want. It need not be aligned to a 128-bit bounday. That makes
98 /// lowering INSERT_VECTOR_ELT operations easier.
99 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
100 unsigned IdxVal, SelectionDAG &DAG,
102 // Inserting UNDEF is Result
103 if (Vec.getOpcode() == ISD::UNDEF)
106 EVT VT = Vec.getValueType();
107 assert(VT.getSizeInBits() == 128 && "Unexpected vector size!");
109 EVT ElVT = VT.getVectorElementType();
110 EVT ResultVT = Result.getValueType();
112 // Insert the relevant 128 bits.
113 unsigned ElemsPerChunk = 128/ElVT.getSizeInBits();
115 // This is the index of the first element of the 128-bit chunk
117 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/128)
120 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
121 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
125 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
126 /// instructions. This is used because creating CONCAT_VECTOR nodes of
127 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
128 /// large BUILD_VECTORS.
129 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
130 unsigned NumElems, SelectionDAG &DAG,
132 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
133 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
136 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
137 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
138 bool is64Bit = Subtarget->is64Bit();
140 if (Subtarget->isTargetEnvMacho()) {
142 return new X8664_MachoTargetObjectFile();
143 return new TargetLoweringObjectFileMachO();
146 if (Subtarget->isTargetLinux())
147 return new X86LinuxTargetObjectFile();
148 if (Subtarget->isTargetELF())
149 return new TargetLoweringObjectFileELF();
150 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
151 return new TargetLoweringObjectFileCOFF();
152 llvm_unreachable("unknown subtarget type");
155 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
156 : TargetLowering(TM, createTLOF(TM)) {
157 Subtarget = &TM.getSubtarget<X86Subtarget>();
158 X86ScalarSSEf64 = Subtarget->hasSSE2();
159 X86ScalarSSEf32 = Subtarget->hasSSE1();
160 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
162 RegInfo = TM.getRegisterInfo();
163 TD = getTargetData();
165 // Set up the TargetLowering object.
166 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
168 // X86 is weird, it always uses i8 for shift amounts and setcc results.
169 setBooleanContents(ZeroOrOneBooleanContent);
170 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
171 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
173 // For 64-bit since we have so many registers use the ILP scheduler, for
174 // 32-bit code use the register pressure specific scheduling.
175 // For Atom, always use ILP scheduling.
176 if (Subtarget->isAtom())
177 setSchedulingPreference(Sched::ILP);
178 else if (Subtarget->is64Bit())
179 setSchedulingPreference(Sched::ILP);
181 setSchedulingPreference(Sched::RegPressure);
182 setStackPointerRegisterToSaveRestore(X86StackPtr);
184 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) {
185 // Setup Windows compiler runtime calls.
186 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
187 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
188 setLibcallName(RTLIB::SREM_I64, "_allrem");
189 setLibcallName(RTLIB::UREM_I64, "_aullrem");
190 setLibcallName(RTLIB::MUL_I64, "_allmul");
191 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
192 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
193 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
194 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
195 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
197 // The _ftol2 runtime function has an unusual calling conv, which
198 // is modeled by a special pseudo-instruction.
199 setLibcallName(RTLIB::FPTOUINT_F64_I64, 0);
200 setLibcallName(RTLIB::FPTOUINT_F32_I64, 0);
201 setLibcallName(RTLIB::FPTOUINT_F64_I32, 0);
202 setLibcallName(RTLIB::FPTOUINT_F32_I32, 0);
205 if (Subtarget->isTargetDarwin()) {
206 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
207 setUseUnderscoreSetJmp(false);
208 setUseUnderscoreLongJmp(false);
209 } else if (Subtarget->isTargetMingw()) {
210 // MS runtime is weird: it exports _setjmp, but longjmp!
211 setUseUnderscoreSetJmp(true);
212 setUseUnderscoreLongJmp(false);
214 setUseUnderscoreSetJmp(true);
215 setUseUnderscoreLongJmp(true);
218 // Set up the register classes.
219 addRegisterClass(MVT::i8, &X86::GR8RegClass);
220 addRegisterClass(MVT::i16, &X86::GR16RegClass);
221 addRegisterClass(MVT::i32, &X86::GR32RegClass);
222 if (Subtarget->is64Bit())
223 addRegisterClass(MVT::i64, &X86::GR64RegClass);
225 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
227 // We don't accept any truncstore of integer registers.
228 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
229 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
230 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
231 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
232 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
233 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
235 // SETOEQ and SETUNE require checking two conditions.
236 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
237 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
238 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
239 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
240 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
241 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
243 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
245 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
246 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
247 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
249 if (Subtarget->is64Bit()) {
250 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
251 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
252 } else if (!TM.Options.UseSoftFloat) {
253 // We have an algorithm for SSE2->double, and we turn this into a
254 // 64-bit FILD followed by conditional FADD for other targets.
255 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
256 // We have an algorithm for SSE2, and we turn this into a 64-bit
257 // FILD for other targets.
258 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
261 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
263 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
264 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
266 if (!TM.Options.UseSoftFloat) {
267 // SSE has no i16 to fp conversion, only i32
268 if (X86ScalarSSEf32) {
269 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
270 // f32 and f64 cases are Legal, f80 case is not
271 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
273 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
274 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
277 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
278 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
281 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
282 // are Legal, f80 is custom lowered.
283 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
284 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
286 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
288 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
289 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
291 if (X86ScalarSSEf32) {
292 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
293 // f32 and f64 cases are Legal, f80 case is not
294 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
296 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
297 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
300 // Handle FP_TO_UINT by promoting the destination to a larger signed
302 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
303 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
304 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
306 if (Subtarget->is64Bit()) {
307 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
308 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
309 } else if (!TM.Options.UseSoftFloat) {
310 // Since AVX is a superset of SSE3, only check for SSE here.
311 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
312 // Expand FP_TO_UINT into a select.
313 // FIXME: We would like to use a Custom expander here eventually to do
314 // the optimal thing for SSE vs. the default expansion in the legalizer.
315 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
317 // With SSE3 we can use fisttpll to convert to a signed i64; without
318 // SSE, we're stuck with a fistpll.
319 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
322 if (isTargetFTOL()) {
323 // Use the _ftol2 runtime function, which has a pseudo-instruction
324 // to handle its weird calling convention.
325 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
328 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
329 if (!X86ScalarSSEf64) {
330 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
331 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
332 if (Subtarget->is64Bit()) {
333 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
334 // Without SSE, i64->f64 goes through memory.
335 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
339 // Scalar integer divide and remainder are lowered to use operations that
340 // produce two results, to match the available instructions. This exposes
341 // the two-result form to trivial CSE, which is able to combine x/y and x%y
342 // into a single instruction.
344 // Scalar integer multiply-high is also lowered to use two-result
345 // operations, to match the available instructions. However, plain multiply
346 // (low) operations are left as Legal, as there are single-result
347 // instructions for this in x86. Using the two-result multiply instructions
348 // when both high and low results are needed must be arranged by dagcombine.
349 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
351 setOperationAction(ISD::MULHS, VT, Expand);
352 setOperationAction(ISD::MULHU, VT, Expand);
353 setOperationAction(ISD::SDIV, VT, Expand);
354 setOperationAction(ISD::UDIV, VT, Expand);
355 setOperationAction(ISD::SREM, VT, Expand);
356 setOperationAction(ISD::UREM, VT, Expand);
358 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
359 setOperationAction(ISD::ADDC, VT, Custom);
360 setOperationAction(ISD::ADDE, VT, Custom);
361 setOperationAction(ISD::SUBC, VT, Custom);
362 setOperationAction(ISD::SUBE, VT, Custom);
365 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
366 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
367 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
368 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
369 if (Subtarget->is64Bit())
370 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
371 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
372 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
373 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
374 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
375 setOperationAction(ISD::FREM , MVT::f32 , Expand);
376 setOperationAction(ISD::FREM , MVT::f64 , Expand);
377 setOperationAction(ISD::FREM , MVT::f80 , Expand);
378 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
380 // Promote the i8 variants and force them on up to i32 which has a shorter
382 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
383 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
384 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
385 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
386 if (Subtarget->hasBMI()) {
387 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
388 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
389 if (Subtarget->is64Bit())
390 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
392 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
393 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
394 if (Subtarget->is64Bit())
395 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
398 if (Subtarget->hasLZCNT()) {
399 // When promoting the i8 variants, force them to i32 for a shorter
401 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
402 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
403 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
404 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
405 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
406 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
407 if (Subtarget->is64Bit())
408 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
410 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
411 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
412 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
413 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
414 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
415 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
416 if (Subtarget->is64Bit()) {
417 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
418 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
422 if (Subtarget->hasPOPCNT()) {
423 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
425 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
426 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
427 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
428 if (Subtarget->is64Bit())
429 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
432 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
433 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
435 // These should be promoted to a larger select which is supported.
436 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
437 // X86 wants to expand cmov itself.
438 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
439 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
440 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
441 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
442 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
443 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
444 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
445 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
446 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
447 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
448 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
449 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
450 if (Subtarget->is64Bit()) {
451 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
452 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
454 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
457 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
458 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
459 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
460 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
461 if (Subtarget->is64Bit())
462 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
463 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
464 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
465 if (Subtarget->is64Bit()) {
466 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
467 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
468 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
469 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
470 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
472 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
473 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
474 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
475 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
476 if (Subtarget->is64Bit()) {
477 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
478 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
479 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
482 if (Subtarget->hasSSE1())
483 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
485 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom);
486 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
488 // On X86 and X86-64, atomic operations are lowered to locked instructions.
489 // Locked instructions, in turn, have implicit fence semantics (all memory
490 // operations are flushed before issuing the locked instruction, and they
491 // are not buffered), so we can fold away the common pattern of
492 // fence-atomic-fence.
493 setShouldFoldAtomicFences(true);
495 // Expand certain atomics
496 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
498 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom);
499 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
500 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
503 if (!Subtarget->is64Bit()) {
504 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
505 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
506 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
507 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
508 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
509 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
510 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
511 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
514 if (Subtarget->hasCmpxchg16b()) {
515 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom);
518 // FIXME - use subtarget debug flags
519 if (!Subtarget->isTargetDarwin() &&
520 !Subtarget->isTargetELF() &&
521 !Subtarget->isTargetCygMing()) {
522 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
525 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
526 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
527 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
528 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
529 if (Subtarget->is64Bit()) {
530 setExceptionPointerRegister(X86::RAX);
531 setExceptionSelectorRegister(X86::RDX);
533 setExceptionPointerRegister(X86::EAX);
534 setExceptionSelectorRegister(X86::EDX);
536 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
537 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
539 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
540 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
542 setOperationAction(ISD::TRAP, MVT::Other, Legal);
544 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
545 setOperationAction(ISD::VASTART , MVT::Other, Custom);
546 setOperationAction(ISD::VAEND , MVT::Other, Expand);
547 if (Subtarget->is64Bit()) {
548 setOperationAction(ISD::VAARG , MVT::Other, Custom);
549 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
551 setOperationAction(ISD::VAARG , MVT::Other, Expand);
552 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
555 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
556 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
558 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
559 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
560 MVT::i64 : MVT::i32, Custom);
561 else if (TM.Options.EnableSegmentedStacks)
562 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
563 MVT::i64 : MVT::i32, Custom);
565 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
566 MVT::i64 : MVT::i32, Expand);
568 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
569 // f32 and f64 use SSE.
570 // Set up the FP register classes.
571 addRegisterClass(MVT::f32, &X86::FR32RegClass);
572 addRegisterClass(MVT::f64, &X86::FR64RegClass);
574 // Use ANDPD to simulate FABS.
575 setOperationAction(ISD::FABS , MVT::f64, Custom);
576 setOperationAction(ISD::FABS , MVT::f32, Custom);
578 // Use XORP to simulate FNEG.
579 setOperationAction(ISD::FNEG , MVT::f64, Custom);
580 setOperationAction(ISD::FNEG , MVT::f32, Custom);
582 // Use ANDPD and ORPD to simulate FCOPYSIGN.
583 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
584 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
586 // Lower this to FGETSIGNx86 plus an AND.
587 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
588 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
590 // We don't support sin/cos/fmod
591 setOperationAction(ISD::FSIN , MVT::f64, Expand);
592 setOperationAction(ISD::FCOS , MVT::f64, Expand);
593 setOperationAction(ISD::FSIN , MVT::f32, Expand);
594 setOperationAction(ISD::FCOS , MVT::f32, Expand);
596 // Expand FP immediates into loads from the stack, except for the special
598 addLegalFPImmediate(APFloat(+0.0)); // xorpd
599 addLegalFPImmediate(APFloat(+0.0f)); // xorps
600 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
601 // Use SSE for f32, x87 for f64.
602 // Set up the FP register classes.
603 addRegisterClass(MVT::f32, &X86::FR32RegClass);
604 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
606 // Use ANDPS to simulate FABS.
607 setOperationAction(ISD::FABS , MVT::f32, Custom);
609 // Use XORP to simulate FNEG.
610 setOperationAction(ISD::FNEG , MVT::f32, Custom);
612 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
614 // Use ANDPS and ORPS to simulate FCOPYSIGN.
615 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
616 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
618 // We don't support sin/cos/fmod
619 setOperationAction(ISD::FSIN , MVT::f32, Expand);
620 setOperationAction(ISD::FCOS , MVT::f32, Expand);
622 // Special cases we handle for FP constants.
623 addLegalFPImmediate(APFloat(+0.0f)); // xorps
624 addLegalFPImmediate(APFloat(+0.0)); // FLD0
625 addLegalFPImmediate(APFloat(+1.0)); // FLD1
626 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
627 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
629 if (!TM.Options.UnsafeFPMath) {
630 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
631 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
633 } else if (!TM.Options.UseSoftFloat) {
634 // f32 and f64 in x87.
635 // Set up the FP register classes.
636 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
637 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
639 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
640 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
641 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
642 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
644 if (!TM.Options.UnsafeFPMath) {
645 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
646 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
648 addLegalFPImmediate(APFloat(+0.0)); // FLD0
649 addLegalFPImmediate(APFloat(+1.0)); // FLD1
650 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
651 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
652 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
653 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
654 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
655 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
658 // We don't support FMA.
659 setOperationAction(ISD::FMA, MVT::f64, Expand);
660 setOperationAction(ISD::FMA, MVT::f32, Expand);
662 // Long double always uses X87.
663 if (!TM.Options.UseSoftFloat) {
664 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
665 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
666 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
668 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
669 addLegalFPImmediate(TmpFlt); // FLD0
671 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
674 APFloat TmpFlt2(+1.0);
675 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
677 addLegalFPImmediate(TmpFlt2); // FLD1
678 TmpFlt2.changeSign();
679 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
682 if (!TM.Options.UnsafeFPMath) {
683 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
684 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
687 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
688 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
689 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
690 setOperationAction(ISD::FRINT, MVT::f80, Expand);
691 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
692 setOperationAction(ISD::FMA, MVT::f80, Expand);
695 // Always use a library call for pow.
696 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
697 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
698 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
700 setOperationAction(ISD::FLOG, MVT::f80, Expand);
701 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
702 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
703 setOperationAction(ISD::FEXP, MVT::f80, Expand);
704 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
706 // First set operation action for all vector types to either promote
707 // (for widening) or expand (for scalarization). Then we will selectively
708 // turn on ones that can be effectively codegen'd.
709 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
710 VT <= MVT::LAST_VECTOR_VALUETYPE; ++VT) {
711 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
712 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
713 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
714 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
715 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
716 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
717 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
718 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
719 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
720 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
721 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
722 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
723 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
724 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
725 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
726 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
727 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
728 setOperationAction(ISD::INSERT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
729 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
730 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
731 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
732 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
733 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
734 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
735 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
736 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
737 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
738 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
739 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
740 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
741 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
742 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
743 setOperationAction(ISD::CTTZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand);
744 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
745 setOperationAction(ISD::CTLZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand);
746 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
747 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
748 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
749 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
750 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
751 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
752 setOperationAction(ISD::SETCC, (MVT::SimpleValueType)VT, Expand);
753 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
754 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
755 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
756 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
757 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
758 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand);
759 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand);
760 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
761 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
762 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand);
763 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand);
764 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand);
765 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand);
766 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand);
767 setOperationAction(ISD::VSELECT, (MVT::SimpleValueType)VT, Expand);
768 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
769 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
770 setTruncStoreAction((MVT::SimpleValueType)VT,
771 (MVT::SimpleValueType)InnerVT, Expand);
772 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
773 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
774 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
777 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
778 // with -msoft-float, disable use of MMX as well.
779 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
780 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
781 // No operations on x86mmx supported, everything uses intrinsics.
784 // MMX-sized vectors (other than x86mmx) are expected to be expanded
785 // into smaller operations.
786 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
787 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
788 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
789 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
790 setOperationAction(ISD::AND, MVT::v8i8, Expand);
791 setOperationAction(ISD::AND, MVT::v4i16, Expand);
792 setOperationAction(ISD::AND, MVT::v2i32, Expand);
793 setOperationAction(ISD::AND, MVT::v1i64, Expand);
794 setOperationAction(ISD::OR, MVT::v8i8, Expand);
795 setOperationAction(ISD::OR, MVT::v4i16, Expand);
796 setOperationAction(ISD::OR, MVT::v2i32, Expand);
797 setOperationAction(ISD::OR, MVT::v1i64, Expand);
798 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
799 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
800 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
801 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
802 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
803 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
804 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
805 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
806 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
807 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
808 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
809 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
810 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
811 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
812 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
813 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
814 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
816 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
817 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
819 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
820 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
821 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
822 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
823 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
824 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
825 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
826 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
827 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
828 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
829 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
830 setOperationAction(ISD::SETCC, MVT::v4f32, Custom);
833 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
834 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
836 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
837 // registers cannot be used even for integer operations.
838 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
839 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
840 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
841 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
843 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
844 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
845 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
846 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
847 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
848 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
849 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
850 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
851 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
852 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
853 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
854 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
855 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
856 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
857 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
858 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
860 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
861 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
862 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
863 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
865 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
866 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
867 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
868 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
869 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
871 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom);
872 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom);
873 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom);
874 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom);
875 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
877 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
878 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
879 EVT VT = (MVT::SimpleValueType)i;
880 // Do not attempt to custom lower non-power-of-2 vectors
881 if (!isPowerOf2_32(VT.getVectorNumElements()))
883 // Do not attempt to custom lower non-128-bit vectors
884 if (!VT.is128BitVector())
886 setOperationAction(ISD::BUILD_VECTOR,
887 VT.getSimpleVT().SimpleTy, Custom);
888 setOperationAction(ISD::VECTOR_SHUFFLE,
889 VT.getSimpleVT().SimpleTy, Custom);
890 setOperationAction(ISD::EXTRACT_VECTOR_ELT,
891 VT.getSimpleVT().SimpleTy, Custom);
894 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
895 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
896 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
897 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
898 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
899 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
901 if (Subtarget->is64Bit()) {
902 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
903 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
906 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
907 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
908 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
911 // Do not attempt to promote non-128-bit vectors
912 if (!VT.is128BitVector())
915 setOperationAction(ISD::AND, SVT, Promote);
916 AddPromotedToType (ISD::AND, SVT, MVT::v2i64);
917 setOperationAction(ISD::OR, SVT, Promote);
918 AddPromotedToType (ISD::OR, SVT, MVT::v2i64);
919 setOperationAction(ISD::XOR, SVT, Promote);
920 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64);
921 setOperationAction(ISD::LOAD, SVT, Promote);
922 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64);
923 setOperationAction(ISD::SELECT, SVT, Promote);
924 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64);
927 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
929 // Custom lower v2i64 and v2f64 selects.
930 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
931 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
932 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
933 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
935 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
936 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
939 if (Subtarget->hasSSE41()) {
940 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
941 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
942 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
943 setOperationAction(ISD::FRINT, MVT::f32, Legal);
944 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
945 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
946 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
947 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
948 setOperationAction(ISD::FRINT, MVT::f64, Legal);
949 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
951 // FIXME: Do we need to handle scalar-to-vector here?
952 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
954 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
955 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal);
956 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
957 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
958 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
960 // i8 and i16 vectors are custom , because the source register and source
961 // source memory operand types are not the same width. f32 vectors are
962 // custom since the immediate controlling the insert encodes additional
964 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
965 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
966 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
967 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
969 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
970 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
971 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
972 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
974 // FIXME: these should be Legal but thats only for the case where
975 // the index is constant. For now custom expand to deal with that.
976 if (Subtarget->is64Bit()) {
977 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
978 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
982 if (Subtarget->hasSSE2()) {
983 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
984 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
986 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
987 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
989 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
990 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
992 if (Subtarget->hasAVX2()) {
993 setOperationAction(ISD::SRL, MVT::v2i64, Legal);
994 setOperationAction(ISD::SRL, MVT::v4i32, Legal);
996 setOperationAction(ISD::SHL, MVT::v2i64, Legal);
997 setOperationAction(ISD::SHL, MVT::v4i32, Legal);
999 setOperationAction(ISD::SRA, MVT::v4i32, Legal);
1001 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1002 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1004 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1005 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1007 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1011 if (Subtarget->hasSSE42())
1012 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
1014 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX()) {
1015 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1016 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1017 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1018 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1019 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1020 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1022 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1023 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1024 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1026 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1027 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1028 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1029 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1030 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1031 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1033 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1034 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1035 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1036 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1037 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1038 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1040 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1041 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1042 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1044 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f64, Custom);
1045 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i64, Custom);
1046 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom);
1047 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom);
1048 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i8, Custom);
1049 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i16, Custom);
1051 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1052 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1054 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1055 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1057 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1058 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1060 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1061 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1062 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1063 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1065 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1066 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1067 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1069 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal);
1070 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal);
1071 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal);
1072 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal);
1074 if (Subtarget->hasAVX2()) {
1075 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1076 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1077 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1078 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1080 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1081 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1082 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1083 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1085 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1086 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1087 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1088 // Don't lower v32i8 because there is no 128-bit byte mul
1090 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1092 setOperationAction(ISD::SRL, MVT::v4i64, Legal);
1093 setOperationAction(ISD::SRL, MVT::v8i32, Legal);
1095 setOperationAction(ISD::SHL, MVT::v4i64, Legal);
1096 setOperationAction(ISD::SHL, MVT::v8i32, Legal);
1098 setOperationAction(ISD::SRA, MVT::v8i32, Legal);
1100 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1101 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1102 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1103 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1105 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1106 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1107 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1108 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1110 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1111 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1112 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1113 // Don't lower v32i8 because there is no 128-bit byte mul
1115 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1116 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1118 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1119 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1121 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1124 // Custom lower several nodes for 256-bit types.
1125 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1126 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1127 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
1130 // Extract subvector is special because the value type
1131 // (result) is 128-bit but the source is 256-bit wide.
1132 if (VT.is128BitVector())
1133 setOperationAction(ISD::EXTRACT_SUBVECTOR, SVT, Custom);
1135 // Do not attempt to custom lower other non-256-bit vectors
1136 if (!VT.is256BitVector())
1139 setOperationAction(ISD::BUILD_VECTOR, SVT, Custom);
1140 setOperationAction(ISD::VECTOR_SHUFFLE, SVT, Custom);
1141 setOperationAction(ISD::INSERT_VECTOR_ELT, SVT, Custom);
1142 setOperationAction(ISD::EXTRACT_VECTOR_ELT, SVT, Custom);
1143 setOperationAction(ISD::SCALAR_TO_VECTOR, SVT, Custom);
1144 setOperationAction(ISD::INSERT_SUBVECTOR, SVT, Custom);
1147 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1148 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1149 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
1152 // Do not attempt to promote non-256-bit vectors
1153 if (!VT.is256BitVector())
1156 setOperationAction(ISD::AND, SVT, Promote);
1157 AddPromotedToType (ISD::AND, SVT, MVT::v4i64);
1158 setOperationAction(ISD::OR, SVT, Promote);
1159 AddPromotedToType (ISD::OR, SVT, MVT::v4i64);
1160 setOperationAction(ISD::XOR, SVT, Promote);
1161 AddPromotedToType (ISD::XOR, SVT, MVT::v4i64);
1162 setOperationAction(ISD::LOAD, SVT, Promote);
1163 AddPromotedToType (ISD::LOAD, SVT, MVT::v4i64);
1164 setOperationAction(ISD::SELECT, SVT, Promote);
1165 AddPromotedToType (ISD::SELECT, SVT, MVT::v4i64);
1169 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1170 // of this type with custom code.
1171 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1172 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1173 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1177 // We want to custom lower some of our intrinsics.
1178 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1181 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1182 // handle type legalization for these operations here.
1184 // FIXME: We really should do custom legalization for addition and
1185 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1186 // than generic legalization for 64-bit multiplication-with-overflow, though.
1187 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1188 // Add/Sub/Mul with overflow operations are custom lowered.
1190 setOperationAction(ISD::SADDO, VT, Custom);
1191 setOperationAction(ISD::UADDO, VT, Custom);
1192 setOperationAction(ISD::SSUBO, VT, Custom);
1193 setOperationAction(ISD::USUBO, VT, Custom);
1194 setOperationAction(ISD::SMULO, VT, Custom);
1195 setOperationAction(ISD::UMULO, VT, Custom);
1198 // There are no 8-bit 3-address imul/mul instructions
1199 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1200 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1202 if (!Subtarget->is64Bit()) {
1203 // These libcalls are not available in 32-bit.
1204 setLibcallName(RTLIB::SHL_I128, 0);
1205 setLibcallName(RTLIB::SRL_I128, 0);
1206 setLibcallName(RTLIB::SRA_I128, 0);
1209 // We have target-specific dag combine patterns for the following nodes:
1210 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1211 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1212 setTargetDAGCombine(ISD::VSELECT);
1213 setTargetDAGCombine(ISD::SELECT);
1214 setTargetDAGCombine(ISD::SHL);
1215 setTargetDAGCombine(ISD::SRA);
1216 setTargetDAGCombine(ISD::SRL);
1217 setTargetDAGCombine(ISD::OR);
1218 setTargetDAGCombine(ISD::AND);
1219 setTargetDAGCombine(ISD::ADD);
1220 setTargetDAGCombine(ISD::FADD);
1221 setTargetDAGCombine(ISD::FSUB);
1222 setTargetDAGCombine(ISD::SUB);
1223 setTargetDAGCombine(ISD::LOAD);
1224 setTargetDAGCombine(ISD::STORE);
1225 setTargetDAGCombine(ISD::ZERO_EXTEND);
1226 setTargetDAGCombine(ISD::ANY_EXTEND);
1227 setTargetDAGCombine(ISD::SIGN_EXTEND);
1228 setTargetDAGCombine(ISD::TRUNCATE);
1229 setTargetDAGCombine(ISD::UINT_TO_FP);
1230 setTargetDAGCombine(ISD::SINT_TO_FP);
1231 setTargetDAGCombine(ISD::SETCC);
1232 setTargetDAGCombine(ISD::FP_TO_SINT);
1233 if (Subtarget->is64Bit())
1234 setTargetDAGCombine(ISD::MUL);
1235 setTargetDAGCombine(ISD::XOR);
1237 computeRegisterProperties();
1239 // On Darwin, -Os means optimize for size without hurting performance,
1240 // do not reduce the limit.
1241 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1242 maxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1243 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1244 maxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1245 maxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1246 maxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1247 setPrefLoopAlignment(4); // 2^4 bytes.
1248 benefitFromCodePlacementOpt = true;
1250 // Predictable cmov don't hurt on atom because it's in-order.
1251 predictableSelectIsExpensive = !Subtarget->isAtom();
1253 setPrefFunctionAlignment(4); // 2^4 bytes.
1257 EVT X86TargetLowering::getSetCCResultType(EVT VT) const {
1258 if (!VT.isVector()) return MVT::i8;
1259 return VT.changeVectorElementTypeToInteger();
1263 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1264 /// the desired ByVal argument alignment.
1265 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1268 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1269 if (VTy->getBitWidth() == 128)
1271 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1272 unsigned EltAlign = 0;
1273 getMaxByValAlign(ATy->getElementType(), EltAlign);
1274 if (EltAlign > MaxAlign)
1275 MaxAlign = EltAlign;
1276 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1277 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1278 unsigned EltAlign = 0;
1279 getMaxByValAlign(STy->getElementType(i), EltAlign);
1280 if (EltAlign > MaxAlign)
1281 MaxAlign = EltAlign;
1288 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1289 /// function arguments in the caller parameter area. For X86, aggregates
1290 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1291 /// are at 4-byte boundaries.
1292 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1293 if (Subtarget->is64Bit()) {
1294 // Max of 8 and alignment of type.
1295 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1302 if (Subtarget->hasSSE1())
1303 getMaxByValAlign(Ty, Align);
1307 /// getOptimalMemOpType - Returns the target specific optimal type for load
1308 /// and store operations as a result of memset, memcpy, and memmove
1309 /// lowering. If DstAlign is zero that means it's safe to destination
1310 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1311 /// means there isn't a need to check it against alignment requirement,
1312 /// probably because the source does not need to be loaded. If
1313 /// 'IsZeroVal' is true, that means it's safe to return a
1314 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
1315 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
1316 /// constant so it does not need to be loaded.
1317 /// It returns EVT::Other if the type should be determined using generic
1318 /// target-independent logic.
1320 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1321 unsigned DstAlign, unsigned SrcAlign,
1324 MachineFunction &MF) const {
1325 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
1326 // linux. This is because the stack realignment code can't handle certain
1327 // cases like PR2962. This should be removed when PR2962 is fixed.
1328 const Function *F = MF.getFunction();
1330 !F->hasFnAttr(Attribute::NoImplicitFloat)) {
1332 (Subtarget->isUnalignedMemAccessFast() ||
1333 ((DstAlign == 0 || DstAlign >= 16) &&
1334 (SrcAlign == 0 || SrcAlign >= 16))) &&
1335 Subtarget->getStackAlignment() >= 16) {
1336 if (Subtarget->getStackAlignment() >= 32) {
1337 if (Subtarget->hasAVX2())
1339 if (Subtarget->hasAVX())
1342 if (Subtarget->hasSSE2())
1344 if (Subtarget->hasSSE1())
1346 } else if (!MemcpyStrSrc && Size >= 8 &&
1347 !Subtarget->is64Bit() &&
1348 Subtarget->getStackAlignment() >= 8 &&
1349 Subtarget->hasSSE2()) {
1350 // Do not use f64 to lower memcpy if source is string constant. It's
1351 // better to use i32 to avoid the loads.
1355 if (Subtarget->is64Bit() && Size >= 8)
1360 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1361 /// current function. The returned value is a member of the
1362 /// MachineJumpTableInfo::JTEntryKind enum.
1363 unsigned X86TargetLowering::getJumpTableEncoding() const {
1364 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1366 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1367 Subtarget->isPICStyleGOT())
1368 return MachineJumpTableInfo::EK_Custom32;
1370 // Otherwise, use the normal jump table encoding heuristics.
1371 return TargetLowering::getJumpTableEncoding();
1375 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1376 const MachineBasicBlock *MBB,
1377 unsigned uid,MCContext &Ctx) const{
1378 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1379 Subtarget->isPICStyleGOT());
1380 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1382 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1383 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1386 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1388 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1389 SelectionDAG &DAG) const {
1390 if (!Subtarget->is64Bit())
1391 // This doesn't have DebugLoc associated with it, but is not really the
1392 // same as a Register.
1393 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy());
1397 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1398 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1400 const MCExpr *X86TargetLowering::
1401 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1402 MCContext &Ctx) const {
1403 // X86-64 uses RIP relative addressing based on the jump table label.
1404 if (Subtarget->isPICStyleRIPRel())
1405 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1407 // Otherwise, the reference is relative to the PIC base.
1408 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1411 // FIXME: Why this routine is here? Move to RegInfo!
1412 std::pair<const TargetRegisterClass*, uint8_t>
1413 X86TargetLowering::findRepresentativeClass(EVT VT) const{
1414 const TargetRegisterClass *RRC = 0;
1416 switch (VT.getSimpleVT().SimpleTy) {
1418 return TargetLowering::findRepresentativeClass(VT);
1419 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1420 RRC = Subtarget->is64Bit() ?
1421 (const TargetRegisterClass*)&X86::GR64RegClass :
1422 (const TargetRegisterClass*)&X86::GR32RegClass;
1425 RRC = &X86::VR64RegClass;
1427 case MVT::f32: case MVT::f64:
1428 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1429 case MVT::v4f32: case MVT::v2f64:
1430 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1432 RRC = &X86::VR128RegClass;
1435 return std::make_pair(RRC, Cost);
1438 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1439 unsigned &Offset) const {
1440 if (!Subtarget->isTargetLinux())
1443 if (Subtarget->is64Bit()) {
1444 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1446 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1459 //===----------------------------------------------------------------------===//
1460 // Return Value Calling Convention Implementation
1461 //===----------------------------------------------------------------------===//
1463 #include "X86GenCallingConv.inc"
1466 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1467 MachineFunction &MF, bool isVarArg,
1468 const SmallVectorImpl<ISD::OutputArg> &Outs,
1469 LLVMContext &Context) const {
1470 SmallVector<CCValAssign, 16> RVLocs;
1471 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1473 return CCInfo.CheckReturn(Outs, RetCC_X86);
1477 X86TargetLowering::LowerReturn(SDValue Chain,
1478 CallingConv::ID CallConv, bool isVarArg,
1479 const SmallVectorImpl<ISD::OutputArg> &Outs,
1480 const SmallVectorImpl<SDValue> &OutVals,
1481 DebugLoc dl, SelectionDAG &DAG) const {
1482 MachineFunction &MF = DAG.getMachineFunction();
1483 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1485 SmallVector<CCValAssign, 16> RVLocs;
1486 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1487 RVLocs, *DAG.getContext());
1488 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1490 // Add the regs to the liveout set for the function.
1491 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1492 for (unsigned i = 0; i != RVLocs.size(); ++i)
1493 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg()))
1494 MRI.addLiveOut(RVLocs[i].getLocReg());
1498 SmallVector<SDValue, 6> RetOps;
1499 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1500 // Operand #1 = Bytes To Pop
1501 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1504 // Copy the result values into the output registers.
1505 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1506 CCValAssign &VA = RVLocs[i];
1507 assert(VA.isRegLoc() && "Can only return in registers!");
1508 SDValue ValToCopy = OutVals[i];
1509 EVT ValVT = ValToCopy.getValueType();
1511 // Promote values to the appropriate types
1512 if (VA.getLocInfo() == CCValAssign::SExt)
1513 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
1514 else if (VA.getLocInfo() == CCValAssign::ZExt)
1515 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
1516 else if (VA.getLocInfo() == CCValAssign::AExt)
1517 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
1518 else if (VA.getLocInfo() == CCValAssign::BCvt)
1519 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
1521 // If this is x86-64, and we disabled SSE, we can't return FP values,
1522 // or SSE or MMX vectors.
1523 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1524 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1525 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1526 report_fatal_error("SSE register return with SSE disabled");
1528 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1529 // llvm-gcc has never done it right and no one has noticed, so this
1530 // should be OK for now.
1531 if (ValVT == MVT::f64 &&
1532 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1533 report_fatal_error("SSE2 register return with SSE2 disabled");
1535 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1536 // the RET instruction and handled by the FP Stackifier.
1537 if (VA.getLocReg() == X86::ST0 ||
1538 VA.getLocReg() == X86::ST1) {
1539 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1540 // change the value to the FP stack register class.
1541 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1542 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1543 RetOps.push_back(ValToCopy);
1544 // Don't emit a copytoreg.
1548 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1549 // which is returned in RAX / RDX.
1550 if (Subtarget->is64Bit()) {
1551 if (ValVT == MVT::x86mmx) {
1552 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1553 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1554 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1556 // If we don't have SSE2 available, convert to v4f32 so the generated
1557 // register is legal.
1558 if (!Subtarget->hasSSE2())
1559 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1564 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1565 Flag = Chain.getValue(1);
1568 // The x86-64 ABI for returning structs by value requires that we copy
1569 // the sret argument into %rax for the return. We saved the argument into
1570 // a virtual register in the entry block, so now we copy the value out
1572 if (Subtarget->is64Bit() &&
1573 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1574 MachineFunction &MF = DAG.getMachineFunction();
1575 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1576 unsigned Reg = FuncInfo->getSRetReturnReg();
1578 "SRetReturnReg should have been set in LowerFormalArguments().");
1579 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1581 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
1582 Flag = Chain.getValue(1);
1584 // RAX now acts like a return value.
1585 MRI.addLiveOut(X86::RAX);
1588 RetOps[0] = Chain; // Update chain.
1590 // Add the flag if we have it.
1592 RetOps.push_back(Flag);
1594 return DAG.getNode(X86ISD::RET_FLAG, dl,
1595 MVT::Other, &RetOps[0], RetOps.size());
1598 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
1599 if (N->getNumValues() != 1)
1601 if (!N->hasNUsesOfValue(1, 0))
1604 SDValue TCChain = Chain;
1605 SDNode *Copy = *N->use_begin();
1606 if (Copy->getOpcode() == ISD::CopyToReg) {
1607 // If the copy has a glue operand, we conservatively assume it isn't safe to
1608 // perform a tail call.
1609 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
1611 TCChain = Copy->getOperand(0);
1612 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
1615 bool HasRet = false;
1616 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1618 if (UI->getOpcode() != X86ISD::RET_FLAG)
1631 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
1632 ISD::NodeType ExtendKind) const {
1634 // TODO: Is this also valid on 32-bit?
1635 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
1636 ReturnMVT = MVT::i8;
1638 ReturnMVT = MVT::i32;
1640 EVT MinVT = getRegisterType(Context, ReturnMVT);
1641 return VT.bitsLT(MinVT) ? MinVT : VT;
1644 /// LowerCallResult - Lower the result values of a call into the
1645 /// appropriate copies out of appropriate physical registers.
1648 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1649 CallingConv::ID CallConv, bool isVarArg,
1650 const SmallVectorImpl<ISD::InputArg> &Ins,
1651 DebugLoc dl, SelectionDAG &DAG,
1652 SmallVectorImpl<SDValue> &InVals) const {
1654 // Assign locations to each value returned by this call.
1655 SmallVector<CCValAssign, 16> RVLocs;
1656 bool Is64Bit = Subtarget->is64Bit();
1657 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1658 getTargetMachine(), RVLocs, *DAG.getContext());
1659 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1661 // Copy all of the result registers out of their specified physreg.
1662 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1663 CCValAssign &VA = RVLocs[i];
1664 EVT CopyVT = VA.getValVT();
1666 // If this is x86-64, and we disabled SSE, we can't return FP values
1667 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1668 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
1669 report_fatal_error("SSE register return with SSE disabled");
1674 // If this is a call to a function that returns an fp value on the floating
1675 // point stack, we must guarantee the the value is popped from the stack, so
1676 // a CopyFromReg is not good enough - the copy instruction may be eliminated
1677 // if the return value is not used. We use the FpPOP_RETVAL instruction
1679 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
1680 // If we prefer to use the value in xmm registers, copy it out as f80 and
1681 // use a truncate to move it from fp stack reg to xmm reg.
1682 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
1683 SDValue Ops[] = { Chain, InFlag };
1684 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT,
1685 MVT::Other, MVT::Glue, Ops, 2), 1);
1686 Val = Chain.getValue(0);
1688 // Round the f80 to the right size, which also moves it to the appropriate
1690 if (CopyVT != VA.getValVT())
1691 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1692 // This truncation won't change the value.
1693 DAG.getIntPtrConstant(1));
1695 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1696 CopyVT, InFlag).getValue(1);
1697 Val = Chain.getValue(0);
1699 InFlag = Chain.getValue(2);
1700 InVals.push_back(Val);
1707 //===----------------------------------------------------------------------===//
1708 // C & StdCall & Fast Calling Convention implementation
1709 //===----------------------------------------------------------------------===//
1710 // StdCall calling convention seems to be standard for many Windows' API
1711 // routines and around. It differs from C calling convention just a little:
1712 // callee should clean up the stack, not caller. Symbols should be also
1713 // decorated in some fancy way :) It doesn't support any vector arguments.
1714 // For info on fast calling convention see Fast Calling Convention (tail call)
1715 // implementation LowerX86_32FastCCCallTo.
1717 /// CallIsStructReturn - Determines whether a call uses struct return
1719 static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1723 return Outs[0].Flags.isSRet();
1726 /// ArgsAreStructReturn - Determines whether a function uses struct
1727 /// return semantics.
1729 ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
1733 return Ins[0].Flags.isSRet();
1736 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1737 /// by "Src" to address "Dst" with size and alignment information specified by
1738 /// the specific parameter attribute. The copy will be passed as a byval
1739 /// function parameter.
1741 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1742 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1744 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1746 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1747 /*isVolatile*/false, /*AlwaysInline=*/true,
1748 MachinePointerInfo(), MachinePointerInfo());
1751 /// IsTailCallConvention - Return true if the calling convention is one that
1752 /// supports tail call optimization.
1753 static bool IsTailCallConvention(CallingConv::ID CC) {
1754 return (CC == CallingConv::Fast || CC == CallingConv::GHC);
1757 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
1758 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
1762 CallingConv::ID CalleeCC = CS.getCallingConv();
1763 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C)
1769 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
1770 /// a tailcall target by changing its ABI.
1771 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
1772 bool GuaranteedTailCallOpt) {
1773 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
1777 X86TargetLowering::LowerMemArgument(SDValue Chain,
1778 CallingConv::ID CallConv,
1779 const SmallVectorImpl<ISD::InputArg> &Ins,
1780 DebugLoc dl, SelectionDAG &DAG,
1781 const CCValAssign &VA,
1782 MachineFrameInfo *MFI,
1784 // Create the nodes corresponding to a load from this parameter slot.
1785 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1786 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv,
1787 getTargetMachine().Options.GuaranteedTailCallOpt);
1788 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1791 // If value is passed by pointer we have address passed instead of the value
1793 if (VA.getLocInfo() == CCValAssign::Indirect)
1794 ValVT = VA.getLocVT();
1796 ValVT = VA.getValVT();
1798 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1799 // changed with more analysis.
1800 // In case of tail call optimization mark all arguments mutable. Since they
1801 // could be overwritten by lowering of arguments in case of a tail call.
1802 if (Flags.isByVal()) {
1803 unsigned Bytes = Flags.getByValSize();
1804 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
1805 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
1806 return DAG.getFrameIndex(FI, getPointerTy());
1808 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
1809 VA.getLocMemOffset(), isImmutable);
1810 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1811 return DAG.getLoad(ValVT, dl, Chain, FIN,
1812 MachinePointerInfo::getFixedStack(FI),
1813 false, false, false, 0);
1818 X86TargetLowering::LowerFormalArguments(SDValue Chain,
1819 CallingConv::ID CallConv,
1821 const SmallVectorImpl<ISD::InputArg> &Ins,
1824 SmallVectorImpl<SDValue> &InVals)
1826 MachineFunction &MF = DAG.getMachineFunction();
1827 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1829 const Function* Fn = MF.getFunction();
1830 if (Fn->hasExternalLinkage() &&
1831 Subtarget->isTargetCygMing() &&
1832 Fn->getName() == "main")
1833 FuncInfo->setForceFramePointer(true);
1835 MachineFrameInfo *MFI = MF.getFrameInfo();
1836 bool Is64Bit = Subtarget->is64Bit();
1837 bool IsWindows = Subtarget->isTargetWindows();
1838 bool IsWin64 = Subtarget->isTargetWin64();
1840 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1841 "Var args not supported with calling convention fastcc or ghc");
1843 // Assign locations to all of the incoming arguments.
1844 SmallVector<CCValAssign, 16> ArgLocs;
1845 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1846 ArgLocs, *DAG.getContext());
1848 // Allocate shadow area for Win64
1850 CCInfo.AllocateStack(32, 8);
1853 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
1855 unsigned LastVal = ~0U;
1857 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1858 CCValAssign &VA = ArgLocs[i];
1859 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1861 assert(VA.getValNo() != LastVal &&
1862 "Don't support value assigned to multiple locs yet");
1864 LastVal = VA.getValNo();
1866 if (VA.isRegLoc()) {
1867 EVT RegVT = VA.getLocVT();
1868 const TargetRegisterClass *RC;
1869 if (RegVT == MVT::i32)
1870 RC = &X86::GR32RegClass;
1871 else if (Is64Bit && RegVT == MVT::i64)
1872 RC = &X86::GR64RegClass;
1873 else if (RegVT == MVT::f32)
1874 RC = &X86::FR32RegClass;
1875 else if (RegVT == MVT::f64)
1876 RC = &X86::FR64RegClass;
1877 else if (RegVT.isVector() && RegVT.getSizeInBits() == 256)
1878 RC = &X86::VR256RegClass;
1879 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1880 RC = &X86::VR128RegClass;
1881 else if (RegVT == MVT::x86mmx)
1882 RC = &X86::VR64RegClass;
1884 llvm_unreachable("Unknown argument type!");
1886 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1887 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1889 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1890 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1892 if (VA.getLocInfo() == CCValAssign::SExt)
1893 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1894 DAG.getValueType(VA.getValVT()));
1895 else if (VA.getLocInfo() == CCValAssign::ZExt)
1896 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1897 DAG.getValueType(VA.getValVT()));
1898 else if (VA.getLocInfo() == CCValAssign::BCvt)
1899 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
1901 if (VA.isExtInLoc()) {
1902 // Handle MMX values passed in XMM regs.
1903 if (RegVT.isVector()) {
1904 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(),
1907 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1910 assert(VA.isMemLoc());
1911 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
1914 // If value is passed via pointer - do a load.
1915 if (VA.getLocInfo() == CCValAssign::Indirect)
1916 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
1917 MachinePointerInfo(), false, false, false, 0);
1919 InVals.push_back(ArgValue);
1922 // The x86-64 ABI for returning structs by value requires that we copy
1923 // the sret argument into %rax for the return. Save the argument into
1924 // a virtual register so that we can access it from the return points.
1925 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) {
1926 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1927 unsigned Reg = FuncInfo->getSRetReturnReg();
1929 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1930 FuncInfo->setSRetReturnReg(Reg);
1932 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1933 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1936 unsigned StackSize = CCInfo.getNextStackOffset();
1937 // Align stack specially for tail calls.
1938 if (FuncIsMadeTailCallSafe(CallConv,
1939 MF.getTarget().Options.GuaranteedTailCallOpt))
1940 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1942 // If the function takes variable number of arguments, make a frame index for
1943 // the start of the first vararg value... for expansion of llvm.va_start.
1945 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
1946 CallConv != CallingConv::X86_ThisCall)) {
1947 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
1950 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1952 // FIXME: We should really autogenerate these arrays
1953 static const uint16_t GPR64ArgRegsWin64[] = {
1954 X86::RCX, X86::RDX, X86::R8, X86::R9
1956 static const uint16_t GPR64ArgRegs64Bit[] = {
1957 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1959 static const uint16_t XMMArgRegs64Bit[] = {
1960 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1961 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1963 const uint16_t *GPR64ArgRegs;
1964 unsigned NumXMMRegs = 0;
1967 // The XMM registers which might contain var arg parameters are shadowed
1968 // in their paired GPR. So we only need to save the GPR to their home
1970 TotalNumIntRegs = 4;
1971 GPR64ArgRegs = GPR64ArgRegsWin64;
1973 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1974 GPR64ArgRegs = GPR64ArgRegs64Bit;
1976 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit,
1979 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1982 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat);
1983 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
1984 "SSE register cannot be used when SSE is disabled!");
1985 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat &&
1986 NoImplicitFloatOps) &&
1987 "SSE register cannot be used when SSE is disabled!");
1988 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
1989 !Subtarget->hasSSE1())
1990 // Kernel mode asks for SSE to be disabled, so don't push them
1992 TotalNumXMMRegs = 0;
1995 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering();
1996 // Get to the caller-allocated home save location. Add 8 to account
1997 // for the return address.
1998 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
1999 FuncInfo->setRegSaveFrameIndex(
2000 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2001 // Fixup to set vararg frame on shadow area (4 x i64).
2003 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2005 // For X86-64, if there are vararg parameters that are passed via
2006 // registers, then we must store them to their spots on the stack so
2007 // they may be loaded by deferencing the result of va_next.
2008 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2009 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
2010 FuncInfo->setRegSaveFrameIndex(
2011 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
2015 // Store the integer parameter registers.
2016 SmallVector<SDValue, 8> MemOps;
2017 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2019 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2020 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
2021 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2022 DAG.getIntPtrConstant(Offset));
2023 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
2024 &X86::GR64RegClass);
2025 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2027 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2028 MachinePointerInfo::getFixedStack(
2029 FuncInfo->getRegSaveFrameIndex(), Offset),
2031 MemOps.push_back(Store);
2035 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
2036 // Now store the XMM (fp + vector) parameter registers.
2037 SmallVector<SDValue, 11> SaveXMMOps;
2038 SaveXMMOps.push_back(Chain);
2040 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2041 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
2042 SaveXMMOps.push_back(ALVal);
2044 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2045 FuncInfo->getRegSaveFrameIndex()));
2046 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2047 FuncInfo->getVarArgsFPOffset()));
2049 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
2050 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
2051 &X86::VR128RegClass);
2052 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
2053 SaveXMMOps.push_back(Val);
2055 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2057 &SaveXMMOps[0], SaveXMMOps.size()));
2060 if (!MemOps.empty())
2061 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2062 &MemOps[0], MemOps.size());
2066 // Some CCs need callee pop.
2067 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2068 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2069 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2071 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2072 // If this is an sret function, the return should pop the hidden pointer.
2073 if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2074 ArgsAreStructReturn(Ins))
2075 FuncInfo->setBytesToPopOnReturn(4);
2079 // RegSaveFrameIndex is X86-64 only.
2080 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2081 if (CallConv == CallingConv::X86_FastCall ||
2082 CallConv == CallingConv::X86_ThisCall)
2083 // fastcc functions can't have varargs.
2084 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2087 FuncInfo->setArgumentStackSize(StackSize);
2093 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2094 SDValue StackPtr, SDValue Arg,
2095 DebugLoc dl, SelectionDAG &DAG,
2096 const CCValAssign &VA,
2097 ISD::ArgFlagsTy Flags) const {
2098 unsigned LocMemOffset = VA.getLocMemOffset();
2099 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2100 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2101 if (Flags.isByVal())
2102 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2104 return DAG.getStore(Chain, dl, Arg, PtrOff,
2105 MachinePointerInfo::getStack(LocMemOffset),
2109 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2110 /// optimization is performed and it is required.
2112 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2113 SDValue &OutRetAddr, SDValue Chain,
2114 bool IsTailCall, bool Is64Bit,
2115 int FPDiff, DebugLoc dl) const {
2116 // Adjust the Return address stack slot.
2117 EVT VT = getPointerTy();
2118 OutRetAddr = getReturnAddressFrameIndex(DAG);
2120 // Load the "old" Return address.
2121 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2122 false, false, false, 0);
2123 return SDValue(OutRetAddr.getNode(), 1);
2126 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2127 /// optimization is performed and it is required (FPDiff!=0).
2129 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
2130 SDValue Chain, SDValue RetAddrFrIdx,
2131 bool Is64Bit, int FPDiff, DebugLoc dl) {
2132 // Store the return address to the appropriate stack slot.
2133 if (!FPDiff) return Chain;
2134 // Calculate the new stack slot for the return address.
2135 int SlotSize = Is64Bit ? 8 : 4;
2136 int NewReturnAddrFI =
2137 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false);
2138 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
2139 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
2140 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2141 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2147 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2148 SmallVectorImpl<SDValue> &InVals) const {
2149 SelectionDAG &DAG = CLI.DAG;
2150 DebugLoc &dl = CLI.DL;
2151 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
2152 SmallVector<SDValue, 32> &OutVals = CLI.OutVals;
2153 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
2154 SDValue Chain = CLI.Chain;
2155 SDValue Callee = CLI.Callee;
2156 CallingConv::ID CallConv = CLI.CallConv;
2157 bool &isTailCall = CLI.IsTailCall;
2158 bool isVarArg = CLI.IsVarArg;
2160 MachineFunction &MF = DAG.getMachineFunction();
2161 bool Is64Bit = Subtarget->is64Bit();
2162 bool IsWin64 = Subtarget->isTargetWin64();
2163 bool IsWindows = Subtarget->isTargetWindows();
2164 bool IsStructRet = CallIsStructReturn(Outs);
2165 bool IsSibcall = false;
2167 if (MF.getTarget().Options.DisableTailCalls)
2171 // Check if it's really possible to do a tail call.
2172 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2173 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
2174 Outs, OutVals, Ins, DAG);
2176 // Sibcalls are automatically detected tailcalls which do not require
2178 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2185 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2186 "Var args not supported with calling convention fastcc or ghc");
2188 // Analyze operands of the call, assigning locations to each operand.
2189 SmallVector<CCValAssign, 16> ArgLocs;
2190 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2191 ArgLocs, *DAG.getContext());
2193 // Allocate shadow area for Win64
2195 CCInfo.AllocateStack(32, 8);
2198 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2200 // Get a count of how many bytes are to be pushed on the stack.
2201 unsigned NumBytes = CCInfo.getNextStackOffset();
2203 // This is a sibcall. The memory operands are available in caller's
2204 // own caller's stack.
2206 else if (getTargetMachine().Options.GuaranteedTailCallOpt &&
2207 IsTailCallConvention(CallConv))
2208 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2211 if (isTailCall && !IsSibcall) {
2212 // Lower arguments at fp - stackoffset + fpdiff.
2213 unsigned NumBytesCallerPushed =
2214 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
2215 FPDiff = NumBytesCallerPushed - NumBytes;
2217 // Set the delta of movement of the returnaddr stackslot.
2218 // But only set if delta is greater than previous delta.
2219 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
2220 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
2224 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
2226 SDValue RetAddrFrIdx;
2227 // Load return address for tail calls.
2228 if (isTailCall && FPDiff)
2229 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2230 Is64Bit, FPDiff, dl);
2232 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2233 SmallVector<SDValue, 8> MemOpChains;
2236 // Walk the register/memloc assignments, inserting copies/loads. In the case
2237 // of tail call optimization arguments are handle later.
2238 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2239 CCValAssign &VA = ArgLocs[i];
2240 EVT RegVT = VA.getLocVT();
2241 SDValue Arg = OutVals[i];
2242 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2243 bool isByVal = Flags.isByVal();
2245 // Promote the value if needed.
2246 switch (VA.getLocInfo()) {
2247 default: llvm_unreachable("Unknown loc info!");
2248 case CCValAssign::Full: break;
2249 case CCValAssign::SExt:
2250 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2252 case CCValAssign::ZExt:
2253 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2255 case CCValAssign::AExt:
2256 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) {
2257 // Special case: passing MMX values in XMM registers.
2258 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2259 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2260 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2262 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2264 case CCValAssign::BCvt:
2265 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2267 case CCValAssign::Indirect: {
2268 // Store the argument.
2269 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2270 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2271 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2272 MachinePointerInfo::getFixedStack(FI),
2279 if (VA.isRegLoc()) {
2280 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2281 if (isVarArg && IsWin64) {
2282 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2283 // shadow reg if callee is a varargs function.
2284 unsigned ShadowReg = 0;
2285 switch (VA.getLocReg()) {
2286 case X86::XMM0: ShadowReg = X86::RCX; break;
2287 case X86::XMM1: ShadowReg = X86::RDX; break;
2288 case X86::XMM2: ShadowReg = X86::R8; break;
2289 case X86::XMM3: ShadowReg = X86::R9; break;
2292 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2294 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2295 assert(VA.isMemLoc());
2296 if (StackPtr.getNode() == 0)
2297 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
2298 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2299 dl, DAG, VA, Flags));
2303 if (!MemOpChains.empty())
2304 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2305 &MemOpChains[0], MemOpChains.size());
2307 // Build a sequence of copy-to-reg nodes chained together with token chain
2308 // and flag operands which copy the outgoing args into registers.
2310 // Tail call byval lowering might overwrite argument registers so in case of
2311 // tail call optimization the copies to registers are lowered later.
2313 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2314 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2315 RegsToPass[i].second, InFlag);
2316 InFlag = Chain.getValue(1);
2319 if (Subtarget->isPICStyleGOT()) {
2320 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2323 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX,
2324 DAG.getNode(X86ISD::GlobalBaseReg,
2325 DebugLoc(), getPointerTy()),
2327 InFlag = Chain.getValue(1);
2329 // If we are tail calling and generating PIC/GOT style code load the
2330 // address of the callee into ECX. The value in ecx is used as target of
2331 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2332 // for tail calls on PIC/GOT architectures. Normally we would just put the
2333 // address of GOT into ebx and then call target@PLT. But for tail calls
2334 // ebx would be restored (since ebx is callee saved) before jumping to the
2337 // Note: The actual moving to ECX is done further down.
2338 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2339 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2340 !G->getGlobal()->hasProtectedVisibility())
2341 Callee = LowerGlobalAddress(Callee, DAG);
2342 else if (isa<ExternalSymbolSDNode>(Callee))
2343 Callee = LowerExternalSymbol(Callee, DAG);
2347 if (Is64Bit && isVarArg && !IsWin64) {
2348 // From AMD64 ABI document:
2349 // For calls that may call functions that use varargs or stdargs
2350 // (prototype-less calls or calls to functions containing ellipsis (...) in
2351 // the declaration) %al is used as hidden argument to specify the number
2352 // of SSE registers used. The contents of %al do not need to match exactly
2353 // the number of registers, but must be an ubound on the number of SSE
2354 // registers used and is in the range 0 - 8 inclusive.
2356 // Count the number of XMM registers allocated.
2357 static const uint16_t XMMArgRegs[] = {
2358 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2359 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2361 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2362 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2363 && "SSE registers cannot be used when SSE is disabled");
2365 Chain = DAG.getCopyToReg(Chain, dl, X86::AL,
2366 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
2367 InFlag = Chain.getValue(1);
2371 // For tail calls lower the arguments to the 'real' stack slot.
2373 // Force all the incoming stack arguments to be loaded from the stack
2374 // before any new outgoing arguments are stored to the stack, because the
2375 // outgoing stack slots may alias the incoming argument stack slots, and
2376 // the alias isn't otherwise explicit. This is slightly more conservative
2377 // than necessary, because it means that each store effectively depends
2378 // on every argument instead of just those arguments it would clobber.
2379 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2381 SmallVector<SDValue, 8> MemOpChains2;
2384 // Do not flag preceding copytoreg stuff together with the following stuff.
2386 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2387 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2388 CCValAssign &VA = ArgLocs[i];
2391 assert(VA.isMemLoc());
2392 SDValue Arg = OutVals[i];
2393 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2394 // Create frame index.
2395 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2396 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2397 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2398 FIN = DAG.getFrameIndex(FI, getPointerTy());
2400 if (Flags.isByVal()) {
2401 // Copy relative to framepointer.
2402 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2403 if (StackPtr.getNode() == 0)
2404 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
2406 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2408 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2412 // Store relative to framepointer.
2413 MemOpChains2.push_back(
2414 DAG.getStore(ArgChain, dl, Arg, FIN,
2415 MachinePointerInfo::getFixedStack(FI),
2421 if (!MemOpChains2.empty())
2422 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2423 &MemOpChains2[0], MemOpChains2.size());
2425 // Copy arguments to their registers.
2426 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2427 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2428 RegsToPass[i].second, InFlag);
2429 InFlag = Chain.getValue(1);
2433 // Store the return address to the appropriate stack slot.
2434 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
2438 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2439 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2440 // In the 64-bit large code model, we have to make all calls
2441 // through a register, since the call instruction's 32-bit
2442 // pc-relative offset may not be large enough to hold the whole
2444 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2445 // If the callee is a GlobalAddress node (quite common, every direct call
2446 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2449 // We should use extra load for direct calls to dllimported functions in
2451 const GlobalValue *GV = G->getGlobal();
2452 if (!GV->hasDLLImportLinkage()) {
2453 unsigned char OpFlags = 0;
2454 bool ExtraLoad = false;
2455 unsigned WrapperKind = ISD::DELETED_NODE;
2457 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2458 // external symbols most go through the PLT in PIC mode. If the symbol
2459 // has hidden or protected visibility, or if it is static or local, then
2460 // we don't need to use the PLT - we can directly call it.
2461 if (Subtarget->isTargetELF() &&
2462 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2463 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2464 OpFlags = X86II::MO_PLT;
2465 } else if (Subtarget->isPICStyleStubAny() &&
2466 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2467 (!Subtarget->getTargetTriple().isMacOSX() ||
2468 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2469 // PC-relative references to external symbols should go through $stub,
2470 // unless we're building with the leopard linker or later, which
2471 // automatically synthesizes these stubs.
2472 OpFlags = X86II::MO_DARWIN_STUB;
2473 } else if (Subtarget->isPICStyleRIPRel() &&
2474 isa<Function>(GV) &&
2475 cast<Function>(GV)->hasFnAttr(Attribute::NonLazyBind)) {
2476 // If the function is marked as non-lazy, generate an indirect call
2477 // which loads from the GOT directly. This avoids runtime overhead
2478 // at the cost of eager binding (and one extra byte of encoding).
2479 OpFlags = X86II::MO_GOTPCREL;
2480 WrapperKind = X86ISD::WrapperRIP;
2484 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2485 G->getOffset(), OpFlags);
2487 // Add a wrapper if needed.
2488 if (WrapperKind != ISD::DELETED_NODE)
2489 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
2490 // Add extra indirection if needed.
2492 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
2493 MachinePointerInfo::getGOT(),
2494 false, false, false, 0);
2496 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2497 unsigned char OpFlags = 0;
2499 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2500 // external symbols should go through the PLT.
2501 if (Subtarget->isTargetELF() &&
2502 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2503 OpFlags = X86II::MO_PLT;
2504 } else if (Subtarget->isPICStyleStubAny() &&
2505 (!Subtarget->getTargetTriple().isMacOSX() ||
2506 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2507 // PC-relative references to external symbols should go through $stub,
2508 // unless we're building with the leopard linker or later, which
2509 // automatically synthesizes these stubs.
2510 OpFlags = X86II::MO_DARWIN_STUB;
2513 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2517 // Returns a chain & a flag for retval copy to use.
2518 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2519 SmallVector<SDValue, 8> Ops;
2521 if (!IsSibcall && isTailCall) {
2522 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2523 DAG.getIntPtrConstant(0, true), InFlag);
2524 InFlag = Chain.getValue(1);
2527 Ops.push_back(Chain);
2528 Ops.push_back(Callee);
2531 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2533 // Add argument registers to the end of the list so that they are known live
2535 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2536 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2537 RegsToPass[i].second.getValueType()));
2539 // Add an implicit use GOT pointer in EBX.
2540 if (!isTailCall && Subtarget->isPICStyleGOT())
2541 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
2543 // Add an implicit use of AL for non-Windows x86 64-bit vararg functions.
2544 if (Is64Bit && isVarArg && !IsWin64)
2545 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
2547 // Add a register mask operand representing the call-preserved registers.
2548 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2549 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
2550 assert(Mask && "Missing call preserved mask for calling convention");
2551 Ops.push_back(DAG.getRegisterMask(Mask));
2553 if (InFlag.getNode())
2554 Ops.push_back(InFlag);
2558 //// If this is the first return lowered for this function, add the regs
2559 //// to the liveout set for the function.
2560 // This isn't right, although it's probably harmless on x86; liveouts
2561 // should be computed from returns not tail calls. Consider a void
2562 // function making a tail call to a function returning int.
2563 return DAG.getNode(X86ISD::TC_RETURN, dl,
2564 NodeTys, &Ops[0], Ops.size());
2567 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2568 InFlag = Chain.getValue(1);
2570 // Create the CALLSEQ_END node.
2571 unsigned NumBytesForCalleeToPush;
2572 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2573 getTargetMachine().Options.GuaranteedTailCallOpt))
2574 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2575 else if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2577 // If this is a call to a struct-return function, the callee
2578 // pops the hidden struct pointer, so we have to push it back.
2579 // This is common for Darwin/X86, Linux & Mingw32 targets.
2580 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
2581 NumBytesForCalleeToPush = 4;
2583 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2585 // Returns a flag for retval copy to use.
2587 Chain = DAG.getCALLSEQ_END(Chain,
2588 DAG.getIntPtrConstant(NumBytes, true),
2589 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2592 InFlag = Chain.getValue(1);
2595 // Handle result values, copying them out of physregs into vregs that we
2597 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2598 Ins, dl, DAG, InVals);
2602 //===----------------------------------------------------------------------===//
2603 // Fast Calling Convention (tail call) implementation
2604 //===----------------------------------------------------------------------===//
2606 // Like std call, callee cleans arguments, convention except that ECX is
2607 // reserved for storing the tail called function address. Only 2 registers are
2608 // free for argument passing (inreg). Tail call optimization is performed
2610 // * tailcallopt is enabled
2611 // * caller/callee are fastcc
2612 // On X86_64 architecture with GOT-style position independent code only local
2613 // (within module) calls are supported at the moment.
2614 // To keep the stack aligned according to platform abi the function
2615 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2616 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2617 // If a tail called function callee has more arguments than the caller the
2618 // caller needs to make sure that there is room to move the RETADDR to. This is
2619 // achieved by reserving an area the size of the argument delta right after the
2620 // original REtADDR, but before the saved framepointer or the spilled registers
2621 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2633 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2634 /// for a 16 byte align requirement.
2636 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2637 SelectionDAG& DAG) const {
2638 MachineFunction &MF = DAG.getMachineFunction();
2639 const TargetMachine &TM = MF.getTarget();
2640 const TargetFrameLowering &TFI = *TM.getFrameLowering();
2641 unsigned StackAlignment = TFI.getStackAlignment();
2642 uint64_t AlignMask = StackAlignment - 1;
2643 int64_t Offset = StackSize;
2644 uint64_t SlotSize = TD->getPointerSize();
2645 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2646 // Number smaller than 12 so just add the difference.
2647 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2649 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2650 Offset = ((~AlignMask) & Offset) + StackAlignment +
2651 (StackAlignment-SlotSize);
2656 /// MatchingStackOffset - Return true if the given stack call argument is
2657 /// already available in the same position (relatively) of the caller's
2658 /// incoming argument stack.
2660 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2661 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2662 const X86InstrInfo *TII) {
2663 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
2665 if (Arg.getOpcode() == ISD::CopyFromReg) {
2666 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2667 if (!TargetRegisterInfo::isVirtualRegister(VR))
2669 MachineInstr *Def = MRI->getVRegDef(VR);
2672 if (!Flags.isByVal()) {
2673 if (!TII->isLoadFromStackSlot(Def, FI))
2676 unsigned Opcode = Def->getOpcode();
2677 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
2678 Def->getOperand(1).isFI()) {
2679 FI = Def->getOperand(1).getIndex();
2680 Bytes = Flags.getByValSize();
2684 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2685 if (Flags.isByVal())
2686 // ByVal argument is passed in as a pointer but it's now being
2687 // dereferenced. e.g.
2688 // define @foo(%struct.X* %A) {
2689 // tail call @bar(%struct.X* byval %A)
2692 SDValue Ptr = Ld->getBasePtr();
2693 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2696 FI = FINode->getIndex();
2697 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
2698 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
2699 FI = FINode->getIndex();
2700 Bytes = Flags.getByValSize();
2704 assert(FI != INT_MAX);
2705 if (!MFI->isFixedObjectIndex(FI))
2707 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
2710 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2711 /// for tail call optimization. Targets which want to do tail call
2712 /// optimization should implement this function.
2714 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2715 CallingConv::ID CalleeCC,
2717 bool isCalleeStructRet,
2718 bool isCallerStructRet,
2719 const SmallVectorImpl<ISD::OutputArg> &Outs,
2720 const SmallVectorImpl<SDValue> &OutVals,
2721 const SmallVectorImpl<ISD::InputArg> &Ins,
2722 SelectionDAG& DAG) const {
2723 if (!IsTailCallConvention(CalleeCC) &&
2724 CalleeCC != CallingConv::C)
2727 // If -tailcallopt is specified, make fastcc functions tail-callable.
2728 const MachineFunction &MF = DAG.getMachineFunction();
2729 const Function *CallerF = DAG.getMachineFunction().getFunction();
2730 CallingConv::ID CallerCC = CallerF->getCallingConv();
2731 bool CCMatch = CallerCC == CalleeCC;
2733 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2734 if (IsTailCallConvention(CalleeCC) && CCMatch)
2739 // Look for obvious safe cases to perform tail call optimization that do not
2740 // require ABI changes. This is what gcc calls sibcall.
2742 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
2743 // emit a special epilogue.
2744 if (RegInfo->needsStackRealignment(MF))
2747 // Also avoid sibcall optimization if either caller or callee uses struct
2748 // return semantics.
2749 if (isCalleeStructRet || isCallerStructRet)
2752 // An stdcall caller is expected to clean up its arguments; the callee
2753 // isn't going to do that.
2754 if (!CCMatch && CallerCC==CallingConv::X86_StdCall)
2757 // Do not sibcall optimize vararg calls unless all arguments are passed via
2759 if (isVarArg && !Outs.empty()) {
2761 // Optimizing for varargs on Win64 is unlikely to be safe without
2762 // additional testing.
2763 if (Subtarget->isTargetWin64())
2766 SmallVector<CCValAssign, 16> ArgLocs;
2767 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2768 getTargetMachine(), ArgLocs, *DAG.getContext());
2770 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2771 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
2772 if (!ArgLocs[i].isRegLoc())
2776 // If the call result is in ST0 / ST1, it needs to be popped off the x87
2777 // stack. Therefore, if it's not used by the call it is not safe to optimize
2778 // this into a sibcall.
2779 bool Unused = false;
2780 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
2787 SmallVector<CCValAssign, 16> RVLocs;
2788 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(),
2789 getTargetMachine(), RVLocs, *DAG.getContext());
2790 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2791 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2792 CCValAssign &VA = RVLocs[i];
2793 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
2798 // If the calling conventions do not match, then we'd better make sure the
2799 // results are returned in the same way as what the caller expects.
2801 SmallVector<CCValAssign, 16> RVLocs1;
2802 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
2803 getTargetMachine(), RVLocs1, *DAG.getContext());
2804 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
2806 SmallVector<CCValAssign, 16> RVLocs2;
2807 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
2808 getTargetMachine(), RVLocs2, *DAG.getContext());
2809 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
2811 if (RVLocs1.size() != RVLocs2.size())
2813 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2814 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2816 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2818 if (RVLocs1[i].isRegLoc()) {
2819 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2822 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2828 // If the callee takes no arguments then go on to check the results of the
2830 if (!Outs.empty()) {
2831 // Check if stack adjustment is needed. For now, do not do this if any
2832 // argument is passed on the stack.
2833 SmallVector<CCValAssign, 16> ArgLocs;
2834 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2835 getTargetMachine(), ArgLocs, *DAG.getContext());
2837 // Allocate shadow area for Win64
2838 if (Subtarget->isTargetWin64()) {
2839 CCInfo.AllocateStack(32, 8);
2842 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2843 if (CCInfo.getNextStackOffset()) {
2844 MachineFunction &MF = DAG.getMachineFunction();
2845 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
2848 // Check if the arguments are already laid out in the right way as
2849 // the caller's fixed stack objects.
2850 MachineFrameInfo *MFI = MF.getFrameInfo();
2851 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2852 const X86InstrInfo *TII =
2853 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
2854 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2855 CCValAssign &VA = ArgLocs[i];
2856 SDValue Arg = OutVals[i];
2857 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2858 if (VA.getLocInfo() == CCValAssign::Indirect)
2860 if (!VA.isRegLoc()) {
2861 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2868 // If the tailcall address may be in a register, then make sure it's
2869 // possible to register allocate for it. In 32-bit, the call address can
2870 // only target EAX, EDX, or ECX since the tail call must be scheduled after
2871 // callee-saved registers are restored. These happen to be the same
2872 // registers used to pass 'inreg' arguments so watch out for those.
2873 if (!Subtarget->is64Bit() &&
2874 !isa<GlobalAddressSDNode>(Callee) &&
2875 !isa<ExternalSymbolSDNode>(Callee)) {
2876 unsigned NumInRegs = 0;
2877 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2878 CCValAssign &VA = ArgLocs[i];
2881 unsigned Reg = VA.getLocReg();
2884 case X86::EAX: case X86::EDX: case X86::ECX:
2885 if (++NumInRegs == 3)
2897 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const {
2898 return X86::createFastISel(funcInfo);
2902 //===----------------------------------------------------------------------===//
2903 // Other Lowering Hooks
2904 //===----------------------------------------------------------------------===//
2906 static bool MayFoldLoad(SDValue Op) {
2907 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
2910 static bool MayFoldIntoStore(SDValue Op) {
2911 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
2914 static bool isTargetShuffle(unsigned Opcode) {
2916 default: return false;
2917 case X86ISD::PSHUFD:
2918 case X86ISD::PSHUFHW:
2919 case X86ISD::PSHUFLW:
2921 case X86ISD::PALIGN:
2922 case X86ISD::MOVLHPS:
2923 case X86ISD::MOVLHPD:
2924 case X86ISD::MOVHLPS:
2925 case X86ISD::MOVLPS:
2926 case X86ISD::MOVLPD:
2927 case X86ISD::MOVSHDUP:
2928 case X86ISD::MOVSLDUP:
2929 case X86ISD::MOVDDUP:
2932 case X86ISD::UNPCKL:
2933 case X86ISD::UNPCKH:
2934 case X86ISD::VPERMILP:
2935 case X86ISD::VPERM2X128:
2936 case X86ISD::VPERMI:
2941 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2942 SDValue V1, SelectionDAG &DAG) {
2944 default: llvm_unreachable("Unknown x86 shuffle node");
2945 case X86ISD::MOVSHDUP:
2946 case X86ISD::MOVSLDUP:
2947 case X86ISD::MOVDDUP:
2948 return DAG.getNode(Opc, dl, VT, V1);
2952 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2953 SDValue V1, unsigned TargetMask,
2954 SelectionDAG &DAG) {
2956 default: llvm_unreachable("Unknown x86 shuffle node");
2957 case X86ISD::PSHUFD:
2958 case X86ISD::PSHUFHW:
2959 case X86ISD::PSHUFLW:
2960 case X86ISD::VPERMILP:
2961 case X86ISD::VPERMI:
2962 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
2966 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2967 SDValue V1, SDValue V2, unsigned TargetMask,
2968 SelectionDAG &DAG) {
2970 default: llvm_unreachable("Unknown x86 shuffle node");
2971 case X86ISD::PALIGN:
2973 case X86ISD::VPERM2X128:
2974 return DAG.getNode(Opc, dl, VT, V1, V2,
2975 DAG.getConstant(TargetMask, MVT::i8));
2979 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2980 SDValue V1, SDValue V2, SelectionDAG &DAG) {
2982 default: llvm_unreachable("Unknown x86 shuffle node");
2983 case X86ISD::MOVLHPS:
2984 case X86ISD::MOVLHPD:
2985 case X86ISD::MOVHLPS:
2986 case X86ISD::MOVLPS:
2987 case X86ISD::MOVLPD:
2990 case X86ISD::UNPCKL:
2991 case X86ISD::UNPCKH:
2992 return DAG.getNode(Opc, dl, VT, V1, V2);
2996 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
2997 MachineFunction &MF = DAG.getMachineFunction();
2998 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2999 int ReturnAddrIndex = FuncInfo->getRAIndex();
3001 if (ReturnAddrIndex == 0) {
3002 // Set up a frame object for the return address.
3003 uint64_t SlotSize = TD->getPointerSize();
3004 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
3006 FuncInfo->setRAIndex(ReturnAddrIndex);
3009 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3013 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3014 bool hasSymbolicDisplacement) {
3015 // Offset should fit into 32 bit immediate field.
3016 if (!isInt<32>(Offset))
3019 // If we don't have a symbolic displacement - we don't have any extra
3021 if (!hasSymbolicDisplacement)
3024 // FIXME: Some tweaks might be needed for medium code model.
3025 if (M != CodeModel::Small && M != CodeModel::Kernel)
3028 // For small code model we assume that latest object is 16MB before end of 31
3029 // bits boundary. We may also accept pretty large negative constants knowing
3030 // that all objects are in the positive half of address space.
3031 if (M == CodeModel::Small && Offset < 16*1024*1024)
3034 // For kernel code model we know that all object resist in the negative half
3035 // of 32bits address space. We may not accept negative offsets, since they may
3036 // be just off and we may accept pretty large positive ones.
3037 if (M == CodeModel::Kernel && Offset > 0)
3043 /// isCalleePop - Determines whether the callee is required to pop its
3044 /// own arguments. Callee pop is necessary to support tail calls.
3045 bool X86::isCalleePop(CallingConv::ID CallingConv,
3046 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3050 switch (CallingConv) {
3053 case CallingConv::X86_StdCall:
3055 case CallingConv::X86_FastCall:
3057 case CallingConv::X86_ThisCall:
3059 case CallingConv::Fast:
3061 case CallingConv::GHC:
3066 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3067 /// specific condition code, returning the condition code and the LHS/RHS of the
3068 /// comparison to make.
3069 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3070 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3072 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3073 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3074 // X > -1 -> X == 0, jump !sign.
3075 RHS = DAG.getConstant(0, RHS.getValueType());
3076 return X86::COND_NS;
3078 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3079 // X < 0 -> X == 0, jump on sign.
3082 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3084 RHS = DAG.getConstant(0, RHS.getValueType());
3085 return X86::COND_LE;
3089 switch (SetCCOpcode) {
3090 default: llvm_unreachable("Invalid integer condition!");
3091 case ISD::SETEQ: return X86::COND_E;
3092 case ISD::SETGT: return X86::COND_G;
3093 case ISD::SETGE: return X86::COND_GE;
3094 case ISD::SETLT: return X86::COND_L;
3095 case ISD::SETLE: return X86::COND_LE;
3096 case ISD::SETNE: return X86::COND_NE;
3097 case ISD::SETULT: return X86::COND_B;
3098 case ISD::SETUGT: return X86::COND_A;
3099 case ISD::SETULE: return X86::COND_BE;
3100 case ISD::SETUGE: return X86::COND_AE;
3104 // First determine if it is required or is profitable to flip the operands.
3106 // If LHS is a foldable load, but RHS is not, flip the condition.
3107 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3108 !ISD::isNON_EXTLoad(RHS.getNode())) {
3109 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3110 std::swap(LHS, RHS);
3113 switch (SetCCOpcode) {
3119 std::swap(LHS, RHS);
3123 // On a floating point condition, the flags are set as follows:
3125 // 0 | 0 | 0 | X > Y
3126 // 0 | 0 | 1 | X < Y
3127 // 1 | 0 | 0 | X == Y
3128 // 1 | 1 | 1 | unordered
3129 switch (SetCCOpcode) {
3130 default: llvm_unreachable("Condcode should be pre-legalized away");
3132 case ISD::SETEQ: return X86::COND_E;
3133 case ISD::SETOLT: // flipped
3135 case ISD::SETGT: return X86::COND_A;
3136 case ISD::SETOLE: // flipped
3138 case ISD::SETGE: return X86::COND_AE;
3139 case ISD::SETUGT: // flipped
3141 case ISD::SETLT: return X86::COND_B;
3142 case ISD::SETUGE: // flipped
3144 case ISD::SETLE: return X86::COND_BE;
3146 case ISD::SETNE: return X86::COND_NE;
3147 case ISD::SETUO: return X86::COND_P;
3148 case ISD::SETO: return X86::COND_NP;
3150 case ISD::SETUNE: return X86::COND_INVALID;
3154 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3155 /// code. Current x86 isa includes the following FP cmov instructions:
3156 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3157 static bool hasFPCMov(unsigned X86CC) {
3173 /// isFPImmLegal - Returns true if the target can instruction select the
3174 /// specified FP immediate natively. If false, the legalizer will
3175 /// materialize the FP immediate as a load from a constant pool.
3176 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3177 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3178 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3184 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3185 /// the specified range (L, H].
3186 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3187 return (Val < 0) || (Val >= Low && Val < Hi);
3190 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3191 /// specified value.
3192 static bool isUndefOrEqual(int Val, int CmpVal) {
3193 if (Val < 0 || Val == CmpVal)
3198 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3199 /// from position Pos and ending in Pos+Size, falls within the specified
3200 /// sequential range (L, L+Pos]. or is undef.
3201 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3202 unsigned Pos, unsigned Size, int Low) {
3203 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3204 if (!isUndefOrEqual(Mask[i], Low))
3209 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3210 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3211 /// the second operand.
3212 static bool isPSHUFDMask(ArrayRef<int> Mask, EVT VT) {
3213 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3214 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3215 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3216 return (Mask[0] < 2 && Mask[1] < 2);
3220 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3221 /// is suitable for input to PSHUFHW.
3222 static bool isPSHUFHWMask(ArrayRef<int> Mask, EVT VT, bool HasAVX2) {
3223 if (VT != MVT::v8i16 && (!HasAVX2 || VT != MVT::v16i16))
3226 // Lower quadword copied in order or undef.
3227 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3230 // Upper quadword shuffled.
3231 for (unsigned i = 4; i != 8; ++i)
3232 if (!isUndefOrInRange(Mask[i], 4, 8))
3235 if (VT == MVT::v16i16) {
3236 // Lower quadword copied in order or undef.
3237 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3240 // Upper quadword shuffled.
3241 for (unsigned i = 12; i != 16; ++i)
3242 if (!isUndefOrInRange(Mask[i], 12, 16))
3249 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3250 /// is suitable for input to PSHUFLW.
3251 static bool isPSHUFLWMask(ArrayRef<int> Mask, EVT VT, bool HasAVX2) {
3252 if (VT != MVT::v8i16 && (!HasAVX2 || VT != MVT::v16i16))
3255 // Upper quadword copied in order.
3256 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3259 // Lower quadword shuffled.
3260 for (unsigned i = 0; i != 4; ++i)
3261 if (!isUndefOrInRange(Mask[i], 0, 4))
3264 if (VT == MVT::v16i16) {
3265 // Upper quadword copied in order.
3266 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3269 // Lower quadword shuffled.
3270 for (unsigned i = 8; i != 12; ++i)
3271 if (!isUndefOrInRange(Mask[i], 8, 12))
3278 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
3279 /// is suitable for input to PALIGNR.
3280 static bool isPALIGNRMask(ArrayRef<int> Mask, EVT VT,
3281 const X86Subtarget *Subtarget) {
3282 if ((VT.getSizeInBits() == 128 && !Subtarget->hasSSSE3()) ||
3283 (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2()))
3286 unsigned NumElts = VT.getVectorNumElements();
3287 unsigned NumLanes = VT.getSizeInBits()/128;
3288 unsigned NumLaneElts = NumElts/NumLanes;
3290 // Do not handle 64-bit element shuffles with palignr.
3291 if (NumLaneElts == 2)
3294 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3296 for (i = 0; i != NumLaneElts; ++i) {
3301 // Lane is all undef, go to next lane
3302 if (i == NumLaneElts)
3305 int Start = Mask[i+l];
3307 // Make sure its in this lane in one of the sources
3308 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3309 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3312 // If not lane 0, then we must match lane 0
3313 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3316 // Correct second source to be contiguous with first source
3317 if (Start >= (int)NumElts)
3318 Start -= NumElts - NumLaneElts;
3320 // Make sure we're shifting in the right direction.
3321 if (Start <= (int)(i+l))
3326 // Check the rest of the elements to see if they are consecutive.
3327 for (++i; i != NumLaneElts; ++i) {
3328 int Idx = Mask[i+l];
3330 // Make sure its in this lane
3331 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3332 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3335 // If not lane 0, then we must match lane 0
3336 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3339 if (Idx >= (int)NumElts)
3340 Idx -= NumElts - NumLaneElts;
3342 if (!isUndefOrEqual(Idx, Start+i))
3351 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3352 /// the two vector operands have swapped position.
3353 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
3354 unsigned NumElems) {
3355 for (unsigned i = 0; i != NumElems; ++i) {
3359 else if (idx < (int)NumElems)
3360 Mask[i] = idx + NumElems;
3362 Mask[i] = idx - NumElems;
3366 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
3367 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
3368 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
3369 /// reverse of what x86 shuffles want.
3370 static bool isSHUFPMask(ArrayRef<int> Mask, EVT VT, bool HasAVX,
3371 bool Commuted = false) {
3372 if (!HasAVX && VT.getSizeInBits() == 256)
3375 unsigned NumElems = VT.getVectorNumElements();
3376 unsigned NumLanes = VT.getSizeInBits()/128;
3377 unsigned NumLaneElems = NumElems/NumLanes;
3379 if (NumLaneElems != 2 && NumLaneElems != 4)
3382 // VSHUFPSY divides the resulting vector into 4 chunks.
3383 // The sources are also splitted into 4 chunks, and each destination
3384 // chunk must come from a different source chunk.
3386 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
3387 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
3389 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
3390 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
3392 // VSHUFPDY divides the resulting vector into 4 chunks.
3393 // The sources are also splitted into 4 chunks, and each destination
3394 // chunk must come from a different source chunk.
3396 // SRC1 => X3 X2 X1 X0
3397 // SRC2 => Y3 Y2 Y1 Y0
3399 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
3401 unsigned HalfLaneElems = NumLaneElems/2;
3402 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
3403 for (unsigned i = 0; i != NumLaneElems; ++i) {
3404 int Idx = Mask[i+l];
3405 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
3406 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
3408 // For VSHUFPSY, the mask of the second half must be the same as the
3409 // first but with the appropriate offsets. This works in the same way as
3410 // VPERMILPS works with masks.
3411 if (NumElems != 8 || l == 0 || Mask[i] < 0)
3413 if (!isUndefOrEqual(Idx, Mask[i]+l))
3421 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3422 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3423 static bool isMOVHLPSMask(ArrayRef<int> Mask, EVT VT) {
3424 unsigned NumElems = VT.getVectorNumElements();
3426 if (VT.getSizeInBits() != 128)
3432 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3433 return isUndefOrEqual(Mask[0], 6) &&
3434 isUndefOrEqual(Mask[1], 7) &&
3435 isUndefOrEqual(Mask[2], 2) &&
3436 isUndefOrEqual(Mask[3], 3);
3439 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3440 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3442 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, EVT VT) {
3443 unsigned NumElems = VT.getVectorNumElements();
3445 if (VT.getSizeInBits() != 128)
3451 return isUndefOrEqual(Mask[0], 2) &&
3452 isUndefOrEqual(Mask[1], 3) &&
3453 isUndefOrEqual(Mask[2], 2) &&
3454 isUndefOrEqual(Mask[3], 3);
3457 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3458 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3459 static bool isMOVLPMask(ArrayRef<int> Mask, EVT VT) {
3460 if (VT.getSizeInBits() != 128)
3463 unsigned NumElems = VT.getVectorNumElements();
3465 if (NumElems != 2 && NumElems != 4)
3468 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3469 if (!isUndefOrEqual(Mask[i], i + NumElems))
3472 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
3473 if (!isUndefOrEqual(Mask[i], i))
3479 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3480 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3481 static bool isMOVLHPSMask(ArrayRef<int> Mask, EVT VT) {
3482 unsigned NumElems = VT.getVectorNumElements();
3484 if ((NumElems != 2 && NumElems != 4)
3485 || VT.getSizeInBits() > 128)
3488 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3489 if (!isUndefOrEqual(Mask[i], i))
3492 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3493 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
3499 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
3500 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
3501 static bool isUNPCKLMask(ArrayRef<int> Mask, EVT VT,
3502 bool HasAVX2, bool V2IsSplat = false) {
3503 unsigned NumElts = VT.getVectorNumElements();
3505 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3506 "Unsupported vector type for unpckh");
3508 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3509 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3512 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3513 // independently on 128-bit lanes.
3514 unsigned NumLanes = VT.getSizeInBits()/128;
3515 unsigned NumLaneElts = NumElts/NumLanes;
3517 for (unsigned l = 0; l != NumLanes; ++l) {
3518 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts;
3519 i != (l+1)*NumLaneElts;
3522 int BitI1 = Mask[i+1];
3523 if (!isUndefOrEqual(BitI, j))
3526 if (!isUndefOrEqual(BitI1, NumElts))
3529 if (!isUndefOrEqual(BitI1, j + NumElts))
3538 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
3539 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
3540 static bool isUNPCKHMask(ArrayRef<int> Mask, EVT VT,
3541 bool HasAVX2, bool V2IsSplat = false) {
3542 unsigned NumElts = VT.getVectorNumElements();
3544 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3545 "Unsupported vector type for unpckh");
3547 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3548 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3551 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3552 // independently on 128-bit lanes.
3553 unsigned NumLanes = VT.getSizeInBits()/128;
3554 unsigned NumLaneElts = NumElts/NumLanes;
3556 for (unsigned l = 0; l != NumLanes; ++l) {
3557 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2;
3558 i != (l+1)*NumLaneElts; i += 2, ++j) {
3560 int BitI1 = Mask[i+1];
3561 if (!isUndefOrEqual(BitI, j))
3564 if (isUndefOrEqual(BitI1, NumElts))
3567 if (!isUndefOrEqual(BitI1, j+NumElts))
3575 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
3576 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
3578 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, EVT VT,
3580 unsigned NumElts = VT.getVectorNumElements();
3582 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3583 "Unsupported vector type for unpckh");
3585 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3586 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3589 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
3590 // FIXME: Need a better way to get rid of this, there's no latency difference
3591 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
3592 // the former later. We should also remove the "_undef" special mask.
3593 if (NumElts == 4 && VT.getSizeInBits() == 256)
3596 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3597 // independently on 128-bit lanes.
3598 unsigned NumLanes = VT.getSizeInBits()/128;
3599 unsigned NumLaneElts = NumElts/NumLanes;
3601 for (unsigned l = 0; l != NumLanes; ++l) {
3602 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts;
3603 i != (l+1)*NumLaneElts;
3606 int BitI1 = Mask[i+1];
3608 if (!isUndefOrEqual(BitI, j))
3610 if (!isUndefOrEqual(BitI1, j))
3618 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
3619 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
3621 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, EVT VT, bool HasAVX2) {
3622 unsigned NumElts = VT.getVectorNumElements();
3624 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3625 "Unsupported vector type for unpckh");
3627 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3628 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3631 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3632 // independently on 128-bit lanes.
3633 unsigned NumLanes = VT.getSizeInBits()/128;
3634 unsigned NumLaneElts = NumElts/NumLanes;
3636 for (unsigned l = 0; l != NumLanes; ++l) {
3637 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2;
3638 i != (l+1)*NumLaneElts; i += 2, ++j) {
3640 int BitI1 = Mask[i+1];
3641 if (!isUndefOrEqual(BitI, j))
3643 if (!isUndefOrEqual(BitI1, j))
3650 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
3651 /// specifies a shuffle of elements that is suitable for input to MOVSS,
3652 /// MOVSD, and MOVD, i.e. setting the lowest element.
3653 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
3654 if (VT.getVectorElementType().getSizeInBits() < 32)
3656 if (VT.getSizeInBits() == 256)
3659 unsigned NumElts = VT.getVectorNumElements();
3661 if (!isUndefOrEqual(Mask[0], NumElts))
3664 for (unsigned i = 1; i != NumElts; ++i)
3665 if (!isUndefOrEqual(Mask[i], i))
3671 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
3672 /// as permutations between 128-bit chunks or halves. As an example: this
3674 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
3675 /// The first half comes from the second half of V1 and the second half from the
3676 /// the second half of V2.
3677 static bool isVPERM2X128Mask(ArrayRef<int> Mask, EVT VT, bool HasAVX) {
3678 if (!HasAVX || VT.getSizeInBits() != 256)
3681 // The shuffle result is divided into half A and half B. In total the two
3682 // sources have 4 halves, namely: C, D, E, F. The final values of A and
3683 // B must come from C, D, E or F.
3684 unsigned HalfSize = VT.getVectorNumElements()/2;
3685 bool MatchA = false, MatchB = false;
3687 // Check if A comes from one of C, D, E, F.
3688 for (unsigned Half = 0; Half != 4; ++Half) {
3689 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
3695 // Check if B comes from one of C, D, E, F.
3696 for (unsigned Half = 0; Half != 4; ++Half) {
3697 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
3703 return MatchA && MatchB;
3706 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
3707 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
3708 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
3709 EVT VT = SVOp->getValueType(0);
3711 unsigned HalfSize = VT.getVectorNumElements()/2;
3713 unsigned FstHalf = 0, SndHalf = 0;
3714 for (unsigned i = 0; i < HalfSize; ++i) {
3715 if (SVOp->getMaskElt(i) > 0) {
3716 FstHalf = SVOp->getMaskElt(i)/HalfSize;
3720 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
3721 if (SVOp->getMaskElt(i) > 0) {
3722 SndHalf = SVOp->getMaskElt(i)/HalfSize;
3727 return (FstHalf | (SndHalf << 4));
3730 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
3731 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
3732 /// Note that VPERMIL mask matching is different depending whether theunderlying
3733 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
3734 /// to the same elements of the low, but to the higher half of the source.
3735 /// In VPERMILPD the two lanes could be shuffled independently of each other
3736 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
3737 static bool isVPERMILPMask(ArrayRef<int> Mask, EVT VT, bool HasAVX) {
3741 unsigned NumElts = VT.getVectorNumElements();
3742 // Only match 256-bit with 32/64-bit types
3743 if (VT.getSizeInBits() != 256 || (NumElts != 4 && NumElts != 8))
3746 unsigned NumLanes = VT.getSizeInBits()/128;
3747 unsigned LaneSize = NumElts/NumLanes;
3748 for (unsigned l = 0; l != NumElts; l += LaneSize) {
3749 for (unsigned i = 0; i != LaneSize; ++i) {
3750 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
3752 if (NumElts != 8 || l == 0)
3754 // VPERMILPS handling
3757 if (!isUndefOrEqual(Mask[i+l], Mask[i]+l))
3765 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
3766 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
3767 /// element of vector 2 and the other elements to come from vector 1 in order.
3768 static bool isCommutedMOVLMask(ArrayRef<int> Mask, EVT VT,
3769 bool V2IsSplat = false, bool V2IsUndef = false) {
3770 unsigned NumOps = VT.getVectorNumElements();
3771 if (VT.getSizeInBits() == 256)
3773 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
3776 if (!isUndefOrEqual(Mask[0], 0))
3779 for (unsigned i = 1; i != NumOps; ++i)
3780 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
3781 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
3782 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
3788 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3789 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
3790 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
3791 static bool isMOVSHDUPMask(ArrayRef<int> Mask, EVT VT,
3792 const X86Subtarget *Subtarget) {
3793 if (!Subtarget->hasSSE3())
3796 unsigned NumElems = VT.getVectorNumElements();
3798 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3799 (VT.getSizeInBits() == 256 && NumElems != 8))
3802 // "i+1" is the value the indexed mask element must have
3803 for (unsigned i = 0; i != NumElems; i += 2)
3804 if (!isUndefOrEqual(Mask[i], i+1) ||
3805 !isUndefOrEqual(Mask[i+1], i+1))
3811 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3812 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
3813 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
3814 static bool isMOVSLDUPMask(ArrayRef<int> Mask, EVT VT,
3815 const X86Subtarget *Subtarget) {
3816 if (!Subtarget->hasSSE3())
3819 unsigned NumElems = VT.getVectorNumElements();
3821 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3822 (VT.getSizeInBits() == 256 && NumElems != 8))
3825 // "i" is the value the indexed mask element must have
3826 for (unsigned i = 0; i != NumElems; i += 2)
3827 if (!isUndefOrEqual(Mask[i], i) ||
3828 !isUndefOrEqual(Mask[i+1], i))
3834 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
3835 /// specifies a shuffle of elements that is suitable for input to 256-bit
3836 /// version of MOVDDUP.
3837 static bool isMOVDDUPYMask(ArrayRef<int> Mask, EVT VT, bool HasAVX) {
3838 unsigned NumElts = VT.getVectorNumElements();
3840 if (!HasAVX || VT.getSizeInBits() != 256 || NumElts != 4)
3843 for (unsigned i = 0; i != NumElts/2; ++i)
3844 if (!isUndefOrEqual(Mask[i], 0))
3846 for (unsigned i = NumElts/2; i != NumElts; ++i)
3847 if (!isUndefOrEqual(Mask[i], NumElts/2))
3852 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3853 /// specifies a shuffle of elements that is suitable for input to 128-bit
3854 /// version of MOVDDUP.
3855 static bool isMOVDDUPMask(ArrayRef<int> Mask, EVT VT) {
3856 if (VT.getSizeInBits() != 128)
3859 unsigned e = VT.getVectorNumElements() / 2;
3860 for (unsigned i = 0; i != e; ++i)
3861 if (!isUndefOrEqual(Mask[i], i))
3863 for (unsigned i = 0; i != e; ++i)
3864 if (!isUndefOrEqual(Mask[e+i], i))
3869 /// isVEXTRACTF128Index - Return true if the specified
3870 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
3871 /// suitable for input to VEXTRACTF128.
3872 bool X86::isVEXTRACTF128Index(SDNode *N) {
3873 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3876 // The index should be aligned on a 128-bit boundary.
3878 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3880 unsigned VL = N->getValueType(0).getVectorNumElements();
3881 unsigned VBits = N->getValueType(0).getSizeInBits();
3882 unsigned ElSize = VBits / VL;
3883 bool Result = (Index * ElSize) % 128 == 0;
3888 /// isVINSERTF128Index - Return true if the specified INSERT_SUBVECTOR
3889 /// operand specifies a subvector insert that is suitable for input to
3891 bool X86::isVINSERTF128Index(SDNode *N) {
3892 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3895 // The index should be aligned on a 128-bit boundary.
3897 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3899 unsigned VL = N->getValueType(0).getVectorNumElements();
3900 unsigned VBits = N->getValueType(0).getSizeInBits();
3901 unsigned ElSize = VBits / VL;
3902 bool Result = (Index * ElSize) % 128 == 0;
3907 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
3908 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
3909 /// Handles 128-bit and 256-bit.
3910 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
3911 EVT VT = N->getValueType(0);
3913 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3914 "Unsupported vector type for PSHUF/SHUFP");
3916 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
3917 // independently on 128-bit lanes.
3918 unsigned NumElts = VT.getVectorNumElements();
3919 unsigned NumLanes = VT.getSizeInBits()/128;
3920 unsigned NumLaneElts = NumElts/NumLanes;
3922 assert((NumLaneElts == 2 || NumLaneElts == 4) &&
3923 "Only supports 2 or 4 elements per lane");
3925 unsigned Shift = (NumLaneElts == 4) ? 1 : 0;
3927 for (unsigned i = 0; i != NumElts; ++i) {
3928 int Elt = N->getMaskElt(i);
3929 if (Elt < 0) continue;
3930 Elt &= NumLaneElts - 1;
3931 unsigned ShAmt = (i << Shift) % 8;
3932 Mask |= Elt << ShAmt;
3938 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
3939 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
3940 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
3941 EVT VT = N->getValueType(0);
3943 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
3944 "Unsupported vector type for PSHUFHW");
3946 unsigned NumElts = VT.getVectorNumElements();
3949 for (unsigned l = 0; l != NumElts; l += 8) {
3950 // 8 nodes per lane, but we only care about the last 4.
3951 for (unsigned i = 0; i < 4; ++i) {
3952 int Elt = N->getMaskElt(l+i+4);
3953 if (Elt < 0) continue;
3954 Elt &= 0x3; // only 2-bits.
3955 Mask |= Elt << (i * 2);
3962 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
3963 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
3964 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
3965 EVT VT = N->getValueType(0);
3967 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
3968 "Unsupported vector type for PSHUFHW");
3970 unsigned NumElts = VT.getVectorNumElements();
3973 for (unsigned l = 0; l != NumElts; l += 8) {
3974 // 8 nodes per lane, but we only care about the first 4.
3975 for (unsigned i = 0; i < 4; ++i) {
3976 int Elt = N->getMaskElt(l+i);
3977 if (Elt < 0) continue;
3978 Elt &= 0x3; // only 2-bits
3979 Mask |= Elt << (i * 2);
3986 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
3987 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
3988 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
3989 EVT VT = SVOp->getValueType(0);
3990 unsigned EltSize = VT.getVectorElementType().getSizeInBits() >> 3;
3992 unsigned NumElts = VT.getVectorNumElements();
3993 unsigned NumLanes = VT.getSizeInBits()/128;
3994 unsigned NumLaneElts = NumElts/NumLanes;
3998 for (i = 0; i != NumElts; ++i) {
3999 Val = SVOp->getMaskElt(i);
4003 if (Val >= (int)NumElts)
4004 Val -= NumElts - NumLaneElts;
4006 assert(Val - i > 0 && "PALIGNR imm should be positive");
4007 return (Val - i) * EltSize;
4010 /// getExtractVEXTRACTF128Immediate - Return the appropriate immediate
4011 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4013 unsigned X86::getExtractVEXTRACTF128Immediate(SDNode *N) {
4014 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4015 llvm_unreachable("Illegal extract subvector for VEXTRACTF128");
4018 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4020 EVT VecVT = N->getOperand(0).getValueType();
4021 EVT ElVT = VecVT.getVectorElementType();
4023 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
4024 return Index / NumElemsPerChunk;
4027 /// getInsertVINSERTF128Immediate - Return the appropriate immediate
4028 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4030 unsigned X86::getInsertVINSERTF128Immediate(SDNode *N) {
4031 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4032 llvm_unreachable("Illegal insert subvector for VINSERTF128");
4035 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4037 EVT VecVT = N->getValueType(0);
4038 EVT ElVT = VecVT.getVectorElementType();
4040 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
4041 return Index / NumElemsPerChunk;
4044 /// getShuffleCLImmediate - Return the appropriate immediate to shuffle
4045 /// the specified VECTOR_SHUFFLE mask with VPERMQ and VPERMPD instructions.
4046 /// Handles 256-bit.
4047 static unsigned getShuffleCLImmediate(ShuffleVectorSDNode *N) {
4048 EVT VT = N->getValueType(0);
4050 unsigned NumElts = VT.getVectorNumElements();
4052 assert((VT.is256BitVector() && NumElts == 4) &&
4053 "Unsupported vector type for VPERMQ/VPERMPD");
4056 for (unsigned i = 0; i != NumElts; ++i) {
4057 int Elt = N->getMaskElt(i);
4060 Mask |= Elt << (i*2);
4065 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4067 bool X86::isZeroNode(SDValue Elt) {
4068 return ((isa<ConstantSDNode>(Elt) &&
4069 cast<ConstantSDNode>(Elt)->isNullValue()) ||
4070 (isa<ConstantFPSDNode>(Elt) &&
4071 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
4074 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
4075 /// their permute mask.
4076 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
4077 SelectionDAG &DAG) {
4078 EVT VT = SVOp->getValueType(0);
4079 unsigned NumElems = VT.getVectorNumElements();
4080 SmallVector<int, 8> MaskVec;
4082 for (unsigned i = 0; i != NumElems; ++i) {
4083 int Idx = SVOp->getMaskElt(i);
4085 if (Idx < (int)NumElems)
4090 MaskVec.push_back(Idx);
4092 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
4093 SVOp->getOperand(0), &MaskVec[0]);
4096 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4097 /// match movhlps. The lower half elements should come from upper half of
4098 /// V1 (and in order), and the upper half elements should come from the upper
4099 /// half of V2 (and in order).
4100 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, EVT VT) {
4101 if (VT.getSizeInBits() != 128)
4103 if (VT.getVectorNumElements() != 4)
4105 for (unsigned i = 0, e = 2; i != e; ++i)
4106 if (!isUndefOrEqual(Mask[i], i+2))
4108 for (unsigned i = 2; i != 4; ++i)
4109 if (!isUndefOrEqual(Mask[i], i+4))
4114 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4115 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4117 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
4118 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4120 N = N->getOperand(0).getNode();
4121 if (!ISD::isNON_EXTLoad(N))
4124 *LD = cast<LoadSDNode>(N);
4128 // Test whether the given value is a vector value which will be legalized
4130 static bool WillBeConstantPoolLoad(SDNode *N) {
4131 if (N->getOpcode() != ISD::BUILD_VECTOR)
4134 // Check for any non-constant elements.
4135 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4136 switch (N->getOperand(i).getNode()->getOpcode()) {
4138 case ISD::ConstantFP:
4145 // Vectors of all-zeros and all-ones are materialized with special
4146 // instructions rather than being loaded.
4147 return !ISD::isBuildVectorAllZeros(N) &&
4148 !ISD::isBuildVectorAllOnes(N);
4151 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4152 /// match movlp{s|d}. The lower half elements should come from lower half of
4153 /// V1 (and in order), and the upper half elements should come from the upper
4154 /// half of V2 (and in order). And since V1 will become the source of the
4155 /// MOVLP, it must be either a vector load or a scalar load to vector.
4156 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
4157 ArrayRef<int> Mask, EVT VT) {
4158 if (VT.getSizeInBits() != 128)
4161 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
4163 // Is V2 is a vector load, don't do this transformation. We will try to use
4164 // load folding shufps op.
4165 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
4168 unsigned NumElems = VT.getVectorNumElements();
4170 if (NumElems != 2 && NumElems != 4)
4172 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4173 if (!isUndefOrEqual(Mask[i], i))
4175 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4176 if (!isUndefOrEqual(Mask[i], i+NumElems))
4181 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
4183 static bool isSplatVector(SDNode *N) {
4184 if (N->getOpcode() != ISD::BUILD_VECTOR)
4187 SDValue SplatValue = N->getOperand(0);
4188 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
4189 if (N->getOperand(i) != SplatValue)
4194 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
4195 /// to an zero vector.
4196 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
4197 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
4198 SDValue V1 = N->getOperand(0);
4199 SDValue V2 = N->getOperand(1);
4200 unsigned NumElems = N->getValueType(0).getVectorNumElements();
4201 for (unsigned i = 0; i != NumElems; ++i) {
4202 int Idx = N->getMaskElt(i);
4203 if (Idx >= (int)NumElems) {
4204 unsigned Opc = V2.getOpcode();
4205 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4207 if (Opc != ISD::BUILD_VECTOR ||
4208 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
4210 } else if (Idx >= 0) {
4211 unsigned Opc = V1.getOpcode();
4212 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
4214 if (Opc != ISD::BUILD_VECTOR ||
4215 !X86::isZeroNode(V1.getOperand(Idx)))
4222 /// getZeroVector - Returns a vector of specified type with all zero elements.
4224 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4225 SelectionDAG &DAG, DebugLoc dl) {
4226 assert(VT.isVector() && "Expected a vector type");
4227 unsigned Size = VT.getSizeInBits();
4229 // Always build SSE zero vectors as <4 x i32> bitcasted
4230 // to their dest type. This ensures they get CSE'd.
4232 if (Size == 128) { // SSE
4233 if (Subtarget->hasSSE2()) { // SSE2
4234 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4235 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4237 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4238 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4240 } else if (Size == 256) { // AVX
4241 if (Subtarget->hasAVX2()) { // AVX2
4242 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4243 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4244 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8);
4246 // 256-bit logic and arithmetic instructions in AVX are all
4247 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4248 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4249 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4250 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8);
4253 llvm_unreachable("Unexpected vector type");
4255 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4258 /// getOnesVector - Returns a vector of specified type with all bits set.
4259 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4260 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4261 /// Then bitcast to their original type, ensuring they get CSE'd.
4262 static SDValue getOnesVector(EVT VT, bool HasAVX2, SelectionDAG &DAG,
4264 assert(VT.isVector() && "Expected a vector type");
4265 unsigned Size = VT.getSizeInBits();
4267 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
4270 if (HasAVX2) { // AVX2
4271 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4272 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8);
4274 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4275 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4277 } else if (Size == 128) {
4278 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4280 llvm_unreachable("Unexpected vector type");
4282 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4285 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
4286 /// that point to V2 points to its first element.
4287 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
4288 for (unsigned i = 0; i != NumElems; ++i) {
4289 if (Mask[i] > (int)NumElems) {
4295 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4296 /// operation of specified width.
4297 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4299 unsigned NumElems = VT.getVectorNumElements();
4300 SmallVector<int, 8> Mask;
4301 Mask.push_back(NumElems);
4302 for (unsigned i = 1; i != NumElems; ++i)
4304 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4307 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4308 static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4310 unsigned NumElems = VT.getVectorNumElements();
4311 SmallVector<int, 8> Mask;
4312 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4314 Mask.push_back(i + NumElems);
4316 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4319 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4320 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4322 unsigned NumElems = VT.getVectorNumElements();
4323 SmallVector<int, 8> Mask;
4324 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4325 Mask.push_back(i + Half);
4326 Mask.push_back(i + NumElems + Half);
4328 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4331 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
4332 // a generic shuffle instruction because the target has no such instructions.
4333 // Generate shuffles which repeat i16 and i8 several times until they can be
4334 // represented by v4f32 and then be manipulated by target suported shuffles.
4335 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
4336 EVT VT = V.getValueType();
4337 int NumElems = VT.getVectorNumElements();
4338 DebugLoc dl = V.getDebugLoc();
4340 while (NumElems > 4) {
4341 if (EltNo < NumElems/2) {
4342 V = getUnpackl(DAG, dl, VT, V, V);
4344 V = getUnpackh(DAG, dl, VT, V, V);
4345 EltNo -= NumElems/2;
4352 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
4353 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
4354 EVT VT = V.getValueType();
4355 DebugLoc dl = V.getDebugLoc();
4356 unsigned Size = VT.getSizeInBits();
4359 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
4360 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
4361 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
4363 } else if (Size == 256) {
4364 // To use VPERMILPS to splat scalars, the second half of indicies must
4365 // refer to the higher part, which is a duplication of the lower one,
4366 // because VPERMILPS can only handle in-lane permutations.
4367 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
4368 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
4370 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
4371 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
4374 llvm_unreachable("Vector size not supported");
4376 return DAG.getNode(ISD::BITCAST, dl, VT, V);
4379 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
4380 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
4381 EVT SrcVT = SV->getValueType(0);
4382 SDValue V1 = SV->getOperand(0);
4383 DebugLoc dl = SV->getDebugLoc();
4385 int EltNo = SV->getSplatIndex();
4386 int NumElems = SrcVT.getVectorNumElements();
4387 unsigned Size = SrcVT.getSizeInBits();
4389 assert(((Size == 128 && NumElems > 4) || Size == 256) &&
4390 "Unknown how to promote splat for type");
4392 // Extract the 128-bit part containing the splat element and update
4393 // the splat element index when it refers to the higher register.
4395 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
4396 if (EltNo >= NumElems/2)
4397 EltNo -= NumElems/2;
4400 // All i16 and i8 vector types can't be used directly by a generic shuffle
4401 // instruction because the target has no such instruction. Generate shuffles
4402 // which repeat i16 and i8 several times until they fit in i32, and then can
4403 // be manipulated by target suported shuffles.
4404 EVT EltVT = SrcVT.getVectorElementType();
4405 if (EltVT == MVT::i8 || EltVT == MVT::i16)
4406 V1 = PromoteSplati8i16(V1, DAG, EltNo);
4408 // Recreate the 256-bit vector and place the same 128-bit vector
4409 // into the low and high part. This is necessary because we want
4410 // to use VPERM* to shuffle the vectors
4412 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
4415 return getLegalSplat(DAG, V1, EltNo);
4418 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4419 /// vector of zero or undef vector. This produces a shuffle where the low
4420 /// element of V2 is swizzled into the zero/undef vector, landing at element
4421 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4422 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4424 const X86Subtarget *Subtarget,
4425 SelectionDAG &DAG) {
4426 EVT VT = V2.getValueType();
4428 ? getZeroVector(VT, Subtarget, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT);
4429 unsigned NumElems = VT.getVectorNumElements();
4430 SmallVector<int, 16> MaskVec;
4431 for (unsigned i = 0; i != NumElems; ++i)
4432 // If this is the insertion idx, put the low elt of V2 here.
4433 MaskVec.push_back(i == Idx ? NumElems : i);
4434 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
4437 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
4438 /// target specific opcode. Returns true if the Mask could be calculated.
4439 /// Sets IsUnary to true if only uses one source.
4440 static bool getTargetShuffleMask(SDNode *N, MVT VT,
4441 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4442 unsigned NumElems = VT.getVectorNumElements();
4446 switch(N->getOpcode()) {
4448 ImmN = N->getOperand(N->getNumOperands()-1);
4449 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4451 case X86ISD::UNPCKH:
4452 DecodeUNPCKHMask(VT, Mask);
4454 case X86ISD::UNPCKL:
4455 DecodeUNPCKLMask(VT, Mask);
4457 case X86ISD::MOVHLPS:
4458 DecodeMOVHLPSMask(NumElems, Mask);
4460 case X86ISD::MOVLHPS:
4461 DecodeMOVLHPSMask(NumElems, Mask);
4463 case X86ISD::PSHUFD:
4464 case X86ISD::VPERMILP:
4465 ImmN = N->getOperand(N->getNumOperands()-1);
4466 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4469 case X86ISD::PSHUFHW:
4470 ImmN = N->getOperand(N->getNumOperands()-1);
4471 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4474 case X86ISD::PSHUFLW:
4475 ImmN = N->getOperand(N->getNumOperands()-1);
4476 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4479 case X86ISD::VPERMI:
4480 ImmN = N->getOperand(N->getNumOperands()-1);
4481 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4485 case X86ISD::MOVSD: {
4486 // The index 0 always comes from the first element of the second source,
4487 // this is why MOVSS and MOVSD are used in the first place. The other
4488 // elements come from the other positions of the first source vector
4489 Mask.push_back(NumElems);
4490 for (unsigned i = 1; i != NumElems; ++i) {
4495 case X86ISD::VPERM2X128:
4496 ImmN = N->getOperand(N->getNumOperands()-1);
4497 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4498 if (Mask.empty()) return false;
4500 case X86ISD::MOVDDUP:
4501 case X86ISD::MOVLHPD:
4502 case X86ISD::MOVLPD:
4503 case X86ISD::MOVLPS:
4504 case X86ISD::MOVSHDUP:
4505 case X86ISD::MOVSLDUP:
4506 case X86ISD::PALIGN:
4507 // Not yet implemented
4509 default: llvm_unreachable("unknown target shuffle node");
4515 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4516 /// element of the result of the vector shuffle.
4517 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
4520 return SDValue(); // Limit search depth.
4522 SDValue V = SDValue(N, 0);
4523 EVT VT = V.getValueType();
4524 unsigned Opcode = V.getOpcode();
4526 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4527 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4528 int Elt = SV->getMaskElt(Index);
4531 return DAG.getUNDEF(VT.getVectorElementType());
4533 unsigned NumElems = VT.getVectorNumElements();
4534 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
4535 : SV->getOperand(1);
4536 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
4539 // Recurse into target specific vector shuffles to find scalars.
4540 if (isTargetShuffle(Opcode)) {
4541 MVT ShufVT = V.getValueType().getSimpleVT();
4542 unsigned NumElems = ShufVT.getVectorNumElements();
4543 SmallVector<int, 16> ShuffleMask;
4547 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
4550 int Elt = ShuffleMask[Index];
4552 return DAG.getUNDEF(ShufVT.getVectorElementType());
4554 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
4556 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
4560 // Actual nodes that may contain scalar elements
4561 if (Opcode == ISD::BITCAST) {
4562 V = V.getOperand(0);
4563 EVT SrcVT = V.getValueType();
4564 unsigned NumElems = VT.getVectorNumElements();
4566 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4570 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4571 return (Index == 0) ? V.getOperand(0)
4572 : DAG.getUNDEF(VT.getVectorElementType());
4574 if (V.getOpcode() == ISD::BUILD_VECTOR)
4575 return V.getOperand(Index);
4580 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
4581 /// shuffle operation which come from a consecutively from a zero. The
4582 /// search can start in two different directions, from left or right.
4584 unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp, unsigned NumElems,
4585 bool ZerosFromLeft, SelectionDAG &DAG) {
4587 for (i = 0; i != NumElems; ++i) {
4588 unsigned Index = ZerosFromLeft ? i : NumElems-i-1;
4589 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
4590 if (!(Elt.getNode() &&
4591 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt))))
4598 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
4599 /// correspond consecutively to elements from one of the vector operands,
4600 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
4602 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
4603 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
4604 unsigned NumElems, unsigned &OpNum) {
4605 bool SeenV1 = false;
4606 bool SeenV2 = false;
4608 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
4609 int Idx = SVOp->getMaskElt(i);
4610 // Ignore undef indicies
4614 if (Idx < (int)NumElems)
4619 // Only accept consecutive elements from the same vector
4620 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
4624 OpNum = SeenV1 ? 0 : 1;
4628 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
4629 /// logical left shift of a vector.
4630 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4631 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4632 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4633 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4634 false /* check zeros from right */, DAG);
4640 // Considering the elements in the mask that are not consecutive zeros,
4641 // check if they consecutively come from only one of the source vectors.
4643 // V1 = {X, A, B, C} 0
4645 // vector_shuffle V1, V2 <1, 2, 3, X>
4647 if (!isShuffleMaskConsecutive(SVOp,
4648 0, // Mask Start Index
4649 NumElems-NumZeros, // Mask End Index(exclusive)
4650 NumZeros, // Where to start looking in the src vector
4651 NumElems, // Number of elements in vector
4652 OpSrc)) // Which source operand ?
4657 ShVal = SVOp->getOperand(OpSrc);
4661 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
4662 /// logical left shift of a vector.
4663 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4664 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4665 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4666 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4667 true /* check zeros from left */, DAG);
4673 // Considering the elements in the mask that are not consecutive zeros,
4674 // check if they consecutively come from only one of the source vectors.
4676 // 0 { A, B, X, X } = V2
4678 // vector_shuffle V1, V2 <X, X, 4, 5>
4680 if (!isShuffleMaskConsecutive(SVOp,
4681 NumZeros, // Mask Start Index
4682 NumElems, // Mask End Index(exclusive)
4683 0, // Where to start looking in the src vector
4684 NumElems, // Number of elements in vector
4685 OpSrc)) // Which source operand ?
4690 ShVal = SVOp->getOperand(OpSrc);
4694 /// isVectorShift - Returns true if the shuffle can be implemented as a
4695 /// logical left or right shift of a vector.
4696 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4697 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4698 // Although the logic below support any bitwidth size, there are no
4699 // shift instructions which handle more than 128-bit vectors.
4700 if (SVOp->getValueType(0).getSizeInBits() > 128)
4703 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
4704 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
4710 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
4712 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4713 unsigned NumNonZero, unsigned NumZero,
4715 const X86Subtarget* Subtarget,
4716 const TargetLowering &TLI) {
4720 DebugLoc dl = Op.getDebugLoc();
4723 for (unsigned i = 0; i < 16; ++i) {
4724 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4725 if (ThisIsNonZero && First) {
4727 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4729 V = DAG.getUNDEF(MVT::v8i16);
4734 SDValue ThisElt(0, 0), LastElt(0, 0);
4735 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4736 if (LastIsNonZero) {
4737 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4738 MVT::i16, Op.getOperand(i-1));
4740 if (ThisIsNonZero) {
4741 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4742 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4743 ThisElt, DAG.getConstant(8, MVT::i8));
4745 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4749 if (ThisElt.getNode())
4750 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
4751 DAG.getIntPtrConstant(i/2));
4755 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
4758 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
4760 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
4761 unsigned NumNonZero, unsigned NumZero,
4763 const X86Subtarget* Subtarget,
4764 const TargetLowering &TLI) {
4768 DebugLoc dl = Op.getDebugLoc();
4771 for (unsigned i = 0; i < 8; ++i) {
4772 bool isNonZero = (NonZeros & (1 << i)) != 0;
4776 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4778 V = DAG.getUNDEF(MVT::v8i16);
4781 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4782 MVT::v8i16, V, Op.getOperand(i),
4783 DAG.getIntPtrConstant(i));
4790 /// getVShift - Return a vector logical shift node.
4792 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
4793 unsigned NumBits, SelectionDAG &DAG,
4794 const TargetLowering &TLI, DebugLoc dl) {
4795 assert(VT.getSizeInBits() == 128 && "Unknown type for VShift");
4796 EVT ShVT = MVT::v2i64;
4797 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
4798 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
4799 return DAG.getNode(ISD::BITCAST, dl, VT,
4800 DAG.getNode(Opc, dl, ShVT, SrcOp,
4801 DAG.getConstant(NumBits,
4802 TLI.getShiftAmountTy(SrcOp.getValueType()))));
4806 X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
4807 SelectionDAG &DAG) const {
4809 // Check if the scalar load can be widened into a vector load. And if
4810 // the address is "base + cst" see if the cst can be "absorbed" into
4811 // the shuffle mask.
4812 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
4813 SDValue Ptr = LD->getBasePtr();
4814 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
4816 EVT PVT = LD->getValueType(0);
4817 if (PVT != MVT::i32 && PVT != MVT::f32)
4822 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
4823 FI = FINode->getIndex();
4825 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
4826 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4827 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4828 Offset = Ptr.getConstantOperandVal(1);
4829 Ptr = Ptr.getOperand(0);
4834 // FIXME: 256-bit vector instructions don't require a strict alignment,
4835 // improve this code to support it better.
4836 unsigned RequiredAlign = VT.getSizeInBits()/8;
4837 SDValue Chain = LD->getChain();
4838 // Make sure the stack object alignment is at least 16 or 32.
4839 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4840 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
4841 if (MFI->isFixedObjectIndex(FI)) {
4842 // Can't change the alignment. FIXME: It's possible to compute
4843 // the exact stack offset and reference FI + adjust offset instead.
4844 // If someone *really* cares about this. That's the way to implement it.
4847 MFI->setObjectAlignment(FI, RequiredAlign);
4851 // (Offset % 16 or 32) must be multiple of 4. Then address is then
4852 // Ptr + (Offset & ~15).
4855 if ((Offset % RequiredAlign) & 3)
4857 int64_t StartOffset = Offset & ~(RequiredAlign-1);
4859 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(),
4860 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
4862 int EltNo = (Offset - StartOffset) >> 2;
4863 unsigned NumElems = VT.getVectorNumElements();
4865 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
4866 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
4867 LD->getPointerInfo().getWithOffset(StartOffset),
4868 false, false, false, 0);
4870 SmallVector<int, 8> Mask;
4871 for (unsigned i = 0; i != NumElems; ++i)
4872 Mask.push_back(EltNo);
4874 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
4880 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
4881 /// vector of type 'VT', see if the elements can be replaced by a single large
4882 /// load which has the same value as a build_vector whose operands are 'elts'.
4884 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
4886 /// FIXME: we'd also like to handle the case where the last elements are zero
4887 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
4888 /// There's even a handy isZeroNode for that purpose.
4889 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
4890 DebugLoc &DL, SelectionDAG &DAG) {
4891 EVT EltVT = VT.getVectorElementType();
4892 unsigned NumElems = Elts.size();
4894 LoadSDNode *LDBase = NULL;
4895 unsigned LastLoadedElt = -1U;
4897 // For each element in the initializer, see if we've found a load or an undef.
4898 // If we don't find an initial load element, or later load elements are
4899 // non-consecutive, bail out.
4900 for (unsigned i = 0; i < NumElems; ++i) {
4901 SDValue Elt = Elts[i];
4903 if (!Elt.getNode() ||
4904 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
4907 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
4909 LDBase = cast<LoadSDNode>(Elt.getNode());
4913 if (Elt.getOpcode() == ISD::UNDEF)
4916 LoadSDNode *LD = cast<LoadSDNode>(Elt);
4917 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
4922 // If we have found an entire vector of loads and undefs, then return a large
4923 // load of the entire vector width starting at the base pointer. If we found
4924 // consecutive loads for the low half, generate a vzext_load node.
4925 if (LastLoadedElt == NumElems - 1) {
4926 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
4927 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4928 LDBase->getPointerInfo(),
4929 LDBase->isVolatile(), LDBase->isNonTemporal(),
4930 LDBase->isInvariant(), 0);
4931 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4932 LDBase->getPointerInfo(),
4933 LDBase->isVolatile(), LDBase->isNonTemporal(),
4934 LDBase->isInvariant(), LDBase->getAlignment());
4936 if (NumElems == 4 && LastLoadedElt == 1 &&
4937 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
4938 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
4939 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
4941 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, 2, MVT::i64,
4942 LDBase->getPointerInfo(),
4943 LDBase->getAlignment(),
4944 false/*isVolatile*/, true/*ReadMem*/,
4946 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
4951 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
4952 /// to generate a splat value for the following cases:
4953 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
4954 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
4955 /// a scalar load, or a constant.
4956 /// The VBROADCAST node is returned when a pattern is found,
4957 /// or SDValue() otherwise.
4959 X86TargetLowering::LowerVectorBroadcast(SDValue &Op, SelectionDAG &DAG) const {
4960 if (!Subtarget->hasAVX())
4963 EVT VT = Op.getValueType();
4964 DebugLoc dl = Op.getDebugLoc();
4966 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4967 "Unsupported vector type for broadcast.");
4972 switch (Op.getOpcode()) {
4974 // Unknown pattern found.
4977 case ISD::BUILD_VECTOR: {
4978 // The BUILD_VECTOR node must be a splat.
4979 if (!isSplatVector(Op.getNode()))
4982 Ld = Op.getOperand(0);
4983 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
4984 Ld.getOpcode() == ISD::ConstantFP);
4986 // The suspected load node has several users. Make sure that all
4987 // of its users are from the BUILD_VECTOR node.
4988 // Constants may have multiple users.
4989 if (!ConstSplatVal && !Ld->hasNUsesOfValue(VT.getVectorNumElements(), 0))
4994 case ISD::VECTOR_SHUFFLE: {
4995 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
4997 // Shuffles must have a splat mask where the first element is
4999 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5002 SDValue Sc = Op.getOperand(0);
5003 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5004 Sc.getOpcode() != ISD::BUILD_VECTOR)
5007 Ld = Sc.getOperand(0);
5008 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5009 Ld.getOpcode() == ISD::ConstantFP);
5011 // The scalar_to_vector node and the suspected
5012 // load node must have exactly one user.
5013 // Constants may have multiple users.
5014 if (!ConstSplatVal && (!Sc.hasOneUse() || !Ld.hasOneUse()))
5020 bool Is256 = VT.getSizeInBits() == 256;
5022 // Handle the broadcasting a single constant scalar from the constant pool
5023 // into a vector. On Sandybridge it is still better to load a constant vector
5024 // from the constant pool and not to broadcast it from a scalar.
5025 if (ConstSplatVal && Subtarget->hasAVX2()) {
5026 EVT CVT = Ld.getValueType();
5027 assert(!CVT.isVector() && "Must not broadcast a vector type");
5028 unsigned ScalarSize = CVT.getSizeInBits();
5030 if (ScalarSize == 32 || (Is256 && ScalarSize == 64)) {
5031 const Constant *C = 0;
5032 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5033 C = CI->getConstantIntValue();
5034 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5035 C = CF->getConstantFPValue();
5037 assert(C && "Invalid constant type");
5039 SDValue CP = DAG.getConstantPool(C, getPointerTy());
5040 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5041 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
5042 MachinePointerInfo::getConstantPool(),
5043 false, false, false, Alignment);
5045 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5049 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5050 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5052 // Handle AVX2 in-register broadcasts.
5053 if (!IsLoad && Subtarget->hasAVX2() &&
5054 (ScalarSize == 32 || (Is256 && ScalarSize == 64)))
5055 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5057 // The scalar source must be a normal load.
5061 if (ScalarSize == 32 || (Is256 && ScalarSize == 64))
5062 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5064 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5065 // double since there is no vbroadcastsd xmm
5066 if (Subtarget->hasAVX2() && Ld.getValueType().isInteger()) {
5067 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5068 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5071 // Unsupported broadcast.
5076 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5077 DebugLoc dl = Op.getDebugLoc();
5079 EVT VT = Op.getValueType();
5080 EVT ExtVT = VT.getVectorElementType();
5081 unsigned NumElems = Op.getNumOperands();
5083 // Vectors containing all zeros can be matched by pxor and xorps later
5084 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5085 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
5086 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
5087 if (VT == MVT::v4i32 || VT == MVT::v8i32)
5090 return getZeroVector(VT, Subtarget, DAG, dl);
5093 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
5094 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
5095 // vpcmpeqd on 256-bit vectors.
5096 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5097 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasAVX2()))
5100 return getOnesVector(VT, Subtarget->hasAVX2(), DAG, dl);
5103 SDValue Broadcast = LowerVectorBroadcast(Op, DAG);
5104 if (Broadcast.getNode())
5107 unsigned EVTBits = ExtVT.getSizeInBits();
5109 unsigned NumZero = 0;
5110 unsigned NumNonZero = 0;
5111 unsigned NonZeros = 0;
5112 bool IsAllConstants = true;
5113 SmallSet<SDValue, 8> Values;
5114 for (unsigned i = 0; i < NumElems; ++i) {
5115 SDValue Elt = Op.getOperand(i);
5116 if (Elt.getOpcode() == ISD::UNDEF)
5119 if (Elt.getOpcode() != ISD::Constant &&
5120 Elt.getOpcode() != ISD::ConstantFP)
5121 IsAllConstants = false;
5122 if (X86::isZeroNode(Elt))
5125 NonZeros |= (1 << i);
5130 // All undef vector. Return an UNDEF. All zero vectors were handled above.
5131 if (NumNonZero == 0)
5132 return DAG.getUNDEF(VT);
5134 // Special case for single non-zero, non-undef, element.
5135 if (NumNonZero == 1) {
5136 unsigned Idx = CountTrailingZeros_32(NonZeros);
5137 SDValue Item = Op.getOperand(Idx);
5139 // If this is an insertion of an i64 value on x86-32, and if the top bits of
5140 // the value are obviously zero, truncate the value to i32 and do the
5141 // insertion that way. Only do this if the value is non-constant or if the
5142 // value is a constant being inserted into element 0. It is cheaper to do
5143 // a constant pool load than it is to do a movd + shuffle.
5144 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5145 (!IsAllConstants || Idx == 0)) {
5146 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
5148 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5149 EVT VecVT = MVT::v4i32;
5150 unsigned VecElts = 4;
5152 // Truncate the value (which may itself be a constant) to i32, and
5153 // convert it to a vector with movd (S2V+shuffle to zero extend).
5154 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5155 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5156 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5158 // Now we have our 32-bit value zero extended in the low element of
5159 // a vector. If Idx != 0, swizzle it into place.
5161 SmallVector<int, 4> Mask;
5162 Mask.push_back(Idx);
5163 for (unsigned i = 1; i != VecElts; ++i)
5165 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
5168 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5172 // If we have a constant or non-constant insertion into the low element of
5173 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5174 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5175 // depending on what the source datatype is.
5178 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5180 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5181 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5182 if (VT.getSizeInBits() == 256) {
5183 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
5184 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
5185 Item, DAG.getIntPtrConstant(0));
5187 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!");
5188 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5189 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
5190 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5193 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
5194 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5195 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5196 if (VT.getSizeInBits() == 256) {
5197 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
5198 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
5200 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!");
5201 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5203 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5207 // Is it a vector logical left shift?
5208 if (NumElems == 2 && Idx == 1 &&
5209 X86::isZeroNode(Op.getOperand(0)) &&
5210 !X86::isZeroNode(Op.getOperand(1))) {
5211 unsigned NumBits = VT.getSizeInBits();
5212 return getVShift(true, VT,
5213 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5214 VT, Op.getOperand(1)),
5215 NumBits/2, DAG, *this, dl);
5218 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
5221 // Otherwise, if this is a vector with i32 or f32 elements, and the element
5222 // is a non-constant being inserted into an element other than the low one,
5223 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
5224 // movd/movss) to move this into the low element, then shuffle it into
5226 if (EVTBits == 32) {
5227 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5229 // Turn it into a shuffle of zero and zero-extended scalar to vector.
5230 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
5231 SmallVector<int, 8> MaskVec;
5232 for (unsigned i = 0; i != NumElems; ++i)
5233 MaskVec.push_back(i == Idx ? 0 : 1);
5234 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
5238 // Splat is obviously ok. Let legalizer expand it to a shuffle.
5239 if (Values.size() == 1) {
5240 if (EVTBits == 32) {
5241 // Instead of a shuffle like this:
5242 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
5243 // Check if it's possible to issue this instead.
5244 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
5245 unsigned Idx = CountTrailingZeros_32(NonZeros);
5246 SDValue Item = Op.getOperand(Idx);
5247 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
5248 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
5253 // A vector full of immediates; various special cases are already
5254 // handled, so this is best done with a single constant-pool load.
5258 // For AVX-length vectors, build the individual 128-bit pieces and use
5259 // shuffles to put them in place.
5260 if (VT.getSizeInBits() == 256) {
5261 SmallVector<SDValue, 32> V;
5262 for (unsigned i = 0; i != NumElems; ++i)
5263 V.push_back(Op.getOperand(i));
5265 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
5267 // Build both the lower and upper subvector.
5268 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2);
5269 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2],
5272 // Recreate the wider vector with the lower and upper part.
5273 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
5276 // Let legalizer expand 2-wide build_vectors.
5277 if (EVTBits == 64) {
5278 if (NumNonZero == 1) {
5279 // One half is zero or undef.
5280 unsigned Idx = CountTrailingZeros_32(NonZeros);
5281 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
5282 Op.getOperand(Idx));
5283 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
5288 // If element VT is < 32 bits, convert it to inserts into a zero vector.
5289 if (EVTBits == 8 && NumElems == 16) {
5290 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
5292 if (V.getNode()) return V;
5295 if (EVTBits == 16 && NumElems == 8) {
5296 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
5298 if (V.getNode()) return V;
5301 // If element VT is == 32 bits, turn it into a number of shuffles.
5302 SmallVector<SDValue, 8> V(NumElems);
5303 if (NumElems == 4 && NumZero > 0) {
5304 for (unsigned i = 0; i < 4; ++i) {
5305 bool isZero = !(NonZeros & (1 << i));
5307 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
5309 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5312 for (unsigned i = 0; i < 2; ++i) {
5313 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
5316 V[i] = V[i*2]; // Must be a zero vector.
5319 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
5322 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
5325 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
5330 bool Reverse1 = (NonZeros & 0x3) == 2;
5331 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
5335 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
5336 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
5338 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
5341 if (Values.size() > 1 && VT.getSizeInBits() == 128) {
5342 // Check for a build vector of consecutive loads.
5343 for (unsigned i = 0; i < NumElems; ++i)
5344 V[i] = Op.getOperand(i);
5346 // Check for elements which are consecutive loads.
5347 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG);
5351 // For SSE 4.1, use insertps to put the high elements into the low element.
5352 if (getSubtarget()->hasSSE41()) {
5354 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
5355 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
5357 Result = DAG.getUNDEF(VT);
5359 for (unsigned i = 1; i < NumElems; ++i) {
5360 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
5361 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
5362 Op.getOperand(i), DAG.getIntPtrConstant(i));
5367 // Otherwise, expand into a number of unpckl*, start by extending each of
5368 // our (non-undef) elements to the full vector width with the element in the
5369 // bottom slot of the vector (which generates no code for SSE).
5370 for (unsigned i = 0; i < NumElems; ++i) {
5371 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
5372 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5374 V[i] = DAG.getUNDEF(VT);
5377 // Next, we iteratively mix elements, e.g. for v4f32:
5378 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
5379 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
5380 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
5381 unsigned EltStride = NumElems >> 1;
5382 while (EltStride != 0) {
5383 for (unsigned i = 0; i < EltStride; ++i) {
5384 // If V[i+EltStride] is undef and this is the first round of mixing,
5385 // then it is safe to just drop this shuffle: V[i] is already in the
5386 // right place, the one element (since it's the first round) being
5387 // inserted as undef can be dropped. This isn't safe for successive
5388 // rounds because they will permute elements within both vectors.
5389 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
5390 EltStride == NumElems/2)
5393 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
5402 // LowerMMXCONCAT_VECTORS - We support concatenate two MMX registers and place
5403 // them in a MMX register. This is better than doing a stack convert.
5404 static SDValue LowerMMXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5405 DebugLoc dl = Op.getDebugLoc();
5406 EVT ResVT = Op.getValueType();
5408 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 ||
5409 ResVT == MVT::v8i16 || ResVT == MVT::v16i8);
5411 SDValue InVec = DAG.getNode(ISD::BITCAST,dl, MVT::v1i64, Op.getOperand(0));
5412 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
5413 InVec = Op.getOperand(1);
5414 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
5415 unsigned NumElts = ResVT.getVectorNumElements();
5416 VecOp = DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
5417 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp,
5418 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1));
5420 InVec = DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, InVec);
5421 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
5422 Mask[0] = 0; Mask[1] = 2;
5423 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask);
5425 return DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
5428 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
5429 // to create 256-bit vectors from two other 128-bit ones.
5430 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5431 DebugLoc dl = Op.getDebugLoc();
5432 EVT ResVT = Op.getValueType();
5434 assert(ResVT.getSizeInBits() == 256 && "Value type must be 256-bit wide");
5436 SDValue V1 = Op.getOperand(0);
5437 SDValue V2 = Op.getOperand(1);
5438 unsigned NumElems = ResVT.getVectorNumElements();
5440 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
5444 X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
5445 EVT ResVT = Op.getValueType();
5447 assert(Op.getNumOperands() == 2);
5448 assert((ResVT.getSizeInBits() == 128 || ResVT.getSizeInBits() == 256) &&
5449 "Unsupported CONCAT_VECTORS for value type");
5451 // We support concatenate two MMX registers and place them in a MMX register.
5452 // This is better than doing a stack convert.
5453 if (ResVT.is128BitVector())
5454 return LowerMMXCONCAT_VECTORS(Op, DAG);
5456 // 256-bit AVX can use the vinsertf128 instruction to create 256-bit vectors
5457 // from two other 128-bit ones.
5458 return LowerAVXCONCAT_VECTORS(Op, DAG);
5461 // Try to lower a shuffle node into a simple blend instruction.
5462 static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
5463 const X86Subtarget *Subtarget,
5464 SelectionDAG &DAG) {
5465 SDValue V1 = SVOp->getOperand(0);
5466 SDValue V2 = SVOp->getOperand(1);
5467 DebugLoc dl = SVOp->getDebugLoc();
5468 MVT VT = SVOp->getValueType(0).getSimpleVT();
5469 unsigned NumElems = VT.getVectorNumElements();
5471 if (!Subtarget->hasSSE41())
5477 switch (VT.SimpleTy) {
5478 default: return SDValue();
5480 ISDNo = X86ISD::BLENDPW;
5485 ISDNo = X86ISD::BLENDPS;
5490 ISDNo = X86ISD::BLENDPD;
5495 if (!Subtarget->hasAVX())
5497 ISDNo = X86ISD::BLENDPS;
5502 if (!Subtarget->hasAVX())
5504 ISDNo = X86ISD::BLENDPD;
5508 assert(ISDNo && "Invalid Op Number");
5510 unsigned MaskVals = 0;
5512 for (unsigned i = 0; i != NumElems; ++i) {
5513 int EltIdx = SVOp->getMaskElt(i);
5514 if (EltIdx == (int)i || EltIdx < 0)
5516 else if (EltIdx == (int)(i + NumElems))
5517 continue; // Bit is set to zero;
5522 V1 = DAG.getNode(ISD::BITCAST, dl, OpTy, V1);
5523 V2 = DAG.getNode(ISD::BITCAST, dl, OpTy, V2);
5524 SDValue Ret = DAG.getNode(ISDNo, dl, OpTy, V1, V2,
5525 DAG.getConstant(MaskVals, MVT::i32));
5526 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
5529 // v8i16 shuffles - Prefer shuffles in the following order:
5530 // 1. [all] pshuflw, pshufhw, optional move
5531 // 2. [ssse3] 1 x pshufb
5532 // 3. [ssse3] 2 x pshufb + 1 x por
5533 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
5535 X86TargetLowering::LowerVECTOR_SHUFFLEv8i16(SDValue Op,
5536 SelectionDAG &DAG) const {
5537 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5538 SDValue V1 = SVOp->getOperand(0);
5539 SDValue V2 = SVOp->getOperand(1);
5540 DebugLoc dl = SVOp->getDebugLoc();
5541 SmallVector<int, 8> MaskVals;
5543 // Determine if more than 1 of the words in each of the low and high quadwords
5544 // of the result come from the same quadword of one of the two inputs. Undef
5545 // mask values count as coming from any quadword, for better codegen.
5546 unsigned LoQuad[] = { 0, 0, 0, 0 };
5547 unsigned HiQuad[] = { 0, 0, 0, 0 };
5548 std::bitset<4> InputQuads;
5549 for (unsigned i = 0; i < 8; ++i) {
5550 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
5551 int EltIdx = SVOp->getMaskElt(i);
5552 MaskVals.push_back(EltIdx);
5561 InputQuads.set(EltIdx / 4);
5564 int BestLoQuad = -1;
5565 unsigned MaxQuad = 1;
5566 for (unsigned i = 0; i < 4; ++i) {
5567 if (LoQuad[i] > MaxQuad) {
5569 MaxQuad = LoQuad[i];
5573 int BestHiQuad = -1;
5575 for (unsigned i = 0; i < 4; ++i) {
5576 if (HiQuad[i] > MaxQuad) {
5578 MaxQuad = HiQuad[i];
5582 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
5583 // of the two input vectors, shuffle them into one input vector so only a
5584 // single pshufb instruction is necessary. If There are more than 2 input
5585 // quads, disable the next transformation since it does not help SSSE3.
5586 bool V1Used = InputQuads[0] || InputQuads[1];
5587 bool V2Used = InputQuads[2] || InputQuads[3];
5588 if (Subtarget->hasSSSE3()) {
5589 if (InputQuads.count() == 2 && V1Used && V2Used) {
5590 BestLoQuad = InputQuads[0] ? 0 : 1;
5591 BestHiQuad = InputQuads[2] ? 2 : 3;
5593 if (InputQuads.count() > 2) {
5599 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
5600 // the shuffle mask. If a quad is scored as -1, that means that it contains
5601 // words from all 4 input quadwords.
5603 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
5605 BestLoQuad < 0 ? 0 : BestLoQuad,
5606 BestHiQuad < 0 ? 1 : BestHiQuad
5608 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
5609 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
5610 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
5611 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
5613 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
5614 // source words for the shuffle, to aid later transformations.
5615 bool AllWordsInNewV = true;
5616 bool InOrder[2] = { true, true };
5617 for (unsigned i = 0; i != 8; ++i) {
5618 int idx = MaskVals[i];
5620 InOrder[i/4] = false;
5621 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
5623 AllWordsInNewV = false;
5627 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
5628 if (AllWordsInNewV) {
5629 for (int i = 0; i != 8; ++i) {
5630 int idx = MaskVals[i];
5633 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
5634 if ((idx != i) && idx < 4)
5636 if ((idx != i) && idx > 3)
5645 // If we've eliminated the use of V2, and the new mask is a pshuflw or
5646 // pshufhw, that's as cheap as it gets. Return the new shuffle.
5647 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
5648 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
5649 unsigned TargetMask = 0;
5650 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
5651 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
5652 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
5653 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
5654 getShufflePSHUFLWImmediate(SVOp);
5655 V1 = NewV.getOperand(0);
5656 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
5660 // If we have SSSE3, and all words of the result are from 1 input vector,
5661 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
5662 // is present, fall back to case 4.
5663 if (Subtarget->hasSSSE3()) {
5664 SmallVector<SDValue,16> pshufbMask;
5666 // If we have elements from both input vectors, set the high bit of the
5667 // shuffle mask element to zero out elements that come from V2 in the V1
5668 // mask, and elements that come from V1 in the V2 mask, so that the two
5669 // results can be OR'd together.
5670 bool TwoInputs = V1Used && V2Used;
5671 for (unsigned i = 0; i != 8; ++i) {
5672 int EltIdx = MaskVals[i] * 2;
5673 int Idx0 = (TwoInputs && (EltIdx >= 16)) ? 0x80 : EltIdx;
5674 int Idx1 = (TwoInputs && (EltIdx >= 16)) ? 0x80 : EltIdx+1;
5675 pshufbMask.push_back(DAG.getConstant(Idx0, MVT::i8));
5676 pshufbMask.push_back(DAG.getConstant(Idx1, MVT::i8));
5678 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1);
5679 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5680 DAG.getNode(ISD::BUILD_VECTOR, dl,
5681 MVT::v16i8, &pshufbMask[0], 16));
5683 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5685 // Calculate the shuffle mask for the second input, shuffle it, and
5686 // OR it with the first shuffled input.
5688 for (unsigned i = 0; i != 8; ++i) {
5689 int EltIdx = MaskVals[i] * 2;
5690 int Idx0 = (EltIdx < 16) ? 0x80 : EltIdx - 16;
5691 int Idx1 = (EltIdx < 16) ? 0x80 : EltIdx - 15;
5692 pshufbMask.push_back(DAG.getConstant(Idx0, MVT::i8));
5693 pshufbMask.push_back(DAG.getConstant(Idx1, MVT::i8));
5695 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2);
5696 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5697 DAG.getNode(ISD::BUILD_VECTOR, dl,
5698 MVT::v16i8, &pshufbMask[0], 16));
5699 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5700 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5703 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
5704 // and update MaskVals with new element order.
5705 std::bitset<8> InOrder;
5706 if (BestLoQuad >= 0) {
5707 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
5708 for (int i = 0; i != 4; ++i) {
5709 int idx = MaskVals[i];
5712 } else if ((idx / 4) == BestLoQuad) {
5717 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5720 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
5721 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
5722 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
5724 getShufflePSHUFLWImmediate(SVOp), DAG);
5728 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
5729 // and update MaskVals with the new element order.
5730 if (BestHiQuad >= 0) {
5731 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
5732 for (unsigned i = 4; i != 8; ++i) {
5733 int idx = MaskVals[i];
5736 } else if ((idx / 4) == BestHiQuad) {
5737 MaskV[i] = (idx & 3) + 4;
5741 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5744 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
5745 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
5746 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
5748 getShufflePSHUFHWImmediate(SVOp), DAG);
5752 // In case BestHi & BestLo were both -1, which means each quadword has a word
5753 // from each of the four input quadwords, calculate the InOrder bitvector now
5754 // before falling through to the insert/extract cleanup.
5755 if (BestLoQuad == -1 && BestHiQuad == -1) {
5757 for (int i = 0; i != 8; ++i)
5758 if (MaskVals[i] < 0 || MaskVals[i] == i)
5762 // The other elements are put in the right place using pextrw and pinsrw.
5763 for (unsigned i = 0; i != 8; ++i) {
5766 int EltIdx = MaskVals[i];
5769 SDValue ExtOp = (EltIdx < 8) ?
5770 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
5771 DAG.getIntPtrConstant(EltIdx)) :
5772 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
5773 DAG.getIntPtrConstant(EltIdx - 8));
5774 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
5775 DAG.getIntPtrConstant(i));
5780 // v16i8 shuffles - Prefer shuffles in the following order:
5781 // 1. [ssse3] 1 x pshufb
5782 // 2. [ssse3] 2 x pshufb + 1 x por
5783 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
5785 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
5787 const X86TargetLowering &TLI) {
5788 SDValue V1 = SVOp->getOperand(0);
5789 SDValue V2 = SVOp->getOperand(1);
5790 DebugLoc dl = SVOp->getDebugLoc();
5791 ArrayRef<int> MaskVals = SVOp->getMask();
5793 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
5795 // If we have SSSE3, case 1 is generated when all result bytes come from
5796 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
5797 // present, fall back to case 3.
5799 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
5800 if (TLI.getSubtarget()->hasSSSE3()) {
5801 SmallVector<SDValue,16> pshufbMask;
5803 // If all result elements are from one input vector, then only translate
5804 // undef mask values to 0x80 (zero out result) in the pshufb mask.
5806 // Otherwise, we have elements from both input vectors, and must zero out
5807 // elements that come from V2 in the first mask, and V1 in the second mask
5808 // so that we can OR them together.
5809 for (unsigned i = 0; i != 16; ++i) {
5810 int EltIdx = MaskVals[i];
5811 if (EltIdx < 0 || EltIdx >= 16)
5813 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5815 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5816 DAG.getNode(ISD::BUILD_VECTOR, dl,
5817 MVT::v16i8, &pshufbMask[0], 16));
5821 // Calculate the shuffle mask for the second input, shuffle it, and
5822 // OR it with the first shuffled input.
5824 for (unsigned i = 0; i != 16; ++i) {
5825 int EltIdx = MaskVals[i];
5826 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
5827 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5829 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5830 DAG.getNode(ISD::BUILD_VECTOR, dl,
5831 MVT::v16i8, &pshufbMask[0], 16));
5832 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5835 // No SSSE3 - Calculate in place words and then fix all out of place words
5836 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
5837 // the 16 different words that comprise the two doublequadword input vectors.
5838 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5839 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
5841 for (int i = 0; i != 8; ++i) {
5842 int Elt0 = MaskVals[i*2];
5843 int Elt1 = MaskVals[i*2+1];
5845 // This word of the result is all undef, skip it.
5846 if (Elt0 < 0 && Elt1 < 0)
5849 // This word of the result is already in the correct place, skip it.
5850 if ((Elt0 == i*2) && (Elt1 == i*2+1))
5853 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
5854 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
5857 // If Elt0 and Elt1 are defined, are consecutive, and can be load
5858 // using a single extract together, load it and store it.
5859 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
5860 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5861 DAG.getIntPtrConstant(Elt1 / 2));
5862 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5863 DAG.getIntPtrConstant(i));
5867 // If Elt1 is defined, extract it from the appropriate source. If the
5868 // source byte is not also odd, shift the extracted word left 8 bits
5869 // otherwise clear the bottom 8 bits if we need to do an or.
5871 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5872 DAG.getIntPtrConstant(Elt1 / 2));
5873 if ((Elt1 & 1) == 0)
5874 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
5876 TLI.getShiftAmountTy(InsElt.getValueType())));
5878 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
5879 DAG.getConstant(0xFF00, MVT::i16));
5881 // If Elt0 is defined, extract it from the appropriate source. If the
5882 // source byte is not also even, shift the extracted word right 8 bits. If
5883 // Elt1 was also defined, OR the extracted values together before
5884 // inserting them in the result.
5886 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
5887 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
5888 if ((Elt0 & 1) != 0)
5889 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
5891 TLI.getShiftAmountTy(InsElt0.getValueType())));
5893 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
5894 DAG.getConstant(0x00FF, MVT::i16));
5895 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
5898 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5899 DAG.getIntPtrConstant(i));
5901 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
5904 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
5905 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
5906 /// done when every pair / quad of shuffle mask elements point to elements in
5907 /// the right sequence. e.g.
5908 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
5910 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
5911 SelectionDAG &DAG, DebugLoc dl) {
5912 MVT VT = SVOp->getValueType(0).getSimpleVT();
5913 unsigned NumElems = VT.getVectorNumElements();
5916 switch (VT.SimpleTy) {
5917 default: llvm_unreachable("Unexpected!");
5918 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
5919 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
5920 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
5921 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
5922 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
5923 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
5926 SmallVector<int, 8> MaskVec;
5927 for (unsigned i = 0; i != NumElems; i += Scale) {
5929 for (unsigned j = 0; j != Scale; ++j) {
5930 int EltIdx = SVOp->getMaskElt(i+j);
5934 StartIdx = (EltIdx / Scale);
5935 if (EltIdx != (int)(StartIdx*Scale + j))
5938 MaskVec.push_back(StartIdx);
5941 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
5942 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
5943 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
5946 /// getVZextMovL - Return a zero-extending vector move low node.
5948 static SDValue getVZextMovL(EVT VT, EVT OpVT,
5949 SDValue SrcOp, SelectionDAG &DAG,
5950 const X86Subtarget *Subtarget, DebugLoc dl) {
5951 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
5952 LoadSDNode *LD = NULL;
5953 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
5954 LD = dyn_cast<LoadSDNode>(SrcOp);
5956 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
5958 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
5959 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
5960 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
5961 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
5962 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
5964 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
5965 return DAG.getNode(ISD::BITCAST, dl, VT,
5966 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
5967 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5975 return DAG.getNode(ISD::BITCAST, dl, VT,
5976 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
5977 DAG.getNode(ISD::BITCAST, dl,
5981 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
5982 /// which could not be matched by any known target speficic shuffle
5984 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
5985 EVT VT = SVOp->getValueType(0);
5987 unsigned NumElems = VT.getVectorNumElements();
5988 unsigned NumLaneElems = NumElems / 2;
5990 DebugLoc dl = SVOp->getDebugLoc();
5991 MVT EltVT = VT.getVectorElementType().getSimpleVT();
5992 EVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
5995 SmallVector<int, 16> Mask;
5996 for (unsigned l = 0; l < 2; ++l) {
5997 // Build a shuffle mask for the output, discovering on the fly which
5998 // input vectors to use as shuffle operands (recorded in InputUsed).
5999 // If building a suitable shuffle vector proves too hard, then bail
6000 // out with UseBuildVector set.
6001 bool UseBuildVector = false;
6002 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
6003 unsigned LaneStart = l * NumLaneElems;
6004 for (unsigned i = 0; i != NumLaneElems; ++i) {
6005 // The mask element. This indexes into the input.
6006 int Idx = SVOp->getMaskElt(i+LaneStart);
6008 // the mask element does not index into any input vector.
6013 // The input vector this mask element indexes into.
6014 int Input = Idx / NumLaneElems;
6016 // Turn the index into an offset from the start of the input vector.
6017 Idx -= Input * NumLaneElems;
6019 // Find or create a shuffle vector operand to hold this input.
6021 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
6022 if (InputUsed[OpNo] == Input)
6023 // This input vector is already an operand.
6025 if (InputUsed[OpNo] < 0) {
6026 // Create a new operand for this input vector.
6027 InputUsed[OpNo] = Input;
6032 if (OpNo >= array_lengthof(InputUsed)) {
6033 // More than two input vectors used! Give up on trying to create a
6034 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
6035 UseBuildVector = true;
6039 // Add the mask index for the new shuffle vector.
6040 Mask.push_back(Idx + OpNo * NumLaneElems);
6043 if (UseBuildVector) {
6044 SmallVector<SDValue, 16> SVOps;
6045 for (unsigned i = 0; i != NumLaneElems; ++i) {
6046 // The mask element. This indexes into the input.
6047 int Idx = SVOp->getMaskElt(i+LaneStart);
6049 SVOps.push_back(DAG.getUNDEF(EltVT));
6053 // The input vector this mask element indexes into.
6054 int Input = Idx / NumElems;
6056 // Turn the index into an offset from the start of the input vector.
6057 Idx -= Input * NumElems;
6059 // Extract the vector element by hand.
6060 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
6061 SVOp->getOperand(Input),
6062 DAG.getIntPtrConstant(Idx)));
6065 // Construct the output using a BUILD_VECTOR.
6066 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, &SVOps[0],
6068 } else if (InputUsed[0] < 0) {
6069 // No input vectors were used! The result is undefined.
6070 Output[l] = DAG.getUNDEF(NVT);
6072 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
6073 (InputUsed[0] % 2) * NumLaneElems,
6075 // If only one input was used, use an undefined vector for the other.
6076 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
6077 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
6078 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
6079 // At least one input vector was used. Create a new shuffle vector.
6080 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
6086 // Concatenate the result back
6087 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
6090 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
6091 /// 4 elements, and match them with several different shuffle types.
6093 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6094 SDValue V1 = SVOp->getOperand(0);
6095 SDValue V2 = SVOp->getOperand(1);
6096 DebugLoc dl = SVOp->getDebugLoc();
6097 EVT VT = SVOp->getValueType(0);
6099 assert(VT.getSizeInBits() == 128 && "Unsupported vector size");
6101 std::pair<int, int> Locs[4];
6102 int Mask1[] = { -1, -1, -1, -1 };
6103 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
6107 for (unsigned i = 0; i != 4; ++i) {
6108 int Idx = PermMask[i];
6110 Locs[i] = std::make_pair(-1, -1);
6112 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
6114 Locs[i] = std::make_pair(0, NumLo);
6118 Locs[i] = std::make_pair(1, NumHi);
6120 Mask1[2+NumHi] = Idx;
6126 if (NumLo <= 2 && NumHi <= 2) {
6127 // If no more than two elements come from either vector. This can be
6128 // implemented with two shuffles. First shuffle gather the elements.
6129 // The second shuffle, which takes the first shuffle as both of its
6130 // vector operands, put the elements into the right order.
6131 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6133 int Mask2[] = { -1, -1, -1, -1 };
6135 for (unsigned i = 0; i != 4; ++i)
6136 if (Locs[i].first != -1) {
6137 unsigned Idx = (i < 2) ? 0 : 4;
6138 Idx += Locs[i].first * 2 + Locs[i].second;
6142 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
6145 if (NumLo == 3 || NumHi == 3) {
6146 // Otherwise, we must have three elements from one vector, call it X, and
6147 // one element from the other, call it Y. First, use a shufps to build an
6148 // intermediate vector with the one element from Y and the element from X
6149 // that will be in the same half in the final destination (the indexes don't
6150 // matter). Then, use a shufps to build the final vector, taking the half
6151 // containing the element from Y from the intermediate, and the other half
6154 // Normalize it so the 3 elements come from V1.
6155 CommuteVectorShuffleMask(PermMask, 4);
6159 // Find the element from V2.
6161 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
6162 int Val = PermMask[HiIndex];
6169 Mask1[0] = PermMask[HiIndex];
6171 Mask1[2] = PermMask[HiIndex^1];
6173 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6176 Mask1[0] = PermMask[0];
6177 Mask1[1] = PermMask[1];
6178 Mask1[2] = HiIndex & 1 ? 6 : 4;
6179 Mask1[3] = HiIndex & 1 ? 4 : 6;
6180 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6183 Mask1[0] = HiIndex & 1 ? 2 : 0;
6184 Mask1[1] = HiIndex & 1 ? 0 : 2;
6185 Mask1[2] = PermMask[2];
6186 Mask1[3] = PermMask[3];
6191 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
6194 // Break it into (shuffle shuffle_hi, shuffle_lo).
6195 int LoMask[] = { -1, -1, -1, -1 };
6196 int HiMask[] = { -1, -1, -1, -1 };
6198 int *MaskPtr = LoMask;
6199 unsigned MaskIdx = 0;
6202 for (unsigned i = 0; i != 4; ++i) {
6209 int Idx = PermMask[i];
6211 Locs[i] = std::make_pair(-1, -1);
6212 } else if (Idx < 4) {
6213 Locs[i] = std::make_pair(MaskIdx, LoIdx);
6214 MaskPtr[LoIdx] = Idx;
6217 Locs[i] = std::make_pair(MaskIdx, HiIdx);
6218 MaskPtr[HiIdx] = Idx;
6223 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
6224 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
6225 int MaskOps[] = { -1, -1, -1, -1 };
6226 for (unsigned i = 0; i != 4; ++i)
6227 if (Locs[i].first != -1)
6228 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
6229 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
6232 static bool MayFoldVectorLoad(SDValue V) {
6233 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6234 V = V.getOperand(0);
6235 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6236 V = V.getOperand(0);
6237 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
6238 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
6239 // BUILD_VECTOR (load), undef
6240 V = V.getOperand(0);
6246 // FIXME: the version above should always be used. Since there's
6247 // a bug where several vector shuffles can't be folded because the
6248 // DAG is not updated during lowering and a node claims to have two
6249 // uses while it only has one, use this version, and let isel match
6250 // another instruction if the load really happens to have more than
6251 // one use. Remove this version after this bug get fixed.
6252 // rdar://8434668, PR8156
6253 static bool RelaxedMayFoldVectorLoad(SDValue V) {
6254 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6255 V = V.getOperand(0);
6256 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6257 V = V.getOperand(0);
6258 if (ISD::isNormalLoad(V.getNode()))
6264 SDValue getMOVDDup(SDValue &Op, DebugLoc &dl, SDValue V1, SelectionDAG &DAG) {
6265 EVT VT = Op.getValueType();
6267 // Canonizalize to v2f64.
6268 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
6269 return DAG.getNode(ISD::BITCAST, dl, VT,
6270 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
6275 SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG,
6277 SDValue V1 = Op.getOperand(0);
6278 SDValue V2 = Op.getOperand(1);
6279 EVT VT = Op.getValueType();
6281 assert(VT != MVT::v2i64 && "unsupported shuffle type");
6283 if (HasSSE2 && VT == MVT::v2f64)
6284 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
6286 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
6287 return DAG.getNode(ISD::BITCAST, dl, VT,
6288 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
6289 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
6290 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
6294 SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) {
6295 SDValue V1 = Op.getOperand(0);
6296 SDValue V2 = Op.getOperand(1);
6297 EVT VT = Op.getValueType();
6299 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
6300 "unsupported shuffle type");
6302 if (V2.getOpcode() == ISD::UNDEF)
6306 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
6310 SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
6311 SDValue V1 = Op.getOperand(0);
6312 SDValue V2 = Op.getOperand(1);
6313 EVT VT = Op.getValueType();
6314 unsigned NumElems = VT.getVectorNumElements();
6316 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
6317 // operand of these instructions is only memory, so check if there's a
6318 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
6320 bool CanFoldLoad = false;
6322 // Trivial case, when V2 comes from a load.
6323 if (MayFoldVectorLoad(V2))
6326 // When V1 is a load, it can be folded later into a store in isel, example:
6327 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
6329 // (MOVLPSmr addr:$src1, VR128:$src2)
6330 // So, recognize this potential and also use MOVLPS or MOVLPD
6331 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
6334 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6336 if (HasSSE2 && NumElems == 2)
6337 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
6340 // If we don't care about the second element, proceed to use movss.
6341 if (SVOp->getMaskElt(1) != -1)
6342 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
6345 // movl and movlp will both match v2i64, but v2i64 is never matched by
6346 // movl earlier because we make it strict to avoid messing with the movlp load
6347 // folding logic (see the code above getMOVLP call). Match it here then,
6348 // this is horrible, but will stay like this until we move all shuffle
6349 // matching to x86 specific nodes. Note that for the 1st condition all
6350 // types are matched with movsd.
6352 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
6353 // as to remove this logic from here, as much as possible
6354 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
6355 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6356 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6359 assert(VT != MVT::v4i32 && "unsupported shuffle type");
6361 // Invert the operand order and use SHUFPS to match it.
6362 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
6363 getShuffleSHUFImmediate(SVOp), DAG);
6367 X86TargetLowering::NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG) const {
6368 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6369 EVT VT = Op.getValueType();
6370 DebugLoc dl = Op.getDebugLoc();
6371 SDValue V1 = Op.getOperand(0);
6372 SDValue V2 = Op.getOperand(1);
6374 if (isZeroShuffle(SVOp))
6375 return getZeroVector(VT, Subtarget, DAG, dl);
6377 // Handle splat operations
6378 if (SVOp->isSplat()) {
6379 unsigned NumElem = VT.getVectorNumElements();
6380 int Size = VT.getSizeInBits();
6382 // Use vbroadcast whenever the splat comes from a foldable load
6383 SDValue Broadcast = LowerVectorBroadcast(Op, DAG);
6384 if (Broadcast.getNode())
6387 // Handle splats by matching through known shuffle masks
6388 if ((Size == 128 && NumElem <= 4) ||
6389 (Size == 256 && NumElem < 8))
6392 // All remaning splats are promoted to target supported vector shuffles.
6393 return PromoteSplat(SVOp, DAG);
6396 // If the shuffle can be profitably rewritten as a narrower shuffle, then
6398 if (VT == MVT::v8i16 || VT == MVT::v16i8 ||
6399 VT == MVT::v16i16 || VT == MVT::v32i8) {
6400 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6401 if (NewOp.getNode())
6402 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
6403 } else if ((VT == MVT::v4i32 ||
6404 (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
6405 // FIXME: Figure out a cleaner way to do this.
6406 // Try to make use of movq to zero out the top part.
6407 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
6408 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6409 if (NewOp.getNode()) {
6410 EVT NewVT = NewOp.getValueType();
6411 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
6412 NewVT, true, false))
6413 return getVZextMovL(VT, NewVT, NewOp.getOperand(0),
6414 DAG, Subtarget, dl);
6416 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
6417 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6418 if (NewOp.getNode()) {
6419 EVT NewVT = NewOp.getValueType();
6420 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
6421 return getVZextMovL(VT, NewVT, NewOp.getOperand(1),
6422 DAG, Subtarget, dl);
6430 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
6431 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6432 SDValue V1 = Op.getOperand(0);
6433 SDValue V2 = Op.getOperand(1);
6434 EVT VT = Op.getValueType();
6435 DebugLoc dl = Op.getDebugLoc();
6436 unsigned NumElems = VT.getVectorNumElements();
6437 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
6438 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
6439 bool V1IsSplat = false;
6440 bool V2IsSplat = false;
6441 bool HasSSE2 = Subtarget->hasSSE2();
6442 bool HasAVX = Subtarget->hasAVX();
6443 bool HasAVX2 = Subtarget->hasAVX2();
6444 MachineFunction &MF = DAG.getMachineFunction();
6445 bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize);
6447 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
6449 if (V1IsUndef && V2IsUndef)
6450 return DAG.getUNDEF(VT);
6452 assert(!V1IsUndef && "Op 1 of shuffle should not be undef");
6454 // Vector shuffle lowering takes 3 steps:
6456 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
6457 // narrowing and commutation of operands should be handled.
6458 // 2) Matching of shuffles with known shuffle masks to x86 target specific
6460 // 3) Rewriting of unmatched masks into new generic shuffle operations,
6461 // so the shuffle can be broken into other shuffles and the legalizer can
6462 // try the lowering again.
6464 // The general idea is that no vector_shuffle operation should be left to
6465 // be matched during isel, all of them must be converted to a target specific
6468 // Normalize the input vectors. Here splats, zeroed vectors, profitable
6469 // narrowing and commutation of operands should be handled. The actual code
6470 // doesn't include all of those, work in progress...
6471 SDValue NewOp = NormalizeVectorShuffle(Op, DAG);
6472 if (NewOp.getNode())
6475 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
6477 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
6478 // unpckh_undef). Only use pshufd if speed is more important than size.
6479 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasAVX2))
6480 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6481 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasAVX2))
6482 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6484 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
6485 V2IsUndef && RelaxedMayFoldVectorLoad(V1))
6486 return getMOVDDup(Op, dl, V1, DAG);
6488 if (isMOVHLPS_v_undef_Mask(M, VT))
6489 return getMOVHighToLow(Op, dl, DAG);
6491 // Use to match splats
6492 if (HasSSE2 && isUNPCKHMask(M, VT, HasAVX2) && V2IsUndef &&
6493 (VT == MVT::v2f64 || VT == MVT::v2i64))
6494 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6496 if (isPSHUFDMask(M, VT)) {
6497 // The actual implementation will match the mask in the if above and then
6498 // during isel it can match several different instructions, not only pshufd
6499 // as its name says, sad but true, emulate the behavior for now...
6500 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
6501 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
6503 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
6505 if (HasAVX && (VT == MVT::v4f32 || VT == MVT::v2f64))
6506 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, TargetMask, DAG);
6508 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
6509 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
6511 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
6515 // Check if this can be converted into a logical shift.
6516 bool isLeft = false;
6519 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
6520 if (isShift && ShVal.hasOneUse()) {
6521 // If the shifted value has multiple uses, it may be cheaper to use
6522 // v_set0 + movlhps or movhlps, etc.
6523 EVT EltVT = VT.getVectorElementType();
6524 ShAmt *= EltVT.getSizeInBits();
6525 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6528 if (isMOVLMask(M, VT)) {
6529 if (ISD::isBuildVectorAllZeros(V1.getNode()))
6530 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
6531 if (!isMOVLPMask(M, VT)) {
6532 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
6533 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6535 if (VT == MVT::v4i32 || VT == MVT::v4f32)
6536 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6540 // FIXME: fold these into legal mask.
6541 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasAVX2))
6542 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
6544 if (isMOVHLPSMask(M, VT))
6545 return getMOVHighToLow(Op, dl, DAG);
6547 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
6548 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
6550 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
6551 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
6553 if (isMOVLPMask(M, VT))
6554 return getMOVLP(Op, dl, DAG, HasSSE2);
6556 if (ShouldXformToMOVHLPS(M, VT) ||
6557 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
6558 return CommuteVectorShuffle(SVOp, DAG);
6561 // No better options. Use a vshldq / vsrldq.
6562 EVT EltVT = VT.getVectorElementType();
6563 ShAmt *= EltVT.getSizeInBits();
6564 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6567 bool Commuted = false;
6568 // FIXME: This should also accept a bitcast of a splat? Be careful, not
6569 // 1,1,1,1 -> v8i16 though.
6570 V1IsSplat = isSplatVector(V1.getNode());
6571 V2IsSplat = isSplatVector(V2.getNode());
6573 // Canonicalize the splat or undef, if present, to be on the RHS.
6574 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
6575 CommuteVectorShuffleMask(M, NumElems);
6577 std::swap(V1IsSplat, V2IsSplat);
6581 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
6582 // Shuffling low element of v1 into undef, just return v1.
6585 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
6586 // the instruction selector will not match, so get a canonical MOVL with
6587 // swapped operands to undo the commute.
6588 return getMOVL(DAG, dl, VT, V2, V1);
6591 if (isUNPCKLMask(M, VT, HasAVX2))
6592 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6594 if (isUNPCKHMask(M, VT, HasAVX2))
6595 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6598 // Normalize mask so all entries that point to V2 points to its first
6599 // element then try to match unpck{h|l} again. If match, return a
6600 // new vector_shuffle with the corrected mask.p
6601 SmallVector<int, 8> NewMask(M.begin(), M.end());
6602 NormalizeMask(NewMask, NumElems);
6603 if (isUNPCKLMask(NewMask, VT, HasAVX2, true))
6604 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6605 if (isUNPCKHMask(NewMask, VT, HasAVX2, true))
6606 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6610 // Commute is back and try unpck* again.
6611 // FIXME: this seems wrong.
6612 CommuteVectorShuffleMask(M, NumElems);
6614 std::swap(V1IsSplat, V2IsSplat);
6617 if (isUNPCKLMask(M, VT, HasAVX2))
6618 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6620 if (isUNPCKHMask(M, VT, HasAVX2))
6621 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6624 // Normalize the node to match x86 shuffle ops if needed
6625 if (!V2IsUndef && (isSHUFPMask(M, VT, HasAVX, /* Commuted */ true)))
6626 return CommuteVectorShuffle(SVOp, DAG);
6628 // The checks below are all present in isShuffleMaskLegal, but they are
6629 // inlined here right now to enable us to directly emit target specific
6630 // nodes, and remove one by one until they don't return Op anymore.
6632 if (isPALIGNRMask(M, VT, Subtarget))
6633 return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2,
6634 getShufflePALIGNRImmediate(SVOp),
6637 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
6638 SVOp->getSplatIndex() == 0 && V2IsUndef) {
6639 if (VT == MVT::v2f64 || VT == MVT::v2i64)
6640 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6643 if (isPSHUFHWMask(M, VT, HasAVX2))
6644 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
6645 getShufflePSHUFHWImmediate(SVOp),
6648 if (isPSHUFLWMask(M, VT, HasAVX2))
6649 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
6650 getShufflePSHUFLWImmediate(SVOp),
6653 if (isSHUFPMask(M, VT, HasAVX))
6654 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
6655 getShuffleSHUFImmediate(SVOp), DAG);
6657 if (isUNPCKL_v_undef_Mask(M, VT, HasAVX2))
6658 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6659 if (isUNPCKH_v_undef_Mask(M, VT, HasAVX2))
6660 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6662 //===--------------------------------------------------------------------===//
6663 // Generate target specific nodes for 128 or 256-bit shuffles only
6664 // supported in the AVX instruction set.
6667 // Handle VMOVDDUPY permutations
6668 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasAVX))
6669 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
6671 // Handle VPERMILPS/D* permutations
6672 if (isVPERMILPMask(M, VT, HasAVX)) {
6673 if (HasAVX2 && VT == MVT::v8i32)
6674 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
6675 getShuffleSHUFImmediate(SVOp), DAG);
6676 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1,
6677 getShuffleSHUFImmediate(SVOp), DAG);
6680 // Handle VPERM2F128/VPERM2I128 permutations
6681 if (isVPERM2X128Mask(M, VT, HasAVX))
6682 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
6683 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
6685 SDValue BlendOp = LowerVECTOR_SHUFFLEtoBlend(SVOp, Subtarget, DAG);
6686 if (BlendOp.getNode())
6689 if (V2IsUndef && HasAVX2 && (VT == MVT::v8i32 || VT == MVT::v8f32)) {
6690 SmallVector<SDValue, 8> permclMask;
6691 for (unsigned i = 0; i != 8; ++i) {
6692 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MVT::i32));
6694 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32,
6696 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
6697 return DAG.getNode(X86ISD::VPERMV, dl, VT,
6698 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
6701 if (V2IsUndef && HasAVX2 && (VT == MVT::v4i64 || VT == MVT::v4f64))
6702 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1,
6703 getShuffleCLImmediate(SVOp), DAG);
6706 //===--------------------------------------------------------------------===//
6707 // Since no target specific shuffle was selected for this generic one,
6708 // lower it into other known shuffles. FIXME: this isn't true yet, but
6709 // this is the plan.
6712 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
6713 if (VT == MVT::v8i16) {
6714 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, DAG);
6715 if (NewOp.getNode())
6719 if (VT == MVT::v16i8) {
6720 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
6721 if (NewOp.getNode())
6725 // Handle all 128-bit wide vectors with 4 elements, and match them with
6726 // several different shuffle types.
6727 if (NumElems == 4 && VT.getSizeInBits() == 128)
6728 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
6730 // Handle general 256-bit shuffles
6731 if (VT.is256BitVector())
6732 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
6738 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
6739 SelectionDAG &DAG) const {
6740 EVT VT = Op.getValueType();
6741 DebugLoc dl = Op.getDebugLoc();
6743 if (Op.getOperand(0).getValueType().getSizeInBits() != 128)
6746 if (VT.getSizeInBits() == 8) {
6747 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
6748 Op.getOperand(0), Op.getOperand(1));
6749 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6750 DAG.getValueType(VT));
6751 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6754 if (VT.getSizeInBits() == 16) {
6755 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6756 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
6758 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6759 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6760 DAG.getNode(ISD::BITCAST, dl,
6764 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
6765 Op.getOperand(0), Op.getOperand(1));
6766 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6767 DAG.getValueType(VT));
6768 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6771 if (VT == MVT::f32) {
6772 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
6773 // the result back to FR32 register. It's only worth matching if the
6774 // result has a single use which is a store or a bitcast to i32. And in
6775 // the case of a store, it's not worth it if the index is a constant 0,
6776 // because a MOVSSmr can be used instead, which is smaller and faster.
6777 if (!Op.hasOneUse())
6779 SDNode *User = *Op.getNode()->use_begin();
6780 if ((User->getOpcode() != ISD::STORE ||
6781 (isa<ConstantSDNode>(Op.getOperand(1)) &&
6782 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
6783 (User->getOpcode() != ISD::BITCAST ||
6784 User->getValueType(0) != MVT::i32))
6786 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6787 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
6790 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
6793 if (VT == MVT::i32 || VT == MVT::i64) {
6794 // ExtractPS/pextrq works with constant index.
6795 if (isa<ConstantSDNode>(Op.getOperand(1)))
6803 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
6804 SelectionDAG &DAG) const {
6805 if (!isa<ConstantSDNode>(Op.getOperand(1)))
6808 SDValue Vec = Op.getOperand(0);
6809 EVT VecVT = Vec.getValueType();
6811 // If this is a 256-bit vector result, first extract the 128-bit vector and
6812 // then extract the element from the 128-bit vector.
6813 if (VecVT.getSizeInBits() == 256) {
6814 DebugLoc dl = Op.getNode()->getDebugLoc();
6815 unsigned NumElems = VecVT.getVectorNumElements();
6816 SDValue Idx = Op.getOperand(1);
6817 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
6819 // Get the 128-bit vector.
6820 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
6822 if (IdxVal >= NumElems/2)
6823 IdxVal -= NumElems/2;
6824 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
6825 DAG.getConstant(IdxVal, MVT::i32));
6828 assert(Vec.getValueSizeInBits() <= 128 && "Unexpected vector length");
6830 if (Subtarget->hasSSE41()) {
6831 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
6836 EVT VT = Op.getValueType();
6837 DebugLoc dl = Op.getDebugLoc();
6838 // TODO: handle v16i8.
6839 if (VT.getSizeInBits() == 16) {
6840 SDValue Vec = Op.getOperand(0);
6841 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6843 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6844 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6845 DAG.getNode(ISD::BITCAST, dl,
6848 // Transform it so it match pextrw which produces a 32-bit result.
6849 EVT EltVT = MVT::i32;
6850 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
6851 Op.getOperand(0), Op.getOperand(1));
6852 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
6853 DAG.getValueType(VT));
6854 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6857 if (VT.getSizeInBits() == 32) {
6858 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6862 // SHUFPS the element to the lowest double word, then movss.
6863 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
6864 EVT VVT = Op.getOperand(0).getValueType();
6865 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6866 DAG.getUNDEF(VVT), Mask);
6867 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6868 DAG.getIntPtrConstant(0));
6871 if (VT.getSizeInBits() == 64) {
6872 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
6873 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
6874 // to match extract_elt for f64.
6875 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6879 // UNPCKHPD the element to the lowest double word, then movsd.
6880 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
6881 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
6882 int Mask[2] = { 1, -1 };
6883 EVT VVT = Op.getOperand(0).getValueType();
6884 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6885 DAG.getUNDEF(VVT), Mask);
6886 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6887 DAG.getIntPtrConstant(0));
6894 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op,
6895 SelectionDAG &DAG) const {
6896 EVT VT = Op.getValueType();
6897 EVT EltVT = VT.getVectorElementType();
6898 DebugLoc dl = Op.getDebugLoc();
6900 SDValue N0 = Op.getOperand(0);
6901 SDValue N1 = Op.getOperand(1);
6902 SDValue N2 = Op.getOperand(2);
6904 if (VT.getSizeInBits() == 256)
6907 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
6908 isa<ConstantSDNode>(N2)) {
6910 if (VT == MVT::v8i16)
6911 Opc = X86ISD::PINSRW;
6912 else if (VT == MVT::v16i8)
6913 Opc = X86ISD::PINSRB;
6915 Opc = X86ISD::PINSRB;
6917 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
6919 if (N1.getValueType() != MVT::i32)
6920 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
6921 if (N2.getValueType() != MVT::i32)
6922 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
6923 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
6926 if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
6927 // Bits [7:6] of the constant are the source select. This will always be
6928 // zero here. The DAG Combiner may combine an extract_elt index into these
6929 // bits. For example (insert (extract, 3), 2) could be matched by putting
6930 // the '3' into bits [7:6] of X86ISD::INSERTPS.
6931 // Bits [5:4] of the constant are the destination select. This is the
6932 // value of the incoming immediate.
6933 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
6934 // combine either bitwise AND or insert of float 0.0 to set these bits.
6935 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
6936 // Create this as a scalar to vector..
6937 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
6938 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
6941 if ((EltVT == MVT::i32 || EltVT == MVT::i64) && isa<ConstantSDNode>(N2)) {
6942 // PINSR* works with constant index.
6949 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
6950 EVT VT = Op.getValueType();
6951 EVT EltVT = VT.getVectorElementType();
6953 DebugLoc dl = Op.getDebugLoc();
6954 SDValue N0 = Op.getOperand(0);
6955 SDValue N1 = Op.getOperand(1);
6956 SDValue N2 = Op.getOperand(2);
6958 // If this is a 256-bit vector result, first extract the 128-bit vector,
6959 // insert the element into the extracted half and then place it back.
6960 if (VT.getSizeInBits() == 256) {
6961 if (!isa<ConstantSDNode>(N2))
6964 // Get the desired 128-bit vector half.
6965 unsigned NumElems = VT.getVectorNumElements();
6966 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue();
6967 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
6969 // Insert the element into the desired half.
6970 bool Upper = IdxVal >= NumElems/2;
6971 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
6972 DAG.getConstant(Upper ? IdxVal-NumElems/2 : IdxVal, MVT::i32));
6974 // Insert the changed part back to the 256-bit vector
6975 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
6978 if (Subtarget->hasSSE41())
6979 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
6981 if (EltVT == MVT::i8)
6984 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
6985 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
6986 // as its second argument.
6987 if (N1.getValueType() != MVT::i32)
6988 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
6989 if (N2.getValueType() != MVT::i32)
6990 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
6991 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
6997 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6998 LLVMContext *Context = DAG.getContext();
6999 DebugLoc dl = Op.getDebugLoc();
7000 EVT OpVT = Op.getValueType();
7002 // If this is a 256-bit vector result, first insert into a 128-bit
7003 // vector and then insert into the 256-bit vector.
7004 if (OpVT.getSizeInBits() > 128) {
7005 // Insert into a 128-bit vector.
7006 EVT VT128 = EVT::getVectorVT(*Context,
7007 OpVT.getVectorElementType(),
7008 OpVT.getVectorNumElements() / 2);
7010 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
7012 // Insert the 128-bit vector.
7013 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
7016 if (OpVT == MVT::v1i64 &&
7017 Op.getOperand(0).getValueType() == MVT::i64)
7018 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
7020 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
7021 assert(OpVT.getSizeInBits() == 128 && "Expected an SSE type!");
7022 return DAG.getNode(ISD::BITCAST, dl, OpVT,
7023 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
7026 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
7027 // a simple subregister reference or explicit instructions to grab
7028 // upper bits of a vector.
7030 X86TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
7031 if (Subtarget->hasAVX()) {
7032 DebugLoc dl = Op.getNode()->getDebugLoc();
7033 SDValue Vec = Op.getNode()->getOperand(0);
7034 SDValue Idx = Op.getNode()->getOperand(1);
7036 if (Op.getNode()->getValueType(0).getSizeInBits() == 128 &&
7037 Vec.getNode()->getValueType(0).getSizeInBits() == 256 &&
7038 isa<ConstantSDNode>(Idx)) {
7039 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7040 return Extract128BitVector(Vec, IdxVal, DAG, dl);
7046 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
7047 // simple superregister reference or explicit instructions to insert
7048 // the upper bits of a vector.
7050 X86TargetLowering::LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
7051 if (Subtarget->hasAVX()) {
7052 DebugLoc dl = Op.getNode()->getDebugLoc();
7053 SDValue Vec = Op.getNode()->getOperand(0);
7054 SDValue SubVec = Op.getNode()->getOperand(1);
7055 SDValue Idx = Op.getNode()->getOperand(2);
7057 if (Op.getNode()->getValueType(0).getSizeInBits() == 256 &&
7058 SubVec.getNode()->getValueType(0).getSizeInBits() == 128 &&
7059 isa<ConstantSDNode>(Idx)) {
7060 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7061 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
7067 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
7068 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
7069 // one of the above mentioned nodes. It has to be wrapped because otherwise
7070 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
7071 // be used to form addressing mode. These wrapped nodes will be selected
7074 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
7075 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
7077 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7079 unsigned char OpFlag = 0;
7080 unsigned WrapperKind = X86ISD::Wrapper;
7081 CodeModel::Model M = getTargetMachine().getCodeModel();
7083 if (Subtarget->isPICStyleRIPRel() &&
7084 (M == CodeModel::Small || M == CodeModel::Kernel))
7085 WrapperKind = X86ISD::WrapperRIP;
7086 else if (Subtarget->isPICStyleGOT())
7087 OpFlag = X86II::MO_GOTOFF;
7088 else if (Subtarget->isPICStyleStubPIC())
7089 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7091 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
7093 CP->getOffset(), OpFlag);
7094 DebugLoc DL = CP->getDebugLoc();
7095 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7096 // With PIC, the address is actually $g + Offset.
7098 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7099 DAG.getNode(X86ISD::GlobalBaseReg,
7100 DebugLoc(), getPointerTy()),
7107 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
7108 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
7110 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7112 unsigned char OpFlag = 0;
7113 unsigned WrapperKind = X86ISD::Wrapper;
7114 CodeModel::Model M = getTargetMachine().getCodeModel();
7116 if (Subtarget->isPICStyleRIPRel() &&
7117 (M == CodeModel::Small || M == CodeModel::Kernel))
7118 WrapperKind = X86ISD::WrapperRIP;
7119 else if (Subtarget->isPICStyleGOT())
7120 OpFlag = X86II::MO_GOTOFF;
7121 else if (Subtarget->isPICStyleStubPIC())
7122 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7124 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
7126 DebugLoc DL = JT->getDebugLoc();
7127 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7129 // With PIC, the address is actually $g + Offset.
7131 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7132 DAG.getNode(X86ISD::GlobalBaseReg,
7133 DebugLoc(), getPointerTy()),
7140 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
7141 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
7143 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7145 unsigned char OpFlag = 0;
7146 unsigned WrapperKind = X86ISD::Wrapper;
7147 CodeModel::Model M = getTargetMachine().getCodeModel();
7149 if (Subtarget->isPICStyleRIPRel() &&
7150 (M == CodeModel::Small || M == CodeModel::Kernel)) {
7151 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
7152 OpFlag = X86II::MO_GOTPCREL;
7153 WrapperKind = X86ISD::WrapperRIP;
7154 } else if (Subtarget->isPICStyleGOT()) {
7155 OpFlag = X86II::MO_GOT;
7156 } else if (Subtarget->isPICStyleStubPIC()) {
7157 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
7158 } else if (Subtarget->isPICStyleStubNoDynamic()) {
7159 OpFlag = X86II::MO_DARWIN_NONLAZY;
7162 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
7164 DebugLoc DL = Op.getDebugLoc();
7165 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7168 // With PIC, the address is actually $g + Offset.
7169 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
7170 !Subtarget->is64Bit()) {
7171 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7172 DAG.getNode(X86ISD::GlobalBaseReg,
7173 DebugLoc(), getPointerTy()),
7177 // For symbols that require a load from a stub to get the address, emit the
7179 if (isGlobalStubReference(OpFlag))
7180 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
7181 MachinePointerInfo::getGOT(), false, false, false, 0);
7187 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
7188 // Create the TargetBlockAddressAddress node.
7189 unsigned char OpFlags =
7190 Subtarget->ClassifyBlockAddressReference();
7191 CodeModel::Model M = getTargetMachine().getCodeModel();
7192 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
7193 DebugLoc dl = Op.getDebugLoc();
7194 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(),
7195 /*isTarget=*/true, OpFlags);
7197 if (Subtarget->isPICStyleRIPRel() &&
7198 (M == CodeModel::Small || M == CodeModel::Kernel))
7199 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7201 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7203 // With PIC, the address is actually $g + Offset.
7204 if (isGlobalRelativeToPICBase(OpFlags)) {
7205 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7206 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7214 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
7216 SelectionDAG &DAG) const {
7217 // Create the TargetGlobalAddress node, folding in the constant
7218 // offset if it is legal.
7219 unsigned char OpFlags =
7220 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
7221 CodeModel::Model M = getTargetMachine().getCodeModel();
7223 if (OpFlags == X86II::MO_NO_FLAG &&
7224 X86::isOffsetSuitableForCodeModel(Offset, M)) {
7225 // A direct static reference to a global.
7226 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
7229 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
7232 if (Subtarget->isPICStyleRIPRel() &&
7233 (M == CodeModel::Small || M == CodeModel::Kernel))
7234 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7236 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7238 // With PIC, the address is actually $g + Offset.
7239 if (isGlobalRelativeToPICBase(OpFlags)) {
7240 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7241 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7245 // For globals that require a load from a stub to get the address, emit the
7247 if (isGlobalStubReference(OpFlags))
7248 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
7249 MachinePointerInfo::getGOT(), false, false, false, 0);
7251 // If there was a non-zero offset that we didn't fold, create an explicit
7254 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
7255 DAG.getConstant(Offset, getPointerTy()));
7261 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
7262 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
7263 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
7264 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
7268 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
7269 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
7270 unsigned char OperandFlags, bool LocalDynamic = false) {
7271 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7272 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7273 DebugLoc dl = GA->getDebugLoc();
7274 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7275 GA->getValueType(0),
7279 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
7283 SDValue Ops[] = { Chain, TGA, *InFlag };
7284 Chain = DAG.getNode(CallType, dl, NodeTys, Ops, 3);
7286 SDValue Ops[] = { Chain, TGA };
7287 Chain = DAG.getNode(CallType, dl, NodeTys, Ops, 2);
7290 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
7291 MFI->setAdjustsStack(true);
7293 SDValue Flag = Chain.getValue(1);
7294 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
7297 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
7299 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7302 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
7303 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
7304 DAG.getNode(X86ISD::GlobalBaseReg,
7305 DebugLoc(), PtrVT), InFlag);
7306 InFlag = Chain.getValue(1);
7308 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
7311 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
7313 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7315 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
7316 X86::RAX, X86II::MO_TLSGD);
7319 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
7323 DebugLoc dl = GA->getDebugLoc();
7325 // Get the start address of the TLS block for this module.
7326 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
7327 .getInfo<X86MachineFunctionInfo>();
7328 MFI->incNumLocalDynamicTLSAccesses();
7332 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT, X86::RAX,
7333 X86II::MO_TLSLD, /*LocalDynamic=*/true);
7336 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
7337 DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), PtrVT), InFlag);
7338 InFlag = Chain.getValue(1);
7339 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
7340 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
7343 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
7347 unsigned char OperandFlags = X86II::MO_DTPOFF;
7348 unsigned WrapperKind = X86ISD::Wrapper;
7349 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7350 GA->getValueType(0),
7351 GA->getOffset(), OperandFlags);
7352 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
7354 // Add x@dtpoff with the base.
7355 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
7358 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
7359 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7360 const EVT PtrVT, TLSModel::Model model,
7361 bool is64Bit, bool isPIC) {
7362 DebugLoc dl = GA->getDebugLoc();
7364 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
7365 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
7366 is64Bit ? 257 : 256));
7368 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
7369 DAG.getIntPtrConstant(0),
7370 MachinePointerInfo(Ptr),
7371 false, false, false, 0);
7373 unsigned char OperandFlags = 0;
7374 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
7376 unsigned WrapperKind = X86ISD::Wrapper;
7377 if (model == TLSModel::LocalExec) {
7378 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
7379 } else if (model == TLSModel::InitialExec) {
7381 OperandFlags = X86II::MO_GOTTPOFF;
7382 WrapperKind = X86ISD::WrapperRIP;
7384 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
7387 llvm_unreachable("Unexpected model");
7390 // emit "addl x@ntpoff,%eax" (local exec)
7391 // or "addl x@indntpoff,%eax" (initial exec)
7392 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
7393 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7394 GA->getValueType(0),
7395 GA->getOffset(), OperandFlags);
7396 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
7398 if (model == TLSModel::InitialExec) {
7399 if (isPIC && !is64Bit) {
7400 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
7401 DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), PtrVT),
7404 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
7405 MachinePointerInfo::getGOT(), false, false, false,
7410 // The address of the thread local variable is the add of the thread
7411 // pointer with the offset of the variable.
7412 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
7416 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
7418 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
7419 const GlobalValue *GV = GA->getGlobal();
7421 if (Subtarget->isTargetELF()) {
7422 TLSModel::Model model = getTargetMachine().getTLSModel(GV);
7425 case TLSModel::GeneralDynamic:
7426 if (Subtarget->is64Bit())
7427 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
7428 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
7429 case TLSModel::LocalDynamic:
7430 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
7431 Subtarget->is64Bit());
7432 case TLSModel::InitialExec:
7433 case TLSModel::LocalExec:
7434 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
7435 Subtarget->is64Bit(),
7436 getTargetMachine().getRelocationModel() == Reloc::PIC_);
7438 llvm_unreachable("Unknown TLS model.");
7441 if (Subtarget->isTargetDarwin()) {
7442 // Darwin only has one model of TLS. Lower to that.
7443 unsigned char OpFlag = 0;
7444 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
7445 X86ISD::WrapperRIP : X86ISD::Wrapper;
7447 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7449 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
7450 !Subtarget->is64Bit();
7452 OpFlag = X86II::MO_TLVP_PIC_BASE;
7454 OpFlag = X86II::MO_TLVP;
7455 DebugLoc DL = Op.getDebugLoc();
7456 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
7457 GA->getValueType(0),
7458 GA->getOffset(), OpFlag);
7459 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7461 // With PIC32, the address is actually $g + Offset.
7463 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7464 DAG.getNode(X86ISD::GlobalBaseReg,
7465 DebugLoc(), getPointerTy()),
7468 // Lowering the machine isd will make sure everything is in the right
7470 SDValue Chain = DAG.getEntryNode();
7471 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7472 SDValue Args[] = { Chain, Offset };
7473 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2);
7475 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
7476 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7477 MFI->setAdjustsStack(true);
7479 // And our return value (tls address) is in the standard call return value
7481 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
7482 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
7486 if (Subtarget->isTargetWindows()) {
7487 // Just use the implicit TLS architecture
7488 // Need to generate someting similar to:
7489 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
7491 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
7492 // mov rcx, qword [rdx+rcx*8]
7493 // mov eax, .tls$:tlsvar
7494 // [rax+rcx] contains the address
7495 // Windows 64bit: gs:0x58
7496 // Windows 32bit: fs:__tls_array
7498 // If GV is an alias then use the aliasee for determining
7499 // thread-localness.
7500 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
7501 GV = GA->resolveAliasedGlobal(false);
7502 DebugLoc dl = GA->getDebugLoc();
7503 SDValue Chain = DAG.getEntryNode();
7505 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
7506 // %gs:0x58 (64-bit).
7507 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
7508 ? Type::getInt8PtrTy(*DAG.getContext(),
7510 : Type::getInt32PtrTy(*DAG.getContext(),
7513 SDValue ThreadPointer = DAG.getLoad(getPointerTy(), dl, Chain,
7514 Subtarget->is64Bit()
7515 ? DAG.getIntPtrConstant(0x58)
7516 : DAG.getExternalSymbol("_tls_array",
7518 MachinePointerInfo(Ptr),
7519 false, false, false, 0);
7521 // Load the _tls_index variable
7522 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
7523 if (Subtarget->is64Bit())
7524 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
7525 IDX, MachinePointerInfo(), MVT::i32,
7528 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
7529 false, false, false, 0);
7531 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
7533 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
7535 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
7536 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
7537 false, false, false, 0);
7539 // Get the offset of start of .tls section
7540 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7541 GA->getValueType(0),
7542 GA->getOffset(), X86II::MO_SECREL);
7543 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
7545 // The address of the thread local variable is the add of the thread
7546 // pointer with the offset of the variable.
7547 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
7550 llvm_unreachable("TLS not implemented for this target.");
7554 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
7555 /// and take a 2 x i32 value to shift plus a shift amount.
7556 SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const{
7557 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
7558 EVT VT = Op.getValueType();
7559 unsigned VTBits = VT.getSizeInBits();
7560 DebugLoc dl = Op.getDebugLoc();
7561 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
7562 SDValue ShOpLo = Op.getOperand(0);
7563 SDValue ShOpHi = Op.getOperand(1);
7564 SDValue ShAmt = Op.getOperand(2);
7565 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
7566 DAG.getConstant(VTBits - 1, MVT::i8))
7567 : DAG.getConstant(0, VT);
7570 if (Op.getOpcode() == ISD::SHL_PARTS) {
7571 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
7572 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
7574 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
7575 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
7578 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
7579 DAG.getConstant(VTBits, MVT::i8));
7580 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
7581 AndNode, DAG.getConstant(0, MVT::i8));
7584 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
7585 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
7586 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
7588 if (Op.getOpcode() == ISD::SHL_PARTS) {
7589 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7590 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7592 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7593 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7596 SDValue Ops[2] = { Lo, Hi };
7597 return DAG.getMergeValues(Ops, 2, dl);
7600 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
7601 SelectionDAG &DAG) const {
7602 EVT SrcVT = Op.getOperand(0).getValueType();
7604 if (SrcVT.isVector())
7607 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
7608 "Unknown SINT_TO_FP to lower!");
7610 // These are really Legal; return the operand so the caller accepts it as
7612 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
7614 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
7615 Subtarget->is64Bit()) {
7619 DebugLoc dl = Op.getDebugLoc();
7620 unsigned Size = SrcVT.getSizeInBits()/8;
7621 MachineFunction &MF = DAG.getMachineFunction();
7622 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
7623 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7624 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7626 MachinePointerInfo::getFixedStack(SSFI),
7628 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
7631 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
7633 SelectionDAG &DAG) const {
7635 DebugLoc DL = Op.getDebugLoc();
7637 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
7639 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
7641 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
7643 unsigned ByteSize = SrcVT.getSizeInBits()/8;
7645 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
7646 MachineMemOperand *MMO;
7648 int SSFI = FI->getIndex();
7650 DAG.getMachineFunction()
7651 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7652 MachineMemOperand::MOLoad, ByteSize, ByteSize);
7654 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
7655 StackSlot = StackSlot.getOperand(1);
7657 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
7658 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
7660 Tys, Ops, array_lengthof(Ops),
7664 Chain = Result.getValue(1);
7665 SDValue InFlag = Result.getValue(2);
7667 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
7668 // shouldn't be necessary except that RFP cannot be live across
7669 // multiple blocks. When stackifier is fixed, they can be uncoupled.
7670 MachineFunction &MF = DAG.getMachineFunction();
7671 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
7672 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
7673 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7674 Tys = DAG.getVTList(MVT::Other);
7676 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
7678 MachineMemOperand *MMO =
7679 DAG.getMachineFunction()
7680 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7681 MachineMemOperand::MOStore, SSFISize, SSFISize);
7683 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
7684 Ops, array_lengthof(Ops),
7685 Op.getValueType(), MMO);
7686 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
7687 MachinePointerInfo::getFixedStack(SSFI),
7688 false, false, false, 0);
7694 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
7695 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
7696 SelectionDAG &DAG) const {
7697 // This algorithm is not obvious. Here it is what we're trying to output:
7700 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
7701 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
7705 pshufd $0x4e, %xmm0, %xmm1
7710 DebugLoc dl = Op.getDebugLoc();
7711 LLVMContext *Context = DAG.getContext();
7713 // Build some magic constants.
7714 const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
7715 Constant *C0 = ConstantDataVector::get(*Context, CV0);
7716 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
7718 SmallVector<Constant*,2> CV1;
7720 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL))));
7722 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL))));
7723 Constant *C1 = ConstantVector::get(CV1);
7724 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
7726 // Load the 64-bit value into an XMM register.
7727 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
7729 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
7730 MachinePointerInfo::getConstantPool(),
7731 false, false, false, 16);
7732 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
7733 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
7736 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
7737 MachinePointerInfo::getConstantPool(),
7738 false, false, false, 16);
7739 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
7740 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
7743 if (Subtarget->hasSSE3()) {
7744 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
7745 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
7747 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
7748 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
7750 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
7751 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
7755 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
7756 DAG.getIntPtrConstant(0));
7759 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
7760 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
7761 SelectionDAG &DAG) const {
7762 DebugLoc dl = Op.getDebugLoc();
7763 // FP constant to bias correct the final result.
7764 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
7767 // Load the 32-bit value into an XMM register.
7768 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
7771 // Zero out the upper parts of the register.
7772 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
7774 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7775 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
7776 DAG.getIntPtrConstant(0));
7778 // Or the load with the bias.
7779 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
7780 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7781 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7783 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7784 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7785 MVT::v2f64, Bias)));
7786 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7787 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
7788 DAG.getIntPtrConstant(0));
7790 // Subtract the bias.
7791 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
7793 // Handle final rounding.
7794 EVT DestVT = Op.getValueType();
7796 if (DestVT.bitsLT(MVT::f64))
7797 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
7798 DAG.getIntPtrConstant(0));
7799 if (DestVT.bitsGT(MVT::f64))
7800 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
7802 // Handle final rounding.
7806 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
7807 SelectionDAG &DAG) const {
7808 SDValue N0 = Op.getOperand(0);
7809 DebugLoc dl = Op.getDebugLoc();
7811 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
7812 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
7813 // the optimization here.
7814 if (DAG.SignBitIsZero(N0))
7815 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
7817 EVT SrcVT = N0.getValueType();
7818 EVT DstVT = Op.getValueType();
7819 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
7820 return LowerUINT_TO_FP_i64(Op, DAG);
7821 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
7822 return LowerUINT_TO_FP_i32(Op, DAG);
7823 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
7826 // Make a 64-bit buffer, and use it to build an FILD.
7827 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
7828 if (SrcVT == MVT::i32) {
7829 SDValue WordOff = DAG.getConstant(4, getPointerTy());
7830 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
7831 getPointerTy(), StackSlot, WordOff);
7832 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7833 StackSlot, MachinePointerInfo(),
7835 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
7836 OffsetSlot, MachinePointerInfo(),
7838 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
7842 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
7843 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7844 StackSlot, MachinePointerInfo(),
7846 // For i64 source, we need to add the appropriate power of 2 if the input
7847 // was negative. This is the same as the optimization in
7848 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
7849 // we must be careful to do the computation in x87 extended precision, not
7850 // in SSE. (The generic code can't know it's OK to do this, or how to.)
7851 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
7852 MachineMemOperand *MMO =
7853 DAG.getMachineFunction()
7854 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7855 MachineMemOperand::MOLoad, 8, 8);
7857 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
7858 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
7859 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, 3,
7862 APInt FF(32, 0x5F800000ULL);
7864 // Check whether the sign bit is set.
7865 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
7866 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
7869 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
7870 SDValue FudgePtr = DAG.getConstantPool(
7871 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
7874 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
7875 SDValue Zero = DAG.getIntPtrConstant(0);
7876 SDValue Four = DAG.getIntPtrConstant(4);
7877 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
7879 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
7881 // Load the value out, extending it from f32 to f80.
7882 // FIXME: Avoid the extend by constructing the right constant pool?
7883 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
7884 FudgePtr, MachinePointerInfo::getConstantPool(),
7885 MVT::f32, false, false, 4);
7886 // Extend everything to 80 bits to force it to be done on x87.
7887 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
7888 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
7891 std::pair<SDValue,SDValue> X86TargetLowering::
7892 FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned, bool IsReplace) const {
7893 DebugLoc DL = Op.getDebugLoc();
7895 EVT DstTy = Op.getValueType();
7897 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
7898 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
7902 assert(DstTy.getSimpleVT() <= MVT::i64 &&
7903 DstTy.getSimpleVT() >= MVT::i16 &&
7904 "Unknown FP_TO_INT to lower!");
7906 // These are really Legal.
7907 if (DstTy == MVT::i32 &&
7908 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
7909 return std::make_pair(SDValue(), SDValue());
7910 if (Subtarget->is64Bit() &&
7911 DstTy == MVT::i64 &&
7912 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
7913 return std::make_pair(SDValue(), SDValue());
7915 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
7916 // stack slot, or into the FTOL runtime function.
7917 MachineFunction &MF = DAG.getMachineFunction();
7918 unsigned MemSize = DstTy.getSizeInBits()/8;
7919 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
7920 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7923 if (!IsSigned && isIntegerTypeFTOL(DstTy))
7924 Opc = X86ISD::WIN_FTOL;
7926 switch (DstTy.getSimpleVT().SimpleTy) {
7927 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
7928 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
7929 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
7930 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
7933 SDValue Chain = DAG.getEntryNode();
7934 SDValue Value = Op.getOperand(0);
7935 EVT TheVT = Op.getOperand(0).getValueType();
7936 // FIXME This causes a redundant load/store if the SSE-class value is already
7937 // in memory, such as if it is on the callstack.
7938 if (isScalarFPTypeInSSEReg(TheVT)) {
7939 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
7940 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
7941 MachinePointerInfo::getFixedStack(SSFI),
7943 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
7945 Chain, StackSlot, DAG.getValueType(TheVT)
7948 MachineMemOperand *MMO =
7949 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7950 MachineMemOperand::MOLoad, MemSize, MemSize);
7951 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, 3,
7953 Chain = Value.getValue(1);
7954 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
7955 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7958 MachineMemOperand *MMO =
7959 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7960 MachineMemOperand::MOStore, MemSize, MemSize);
7962 if (Opc != X86ISD::WIN_FTOL) {
7963 // Build the FP_TO_INT*_IN_MEM
7964 SDValue Ops[] = { Chain, Value, StackSlot };
7965 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
7966 Ops, 3, DstTy, MMO);
7967 return std::make_pair(FIST, StackSlot);
7969 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
7970 DAG.getVTList(MVT::Other, MVT::Glue),
7972 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
7973 MVT::i32, ftol.getValue(1));
7974 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
7975 MVT::i32, eax.getValue(2));
7976 SDValue Ops[] = { eax, edx };
7977 SDValue pair = IsReplace
7978 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops, 2)
7979 : DAG.getMergeValues(Ops, 2, DL);
7980 return std::make_pair(pair, SDValue());
7984 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
7985 SelectionDAG &DAG) const {
7986 if (Op.getValueType().isVector())
7989 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
7990 /*IsSigned=*/ true, /*IsReplace=*/ false);
7991 SDValue FIST = Vals.first, StackSlot = Vals.second;
7992 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
7993 if (FIST.getNode() == 0) return Op;
7995 if (StackSlot.getNode())
7997 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
7998 FIST, StackSlot, MachinePointerInfo(),
7999 false, false, false, 0);
8001 // The node is the result.
8005 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
8006 SelectionDAG &DAG) const {
8007 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
8008 /*IsSigned=*/ false, /*IsReplace=*/ false);
8009 SDValue FIST = Vals.first, StackSlot = Vals.second;
8010 assert(FIST.getNode() && "Unexpected failure");
8012 if (StackSlot.getNode())
8014 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
8015 FIST, StackSlot, MachinePointerInfo(),
8016 false, false, false, 0);
8018 // The node is the result.
8022 SDValue X86TargetLowering::LowerFABS(SDValue Op,
8023 SelectionDAG &DAG) const {
8024 LLVMContext *Context = DAG.getContext();
8025 DebugLoc dl = Op.getDebugLoc();
8026 EVT VT = Op.getValueType();
8029 EltVT = VT.getVectorElementType();
8031 if (EltVT == MVT::f64) {
8032 C = ConstantVector::getSplat(2,
8033 ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
8035 C = ConstantVector::getSplat(4,
8036 ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
8038 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8039 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8040 MachinePointerInfo::getConstantPool(),
8041 false, false, false, 16);
8042 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
8045 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
8046 LLVMContext *Context = DAG.getContext();
8047 DebugLoc dl = Op.getDebugLoc();
8048 EVT VT = Op.getValueType();
8050 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
8051 if (VT.isVector()) {
8052 EltVT = VT.getVectorElementType();
8053 NumElts = VT.getVectorNumElements();
8056 if (EltVT == MVT::f64)
8057 C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)));
8059 C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)));
8060 C = ConstantVector::getSplat(NumElts, C);
8061 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8062 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8063 MachinePointerInfo::getConstantPool(),
8064 false, false, false, 16);
8065 if (VT.isVector()) {
8066 MVT XORVT = VT.getSizeInBits() == 128 ? MVT::v2i64 : MVT::v4i64;
8067 return DAG.getNode(ISD::BITCAST, dl, VT,
8068 DAG.getNode(ISD::XOR, dl, XORVT,
8069 DAG.getNode(ISD::BITCAST, dl, XORVT,
8071 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask)));
8074 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
8077 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
8078 LLVMContext *Context = DAG.getContext();
8079 SDValue Op0 = Op.getOperand(0);
8080 SDValue Op1 = Op.getOperand(1);
8081 DebugLoc dl = Op.getDebugLoc();
8082 EVT VT = Op.getValueType();
8083 EVT SrcVT = Op1.getValueType();
8085 // If second operand is smaller, extend it first.
8086 if (SrcVT.bitsLT(VT)) {
8087 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
8090 // And if it is bigger, shrink it first.
8091 if (SrcVT.bitsGT(VT)) {
8092 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
8096 // At this point the operands and the result should have the same
8097 // type, and that won't be f80 since that is not custom lowered.
8099 // First get the sign bit of second operand.
8100 SmallVector<Constant*,4> CV;
8101 if (SrcVT == MVT::f64) {
8102 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))));
8103 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
8105 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))));
8106 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8107 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8108 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8110 Constant *C = ConstantVector::get(CV);
8111 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8112 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
8113 MachinePointerInfo::getConstantPool(),
8114 false, false, false, 16);
8115 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
8117 // Shift sign bit right or left if the two operands have different types.
8118 if (SrcVT.bitsGT(VT)) {
8119 // Op0 is MVT::f32, Op1 is MVT::f64.
8120 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
8121 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
8122 DAG.getConstant(32, MVT::i32));
8123 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
8124 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
8125 DAG.getIntPtrConstant(0));
8128 // Clear first operand sign bit.
8130 if (VT == MVT::f64) {
8131 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
8132 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
8134 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
8135 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8136 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8137 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8139 C = ConstantVector::get(CV);
8140 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8141 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8142 MachinePointerInfo::getConstantPool(),
8143 false, false, false, 16);
8144 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
8146 // Or the value with the sign bit.
8147 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
8150 SDValue X86TargetLowering::LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) const {
8151 SDValue N0 = Op.getOperand(0);
8152 DebugLoc dl = Op.getDebugLoc();
8153 EVT VT = Op.getValueType();
8155 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
8156 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
8157 DAG.getConstant(1, VT));
8158 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
8161 /// Emit nodes that will be selected as "test Op0,Op0", or something
8163 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
8164 SelectionDAG &DAG) const {
8165 DebugLoc dl = Op.getDebugLoc();
8167 // CF and OF aren't always set the way we want. Determine which
8168 // of these we need.
8169 bool NeedCF = false;
8170 bool NeedOF = false;
8173 case X86::COND_A: case X86::COND_AE:
8174 case X86::COND_B: case X86::COND_BE:
8177 case X86::COND_G: case X86::COND_GE:
8178 case X86::COND_L: case X86::COND_LE:
8179 case X86::COND_O: case X86::COND_NO:
8184 // See if we can use the EFLAGS value from the operand instead of
8185 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
8186 // we prove that the arithmetic won't overflow, we can't use OF or CF.
8187 if (Op.getResNo() != 0 || NeedOF || NeedCF)
8188 // Emit a CMP with 0, which is the TEST pattern.
8189 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8190 DAG.getConstant(0, Op.getValueType()));
8192 unsigned Opcode = 0;
8193 unsigned NumOperands = 0;
8194 switch (Op.getNode()->getOpcode()) {
8196 // Due to an isel shortcoming, be conservative if this add is likely to be
8197 // selected as part of a load-modify-store instruction. When the root node
8198 // in a match is a store, isel doesn't know how to remap non-chain non-flag
8199 // uses of other nodes in the match, such as the ADD in this case. This
8200 // leads to the ADD being left around and reselected, with the result being
8201 // two adds in the output. Alas, even if none our users are stores, that
8202 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
8203 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
8204 // climbing the DAG back to the root, and it doesn't seem to be worth the
8206 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8207 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8208 if (UI->getOpcode() != ISD::CopyToReg &&
8209 UI->getOpcode() != ISD::SETCC &&
8210 UI->getOpcode() != ISD::STORE)
8213 if (ConstantSDNode *C =
8214 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
8215 // An add of one will be selected as an INC.
8216 if (C->getAPIntValue() == 1) {
8217 Opcode = X86ISD::INC;
8222 // An add of negative one (subtract of one) will be selected as a DEC.
8223 if (C->getAPIntValue().isAllOnesValue()) {
8224 Opcode = X86ISD::DEC;
8230 // Otherwise use a regular EFLAGS-setting add.
8231 Opcode = X86ISD::ADD;
8235 // If the primary and result isn't used, don't bother using X86ISD::AND,
8236 // because a TEST instruction will be better.
8237 bool NonFlagUse = false;
8238 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8239 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
8241 unsigned UOpNo = UI.getOperandNo();
8242 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
8243 // Look pass truncate.
8244 UOpNo = User->use_begin().getOperandNo();
8245 User = *User->use_begin();
8248 if (User->getOpcode() != ISD::BRCOND &&
8249 User->getOpcode() != ISD::SETCC &&
8250 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) {
8263 // Due to the ISEL shortcoming noted above, be conservative if this op is
8264 // likely to be selected as part of a load-modify-store instruction.
8265 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8266 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8267 if (UI->getOpcode() == ISD::STORE)
8270 // Otherwise use a regular EFLAGS-setting instruction.
8271 switch (Op.getNode()->getOpcode()) {
8272 default: llvm_unreachable("unexpected operator!");
8274 // If the only use of SUB is EFLAGS, use CMP instead.
8276 Opcode = X86ISD::CMP;
8278 Opcode = X86ISD::SUB;
8280 case ISD::OR: Opcode = X86ISD::OR; break;
8281 case ISD::XOR: Opcode = X86ISD::XOR; break;
8282 case ISD::AND: Opcode = X86ISD::AND; break;
8294 return SDValue(Op.getNode(), 1);
8301 // Emit a CMP with 0, which is the TEST pattern.
8302 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8303 DAG.getConstant(0, Op.getValueType()));
8305 if (Opcode == X86ISD::CMP) {
8306 SDValue New = DAG.getNode(Opcode, dl, MVT::i32, Op.getOperand(0),
8308 // We can't replace usage of SUB with CMP.
8309 // The SUB node will be removed later because there is no use of it.
8310 return SDValue(New.getNode(), 0);
8313 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
8314 SmallVector<SDValue, 4> Ops;
8315 for (unsigned i = 0; i != NumOperands; ++i)
8316 Ops.push_back(Op.getOperand(i));
8318 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
8319 DAG.ReplaceAllUsesWith(Op, New);
8320 return SDValue(New.getNode(), 1);
8323 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
8325 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
8326 SelectionDAG &DAG) const {
8327 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
8328 if (C->getAPIntValue() == 0)
8329 return EmitTest(Op0, X86CC, DAG);
8331 DebugLoc dl = Op0.getDebugLoc();
8332 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
8335 /// Convert a comparison if required by the subtarget.
8336 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
8337 SelectionDAG &DAG) const {
8338 // If the subtarget does not support the FUCOMI instruction, floating-point
8339 // comparisons have to be converted.
8340 if (Subtarget->hasCMov() ||
8341 Cmp.getOpcode() != X86ISD::CMP ||
8342 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
8343 !Cmp.getOperand(1).getValueType().isFloatingPoint())
8346 // The instruction selector will select an FUCOM instruction instead of
8347 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
8348 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
8349 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
8350 DebugLoc dl = Cmp.getDebugLoc();
8351 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
8352 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
8353 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
8354 DAG.getConstant(8, MVT::i8));
8355 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
8356 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
8359 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
8360 /// if it's possible.
8361 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
8362 DebugLoc dl, SelectionDAG &DAG) const {
8363 SDValue Op0 = And.getOperand(0);
8364 SDValue Op1 = And.getOperand(1);
8365 if (Op0.getOpcode() == ISD::TRUNCATE)
8366 Op0 = Op0.getOperand(0);
8367 if (Op1.getOpcode() == ISD::TRUNCATE)
8368 Op1 = Op1.getOperand(0);
8371 if (Op1.getOpcode() == ISD::SHL)
8372 std::swap(Op0, Op1);
8373 if (Op0.getOpcode() == ISD::SHL) {
8374 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
8375 if (And00C->getZExtValue() == 1) {
8376 // If we looked past a truncate, check that it's only truncating away
8378 unsigned BitWidth = Op0.getValueSizeInBits();
8379 unsigned AndBitWidth = And.getValueSizeInBits();
8380 if (BitWidth > AndBitWidth) {
8382 DAG.ComputeMaskedBits(Op0, Zeros, Ones);
8383 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
8387 RHS = Op0.getOperand(1);
8389 } else if (Op1.getOpcode() == ISD::Constant) {
8390 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
8391 uint64_t AndRHSVal = AndRHS->getZExtValue();
8392 SDValue AndLHS = Op0;
8394 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
8395 LHS = AndLHS.getOperand(0);
8396 RHS = AndLHS.getOperand(1);
8399 // Use BT if the immediate can't be encoded in a TEST instruction.
8400 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
8402 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
8406 if (LHS.getNode()) {
8407 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
8408 // instruction. Since the shift amount is in-range-or-undefined, we know
8409 // that doing a bittest on the i32 value is ok. We extend to i32 because
8410 // the encoding for the i16 version is larger than the i32 version.
8411 // Also promote i16 to i32 for performance / code size reason.
8412 if (LHS.getValueType() == MVT::i8 ||
8413 LHS.getValueType() == MVT::i16)
8414 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
8416 // If the operand types disagree, extend the shift amount to match. Since
8417 // BT ignores high bits (like shifts) we can use anyextend.
8418 if (LHS.getValueType() != RHS.getValueType())
8419 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
8421 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
8422 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
8423 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8424 DAG.getConstant(Cond, MVT::i8), BT);
8430 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
8432 if (Op.getValueType().isVector()) return LowerVSETCC(Op, DAG);
8434 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
8435 SDValue Op0 = Op.getOperand(0);
8436 SDValue Op1 = Op.getOperand(1);
8437 DebugLoc dl = Op.getDebugLoc();
8438 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
8440 // Optimize to BT if possible.
8441 // Lower (X & (1 << N)) == 0 to BT(X, N).
8442 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
8443 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
8444 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
8445 Op1.getOpcode() == ISD::Constant &&
8446 cast<ConstantSDNode>(Op1)->isNullValue() &&
8447 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8448 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
8449 if (NewSetCC.getNode())
8453 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
8455 if (Op1.getOpcode() == ISD::Constant &&
8456 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
8457 cast<ConstantSDNode>(Op1)->isNullValue()) &&
8458 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8460 // If the input is a setcc, then reuse the input setcc or use a new one with
8461 // the inverted condition.
8462 if (Op0.getOpcode() == X86ISD::SETCC) {
8463 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
8464 bool Invert = (CC == ISD::SETNE) ^
8465 cast<ConstantSDNode>(Op1)->isNullValue();
8466 if (!Invert) return Op0;
8468 CCode = X86::GetOppositeBranchCondition(CCode);
8469 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8470 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
8474 bool isFP = Op1.getValueType().isFloatingPoint();
8475 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
8476 if (X86CC == X86::COND_INVALID)
8479 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG);
8480 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
8481 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8482 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
8485 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
8486 // ones, and then concatenate the result back.
8487 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
8488 EVT VT = Op.getValueType();
8490 assert(VT.getSizeInBits() == 256 && Op.getOpcode() == ISD::SETCC &&
8491 "Unsupported value type for operation");
8493 unsigned NumElems = VT.getVectorNumElements();
8494 DebugLoc dl = Op.getDebugLoc();
8495 SDValue CC = Op.getOperand(2);
8497 // Extract the LHS vectors
8498 SDValue LHS = Op.getOperand(0);
8499 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
8500 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
8502 // Extract the RHS vectors
8503 SDValue RHS = Op.getOperand(1);
8504 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
8505 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
8507 // Issue the operation on the smaller types and concatenate the result back
8508 MVT EltVT = VT.getVectorElementType().getSimpleVT();
8509 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
8510 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
8511 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
8512 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
8516 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const {
8518 SDValue Op0 = Op.getOperand(0);
8519 SDValue Op1 = Op.getOperand(1);
8520 SDValue CC = Op.getOperand(2);
8521 EVT VT = Op.getValueType();
8522 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
8523 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
8524 DebugLoc dl = Op.getDebugLoc();
8528 EVT EltVT = Op0.getValueType().getVectorElementType();
8529 assert(EltVT == MVT::f32 || EltVT == MVT::f64); (void)EltVT;
8533 // SSE Condition code mapping:
8542 switch (SetCCOpcode) {
8545 case ISD::SETEQ: SSECC = 0; break;
8547 case ISD::SETGT: Swap = true; // Fallthrough
8549 case ISD::SETOLT: SSECC = 1; break;
8551 case ISD::SETGE: Swap = true; // Fallthrough
8553 case ISD::SETOLE: SSECC = 2; break;
8554 case ISD::SETUO: SSECC = 3; break;
8556 case ISD::SETNE: SSECC = 4; break;
8557 case ISD::SETULE: Swap = true;
8558 case ISD::SETUGE: SSECC = 5; break;
8559 case ISD::SETULT: Swap = true;
8560 case ISD::SETUGT: SSECC = 6; break;
8561 case ISD::SETO: SSECC = 7; break;
8564 std::swap(Op0, Op1);
8566 // In the two special cases we can't handle, emit two comparisons.
8568 if (SetCCOpcode == ISD::SETUEQ) {
8570 UNORD = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8571 DAG.getConstant(3, MVT::i8));
8572 EQ = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8573 DAG.getConstant(0, MVT::i8));
8574 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
8576 if (SetCCOpcode == ISD::SETONE) {
8578 ORD = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8579 DAG.getConstant(7, MVT::i8));
8580 NEQ = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8581 DAG.getConstant(4, MVT::i8));
8582 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
8584 llvm_unreachable("Illegal FP comparison");
8586 // Handle all other FP comparisons here.
8587 return DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8588 DAG.getConstant(SSECC, MVT::i8));
8591 // Break 256-bit integer vector compare into smaller ones.
8592 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2())
8593 return Lower256IntVSETCC(Op, DAG);
8595 // We are handling one of the integer comparisons here. Since SSE only has
8596 // GT and EQ comparisons for integer, swapping operands and multiple
8597 // operations may be required for some comparisons.
8599 bool Swap = false, Invert = false, FlipSigns = false;
8601 switch (SetCCOpcode) {
8603 case ISD::SETNE: Invert = true;
8604 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
8605 case ISD::SETLT: Swap = true;
8606 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
8607 case ISD::SETGE: Swap = true;
8608 case ISD::SETLE: Opc = X86ISD::PCMPGT; Invert = true; break;
8609 case ISD::SETULT: Swap = true;
8610 case ISD::SETUGT: Opc = X86ISD::PCMPGT; FlipSigns = true; break;
8611 case ISD::SETUGE: Swap = true;
8612 case ISD::SETULE: Opc = X86ISD::PCMPGT; FlipSigns = true; Invert = true; break;
8615 std::swap(Op0, Op1);
8617 // Check that the operation in question is available (most are plain SSE2,
8618 // but PCMPGTQ and PCMPEQQ have different requirements).
8619 if (Opc == X86ISD::PCMPGT && VT == MVT::v2i64 && !Subtarget->hasSSE42())
8621 if (Opc == X86ISD::PCMPEQ && VT == MVT::v2i64 && !Subtarget->hasSSE41())
8624 // Since SSE has no unsigned integer comparisons, we need to flip the sign
8625 // bits of the inputs before performing those operations.
8627 EVT EltVT = VT.getVectorElementType();
8628 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
8630 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
8631 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
8633 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
8634 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
8637 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
8639 // If the logical-not of the result is required, perform that now.
8641 Result = DAG.getNOT(dl, Result, VT);
8646 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
8647 static bool isX86LogicalCmp(SDValue Op) {
8648 unsigned Opc = Op.getNode()->getOpcode();
8649 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
8650 Opc == X86ISD::SAHF)
8652 if (Op.getResNo() == 1 &&
8653 (Opc == X86ISD::ADD ||
8654 Opc == X86ISD::SUB ||
8655 Opc == X86ISD::ADC ||
8656 Opc == X86ISD::SBB ||
8657 Opc == X86ISD::SMUL ||
8658 Opc == X86ISD::UMUL ||
8659 Opc == X86ISD::INC ||
8660 Opc == X86ISD::DEC ||
8661 Opc == X86ISD::OR ||
8662 Opc == X86ISD::XOR ||
8663 Opc == X86ISD::AND))
8666 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
8672 static bool isZero(SDValue V) {
8673 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
8674 return C && C->isNullValue();
8677 static bool isAllOnes(SDValue V) {
8678 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
8679 return C && C->isAllOnesValue();
8682 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
8683 bool addTest = true;
8684 SDValue Cond = Op.getOperand(0);
8685 SDValue Op1 = Op.getOperand(1);
8686 SDValue Op2 = Op.getOperand(2);
8687 DebugLoc DL = Op.getDebugLoc();
8690 if (Cond.getOpcode() == ISD::SETCC) {
8691 SDValue NewCond = LowerSETCC(Cond, DAG);
8692 if (NewCond.getNode())
8696 // Handle the following cases related to max and min:
8697 // (a > b) ? (a-b) : 0
8698 // (a >= b) ? (a-b) : 0
8699 // (b < a) ? (a-b) : 0
8700 // (b <= a) ? (a-b) : 0
8701 // Comparison is removed to use EFLAGS from SUB.
8702 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op2))
8703 if (Cond.getOpcode() == X86ISD::SETCC &&
8704 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
8705 (Op1.getOpcode() == ISD::SUB || Op1.getOpcode() == X86ISD::SUB) &&
8706 C->getAPIntValue() == 0) {
8707 SDValue Cmp = Cond.getOperand(1);
8708 unsigned CC = cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
8709 if ((DAG.isEqualTo(Op1.getOperand(0), Cmp.getOperand(0)) &&
8710 DAG.isEqualTo(Op1.getOperand(1), Cmp.getOperand(1)) &&
8711 (CC == X86::COND_G || CC == X86::COND_GE ||
8712 CC == X86::COND_A || CC == X86::COND_AE)) ||
8713 (DAG.isEqualTo(Op1.getOperand(0), Cmp.getOperand(1)) &&
8714 DAG.isEqualTo(Op1.getOperand(1), Cmp.getOperand(0)) &&
8715 (CC == X86::COND_L || CC == X86::COND_LE ||
8716 CC == X86::COND_B || CC == X86::COND_BE))) {
8718 if (Op1.getOpcode() == ISD::SUB) {
8719 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i32);
8720 SDValue New = DAG.getNode(X86ISD::SUB, DL, VTs,
8721 Op1.getOperand(0), Op1.getOperand(1));
8722 DAG.ReplaceAllUsesWith(Op1, New);
8726 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
8727 unsigned NewCC = (CC == X86::COND_G || CC == X86::COND_GE ||
8728 CC == X86::COND_L ||
8729 CC == X86::COND_LE) ? X86::COND_GE : X86::COND_AE;
8730 SDValue Ops[] = { Op2, Op1, DAG.getConstant(NewCC, MVT::i8),
8731 SDValue(Op1.getNode(), 1) };
8732 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
8736 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
8737 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
8738 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
8739 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
8740 if (Cond.getOpcode() == X86ISD::SETCC &&
8741 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
8742 isZero(Cond.getOperand(1).getOperand(1))) {
8743 SDValue Cmp = Cond.getOperand(1);
8745 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
8747 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
8748 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
8749 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
8751 SDValue CmpOp0 = Cmp.getOperand(0);
8752 // Apply further optimizations for special cases
8753 // (select (x != 0), -1, 0) -> neg & sbb
8754 // (select (x == 0), 0, -1) -> neg & sbb
8755 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
8756 if (YC->isNullValue() &&
8757 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
8758 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
8759 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
8760 DAG.getConstant(0, CmpOp0.getValueType()),
8762 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8763 DAG.getConstant(X86::COND_B, MVT::i8),
8764 SDValue(Neg.getNode(), 1));
8768 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
8769 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
8770 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
8772 SDValue Res = // Res = 0 or -1.
8773 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8774 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
8776 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
8777 Res = DAG.getNOT(DL, Res, Res.getValueType());
8779 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
8780 if (N2C == 0 || !N2C->isNullValue())
8781 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
8786 // Look past (and (setcc_carry (cmp ...)), 1).
8787 if (Cond.getOpcode() == ISD::AND &&
8788 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
8789 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
8790 if (C && C->getAPIntValue() == 1)
8791 Cond = Cond.getOperand(0);
8794 // If condition flag is set by a X86ISD::CMP, then use it as the condition
8795 // setting operand in place of the X86ISD::SETCC.
8796 unsigned CondOpcode = Cond.getOpcode();
8797 if (CondOpcode == X86ISD::SETCC ||
8798 CondOpcode == X86ISD::SETCC_CARRY) {
8799 CC = Cond.getOperand(0);
8801 SDValue Cmp = Cond.getOperand(1);
8802 unsigned Opc = Cmp.getOpcode();
8803 EVT VT = Op.getValueType();
8805 bool IllegalFPCMov = false;
8806 if (VT.isFloatingPoint() && !VT.isVector() &&
8807 !isScalarFPTypeInSSEReg(VT)) // FPStack?
8808 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
8810 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
8811 Opc == X86ISD::BT) { // FIXME
8815 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
8816 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
8817 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
8818 Cond.getOperand(0).getValueType() != MVT::i8)) {
8819 SDValue LHS = Cond.getOperand(0);
8820 SDValue RHS = Cond.getOperand(1);
8824 switch (CondOpcode) {
8825 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
8826 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
8827 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
8828 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
8829 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
8830 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
8831 default: llvm_unreachable("unexpected overflowing operator");
8833 if (CondOpcode == ISD::UMULO)
8834 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
8837 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
8839 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
8841 if (CondOpcode == ISD::UMULO)
8842 Cond = X86Op.getValue(2);
8844 Cond = X86Op.getValue(1);
8846 CC = DAG.getConstant(X86Cond, MVT::i8);
8851 // Look pass the truncate.
8852 if (Cond.getOpcode() == ISD::TRUNCATE)
8853 Cond = Cond.getOperand(0);
8855 // We know the result of AND is compared against zero. Try to match
8857 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
8858 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
8859 if (NewSetCC.getNode()) {
8860 CC = NewSetCC.getOperand(0);
8861 Cond = NewSetCC.getOperand(1);
8868 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8869 Cond = EmitTest(Cond, X86::COND_NE, DAG);
8872 // a < b ? -1 : 0 -> RES = ~setcc_carry
8873 // a < b ? 0 : -1 -> RES = setcc_carry
8874 // a >= b ? -1 : 0 -> RES = setcc_carry
8875 // a >= b ? 0 : -1 -> RES = ~setcc_carry
8876 if (Cond.getOpcode() == X86ISD::CMP) {
8877 Cond = ConvertCmpIfNecessary(Cond, DAG);
8878 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
8880 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
8881 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
8882 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8883 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
8884 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
8885 return DAG.getNOT(DL, Res, Res.getValueType());
8890 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
8891 // condition is true.
8892 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
8893 SDValue Ops[] = { Op2, Op1, CC, Cond };
8894 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
8897 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
8898 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
8899 // from the AND / OR.
8900 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
8901 Opc = Op.getOpcode();
8902 if (Opc != ISD::OR && Opc != ISD::AND)
8904 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
8905 Op.getOperand(0).hasOneUse() &&
8906 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
8907 Op.getOperand(1).hasOneUse());
8910 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
8911 // 1 and that the SETCC node has a single use.
8912 static bool isXor1OfSetCC(SDValue Op) {
8913 if (Op.getOpcode() != ISD::XOR)
8915 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
8916 if (N1C && N1C->getAPIntValue() == 1) {
8917 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
8918 Op.getOperand(0).hasOneUse();
8923 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
8924 bool addTest = true;
8925 SDValue Chain = Op.getOperand(0);
8926 SDValue Cond = Op.getOperand(1);
8927 SDValue Dest = Op.getOperand(2);
8928 DebugLoc dl = Op.getDebugLoc();
8930 bool Inverted = false;
8932 if (Cond.getOpcode() == ISD::SETCC) {
8933 // Check for setcc([su]{add,sub,mul}o == 0).
8934 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
8935 isa<ConstantSDNode>(Cond.getOperand(1)) &&
8936 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
8937 Cond.getOperand(0).getResNo() == 1 &&
8938 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
8939 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
8940 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
8941 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
8942 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
8943 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
8945 Cond = Cond.getOperand(0);
8947 SDValue NewCond = LowerSETCC(Cond, DAG);
8948 if (NewCond.getNode())
8953 // FIXME: LowerXALUO doesn't handle these!!
8954 else if (Cond.getOpcode() == X86ISD::ADD ||
8955 Cond.getOpcode() == X86ISD::SUB ||
8956 Cond.getOpcode() == X86ISD::SMUL ||
8957 Cond.getOpcode() == X86ISD::UMUL)
8958 Cond = LowerXALUO(Cond, DAG);
8961 // Look pass (and (setcc_carry (cmp ...)), 1).
8962 if (Cond.getOpcode() == ISD::AND &&
8963 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
8964 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
8965 if (C && C->getAPIntValue() == 1)
8966 Cond = Cond.getOperand(0);
8969 // If condition flag is set by a X86ISD::CMP, then use it as the condition
8970 // setting operand in place of the X86ISD::SETCC.
8971 unsigned CondOpcode = Cond.getOpcode();
8972 if (CondOpcode == X86ISD::SETCC ||
8973 CondOpcode == X86ISD::SETCC_CARRY) {
8974 CC = Cond.getOperand(0);
8976 SDValue Cmp = Cond.getOperand(1);
8977 unsigned Opc = Cmp.getOpcode();
8978 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
8979 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
8983 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
8987 // These can only come from an arithmetic instruction with overflow,
8988 // e.g. SADDO, UADDO.
8989 Cond = Cond.getNode()->getOperand(1);
8995 CondOpcode = Cond.getOpcode();
8996 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
8997 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
8998 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
8999 Cond.getOperand(0).getValueType() != MVT::i8)) {
9000 SDValue LHS = Cond.getOperand(0);
9001 SDValue RHS = Cond.getOperand(1);
9005 switch (CondOpcode) {
9006 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
9007 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
9008 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
9009 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
9010 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
9011 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
9012 default: llvm_unreachable("unexpected overflowing operator");
9015 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
9016 if (CondOpcode == ISD::UMULO)
9017 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
9020 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
9022 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
9024 if (CondOpcode == ISD::UMULO)
9025 Cond = X86Op.getValue(2);
9027 Cond = X86Op.getValue(1);
9029 CC = DAG.getConstant(X86Cond, MVT::i8);
9033 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
9034 SDValue Cmp = Cond.getOperand(0).getOperand(1);
9035 if (CondOpc == ISD::OR) {
9036 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
9037 // two branches instead of an explicit OR instruction with a
9039 if (Cmp == Cond.getOperand(1).getOperand(1) &&
9040 isX86LogicalCmp(Cmp)) {
9041 CC = Cond.getOperand(0).getOperand(0);
9042 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
9043 Chain, Dest, CC, Cmp);
9044 CC = Cond.getOperand(1).getOperand(0);
9048 } else { // ISD::AND
9049 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
9050 // two branches instead of an explicit AND instruction with a
9051 // separate test. However, we only do this if this block doesn't
9052 // have a fall-through edge, because this requires an explicit
9053 // jmp when the condition is false.
9054 if (Cmp == Cond.getOperand(1).getOperand(1) &&
9055 isX86LogicalCmp(Cmp) &&
9056 Op.getNode()->hasOneUse()) {
9057 X86::CondCode CCode =
9058 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
9059 CCode = X86::GetOppositeBranchCondition(CCode);
9060 CC = DAG.getConstant(CCode, MVT::i8);
9061 SDNode *User = *Op.getNode()->use_begin();
9062 // Look for an unconditional branch following this conditional branch.
9063 // We need this because we need to reverse the successors in order
9064 // to implement FCMP_OEQ.
9065 if (User->getOpcode() == ISD::BR) {
9066 SDValue FalseBB = User->getOperand(1);
9068 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
9069 assert(NewBR == User);
9073 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
9074 Chain, Dest, CC, Cmp);
9075 X86::CondCode CCode =
9076 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
9077 CCode = X86::GetOppositeBranchCondition(CCode);
9078 CC = DAG.getConstant(CCode, MVT::i8);
9084 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
9085 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
9086 // It should be transformed during dag combiner except when the condition
9087 // is set by a arithmetics with overflow node.
9088 X86::CondCode CCode =
9089 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
9090 CCode = X86::GetOppositeBranchCondition(CCode);
9091 CC = DAG.getConstant(CCode, MVT::i8);
9092 Cond = Cond.getOperand(0).getOperand(1);
9094 } else if (Cond.getOpcode() == ISD::SETCC &&
9095 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
9096 // For FCMP_OEQ, we can emit
9097 // two branches instead of an explicit AND instruction with a
9098 // separate test. However, we only do this if this block doesn't
9099 // have a fall-through edge, because this requires an explicit
9100 // jmp when the condition is false.
9101 if (Op.getNode()->hasOneUse()) {
9102 SDNode *User = *Op.getNode()->use_begin();
9103 // Look for an unconditional branch following this conditional branch.
9104 // We need this because we need to reverse the successors in order
9105 // to implement FCMP_OEQ.
9106 if (User->getOpcode() == ISD::BR) {
9107 SDValue FalseBB = User->getOperand(1);
9109 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
9110 assert(NewBR == User);
9114 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
9115 Cond.getOperand(0), Cond.getOperand(1));
9116 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
9117 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
9118 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
9119 Chain, Dest, CC, Cmp);
9120 CC = DAG.getConstant(X86::COND_P, MVT::i8);
9125 } else if (Cond.getOpcode() == ISD::SETCC &&
9126 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
9127 // For FCMP_UNE, we can emit
9128 // two branches instead of an explicit AND instruction with a
9129 // separate test. However, we only do this if this block doesn't
9130 // have a fall-through edge, because this requires an explicit
9131 // jmp when the condition is false.
9132 if (Op.getNode()->hasOneUse()) {
9133 SDNode *User = *Op.getNode()->use_begin();
9134 // Look for an unconditional branch following this conditional branch.
9135 // We need this because we need to reverse the successors in order
9136 // to implement FCMP_UNE.
9137 if (User->getOpcode() == ISD::BR) {
9138 SDValue FalseBB = User->getOperand(1);
9140 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
9141 assert(NewBR == User);
9144 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
9145 Cond.getOperand(0), Cond.getOperand(1));
9146 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
9147 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
9148 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
9149 Chain, Dest, CC, Cmp);
9150 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
9160 // Look pass the truncate.
9161 if (Cond.getOpcode() == ISD::TRUNCATE)
9162 Cond = Cond.getOperand(0);
9164 // We know the result of AND is compared against zero. Try to match
9166 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
9167 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
9168 if (NewSetCC.getNode()) {
9169 CC = NewSetCC.getOperand(0);
9170 Cond = NewSetCC.getOperand(1);
9177 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
9178 Cond = EmitTest(Cond, X86::COND_NE, DAG);
9180 Cond = ConvertCmpIfNecessary(Cond, DAG);
9181 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
9182 Chain, Dest, CC, Cond);
9186 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
9187 // Calls to _alloca is needed to probe the stack when allocating more than 4k
9188 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
9189 // that the guard pages used by the OS virtual memory manager are allocated in
9190 // correct sequence.
9192 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
9193 SelectionDAG &DAG) const {
9194 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() ||
9195 getTargetMachine().Options.EnableSegmentedStacks) &&
9196 "This should be used only on Windows targets or when segmented stacks "
9198 assert(!Subtarget->isTargetEnvMacho() && "Not implemented");
9199 DebugLoc dl = Op.getDebugLoc();
9202 SDValue Chain = Op.getOperand(0);
9203 SDValue Size = Op.getOperand(1);
9204 // FIXME: Ensure alignment here
9206 bool Is64Bit = Subtarget->is64Bit();
9207 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32;
9209 if (getTargetMachine().Options.EnableSegmentedStacks) {
9210 MachineFunction &MF = DAG.getMachineFunction();
9211 MachineRegisterInfo &MRI = MF.getRegInfo();
9214 // The 64 bit implementation of segmented stacks needs to clobber both r10
9215 // r11. This makes it impossible to use it along with nested parameters.
9216 const Function *F = MF.getFunction();
9218 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
9220 if (I->hasNestAttr())
9221 report_fatal_error("Cannot use segmented stacks with functions that "
9222 "have nested arguments.");
9225 const TargetRegisterClass *AddrRegClass =
9226 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
9227 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
9228 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
9229 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
9230 DAG.getRegister(Vreg, SPTy));
9231 SDValue Ops1[2] = { Value, Chain };
9232 return DAG.getMergeValues(Ops1, 2, dl);
9235 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
9237 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
9238 Flag = Chain.getValue(1);
9239 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
9241 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
9242 Flag = Chain.getValue(1);
9244 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
9246 SDValue Ops1[2] = { Chain.getValue(0), Chain };
9247 return DAG.getMergeValues(Ops1, 2, dl);
9251 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
9252 MachineFunction &MF = DAG.getMachineFunction();
9253 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
9255 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
9256 DebugLoc DL = Op.getDebugLoc();
9258 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
9259 // vastart just stores the address of the VarArgsFrameIndex slot into the
9260 // memory location argument.
9261 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
9263 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
9264 MachinePointerInfo(SV), false, false, 0);
9268 // gp_offset (0 - 6 * 8)
9269 // fp_offset (48 - 48 + 8 * 16)
9270 // overflow_arg_area (point to parameters coming in memory).
9272 SmallVector<SDValue, 8> MemOps;
9273 SDValue FIN = Op.getOperand(1);
9275 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
9276 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
9278 FIN, MachinePointerInfo(SV), false, false, 0);
9279 MemOps.push_back(Store);
9282 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9283 FIN, DAG.getIntPtrConstant(4));
9284 Store = DAG.getStore(Op.getOperand(0), DL,
9285 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
9287 FIN, MachinePointerInfo(SV, 4), false, false, 0);
9288 MemOps.push_back(Store);
9290 // Store ptr to overflow_arg_area
9291 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9292 FIN, DAG.getIntPtrConstant(4));
9293 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
9295 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
9296 MachinePointerInfo(SV, 8),
9298 MemOps.push_back(Store);
9300 // Store ptr to reg_save_area.
9301 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9302 FIN, DAG.getIntPtrConstant(8));
9303 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
9305 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
9306 MachinePointerInfo(SV, 16), false, false, 0);
9307 MemOps.push_back(Store);
9308 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
9309 &MemOps[0], MemOps.size());
9312 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
9313 assert(Subtarget->is64Bit() &&
9314 "LowerVAARG only handles 64-bit va_arg!");
9315 assert((Subtarget->isTargetLinux() ||
9316 Subtarget->isTargetDarwin()) &&
9317 "Unhandled target in LowerVAARG");
9318 assert(Op.getNode()->getNumOperands() == 4);
9319 SDValue Chain = Op.getOperand(0);
9320 SDValue SrcPtr = Op.getOperand(1);
9321 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
9322 unsigned Align = Op.getConstantOperandVal(3);
9323 DebugLoc dl = Op.getDebugLoc();
9325 EVT ArgVT = Op.getNode()->getValueType(0);
9326 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
9327 uint32_t ArgSize = getTargetData()->getTypeAllocSize(ArgTy);
9330 // Decide which area this value should be read from.
9331 // TODO: Implement the AMD64 ABI in its entirety. This simple
9332 // selection mechanism works only for the basic types.
9333 if (ArgVT == MVT::f80) {
9334 llvm_unreachable("va_arg for f80 not yet implemented");
9335 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
9336 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
9337 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
9338 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
9340 llvm_unreachable("Unhandled argument type in LowerVAARG");
9344 // Sanity Check: Make sure using fp_offset makes sense.
9345 assert(!getTargetMachine().Options.UseSoftFloat &&
9346 !(DAG.getMachineFunction()
9347 .getFunction()->hasFnAttr(Attribute::NoImplicitFloat)) &&
9348 Subtarget->hasSSE1());
9351 // Insert VAARG_64 node into the DAG
9352 // VAARG_64 returns two values: Variable Argument Address, Chain
9353 SmallVector<SDValue, 11> InstOps;
9354 InstOps.push_back(Chain);
9355 InstOps.push_back(SrcPtr);
9356 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
9357 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
9358 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
9359 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
9360 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
9361 VTs, &InstOps[0], InstOps.size(),
9363 MachinePointerInfo(SV),
9368 Chain = VAARG.getValue(1);
9370 // Load the next argument and return it
9371 return DAG.getLoad(ArgVT, dl,
9374 MachinePointerInfo(),
9375 false, false, false, 0);
9378 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
9379 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
9380 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
9381 SDValue Chain = Op.getOperand(0);
9382 SDValue DstPtr = Op.getOperand(1);
9383 SDValue SrcPtr = Op.getOperand(2);
9384 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
9385 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
9386 DebugLoc DL = Op.getDebugLoc();
9388 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
9389 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
9391 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
9394 // getTargetVShiftNOde - Handle vector element shifts where the shift amount
9395 // may or may not be a constant. Takes immediate version of shift as input.
9396 static SDValue getTargetVShiftNode(unsigned Opc, DebugLoc dl, EVT VT,
9397 SDValue SrcOp, SDValue ShAmt,
9398 SelectionDAG &DAG) {
9399 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
9401 if (isa<ConstantSDNode>(ShAmt)) {
9403 default: llvm_unreachable("Unknown target vector shift node");
9407 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
9411 // Change opcode to non-immediate version
9413 default: llvm_unreachable("Unknown target vector shift node");
9414 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
9415 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
9416 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
9419 // Need to build a vector containing shift amount
9420 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
9423 ShOps[1] = DAG.getConstant(0, MVT::i32);
9424 ShOps[2] = DAG.getUNDEF(MVT::i32);
9425 ShOps[3] = DAG.getUNDEF(MVT::i32);
9426 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &ShOps[0], 4);
9427 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt);
9428 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
9432 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const {
9433 DebugLoc dl = Op.getDebugLoc();
9434 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9436 default: return SDValue(); // Don't custom lower most intrinsics.
9437 // Comparison intrinsics.
9438 case Intrinsic::x86_sse_comieq_ss:
9439 case Intrinsic::x86_sse_comilt_ss:
9440 case Intrinsic::x86_sse_comile_ss:
9441 case Intrinsic::x86_sse_comigt_ss:
9442 case Intrinsic::x86_sse_comige_ss:
9443 case Intrinsic::x86_sse_comineq_ss:
9444 case Intrinsic::x86_sse_ucomieq_ss:
9445 case Intrinsic::x86_sse_ucomilt_ss:
9446 case Intrinsic::x86_sse_ucomile_ss:
9447 case Intrinsic::x86_sse_ucomigt_ss:
9448 case Intrinsic::x86_sse_ucomige_ss:
9449 case Intrinsic::x86_sse_ucomineq_ss:
9450 case Intrinsic::x86_sse2_comieq_sd:
9451 case Intrinsic::x86_sse2_comilt_sd:
9452 case Intrinsic::x86_sse2_comile_sd:
9453 case Intrinsic::x86_sse2_comigt_sd:
9454 case Intrinsic::x86_sse2_comige_sd:
9455 case Intrinsic::x86_sse2_comineq_sd:
9456 case Intrinsic::x86_sse2_ucomieq_sd:
9457 case Intrinsic::x86_sse2_ucomilt_sd:
9458 case Intrinsic::x86_sse2_ucomile_sd:
9459 case Intrinsic::x86_sse2_ucomigt_sd:
9460 case Intrinsic::x86_sse2_ucomige_sd:
9461 case Intrinsic::x86_sse2_ucomineq_sd: {
9463 ISD::CondCode CC = ISD::SETCC_INVALID;
9465 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9466 case Intrinsic::x86_sse_comieq_ss:
9467 case Intrinsic::x86_sse2_comieq_sd:
9471 case Intrinsic::x86_sse_comilt_ss:
9472 case Intrinsic::x86_sse2_comilt_sd:
9476 case Intrinsic::x86_sse_comile_ss:
9477 case Intrinsic::x86_sse2_comile_sd:
9481 case Intrinsic::x86_sse_comigt_ss:
9482 case Intrinsic::x86_sse2_comigt_sd:
9486 case Intrinsic::x86_sse_comige_ss:
9487 case Intrinsic::x86_sse2_comige_sd:
9491 case Intrinsic::x86_sse_comineq_ss:
9492 case Intrinsic::x86_sse2_comineq_sd:
9496 case Intrinsic::x86_sse_ucomieq_ss:
9497 case Intrinsic::x86_sse2_ucomieq_sd:
9498 Opc = X86ISD::UCOMI;
9501 case Intrinsic::x86_sse_ucomilt_ss:
9502 case Intrinsic::x86_sse2_ucomilt_sd:
9503 Opc = X86ISD::UCOMI;
9506 case Intrinsic::x86_sse_ucomile_ss:
9507 case Intrinsic::x86_sse2_ucomile_sd:
9508 Opc = X86ISD::UCOMI;
9511 case Intrinsic::x86_sse_ucomigt_ss:
9512 case Intrinsic::x86_sse2_ucomigt_sd:
9513 Opc = X86ISD::UCOMI;
9516 case Intrinsic::x86_sse_ucomige_ss:
9517 case Intrinsic::x86_sse2_ucomige_sd:
9518 Opc = X86ISD::UCOMI;
9521 case Intrinsic::x86_sse_ucomineq_ss:
9522 case Intrinsic::x86_sse2_ucomineq_sd:
9523 Opc = X86ISD::UCOMI;
9528 SDValue LHS = Op.getOperand(1);
9529 SDValue RHS = Op.getOperand(2);
9530 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
9531 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
9532 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
9533 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9534 DAG.getConstant(X86CC, MVT::i8), Cond);
9535 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
9537 // Arithmetic intrinsics.
9538 case Intrinsic::x86_sse2_pmulu_dq:
9539 case Intrinsic::x86_avx2_pmulu_dq:
9540 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
9541 Op.getOperand(1), Op.getOperand(2));
9542 case Intrinsic::x86_sse3_hadd_ps:
9543 case Intrinsic::x86_sse3_hadd_pd:
9544 case Intrinsic::x86_avx_hadd_ps_256:
9545 case Intrinsic::x86_avx_hadd_pd_256:
9546 return DAG.getNode(X86ISD::FHADD, dl, Op.getValueType(),
9547 Op.getOperand(1), Op.getOperand(2));
9548 case Intrinsic::x86_sse3_hsub_ps:
9549 case Intrinsic::x86_sse3_hsub_pd:
9550 case Intrinsic::x86_avx_hsub_ps_256:
9551 case Intrinsic::x86_avx_hsub_pd_256:
9552 return DAG.getNode(X86ISD::FHSUB, dl, Op.getValueType(),
9553 Op.getOperand(1), Op.getOperand(2));
9554 case Intrinsic::x86_ssse3_phadd_w_128:
9555 case Intrinsic::x86_ssse3_phadd_d_128:
9556 case Intrinsic::x86_avx2_phadd_w:
9557 case Intrinsic::x86_avx2_phadd_d:
9558 return DAG.getNode(X86ISD::HADD, dl, Op.getValueType(),
9559 Op.getOperand(1), Op.getOperand(2));
9560 case Intrinsic::x86_ssse3_phsub_w_128:
9561 case Intrinsic::x86_ssse3_phsub_d_128:
9562 case Intrinsic::x86_avx2_phsub_w:
9563 case Intrinsic::x86_avx2_phsub_d:
9564 return DAG.getNode(X86ISD::HSUB, dl, Op.getValueType(),
9565 Op.getOperand(1), Op.getOperand(2));
9566 case Intrinsic::x86_avx2_psllv_d:
9567 case Intrinsic::x86_avx2_psllv_q:
9568 case Intrinsic::x86_avx2_psllv_d_256:
9569 case Intrinsic::x86_avx2_psllv_q_256:
9570 return DAG.getNode(ISD::SHL, dl, Op.getValueType(),
9571 Op.getOperand(1), Op.getOperand(2));
9572 case Intrinsic::x86_avx2_psrlv_d:
9573 case Intrinsic::x86_avx2_psrlv_q:
9574 case Intrinsic::x86_avx2_psrlv_d_256:
9575 case Intrinsic::x86_avx2_psrlv_q_256:
9576 return DAG.getNode(ISD::SRL, dl, Op.getValueType(),
9577 Op.getOperand(1), Op.getOperand(2));
9578 case Intrinsic::x86_avx2_psrav_d:
9579 case Intrinsic::x86_avx2_psrav_d_256:
9580 return DAG.getNode(ISD::SRA, dl, Op.getValueType(),
9581 Op.getOperand(1), Op.getOperand(2));
9582 case Intrinsic::x86_ssse3_pshuf_b_128:
9583 case Intrinsic::x86_avx2_pshuf_b:
9584 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
9585 Op.getOperand(1), Op.getOperand(2));
9586 case Intrinsic::x86_ssse3_psign_b_128:
9587 case Intrinsic::x86_ssse3_psign_w_128:
9588 case Intrinsic::x86_ssse3_psign_d_128:
9589 case Intrinsic::x86_avx2_psign_b:
9590 case Intrinsic::x86_avx2_psign_w:
9591 case Intrinsic::x86_avx2_psign_d:
9592 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
9593 Op.getOperand(1), Op.getOperand(2));
9594 case Intrinsic::x86_sse41_insertps:
9595 return DAG.getNode(X86ISD::INSERTPS, dl, Op.getValueType(),
9596 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
9597 case Intrinsic::x86_avx_vperm2f128_ps_256:
9598 case Intrinsic::x86_avx_vperm2f128_pd_256:
9599 case Intrinsic::x86_avx_vperm2f128_si_256:
9600 case Intrinsic::x86_avx2_vperm2i128:
9601 return DAG.getNode(X86ISD::VPERM2X128, dl, Op.getValueType(),
9602 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
9603 case Intrinsic::x86_avx2_permd:
9604 case Intrinsic::x86_avx2_permps:
9605 // Operands intentionally swapped. Mask is last operand to intrinsic,
9606 // but second operand for node/intruction.
9607 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
9608 Op.getOperand(2), Op.getOperand(1));
9610 // ptest and testp intrinsics. The intrinsic these come from are designed to
9611 // return an integer value, not just an instruction so lower it to the ptest
9612 // or testp pattern and a setcc for the result.
9613 case Intrinsic::x86_sse41_ptestz:
9614 case Intrinsic::x86_sse41_ptestc:
9615 case Intrinsic::x86_sse41_ptestnzc:
9616 case Intrinsic::x86_avx_ptestz_256:
9617 case Intrinsic::x86_avx_ptestc_256:
9618 case Intrinsic::x86_avx_ptestnzc_256:
9619 case Intrinsic::x86_avx_vtestz_ps:
9620 case Intrinsic::x86_avx_vtestc_ps:
9621 case Intrinsic::x86_avx_vtestnzc_ps:
9622 case Intrinsic::x86_avx_vtestz_pd:
9623 case Intrinsic::x86_avx_vtestc_pd:
9624 case Intrinsic::x86_avx_vtestnzc_pd:
9625 case Intrinsic::x86_avx_vtestz_ps_256:
9626 case Intrinsic::x86_avx_vtestc_ps_256:
9627 case Intrinsic::x86_avx_vtestnzc_ps_256:
9628 case Intrinsic::x86_avx_vtestz_pd_256:
9629 case Intrinsic::x86_avx_vtestc_pd_256:
9630 case Intrinsic::x86_avx_vtestnzc_pd_256: {
9631 bool IsTestPacked = false;
9634 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
9635 case Intrinsic::x86_avx_vtestz_ps:
9636 case Intrinsic::x86_avx_vtestz_pd:
9637 case Intrinsic::x86_avx_vtestz_ps_256:
9638 case Intrinsic::x86_avx_vtestz_pd_256:
9639 IsTestPacked = true; // Fallthrough
9640 case Intrinsic::x86_sse41_ptestz:
9641 case Intrinsic::x86_avx_ptestz_256:
9643 X86CC = X86::COND_E;
9645 case Intrinsic::x86_avx_vtestc_ps:
9646 case Intrinsic::x86_avx_vtestc_pd:
9647 case Intrinsic::x86_avx_vtestc_ps_256:
9648 case Intrinsic::x86_avx_vtestc_pd_256:
9649 IsTestPacked = true; // Fallthrough
9650 case Intrinsic::x86_sse41_ptestc:
9651 case Intrinsic::x86_avx_ptestc_256:
9653 X86CC = X86::COND_B;
9655 case Intrinsic::x86_avx_vtestnzc_ps:
9656 case Intrinsic::x86_avx_vtestnzc_pd:
9657 case Intrinsic::x86_avx_vtestnzc_ps_256:
9658 case Intrinsic::x86_avx_vtestnzc_pd_256:
9659 IsTestPacked = true; // Fallthrough
9660 case Intrinsic::x86_sse41_ptestnzc:
9661 case Intrinsic::x86_avx_ptestnzc_256:
9663 X86CC = X86::COND_A;
9667 SDValue LHS = Op.getOperand(1);
9668 SDValue RHS = Op.getOperand(2);
9669 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
9670 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
9671 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
9672 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
9673 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
9676 // SSE/AVX shift intrinsics
9677 case Intrinsic::x86_sse2_psll_w:
9678 case Intrinsic::x86_sse2_psll_d:
9679 case Intrinsic::x86_sse2_psll_q:
9680 case Intrinsic::x86_avx2_psll_w:
9681 case Intrinsic::x86_avx2_psll_d:
9682 case Intrinsic::x86_avx2_psll_q:
9683 return DAG.getNode(X86ISD::VSHL, dl, Op.getValueType(),
9684 Op.getOperand(1), Op.getOperand(2));
9685 case Intrinsic::x86_sse2_psrl_w:
9686 case Intrinsic::x86_sse2_psrl_d:
9687 case Intrinsic::x86_sse2_psrl_q:
9688 case Intrinsic::x86_avx2_psrl_w:
9689 case Intrinsic::x86_avx2_psrl_d:
9690 case Intrinsic::x86_avx2_psrl_q:
9691 return DAG.getNode(X86ISD::VSRL, dl, Op.getValueType(),
9692 Op.getOperand(1), Op.getOperand(2));
9693 case Intrinsic::x86_sse2_psra_w:
9694 case Intrinsic::x86_sse2_psra_d:
9695 case Intrinsic::x86_avx2_psra_w:
9696 case Intrinsic::x86_avx2_psra_d:
9697 return DAG.getNode(X86ISD::VSRA, dl, Op.getValueType(),
9698 Op.getOperand(1), Op.getOperand(2));
9699 case Intrinsic::x86_sse2_pslli_w:
9700 case Intrinsic::x86_sse2_pslli_d:
9701 case Intrinsic::x86_sse2_pslli_q:
9702 case Intrinsic::x86_avx2_pslli_w:
9703 case Intrinsic::x86_avx2_pslli_d:
9704 case Intrinsic::x86_avx2_pslli_q:
9705 return getTargetVShiftNode(X86ISD::VSHLI, dl, Op.getValueType(),
9706 Op.getOperand(1), Op.getOperand(2), DAG);
9707 case Intrinsic::x86_sse2_psrli_w:
9708 case Intrinsic::x86_sse2_psrli_d:
9709 case Intrinsic::x86_sse2_psrli_q:
9710 case Intrinsic::x86_avx2_psrli_w:
9711 case Intrinsic::x86_avx2_psrli_d:
9712 case Intrinsic::x86_avx2_psrli_q:
9713 return getTargetVShiftNode(X86ISD::VSRLI, dl, Op.getValueType(),
9714 Op.getOperand(1), Op.getOperand(2), DAG);
9715 case Intrinsic::x86_sse2_psrai_w:
9716 case Intrinsic::x86_sse2_psrai_d:
9717 case Intrinsic::x86_avx2_psrai_w:
9718 case Intrinsic::x86_avx2_psrai_d:
9719 return getTargetVShiftNode(X86ISD::VSRAI, dl, Op.getValueType(),
9720 Op.getOperand(1), Op.getOperand(2), DAG);
9721 // Fix vector shift instructions where the last operand is a non-immediate
9723 case Intrinsic::x86_mmx_pslli_w:
9724 case Intrinsic::x86_mmx_pslli_d:
9725 case Intrinsic::x86_mmx_pslli_q:
9726 case Intrinsic::x86_mmx_psrli_w:
9727 case Intrinsic::x86_mmx_psrli_d:
9728 case Intrinsic::x86_mmx_psrli_q:
9729 case Intrinsic::x86_mmx_psrai_w:
9730 case Intrinsic::x86_mmx_psrai_d: {
9731 SDValue ShAmt = Op.getOperand(2);
9732 if (isa<ConstantSDNode>(ShAmt))
9735 unsigned NewIntNo = 0;
9737 case Intrinsic::x86_mmx_pslli_w:
9738 NewIntNo = Intrinsic::x86_mmx_psll_w;
9740 case Intrinsic::x86_mmx_pslli_d:
9741 NewIntNo = Intrinsic::x86_mmx_psll_d;
9743 case Intrinsic::x86_mmx_pslli_q:
9744 NewIntNo = Intrinsic::x86_mmx_psll_q;
9746 case Intrinsic::x86_mmx_psrli_w:
9747 NewIntNo = Intrinsic::x86_mmx_psrl_w;
9749 case Intrinsic::x86_mmx_psrli_d:
9750 NewIntNo = Intrinsic::x86_mmx_psrl_d;
9752 case Intrinsic::x86_mmx_psrli_q:
9753 NewIntNo = Intrinsic::x86_mmx_psrl_q;
9755 case Intrinsic::x86_mmx_psrai_w:
9756 NewIntNo = Intrinsic::x86_mmx_psra_w;
9758 case Intrinsic::x86_mmx_psrai_d:
9759 NewIntNo = Intrinsic::x86_mmx_psra_d;
9761 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9764 // The vector shift intrinsics with scalars uses 32b shift amounts but
9765 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
9767 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, ShAmt,
9768 DAG.getConstant(0, MVT::i32));
9769 // FIXME this must be lowered to get rid of the invalid type.
9771 EVT VT = Op.getValueType();
9772 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt);
9773 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9774 DAG.getConstant(NewIntNo, MVT::i32),
9775 Op.getOperand(1), ShAmt);
9780 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
9781 SelectionDAG &DAG) const {
9782 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9783 MFI->setReturnAddressIsTaken(true);
9785 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9786 DebugLoc dl = Op.getDebugLoc();
9789 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
9791 DAG.getConstant(TD->getPointerSize(),
9792 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
9793 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9794 DAG.getNode(ISD::ADD, dl, getPointerTy(),
9796 MachinePointerInfo(), false, false, false, 0);
9799 // Just load the return address.
9800 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
9801 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9802 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
9805 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
9806 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9807 MFI->setFrameAddressIsTaken(true);
9809 EVT VT = Op.getValueType();
9810 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
9811 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9812 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
9813 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
9815 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
9816 MachinePointerInfo(),
9817 false, false, false, 0);
9821 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
9822 SelectionDAG &DAG) const {
9823 return DAG.getIntPtrConstant(2*TD->getPointerSize());
9826 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
9827 MachineFunction &MF = DAG.getMachineFunction();
9828 SDValue Chain = Op.getOperand(0);
9829 SDValue Offset = Op.getOperand(1);
9830 SDValue Handler = Op.getOperand(2);
9831 DebugLoc dl = Op.getDebugLoc();
9833 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
9834 Subtarget->is64Bit() ? X86::RBP : X86::EBP,
9836 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
9838 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame,
9839 DAG.getIntPtrConstant(TD->getPointerSize()));
9840 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
9841 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
9843 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
9844 MF.getRegInfo().addLiveOut(StoreAddrReg);
9846 return DAG.getNode(X86ISD::EH_RETURN, dl,
9848 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
9851 SDValue X86TargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
9852 SelectionDAG &DAG) const {
9853 return Op.getOperand(0);
9856 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
9857 SelectionDAG &DAG) const {
9858 SDValue Root = Op.getOperand(0);
9859 SDValue Trmp = Op.getOperand(1); // trampoline
9860 SDValue FPtr = Op.getOperand(2); // nested function
9861 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
9862 DebugLoc dl = Op.getDebugLoc();
9864 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
9866 if (Subtarget->is64Bit()) {
9867 SDValue OutChains[6];
9869 // Large code-model.
9870 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
9871 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
9873 const unsigned char N86R10 = X86_MC::getX86RegNum(X86::R10);
9874 const unsigned char N86R11 = X86_MC::getX86RegNum(X86::R11);
9876 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
9878 // Load the pointer to the nested function into R11.
9879 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
9880 SDValue Addr = Trmp;
9881 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9882 Addr, MachinePointerInfo(TrmpAddr),
9885 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9886 DAG.getConstant(2, MVT::i64));
9887 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
9888 MachinePointerInfo(TrmpAddr, 2),
9891 // Load the 'nest' parameter value into R10.
9892 // R10 is specified in X86CallingConv.td
9893 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
9894 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9895 DAG.getConstant(10, MVT::i64));
9896 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9897 Addr, MachinePointerInfo(TrmpAddr, 10),
9900 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9901 DAG.getConstant(12, MVT::i64));
9902 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
9903 MachinePointerInfo(TrmpAddr, 12),
9906 // Jump to the nested function.
9907 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
9908 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9909 DAG.getConstant(20, MVT::i64));
9910 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9911 Addr, MachinePointerInfo(TrmpAddr, 20),
9914 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
9915 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9916 DAG.getConstant(22, MVT::i64));
9917 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
9918 MachinePointerInfo(TrmpAddr, 22),
9921 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6);
9923 const Function *Func =
9924 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
9925 CallingConv::ID CC = Func->getCallingConv();
9930 llvm_unreachable("Unsupported calling convention");
9931 case CallingConv::C:
9932 case CallingConv::X86_StdCall: {
9933 // Pass 'nest' parameter in ECX.
9934 // Must be kept in sync with X86CallingConv.td
9937 // Check that ECX wasn't needed by an 'inreg' parameter.
9938 FunctionType *FTy = Func->getFunctionType();
9939 const AttrListPtr &Attrs = Func->getAttributes();
9941 if (!Attrs.isEmpty() && !Func->isVarArg()) {
9942 unsigned InRegCount = 0;
9945 for (FunctionType::param_iterator I = FTy->param_begin(),
9946 E = FTy->param_end(); I != E; ++I, ++Idx)
9947 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
9948 // FIXME: should only count parameters that are lowered to integers.
9949 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
9951 if (InRegCount > 2) {
9952 report_fatal_error("Nest register in use - reduce number of inreg"
9958 case CallingConv::X86_FastCall:
9959 case CallingConv::X86_ThisCall:
9960 case CallingConv::Fast:
9961 // Pass 'nest' parameter in EAX.
9962 // Must be kept in sync with X86CallingConv.td
9967 SDValue OutChains[4];
9970 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9971 DAG.getConstant(10, MVT::i32));
9972 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
9974 // This is storing the opcode for MOV32ri.
9975 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
9976 const unsigned char N86Reg = X86_MC::getX86RegNum(NestReg);
9977 OutChains[0] = DAG.getStore(Root, dl,
9978 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
9979 Trmp, MachinePointerInfo(TrmpAddr),
9982 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9983 DAG.getConstant(1, MVT::i32));
9984 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
9985 MachinePointerInfo(TrmpAddr, 1),
9988 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
9989 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9990 DAG.getConstant(5, MVT::i32));
9991 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
9992 MachinePointerInfo(TrmpAddr, 5),
9995 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9996 DAG.getConstant(6, MVT::i32));
9997 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
9998 MachinePointerInfo(TrmpAddr, 6),
10001 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4);
10005 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
10006 SelectionDAG &DAG) const {
10008 The rounding mode is in bits 11:10 of FPSR, and has the following
10010 00 Round to nearest
10015 FLT_ROUNDS, on the other hand, expects the following:
10022 To perform the conversion, we do:
10023 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
10026 MachineFunction &MF = DAG.getMachineFunction();
10027 const TargetMachine &TM = MF.getTarget();
10028 const TargetFrameLowering &TFI = *TM.getFrameLowering();
10029 unsigned StackAlignment = TFI.getStackAlignment();
10030 EVT VT = Op.getValueType();
10031 DebugLoc DL = Op.getDebugLoc();
10033 // Save FP Control Word to stack slot
10034 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
10035 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
10038 MachineMemOperand *MMO =
10039 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
10040 MachineMemOperand::MOStore, 2, 2);
10042 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
10043 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
10044 DAG.getVTList(MVT::Other),
10045 Ops, 2, MVT::i16, MMO);
10047 // Load FP Control Word from stack slot
10048 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
10049 MachinePointerInfo(), false, false, false, 0);
10051 // Transform as necessary
10053 DAG.getNode(ISD::SRL, DL, MVT::i16,
10054 DAG.getNode(ISD::AND, DL, MVT::i16,
10055 CWD, DAG.getConstant(0x800, MVT::i16)),
10056 DAG.getConstant(11, MVT::i8));
10058 DAG.getNode(ISD::SRL, DL, MVT::i16,
10059 DAG.getNode(ISD::AND, DL, MVT::i16,
10060 CWD, DAG.getConstant(0x400, MVT::i16)),
10061 DAG.getConstant(9, MVT::i8));
10064 DAG.getNode(ISD::AND, DL, MVT::i16,
10065 DAG.getNode(ISD::ADD, DL, MVT::i16,
10066 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
10067 DAG.getConstant(1, MVT::i16)),
10068 DAG.getConstant(3, MVT::i16));
10071 return DAG.getNode((VT.getSizeInBits() < 16 ?
10072 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
10075 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const {
10076 EVT VT = Op.getValueType();
10078 unsigned NumBits = VT.getSizeInBits();
10079 DebugLoc dl = Op.getDebugLoc();
10081 Op = Op.getOperand(0);
10082 if (VT == MVT::i8) {
10083 // Zero extend to i32 since there is not an i8 bsr.
10085 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
10088 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
10089 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
10090 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
10092 // If src is zero (i.e. bsr sets ZF), returns NumBits.
10095 DAG.getConstant(NumBits+NumBits-1, OpVT),
10096 DAG.getConstant(X86::COND_E, MVT::i8),
10099 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
10101 // Finally xor with NumBits-1.
10102 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
10105 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
10109 SDValue X86TargetLowering::LowerCTLZ_ZERO_UNDEF(SDValue Op,
10110 SelectionDAG &DAG) const {
10111 EVT VT = Op.getValueType();
10113 unsigned NumBits = VT.getSizeInBits();
10114 DebugLoc dl = Op.getDebugLoc();
10116 Op = Op.getOperand(0);
10117 if (VT == MVT::i8) {
10118 // Zero extend to i32 since there is not an i8 bsr.
10120 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
10123 // Issue a bsr (scan bits in reverse).
10124 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
10125 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
10127 // And xor with NumBits-1.
10128 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
10131 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
10135 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const {
10136 EVT VT = Op.getValueType();
10137 unsigned NumBits = VT.getSizeInBits();
10138 DebugLoc dl = Op.getDebugLoc();
10139 Op = Op.getOperand(0);
10141 // Issue a bsf (scan bits forward) which also sets EFLAGS.
10142 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
10143 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
10145 // If src is zero (i.e. bsf sets ZF), returns NumBits.
10148 DAG.getConstant(NumBits, VT),
10149 DAG.getConstant(X86::COND_E, MVT::i8),
10152 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops, array_lengthof(Ops));
10155 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
10156 // ones, and then concatenate the result back.
10157 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
10158 EVT VT = Op.getValueType();
10160 assert(VT.getSizeInBits() == 256 && VT.isInteger() &&
10161 "Unsupported value type for operation");
10163 unsigned NumElems = VT.getVectorNumElements();
10164 DebugLoc dl = Op.getDebugLoc();
10166 // Extract the LHS vectors
10167 SDValue LHS = Op.getOperand(0);
10168 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
10169 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
10171 // Extract the RHS vectors
10172 SDValue RHS = Op.getOperand(1);
10173 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
10174 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
10176 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10177 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10179 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
10180 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
10181 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
10184 SDValue X86TargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) const {
10185 assert(Op.getValueType().getSizeInBits() == 256 &&
10186 Op.getValueType().isInteger() &&
10187 "Only handle AVX 256-bit vector integer operation");
10188 return Lower256IntArith(Op, DAG);
10191 SDValue X86TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) const {
10192 assert(Op.getValueType().getSizeInBits() == 256 &&
10193 Op.getValueType().isInteger() &&
10194 "Only handle AVX 256-bit vector integer operation");
10195 return Lower256IntArith(Op, DAG);
10198 SDValue X86TargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
10199 EVT VT = Op.getValueType();
10201 // Decompose 256-bit ops into smaller 128-bit ops.
10202 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2())
10203 return Lower256IntArith(Op, DAG);
10205 assert((VT == MVT::v2i64 || VT == MVT::v4i64) &&
10206 "Only know how to lower V2I64/V4I64 multiply");
10208 DebugLoc dl = Op.getDebugLoc();
10210 // Ahi = psrlqi(a, 32);
10211 // Bhi = psrlqi(b, 32);
10213 // AloBlo = pmuludq(a, b);
10214 // AloBhi = pmuludq(a, Bhi);
10215 // AhiBlo = pmuludq(Ahi, b);
10217 // AloBhi = psllqi(AloBhi, 32);
10218 // AhiBlo = psllqi(AhiBlo, 32);
10219 // return AloBlo + AloBhi + AhiBlo;
10221 SDValue A = Op.getOperand(0);
10222 SDValue B = Op.getOperand(1);
10224 SDValue ShAmt = DAG.getConstant(32, MVT::i32);
10226 SDValue Ahi = DAG.getNode(X86ISD::VSRLI, dl, VT, A, ShAmt);
10227 SDValue Bhi = DAG.getNode(X86ISD::VSRLI, dl, VT, B, ShAmt);
10229 // Bit cast to 32-bit vectors for MULUDQ
10230 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 : MVT::v8i32;
10231 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
10232 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
10233 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
10234 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
10236 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
10237 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
10238 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
10240 AloBhi = DAG.getNode(X86ISD::VSHLI, dl, VT, AloBhi, ShAmt);
10241 AhiBlo = DAG.getNode(X86ISD::VSHLI, dl, VT, AhiBlo, ShAmt);
10243 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
10244 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
10247 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
10249 EVT VT = Op.getValueType();
10250 DebugLoc dl = Op.getDebugLoc();
10251 SDValue R = Op.getOperand(0);
10252 SDValue Amt = Op.getOperand(1);
10253 LLVMContext *Context = DAG.getContext();
10255 if (!Subtarget->hasSSE2())
10258 // Optimize shl/srl/sra with constant shift amount.
10259 if (isSplatVector(Amt.getNode())) {
10260 SDValue SclrAmt = Amt->getOperand(0);
10261 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
10262 uint64_t ShiftAmt = C->getZExtValue();
10264 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
10265 (Subtarget->hasAVX2() &&
10266 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16))) {
10267 if (Op.getOpcode() == ISD::SHL)
10268 return DAG.getNode(X86ISD::VSHLI, dl, VT, R,
10269 DAG.getConstant(ShiftAmt, MVT::i32));
10270 if (Op.getOpcode() == ISD::SRL)
10271 return DAG.getNode(X86ISD::VSRLI, dl, VT, R,
10272 DAG.getConstant(ShiftAmt, MVT::i32));
10273 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
10274 return DAG.getNode(X86ISD::VSRAI, dl, VT, R,
10275 DAG.getConstant(ShiftAmt, MVT::i32));
10278 if (VT == MVT::v16i8) {
10279 if (Op.getOpcode() == ISD::SHL) {
10280 // Make a large shift.
10281 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, R,
10282 DAG.getConstant(ShiftAmt, MVT::i32));
10283 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
10284 // Zero out the rightmost bits.
10285 SmallVector<SDValue, 16> V(16,
10286 DAG.getConstant(uint8_t(-1U << ShiftAmt),
10288 return DAG.getNode(ISD::AND, dl, VT, SHL,
10289 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
10291 if (Op.getOpcode() == ISD::SRL) {
10292 // Make a large shift.
10293 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v8i16, R,
10294 DAG.getConstant(ShiftAmt, MVT::i32));
10295 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
10296 // Zero out the leftmost bits.
10297 SmallVector<SDValue, 16> V(16,
10298 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
10300 return DAG.getNode(ISD::AND, dl, VT, SRL,
10301 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
10303 if (Op.getOpcode() == ISD::SRA) {
10304 if (ShiftAmt == 7) {
10305 // R s>> 7 === R s< 0
10306 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
10307 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
10310 // R s>> a === ((R u>> a) ^ m) - m
10311 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
10312 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
10314 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16);
10315 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
10316 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
10319 llvm_unreachable("Unknown shift opcode.");
10322 if (Subtarget->hasAVX2() && VT == MVT::v32i8) {
10323 if (Op.getOpcode() == ISD::SHL) {
10324 // Make a large shift.
10325 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v16i16, R,
10326 DAG.getConstant(ShiftAmt, MVT::i32));
10327 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
10328 // Zero out the rightmost bits.
10329 SmallVector<SDValue, 32> V(32,
10330 DAG.getConstant(uint8_t(-1U << ShiftAmt),
10332 return DAG.getNode(ISD::AND, dl, VT, SHL,
10333 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
10335 if (Op.getOpcode() == ISD::SRL) {
10336 // Make a large shift.
10337 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v16i16, R,
10338 DAG.getConstant(ShiftAmt, MVT::i32));
10339 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
10340 // Zero out the leftmost bits.
10341 SmallVector<SDValue, 32> V(32,
10342 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
10344 return DAG.getNode(ISD::AND, dl, VT, SRL,
10345 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
10347 if (Op.getOpcode() == ISD::SRA) {
10348 if (ShiftAmt == 7) {
10349 // R s>> 7 === R s< 0
10350 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
10351 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
10354 // R s>> a === ((R u>> a) ^ m) - m
10355 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
10356 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
10358 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32);
10359 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
10360 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
10363 llvm_unreachable("Unknown shift opcode.");
10368 // Lower SHL with variable shift amount.
10369 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
10370 Op = DAG.getNode(X86ISD::VSHLI, dl, VT, Op.getOperand(1),
10371 DAG.getConstant(23, MVT::i32));
10373 const uint32_t CV[] = { 0x3f800000U, 0x3f800000U, 0x3f800000U, 0x3f800000U};
10374 Constant *C = ConstantDataVector::get(*Context, CV);
10375 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
10376 SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
10377 MachinePointerInfo::getConstantPool(),
10378 false, false, false, 16);
10380 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend);
10381 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
10382 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
10383 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
10385 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
10386 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
10389 Op = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, Op.getOperand(1),
10390 DAG.getConstant(5, MVT::i32));
10391 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
10393 // Turn 'a' into a mask suitable for VSELECT
10394 SDValue VSelM = DAG.getConstant(0x80, VT);
10395 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10396 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
10398 SDValue CM1 = DAG.getConstant(0x0f, VT);
10399 SDValue CM2 = DAG.getConstant(0x3f, VT);
10401 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
10402 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
10403 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M,
10404 DAG.getConstant(4, MVT::i32), DAG);
10405 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
10406 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
10409 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
10410 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10411 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
10413 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
10414 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
10415 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M,
10416 DAG.getConstant(2, MVT::i32), DAG);
10417 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
10418 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
10421 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
10422 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10423 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
10425 // return VSELECT(r, r+r, a);
10426 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
10427 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
10431 // Decompose 256-bit shifts into smaller 128-bit shifts.
10432 if (VT.getSizeInBits() == 256) {
10433 unsigned NumElems = VT.getVectorNumElements();
10434 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10435 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10437 // Extract the two vectors
10438 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
10439 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
10441 // Recreate the shift amount vectors
10442 SDValue Amt1, Amt2;
10443 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
10444 // Constant shift amount
10445 SmallVector<SDValue, 4> Amt1Csts;
10446 SmallVector<SDValue, 4> Amt2Csts;
10447 for (unsigned i = 0; i != NumElems/2; ++i)
10448 Amt1Csts.push_back(Amt->getOperand(i));
10449 for (unsigned i = NumElems/2; i != NumElems; ++i)
10450 Amt2Csts.push_back(Amt->getOperand(i));
10452 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
10453 &Amt1Csts[0], NumElems/2);
10454 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
10455 &Amt2Csts[0], NumElems/2);
10457 // Variable shift amount
10458 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
10459 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
10462 // Issue new vector shifts for the smaller types
10463 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
10464 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
10466 // Concatenate the result back
10467 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
10473 SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {
10474 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
10475 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
10476 // looks for this combo and may remove the "setcc" instruction if the "setcc"
10477 // has only one use.
10478 SDNode *N = Op.getNode();
10479 SDValue LHS = N->getOperand(0);
10480 SDValue RHS = N->getOperand(1);
10481 unsigned BaseOp = 0;
10483 DebugLoc DL = Op.getDebugLoc();
10484 switch (Op.getOpcode()) {
10485 default: llvm_unreachable("Unknown ovf instruction!");
10487 // A subtract of one will be selected as a INC. Note that INC doesn't
10488 // set CF, so we can't do this for UADDO.
10489 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
10491 BaseOp = X86ISD::INC;
10492 Cond = X86::COND_O;
10495 BaseOp = X86ISD::ADD;
10496 Cond = X86::COND_O;
10499 BaseOp = X86ISD::ADD;
10500 Cond = X86::COND_B;
10503 // A subtract of one will be selected as a DEC. Note that DEC doesn't
10504 // set CF, so we can't do this for USUBO.
10505 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
10507 BaseOp = X86ISD::DEC;
10508 Cond = X86::COND_O;
10511 BaseOp = X86ISD::SUB;
10512 Cond = X86::COND_O;
10515 BaseOp = X86ISD::SUB;
10516 Cond = X86::COND_B;
10519 BaseOp = X86ISD::SMUL;
10520 Cond = X86::COND_O;
10522 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
10523 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
10525 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
10528 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
10529 DAG.getConstant(X86::COND_O, MVT::i32),
10530 SDValue(Sum.getNode(), 2));
10532 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
10536 // Also sets EFLAGS.
10537 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
10538 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
10541 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
10542 DAG.getConstant(Cond, MVT::i32),
10543 SDValue(Sum.getNode(), 1));
10545 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
10548 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
10549 SelectionDAG &DAG) const {
10550 DebugLoc dl = Op.getDebugLoc();
10551 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
10552 EVT VT = Op.getValueType();
10554 if (!Subtarget->hasSSE2() || !VT.isVector())
10557 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
10558 ExtraVT.getScalarType().getSizeInBits();
10559 SDValue ShAmt = DAG.getConstant(BitsDiff, MVT::i32);
10561 switch (VT.getSimpleVT().SimpleTy) {
10562 default: return SDValue();
10565 if (!Subtarget->hasAVX())
10567 if (!Subtarget->hasAVX2()) {
10568 // needs to be split
10569 unsigned NumElems = VT.getVectorNumElements();
10571 // Extract the LHS vectors
10572 SDValue LHS = Op.getOperand(0);
10573 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
10574 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
10576 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10577 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10579 EVT ExtraEltVT = ExtraVT.getVectorElementType();
10580 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
10581 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
10583 SDValue Extra = DAG.getValueType(ExtraVT);
10585 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
10586 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
10588 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);;
10593 SDValue Tmp1 = getTargetVShiftNode(X86ISD::VSHLI, dl, VT,
10594 Op.getOperand(0), ShAmt, DAG);
10595 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, Tmp1, ShAmt, DAG);
10601 SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{
10602 DebugLoc dl = Op.getDebugLoc();
10604 // Go ahead and emit the fence on x86-64 even if we asked for no-sse2.
10605 // There isn't any reason to disable it if the target processor supports it.
10606 if (!Subtarget->hasSSE2() && !Subtarget->is64Bit()) {
10607 SDValue Chain = Op.getOperand(0);
10608 SDValue Zero = DAG.getConstant(0, MVT::i32);
10610 DAG.getRegister(X86::ESP, MVT::i32), // Base
10611 DAG.getTargetConstant(1, MVT::i8), // Scale
10612 DAG.getRegister(0, MVT::i32), // Index
10613 DAG.getTargetConstant(0, MVT::i32), // Disp
10614 DAG.getRegister(0, MVT::i32), // Segment.
10619 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
10620 array_lengthof(Ops));
10621 return SDValue(Res, 0);
10624 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue();
10626 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
10628 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10629 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
10630 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
10631 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
10633 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
10634 if (!Op1 && !Op2 && !Op3 && Op4)
10635 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0));
10637 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
10638 if (Op1 && !Op2 && !Op3 && !Op4)
10639 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0));
10641 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)),
10643 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
10646 SDValue X86TargetLowering::LowerATOMIC_FENCE(SDValue Op,
10647 SelectionDAG &DAG) const {
10648 DebugLoc dl = Op.getDebugLoc();
10649 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
10650 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
10651 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
10652 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
10654 // The only fence that needs an instruction is a sequentially-consistent
10655 // cross-thread fence.
10656 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
10657 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
10658 // no-sse2). There isn't any reason to disable it if the target processor
10660 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
10661 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
10663 SDValue Chain = Op.getOperand(0);
10664 SDValue Zero = DAG.getConstant(0, MVT::i32);
10666 DAG.getRegister(X86::ESP, MVT::i32), // Base
10667 DAG.getTargetConstant(1, MVT::i8), // Scale
10668 DAG.getRegister(0, MVT::i32), // Index
10669 DAG.getTargetConstant(0, MVT::i32), // Disp
10670 DAG.getRegister(0, MVT::i32), // Segment.
10675 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
10676 array_lengthof(Ops));
10677 return SDValue(Res, 0);
10680 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
10681 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
10685 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const {
10686 EVT T = Op.getValueType();
10687 DebugLoc DL = Op.getDebugLoc();
10690 switch(T.getSimpleVT().SimpleTy) {
10691 default: llvm_unreachable("Invalid value type!");
10692 case MVT::i8: Reg = X86::AL; size = 1; break;
10693 case MVT::i16: Reg = X86::AX; size = 2; break;
10694 case MVT::i32: Reg = X86::EAX; size = 4; break;
10696 assert(Subtarget->is64Bit() && "Node not type legal!");
10697 Reg = X86::RAX; size = 8;
10700 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
10701 Op.getOperand(2), SDValue());
10702 SDValue Ops[] = { cpIn.getValue(0),
10705 DAG.getTargetConstant(size, MVT::i8),
10706 cpIn.getValue(1) };
10707 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10708 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
10709 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
10712 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
10716 SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
10717 SelectionDAG &DAG) const {
10718 assert(Subtarget->is64Bit() && "Result not type legalized?");
10719 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10720 SDValue TheChain = Op.getOperand(0);
10721 DebugLoc dl = Op.getDebugLoc();
10722 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
10723 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
10724 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
10726 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
10727 DAG.getConstant(32, MVT::i8));
10729 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
10732 return DAG.getMergeValues(Ops, 2, dl);
10735 SDValue X86TargetLowering::LowerBITCAST(SDValue Op,
10736 SelectionDAG &DAG) const {
10737 EVT SrcVT = Op.getOperand(0).getValueType();
10738 EVT DstVT = Op.getValueType();
10739 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
10740 Subtarget->hasMMX() && "Unexpected custom BITCAST");
10741 assert((DstVT == MVT::i64 ||
10742 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
10743 "Unexpected custom BITCAST");
10744 // i64 <=> MMX conversions are Legal.
10745 if (SrcVT==MVT::i64 && DstVT.isVector())
10747 if (DstVT==MVT::i64 && SrcVT.isVector())
10749 // MMX <=> MMX conversions are Legal.
10750 if (SrcVT.isVector() && DstVT.isVector())
10752 // All other conversions need to be expanded.
10756 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const {
10757 SDNode *Node = Op.getNode();
10758 DebugLoc dl = Node->getDebugLoc();
10759 EVT T = Node->getValueType(0);
10760 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
10761 DAG.getConstant(0, T), Node->getOperand(2));
10762 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
10763 cast<AtomicSDNode>(Node)->getMemoryVT(),
10764 Node->getOperand(0),
10765 Node->getOperand(1), negOp,
10766 cast<AtomicSDNode>(Node)->getSrcValue(),
10767 cast<AtomicSDNode>(Node)->getAlignment(),
10768 cast<AtomicSDNode>(Node)->getOrdering(),
10769 cast<AtomicSDNode>(Node)->getSynchScope());
10772 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
10773 SDNode *Node = Op.getNode();
10774 DebugLoc dl = Node->getDebugLoc();
10775 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
10777 // Convert seq_cst store -> xchg
10778 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
10779 // FIXME: On 32-bit, store -> fist or movq would be more efficient
10780 // (The only way to get a 16-byte store is cmpxchg16b)
10781 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
10782 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
10783 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
10784 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
10785 cast<AtomicSDNode>(Node)->getMemoryVT(),
10786 Node->getOperand(0),
10787 Node->getOperand(1), Node->getOperand(2),
10788 cast<AtomicSDNode>(Node)->getMemOperand(),
10789 cast<AtomicSDNode>(Node)->getOrdering(),
10790 cast<AtomicSDNode>(Node)->getSynchScope());
10791 return Swap.getValue(1);
10793 // Other atomic stores have a simple pattern.
10797 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
10798 EVT VT = Op.getNode()->getValueType(0);
10800 // Let legalize expand this if it isn't a legal type yet.
10801 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
10804 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
10807 bool ExtraOp = false;
10808 switch (Op.getOpcode()) {
10809 default: llvm_unreachable("Invalid code");
10810 case ISD::ADDC: Opc = X86ISD::ADD; break;
10811 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
10812 case ISD::SUBC: Opc = X86ISD::SUB; break;
10813 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
10817 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
10819 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
10820 Op.getOperand(1), Op.getOperand(2));
10823 /// LowerOperation - Provide custom lowering hooks for some operations.
10825 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
10826 switch (Op.getOpcode()) {
10827 default: llvm_unreachable("Should not custom lower this!");
10828 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
10829 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op,DAG);
10830 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op,DAG);
10831 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
10832 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
10833 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
10834 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
10835 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
10836 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
10837 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
10838 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
10839 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
10840 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG);
10841 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
10842 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
10843 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
10844 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
10845 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
10846 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
10847 case ISD::SHL_PARTS:
10848 case ISD::SRA_PARTS:
10849 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
10850 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
10851 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
10852 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
10853 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
10854 case ISD::FABS: return LowerFABS(Op, DAG);
10855 case ISD::FNEG: return LowerFNEG(Op, DAG);
10856 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
10857 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
10858 case ISD::SETCC: return LowerSETCC(Op, DAG);
10859 case ISD::SELECT: return LowerSELECT(Op, DAG);
10860 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
10861 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
10862 case ISD::VASTART: return LowerVASTART(Op, DAG);
10863 case ISD::VAARG: return LowerVAARG(Op, DAG);
10864 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
10865 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
10866 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
10867 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
10868 case ISD::FRAME_TO_ARGS_OFFSET:
10869 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
10870 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
10871 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
10872 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
10873 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
10874 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
10875 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
10876 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
10877 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
10878 case ISD::MUL: return LowerMUL(Op, DAG);
10881 case ISD::SHL: return LowerShift(Op, DAG);
10887 case ISD::UMULO: return LowerXALUO(Op, DAG);
10888 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
10889 case ISD::BITCAST: return LowerBITCAST(Op, DAG);
10893 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
10894 case ISD::ADD: return LowerADD(Op, DAG);
10895 case ISD::SUB: return LowerSUB(Op, DAG);
10899 static void ReplaceATOMIC_LOAD(SDNode *Node,
10900 SmallVectorImpl<SDValue> &Results,
10901 SelectionDAG &DAG) {
10902 DebugLoc dl = Node->getDebugLoc();
10903 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
10905 // Convert wide load -> cmpxchg8b/cmpxchg16b
10906 // FIXME: On 32-bit, load -> fild or movq would be more efficient
10907 // (The only way to get a 16-byte load is cmpxchg16b)
10908 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
10909 SDValue Zero = DAG.getConstant(0, VT);
10910 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT,
10911 Node->getOperand(0),
10912 Node->getOperand(1), Zero, Zero,
10913 cast<AtomicSDNode>(Node)->getMemOperand(),
10914 cast<AtomicSDNode>(Node)->getOrdering(),
10915 cast<AtomicSDNode>(Node)->getSynchScope());
10916 Results.push_back(Swap.getValue(0));
10917 Results.push_back(Swap.getValue(1));
10920 void X86TargetLowering::
10921 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
10922 SelectionDAG &DAG, unsigned NewOp) const {
10923 DebugLoc dl = Node->getDebugLoc();
10924 assert (Node->getValueType(0) == MVT::i64 &&
10925 "Only know how to expand i64 atomics");
10927 SDValue Chain = Node->getOperand(0);
10928 SDValue In1 = Node->getOperand(1);
10929 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
10930 Node->getOperand(2), DAG.getIntPtrConstant(0));
10931 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
10932 Node->getOperand(2), DAG.getIntPtrConstant(1));
10933 SDValue Ops[] = { Chain, In1, In2L, In2H };
10934 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
10936 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64,
10937 cast<MemSDNode>(Node)->getMemOperand());
10938 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
10939 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
10940 Results.push_back(Result.getValue(2));
10943 /// ReplaceNodeResults - Replace a node with an illegal result type
10944 /// with a new node built out of custom code.
10945 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
10946 SmallVectorImpl<SDValue>&Results,
10947 SelectionDAG &DAG) const {
10948 DebugLoc dl = N->getDebugLoc();
10949 switch (N->getOpcode()) {
10951 llvm_unreachable("Do not know how to custom type legalize this operation!");
10952 case ISD::SIGN_EXTEND_INREG:
10957 // We don't want to expand or promote these.
10959 case ISD::FP_TO_SINT:
10960 case ISD::FP_TO_UINT: {
10961 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
10963 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
10966 std::pair<SDValue,SDValue> Vals =
10967 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
10968 SDValue FIST = Vals.first, StackSlot = Vals.second;
10969 if (FIST.getNode() != 0) {
10970 EVT VT = N->getValueType(0);
10971 // Return a load from the stack slot.
10972 if (StackSlot.getNode() != 0)
10973 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
10974 MachinePointerInfo(),
10975 false, false, false, 0));
10977 Results.push_back(FIST);
10981 case ISD::READCYCLECOUNTER: {
10982 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10983 SDValue TheChain = N->getOperand(0);
10984 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
10985 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
10987 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
10989 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
10990 SDValue Ops[] = { eax, edx };
10991 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
10992 Results.push_back(edx.getValue(1));
10995 case ISD::ATOMIC_CMP_SWAP: {
10996 EVT T = N->getValueType(0);
10997 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
10998 bool Regs64bit = T == MVT::i128;
10999 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
11000 SDValue cpInL, cpInH;
11001 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
11002 DAG.getConstant(0, HalfT));
11003 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
11004 DAG.getConstant(1, HalfT));
11005 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
11006 Regs64bit ? X86::RAX : X86::EAX,
11008 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
11009 Regs64bit ? X86::RDX : X86::EDX,
11010 cpInH, cpInL.getValue(1));
11011 SDValue swapInL, swapInH;
11012 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
11013 DAG.getConstant(0, HalfT));
11014 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
11015 DAG.getConstant(1, HalfT));
11016 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
11017 Regs64bit ? X86::RBX : X86::EBX,
11018 swapInL, cpInH.getValue(1));
11019 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
11020 Regs64bit ? X86::RCX : X86::ECX,
11021 swapInH, swapInL.getValue(1));
11022 SDValue Ops[] = { swapInH.getValue(0),
11024 swapInH.getValue(1) };
11025 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
11026 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
11027 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
11028 X86ISD::LCMPXCHG8_DAG;
11029 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys,
11031 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
11032 Regs64bit ? X86::RAX : X86::EAX,
11033 HalfT, Result.getValue(1));
11034 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
11035 Regs64bit ? X86::RDX : X86::EDX,
11036 HalfT, cpOutL.getValue(2));
11037 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
11038 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2));
11039 Results.push_back(cpOutH.getValue(1));
11042 case ISD::ATOMIC_LOAD_ADD:
11043 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
11045 case ISD::ATOMIC_LOAD_AND:
11046 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
11048 case ISD::ATOMIC_LOAD_NAND:
11049 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
11051 case ISD::ATOMIC_LOAD_OR:
11052 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
11054 case ISD::ATOMIC_LOAD_SUB:
11055 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
11057 case ISD::ATOMIC_LOAD_XOR:
11058 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
11060 case ISD::ATOMIC_SWAP:
11061 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
11063 case ISD::ATOMIC_LOAD:
11064 ReplaceATOMIC_LOAD(N, Results, DAG);
11068 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
11070 default: return NULL;
11071 case X86ISD::BSF: return "X86ISD::BSF";
11072 case X86ISD::BSR: return "X86ISD::BSR";
11073 case X86ISD::SHLD: return "X86ISD::SHLD";
11074 case X86ISD::SHRD: return "X86ISD::SHRD";
11075 case X86ISD::FAND: return "X86ISD::FAND";
11076 case X86ISD::FOR: return "X86ISD::FOR";
11077 case X86ISD::FXOR: return "X86ISD::FXOR";
11078 case X86ISD::FSRL: return "X86ISD::FSRL";
11079 case X86ISD::FILD: return "X86ISD::FILD";
11080 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
11081 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
11082 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
11083 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
11084 case X86ISD::FLD: return "X86ISD::FLD";
11085 case X86ISD::FST: return "X86ISD::FST";
11086 case X86ISD::CALL: return "X86ISD::CALL";
11087 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
11088 case X86ISD::BT: return "X86ISD::BT";
11089 case X86ISD::CMP: return "X86ISD::CMP";
11090 case X86ISD::COMI: return "X86ISD::COMI";
11091 case X86ISD::UCOMI: return "X86ISD::UCOMI";
11092 case X86ISD::SETCC: return "X86ISD::SETCC";
11093 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
11094 case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd";
11095 case X86ISD::FSETCCss: return "X86ISD::FSETCCss";
11096 case X86ISD::CMOV: return "X86ISD::CMOV";
11097 case X86ISD::BRCOND: return "X86ISD::BRCOND";
11098 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
11099 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
11100 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
11101 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
11102 case X86ISD::Wrapper: return "X86ISD::Wrapper";
11103 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
11104 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
11105 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
11106 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
11107 case X86ISD::PINSRB: return "X86ISD::PINSRB";
11108 case X86ISD::PINSRW: return "X86ISD::PINSRW";
11109 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
11110 case X86ISD::ANDNP: return "X86ISD::ANDNP";
11111 case X86ISD::PSIGN: return "X86ISD::PSIGN";
11112 case X86ISD::BLENDV: return "X86ISD::BLENDV";
11113 case X86ISD::BLENDPW: return "X86ISD::BLENDPW";
11114 case X86ISD::BLENDPS: return "X86ISD::BLENDPS";
11115 case X86ISD::BLENDPD: return "X86ISD::BLENDPD";
11116 case X86ISD::HADD: return "X86ISD::HADD";
11117 case X86ISD::HSUB: return "X86ISD::HSUB";
11118 case X86ISD::FHADD: return "X86ISD::FHADD";
11119 case X86ISD::FHSUB: return "X86ISD::FHSUB";
11120 case X86ISD::FMAX: return "X86ISD::FMAX";
11121 case X86ISD::FMIN: return "X86ISD::FMIN";
11122 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
11123 case X86ISD::FRCP: return "X86ISD::FRCP";
11124 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
11125 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
11126 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
11127 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
11128 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
11129 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
11130 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
11131 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
11132 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
11133 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
11134 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
11135 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
11136 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
11137 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
11138 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
11139 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
11140 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
11141 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
11142 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
11143 case X86ISD::VSHL: return "X86ISD::VSHL";
11144 case X86ISD::VSRL: return "X86ISD::VSRL";
11145 case X86ISD::VSRA: return "X86ISD::VSRA";
11146 case X86ISD::VSHLI: return "X86ISD::VSHLI";
11147 case X86ISD::VSRLI: return "X86ISD::VSRLI";
11148 case X86ISD::VSRAI: return "X86ISD::VSRAI";
11149 case X86ISD::CMPP: return "X86ISD::CMPP";
11150 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
11151 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
11152 case X86ISD::ADD: return "X86ISD::ADD";
11153 case X86ISD::SUB: return "X86ISD::SUB";
11154 case X86ISD::ADC: return "X86ISD::ADC";
11155 case X86ISD::SBB: return "X86ISD::SBB";
11156 case X86ISD::SMUL: return "X86ISD::SMUL";
11157 case X86ISD::UMUL: return "X86ISD::UMUL";
11158 case X86ISD::INC: return "X86ISD::INC";
11159 case X86ISD::DEC: return "X86ISD::DEC";
11160 case X86ISD::OR: return "X86ISD::OR";
11161 case X86ISD::XOR: return "X86ISD::XOR";
11162 case X86ISD::AND: return "X86ISD::AND";
11163 case X86ISD::ANDN: return "X86ISD::ANDN";
11164 case X86ISD::BLSI: return "X86ISD::BLSI";
11165 case X86ISD::BLSMSK: return "X86ISD::BLSMSK";
11166 case X86ISD::BLSR: return "X86ISD::BLSR";
11167 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
11168 case X86ISD::PTEST: return "X86ISD::PTEST";
11169 case X86ISD::TESTP: return "X86ISD::TESTP";
11170 case X86ISD::PALIGN: return "X86ISD::PALIGN";
11171 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
11172 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
11173 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
11174 case X86ISD::SHUFP: return "X86ISD::SHUFP";
11175 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
11176 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
11177 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
11178 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
11179 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
11180 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
11181 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
11182 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
11183 case X86ISD::MOVSD: return "X86ISD::MOVSD";
11184 case X86ISD::MOVSS: return "X86ISD::MOVSS";
11185 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
11186 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
11187 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
11188 case X86ISD::VPERMILP: return "X86ISD::VPERMILP";
11189 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
11190 case X86ISD::VPERMV: return "X86ISD::VPERMV";
11191 case X86ISD::VPERMI: return "X86ISD::VPERMI";
11192 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
11193 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
11194 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
11195 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
11196 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
11197 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
11198 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
11199 case X86ISD::SAHF: return "X86ISD::SAHF";
11203 // isLegalAddressingMode - Return true if the addressing mode represented
11204 // by AM is legal for this target, for a load/store of the specified type.
11205 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
11207 // X86 supports extremely general addressing modes.
11208 CodeModel::Model M = getTargetMachine().getCodeModel();
11209 Reloc::Model R = getTargetMachine().getRelocationModel();
11211 // X86 allows a sign-extended 32-bit immediate field as a displacement.
11212 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
11217 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
11219 // If a reference to this global requires an extra load, we can't fold it.
11220 if (isGlobalStubReference(GVFlags))
11223 // If BaseGV requires a register for the PIC base, we cannot also have a
11224 // BaseReg specified.
11225 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
11228 // If lower 4G is not available, then we must use rip-relative addressing.
11229 if ((M != CodeModel::Small || R != Reloc::Static) &&
11230 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
11234 switch (AM.Scale) {
11240 // These scales always work.
11245 // These scales are formed with basereg+scalereg. Only accept if there is
11250 default: // Other stuff never works.
11258 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
11259 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
11261 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
11262 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
11263 if (NumBits1 <= NumBits2)
11268 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
11269 if (!VT1.isInteger() || !VT2.isInteger())
11271 unsigned NumBits1 = VT1.getSizeInBits();
11272 unsigned NumBits2 = VT2.getSizeInBits();
11273 if (NumBits1 <= NumBits2)
11278 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
11279 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
11280 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
11283 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
11284 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
11285 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
11288 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
11289 // i16 instructions are longer (0x66 prefix) and potentially slower.
11290 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
11293 /// isShuffleMaskLegal - Targets can use this to indicate that they only
11294 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
11295 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
11296 /// are assumed to be legal.
11298 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
11300 // Very little shuffling can be done for 64-bit vectors right now.
11301 if (VT.getSizeInBits() == 64)
11304 // FIXME: pshufb, blends, shifts.
11305 return (VT.getVectorNumElements() == 2 ||
11306 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
11307 isMOVLMask(M, VT) ||
11308 isSHUFPMask(M, VT, Subtarget->hasAVX()) ||
11309 isPSHUFDMask(M, VT) ||
11310 isPSHUFHWMask(M, VT, Subtarget->hasAVX2()) ||
11311 isPSHUFLWMask(M, VT, Subtarget->hasAVX2()) ||
11312 isPALIGNRMask(M, VT, Subtarget) ||
11313 isUNPCKLMask(M, VT, Subtarget->hasAVX2()) ||
11314 isUNPCKHMask(M, VT, Subtarget->hasAVX2()) ||
11315 isUNPCKL_v_undef_Mask(M, VT, Subtarget->hasAVX2()) ||
11316 isUNPCKH_v_undef_Mask(M, VT, Subtarget->hasAVX2()));
11320 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
11322 unsigned NumElts = VT.getVectorNumElements();
11323 // FIXME: This collection of masks seems suspect.
11326 if (NumElts == 4 && VT.getSizeInBits() == 128) {
11327 return (isMOVLMask(Mask, VT) ||
11328 isCommutedMOVLMask(Mask, VT, true) ||
11329 isSHUFPMask(Mask, VT, Subtarget->hasAVX()) ||
11330 isSHUFPMask(Mask, VT, Subtarget->hasAVX(), /* Commuted */ true));
11335 //===----------------------------------------------------------------------===//
11336 // X86 Scheduler Hooks
11337 //===----------------------------------------------------------------------===//
11339 // private utility function
11340 MachineBasicBlock *
11341 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
11342 MachineBasicBlock *MBB,
11349 const TargetRegisterClass *RC,
11350 bool Invert) const {
11351 // For the atomic bitwise operator, we generate
11354 // ld t1 = [bitinstr.addr]
11355 // op t2 = t1, [bitinstr.val]
11356 // not t3 = t2 (if Invert)
11358 // lcs dest = [bitinstr.addr], t3 [EAX is implicit]
11360 // fallthrough -->nextMBB
11361 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11362 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11363 MachineFunction::iterator MBBIter = MBB;
11366 /// First build the CFG
11367 MachineFunction *F = MBB->getParent();
11368 MachineBasicBlock *thisMBB = MBB;
11369 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11370 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11371 F->insert(MBBIter, newMBB);
11372 F->insert(MBBIter, nextMBB);
11374 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11375 nextMBB->splice(nextMBB->begin(), thisMBB,
11376 llvm::next(MachineBasicBlock::iterator(bInstr)),
11378 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11380 // Update thisMBB to fall through to newMBB
11381 thisMBB->addSuccessor(newMBB);
11383 // newMBB jumps to itself and fall through to nextMBB
11384 newMBB->addSuccessor(nextMBB);
11385 newMBB->addSuccessor(newMBB);
11387 // Insert instructions into newMBB based on incoming instruction
11388 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
11389 "unexpected number of operands");
11390 DebugLoc dl = bInstr->getDebugLoc();
11391 MachineOperand& destOper = bInstr->getOperand(0);
11392 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11393 int numArgs = bInstr->getNumOperands() - 1;
11394 for (int i=0; i < numArgs; ++i)
11395 argOpers[i] = &bInstr->getOperand(i+1);
11397 // x86 address has 4 operands: base, index, scale, and displacement
11398 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11399 int valArgIndx = lastAddrIndx + 1;
11401 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
11402 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1);
11403 for (int i=0; i <= lastAddrIndx; ++i)
11404 (*MIB).addOperand(*argOpers[i]);
11406 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
11407 assert((argOpers[valArgIndx]->isReg() ||
11408 argOpers[valArgIndx]->isImm()) &&
11409 "invalid operand");
11410 if (argOpers[valArgIndx]->isReg())
11411 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2);
11413 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2);
11415 (*MIB).addOperand(*argOpers[valArgIndx]);
11417 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
11419 MIB = BuildMI(newMBB, dl, TII->get(notOpc), t3).addReg(t2);
11424 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg);
11427 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
11428 for (int i=0; i <= lastAddrIndx; ++i)
11429 (*MIB).addOperand(*argOpers[i]);
11431 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11432 (*MIB).setMemRefs(bInstr->memoperands_begin(),
11433 bInstr->memoperands_end());
11435 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
11436 MIB.addReg(EAXreg);
11439 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11441 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
11445 // private utility function: 64 bit atomics on 32 bit host.
11446 MachineBasicBlock *
11447 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
11448 MachineBasicBlock *MBB,
11453 bool Invert) const {
11454 // For the atomic bitwise operator, we generate
11455 // thisMBB (instructions are in pairs, except cmpxchg8b)
11456 // ld t1,t2 = [bitinstr.addr]
11458 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
11459 // op t5, t6 <- out1, out2, [bitinstr.val]
11460 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
11461 // neg t7, t8 < t5, t6 (if Invert)
11462 // mov ECX, EBX <- t5, t6
11463 // mov EAX, EDX <- t1, t2
11464 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
11465 // mov t3, t4 <- EAX, EDX
11467 // result in out1, out2
11468 // fallthrough -->nextMBB
11470 const TargetRegisterClass *RC = &X86::GR32RegClass;
11471 const unsigned LoadOpc = X86::MOV32rm;
11472 const unsigned NotOpc = X86::NOT32r;
11473 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11474 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11475 MachineFunction::iterator MBBIter = MBB;
11478 /// First build the CFG
11479 MachineFunction *F = MBB->getParent();
11480 MachineBasicBlock *thisMBB = MBB;
11481 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11482 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11483 F->insert(MBBIter, newMBB);
11484 F->insert(MBBIter, nextMBB);
11486 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11487 nextMBB->splice(nextMBB->begin(), thisMBB,
11488 llvm::next(MachineBasicBlock::iterator(bInstr)),
11490 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11492 // Update thisMBB to fall through to newMBB
11493 thisMBB->addSuccessor(newMBB);
11495 // newMBB jumps to itself and fall through to nextMBB
11496 newMBB->addSuccessor(nextMBB);
11497 newMBB->addSuccessor(newMBB);
11499 DebugLoc dl = bInstr->getDebugLoc();
11500 // Insert instructions into newMBB based on incoming instruction
11501 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
11502 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 14 &&
11503 "unexpected number of operands");
11504 MachineOperand& dest1Oper = bInstr->getOperand(0);
11505 MachineOperand& dest2Oper = bInstr->getOperand(1);
11506 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11507 for (int i=0; i < 2 + X86::AddrNumOperands; ++i) {
11508 argOpers[i] = &bInstr->getOperand(i+2);
11510 // We use some of the operands multiple times, so conservatively just
11511 // clear any kill flags that might be present.
11512 if (argOpers[i]->isReg() && argOpers[i]->isUse())
11513 argOpers[i]->setIsKill(false);
11516 // x86 address has 5 operands: base, index, scale, displacement, and segment.
11517 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11519 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
11520 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1);
11521 for (int i=0; i <= lastAddrIndx; ++i)
11522 (*MIB).addOperand(*argOpers[i]);
11523 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
11524 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
11525 // add 4 to displacement.
11526 for (int i=0; i <= lastAddrIndx-2; ++i)
11527 (*MIB).addOperand(*argOpers[i]);
11528 MachineOperand newOp3 = *(argOpers[3]);
11529 if (newOp3.isImm())
11530 newOp3.setImm(newOp3.getImm()+4);
11532 newOp3.setOffset(newOp3.getOffset()+4);
11533 (*MIB).addOperand(newOp3);
11534 (*MIB).addOperand(*argOpers[lastAddrIndx]);
11536 // t3/4 are defined later, at the bottom of the loop
11537 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
11538 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
11539 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg())
11540 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
11541 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
11542 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
11544 // The subsequent operations should be using the destination registers of
11545 // the PHI instructions.
11546 t1 = dest1Oper.getReg();
11547 t2 = dest2Oper.getReg();
11549 int valArgIndx = lastAddrIndx + 1;
11550 assert((argOpers[valArgIndx]->isReg() ||
11551 argOpers[valArgIndx]->isImm()) &&
11552 "invalid operand");
11553 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
11554 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
11555 if (argOpers[valArgIndx]->isReg())
11556 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5);
11558 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
11559 if (regOpcL != X86::MOV32rr)
11561 (*MIB).addOperand(*argOpers[valArgIndx]);
11562 assert(argOpers[valArgIndx + 1]->isReg() ==
11563 argOpers[valArgIndx]->isReg());
11564 assert(argOpers[valArgIndx + 1]->isImm() ==
11565 argOpers[valArgIndx]->isImm());
11566 if (argOpers[valArgIndx + 1]->isReg())
11567 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
11569 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
11570 if (regOpcH != X86::MOV32rr)
11572 (*MIB).addOperand(*argOpers[valArgIndx + 1]);
11576 t7 = F->getRegInfo().createVirtualRegister(RC);
11577 t8 = F->getRegInfo().createVirtualRegister(RC);
11578 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t7).addReg(t5);
11579 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t8).addReg(t6);
11585 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
11587 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EDX);
11590 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EBX);
11592 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::ECX);
11595 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
11596 for (int i=0; i <= lastAddrIndx; ++i)
11597 (*MIB).addOperand(*argOpers[i]);
11599 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11600 (*MIB).setMemRefs(bInstr->memoperands_begin(),
11601 bInstr->memoperands_end());
11603 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t3);
11604 MIB.addReg(X86::EAX);
11605 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t4);
11606 MIB.addReg(X86::EDX);
11609 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11611 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
11615 // private utility function
11616 MachineBasicBlock *
11617 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
11618 MachineBasicBlock *MBB,
11619 unsigned cmovOpc) const {
11620 // For the atomic min/max operator, we generate
11623 // ld t1 = [min/max.addr]
11624 // mov t2 = [min/max.val]
11626 // cmov[cond] t2 = t1
11628 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
11630 // fallthrough -->nextMBB
11632 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11633 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11634 MachineFunction::iterator MBBIter = MBB;
11637 /// First build the CFG
11638 MachineFunction *F = MBB->getParent();
11639 MachineBasicBlock *thisMBB = MBB;
11640 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11641 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11642 F->insert(MBBIter, newMBB);
11643 F->insert(MBBIter, nextMBB);
11645 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11646 nextMBB->splice(nextMBB->begin(), thisMBB,
11647 llvm::next(MachineBasicBlock::iterator(mInstr)),
11649 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11651 // Update thisMBB to fall through to newMBB
11652 thisMBB->addSuccessor(newMBB);
11654 // newMBB jumps to newMBB and fall through to nextMBB
11655 newMBB->addSuccessor(nextMBB);
11656 newMBB->addSuccessor(newMBB);
11658 DebugLoc dl = mInstr->getDebugLoc();
11659 // Insert instructions into newMBB based on incoming instruction
11660 assert(mInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
11661 "unexpected number of operands");
11662 MachineOperand& destOper = mInstr->getOperand(0);
11663 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11664 int numArgs = mInstr->getNumOperands() - 1;
11665 for (int i=0; i < numArgs; ++i)
11666 argOpers[i] = &mInstr->getOperand(i+1);
11668 // x86 address has 4 operands: base, index, scale, and displacement
11669 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11670 int valArgIndx = lastAddrIndx + 1;
11672 unsigned t1 = F->getRegInfo().createVirtualRegister(&X86::GR32RegClass);
11673 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1);
11674 for (int i=0; i <= lastAddrIndx; ++i)
11675 (*MIB).addOperand(*argOpers[i]);
11677 // We only support register and immediate values
11678 assert((argOpers[valArgIndx]->isReg() ||
11679 argOpers[valArgIndx]->isImm()) &&
11680 "invalid operand");
11682 unsigned t2 = F->getRegInfo().createVirtualRegister(&X86::GR32RegClass);
11683 if (argOpers[valArgIndx]->isReg())
11684 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t2);
11686 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
11687 (*MIB).addOperand(*argOpers[valArgIndx]);
11689 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
11692 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr));
11697 unsigned t3 = F->getRegInfo().createVirtualRegister(&X86::GR32RegClass);
11698 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3);
11702 // Cmp and exchange if none has modified the memory location
11703 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32));
11704 for (int i=0; i <= lastAddrIndx; ++i)
11705 (*MIB).addOperand(*argOpers[i]);
11707 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11708 (*MIB).setMemRefs(mInstr->memoperands_begin(),
11709 mInstr->memoperands_end());
11711 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
11712 MIB.addReg(X86::EAX);
11715 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11717 mInstr->eraseFromParent(); // The pseudo instruction is gone now.
11721 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
11722 // or XMM0_V32I8 in AVX all of this code can be replaced with that
11723 // in the .td file.
11724 MachineBasicBlock *
11725 X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB,
11726 unsigned numArgs, bool memArg) const {
11727 assert(Subtarget->hasSSE42() &&
11728 "Target must have SSE4.2 or AVX features enabled");
11730 DebugLoc dl = MI->getDebugLoc();
11731 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11733 if (!Subtarget->hasAVX()) {
11735 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm;
11737 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr;
11740 Opc = numArgs == 3 ? X86::VPCMPISTRM128rm : X86::VPCMPESTRM128rm;
11742 Opc = numArgs == 3 ? X86::VPCMPISTRM128rr : X86::VPCMPESTRM128rr;
11745 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
11746 for (unsigned i = 0; i < numArgs; ++i) {
11747 MachineOperand &Op = MI->getOperand(i+1);
11748 if (!(Op.isReg() && Op.isImplicit()))
11749 MIB.addOperand(Op);
11751 BuildMI(*BB, MI, dl,
11752 TII->get(Subtarget->hasAVX() ? X86::VMOVAPSrr : X86::MOVAPSrr),
11753 MI->getOperand(0).getReg())
11754 .addReg(X86::XMM0);
11756 MI->eraseFromParent();
11760 MachineBasicBlock *
11761 X86TargetLowering::EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB) const {
11762 DebugLoc dl = MI->getDebugLoc();
11763 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11765 // Address into RAX/EAX, other two args into ECX, EDX.
11766 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
11767 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
11768 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
11769 for (int i = 0; i < X86::AddrNumOperands; ++i)
11770 MIB.addOperand(MI->getOperand(i));
11772 unsigned ValOps = X86::AddrNumOperands;
11773 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
11774 .addReg(MI->getOperand(ValOps).getReg());
11775 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
11776 .addReg(MI->getOperand(ValOps+1).getReg());
11778 // The instruction doesn't actually take any operands though.
11779 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
11781 MI->eraseFromParent(); // The pseudo is gone now.
11785 MachineBasicBlock *
11786 X86TargetLowering::EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const {
11787 DebugLoc dl = MI->getDebugLoc();
11788 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11790 // First arg in ECX, the second in EAX.
11791 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
11792 .addReg(MI->getOperand(0).getReg());
11793 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EAX)
11794 .addReg(MI->getOperand(1).getReg());
11796 // The instruction doesn't actually take any operands though.
11797 BuildMI(*BB, MI, dl, TII->get(X86::MWAITrr));
11799 MI->eraseFromParent(); // The pseudo is gone now.
11803 MachineBasicBlock *
11804 X86TargetLowering::EmitVAARG64WithCustomInserter(
11806 MachineBasicBlock *MBB) const {
11807 // Emit va_arg instruction on X86-64.
11809 // Operands to this pseudo-instruction:
11810 // 0 ) Output : destination address (reg)
11811 // 1-5) Input : va_list address (addr, i64mem)
11812 // 6 ) ArgSize : Size (in bytes) of vararg type
11813 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
11814 // 8 ) Align : Alignment of type
11815 // 9 ) EFLAGS (implicit-def)
11817 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
11818 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
11820 unsigned DestReg = MI->getOperand(0).getReg();
11821 MachineOperand &Base = MI->getOperand(1);
11822 MachineOperand &Scale = MI->getOperand(2);
11823 MachineOperand &Index = MI->getOperand(3);
11824 MachineOperand &Disp = MI->getOperand(4);
11825 MachineOperand &Segment = MI->getOperand(5);
11826 unsigned ArgSize = MI->getOperand(6).getImm();
11827 unsigned ArgMode = MI->getOperand(7).getImm();
11828 unsigned Align = MI->getOperand(8).getImm();
11830 // Memory Reference
11831 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
11832 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
11833 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
11835 // Machine Information
11836 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11837 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
11838 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
11839 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
11840 DebugLoc DL = MI->getDebugLoc();
11842 // struct va_list {
11845 // i64 overflow_area (address)
11846 // i64 reg_save_area (address)
11848 // sizeof(va_list) = 24
11849 // alignment(va_list) = 8
11851 unsigned TotalNumIntRegs = 6;
11852 unsigned TotalNumXMMRegs = 8;
11853 bool UseGPOffset = (ArgMode == 1);
11854 bool UseFPOffset = (ArgMode == 2);
11855 unsigned MaxOffset = TotalNumIntRegs * 8 +
11856 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
11858 /* Align ArgSize to a multiple of 8 */
11859 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
11860 bool NeedsAlign = (Align > 8);
11862 MachineBasicBlock *thisMBB = MBB;
11863 MachineBasicBlock *overflowMBB;
11864 MachineBasicBlock *offsetMBB;
11865 MachineBasicBlock *endMBB;
11867 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
11868 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
11869 unsigned OffsetReg = 0;
11871 if (!UseGPOffset && !UseFPOffset) {
11872 // If we only pull from the overflow region, we don't create a branch.
11873 // We don't need to alter control flow.
11874 OffsetDestReg = 0; // unused
11875 OverflowDestReg = DestReg;
11878 overflowMBB = thisMBB;
11881 // First emit code to check if gp_offset (or fp_offset) is below the bound.
11882 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
11883 // If not, pull from overflow_area. (branch to overflowMBB)
11888 // offsetMBB overflowMBB
11893 // Registers for the PHI in endMBB
11894 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
11895 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
11897 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11898 MachineFunction *MF = MBB->getParent();
11899 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11900 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11901 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11903 MachineFunction::iterator MBBIter = MBB;
11906 // Insert the new basic blocks
11907 MF->insert(MBBIter, offsetMBB);
11908 MF->insert(MBBIter, overflowMBB);
11909 MF->insert(MBBIter, endMBB);
11911 // Transfer the remainder of MBB and its successor edges to endMBB.
11912 endMBB->splice(endMBB->begin(), thisMBB,
11913 llvm::next(MachineBasicBlock::iterator(MI)),
11915 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11917 // Make offsetMBB and overflowMBB successors of thisMBB
11918 thisMBB->addSuccessor(offsetMBB);
11919 thisMBB->addSuccessor(overflowMBB);
11921 // endMBB is a successor of both offsetMBB and overflowMBB
11922 offsetMBB->addSuccessor(endMBB);
11923 overflowMBB->addSuccessor(endMBB);
11925 // Load the offset value into a register
11926 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
11927 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
11931 .addDisp(Disp, UseFPOffset ? 4 : 0)
11932 .addOperand(Segment)
11933 .setMemRefs(MMOBegin, MMOEnd);
11935 // Check if there is enough room left to pull this argument.
11936 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
11938 .addImm(MaxOffset + 8 - ArgSizeA8);
11940 // Branch to "overflowMBB" if offset >= max
11941 // Fall through to "offsetMBB" otherwise
11942 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
11943 .addMBB(overflowMBB);
11946 // In offsetMBB, emit code to use the reg_save_area.
11948 assert(OffsetReg != 0);
11950 // Read the reg_save_area address.
11951 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
11952 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
11957 .addOperand(Segment)
11958 .setMemRefs(MMOBegin, MMOEnd);
11960 // Zero-extend the offset
11961 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
11962 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
11965 .addImm(X86::sub_32bit);
11967 // Add the offset to the reg_save_area to get the final address.
11968 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
11969 .addReg(OffsetReg64)
11970 .addReg(RegSaveReg);
11972 // Compute the offset for the next argument
11973 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
11974 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
11976 .addImm(UseFPOffset ? 16 : 8);
11978 // Store it back into the va_list.
11979 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
11983 .addDisp(Disp, UseFPOffset ? 4 : 0)
11984 .addOperand(Segment)
11985 .addReg(NextOffsetReg)
11986 .setMemRefs(MMOBegin, MMOEnd);
11989 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
11994 // Emit code to use overflow area
11997 // Load the overflow_area address into a register.
11998 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
11999 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
12004 .addOperand(Segment)
12005 .setMemRefs(MMOBegin, MMOEnd);
12007 // If we need to align it, do so. Otherwise, just copy the address
12008 // to OverflowDestReg.
12010 // Align the overflow address
12011 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
12012 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
12014 // aligned_addr = (addr + (align-1)) & ~(align-1)
12015 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
12016 .addReg(OverflowAddrReg)
12019 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
12021 .addImm(~(uint64_t)(Align-1));
12023 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
12024 .addReg(OverflowAddrReg);
12027 // Compute the next overflow address after this argument.
12028 // (the overflow address should be kept 8-byte aligned)
12029 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
12030 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
12031 .addReg(OverflowDestReg)
12032 .addImm(ArgSizeA8);
12034 // Store the new overflow address.
12035 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
12040 .addOperand(Segment)
12041 .addReg(NextAddrReg)
12042 .setMemRefs(MMOBegin, MMOEnd);
12044 // If we branched, emit the PHI to the front of endMBB.
12046 BuildMI(*endMBB, endMBB->begin(), DL,
12047 TII->get(X86::PHI), DestReg)
12048 .addReg(OffsetDestReg).addMBB(offsetMBB)
12049 .addReg(OverflowDestReg).addMBB(overflowMBB);
12052 // Erase the pseudo instruction
12053 MI->eraseFromParent();
12058 MachineBasicBlock *
12059 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
12061 MachineBasicBlock *MBB) const {
12062 // Emit code to save XMM registers to the stack. The ABI says that the
12063 // number of registers to save is given in %al, so it's theoretically
12064 // possible to do an indirect jump trick to avoid saving all of them,
12065 // however this code takes a simpler approach and just executes all
12066 // of the stores if %al is non-zero. It's less code, and it's probably
12067 // easier on the hardware branch predictor, and stores aren't all that
12068 // expensive anyway.
12070 // Create the new basic blocks. One block contains all the XMM stores,
12071 // and one block is the final destination regardless of whether any
12072 // stores were performed.
12073 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
12074 MachineFunction *F = MBB->getParent();
12075 MachineFunction::iterator MBBIter = MBB;
12077 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
12078 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
12079 F->insert(MBBIter, XMMSaveMBB);
12080 F->insert(MBBIter, EndMBB);
12082 // Transfer the remainder of MBB and its successor edges to EndMBB.
12083 EndMBB->splice(EndMBB->begin(), MBB,
12084 llvm::next(MachineBasicBlock::iterator(MI)),
12086 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
12088 // The original block will now fall through to the XMM save block.
12089 MBB->addSuccessor(XMMSaveMBB);
12090 // The XMMSaveMBB will fall through to the end block.
12091 XMMSaveMBB->addSuccessor(EndMBB);
12093 // Now add the instructions.
12094 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12095 DebugLoc DL = MI->getDebugLoc();
12097 unsigned CountReg = MI->getOperand(0).getReg();
12098 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
12099 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
12101 if (!Subtarget->isTargetWin64()) {
12102 // If %al is 0, branch around the XMM save block.
12103 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
12104 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
12105 MBB->addSuccessor(EndMBB);
12108 unsigned MOVOpc = Subtarget->hasAVX() ? X86::VMOVAPSmr : X86::MOVAPSmr;
12109 // In the XMM save block, save all the XMM argument registers.
12110 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
12111 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
12112 MachineMemOperand *MMO =
12113 F->getMachineMemOperand(
12114 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
12115 MachineMemOperand::MOStore,
12116 /*Size=*/16, /*Align=*/16);
12117 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
12118 .addFrameIndex(RegSaveFrameIndex)
12119 .addImm(/*Scale=*/1)
12120 .addReg(/*IndexReg=*/0)
12121 .addImm(/*Disp=*/Offset)
12122 .addReg(/*Segment=*/0)
12123 .addReg(MI->getOperand(i).getReg())
12124 .addMemOperand(MMO);
12127 MI->eraseFromParent(); // The pseudo instruction is gone now.
12132 // The EFLAGS operand of SelectItr might be missing a kill marker
12133 // because there were multiple uses of EFLAGS, and ISel didn't know
12134 // which to mark. Figure out whether SelectItr should have had a
12135 // kill marker, and set it if it should. Returns the correct kill
12137 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
12138 MachineBasicBlock* BB,
12139 const TargetRegisterInfo* TRI) {
12140 // Scan forward through BB for a use/def of EFLAGS.
12141 MachineBasicBlock::iterator miI(llvm::next(SelectItr));
12142 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
12143 const MachineInstr& mi = *miI;
12144 if (mi.readsRegister(X86::EFLAGS))
12146 if (mi.definesRegister(X86::EFLAGS))
12147 break; // Should have kill-flag - update below.
12150 // If we hit the end of the block, check whether EFLAGS is live into a
12152 if (miI == BB->end()) {
12153 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
12154 sEnd = BB->succ_end();
12155 sItr != sEnd; ++sItr) {
12156 MachineBasicBlock* succ = *sItr;
12157 if (succ->isLiveIn(X86::EFLAGS))
12162 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
12163 // out. SelectMI should have a kill flag on EFLAGS.
12164 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
12168 MachineBasicBlock *
12169 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
12170 MachineBasicBlock *BB) const {
12171 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12172 DebugLoc DL = MI->getDebugLoc();
12174 // To "insert" a SELECT_CC instruction, we actually have to insert the
12175 // diamond control-flow pattern. The incoming instruction knows the
12176 // destination vreg to set, the condition code register to branch on, the
12177 // true/false values to select between, and a branch opcode to use.
12178 const BasicBlock *LLVM_BB = BB->getBasicBlock();
12179 MachineFunction::iterator It = BB;
12185 // cmpTY ccX, r1, r2
12187 // fallthrough --> copy0MBB
12188 MachineBasicBlock *thisMBB = BB;
12189 MachineFunction *F = BB->getParent();
12190 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
12191 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
12192 F->insert(It, copy0MBB);
12193 F->insert(It, sinkMBB);
12195 // If the EFLAGS register isn't dead in the terminator, then claim that it's
12196 // live into the sink and copy blocks.
12197 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
12198 if (!MI->killsRegister(X86::EFLAGS) &&
12199 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
12200 copy0MBB->addLiveIn(X86::EFLAGS);
12201 sinkMBB->addLiveIn(X86::EFLAGS);
12204 // Transfer the remainder of BB and its successor edges to sinkMBB.
12205 sinkMBB->splice(sinkMBB->begin(), BB,
12206 llvm::next(MachineBasicBlock::iterator(MI)),
12208 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
12210 // Add the true and fallthrough blocks as its successors.
12211 BB->addSuccessor(copy0MBB);
12212 BB->addSuccessor(sinkMBB);
12214 // Create the conditional branch instruction.
12216 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
12217 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
12220 // %FalseValue = ...
12221 // # fallthrough to sinkMBB
12222 copy0MBB->addSuccessor(sinkMBB);
12225 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
12227 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
12228 TII->get(X86::PHI), MI->getOperand(0).getReg())
12229 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
12230 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
12232 MI->eraseFromParent(); // The pseudo instruction is gone now.
12236 MachineBasicBlock *
12237 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
12238 bool Is64Bit) const {
12239 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12240 DebugLoc DL = MI->getDebugLoc();
12241 MachineFunction *MF = BB->getParent();
12242 const BasicBlock *LLVM_BB = BB->getBasicBlock();
12244 assert(getTargetMachine().Options.EnableSegmentedStacks);
12246 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
12247 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30;
12250 // ... [Till the alloca]
12251 // If stacklet is not large enough, jump to mallocMBB
12254 // Allocate by subtracting from RSP
12255 // Jump to continueMBB
12258 // Allocate by call to runtime
12262 // [rest of original BB]
12265 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12266 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12267 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12269 MachineRegisterInfo &MRI = MF->getRegInfo();
12270 const TargetRegisterClass *AddrRegClass =
12271 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32);
12273 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
12274 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
12275 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
12276 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
12277 sizeVReg = MI->getOperand(1).getReg(),
12278 physSPReg = Is64Bit ? X86::RSP : X86::ESP;
12280 MachineFunction::iterator MBBIter = BB;
12283 MF->insert(MBBIter, bumpMBB);
12284 MF->insert(MBBIter, mallocMBB);
12285 MF->insert(MBBIter, continueMBB);
12287 continueMBB->splice(continueMBB->begin(), BB, llvm::next
12288 (MachineBasicBlock::iterator(MI)), BB->end());
12289 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
12291 // Add code to the main basic block to check if the stack limit has been hit,
12292 // and if so, jump to mallocMBB otherwise to bumpMBB.
12293 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
12294 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
12295 .addReg(tmpSPVReg).addReg(sizeVReg);
12296 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr))
12297 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
12298 .addReg(SPLimitVReg);
12299 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
12301 // bumpMBB simply decreases the stack pointer, since we know the current
12302 // stacklet has enough space.
12303 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
12304 .addReg(SPLimitVReg);
12305 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
12306 .addReg(SPLimitVReg);
12307 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
12309 // Calls into a routine in libgcc to allocate more space from the heap.
12310 const uint32_t *RegMask =
12311 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
12313 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
12315 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
12316 .addExternalSymbol("__morestack_allocate_stack_space").addReg(X86::RDI)
12317 .addRegMask(RegMask)
12318 .addReg(X86::RAX, RegState::ImplicitDefine);
12320 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
12322 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
12323 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
12324 .addExternalSymbol("__morestack_allocate_stack_space")
12325 .addRegMask(RegMask)
12326 .addReg(X86::EAX, RegState::ImplicitDefine);
12330 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
12333 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
12334 .addReg(Is64Bit ? X86::RAX : X86::EAX);
12335 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
12337 // Set up the CFG correctly.
12338 BB->addSuccessor(bumpMBB);
12339 BB->addSuccessor(mallocMBB);
12340 mallocMBB->addSuccessor(continueMBB);
12341 bumpMBB->addSuccessor(continueMBB);
12343 // Take care of the PHI nodes.
12344 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
12345 MI->getOperand(0).getReg())
12346 .addReg(mallocPtrVReg).addMBB(mallocMBB)
12347 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
12349 // Delete the original pseudo instruction.
12350 MI->eraseFromParent();
12353 return continueMBB;
12356 MachineBasicBlock *
12357 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
12358 MachineBasicBlock *BB) const {
12359 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12360 DebugLoc DL = MI->getDebugLoc();
12362 assert(!Subtarget->isTargetEnvMacho());
12364 // The lowering is pretty easy: we're just emitting the call to _alloca. The
12365 // non-trivial part is impdef of ESP.
12367 if (Subtarget->isTargetWin64()) {
12368 if (Subtarget->isTargetCygMing()) {
12369 // ___chkstk(Mingw64):
12370 // Clobbers R10, R11, RAX and EFLAGS.
12372 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
12373 .addExternalSymbol("___chkstk")
12374 .addReg(X86::RAX, RegState::Implicit)
12375 .addReg(X86::RSP, RegState::Implicit)
12376 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
12377 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
12378 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12380 // __chkstk(MSVCRT): does not update stack pointer.
12381 // Clobbers R10, R11 and EFLAGS.
12382 // FIXME: RAX(allocated size) might be reused and not killed.
12383 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
12384 .addExternalSymbol("__chkstk")
12385 .addReg(X86::RAX, RegState::Implicit)
12386 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12387 // RAX has the offset to subtracted from RSP.
12388 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
12393 const char *StackProbeSymbol =
12394 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca";
12396 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
12397 .addExternalSymbol(StackProbeSymbol)
12398 .addReg(X86::EAX, RegState::Implicit)
12399 .addReg(X86::ESP, RegState::Implicit)
12400 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
12401 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
12402 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12405 MI->eraseFromParent(); // The pseudo instruction is gone now.
12409 MachineBasicBlock *
12410 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
12411 MachineBasicBlock *BB) const {
12412 // This is pretty easy. We're taking the value that we received from
12413 // our load from the relocation, sticking it in either RDI (x86-64)
12414 // or EAX and doing an indirect call. The return value will then
12415 // be in the normal return register.
12416 const X86InstrInfo *TII
12417 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
12418 DebugLoc DL = MI->getDebugLoc();
12419 MachineFunction *F = BB->getParent();
12421 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
12422 assert(MI->getOperand(3).isGlobal() && "This should be a global");
12424 // Get a register mask for the lowered call.
12425 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
12426 // proper register mask.
12427 const uint32_t *RegMask =
12428 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
12429 if (Subtarget->is64Bit()) {
12430 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12431 TII->get(X86::MOV64rm), X86::RDI)
12433 .addImm(0).addReg(0)
12434 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12435 MI->getOperand(3).getTargetFlags())
12437 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
12438 addDirectMem(MIB, X86::RDI);
12439 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
12440 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
12441 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12442 TII->get(X86::MOV32rm), X86::EAX)
12444 .addImm(0).addReg(0)
12445 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12446 MI->getOperand(3).getTargetFlags())
12448 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
12449 addDirectMem(MIB, X86::EAX);
12450 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
12452 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12453 TII->get(X86::MOV32rm), X86::EAX)
12454 .addReg(TII->getGlobalBaseReg(F))
12455 .addImm(0).addReg(0)
12456 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12457 MI->getOperand(3).getTargetFlags())
12459 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
12460 addDirectMem(MIB, X86::EAX);
12461 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
12464 MI->eraseFromParent(); // The pseudo instruction is gone now.
12468 MachineBasicBlock *
12469 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
12470 MachineBasicBlock *BB) const {
12471 switch (MI->getOpcode()) {
12472 default: llvm_unreachable("Unexpected instr type to insert");
12473 case X86::TAILJMPd64:
12474 case X86::TAILJMPr64:
12475 case X86::TAILJMPm64:
12476 llvm_unreachable("TAILJMP64 would not be touched here.");
12477 case X86::TCRETURNdi64:
12478 case X86::TCRETURNri64:
12479 case X86::TCRETURNmi64:
12481 case X86::WIN_ALLOCA:
12482 return EmitLoweredWinAlloca(MI, BB);
12483 case X86::SEG_ALLOCA_32:
12484 return EmitLoweredSegAlloca(MI, BB, false);
12485 case X86::SEG_ALLOCA_64:
12486 return EmitLoweredSegAlloca(MI, BB, true);
12487 case X86::TLSCall_32:
12488 case X86::TLSCall_64:
12489 return EmitLoweredTLSCall(MI, BB);
12490 case X86::CMOV_GR8:
12491 case X86::CMOV_FR32:
12492 case X86::CMOV_FR64:
12493 case X86::CMOV_V4F32:
12494 case X86::CMOV_V2F64:
12495 case X86::CMOV_V2I64:
12496 case X86::CMOV_V8F32:
12497 case X86::CMOV_V4F64:
12498 case X86::CMOV_V4I64:
12499 case X86::CMOV_GR16:
12500 case X86::CMOV_GR32:
12501 case X86::CMOV_RFP32:
12502 case X86::CMOV_RFP64:
12503 case X86::CMOV_RFP80:
12504 return EmitLoweredSelect(MI, BB);
12506 case X86::FP32_TO_INT16_IN_MEM:
12507 case X86::FP32_TO_INT32_IN_MEM:
12508 case X86::FP32_TO_INT64_IN_MEM:
12509 case X86::FP64_TO_INT16_IN_MEM:
12510 case X86::FP64_TO_INT32_IN_MEM:
12511 case X86::FP64_TO_INT64_IN_MEM:
12512 case X86::FP80_TO_INT16_IN_MEM:
12513 case X86::FP80_TO_INT32_IN_MEM:
12514 case X86::FP80_TO_INT64_IN_MEM: {
12515 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12516 DebugLoc DL = MI->getDebugLoc();
12518 // Change the floating point control register to use "round towards zero"
12519 // mode when truncating to an integer value.
12520 MachineFunction *F = BB->getParent();
12521 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
12522 addFrameReference(BuildMI(*BB, MI, DL,
12523 TII->get(X86::FNSTCW16m)), CWFrameIdx);
12525 // Load the old value of the high byte of the control word...
12527 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
12528 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
12531 // Set the high part to be round to zero...
12532 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
12535 // Reload the modified control word now...
12536 addFrameReference(BuildMI(*BB, MI, DL,
12537 TII->get(X86::FLDCW16m)), CWFrameIdx);
12539 // Restore the memory image of control word to original value
12540 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
12543 // Get the X86 opcode to use.
12545 switch (MI->getOpcode()) {
12546 default: llvm_unreachable("illegal opcode!");
12547 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
12548 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
12549 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
12550 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
12551 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
12552 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
12553 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
12554 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
12555 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
12559 MachineOperand &Op = MI->getOperand(0);
12561 AM.BaseType = X86AddressMode::RegBase;
12562 AM.Base.Reg = Op.getReg();
12564 AM.BaseType = X86AddressMode::FrameIndexBase;
12565 AM.Base.FrameIndex = Op.getIndex();
12567 Op = MI->getOperand(1);
12569 AM.Scale = Op.getImm();
12570 Op = MI->getOperand(2);
12572 AM.IndexReg = Op.getImm();
12573 Op = MI->getOperand(3);
12574 if (Op.isGlobal()) {
12575 AM.GV = Op.getGlobal();
12577 AM.Disp = Op.getImm();
12579 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
12580 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
12582 // Reload the original control word now.
12583 addFrameReference(BuildMI(*BB, MI, DL,
12584 TII->get(X86::FLDCW16m)), CWFrameIdx);
12586 MI->eraseFromParent(); // The pseudo instruction is gone now.
12589 // String/text processing lowering.
12590 case X86::PCMPISTRM128REG:
12591 case X86::VPCMPISTRM128REG:
12592 return EmitPCMP(MI, BB, 3, false /* in-mem */);
12593 case X86::PCMPISTRM128MEM:
12594 case X86::VPCMPISTRM128MEM:
12595 return EmitPCMP(MI, BB, 3, true /* in-mem */);
12596 case X86::PCMPESTRM128REG:
12597 case X86::VPCMPESTRM128REG:
12598 return EmitPCMP(MI, BB, 5, false /* in mem */);
12599 case X86::PCMPESTRM128MEM:
12600 case X86::VPCMPESTRM128MEM:
12601 return EmitPCMP(MI, BB, 5, true /* in mem */);
12603 // Thread synchronization.
12605 return EmitMonitor(MI, BB);
12607 return EmitMwait(MI, BB);
12609 // Atomic Lowering.
12610 case X86::ATOMAND32:
12611 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
12612 X86::AND32ri, X86::MOV32rm,
12614 X86::NOT32r, X86::EAX,
12615 &X86::GR32RegClass);
12616 case X86::ATOMOR32:
12617 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
12618 X86::OR32ri, X86::MOV32rm,
12620 X86::NOT32r, X86::EAX,
12621 &X86::GR32RegClass);
12622 case X86::ATOMXOR32:
12623 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
12624 X86::XOR32ri, X86::MOV32rm,
12626 X86::NOT32r, X86::EAX,
12627 &X86::GR32RegClass);
12628 case X86::ATOMNAND32:
12629 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
12630 X86::AND32ri, X86::MOV32rm,
12632 X86::NOT32r, X86::EAX,
12633 &X86::GR32RegClass, true);
12634 case X86::ATOMMIN32:
12635 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
12636 case X86::ATOMMAX32:
12637 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
12638 case X86::ATOMUMIN32:
12639 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
12640 case X86::ATOMUMAX32:
12641 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
12643 case X86::ATOMAND16:
12644 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
12645 X86::AND16ri, X86::MOV16rm,
12647 X86::NOT16r, X86::AX,
12648 &X86::GR16RegClass);
12649 case X86::ATOMOR16:
12650 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
12651 X86::OR16ri, X86::MOV16rm,
12653 X86::NOT16r, X86::AX,
12654 &X86::GR16RegClass);
12655 case X86::ATOMXOR16:
12656 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
12657 X86::XOR16ri, X86::MOV16rm,
12659 X86::NOT16r, X86::AX,
12660 &X86::GR16RegClass);
12661 case X86::ATOMNAND16:
12662 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
12663 X86::AND16ri, X86::MOV16rm,
12665 X86::NOT16r, X86::AX,
12666 &X86::GR16RegClass, true);
12667 case X86::ATOMMIN16:
12668 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
12669 case X86::ATOMMAX16:
12670 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
12671 case X86::ATOMUMIN16:
12672 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
12673 case X86::ATOMUMAX16:
12674 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
12676 case X86::ATOMAND8:
12677 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
12678 X86::AND8ri, X86::MOV8rm,
12680 X86::NOT8r, X86::AL,
12681 &X86::GR8RegClass);
12683 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
12684 X86::OR8ri, X86::MOV8rm,
12686 X86::NOT8r, X86::AL,
12687 &X86::GR8RegClass);
12688 case X86::ATOMXOR8:
12689 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
12690 X86::XOR8ri, X86::MOV8rm,
12692 X86::NOT8r, X86::AL,
12693 &X86::GR8RegClass);
12694 case X86::ATOMNAND8:
12695 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
12696 X86::AND8ri, X86::MOV8rm,
12698 X86::NOT8r, X86::AL,
12699 &X86::GR8RegClass, true);
12700 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
12701 // This group is for 64-bit host.
12702 case X86::ATOMAND64:
12703 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
12704 X86::AND64ri32, X86::MOV64rm,
12706 X86::NOT64r, X86::RAX,
12707 &X86::GR64RegClass);
12708 case X86::ATOMOR64:
12709 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
12710 X86::OR64ri32, X86::MOV64rm,
12712 X86::NOT64r, X86::RAX,
12713 &X86::GR64RegClass);
12714 case X86::ATOMXOR64:
12715 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
12716 X86::XOR64ri32, X86::MOV64rm,
12718 X86::NOT64r, X86::RAX,
12719 &X86::GR64RegClass);
12720 case X86::ATOMNAND64:
12721 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
12722 X86::AND64ri32, X86::MOV64rm,
12724 X86::NOT64r, X86::RAX,
12725 &X86::GR64RegClass, true);
12726 case X86::ATOMMIN64:
12727 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
12728 case X86::ATOMMAX64:
12729 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
12730 case X86::ATOMUMIN64:
12731 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
12732 case X86::ATOMUMAX64:
12733 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
12735 // This group does 64-bit operations on a 32-bit host.
12736 case X86::ATOMAND6432:
12737 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12738 X86::AND32rr, X86::AND32rr,
12739 X86::AND32ri, X86::AND32ri,
12741 case X86::ATOMOR6432:
12742 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12743 X86::OR32rr, X86::OR32rr,
12744 X86::OR32ri, X86::OR32ri,
12746 case X86::ATOMXOR6432:
12747 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12748 X86::XOR32rr, X86::XOR32rr,
12749 X86::XOR32ri, X86::XOR32ri,
12751 case X86::ATOMNAND6432:
12752 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12753 X86::AND32rr, X86::AND32rr,
12754 X86::AND32ri, X86::AND32ri,
12756 case X86::ATOMADD6432:
12757 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12758 X86::ADD32rr, X86::ADC32rr,
12759 X86::ADD32ri, X86::ADC32ri,
12761 case X86::ATOMSUB6432:
12762 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12763 X86::SUB32rr, X86::SBB32rr,
12764 X86::SUB32ri, X86::SBB32ri,
12766 case X86::ATOMSWAP6432:
12767 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12768 X86::MOV32rr, X86::MOV32rr,
12769 X86::MOV32ri, X86::MOV32ri,
12771 case X86::VASTART_SAVE_XMM_REGS:
12772 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
12774 case X86::VAARG_64:
12775 return EmitVAARG64WithCustomInserter(MI, BB);
12779 //===----------------------------------------------------------------------===//
12780 // X86 Optimization Hooks
12781 //===----------------------------------------------------------------------===//
12783 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
12786 const SelectionDAG &DAG,
12787 unsigned Depth) const {
12788 unsigned BitWidth = KnownZero.getBitWidth();
12789 unsigned Opc = Op.getOpcode();
12790 assert((Opc >= ISD::BUILTIN_OP_END ||
12791 Opc == ISD::INTRINSIC_WO_CHAIN ||
12792 Opc == ISD::INTRINSIC_W_CHAIN ||
12793 Opc == ISD::INTRINSIC_VOID) &&
12794 "Should use MaskedValueIsZero if you don't know whether Op"
12795 " is a target node!");
12797 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
12811 // These nodes' second result is a boolean.
12812 if (Op.getResNo() == 0)
12815 case X86ISD::SETCC:
12816 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
12818 case ISD::INTRINSIC_WO_CHAIN: {
12819 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
12820 unsigned NumLoBits = 0;
12823 case Intrinsic::x86_sse_movmsk_ps:
12824 case Intrinsic::x86_avx_movmsk_ps_256:
12825 case Intrinsic::x86_sse2_movmsk_pd:
12826 case Intrinsic::x86_avx_movmsk_pd_256:
12827 case Intrinsic::x86_mmx_pmovmskb:
12828 case Intrinsic::x86_sse2_pmovmskb_128:
12829 case Intrinsic::x86_avx2_pmovmskb: {
12830 // High bits of movmskp{s|d}, pmovmskb are known zero.
12832 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
12833 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
12834 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
12835 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
12836 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
12837 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
12838 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
12839 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
12841 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
12850 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
12851 unsigned Depth) const {
12852 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
12853 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
12854 return Op.getValueType().getScalarType().getSizeInBits();
12860 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
12861 /// node is a GlobalAddress + offset.
12862 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
12863 const GlobalValue* &GA,
12864 int64_t &Offset) const {
12865 if (N->getOpcode() == X86ISD::Wrapper) {
12866 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
12867 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
12868 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
12872 return TargetLowering::isGAPlusOffset(N, GA, Offset);
12875 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
12876 /// same as extracting the high 128-bit part of 256-bit vector and then
12877 /// inserting the result into the low part of a new 256-bit vector
12878 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
12879 EVT VT = SVOp->getValueType(0);
12880 unsigned NumElems = VT.getVectorNumElements();
12882 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
12883 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
12884 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
12885 SVOp->getMaskElt(j) >= 0)
12891 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
12892 /// same as extracting the low 128-bit part of 256-bit vector and then
12893 /// inserting the result into the high part of a new 256-bit vector
12894 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
12895 EVT VT = SVOp->getValueType(0);
12896 unsigned NumElems = VT.getVectorNumElements();
12898 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
12899 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
12900 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
12901 SVOp->getMaskElt(j) >= 0)
12907 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
12908 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
12909 TargetLowering::DAGCombinerInfo &DCI,
12910 const X86Subtarget* Subtarget) {
12911 DebugLoc dl = N->getDebugLoc();
12912 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
12913 SDValue V1 = SVOp->getOperand(0);
12914 SDValue V2 = SVOp->getOperand(1);
12915 EVT VT = SVOp->getValueType(0);
12916 unsigned NumElems = VT.getVectorNumElements();
12918 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
12919 V2.getOpcode() == ISD::CONCAT_VECTORS) {
12923 // V UNDEF BUILD_VECTOR UNDEF
12925 // CONCAT_VECTOR CONCAT_VECTOR
12928 // RESULT: V + zero extended
12930 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
12931 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
12932 V1.getOperand(1).getOpcode() != ISD::UNDEF)
12935 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
12938 // To match the shuffle mask, the first half of the mask should
12939 // be exactly the first vector, and all the rest a splat with the
12940 // first element of the second one.
12941 for (unsigned i = 0; i != NumElems/2; ++i)
12942 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
12943 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
12946 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
12947 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
12948 if (Ld->hasNUsesOfValue(1, 0)) {
12949 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
12950 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
12952 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2,
12954 Ld->getPointerInfo(),
12955 Ld->getAlignment(),
12956 false/*isVolatile*/, true/*ReadMem*/,
12957 false/*WriteMem*/);
12958 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
12962 // Emit a zeroed vector and insert the desired subvector on its
12964 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
12965 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
12966 return DCI.CombineTo(N, InsV);
12969 //===--------------------------------------------------------------------===//
12970 // Combine some shuffles into subvector extracts and inserts:
12973 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
12974 if (isShuffleHigh128VectorInsertLow(SVOp)) {
12975 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
12976 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
12977 return DCI.CombineTo(N, InsV);
12980 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
12981 if (isShuffleLow128VectorInsertHigh(SVOp)) {
12982 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
12983 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
12984 return DCI.CombineTo(N, InsV);
12990 /// PerformShuffleCombine - Performs several different shuffle combines.
12991 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
12992 TargetLowering::DAGCombinerInfo &DCI,
12993 const X86Subtarget *Subtarget) {
12994 DebugLoc dl = N->getDebugLoc();
12995 EVT VT = N->getValueType(0);
12997 // Don't create instructions with illegal types after legalize types has run.
12998 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12999 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
13002 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
13003 if (Subtarget->hasAVX() && VT.getSizeInBits() == 256 &&
13004 N->getOpcode() == ISD::VECTOR_SHUFFLE)
13005 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
13007 // Only handle 128 wide vector from here on.
13008 if (VT.getSizeInBits() != 128)
13011 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
13012 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
13013 // consecutive, non-overlapping, and in the right order.
13014 SmallVector<SDValue, 16> Elts;
13015 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
13016 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
13018 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG);
13022 /// DCI, PerformTruncateCombine - Converts truncate operation to
13023 /// a sequence of vector shuffle operations.
13024 /// It is possible when we truncate 256-bit vector to 128-bit vector
13026 SDValue X86TargetLowering::PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
13027 DAGCombinerInfo &DCI) const {
13028 if (!DCI.isBeforeLegalizeOps())
13031 if (!Subtarget->hasAVX())
13034 EVT VT = N->getValueType(0);
13035 SDValue Op = N->getOperand(0);
13036 EVT OpVT = Op.getValueType();
13037 DebugLoc dl = N->getDebugLoc();
13039 if ((VT == MVT::v4i32) && (OpVT == MVT::v4i64)) {
13041 if (Subtarget->hasAVX2()) {
13042 // AVX2: v4i64 -> v4i32
13045 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
13047 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v8i32, Op);
13048 Op = DAG.getVectorShuffle(MVT::v8i32, dl, Op, DAG.getUNDEF(MVT::v8i32),
13051 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, Op,
13052 DAG.getIntPtrConstant(0));
13055 // AVX: v4i64 -> v4i32
13056 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op,
13057 DAG.getIntPtrConstant(0));
13059 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op,
13060 DAG.getIntPtrConstant(2));
13062 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpLo);
13063 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpHi);
13066 static const int ShufMask1[] = {0, 2, 0, 0};
13068 OpLo = DAG.getVectorShuffle(VT, dl, OpLo, DAG.getUNDEF(VT), ShufMask1);
13069 OpHi = DAG.getVectorShuffle(VT, dl, OpHi, DAG.getUNDEF(VT), ShufMask1);
13072 static const int ShufMask2[] = {0, 1, 4, 5};
13074 return DAG.getVectorShuffle(VT, dl, OpLo, OpHi, ShufMask2);
13077 if ((VT == MVT::v8i16) && (OpVT == MVT::v8i32)) {
13079 if (Subtarget->hasAVX2()) {
13080 // AVX2: v8i32 -> v8i16
13082 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v32i8, Op);
13085 SmallVector<SDValue,32> pshufbMask;
13086 for (unsigned i = 0; i < 2; ++i) {
13087 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
13088 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
13089 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
13090 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
13091 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
13092 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
13093 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
13094 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
13095 for (unsigned j = 0; j < 8; ++j)
13096 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
13098 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v32i8,
13099 &pshufbMask[0], 32);
13100 Op = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v32i8, Op, BV);
13102 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4i64, Op);
13104 static const int ShufMask[] = {0, 2, -1, -1};
13105 Op = DAG.getVectorShuffle(MVT::v4i64, dl, Op, DAG.getUNDEF(MVT::v4i64),
13108 Op = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op,
13109 DAG.getIntPtrConstant(0));
13111 return DAG.getNode(ISD::BITCAST, dl, VT, Op);
13114 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i32, Op,
13115 DAG.getIntPtrConstant(0));
13117 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i32, Op,
13118 DAG.getIntPtrConstant(4));
13120 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLo);
13121 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpHi);
13124 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
13125 -1, -1, -1, -1, -1, -1, -1, -1};
13127 OpLo = DAG.getVectorShuffle(MVT::v16i8, dl, OpLo, DAG.getUNDEF(MVT::v16i8),
13129 OpHi = DAG.getVectorShuffle(MVT::v16i8, dl, OpHi, DAG.getUNDEF(MVT::v16i8),
13132 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpLo);
13133 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpHi);
13136 static const int ShufMask2[] = {0, 1, 4, 5};
13138 SDValue res = DAG.getVectorShuffle(MVT::v4i32, dl, OpLo, OpHi, ShufMask2);
13139 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, res);
13145 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
13146 /// specific shuffle of a load can be folded into a single element load.
13147 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
13148 /// shuffles have been customed lowered so we need to handle those here.
13149 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
13150 TargetLowering::DAGCombinerInfo &DCI) {
13151 if (DCI.isBeforeLegalizeOps())
13154 SDValue InVec = N->getOperand(0);
13155 SDValue EltNo = N->getOperand(1);
13157 if (!isa<ConstantSDNode>(EltNo))
13160 EVT VT = InVec.getValueType();
13162 bool HasShuffleIntoBitcast = false;
13163 if (InVec.getOpcode() == ISD::BITCAST) {
13164 // Don't duplicate a load with other uses.
13165 if (!InVec.hasOneUse())
13167 EVT BCVT = InVec.getOperand(0).getValueType();
13168 if (BCVT.getVectorNumElements() != VT.getVectorNumElements())
13170 InVec = InVec.getOperand(0);
13171 HasShuffleIntoBitcast = true;
13174 if (!isTargetShuffle(InVec.getOpcode()))
13177 // Don't duplicate a load with other uses.
13178 if (!InVec.hasOneUse())
13181 SmallVector<int, 16> ShuffleMask;
13183 if (!getTargetShuffleMask(InVec.getNode(), VT.getSimpleVT(), ShuffleMask,
13187 // Select the input vector, guarding against out of range extract vector.
13188 unsigned NumElems = VT.getVectorNumElements();
13189 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
13190 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
13191 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
13192 : InVec.getOperand(1);
13194 // If inputs to shuffle are the same for both ops, then allow 2 uses
13195 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
13197 if (LdNode.getOpcode() == ISD::BITCAST) {
13198 // Don't duplicate a load with other uses.
13199 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
13202 AllowedUses = 1; // only allow 1 load use if we have a bitcast
13203 LdNode = LdNode.getOperand(0);
13206 if (!ISD::isNormalLoad(LdNode.getNode()))
13209 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
13211 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
13214 if (HasShuffleIntoBitcast) {
13215 // If there's a bitcast before the shuffle, check if the load type and
13216 // alignment is valid.
13217 unsigned Align = LN0->getAlignment();
13218 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13219 unsigned NewAlign = TLI.getTargetData()->
13220 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
13222 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
13226 // All checks match so transform back to vector_shuffle so that DAG combiner
13227 // can finish the job
13228 DebugLoc dl = N->getDebugLoc();
13230 // Create shuffle node taking into account the case that its a unary shuffle
13231 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1);
13232 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl,
13233 InVec.getOperand(0), Shuffle,
13235 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
13236 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
13240 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
13241 /// generation and convert it from being a bunch of shuffles and extracts
13242 /// to a simple store and scalar loads to extract the elements.
13243 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
13244 TargetLowering::DAGCombinerInfo &DCI) {
13245 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
13246 if (NewOp.getNode())
13249 SDValue InputVector = N->getOperand(0);
13251 // Only operate on vectors of 4 elements, where the alternative shuffling
13252 // gets to be more expensive.
13253 if (InputVector.getValueType() != MVT::v4i32)
13256 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
13257 // single use which is a sign-extend or zero-extend, and all elements are
13259 SmallVector<SDNode *, 4> Uses;
13260 unsigned ExtractedElements = 0;
13261 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
13262 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
13263 if (UI.getUse().getResNo() != InputVector.getResNo())
13266 SDNode *Extract = *UI;
13267 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
13270 if (Extract->getValueType(0) != MVT::i32)
13272 if (!Extract->hasOneUse())
13274 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
13275 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
13277 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
13280 // Record which element was extracted.
13281 ExtractedElements |=
13282 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
13284 Uses.push_back(Extract);
13287 // If not all the elements were used, this may not be worthwhile.
13288 if (ExtractedElements != 15)
13291 // Ok, we've now decided to do the transformation.
13292 DebugLoc dl = InputVector.getDebugLoc();
13294 // Store the value to a temporary stack slot.
13295 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
13296 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
13297 MachinePointerInfo(), false, false, 0);
13299 // Replace each use (extract) with a load of the appropriate element.
13300 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
13301 UE = Uses.end(); UI != UE; ++UI) {
13302 SDNode *Extract = *UI;
13304 // cOMpute the element's address.
13305 SDValue Idx = Extract->getOperand(1);
13307 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
13308 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
13309 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13310 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
13312 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
13313 StackPtr, OffsetVal);
13315 // Load the scalar.
13316 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
13317 ScalarAddr, MachinePointerInfo(),
13318 false, false, false, 0);
13320 // Replace the exact with the load.
13321 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
13324 // The replacement was made in place; don't return anything.
13328 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
13330 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
13331 TargetLowering::DAGCombinerInfo &DCI,
13332 const X86Subtarget *Subtarget) {
13333 DebugLoc DL = N->getDebugLoc();
13334 SDValue Cond = N->getOperand(0);
13335 // Get the LHS/RHS of the select.
13336 SDValue LHS = N->getOperand(1);
13337 SDValue RHS = N->getOperand(2);
13338 EVT VT = LHS.getValueType();
13340 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
13341 // instructions match the semantics of the common C idiom x<y?x:y but not
13342 // x<=y?x:y, because of how they handle negative zero (which can be
13343 // ignored in unsafe-math mode).
13344 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
13345 VT != MVT::f80 && DAG.getTargetLoweringInfo().isTypeLegal(VT) &&
13346 (Subtarget->hasSSE2() ||
13347 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
13348 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
13350 unsigned Opcode = 0;
13351 // Check for x CC y ? x : y.
13352 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
13353 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
13357 // Converting this to a min would handle NaNs incorrectly, and swapping
13358 // the operands would cause it to handle comparisons between positive
13359 // and negative zero incorrectly.
13360 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
13361 if (!DAG.getTarget().Options.UnsafeFPMath &&
13362 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
13364 std::swap(LHS, RHS);
13366 Opcode = X86ISD::FMIN;
13369 // Converting this to a min would handle comparisons between positive
13370 // and negative zero incorrectly.
13371 if (!DAG.getTarget().Options.UnsafeFPMath &&
13372 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
13374 Opcode = X86ISD::FMIN;
13377 // Converting this to a min would handle both negative zeros and NaNs
13378 // incorrectly, but we can swap the operands to fix both.
13379 std::swap(LHS, RHS);
13383 Opcode = X86ISD::FMIN;
13387 // Converting this to a max would handle comparisons between positive
13388 // and negative zero incorrectly.
13389 if (!DAG.getTarget().Options.UnsafeFPMath &&
13390 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
13392 Opcode = X86ISD::FMAX;
13395 // Converting this to a max would handle NaNs incorrectly, and swapping
13396 // the operands would cause it to handle comparisons between positive
13397 // and negative zero incorrectly.
13398 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
13399 if (!DAG.getTarget().Options.UnsafeFPMath &&
13400 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
13402 std::swap(LHS, RHS);
13404 Opcode = X86ISD::FMAX;
13407 // Converting this to a max would handle both negative zeros and NaNs
13408 // incorrectly, but we can swap the operands to fix both.
13409 std::swap(LHS, RHS);
13413 Opcode = X86ISD::FMAX;
13416 // Check for x CC y ? y : x -- a min/max with reversed arms.
13417 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
13418 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
13422 // Converting this to a min would handle comparisons between positive
13423 // and negative zero incorrectly, and swapping the operands would
13424 // cause it to handle NaNs incorrectly.
13425 if (!DAG.getTarget().Options.UnsafeFPMath &&
13426 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
13427 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
13429 std::swap(LHS, RHS);
13431 Opcode = X86ISD::FMIN;
13434 // Converting this to a min would handle NaNs incorrectly.
13435 if (!DAG.getTarget().Options.UnsafeFPMath &&
13436 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
13438 Opcode = X86ISD::FMIN;
13441 // Converting this to a min would handle both negative zeros and NaNs
13442 // incorrectly, but we can swap the operands to fix both.
13443 std::swap(LHS, RHS);
13447 Opcode = X86ISD::FMIN;
13451 // Converting this to a max would handle NaNs incorrectly.
13452 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
13454 Opcode = X86ISD::FMAX;
13457 // Converting this to a max would handle comparisons between positive
13458 // and negative zero incorrectly, and swapping the operands would
13459 // cause it to handle NaNs incorrectly.
13460 if (!DAG.getTarget().Options.UnsafeFPMath &&
13461 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
13462 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
13464 std::swap(LHS, RHS);
13466 Opcode = X86ISD::FMAX;
13469 // Converting this to a max would handle both negative zeros and NaNs
13470 // incorrectly, but we can swap the operands to fix both.
13471 std::swap(LHS, RHS);
13475 Opcode = X86ISD::FMAX;
13481 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
13484 // If this is a select between two integer constants, try to do some
13486 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
13487 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
13488 // Don't do this for crazy integer types.
13489 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
13490 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
13491 // so that TrueC (the true value) is larger than FalseC.
13492 bool NeedsCondInvert = false;
13494 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
13495 // Efficiently invertible.
13496 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
13497 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
13498 isa<ConstantSDNode>(Cond.getOperand(1))))) {
13499 NeedsCondInvert = true;
13500 std::swap(TrueC, FalseC);
13503 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
13504 if (FalseC->getAPIntValue() == 0 &&
13505 TrueC->getAPIntValue().isPowerOf2()) {
13506 if (NeedsCondInvert) // Invert the condition if needed.
13507 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13508 DAG.getConstant(1, Cond.getValueType()));
13510 // Zero extend the condition if needed.
13511 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
13513 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
13514 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
13515 DAG.getConstant(ShAmt, MVT::i8));
13518 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
13519 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
13520 if (NeedsCondInvert) // Invert the condition if needed.
13521 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13522 DAG.getConstant(1, Cond.getValueType()));
13524 // Zero extend the condition if needed.
13525 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
13526 FalseC->getValueType(0), Cond);
13527 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13528 SDValue(FalseC, 0));
13531 // Optimize cases that will turn into an LEA instruction. This requires
13532 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
13533 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
13534 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
13535 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
13537 bool isFastMultiplier = false;
13539 switch ((unsigned char)Diff) {
13541 case 1: // result = add base, cond
13542 case 2: // result = lea base( , cond*2)
13543 case 3: // result = lea base(cond, cond*2)
13544 case 4: // result = lea base( , cond*4)
13545 case 5: // result = lea base(cond, cond*4)
13546 case 8: // result = lea base( , cond*8)
13547 case 9: // result = lea base(cond, cond*8)
13548 isFastMultiplier = true;
13553 if (isFastMultiplier) {
13554 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
13555 if (NeedsCondInvert) // Invert the condition if needed.
13556 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13557 DAG.getConstant(1, Cond.getValueType()));
13559 // Zero extend the condition if needed.
13560 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
13562 // Scale the condition by the difference.
13564 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
13565 DAG.getConstant(Diff, Cond.getValueType()));
13567 // Add the base if non-zero.
13568 if (FalseC->getAPIntValue() != 0)
13569 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13570 SDValue(FalseC, 0));
13577 // Canonicalize max and min:
13578 // (x > y) ? x : y -> (x >= y) ? x : y
13579 // (x < y) ? x : y -> (x <= y) ? x : y
13580 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
13581 // the need for an extra compare
13582 // against zero. e.g.
13583 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
13585 // testl %edi, %edi
13587 // cmovgl %edi, %eax
13591 // cmovsl %eax, %edi
13592 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
13593 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
13594 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
13595 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
13600 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
13601 Cond = DAG.getSetCC(Cond.getDebugLoc(), Cond.getValueType(),
13602 Cond.getOperand(0), Cond.getOperand(1), NewCC);
13603 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
13608 // If we know that this node is legal then we know that it is going to be
13609 // matched by one of the SSE/AVX BLEND instructions. These instructions only
13610 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
13611 // to simplify previous instructions.
13612 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13613 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
13614 !DCI.isBeforeLegalize() && TLI.isOperationLegal(ISD::VSELECT, VT)) {
13615 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
13617 // Don't optimize vector selects that map to mask-registers.
13621 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
13622 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
13624 APInt KnownZero, KnownOne;
13625 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
13626 DCI.isBeforeLegalizeOps());
13627 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
13628 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
13629 DCI.CommitTargetLoweringOpt(TLO);
13635 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
13636 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
13637 TargetLowering::DAGCombinerInfo &DCI) {
13638 DebugLoc DL = N->getDebugLoc();
13640 // If the flag operand isn't dead, don't touch this CMOV.
13641 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
13644 SDValue FalseOp = N->getOperand(0);
13645 SDValue TrueOp = N->getOperand(1);
13646 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
13647 SDValue Cond = N->getOperand(3);
13648 if (CC == X86::COND_E || CC == X86::COND_NE) {
13649 switch (Cond.getOpcode()) {
13653 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
13654 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
13655 return (CC == X86::COND_E) ? FalseOp : TrueOp;
13659 // If this is a select between two integer constants, try to do some
13660 // optimizations. Note that the operands are ordered the opposite of SELECT
13662 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
13663 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
13664 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
13665 // larger than FalseC (the false value).
13666 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
13667 CC = X86::GetOppositeBranchCondition(CC);
13668 std::swap(TrueC, FalseC);
13671 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
13672 // This is efficient for any integer data type (including i8/i16) and
13674 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
13675 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13676 DAG.getConstant(CC, MVT::i8), Cond);
13678 // Zero extend the condition if needed.
13679 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
13681 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
13682 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
13683 DAG.getConstant(ShAmt, MVT::i8));
13684 if (N->getNumValues() == 2) // Dead flag value?
13685 return DCI.CombineTo(N, Cond, SDValue());
13689 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
13690 // for any integer data type, including i8/i16.
13691 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
13692 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13693 DAG.getConstant(CC, MVT::i8), Cond);
13695 // Zero extend the condition if needed.
13696 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
13697 FalseC->getValueType(0), Cond);
13698 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13699 SDValue(FalseC, 0));
13701 if (N->getNumValues() == 2) // Dead flag value?
13702 return DCI.CombineTo(N, Cond, SDValue());
13706 // Optimize cases that will turn into an LEA instruction. This requires
13707 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
13708 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
13709 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
13710 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
13712 bool isFastMultiplier = false;
13714 switch ((unsigned char)Diff) {
13716 case 1: // result = add base, cond
13717 case 2: // result = lea base( , cond*2)
13718 case 3: // result = lea base(cond, cond*2)
13719 case 4: // result = lea base( , cond*4)
13720 case 5: // result = lea base(cond, cond*4)
13721 case 8: // result = lea base( , cond*8)
13722 case 9: // result = lea base(cond, cond*8)
13723 isFastMultiplier = true;
13728 if (isFastMultiplier) {
13729 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
13730 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13731 DAG.getConstant(CC, MVT::i8), Cond);
13732 // Zero extend the condition if needed.
13733 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
13735 // Scale the condition by the difference.
13737 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
13738 DAG.getConstant(Diff, Cond.getValueType()));
13740 // Add the base if non-zero.
13741 if (FalseC->getAPIntValue() != 0)
13742 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13743 SDValue(FalseC, 0));
13744 if (N->getNumValues() == 2) // Dead flag value?
13745 return DCI.CombineTo(N, Cond, SDValue());
13755 /// PerformMulCombine - Optimize a single multiply with constant into two
13756 /// in order to implement it with two cheaper instructions, e.g.
13757 /// LEA + SHL, LEA + LEA.
13758 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
13759 TargetLowering::DAGCombinerInfo &DCI) {
13760 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
13763 EVT VT = N->getValueType(0);
13764 if (VT != MVT::i64)
13767 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
13770 uint64_t MulAmt = C->getZExtValue();
13771 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
13774 uint64_t MulAmt1 = 0;
13775 uint64_t MulAmt2 = 0;
13776 if ((MulAmt % 9) == 0) {
13778 MulAmt2 = MulAmt / 9;
13779 } else if ((MulAmt % 5) == 0) {
13781 MulAmt2 = MulAmt / 5;
13782 } else if ((MulAmt % 3) == 0) {
13784 MulAmt2 = MulAmt / 3;
13787 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
13788 DebugLoc DL = N->getDebugLoc();
13790 if (isPowerOf2_64(MulAmt2) &&
13791 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
13792 // If second multiplifer is pow2, issue it first. We want the multiply by
13793 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
13795 std::swap(MulAmt1, MulAmt2);
13798 if (isPowerOf2_64(MulAmt1))
13799 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
13800 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
13802 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
13803 DAG.getConstant(MulAmt1, VT));
13805 if (isPowerOf2_64(MulAmt2))
13806 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
13807 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
13809 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
13810 DAG.getConstant(MulAmt2, VT));
13812 // Do not add new nodes to DAG combiner worklist.
13813 DCI.CombineTo(N, NewMul, false);
13818 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
13819 SDValue N0 = N->getOperand(0);
13820 SDValue N1 = N->getOperand(1);
13821 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
13822 EVT VT = N0.getValueType();
13824 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
13825 // since the result of setcc_c is all zero's or all ones.
13826 if (VT.isInteger() && !VT.isVector() &&
13827 N1C && N0.getOpcode() == ISD::AND &&
13828 N0.getOperand(1).getOpcode() == ISD::Constant) {
13829 SDValue N00 = N0.getOperand(0);
13830 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
13831 ((N00.getOpcode() == ISD::ANY_EXTEND ||
13832 N00.getOpcode() == ISD::ZERO_EXTEND) &&
13833 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
13834 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
13835 APInt ShAmt = N1C->getAPIntValue();
13836 Mask = Mask.shl(ShAmt);
13838 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
13839 N00, DAG.getConstant(Mask, VT));
13844 // Hardware support for vector shifts is sparse which makes us scalarize the
13845 // vector operations in many cases. Also, on sandybridge ADD is faster than
13847 // (shl V, 1) -> add V,V
13848 if (isSplatVector(N1.getNode())) {
13849 assert(N0.getValueType().isVector() && "Invalid vector shift type");
13850 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1->getOperand(0));
13851 // We shift all of the values by one. In many cases we do not have
13852 // hardware support for this operation. This is better expressed as an ADD
13854 if (N1C && (1 == N1C->getZExtValue())) {
13855 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N0);
13862 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
13864 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
13865 TargetLowering::DAGCombinerInfo &DCI,
13866 const X86Subtarget *Subtarget) {
13867 EVT VT = N->getValueType(0);
13868 if (N->getOpcode() == ISD::SHL) {
13869 SDValue V = PerformSHLCombine(N, DAG);
13870 if (V.getNode()) return V;
13873 // On X86 with SSE2 support, we can transform this to a vector shift if
13874 // all elements are shifted by the same amount. We can't do this in legalize
13875 // because the a constant vector is typically transformed to a constant pool
13876 // so we have no knowledge of the shift amount.
13877 if (!Subtarget->hasSSE2())
13880 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
13881 (!Subtarget->hasAVX2() ||
13882 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
13885 SDValue ShAmtOp = N->getOperand(1);
13886 EVT EltVT = VT.getVectorElementType();
13887 DebugLoc DL = N->getDebugLoc();
13888 SDValue BaseShAmt = SDValue();
13889 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
13890 unsigned NumElts = VT.getVectorNumElements();
13892 for (; i != NumElts; ++i) {
13893 SDValue Arg = ShAmtOp.getOperand(i);
13894 if (Arg.getOpcode() == ISD::UNDEF) continue;
13898 // Handle the case where the build_vector is all undef
13899 // FIXME: Should DAG allow this?
13903 for (; i != NumElts; ++i) {
13904 SDValue Arg = ShAmtOp.getOperand(i);
13905 if (Arg.getOpcode() == ISD::UNDEF) continue;
13906 if (Arg != BaseShAmt) {
13910 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
13911 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
13912 SDValue InVec = ShAmtOp.getOperand(0);
13913 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
13914 unsigned NumElts = InVec.getValueType().getVectorNumElements();
13916 for (; i != NumElts; ++i) {
13917 SDValue Arg = InVec.getOperand(i);
13918 if (Arg.getOpcode() == ISD::UNDEF) continue;
13922 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
13923 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
13924 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex();
13925 if (C->getZExtValue() == SplatIdx)
13926 BaseShAmt = InVec.getOperand(1);
13929 if (BaseShAmt.getNode() == 0) {
13930 // Don't create instructions with illegal types after legalize
13932 if (!DAG.getTargetLoweringInfo().isTypeLegal(EltVT) &&
13933 !DCI.isBeforeLegalize())
13936 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
13937 DAG.getIntPtrConstant(0));
13942 // The shift amount is an i32.
13943 if (EltVT.bitsGT(MVT::i32))
13944 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
13945 else if (EltVT.bitsLT(MVT::i32))
13946 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt);
13948 // The shift amount is identical so we can do a vector shift.
13949 SDValue ValOp = N->getOperand(0);
13950 switch (N->getOpcode()) {
13952 llvm_unreachable("Unknown shift opcode!");
13954 switch (VT.getSimpleVT().SimpleTy) {
13955 default: return SDValue();
13962 return getTargetVShiftNode(X86ISD::VSHLI, DL, VT, ValOp, BaseShAmt, DAG);
13965 switch (VT.getSimpleVT().SimpleTy) {
13966 default: return SDValue();
13971 return getTargetVShiftNode(X86ISD::VSRAI, DL, VT, ValOp, BaseShAmt, DAG);
13974 switch (VT.getSimpleVT().SimpleTy) {
13975 default: return SDValue();
13982 return getTargetVShiftNode(X86ISD::VSRLI, DL, VT, ValOp, BaseShAmt, DAG);
13988 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
13989 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
13990 // and friends. Likewise for OR -> CMPNEQSS.
13991 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
13992 TargetLowering::DAGCombinerInfo &DCI,
13993 const X86Subtarget *Subtarget) {
13996 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
13997 // we're requiring SSE2 for both.
13998 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
13999 SDValue N0 = N->getOperand(0);
14000 SDValue N1 = N->getOperand(1);
14001 SDValue CMP0 = N0->getOperand(1);
14002 SDValue CMP1 = N1->getOperand(1);
14003 DebugLoc DL = N->getDebugLoc();
14005 // The SETCCs should both refer to the same CMP.
14006 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
14009 SDValue CMP00 = CMP0->getOperand(0);
14010 SDValue CMP01 = CMP0->getOperand(1);
14011 EVT VT = CMP00.getValueType();
14013 if (VT == MVT::f32 || VT == MVT::f64) {
14014 bool ExpectingFlags = false;
14015 // Check for any users that want flags:
14016 for (SDNode::use_iterator UI = N->use_begin(),
14018 !ExpectingFlags && UI != UE; ++UI)
14019 switch (UI->getOpcode()) {
14024 ExpectingFlags = true;
14026 case ISD::CopyToReg:
14027 case ISD::SIGN_EXTEND:
14028 case ISD::ZERO_EXTEND:
14029 case ISD::ANY_EXTEND:
14033 if (!ExpectingFlags) {
14034 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
14035 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
14037 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
14038 X86::CondCode tmp = cc0;
14043 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
14044 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
14045 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
14046 X86ISD::NodeType NTOperator = is64BitFP ?
14047 X86ISD::FSETCCsd : X86ISD::FSETCCss;
14048 // FIXME: need symbolic constants for these magic numbers.
14049 // See X86ATTInstPrinter.cpp:printSSECC().
14050 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
14051 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01,
14052 DAG.getConstant(x86cc, MVT::i8));
14053 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32,
14055 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI,
14056 DAG.getConstant(1, MVT::i32));
14057 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
14058 return OneBitOfTruth;
14066 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
14067 /// so it can be folded inside ANDNP.
14068 static bool CanFoldXORWithAllOnes(const SDNode *N) {
14069 EVT VT = N->getValueType(0);
14071 // Match direct AllOnes for 128 and 256-bit vectors
14072 if (ISD::isBuildVectorAllOnes(N))
14075 // Look through a bit convert.
14076 if (N->getOpcode() == ISD::BITCAST)
14077 N = N->getOperand(0).getNode();
14079 // Sometimes the operand may come from a insert_subvector building a 256-bit
14081 if (VT.getSizeInBits() == 256 &&
14082 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
14083 SDValue V1 = N->getOperand(0);
14084 SDValue V2 = N->getOperand(1);
14086 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
14087 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
14088 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
14089 ISD::isBuildVectorAllOnes(V2.getNode()))
14096 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
14097 TargetLowering::DAGCombinerInfo &DCI,
14098 const X86Subtarget *Subtarget) {
14099 if (DCI.isBeforeLegalizeOps())
14102 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
14106 EVT VT = N->getValueType(0);
14108 // Create ANDN, BLSI, and BLSR instructions
14109 // BLSI is X & (-X)
14110 // BLSR is X & (X-1)
14111 if (Subtarget->hasBMI() && (VT == MVT::i32 || VT == MVT::i64)) {
14112 SDValue N0 = N->getOperand(0);
14113 SDValue N1 = N->getOperand(1);
14114 DebugLoc DL = N->getDebugLoc();
14116 // Check LHS for not
14117 if (N0.getOpcode() == ISD::XOR && isAllOnes(N0.getOperand(1)))
14118 return DAG.getNode(X86ISD::ANDN, DL, VT, N0.getOperand(0), N1);
14119 // Check RHS for not
14120 if (N1.getOpcode() == ISD::XOR && isAllOnes(N1.getOperand(1)))
14121 return DAG.getNode(X86ISD::ANDN, DL, VT, N1.getOperand(0), N0);
14123 // Check LHS for neg
14124 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1) == N1 &&
14125 isZero(N0.getOperand(0)))
14126 return DAG.getNode(X86ISD::BLSI, DL, VT, N1);
14128 // Check RHS for neg
14129 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1) == N0 &&
14130 isZero(N1.getOperand(0)))
14131 return DAG.getNode(X86ISD::BLSI, DL, VT, N0);
14133 // Check LHS for X-1
14134 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
14135 isAllOnes(N0.getOperand(1)))
14136 return DAG.getNode(X86ISD::BLSR, DL, VT, N1);
14138 // Check RHS for X-1
14139 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
14140 isAllOnes(N1.getOperand(1)))
14141 return DAG.getNode(X86ISD::BLSR, DL, VT, N0);
14146 // Want to form ANDNP nodes:
14147 // 1) In the hopes of then easily combining them with OR and AND nodes
14148 // to form PBLEND/PSIGN.
14149 // 2) To match ANDN packed intrinsics
14150 if (VT != MVT::v2i64 && VT != MVT::v4i64)
14153 SDValue N0 = N->getOperand(0);
14154 SDValue N1 = N->getOperand(1);
14155 DebugLoc DL = N->getDebugLoc();
14157 // Check LHS for vnot
14158 if (N0.getOpcode() == ISD::XOR &&
14159 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
14160 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
14161 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
14163 // Check RHS for vnot
14164 if (N1.getOpcode() == ISD::XOR &&
14165 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
14166 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
14167 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
14172 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
14173 TargetLowering::DAGCombinerInfo &DCI,
14174 const X86Subtarget *Subtarget) {
14175 if (DCI.isBeforeLegalizeOps())
14178 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
14182 EVT VT = N->getValueType(0);
14184 SDValue N0 = N->getOperand(0);
14185 SDValue N1 = N->getOperand(1);
14187 // look for psign/blend
14188 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
14189 if (!Subtarget->hasSSSE3() ||
14190 (VT == MVT::v4i64 && !Subtarget->hasAVX2()))
14193 // Canonicalize pandn to RHS
14194 if (N0.getOpcode() == X86ISD::ANDNP)
14196 // or (and (m, y), (pandn m, x))
14197 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
14198 SDValue Mask = N1.getOperand(0);
14199 SDValue X = N1.getOperand(1);
14201 if (N0.getOperand(0) == Mask)
14202 Y = N0.getOperand(1);
14203 if (N0.getOperand(1) == Mask)
14204 Y = N0.getOperand(0);
14206 // Check to see if the mask appeared in both the AND and ANDNP and
14210 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
14211 // Look through mask bitcast.
14212 if (Mask.getOpcode() == ISD::BITCAST)
14213 Mask = Mask.getOperand(0);
14214 if (X.getOpcode() == ISD::BITCAST)
14215 X = X.getOperand(0);
14216 if (Y.getOpcode() == ISD::BITCAST)
14217 Y = Y.getOperand(0);
14219 EVT MaskVT = Mask.getValueType();
14221 // Validate that the Mask operand is a vector sra node.
14222 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
14223 // there is no psrai.b
14224 if (Mask.getOpcode() != X86ISD::VSRAI)
14227 // Check that the SRA is all signbits.
14228 SDValue SraC = Mask.getOperand(1);
14229 unsigned SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
14230 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
14231 if ((SraAmt + 1) != EltBits)
14234 DebugLoc DL = N->getDebugLoc();
14236 // Now we know we at least have a plendvb with the mask val. See if
14237 // we can form a psignb/w/d.
14238 // psign = x.type == y.type == mask.type && y = sub(0, x);
14239 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
14240 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
14241 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
14242 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
14243 "Unsupported VT for PSIGN");
14244 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
14245 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
14247 // PBLENDVB only available on SSE 4.1
14248 if (!Subtarget->hasSSE41())
14251 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
14253 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
14254 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
14255 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
14256 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
14257 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
14261 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
14264 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
14265 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
14267 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
14269 if (!N0.hasOneUse() || !N1.hasOneUse())
14272 SDValue ShAmt0 = N0.getOperand(1);
14273 if (ShAmt0.getValueType() != MVT::i8)
14275 SDValue ShAmt1 = N1.getOperand(1);
14276 if (ShAmt1.getValueType() != MVT::i8)
14278 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
14279 ShAmt0 = ShAmt0.getOperand(0);
14280 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
14281 ShAmt1 = ShAmt1.getOperand(0);
14283 DebugLoc DL = N->getDebugLoc();
14284 unsigned Opc = X86ISD::SHLD;
14285 SDValue Op0 = N0.getOperand(0);
14286 SDValue Op1 = N1.getOperand(0);
14287 if (ShAmt0.getOpcode() == ISD::SUB) {
14288 Opc = X86ISD::SHRD;
14289 std::swap(Op0, Op1);
14290 std::swap(ShAmt0, ShAmt1);
14293 unsigned Bits = VT.getSizeInBits();
14294 if (ShAmt1.getOpcode() == ISD::SUB) {
14295 SDValue Sum = ShAmt1.getOperand(0);
14296 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
14297 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
14298 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
14299 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
14300 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
14301 return DAG.getNode(Opc, DL, VT,
14303 DAG.getNode(ISD::TRUNCATE, DL,
14306 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
14307 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
14309 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
14310 return DAG.getNode(Opc, DL, VT,
14311 N0.getOperand(0), N1.getOperand(0),
14312 DAG.getNode(ISD::TRUNCATE, DL,
14319 // Generate NEG and CMOV for integer abs.
14320 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
14321 EVT VT = N->getValueType(0);
14323 // Since X86 does not have CMOV for 8-bit integer, we don't convert
14324 // 8-bit integer abs to NEG and CMOV.
14325 if (VT.isInteger() && VT.getSizeInBits() == 8)
14328 SDValue N0 = N->getOperand(0);
14329 SDValue N1 = N->getOperand(1);
14330 DebugLoc DL = N->getDebugLoc();
14332 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
14333 // and change it to SUB and CMOV.
14334 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
14335 N0.getOpcode() == ISD::ADD &&
14336 N0.getOperand(1) == N1 &&
14337 N1.getOpcode() == ISD::SRA &&
14338 N1.getOperand(0) == N0.getOperand(0))
14339 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
14340 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
14341 // Generate SUB & CMOV.
14342 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
14343 DAG.getConstant(0, VT), N0.getOperand(0));
14345 SDValue Ops[] = { N0.getOperand(0), Neg,
14346 DAG.getConstant(X86::COND_GE, MVT::i8),
14347 SDValue(Neg.getNode(), 1) };
14348 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue),
14349 Ops, array_lengthof(Ops));
14354 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
14355 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
14356 TargetLowering::DAGCombinerInfo &DCI,
14357 const X86Subtarget *Subtarget) {
14358 if (DCI.isBeforeLegalizeOps())
14361 if (Subtarget->hasCMov()) {
14362 SDValue RV = performIntegerAbsCombine(N, DAG);
14367 // Try forming BMI if it is available.
14368 if (!Subtarget->hasBMI())
14371 EVT VT = N->getValueType(0);
14373 if (VT != MVT::i32 && VT != MVT::i64)
14376 assert(Subtarget->hasBMI() && "Creating BLSMSK requires BMI instructions");
14378 // Create BLSMSK instructions by finding X ^ (X-1)
14379 SDValue N0 = N->getOperand(0);
14380 SDValue N1 = N->getOperand(1);
14381 DebugLoc DL = N->getDebugLoc();
14383 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
14384 isAllOnes(N0.getOperand(1)))
14385 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N1);
14387 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
14388 isAllOnes(N1.getOperand(1)))
14389 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N0);
14394 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
14395 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
14396 const X86Subtarget *Subtarget) {
14397 LoadSDNode *Ld = cast<LoadSDNode>(N);
14398 EVT RegVT = Ld->getValueType(0);
14399 EVT MemVT = Ld->getMemoryVT();
14400 DebugLoc dl = Ld->getDebugLoc();
14401 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14403 ISD::LoadExtType Ext = Ld->getExtensionType();
14405 // If this is a vector EXT Load then attempt to optimize it using a
14406 // shuffle. We need SSE4 for the shuffles.
14407 // TODO: It is possible to support ZExt by zeroing the undef values
14408 // during the shuffle phase or after the shuffle.
14409 if (RegVT.isVector() && RegVT.isInteger() &&
14410 Ext == ISD::EXTLOAD && Subtarget->hasSSE41()) {
14411 assert(MemVT != RegVT && "Cannot extend to the same type");
14412 assert(MemVT.isVector() && "Must load a vector from memory");
14414 unsigned NumElems = RegVT.getVectorNumElements();
14415 unsigned RegSz = RegVT.getSizeInBits();
14416 unsigned MemSz = MemVT.getSizeInBits();
14417 assert(RegSz > MemSz && "Register size must be greater than the mem size");
14418 // All sizes must be a power of two
14419 if (!isPowerOf2_32(RegSz * MemSz * NumElems)) return SDValue();
14421 // Attempt to load the original value using a single load op.
14422 // Find a scalar type which is equal to the loaded word size.
14423 MVT SclrLoadTy = MVT::i8;
14424 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
14425 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
14426 MVT Tp = (MVT::SimpleValueType)tp;
14427 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() == MemSz) {
14433 // Proceed if a load word is found.
14434 if (SclrLoadTy.getSizeInBits() != MemSz) return SDValue();
14436 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy,
14437 RegSz/SclrLoadTy.getSizeInBits());
14439 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
14440 RegSz/MemVT.getScalarType().getSizeInBits());
14441 // Can't shuffle using an illegal type.
14442 if (!TLI.isTypeLegal(WideVecVT)) return SDValue();
14444 // Perform a single load.
14445 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(),
14447 Ld->getPointerInfo(), Ld->isVolatile(),
14448 Ld->isNonTemporal(), Ld->isInvariant(),
14449 Ld->getAlignment());
14451 // Insert the word loaded into a vector.
14452 SDValue ScalarInVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
14453 LoadUnitVecVT, ScalarLoad);
14455 // Bitcast the loaded value to a vector of the original element type, in
14456 // the size of the target vector type.
14457 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT,
14459 unsigned SizeRatio = RegSz/MemSz;
14461 // Redistribute the loaded elements into the different locations.
14462 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
14463 for (unsigned i = 0; i != NumElems; ++i)
14464 ShuffleVec[i*SizeRatio] = i;
14466 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
14467 DAG.getUNDEF(WideVecVT),
14470 // Bitcast to the requested type.
14471 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
14472 // Replace the original load with the new sequence
14473 // and return the new chain.
14474 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Shuff);
14475 return SDValue(ScalarLoad.getNode(), 1);
14481 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
14482 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
14483 const X86Subtarget *Subtarget) {
14484 StoreSDNode *St = cast<StoreSDNode>(N);
14485 EVT VT = St->getValue().getValueType();
14486 EVT StVT = St->getMemoryVT();
14487 DebugLoc dl = St->getDebugLoc();
14488 SDValue StoredVal = St->getOperand(1);
14489 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14491 // If we are saving a concatenation of two XMM registers, perform two stores.
14492 // On Sandy Bridge, 256-bit memory operations are executed by two
14493 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit
14494 // memory operation.
14495 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2() &&
14496 StoredVal.getNode()->getOpcode() == ISD::CONCAT_VECTORS &&
14497 StoredVal.getNumOperands() == 2) {
14498 SDValue Value0 = StoredVal.getOperand(0);
14499 SDValue Value1 = StoredVal.getOperand(1);
14501 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
14502 SDValue Ptr0 = St->getBasePtr();
14503 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
14505 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
14506 St->getPointerInfo(), St->isVolatile(),
14507 St->isNonTemporal(), St->getAlignment());
14508 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
14509 St->getPointerInfo(), St->isVolatile(),
14510 St->isNonTemporal(), St->getAlignment());
14511 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
14514 // Optimize trunc store (of multiple scalars) to shuffle and store.
14515 // First, pack all of the elements in one place. Next, store to memory
14516 // in fewer chunks.
14517 if (St->isTruncatingStore() && VT.isVector()) {
14518 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14519 unsigned NumElems = VT.getVectorNumElements();
14520 assert(StVT != VT && "Cannot truncate to the same type");
14521 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
14522 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
14524 // From, To sizes and ElemCount must be pow of two
14525 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
14526 // We are going to use the original vector elt for storing.
14527 // Accumulated smaller vector elements must be a multiple of the store size.
14528 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
14530 unsigned SizeRatio = FromSz / ToSz;
14532 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
14534 // Create a type on which we perform the shuffle
14535 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
14536 StVT.getScalarType(), NumElems*SizeRatio);
14538 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
14540 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
14541 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
14542 for (unsigned i = 0; i != NumElems; ++i)
14543 ShuffleVec[i] = i * SizeRatio;
14545 // Can't shuffle using an illegal type
14546 if (!TLI.isTypeLegal(WideVecVT)) return SDValue();
14548 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
14549 DAG.getUNDEF(WideVecVT),
14551 // At this point all of the data is stored at the bottom of the
14552 // register. We now need to save it to mem.
14554 // Find the largest store unit
14555 MVT StoreType = MVT::i8;
14556 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
14557 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
14558 MVT Tp = (MVT::SimpleValueType)tp;
14559 if (TLI.isTypeLegal(Tp) && StoreType.getSizeInBits() < NumElems * ToSz)
14563 // Bitcast the original vector into a vector of store-size units
14564 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
14565 StoreType, VT.getSizeInBits()/EVT(StoreType).getSizeInBits());
14566 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
14567 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
14568 SmallVector<SDValue, 8> Chains;
14569 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
14570 TLI.getPointerTy());
14571 SDValue Ptr = St->getBasePtr();
14573 // Perform one or more big stores into memory.
14574 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
14575 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
14576 StoreType, ShuffWide,
14577 DAG.getIntPtrConstant(i));
14578 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
14579 St->getPointerInfo(), St->isVolatile(),
14580 St->isNonTemporal(), St->getAlignment());
14581 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
14582 Chains.push_back(Ch);
14585 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
14590 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
14591 // the FP state in cases where an emms may be missing.
14592 // A preferable solution to the general problem is to figure out the right
14593 // places to insert EMMS. This qualifies as a quick hack.
14595 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
14596 if (VT.getSizeInBits() != 64)
14599 const Function *F = DAG.getMachineFunction().getFunction();
14600 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
14601 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
14602 && Subtarget->hasSSE2();
14603 if ((VT.isVector() ||
14604 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
14605 isa<LoadSDNode>(St->getValue()) &&
14606 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
14607 St->getChain().hasOneUse() && !St->isVolatile()) {
14608 SDNode* LdVal = St->getValue().getNode();
14609 LoadSDNode *Ld = 0;
14610 int TokenFactorIndex = -1;
14611 SmallVector<SDValue, 8> Ops;
14612 SDNode* ChainVal = St->getChain().getNode();
14613 // Must be a store of a load. We currently handle two cases: the load
14614 // is a direct child, and it's under an intervening TokenFactor. It is
14615 // possible to dig deeper under nested TokenFactors.
14616 if (ChainVal == LdVal)
14617 Ld = cast<LoadSDNode>(St->getChain());
14618 else if (St->getValue().hasOneUse() &&
14619 ChainVal->getOpcode() == ISD::TokenFactor) {
14620 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
14621 if (ChainVal->getOperand(i).getNode() == LdVal) {
14622 TokenFactorIndex = i;
14623 Ld = cast<LoadSDNode>(St->getValue());
14625 Ops.push_back(ChainVal->getOperand(i));
14629 if (!Ld || !ISD::isNormalLoad(Ld))
14632 // If this is not the MMX case, i.e. we are just turning i64 load/store
14633 // into f64 load/store, avoid the transformation if there are multiple
14634 // uses of the loaded value.
14635 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
14638 DebugLoc LdDL = Ld->getDebugLoc();
14639 DebugLoc StDL = N->getDebugLoc();
14640 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
14641 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
14643 if (Subtarget->is64Bit() || F64IsLegal) {
14644 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
14645 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
14646 Ld->getPointerInfo(), Ld->isVolatile(),
14647 Ld->isNonTemporal(), Ld->isInvariant(),
14648 Ld->getAlignment());
14649 SDValue NewChain = NewLd.getValue(1);
14650 if (TokenFactorIndex != -1) {
14651 Ops.push_back(NewChain);
14652 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
14655 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
14656 St->getPointerInfo(),
14657 St->isVolatile(), St->isNonTemporal(),
14658 St->getAlignment());
14661 // Otherwise, lower to two pairs of 32-bit loads / stores.
14662 SDValue LoAddr = Ld->getBasePtr();
14663 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
14664 DAG.getConstant(4, MVT::i32));
14666 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
14667 Ld->getPointerInfo(),
14668 Ld->isVolatile(), Ld->isNonTemporal(),
14669 Ld->isInvariant(), Ld->getAlignment());
14670 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
14671 Ld->getPointerInfo().getWithOffset(4),
14672 Ld->isVolatile(), Ld->isNonTemporal(),
14674 MinAlign(Ld->getAlignment(), 4));
14676 SDValue NewChain = LoLd.getValue(1);
14677 if (TokenFactorIndex != -1) {
14678 Ops.push_back(LoLd);
14679 Ops.push_back(HiLd);
14680 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
14684 LoAddr = St->getBasePtr();
14685 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
14686 DAG.getConstant(4, MVT::i32));
14688 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
14689 St->getPointerInfo(),
14690 St->isVolatile(), St->isNonTemporal(),
14691 St->getAlignment());
14692 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
14693 St->getPointerInfo().getWithOffset(4),
14695 St->isNonTemporal(),
14696 MinAlign(St->getAlignment(), 4));
14697 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
14702 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
14703 /// and return the operands for the horizontal operation in LHS and RHS. A
14704 /// horizontal operation performs the binary operation on successive elements
14705 /// of its first operand, then on successive elements of its second operand,
14706 /// returning the resulting values in a vector. For example, if
14707 /// A = < float a0, float a1, float a2, float a3 >
14709 /// B = < float b0, float b1, float b2, float b3 >
14710 /// then the result of doing a horizontal operation on A and B is
14711 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
14712 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
14713 /// A horizontal-op B, for some already available A and B, and if so then LHS is
14714 /// set to A, RHS to B, and the routine returns 'true'.
14715 /// Note that the binary operation should have the property that if one of the
14716 /// operands is UNDEF then the result is UNDEF.
14717 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
14718 // Look for the following pattern: if
14719 // A = < float a0, float a1, float a2, float a3 >
14720 // B = < float b0, float b1, float b2, float b3 >
14722 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
14723 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
14724 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
14725 // which is A horizontal-op B.
14727 // At least one of the operands should be a vector shuffle.
14728 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
14729 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
14732 EVT VT = LHS.getValueType();
14734 assert((VT.is128BitVector() || VT.is256BitVector()) &&
14735 "Unsupported vector type for horizontal add/sub");
14737 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
14738 // operate independently on 128-bit lanes.
14739 unsigned NumElts = VT.getVectorNumElements();
14740 unsigned NumLanes = VT.getSizeInBits()/128;
14741 unsigned NumLaneElts = NumElts / NumLanes;
14742 assert((NumLaneElts % 2 == 0) &&
14743 "Vector type should have an even number of elements in each lane");
14744 unsigned HalfLaneElts = NumLaneElts/2;
14746 // View LHS in the form
14747 // LHS = VECTOR_SHUFFLE A, B, LMask
14748 // If LHS is not a shuffle then pretend it is the shuffle
14749 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
14750 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
14753 SmallVector<int, 16> LMask(NumElts);
14754 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
14755 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
14756 A = LHS.getOperand(0);
14757 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
14758 B = LHS.getOperand(1);
14759 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
14760 std::copy(Mask.begin(), Mask.end(), LMask.begin());
14762 if (LHS.getOpcode() != ISD::UNDEF)
14764 for (unsigned i = 0; i != NumElts; ++i)
14768 // Likewise, view RHS in the form
14769 // RHS = VECTOR_SHUFFLE C, D, RMask
14771 SmallVector<int, 16> RMask(NumElts);
14772 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
14773 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
14774 C = RHS.getOperand(0);
14775 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
14776 D = RHS.getOperand(1);
14777 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
14778 std::copy(Mask.begin(), Mask.end(), RMask.begin());
14780 if (RHS.getOpcode() != ISD::UNDEF)
14782 for (unsigned i = 0; i != NumElts; ++i)
14786 // Check that the shuffles are both shuffling the same vectors.
14787 if (!(A == C && B == D) && !(A == D && B == C))
14790 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
14791 if (!A.getNode() && !B.getNode())
14794 // If A and B occur in reverse order in RHS, then "swap" them (which means
14795 // rewriting the mask).
14797 CommuteVectorShuffleMask(RMask, NumElts);
14799 // At this point LHS and RHS are equivalent to
14800 // LHS = VECTOR_SHUFFLE A, B, LMask
14801 // RHS = VECTOR_SHUFFLE A, B, RMask
14802 // Check that the masks correspond to performing a horizontal operation.
14803 for (unsigned i = 0; i != NumElts; ++i) {
14804 int LIdx = LMask[i], RIdx = RMask[i];
14806 // Ignore any UNDEF components.
14807 if (LIdx < 0 || RIdx < 0 ||
14808 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
14809 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
14812 // Check that successive elements are being operated on. If not, this is
14813 // not a horizontal operation.
14814 unsigned Src = (i/HalfLaneElts) % 2; // each lane is split between srcs
14815 unsigned LaneStart = (i/NumLaneElts) * NumLaneElts;
14816 int Index = 2*(i%HalfLaneElts) + NumElts*Src + LaneStart;
14817 if (!(LIdx == Index && RIdx == Index + 1) &&
14818 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
14822 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
14823 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
14827 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
14828 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
14829 const X86Subtarget *Subtarget) {
14830 EVT VT = N->getValueType(0);
14831 SDValue LHS = N->getOperand(0);
14832 SDValue RHS = N->getOperand(1);
14834 // Try to synthesize horizontal adds from adds of shuffles.
14835 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
14836 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
14837 isHorizontalBinOp(LHS, RHS, true))
14838 return DAG.getNode(X86ISD::FHADD, N->getDebugLoc(), VT, LHS, RHS);
14842 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
14843 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
14844 const X86Subtarget *Subtarget) {
14845 EVT VT = N->getValueType(0);
14846 SDValue LHS = N->getOperand(0);
14847 SDValue RHS = N->getOperand(1);
14849 // Try to synthesize horizontal subs from subs of shuffles.
14850 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
14851 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
14852 isHorizontalBinOp(LHS, RHS, false))
14853 return DAG.getNode(X86ISD::FHSUB, N->getDebugLoc(), VT, LHS, RHS);
14857 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
14858 /// X86ISD::FXOR nodes.
14859 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
14860 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
14861 // F[X]OR(0.0, x) -> x
14862 // F[X]OR(x, 0.0) -> x
14863 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
14864 if (C->getValueAPF().isPosZero())
14865 return N->getOperand(1);
14866 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
14867 if (C->getValueAPF().isPosZero())
14868 return N->getOperand(0);
14872 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
14873 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
14874 // FAND(0.0, x) -> 0.0
14875 // FAND(x, 0.0) -> 0.0
14876 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
14877 if (C->getValueAPF().isPosZero())
14878 return N->getOperand(0);
14879 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
14880 if (C->getValueAPF().isPosZero())
14881 return N->getOperand(1);
14885 static SDValue PerformBTCombine(SDNode *N,
14887 TargetLowering::DAGCombinerInfo &DCI) {
14888 // BT ignores high bits in the bit index operand.
14889 SDValue Op1 = N->getOperand(1);
14890 if (Op1.hasOneUse()) {
14891 unsigned BitWidth = Op1.getValueSizeInBits();
14892 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
14893 APInt KnownZero, KnownOne;
14894 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
14895 !DCI.isBeforeLegalizeOps());
14896 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14897 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
14898 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
14899 DCI.CommitTargetLoweringOpt(TLO);
14904 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
14905 SDValue Op = N->getOperand(0);
14906 if (Op.getOpcode() == ISD::BITCAST)
14907 Op = Op.getOperand(0);
14908 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
14909 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
14910 VT.getVectorElementType().getSizeInBits() ==
14911 OpVT.getVectorElementType().getSizeInBits()) {
14912 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op);
14917 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
14918 TargetLowering::DAGCombinerInfo &DCI,
14919 const X86Subtarget *Subtarget) {
14920 if (!DCI.isBeforeLegalizeOps())
14923 if (!Subtarget->hasAVX())
14926 EVT VT = N->getValueType(0);
14927 SDValue Op = N->getOperand(0);
14928 EVT OpVT = Op.getValueType();
14929 DebugLoc dl = N->getDebugLoc();
14931 if ((VT == MVT::v4i64 && OpVT == MVT::v4i32) ||
14932 (VT == MVT::v8i32 && OpVT == MVT::v8i16)) {
14934 if (Subtarget->hasAVX2())
14935 return DAG.getNode(X86ISD::VSEXT_MOVL, dl, VT, Op);
14937 // Optimize vectors in AVX mode
14938 // Sign extend v8i16 to v8i32 and
14941 // Divide input vector into two parts
14942 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
14943 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
14944 // concat the vectors to original VT
14946 unsigned NumElems = OpVT.getVectorNumElements();
14947 SmallVector<int,8> ShufMask1(NumElems, -1);
14948 for (unsigned i = 0; i != NumElems/2; ++i)
14951 SDValue OpLo = DAG.getVectorShuffle(OpVT, dl, Op, DAG.getUNDEF(OpVT),
14954 SmallVector<int,8> ShufMask2(NumElems, -1);
14955 for (unsigned i = 0; i != NumElems/2; ++i)
14956 ShufMask2[i] = i + NumElems/2;
14958 SDValue OpHi = DAG.getVectorShuffle(OpVT, dl, Op, DAG.getUNDEF(OpVT),
14961 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), VT.getScalarType(),
14962 VT.getVectorNumElements()/2);
14964 OpLo = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpLo);
14965 OpHi = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpHi);
14967 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14972 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
14973 TargetLowering::DAGCombinerInfo &DCI,
14974 const X86Subtarget *Subtarget) {
14975 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
14976 // (and (i32 x86isd::setcc_carry), 1)
14977 // This eliminates the zext. This transformation is necessary because
14978 // ISD::SETCC is always legalized to i8.
14979 DebugLoc dl = N->getDebugLoc();
14980 SDValue N0 = N->getOperand(0);
14981 EVT VT = N->getValueType(0);
14982 EVT OpVT = N0.getValueType();
14984 if (N0.getOpcode() == ISD::AND &&
14986 N0.getOperand(0).hasOneUse()) {
14987 SDValue N00 = N0.getOperand(0);
14988 if (N00.getOpcode() != X86ISD::SETCC_CARRY)
14990 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
14991 if (!C || C->getZExtValue() != 1)
14993 return DAG.getNode(ISD::AND, dl, VT,
14994 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
14995 N00.getOperand(0), N00.getOperand(1)),
14996 DAG.getConstant(1, VT));
14999 // Optimize vectors in AVX mode:
15002 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
15003 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
15004 // Concat upper and lower parts.
15007 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
15008 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
15009 // Concat upper and lower parts.
15011 if (!DCI.isBeforeLegalizeOps())
15014 if (!Subtarget->hasAVX())
15017 if (((VT == MVT::v8i32) && (OpVT == MVT::v8i16)) ||
15018 ((VT == MVT::v4i64) && (OpVT == MVT::v4i32))) {
15020 if (Subtarget->hasAVX2())
15021 return DAG.getNode(X86ISD::VZEXT_MOVL, dl, VT, N0);
15023 SDValue ZeroVec = getZeroVector(OpVT, Subtarget, DAG, dl);
15024 SDValue OpLo = getUnpackl(DAG, dl, OpVT, N0, ZeroVec);
15025 SDValue OpHi = getUnpackh(DAG, dl, OpVT, N0, ZeroVec);
15027 EVT HVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
15028 VT.getVectorNumElements()/2);
15030 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
15031 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
15033 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
15039 // Optimize x == -y --> x+y == 0
15040 // x != -y --> x+y != 0
15041 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG) {
15042 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
15043 SDValue LHS = N->getOperand(0);
15044 SDValue RHS = N->getOperand(1);
15046 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
15047 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
15048 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
15049 SDValue addV = DAG.getNode(ISD::ADD, N->getDebugLoc(),
15050 LHS.getValueType(), RHS, LHS.getOperand(1));
15051 return DAG.getSetCC(N->getDebugLoc(), N->getValueType(0),
15052 addV, DAG.getConstant(0, addV.getValueType()), CC);
15054 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
15055 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
15056 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
15057 SDValue addV = DAG.getNode(ISD::ADD, N->getDebugLoc(),
15058 RHS.getValueType(), LHS, RHS.getOperand(1));
15059 return DAG.getSetCC(N->getDebugLoc(), N->getValueType(0),
15060 addV, DAG.getConstant(0, addV.getValueType()), CC);
15065 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
15066 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG) {
15067 unsigned X86CC = N->getConstantOperandVal(0);
15068 SDValue EFLAG = N->getOperand(1);
15069 DebugLoc DL = N->getDebugLoc();
15071 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
15072 // a zext and produces an all-ones bit which is more useful than 0/1 in some
15074 if (X86CC == X86::COND_B)
15075 return DAG.getNode(ISD::AND, DL, MVT::i8,
15076 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
15077 DAG.getConstant(X86CC, MVT::i8), EFLAG),
15078 DAG.getConstant(1, MVT::i8));
15083 static SDValue PerformUINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG) {
15084 SDValue Op0 = N->getOperand(0);
15085 EVT InVT = Op0->getValueType(0);
15087 // UINT_TO_FP(v4i8) -> SINT_TO_FP(ZEXT(v4i8 to v4i32))
15088 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
15089 DebugLoc dl = N->getDebugLoc();
15090 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
15091 SDValue P = DAG.getNode(ISD::ZERO_EXTEND, dl, DstVT, Op0);
15092 // Notice that we use SINT_TO_FP because we know that the high bits
15093 // are zero and SINT_TO_FP is better supported by the hardware.
15094 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
15100 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
15101 const X86TargetLowering *XTLI) {
15102 SDValue Op0 = N->getOperand(0);
15103 EVT InVT = Op0->getValueType(0);
15105 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
15106 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
15107 DebugLoc dl = N->getDebugLoc();
15108 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
15109 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
15110 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
15113 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
15114 // a 32-bit target where SSE doesn't support i64->FP operations.
15115 if (Op0.getOpcode() == ISD::LOAD) {
15116 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
15117 EVT VT = Ld->getValueType(0);
15118 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
15119 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
15120 !XTLI->getSubtarget()->is64Bit() &&
15121 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
15122 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
15123 Ld->getChain(), Op0, DAG);
15124 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
15131 static SDValue PerformFP_TO_SINTCombine(SDNode *N, SelectionDAG &DAG) {
15132 EVT VT = N->getValueType(0);
15134 // v4i8 = FP_TO_SINT() -> v4i8 = TRUNCATE (V4i32 = FP_TO_SINT()
15135 if (VT == MVT::v8i8 || VT == MVT::v4i8) {
15136 DebugLoc dl = N->getDebugLoc();
15137 MVT DstVT = VT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
15138 SDValue I = DAG.getNode(ISD::FP_TO_SINT, dl, DstVT, N->getOperand(0));
15139 return DAG.getNode(ISD::TRUNCATE, dl, VT, I);
15145 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
15146 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
15147 X86TargetLowering::DAGCombinerInfo &DCI) {
15148 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
15149 // the result is either zero or one (depending on the input carry bit).
15150 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
15151 if (X86::isZeroNode(N->getOperand(0)) &&
15152 X86::isZeroNode(N->getOperand(1)) &&
15153 // We don't have a good way to replace an EFLAGS use, so only do this when
15155 SDValue(N, 1).use_empty()) {
15156 DebugLoc DL = N->getDebugLoc();
15157 EVT VT = N->getValueType(0);
15158 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
15159 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
15160 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
15161 DAG.getConstant(X86::COND_B,MVT::i8),
15163 DAG.getConstant(1, VT));
15164 return DCI.CombineTo(N, Res1, CarryOut);
15170 // fold (add Y, (sete X, 0)) -> adc 0, Y
15171 // (add Y, (setne X, 0)) -> sbb -1, Y
15172 // (sub (sete X, 0), Y) -> sbb 0, Y
15173 // (sub (setne X, 0), Y) -> adc -1, Y
15174 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
15175 DebugLoc DL = N->getDebugLoc();
15177 // Look through ZExts.
15178 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
15179 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
15182 SDValue SetCC = Ext.getOperand(0);
15183 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
15186 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
15187 if (CC != X86::COND_E && CC != X86::COND_NE)
15190 SDValue Cmp = SetCC.getOperand(1);
15191 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
15192 !X86::isZeroNode(Cmp.getOperand(1)) ||
15193 !Cmp.getOperand(0).getValueType().isInteger())
15196 SDValue CmpOp0 = Cmp.getOperand(0);
15197 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
15198 DAG.getConstant(1, CmpOp0.getValueType()));
15200 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
15201 if (CC == X86::COND_NE)
15202 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
15203 DL, OtherVal.getValueType(), OtherVal,
15204 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
15205 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
15206 DL, OtherVal.getValueType(), OtherVal,
15207 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
15210 /// PerformADDCombine - Do target-specific dag combines on integer adds.
15211 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
15212 const X86Subtarget *Subtarget) {
15213 EVT VT = N->getValueType(0);
15214 SDValue Op0 = N->getOperand(0);
15215 SDValue Op1 = N->getOperand(1);
15217 // Try to synthesize horizontal adds from adds of shuffles.
15218 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
15219 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
15220 isHorizontalBinOp(Op0, Op1, true))
15221 return DAG.getNode(X86ISD::HADD, N->getDebugLoc(), VT, Op0, Op1);
15223 return OptimizeConditionalInDecrement(N, DAG);
15226 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
15227 const X86Subtarget *Subtarget) {
15228 SDValue Op0 = N->getOperand(0);
15229 SDValue Op1 = N->getOperand(1);
15231 // X86 can't encode an immediate LHS of a sub. See if we can push the
15232 // negation into a preceding instruction.
15233 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
15234 // If the RHS of the sub is a XOR with one use and a constant, invert the
15235 // immediate. Then add one to the LHS of the sub so we can turn
15236 // X-Y -> X+~Y+1, saving one register.
15237 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
15238 isa<ConstantSDNode>(Op1.getOperand(1))) {
15239 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
15240 EVT VT = Op0.getValueType();
15241 SDValue NewXor = DAG.getNode(ISD::XOR, Op1.getDebugLoc(), VT,
15243 DAG.getConstant(~XorC, VT));
15244 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, NewXor,
15245 DAG.getConstant(C->getAPIntValue()+1, VT));
15249 // Try to synthesize horizontal adds from adds of shuffles.
15250 EVT VT = N->getValueType(0);
15251 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
15252 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
15253 isHorizontalBinOp(Op0, Op1, true))
15254 return DAG.getNode(X86ISD::HSUB, N->getDebugLoc(), VT, Op0, Op1);
15256 return OptimizeConditionalInDecrement(N, DAG);
15259 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
15260 DAGCombinerInfo &DCI) const {
15261 SelectionDAG &DAG = DCI.DAG;
15262 switch (N->getOpcode()) {
15264 case ISD::EXTRACT_VECTOR_ELT:
15265 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
15267 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
15268 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);
15269 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
15270 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
15271 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
15272 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
15275 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
15276 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
15277 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
15278 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
15279 case ISD::LOAD: return PerformLOADCombine(N, DAG, Subtarget);
15280 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
15281 case ISD::UINT_TO_FP: return PerformUINT_TO_FPCombine(N, DAG);
15282 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
15283 case ISD::FP_TO_SINT: return PerformFP_TO_SINTCombine(N, DAG);
15284 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
15285 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
15287 case X86ISD::FOR: return PerformFORCombine(N, DAG);
15288 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
15289 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
15290 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
15291 case ISD::ANY_EXTEND:
15292 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
15293 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
15294 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG, DCI);
15295 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG);
15296 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG);
15297 case X86ISD::SHUFP: // Handle all target specific shuffles
15298 case X86ISD::PALIGN:
15299 case X86ISD::UNPCKH:
15300 case X86ISD::UNPCKL:
15301 case X86ISD::MOVHLPS:
15302 case X86ISD::MOVLHPS:
15303 case X86ISD::PSHUFD:
15304 case X86ISD::PSHUFHW:
15305 case X86ISD::PSHUFLW:
15306 case X86ISD::MOVSS:
15307 case X86ISD::MOVSD:
15308 case X86ISD::VPERMILP:
15309 case X86ISD::VPERM2X128:
15310 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
15316 /// isTypeDesirableForOp - Return true if the target has native support for
15317 /// the specified value type and it is 'desirable' to use the type for the
15318 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
15319 /// instruction encodings are longer and some i16 instructions are slow.
15320 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
15321 if (!isTypeLegal(VT))
15323 if (VT != MVT::i16)
15330 case ISD::SIGN_EXTEND:
15331 case ISD::ZERO_EXTEND:
15332 case ISD::ANY_EXTEND:
15345 /// IsDesirableToPromoteOp - This method query the target whether it is
15346 /// beneficial for dag combiner to promote the specified node. If true, it
15347 /// should return the desired promotion type by reference.
15348 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
15349 EVT VT = Op.getValueType();
15350 if (VT != MVT::i16)
15353 bool Promote = false;
15354 bool Commute = false;
15355 switch (Op.getOpcode()) {
15358 LoadSDNode *LD = cast<LoadSDNode>(Op);
15359 // If the non-extending load has a single use and it's not live out, then it
15360 // might be folded.
15361 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
15362 Op.hasOneUse()*/) {
15363 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
15364 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
15365 // The only case where we'd want to promote LOAD (rather then it being
15366 // promoted as an operand is when it's only use is liveout.
15367 if (UI->getOpcode() != ISD::CopyToReg)
15374 case ISD::SIGN_EXTEND:
15375 case ISD::ZERO_EXTEND:
15376 case ISD::ANY_EXTEND:
15381 SDValue N0 = Op.getOperand(0);
15382 // Look out for (store (shl (load), x)).
15383 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
15396 SDValue N0 = Op.getOperand(0);
15397 SDValue N1 = Op.getOperand(1);
15398 if (!Commute && MayFoldLoad(N1))
15400 // Avoid disabling potential load folding opportunities.
15401 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
15403 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
15413 //===----------------------------------------------------------------------===//
15414 // X86 Inline Assembly Support
15415 //===----------------------------------------------------------------------===//
15418 // Helper to match a string separated by whitespace.
15419 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
15420 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
15422 for (unsigned i = 0, e = args.size(); i != e; ++i) {
15423 StringRef piece(*args[i]);
15424 if (!s.startswith(piece)) // Check if the piece matches.
15427 s = s.substr(piece.size());
15428 StringRef::size_type pos = s.find_first_not_of(" \t");
15429 if (pos == 0) // We matched a prefix.
15437 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
15440 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
15441 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
15443 std::string AsmStr = IA->getAsmString();
15445 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
15446 if (!Ty || Ty->getBitWidth() % 16 != 0)
15449 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
15450 SmallVector<StringRef, 4> AsmPieces;
15451 SplitString(AsmStr, AsmPieces, ";\n");
15453 switch (AsmPieces.size()) {
15454 default: return false;
15456 // FIXME: this should verify that we are targeting a 486 or better. If not,
15457 // we will turn this bswap into something that will be lowered to logical
15458 // ops instead of emitting the bswap asm. For now, we don't support 486 or
15459 // lower so don't worry about this.
15461 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
15462 matchAsm(AsmPieces[0], "bswapl", "$0") ||
15463 matchAsm(AsmPieces[0], "bswapq", "$0") ||
15464 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
15465 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
15466 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
15467 // No need to check constraints, nothing other than the equivalent of
15468 // "=r,0" would be valid here.
15469 return IntrinsicLowering::LowerToByteSwap(CI);
15472 // rorw $$8, ${0:w} --> llvm.bswap.i16
15473 if (CI->getType()->isIntegerTy(16) &&
15474 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
15475 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
15476 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
15478 const std::string &ConstraintsStr = IA->getConstraintString();
15479 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
15480 std::sort(AsmPieces.begin(), AsmPieces.end());
15481 if (AsmPieces.size() == 4 &&
15482 AsmPieces[0] == "~{cc}" &&
15483 AsmPieces[1] == "~{dirflag}" &&
15484 AsmPieces[2] == "~{flags}" &&
15485 AsmPieces[3] == "~{fpsr}")
15486 return IntrinsicLowering::LowerToByteSwap(CI);
15490 if (CI->getType()->isIntegerTy(32) &&
15491 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
15492 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
15493 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
15494 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
15496 const std::string &ConstraintsStr = IA->getConstraintString();
15497 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
15498 std::sort(AsmPieces.begin(), AsmPieces.end());
15499 if (AsmPieces.size() == 4 &&
15500 AsmPieces[0] == "~{cc}" &&
15501 AsmPieces[1] == "~{dirflag}" &&
15502 AsmPieces[2] == "~{flags}" &&
15503 AsmPieces[3] == "~{fpsr}")
15504 return IntrinsicLowering::LowerToByteSwap(CI);
15507 if (CI->getType()->isIntegerTy(64)) {
15508 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
15509 if (Constraints.size() >= 2 &&
15510 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
15511 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
15512 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
15513 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
15514 matchAsm(AsmPieces[1], "bswap", "%edx") &&
15515 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
15516 return IntrinsicLowering::LowerToByteSwap(CI);
15526 /// getConstraintType - Given a constraint letter, return the type of
15527 /// constraint it is for this target.
15528 X86TargetLowering::ConstraintType
15529 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
15530 if (Constraint.size() == 1) {
15531 switch (Constraint[0]) {
15542 return C_RegisterClass;
15566 return TargetLowering::getConstraintType(Constraint);
15569 /// Examine constraint type and operand type and determine a weight value.
15570 /// This object must already have been set up with the operand type
15571 /// and the current alternative constraint selected.
15572 TargetLowering::ConstraintWeight
15573 X86TargetLowering::getSingleConstraintMatchWeight(
15574 AsmOperandInfo &info, const char *constraint) const {
15575 ConstraintWeight weight = CW_Invalid;
15576 Value *CallOperandVal = info.CallOperandVal;
15577 // If we don't have a value, we can't do a match,
15578 // but allow it at the lowest weight.
15579 if (CallOperandVal == NULL)
15581 Type *type = CallOperandVal->getType();
15582 // Look at the constraint type.
15583 switch (*constraint) {
15585 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
15596 if (CallOperandVal->getType()->isIntegerTy())
15597 weight = CW_SpecificReg;
15602 if (type->isFloatingPointTy())
15603 weight = CW_SpecificReg;
15606 if (type->isX86_MMXTy() && Subtarget->hasMMX())
15607 weight = CW_SpecificReg;
15611 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
15612 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasAVX()))
15613 weight = CW_Register;
15616 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
15617 if (C->getZExtValue() <= 31)
15618 weight = CW_Constant;
15622 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15623 if (C->getZExtValue() <= 63)
15624 weight = CW_Constant;
15628 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15629 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
15630 weight = CW_Constant;
15634 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15635 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
15636 weight = CW_Constant;
15640 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15641 if (C->getZExtValue() <= 3)
15642 weight = CW_Constant;
15646 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15647 if (C->getZExtValue() <= 0xff)
15648 weight = CW_Constant;
15653 if (dyn_cast<ConstantFP>(CallOperandVal)) {
15654 weight = CW_Constant;
15658 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15659 if ((C->getSExtValue() >= -0x80000000LL) &&
15660 (C->getSExtValue() <= 0x7fffffffLL))
15661 weight = CW_Constant;
15665 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15666 if (C->getZExtValue() <= 0xffffffff)
15667 weight = CW_Constant;
15674 /// LowerXConstraint - try to replace an X constraint, which matches anything,
15675 /// with another that has more specific requirements based on the type of the
15676 /// corresponding operand.
15677 const char *X86TargetLowering::
15678 LowerXConstraint(EVT ConstraintVT) const {
15679 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
15680 // 'f' like normal targets.
15681 if (ConstraintVT.isFloatingPoint()) {
15682 if (Subtarget->hasSSE2())
15684 if (Subtarget->hasSSE1())
15688 return TargetLowering::LowerXConstraint(ConstraintVT);
15691 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
15692 /// vector. If it is invalid, don't add anything to Ops.
15693 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
15694 std::string &Constraint,
15695 std::vector<SDValue>&Ops,
15696 SelectionDAG &DAG) const {
15697 SDValue Result(0, 0);
15699 // Only support length 1 constraints for now.
15700 if (Constraint.length() > 1) return;
15702 char ConstraintLetter = Constraint[0];
15703 switch (ConstraintLetter) {
15706 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15707 if (C->getZExtValue() <= 31) {
15708 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15714 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15715 if (C->getZExtValue() <= 63) {
15716 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15722 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15723 if ((int8_t)C->getSExtValue() == C->getSExtValue()) {
15724 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15730 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15731 if (C->getZExtValue() <= 255) {
15732 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15738 // 32-bit signed value
15739 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15740 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
15741 C->getSExtValue())) {
15742 // Widen to 64 bits here to get it sign extended.
15743 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
15746 // FIXME gcc accepts some relocatable values here too, but only in certain
15747 // memory models; it's complicated.
15752 // 32-bit unsigned value
15753 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15754 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
15755 C->getZExtValue())) {
15756 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15760 // FIXME gcc accepts some relocatable values here too, but only in certain
15761 // memory models; it's complicated.
15765 // Literal immediates are always ok.
15766 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
15767 // Widen to 64 bits here to get it sign extended.
15768 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
15772 // In any sort of PIC mode addresses need to be computed at runtime by
15773 // adding in a register or some sort of table lookup. These can't
15774 // be used as immediates.
15775 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
15778 // If we are in non-pic codegen mode, we allow the address of a global (with
15779 // an optional displacement) to be used with 'i'.
15780 GlobalAddressSDNode *GA = 0;
15781 int64_t Offset = 0;
15783 // Match either (GA), (GA+C), (GA+C1+C2), etc.
15785 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
15786 Offset += GA->getOffset();
15788 } else if (Op.getOpcode() == ISD::ADD) {
15789 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
15790 Offset += C->getZExtValue();
15791 Op = Op.getOperand(0);
15794 } else if (Op.getOpcode() == ISD::SUB) {
15795 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
15796 Offset += -C->getZExtValue();
15797 Op = Op.getOperand(0);
15802 // Otherwise, this isn't something we can handle, reject it.
15806 const GlobalValue *GV = GA->getGlobal();
15807 // If we require an extra load to get this address, as in PIC mode, we
15808 // can't accept it.
15809 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
15810 getTargetMachine())))
15813 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(),
15814 GA->getValueType(0), Offset);
15819 if (Result.getNode()) {
15820 Ops.push_back(Result);
15823 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
15826 std::pair<unsigned, const TargetRegisterClass*>
15827 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
15829 // First, see if this is a constraint that directly corresponds to an LLVM
15831 if (Constraint.size() == 1) {
15832 // GCC Constraint Letters
15833 switch (Constraint[0]) {
15835 // TODO: Slight differences here in allocation order and leaving
15836 // RIP in the class. Do they matter any more here than they do
15837 // in the normal allocation?
15838 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
15839 if (Subtarget->is64Bit()) {
15840 if (VT == MVT::i32 || VT == MVT::f32)
15841 return std::make_pair(0U, &X86::GR32RegClass);
15842 if (VT == MVT::i16)
15843 return std::make_pair(0U, &X86::GR16RegClass);
15844 if (VT == MVT::i8 || VT == MVT::i1)
15845 return std::make_pair(0U, &X86::GR8RegClass);
15846 if (VT == MVT::i64 || VT == MVT::f64)
15847 return std::make_pair(0U, &X86::GR64RegClass);
15850 // 32-bit fallthrough
15851 case 'Q': // Q_REGS
15852 if (VT == MVT::i32 || VT == MVT::f32)
15853 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
15854 if (VT == MVT::i16)
15855 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
15856 if (VT == MVT::i8 || VT == MVT::i1)
15857 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
15858 if (VT == MVT::i64)
15859 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
15861 case 'r': // GENERAL_REGS
15862 case 'l': // INDEX_REGS
15863 if (VT == MVT::i8 || VT == MVT::i1)
15864 return std::make_pair(0U, &X86::GR8RegClass);
15865 if (VT == MVT::i16)
15866 return std::make_pair(0U, &X86::GR16RegClass);
15867 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
15868 return std::make_pair(0U, &X86::GR32RegClass);
15869 return std::make_pair(0U, &X86::GR64RegClass);
15870 case 'R': // LEGACY_REGS
15871 if (VT == MVT::i8 || VT == MVT::i1)
15872 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
15873 if (VT == MVT::i16)
15874 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
15875 if (VT == MVT::i32 || !Subtarget->is64Bit())
15876 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
15877 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
15878 case 'f': // FP Stack registers.
15879 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
15880 // value to the correct fpstack register class.
15881 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
15882 return std::make_pair(0U, &X86::RFP32RegClass);
15883 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
15884 return std::make_pair(0U, &X86::RFP64RegClass);
15885 return std::make_pair(0U, &X86::RFP80RegClass);
15886 case 'y': // MMX_REGS if MMX allowed.
15887 if (!Subtarget->hasMMX()) break;
15888 return std::make_pair(0U, &X86::VR64RegClass);
15889 case 'Y': // SSE_REGS if SSE2 allowed
15890 if (!Subtarget->hasSSE2()) break;
15892 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
15893 if (!Subtarget->hasSSE1()) break;
15895 switch (VT.getSimpleVT().SimpleTy) {
15897 // Scalar SSE types.
15900 return std::make_pair(0U, &X86::FR32RegClass);
15903 return std::make_pair(0U, &X86::FR64RegClass);
15911 return std::make_pair(0U, &X86::VR128RegClass);
15919 return std::make_pair(0U, &X86::VR256RegClass);
15925 // Use the default implementation in TargetLowering to convert the register
15926 // constraint into a member of a register class.
15927 std::pair<unsigned, const TargetRegisterClass*> Res;
15928 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
15930 // Not found as a standard register?
15931 if (Res.second == 0) {
15932 // Map st(0) -> st(7) -> ST0
15933 if (Constraint.size() == 7 && Constraint[0] == '{' &&
15934 tolower(Constraint[1]) == 's' &&
15935 tolower(Constraint[2]) == 't' &&
15936 Constraint[3] == '(' &&
15937 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
15938 Constraint[5] == ')' &&
15939 Constraint[6] == '}') {
15941 Res.first = X86::ST0+Constraint[4]-'0';
15942 Res.second = &X86::RFP80RegClass;
15946 // GCC allows "st(0)" to be called just plain "st".
15947 if (StringRef("{st}").equals_lower(Constraint)) {
15948 Res.first = X86::ST0;
15949 Res.second = &X86::RFP80RegClass;
15954 if (StringRef("{flags}").equals_lower(Constraint)) {
15955 Res.first = X86::EFLAGS;
15956 Res.second = &X86::CCRRegClass;
15960 // 'A' means EAX + EDX.
15961 if (Constraint == "A") {
15962 Res.first = X86::EAX;
15963 Res.second = &X86::GR32_ADRegClass;
15969 // Otherwise, check to see if this is a register class of the wrong value
15970 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
15971 // turn into {ax},{dx}.
15972 if (Res.second->hasType(VT))
15973 return Res; // Correct type already, nothing to do.
15975 // All of the single-register GCC register classes map their values onto
15976 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
15977 // really want an 8-bit or 32-bit register, map to the appropriate register
15978 // class and return the appropriate register.
15979 if (Res.second == &X86::GR16RegClass) {
15980 if (VT == MVT::i8) {
15981 unsigned DestReg = 0;
15982 switch (Res.first) {
15984 case X86::AX: DestReg = X86::AL; break;
15985 case X86::DX: DestReg = X86::DL; break;
15986 case X86::CX: DestReg = X86::CL; break;
15987 case X86::BX: DestReg = X86::BL; break;
15990 Res.first = DestReg;
15991 Res.second = &X86::GR8RegClass;
15993 } else if (VT == MVT::i32) {
15994 unsigned DestReg = 0;
15995 switch (Res.first) {
15997 case X86::AX: DestReg = X86::EAX; break;
15998 case X86::DX: DestReg = X86::EDX; break;
15999 case X86::CX: DestReg = X86::ECX; break;
16000 case X86::BX: DestReg = X86::EBX; break;
16001 case X86::SI: DestReg = X86::ESI; break;
16002 case X86::DI: DestReg = X86::EDI; break;
16003 case X86::BP: DestReg = X86::EBP; break;
16004 case X86::SP: DestReg = X86::ESP; break;
16007 Res.first = DestReg;
16008 Res.second = &X86::GR32RegClass;
16010 } else if (VT == MVT::i64) {
16011 unsigned DestReg = 0;
16012 switch (Res.first) {
16014 case X86::AX: DestReg = X86::RAX; break;
16015 case X86::DX: DestReg = X86::RDX; break;
16016 case X86::CX: DestReg = X86::RCX; break;
16017 case X86::BX: DestReg = X86::RBX; break;
16018 case X86::SI: DestReg = X86::RSI; break;
16019 case X86::DI: DestReg = X86::RDI; break;
16020 case X86::BP: DestReg = X86::RBP; break;
16021 case X86::SP: DestReg = X86::RSP; break;
16024 Res.first = DestReg;
16025 Res.second = &X86::GR64RegClass;
16028 } else if (Res.second == &X86::FR32RegClass ||
16029 Res.second == &X86::FR64RegClass ||
16030 Res.second == &X86::VR128RegClass) {
16031 // Handle references to XMM physical registers that got mapped into the
16032 // wrong class. This can happen with constraints like {xmm0} where the
16033 // target independent register mapper will just pick the first match it can
16034 // find, ignoring the required type.
16035 if (VT == MVT::f32)
16036 Res.second = &X86::FR32RegClass;
16037 else if (VT == MVT::f64)
16038 Res.second = &X86::FR64RegClass;
16039 else if (X86::VR128RegClass.hasType(VT))
16040 Res.second = &X86::VR128RegClass;