1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
16 #include "X86ISelLowering.h"
17 #include "Utils/X86ShuffleDecode.h"
19 #include "X86InstrBuilder.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/ADT/SmallSet.h"
23 #include "llvm/ADT/Statistic.h"
24 #include "llvm/ADT/StringExtras.h"
25 #include "llvm/ADT/VariadicFunction.h"
26 #include "llvm/CodeGen/IntrinsicLowering.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineJumpTableInfo.h"
31 #include "llvm/CodeGen/MachineModuleInfo.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/IR/CallingConv.h"
34 #include "llvm/IR/Constants.h"
35 #include "llvm/IR/DerivedTypes.h"
36 #include "llvm/IR/Function.h"
37 #include "llvm/IR/GlobalAlias.h"
38 #include "llvm/IR/GlobalVariable.h"
39 #include "llvm/IR/Instructions.h"
40 #include "llvm/IR/Intrinsics.h"
41 #include "llvm/IR/LLVMContext.h"
42 #include "llvm/MC/MCAsmInfo.h"
43 #include "llvm/MC/MCContext.h"
44 #include "llvm/MC/MCExpr.h"
45 #include "llvm/MC/MCSymbol.h"
46 #include "llvm/Support/CallSite.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/MathExtras.h"
50 #include "llvm/Target/TargetOptions.h"
55 STATISTIC(NumTailCalls, "Number of tail calls");
57 // Forward declarations.
58 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
61 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
62 SelectionDAG &DAG, SDLoc dl,
63 unsigned vectorWidth) {
64 assert((vectorWidth == 128 || vectorWidth == 256) &&
65 "Unsupported vector width");
66 EVT VT = Vec.getValueType();
67 EVT ElVT = VT.getVectorElementType();
68 unsigned Factor = VT.getSizeInBits()/vectorWidth;
69 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
70 VT.getVectorNumElements()/Factor);
72 // Extract from UNDEF is UNDEF.
73 if (Vec.getOpcode() == ISD::UNDEF)
74 return DAG.getUNDEF(ResultVT);
76 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
77 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
79 // This is the index of the first element of the vectorWidth-bit chunk
81 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
84 // If the input is a buildvector just emit a smaller one.
85 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
86 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
87 Vec->op_begin()+NormalizedIdxVal, ElemsPerChunk);
89 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
90 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
96 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
97 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
98 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
99 /// instructions or a simple subregister reference. Idx is an index in the
100 /// 128 bits we want. It need not be aligned to a 128-bit bounday. That makes
101 /// lowering EXTRACT_VECTOR_ELT operations easier.
102 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
103 SelectionDAG &DAG, SDLoc dl) {
104 assert((Vec.getValueType().is256BitVector() ||
105 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
106 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
109 /// Generate a DAG to grab 256-bits from a 512-bit vector.
110 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
111 SelectionDAG &DAG, SDLoc dl) {
112 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
113 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
116 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
117 unsigned IdxVal, SelectionDAG &DAG,
118 SDLoc dl, unsigned vectorWidth) {
119 assert((vectorWidth == 128 || vectorWidth == 256) &&
120 "Unsupported vector width");
121 // Inserting UNDEF is Result
122 if (Vec.getOpcode() == ISD::UNDEF)
124 EVT VT = Vec.getValueType();
125 EVT ElVT = VT.getVectorElementType();
126 EVT ResultVT = Result.getValueType();
128 // Insert the relevant vectorWidth bits.
129 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
131 // This is the index of the first element of the vectorWidth-bit chunk
133 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
136 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
137 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
140 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
141 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
142 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
143 /// simple superregister reference. Idx is an index in the 128 bits
144 /// we want. It need not be aligned to a 128-bit bounday. That makes
145 /// lowering INSERT_VECTOR_ELT operations easier.
146 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
147 unsigned IdxVal, SelectionDAG &DAG,
149 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
150 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
153 static SDValue Insert256BitVector(SDValue Result, SDValue Vec,
154 unsigned IdxVal, SelectionDAG &DAG,
156 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
157 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
160 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
161 /// instructions. This is used because creating CONCAT_VECTOR nodes of
162 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
163 /// large BUILD_VECTORS.
164 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
165 unsigned NumElems, SelectionDAG &DAG,
167 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
168 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
171 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
172 unsigned NumElems, SelectionDAG &DAG,
174 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
175 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
178 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
179 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
180 bool is64Bit = Subtarget->is64Bit();
182 if (Subtarget->isTargetEnvMacho()) {
184 return new X86_64MachoTargetObjectFile();
185 return new TargetLoweringObjectFileMachO();
188 if (Subtarget->isTargetLinux())
189 return new X86LinuxTargetObjectFile();
190 if (Subtarget->isTargetELF())
191 return new TargetLoweringObjectFileELF();
192 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
193 return new TargetLoweringObjectFileCOFF();
194 llvm_unreachable("unknown subtarget type");
197 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
198 : TargetLowering(TM, createTLOF(TM)) {
199 Subtarget = &TM.getSubtarget<X86Subtarget>();
200 X86ScalarSSEf64 = Subtarget->hasSSE2();
201 X86ScalarSSEf32 = Subtarget->hasSSE1();
202 TD = getDataLayout();
204 resetOperationActions();
207 void X86TargetLowering::resetOperationActions() {
208 const TargetMachine &TM = getTargetMachine();
209 static bool FirstTimeThrough = true;
211 // If none of the target options have changed, then we don't need to reset the
212 // operation actions.
213 if (!FirstTimeThrough && TO == TM.Options) return;
215 if (!FirstTimeThrough) {
216 // Reinitialize the actions.
218 FirstTimeThrough = false;
223 // Set up the TargetLowering object.
224 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
226 // X86 is weird, it always uses i8 for shift amounts and setcc results.
227 setBooleanContents(ZeroOrOneBooleanContent);
228 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
229 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
231 // For 64-bit since we have so many registers use the ILP scheduler, for
232 // 32-bit code use the register pressure specific scheduling.
233 // For Atom, always use ILP scheduling.
234 if (Subtarget->isAtom())
235 setSchedulingPreference(Sched::ILP);
236 else if (Subtarget->is64Bit())
237 setSchedulingPreference(Sched::ILP);
239 setSchedulingPreference(Sched::RegPressure);
240 const X86RegisterInfo *RegInfo =
241 static_cast<const X86RegisterInfo*>(TM.getRegisterInfo());
242 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
244 // Bypass expensive divides on Atom when compiling with O2
245 if (Subtarget->hasSlowDivide() && TM.getOptLevel() >= CodeGenOpt::Default) {
246 addBypassSlowDiv(32, 8);
247 if (Subtarget->is64Bit())
248 addBypassSlowDiv(64, 16);
251 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) {
252 // Setup Windows compiler runtime calls.
253 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
254 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
255 setLibcallName(RTLIB::SREM_I64, "_allrem");
256 setLibcallName(RTLIB::UREM_I64, "_aullrem");
257 setLibcallName(RTLIB::MUL_I64, "_allmul");
258 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
259 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
260 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
261 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
262 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
264 // The _ftol2 runtime function has an unusual calling conv, which
265 // is modeled by a special pseudo-instruction.
266 setLibcallName(RTLIB::FPTOUINT_F64_I64, 0);
267 setLibcallName(RTLIB::FPTOUINT_F32_I64, 0);
268 setLibcallName(RTLIB::FPTOUINT_F64_I32, 0);
269 setLibcallName(RTLIB::FPTOUINT_F32_I32, 0);
272 if (Subtarget->isTargetDarwin()) {
273 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
274 setUseUnderscoreSetJmp(false);
275 setUseUnderscoreLongJmp(false);
276 } else if (Subtarget->isTargetMingw()) {
277 // MS runtime is weird: it exports _setjmp, but longjmp!
278 setUseUnderscoreSetJmp(true);
279 setUseUnderscoreLongJmp(false);
281 setUseUnderscoreSetJmp(true);
282 setUseUnderscoreLongJmp(true);
285 // Set up the register classes.
286 addRegisterClass(MVT::i8, &X86::GR8RegClass);
287 addRegisterClass(MVT::i16, &X86::GR16RegClass);
288 addRegisterClass(MVT::i32, &X86::GR32RegClass);
289 if (Subtarget->is64Bit())
290 addRegisterClass(MVT::i64, &X86::GR64RegClass);
292 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
294 // We don't accept any truncstore of integer registers.
295 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
296 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
297 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
298 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
299 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
300 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
302 // SETOEQ and SETUNE require checking two conditions.
303 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
304 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
305 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
306 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
307 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
308 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
310 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
312 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
313 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
314 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
316 if (Subtarget->is64Bit()) {
317 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
318 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
319 } else if (!TM.Options.UseSoftFloat) {
320 // We have an algorithm for SSE2->double, and we turn this into a
321 // 64-bit FILD followed by conditional FADD for other targets.
322 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
323 // We have an algorithm for SSE2, and we turn this into a 64-bit
324 // FILD for other targets.
325 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
328 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
330 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
331 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
333 if (!TM.Options.UseSoftFloat) {
334 // SSE has no i16 to fp conversion, only i32
335 if (X86ScalarSSEf32) {
336 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
337 // f32 and f64 cases are Legal, f80 case is not
338 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
340 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
341 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
344 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
345 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
348 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
349 // are Legal, f80 is custom lowered.
350 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
351 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
353 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
355 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
356 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
358 if (X86ScalarSSEf32) {
359 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
360 // f32 and f64 cases are Legal, f80 case is not
361 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
363 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
364 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
367 // Handle FP_TO_UINT by promoting the destination to a larger signed
369 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
370 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
371 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
373 if (Subtarget->is64Bit()) {
374 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
375 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
376 } else if (!TM.Options.UseSoftFloat) {
377 // Since AVX is a superset of SSE3, only check for SSE here.
378 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
379 // Expand FP_TO_UINT into a select.
380 // FIXME: We would like to use a Custom expander here eventually to do
381 // the optimal thing for SSE vs. the default expansion in the legalizer.
382 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
384 // With SSE3 we can use fisttpll to convert to a signed i64; without
385 // SSE, we're stuck with a fistpll.
386 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
389 if (isTargetFTOL()) {
390 // Use the _ftol2 runtime function, which has a pseudo-instruction
391 // to handle its weird calling convention.
392 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
395 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
396 if (!X86ScalarSSEf64) {
397 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
398 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
399 if (Subtarget->is64Bit()) {
400 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
401 // Without SSE, i64->f64 goes through memory.
402 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
406 // Scalar integer divide and remainder are lowered to use operations that
407 // produce two results, to match the available instructions. This exposes
408 // the two-result form to trivial CSE, which is able to combine x/y and x%y
409 // into a single instruction.
411 // Scalar integer multiply-high is also lowered to use two-result
412 // operations, to match the available instructions. However, plain multiply
413 // (low) operations are left as Legal, as there are single-result
414 // instructions for this in x86. Using the two-result multiply instructions
415 // when both high and low results are needed must be arranged by dagcombine.
416 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
418 setOperationAction(ISD::MULHS, VT, Expand);
419 setOperationAction(ISD::MULHU, VT, Expand);
420 setOperationAction(ISD::SDIV, VT, Expand);
421 setOperationAction(ISD::UDIV, VT, Expand);
422 setOperationAction(ISD::SREM, VT, Expand);
423 setOperationAction(ISD::UREM, VT, Expand);
425 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
426 setOperationAction(ISD::ADDC, VT, Custom);
427 setOperationAction(ISD::ADDE, VT, Custom);
428 setOperationAction(ISD::SUBC, VT, Custom);
429 setOperationAction(ISD::SUBE, VT, Custom);
432 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
433 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
434 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
435 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
436 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
437 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
438 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
439 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
440 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
441 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
442 if (Subtarget->is64Bit())
443 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
444 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
445 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
446 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
447 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
448 setOperationAction(ISD::FREM , MVT::f32 , Expand);
449 setOperationAction(ISD::FREM , MVT::f64 , Expand);
450 setOperationAction(ISD::FREM , MVT::f80 , Expand);
451 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
453 // Promote the i8 variants and force them on up to i32 which has a shorter
455 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
456 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
457 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
458 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
459 if (Subtarget->hasBMI()) {
460 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
461 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
462 if (Subtarget->is64Bit())
463 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
465 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
466 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
467 if (Subtarget->is64Bit())
468 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
471 if (Subtarget->hasLZCNT()) {
472 // When promoting the i8 variants, force them to i32 for a shorter
474 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
475 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
476 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
477 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
478 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
479 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
480 if (Subtarget->is64Bit())
481 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
483 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
484 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
485 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
486 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
487 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
488 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
489 if (Subtarget->is64Bit()) {
490 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
491 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
495 if (Subtarget->hasPOPCNT()) {
496 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
498 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
499 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
500 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
501 if (Subtarget->is64Bit())
502 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
505 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
506 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
508 // These should be promoted to a larger select which is supported.
509 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
510 // X86 wants to expand cmov itself.
511 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
512 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
513 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
514 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
515 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
516 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
517 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
518 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
519 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
520 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
521 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
522 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
523 if (Subtarget->is64Bit()) {
524 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
525 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
527 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
528 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
529 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
530 // support continuation, user-level threading, and etc.. As a result, no
531 // other SjLj exception interfaces are implemented and please don't build
532 // your own exception handling based on them.
533 // LLVM/Clang supports zero-cost DWARF exception handling.
534 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
535 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
538 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
539 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
540 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
541 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
542 if (Subtarget->is64Bit())
543 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
544 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
545 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
546 if (Subtarget->is64Bit()) {
547 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
548 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
549 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
550 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
551 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
553 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
554 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
555 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
556 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
557 if (Subtarget->is64Bit()) {
558 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
559 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
560 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
563 if (Subtarget->hasSSE1())
564 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
566 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
568 // Expand certain atomics
569 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
571 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom);
572 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
573 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
576 if (!Subtarget->is64Bit()) {
577 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
578 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
579 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
580 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
581 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
582 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
583 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
584 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
585 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i64, Custom);
586 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i64, Custom);
587 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i64, Custom);
588 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i64, Custom);
591 if (Subtarget->hasCmpxchg16b()) {
592 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom);
595 // FIXME - use subtarget debug flags
596 if (!Subtarget->isTargetDarwin() &&
597 !Subtarget->isTargetELF() &&
598 !Subtarget->isTargetCygMing()) {
599 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
602 if (Subtarget->is64Bit()) {
603 setExceptionPointerRegister(X86::RAX);
604 setExceptionSelectorRegister(X86::RDX);
606 setExceptionPointerRegister(X86::EAX);
607 setExceptionSelectorRegister(X86::EDX);
609 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
610 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
612 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
613 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
615 setOperationAction(ISD::TRAP, MVT::Other, Legal);
616 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
618 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
619 setOperationAction(ISD::VASTART , MVT::Other, Custom);
620 setOperationAction(ISD::VAEND , MVT::Other, Expand);
621 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
622 // TargetInfo::X86_64ABIBuiltinVaList
623 setOperationAction(ISD::VAARG , MVT::Other, Custom);
624 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
626 // TargetInfo::CharPtrBuiltinVaList
627 setOperationAction(ISD::VAARG , MVT::Other, Expand);
628 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
631 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
632 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
634 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
635 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
636 MVT::i64 : MVT::i32, Custom);
637 else if (TM.Options.EnableSegmentedStacks)
638 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
639 MVT::i64 : MVT::i32, Custom);
641 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
642 MVT::i64 : MVT::i32, Expand);
644 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
645 // f32 and f64 use SSE.
646 // Set up the FP register classes.
647 addRegisterClass(MVT::f32, &X86::FR32RegClass);
648 addRegisterClass(MVT::f64, &X86::FR64RegClass);
650 // Use ANDPD to simulate FABS.
651 setOperationAction(ISD::FABS , MVT::f64, Custom);
652 setOperationAction(ISD::FABS , MVT::f32, Custom);
654 // Use XORP to simulate FNEG.
655 setOperationAction(ISD::FNEG , MVT::f64, Custom);
656 setOperationAction(ISD::FNEG , MVT::f32, Custom);
658 // Use ANDPD and ORPD to simulate FCOPYSIGN.
659 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
660 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
662 // Lower this to FGETSIGNx86 plus an AND.
663 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
664 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
666 // We don't support sin/cos/fmod
667 setOperationAction(ISD::FSIN , MVT::f64, Expand);
668 setOperationAction(ISD::FCOS , MVT::f64, Expand);
669 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
670 setOperationAction(ISD::FSIN , MVT::f32, Expand);
671 setOperationAction(ISD::FCOS , MVT::f32, Expand);
672 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
674 // Expand FP immediates into loads from the stack, except for the special
676 addLegalFPImmediate(APFloat(+0.0)); // xorpd
677 addLegalFPImmediate(APFloat(+0.0f)); // xorps
678 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
679 // Use SSE for f32, x87 for f64.
680 // Set up the FP register classes.
681 addRegisterClass(MVT::f32, &X86::FR32RegClass);
682 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
684 // Use ANDPS to simulate FABS.
685 setOperationAction(ISD::FABS , MVT::f32, Custom);
687 // Use XORP to simulate FNEG.
688 setOperationAction(ISD::FNEG , MVT::f32, Custom);
690 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
692 // Use ANDPS and ORPS to simulate FCOPYSIGN.
693 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
694 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
696 // We don't support sin/cos/fmod
697 setOperationAction(ISD::FSIN , MVT::f32, Expand);
698 setOperationAction(ISD::FCOS , MVT::f32, Expand);
699 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
701 // Special cases we handle for FP constants.
702 addLegalFPImmediate(APFloat(+0.0f)); // xorps
703 addLegalFPImmediate(APFloat(+0.0)); // FLD0
704 addLegalFPImmediate(APFloat(+1.0)); // FLD1
705 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
706 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
708 if (!TM.Options.UnsafeFPMath) {
709 setOperationAction(ISD::FSIN , MVT::f64, Expand);
710 setOperationAction(ISD::FCOS , MVT::f64, Expand);
711 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
713 } else if (!TM.Options.UseSoftFloat) {
714 // f32 and f64 in x87.
715 // Set up the FP register classes.
716 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
717 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
719 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
720 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
721 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
722 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
724 if (!TM.Options.UnsafeFPMath) {
725 setOperationAction(ISD::FSIN , MVT::f64, Expand);
726 setOperationAction(ISD::FSIN , MVT::f32, Expand);
727 setOperationAction(ISD::FCOS , MVT::f64, Expand);
728 setOperationAction(ISD::FCOS , MVT::f32, Expand);
729 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
730 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
732 addLegalFPImmediate(APFloat(+0.0)); // FLD0
733 addLegalFPImmediate(APFloat(+1.0)); // FLD1
734 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
735 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
736 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
737 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
738 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
739 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
742 // We don't support FMA.
743 setOperationAction(ISD::FMA, MVT::f64, Expand);
744 setOperationAction(ISD::FMA, MVT::f32, Expand);
746 // Long double always uses X87.
747 if (!TM.Options.UseSoftFloat) {
748 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
749 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
750 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
752 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
753 addLegalFPImmediate(TmpFlt); // FLD0
755 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
758 APFloat TmpFlt2(+1.0);
759 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
761 addLegalFPImmediate(TmpFlt2); // FLD1
762 TmpFlt2.changeSign();
763 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
766 if (!TM.Options.UnsafeFPMath) {
767 setOperationAction(ISD::FSIN , MVT::f80, Expand);
768 setOperationAction(ISD::FCOS , MVT::f80, Expand);
769 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
772 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
773 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
774 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
775 setOperationAction(ISD::FRINT, MVT::f80, Expand);
776 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
777 setOperationAction(ISD::FMA, MVT::f80, Expand);
780 // Always use a library call for pow.
781 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
782 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
783 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
785 setOperationAction(ISD::FLOG, MVT::f80, Expand);
786 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
787 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
788 setOperationAction(ISD::FEXP, MVT::f80, Expand);
789 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
791 // First set operation action for all vector types to either promote
792 // (for widening) or expand (for scalarization). Then we will selectively
793 // turn on ones that can be effectively codegen'd.
794 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
795 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
796 MVT VT = (MVT::SimpleValueType)i;
797 setOperationAction(ISD::ADD , VT, Expand);
798 setOperationAction(ISD::SUB , VT, Expand);
799 setOperationAction(ISD::FADD, VT, Expand);
800 setOperationAction(ISD::FNEG, VT, Expand);
801 setOperationAction(ISD::FSUB, VT, Expand);
802 setOperationAction(ISD::MUL , VT, Expand);
803 setOperationAction(ISD::FMUL, VT, Expand);
804 setOperationAction(ISD::SDIV, VT, Expand);
805 setOperationAction(ISD::UDIV, VT, Expand);
806 setOperationAction(ISD::FDIV, VT, Expand);
807 setOperationAction(ISD::SREM, VT, Expand);
808 setOperationAction(ISD::UREM, VT, Expand);
809 setOperationAction(ISD::LOAD, VT, Expand);
810 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
811 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
812 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
813 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
814 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
815 setOperationAction(ISD::FABS, VT, Expand);
816 setOperationAction(ISD::FSIN, VT, Expand);
817 setOperationAction(ISD::FSINCOS, VT, Expand);
818 setOperationAction(ISD::FCOS, VT, Expand);
819 setOperationAction(ISD::FSINCOS, VT, Expand);
820 setOperationAction(ISD::FREM, VT, Expand);
821 setOperationAction(ISD::FMA, VT, Expand);
822 setOperationAction(ISD::FPOWI, VT, Expand);
823 setOperationAction(ISD::FSQRT, VT, Expand);
824 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
825 setOperationAction(ISD::FFLOOR, VT, Expand);
826 setOperationAction(ISD::FCEIL, VT, Expand);
827 setOperationAction(ISD::FTRUNC, VT, Expand);
828 setOperationAction(ISD::FRINT, VT, Expand);
829 setOperationAction(ISD::FNEARBYINT, VT, Expand);
830 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
831 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
832 setOperationAction(ISD::SDIVREM, VT, Expand);
833 setOperationAction(ISD::UDIVREM, VT, Expand);
834 setOperationAction(ISD::FPOW, VT, Expand);
835 setOperationAction(ISD::CTPOP, VT, Expand);
836 setOperationAction(ISD::CTTZ, VT, Expand);
837 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
838 setOperationAction(ISD::CTLZ, VT, Expand);
839 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
840 setOperationAction(ISD::SHL, VT, Expand);
841 setOperationAction(ISD::SRA, VT, Expand);
842 setOperationAction(ISD::SRL, VT, Expand);
843 setOperationAction(ISD::ROTL, VT, Expand);
844 setOperationAction(ISD::ROTR, VT, Expand);
845 setOperationAction(ISD::BSWAP, VT, Expand);
846 setOperationAction(ISD::SETCC, VT, Expand);
847 setOperationAction(ISD::FLOG, VT, Expand);
848 setOperationAction(ISD::FLOG2, VT, Expand);
849 setOperationAction(ISD::FLOG10, VT, Expand);
850 setOperationAction(ISD::FEXP, VT, Expand);
851 setOperationAction(ISD::FEXP2, VT, Expand);
852 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
853 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
854 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
855 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
856 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
857 setOperationAction(ISD::TRUNCATE, VT, Expand);
858 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
859 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
860 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
861 setOperationAction(ISD::VSELECT, VT, Expand);
862 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
863 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
864 setTruncStoreAction(VT,
865 (MVT::SimpleValueType)InnerVT, Expand);
866 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
867 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
868 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
871 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
872 // with -msoft-float, disable use of MMX as well.
873 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
874 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
875 // No operations on x86mmx supported, everything uses intrinsics.
878 // MMX-sized vectors (other than x86mmx) are expected to be expanded
879 // into smaller operations.
880 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
881 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
882 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
883 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
884 setOperationAction(ISD::AND, MVT::v8i8, Expand);
885 setOperationAction(ISD::AND, MVT::v4i16, Expand);
886 setOperationAction(ISD::AND, MVT::v2i32, Expand);
887 setOperationAction(ISD::AND, MVT::v1i64, Expand);
888 setOperationAction(ISD::OR, MVT::v8i8, Expand);
889 setOperationAction(ISD::OR, MVT::v4i16, Expand);
890 setOperationAction(ISD::OR, MVT::v2i32, Expand);
891 setOperationAction(ISD::OR, MVT::v1i64, Expand);
892 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
893 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
894 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
895 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
896 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
897 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
898 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
899 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
900 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
901 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
902 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
903 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
904 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
905 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
906 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
907 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
908 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
910 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
911 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
913 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
914 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
915 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
916 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
917 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
918 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
919 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
920 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
921 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
922 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
923 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
924 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
927 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
928 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
930 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
931 // registers cannot be used even for integer operations.
932 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
933 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
934 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
935 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
937 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
938 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
939 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
940 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
941 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
942 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
943 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
944 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
945 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
946 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
947 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
948 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
949 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
950 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
951 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
952 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
953 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
954 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
956 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
957 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
958 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
959 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
961 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
962 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
963 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
964 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
965 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
967 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
968 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
969 MVT VT = (MVT::SimpleValueType)i;
970 // Do not attempt to custom lower non-power-of-2 vectors
971 if (!isPowerOf2_32(VT.getVectorNumElements()))
973 // Do not attempt to custom lower non-128-bit vectors
974 if (!VT.is128BitVector())
976 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
977 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
978 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
981 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
982 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
983 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
984 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
985 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
986 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
988 if (Subtarget->is64Bit()) {
989 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
990 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
993 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
994 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
995 MVT VT = (MVT::SimpleValueType)i;
997 // Do not attempt to promote non-128-bit vectors
998 if (!VT.is128BitVector())
1001 setOperationAction(ISD::AND, VT, Promote);
1002 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1003 setOperationAction(ISD::OR, VT, Promote);
1004 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1005 setOperationAction(ISD::XOR, VT, Promote);
1006 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1007 setOperationAction(ISD::LOAD, VT, Promote);
1008 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1009 setOperationAction(ISD::SELECT, VT, Promote);
1010 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1013 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
1015 // Custom lower v2i64 and v2f64 selects.
1016 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1017 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1018 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1019 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1021 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1022 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1024 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1025 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1026 // As there is no 64-bit GPR available, we need build a special custom
1027 // sequence to convert from v2i32 to v2f32.
1028 if (!Subtarget->is64Bit())
1029 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1031 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1032 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1034 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
1037 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1038 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1039 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1040 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1041 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1042 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1043 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1044 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1045 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1046 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1047 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1049 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1050 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1051 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1052 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1053 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1054 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1055 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1056 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1057 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1058 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1060 // FIXME: Do we need to handle scalar-to-vector here?
1061 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1063 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
1064 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal);
1065 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1066 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
1067 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
1069 // i8 and i16 vectors are custom , because the source register and source
1070 // source memory operand types are not the same width. f32 vectors are
1071 // custom since the immediate controlling the insert encodes additional
1073 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1074 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1075 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1076 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1078 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1079 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1080 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1081 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1083 // FIXME: these should be Legal but thats only for the case where
1084 // the index is constant. For now custom expand to deal with that.
1085 if (Subtarget->is64Bit()) {
1086 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1087 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1091 if (Subtarget->hasSSE2()) {
1092 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1093 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1095 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1096 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1098 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1099 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1101 // In the customized shift lowering, the legal cases in AVX2 will be
1103 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1104 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1106 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1107 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1109 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1111 setOperationAction(ISD::SDIV, MVT::v8i16, Custom);
1112 setOperationAction(ISD::SDIV, MVT::v4i32, Custom);
1115 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1116 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1117 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1118 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1119 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1120 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1121 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1123 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1124 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1125 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1127 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1128 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1129 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1130 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1131 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1132 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1133 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1134 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1135 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1136 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1137 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1138 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1140 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1141 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1142 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1143 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1144 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1145 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1146 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1147 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1148 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1149 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1150 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1151 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1153 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1154 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1156 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Custom);
1158 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1159 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1160 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1161 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1163 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1164 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1165 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1167 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1169 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1170 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1172 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1173 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1175 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1176 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1178 setOperationAction(ISD::SDIV, MVT::v16i16, Custom);
1180 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1181 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1182 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1183 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1185 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1186 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1187 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1189 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal);
1190 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal);
1191 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal);
1192 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal);
1194 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1195 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1196 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1197 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1198 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1199 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1201 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1202 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1203 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1204 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1205 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1206 setOperationAction(ISD::FMA, MVT::f32, Legal);
1207 setOperationAction(ISD::FMA, MVT::f64, Legal);
1210 if (Subtarget->hasInt256()) {
1211 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1212 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1213 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1214 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1216 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1217 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1218 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1219 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1221 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1222 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1223 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1224 // Don't lower v32i8 because there is no 128-bit byte mul
1226 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1228 setOperationAction(ISD::SDIV, MVT::v8i32, Custom);
1230 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1231 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1232 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1233 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1235 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1236 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1237 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1238 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1240 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1241 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1242 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1243 // Don't lower v32i8 because there is no 128-bit byte mul
1246 // In the customized shift lowering, the legal cases in AVX2 will be
1248 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1249 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1251 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1252 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1254 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1256 // Custom lower several nodes for 256-bit types.
1257 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1258 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1259 MVT VT = (MVT::SimpleValueType)i;
1261 // Extract subvector is special because the value type
1262 // (result) is 128-bit but the source is 256-bit wide.
1263 if (VT.is128BitVector())
1264 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1266 // Do not attempt to custom lower other non-256-bit vectors
1267 if (!VT.is256BitVector())
1270 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1271 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1272 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1273 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1274 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1275 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1276 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1279 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1280 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1281 MVT VT = (MVT::SimpleValueType)i;
1283 // Do not attempt to promote non-256-bit vectors
1284 if (!VT.is256BitVector())
1287 setOperationAction(ISD::AND, VT, Promote);
1288 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1289 setOperationAction(ISD::OR, VT, Promote);
1290 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1291 setOperationAction(ISD::XOR, VT, Promote);
1292 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1293 setOperationAction(ISD::LOAD, VT, Promote);
1294 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1295 setOperationAction(ISD::SELECT, VT, Promote);
1296 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1300 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1301 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1302 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1303 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1304 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1306 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1307 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1309 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, Legal);
1310 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1311 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1312 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1313 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1314 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1316 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1317 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1318 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1319 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1320 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1321 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1323 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1324 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1325 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1326 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1327 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1328 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1329 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1330 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1331 setOperationAction(ISD::SDIV, MVT::v16i32, Custom);
1334 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1335 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1336 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1337 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1338 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1339 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1340 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1341 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1343 setOperationAction(ISD::TRUNCATE, MVT::i1, Legal);
1344 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1345 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1346 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1347 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1348 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1349 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1350 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1351 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1352 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1353 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1354 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1356 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1357 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1358 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1359 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1360 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1362 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1363 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1365 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1367 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1368 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1369 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1370 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1371 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1373 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1374 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1376 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1377 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1379 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1381 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1382 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1384 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1385 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1387 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1388 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1390 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1391 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1392 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1393 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1394 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1395 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1397 // Custom lower several nodes.
1398 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1399 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1400 MVT VT = (MVT::SimpleValueType)i;
1402 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1403 // Extract subvector is special because the value type
1404 // (result) is 256/128-bit but the source is 512-bit wide.
1405 if (VT.is128BitVector() || VT.is256BitVector())
1406 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1408 if (VT.getVectorElementType() == MVT::i1)
1409 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1411 // Do not attempt to custom lower other non-512-bit vectors
1412 if (!VT.is512BitVector())
1415 if ( EltSize >= 32) {
1416 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1417 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1418 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1419 setOperationAction(ISD::VSELECT, VT, Legal);
1420 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1421 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1422 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1425 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1426 MVT VT = (MVT::SimpleValueType)i;
1428 // Do not attempt to promote non-256-bit vectors
1429 if (!VT.is512BitVector())
1432 setOperationAction(ISD::SELECT, VT, Promote);
1433 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1437 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1438 // of this type with custom code.
1439 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1440 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1441 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1445 // We want to custom lower some of our intrinsics.
1446 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1447 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1449 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1450 // handle type legalization for these operations here.
1452 // FIXME: We really should do custom legalization for addition and
1453 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1454 // than generic legalization for 64-bit multiplication-with-overflow, though.
1455 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1456 // Add/Sub/Mul with overflow operations are custom lowered.
1458 setOperationAction(ISD::SADDO, VT, Custom);
1459 setOperationAction(ISD::UADDO, VT, Custom);
1460 setOperationAction(ISD::SSUBO, VT, Custom);
1461 setOperationAction(ISD::USUBO, VT, Custom);
1462 setOperationAction(ISD::SMULO, VT, Custom);
1463 setOperationAction(ISD::UMULO, VT, Custom);
1466 // There are no 8-bit 3-address imul/mul instructions
1467 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1468 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1470 if (!Subtarget->is64Bit()) {
1471 // These libcalls are not available in 32-bit.
1472 setLibcallName(RTLIB::SHL_I128, 0);
1473 setLibcallName(RTLIB::SRL_I128, 0);
1474 setLibcallName(RTLIB::SRA_I128, 0);
1477 // Combine sin / cos into one node or libcall if possible.
1478 if (Subtarget->hasSinCos()) {
1479 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1480 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1481 if (Subtarget->isTargetDarwin()) {
1482 // For MacOSX, we don't want to the normal expansion of a libcall to
1483 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
1485 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1486 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1490 // We have target-specific dag combine patterns for the following nodes:
1491 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1492 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1493 setTargetDAGCombine(ISD::VSELECT);
1494 setTargetDAGCombine(ISD::SELECT);
1495 setTargetDAGCombine(ISD::SHL);
1496 setTargetDAGCombine(ISD::SRA);
1497 setTargetDAGCombine(ISD::SRL);
1498 setTargetDAGCombine(ISD::OR);
1499 setTargetDAGCombine(ISD::AND);
1500 setTargetDAGCombine(ISD::ADD);
1501 setTargetDAGCombine(ISD::FADD);
1502 setTargetDAGCombine(ISD::FSUB);
1503 setTargetDAGCombine(ISD::FMA);
1504 setTargetDAGCombine(ISD::SUB);
1505 setTargetDAGCombine(ISD::LOAD);
1506 setTargetDAGCombine(ISD::STORE);
1507 setTargetDAGCombine(ISD::ZERO_EXTEND);
1508 setTargetDAGCombine(ISD::ANY_EXTEND);
1509 setTargetDAGCombine(ISD::SIGN_EXTEND);
1510 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1511 setTargetDAGCombine(ISD::TRUNCATE);
1512 setTargetDAGCombine(ISD::SINT_TO_FP);
1513 setTargetDAGCombine(ISD::SETCC);
1514 if (Subtarget->is64Bit())
1515 setTargetDAGCombine(ISD::MUL);
1516 setTargetDAGCombine(ISD::XOR);
1518 computeRegisterProperties();
1520 // On Darwin, -Os means optimize for size without hurting performance,
1521 // do not reduce the limit.
1522 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1523 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1524 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1525 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1526 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1527 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1528 setPrefLoopAlignment(4); // 2^4 bytes.
1530 // Predictable cmov don't hurt on atom because it's in-order.
1531 PredictableSelectIsExpensive = !Subtarget->isAtom();
1533 setPrefFunctionAlignment(4); // 2^4 bytes.
1536 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1537 if (!VT.isVector()) return MVT::i8;
1538 return VT.changeVectorElementTypeToInteger();
1541 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1542 /// the desired ByVal argument alignment.
1543 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1546 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1547 if (VTy->getBitWidth() == 128)
1549 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1550 unsigned EltAlign = 0;
1551 getMaxByValAlign(ATy->getElementType(), EltAlign);
1552 if (EltAlign > MaxAlign)
1553 MaxAlign = EltAlign;
1554 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1555 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1556 unsigned EltAlign = 0;
1557 getMaxByValAlign(STy->getElementType(i), EltAlign);
1558 if (EltAlign > MaxAlign)
1559 MaxAlign = EltAlign;
1566 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1567 /// function arguments in the caller parameter area. For X86, aggregates
1568 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1569 /// are at 4-byte boundaries.
1570 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1571 if (Subtarget->is64Bit()) {
1572 // Max of 8 and alignment of type.
1573 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1580 if (Subtarget->hasSSE1())
1581 getMaxByValAlign(Ty, Align);
1585 /// getOptimalMemOpType - Returns the target specific optimal type for load
1586 /// and store operations as a result of memset, memcpy, and memmove
1587 /// lowering. If DstAlign is zero that means it's safe to destination
1588 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1589 /// means there isn't a need to check it against alignment requirement,
1590 /// probably because the source does not need to be loaded. If 'IsMemset' is
1591 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1592 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1593 /// source is constant so it does not need to be loaded.
1594 /// It returns EVT::Other if the type should be determined using generic
1595 /// target-independent logic.
1597 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1598 unsigned DstAlign, unsigned SrcAlign,
1599 bool IsMemset, bool ZeroMemset,
1601 MachineFunction &MF) const {
1602 const Function *F = MF.getFunction();
1603 if ((!IsMemset || ZeroMemset) &&
1604 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1605 Attribute::NoImplicitFloat)) {
1607 (Subtarget->isUnalignedMemAccessFast() ||
1608 ((DstAlign == 0 || DstAlign >= 16) &&
1609 (SrcAlign == 0 || SrcAlign >= 16)))) {
1611 if (Subtarget->hasInt256())
1613 if (Subtarget->hasFp256())
1616 if (Subtarget->hasSSE2())
1618 if (Subtarget->hasSSE1())
1620 } else if (!MemcpyStrSrc && Size >= 8 &&
1621 !Subtarget->is64Bit() &&
1622 Subtarget->hasSSE2()) {
1623 // Do not use f64 to lower memcpy if source is string constant. It's
1624 // better to use i32 to avoid the loads.
1628 if (Subtarget->is64Bit() && Size >= 8)
1633 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1635 return X86ScalarSSEf32;
1636 else if (VT == MVT::f64)
1637 return X86ScalarSSEf64;
1642 X86TargetLowering::allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const {
1644 *Fast = Subtarget->isUnalignedMemAccessFast();
1648 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1649 /// current function. The returned value is a member of the
1650 /// MachineJumpTableInfo::JTEntryKind enum.
1651 unsigned X86TargetLowering::getJumpTableEncoding() const {
1652 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1654 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1655 Subtarget->isPICStyleGOT())
1656 return MachineJumpTableInfo::EK_Custom32;
1658 // Otherwise, use the normal jump table encoding heuristics.
1659 return TargetLowering::getJumpTableEncoding();
1663 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1664 const MachineBasicBlock *MBB,
1665 unsigned uid,MCContext &Ctx) const{
1666 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1667 Subtarget->isPICStyleGOT());
1668 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1670 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1671 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1674 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1676 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1677 SelectionDAG &DAG) const {
1678 if (!Subtarget->is64Bit())
1679 // This doesn't have SDLoc associated with it, but is not really the
1680 // same as a Register.
1681 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1685 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1686 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1688 const MCExpr *X86TargetLowering::
1689 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1690 MCContext &Ctx) const {
1691 // X86-64 uses RIP relative addressing based on the jump table label.
1692 if (Subtarget->isPICStyleRIPRel())
1693 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1695 // Otherwise, the reference is relative to the PIC base.
1696 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1699 // FIXME: Why this routine is here? Move to RegInfo!
1700 std::pair<const TargetRegisterClass*, uint8_t>
1701 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1702 const TargetRegisterClass *RRC = 0;
1704 switch (VT.SimpleTy) {
1706 return TargetLowering::findRepresentativeClass(VT);
1707 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1708 RRC = Subtarget->is64Bit() ?
1709 (const TargetRegisterClass*)&X86::GR64RegClass :
1710 (const TargetRegisterClass*)&X86::GR32RegClass;
1713 RRC = &X86::VR64RegClass;
1715 case MVT::f32: case MVT::f64:
1716 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1717 case MVT::v4f32: case MVT::v2f64:
1718 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1720 RRC = &X86::VR128RegClass;
1723 return std::make_pair(RRC, Cost);
1726 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1727 unsigned &Offset) const {
1728 if (!Subtarget->isTargetLinux())
1731 if (Subtarget->is64Bit()) {
1732 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1734 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1746 //===----------------------------------------------------------------------===//
1747 // Return Value Calling Convention Implementation
1748 //===----------------------------------------------------------------------===//
1750 #include "X86GenCallingConv.inc"
1753 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1754 MachineFunction &MF, bool isVarArg,
1755 const SmallVectorImpl<ISD::OutputArg> &Outs,
1756 LLVMContext &Context) const {
1757 SmallVector<CCValAssign, 16> RVLocs;
1758 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1760 return CCInfo.CheckReturn(Outs, RetCC_X86);
1764 X86TargetLowering::LowerReturn(SDValue Chain,
1765 CallingConv::ID CallConv, bool isVarArg,
1766 const SmallVectorImpl<ISD::OutputArg> &Outs,
1767 const SmallVectorImpl<SDValue> &OutVals,
1768 SDLoc dl, SelectionDAG &DAG) const {
1769 MachineFunction &MF = DAG.getMachineFunction();
1770 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1772 SmallVector<CCValAssign, 16> RVLocs;
1773 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1774 RVLocs, *DAG.getContext());
1775 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1778 SmallVector<SDValue, 6> RetOps;
1779 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1780 // Operand #1 = Bytes To Pop
1781 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1784 // Copy the result values into the output registers.
1785 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1786 CCValAssign &VA = RVLocs[i];
1787 assert(VA.isRegLoc() && "Can only return in registers!");
1788 SDValue ValToCopy = OutVals[i];
1789 EVT ValVT = ValToCopy.getValueType();
1791 // Promote values to the appropriate types
1792 if (VA.getLocInfo() == CCValAssign::SExt)
1793 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
1794 else if (VA.getLocInfo() == CCValAssign::ZExt)
1795 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
1796 else if (VA.getLocInfo() == CCValAssign::AExt)
1797 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
1798 else if (VA.getLocInfo() == CCValAssign::BCvt)
1799 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
1801 // If this is x86-64, and we disabled SSE, we can't return FP values,
1802 // or SSE or MMX vectors.
1803 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1804 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1805 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1806 report_fatal_error("SSE register return with SSE disabled");
1808 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1809 // llvm-gcc has never done it right and no one has noticed, so this
1810 // should be OK for now.
1811 if (ValVT == MVT::f64 &&
1812 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1813 report_fatal_error("SSE2 register return with SSE2 disabled");
1815 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1816 // the RET instruction and handled by the FP Stackifier.
1817 if (VA.getLocReg() == X86::ST0 ||
1818 VA.getLocReg() == X86::ST1) {
1819 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1820 // change the value to the FP stack register class.
1821 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1822 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1823 RetOps.push_back(ValToCopy);
1824 // Don't emit a copytoreg.
1828 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1829 // which is returned in RAX / RDX.
1830 if (Subtarget->is64Bit()) {
1831 if (ValVT == MVT::x86mmx) {
1832 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1833 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1834 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1836 // If we don't have SSE2 available, convert to v4f32 so the generated
1837 // register is legal.
1838 if (!Subtarget->hasSSE2())
1839 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1844 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1845 Flag = Chain.getValue(1);
1846 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
1849 // The x86-64 ABIs require that for returning structs by value we copy
1850 // the sret argument into %rax/%eax (depending on ABI) for the return.
1851 // Win32 requires us to put the sret argument to %eax as well.
1852 // We saved the argument into a virtual register in the entry block,
1853 // so now we copy the value out and into %rax/%eax.
1854 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
1855 (Subtarget->is64Bit() || Subtarget->isTargetWindows())) {
1856 MachineFunction &MF = DAG.getMachineFunction();
1857 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1858 unsigned Reg = FuncInfo->getSRetReturnReg();
1860 "SRetReturnReg should have been set in LowerFormalArguments().");
1861 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1864 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
1865 X86::RAX : X86::EAX;
1866 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
1867 Flag = Chain.getValue(1);
1869 // RAX/EAX now acts like a return value.
1870 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
1873 RetOps[0] = Chain; // Update chain.
1875 // Add the flag if we have it.
1877 RetOps.push_back(Flag);
1879 return DAG.getNode(X86ISD::RET_FLAG, dl,
1880 MVT::Other, &RetOps[0], RetOps.size());
1883 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
1884 if (N->getNumValues() != 1)
1886 if (!N->hasNUsesOfValue(1, 0))
1889 SDValue TCChain = Chain;
1890 SDNode *Copy = *N->use_begin();
1891 if (Copy->getOpcode() == ISD::CopyToReg) {
1892 // If the copy has a glue operand, we conservatively assume it isn't safe to
1893 // perform a tail call.
1894 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
1896 TCChain = Copy->getOperand(0);
1897 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
1900 bool HasRet = false;
1901 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1903 if (UI->getOpcode() != X86ISD::RET_FLAG)
1916 X86TargetLowering::getTypeForExtArgOrReturn(MVT VT,
1917 ISD::NodeType ExtendKind) const {
1919 // TODO: Is this also valid on 32-bit?
1920 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
1921 ReturnMVT = MVT::i8;
1923 ReturnMVT = MVT::i32;
1925 MVT MinVT = getRegisterType(ReturnMVT);
1926 return VT.bitsLT(MinVT) ? MinVT : VT;
1929 /// LowerCallResult - Lower the result values of a call into the
1930 /// appropriate copies out of appropriate physical registers.
1933 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1934 CallingConv::ID CallConv, bool isVarArg,
1935 const SmallVectorImpl<ISD::InputArg> &Ins,
1936 SDLoc dl, SelectionDAG &DAG,
1937 SmallVectorImpl<SDValue> &InVals) const {
1939 // Assign locations to each value returned by this call.
1940 SmallVector<CCValAssign, 16> RVLocs;
1941 bool Is64Bit = Subtarget->is64Bit();
1942 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1943 getTargetMachine(), RVLocs, *DAG.getContext());
1944 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1946 // Copy all of the result registers out of their specified physreg.
1947 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
1948 CCValAssign &VA = RVLocs[i];
1949 EVT CopyVT = VA.getValVT();
1951 // If this is x86-64, and we disabled SSE, we can't return FP values
1952 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1953 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
1954 report_fatal_error("SSE register return with SSE disabled");
1959 // If this is a call to a function that returns an fp value on the floating
1960 // point stack, we must guarantee the value is popped from the stack, so
1961 // a CopyFromReg is not good enough - the copy instruction may be eliminated
1962 // if the return value is not used. We use the FpPOP_RETVAL instruction
1964 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
1965 // If we prefer to use the value in xmm registers, copy it out as f80 and
1966 // use a truncate to move it from fp stack reg to xmm reg.
1967 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
1968 SDValue Ops[] = { Chain, InFlag };
1969 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT,
1970 MVT::Other, MVT::Glue, Ops), 1);
1971 Val = Chain.getValue(0);
1973 // Round the f80 to the right size, which also moves it to the appropriate
1975 if (CopyVT != VA.getValVT())
1976 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1977 // This truncation won't change the value.
1978 DAG.getIntPtrConstant(1));
1980 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1981 CopyVT, InFlag).getValue(1);
1982 Val = Chain.getValue(0);
1984 InFlag = Chain.getValue(2);
1985 InVals.push_back(Val);
1991 //===----------------------------------------------------------------------===//
1992 // C & StdCall & Fast Calling Convention implementation
1993 //===----------------------------------------------------------------------===//
1994 // StdCall calling convention seems to be standard for many Windows' API
1995 // routines and around. It differs from C calling convention just a little:
1996 // callee should clean up the stack, not caller. Symbols should be also
1997 // decorated in some fancy way :) It doesn't support any vector arguments.
1998 // For info on fast calling convention see Fast Calling Convention (tail call)
1999 // implementation LowerX86_32FastCCCallTo.
2001 /// CallIsStructReturn - Determines whether a call uses struct return
2003 enum StructReturnType {
2008 static StructReturnType
2009 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2011 return NotStructReturn;
2013 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2014 if (!Flags.isSRet())
2015 return NotStructReturn;
2016 if (Flags.isInReg())
2017 return RegStructReturn;
2018 return StackStructReturn;
2021 /// ArgsAreStructReturn - Determines whether a function uses struct
2022 /// return semantics.
2023 static StructReturnType
2024 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2026 return NotStructReturn;
2028 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2029 if (!Flags.isSRet())
2030 return NotStructReturn;
2031 if (Flags.isInReg())
2032 return RegStructReturn;
2033 return StackStructReturn;
2036 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2037 /// by "Src" to address "Dst" with size and alignment information specified by
2038 /// the specific parameter attribute. The copy will be passed as a byval
2039 /// function parameter.
2041 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2042 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2044 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2046 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2047 /*isVolatile*/false, /*AlwaysInline=*/true,
2048 MachinePointerInfo(), MachinePointerInfo());
2051 /// IsTailCallConvention - Return true if the calling convention is one that
2052 /// supports tail call optimization.
2053 static bool IsTailCallConvention(CallingConv::ID CC) {
2054 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2055 CC == CallingConv::HiPE);
2058 /// \brief Return true if the calling convention is a C calling convention.
2059 static bool IsCCallConvention(CallingConv::ID CC) {
2060 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2061 CC == CallingConv::X86_64_SysV);
2064 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2065 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2069 CallingConv::ID CalleeCC = CS.getCallingConv();
2070 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2076 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
2077 /// a tailcall target by changing its ABI.
2078 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2079 bool GuaranteedTailCallOpt) {
2080 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2084 X86TargetLowering::LowerMemArgument(SDValue Chain,
2085 CallingConv::ID CallConv,
2086 const SmallVectorImpl<ISD::InputArg> &Ins,
2087 SDLoc dl, SelectionDAG &DAG,
2088 const CCValAssign &VA,
2089 MachineFrameInfo *MFI,
2091 // Create the nodes corresponding to a load from this parameter slot.
2092 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2093 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv,
2094 getTargetMachine().Options.GuaranteedTailCallOpt);
2095 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2098 // If value is passed by pointer we have address passed instead of the value
2100 if (VA.getLocInfo() == CCValAssign::Indirect)
2101 ValVT = VA.getLocVT();
2103 ValVT = VA.getValVT();
2105 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2106 // changed with more analysis.
2107 // In case of tail call optimization mark all arguments mutable. Since they
2108 // could be overwritten by lowering of arguments in case of a tail call.
2109 if (Flags.isByVal()) {
2110 unsigned Bytes = Flags.getByValSize();
2111 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2112 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2113 return DAG.getFrameIndex(FI, getPointerTy());
2115 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2116 VA.getLocMemOffset(), isImmutable);
2117 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2118 return DAG.getLoad(ValVT, dl, Chain, FIN,
2119 MachinePointerInfo::getFixedStack(FI),
2120 false, false, false, 0);
2125 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2126 CallingConv::ID CallConv,
2128 const SmallVectorImpl<ISD::InputArg> &Ins,
2131 SmallVectorImpl<SDValue> &InVals)
2133 MachineFunction &MF = DAG.getMachineFunction();
2134 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2136 const Function* Fn = MF.getFunction();
2137 if (Fn->hasExternalLinkage() &&
2138 Subtarget->isTargetCygMing() &&
2139 Fn->getName() == "main")
2140 FuncInfo->setForceFramePointer(true);
2142 MachineFrameInfo *MFI = MF.getFrameInfo();
2143 bool Is64Bit = Subtarget->is64Bit();
2144 bool IsWindows = Subtarget->isTargetWindows();
2145 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2147 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2148 "Var args not supported with calling convention fastcc, ghc or hipe");
2150 // Assign locations to all of the incoming arguments.
2151 SmallVector<CCValAssign, 16> ArgLocs;
2152 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2153 ArgLocs, *DAG.getContext());
2155 // Allocate shadow area for Win64
2157 CCInfo.AllocateStack(32, 8);
2159 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2161 unsigned LastVal = ~0U;
2163 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2164 CCValAssign &VA = ArgLocs[i];
2165 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2167 assert(VA.getValNo() != LastVal &&
2168 "Don't support value assigned to multiple locs yet");
2170 LastVal = VA.getValNo();
2172 if (VA.isRegLoc()) {
2173 EVT RegVT = VA.getLocVT();
2174 const TargetRegisterClass *RC;
2175 if (RegVT == MVT::i32)
2176 RC = &X86::GR32RegClass;
2177 else if (Is64Bit && RegVT == MVT::i64)
2178 RC = &X86::GR64RegClass;
2179 else if (RegVT == MVT::f32)
2180 RC = &X86::FR32RegClass;
2181 else if (RegVT == MVT::f64)
2182 RC = &X86::FR64RegClass;
2183 else if (RegVT.is512BitVector())
2184 RC = &X86::VR512RegClass;
2185 else if (RegVT.is256BitVector())
2186 RC = &X86::VR256RegClass;
2187 else if (RegVT.is128BitVector())
2188 RC = &X86::VR128RegClass;
2189 else if (RegVT == MVT::x86mmx)
2190 RC = &X86::VR64RegClass;
2191 else if (RegVT == MVT::v8i1)
2192 RC = &X86::VK8RegClass;
2193 else if (RegVT == MVT::v16i1)
2194 RC = &X86::VK16RegClass;
2196 llvm_unreachable("Unknown argument type!");
2198 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2199 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2201 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2202 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2204 if (VA.getLocInfo() == CCValAssign::SExt)
2205 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2206 DAG.getValueType(VA.getValVT()));
2207 else if (VA.getLocInfo() == CCValAssign::ZExt)
2208 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2209 DAG.getValueType(VA.getValVT()));
2210 else if (VA.getLocInfo() == CCValAssign::BCvt)
2211 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2213 if (VA.isExtInLoc()) {
2214 // Handle MMX values passed in XMM regs.
2215 if (RegVT.isVector())
2216 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2218 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2221 assert(VA.isMemLoc());
2222 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2225 // If value is passed via pointer - do a load.
2226 if (VA.getLocInfo() == CCValAssign::Indirect)
2227 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2228 MachinePointerInfo(), false, false, false, 0);
2230 InVals.push_back(ArgValue);
2233 // The x86-64 ABIs require that for returning structs by value we copy
2234 // the sret argument into %rax/%eax (depending on ABI) for the return.
2235 // Win32 requires us to put the sret argument to %eax as well.
2236 // Save the argument into a virtual register so that we can access it
2237 // from the return points.
2238 if (MF.getFunction()->hasStructRetAttr() &&
2239 (Subtarget->is64Bit() || Subtarget->isTargetWindows())) {
2240 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2241 unsigned Reg = FuncInfo->getSRetReturnReg();
2243 MVT PtrTy = getPointerTy();
2244 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2245 FuncInfo->setSRetReturnReg(Reg);
2247 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
2248 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2251 unsigned StackSize = CCInfo.getNextStackOffset();
2252 // Align stack specially for tail calls.
2253 if (FuncIsMadeTailCallSafe(CallConv,
2254 MF.getTarget().Options.GuaranteedTailCallOpt))
2255 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2257 // If the function takes variable number of arguments, make a frame index for
2258 // the start of the first vararg value... for expansion of llvm.va_start.
2260 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2261 CallConv != CallingConv::X86_ThisCall)) {
2262 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
2265 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
2267 // FIXME: We should really autogenerate these arrays
2268 static const uint16_t GPR64ArgRegsWin64[] = {
2269 X86::RCX, X86::RDX, X86::R8, X86::R9
2271 static const uint16_t GPR64ArgRegs64Bit[] = {
2272 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2274 static const uint16_t XMMArgRegs64Bit[] = {
2275 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2276 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2278 const uint16_t *GPR64ArgRegs;
2279 unsigned NumXMMRegs = 0;
2282 // The XMM registers which might contain var arg parameters are shadowed
2283 // in their paired GPR. So we only need to save the GPR to their home
2285 TotalNumIntRegs = 4;
2286 GPR64ArgRegs = GPR64ArgRegsWin64;
2288 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
2289 GPR64ArgRegs = GPR64ArgRegs64Bit;
2291 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit,
2294 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
2297 bool NoImplicitFloatOps = Fn->getAttributes().
2298 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2299 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2300 "SSE register cannot be used when SSE is disabled!");
2301 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat &&
2302 NoImplicitFloatOps) &&
2303 "SSE register cannot be used when SSE is disabled!");
2304 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2305 !Subtarget->hasSSE1())
2306 // Kernel mode asks for SSE to be disabled, so don't push them
2308 TotalNumXMMRegs = 0;
2311 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering();
2312 // Get to the caller-allocated home save location. Add 8 to account
2313 // for the return address.
2314 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2315 FuncInfo->setRegSaveFrameIndex(
2316 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2317 // Fixup to set vararg frame on shadow area (4 x i64).
2319 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2321 // For X86-64, if there are vararg parameters that are passed via
2322 // registers, then we must store them to their spots on the stack so
2323 // they may be loaded by deferencing the result of va_next.
2324 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2325 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
2326 FuncInfo->setRegSaveFrameIndex(
2327 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
2331 // Store the integer parameter registers.
2332 SmallVector<SDValue, 8> MemOps;
2333 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2335 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2336 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
2337 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2338 DAG.getIntPtrConstant(Offset));
2339 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
2340 &X86::GR64RegClass);
2341 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2343 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2344 MachinePointerInfo::getFixedStack(
2345 FuncInfo->getRegSaveFrameIndex(), Offset),
2347 MemOps.push_back(Store);
2351 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
2352 // Now store the XMM (fp + vector) parameter registers.
2353 SmallVector<SDValue, 11> SaveXMMOps;
2354 SaveXMMOps.push_back(Chain);
2356 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2357 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
2358 SaveXMMOps.push_back(ALVal);
2360 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2361 FuncInfo->getRegSaveFrameIndex()));
2362 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2363 FuncInfo->getVarArgsFPOffset()));
2365 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
2366 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
2367 &X86::VR128RegClass);
2368 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
2369 SaveXMMOps.push_back(Val);
2371 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2373 &SaveXMMOps[0], SaveXMMOps.size()));
2376 if (!MemOps.empty())
2377 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2378 &MemOps[0], MemOps.size());
2382 // Some CCs need callee pop.
2383 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2384 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2385 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2387 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2388 // If this is an sret function, the return should pop the hidden pointer.
2389 if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2390 argsAreStructReturn(Ins) == StackStructReturn)
2391 FuncInfo->setBytesToPopOnReturn(4);
2395 // RegSaveFrameIndex is X86-64 only.
2396 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2397 if (CallConv == CallingConv::X86_FastCall ||
2398 CallConv == CallingConv::X86_ThisCall)
2399 // fastcc functions can't have varargs.
2400 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2403 FuncInfo->setArgumentStackSize(StackSize);
2409 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2410 SDValue StackPtr, SDValue Arg,
2411 SDLoc dl, SelectionDAG &DAG,
2412 const CCValAssign &VA,
2413 ISD::ArgFlagsTy Flags) const {
2414 unsigned LocMemOffset = VA.getLocMemOffset();
2415 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2416 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2417 if (Flags.isByVal())
2418 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2420 return DAG.getStore(Chain, dl, Arg, PtrOff,
2421 MachinePointerInfo::getStack(LocMemOffset),
2425 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2426 /// optimization is performed and it is required.
2428 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2429 SDValue &OutRetAddr, SDValue Chain,
2430 bool IsTailCall, bool Is64Bit,
2431 int FPDiff, SDLoc dl) const {
2432 // Adjust the Return address stack slot.
2433 EVT VT = getPointerTy();
2434 OutRetAddr = getReturnAddressFrameIndex(DAG);
2436 // Load the "old" Return address.
2437 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2438 false, false, false, 0);
2439 return SDValue(OutRetAddr.getNode(), 1);
2442 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2443 /// optimization is performed and it is required (FPDiff!=0).
2445 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
2446 SDValue Chain, SDValue RetAddrFrIdx, EVT PtrVT,
2447 unsigned SlotSize, int FPDiff, SDLoc dl) {
2448 // Store the return address to the appropriate stack slot.
2449 if (!FPDiff) return Chain;
2450 // Calculate the new stack slot for the return address.
2451 int NewReturnAddrFI =
2452 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2454 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2455 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2456 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2462 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2463 SmallVectorImpl<SDValue> &InVals) const {
2464 SelectionDAG &DAG = CLI.DAG;
2466 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2467 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2468 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2469 SDValue Chain = CLI.Chain;
2470 SDValue Callee = CLI.Callee;
2471 CallingConv::ID CallConv = CLI.CallConv;
2472 bool &isTailCall = CLI.IsTailCall;
2473 bool isVarArg = CLI.IsVarArg;
2475 MachineFunction &MF = DAG.getMachineFunction();
2476 bool Is64Bit = Subtarget->is64Bit();
2477 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2478 bool IsWindows = Subtarget->isTargetWindows();
2479 StructReturnType SR = callIsStructReturn(Outs);
2480 bool IsSibcall = false;
2482 if (MF.getTarget().Options.DisableTailCalls)
2486 // Check if it's really possible to do a tail call.
2487 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2488 isVarArg, SR != NotStructReturn,
2489 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2490 Outs, OutVals, Ins, DAG);
2492 // Sibcalls are automatically detected tailcalls which do not require
2494 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2501 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2502 "Var args not supported with calling convention fastcc, ghc or hipe");
2504 // Analyze operands of the call, assigning locations to each operand.
2505 SmallVector<CCValAssign, 16> ArgLocs;
2506 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2507 ArgLocs, *DAG.getContext());
2509 // Allocate shadow area for Win64
2511 CCInfo.AllocateStack(32, 8);
2513 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2515 // Get a count of how many bytes are to be pushed on the stack.
2516 unsigned NumBytes = CCInfo.getNextStackOffset();
2518 // This is a sibcall. The memory operands are available in caller's
2519 // own caller's stack.
2521 else if (getTargetMachine().Options.GuaranteedTailCallOpt &&
2522 IsTailCallConvention(CallConv))
2523 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2526 if (isTailCall && !IsSibcall) {
2527 // Lower arguments at fp - stackoffset + fpdiff.
2528 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2529 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2531 FPDiff = NumBytesCallerPushed - NumBytes;
2533 // Set the delta of movement of the returnaddr stackslot.
2534 // But only set if delta is greater than previous delta.
2535 if (FPDiff < X86Info->getTCReturnAddrDelta())
2536 X86Info->setTCReturnAddrDelta(FPDiff);
2540 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
2543 SDValue RetAddrFrIdx;
2544 // Load return address for tail calls.
2545 if (isTailCall && FPDiff)
2546 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2547 Is64Bit, FPDiff, dl);
2549 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2550 SmallVector<SDValue, 8> MemOpChains;
2553 // Walk the register/memloc assignments, inserting copies/loads. In the case
2554 // of tail call optimization arguments are handle later.
2555 const X86RegisterInfo *RegInfo =
2556 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
2557 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2558 CCValAssign &VA = ArgLocs[i];
2559 EVT RegVT = VA.getLocVT();
2560 SDValue Arg = OutVals[i];
2561 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2562 bool isByVal = Flags.isByVal();
2564 // Promote the value if needed.
2565 switch (VA.getLocInfo()) {
2566 default: llvm_unreachable("Unknown loc info!");
2567 case CCValAssign::Full: break;
2568 case CCValAssign::SExt:
2569 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2571 case CCValAssign::ZExt:
2572 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2574 case CCValAssign::AExt:
2575 if (RegVT.is128BitVector()) {
2576 // Special case: passing MMX values in XMM registers.
2577 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2578 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2579 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2581 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2583 case CCValAssign::BCvt:
2584 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2586 case CCValAssign::Indirect: {
2587 // Store the argument.
2588 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2589 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2590 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2591 MachinePointerInfo::getFixedStack(FI),
2598 if (VA.isRegLoc()) {
2599 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2600 if (isVarArg && IsWin64) {
2601 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2602 // shadow reg if callee is a varargs function.
2603 unsigned ShadowReg = 0;
2604 switch (VA.getLocReg()) {
2605 case X86::XMM0: ShadowReg = X86::RCX; break;
2606 case X86::XMM1: ShadowReg = X86::RDX; break;
2607 case X86::XMM2: ShadowReg = X86::R8; break;
2608 case X86::XMM3: ShadowReg = X86::R9; break;
2611 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2613 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2614 assert(VA.isMemLoc());
2615 if (StackPtr.getNode() == 0)
2616 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2618 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2619 dl, DAG, VA, Flags));
2623 if (!MemOpChains.empty())
2624 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2625 &MemOpChains[0], MemOpChains.size());
2627 if (Subtarget->isPICStyleGOT()) {
2628 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2631 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2632 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2634 // If we are tail calling and generating PIC/GOT style code load the
2635 // address of the callee into ECX. The value in ecx is used as target of
2636 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2637 // for tail calls on PIC/GOT architectures. Normally we would just put the
2638 // address of GOT into ebx and then call target@PLT. But for tail calls
2639 // ebx would be restored (since ebx is callee saved) before jumping to the
2642 // Note: The actual moving to ECX is done further down.
2643 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2644 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2645 !G->getGlobal()->hasProtectedVisibility())
2646 Callee = LowerGlobalAddress(Callee, DAG);
2647 else if (isa<ExternalSymbolSDNode>(Callee))
2648 Callee = LowerExternalSymbol(Callee, DAG);
2652 if (Is64Bit && isVarArg && !IsWin64) {
2653 // From AMD64 ABI document:
2654 // For calls that may call functions that use varargs or stdargs
2655 // (prototype-less calls or calls to functions containing ellipsis (...) in
2656 // the declaration) %al is used as hidden argument to specify the number
2657 // of SSE registers used. The contents of %al do not need to match exactly
2658 // the number of registers, but must be an ubound on the number of SSE
2659 // registers used and is in the range 0 - 8 inclusive.
2661 // Count the number of XMM registers allocated.
2662 static const uint16_t XMMArgRegs[] = {
2663 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2664 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2666 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2667 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2668 && "SSE registers cannot be used when SSE is disabled");
2670 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2671 DAG.getConstant(NumXMMRegs, MVT::i8)));
2674 // For tail calls lower the arguments to the 'real' stack slot.
2676 // Force all the incoming stack arguments to be loaded from the stack
2677 // before any new outgoing arguments are stored to the stack, because the
2678 // outgoing stack slots may alias the incoming argument stack slots, and
2679 // the alias isn't otherwise explicit. This is slightly more conservative
2680 // than necessary, because it means that each store effectively depends
2681 // on every argument instead of just those arguments it would clobber.
2682 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2684 SmallVector<SDValue, 8> MemOpChains2;
2687 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2688 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2689 CCValAssign &VA = ArgLocs[i];
2692 assert(VA.isMemLoc());
2693 SDValue Arg = OutVals[i];
2694 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2695 // Create frame index.
2696 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2697 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2698 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2699 FIN = DAG.getFrameIndex(FI, getPointerTy());
2701 if (Flags.isByVal()) {
2702 // Copy relative to framepointer.
2703 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2704 if (StackPtr.getNode() == 0)
2705 StackPtr = DAG.getCopyFromReg(Chain, dl,
2706 RegInfo->getStackRegister(),
2708 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2710 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2714 // Store relative to framepointer.
2715 MemOpChains2.push_back(
2716 DAG.getStore(ArgChain, dl, Arg, FIN,
2717 MachinePointerInfo::getFixedStack(FI),
2723 if (!MemOpChains2.empty())
2724 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2725 &MemOpChains2[0], MemOpChains2.size());
2727 // Store the return address to the appropriate stack slot.
2728 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
2729 getPointerTy(), RegInfo->getSlotSize(),
2733 // Build a sequence of copy-to-reg nodes chained together with token chain
2734 // and flag operands which copy the outgoing args into registers.
2736 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2737 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2738 RegsToPass[i].second, InFlag);
2739 InFlag = Chain.getValue(1);
2742 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2743 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2744 // In the 64-bit large code model, we have to make all calls
2745 // through a register, since the call instruction's 32-bit
2746 // pc-relative offset may not be large enough to hold the whole
2748 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2749 // If the callee is a GlobalAddress node (quite common, every direct call
2750 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2753 // We should use extra load for direct calls to dllimported functions in
2755 const GlobalValue *GV = G->getGlobal();
2756 if (!GV->hasDLLImportLinkage()) {
2757 unsigned char OpFlags = 0;
2758 bool ExtraLoad = false;
2759 unsigned WrapperKind = ISD::DELETED_NODE;
2761 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2762 // external symbols most go through the PLT in PIC mode. If the symbol
2763 // has hidden or protected visibility, or if it is static or local, then
2764 // we don't need to use the PLT - we can directly call it.
2765 if (Subtarget->isTargetELF() &&
2766 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2767 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2768 OpFlags = X86II::MO_PLT;
2769 } else if (Subtarget->isPICStyleStubAny() &&
2770 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2771 (!Subtarget->getTargetTriple().isMacOSX() ||
2772 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2773 // PC-relative references to external symbols should go through $stub,
2774 // unless we're building with the leopard linker or later, which
2775 // automatically synthesizes these stubs.
2776 OpFlags = X86II::MO_DARWIN_STUB;
2777 } else if (Subtarget->isPICStyleRIPRel() &&
2778 isa<Function>(GV) &&
2779 cast<Function>(GV)->getAttributes().
2780 hasAttribute(AttributeSet::FunctionIndex,
2781 Attribute::NonLazyBind)) {
2782 // If the function is marked as non-lazy, generate an indirect call
2783 // which loads from the GOT directly. This avoids runtime overhead
2784 // at the cost of eager binding (and one extra byte of encoding).
2785 OpFlags = X86II::MO_GOTPCREL;
2786 WrapperKind = X86ISD::WrapperRIP;
2790 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2791 G->getOffset(), OpFlags);
2793 // Add a wrapper if needed.
2794 if (WrapperKind != ISD::DELETED_NODE)
2795 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
2796 // Add extra indirection if needed.
2798 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
2799 MachinePointerInfo::getGOT(),
2800 false, false, false, 0);
2802 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2803 unsigned char OpFlags = 0;
2805 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2806 // external symbols should go through the PLT.
2807 if (Subtarget->isTargetELF() &&
2808 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2809 OpFlags = X86II::MO_PLT;
2810 } else if (Subtarget->isPICStyleStubAny() &&
2811 (!Subtarget->getTargetTriple().isMacOSX() ||
2812 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2813 // PC-relative references to external symbols should go through $stub,
2814 // unless we're building with the leopard linker or later, which
2815 // automatically synthesizes these stubs.
2816 OpFlags = X86II::MO_DARWIN_STUB;
2819 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2823 // Returns a chain & a flag for retval copy to use.
2824 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2825 SmallVector<SDValue, 8> Ops;
2827 if (!IsSibcall && isTailCall) {
2828 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2829 DAG.getIntPtrConstant(0, true), InFlag, dl);
2830 InFlag = Chain.getValue(1);
2833 Ops.push_back(Chain);
2834 Ops.push_back(Callee);
2837 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2839 // Add argument registers to the end of the list so that they are known live
2841 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2842 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2843 RegsToPass[i].second.getValueType()));
2845 // Add a register mask operand representing the call-preserved registers.
2846 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2847 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
2848 assert(Mask && "Missing call preserved mask for calling convention");
2849 Ops.push_back(DAG.getRegisterMask(Mask));
2851 if (InFlag.getNode())
2852 Ops.push_back(InFlag);
2856 //// If this is the first return lowered for this function, add the regs
2857 //// to the liveout set for the function.
2858 // This isn't right, although it's probably harmless on x86; liveouts
2859 // should be computed from returns not tail calls. Consider a void
2860 // function making a tail call to a function returning int.
2861 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size());
2864 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2865 InFlag = Chain.getValue(1);
2867 // Create the CALLSEQ_END node.
2868 unsigned NumBytesForCalleeToPush;
2869 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2870 getTargetMachine().Options.GuaranteedTailCallOpt))
2871 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2872 else if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2873 SR == StackStructReturn)
2874 // If this is a call to a struct-return function, the callee
2875 // pops the hidden struct pointer, so we have to push it back.
2876 // This is common for Darwin/X86, Linux & Mingw32 targets.
2877 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
2878 NumBytesForCalleeToPush = 4;
2880 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2882 // Returns a flag for retval copy to use.
2884 Chain = DAG.getCALLSEQ_END(Chain,
2885 DAG.getIntPtrConstant(NumBytes, true),
2886 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2889 InFlag = Chain.getValue(1);
2892 // Handle result values, copying them out of physregs into vregs that we
2894 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2895 Ins, dl, DAG, InVals);
2898 //===----------------------------------------------------------------------===//
2899 // Fast Calling Convention (tail call) implementation
2900 //===----------------------------------------------------------------------===//
2902 // Like std call, callee cleans arguments, convention except that ECX is
2903 // reserved for storing the tail called function address. Only 2 registers are
2904 // free for argument passing (inreg). Tail call optimization is performed
2906 // * tailcallopt is enabled
2907 // * caller/callee are fastcc
2908 // On X86_64 architecture with GOT-style position independent code only local
2909 // (within module) calls are supported at the moment.
2910 // To keep the stack aligned according to platform abi the function
2911 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2912 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2913 // If a tail called function callee has more arguments than the caller the
2914 // caller needs to make sure that there is room to move the RETADDR to. This is
2915 // achieved by reserving an area the size of the argument delta right after the
2916 // original REtADDR, but before the saved framepointer or the spilled registers
2917 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2929 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2930 /// for a 16 byte align requirement.
2932 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2933 SelectionDAG& DAG) const {
2934 MachineFunction &MF = DAG.getMachineFunction();
2935 const TargetMachine &TM = MF.getTarget();
2936 const X86RegisterInfo *RegInfo =
2937 static_cast<const X86RegisterInfo*>(TM.getRegisterInfo());
2938 const TargetFrameLowering &TFI = *TM.getFrameLowering();
2939 unsigned StackAlignment = TFI.getStackAlignment();
2940 uint64_t AlignMask = StackAlignment - 1;
2941 int64_t Offset = StackSize;
2942 unsigned SlotSize = RegInfo->getSlotSize();
2943 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2944 // Number smaller than 12 so just add the difference.
2945 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2947 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2948 Offset = ((~AlignMask) & Offset) + StackAlignment +
2949 (StackAlignment-SlotSize);
2954 /// MatchingStackOffset - Return true if the given stack call argument is
2955 /// already available in the same position (relatively) of the caller's
2956 /// incoming argument stack.
2958 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2959 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2960 const X86InstrInfo *TII) {
2961 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
2963 if (Arg.getOpcode() == ISD::CopyFromReg) {
2964 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2965 if (!TargetRegisterInfo::isVirtualRegister(VR))
2967 MachineInstr *Def = MRI->getVRegDef(VR);
2970 if (!Flags.isByVal()) {
2971 if (!TII->isLoadFromStackSlot(Def, FI))
2974 unsigned Opcode = Def->getOpcode();
2975 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
2976 Def->getOperand(1).isFI()) {
2977 FI = Def->getOperand(1).getIndex();
2978 Bytes = Flags.getByValSize();
2982 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2983 if (Flags.isByVal())
2984 // ByVal argument is passed in as a pointer but it's now being
2985 // dereferenced. e.g.
2986 // define @foo(%struct.X* %A) {
2987 // tail call @bar(%struct.X* byval %A)
2990 SDValue Ptr = Ld->getBasePtr();
2991 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2994 FI = FINode->getIndex();
2995 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
2996 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
2997 FI = FINode->getIndex();
2998 Bytes = Flags.getByValSize();
3002 assert(FI != INT_MAX);
3003 if (!MFI->isFixedObjectIndex(FI))
3005 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3008 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3009 /// for tail call optimization. Targets which want to do tail call
3010 /// optimization should implement this function.
3012 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3013 CallingConv::ID CalleeCC,
3015 bool isCalleeStructRet,
3016 bool isCallerStructRet,
3018 const SmallVectorImpl<ISD::OutputArg> &Outs,
3019 const SmallVectorImpl<SDValue> &OutVals,
3020 const SmallVectorImpl<ISD::InputArg> &Ins,
3021 SelectionDAG &DAG) const {
3022 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3025 // If -tailcallopt is specified, make fastcc functions tail-callable.
3026 const MachineFunction &MF = DAG.getMachineFunction();
3027 const Function *CallerF = MF.getFunction();
3029 // If the function return type is x86_fp80 and the callee return type is not,
3030 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3031 // perform a tailcall optimization here.
3032 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3035 CallingConv::ID CallerCC = CallerF->getCallingConv();
3036 bool CCMatch = CallerCC == CalleeCC;
3037 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3038 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3040 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
3041 if (IsTailCallConvention(CalleeCC) && CCMatch)
3046 // Look for obvious safe cases to perform tail call optimization that do not
3047 // require ABI changes. This is what gcc calls sibcall.
3049 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3050 // emit a special epilogue.
3051 const X86RegisterInfo *RegInfo =
3052 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
3053 if (RegInfo->needsStackRealignment(MF))
3056 // Also avoid sibcall optimization if either caller or callee uses struct
3057 // return semantics.
3058 if (isCalleeStructRet || isCallerStructRet)
3061 // An stdcall caller is expected to clean up its arguments; the callee
3062 // isn't going to do that.
3063 if (!CCMatch && CallerCC == CallingConv::X86_StdCall)
3066 // Do not sibcall optimize vararg calls unless all arguments are passed via
3068 if (isVarArg && !Outs.empty()) {
3070 // Optimizing for varargs on Win64 is unlikely to be safe without
3071 // additional testing.
3072 if (IsCalleeWin64 || IsCallerWin64)
3075 SmallVector<CCValAssign, 16> ArgLocs;
3076 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
3077 getTargetMachine(), ArgLocs, *DAG.getContext());
3079 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3080 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3081 if (!ArgLocs[i].isRegLoc())
3085 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3086 // stack. Therefore, if it's not used by the call it is not safe to optimize
3087 // this into a sibcall.
3088 bool Unused = false;
3089 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3096 SmallVector<CCValAssign, 16> RVLocs;
3097 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(),
3098 getTargetMachine(), RVLocs, *DAG.getContext());
3099 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3100 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3101 CCValAssign &VA = RVLocs[i];
3102 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
3107 // If the calling conventions do not match, then we'd better make sure the
3108 // results are returned in the same way as what the caller expects.
3110 SmallVector<CCValAssign, 16> RVLocs1;
3111 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
3112 getTargetMachine(), RVLocs1, *DAG.getContext());
3113 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3115 SmallVector<CCValAssign, 16> RVLocs2;
3116 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
3117 getTargetMachine(), RVLocs2, *DAG.getContext());
3118 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3120 if (RVLocs1.size() != RVLocs2.size())
3122 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3123 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3125 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3127 if (RVLocs1[i].isRegLoc()) {
3128 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3131 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3137 // If the callee takes no arguments then go on to check the results of the
3139 if (!Outs.empty()) {
3140 // Check if stack adjustment is needed. For now, do not do this if any
3141 // argument is passed on the stack.
3142 SmallVector<CCValAssign, 16> ArgLocs;
3143 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
3144 getTargetMachine(), ArgLocs, *DAG.getContext());
3146 // Allocate shadow area for Win64
3148 CCInfo.AllocateStack(32, 8);
3150 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3151 if (CCInfo.getNextStackOffset()) {
3152 MachineFunction &MF = DAG.getMachineFunction();
3153 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3156 // Check if the arguments are already laid out in the right way as
3157 // the caller's fixed stack objects.
3158 MachineFrameInfo *MFI = MF.getFrameInfo();
3159 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3160 const X86InstrInfo *TII =
3161 ((const X86TargetMachine&)getTargetMachine()).getInstrInfo();
3162 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3163 CCValAssign &VA = ArgLocs[i];
3164 SDValue Arg = OutVals[i];
3165 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3166 if (VA.getLocInfo() == CCValAssign::Indirect)
3168 if (!VA.isRegLoc()) {
3169 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3176 // If the tailcall address may be in a register, then make sure it's
3177 // possible to register allocate for it. In 32-bit, the call address can
3178 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3179 // callee-saved registers are restored. These happen to be the same
3180 // registers used to pass 'inreg' arguments so watch out for those.
3181 if (!Subtarget->is64Bit() &&
3182 ((!isa<GlobalAddressSDNode>(Callee) &&
3183 !isa<ExternalSymbolSDNode>(Callee)) ||
3184 getTargetMachine().getRelocationModel() == Reloc::PIC_)) {
3185 unsigned NumInRegs = 0;
3186 // In PIC we need an extra register to formulate the address computation
3188 unsigned MaxInRegs =
3189 (getTargetMachine().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3191 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3192 CCValAssign &VA = ArgLocs[i];
3195 unsigned Reg = VA.getLocReg();
3198 case X86::EAX: case X86::EDX: case X86::ECX:
3199 if (++NumInRegs == MaxInRegs)
3211 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3212 const TargetLibraryInfo *libInfo) const {
3213 return X86::createFastISel(funcInfo, libInfo);
3216 //===----------------------------------------------------------------------===//
3217 // Other Lowering Hooks
3218 //===----------------------------------------------------------------------===//
3220 static bool MayFoldLoad(SDValue Op) {
3221 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3224 static bool MayFoldIntoStore(SDValue Op) {
3225 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3228 static bool isTargetShuffle(unsigned Opcode) {
3230 default: return false;
3231 case X86ISD::PSHUFD:
3232 case X86ISD::PSHUFHW:
3233 case X86ISD::PSHUFLW:
3235 case X86ISD::PALIGNR:
3236 case X86ISD::MOVLHPS:
3237 case X86ISD::MOVLHPD:
3238 case X86ISD::MOVHLPS:
3239 case X86ISD::MOVLPS:
3240 case X86ISD::MOVLPD:
3241 case X86ISD::MOVSHDUP:
3242 case X86ISD::MOVSLDUP:
3243 case X86ISD::MOVDDUP:
3246 case X86ISD::UNPCKL:
3247 case X86ISD::UNPCKH:
3248 case X86ISD::VPERMILP:
3249 case X86ISD::VPERM2X128:
3250 case X86ISD::VPERMI:
3255 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3256 SDValue V1, SelectionDAG &DAG) {
3258 default: llvm_unreachable("Unknown x86 shuffle node");
3259 case X86ISD::MOVSHDUP:
3260 case X86ISD::MOVSLDUP:
3261 case X86ISD::MOVDDUP:
3262 return DAG.getNode(Opc, dl, VT, V1);
3266 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3267 SDValue V1, unsigned TargetMask,
3268 SelectionDAG &DAG) {
3270 default: llvm_unreachable("Unknown x86 shuffle node");
3271 case X86ISD::PSHUFD:
3272 case X86ISD::PSHUFHW:
3273 case X86ISD::PSHUFLW:
3274 case X86ISD::VPERMILP:
3275 case X86ISD::VPERMI:
3276 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3280 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3281 SDValue V1, SDValue V2, unsigned TargetMask,
3282 SelectionDAG &DAG) {
3284 default: llvm_unreachable("Unknown x86 shuffle node");
3285 case X86ISD::PALIGNR:
3287 case X86ISD::VPERM2X128:
3288 return DAG.getNode(Opc, dl, VT, V1, V2,
3289 DAG.getConstant(TargetMask, MVT::i8));
3293 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3294 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3296 default: llvm_unreachable("Unknown x86 shuffle node");
3297 case X86ISD::MOVLHPS:
3298 case X86ISD::MOVLHPD:
3299 case X86ISD::MOVHLPS:
3300 case X86ISD::MOVLPS:
3301 case X86ISD::MOVLPD:
3304 case X86ISD::UNPCKL:
3305 case X86ISD::UNPCKH:
3306 return DAG.getNode(Opc, dl, VT, V1, V2);
3310 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3311 MachineFunction &MF = DAG.getMachineFunction();
3312 const X86RegisterInfo *RegInfo =
3313 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
3314 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3315 int ReturnAddrIndex = FuncInfo->getRAIndex();
3317 if (ReturnAddrIndex == 0) {
3318 // Set up a frame object for the return address.
3319 unsigned SlotSize = RegInfo->getSlotSize();
3320 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3323 FuncInfo->setRAIndex(ReturnAddrIndex);
3326 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3329 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3330 bool hasSymbolicDisplacement) {
3331 // Offset should fit into 32 bit immediate field.
3332 if (!isInt<32>(Offset))
3335 // If we don't have a symbolic displacement - we don't have any extra
3337 if (!hasSymbolicDisplacement)
3340 // FIXME: Some tweaks might be needed for medium code model.
3341 if (M != CodeModel::Small && M != CodeModel::Kernel)
3344 // For small code model we assume that latest object is 16MB before end of 31
3345 // bits boundary. We may also accept pretty large negative constants knowing
3346 // that all objects are in the positive half of address space.
3347 if (M == CodeModel::Small && Offset < 16*1024*1024)
3350 // For kernel code model we know that all object resist in the negative half
3351 // of 32bits address space. We may not accept negative offsets, since they may
3352 // be just off and we may accept pretty large positive ones.
3353 if (M == CodeModel::Kernel && Offset > 0)
3359 /// isCalleePop - Determines whether the callee is required to pop its
3360 /// own arguments. Callee pop is necessary to support tail calls.
3361 bool X86::isCalleePop(CallingConv::ID CallingConv,
3362 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3366 switch (CallingConv) {
3369 case CallingConv::X86_StdCall:
3371 case CallingConv::X86_FastCall:
3373 case CallingConv::X86_ThisCall:
3375 case CallingConv::Fast:
3377 case CallingConv::GHC:
3379 case CallingConv::HiPE:
3384 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3385 /// specific condition code, returning the condition code and the LHS/RHS of the
3386 /// comparison to make.
3387 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3388 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3390 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3391 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3392 // X > -1 -> X == 0, jump !sign.
3393 RHS = DAG.getConstant(0, RHS.getValueType());
3394 return X86::COND_NS;
3396 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3397 // X < 0 -> X == 0, jump on sign.
3400 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3402 RHS = DAG.getConstant(0, RHS.getValueType());
3403 return X86::COND_LE;
3407 switch (SetCCOpcode) {
3408 default: llvm_unreachable("Invalid integer condition!");
3409 case ISD::SETEQ: return X86::COND_E;
3410 case ISD::SETGT: return X86::COND_G;
3411 case ISD::SETGE: return X86::COND_GE;
3412 case ISD::SETLT: return X86::COND_L;
3413 case ISD::SETLE: return X86::COND_LE;
3414 case ISD::SETNE: return X86::COND_NE;
3415 case ISD::SETULT: return X86::COND_B;
3416 case ISD::SETUGT: return X86::COND_A;
3417 case ISD::SETULE: return X86::COND_BE;
3418 case ISD::SETUGE: return X86::COND_AE;
3422 // First determine if it is required or is profitable to flip the operands.
3424 // If LHS is a foldable load, but RHS is not, flip the condition.
3425 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3426 !ISD::isNON_EXTLoad(RHS.getNode())) {
3427 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3428 std::swap(LHS, RHS);
3431 switch (SetCCOpcode) {
3437 std::swap(LHS, RHS);
3441 // On a floating point condition, the flags are set as follows:
3443 // 0 | 0 | 0 | X > Y
3444 // 0 | 0 | 1 | X < Y
3445 // 1 | 0 | 0 | X == Y
3446 // 1 | 1 | 1 | unordered
3447 switch (SetCCOpcode) {
3448 default: llvm_unreachable("Condcode should be pre-legalized away");
3450 case ISD::SETEQ: return X86::COND_E;
3451 case ISD::SETOLT: // flipped
3453 case ISD::SETGT: return X86::COND_A;
3454 case ISD::SETOLE: // flipped
3456 case ISD::SETGE: return X86::COND_AE;
3457 case ISD::SETUGT: // flipped
3459 case ISD::SETLT: return X86::COND_B;
3460 case ISD::SETUGE: // flipped
3462 case ISD::SETLE: return X86::COND_BE;
3464 case ISD::SETNE: return X86::COND_NE;
3465 case ISD::SETUO: return X86::COND_P;
3466 case ISD::SETO: return X86::COND_NP;
3468 case ISD::SETUNE: return X86::COND_INVALID;
3472 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3473 /// code. Current x86 isa includes the following FP cmov instructions:
3474 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3475 static bool hasFPCMov(unsigned X86CC) {
3491 /// isFPImmLegal - Returns true if the target can instruction select the
3492 /// specified FP immediate natively. If false, the legalizer will
3493 /// materialize the FP immediate as a load from a constant pool.
3494 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3495 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3496 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3502 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3503 /// the specified range (L, H].
3504 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3505 return (Val < 0) || (Val >= Low && Val < Hi);
3508 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3509 /// specified value.
3510 static bool isUndefOrEqual(int Val, int CmpVal) {
3511 return (Val < 0 || Val == CmpVal);
3514 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3515 /// from position Pos and ending in Pos+Size, falls within the specified
3516 /// sequential range (L, L+Pos]. or is undef.
3517 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3518 unsigned Pos, unsigned Size, int Low) {
3519 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3520 if (!isUndefOrEqual(Mask[i], Low))
3525 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3526 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3527 /// the second operand.
3528 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT) {
3529 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3530 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3531 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3532 return (Mask[0] < 2 && Mask[1] < 2);
3536 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3537 /// is suitable for input to PSHUFHW.
3538 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3539 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3542 // Lower quadword copied in order or undef.
3543 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3546 // Upper quadword shuffled.
3547 for (unsigned i = 4; i != 8; ++i)
3548 if (!isUndefOrInRange(Mask[i], 4, 8))
3551 if (VT == MVT::v16i16) {
3552 // Lower quadword copied in order or undef.
3553 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3556 // Upper quadword shuffled.
3557 for (unsigned i = 12; i != 16; ++i)
3558 if (!isUndefOrInRange(Mask[i], 12, 16))
3565 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3566 /// is suitable for input to PSHUFLW.
3567 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3568 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3571 // Upper quadword copied in order.
3572 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3575 // Lower quadword shuffled.
3576 for (unsigned i = 0; i != 4; ++i)
3577 if (!isUndefOrInRange(Mask[i], 0, 4))
3580 if (VT == MVT::v16i16) {
3581 // Upper quadword copied in order.
3582 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3585 // Lower quadword shuffled.
3586 for (unsigned i = 8; i != 12; ++i)
3587 if (!isUndefOrInRange(Mask[i], 8, 12))
3594 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
3595 /// is suitable for input to PALIGNR.
3596 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
3597 const X86Subtarget *Subtarget) {
3598 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
3599 (VT.is256BitVector() && !Subtarget->hasInt256()))
3602 unsigned NumElts = VT.getVectorNumElements();
3603 unsigned NumLanes = VT.getSizeInBits()/128;
3604 unsigned NumLaneElts = NumElts/NumLanes;
3606 // Do not handle 64-bit element shuffles with palignr.
3607 if (NumLaneElts == 2)
3610 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3612 for (i = 0; i != NumLaneElts; ++i) {
3617 // Lane is all undef, go to next lane
3618 if (i == NumLaneElts)
3621 int Start = Mask[i+l];
3623 // Make sure its in this lane in one of the sources
3624 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3625 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3628 // If not lane 0, then we must match lane 0
3629 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3632 // Correct second source to be contiguous with first source
3633 if (Start >= (int)NumElts)
3634 Start -= NumElts - NumLaneElts;
3636 // Make sure we're shifting in the right direction.
3637 if (Start <= (int)(i+l))
3642 // Check the rest of the elements to see if they are consecutive.
3643 for (++i; i != NumLaneElts; ++i) {
3644 int Idx = Mask[i+l];
3646 // Make sure its in this lane
3647 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3648 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3651 // If not lane 0, then we must match lane 0
3652 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3655 if (Idx >= (int)NumElts)
3656 Idx -= NumElts - NumLaneElts;
3658 if (!isUndefOrEqual(Idx, Start+i))
3667 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3668 /// the two vector operands have swapped position.
3669 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
3670 unsigned NumElems) {
3671 for (unsigned i = 0; i != NumElems; ++i) {
3675 else if (idx < (int)NumElems)
3676 Mask[i] = idx + NumElems;
3678 Mask[i] = idx - NumElems;
3682 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
3683 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
3684 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
3685 /// reverse of what x86 shuffles want.
3686 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool HasFp256,
3687 bool Commuted = false) {
3688 if (!HasFp256 && VT.is256BitVector())
3691 unsigned NumElems = VT.getVectorNumElements();
3692 unsigned NumLanes = VT.getSizeInBits()/128;
3693 unsigned NumLaneElems = NumElems/NumLanes;
3695 if (NumLaneElems != 2 && NumLaneElems != 4)
3698 // VSHUFPSY divides the resulting vector into 4 chunks.
3699 // The sources are also splitted into 4 chunks, and each destination
3700 // chunk must come from a different source chunk.
3702 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
3703 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
3705 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
3706 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
3708 // VSHUFPDY divides the resulting vector into 4 chunks.
3709 // The sources are also splitted into 4 chunks, and each destination
3710 // chunk must come from a different source chunk.
3712 // SRC1 => X3 X2 X1 X0
3713 // SRC2 => Y3 Y2 Y1 Y0
3715 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
3717 unsigned HalfLaneElems = NumLaneElems/2;
3718 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
3719 for (unsigned i = 0; i != NumLaneElems; ++i) {
3720 int Idx = Mask[i+l];
3721 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
3722 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
3724 // For VSHUFPSY, the mask of the second half must be the same as the
3725 // first but with the appropriate offsets. This works in the same way as
3726 // VPERMILPS works with masks.
3727 if (NumElems != 8 || l == 0 || Mask[i] < 0)
3729 if (!isUndefOrEqual(Idx, Mask[i]+l))
3737 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3738 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3739 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
3740 if (!VT.is128BitVector())
3743 unsigned NumElems = VT.getVectorNumElements();
3748 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3749 return isUndefOrEqual(Mask[0], 6) &&
3750 isUndefOrEqual(Mask[1], 7) &&
3751 isUndefOrEqual(Mask[2], 2) &&
3752 isUndefOrEqual(Mask[3], 3);
3755 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3756 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3758 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
3759 if (!VT.is128BitVector())
3762 unsigned NumElems = VT.getVectorNumElements();
3767 return isUndefOrEqual(Mask[0], 2) &&
3768 isUndefOrEqual(Mask[1], 3) &&
3769 isUndefOrEqual(Mask[2], 2) &&
3770 isUndefOrEqual(Mask[3], 3);
3773 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3774 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3775 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
3776 if (!VT.is128BitVector())
3779 unsigned NumElems = VT.getVectorNumElements();
3781 if (NumElems != 2 && NumElems != 4)
3784 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3785 if (!isUndefOrEqual(Mask[i], i + NumElems))
3788 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
3789 if (!isUndefOrEqual(Mask[i], i))
3795 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3796 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3797 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
3798 if (!VT.is128BitVector())
3801 unsigned NumElems = VT.getVectorNumElements();
3803 if (NumElems != 2 && NumElems != 4)
3806 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3807 if (!isUndefOrEqual(Mask[i], i))
3810 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3811 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
3818 // Some special combinations that can be optimized.
3821 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
3822 SelectionDAG &DAG) {
3823 MVT VT = SVOp->getSimpleValueType(0);
3826 if (VT != MVT::v8i32 && VT != MVT::v8f32)
3829 ArrayRef<int> Mask = SVOp->getMask();
3831 // These are the special masks that may be optimized.
3832 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
3833 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
3834 bool MatchEvenMask = true;
3835 bool MatchOddMask = true;
3836 for (int i=0; i<8; ++i) {
3837 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
3838 MatchEvenMask = false;
3839 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
3840 MatchOddMask = false;
3843 if (!MatchEvenMask && !MatchOddMask)
3846 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
3848 SDValue Op0 = SVOp->getOperand(0);
3849 SDValue Op1 = SVOp->getOperand(1);
3851 if (MatchEvenMask) {
3852 // Shift the second operand right to 32 bits.
3853 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
3854 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
3856 // Shift the first operand left to 32 bits.
3857 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
3858 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
3860 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
3861 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
3864 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
3865 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
3866 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
3867 bool HasInt256, bool V2IsSplat = false) {
3869 if (VT.is512BitVector())
3871 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3872 "Unsupported vector type for unpckh");
3874 unsigned NumElts = VT.getVectorNumElements();
3875 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
3876 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
3879 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3880 // independently on 128-bit lanes.
3881 unsigned NumLanes = VT.getSizeInBits()/128;
3882 unsigned NumLaneElts = NumElts/NumLanes;
3884 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
3885 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
3886 int BitI = Mask[l+i];
3887 int BitI1 = Mask[l+i+1];
3888 if (!isUndefOrEqual(BitI, j))
3891 if (!isUndefOrEqual(BitI1, NumElts))
3894 if (!isUndefOrEqual(BitI1, j + NumElts))
3903 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
3904 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
3905 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
3906 bool HasInt256, bool V2IsSplat = false) {
3907 unsigned NumElts = VT.getVectorNumElements();
3909 if (VT.is512BitVector())
3911 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3912 "Unsupported vector type for unpckh");
3914 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
3915 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
3918 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3919 // independently on 128-bit lanes.
3920 unsigned NumLanes = VT.getSizeInBits()/128;
3921 unsigned NumLaneElts = NumElts/NumLanes;
3923 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
3924 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
3925 int BitI = Mask[l+i];
3926 int BitI1 = Mask[l+i+1];
3927 if (!isUndefOrEqual(BitI, j))
3930 if (isUndefOrEqual(BitI1, NumElts))
3933 if (!isUndefOrEqual(BitI1, j+NumElts))
3941 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
3942 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
3944 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3945 unsigned NumElts = VT.getVectorNumElements();
3946 bool Is256BitVec = VT.is256BitVector();
3948 if (VT.is512BitVector())
3950 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3951 "Unsupported vector type for unpckh");
3953 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
3954 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
3957 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
3958 // FIXME: Need a better way to get rid of this, there's no latency difference
3959 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
3960 // the former later. We should also remove the "_undef" special mask.
3961 if (NumElts == 4 && Is256BitVec)
3964 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3965 // independently on 128-bit lanes.
3966 unsigned NumLanes = VT.getSizeInBits()/128;
3967 unsigned NumLaneElts = NumElts/NumLanes;
3969 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
3970 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
3971 int BitI = Mask[l+i];
3972 int BitI1 = Mask[l+i+1];
3974 if (!isUndefOrEqual(BitI, j))
3976 if (!isUndefOrEqual(BitI1, j))
3984 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
3985 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
3987 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3988 unsigned NumElts = VT.getVectorNumElements();
3990 if (VT.is512BitVector())
3993 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3994 "Unsupported vector type for unpckh");
3996 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
3997 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4000 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4001 // independently on 128-bit lanes.
4002 unsigned NumLanes = VT.getSizeInBits()/128;
4003 unsigned NumLaneElts = NumElts/NumLanes;
4005 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4006 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4007 int BitI = Mask[l+i];
4008 int BitI1 = Mask[l+i+1];
4009 if (!isUndefOrEqual(BitI, j))
4011 if (!isUndefOrEqual(BitI1, j))
4018 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4019 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4020 /// MOVSD, and MOVD, i.e. setting the lowest element.
4021 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4022 if (VT.getVectorElementType().getSizeInBits() < 32)
4024 if (!VT.is128BitVector())
4027 unsigned NumElts = VT.getVectorNumElements();
4029 if (!isUndefOrEqual(Mask[0], NumElts))
4032 for (unsigned i = 1; i != NumElts; ++i)
4033 if (!isUndefOrEqual(Mask[i], i))
4039 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4040 /// as permutations between 128-bit chunks or halves. As an example: this
4042 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4043 /// The first half comes from the second half of V1 and the second half from the
4044 /// the second half of V2.
4045 static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4046 if (!HasFp256 || !VT.is256BitVector())
4049 // The shuffle result is divided into half A and half B. In total the two
4050 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4051 // B must come from C, D, E or F.
4052 unsigned HalfSize = VT.getVectorNumElements()/2;
4053 bool MatchA = false, MatchB = false;
4055 // Check if A comes from one of C, D, E, F.
4056 for (unsigned Half = 0; Half != 4; ++Half) {
4057 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4063 // Check if B comes from one of C, D, E, F.
4064 for (unsigned Half = 0; Half != 4; ++Half) {
4065 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4071 return MatchA && MatchB;
4074 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4075 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4076 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4077 MVT VT = SVOp->getSimpleValueType(0);
4079 unsigned HalfSize = VT.getVectorNumElements()/2;
4081 unsigned FstHalf = 0, SndHalf = 0;
4082 for (unsigned i = 0; i < HalfSize; ++i) {
4083 if (SVOp->getMaskElt(i) > 0) {
4084 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4088 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4089 if (SVOp->getMaskElt(i) > 0) {
4090 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4095 return (FstHalf | (SndHalf << 4));
4098 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4099 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
4100 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4104 unsigned NumElts = VT.getVectorNumElements();
4106 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4107 for (unsigned i = 0; i != NumElts; ++i) {
4110 Imm8 |= Mask[i] << (i*2);
4115 unsigned LaneSize = 4;
4116 SmallVector<int, 4> MaskVal(LaneSize, -1);
4118 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4119 for (unsigned i = 0; i != LaneSize; ++i) {
4120 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4124 if (MaskVal[i] < 0) {
4125 MaskVal[i] = Mask[i+l] - l;
4126 Imm8 |= MaskVal[i] << (i*2);
4129 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4136 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4137 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4138 /// Note that VPERMIL mask matching is different depending whether theunderlying
4139 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4140 /// to the same elements of the low, but to the higher half of the source.
4141 /// In VPERMILPD the two lanes could be shuffled independently of each other
4142 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4143 static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4147 unsigned NumElts = VT.getVectorNumElements();
4148 // Only match 256-bit with 32/64-bit types
4149 if (!VT.is256BitVector() || (NumElts != 4 && NumElts != 8))
4152 unsigned NumLanes = VT.getSizeInBits()/128;
4153 unsigned LaneSize = NumElts/NumLanes;
4154 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4155 for (unsigned i = 0; i != LaneSize; ++i) {
4156 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4158 if (NumElts != 8 || l == 0)
4160 // VPERMILPS handling
4163 if (!isUndefOrEqual(Mask[i+l], Mask[i]+l))
4171 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4172 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4173 /// element of vector 2 and the other elements to come from vector 1 in order.
4174 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4175 bool V2IsSplat = false, bool V2IsUndef = false) {
4176 if (!VT.is128BitVector())
4179 unsigned NumOps = VT.getVectorNumElements();
4180 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4183 if (!isUndefOrEqual(Mask[0], 0))
4186 for (unsigned i = 1; i != NumOps; ++i)
4187 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4188 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4189 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4195 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4196 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4197 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4198 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4199 const X86Subtarget *Subtarget) {
4200 if (!Subtarget->hasSSE3())
4203 unsigned NumElems = VT.getVectorNumElements();
4205 if ((VT.is128BitVector() && NumElems != 4) ||
4206 (VT.is256BitVector() && NumElems != 8) ||
4207 (VT.is512BitVector() && NumElems != 16))
4210 // "i+1" is the value the indexed mask element must have
4211 for (unsigned i = 0; i != NumElems; i += 2)
4212 if (!isUndefOrEqual(Mask[i], i+1) ||
4213 !isUndefOrEqual(Mask[i+1], i+1))
4219 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4220 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4221 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4222 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4223 const X86Subtarget *Subtarget) {
4224 if (!Subtarget->hasSSE3())
4227 unsigned NumElems = VT.getVectorNumElements();
4229 if ((VT.is128BitVector() && NumElems != 4) ||
4230 (VT.is256BitVector() && NumElems != 8) ||
4231 (VT.is512BitVector() && NumElems != 16))
4234 // "i" is the value the indexed mask element must have
4235 for (unsigned i = 0; i != NumElems; i += 2)
4236 if (!isUndefOrEqual(Mask[i], i) ||
4237 !isUndefOrEqual(Mask[i+1], i))
4243 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4244 /// specifies a shuffle of elements that is suitable for input to 256-bit
4245 /// version of MOVDDUP.
4246 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4247 if (!HasFp256 || !VT.is256BitVector())
4250 unsigned NumElts = VT.getVectorNumElements();
4254 for (unsigned i = 0; i != NumElts/2; ++i)
4255 if (!isUndefOrEqual(Mask[i], 0))
4257 for (unsigned i = NumElts/2; i != NumElts; ++i)
4258 if (!isUndefOrEqual(Mask[i], NumElts/2))
4263 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4264 /// specifies a shuffle of elements that is suitable for input to 128-bit
4265 /// version of MOVDDUP.
4266 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4267 if (!VT.is128BitVector())
4270 unsigned e = VT.getVectorNumElements() / 2;
4271 for (unsigned i = 0; i != e; ++i)
4272 if (!isUndefOrEqual(Mask[i], i))
4274 for (unsigned i = 0; i != e; ++i)
4275 if (!isUndefOrEqual(Mask[e+i], i))
4280 /// isVEXTRACTIndex - Return true if the specified
4281 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4282 /// suitable for instruction that extract 128 or 256 bit vectors
4283 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4284 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4285 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4288 // The index should be aligned on a vecWidth-bit boundary.
4290 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4292 MVT VT = N->getSimpleValueType(0);
4293 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4294 bool Result = (Index * ElSize) % vecWidth == 0;
4299 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4300 /// operand specifies a subvector insert that is suitable for input to
4301 /// insertion of 128 or 256-bit subvectors
4302 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4303 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4304 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4306 // The index should be aligned on a vecWidth-bit boundary.
4308 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4310 MVT VT = N->getSimpleValueType(0);
4311 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4312 bool Result = (Index * ElSize) % vecWidth == 0;
4317 bool X86::isVINSERT128Index(SDNode *N) {
4318 return isVINSERTIndex(N, 128);
4321 bool X86::isVINSERT256Index(SDNode *N) {
4322 return isVINSERTIndex(N, 256);
4325 bool X86::isVEXTRACT128Index(SDNode *N) {
4326 return isVEXTRACTIndex(N, 128);
4329 bool X86::isVEXTRACT256Index(SDNode *N) {
4330 return isVEXTRACTIndex(N, 256);
4333 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4334 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4335 /// Handles 128-bit and 256-bit.
4336 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4337 MVT VT = N->getSimpleValueType(0);
4339 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4340 "Unsupported vector type for PSHUF/SHUFP");
4342 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4343 // independently on 128-bit lanes.
4344 unsigned NumElts = VT.getVectorNumElements();
4345 unsigned NumLanes = VT.getSizeInBits()/128;
4346 unsigned NumLaneElts = NumElts/NumLanes;
4348 assert((NumLaneElts == 2 || NumLaneElts == 4) &&
4349 "Only supports 2 or 4 elements per lane");
4351 unsigned Shift = (NumLaneElts == 4) ? 1 : 0;
4353 for (unsigned i = 0; i != NumElts; ++i) {
4354 int Elt = N->getMaskElt(i);
4355 if (Elt < 0) continue;
4356 Elt &= NumLaneElts - 1;
4357 unsigned ShAmt = (i << Shift) % 8;
4358 Mask |= Elt << ShAmt;
4364 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4365 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4366 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4367 MVT VT = N->getSimpleValueType(0);
4369 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4370 "Unsupported vector type for PSHUFHW");
4372 unsigned NumElts = VT.getVectorNumElements();
4375 for (unsigned l = 0; l != NumElts; l += 8) {
4376 // 8 nodes per lane, but we only care about the last 4.
4377 for (unsigned i = 0; i < 4; ++i) {
4378 int Elt = N->getMaskElt(l+i+4);
4379 if (Elt < 0) continue;
4380 Elt &= 0x3; // only 2-bits.
4381 Mask |= Elt << (i * 2);
4388 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4389 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4390 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4391 MVT VT = N->getSimpleValueType(0);
4393 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4394 "Unsupported vector type for PSHUFHW");
4396 unsigned NumElts = VT.getVectorNumElements();
4399 for (unsigned l = 0; l != NumElts; l += 8) {
4400 // 8 nodes per lane, but we only care about the first 4.
4401 for (unsigned i = 0; i < 4; ++i) {
4402 int Elt = N->getMaskElt(l+i);
4403 if (Elt < 0) continue;
4404 Elt &= 0x3; // only 2-bits
4405 Mask |= Elt << (i * 2);
4412 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
4413 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
4414 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4415 MVT VT = SVOp->getSimpleValueType(0);
4416 unsigned EltSize = VT.getVectorElementType().getSizeInBits() >> 3;
4418 unsigned NumElts = VT.getVectorNumElements();
4419 unsigned NumLanes = VT.getSizeInBits()/128;
4420 unsigned NumLaneElts = NumElts/NumLanes;
4424 for (i = 0; i != NumElts; ++i) {
4425 Val = SVOp->getMaskElt(i);
4429 if (Val >= (int)NumElts)
4430 Val -= NumElts - NumLaneElts;
4432 assert(Val - i > 0 && "PALIGNR imm should be positive");
4433 return (Val - i) * EltSize;
4436 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4437 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4438 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4439 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4442 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4444 MVT VecVT = N->getOperand(0).getSimpleValueType();
4445 MVT ElVT = VecVT.getVectorElementType();
4447 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4448 return Index / NumElemsPerChunk;
4451 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4452 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4453 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4454 llvm_unreachable("Illegal insert subvector for VINSERT");
4457 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4459 MVT VecVT = N->getSimpleValueType(0);
4460 MVT ElVT = VecVT.getVectorElementType();
4462 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4463 return Index / NumElemsPerChunk;
4466 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4467 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4468 /// and VINSERTI128 instructions.
4469 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4470 return getExtractVEXTRACTImmediate(N, 128);
4473 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4474 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4475 /// and VINSERTI64x4 instructions.
4476 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4477 return getExtractVEXTRACTImmediate(N, 256);
4480 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4481 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4482 /// and VINSERTI128 instructions.
4483 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4484 return getInsertVINSERTImmediate(N, 128);
4487 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4488 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4489 /// and VINSERTI64x4 instructions.
4490 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4491 return getInsertVINSERTImmediate(N, 256);
4494 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4496 bool X86::isZeroNode(SDValue Elt) {
4497 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Elt))
4498 return CN->isNullValue();
4499 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4500 return CFP->getValueAPF().isPosZero();
4504 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
4505 /// their permute mask.
4506 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
4507 SelectionDAG &DAG) {
4508 MVT VT = SVOp->getSimpleValueType(0);
4509 unsigned NumElems = VT.getVectorNumElements();
4510 SmallVector<int, 8> MaskVec;
4512 for (unsigned i = 0; i != NumElems; ++i) {
4513 int Idx = SVOp->getMaskElt(i);
4515 if (Idx < (int)NumElems)
4520 MaskVec.push_back(Idx);
4522 return DAG.getVectorShuffle(VT, SDLoc(SVOp), SVOp->getOperand(1),
4523 SVOp->getOperand(0), &MaskVec[0]);
4526 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4527 /// match movhlps. The lower half elements should come from upper half of
4528 /// V1 (and in order), and the upper half elements should come from the upper
4529 /// half of V2 (and in order).
4530 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
4531 if (!VT.is128BitVector())
4533 if (VT.getVectorNumElements() != 4)
4535 for (unsigned i = 0, e = 2; i != e; ++i)
4536 if (!isUndefOrEqual(Mask[i], i+2))
4538 for (unsigned i = 2; i != 4; ++i)
4539 if (!isUndefOrEqual(Mask[i], i+4))
4544 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4545 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4547 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
4548 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4550 N = N->getOperand(0).getNode();
4551 if (!ISD::isNON_EXTLoad(N))
4554 *LD = cast<LoadSDNode>(N);
4558 // Test whether the given value is a vector value which will be legalized
4560 static bool WillBeConstantPoolLoad(SDNode *N) {
4561 if (N->getOpcode() != ISD::BUILD_VECTOR)
4564 // Check for any non-constant elements.
4565 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4566 switch (N->getOperand(i).getNode()->getOpcode()) {
4568 case ISD::ConstantFP:
4575 // Vectors of all-zeros and all-ones are materialized with special
4576 // instructions rather than being loaded.
4577 return !ISD::isBuildVectorAllZeros(N) &&
4578 !ISD::isBuildVectorAllOnes(N);
4581 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4582 /// match movlp{s|d}. The lower half elements should come from lower half of
4583 /// V1 (and in order), and the upper half elements should come from the upper
4584 /// half of V2 (and in order). And since V1 will become the source of the
4585 /// MOVLP, it must be either a vector load or a scalar load to vector.
4586 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
4587 ArrayRef<int> Mask, MVT VT) {
4588 if (!VT.is128BitVector())
4591 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
4593 // Is V2 is a vector load, don't do this transformation. We will try to use
4594 // load folding shufps op.
4595 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
4598 unsigned NumElems = VT.getVectorNumElements();
4600 if (NumElems != 2 && NumElems != 4)
4602 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4603 if (!isUndefOrEqual(Mask[i], i))
4605 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4606 if (!isUndefOrEqual(Mask[i], i+NumElems))
4611 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
4613 static bool isSplatVector(SDNode *N) {
4614 if (N->getOpcode() != ISD::BUILD_VECTOR)
4617 SDValue SplatValue = N->getOperand(0);
4618 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
4619 if (N->getOperand(i) != SplatValue)
4624 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
4625 /// to an zero vector.
4626 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
4627 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
4628 SDValue V1 = N->getOperand(0);
4629 SDValue V2 = N->getOperand(1);
4630 unsigned NumElems = N->getValueType(0).getVectorNumElements();
4631 for (unsigned i = 0; i != NumElems; ++i) {
4632 int Idx = N->getMaskElt(i);
4633 if (Idx >= (int)NumElems) {
4634 unsigned Opc = V2.getOpcode();
4635 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4637 if (Opc != ISD::BUILD_VECTOR ||
4638 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
4640 } else if (Idx >= 0) {
4641 unsigned Opc = V1.getOpcode();
4642 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
4644 if (Opc != ISD::BUILD_VECTOR ||
4645 !X86::isZeroNode(V1.getOperand(Idx)))
4652 /// getZeroVector - Returns a vector of specified type with all zero elements.
4654 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4655 SelectionDAG &DAG, SDLoc dl) {
4656 assert(VT.isVector() && "Expected a vector type");
4658 // Always build SSE zero vectors as <4 x i32> bitcasted
4659 // to their dest type. This ensures they get CSE'd.
4661 if (VT.is128BitVector()) { // SSE
4662 if (Subtarget->hasSSE2()) { // SSE2
4663 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4664 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4666 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4667 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4669 } else if (VT.is256BitVector()) { // AVX
4670 if (Subtarget->hasInt256()) { // AVX2
4671 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4672 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4673 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops,
4674 array_lengthof(Ops));
4676 // 256-bit logic and arithmetic instructions in AVX are all
4677 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4678 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4679 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4680 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops,
4681 array_lengthof(Ops));
4684 llvm_unreachable("Unexpected vector type");
4686 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4689 /// getOnesVector - Returns a vector of specified type with all bits set.
4690 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4691 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4692 /// Then bitcast to their original type, ensuring they get CSE'd.
4693 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
4695 assert(VT.isVector() && "Expected a vector type");
4697 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
4699 if (VT.is256BitVector()) {
4700 if (HasInt256) { // AVX2
4701 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4702 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops,
4703 array_lengthof(Ops));
4705 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4706 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4708 } else if (VT.is128BitVector()) {
4709 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4711 llvm_unreachable("Unexpected vector type");
4713 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4716 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
4717 /// that point to V2 points to its first element.
4718 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
4719 for (unsigned i = 0; i != NumElems; ++i) {
4720 if (Mask[i] > (int)NumElems) {
4726 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4727 /// operation of specified width.
4728 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
4730 unsigned NumElems = VT.getVectorNumElements();
4731 SmallVector<int, 8> Mask;
4732 Mask.push_back(NumElems);
4733 for (unsigned i = 1; i != NumElems; ++i)
4735 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4738 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4739 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4741 unsigned NumElems = VT.getVectorNumElements();
4742 SmallVector<int, 8> Mask;
4743 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4745 Mask.push_back(i + NumElems);
4747 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4750 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4751 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4753 unsigned NumElems = VT.getVectorNumElements();
4754 SmallVector<int, 8> Mask;
4755 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4756 Mask.push_back(i + Half);
4757 Mask.push_back(i + NumElems + Half);
4759 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4762 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
4763 // a generic shuffle instruction because the target has no such instructions.
4764 // Generate shuffles which repeat i16 and i8 several times until they can be
4765 // represented by v4f32 and then be manipulated by target suported shuffles.
4766 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
4767 MVT VT = V.getSimpleValueType();
4768 int NumElems = VT.getVectorNumElements();
4771 while (NumElems > 4) {
4772 if (EltNo < NumElems/2) {
4773 V = getUnpackl(DAG, dl, VT, V, V);
4775 V = getUnpackh(DAG, dl, VT, V, V);
4776 EltNo -= NumElems/2;
4783 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
4784 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
4785 MVT VT = V.getSimpleValueType();
4788 if (VT.is128BitVector()) {
4789 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
4790 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
4791 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
4793 } else if (VT.is256BitVector()) {
4794 // To use VPERMILPS to splat scalars, the second half of indicies must
4795 // refer to the higher part, which is a duplication of the lower one,
4796 // because VPERMILPS can only handle in-lane permutations.
4797 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
4798 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
4800 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
4801 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
4804 llvm_unreachable("Vector size not supported");
4806 return DAG.getNode(ISD::BITCAST, dl, VT, V);
4809 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
4810 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
4811 MVT SrcVT = SV->getSimpleValueType(0);
4812 SDValue V1 = SV->getOperand(0);
4815 int EltNo = SV->getSplatIndex();
4816 int NumElems = SrcVT.getVectorNumElements();
4817 bool Is256BitVec = SrcVT.is256BitVector();
4819 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
4820 "Unknown how to promote splat for type");
4822 // Extract the 128-bit part containing the splat element and update
4823 // the splat element index when it refers to the higher register.
4825 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
4826 if (EltNo >= NumElems/2)
4827 EltNo -= NumElems/2;
4830 // All i16 and i8 vector types can't be used directly by a generic shuffle
4831 // instruction because the target has no such instruction. Generate shuffles
4832 // which repeat i16 and i8 several times until they fit in i32, and then can
4833 // be manipulated by target suported shuffles.
4834 MVT EltVT = SrcVT.getVectorElementType();
4835 if (EltVT == MVT::i8 || EltVT == MVT::i16)
4836 V1 = PromoteSplati8i16(V1, DAG, EltNo);
4838 // Recreate the 256-bit vector and place the same 128-bit vector
4839 // into the low and high part. This is necessary because we want
4840 // to use VPERM* to shuffle the vectors
4842 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
4845 return getLegalSplat(DAG, V1, EltNo);
4848 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4849 /// vector of zero or undef vector. This produces a shuffle where the low
4850 /// element of V2 is swizzled into the zero/undef vector, landing at element
4851 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4852 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4854 const X86Subtarget *Subtarget,
4855 SelectionDAG &DAG) {
4856 MVT VT = V2.getSimpleValueType();
4858 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
4859 unsigned NumElems = VT.getVectorNumElements();
4860 SmallVector<int, 16> MaskVec;
4861 for (unsigned i = 0; i != NumElems; ++i)
4862 // If this is the insertion idx, put the low elt of V2 here.
4863 MaskVec.push_back(i == Idx ? NumElems : i);
4864 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
4867 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
4868 /// target specific opcode. Returns true if the Mask could be calculated.
4869 /// Sets IsUnary to true if only uses one source.
4870 static bool getTargetShuffleMask(SDNode *N, MVT VT,
4871 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4872 unsigned NumElems = VT.getVectorNumElements();
4876 switch(N->getOpcode()) {
4878 ImmN = N->getOperand(N->getNumOperands()-1);
4879 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4881 case X86ISD::UNPCKH:
4882 DecodeUNPCKHMask(VT, Mask);
4884 case X86ISD::UNPCKL:
4885 DecodeUNPCKLMask(VT, Mask);
4887 case X86ISD::MOVHLPS:
4888 DecodeMOVHLPSMask(NumElems, Mask);
4890 case X86ISD::MOVLHPS:
4891 DecodeMOVLHPSMask(NumElems, Mask);
4893 case X86ISD::PALIGNR:
4894 ImmN = N->getOperand(N->getNumOperands()-1);
4895 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4897 case X86ISD::PSHUFD:
4898 case X86ISD::VPERMILP:
4899 ImmN = N->getOperand(N->getNumOperands()-1);
4900 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4903 case X86ISD::PSHUFHW:
4904 ImmN = N->getOperand(N->getNumOperands()-1);
4905 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4908 case X86ISD::PSHUFLW:
4909 ImmN = N->getOperand(N->getNumOperands()-1);
4910 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4913 case X86ISD::VPERMI:
4914 ImmN = N->getOperand(N->getNumOperands()-1);
4915 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4919 case X86ISD::MOVSD: {
4920 // The index 0 always comes from the first element of the second source,
4921 // this is why MOVSS and MOVSD are used in the first place. The other
4922 // elements come from the other positions of the first source vector
4923 Mask.push_back(NumElems);
4924 for (unsigned i = 1; i != NumElems; ++i) {
4929 case X86ISD::VPERM2X128:
4930 ImmN = N->getOperand(N->getNumOperands()-1);
4931 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4932 if (Mask.empty()) return false;
4934 case X86ISD::MOVDDUP:
4935 case X86ISD::MOVLHPD:
4936 case X86ISD::MOVLPD:
4937 case X86ISD::MOVLPS:
4938 case X86ISD::MOVSHDUP:
4939 case X86ISD::MOVSLDUP:
4940 // Not yet implemented
4942 default: llvm_unreachable("unknown target shuffle node");
4948 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4949 /// element of the result of the vector shuffle.
4950 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
4953 return SDValue(); // Limit search depth.
4955 SDValue V = SDValue(N, 0);
4956 EVT VT = V.getValueType();
4957 unsigned Opcode = V.getOpcode();
4959 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4960 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4961 int Elt = SV->getMaskElt(Index);
4964 return DAG.getUNDEF(VT.getVectorElementType());
4966 unsigned NumElems = VT.getVectorNumElements();
4967 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
4968 : SV->getOperand(1);
4969 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
4972 // Recurse into target specific vector shuffles to find scalars.
4973 if (isTargetShuffle(Opcode)) {
4974 MVT ShufVT = V.getSimpleValueType();
4975 unsigned NumElems = ShufVT.getVectorNumElements();
4976 SmallVector<int, 16> ShuffleMask;
4979 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
4982 int Elt = ShuffleMask[Index];
4984 return DAG.getUNDEF(ShufVT.getVectorElementType());
4986 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
4988 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
4992 // Actual nodes that may contain scalar elements
4993 if (Opcode == ISD::BITCAST) {
4994 V = V.getOperand(0);
4995 EVT SrcVT = V.getValueType();
4996 unsigned NumElems = VT.getVectorNumElements();
4998 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5002 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5003 return (Index == 0) ? V.getOperand(0)
5004 : DAG.getUNDEF(VT.getVectorElementType());
5006 if (V.getOpcode() == ISD::BUILD_VECTOR)
5007 return V.getOperand(Index);
5012 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5013 /// shuffle operation which come from a consecutively from a zero. The
5014 /// search can start in two different directions, from left or right.
5015 /// We count undefs as zeros until PreferredNum is reached.
5016 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5017 unsigned NumElems, bool ZerosFromLeft,
5019 unsigned PreferredNum = -1U) {
5020 unsigned NumZeros = 0;
5021 for (unsigned i = 0; i != NumElems; ++i) {
5022 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5023 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5027 if (X86::isZeroNode(Elt))
5029 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5030 NumZeros = std::min(NumZeros + 1, PreferredNum);
5038 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5039 /// correspond consecutively to elements from one of the vector operands,
5040 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5042 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5043 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5044 unsigned NumElems, unsigned &OpNum) {
5045 bool SeenV1 = false;
5046 bool SeenV2 = false;
5048 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5049 int Idx = SVOp->getMaskElt(i);
5050 // Ignore undef indicies
5054 if (Idx < (int)NumElems)
5059 // Only accept consecutive elements from the same vector
5060 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5064 OpNum = SeenV1 ? 0 : 1;
5068 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5069 /// logical left shift of a vector.
5070 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5071 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5073 SVOp->getSimpleValueType(0).getVectorNumElements();
5074 unsigned NumZeros = getNumOfConsecutiveZeros(
5075 SVOp, NumElems, false /* check zeros from right */, DAG,
5076 SVOp->getMaskElt(0));
5082 // Considering the elements in the mask that are not consecutive zeros,
5083 // check if they consecutively come from only one of the source vectors.
5085 // V1 = {X, A, B, C} 0
5087 // vector_shuffle V1, V2 <1, 2, 3, X>
5089 if (!isShuffleMaskConsecutive(SVOp,
5090 0, // Mask Start Index
5091 NumElems-NumZeros, // Mask End Index(exclusive)
5092 NumZeros, // Where to start looking in the src vector
5093 NumElems, // Number of elements in vector
5094 OpSrc)) // Which source operand ?
5099 ShVal = SVOp->getOperand(OpSrc);
5103 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5104 /// logical left shift of a vector.
5105 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5106 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5108 SVOp->getSimpleValueType(0).getVectorNumElements();
5109 unsigned NumZeros = getNumOfConsecutiveZeros(
5110 SVOp, NumElems, true /* check zeros from left */, DAG,
5111 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5117 // Considering the elements in the mask that are not consecutive zeros,
5118 // check if they consecutively come from only one of the source vectors.
5120 // 0 { A, B, X, X } = V2
5122 // vector_shuffle V1, V2 <X, X, 4, 5>
5124 if (!isShuffleMaskConsecutive(SVOp,
5125 NumZeros, // Mask Start Index
5126 NumElems, // Mask End Index(exclusive)
5127 0, // Where to start looking in the src vector
5128 NumElems, // Number of elements in vector
5129 OpSrc)) // Which source operand ?
5134 ShVal = SVOp->getOperand(OpSrc);
5138 /// isVectorShift - Returns true if the shuffle can be implemented as a
5139 /// logical left or right shift of a vector.
5140 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5141 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5142 // Although the logic below support any bitwidth size, there are no
5143 // shift instructions which handle more than 128-bit vectors.
5144 if (!SVOp->getSimpleValueType(0).is128BitVector())
5147 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5148 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5154 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5156 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5157 unsigned NumNonZero, unsigned NumZero,
5159 const X86Subtarget* Subtarget,
5160 const TargetLowering &TLI) {
5167 for (unsigned i = 0; i < 16; ++i) {
5168 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5169 if (ThisIsNonZero && First) {
5171 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5173 V = DAG.getUNDEF(MVT::v8i16);
5178 SDValue ThisElt(0, 0), LastElt(0, 0);
5179 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5180 if (LastIsNonZero) {
5181 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5182 MVT::i16, Op.getOperand(i-1));
5184 if (ThisIsNonZero) {
5185 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5186 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5187 ThisElt, DAG.getConstant(8, MVT::i8));
5189 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5193 if (ThisElt.getNode())
5194 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5195 DAG.getIntPtrConstant(i/2));
5199 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5202 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5204 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5205 unsigned NumNonZero, unsigned NumZero,
5207 const X86Subtarget* Subtarget,
5208 const TargetLowering &TLI) {
5215 for (unsigned i = 0; i < 8; ++i) {
5216 bool isNonZero = (NonZeros & (1 << i)) != 0;
5220 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5222 V = DAG.getUNDEF(MVT::v8i16);
5225 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5226 MVT::v8i16, V, Op.getOperand(i),
5227 DAG.getIntPtrConstant(i));
5234 /// getVShift - Return a vector logical shift node.
5236 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5237 unsigned NumBits, SelectionDAG &DAG,
5238 const TargetLowering &TLI, SDLoc dl) {
5239 assert(VT.is128BitVector() && "Unknown type for VShift");
5240 EVT ShVT = MVT::v2i64;
5241 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5242 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5243 return DAG.getNode(ISD::BITCAST, dl, VT,
5244 DAG.getNode(Opc, dl, ShVT, SrcOp,
5245 DAG.getConstant(NumBits,
5246 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5250 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5252 // Check if the scalar load can be widened into a vector load. And if
5253 // the address is "base + cst" see if the cst can be "absorbed" into
5254 // the shuffle mask.
5255 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5256 SDValue Ptr = LD->getBasePtr();
5257 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5259 EVT PVT = LD->getValueType(0);
5260 if (PVT != MVT::i32 && PVT != MVT::f32)
5265 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5266 FI = FINode->getIndex();
5268 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5269 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5270 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5271 Offset = Ptr.getConstantOperandVal(1);
5272 Ptr = Ptr.getOperand(0);
5277 // FIXME: 256-bit vector instructions don't require a strict alignment,
5278 // improve this code to support it better.
5279 unsigned RequiredAlign = VT.getSizeInBits()/8;
5280 SDValue Chain = LD->getChain();
5281 // Make sure the stack object alignment is at least 16 or 32.
5282 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5283 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5284 if (MFI->isFixedObjectIndex(FI)) {
5285 // Can't change the alignment. FIXME: It's possible to compute
5286 // the exact stack offset and reference FI + adjust offset instead.
5287 // If someone *really* cares about this. That's the way to implement it.
5290 MFI->setObjectAlignment(FI, RequiredAlign);
5294 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5295 // Ptr + (Offset & ~15).
5298 if ((Offset % RequiredAlign) & 3)
5300 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5302 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5303 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5305 int EltNo = (Offset - StartOffset) >> 2;
5306 unsigned NumElems = VT.getVectorNumElements();
5308 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5309 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5310 LD->getPointerInfo().getWithOffset(StartOffset),
5311 false, false, false, 0);
5313 SmallVector<int, 8> Mask;
5314 for (unsigned i = 0; i != NumElems; ++i)
5315 Mask.push_back(EltNo);
5317 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5323 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5324 /// vector of type 'VT', see if the elements can be replaced by a single large
5325 /// load which has the same value as a build_vector whose operands are 'elts'.
5327 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5329 /// FIXME: we'd also like to handle the case where the last elements are zero
5330 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5331 /// There's even a handy isZeroNode for that purpose.
5332 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
5333 SDLoc &DL, SelectionDAG &DAG) {
5334 EVT EltVT = VT.getVectorElementType();
5335 unsigned NumElems = Elts.size();
5337 LoadSDNode *LDBase = NULL;
5338 unsigned LastLoadedElt = -1U;
5340 // For each element in the initializer, see if we've found a load or an undef.
5341 // If we don't find an initial load element, or later load elements are
5342 // non-consecutive, bail out.
5343 for (unsigned i = 0; i < NumElems; ++i) {
5344 SDValue Elt = Elts[i];
5346 if (!Elt.getNode() ||
5347 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5350 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5352 LDBase = cast<LoadSDNode>(Elt.getNode());
5356 if (Elt.getOpcode() == ISD::UNDEF)
5359 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5360 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5365 // If we have found an entire vector of loads and undefs, then return a large
5366 // load of the entire vector width starting at the base pointer. If we found
5367 // consecutive loads for the low half, generate a vzext_load node.
5368 if (LastLoadedElt == NumElems - 1) {
5369 SDValue NewLd = SDValue();
5370 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
5371 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5372 LDBase->getPointerInfo(),
5373 LDBase->isVolatile(), LDBase->isNonTemporal(),
5374 LDBase->isInvariant(), 0);
5375 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5376 LDBase->getPointerInfo(),
5377 LDBase->isVolatile(), LDBase->isNonTemporal(),
5378 LDBase->isInvariant(), LDBase->getAlignment());
5380 if (LDBase->hasAnyUseOfValue(1)) {
5381 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5383 SDValue(NewLd.getNode(), 1));
5384 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5385 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5386 SDValue(NewLd.getNode(), 1));
5391 if (NumElems == 4 && LastLoadedElt == 1 &&
5392 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5393 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5394 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5396 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops,
5397 array_lengthof(Ops), MVT::i64,
5398 LDBase->getPointerInfo(),
5399 LDBase->getAlignment(),
5400 false/*isVolatile*/, true/*ReadMem*/,
5403 // Make sure the newly-created LOAD is in the same position as LDBase in
5404 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5405 // update uses of LDBase's output chain to use the TokenFactor.
5406 if (LDBase->hasAnyUseOfValue(1)) {
5407 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5408 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5409 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5410 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5411 SDValue(ResNode.getNode(), 1));
5414 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
5419 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
5420 /// to generate a splat value for the following cases:
5421 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
5422 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
5423 /// a scalar load, or a constant.
5424 /// The VBROADCAST node is returned when a pattern is found,
5425 /// or SDValue() otherwise.
5426 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
5427 SelectionDAG &DAG) {
5428 if (!Subtarget->hasFp256())
5431 MVT VT = Op.getSimpleValueType();
5434 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
5435 "Unsupported vector type for broadcast.");
5440 switch (Op.getOpcode()) {
5442 // Unknown pattern found.
5445 case ISD::BUILD_VECTOR: {
5446 // The BUILD_VECTOR node must be a splat.
5447 if (!isSplatVector(Op.getNode()))
5450 Ld = Op.getOperand(0);
5451 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5452 Ld.getOpcode() == ISD::ConstantFP);
5454 // The suspected load node has several users. Make sure that all
5455 // of its users are from the BUILD_VECTOR node.
5456 // Constants may have multiple users.
5457 if (!ConstSplatVal && !Ld->hasNUsesOfValue(VT.getVectorNumElements(), 0))
5462 case ISD::VECTOR_SHUFFLE: {
5463 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5465 // Shuffles must have a splat mask where the first element is
5467 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5470 SDValue Sc = Op.getOperand(0);
5471 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5472 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5474 if (!Subtarget->hasInt256())
5477 // Use the register form of the broadcast instruction available on AVX2.
5478 if (VT.getSizeInBits() >= 256)
5479 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5480 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5483 Ld = Sc.getOperand(0);
5484 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5485 Ld.getOpcode() == ISD::ConstantFP);
5487 // The scalar_to_vector node and the suspected
5488 // load node must have exactly one user.
5489 // Constants may have multiple users.
5491 // AVX-512 has register version of the broadcast
5492 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
5493 Ld.getValueType().getSizeInBits() >= 32;
5494 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
5501 bool IsGE256 = (VT.getSizeInBits() >= 256);
5503 // Handle the broadcasting a single constant scalar from the constant pool
5504 // into a vector. On Sandybridge it is still better to load a constant vector
5505 // from the constant pool and not to broadcast it from a scalar.
5506 if (ConstSplatVal && Subtarget->hasInt256()) {
5507 EVT CVT = Ld.getValueType();
5508 assert(!CVT.isVector() && "Must not broadcast a vector type");
5509 unsigned ScalarSize = CVT.getSizeInBits();
5511 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)) {
5512 const Constant *C = 0;
5513 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5514 C = CI->getConstantIntValue();
5515 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5516 C = CF->getConstantFPValue();
5518 assert(C && "Invalid constant type");
5520 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5521 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
5522 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5523 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
5524 MachinePointerInfo::getConstantPool(),
5525 false, false, false, Alignment);
5527 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5531 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5532 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5534 // Handle AVX2 in-register broadcasts.
5535 if (!IsLoad && Subtarget->hasInt256() &&
5536 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
5537 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5539 // The scalar source must be a normal load.
5543 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64))
5544 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5546 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5547 // double since there is no vbroadcastsd xmm
5548 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
5549 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5550 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5553 // Unsupported broadcast.
5557 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
5558 MVT VT = Op.getSimpleValueType();
5560 // Skip if insert_vec_elt is not supported.
5561 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5562 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
5566 unsigned NumElems = Op.getNumOperands();
5570 SmallVector<unsigned, 4> InsertIndices;
5571 SmallVector<int, 8> Mask(NumElems, -1);
5573 for (unsigned i = 0; i != NumElems; ++i) {
5574 unsigned Opc = Op.getOperand(i).getOpcode();
5576 if (Opc == ISD::UNDEF)
5579 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
5580 // Quit if more than 1 elements need inserting.
5581 if (InsertIndices.size() > 1)
5584 InsertIndices.push_back(i);
5588 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
5589 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
5591 // Quit if extracted from vector of different type.
5592 if (ExtractedFromVec.getValueType() != VT)
5595 // Quit if non-constant index.
5596 if (!isa<ConstantSDNode>(ExtIdx))
5599 if (VecIn1.getNode() == 0)
5600 VecIn1 = ExtractedFromVec;
5601 else if (VecIn1 != ExtractedFromVec) {
5602 if (VecIn2.getNode() == 0)
5603 VecIn2 = ExtractedFromVec;
5604 else if (VecIn2 != ExtractedFromVec)
5605 // Quit if more than 2 vectors to shuffle
5609 unsigned Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
5611 if (ExtractedFromVec == VecIn1)
5613 else if (ExtractedFromVec == VecIn2)
5614 Mask[i] = Idx + NumElems;
5617 if (VecIn1.getNode() == 0)
5620 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5621 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
5622 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
5623 unsigned Idx = InsertIndices[i];
5624 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
5625 DAG.getIntPtrConstant(Idx));
5631 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
5633 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
5635 MVT VT = Op.getSimpleValueType();
5636 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
5637 "Unexpected type in LowerBUILD_VECTORvXi1!");
5640 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5641 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
5642 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5643 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5644 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
5645 Ops, VT.getVectorNumElements());
5648 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5649 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
5650 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5651 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5652 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
5653 Ops, VT.getVectorNumElements());
5656 bool AllContants = true;
5657 uint64_t Immediate = 0;
5658 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5659 SDValue In = Op.getOperand(idx);
5660 if (In.getOpcode() == ISD::UNDEF)
5662 if (!isa<ConstantSDNode>(In)) {
5663 AllContants = false;
5666 if (cast<ConstantSDNode>(In)->getZExtValue())
5667 Immediate |= (1ULL << idx);
5671 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
5672 DAG.getConstant(Immediate, MVT::i16));
5673 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
5674 DAG.getIntPtrConstant(0));
5677 if (!isSplatVector(Op.getNode()))
5678 llvm_unreachable("Unsupported predicate operation");
5680 SDValue In = Op.getOperand(0);
5681 SDValue EFLAGS, X86CC;
5682 if (In.getOpcode() == ISD::SETCC) {
5683 SDValue Op0 = In.getOperand(0);
5684 SDValue Op1 = In.getOperand(1);
5685 ISD::CondCode CC = cast<CondCodeSDNode>(In.getOperand(2))->get();
5686 bool isFP = Op1.getValueType().isFloatingPoint();
5687 unsigned X86CCVal = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
5689 assert(X86CCVal != X86::COND_INVALID && "Unsupported predicate operation");
5691 X86CC = DAG.getConstant(X86CCVal, MVT::i8);
5692 EFLAGS = EmitCmp(Op0, Op1, X86CCVal, DAG);
5693 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
5694 } else if (In.getOpcode() == X86ISD::SETCC) {
5695 X86CC = In.getOperand(0);
5696 EFLAGS = In.getOperand(1);
5705 // res = allOnes ### CMOVNE -1, %res
5708 MVT InVT = In.getSimpleValueType();
5709 SDValue Bit1 = DAG.getNode(ISD::AND, dl, InVT, In, DAG.getConstant(1, InVT));
5710 EFLAGS = EmitTest(Bit1, X86::COND_NE, DAG);
5711 X86CC = DAG.getConstant(X86::COND_NE, MVT::i8);
5714 if (VT == MVT::v16i1) {
5715 SDValue Cst1 = DAG.getConstant(-1, MVT::i16);
5716 SDValue Cst0 = DAG.getConstant(0, MVT::i16);
5717 SDValue CmovOp = DAG.getNode(X86ISD::CMOV, dl, MVT::i16,
5718 Cst0, Cst1, X86CC, EFLAGS);
5719 return DAG.getNode(ISD::BITCAST, dl, VT, CmovOp);
5722 if (VT == MVT::v8i1) {
5723 SDValue Cst1 = DAG.getConstant(-1, MVT::i32);
5724 SDValue Cst0 = DAG.getConstant(0, MVT::i32);
5725 SDValue CmovOp = DAG.getNode(X86ISD::CMOV, dl, MVT::i32,
5726 Cst0, Cst1, X86CC, EFLAGS);
5727 CmovOp = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, CmovOp);
5728 return DAG.getNode(ISD::BITCAST, dl, VT, CmovOp);
5730 llvm_unreachable("Unsupported predicate operation");
5734 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5737 MVT VT = Op.getSimpleValueType();
5738 MVT ExtVT = VT.getVectorElementType();
5739 unsigned NumElems = Op.getNumOperands();
5741 // Generate vectors for predicate vectors.
5742 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
5743 return LowerBUILD_VECTORvXi1(Op, DAG);
5745 // Vectors containing all zeros can be matched by pxor and xorps later
5746 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5747 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
5748 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
5749 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
5752 return getZeroVector(VT, Subtarget, DAG, dl);
5755 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
5756 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
5757 // vpcmpeqd on 256-bit vectors.
5758 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
5759 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
5762 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
5765 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
5766 if (Broadcast.getNode())
5769 unsigned EVTBits = ExtVT.getSizeInBits();
5771 unsigned NumZero = 0;
5772 unsigned NumNonZero = 0;
5773 unsigned NonZeros = 0;
5774 bool IsAllConstants = true;
5775 SmallSet<SDValue, 8> Values;
5776 for (unsigned i = 0; i < NumElems; ++i) {
5777 SDValue Elt = Op.getOperand(i);
5778 if (Elt.getOpcode() == ISD::UNDEF)
5781 if (Elt.getOpcode() != ISD::Constant &&
5782 Elt.getOpcode() != ISD::ConstantFP)
5783 IsAllConstants = false;
5784 if (X86::isZeroNode(Elt))
5787 NonZeros |= (1 << i);
5792 // All undef vector. Return an UNDEF. All zero vectors were handled above.
5793 if (NumNonZero == 0)
5794 return DAG.getUNDEF(VT);
5796 // Special case for single non-zero, non-undef, element.
5797 if (NumNonZero == 1) {
5798 unsigned Idx = countTrailingZeros(NonZeros);
5799 SDValue Item = Op.getOperand(Idx);
5801 // If this is an insertion of an i64 value on x86-32, and if the top bits of
5802 // the value are obviously zero, truncate the value to i32 and do the
5803 // insertion that way. Only do this if the value is non-constant or if the
5804 // value is a constant being inserted into element 0. It is cheaper to do
5805 // a constant pool load than it is to do a movd + shuffle.
5806 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5807 (!IsAllConstants || Idx == 0)) {
5808 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
5810 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5811 EVT VecVT = MVT::v4i32;
5812 unsigned VecElts = 4;
5814 // Truncate the value (which may itself be a constant) to i32, and
5815 // convert it to a vector with movd (S2V+shuffle to zero extend).
5816 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5817 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5818 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5820 // Now we have our 32-bit value zero extended in the low element of
5821 // a vector. If Idx != 0, swizzle it into place.
5823 SmallVector<int, 4> Mask;
5824 Mask.push_back(Idx);
5825 for (unsigned i = 1; i != VecElts; ++i)
5827 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
5830 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5834 // If we have a constant or non-constant insertion into the low element of
5835 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5836 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5837 // depending on what the source datatype is.
5840 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5842 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5843 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5844 if (VT.is256BitVector()) {
5845 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
5846 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
5847 Item, DAG.getIntPtrConstant(0));
5849 assert(VT.is128BitVector() && "Expected an SSE value type!");
5850 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5851 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
5852 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5855 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
5856 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5857 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5858 if (VT.is256BitVector()) {
5859 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
5860 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
5862 assert(VT.is128BitVector() && "Expected an SSE value type!");
5863 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5865 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5869 // Is it a vector logical left shift?
5870 if (NumElems == 2 && Idx == 1 &&
5871 X86::isZeroNode(Op.getOperand(0)) &&
5872 !X86::isZeroNode(Op.getOperand(1))) {
5873 unsigned NumBits = VT.getSizeInBits();
5874 return getVShift(true, VT,
5875 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5876 VT, Op.getOperand(1)),
5877 NumBits/2, DAG, *this, dl);
5880 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
5883 // Otherwise, if this is a vector with i32 or f32 elements, and the element
5884 // is a non-constant being inserted into an element other than the low one,
5885 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
5886 // movd/movss) to move this into the low element, then shuffle it into
5888 if (EVTBits == 32) {
5889 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5891 // Turn it into a shuffle of zero and zero-extended scalar to vector.
5892 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
5893 SmallVector<int, 8> MaskVec;
5894 for (unsigned i = 0; i != NumElems; ++i)
5895 MaskVec.push_back(i == Idx ? 0 : 1);
5896 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
5900 // Splat is obviously ok. Let legalizer expand it to a shuffle.
5901 if (Values.size() == 1) {
5902 if (EVTBits == 32) {
5903 // Instead of a shuffle like this:
5904 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
5905 // Check if it's possible to issue this instead.
5906 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
5907 unsigned Idx = countTrailingZeros(NonZeros);
5908 SDValue Item = Op.getOperand(Idx);
5909 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
5910 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
5915 // A vector full of immediates; various special cases are already
5916 // handled, so this is best done with a single constant-pool load.
5920 // For AVX-length vectors, build the individual 128-bit pieces and use
5921 // shuffles to put them in place.
5922 if (VT.is256BitVector()) {
5923 SmallVector<SDValue, 32> V;
5924 for (unsigned i = 0; i != NumElems; ++i)
5925 V.push_back(Op.getOperand(i));
5927 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
5929 // Build both the lower and upper subvector.
5930 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2);
5931 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2],
5934 // Recreate the wider vector with the lower and upper part.
5935 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
5938 // Let legalizer expand 2-wide build_vectors.
5939 if (EVTBits == 64) {
5940 if (NumNonZero == 1) {
5941 // One half is zero or undef.
5942 unsigned Idx = countTrailingZeros(NonZeros);
5943 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
5944 Op.getOperand(Idx));
5945 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
5950 // If element VT is < 32 bits, convert it to inserts into a zero vector.
5951 if (EVTBits == 8 && NumElems == 16) {
5952 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
5954 if (V.getNode()) return V;
5957 if (EVTBits == 16 && NumElems == 8) {
5958 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
5960 if (V.getNode()) return V;
5963 // If element VT is == 32 bits, turn it into a number of shuffles.
5964 SmallVector<SDValue, 8> V(NumElems);
5965 if (NumElems == 4 && NumZero > 0) {
5966 for (unsigned i = 0; i < 4; ++i) {
5967 bool isZero = !(NonZeros & (1 << i));
5969 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
5971 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5974 for (unsigned i = 0; i < 2; ++i) {
5975 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
5978 V[i] = V[i*2]; // Must be a zero vector.
5981 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
5984 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
5987 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
5992 bool Reverse1 = (NonZeros & 0x3) == 2;
5993 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
5997 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
5998 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
6000 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
6003 if (Values.size() > 1 && VT.is128BitVector()) {
6004 // Check for a build vector of consecutive loads.
6005 for (unsigned i = 0; i < NumElems; ++i)
6006 V[i] = Op.getOperand(i);
6008 // Check for elements which are consecutive loads.
6009 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG);
6013 // Check for a build vector from mostly shuffle plus few inserting.
6014 SDValue Sh = buildFromShuffleMostly(Op, DAG);
6018 // For SSE 4.1, use insertps to put the high elements into the low element.
6019 if (getSubtarget()->hasSSE41()) {
6021 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
6022 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
6024 Result = DAG.getUNDEF(VT);
6026 for (unsigned i = 1; i < NumElems; ++i) {
6027 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
6028 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
6029 Op.getOperand(i), DAG.getIntPtrConstant(i));
6034 // Otherwise, expand into a number of unpckl*, start by extending each of
6035 // our (non-undef) elements to the full vector width with the element in the
6036 // bottom slot of the vector (which generates no code for SSE).
6037 for (unsigned i = 0; i < NumElems; ++i) {
6038 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
6039 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6041 V[i] = DAG.getUNDEF(VT);
6044 // Next, we iteratively mix elements, e.g. for v4f32:
6045 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
6046 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
6047 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
6048 unsigned EltStride = NumElems >> 1;
6049 while (EltStride != 0) {
6050 for (unsigned i = 0; i < EltStride; ++i) {
6051 // If V[i+EltStride] is undef and this is the first round of mixing,
6052 // then it is safe to just drop this shuffle: V[i] is already in the
6053 // right place, the one element (since it's the first round) being
6054 // inserted as undef can be dropped. This isn't safe for successive
6055 // rounds because they will permute elements within both vectors.
6056 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
6057 EltStride == NumElems/2)
6060 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
6069 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
6070 // to create 256-bit vectors from two other 128-bit ones.
6071 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6073 MVT ResVT = Op.getSimpleValueType();
6075 assert((ResVT.is256BitVector() ||
6076 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
6078 SDValue V1 = Op.getOperand(0);
6079 SDValue V2 = Op.getOperand(1);
6080 unsigned NumElems = ResVT.getVectorNumElements();
6081 if(ResVT.is256BitVector())
6082 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6084 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6087 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6088 assert(Op.getNumOperands() == 2);
6090 // AVX/AVX-512 can use the vinsertf128 instruction to create 256-bit vectors
6091 // from two other 128-bit ones.
6092 return LowerAVXCONCAT_VECTORS(Op, DAG);
6095 // Try to lower a shuffle node into a simple blend instruction.
6097 LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
6098 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
6099 SDValue V1 = SVOp->getOperand(0);
6100 SDValue V2 = SVOp->getOperand(1);
6102 MVT VT = SVOp->getSimpleValueType(0);
6103 MVT EltVT = VT.getVectorElementType();
6104 unsigned NumElems = VT.getVectorNumElements();
6106 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
6108 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
6111 // Check the mask for BLEND and build the value.
6112 unsigned MaskValue = 0;
6113 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
6114 unsigned NumLanes = (NumElems-1)/8 + 1;
6115 unsigned NumElemsInLane = NumElems / NumLanes;
6117 // Blend for v16i16 should be symetric for the both lanes.
6118 for (unsigned i = 0; i < NumElemsInLane; ++i) {
6120 int SndLaneEltIdx = (NumLanes == 2) ?
6121 SVOp->getMaskElt(i + NumElemsInLane) : -1;
6122 int EltIdx = SVOp->getMaskElt(i);
6124 if ((EltIdx < 0 || EltIdx == (int)i) &&
6125 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
6128 if (((unsigned)EltIdx == (i + NumElems)) &&
6129 (SndLaneEltIdx < 0 ||
6130 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
6131 MaskValue |= (1<<i);
6136 // Convert i32 vectors to floating point if it is not AVX2.
6137 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
6139 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
6140 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
6142 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
6143 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
6146 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
6147 DAG.getConstant(MaskValue, MVT::i32));
6148 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
6151 // v8i16 shuffles - Prefer shuffles in the following order:
6152 // 1. [all] pshuflw, pshufhw, optional move
6153 // 2. [ssse3] 1 x pshufb
6154 // 3. [ssse3] 2 x pshufb + 1 x por
6155 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
6157 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
6158 SelectionDAG &DAG) {
6159 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6160 SDValue V1 = SVOp->getOperand(0);
6161 SDValue V2 = SVOp->getOperand(1);
6163 SmallVector<int, 8> MaskVals;
6165 // Determine if more than 1 of the words in each of the low and high quadwords
6166 // of the result come from the same quadword of one of the two inputs. Undef
6167 // mask values count as coming from any quadword, for better codegen.
6168 unsigned LoQuad[] = { 0, 0, 0, 0 };
6169 unsigned HiQuad[] = { 0, 0, 0, 0 };
6170 std::bitset<4> InputQuads;
6171 for (unsigned i = 0; i < 8; ++i) {
6172 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
6173 int EltIdx = SVOp->getMaskElt(i);
6174 MaskVals.push_back(EltIdx);
6183 InputQuads.set(EltIdx / 4);
6186 int BestLoQuad = -1;
6187 unsigned MaxQuad = 1;
6188 for (unsigned i = 0; i < 4; ++i) {
6189 if (LoQuad[i] > MaxQuad) {
6191 MaxQuad = LoQuad[i];
6195 int BestHiQuad = -1;
6197 for (unsigned i = 0; i < 4; ++i) {
6198 if (HiQuad[i] > MaxQuad) {
6200 MaxQuad = HiQuad[i];
6204 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
6205 // of the two input vectors, shuffle them into one input vector so only a
6206 // single pshufb instruction is necessary. If There are more than 2 input
6207 // quads, disable the next transformation since it does not help SSSE3.
6208 bool V1Used = InputQuads[0] || InputQuads[1];
6209 bool V2Used = InputQuads[2] || InputQuads[3];
6210 if (Subtarget->hasSSSE3()) {
6211 if (InputQuads.count() == 2 && V1Used && V2Used) {
6212 BestLoQuad = InputQuads[0] ? 0 : 1;
6213 BestHiQuad = InputQuads[2] ? 2 : 3;
6215 if (InputQuads.count() > 2) {
6221 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
6222 // the shuffle mask. If a quad is scored as -1, that means that it contains
6223 // words from all 4 input quadwords.
6225 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
6227 BestLoQuad < 0 ? 0 : BestLoQuad,
6228 BestHiQuad < 0 ? 1 : BestHiQuad
6230 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
6231 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
6232 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
6233 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
6235 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
6236 // source words for the shuffle, to aid later transformations.
6237 bool AllWordsInNewV = true;
6238 bool InOrder[2] = { true, true };
6239 for (unsigned i = 0; i != 8; ++i) {
6240 int idx = MaskVals[i];
6242 InOrder[i/4] = false;
6243 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
6245 AllWordsInNewV = false;
6249 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
6250 if (AllWordsInNewV) {
6251 for (int i = 0; i != 8; ++i) {
6252 int idx = MaskVals[i];
6255 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
6256 if ((idx != i) && idx < 4)
6258 if ((idx != i) && idx > 3)
6267 // If we've eliminated the use of V2, and the new mask is a pshuflw or
6268 // pshufhw, that's as cheap as it gets. Return the new shuffle.
6269 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
6270 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
6271 unsigned TargetMask = 0;
6272 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
6273 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
6274 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
6275 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
6276 getShufflePSHUFLWImmediate(SVOp);
6277 V1 = NewV.getOperand(0);
6278 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
6282 // Promote splats to a larger type which usually leads to more efficient code.
6283 // FIXME: Is this true if pshufb is available?
6284 if (SVOp->isSplat())
6285 return PromoteSplat(SVOp, DAG);
6287 // If we have SSSE3, and all words of the result are from 1 input vector,
6288 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
6289 // is present, fall back to case 4.
6290 if (Subtarget->hasSSSE3()) {
6291 SmallVector<SDValue,16> pshufbMask;
6293 // If we have elements from both input vectors, set the high bit of the
6294 // shuffle mask element to zero out elements that come from V2 in the V1
6295 // mask, and elements that come from V1 in the V2 mask, so that the two
6296 // results can be OR'd together.
6297 bool TwoInputs = V1Used && V2Used;
6298 for (unsigned i = 0; i != 8; ++i) {
6299 int EltIdx = MaskVals[i] * 2;
6300 int Idx0 = (TwoInputs && (EltIdx >= 16)) ? 0x80 : EltIdx;
6301 int Idx1 = (TwoInputs && (EltIdx >= 16)) ? 0x80 : EltIdx+1;
6302 pshufbMask.push_back(DAG.getConstant(Idx0, MVT::i8));
6303 pshufbMask.push_back(DAG.getConstant(Idx1, MVT::i8));
6305 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1);
6306 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
6307 DAG.getNode(ISD::BUILD_VECTOR, dl,
6308 MVT::v16i8, &pshufbMask[0], 16));
6310 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
6312 // Calculate the shuffle mask for the second input, shuffle it, and
6313 // OR it with the first shuffled input.
6315 for (unsigned i = 0; i != 8; ++i) {
6316 int EltIdx = MaskVals[i] * 2;
6317 int Idx0 = (EltIdx < 16) ? 0x80 : EltIdx - 16;
6318 int Idx1 = (EltIdx < 16) ? 0x80 : EltIdx - 15;
6319 pshufbMask.push_back(DAG.getConstant(Idx0, MVT::i8));
6320 pshufbMask.push_back(DAG.getConstant(Idx1, MVT::i8));
6322 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2);
6323 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
6324 DAG.getNode(ISD::BUILD_VECTOR, dl,
6325 MVT::v16i8, &pshufbMask[0], 16));
6326 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
6327 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
6330 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
6331 // and update MaskVals with new element order.
6332 std::bitset<8> InOrder;
6333 if (BestLoQuad >= 0) {
6334 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
6335 for (int i = 0; i != 4; ++i) {
6336 int idx = MaskVals[i];
6339 } else if ((idx / 4) == BestLoQuad) {
6344 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
6347 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
6348 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
6349 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
6351 getShufflePSHUFLWImmediate(SVOp), DAG);
6355 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
6356 // and update MaskVals with the new element order.
6357 if (BestHiQuad >= 0) {
6358 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
6359 for (unsigned i = 4; i != 8; ++i) {
6360 int idx = MaskVals[i];
6363 } else if ((idx / 4) == BestHiQuad) {
6364 MaskV[i] = (idx & 3) + 4;
6368 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
6371 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
6372 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
6373 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
6375 getShufflePSHUFHWImmediate(SVOp), DAG);
6379 // In case BestHi & BestLo were both -1, which means each quadword has a word
6380 // from each of the four input quadwords, calculate the InOrder bitvector now
6381 // before falling through to the insert/extract cleanup.
6382 if (BestLoQuad == -1 && BestHiQuad == -1) {
6384 for (int i = 0; i != 8; ++i)
6385 if (MaskVals[i] < 0 || MaskVals[i] == i)
6389 // The other elements are put in the right place using pextrw and pinsrw.
6390 for (unsigned i = 0; i != 8; ++i) {
6393 int EltIdx = MaskVals[i];
6396 SDValue ExtOp = (EltIdx < 8) ?
6397 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
6398 DAG.getIntPtrConstant(EltIdx)) :
6399 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
6400 DAG.getIntPtrConstant(EltIdx - 8));
6401 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
6402 DAG.getIntPtrConstant(i));
6407 // v16i8 shuffles - Prefer shuffles in the following order:
6408 // 1. [ssse3] 1 x pshufb
6409 // 2. [ssse3] 2 x pshufb + 1 x por
6410 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
6411 static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
6412 const X86Subtarget* Subtarget,
6413 SelectionDAG &DAG) {
6414 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6415 SDValue V1 = SVOp->getOperand(0);
6416 SDValue V2 = SVOp->getOperand(1);
6418 ArrayRef<int> MaskVals = SVOp->getMask();
6420 // Promote splats to a larger type which usually leads to more efficient code.
6421 // FIXME: Is this true if pshufb is available?
6422 if (SVOp->isSplat())
6423 return PromoteSplat(SVOp, DAG);
6425 // If we have SSSE3, case 1 is generated when all result bytes come from
6426 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
6427 // present, fall back to case 3.
6429 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
6430 if (Subtarget->hasSSSE3()) {
6431 SmallVector<SDValue,16> pshufbMask;
6433 // If all result elements are from one input vector, then only translate
6434 // undef mask values to 0x80 (zero out result) in the pshufb mask.
6436 // Otherwise, we have elements from both input vectors, and must zero out
6437 // elements that come from V2 in the first mask, and V1 in the second mask
6438 // so that we can OR them together.
6439 for (unsigned i = 0; i != 16; ++i) {
6440 int EltIdx = MaskVals[i];
6441 if (EltIdx < 0 || EltIdx >= 16)
6443 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
6445 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
6446 DAG.getNode(ISD::BUILD_VECTOR, dl,
6447 MVT::v16i8, &pshufbMask[0], 16));
6449 // As PSHUFB will zero elements with negative indices, it's safe to ignore
6450 // the 2nd operand if it's undefined or zero.
6451 if (V2.getOpcode() == ISD::UNDEF ||
6452 ISD::isBuildVectorAllZeros(V2.getNode()))
6455 // Calculate the shuffle mask for the second input, shuffle it, and
6456 // OR it with the first shuffled input.
6458 for (unsigned i = 0; i != 16; ++i) {
6459 int EltIdx = MaskVals[i];
6460 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
6461 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
6463 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
6464 DAG.getNode(ISD::BUILD_VECTOR, dl,
6465 MVT::v16i8, &pshufbMask[0], 16));
6466 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
6469 // No SSSE3 - Calculate in place words and then fix all out of place words
6470 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
6471 // the 16 different words that comprise the two doublequadword input vectors.
6472 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
6473 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
6475 for (int i = 0; i != 8; ++i) {
6476 int Elt0 = MaskVals[i*2];
6477 int Elt1 = MaskVals[i*2+1];
6479 // This word of the result is all undef, skip it.
6480 if (Elt0 < 0 && Elt1 < 0)
6483 // This word of the result is already in the correct place, skip it.
6484 if ((Elt0 == i*2) && (Elt1 == i*2+1))
6487 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
6488 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
6491 // If Elt0 and Elt1 are defined, are consecutive, and can be load
6492 // using a single extract together, load it and store it.
6493 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
6494 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
6495 DAG.getIntPtrConstant(Elt1 / 2));
6496 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
6497 DAG.getIntPtrConstant(i));
6501 // If Elt1 is defined, extract it from the appropriate source. If the
6502 // source byte is not also odd, shift the extracted word left 8 bits
6503 // otherwise clear the bottom 8 bits if we need to do an or.
6505 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
6506 DAG.getIntPtrConstant(Elt1 / 2));
6507 if ((Elt1 & 1) == 0)
6508 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
6510 TLI.getShiftAmountTy(InsElt.getValueType())));
6512 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
6513 DAG.getConstant(0xFF00, MVT::i16));
6515 // If Elt0 is defined, extract it from the appropriate source. If the
6516 // source byte is not also even, shift the extracted word right 8 bits. If
6517 // Elt1 was also defined, OR the extracted values together before
6518 // inserting them in the result.
6520 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
6521 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
6522 if ((Elt0 & 1) != 0)
6523 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
6525 TLI.getShiftAmountTy(InsElt0.getValueType())));
6527 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
6528 DAG.getConstant(0x00FF, MVT::i16));
6529 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
6532 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
6533 DAG.getIntPtrConstant(i));
6535 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
6538 // v32i8 shuffles - Translate to VPSHUFB if possible.
6540 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
6541 const X86Subtarget *Subtarget,
6542 SelectionDAG &DAG) {
6543 MVT VT = SVOp->getSimpleValueType(0);
6544 SDValue V1 = SVOp->getOperand(0);
6545 SDValue V2 = SVOp->getOperand(1);
6547 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
6549 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
6550 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
6551 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
6553 // VPSHUFB may be generated if
6554 // (1) one of input vector is undefined or zeroinitializer.
6555 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
6556 // And (2) the mask indexes don't cross the 128-bit lane.
6557 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
6558 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
6561 if (V1IsAllZero && !V2IsAllZero) {
6562 CommuteVectorShuffleMask(MaskVals, 32);
6565 SmallVector<SDValue, 32> pshufbMask;
6566 for (unsigned i = 0; i != 32; i++) {
6567 int EltIdx = MaskVals[i];
6568 if (EltIdx < 0 || EltIdx >= 32)
6571 if ((EltIdx >= 16 && i < 16) || (EltIdx < 16 && i >= 16))
6572 // Cross lane is not allowed.
6576 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
6578 return DAG.getNode(X86ISD::PSHUFB, dl, MVT::v32i8, V1,
6579 DAG.getNode(ISD::BUILD_VECTOR, dl,
6580 MVT::v32i8, &pshufbMask[0], 32));
6583 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
6584 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
6585 /// done when every pair / quad of shuffle mask elements point to elements in
6586 /// the right sequence. e.g.
6587 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
6589 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
6590 SelectionDAG &DAG) {
6591 MVT VT = SVOp->getSimpleValueType(0);
6593 unsigned NumElems = VT.getVectorNumElements();
6596 switch (VT.SimpleTy) {
6597 default: llvm_unreachable("Unexpected!");
6598 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
6599 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
6600 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
6601 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
6602 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
6603 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
6606 SmallVector<int, 8> MaskVec;
6607 for (unsigned i = 0; i != NumElems; i += Scale) {
6609 for (unsigned j = 0; j != Scale; ++j) {
6610 int EltIdx = SVOp->getMaskElt(i+j);
6614 StartIdx = (EltIdx / Scale);
6615 if (EltIdx != (int)(StartIdx*Scale + j))
6618 MaskVec.push_back(StartIdx);
6621 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
6622 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
6623 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
6626 /// getVZextMovL - Return a zero-extending vector move low node.
6628 static SDValue getVZextMovL(MVT VT, MVT OpVT,
6629 SDValue SrcOp, SelectionDAG &DAG,
6630 const X86Subtarget *Subtarget, SDLoc dl) {
6631 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
6632 LoadSDNode *LD = NULL;
6633 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
6634 LD = dyn_cast<LoadSDNode>(SrcOp);
6636 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
6638 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
6639 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
6640 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
6641 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
6642 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
6644 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
6645 return DAG.getNode(ISD::BITCAST, dl, VT,
6646 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
6647 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6655 return DAG.getNode(ISD::BITCAST, dl, VT,
6656 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
6657 DAG.getNode(ISD::BITCAST, dl,
6661 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
6662 /// which could not be matched by any known target speficic shuffle
6664 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6666 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
6667 if (NewOp.getNode())
6670 MVT VT = SVOp->getSimpleValueType(0);
6672 unsigned NumElems = VT.getVectorNumElements();
6673 unsigned NumLaneElems = NumElems / 2;
6676 MVT EltVT = VT.getVectorElementType();
6677 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
6680 SmallVector<int, 16> Mask;
6681 for (unsigned l = 0; l < 2; ++l) {
6682 // Build a shuffle mask for the output, discovering on the fly which
6683 // input vectors to use as shuffle operands (recorded in InputUsed).
6684 // If building a suitable shuffle vector proves too hard, then bail
6685 // out with UseBuildVector set.
6686 bool UseBuildVector = false;
6687 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
6688 unsigned LaneStart = l * NumLaneElems;
6689 for (unsigned i = 0; i != NumLaneElems; ++i) {
6690 // The mask element. This indexes into the input.
6691 int Idx = SVOp->getMaskElt(i+LaneStart);
6693 // the mask element does not index into any input vector.
6698 // The input vector this mask element indexes into.
6699 int Input = Idx / NumLaneElems;
6701 // Turn the index into an offset from the start of the input vector.
6702 Idx -= Input * NumLaneElems;
6704 // Find or create a shuffle vector operand to hold this input.
6706 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
6707 if (InputUsed[OpNo] == Input)
6708 // This input vector is already an operand.
6710 if (InputUsed[OpNo] < 0) {
6711 // Create a new operand for this input vector.
6712 InputUsed[OpNo] = Input;
6717 if (OpNo >= array_lengthof(InputUsed)) {
6718 // More than two input vectors used! Give up on trying to create a
6719 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
6720 UseBuildVector = true;
6724 // Add the mask index for the new shuffle vector.
6725 Mask.push_back(Idx + OpNo * NumLaneElems);
6728 if (UseBuildVector) {
6729 SmallVector<SDValue, 16> SVOps;
6730 for (unsigned i = 0; i != NumLaneElems; ++i) {
6731 // The mask element. This indexes into the input.
6732 int Idx = SVOp->getMaskElt(i+LaneStart);
6734 SVOps.push_back(DAG.getUNDEF(EltVT));
6738 // The input vector this mask element indexes into.
6739 int Input = Idx / NumElems;
6741 // Turn the index into an offset from the start of the input vector.
6742 Idx -= Input * NumElems;
6744 // Extract the vector element by hand.
6745 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
6746 SVOp->getOperand(Input),
6747 DAG.getIntPtrConstant(Idx)));
6750 // Construct the output using a BUILD_VECTOR.
6751 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, &SVOps[0],
6753 } else if (InputUsed[0] < 0) {
6754 // No input vectors were used! The result is undefined.
6755 Output[l] = DAG.getUNDEF(NVT);
6757 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
6758 (InputUsed[0] % 2) * NumLaneElems,
6760 // If only one input was used, use an undefined vector for the other.
6761 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
6762 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
6763 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
6764 // At least one input vector was used. Create a new shuffle vector.
6765 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
6771 // Concatenate the result back
6772 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
6775 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
6776 /// 4 elements, and match them with several different shuffle types.
6778 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6779 SDValue V1 = SVOp->getOperand(0);
6780 SDValue V2 = SVOp->getOperand(1);
6782 MVT VT = SVOp->getSimpleValueType(0);
6784 assert(VT.is128BitVector() && "Unsupported vector size");
6786 std::pair<int, int> Locs[4];
6787 int Mask1[] = { -1, -1, -1, -1 };
6788 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
6792 for (unsigned i = 0; i != 4; ++i) {
6793 int Idx = PermMask[i];
6795 Locs[i] = std::make_pair(-1, -1);
6797 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
6799 Locs[i] = std::make_pair(0, NumLo);
6803 Locs[i] = std::make_pair(1, NumHi);
6805 Mask1[2+NumHi] = Idx;
6811 if (NumLo <= 2 && NumHi <= 2) {
6812 // If no more than two elements come from either vector. This can be
6813 // implemented with two shuffles. First shuffle gather the elements.
6814 // The second shuffle, which takes the first shuffle as both of its
6815 // vector operands, put the elements into the right order.
6816 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6818 int Mask2[] = { -1, -1, -1, -1 };
6820 for (unsigned i = 0; i != 4; ++i)
6821 if (Locs[i].first != -1) {
6822 unsigned Idx = (i < 2) ? 0 : 4;
6823 Idx += Locs[i].first * 2 + Locs[i].second;
6827 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
6830 if (NumLo == 3 || NumHi == 3) {
6831 // Otherwise, we must have three elements from one vector, call it X, and
6832 // one element from the other, call it Y. First, use a shufps to build an
6833 // intermediate vector with the one element from Y and the element from X
6834 // that will be in the same half in the final destination (the indexes don't
6835 // matter). Then, use a shufps to build the final vector, taking the half
6836 // containing the element from Y from the intermediate, and the other half
6839 // Normalize it so the 3 elements come from V1.
6840 CommuteVectorShuffleMask(PermMask, 4);
6844 // Find the element from V2.
6846 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
6847 int Val = PermMask[HiIndex];
6854 Mask1[0] = PermMask[HiIndex];
6856 Mask1[2] = PermMask[HiIndex^1];
6858 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6861 Mask1[0] = PermMask[0];
6862 Mask1[1] = PermMask[1];
6863 Mask1[2] = HiIndex & 1 ? 6 : 4;
6864 Mask1[3] = HiIndex & 1 ? 4 : 6;
6865 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6868 Mask1[0] = HiIndex & 1 ? 2 : 0;
6869 Mask1[1] = HiIndex & 1 ? 0 : 2;
6870 Mask1[2] = PermMask[2];
6871 Mask1[3] = PermMask[3];
6876 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
6879 // Break it into (shuffle shuffle_hi, shuffle_lo).
6880 int LoMask[] = { -1, -1, -1, -1 };
6881 int HiMask[] = { -1, -1, -1, -1 };
6883 int *MaskPtr = LoMask;
6884 unsigned MaskIdx = 0;
6887 for (unsigned i = 0; i != 4; ++i) {
6894 int Idx = PermMask[i];
6896 Locs[i] = std::make_pair(-1, -1);
6897 } else if (Idx < 4) {
6898 Locs[i] = std::make_pair(MaskIdx, LoIdx);
6899 MaskPtr[LoIdx] = Idx;
6902 Locs[i] = std::make_pair(MaskIdx, HiIdx);
6903 MaskPtr[HiIdx] = Idx;
6908 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
6909 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
6910 int MaskOps[] = { -1, -1, -1, -1 };
6911 for (unsigned i = 0; i != 4; ++i)
6912 if (Locs[i].first != -1)
6913 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
6914 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
6917 static bool MayFoldVectorLoad(SDValue V) {
6918 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6919 V = V.getOperand(0);
6921 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6922 V = V.getOperand(0);
6923 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
6924 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
6925 // BUILD_VECTOR (load), undef
6926 V = V.getOperand(0);
6928 return MayFoldLoad(V);
6932 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
6933 MVT VT = Op.getSimpleValueType();
6935 // Canonizalize to v2f64.
6936 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
6937 return DAG.getNode(ISD::BITCAST, dl, VT,
6938 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
6943 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
6945 SDValue V1 = Op.getOperand(0);
6946 SDValue V2 = Op.getOperand(1);
6947 MVT VT = Op.getSimpleValueType();
6949 assert(VT != MVT::v2i64 && "unsupported shuffle type");
6951 if (HasSSE2 && VT == MVT::v2f64)
6952 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
6954 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
6955 return DAG.getNode(ISD::BITCAST, dl, VT,
6956 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
6957 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
6958 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
6962 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
6963 SDValue V1 = Op.getOperand(0);
6964 SDValue V2 = Op.getOperand(1);
6965 MVT VT = Op.getSimpleValueType();
6967 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
6968 "unsupported shuffle type");
6970 if (V2.getOpcode() == ISD::UNDEF)
6974 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
6978 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
6979 SDValue V1 = Op.getOperand(0);
6980 SDValue V2 = Op.getOperand(1);
6981 MVT VT = Op.getSimpleValueType();
6982 unsigned NumElems = VT.getVectorNumElements();
6984 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
6985 // operand of these instructions is only memory, so check if there's a
6986 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
6988 bool CanFoldLoad = false;
6990 // Trivial case, when V2 comes from a load.
6991 if (MayFoldVectorLoad(V2))
6994 // When V1 is a load, it can be folded later into a store in isel, example:
6995 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
6997 // (MOVLPSmr addr:$src1, VR128:$src2)
6998 // So, recognize this potential and also use MOVLPS or MOVLPD
6999 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
7002 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7004 if (HasSSE2 && NumElems == 2)
7005 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
7008 // If we don't care about the second element, proceed to use movss.
7009 if (SVOp->getMaskElt(1) != -1)
7010 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
7013 // movl and movlp will both match v2i64, but v2i64 is never matched by
7014 // movl earlier because we make it strict to avoid messing with the movlp load
7015 // folding logic (see the code above getMOVLP call). Match it here then,
7016 // this is horrible, but will stay like this until we move all shuffle
7017 // matching to x86 specific nodes. Note that for the 1st condition all
7018 // types are matched with movsd.
7020 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
7021 // as to remove this logic from here, as much as possible
7022 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
7023 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
7024 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
7027 assert(VT != MVT::v4i32 && "unsupported shuffle type");
7029 // Invert the operand order and use SHUFPS to match it.
7030 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
7031 getShuffleSHUFImmediate(SVOp), DAG);
7034 // Reduce a vector shuffle to zext.
7035 static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
7036 SelectionDAG &DAG) {
7037 // PMOVZX is only available from SSE41.
7038 if (!Subtarget->hasSSE41())
7041 MVT VT = Op.getSimpleValueType();
7043 // Only AVX2 support 256-bit vector integer extending.
7044 if (!Subtarget->hasInt256() && VT.is256BitVector())
7047 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7049 SDValue V1 = Op.getOperand(0);
7050 SDValue V2 = Op.getOperand(1);
7051 unsigned NumElems = VT.getVectorNumElements();
7053 // Extending is an unary operation and the element type of the source vector
7054 // won't be equal to or larger than i64.
7055 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
7056 VT.getVectorElementType() == MVT::i64)
7059 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
7060 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
7061 while ((1U << Shift) < NumElems) {
7062 if (SVOp->getMaskElt(1U << Shift) == 1)
7065 // The maximal ratio is 8, i.e. from i8 to i64.
7070 // Check the shuffle mask.
7071 unsigned Mask = (1U << Shift) - 1;
7072 for (unsigned i = 0; i != NumElems; ++i) {
7073 int EltIdx = SVOp->getMaskElt(i);
7074 if ((i & Mask) != 0 && EltIdx != -1)
7076 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
7080 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
7081 MVT NeVT = MVT::getIntegerVT(NBits);
7082 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift);
7084 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT))
7087 // Simplify the operand as it's prepared to be fed into shuffle.
7088 unsigned SignificantBits = NVT.getSizeInBits() >> Shift;
7089 if (V1.getOpcode() == ISD::BITCAST &&
7090 V1.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
7091 V1.getOperand(0).getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
7092 V1.getOperand(0).getOperand(0)
7093 .getSimpleValueType().getSizeInBits() == SignificantBits) {
7094 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
7095 SDValue V = V1.getOperand(0).getOperand(0).getOperand(0);
7096 ConstantSDNode *CIdx =
7097 dyn_cast<ConstantSDNode>(V1.getOperand(0).getOperand(0).getOperand(1));
7098 // If it's foldable, i.e. normal load with single use, we will let code
7099 // selection to fold it. Otherwise, we will short the conversion sequence.
7100 if (CIdx && CIdx->getZExtValue() == 0 &&
7101 (!ISD::isNormalLoad(V.getNode()) || !V.hasOneUse())) {
7102 MVT FullVT = V.getSimpleValueType();
7103 MVT V1VT = V1.getSimpleValueType();
7104 if (FullVT.getSizeInBits() > V1VT.getSizeInBits()) {
7105 // The "ext_vec_elt" node is wider than the result node.
7106 // In this case we should extract subvector from V.
7107 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast (extract_subvector x)).
7108 unsigned Ratio = FullVT.getSizeInBits() / V1VT.getSizeInBits();
7109 MVT SubVecVT = MVT::getVectorVT(FullVT.getVectorElementType(),
7110 FullVT.getVectorNumElements()/Ratio);
7111 V = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVecVT, V,
7112 DAG.getIntPtrConstant(0));
7114 V1 = DAG.getNode(ISD::BITCAST, DL, V1VT, V);
7118 return DAG.getNode(ISD::BITCAST, DL, VT,
7119 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
7123 NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
7124 SelectionDAG &DAG) {
7125 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7126 MVT VT = Op.getSimpleValueType();
7128 SDValue V1 = Op.getOperand(0);
7129 SDValue V2 = Op.getOperand(1);
7131 if (isZeroShuffle(SVOp))
7132 return getZeroVector(VT, Subtarget, DAG, dl);
7134 // Handle splat operations
7135 if (SVOp->isSplat()) {
7136 // Use vbroadcast whenever the splat comes from a foldable load
7137 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
7138 if (Broadcast.getNode())
7142 // Check integer expanding shuffles.
7143 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG);
7144 if (NewOp.getNode())
7147 // If the shuffle can be profitably rewritten as a narrower shuffle, then
7149 if (VT == MVT::v8i16 || VT == MVT::v16i8 ||
7150 VT == MVT::v16i16 || VT == MVT::v32i8) {
7151 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
7152 if (NewOp.getNode())
7153 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
7154 } else if ((VT == MVT::v4i32 ||
7155 (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
7156 // FIXME: Figure out a cleaner way to do this.
7157 // Try to make use of movq to zero out the top part.
7158 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
7159 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
7160 if (NewOp.getNode()) {
7161 MVT NewVT = NewOp.getSimpleValueType();
7162 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
7163 NewVT, true, false))
7164 return getVZextMovL(VT, NewVT, NewOp.getOperand(0),
7165 DAG, Subtarget, dl);
7167 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
7168 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
7169 if (NewOp.getNode()) {
7170 MVT NewVT = NewOp.getSimpleValueType();
7171 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
7172 return getVZextMovL(VT, NewVT, NewOp.getOperand(1),
7173 DAG, Subtarget, dl);
7181 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
7182 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7183 SDValue V1 = Op.getOperand(0);
7184 SDValue V2 = Op.getOperand(1);
7185 MVT VT = Op.getSimpleValueType();
7187 unsigned NumElems = VT.getVectorNumElements();
7188 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
7189 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
7190 bool V1IsSplat = false;
7191 bool V2IsSplat = false;
7192 bool HasSSE2 = Subtarget->hasSSE2();
7193 bool HasFp256 = Subtarget->hasFp256();
7194 bool HasInt256 = Subtarget->hasInt256();
7195 MachineFunction &MF = DAG.getMachineFunction();
7196 bool OptForSize = MF.getFunction()->getAttributes().
7197 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
7199 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
7201 if (V1IsUndef && V2IsUndef)
7202 return DAG.getUNDEF(VT);
7204 assert(!V1IsUndef && "Op 1 of shuffle should not be undef");
7206 // Vector shuffle lowering takes 3 steps:
7208 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
7209 // narrowing and commutation of operands should be handled.
7210 // 2) Matching of shuffles with known shuffle masks to x86 target specific
7212 // 3) Rewriting of unmatched masks into new generic shuffle operations,
7213 // so the shuffle can be broken into other shuffles and the legalizer can
7214 // try the lowering again.
7216 // The general idea is that no vector_shuffle operation should be left to
7217 // be matched during isel, all of them must be converted to a target specific
7220 // Normalize the input vectors. Here splats, zeroed vectors, profitable
7221 // narrowing and commutation of operands should be handled. The actual code
7222 // doesn't include all of those, work in progress...
7223 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
7224 if (NewOp.getNode())
7227 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
7229 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
7230 // unpckh_undef). Only use pshufd if speed is more important than size.
7231 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
7232 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
7233 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
7234 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
7236 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
7237 V2IsUndef && MayFoldVectorLoad(V1))
7238 return getMOVDDup(Op, dl, V1, DAG);
7240 if (isMOVHLPS_v_undef_Mask(M, VT))
7241 return getMOVHighToLow(Op, dl, DAG);
7243 // Use to match splats
7244 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
7245 (VT == MVT::v2f64 || VT == MVT::v2i64))
7246 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
7248 if (isPSHUFDMask(M, VT)) {
7249 // The actual implementation will match the mask in the if above and then
7250 // during isel it can match several different instructions, not only pshufd
7251 // as its name says, sad but true, emulate the behavior for now...
7252 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
7253 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
7255 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
7257 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
7258 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
7260 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
7261 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, TargetMask,
7264 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
7268 if (isPALIGNRMask(M, VT, Subtarget))
7269 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
7270 getShufflePALIGNRImmediate(SVOp),
7273 // Check if this can be converted into a logical shift.
7274 bool isLeft = false;
7277 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
7278 if (isShift && ShVal.hasOneUse()) {
7279 // If the shifted value has multiple uses, it may be cheaper to use
7280 // v_set0 + movlhps or movhlps, etc.
7281 MVT EltVT = VT.getVectorElementType();
7282 ShAmt *= EltVT.getSizeInBits();
7283 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
7286 if (isMOVLMask(M, VT)) {
7287 if (ISD::isBuildVectorAllZeros(V1.getNode()))
7288 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
7289 if (!isMOVLPMask(M, VT)) {
7290 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
7291 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
7293 if (VT == MVT::v4i32 || VT == MVT::v4f32)
7294 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
7298 // FIXME: fold these into legal mask.
7299 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
7300 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
7302 if (isMOVHLPSMask(M, VT))
7303 return getMOVHighToLow(Op, dl, DAG);
7305 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
7306 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
7308 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
7309 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
7311 if (isMOVLPMask(M, VT))
7312 return getMOVLP(Op, dl, DAG, HasSSE2);
7314 if (ShouldXformToMOVHLPS(M, VT) ||
7315 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
7316 return CommuteVectorShuffle(SVOp, DAG);
7319 // No better options. Use a vshldq / vsrldq.
7320 MVT EltVT = VT.getVectorElementType();
7321 ShAmt *= EltVT.getSizeInBits();
7322 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
7325 bool Commuted = false;
7326 // FIXME: This should also accept a bitcast of a splat? Be careful, not
7327 // 1,1,1,1 -> v8i16 though.
7328 V1IsSplat = isSplatVector(V1.getNode());
7329 V2IsSplat = isSplatVector(V2.getNode());
7331 // Canonicalize the splat or undef, if present, to be on the RHS.
7332 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
7333 CommuteVectorShuffleMask(M, NumElems);
7335 std::swap(V1IsSplat, V2IsSplat);
7339 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
7340 // Shuffling low element of v1 into undef, just return v1.
7343 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
7344 // the instruction selector will not match, so get a canonical MOVL with
7345 // swapped operands to undo the commute.
7346 return getMOVL(DAG, dl, VT, V2, V1);
7349 if (isUNPCKLMask(M, VT, HasInt256))
7350 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
7352 if (isUNPCKHMask(M, VT, HasInt256))
7353 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
7356 // Normalize mask so all entries that point to V2 points to its first
7357 // element then try to match unpck{h|l} again. If match, return a
7358 // new vector_shuffle with the corrected mask.p
7359 SmallVector<int, 8> NewMask(M.begin(), M.end());
7360 NormalizeMask(NewMask, NumElems);
7361 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
7362 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
7363 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
7364 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
7368 // Commute is back and try unpck* again.
7369 // FIXME: this seems wrong.
7370 CommuteVectorShuffleMask(M, NumElems);
7372 std::swap(V1IsSplat, V2IsSplat);
7375 if (isUNPCKLMask(M, VT, HasInt256))
7376 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
7378 if (isUNPCKHMask(M, VT, HasInt256))
7379 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
7382 // Normalize the node to match x86 shuffle ops if needed
7383 if (!V2IsUndef && (isSHUFPMask(M, VT, HasFp256, /* Commuted */ true)))
7384 return CommuteVectorShuffle(SVOp, DAG);
7386 // The checks below are all present in isShuffleMaskLegal, but they are
7387 // inlined here right now to enable us to directly emit target specific
7388 // nodes, and remove one by one until they don't return Op anymore.
7390 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
7391 SVOp->getSplatIndex() == 0 && V2IsUndef) {
7392 if (VT == MVT::v2f64 || VT == MVT::v2i64)
7393 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
7396 if (isPSHUFHWMask(M, VT, HasInt256))
7397 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
7398 getShufflePSHUFHWImmediate(SVOp),
7401 if (isPSHUFLWMask(M, VT, HasInt256))
7402 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
7403 getShufflePSHUFLWImmediate(SVOp),
7406 if (isSHUFPMask(M, VT, HasFp256))
7407 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
7408 getShuffleSHUFImmediate(SVOp), DAG);
7410 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
7411 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
7412 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
7413 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
7415 //===--------------------------------------------------------------------===//
7416 // Generate target specific nodes for 128 or 256-bit shuffles only
7417 // supported in the AVX instruction set.
7420 // Handle VMOVDDUPY permutations
7421 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
7422 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
7424 // Handle VPERMILPS/D* permutations
7425 if (isVPERMILPMask(M, VT, HasFp256)) {
7426 if (HasInt256 && VT == MVT::v8i32)
7427 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
7428 getShuffleSHUFImmediate(SVOp), DAG);
7429 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1,
7430 getShuffleSHUFImmediate(SVOp), DAG);
7433 // Handle VPERM2F128/VPERM2I128 permutations
7434 if (isVPERM2X128Mask(M, VT, HasFp256))
7435 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
7436 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
7438 SDValue BlendOp = LowerVECTOR_SHUFFLEtoBlend(SVOp, Subtarget, DAG);
7439 if (BlendOp.getNode())
7443 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
7444 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
7446 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
7447 VT.is512BitVector()) {
7448 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
7449 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
7450 SmallVector<SDValue, 16> permclMask;
7451 for (unsigned i = 0; i != NumElems; ++i) {
7452 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
7455 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT,
7456 &permclMask[0], NumElems);
7458 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
7459 return DAG.getNode(X86ISD::VPERMV, dl, VT,
7460 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
7461 return DAG.getNode(X86ISD::VPERMV3, dl, VT,
7462 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1, V2);
7465 //===--------------------------------------------------------------------===//
7466 // Since no target specific shuffle was selected for this generic one,
7467 // lower it into other known shuffles. FIXME: this isn't true yet, but
7468 // this is the plan.
7471 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
7472 if (VT == MVT::v8i16) {
7473 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
7474 if (NewOp.getNode())
7478 if (VT == MVT::v16i8) {
7479 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
7480 if (NewOp.getNode())
7484 if (VT == MVT::v32i8) {
7485 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
7486 if (NewOp.getNode())
7490 // Handle all 128-bit wide vectors with 4 elements, and match them with
7491 // several different shuffle types.
7492 if (NumElems == 4 && VT.is128BitVector())
7493 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
7495 // Handle general 256-bit shuffles
7496 if (VT.is256BitVector())
7497 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
7502 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
7503 MVT VT = Op.getSimpleValueType();
7506 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
7509 if (VT.getSizeInBits() == 8) {
7510 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
7511 Op.getOperand(0), Op.getOperand(1));
7512 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
7513 DAG.getValueType(VT));
7514 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7517 if (VT.getSizeInBits() == 16) {
7518 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7519 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
7521 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
7522 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7523 DAG.getNode(ISD::BITCAST, dl,
7527 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
7528 Op.getOperand(0), Op.getOperand(1));
7529 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
7530 DAG.getValueType(VT));
7531 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7534 if (VT == MVT::f32) {
7535 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
7536 // the result back to FR32 register. It's only worth matching if the
7537 // result has a single use which is a store or a bitcast to i32. And in
7538 // the case of a store, it's not worth it if the index is a constant 0,
7539 // because a MOVSSmr can be used instead, which is smaller and faster.
7540 if (!Op.hasOneUse())
7542 SDNode *User = *Op.getNode()->use_begin();
7543 if ((User->getOpcode() != ISD::STORE ||
7544 (isa<ConstantSDNode>(Op.getOperand(1)) &&
7545 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
7546 (User->getOpcode() != ISD::BITCAST ||
7547 User->getValueType(0) != MVT::i32))
7549 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7550 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
7553 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
7556 if (VT == MVT::i32 || VT == MVT::i64) {
7557 // ExtractPS/pextrq works with constant index.
7558 if (isa<ConstantSDNode>(Op.getOperand(1)))
7565 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
7566 SelectionDAG &DAG) const {
7568 if (!isa<ConstantSDNode>(Op.getOperand(1)))
7571 SDValue Vec = Op.getOperand(0);
7572 MVT VecVT = Vec.getSimpleValueType();
7574 // If this is a 256-bit vector result, first extract the 128-bit vector and
7575 // then extract the element from the 128-bit vector.
7576 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
7577 SDValue Idx = Op.getOperand(1);
7578 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7580 // Get the 128-bit vector.
7581 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
7582 MVT EltVT = VecVT.getVectorElementType();
7584 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
7586 //if (IdxVal >= NumElems/2)
7587 // IdxVal -= NumElems/2;
7588 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
7589 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
7590 DAG.getConstant(IdxVal, MVT::i32));
7593 assert(VecVT.is128BitVector() && "Unexpected vector length");
7595 if (Subtarget->hasSSE41()) {
7596 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
7601 MVT VT = Op.getSimpleValueType();
7602 // TODO: handle v16i8.
7603 if (VT.getSizeInBits() == 16) {
7604 SDValue Vec = Op.getOperand(0);
7605 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7607 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
7608 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7609 DAG.getNode(ISD::BITCAST, dl,
7612 // Transform it so it match pextrw which produces a 32-bit result.
7613 MVT EltVT = MVT::i32;
7614 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
7615 Op.getOperand(0), Op.getOperand(1));
7616 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
7617 DAG.getValueType(VT));
7618 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7621 if (VT.getSizeInBits() == 32) {
7622 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7626 // SHUFPS the element to the lowest double word, then movss.
7627 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
7628 MVT VVT = Op.getOperand(0).getSimpleValueType();
7629 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
7630 DAG.getUNDEF(VVT), Mask);
7631 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
7632 DAG.getIntPtrConstant(0));
7635 if (VT.getSizeInBits() == 64) {
7636 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
7637 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
7638 // to match extract_elt for f64.
7639 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7643 // UNPCKHPD the element to the lowest double word, then movsd.
7644 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
7645 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
7646 int Mask[2] = { 1, -1 };
7647 MVT VVT = Op.getOperand(0).getSimpleValueType();
7648 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
7649 DAG.getUNDEF(VVT), Mask);
7650 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
7651 DAG.getIntPtrConstant(0));
7657 static SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
7658 MVT VT = Op.getSimpleValueType();
7659 MVT EltVT = VT.getVectorElementType();
7662 SDValue N0 = Op.getOperand(0);
7663 SDValue N1 = Op.getOperand(1);
7664 SDValue N2 = Op.getOperand(2);
7666 if (!VT.is128BitVector())
7669 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
7670 isa<ConstantSDNode>(N2)) {
7672 if (VT == MVT::v8i16)
7673 Opc = X86ISD::PINSRW;
7674 else if (VT == MVT::v16i8)
7675 Opc = X86ISD::PINSRB;
7677 Opc = X86ISD::PINSRB;
7679 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
7681 if (N1.getValueType() != MVT::i32)
7682 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
7683 if (N2.getValueType() != MVT::i32)
7684 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
7685 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
7688 if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
7689 // Bits [7:6] of the constant are the source select. This will always be
7690 // zero here. The DAG Combiner may combine an extract_elt index into these
7691 // bits. For example (insert (extract, 3), 2) could be matched by putting
7692 // the '3' into bits [7:6] of X86ISD::INSERTPS.
7693 // Bits [5:4] of the constant are the destination select. This is the
7694 // value of the incoming immediate.
7695 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
7696 // combine either bitwise AND or insert of float 0.0 to set these bits.
7697 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
7698 // Create this as a scalar to vector..
7699 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
7700 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
7703 if ((EltVT == MVT::i32 || EltVT == MVT::i64) && isa<ConstantSDNode>(N2)) {
7704 // PINSR* works with constant index.
7711 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
7712 MVT VT = Op.getSimpleValueType();
7713 MVT EltVT = VT.getVectorElementType();
7716 SDValue N0 = Op.getOperand(0);
7717 SDValue N1 = Op.getOperand(1);
7718 SDValue N2 = Op.getOperand(2);
7720 // If this is a 256-bit vector result, first extract the 128-bit vector,
7721 // insert the element into the extracted half and then place it back.
7722 if (VT.is256BitVector() || VT.is512BitVector()) {
7723 if (!isa<ConstantSDNode>(N2))
7726 // Get the desired 128-bit vector half.
7727 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue();
7728 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
7730 // Insert the element into the desired half.
7731 unsigned NumEltsIn128 = 128/EltVT.getSizeInBits();
7732 unsigned IdxIn128 = IdxVal - (IdxVal/NumEltsIn128) * NumEltsIn128;
7734 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
7735 DAG.getConstant(IdxIn128, MVT::i32));
7737 // Insert the changed part back to the 256-bit vector
7738 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
7741 if (Subtarget->hasSSE41())
7742 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
7744 if (EltVT == MVT::i8)
7747 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
7748 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
7749 // as its second argument.
7750 if (N1.getValueType() != MVT::i32)
7751 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
7752 if (N2.getValueType() != MVT::i32)
7753 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
7754 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
7759 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
7761 MVT OpVT = Op.getSimpleValueType();
7763 // If this is a 256-bit vector result, first insert into a 128-bit
7764 // vector and then insert into the 256-bit vector.
7765 if (!OpVT.is128BitVector()) {
7766 // Insert into a 128-bit vector.
7767 unsigned SizeFactor = OpVT.getSizeInBits()/128;
7768 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
7769 OpVT.getVectorNumElements() / SizeFactor);
7771 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
7773 // Insert the 128-bit vector.
7774 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
7777 if (OpVT == MVT::v1i64 &&
7778 Op.getOperand(0).getValueType() == MVT::i64)
7779 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
7781 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
7782 assert(OpVT.is128BitVector() && "Expected an SSE type!");
7783 return DAG.getNode(ISD::BITCAST, dl, OpVT,
7784 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
7787 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
7788 // a simple subregister reference or explicit instructions to grab
7789 // upper bits of a vector.
7790 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
7791 SelectionDAG &DAG) {
7793 SDValue In = Op.getOperand(0);
7794 SDValue Idx = Op.getOperand(1);
7795 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7796 MVT ResVT = Op.getSimpleValueType();
7797 MVT InVT = In.getSimpleValueType();
7799 if (Subtarget->hasFp256()) {
7800 if (ResVT.is128BitVector() &&
7801 (InVT.is256BitVector() || InVT.is512BitVector()) &&
7802 isa<ConstantSDNode>(Idx)) {
7803 return Extract128BitVector(In, IdxVal, DAG, dl);
7805 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
7806 isa<ConstantSDNode>(Idx)) {
7807 return Extract256BitVector(In, IdxVal, DAG, dl);
7813 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
7814 // simple superregister reference or explicit instructions to insert
7815 // the upper bits of a vector.
7816 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
7817 SelectionDAG &DAG) {
7818 if (Subtarget->hasFp256()) {
7819 SDLoc dl(Op.getNode());
7820 SDValue Vec = Op.getNode()->getOperand(0);
7821 SDValue SubVec = Op.getNode()->getOperand(1);
7822 SDValue Idx = Op.getNode()->getOperand(2);
7824 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() ||
7825 Op.getNode()->getSimpleValueType(0).is512BitVector()) &&
7826 SubVec.getNode()->getSimpleValueType(0).is128BitVector() &&
7827 isa<ConstantSDNode>(Idx)) {
7828 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7829 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
7832 if (Op.getNode()->getSimpleValueType(0).is512BitVector() &&
7833 SubVec.getNode()->getSimpleValueType(0).is256BitVector() &&
7834 isa<ConstantSDNode>(Idx)) {
7835 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7836 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
7842 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
7843 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
7844 // one of the above mentioned nodes. It has to be wrapped because otherwise
7845 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
7846 // be used to form addressing mode. These wrapped nodes will be selected
7849 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
7850 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
7852 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7854 unsigned char OpFlag = 0;
7855 unsigned WrapperKind = X86ISD::Wrapper;
7856 CodeModel::Model M = getTargetMachine().getCodeModel();
7858 if (Subtarget->isPICStyleRIPRel() &&
7859 (M == CodeModel::Small || M == CodeModel::Kernel))
7860 WrapperKind = X86ISD::WrapperRIP;
7861 else if (Subtarget->isPICStyleGOT())
7862 OpFlag = X86II::MO_GOTOFF;
7863 else if (Subtarget->isPICStyleStubPIC())
7864 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7866 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
7868 CP->getOffset(), OpFlag);
7870 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7871 // With PIC, the address is actually $g + Offset.
7873 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7874 DAG.getNode(X86ISD::GlobalBaseReg,
7875 SDLoc(), getPointerTy()),
7882 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
7883 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
7885 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7887 unsigned char OpFlag = 0;
7888 unsigned WrapperKind = X86ISD::Wrapper;
7889 CodeModel::Model M = getTargetMachine().getCodeModel();
7891 if (Subtarget->isPICStyleRIPRel() &&
7892 (M == CodeModel::Small || M == CodeModel::Kernel))
7893 WrapperKind = X86ISD::WrapperRIP;
7894 else if (Subtarget->isPICStyleGOT())
7895 OpFlag = X86II::MO_GOTOFF;
7896 else if (Subtarget->isPICStyleStubPIC())
7897 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7899 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
7902 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7904 // With PIC, the address is actually $g + Offset.
7906 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7907 DAG.getNode(X86ISD::GlobalBaseReg,
7908 SDLoc(), getPointerTy()),
7915 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
7916 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
7918 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7920 unsigned char OpFlag = 0;
7921 unsigned WrapperKind = X86ISD::Wrapper;
7922 CodeModel::Model M = getTargetMachine().getCodeModel();
7924 if (Subtarget->isPICStyleRIPRel() &&
7925 (M == CodeModel::Small || M == CodeModel::Kernel)) {
7926 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
7927 OpFlag = X86II::MO_GOTPCREL;
7928 WrapperKind = X86ISD::WrapperRIP;
7929 } else if (Subtarget->isPICStyleGOT()) {
7930 OpFlag = X86II::MO_GOT;
7931 } else if (Subtarget->isPICStyleStubPIC()) {
7932 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
7933 } else if (Subtarget->isPICStyleStubNoDynamic()) {
7934 OpFlag = X86II::MO_DARWIN_NONLAZY;
7937 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
7940 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7942 // With PIC, the address is actually $g + Offset.
7943 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
7944 !Subtarget->is64Bit()) {
7945 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7946 DAG.getNode(X86ISD::GlobalBaseReg,
7947 SDLoc(), getPointerTy()),
7951 // For symbols that require a load from a stub to get the address, emit the
7953 if (isGlobalStubReference(OpFlag))
7954 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
7955 MachinePointerInfo::getGOT(), false, false, false, 0);
7961 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
7962 // Create the TargetBlockAddressAddress node.
7963 unsigned char OpFlags =
7964 Subtarget->ClassifyBlockAddressReference();
7965 CodeModel::Model M = getTargetMachine().getCodeModel();
7966 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
7967 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
7969 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
7972 if (Subtarget->isPICStyleRIPRel() &&
7973 (M == CodeModel::Small || M == CodeModel::Kernel))
7974 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7976 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7978 // With PIC, the address is actually $g + Offset.
7979 if (isGlobalRelativeToPICBase(OpFlags)) {
7980 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7981 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7989 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
7990 int64_t Offset, SelectionDAG &DAG) const {
7991 // Create the TargetGlobalAddress node, folding in the constant
7992 // offset if it is legal.
7993 unsigned char OpFlags =
7994 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
7995 CodeModel::Model M = getTargetMachine().getCodeModel();
7997 if (OpFlags == X86II::MO_NO_FLAG &&
7998 X86::isOffsetSuitableForCodeModel(Offset, M)) {
7999 // A direct static reference to a global.
8000 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
8003 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
8006 if (Subtarget->isPICStyleRIPRel() &&
8007 (M == CodeModel::Small || M == CodeModel::Kernel))
8008 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
8010 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
8012 // With PIC, the address is actually $g + Offset.
8013 if (isGlobalRelativeToPICBase(OpFlags)) {
8014 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
8015 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
8019 // For globals that require a load from a stub to get the address, emit the
8021 if (isGlobalStubReference(OpFlags))
8022 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
8023 MachinePointerInfo::getGOT(), false, false, false, 0);
8025 // If there was a non-zero offset that we didn't fold, create an explicit
8028 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
8029 DAG.getConstant(Offset, getPointerTy()));
8035 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
8036 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
8037 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
8038 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
8042 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
8043 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
8044 unsigned char OperandFlags, bool LocalDynamic = false) {
8045 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
8046 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
8048 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
8049 GA->getValueType(0),
8053 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
8057 SDValue Ops[] = { Chain, TGA, *InFlag };
8058 Chain = DAG.getNode(CallType, dl, NodeTys, Ops, array_lengthof(Ops));
8060 SDValue Ops[] = { Chain, TGA };
8061 Chain = DAG.getNode(CallType, dl, NodeTys, Ops, array_lengthof(Ops));
8064 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
8065 MFI->setAdjustsStack(true);
8067 SDValue Flag = Chain.getValue(1);
8068 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
8071 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
8073 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
8076 SDLoc dl(GA); // ? function entry point might be better
8077 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
8078 DAG.getNode(X86ISD::GlobalBaseReg,
8079 SDLoc(), PtrVT), InFlag);
8080 InFlag = Chain.getValue(1);
8082 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
8085 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
8087 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
8089 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
8090 X86::RAX, X86II::MO_TLSGD);
8093 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
8099 // Get the start address of the TLS block for this module.
8100 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
8101 .getInfo<X86MachineFunctionInfo>();
8102 MFI->incNumLocalDynamicTLSAccesses();
8106 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT, X86::RAX,
8107 X86II::MO_TLSLD, /*LocalDynamic=*/true);
8110 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
8111 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
8112 InFlag = Chain.getValue(1);
8113 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
8114 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
8117 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
8121 unsigned char OperandFlags = X86II::MO_DTPOFF;
8122 unsigned WrapperKind = X86ISD::Wrapper;
8123 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
8124 GA->getValueType(0),
8125 GA->getOffset(), OperandFlags);
8126 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
8128 // Add x@dtpoff with the base.
8129 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
8132 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
8133 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
8134 const EVT PtrVT, TLSModel::Model model,
8135 bool is64Bit, bool isPIC) {
8138 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
8139 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
8140 is64Bit ? 257 : 256));
8142 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
8143 DAG.getIntPtrConstant(0),
8144 MachinePointerInfo(Ptr),
8145 false, false, false, 0);
8147 unsigned char OperandFlags = 0;
8148 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
8150 unsigned WrapperKind = X86ISD::Wrapper;
8151 if (model == TLSModel::LocalExec) {
8152 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
8153 } else if (model == TLSModel::InitialExec) {
8155 OperandFlags = X86II::MO_GOTTPOFF;
8156 WrapperKind = X86ISD::WrapperRIP;
8158 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
8161 llvm_unreachable("Unexpected model");
8164 // emit "addl x@ntpoff,%eax" (local exec)
8165 // or "addl x@indntpoff,%eax" (initial exec)
8166 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
8167 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
8168 GA->getValueType(0),
8169 GA->getOffset(), OperandFlags);
8170 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
8172 if (model == TLSModel::InitialExec) {
8173 if (isPIC && !is64Bit) {
8174 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
8175 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
8179 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
8180 MachinePointerInfo::getGOT(), false, false, false,
8184 // The address of the thread local variable is the add of the thread
8185 // pointer with the offset of the variable.
8186 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
8190 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
8192 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
8193 const GlobalValue *GV = GA->getGlobal();
8195 if (Subtarget->isTargetELF()) {
8196 TLSModel::Model model = getTargetMachine().getTLSModel(GV);
8199 case TLSModel::GeneralDynamic:
8200 if (Subtarget->is64Bit())
8201 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
8202 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
8203 case TLSModel::LocalDynamic:
8204 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
8205 Subtarget->is64Bit());
8206 case TLSModel::InitialExec:
8207 case TLSModel::LocalExec:
8208 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
8209 Subtarget->is64Bit(),
8210 getTargetMachine().getRelocationModel() == Reloc::PIC_);
8212 llvm_unreachable("Unknown TLS model.");
8215 if (Subtarget->isTargetDarwin()) {
8216 // Darwin only has one model of TLS. Lower to that.
8217 unsigned char OpFlag = 0;
8218 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
8219 X86ISD::WrapperRIP : X86ISD::Wrapper;
8221 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
8223 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
8224 !Subtarget->is64Bit();
8226 OpFlag = X86II::MO_TLVP_PIC_BASE;
8228 OpFlag = X86II::MO_TLVP;
8230 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
8231 GA->getValueType(0),
8232 GA->getOffset(), OpFlag);
8233 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
8235 // With PIC32, the address is actually $g + Offset.
8237 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8238 DAG.getNode(X86ISD::GlobalBaseReg,
8239 SDLoc(), getPointerTy()),
8242 // Lowering the machine isd will make sure everything is in the right
8244 SDValue Chain = DAG.getEntryNode();
8245 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
8246 SDValue Args[] = { Chain, Offset };
8247 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2);
8249 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
8250 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
8251 MFI->setAdjustsStack(true);
8253 // And our return value (tls address) is in the standard call return value
8255 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
8256 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
8260 if (Subtarget->isTargetWindows() || Subtarget->isTargetMingw()) {
8261 // Just use the implicit TLS architecture
8262 // Need to generate someting similar to:
8263 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
8265 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
8266 // mov rcx, qword [rdx+rcx*8]
8267 // mov eax, .tls$:tlsvar
8268 // [rax+rcx] contains the address
8269 // Windows 64bit: gs:0x58
8270 // Windows 32bit: fs:__tls_array
8272 // If GV is an alias then use the aliasee for determining
8273 // thread-localness.
8274 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
8275 GV = GA->resolveAliasedGlobal(false);
8277 SDValue Chain = DAG.getEntryNode();
8279 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
8280 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
8281 // use its literal value of 0x2C.
8282 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
8283 ? Type::getInt8PtrTy(*DAG.getContext(),
8285 : Type::getInt32PtrTy(*DAG.getContext(),
8288 SDValue TlsArray = Subtarget->is64Bit() ? DAG.getIntPtrConstant(0x58) :
8289 (Subtarget->isTargetMingw() ? DAG.getIntPtrConstant(0x2C) :
8290 DAG.getExternalSymbol("_tls_array", getPointerTy()));
8292 SDValue ThreadPointer = DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
8293 MachinePointerInfo(Ptr),
8294 false, false, false, 0);
8296 // Load the _tls_index variable
8297 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
8298 if (Subtarget->is64Bit())
8299 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
8300 IDX, MachinePointerInfo(), MVT::i32,
8303 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
8304 false, false, false, 0);
8306 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
8308 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
8310 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
8311 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
8312 false, false, false, 0);
8314 // Get the offset of start of .tls section
8315 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
8316 GA->getValueType(0),
8317 GA->getOffset(), X86II::MO_SECREL);
8318 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
8320 // The address of the thread local variable is the add of the thread
8321 // pointer with the offset of the variable.
8322 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
8325 llvm_unreachable("TLS not implemented for this target.");
8328 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
8329 /// and take a 2 x i32 value to shift plus a shift amount.
8330 SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const{
8331 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
8332 EVT VT = Op.getValueType();
8333 unsigned VTBits = VT.getSizeInBits();
8335 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
8336 SDValue ShOpLo = Op.getOperand(0);
8337 SDValue ShOpHi = Op.getOperand(1);
8338 SDValue ShAmt = Op.getOperand(2);
8339 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
8340 DAG.getConstant(VTBits - 1, MVT::i8))
8341 : DAG.getConstant(0, VT);
8344 if (Op.getOpcode() == ISD::SHL_PARTS) {
8345 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
8346 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
8348 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
8349 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
8352 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
8353 DAG.getConstant(VTBits, MVT::i8));
8354 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
8355 AndNode, DAG.getConstant(0, MVT::i8));
8358 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8359 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
8360 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
8362 if (Op.getOpcode() == ISD::SHL_PARTS) {
8363 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
8364 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
8366 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
8367 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
8370 SDValue Ops[2] = { Lo, Hi };
8371 return DAG.getMergeValues(Ops, array_lengthof(Ops), dl);
8374 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
8375 SelectionDAG &DAG) const {
8376 EVT SrcVT = Op.getOperand(0).getValueType();
8378 if (SrcVT.isVector())
8381 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
8382 "Unknown SINT_TO_FP to lower!");
8384 // These are really Legal; return the operand so the caller accepts it as
8386 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
8388 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
8389 Subtarget->is64Bit()) {
8394 unsigned Size = SrcVT.getSizeInBits()/8;
8395 MachineFunction &MF = DAG.getMachineFunction();
8396 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
8397 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8398 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
8400 MachinePointerInfo::getFixedStack(SSFI),
8402 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
8405 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
8407 SelectionDAG &DAG) const {
8411 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
8413 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
8415 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
8417 unsigned ByteSize = SrcVT.getSizeInBits()/8;
8419 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
8420 MachineMemOperand *MMO;
8422 int SSFI = FI->getIndex();
8424 DAG.getMachineFunction()
8425 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8426 MachineMemOperand::MOLoad, ByteSize, ByteSize);
8428 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
8429 StackSlot = StackSlot.getOperand(1);
8431 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
8432 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
8434 Tys, Ops, array_lengthof(Ops),
8438 Chain = Result.getValue(1);
8439 SDValue InFlag = Result.getValue(2);
8441 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
8442 // shouldn't be necessary except that RFP cannot be live across
8443 // multiple blocks. When stackifier is fixed, they can be uncoupled.
8444 MachineFunction &MF = DAG.getMachineFunction();
8445 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
8446 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
8447 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8448 Tys = DAG.getVTList(MVT::Other);
8450 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
8452 MachineMemOperand *MMO =
8453 DAG.getMachineFunction()
8454 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8455 MachineMemOperand::MOStore, SSFISize, SSFISize);
8457 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
8458 Ops, array_lengthof(Ops),
8459 Op.getValueType(), MMO);
8460 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
8461 MachinePointerInfo::getFixedStack(SSFI),
8462 false, false, false, 0);
8468 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
8469 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
8470 SelectionDAG &DAG) const {
8471 // This algorithm is not obvious. Here it is what we're trying to output:
8474 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
8475 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
8479 pshufd $0x4e, %xmm0, %xmm1
8485 LLVMContext *Context = DAG.getContext();
8487 // Build some magic constants.
8488 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
8489 Constant *C0 = ConstantDataVector::get(*Context, CV0);
8490 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
8492 SmallVector<Constant*,2> CV1;
8494 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
8495 APInt(64, 0x4330000000000000ULL))));
8497 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
8498 APInt(64, 0x4530000000000000ULL))));
8499 Constant *C1 = ConstantVector::get(CV1);
8500 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
8502 // Load the 64-bit value into an XMM register.
8503 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
8505 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
8506 MachinePointerInfo::getConstantPool(),
8507 false, false, false, 16);
8508 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
8509 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
8512 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
8513 MachinePointerInfo::getConstantPool(),
8514 false, false, false, 16);
8515 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
8516 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
8519 if (Subtarget->hasSSE3()) {
8520 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
8521 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
8523 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
8524 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
8526 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
8527 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
8531 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
8532 DAG.getIntPtrConstant(0));
8535 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
8536 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
8537 SelectionDAG &DAG) const {
8539 // FP constant to bias correct the final result.
8540 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
8543 // Load the 32-bit value into an XMM register.
8544 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
8547 // Zero out the upper parts of the register.
8548 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
8550 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
8551 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
8552 DAG.getIntPtrConstant(0));
8554 // Or the load with the bias.
8555 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
8556 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
8557 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
8559 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
8560 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
8561 MVT::v2f64, Bias)));
8562 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
8563 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
8564 DAG.getIntPtrConstant(0));
8566 // Subtract the bias.
8567 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
8569 // Handle final rounding.
8570 EVT DestVT = Op.getValueType();
8572 if (DestVT.bitsLT(MVT::f64))
8573 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
8574 DAG.getIntPtrConstant(0));
8575 if (DestVT.bitsGT(MVT::f64))
8576 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
8578 // Handle final rounding.
8582 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
8583 SelectionDAG &DAG) const {
8584 SDValue N0 = Op.getOperand(0);
8585 EVT SVT = N0.getValueType();
8588 assert((SVT == MVT::v4i8 || SVT == MVT::v4i16 ||
8589 SVT == MVT::v8i8 || SVT == MVT::v8i16) &&
8590 "Custom UINT_TO_FP is not supported!");
8592 EVT NVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
8593 SVT.getVectorNumElements());
8594 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
8595 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
8598 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
8599 SelectionDAG &DAG) const {
8600 SDValue N0 = Op.getOperand(0);
8603 if (Op.getValueType().isVector())
8604 return lowerUINT_TO_FP_vec(Op, DAG);
8606 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
8607 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
8608 // the optimization here.
8609 if (DAG.SignBitIsZero(N0))
8610 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
8612 EVT SrcVT = N0.getValueType();
8613 EVT DstVT = Op.getValueType();
8614 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
8615 return LowerUINT_TO_FP_i64(Op, DAG);
8616 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
8617 return LowerUINT_TO_FP_i32(Op, DAG);
8618 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
8621 // Make a 64-bit buffer, and use it to build an FILD.
8622 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
8623 if (SrcVT == MVT::i32) {
8624 SDValue WordOff = DAG.getConstant(4, getPointerTy());
8625 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
8626 getPointerTy(), StackSlot, WordOff);
8627 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
8628 StackSlot, MachinePointerInfo(),
8630 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
8631 OffsetSlot, MachinePointerInfo(),
8633 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
8637 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
8638 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
8639 StackSlot, MachinePointerInfo(),
8641 // For i64 source, we need to add the appropriate power of 2 if the input
8642 // was negative. This is the same as the optimization in
8643 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
8644 // we must be careful to do the computation in x87 extended precision, not
8645 // in SSE. (The generic code can't know it's OK to do this, or how to.)
8646 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
8647 MachineMemOperand *MMO =
8648 DAG.getMachineFunction()
8649 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8650 MachineMemOperand::MOLoad, 8, 8);
8652 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
8653 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
8654 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
8655 array_lengthof(Ops), MVT::i64, MMO);
8657 APInt FF(32, 0x5F800000ULL);
8659 // Check whether the sign bit is set.
8660 SDValue SignSet = DAG.getSetCC(dl,
8661 getSetCCResultType(*DAG.getContext(), MVT::i64),
8662 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
8665 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
8666 SDValue FudgePtr = DAG.getConstantPool(
8667 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
8670 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
8671 SDValue Zero = DAG.getIntPtrConstant(0);
8672 SDValue Four = DAG.getIntPtrConstant(4);
8673 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
8675 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
8677 // Load the value out, extending it from f32 to f80.
8678 // FIXME: Avoid the extend by constructing the right constant pool?
8679 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
8680 FudgePtr, MachinePointerInfo::getConstantPool(),
8681 MVT::f32, false, false, 4);
8682 // Extend everything to 80 bits to force it to be done on x87.
8683 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
8684 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
8687 std::pair<SDValue,SDValue>
8688 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
8689 bool IsSigned, bool IsReplace) const {
8692 EVT DstTy = Op.getValueType();
8694 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
8695 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
8699 assert(DstTy.getSimpleVT() <= MVT::i64 &&
8700 DstTy.getSimpleVT() >= MVT::i16 &&
8701 "Unknown FP_TO_INT to lower!");
8703 // These are really Legal.
8704 if (DstTy == MVT::i32 &&
8705 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
8706 return std::make_pair(SDValue(), SDValue());
8707 if (Subtarget->is64Bit() &&
8708 DstTy == MVT::i64 &&
8709 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
8710 return std::make_pair(SDValue(), SDValue());
8712 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
8713 // stack slot, or into the FTOL runtime function.
8714 MachineFunction &MF = DAG.getMachineFunction();
8715 unsigned MemSize = DstTy.getSizeInBits()/8;
8716 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
8717 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8720 if (!IsSigned && isIntegerTypeFTOL(DstTy))
8721 Opc = X86ISD::WIN_FTOL;
8723 switch (DstTy.getSimpleVT().SimpleTy) {
8724 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
8725 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
8726 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
8727 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
8730 SDValue Chain = DAG.getEntryNode();
8731 SDValue Value = Op.getOperand(0);
8732 EVT TheVT = Op.getOperand(0).getValueType();
8733 // FIXME This causes a redundant load/store if the SSE-class value is already
8734 // in memory, such as if it is on the callstack.
8735 if (isScalarFPTypeInSSEReg(TheVT)) {
8736 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
8737 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
8738 MachinePointerInfo::getFixedStack(SSFI),
8740 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
8742 Chain, StackSlot, DAG.getValueType(TheVT)
8745 MachineMemOperand *MMO =
8746 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8747 MachineMemOperand::MOLoad, MemSize, MemSize);
8748 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops,
8749 array_lengthof(Ops), DstTy, MMO);
8750 Chain = Value.getValue(1);
8751 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
8752 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8755 MachineMemOperand *MMO =
8756 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8757 MachineMemOperand::MOStore, MemSize, MemSize);
8759 if (Opc != X86ISD::WIN_FTOL) {
8760 // Build the FP_TO_INT*_IN_MEM
8761 SDValue Ops[] = { Chain, Value, StackSlot };
8762 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
8763 Ops, array_lengthof(Ops), DstTy,
8765 return std::make_pair(FIST, StackSlot);
8767 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
8768 DAG.getVTList(MVT::Other, MVT::Glue),
8770 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
8771 MVT::i32, ftol.getValue(1));
8772 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
8773 MVT::i32, eax.getValue(2));
8774 SDValue Ops[] = { eax, edx };
8775 SDValue pair = IsReplace
8776 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops, array_lengthof(Ops))
8777 : DAG.getMergeValues(Ops, array_lengthof(Ops), DL);
8778 return std::make_pair(pair, SDValue());
8782 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
8783 const X86Subtarget *Subtarget) {
8784 MVT VT = Op->getSimpleValueType(0);
8785 SDValue In = Op->getOperand(0);
8786 MVT InVT = In.getSimpleValueType();
8789 // Optimize vectors in AVX mode:
8792 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
8793 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
8794 // Concat upper and lower parts.
8797 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
8798 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
8799 // Concat upper and lower parts.
8802 if (((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
8803 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
8806 if (Subtarget->hasInt256())
8807 return DAG.getNode(X86ISD::VZEXT_MOVL, dl, VT, In);
8809 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
8810 SDValue Undef = DAG.getUNDEF(InVT);
8811 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
8812 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
8813 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
8815 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
8816 VT.getVectorNumElements()/2);
8818 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
8819 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
8821 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
8824 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
8825 SelectionDAG &DAG) {
8826 if (Subtarget->hasFp256()) {
8827 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
8835 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
8836 SelectionDAG &DAG) {
8838 MVT VT = Op.getSimpleValueType();
8839 SDValue In = Op.getOperand(0);
8840 MVT SVT = In.getSimpleValueType();
8842 if (Subtarget->hasFp256()) {
8843 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
8848 if (!VT.is256BitVector() || !SVT.is128BitVector() ||
8849 VT.getVectorNumElements() != SVT.getVectorNumElements())
8852 assert(Subtarget->hasFp256() && "256-bit vector is observed without AVX!");
8854 // AVX2 has better support of integer extending.
8855 if (Subtarget->hasInt256())
8856 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
8858 SDValue Lo = DAG.getNode(X86ISD::VZEXT, DL, MVT::v4i32, In);
8859 static const int Mask[] = {4, 5, 6, 7, -1, -1, -1, -1};
8860 SDValue Hi = DAG.getNode(X86ISD::VZEXT, DL, MVT::v4i32,
8861 DAG.getVectorShuffle(MVT::v8i16, DL, In,
8862 DAG.getUNDEF(MVT::v8i16),
8865 return DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v8i32, Lo, Hi);
8868 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
8870 MVT VT = Op.getSimpleValueType();
8871 SDValue In = Op.getOperand(0);
8872 MVT SVT = In.getSimpleValueType();
8874 if ((VT == MVT::v4i32) && (SVT == MVT::v4i64)) {
8875 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
8876 if (Subtarget->hasInt256()) {
8877 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
8878 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
8879 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
8881 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
8882 DAG.getIntPtrConstant(0));
8885 // On AVX, v4i64 -> v4i32 becomes a sequence that uses PSHUFD and MOVLHPS.
8886 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
8887 DAG.getIntPtrConstant(0));
8888 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
8889 DAG.getIntPtrConstant(2));
8891 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
8892 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
8895 static const int ShufMask1[] = {0, 2, 0, 0};
8896 SDValue Undef = DAG.getUNDEF(VT);
8897 OpLo = DAG.getVectorShuffle(VT, DL, OpLo, Undef, ShufMask1);
8898 OpHi = DAG.getVectorShuffle(VT, DL, OpHi, Undef, ShufMask1);
8900 // The MOVLHPS mask:
8901 static const int ShufMask2[] = {0, 1, 4, 5};
8902 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask2);
8905 if ((VT == MVT::v8i16) && (SVT == MVT::v8i32)) {
8906 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
8907 if (Subtarget->hasInt256()) {
8908 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
8910 SmallVector<SDValue,32> pshufbMask;
8911 for (unsigned i = 0; i < 2; ++i) {
8912 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
8913 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
8914 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
8915 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
8916 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
8917 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
8918 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
8919 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
8920 for (unsigned j = 0; j < 8; ++j)
8921 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
8923 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8,
8924 &pshufbMask[0], 32);
8925 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
8926 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
8928 static const int ShufMask[] = {0, 2, -1, -1};
8929 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
8931 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
8932 DAG.getIntPtrConstant(0));
8933 return DAG.getNode(ISD::BITCAST, DL, VT, In);
8936 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
8937 DAG.getIntPtrConstant(0));
8939 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
8940 DAG.getIntPtrConstant(4));
8942 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
8943 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
8946 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
8947 -1, -1, -1, -1, -1, -1, -1, -1};
8949 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
8950 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
8951 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
8953 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
8954 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
8956 // The MOVLHPS Mask:
8957 static const int ShufMask2[] = {0, 1, 4, 5};
8958 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
8959 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
8962 // Handle truncation of V256 to V128 using shuffles.
8963 if (!VT.is128BitVector() || !SVT.is256BitVector())
8966 assert(VT.getVectorNumElements() != SVT.getVectorNumElements() &&
8968 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
8970 unsigned NumElems = VT.getVectorNumElements();
8971 EVT NVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
8974 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
8975 // Prepare truncation shuffle mask
8976 for (unsigned i = 0; i != NumElems; ++i)
8978 SDValue V = DAG.getVectorShuffle(NVT, DL,
8979 DAG.getNode(ISD::BITCAST, DL, NVT, In),
8980 DAG.getUNDEF(NVT), &MaskVec[0]);
8981 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
8982 DAG.getIntPtrConstant(0));
8985 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
8986 SelectionDAG &DAG) const {
8987 MVT VT = Op.getSimpleValueType();
8988 if (VT.isVector()) {
8989 if (VT == MVT::v8i16)
8990 return DAG.getNode(ISD::TRUNCATE, SDLoc(Op), VT,
8991 DAG.getNode(ISD::FP_TO_SINT, SDLoc(Op),
8992 MVT::v8i32, Op.getOperand(0)));
8996 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
8997 /*IsSigned=*/ true, /*IsReplace=*/ false);
8998 SDValue FIST = Vals.first, StackSlot = Vals.second;
8999 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
9000 if (FIST.getNode() == 0) return Op;
9002 if (StackSlot.getNode())
9004 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
9005 FIST, StackSlot, MachinePointerInfo(),
9006 false, false, false, 0);
9008 // The node is the result.
9012 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
9013 SelectionDAG &DAG) const {
9014 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
9015 /*IsSigned=*/ false, /*IsReplace=*/ false);
9016 SDValue FIST = Vals.first, StackSlot = Vals.second;
9017 assert(FIST.getNode() && "Unexpected failure");
9019 if (StackSlot.getNode())
9021 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
9022 FIST, StackSlot, MachinePointerInfo(),
9023 false, false, false, 0);
9025 // The node is the result.
9029 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
9031 MVT VT = Op.getSimpleValueType();
9032 SDValue In = Op.getOperand(0);
9033 MVT SVT = In.getSimpleValueType();
9035 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
9037 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
9038 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
9039 In, DAG.getUNDEF(SVT)));
9042 SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) const {
9043 LLVMContext *Context = DAG.getContext();
9045 MVT VT = Op.getSimpleValueType();
9047 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
9048 if (VT.isVector()) {
9049 EltVT = VT.getVectorElementType();
9050 NumElts = VT.getVectorNumElements();
9053 if (EltVT == MVT::f64)
9054 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
9055 APInt(64, ~(1ULL << 63))));
9057 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEsingle,
9058 APInt(32, ~(1U << 31))));
9059 C = ConstantVector::getSplat(NumElts, C);
9060 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy());
9061 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
9062 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9063 MachinePointerInfo::getConstantPool(),
9064 false, false, false, Alignment);
9065 if (VT.isVector()) {
9066 MVT ANDVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
9067 return DAG.getNode(ISD::BITCAST, dl, VT,
9068 DAG.getNode(ISD::AND, dl, ANDVT,
9069 DAG.getNode(ISD::BITCAST, dl, ANDVT,
9071 DAG.getNode(ISD::BITCAST, dl, ANDVT, Mask)));
9073 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
9076 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
9077 LLVMContext *Context = DAG.getContext();
9079 MVT VT = Op.getSimpleValueType();
9081 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
9082 if (VT.isVector()) {
9083 EltVT = VT.getVectorElementType();
9084 NumElts = VT.getVectorNumElements();
9087 if (EltVT == MVT::f64)
9088 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
9089 APInt(64, 1ULL << 63)));
9091 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEsingle,
9092 APInt(32, 1U << 31)));
9093 C = ConstantVector::getSplat(NumElts, C);
9094 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy());
9095 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
9096 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9097 MachinePointerInfo::getConstantPool(),
9098 false, false, false, Alignment);
9099 if (VT.isVector()) {
9100 MVT XORVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
9101 return DAG.getNode(ISD::BITCAST, dl, VT,
9102 DAG.getNode(ISD::XOR, dl, XORVT,
9103 DAG.getNode(ISD::BITCAST, dl, XORVT,
9105 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask)));
9108 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
9111 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
9112 LLVMContext *Context = DAG.getContext();
9113 SDValue Op0 = Op.getOperand(0);
9114 SDValue Op1 = Op.getOperand(1);
9116 MVT VT = Op.getSimpleValueType();
9117 MVT SrcVT = Op1.getSimpleValueType();
9119 // If second operand is smaller, extend it first.
9120 if (SrcVT.bitsLT(VT)) {
9121 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
9124 // And if it is bigger, shrink it first.
9125 if (SrcVT.bitsGT(VT)) {
9126 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
9130 // At this point the operands and the result should have the same
9131 // type, and that won't be f80 since that is not custom lowered.
9133 // First get the sign bit of second operand.
9134 SmallVector<Constant*,4> CV;
9135 if (SrcVT == MVT::f64) {
9136 const fltSemantics &Sem = APFloat::IEEEdouble;
9137 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 1ULL << 63))));
9138 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
9140 const fltSemantics &Sem = APFloat::IEEEsingle;
9141 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 1U << 31))));
9142 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9143 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9144 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9146 Constant *C = ConstantVector::get(CV);
9147 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
9148 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
9149 MachinePointerInfo::getConstantPool(),
9150 false, false, false, 16);
9151 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
9153 // Shift sign bit right or left if the two operands have different types.
9154 if (SrcVT.bitsGT(VT)) {
9155 // Op0 is MVT::f32, Op1 is MVT::f64.
9156 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
9157 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
9158 DAG.getConstant(32, MVT::i32));
9159 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
9160 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
9161 DAG.getIntPtrConstant(0));
9164 // Clear first operand sign bit.
9166 if (VT == MVT::f64) {
9167 const fltSemantics &Sem = APFloat::IEEEdouble;
9168 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
9169 APInt(64, ~(1ULL << 63)))));
9170 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
9172 const fltSemantics &Sem = APFloat::IEEEsingle;
9173 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
9174 APInt(32, ~(1U << 31)))));
9175 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9176 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9177 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9179 C = ConstantVector::get(CV);
9180 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
9181 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9182 MachinePointerInfo::getConstantPool(),
9183 false, false, false, 16);
9184 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
9186 // Or the value with the sign bit.
9187 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
9190 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
9191 SDValue N0 = Op.getOperand(0);
9193 MVT VT = Op.getSimpleValueType();
9195 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
9196 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
9197 DAG.getConstant(1, VT));
9198 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
9201 // LowerVectorAllZeroTest - Check whether an OR'd tree is PTEST-able.
9203 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
9204 SelectionDAG &DAG) {
9205 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
9207 if (!Subtarget->hasSSE41())
9210 if (!Op->hasOneUse())
9213 SDNode *N = Op.getNode();
9216 SmallVector<SDValue, 8> Opnds;
9217 DenseMap<SDValue, unsigned> VecInMap;
9218 EVT VT = MVT::Other;
9220 // Recognize a special case where a vector is casted into wide integer to
9222 Opnds.push_back(N->getOperand(0));
9223 Opnds.push_back(N->getOperand(1));
9225 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
9226 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
9227 // BFS traverse all OR'd operands.
9228 if (I->getOpcode() == ISD::OR) {
9229 Opnds.push_back(I->getOperand(0));
9230 Opnds.push_back(I->getOperand(1));
9231 // Re-evaluate the number of nodes to be traversed.
9232 e += 2; // 2 more nodes (LHS and RHS) are pushed.
9236 // Quit if a non-EXTRACT_VECTOR_ELT
9237 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
9240 // Quit if without a constant index.
9241 SDValue Idx = I->getOperand(1);
9242 if (!isa<ConstantSDNode>(Idx))
9245 SDValue ExtractedFromVec = I->getOperand(0);
9246 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
9247 if (M == VecInMap.end()) {
9248 VT = ExtractedFromVec.getValueType();
9249 // Quit if not 128/256-bit vector.
9250 if (!VT.is128BitVector() && !VT.is256BitVector())
9252 // Quit if not the same type.
9253 if (VecInMap.begin() != VecInMap.end() &&
9254 VT != VecInMap.begin()->first.getValueType())
9256 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
9258 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
9261 assert((VT.is128BitVector() || VT.is256BitVector()) &&
9262 "Not extracted from 128-/256-bit vector.");
9264 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
9265 SmallVector<SDValue, 8> VecIns;
9267 for (DenseMap<SDValue, unsigned>::const_iterator
9268 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
9269 // Quit if not all elements are used.
9270 if (I->second != FullMask)
9272 VecIns.push_back(I->first);
9275 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
9277 // Cast all vectors into TestVT for PTEST.
9278 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
9279 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
9281 // If more than one full vectors are evaluated, OR them first before PTEST.
9282 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
9283 // Each iteration will OR 2 nodes and append the result until there is only
9284 // 1 node left, i.e. the final OR'd value of all vectors.
9285 SDValue LHS = VecIns[Slot];
9286 SDValue RHS = VecIns[Slot + 1];
9287 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
9290 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
9291 VecIns.back(), VecIns.back());
9294 /// Emit nodes that will be selected as "test Op0,Op0", or something
9296 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
9297 SelectionDAG &DAG) const {
9300 // CF and OF aren't always set the way we want. Determine which
9301 // of these we need.
9302 bool NeedCF = false;
9303 bool NeedOF = false;
9306 case X86::COND_A: case X86::COND_AE:
9307 case X86::COND_B: case X86::COND_BE:
9310 case X86::COND_G: case X86::COND_GE:
9311 case X86::COND_L: case X86::COND_LE:
9312 case X86::COND_O: case X86::COND_NO:
9317 // See if we can use the EFLAGS value from the operand instead of
9318 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
9319 // we prove that the arithmetic won't overflow, we can't use OF or CF.
9320 if (Op.getResNo() != 0 || NeedOF || NeedCF)
9321 // Emit a CMP with 0, which is the TEST pattern.
9322 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
9323 DAG.getConstant(0, Op.getValueType()));
9325 unsigned Opcode = 0;
9326 unsigned NumOperands = 0;
9328 // Truncate operations may prevent the merge of the SETCC instruction
9329 // and the arithmetic intruction before it. Attempt to truncate the operands
9330 // of the arithmetic instruction and use a reduced bit-width instruction.
9331 bool NeedTruncation = false;
9332 SDValue ArithOp = Op;
9333 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
9334 SDValue Arith = Op->getOperand(0);
9335 // Both the trunc and the arithmetic op need to have one user each.
9336 if (Arith->hasOneUse())
9337 switch (Arith.getOpcode()) {
9344 NeedTruncation = true;
9350 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
9351 // which may be the result of a CAST. We use the variable 'Op', which is the
9352 // non-casted variable when we check for possible users.
9353 switch (ArithOp.getOpcode()) {
9355 // Due to an isel shortcoming, be conservative if this add is likely to be
9356 // selected as part of a load-modify-store instruction. When the root node
9357 // in a match is a store, isel doesn't know how to remap non-chain non-flag
9358 // uses of other nodes in the match, such as the ADD in this case. This
9359 // leads to the ADD being left around and reselected, with the result being
9360 // two adds in the output. Alas, even if none our users are stores, that
9361 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
9362 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
9363 // climbing the DAG back to the root, and it doesn't seem to be worth the
9365 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
9366 UE = Op.getNode()->use_end(); UI != UE; ++UI)
9367 if (UI->getOpcode() != ISD::CopyToReg &&
9368 UI->getOpcode() != ISD::SETCC &&
9369 UI->getOpcode() != ISD::STORE)
9372 if (ConstantSDNode *C =
9373 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
9374 // An add of one will be selected as an INC.
9375 if (C->getAPIntValue() == 1) {
9376 Opcode = X86ISD::INC;
9381 // An add of negative one (subtract of one) will be selected as a DEC.
9382 if (C->getAPIntValue().isAllOnesValue()) {
9383 Opcode = X86ISD::DEC;
9389 // Otherwise use a regular EFLAGS-setting add.
9390 Opcode = X86ISD::ADD;
9394 // If the primary and result isn't used, don't bother using X86ISD::AND,
9395 // because a TEST instruction will be better.
9396 bool NonFlagUse = false;
9397 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
9398 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
9400 unsigned UOpNo = UI.getOperandNo();
9401 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
9402 // Look pass truncate.
9403 UOpNo = User->use_begin().getOperandNo();
9404 User = *User->use_begin();
9407 if (User->getOpcode() != ISD::BRCOND &&
9408 User->getOpcode() != ISD::SETCC &&
9409 !(User->getOpcode() == ISD::SELECT && UOpNo == 0)) {
9422 // Due to the ISEL shortcoming noted above, be conservative if this op is
9423 // likely to be selected as part of a load-modify-store instruction.
9424 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
9425 UE = Op.getNode()->use_end(); UI != UE; ++UI)
9426 if (UI->getOpcode() == ISD::STORE)
9429 // Otherwise use a regular EFLAGS-setting instruction.
9430 switch (ArithOp.getOpcode()) {
9431 default: llvm_unreachable("unexpected operator!");
9432 case ISD::SUB: Opcode = X86ISD::SUB; break;
9433 case ISD::XOR: Opcode = X86ISD::XOR; break;
9434 case ISD::AND: Opcode = X86ISD::AND; break;
9436 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
9437 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
9438 if (EFLAGS.getNode())
9441 Opcode = X86ISD::OR;
9455 return SDValue(Op.getNode(), 1);
9461 // If we found that truncation is beneficial, perform the truncation and
9463 if (NeedTruncation) {
9464 EVT VT = Op.getValueType();
9465 SDValue WideVal = Op->getOperand(0);
9466 EVT WideVT = WideVal.getValueType();
9467 unsigned ConvertedOp = 0;
9468 // Use a target machine opcode to prevent further DAGCombine
9469 // optimizations that may separate the arithmetic operations
9470 // from the setcc node.
9471 switch (WideVal.getOpcode()) {
9473 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
9474 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
9475 case ISD::AND: ConvertedOp = X86ISD::AND; break;
9476 case ISD::OR: ConvertedOp = X86ISD::OR; break;
9477 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
9481 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9482 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
9483 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
9484 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
9485 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
9491 // Emit a CMP with 0, which is the TEST pattern.
9492 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
9493 DAG.getConstant(0, Op.getValueType()));
9495 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
9496 SmallVector<SDValue, 4> Ops;
9497 for (unsigned i = 0; i != NumOperands; ++i)
9498 Ops.push_back(Op.getOperand(i));
9500 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
9501 DAG.ReplaceAllUsesWith(Op, New);
9502 return SDValue(New.getNode(), 1);
9505 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
9507 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
9508 SelectionDAG &DAG) const {
9509 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
9510 if (C->getAPIntValue() == 0)
9511 return EmitTest(Op0, X86CC, DAG);
9514 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
9515 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
9516 // Use SUB instead of CMP to enable CSE between SUB and CMP.
9517 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
9518 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
9520 return SDValue(Sub.getNode(), 1);
9522 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
9525 /// Convert a comparison if required by the subtarget.
9526 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
9527 SelectionDAG &DAG) const {
9528 // If the subtarget does not support the FUCOMI instruction, floating-point
9529 // comparisons have to be converted.
9530 if (Subtarget->hasCMov() ||
9531 Cmp.getOpcode() != X86ISD::CMP ||
9532 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
9533 !Cmp.getOperand(1).getValueType().isFloatingPoint())
9536 // The instruction selector will select an FUCOM instruction instead of
9537 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
9538 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
9539 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
9541 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
9542 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
9543 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
9544 DAG.getConstant(8, MVT::i8));
9545 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
9546 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
9549 static bool isAllOnes(SDValue V) {
9550 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
9551 return C && C->isAllOnesValue();
9554 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
9555 /// if it's possible.
9556 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
9557 SDLoc dl, SelectionDAG &DAG) const {
9558 SDValue Op0 = And.getOperand(0);
9559 SDValue Op1 = And.getOperand(1);
9560 if (Op0.getOpcode() == ISD::TRUNCATE)
9561 Op0 = Op0.getOperand(0);
9562 if (Op1.getOpcode() == ISD::TRUNCATE)
9563 Op1 = Op1.getOperand(0);
9566 if (Op1.getOpcode() == ISD::SHL)
9567 std::swap(Op0, Op1);
9568 if (Op0.getOpcode() == ISD::SHL) {
9569 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
9570 if (And00C->getZExtValue() == 1) {
9571 // If we looked past a truncate, check that it's only truncating away
9573 unsigned BitWidth = Op0.getValueSizeInBits();
9574 unsigned AndBitWidth = And.getValueSizeInBits();
9575 if (BitWidth > AndBitWidth) {
9577 DAG.ComputeMaskedBits(Op0, Zeros, Ones);
9578 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
9582 RHS = Op0.getOperand(1);
9584 } else if (Op1.getOpcode() == ISD::Constant) {
9585 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
9586 uint64_t AndRHSVal = AndRHS->getZExtValue();
9587 SDValue AndLHS = Op0;
9589 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
9590 LHS = AndLHS.getOperand(0);
9591 RHS = AndLHS.getOperand(1);
9594 // Use BT if the immediate can't be encoded in a TEST instruction.
9595 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
9597 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
9601 if (LHS.getNode()) {
9602 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
9603 // instruction. Since the shift amount is in-range-or-undefined, we know
9604 // that doing a bittest on the i32 value is ok. We extend to i32 because
9605 // the encoding for the i16 version is larger than the i32 version.
9606 // Also promote i16 to i32 for performance / code size reason.
9607 if (LHS.getValueType() == MVT::i8 ||
9608 LHS.getValueType() == MVT::i16)
9609 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
9611 // If the operand types disagree, extend the shift amount to match. Since
9612 // BT ignores high bits (like shifts) we can use anyextend.
9613 if (LHS.getValueType() != RHS.getValueType())
9614 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
9616 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
9617 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
9618 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9619 DAG.getConstant(Cond, MVT::i8), BT);
9625 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
9627 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
9632 // SSE Condition code mapping:
9641 switch (SetCCOpcode) {
9642 default: llvm_unreachable("Unexpected SETCC condition");
9644 case ISD::SETEQ: SSECC = 0; break;
9646 case ISD::SETGT: Swap = true; // Fallthrough
9648 case ISD::SETOLT: SSECC = 1; break;
9650 case ISD::SETGE: Swap = true; // Fallthrough
9652 case ISD::SETOLE: SSECC = 2; break;
9653 case ISD::SETUO: SSECC = 3; break;
9655 case ISD::SETNE: SSECC = 4; break;
9656 case ISD::SETULE: Swap = true; // Fallthrough
9657 case ISD::SETUGE: SSECC = 5; break;
9658 case ISD::SETULT: Swap = true; // Fallthrough
9659 case ISD::SETUGT: SSECC = 6; break;
9660 case ISD::SETO: SSECC = 7; break;
9662 case ISD::SETONE: SSECC = 8; break;
9665 std::swap(Op0, Op1);
9670 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
9671 // ones, and then concatenate the result back.
9672 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
9673 MVT VT = Op.getSimpleValueType();
9675 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
9676 "Unsupported value type for operation");
9678 unsigned NumElems = VT.getVectorNumElements();
9680 SDValue CC = Op.getOperand(2);
9682 // Extract the LHS vectors
9683 SDValue LHS = Op.getOperand(0);
9684 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
9685 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
9687 // Extract the RHS vectors
9688 SDValue RHS = Op.getOperand(1);
9689 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
9690 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
9692 // Issue the operation on the smaller types and concatenate the result back
9693 MVT EltVT = VT.getVectorElementType();
9694 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
9695 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
9696 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
9697 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
9700 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG) {
9702 SDValue Op0 = Op.getOperand(0);
9703 SDValue Op1 = Op.getOperand(1);
9704 SDValue CC = Op.getOperand(2);
9705 MVT VT = Op.getSimpleValueType();
9707 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 32 &&
9708 Op.getValueType().getScalarType() == MVT::i1 &&
9709 "Cannot set masked compare for this operation");
9711 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
9714 bool Unsigned = false;
9716 switch (SetCCOpcode) {
9717 default: llvm_unreachable("Unexpected SETCC condition");
9718 case ISD::SETNE: SSECC = 4; break;
9719 case ISD::SETEQ: SSECC = 0; break;
9720 case ISD::SETUGT: Unsigned = true;
9721 case ISD::SETGT: SSECC = 6; break; // NLE
9722 case ISD::SETULT: Unsigned = true;
9723 case ISD::SETLT: SSECC = 1; break;
9724 case ISD::SETUGE: Unsigned = true;
9725 case ISD::SETGE: SSECC = 5; break; // NLT
9726 case ISD::SETULE: Unsigned = true;
9727 case ISD::SETLE: SSECC = 2; break;
9729 unsigned Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
9730 return DAG.getNode(Opc, dl, VT, Op0, Op1,
9731 DAG.getConstant(SSECC, MVT::i8));
9735 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
9736 SelectionDAG &DAG) {
9738 SDValue Op0 = Op.getOperand(0);
9739 SDValue Op1 = Op.getOperand(1);
9740 SDValue CC = Op.getOperand(2);
9741 MVT VT = Op.getSimpleValueType();
9742 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
9743 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
9748 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
9749 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
9752 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
9753 unsigned Opc = X86ISD::CMPP;
9754 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
9755 assert(VT.getVectorNumElements() <= 16);
9758 // In the two special cases we can't handle, emit two comparisons.
9761 unsigned CombineOpc;
9762 if (SetCCOpcode == ISD::SETUEQ) {
9763 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
9765 assert(SetCCOpcode == ISD::SETONE);
9766 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
9769 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
9770 DAG.getConstant(CC0, MVT::i8));
9771 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
9772 DAG.getConstant(CC1, MVT::i8));
9773 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
9775 // Handle all other FP comparisons here.
9776 return DAG.getNode(Opc, dl, VT, Op0, Op1,
9777 DAG.getConstant(SSECC, MVT::i8));
9780 // Break 256-bit integer vector compare into smaller ones.
9781 if (VT.is256BitVector() && !Subtarget->hasInt256())
9782 return Lower256IntVSETCC(Op, DAG);
9784 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
9785 EVT OpVT = Op1.getValueType();
9786 if (Subtarget->hasAVX512()) {
9787 if (Op1.getValueType().is512BitVector() ||
9788 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
9789 return LowerIntVSETCC_AVX512(Op, DAG);
9791 // In AVX-512 architecture setcc returns mask with i1 elements,
9792 // But there is no compare instruction for i8 and i16 elements.
9793 // We are not talking about 512-bit operands in this case, these
9794 // types are illegal.
9796 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
9797 OpVT.getVectorElementType().getSizeInBits() >= 8))
9798 return DAG.getNode(ISD::TRUNCATE, dl, VT,
9799 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
9802 // We are handling one of the integer comparisons here. Since SSE only has
9803 // GT and EQ comparisons for integer, swapping operands and multiple
9804 // operations may be required for some comparisons.
9806 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
9808 switch (SetCCOpcode) {
9809 default: llvm_unreachable("Unexpected SETCC condition");
9810 case ISD::SETNE: Invert = true;
9811 case ISD::SETEQ: Opc = MaskResult? X86ISD::PCMPEQM: X86ISD::PCMPEQ; break;
9812 case ISD::SETLT: Swap = true;
9813 case ISD::SETGT: Opc = MaskResult? X86ISD::PCMPGTM: X86ISD::PCMPGT; break;
9814 case ISD::SETGE: Swap = true;
9815 case ISD::SETLE: Opc = MaskResult? X86ISD::PCMPGTM: X86ISD::PCMPGT;
9816 Invert = true; break;
9817 case ISD::SETULT: Swap = true;
9818 case ISD::SETUGT: Opc = MaskResult? X86ISD::PCMPGTM: X86ISD::PCMPGT;
9819 FlipSigns = true; break;
9820 case ISD::SETUGE: Swap = true;
9821 case ISD::SETULE: Opc = MaskResult? X86ISD::PCMPGTM: X86ISD::PCMPGT;
9822 FlipSigns = true; Invert = true; break;
9825 // Special case: Use min/max operations for SETULE/SETUGE
9826 MVT VET = VT.getVectorElementType();
9828 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
9829 || (Subtarget->hasSSE2() && (VET == MVT::i8));
9832 switch (SetCCOpcode) {
9834 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
9835 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
9838 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
9842 std::swap(Op0, Op1);
9844 // Check that the operation in question is available (most are plain SSE2,
9845 // but PCMPGTQ and PCMPEQQ have different requirements).
9846 if (VT == MVT::v2i64) {
9847 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
9848 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
9850 // First cast everything to the right type.
9851 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
9852 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
9854 // Since SSE has no unsigned integer comparisons, we need to flip the sign
9855 // bits of the inputs before performing those operations. The lower
9856 // compare is always unsigned.
9859 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
9861 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
9862 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
9863 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
9864 Sign, Zero, Sign, Zero);
9866 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
9867 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
9869 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
9870 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
9871 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
9873 // Create masks for only the low parts/high parts of the 64 bit integers.
9874 static const int MaskHi[] = { 1, 1, 3, 3 };
9875 static const int MaskLo[] = { 0, 0, 2, 2 };
9876 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
9877 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
9878 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
9880 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
9881 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
9884 Result = DAG.getNOT(dl, Result, MVT::v4i32);
9886 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
9889 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
9890 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
9891 // pcmpeqd + pshufd + pand.
9892 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
9894 // First cast everything to the right type.
9895 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
9896 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
9899 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
9901 // Make sure the lower and upper halves are both all-ones.
9902 static const int Mask[] = { 1, 0, 3, 2 };
9903 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
9904 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
9907 Result = DAG.getNOT(dl, Result, MVT::v4i32);
9909 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
9913 // Since SSE has no unsigned integer comparisons, we need to flip the sign
9914 // bits of the inputs before performing those operations.
9916 EVT EltVT = VT.getVectorElementType();
9917 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
9918 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
9919 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
9922 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
9924 // If the logical-not of the result is required, perform that now.
9926 Result = DAG.getNOT(dl, Result, VT);
9929 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
9934 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
9936 MVT VT = Op.getSimpleValueType();
9938 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
9940 assert(VT == MVT::i8 && "SetCC type must be 8-bit integer");
9941 SDValue Op0 = Op.getOperand(0);
9942 SDValue Op1 = Op.getOperand(1);
9944 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
9946 // Optimize to BT if possible.
9947 // Lower (X & (1 << N)) == 0 to BT(X, N).
9948 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
9949 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
9950 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
9951 Op1.getOpcode() == ISD::Constant &&
9952 cast<ConstantSDNode>(Op1)->isNullValue() &&
9953 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
9954 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
9955 if (NewSetCC.getNode())
9959 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
9961 if (Op1.getOpcode() == ISD::Constant &&
9962 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
9963 cast<ConstantSDNode>(Op1)->isNullValue()) &&
9964 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
9966 // If the input is a setcc, then reuse the input setcc or use a new one with
9967 // the inverted condition.
9968 if (Op0.getOpcode() == X86ISD::SETCC) {
9969 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
9970 bool Invert = (CC == ISD::SETNE) ^
9971 cast<ConstantSDNode>(Op1)->isNullValue();
9972 if (!Invert) return Op0;
9974 CCode = X86::GetOppositeBranchCondition(CCode);
9975 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9976 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
9980 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
9981 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
9982 if (X86CC == X86::COND_INVALID)
9985 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG);
9986 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
9987 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9988 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
9991 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
9992 static bool isX86LogicalCmp(SDValue Op) {
9993 unsigned Opc = Op.getNode()->getOpcode();
9994 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
9995 Opc == X86ISD::SAHF)
9997 if (Op.getResNo() == 1 &&
9998 (Opc == X86ISD::ADD ||
9999 Opc == X86ISD::SUB ||
10000 Opc == X86ISD::ADC ||
10001 Opc == X86ISD::SBB ||
10002 Opc == X86ISD::SMUL ||
10003 Opc == X86ISD::UMUL ||
10004 Opc == X86ISD::INC ||
10005 Opc == X86ISD::DEC ||
10006 Opc == X86ISD::OR ||
10007 Opc == X86ISD::XOR ||
10008 Opc == X86ISD::AND))
10011 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
10017 static bool isZero(SDValue V) {
10018 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
10019 return C && C->isNullValue();
10022 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
10023 if (V.getOpcode() != ISD::TRUNCATE)
10026 SDValue VOp0 = V.getOperand(0);
10027 unsigned InBits = VOp0.getValueSizeInBits();
10028 unsigned Bits = V.getValueSizeInBits();
10029 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
10032 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
10033 bool addTest = true;
10034 SDValue Cond = Op.getOperand(0);
10035 SDValue Op1 = Op.getOperand(1);
10036 SDValue Op2 = Op.getOperand(2);
10038 EVT VT = Op1.getValueType();
10041 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
10042 // are available. Otherwise fp cmovs get lowered into a less efficient branch
10043 // sequence later on.
10044 if (Cond.getOpcode() == ISD::SETCC &&
10045 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
10046 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
10047 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
10048 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
10049 int SSECC = translateX86FSETCC(
10050 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
10053 unsigned Opcode = VT == MVT::f32 ? X86ISD::FSETCCss : X86ISD::FSETCCsd;
10054 SDValue Cmp = DAG.getNode(Opcode, DL, VT, CondOp0, CondOp1,
10055 DAG.getConstant(SSECC, MVT::i8));
10056 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
10057 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
10058 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
10062 if (Cond.getOpcode() == ISD::SETCC) {
10063 SDValue NewCond = LowerSETCC(Cond, DAG);
10064 if (NewCond.getNode())
10068 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
10069 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
10070 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
10071 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
10072 if (Cond.getOpcode() == X86ISD::SETCC &&
10073 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
10074 isZero(Cond.getOperand(1).getOperand(1))) {
10075 SDValue Cmp = Cond.getOperand(1);
10077 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
10079 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
10080 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
10081 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
10083 SDValue CmpOp0 = Cmp.getOperand(0);
10084 // Apply further optimizations for special cases
10085 // (select (x != 0), -1, 0) -> neg & sbb
10086 // (select (x == 0), 0, -1) -> neg & sbb
10087 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
10088 if (YC->isNullValue() &&
10089 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
10090 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
10091 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
10092 DAG.getConstant(0, CmpOp0.getValueType()),
10094 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
10095 DAG.getConstant(X86::COND_B, MVT::i8),
10096 SDValue(Neg.getNode(), 1));
10100 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
10101 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
10102 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
10104 SDValue Res = // Res = 0 or -1.
10105 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
10106 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
10108 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
10109 Res = DAG.getNOT(DL, Res, Res.getValueType());
10111 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
10112 if (N2C == 0 || !N2C->isNullValue())
10113 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
10118 // Look past (and (setcc_carry (cmp ...)), 1).
10119 if (Cond.getOpcode() == ISD::AND &&
10120 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
10121 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
10122 if (C && C->getAPIntValue() == 1)
10123 Cond = Cond.getOperand(0);
10126 // If condition flag is set by a X86ISD::CMP, then use it as the condition
10127 // setting operand in place of the X86ISD::SETCC.
10128 unsigned CondOpcode = Cond.getOpcode();
10129 if (CondOpcode == X86ISD::SETCC ||
10130 CondOpcode == X86ISD::SETCC_CARRY) {
10131 CC = Cond.getOperand(0);
10133 SDValue Cmp = Cond.getOperand(1);
10134 unsigned Opc = Cmp.getOpcode();
10135 MVT VT = Op.getSimpleValueType();
10137 bool IllegalFPCMov = false;
10138 if (VT.isFloatingPoint() && !VT.isVector() &&
10139 !isScalarFPTypeInSSEReg(VT)) // FPStack?
10140 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
10142 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
10143 Opc == X86ISD::BT) { // FIXME
10147 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
10148 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
10149 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
10150 Cond.getOperand(0).getValueType() != MVT::i8)) {
10151 SDValue LHS = Cond.getOperand(0);
10152 SDValue RHS = Cond.getOperand(1);
10153 unsigned X86Opcode;
10156 switch (CondOpcode) {
10157 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
10158 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
10159 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
10160 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
10161 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
10162 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
10163 default: llvm_unreachable("unexpected overflowing operator");
10165 if (CondOpcode == ISD::UMULO)
10166 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
10169 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
10171 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
10173 if (CondOpcode == ISD::UMULO)
10174 Cond = X86Op.getValue(2);
10176 Cond = X86Op.getValue(1);
10178 CC = DAG.getConstant(X86Cond, MVT::i8);
10183 // Look pass the truncate if the high bits are known zero.
10184 if (isTruncWithZeroHighBitsInput(Cond, DAG))
10185 Cond = Cond.getOperand(0);
10187 // We know the result of AND is compared against zero. Try to match
10189 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
10190 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
10191 if (NewSetCC.getNode()) {
10192 CC = NewSetCC.getOperand(0);
10193 Cond = NewSetCC.getOperand(1);
10200 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10201 Cond = EmitTest(Cond, X86::COND_NE, DAG);
10204 // a < b ? -1 : 0 -> RES = ~setcc_carry
10205 // a < b ? 0 : -1 -> RES = setcc_carry
10206 // a >= b ? -1 : 0 -> RES = setcc_carry
10207 // a >= b ? 0 : -1 -> RES = ~setcc_carry
10208 if (Cond.getOpcode() == X86ISD::SUB) {
10209 Cond = ConvertCmpIfNecessary(Cond, DAG);
10210 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
10212 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
10213 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
10214 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
10215 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
10216 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
10217 return DAG.getNOT(DL, Res, Res.getValueType());
10222 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
10223 // widen the cmov and push the truncate through. This avoids introducing a new
10224 // branch during isel and doesn't add any extensions.
10225 if (Op.getValueType() == MVT::i8 &&
10226 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
10227 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
10228 if (T1.getValueType() == T2.getValueType() &&
10229 // Blacklist CopyFromReg to avoid partial register stalls.
10230 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
10231 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
10232 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
10233 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
10237 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
10238 // condition is true.
10239 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
10240 SDValue Ops[] = { Op2, Op1, CC, Cond };
10241 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
10244 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, SelectionDAG &DAG) {
10245 MVT VT = Op->getSimpleValueType(0);
10246 SDValue In = Op->getOperand(0);
10247 MVT InVT = In.getSimpleValueType();
10250 if (InVT.getVectorElementType().getSizeInBits() >=8 &&
10251 VT.getVectorElementType().getSizeInBits() >= 32)
10252 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
10254 if (InVT.getVectorElementType() == MVT::i1) {
10255 unsigned int NumElts = InVT.getVectorNumElements();
10256 assert ((NumElts == 8 || NumElts == 16) &&
10257 "Unsupported SIGN_EXTEND operation");
10258 if (VT.getVectorElementType().getSizeInBits() >= 32) {
10260 ConstantInt::get(*DAG.getContext(),
10261 (NumElts == 8)? APInt(64, ~0ULL): APInt(32, ~0U));
10262 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
10263 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
10264 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
10265 SDValue Ld = DAG.getLoad(VT.getScalarType(), dl, DAG.getEntryNode(), CP,
10266 MachinePointerInfo::getConstantPool(),
10267 false, false, false, Alignment);
10268 return DAG.getNode(X86ISD::VBROADCASTM, dl, VT, In, Ld);
10274 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
10275 SelectionDAG &DAG) {
10276 MVT VT = Op->getSimpleValueType(0);
10277 SDValue In = Op->getOperand(0);
10278 MVT InVT = In.getSimpleValueType();
10281 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
10282 return LowerSIGN_EXTEND_AVX512(Op, DAG);
10284 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
10285 (VT != MVT::v8i32 || InVT != MVT::v8i16))
10288 if (Subtarget->hasInt256())
10289 return DAG.getNode(X86ISD::VSEXT_MOVL, dl, VT, In);
10291 // Optimize vectors in AVX mode
10292 // Sign extend v8i16 to v8i32 and
10295 // Divide input vector into two parts
10296 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
10297 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
10298 // concat the vectors to original VT
10300 unsigned NumElems = InVT.getVectorNumElements();
10301 SDValue Undef = DAG.getUNDEF(InVT);
10303 SmallVector<int,8> ShufMask1(NumElems, -1);
10304 for (unsigned i = 0; i != NumElems/2; ++i)
10307 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
10309 SmallVector<int,8> ShufMask2(NumElems, -1);
10310 for (unsigned i = 0; i != NumElems/2; ++i)
10311 ShufMask2[i] = i + NumElems/2;
10313 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
10315 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
10316 VT.getVectorNumElements()/2);
10318 OpLo = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpLo);
10319 OpHi = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpHi);
10321 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
10324 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
10325 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
10326 // from the AND / OR.
10327 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
10328 Opc = Op.getOpcode();
10329 if (Opc != ISD::OR && Opc != ISD::AND)
10331 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
10332 Op.getOperand(0).hasOneUse() &&
10333 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
10334 Op.getOperand(1).hasOneUse());
10337 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
10338 // 1 and that the SETCC node has a single use.
10339 static bool isXor1OfSetCC(SDValue Op) {
10340 if (Op.getOpcode() != ISD::XOR)
10342 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
10343 if (N1C && N1C->getAPIntValue() == 1) {
10344 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
10345 Op.getOperand(0).hasOneUse();
10350 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
10351 bool addTest = true;
10352 SDValue Chain = Op.getOperand(0);
10353 SDValue Cond = Op.getOperand(1);
10354 SDValue Dest = Op.getOperand(2);
10357 bool Inverted = false;
10359 if (Cond.getOpcode() == ISD::SETCC) {
10360 // Check for setcc([su]{add,sub,mul}o == 0).
10361 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
10362 isa<ConstantSDNode>(Cond.getOperand(1)) &&
10363 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
10364 Cond.getOperand(0).getResNo() == 1 &&
10365 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
10366 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
10367 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
10368 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
10369 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
10370 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
10372 Cond = Cond.getOperand(0);
10374 SDValue NewCond = LowerSETCC(Cond, DAG);
10375 if (NewCond.getNode())
10380 // FIXME: LowerXALUO doesn't handle these!!
10381 else if (Cond.getOpcode() == X86ISD::ADD ||
10382 Cond.getOpcode() == X86ISD::SUB ||
10383 Cond.getOpcode() == X86ISD::SMUL ||
10384 Cond.getOpcode() == X86ISD::UMUL)
10385 Cond = LowerXALUO(Cond, DAG);
10388 // Look pass (and (setcc_carry (cmp ...)), 1).
10389 if (Cond.getOpcode() == ISD::AND &&
10390 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
10391 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
10392 if (C && C->getAPIntValue() == 1)
10393 Cond = Cond.getOperand(0);
10396 // If condition flag is set by a X86ISD::CMP, then use it as the condition
10397 // setting operand in place of the X86ISD::SETCC.
10398 unsigned CondOpcode = Cond.getOpcode();
10399 if (CondOpcode == X86ISD::SETCC ||
10400 CondOpcode == X86ISD::SETCC_CARRY) {
10401 CC = Cond.getOperand(0);
10403 SDValue Cmp = Cond.getOperand(1);
10404 unsigned Opc = Cmp.getOpcode();
10405 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
10406 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
10410 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
10414 // These can only come from an arithmetic instruction with overflow,
10415 // e.g. SADDO, UADDO.
10416 Cond = Cond.getNode()->getOperand(1);
10422 CondOpcode = Cond.getOpcode();
10423 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
10424 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
10425 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
10426 Cond.getOperand(0).getValueType() != MVT::i8)) {
10427 SDValue LHS = Cond.getOperand(0);
10428 SDValue RHS = Cond.getOperand(1);
10429 unsigned X86Opcode;
10432 switch (CondOpcode) {
10433 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
10434 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
10435 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
10436 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
10437 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
10438 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
10439 default: llvm_unreachable("unexpected overflowing operator");
10442 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
10443 if (CondOpcode == ISD::UMULO)
10444 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
10447 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
10449 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
10451 if (CondOpcode == ISD::UMULO)
10452 Cond = X86Op.getValue(2);
10454 Cond = X86Op.getValue(1);
10456 CC = DAG.getConstant(X86Cond, MVT::i8);
10460 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
10461 SDValue Cmp = Cond.getOperand(0).getOperand(1);
10462 if (CondOpc == ISD::OR) {
10463 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
10464 // two branches instead of an explicit OR instruction with a
10466 if (Cmp == Cond.getOperand(1).getOperand(1) &&
10467 isX86LogicalCmp(Cmp)) {
10468 CC = Cond.getOperand(0).getOperand(0);
10469 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10470 Chain, Dest, CC, Cmp);
10471 CC = Cond.getOperand(1).getOperand(0);
10475 } else { // ISD::AND
10476 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
10477 // two branches instead of an explicit AND instruction with a
10478 // separate test. However, we only do this if this block doesn't
10479 // have a fall-through edge, because this requires an explicit
10480 // jmp when the condition is false.
10481 if (Cmp == Cond.getOperand(1).getOperand(1) &&
10482 isX86LogicalCmp(Cmp) &&
10483 Op.getNode()->hasOneUse()) {
10484 X86::CondCode CCode =
10485 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
10486 CCode = X86::GetOppositeBranchCondition(CCode);
10487 CC = DAG.getConstant(CCode, MVT::i8);
10488 SDNode *User = *Op.getNode()->use_begin();
10489 // Look for an unconditional branch following this conditional branch.
10490 // We need this because we need to reverse the successors in order
10491 // to implement FCMP_OEQ.
10492 if (User->getOpcode() == ISD::BR) {
10493 SDValue FalseBB = User->getOperand(1);
10495 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
10496 assert(NewBR == User);
10500 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10501 Chain, Dest, CC, Cmp);
10502 X86::CondCode CCode =
10503 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
10504 CCode = X86::GetOppositeBranchCondition(CCode);
10505 CC = DAG.getConstant(CCode, MVT::i8);
10511 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
10512 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
10513 // It should be transformed during dag combiner except when the condition
10514 // is set by a arithmetics with overflow node.
10515 X86::CondCode CCode =
10516 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
10517 CCode = X86::GetOppositeBranchCondition(CCode);
10518 CC = DAG.getConstant(CCode, MVT::i8);
10519 Cond = Cond.getOperand(0).getOperand(1);
10521 } else if (Cond.getOpcode() == ISD::SETCC &&
10522 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
10523 // For FCMP_OEQ, we can emit
10524 // two branches instead of an explicit AND instruction with a
10525 // separate test. However, we only do this if this block doesn't
10526 // have a fall-through edge, because this requires an explicit
10527 // jmp when the condition is false.
10528 if (Op.getNode()->hasOneUse()) {
10529 SDNode *User = *Op.getNode()->use_begin();
10530 // Look for an unconditional branch following this conditional branch.
10531 // We need this because we need to reverse the successors in order
10532 // to implement FCMP_OEQ.
10533 if (User->getOpcode() == ISD::BR) {
10534 SDValue FalseBB = User->getOperand(1);
10536 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
10537 assert(NewBR == User);
10541 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
10542 Cond.getOperand(0), Cond.getOperand(1));
10543 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
10544 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10545 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10546 Chain, Dest, CC, Cmp);
10547 CC = DAG.getConstant(X86::COND_P, MVT::i8);
10552 } else if (Cond.getOpcode() == ISD::SETCC &&
10553 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
10554 // For FCMP_UNE, we can emit
10555 // two branches instead of an explicit AND instruction with a
10556 // separate test. However, we only do this if this block doesn't
10557 // have a fall-through edge, because this requires an explicit
10558 // jmp when the condition is false.
10559 if (Op.getNode()->hasOneUse()) {
10560 SDNode *User = *Op.getNode()->use_begin();
10561 // Look for an unconditional branch following this conditional branch.
10562 // We need this because we need to reverse the successors in order
10563 // to implement FCMP_UNE.
10564 if (User->getOpcode() == ISD::BR) {
10565 SDValue FalseBB = User->getOperand(1);
10567 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
10568 assert(NewBR == User);
10571 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
10572 Cond.getOperand(0), Cond.getOperand(1));
10573 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
10574 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10575 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10576 Chain, Dest, CC, Cmp);
10577 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
10587 // Look pass the truncate if the high bits are known zero.
10588 if (isTruncWithZeroHighBitsInput(Cond, DAG))
10589 Cond = Cond.getOperand(0);
10591 // We know the result of AND is compared against zero. Try to match
10593 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
10594 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
10595 if (NewSetCC.getNode()) {
10596 CC = NewSetCC.getOperand(0);
10597 Cond = NewSetCC.getOperand(1);
10604 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10605 Cond = EmitTest(Cond, X86::COND_NE, DAG);
10607 Cond = ConvertCmpIfNecessary(Cond, DAG);
10608 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10609 Chain, Dest, CC, Cond);
10612 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
10613 // Calls to _alloca is needed to probe the stack when allocating more than 4k
10614 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
10615 // that the guard pages used by the OS virtual memory manager are allocated in
10616 // correct sequence.
10618 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
10619 SelectionDAG &DAG) const {
10620 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() ||
10621 getTargetMachine().Options.EnableSegmentedStacks) &&
10622 "This should be used only on Windows targets or when segmented stacks "
10624 assert(!Subtarget->isTargetEnvMacho() && "Not implemented");
10628 SDValue Chain = Op.getOperand(0);
10629 SDValue Size = Op.getOperand(1);
10630 // FIXME: Ensure alignment here
10632 bool Is64Bit = Subtarget->is64Bit();
10633 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32;
10635 if (getTargetMachine().Options.EnableSegmentedStacks) {
10636 MachineFunction &MF = DAG.getMachineFunction();
10637 MachineRegisterInfo &MRI = MF.getRegInfo();
10640 // The 64 bit implementation of segmented stacks needs to clobber both r10
10641 // r11. This makes it impossible to use it along with nested parameters.
10642 const Function *F = MF.getFunction();
10644 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
10646 if (I->hasNestAttr())
10647 report_fatal_error("Cannot use segmented stacks with functions that "
10648 "have nested arguments.");
10651 const TargetRegisterClass *AddrRegClass =
10652 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
10653 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
10654 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
10655 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
10656 DAG.getRegister(Vreg, SPTy));
10657 SDValue Ops1[2] = { Value, Chain };
10658 return DAG.getMergeValues(Ops1, 2, dl);
10661 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
10663 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
10664 Flag = Chain.getValue(1);
10665 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
10667 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
10668 Flag = Chain.getValue(1);
10670 const X86RegisterInfo *RegInfo =
10671 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
10672 Chain = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
10675 SDValue Ops1[2] = { Chain.getValue(0), Chain };
10676 return DAG.getMergeValues(Ops1, 2, dl);
10680 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
10681 MachineFunction &MF = DAG.getMachineFunction();
10682 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
10684 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
10687 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
10688 // vastart just stores the address of the VarArgsFrameIndex slot into the
10689 // memory location argument.
10690 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
10692 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
10693 MachinePointerInfo(SV), false, false, 0);
10697 // gp_offset (0 - 6 * 8)
10698 // fp_offset (48 - 48 + 8 * 16)
10699 // overflow_arg_area (point to parameters coming in memory).
10701 SmallVector<SDValue, 8> MemOps;
10702 SDValue FIN = Op.getOperand(1);
10704 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
10705 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
10707 FIN, MachinePointerInfo(SV), false, false, 0);
10708 MemOps.push_back(Store);
10711 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10712 FIN, DAG.getIntPtrConstant(4));
10713 Store = DAG.getStore(Op.getOperand(0), DL,
10714 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
10716 FIN, MachinePointerInfo(SV, 4), false, false, 0);
10717 MemOps.push_back(Store);
10719 // Store ptr to overflow_arg_area
10720 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10721 FIN, DAG.getIntPtrConstant(4));
10722 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
10724 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
10725 MachinePointerInfo(SV, 8),
10727 MemOps.push_back(Store);
10729 // Store ptr to reg_save_area.
10730 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10731 FIN, DAG.getIntPtrConstant(8));
10732 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
10734 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
10735 MachinePointerInfo(SV, 16), false, false, 0);
10736 MemOps.push_back(Store);
10737 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
10738 &MemOps[0], MemOps.size());
10741 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
10742 assert(Subtarget->is64Bit() &&
10743 "LowerVAARG only handles 64-bit va_arg!");
10744 assert((Subtarget->isTargetLinux() ||
10745 Subtarget->isTargetDarwin()) &&
10746 "Unhandled target in LowerVAARG");
10747 assert(Op.getNode()->getNumOperands() == 4);
10748 SDValue Chain = Op.getOperand(0);
10749 SDValue SrcPtr = Op.getOperand(1);
10750 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
10751 unsigned Align = Op.getConstantOperandVal(3);
10754 EVT ArgVT = Op.getNode()->getValueType(0);
10755 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
10756 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
10759 // Decide which area this value should be read from.
10760 // TODO: Implement the AMD64 ABI in its entirety. This simple
10761 // selection mechanism works only for the basic types.
10762 if (ArgVT == MVT::f80) {
10763 llvm_unreachable("va_arg for f80 not yet implemented");
10764 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
10765 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
10766 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
10767 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
10769 llvm_unreachable("Unhandled argument type in LowerVAARG");
10772 if (ArgMode == 2) {
10773 // Sanity Check: Make sure using fp_offset makes sense.
10774 assert(!getTargetMachine().Options.UseSoftFloat &&
10775 !(DAG.getMachineFunction()
10776 .getFunction()->getAttributes()
10777 .hasAttribute(AttributeSet::FunctionIndex,
10778 Attribute::NoImplicitFloat)) &&
10779 Subtarget->hasSSE1());
10782 // Insert VAARG_64 node into the DAG
10783 // VAARG_64 returns two values: Variable Argument Address, Chain
10784 SmallVector<SDValue, 11> InstOps;
10785 InstOps.push_back(Chain);
10786 InstOps.push_back(SrcPtr);
10787 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
10788 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
10789 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
10790 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
10791 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
10792 VTs, &InstOps[0], InstOps.size(),
10794 MachinePointerInfo(SV),
10796 /*Volatile=*/false,
10798 /*WriteMem=*/true);
10799 Chain = VAARG.getValue(1);
10801 // Load the next argument and return it
10802 return DAG.getLoad(ArgVT, dl,
10805 MachinePointerInfo(),
10806 false, false, false, 0);
10809 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
10810 SelectionDAG &DAG) {
10811 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
10812 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
10813 SDValue Chain = Op.getOperand(0);
10814 SDValue DstPtr = Op.getOperand(1);
10815 SDValue SrcPtr = Op.getOperand(2);
10816 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
10817 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
10820 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
10821 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
10823 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
10826 // getTargetVShiftNode - Handle vector element shifts where the shift amount
10827 // may or may not be a constant. Takes immediate version of shift as input.
10828 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, EVT VT,
10829 SDValue SrcOp, SDValue ShAmt,
10830 SelectionDAG &DAG) {
10831 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
10833 if (isa<ConstantSDNode>(ShAmt)) {
10834 // Constant may be a TargetConstant. Use a regular constant.
10835 uint32_t ShiftAmt = cast<ConstantSDNode>(ShAmt)->getZExtValue();
10837 default: llvm_unreachable("Unknown target vector shift node");
10838 case X86ISD::VSHLI:
10839 case X86ISD::VSRLI:
10840 case X86ISD::VSRAI:
10841 return DAG.getNode(Opc, dl, VT, SrcOp,
10842 DAG.getConstant(ShiftAmt, MVT::i32));
10846 // Change opcode to non-immediate version
10848 default: llvm_unreachable("Unknown target vector shift node");
10849 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
10850 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
10851 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
10854 // Need to build a vector containing shift amount
10855 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
10858 ShOps[1] = DAG.getConstant(0, MVT::i32);
10859 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32);
10860 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &ShOps[0], 4);
10862 // The return type has to be a 128-bit type with the same element
10863 // type as the input type.
10864 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10865 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
10867 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
10868 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
10871 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
10873 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
10875 default: return SDValue(); // Don't custom lower most intrinsics.
10876 // Comparison intrinsics.
10877 case Intrinsic::x86_sse_comieq_ss:
10878 case Intrinsic::x86_sse_comilt_ss:
10879 case Intrinsic::x86_sse_comile_ss:
10880 case Intrinsic::x86_sse_comigt_ss:
10881 case Intrinsic::x86_sse_comige_ss:
10882 case Intrinsic::x86_sse_comineq_ss:
10883 case Intrinsic::x86_sse_ucomieq_ss:
10884 case Intrinsic::x86_sse_ucomilt_ss:
10885 case Intrinsic::x86_sse_ucomile_ss:
10886 case Intrinsic::x86_sse_ucomigt_ss:
10887 case Intrinsic::x86_sse_ucomige_ss:
10888 case Intrinsic::x86_sse_ucomineq_ss:
10889 case Intrinsic::x86_sse2_comieq_sd:
10890 case Intrinsic::x86_sse2_comilt_sd:
10891 case Intrinsic::x86_sse2_comile_sd:
10892 case Intrinsic::x86_sse2_comigt_sd:
10893 case Intrinsic::x86_sse2_comige_sd:
10894 case Intrinsic::x86_sse2_comineq_sd:
10895 case Intrinsic::x86_sse2_ucomieq_sd:
10896 case Intrinsic::x86_sse2_ucomilt_sd:
10897 case Intrinsic::x86_sse2_ucomile_sd:
10898 case Intrinsic::x86_sse2_ucomigt_sd:
10899 case Intrinsic::x86_sse2_ucomige_sd:
10900 case Intrinsic::x86_sse2_ucomineq_sd: {
10904 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
10905 case Intrinsic::x86_sse_comieq_ss:
10906 case Intrinsic::x86_sse2_comieq_sd:
10907 Opc = X86ISD::COMI;
10910 case Intrinsic::x86_sse_comilt_ss:
10911 case Intrinsic::x86_sse2_comilt_sd:
10912 Opc = X86ISD::COMI;
10915 case Intrinsic::x86_sse_comile_ss:
10916 case Intrinsic::x86_sse2_comile_sd:
10917 Opc = X86ISD::COMI;
10920 case Intrinsic::x86_sse_comigt_ss:
10921 case Intrinsic::x86_sse2_comigt_sd:
10922 Opc = X86ISD::COMI;
10925 case Intrinsic::x86_sse_comige_ss:
10926 case Intrinsic::x86_sse2_comige_sd:
10927 Opc = X86ISD::COMI;
10930 case Intrinsic::x86_sse_comineq_ss:
10931 case Intrinsic::x86_sse2_comineq_sd:
10932 Opc = X86ISD::COMI;
10935 case Intrinsic::x86_sse_ucomieq_ss:
10936 case Intrinsic::x86_sse2_ucomieq_sd:
10937 Opc = X86ISD::UCOMI;
10940 case Intrinsic::x86_sse_ucomilt_ss:
10941 case Intrinsic::x86_sse2_ucomilt_sd:
10942 Opc = X86ISD::UCOMI;
10945 case Intrinsic::x86_sse_ucomile_ss:
10946 case Intrinsic::x86_sse2_ucomile_sd:
10947 Opc = X86ISD::UCOMI;
10950 case Intrinsic::x86_sse_ucomigt_ss:
10951 case Intrinsic::x86_sse2_ucomigt_sd:
10952 Opc = X86ISD::UCOMI;
10955 case Intrinsic::x86_sse_ucomige_ss:
10956 case Intrinsic::x86_sse2_ucomige_sd:
10957 Opc = X86ISD::UCOMI;
10960 case Intrinsic::x86_sse_ucomineq_ss:
10961 case Intrinsic::x86_sse2_ucomineq_sd:
10962 Opc = X86ISD::UCOMI;
10967 SDValue LHS = Op.getOperand(1);
10968 SDValue RHS = Op.getOperand(2);
10969 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
10970 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
10971 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
10972 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
10973 DAG.getConstant(X86CC, MVT::i8), Cond);
10974 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
10977 // Arithmetic intrinsics.
10978 case Intrinsic::x86_sse2_pmulu_dq:
10979 case Intrinsic::x86_avx2_pmulu_dq:
10980 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
10981 Op.getOperand(1), Op.getOperand(2));
10983 // SSE2/AVX2 sub with unsigned saturation intrinsics
10984 case Intrinsic::x86_sse2_psubus_b:
10985 case Intrinsic::x86_sse2_psubus_w:
10986 case Intrinsic::x86_avx2_psubus_b:
10987 case Intrinsic::x86_avx2_psubus_w:
10988 return DAG.getNode(X86ISD::SUBUS, dl, Op.getValueType(),
10989 Op.getOperand(1), Op.getOperand(2));
10991 // SSE3/AVX horizontal add/sub intrinsics
10992 case Intrinsic::x86_sse3_hadd_ps:
10993 case Intrinsic::x86_sse3_hadd_pd:
10994 case Intrinsic::x86_avx_hadd_ps_256:
10995 case Intrinsic::x86_avx_hadd_pd_256:
10996 case Intrinsic::x86_sse3_hsub_ps:
10997 case Intrinsic::x86_sse3_hsub_pd:
10998 case Intrinsic::x86_avx_hsub_ps_256:
10999 case Intrinsic::x86_avx_hsub_pd_256:
11000 case Intrinsic::x86_ssse3_phadd_w_128:
11001 case Intrinsic::x86_ssse3_phadd_d_128:
11002 case Intrinsic::x86_avx2_phadd_w:
11003 case Intrinsic::x86_avx2_phadd_d:
11004 case Intrinsic::x86_ssse3_phsub_w_128:
11005 case Intrinsic::x86_ssse3_phsub_d_128:
11006 case Intrinsic::x86_avx2_phsub_w:
11007 case Intrinsic::x86_avx2_phsub_d: {
11010 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11011 case Intrinsic::x86_sse3_hadd_ps:
11012 case Intrinsic::x86_sse3_hadd_pd:
11013 case Intrinsic::x86_avx_hadd_ps_256:
11014 case Intrinsic::x86_avx_hadd_pd_256:
11015 Opcode = X86ISD::FHADD;
11017 case Intrinsic::x86_sse3_hsub_ps:
11018 case Intrinsic::x86_sse3_hsub_pd:
11019 case Intrinsic::x86_avx_hsub_ps_256:
11020 case Intrinsic::x86_avx_hsub_pd_256:
11021 Opcode = X86ISD::FHSUB;
11023 case Intrinsic::x86_ssse3_phadd_w_128:
11024 case Intrinsic::x86_ssse3_phadd_d_128:
11025 case Intrinsic::x86_avx2_phadd_w:
11026 case Intrinsic::x86_avx2_phadd_d:
11027 Opcode = X86ISD::HADD;
11029 case Intrinsic::x86_ssse3_phsub_w_128:
11030 case Intrinsic::x86_ssse3_phsub_d_128:
11031 case Intrinsic::x86_avx2_phsub_w:
11032 case Intrinsic::x86_avx2_phsub_d:
11033 Opcode = X86ISD::HSUB;
11036 return DAG.getNode(Opcode, dl, Op.getValueType(),
11037 Op.getOperand(1), Op.getOperand(2));
11040 // SSE2/SSE41/AVX2 integer max/min intrinsics.
11041 case Intrinsic::x86_sse2_pmaxu_b:
11042 case Intrinsic::x86_sse41_pmaxuw:
11043 case Intrinsic::x86_sse41_pmaxud:
11044 case Intrinsic::x86_avx2_pmaxu_b:
11045 case Intrinsic::x86_avx2_pmaxu_w:
11046 case Intrinsic::x86_avx2_pmaxu_d:
11047 case Intrinsic::x86_sse2_pminu_b:
11048 case Intrinsic::x86_sse41_pminuw:
11049 case Intrinsic::x86_sse41_pminud:
11050 case Intrinsic::x86_avx2_pminu_b:
11051 case Intrinsic::x86_avx2_pminu_w:
11052 case Intrinsic::x86_avx2_pminu_d:
11053 case Intrinsic::x86_sse41_pmaxsb:
11054 case Intrinsic::x86_sse2_pmaxs_w:
11055 case Intrinsic::x86_sse41_pmaxsd:
11056 case Intrinsic::x86_avx2_pmaxs_b:
11057 case Intrinsic::x86_avx2_pmaxs_w:
11058 case Intrinsic::x86_avx2_pmaxs_d:
11059 case Intrinsic::x86_sse41_pminsb:
11060 case Intrinsic::x86_sse2_pmins_w:
11061 case Intrinsic::x86_sse41_pminsd:
11062 case Intrinsic::x86_avx2_pmins_b:
11063 case Intrinsic::x86_avx2_pmins_w:
11064 case Intrinsic::x86_avx2_pmins_d: {
11067 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11068 case Intrinsic::x86_sse2_pmaxu_b:
11069 case Intrinsic::x86_sse41_pmaxuw:
11070 case Intrinsic::x86_sse41_pmaxud:
11071 case Intrinsic::x86_avx2_pmaxu_b:
11072 case Intrinsic::x86_avx2_pmaxu_w:
11073 case Intrinsic::x86_avx2_pmaxu_d:
11074 Opcode = X86ISD::UMAX;
11076 case Intrinsic::x86_sse2_pminu_b:
11077 case Intrinsic::x86_sse41_pminuw:
11078 case Intrinsic::x86_sse41_pminud:
11079 case Intrinsic::x86_avx2_pminu_b:
11080 case Intrinsic::x86_avx2_pminu_w:
11081 case Intrinsic::x86_avx2_pminu_d:
11082 Opcode = X86ISD::UMIN;
11084 case Intrinsic::x86_sse41_pmaxsb:
11085 case Intrinsic::x86_sse2_pmaxs_w:
11086 case Intrinsic::x86_sse41_pmaxsd:
11087 case Intrinsic::x86_avx2_pmaxs_b:
11088 case Intrinsic::x86_avx2_pmaxs_w:
11089 case Intrinsic::x86_avx2_pmaxs_d:
11090 Opcode = X86ISD::SMAX;
11092 case Intrinsic::x86_sse41_pminsb:
11093 case Intrinsic::x86_sse2_pmins_w:
11094 case Intrinsic::x86_sse41_pminsd:
11095 case Intrinsic::x86_avx2_pmins_b:
11096 case Intrinsic::x86_avx2_pmins_w:
11097 case Intrinsic::x86_avx2_pmins_d:
11098 Opcode = X86ISD::SMIN;
11101 return DAG.getNode(Opcode, dl, Op.getValueType(),
11102 Op.getOperand(1), Op.getOperand(2));
11105 // SSE/SSE2/AVX floating point max/min intrinsics.
11106 case Intrinsic::x86_sse_max_ps:
11107 case Intrinsic::x86_sse2_max_pd:
11108 case Intrinsic::x86_avx_max_ps_256:
11109 case Intrinsic::x86_avx_max_pd_256:
11110 case Intrinsic::x86_sse_min_ps:
11111 case Intrinsic::x86_sse2_min_pd:
11112 case Intrinsic::x86_avx_min_ps_256:
11113 case Intrinsic::x86_avx_min_pd_256: {
11116 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11117 case Intrinsic::x86_sse_max_ps:
11118 case Intrinsic::x86_sse2_max_pd:
11119 case Intrinsic::x86_avx_max_ps_256:
11120 case Intrinsic::x86_avx_max_pd_256:
11121 Opcode = X86ISD::FMAX;
11123 case Intrinsic::x86_sse_min_ps:
11124 case Intrinsic::x86_sse2_min_pd:
11125 case Intrinsic::x86_avx_min_ps_256:
11126 case Intrinsic::x86_avx_min_pd_256:
11127 Opcode = X86ISD::FMIN;
11130 return DAG.getNode(Opcode, dl, Op.getValueType(),
11131 Op.getOperand(1), Op.getOperand(2));
11134 // AVX2 variable shift intrinsics
11135 case Intrinsic::x86_avx2_psllv_d:
11136 case Intrinsic::x86_avx2_psllv_q:
11137 case Intrinsic::x86_avx2_psllv_d_256:
11138 case Intrinsic::x86_avx2_psllv_q_256:
11139 case Intrinsic::x86_avx2_psrlv_d:
11140 case Intrinsic::x86_avx2_psrlv_q:
11141 case Intrinsic::x86_avx2_psrlv_d_256:
11142 case Intrinsic::x86_avx2_psrlv_q_256:
11143 case Intrinsic::x86_avx2_psrav_d:
11144 case Intrinsic::x86_avx2_psrav_d_256: {
11147 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11148 case Intrinsic::x86_avx2_psllv_d:
11149 case Intrinsic::x86_avx2_psllv_q:
11150 case Intrinsic::x86_avx2_psllv_d_256:
11151 case Intrinsic::x86_avx2_psllv_q_256:
11154 case Intrinsic::x86_avx2_psrlv_d:
11155 case Intrinsic::x86_avx2_psrlv_q:
11156 case Intrinsic::x86_avx2_psrlv_d_256:
11157 case Intrinsic::x86_avx2_psrlv_q_256:
11160 case Intrinsic::x86_avx2_psrav_d:
11161 case Intrinsic::x86_avx2_psrav_d_256:
11165 return DAG.getNode(Opcode, dl, Op.getValueType(),
11166 Op.getOperand(1), Op.getOperand(2));
11169 case Intrinsic::x86_ssse3_pshuf_b_128:
11170 case Intrinsic::x86_avx2_pshuf_b:
11171 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
11172 Op.getOperand(1), Op.getOperand(2));
11174 case Intrinsic::x86_ssse3_psign_b_128:
11175 case Intrinsic::x86_ssse3_psign_w_128:
11176 case Intrinsic::x86_ssse3_psign_d_128:
11177 case Intrinsic::x86_avx2_psign_b:
11178 case Intrinsic::x86_avx2_psign_w:
11179 case Intrinsic::x86_avx2_psign_d:
11180 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
11181 Op.getOperand(1), Op.getOperand(2));
11183 case Intrinsic::x86_sse41_insertps:
11184 return DAG.getNode(X86ISD::INSERTPS, dl, Op.getValueType(),
11185 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
11187 case Intrinsic::x86_avx_vperm2f128_ps_256:
11188 case Intrinsic::x86_avx_vperm2f128_pd_256:
11189 case Intrinsic::x86_avx_vperm2f128_si_256:
11190 case Intrinsic::x86_avx2_vperm2i128:
11191 return DAG.getNode(X86ISD::VPERM2X128, dl, Op.getValueType(),
11192 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
11194 case Intrinsic::x86_avx2_permd:
11195 case Intrinsic::x86_avx2_permps:
11196 // Operands intentionally swapped. Mask is last operand to intrinsic,
11197 // but second operand for node/intruction.
11198 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
11199 Op.getOperand(2), Op.getOperand(1));
11201 case Intrinsic::x86_sse_sqrt_ps:
11202 case Intrinsic::x86_sse2_sqrt_pd:
11203 case Intrinsic::x86_avx_sqrt_ps_256:
11204 case Intrinsic::x86_avx_sqrt_pd_256:
11205 return DAG.getNode(ISD::FSQRT, dl, Op.getValueType(), Op.getOperand(1));
11207 // ptest and testp intrinsics. The intrinsic these come from are designed to
11208 // return an integer value, not just an instruction so lower it to the ptest
11209 // or testp pattern and a setcc for the result.
11210 case Intrinsic::x86_sse41_ptestz:
11211 case Intrinsic::x86_sse41_ptestc:
11212 case Intrinsic::x86_sse41_ptestnzc:
11213 case Intrinsic::x86_avx_ptestz_256:
11214 case Intrinsic::x86_avx_ptestc_256:
11215 case Intrinsic::x86_avx_ptestnzc_256:
11216 case Intrinsic::x86_avx_vtestz_ps:
11217 case Intrinsic::x86_avx_vtestc_ps:
11218 case Intrinsic::x86_avx_vtestnzc_ps:
11219 case Intrinsic::x86_avx_vtestz_pd:
11220 case Intrinsic::x86_avx_vtestc_pd:
11221 case Intrinsic::x86_avx_vtestnzc_pd:
11222 case Intrinsic::x86_avx_vtestz_ps_256:
11223 case Intrinsic::x86_avx_vtestc_ps_256:
11224 case Intrinsic::x86_avx_vtestnzc_ps_256:
11225 case Intrinsic::x86_avx_vtestz_pd_256:
11226 case Intrinsic::x86_avx_vtestc_pd_256:
11227 case Intrinsic::x86_avx_vtestnzc_pd_256: {
11228 bool IsTestPacked = false;
11231 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
11232 case Intrinsic::x86_avx_vtestz_ps:
11233 case Intrinsic::x86_avx_vtestz_pd:
11234 case Intrinsic::x86_avx_vtestz_ps_256:
11235 case Intrinsic::x86_avx_vtestz_pd_256:
11236 IsTestPacked = true; // Fallthrough
11237 case Intrinsic::x86_sse41_ptestz:
11238 case Intrinsic::x86_avx_ptestz_256:
11240 X86CC = X86::COND_E;
11242 case Intrinsic::x86_avx_vtestc_ps:
11243 case Intrinsic::x86_avx_vtestc_pd:
11244 case Intrinsic::x86_avx_vtestc_ps_256:
11245 case Intrinsic::x86_avx_vtestc_pd_256:
11246 IsTestPacked = true; // Fallthrough
11247 case Intrinsic::x86_sse41_ptestc:
11248 case Intrinsic::x86_avx_ptestc_256:
11250 X86CC = X86::COND_B;
11252 case Intrinsic::x86_avx_vtestnzc_ps:
11253 case Intrinsic::x86_avx_vtestnzc_pd:
11254 case Intrinsic::x86_avx_vtestnzc_ps_256:
11255 case Intrinsic::x86_avx_vtestnzc_pd_256:
11256 IsTestPacked = true; // Fallthrough
11257 case Intrinsic::x86_sse41_ptestnzc:
11258 case Intrinsic::x86_avx_ptestnzc_256:
11260 X86CC = X86::COND_A;
11264 SDValue LHS = Op.getOperand(1);
11265 SDValue RHS = Op.getOperand(2);
11266 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
11267 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
11268 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
11269 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
11270 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
11273 // SSE/AVX shift intrinsics
11274 case Intrinsic::x86_sse2_psll_w:
11275 case Intrinsic::x86_sse2_psll_d:
11276 case Intrinsic::x86_sse2_psll_q:
11277 case Intrinsic::x86_avx2_psll_w:
11278 case Intrinsic::x86_avx2_psll_d:
11279 case Intrinsic::x86_avx2_psll_q:
11280 case Intrinsic::x86_sse2_psrl_w:
11281 case Intrinsic::x86_sse2_psrl_d:
11282 case Intrinsic::x86_sse2_psrl_q:
11283 case Intrinsic::x86_avx2_psrl_w:
11284 case Intrinsic::x86_avx2_psrl_d:
11285 case Intrinsic::x86_avx2_psrl_q:
11286 case Intrinsic::x86_sse2_psra_w:
11287 case Intrinsic::x86_sse2_psra_d:
11288 case Intrinsic::x86_avx2_psra_w:
11289 case Intrinsic::x86_avx2_psra_d: {
11292 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11293 case Intrinsic::x86_sse2_psll_w:
11294 case Intrinsic::x86_sse2_psll_d:
11295 case Intrinsic::x86_sse2_psll_q:
11296 case Intrinsic::x86_avx2_psll_w:
11297 case Intrinsic::x86_avx2_psll_d:
11298 case Intrinsic::x86_avx2_psll_q:
11299 Opcode = X86ISD::VSHL;
11301 case Intrinsic::x86_sse2_psrl_w:
11302 case Intrinsic::x86_sse2_psrl_d:
11303 case Intrinsic::x86_sse2_psrl_q:
11304 case Intrinsic::x86_avx2_psrl_w:
11305 case Intrinsic::x86_avx2_psrl_d:
11306 case Intrinsic::x86_avx2_psrl_q:
11307 Opcode = X86ISD::VSRL;
11309 case Intrinsic::x86_sse2_psra_w:
11310 case Intrinsic::x86_sse2_psra_d:
11311 case Intrinsic::x86_avx2_psra_w:
11312 case Intrinsic::x86_avx2_psra_d:
11313 Opcode = X86ISD::VSRA;
11316 return DAG.getNode(Opcode, dl, Op.getValueType(),
11317 Op.getOperand(1), Op.getOperand(2));
11320 // SSE/AVX immediate shift intrinsics
11321 case Intrinsic::x86_sse2_pslli_w:
11322 case Intrinsic::x86_sse2_pslli_d:
11323 case Intrinsic::x86_sse2_pslli_q:
11324 case Intrinsic::x86_avx2_pslli_w:
11325 case Intrinsic::x86_avx2_pslli_d:
11326 case Intrinsic::x86_avx2_pslli_q:
11327 case Intrinsic::x86_sse2_psrli_w:
11328 case Intrinsic::x86_sse2_psrli_d:
11329 case Intrinsic::x86_sse2_psrli_q:
11330 case Intrinsic::x86_avx2_psrli_w:
11331 case Intrinsic::x86_avx2_psrli_d:
11332 case Intrinsic::x86_avx2_psrli_q:
11333 case Intrinsic::x86_sse2_psrai_w:
11334 case Intrinsic::x86_sse2_psrai_d:
11335 case Intrinsic::x86_avx2_psrai_w:
11336 case Intrinsic::x86_avx2_psrai_d: {
11339 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11340 case Intrinsic::x86_sse2_pslli_w:
11341 case Intrinsic::x86_sse2_pslli_d:
11342 case Intrinsic::x86_sse2_pslli_q:
11343 case Intrinsic::x86_avx2_pslli_w:
11344 case Intrinsic::x86_avx2_pslli_d:
11345 case Intrinsic::x86_avx2_pslli_q:
11346 Opcode = X86ISD::VSHLI;
11348 case Intrinsic::x86_sse2_psrli_w:
11349 case Intrinsic::x86_sse2_psrli_d:
11350 case Intrinsic::x86_sse2_psrli_q:
11351 case Intrinsic::x86_avx2_psrli_w:
11352 case Intrinsic::x86_avx2_psrli_d:
11353 case Intrinsic::x86_avx2_psrli_q:
11354 Opcode = X86ISD::VSRLI;
11356 case Intrinsic::x86_sse2_psrai_w:
11357 case Intrinsic::x86_sse2_psrai_d:
11358 case Intrinsic::x86_avx2_psrai_w:
11359 case Intrinsic::x86_avx2_psrai_d:
11360 Opcode = X86ISD::VSRAI;
11363 return getTargetVShiftNode(Opcode, dl, Op.getValueType(),
11364 Op.getOperand(1), Op.getOperand(2), DAG);
11367 case Intrinsic::x86_sse42_pcmpistria128:
11368 case Intrinsic::x86_sse42_pcmpestria128:
11369 case Intrinsic::x86_sse42_pcmpistric128:
11370 case Intrinsic::x86_sse42_pcmpestric128:
11371 case Intrinsic::x86_sse42_pcmpistrio128:
11372 case Intrinsic::x86_sse42_pcmpestrio128:
11373 case Intrinsic::x86_sse42_pcmpistris128:
11374 case Intrinsic::x86_sse42_pcmpestris128:
11375 case Intrinsic::x86_sse42_pcmpistriz128:
11376 case Intrinsic::x86_sse42_pcmpestriz128: {
11380 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11381 case Intrinsic::x86_sse42_pcmpistria128:
11382 Opcode = X86ISD::PCMPISTRI;
11383 X86CC = X86::COND_A;
11385 case Intrinsic::x86_sse42_pcmpestria128:
11386 Opcode = X86ISD::PCMPESTRI;
11387 X86CC = X86::COND_A;
11389 case Intrinsic::x86_sse42_pcmpistric128:
11390 Opcode = X86ISD::PCMPISTRI;
11391 X86CC = X86::COND_B;
11393 case Intrinsic::x86_sse42_pcmpestric128:
11394 Opcode = X86ISD::PCMPESTRI;
11395 X86CC = X86::COND_B;
11397 case Intrinsic::x86_sse42_pcmpistrio128:
11398 Opcode = X86ISD::PCMPISTRI;
11399 X86CC = X86::COND_O;
11401 case Intrinsic::x86_sse42_pcmpestrio128:
11402 Opcode = X86ISD::PCMPESTRI;
11403 X86CC = X86::COND_O;
11405 case Intrinsic::x86_sse42_pcmpistris128:
11406 Opcode = X86ISD::PCMPISTRI;
11407 X86CC = X86::COND_S;
11409 case Intrinsic::x86_sse42_pcmpestris128:
11410 Opcode = X86ISD::PCMPESTRI;
11411 X86CC = X86::COND_S;
11413 case Intrinsic::x86_sse42_pcmpistriz128:
11414 Opcode = X86ISD::PCMPISTRI;
11415 X86CC = X86::COND_E;
11417 case Intrinsic::x86_sse42_pcmpestriz128:
11418 Opcode = X86ISD::PCMPESTRI;
11419 X86CC = X86::COND_E;
11422 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
11423 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
11424 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps.data(), NewOps.size());
11425 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
11426 DAG.getConstant(X86CC, MVT::i8),
11427 SDValue(PCMP.getNode(), 1));
11428 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
11431 case Intrinsic::x86_sse42_pcmpistri128:
11432 case Intrinsic::x86_sse42_pcmpestri128: {
11434 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
11435 Opcode = X86ISD::PCMPISTRI;
11437 Opcode = X86ISD::PCMPESTRI;
11439 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
11440 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
11441 return DAG.getNode(Opcode, dl, VTs, NewOps.data(), NewOps.size());
11443 case Intrinsic::x86_fma_vfmadd_ps:
11444 case Intrinsic::x86_fma_vfmadd_pd:
11445 case Intrinsic::x86_fma_vfmsub_ps:
11446 case Intrinsic::x86_fma_vfmsub_pd:
11447 case Intrinsic::x86_fma_vfnmadd_ps:
11448 case Intrinsic::x86_fma_vfnmadd_pd:
11449 case Intrinsic::x86_fma_vfnmsub_ps:
11450 case Intrinsic::x86_fma_vfnmsub_pd:
11451 case Intrinsic::x86_fma_vfmaddsub_ps:
11452 case Intrinsic::x86_fma_vfmaddsub_pd:
11453 case Intrinsic::x86_fma_vfmsubadd_ps:
11454 case Intrinsic::x86_fma_vfmsubadd_pd:
11455 case Intrinsic::x86_fma_vfmadd_ps_256:
11456 case Intrinsic::x86_fma_vfmadd_pd_256:
11457 case Intrinsic::x86_fma_vfmsub_ps_256:
11458 case Intrinsic::x86_fma_vfmsub_pd_256:
11459 case Intrinsic::x86_fma_vfnmadd_ps_256:
11460 case Intrinsic::x86_fma_vfnmadd_pd_256:
11461 case Intrinsic::x86_fma_vfnmsub_ps_256:
11462 case Intrinsic::x86_fma_vfnmsub_pd_256:
11463 case Intrinsic::x86_fma_vfmaddsub_ps_256:
11464 case Intrinsic::x86_fma_vfmaddsub_pd_256:
11465 case Intrinsic::x86_fma_vfmsubadd_ps_256:
11466 case Intrinsic::x86_fma_vfmsubadd_pd_256: {
11469 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11470 case Intrinsic::x86_fma_vfmadd_ps:
11471 case Intrinsic::x86_fma_vfmadd_pd:
11472 case Intrinsic::x86_fma_vfmadd_ps_256:
11473 case Intrinsic::x86_fma_vfmadd_pd_256:
11474 Opc = X86ISD::FMADD;
11476 case Intrinsic::x86_fma_vfmsub_ps:
11477 case Intrinsic::x86_fma_vfmsub_pd:
11478 case Intrinsic::x86_fma_vfmsub_ps_256:
11479 case Intrinsic::x86_fma_vfmsub_pd_256:
11480 Opc = X86ISD::FMSUB;
11482 case Intrinsic::x86_fma_vfnmadd_ps:
11483 case Intrinsic::x86_fma_vfnmadd_pd:
11484 case Intrinsic::x86_fma_vfnmadd_ps_256:
11485 case Intrinsic::x86_fma_vfnmadd_pd_256:
11486 Opc = X86ISD::FNMADD;
11488 case Intrinsic::x86_fma_vfnmsub_ps:
11489 case Intrinsic::x86_fma_vfnmsub_pd:
11490 case Intrinsic::x86_fma_vfnmsub_ps_256:
11491 case Intrinsic::x86_fma_vfnmsub_pd_256:
11492 Opc = X86ISD::FNMSUB;
11494 case Intrinsic::x86_fma_vfmaddsub_ps:
11495 case Intrinsic::x86_fma_vfmaddsub_pd:
11496 case Intrinsic::x86_fma_vfmaddsub_ps_256:
11497 case Intrinsic::x86_fma_vfmaddsub_pd_256:
11498 Opc = X86ISD::FMADDSUB;
11500 case Intrinsic::x86_fma_vfmsubadd_ps:
11501 case Intrinsic::x86_fma_vfmsubadd_pd:
11502 case Intrinsic::x86_fma_vfmsubadd_ps_256:
11503 case Intrinsic::x86_fma_vfmsubadd_pd_256:
11504 Opc = X86ISD::FMSUBADD;
11508 return DAG.getNode(Opc, dl, Op.getValueType(), Op.getOperand(1),
11509 Op.getOperand(2), Op.getOperand(3));
11514 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) {
11516 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11518 default: return SDValue(); // Don't custom lower most intrinsics.
11520 // RDRAND/RDSEED intrinsics.
11521 case Intrinsic::x86_rdrand_16:
11522 case Intrinsic::x86_rdrand_32:
11523 case Intrinsic::x86_rdrand_64:
11524 case Intrinsic::x86_rdseed_16:
11525 case Intrinsic::x86_rdseed_32:
11526 case Intrinsic::x86_rdseed_64: {
11527 unsigned Opcode = (IntNo == Intrinsic::x86_rdseed_16 ||
11528 IntNo == Intrinsic::x86_rdseed_32 ||
11529 IntNo == Intrinsic::x86_rdseed_64) ? X86ISD::RDSEED :
11531 // Emit the node with the right value type.
11532 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
11533 SDValue Result = DAG.getNode(Opcode, dl, VTs, Op.getOperand(0));
11535 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
11536 // Otherwise return the value from Rand, which is always 0, casted to i32.
11537 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
11538 DAG.getConstant(1, Op->getValueType(1)),
11539 DAG.getConstant(X86::COND_B, MVT::i32),
11540 SDValue(Result.getNode(), 1) };
11541 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
11542 DAG.getVTList(Op->getValueType(1), MVT::Glue),
11543 Ops, array_lengthof(Ops));
11545 // Return { result, isValid, chain }.
11546 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
11547 SDValue(Result.getNode(), 2));
11550 // XTEST intrinsics.
11551 case Intrinsic::x86_xtest: {
11552 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
11553 SDValue InTrans = DAG.getNode(X86ISD::XTEST, dl, VTs, Op.getOperand(0));
11554 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
11555 DAG.getConstant(X86::COND_NE, MVT::i8),
11557 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
11558 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
11559 Ret, SDValue(InTrans.getNode(), 1));
11564 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
11565 SelectionDAG &DAG) const {
11566 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11567 MFI->setReturnAddressIsTaken(true);
11569 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
11571 EVT PtrVT = getPointerTy();
11574 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
11575 const X86RegisterInfo *RegInfo =
11576 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
11577 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
11578 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
11579 DAG.getNode(ISD::ADD, dl, PtrVT,
11580 FrameAddr, Offset),
11581 MachinePointerInfo(), false, false, false, 0);
11584 // Just load the return address.
11585 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
11586 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
11587 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
11590 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
11591 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11592 MFI->setFrameAddressIsTaken(true);
11594 EVT VT = Op.getValueType();
11595 SDLoc dl(Op); // FIXME probably not meaningful
11596 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
11597 const X86RegisterInfo *RegInfo =
11598 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
11599 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
11600 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
11601 (FrameReg == X86::EBP && VT == MVT::i32)) &&
11602 "Invalid Frame Register!");
11603 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
11605 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
11606 MachinePointerInfo(),
11607 false, false, false, 0);
11611 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
11612 SelectionDAG &DAG) const {
11613 const X86RegisterInfo *RegInfo =
11614 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
11615 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
11618 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
11619 SDValue Chain = Op.getOperand(0);
11620 SDValue Offset = Op.getOperand(1);
11621 SDValue Handler = Op.getOperand(2);
11624 EVT PtrVT = getPointerTy();
11625 const X86RegisterInfo *RegInfo =
11626 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
11627 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
11628 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
11629 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
11630 "Invalid Frame Register!");
11631 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
11632 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
11634 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
11635 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
11636 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
11637 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
11639 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
11641 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
11642 DAG.getRegister(StoreAddrReg, PtrVT));
11645 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
11646 SelectionDAG &DAG) const {
11648 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
11649 DAG.getVTList(MVT::i32, MVT::Other),
11650 Op.getOperand(0), Op.getOperand(1));
11653 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
11654 SelectionDAG &DAG) const {
11656 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
11657 Op.getOperand(0), Op.getOperand(1));
11660 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
11661 return Op.getOperand(0);
11664 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
11665 SelectionDAG &DAG) const {
11666 SDValue Root = Op.getOperand(0);
11667 SDValue Trmp = Op.getOperand(1); // trampoline
11668 SDValue FPtr = Op.getOperand(2); // nested function
11669 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
11672 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
11673 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
11675 if (Subtarget->is64Bit()) {
11676 SDValue OutChains[6];
11678 // Large code-model.
11679 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
11680 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
11682 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
11683 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
11685 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
11687 // Load the pointer to the nested function into R11.
11688 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
11689 SDValue Addr = Trmp;
11690 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
11691 Addr, MachinePointerInfo(TrmpAddr),
11694 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
11695 DAG.getConstant(2, MVT::i64));
11696 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
11697 MachinePointerInfo(TrmpAddr, 2),
11700 // Load the 'nest' parameter value into R10.
11701 // R10 is specified in X86CallingConv.td
11702 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
11703 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
11704 DAG.getConstant(10, MVT::i64));
11705 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
11706 Addr, MachinePointerInfo(TrmpAddr, 10),
11709 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
11710 DAG.getConstant(12, MVT::i64));
11711 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
11712 MachinePointerInfo(TrmpAddr, 12),
11715 // Jump to the nested function.
11716 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
11717 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
11718 DAG.getConstant(20, MVT::i64));
11719 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
11720 Addr, MachinePointerInfo(TrmpAddr, 20),
11723 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
11724 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
11725 DAG.getConstant(22, MVT::i64));
11726 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
11727 MachinePointerInfo(TrmpAddr, 22),
11730 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6);
11732 const Function *Func =
11733 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
11734 CallingConv::ID CC = Func->getCallingConv();
11739 llvm_unreachable("Unsupported calling convention");
11740 case CallingConv::C:
11741 case CallingConv::X86_StdCall: {
11742 // Pass 'nest' parameter in ECX.
11743 // Must be kept in sync with X86CallingConv.td
11744 NestReg = X86::ECX;
11746 // Check that ECX wasn't needed by an 'inreg' parameter.
11747 FunctionType *FTy = Func->getFunctionType();
11748 const AttributeSet &Attrs = Func->getAttributes();
11750 if (!Attrs.isEmpty() && !Func->isVarArg()) {
11751 unsigned InRegCount = 0;
11754 for (FunctionType::param_iterator I = FTy->param_begin(),
11755 E = FTy->param_end(); I != E; ++I, ++Idx)
11756 if (Attrs.hasAttribute(Idx, Attribute::InReg))
11757 // FIXME: should only count parameters that are lowered to integers.
11758 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
11760 if (InRegCount > 2) {
11761 report_fatal_error("Nest register in use - reduce number of inreg"
11767 case CallingConv::X86_FastCall:
11768 case CallingConv::X86_ThisCall:
11769 case CallingConv::Fast:
11770 // Pass 'nest' parameter in EAX.
11771 // Must be kept in sync with X86CallingConv.td
11772 NestReg = X86::EAX;
11776 SDValue OutChains[4];
11777 SDValue Addr, Disp;
11779 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
11780 DAG.getConstant(10, MVT::i32));
11781 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
11783 // This is storing the opcode for MOV32ri.
11784 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
11785 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
11786 OutChains[0] = DAG.getStore(Root, dl,
11787 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
11788 Trmp, MachinePointerInfo(TrmpAddr),
11791 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
11792 DAG.getConstant(1, MVT::i32));
11793 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
11794 MachinePointerInfo(TrmpAddr, 1),
11797 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
11798 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
11799 DAG.getConstant(5, MVT::i32));
11800 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
11801 MachinePointerInfo(TrmpAddr, 5),
11804 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
11805 DAG.getConstant(6, MVT::i32));
11806 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
11807 MachinePointerInfo(TrmpAddr, 6),
11810 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4);
11814 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
11815 SelectionDAG &DAG) const {
11817 The rounding mode is in bits 11:10 of FPSR, and has the following
11819 00 Round to nearest
11824 FLT_ROUNDS, on the other hand, expects the following:
11831 To perform the conversion, we do:
11832 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
11835 MachineFunction &MF = DAG.getMachineFunction();
11836 const TargetMachine &TM = MF.getTarget();
11837 const TargetFrameLowering &TFI = *TM.getFrameLowering();
11838 unsigned StackAlignment = TFI.getStackAlignment();
11839 EVT VT = Op.getValueType();
11842 // Save FP Control Word to stack slot
11843 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
11844 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11846 MachineMemOperand *MMO =
11847 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11848 MachineMemOperand::MOStore, 2, 2);
11850 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
11851 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
11852 DAG.getVTList(MVT::Other),
11853 Ops, array_lengthof(Ops), MVT::i16,
11856 // Load FP Control Word from stack slot
11857 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
11858 MachinePointerInfo(), false, false, false, 0);
11860 // Transform as necessary
11862 DAG.getNode(ISD::SRL, DL, MVT::i16,
11863 DAG.getNode(ISD::AND, DL, MVT::i16,
11864 CWD, DAG.getConstant(0x800, MVT::i16)),
11865 DAG.getConstant(11, MVT::i8));
11867 DAG.getNode(ISD::SRL, DL, MVT::i16,
11868 DAG.getNode(ISD::AND, DL, MVT::i16,
11869 CWD, DAG.getConstant(0x400, MVT::i16)),
11870 DAG.getConstant(9, MVT::i8));
11873 DAG.getNode(ISD::AND, DL, MVT::i16,
11874 DAG.getNode(ISD::ADD, DL, MVT::i16,
11875 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
11876 DAG.getConstant(1, MVT::i16)),
11877 DAG.getConstant(3, MVT::i16));
11879 return DAG.getNode((VT.getSizeInBits() < 16 ?
11880 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
11883 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
11884 EVT VT = Op.getValueType();
11886 unsigned NumBits = VT.getSizeInBits();
11889 Op = Op.getOperand(0);
11890 if (VT == MVT::i8) {
11891 // Zero extend to i32 since there is not an i8 bsr.
11893 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
11896 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
11897 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
11898 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
11900 // If src is zero (i.e. bsr sets ZF), returns NumBits.
11903 DAG.getConstant(NumBits+NumBits-1, OpVT),
11904 DAG.getConstant(X86::COND_E, MVT::i8),
11907 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
11909 // Finally xor with NumBits-1.
11910 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
11913 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
11917 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
11918 EVT VT = Op.getValueType();
11920 unsigned NumBits = VT.getSizeInBits();
11923 Op = Op.getOperand(0);
11924 if (VT == MVT::i8) {
11925 // Zero extend to i32 since there is not an i8 bsr.
11927 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
11930 // Issue a bsr (scan bits in reverse).
11931 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
11932 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
11934 // And xor with NumBits-1.
11935 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
11938 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
11942 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
11943 EVT VT = Op.getValueType();
11944 unsigned NumBits = VT.getSizeInBits();
11946 Op = Op.getOperand(0);
11948 // Issue a bsf (scan bits forward) which also sets EFLAGS.
11949 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
11950 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
11952 // If src is zero (i.e. bsf sets ZF), returns NumBits.
11955 DAG.getConstant(NumBits, VT),
11956 DAG.getConstant(X86::COND_E, MVT::i8),
11959 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops, array_lengthof(Ops));
11962 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
11963 // ones, and then concatenate the result back.
11964 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
11965 EVT VT = Op.getValueType();
11967 assert(VT.is256BitVector() && VT.isInteger() &&
11968 "Unsupported value type for operation");
11970 unsigned NumElems = VT.getVectorNumElements();
11973 // Extract the LHS vectors
11974 SDValue LHS = Op.getOperand(0);
11975 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
11976 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
11978 // Extract the RHS vectors
11979 SDValue RHS = Op.getOperand(1);
11980 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
11981 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
11983 MVT EltVT = VT.getVectorElementType().getSimpleVT();
11984 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
11986 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
11987 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
11988 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
11991 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
11992 assert(Op.getValueType().is256BitVector() &&
11993 Op.getValueType().isInteger() &&
11994 "Only handle AVX 256-bit vector integer operation");
11995 return Lower256IntArith(Op, DAG);
11998 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
11999 assert(Op.getValueType().is256BitVector() &&
12000 Op.getValueType().isInteger() &&
12001 "Only handle AVX 256-bit vector integer operation");
12002 return Lower256IntArith(Op, DAG);
12005 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
12006 SelectionDAG &DAG) {
12008 EVT VT = Op.getValueType();
12010 // Decompose 256-bit ops into smaller 128-bit ops.
12011 if (VT.is256BitVector() && !Subtarget->hasInt256())
12012 return Lower256IntArith(Op, DAG);
12014 SDValue A = Op.getOperand(0);
12015 SDValue B = Op.getOperand(1);
12017 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
12018 if (VT == MVT::v4i32) {
12019 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
12020 "Should not custom lower when pmuldq is available!");
12022 // Extract the odd parts.
12023 static const int UnpackMask[] = { 1, -1, 3, -1 };
12024 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
12025 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
12027 // Multiply the even parts.
12028 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
12029 // Now multiply odd parts.
12030 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
12032 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
12033 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
12035 // Merge the two vectors back together with a shuffle. This expands into 2
12037 static const int ShufMask[] = { 0, 4, 2, 6 };
12038 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
12041 assert((VT == MVT::v2i64 || VT == MVT::v4i64) &&
12042 "Only know how to lower V2I64/V4I64 multiply");
12044 // Ahi = psrlqi(a, 32);
12045 // Bhi = psrlqi(b, 32);
12047 // AloBlo = pmuludq(a, b);
12048 // AloBhi = pmuludq(a, Bhi);
12049 // AhiBlo = pmuludq(Ahi, b);
12051 // AloBhi = psllqi(AloBhi, 32);
12052 // AhiBlo = psllqi(AhiBlo, 32);
12053 // return AloBlo + AloBhi + AhiBlo;
12055 SDValue ShAmt = DAG.getConstant(32, MVT::i32);
12057 SDValue Ahi = DAG.getNode(X86ISD::VSRLI, dl, VT, A, ShAmt);
12058 SDValue Bhi = DAG.getNode(X86ISD::VSRLI, dl, VT, B, ShAmt);
12060 // Bit cast to 32-bit vectors for MULUDQ
12061 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 : MVT::v8i32;
12062 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
12063 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
12064 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
12065 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
12067 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
12068 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
12069 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
12071 AloBhi = DAG.getNode(X86ISD::VSHLI, dl, VT, AloBhi, ShAmt);
12072 AhiBlo = DAG.getNode(X86ISD::VSHLI, dl, VT, AhiBlo, ShAmt);
12074 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
12075 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
12078 static SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) {
12079 EVT VT = Op.getValueType();
12080 EVT EltTy = VT.getVectorElementType();
12081 unsigned NumElts = VT.getVectorNumElements();
12082 SDValue N0 = Op.getOperand(0);
12085 // Lower sdiv X, pow2-const.
12086 BuildVectorSDNode *C = dyn_cast<BuildVectorSDNode>(Op.getOperand(1));
12090 APInt SplatValue, SplatUndef;
12091 unsigned SplatBitSize;
12093 if (!C->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
12095 EltTy.getSizeInBits() < SplatBitSize)
12098 if ((SplatValue != 0) &&
12099 (SplatValue.isPowerOf2() || (-SplatValue).isPowerOf2())) {
12100 unsigned lg2 = SplatValue.countTrailingZeros();
12101 // Splat the sign bit.
12102 SDValue Sz = DAG.getConstant(EltTy.getSizeInBits()-1, MVT::i32);
12103 SDValue SGN = getTargetVShiftNode(X86ISD::VSRAI, dl, VT, N0, Sz, DAG);
12104 // Add (N0 < 0) ? abs2 - 1 : 0;
12105 SDValue Amt = DAG.getConstant(EltTy.getSizeInBits() - lg2, MVT::i32);
12106 SDValue SRL = getTargetVShiftNode(X86ISD::VSRLI, dl, VT, SGN, Amt, DAG);
12107 SDValue ADD = DAG.getNode(ISD::ADD, dl, VT, N0, SRL);
12108 SDValue Lg2Amt = DAG.getConstant(lg2, MVT::i32);
12109 SDValue SRA = getTargetVShiftNode(X86ISD::VSRAI, dl, VT, ADD, Lg2Amt, DAG);
12111 // If we're dividing by a positive value, we're done. Otherwise, we must
12112 // negate the result.
12113 if (SplatValue.isNonNegative())
12116 SmallVector<SDValue, 16> V(NumElts, DAG.getConstant(0, EltTy));
12117 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], NumElts);
12118 return DAG.getNode(ISD::SUB, dl, VT, Zero, SRA);
12123 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
12124 const X86Subtarget *Subtarget) {
12125 EVT VT = Op.getValueType();
12127 SDValue R = Op.getOperand(0);
12128 SDValue Amt = Op.getOperand(1);
12130 // Optimize shl/srl/sra with constant shift amount.
12131 if (isSplatVector(Amt.getNode())) {
12132 SDValue SclrAmt = Amt->getOperand(0);
12133 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
12134 uint64_t ShiftAmt = C->getZExtValue();
12136 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
12137 (Subtarget->hasInt256() &&
12138 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16))) {
12139 if (Op.getOpcode() == ISD::SHL)
12140 return DAG.getNode(X86ISD::VSHLI, dl, VT, R,
12141 DAG.getConstant(ShiftAmt, MVT::i32));
12142 if (Op.getOpcode() == ISD::SRL)
12143 return DAG.getNode(X86ISD::VSRLI, dl, VT, R,
12144 DAG.getConstant(ShiftAmt, MVT::i32));
12145 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
12146 return DAG.getNode(X86ISD::VSRAI, dl, VT, R,
12147 DAG.getConstant(ShiftAmt, MVT::i32));
12150 if (VT == MVT::v16i8) {
12151 if (Op.getOpcode() == ISD::SHL) {
12152 // Make a large shift.
12153 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, R,
12154 DAG.getConstant(ShiftAmt, MVT::i32));
12155 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
12156 // Zero out the rightmost bits.
12157 SmallVector<SDValue, 16> V(16,
12158 DAG.getConstant(uint8_t(-1U << ShiftAmt),
12160 return DAG.getNode(ISD::AND, dl, VT, SHL,
12161 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
12163 if (Op.getOpcode() == ISD::SRL) {
12164 // Make a large shift.
12165 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v8i16, R,
12166 DAG.getConstant(ShiftAmt, MVT::i32));
12167 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
12168 // Zero out the leftmost bits.
12169 SmallVector<SDValue, 16> V(16,
12170 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
12172 return DAG.getNode(ISD::AND, dl, VT, SRL,
12173 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
12175 if (Op.getOpcode() == ISD::SRA) {
12176 if (ShiftAmt == 7) {
12177 // R s>> 7 === R s< 0
12178 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
12179 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
12182 // R s>> a === ((R u>> a) ^ m) - m
12183 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
12184 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
12186 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16);
12187 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
12188 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
12191 llvm_unreachable("Unknown shift opcode.");
12194 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
12195 if (Op.getOpcode() == ISD::SHL) {
12196 // Make a large shift.
12197 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v16i16, R,
12198 DAG.getConstant(ShiftAmt, MVT::i32));
12199 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
12200 // Zero out the rightmost bits.
12201 SmallVector<SDValue, 32> V(32,
12202 DAG.getConstant(uint8_t(-1U << ShiftAmt),
12204 return DAG.getNode(ISD::AND, dl, VT, SHL,
12205 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
12207 if (Op.getOpcode() == ISD::SRL) {
12208 // Make a large shift.
12209 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v16i16, R,
12210 DAG.getConstant(ShiftAmt, MVT::i32));
12211 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
12212 // Zero out the leftmost bits.
12213 SmallVector<SDValue, 32> V(32,
12214 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
12216 return DAG.getNode(ISD::AND, dl, VT, SRL,
12217 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
12219 if (Op.getOpcode() == ISD::SRA) {
12220 if (ShiftAmt == 7) {
12221 // R s>> 7 === R s< 0
12222 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
12223 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
12226 // R s>> a === ((R u>> a) ^ m) - m
12227 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
12228 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
12230 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32);
12231 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
12232 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
12235 llvm_unreachable("Unknown shift opcode.");
12240 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
12241 if (!Subtarget->is64Bit() &&
12242 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
12243 Amt.getOpcode() == ISD::BITCAST &&
12244 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
12245 Amt = Amt.getOperand(0);
12246 unsigned Ratio = Amt.getValueType().getVectorNumElements() /
12247 VT.getVectorNumElements();
12248 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
12249 uint64_t ShiftAmt = 0;
12250 for (unsigned i = 0; i != Ratio; ++i) {
12251 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
12255 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
12257 // Check remaining shift amounts.
12258 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
12259 uint64_t ShAmt = 0;
12260 for (unsigned j = 0; j != Ratio; ++j) {
12261 ConstantSDNode *C =
12262 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
12266 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
12268 if (ShAmt != ShiftAmt)
12271 switch (Op.getOpcode()) {
12273 llvm_unreachable("Unknown shift opcode!");
12275 return DAG.getNode(X86ISD::VSHLI, dl, VT, R,
12276 DAG.getConstant(ShiftAmt, MVT::i32));
12278 return DAG.getNode(X86ISD::VSRLI, dl, VT, R,
12279 DAG.getConstant(ShiftAmt, MVT::i32));
12281 return DAG.getNode(X86ISD::VSRAI, dl, VT, R,
12282 DAG.getConstant(ShiftAmt, MVT::i32));
12289 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
12290 const X86Subtarget* Subtarget) {
12291 EVT VT = Op.getValueType();
12293 SDValue R = Op.getOperand(0);
12294 SDValue Amt = Op.getOperand(1);
12296 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
12297 VT == MVT::v4i32 || VT == MVT::v8i16 ||
12298 (Subtarget->hasInt256() &&
12299 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
12300 VT == MVT::v8i32 || VT == MVT::v16i16))) {
12302 EVT EltVT = VT.getVectorElementType();
12304 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
12305 unsigned NumElts = VT.getVectorNumElements();
12307 for (i = 0; i != NumElts; ++i) {
12308 if (Amt.getOperand(i).getOpcode() == ISD::UNDEF)
12312 for (j = i; j != NumElts; ++j) {
12313 SDValue Arg = Amt.getOperand(j);
12314 if (Arg.getOpcode() == ISD::UNDEF) continue;
12315 if (Arg != Amt.getOperand(i))
12318 if (i != NumElts && j == NumElts)
12319 BaseShAmt = Amt.getOperand(i);
12321 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
12322 Amt = Amt.getOperand(0);
12323 if (Amt.getOpcode() == ISD::VECTOR_SHUFFLE &&
12324 cast<ShuffleVectorSDNode>(Amt)->isSplat()) {
12325 SDValue InVec = Amt.getOperand(0);
12326 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
12327 unsigned NumElts = InVec.getValueType().getVectorNumElements();
12329 for (; i != NumElts; ++i) {
12330 SDValue Arg = InVec.getOperand(i);
12331 if (Arg.getOpcode() == ISD::UNDEF) continue;
12335 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
12336 if (ConstantSDNode *C =
12337 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
12338 unsigned SplatIdx =
12339 cast<ShuffleVectorSDNode>(Amt)->getSplatIndex();
12340 if (C->getZExtValue() == SplatIdx)
12341 BaseShAmt = InVec.getOperand(1);
12344 if (BaseShAmt.getNode() == 0)
12345 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Amt,
12346 DAG.getIntPtrConstant(0));
12350 if (BaseShAmt.getNode()) {
12351 if (EltVT.bitsGT(MVT::i32))
12352 BaseShAmt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BaseShAmt);
12353 else if (EltVT.bitsLT(MVT::i32))
12354 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
12356 switch (Op.getOpcode()) {
12358 llvm_unreachable("Unknown shift opcode!");
12360 switch (VT.getSimpleVT().SimpleTy) {
12361 default: return SDValue();
12368 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
12371 switch (VT.getSimpleVT().SimpleTy) {
12372 default: return SDValue();
12377 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
12380 switch (VT.getSimpleVT().SimpleTy) {
12381 default: return SDValue();
12388 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
12394 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
12395 if (!Subtarget->is64Bit() &&
12396 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
12397 Amt.getOpcode() == ISD::BITCAST &&
12398 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
12399 Amt = Amt.getOperand(0);
12400 unsigned Ratio = Amt.getValueType().getVectorNumElements() /
12401 VT.getVectorNumElements();
12402 std::vector<SDValue> Vals(Ratio);
12403 for (unsigned i = 0; i != Ratio; ++i)
12404 Vals[i] = Amt.getOperand(i);
12405 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
12406 for (unsigned j = 0; j != Ratio; ++j)
12407 if (Vals[j] != Amt.getOperand(i + j))
12410 switch (Op.getOpcode()) {
12412 llvm_unreachable("Unknown shift opcode!");
12414 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
12416 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
12418 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
12425 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
12426 SelectionDAG &DAG) {
12428 EVT VT = Op.getValueType();
12430 SDValue R = Op.getOperand(0);
12431 SDValue Amt = Op.getOperand(1);
12434 if (!Subtarget->hasSSE2())
12437 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
12441 V = LowerScalarVariableShift(Op, DAG, Subtarget);
12445 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
12446 if (Subtarget->hasInt256()) {
12447 if (Op.getOpcode() == ISD::SRL &&
12448 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
12449 VT == MVT::v4i64 || VT == MVT::v8i32))
12451 if (Op.getOpcode() == ISD::SHL &&
12452 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
12453 VT == MVT::v4i64 || VT == MVT::v8i32))
12455 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
12459 // Lower SHL with variable shift amount.
12460 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
12461 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
12463 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
12464 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
12465 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
12466 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
12468 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
12469 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
12472 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
12473 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
12475 // Turn 'a' into a mask suitable for VSELECT
12476 SDValue VSelM = DAG.getConstant(0x80, VT);
12477 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
12478 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
12480 SDValue CM1 = DAG.getConstant(0x0f, VT);
12481 SDValue CM2 = DAG.getConstant(0x3f, VT);
12483 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
12484 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
12485 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M,
12486 DAG.getConstant(4, MVT::i32), DAG);
12487 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
12488 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
12491 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
12492 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
12493 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
12495 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
12496 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
12497 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M,
12498 DAG.getConstant(2, MVT::i32), DAG);
12499 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
12500 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
12503 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
12504 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
12505 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
12507 // return VSELECT(r, r+r, a);
12508 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
12509 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
12513 // Decompose 256-bit shifts into smaller 128-bit shifts.
12514 if (VT.is256BitVector()) {
12515 unsigned NumElems = VT.getVectorNumElements();
12516 MVT EltVT = VT.getVectorElementType().getSimpleVT();
12517 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
12519 // Extract the two vectors
12520 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
12521 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
12523 // Recreate the shift amount vectors
12524 SDValue Amt1, Amt2;
12525 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
12526 // Constant shift amount
12527 SmallVector<SDValue, 4> Amt1Csts;
12528 SmallVector<SDValue, 4> Amt2Csts;
12529 for (unsigned i = 0; i != NumElems/2; ++i)
12530 Amt1Csts.push_back(Amt->getOperand(i));
12531 for (unsigned i = NumElems/2; i != NumElems; ++i)
12532 Amt2Csts.push_back(Amt->getOperand(i));
12534 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
12535 &Amt1Csts[0], NumElems/2);
12536 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
12537 &Amt2Csts[0], NumElems/2);
12539 // Variable shift amount
12540 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
12541 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
12544 // Issue new vector shifts for the smaller types
12545 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
12546 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
12548 // Concatenate the result back
12549 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
12555 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
12556 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
12557 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
12558 // looks for this combo and may remove the "setcc" instruction if the "setcc"
12559 // has only one use.
12560 SDNode *N = Op.getNode();
12561 SDValue LHS = N->getOperand(0);
12562 SDValue RHS = N->getOperand(1);
12563 unsigned BaseOp = 0;
12566 switch (Op.getOpcode()) {
12567 default: llvm_unreachable("Unknown ovf instruction!");
12569 // A subtract of one will be selected as a INC. Note that INC doesn't
12570 // set CF, so we can't do this for UADDO.
12571 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
12573 BaseOp = X86ISD::INC;
12574 Cond = X86::COND_O;
12577 BaseOp = X86ISD::ADD;
12578 Cond = X86::COND_O;
12581 BaseOp = X86ISD::ADD;
12582 Cond = X86::COND_B;
12585 // A subtract of one will be selected as a DEC. Note that DEC doesn't
12586 // set CF, so we can't do this for USUBO.
12587 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
12589 BaseOp = X86ISD::DEC;
12590 Cond = X86::COND_O;
12593 BaseOp = X86ISD::SUB;
12594 Cond = X86::COND_O;
12597 BaseOp = X86ISD::SUB;
12598 Cond = X86::COND_B;
12601 BaseOp = X86ISD::SMUL;
12602 Cond = X86::COND_O;
12604 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
12605 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
12607 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
12610 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
12611 DAG.getConstant(X86::COND_O, MVT::i32),
12612 SDValue(Sum.getNode(), 2));
12614 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
12618 // Also sets EFLAGS.
12619 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
12620 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
12623 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
12624 DAG.getConstant(Cond, MVT::i32),
12625 SDValue(Sum.getNode(), 1));
12627 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
12630 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
12631 SelectionDAG &DAG) const {
12633 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
12634 EVT VT = Op.getValueType();
12636 if (!Subtarget->hasSSE2() || !VT.isVector())
12639 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
12640 ExtraVT.getScalarType().getSizeInBits();
12641 SDValue ShAmt = DAG.getConstant(BitsDiff, MVT::i32);
12643 switch (VT.getSimpleVT().SimpleTy) {
12644 default: return SDValue();
12647 if (!Subtarget->hasFp256())
12649 if (!Subtarget->hasInt256()) {
12650 // needs to be split
12651 unsigned NumElems = VT.getVectorNumElements();
12653 // Extract the LHS vectors
12654 SDValue LHS = Op.getOperand(0);
12655 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
12656 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
12658 MVT EltVT = VT.getVectorElementType().getSimpleVT();
12659 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
12661 EVT ExtraEltVT = ExtraVT.getVectorElementType();
12662 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
12663 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
12665 SDValue Extra = DAG.getValueType(ExtraVT);
12667 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
12668 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
12670 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
12675 // (sext (vzext x)) -> (vsext x)
12676 SDValue Op0 = Op.getOperand(0);
12677 SDValue Op00 = Op0.getOperand(0);
12679 // Hopefully, this VECTOR_SHUFFLE is just a VZEXT.
12680 if (Op0.getOpcode() == ISD::BITCAST &&
12681 Op00.getOpcode() == ISD::VECTOR_SHUFFLE)
12682 Tmp1 = LowerVectorIntExtend(Op00, Subtarget, DAG);
12683 if (Tmp1.getNode()) {
12684 SDValue Tmp1Op0 = Tmp1.getOperand(0);
12685 assert(Tmp1Op0.getOpcode() == X86ISD::VZEXT &&
12686 "This optimization is invalid without a VZEXT.");
12687 return DAG.getNode(X86ISD::VSEXT, dl, VT, Tmp1Op0.getOperand(0));
12690 // If the above didn't work, then just use Shift-Left + Shift-Right.
12691 Tmp1 = getTargetVShiftNode(X86ISD::VSHLI, dl, VT, Op0, ShAmt, DAG);
12692 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, Tmp1, ShAmt, DAG);
12697 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
12698 SelectionDAG &DAG) {
12700 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
12701 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
12702 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
12703 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
12705 // The only fence that needs an instruction is a sequentially-consistent
12706 // cross-thread fence.
12707 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
12708 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
12709 // no-sse2). There isn't any reason to disable it if the target processor
12711 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
12712 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
12714 SDValue Chain = Op.getOperand(0);
12715 SDValue Zero = DAG.getConstant(0, MVT::i32);
12717 DAG.getRegister(X86::ESP, MVT::i32), // Base
12718 DAG.getTargetConstant(1, MVT::i8), // Scale
12719 DAG.getRegister(0, MVT::i32), // Index
12720 DAG.getTargetConstant(0, MVT::i32), // Disp
12721 DAG.getRegister(0, MVT::i32), // Segment.
12725 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
12726 return SDValue(Res, 0);
12729 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
12730 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
12733 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
12734 SelectionDAG &DAG) {
12735 EVT T = Op.getValueType();
12739 switch(T.getSimpleVT().SimpleTy) {
12740 default: llvm_unreachable("Invalid value type!");
12741 case MVT::i8: Reg = X86::AL; size = 1; break;
12742 case MVT::i16: Reg = X86::AX; size = 2; break;
12743 case MVT::i32: Reg = X86::EAX; size = 4; break;
12745 assert(Subtarget->is64Bit() && "Node not type legal!");
12746 Reg = X86::RAX; size = 8;
12749 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
12750 Op.getOperand(2), SDValue());
12751 SDValue Ops[] = { cpIn.getValue(0),
12754 DAG.getTargetConstant(size, MVT::i8),
12755 cpIn.getValue(1) };
12756 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
12757 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
12758 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
12759 Ops, array_lengthof(Ops), T, MMO);
12761 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
12765 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
12766 SelectionDAG &DAG) {
12767 assert(Subtarget->is64Bit() && "Result not type legalized?");
12768 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
12769 SDValue TheChain = Op.getOperand(0);
12771 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
12772 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
12773 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
12775 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
12776 DAG.getConstant(32, MVT::i8));
12778 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
12781 return DAG.getMergeValues(Ops, array_lengthof(Ops), dl);
12784 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
12785 SelectionDAG &DAG) {
12786 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
12787 MVT DstVT = Op.getSimpleValueType();
12788 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
12789 Subtarget->hasMMX() && "Unexpected custom BITCAST");
12790 assert((DstVT == MVT::i64 ||
12791 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
12792 "Unexpected custom BITCAST");
12793 // i64 <=> MMX conversions are Legal.
12794 if (SrcVT==MVT::i64 && DstVT.isVector())
12796 if (DstVT==MVT::i64 && SrcVT.isVector())
12798 // MMX <=> MMX conversions are Legal.
12799 if (SrcVT.isVector() && DstVT.isVector())
12801 // All other conversions need to be expanded.
12805 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
12806 SDNode *Node = Op.getNode();
12808 EVT T = Node->getValueType(0);
12809 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
12810 DAG.getConstant(0, T), Node->getOperand(2));
12811 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
12812 cast<AtomicSDNode>(Node)->getMemoryVT(),
12813 Node->getOperand(0),
12814 Node->getOperand(1), negOp,
12815 cast<AtomicSDNode>(Node)->getSrcValue(),
12816 cast<AtomicSDNode>(Node)->getAlignment(),
12817 cast<AtomicSDNode>(Node)->getOrdering(),
12818 cast<AtomicSDNode>(Node)->getSynchScope());
12821 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
12822 SDNode *Node = Op.getNode();
12824 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
12826 // Convert seq_cst store -> xchg
12827 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
12828 // FIXME: On 32-bit, store -> fist or movq would be more efficient
12829 // (The only way to get a 16-byte store is cmpxchg16b)
12830 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
12831 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
12832 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
12833 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
12834 cast<AtomicSDNode>(Node)->getMemoryVT(),
12835 Node->getOperand(0),
12836 Node->getOperand(1), Node->getOperand(2),
12837 cast<AtomicSDNode>(Node)->getMemOperand(),
12838 cast<AtomicSDNode>(Node)->getOrdering(),
12839 cast<AtomicSDNode>(Node)->getSynchScope());
12840 return Swap.getValue(1);
12842 // Other atomic stores have a simple pattern.
12846 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
12847 EVT VT = Op.getNode()->getValueType(0);
12849 // Let legalize expand this if it isn't a legal type yet.
12850 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
12853 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
12856 bool ExtraOp = false;
12857 switch (Op.getOpcode()) {
12858 default: llvm_unreachable("Invalid code");
12859 case ISD::ADDC: Opc = X86ISD::ADD; break;
12860 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
12861 case ISD::SUBC: Opc = X86ISD::SUB; break;
12862 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
12866 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
12868 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
12869 Op.getOperand(1), Op.getOperand(2));
12872 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
12873 SelectionDAG &DAG) {
12874 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
12876 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
12877 // which returns the values as { float, float } (in XMM0) or
12878 // { double, double } (which is returned in XMM0, XMM1).
12880 SDValue Arg = Op.getOperand(0);
12881 EVT ArgVT = Arg.getValueType();
12882 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
12884 TargetLowering::ArgListTy Args;
12885 TargetLowering::ArgListEntry Entry;
12889 Entry.isSExt = false;
12890 Entry.isZExt = false;
12891 Args.push_back(Entry);
12893 bool isF64 = ArgVT == MVT::f64;
12894 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
12895 // the small struct {f32, f32} is returned in (eax, edx). For f64,
12896 // the results are returned via SRet in memory.
12897 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
12898 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12899 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
12901 Type *RetTy = isF64
12902 ? (Type*)StructType::get(ArgTy, ArgTy, NULL)
12903 : (Type*)VectorType::get(ArgTy, 4);
12905 CallLoweringInfo CLI(DAG.getEntryNode(), RetTy,
12906 false, false, false, false, 0,
12907 CallingConv::C, /*isTaillCall=*/false,
12908 /*doesNotRet=*/false, /*isReturnValueUsed*/true,
12909 Callee, Args, DAG, dl);
12910 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
12913 // Returned in xmm0 and xmm1.
12914 return CallResult.first;
12916 // Returned in bits 0:31 and 32:64 xmm0.
12917 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
12918 CallResult.first, DAG.getIntPtrConstant(0));
12919 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
12920 CallResult.first, DAG.getIntPtrConstant(1));
12921 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
12922 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
12925 /// LowerOperation - Provide custom lowering hooks for some operations.
12927 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
12928 switch (Op.getOpcode()) {
12929 default: llvm_unreachable("Should not custom lower this!");
12930 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
12931 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
12932 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op, Subtarget, DAG);
12933 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
12934 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
12935 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
12936 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
12937 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
12938 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
12939 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
12940 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
12941 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
12942 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
12943 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
12944 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
12945 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
12946 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
12947 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
12948 case ISD::SHL_PARTS:
12949 case ISD::SRA_PARTS:
12950 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
12951 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
12952 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
12953 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
12954 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
12955 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
12956 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
12957 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
12958 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
12959 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
12960 case ISD::FABS: return LowerFABS(Op, DAG);
12961 case ISD::FNEG: return LowerFNEG(Op, DAG);
12962 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
12963 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
12964 case ISD::SETCC: return LowerSETCC(Op, DAG);
12965 case ISD::SELECT: return LowerSELECT(Op, DAG);
12966 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
12967 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
12968 case ISD::VASTART: return LowerVASTART(Op, DAG);
12969 case ISD::VAARG: return LowerVAARG(Op, DAG);
12970 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
12971 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
12972 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, DAG);
12973 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
12974 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
12975 case ISD::FRAME_TO_ARGS_OFFSET:
12976 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
12977 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
12978 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
12979 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
12980 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
12981 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
12982 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
12983 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
12984 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
12985 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
12986 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
12987 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
12990 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
12996 case ISD::UMULO: return LowerXALUO(Op, DAG);
12997 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
12998 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
13002 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
13003 case ISD::ADD: return LowerADD(Op, DAG);
13004 case ISD::SUB: return LowerSUB(Op, DAG);
13005 case ISD::SDIV: return LowerSDIV(Op, DAG);
13006 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
13010 static void ReplaceATOMIC_LOAD(SDNode *Node,
13011 SmallVectorImpl<SDValue> &Results,
13012 SelectionDAG &DAG) {
13014 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
13016 // Convert wide load -> cmpxchg8b/cmpxchg16b
13017 // FIXME: On 32-bit, load -> fild or movq would be more efficient
13018 // (The only way to get a 16-byte load is cmpxchg16b)
13019 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
13020 SDValue Zero = DAG.getConstant(0, VT);
13021 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT,
13022 Node->getOperand(0),
13023 Node->getOperand(1), Zero, Zero,
13024 cast<AtomicSDNode>(Node)->getMemOperand(),
13025 cast<AtomicSDNode>(Node)->getOrdering(),
13026 cast<AtomicSDNode>(Node)->getSynchScope());
13027 Results.push_back(Swap.getValue(0));
13028 Results.push_back(Swap.getValue(1));
13032 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
13033 SelectionDAG &DAG, unsigned NewOp) {
13035 assert (Node->getValueType(0) == MVT::i64 &&
13036 "Only know how to expand i64 atomics");
13038 SDValue Chain = Node->getOperand(0);
13039 SDValue In1 = Node->getOperand(1);
13040 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
13041 Node->getOperand(2), DAG.getIntPtrConstant(0));
13042 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
13043 Node->getOperand(2), DAG.getIntPtrConstant(1));
13044 SDValue Ops[] = { Chain, In1, In2L, In2H };
13045 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
13047 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, array_lengthof(Ops), MVT::i64,
13048 cast<MemSDNode>(Node)->getMemOperand());
13049 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
13050 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
13051 Results.push_back(Result.getValue(2));
13054 /// ReplaceNodeResults - Replace a node with an illegal result type
13055 /// with a new node built out of custom code.
13056 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
13057 SmallVectorImpl<SDValue>&Results,
13058 SelectionDAG &DAG) const {
13060 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13061 switch (N->getOpcode()) {
13063 llvm_unreachable("Do not know how to custom type legalize this operation!");
13064 case ISD::SIGN_EXTEND_INREG:
13069 // We don't want to expand or promote these.
13071 case ISD::FP_TO_SINT:
13072 case ISD::FP_TO_UINT: {
13073 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
13075 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
13078 std::pair<SDValue,SDValue> Vals =
13079 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
13080 SDValue FIST = Vals.first, StackSlot = Vals.second;
13081 if (FIST.getNode() != 0) {
13082 EVT VT = N->getValueType(0);
13083 // Return a load from the stack slot.
13084 if (StackSlot.getNode() != 0)
13085 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
13086 MachinePointerInfo(),
13087 false, false, false, 0));
13089 Results.push_back(FIST);
13093 case ISD::UINT_TO_FP: {
13094 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
13095 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
13096 N->getValueType(0) != MVT::v2f32)
13098 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
13100 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
13102 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
13103 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
13104 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
13105 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
13106 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
13107 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
13110 case ISD::FP_ROUND: {
13111 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
13113 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
13114 Results.push_back(V);
13117 case ISD::READCYCLECOUNTER: {
13118 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
13119 SDValue TheChain = N->getOperand(0);
13120 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
13121 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
13123 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
13125 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
13126 SDValue Ops[] = { eax, edx };
13127 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops,
13128 array_lengthof(Ops)));
13129 Results.push_back(edx.getValue(1));
13132 case ISD::ATOMIC_CMP_SWAP: {
13133 EVT T = N->getValueType(0);
13134 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
13135 bool Regs64bit = T == MVT::i128;
13136 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
13137 SDValue cpInL, cpInH;
13138 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
13139 DAG.getConstant(0, HalfT));
13140 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
13141 DAG.getConstant(1, HalfT));
13142 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
13143 Regs64bit ? X86::RAX : X86::EAX,
13145 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
13146 Regs64bit ? X86::RDX : X86::EDX,
13147 cpInH, cpInL.getValue(1));
13148 SDValue swapInL, swapInH;
13149 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
13150 DAG.getConstant(0, HalfT));
13151 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
13152 DAG.getConstant(1, HalfT));
13153 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
13154 Regs64bit ? X86::RBX : X86::EBX,
13155 swapInL, cpInH.getValue(1));
13156 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
13157 Regs64bit ? X86::RCX : X86::ECX,
13158 swapInH, swapInL.getValue(1));
13159 SDValue Ops[] = { swapInH.getValue(0),
13161 swapInH.getValue(1) };
13162 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
13163 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
13164 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
13165 X86ISD::LCMPXCHG8_DAG;
13166 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys,
13167 Ops, array_lengthof(Ops), T, MMO);
13168 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
13169 Regs64bit ? X86::RAX : X86::EAX,
13170 HalfT, Result.getValue(1));
13171 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
13172 Regs64bit ? X86::RDX : X86::EDX,
13173 HalfT, cpOutL.getValue(2));
13174 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
13175 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2));
13176 Results.push_back(cpOutH.getValue(1));
13179 case ISD::ATOMIC_LOAD_ADD:
13180 case ISD::ATOMIC_LOAD_AND:
13181 case ISD::ATOMIC_LOAD_NAND:
13182 case ISD::ATOMIC_LOAD_OR:
13183 case ISD::ATOMIC_LOAD_SUB:
13184 case ISD::ATOMIC_LOAD_XOR:
13185 case ISD::ATOMIC_LOAD_MAX:
13186 case ISD::ATOMIC_LOAD_MIN:
13187 case ISD::ATOMIC_LOAD_UMAX:
13188 case ISD::ATOMIC_LOAD_UMIN:
13189 case ISD::ATOMIC_SWAP: {
13191 switch (N->getOpcode()) {
13192 default: llvm_unreachable("Unexpected opcode");
13193 case ISD::ATOMIC_LOAD_ADD:
13194 Opc = X86ISD::ATOMADD64_DAG;
13196 case ISD::ATOMIC_LOAD_AND:
13197 Opc = X86ISD::ATOMAND64_DAG;
13199 case ISD::ATOMIC_LOAD_NAND:
13200 Opc = X86ISD::ATOMNAND64_DAG;
13202 case ISD::ATOMIC_LOAD_OR:
13203 Opc = X86ISD::ATOMOR64_DAG;
13205 case ISD::ATOMIC_LOAD_SUB:
13206 Opc = X86ISD::ATOMSUB64_DAG;
13208 case ISD::ATOMIC_LOAD_XOR:
13209 Opc = X86ISD::ATOMXOR64_DAG;
13211 case ISD::ATOMIC_LOAD_MAX:
13212 Opc = X86ISD::ATOMMAX64_DAG;
13214 case ISD::ATOMIC_LOAD_MIN:
13215 Opc = X86ISD::ATOMMIN64_DAG;
13217 case ISD::ATOMIC_LOAD_UMAX:
13218 Opc = X86ISD::ATOMUMAX64_DAG;
13220 case ISD::ATOMIC_LOAD_UMIN:
13221 Opc = X86ISD::ATOMUMIN64_DAG;
13223 case ISD::ATOMIC_SWAP:
13224 Opc = X86ISD::ATOMSWAP64_DAG;
13227 ReplaceATOMIC_BINARY_64(N, Results, DAG, Opc);
13230 case ISD::ATOMIC_LOAD:
13231 ReplaceATOMIC_LOAD(N, Results, DAG);
13235 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
13237 default: return NULL;
13238 case X86ISD::BSF: return "X86ISD::BSF";
13239 case X86ISD::BSR: return "X86ISD::BSR";
13240 case X86ISD::SHLD: return "X86ISD::SHLD";
13241 case X86ISD::SHRD: return "X86ISD::SHRD";
13242 case X86ISD::FAND: return "X86ISD::FAND";
13243 case X86ISD::FANDN: return "X86ISD::FANDN";
13244 case X86ISD::FOR: return "X86ISD::FOR";
13245 case X86ISD::FXOR: return "X86ISD::FXOR";
13246 case X86ISD::FSRL: return "X86ISD::FSRL";
13247 case X86ISD::FILD: return "X86ISD::FILD";
13248 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
13249 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
13250 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
13251 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
13252 case X86ISD::FLD: return "X86ISD::FLD";
13253 case X86ISD::FST: return "X86ISD::FST";
13254 case X86ISD::CALL: return "X86ISD::CALL";
13255 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
13256 case X86ISD::BT: return "X86ISD::BT";
13257 case X86ISD::CMP: return "X86ISD::CMP";
13258 case X86ISD::COMI: return "X86ISD::COMI";
13259 case X86ISD::UCOMI: return "X86ISD::UCOMI";
13260 case X86ISD::CMPM: return "X86ISD::CMPM";
13261 case X86ISD::CMPMU: return "X86ISD::CMPMU";
13262 case X86ISD::SETCC: return "X86ISD::SETCC";
13263 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
13264 case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd";
13265 case X86ISD::FSETCCss: return "X86ISD::FSETCCss";
13266 case X86ISD::CMOV: return "X86ISD::CMOV";
13267 case X86ISD::BRCOND: return "X86ISD::BRCOND";
13268 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
13269 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
13270 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
13271 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
13272 case X86ISD::Wrapper: return "X86ISD::Wrapper";
13273 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
13274 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
13275 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
13276 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
13277 case X86ISD::PINSRB: return "X86ISD::PINSRB";
13278 case X86ISD::PINSRW: return "X86ISD::PINSRW";
13279 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
13280 case X86ISD::ANDNP: return "X86ISD::ANDNP";
13281 case X86ISD::PSIGN: return "X86ISD::PSIGN";
13282 case X86ISD::BLENDV: return "X86ISD::BLENDV";
13283 case X86ISD::BLENDI: return "X86ISD::BLENDI";
13284 case X86ISD::SUBUS: return "X86ISD::SUBUS";
13285 case X86ISD::HADD: return "X86ISD::HADD";
13286 case X86ISD::HSUB: return "X86ISD::HSUB";
13287 case X86ISD::FHADD: return "X86ISD::FHADD";
13288 case X86ISD::FHSUB: return "X86ISD::FHSUB";
13289 case X86ISD::UMAX: return "X86ISD::UMAX";
13290 case X86ISD::UMIN: return "X86ISD::UMIN";
13291 case X86ISD::SMAX: return "X86ISD::SMAX";
13292 case X86ISD::SMIN: return "X86ISD::SMIN";
13293 case X86ISD::FMAX: return "X86ISD::FMAX";
13294 case X86ISD::FMIN: return "X86ISD::FMIN";
13295 case X86ISD::FMAXC: return "X86ISD::FMAXC";
13296 case X86ISD::FMINC: return "X86ISD::FMINC";
13297 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
13298 case X86ISD::FRCP: return "X86ISD::FRCP";
13299 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
13300 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
13301 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
13302 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
13303 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
13304 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
13305 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
13306 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
13307 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
13308 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
13309 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
13310 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
13311 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
13312 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
13313 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
13314 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
13315 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
13316 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
13317 case X86ISD::VSEXT_MOVL: return "X86ISD::VSEXT_MOVL";
13318 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
13319 case X86ISD::VZEXT: return "X86ISD::VZEXT";
13320 case X86ISD::VSEXT: return "X86ISD::VSEXT";
13321 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
13322 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
13323 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
13324 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
13325 case X86ISD::VSHL: return "X86ISD::VSHL";
13326 case X86ISD::VSRL: return "X86ISD::VSRL";
13327 case X86ISD::VSRA: return "X86ISD::VSRA";
13328 case X86ISD::VSHLI: return "X86ISD::VSHLI";
13329 case X86ISD::VSRLI: return "X86ISD::VSRLI";
13330 case X86ISD::VSRAI: return "X86ISD::VSRAI";
13331 case X86ISD::CMPP: return "X86ISD::CMPP";
13332 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
13333 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
13334 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
13335 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
13336 case X86ISD::ADD: return "X86ISD::ADD";
13337 case X86ISD::SUB: return "X86ISD::SUB";
13338 case X86ISD::ADC: return "X86ISD::ADC";
13339 case X86ISD::SBB: return "X86ISD::SBB";
13340 case X86ISD::SMUL: return "X86ISD::SMUL";
13341 case X86ISD::UMUL: return "X86ISD::UMUL";
13342 case X86ISD::INC: return "X86ISD::INC";
13343 case X86ISD::DEC: return "X86ISD::DEC";
13344 case X86ISD::OR: return "X86ISD::OR";
13345 case X86ISD::XOR: return "X86ISD::XOR";
13346 case X86ISD::AND: return "X86ISD::AND";
13347 case X86ISD::BLSI: return "X86ISD::BLSI";
13348 case X86ISD::BLSMSK: return "X86ISD::BLSMSK";
13349 case X86ISD::BLSR: return "X86ISD::BLSR";
13350 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
13351 case X86ISD::PTEST: return "X86ISD::PTEST";
13352 case X86ISD::TESTP: return "X86ISD::TESTP";
13353 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
13354 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
13355 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
13356 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
13357 case X86ISD::SHUFP: return "X86ISD::SHUFP";
13358 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
13359 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
13360 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
13361 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
13362 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
13363 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
13364 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
13365 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
13366 case X86ISD::MOVSD: return "X86ISD::MOVSD";
13367 case X86ISD::MOVSS: return "X86ISD::MOVSS";
13368 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
13369 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
13370 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
13371 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
13372 case X86ISD::VPERMILP: return "X86ISD::VPERMILP";
13373 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
13374 case X86ISD::VPERMV: return "X86ISD::VPERMV";
13375 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
13376 case X86ISD::VPERMI: return "X86ISD::VPERMI";
13377 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
13378 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
13379 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
13380 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
13381 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
13382 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
13383 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
13384 case X86ISD::SAHF: return "X86ISD::SAHF";
13385 case X86ISD::RDRAND: return "X86ISD::RDRAND";
13386 case X86ISD::RDSEED: return "X86ISD::RDSEED";
13387 case X86ISD::FMADD: return "X86ISD::FMADD";
13388 case X86ISD::FMSUB: return "X86ISD::FMSUB";
13389 case X86ISD::FNMADD: return "X86ISD::FNMADD";
13390 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
13391 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
13392 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
13393 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
13394 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
13395 case X86ISD::XTEST: return "X86ISD::XTEST";
13399 // isLegalAddressingMode - Return true if the addressing mode represented
13400 // by AM is legal for this target, for a load/store of the specified type.
13401 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
13403 // X86 supports extremely general addressing modes.
13404 CodeModel::Model M = getTargetMachine().getCodeModel();
13405 Reloc::Model R = getTargetMachine().getRelocationModel();
13407 // X86 allows a sign-extended 32-bit immediate field as a displacement.
13408 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
13413 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
13415 // If a reference to this global requires an extra load, we can't fold it.
13416 if (isGlobalStubReference(GVFlags))
13419 // If BaseGV requires a register for the PIC base, we cannot also have a
13420 // BaseReg specified.
13421 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
13424 // If lower 4G is not available, then we must use rip-relative addressing.
13425 if ((M != CodeModel::Small || R != Reloc::Static) &&
13426 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
13430 switch (AM.Scale) {
13436 // These scales always work.
13441 // These scales are formed with basereg+scalereg. Only accept if there is
13446 default: // Other stuff never works.
13453 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
13454 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
13456 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
13457 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
13458 return NumBits1 > NumBits2;
13461 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
13462 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
13465 if (!isTypeLegal(EVT::getEVT(Ty1)))
13468 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
13470 // Assuming the caller doesn't have a zeroext or signext return parameter,
13471 // truncation all the way down to i1 is valid.
13475 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
13476 return isInt<32>(Imm);
13479 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
13480 // Can also use sub to handle negated immediates.
13481 return isInt<32>(Imm);
13484 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
13485 if (!VT1.isInteger() || !VT2.isInteger())
13487 unsigned NumBits1 = VT1.getSizeInBits();
13488 unsigned NumBits2 = VT2.getSizeInBits();
13489 return NumBits1 > NumBits2;
13492 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
13493 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
13494 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
13497 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
13498 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
13499 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
13502 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
13503 EVT VT1 = Val.getValueType();
13504 if (isZExtFree(VT1, VT2))
13507 if (Val.getOpcode() != ISD::LOAD)
13510 if (!VT1.isSimple() || !VT1.isInteger() ||
13511 !VT2.isSimple() || !VT2.isInteger())
13514 switch (VT1.getSimpleVT().SimpleTy) {
13519 // X86 has 8, 16, and 32-bit zero-extending loads.
13527 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
13528 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
13531 VT = VT.getScalarType();
13533 if (!VT.isSimple())
13536 switch (VT.getSimpleVT().SimpleTy) {
13547 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
13548 // i16 instructions are longer (0x66 prefix) and potentially slower.
13549 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
13552 /// isShuffleMaskLegal - Targets can use this to indicate that they only
13553 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
13554 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
13555 /// are assumed to be legal.
13557 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
13559 if (!VT.isSimple())
13562 MVT SVT = VT.getSimpleVT();
13564 // Very little shuffling can be done for 64-bit vectors right now.
13565 if (VT.getSizeInBits() == 64)
13568 // FIXME: pshufb, blends, shifts.
13569 return (SVT.getVectorNumElements() == 2 ||
13570 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
13571 isMOVLMask(M, SVT) ||
13572 isSHUFPMask(M, SVT, Subtarget->hasFp256()) ||
13573 isPSHUFDMask(M, SVT) ||
13574 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
13575 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
13576 isPALIGNRMask(M, SVT, Subtarget) ||
13577 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
13578 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
13579 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
13580 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()));
13584 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
13586 if (!VT.isSimple())
13589 MVT SVT = VT.getSimpleVT();
13590 unsigned NumElts = SVT.getVectorNumElements();
13591 // FIXME: This collection of masks seems suspect.
13594 if (NumElts == 4 && SVT.is128BitVector()) {
13595 return (isMOVLMask(Mask, SVT) ||
13596 isCommutedMOVLMask(Mask, SVT, true) ||
13597 isSHUFPMask(Mask, SVT, Subtarget->hasFp256()) ||
13598 isSHUFPMask(Mask, SVT, Subtarget->hasFp256(), /* Commuted */ true));
13603 //===----------------------------------------------------------------------===//
13604 // X86 Scheduler Hooks
13605 //===----------------------------------------------------------------------===//
13607 /// Utility function to emit xbegin specifying the start of an RTM region.
13608 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
13609 const TargetInstrInfo *TII) {
13610 DebugLoc DL = MI->getDebugLoc();
13612 const BasicBlock *BB = MBB->getBasicBlock();
13613 MachineFunction::iterator I = MBB;
13616 // For the v = xbegin(), we generate
13627 MachineBasicBlock *thisMBB = MBB;
13628 MachineFunction *MF = MBB->getParent();
13629 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
13630 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
13631 MF->insert(I, mainMBB);
13632 MF->insert(I, sinkMBB);
13634 // Transfer the remainder of BB and its successor edges to sinkMBB.
13635 sinkMBB->splice(sinkMBB->begin(), MBB,
13636 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
13637 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
13641 // # fallthrough to mainMBB
13642 // # abortion to sinkMBB
13643 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
13644 thisMBB->addSuccessor(mainMBB);
13645 thisMBB->addSuccessor(sinkMBB);
13649 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
13650 mainMBB->addSuccessor(sinkMBB);
13653 // EAX is live into the sinkMBB
13654 sinkMBB->addLiveIn(X86::EAX);
13655 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
13656 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
13659 MI->eraseFromParent();
13663 // Get CMPXCHG opcode for the specified data type.
13664 static unsigned getCmpXChgOpcode(EVT VT) {
13665 switch (VT.getSimpleVT().SimpleTy) {
13666 case MVT::i8: return X86::LCMPXCHG8;
13667 case MVT::i16: return X86::LCMPXCHG16;
13668 case MVT::i32: return X86::LCMPXCHG32;
13669 case MVT::i64: return X86::LCMPXCHG64;
13673 llvm_unreachable("Invalid operand size!");
13676 // Get LOAD opcode for the specified data type.
13677 static unsigned getLoadOpcode(EVT VT) {
13678 switch (VT.getSimpleVT().SimpleTy) {
13679 case MVT::i8: return X86::MOV8rm;
13680 case MVT::i16: return X86::MOV16rm;
13681 case MVT::i32: return X86::MOV32rm;
13682 case MVT::i64: return X86::MOV64rm;
13686 llvm_unreachable("Invalid operand size!");
13689 // Get opcode of the non-atomic one from the specified atomic instruction.
13690 static unsigned getNonAtomicOpcode(unsigned Opc) {
13692 case X86::ATOMAND8: return X86::AND8rr;
13693 case X86::ATOMAND16: return X86::AND16rr;
13694 case X86::ATOMAND32: return X86::AND32rr;
13695 case X86::ATOMAND64: return X86::AND64rr;
13696 case X86::ATOMOR8: return X86::OR8rr;
13697 case X86::ATOMOR16: return X86::OR16rr;
13698 case X86::ATOMOR32: return X86::OR32rr;
13699 case X86::ATOMOR64: return X86::OR64rr;
13700 case X86::ATOMXOR8: return X86::XOR8rr;
13701 case X86::ATOMXOR16: return X86::XOR16rr;
13702 case X86::ATOMXOR32: return X86::XOR32rr;
13703 case X86::ATOMXOR64: return X86::XOR64rr;
13705 llvm_unreachable("Unhandled atomic-load-op opcode!");
13708 // Get opcode of the non-atomic one from the specified atomic instruction with
13710 static unsigned getNonAtomicOpcodeWithExtraOpc(unsigned Opc,
13711 unsigned &ExtraOpc) {
13713 case X86::ATOMNAND8: ExtraOpc = X86::NOT8r; return X86::AND8rr;
13714 case X86::ATOMNAND16: ExtraOpc = X86::NOT16r; return X86::AND16rr;
13715 case X86::ATOMNAND32: ExtraOpc = X86::NOT32r; return X86::AND32rr;
13716 case X86::ATOMNAND64: ExtraOpc = X86::NOT64r; return X86::AND64rr;
13717 case X86::ATOMMAX8: ExtraOpc = X86::CMP8rr; return X86::CMOVL32rr;
13718 case X86::ATOMMAX16: ExtraOpc = X86::CMP16rr; return X86::CMOVL16rr;
13719 case X86::ATOMMAX32: ExtraOpc = X86::CMP32rr; return X86::CMOVL32rr;
13720 case X86::ATOMMAX64: ExtraOpc = X86::CMP64rr; return X86::CMOVL64rr;
13721 case X86::ATOMMIN8: ExtraOpc = X86::CMP8rr; return X86::CMOVG32rr;
13722 case X86::ATOMMIN16: ExtraOpc = X86::CMP16rr; return X86::CMOVG16rr;
13723 case X86::ATOMMIN32: ExtraOpc = X86::CMP32rr; return X86::CMOVG32rr;
13724 case X86::ATOMMIN64: ExtraOpc = X86::CMP64rr; return X86::CMOVG64rr;
13725 case X86::ATOMUMAX8: ExtraOpc = X86::CMP8rr; return X86::CMOVB32rr;
13726 case X86::ATOMUMAX16: ExtraOpc = X86::CMP16rr; return X86::CMOVB16rr;
13727 case X86::ATOMUMAX32: ExtraOpc = X86::CMP32rr; return X86::CMOVB32rr;
13728 case X86::ATOMUMAX64: ExtraOpc = X86::CMP64rr; return X86::CMOVB64rr;
13729 case X86::ATOMUMIN8: ExtraOpc = X86::CMP8rr; return X86::CMOVA32rr;
13730 case X86::ATOMUMIN16: ExtraOpc = X86::CMP16rr; return X86::CMOVA16rr;
13731 case X86::ATOMUMIN32: ExtraOpc = X86::CMP32rr; return X86::CMOVA32rr;
13732 case X86::ATOMUMIN64: ExtraOpc = X86::CMP64rr; return X86::CMOVA64rr;
13734 llvm_unreachable("Unhandled atomic-load-op opcode!");
13737 // Get opcode of the non-atomic one from the specified atomic instruction for
13738 // 64-bit data type on 32-bit target.
13739 static unsigned getNonAtomic6432Opcode(unsigned Opc, unsigned &HiOpc) {
13741 case X86::ATOMAND6432: HiOpc = X86::AND32rr; return X86::AND32rr;
13742 case X86::ATOMOR6432: HiOpc = X86::OR32rr; return X86::OR32rr;
13743 case X86::ATOMXOR6432: HiOpc = X86::XOR32rr; return X86::XOR32rr;
13744 case X86::ATOMADD6432: HiOpc = X86::ADC32rr; return X86::ADD32rr;
13745 case X86::ATOMSUB6432: HiOpc = X86::SBB32rr; return X86::SUB32rr;
13746 case X86::ATOMSWAP6432: HiOpc = X86::MOV32rr; return X86::MOV32rr;
13747 case X86::ATOMMAX6432: HiOpc = X86::SETLr; return X86::SETLr;
13748 case X86::ATOMMIN6432: HiOpc = X86::SETGr; return X86::SETGr;
13749 case X86::ATOMUMAX6432: HiOpc = X86::SETBr; return X86::SETBr;
13750 case X86::ATOMUMIN6432: HiOpc = X86::SETAr; return X86::SETAr;
13752 llvm_unreachable("Unhandled atomic-load-op opcode!");
13755 // Get opcode of the non-atomic one from the specified atomic instruction for
13756 // 64-bit data type on 32-bit target with extra opcode.
13757 static unsigned getNonAtomic6432OpcodeWithExtraOpc(unsigned Opc,
13759 unsigned &ExtraOpc) {
13761 case X86::ATOMNAND6432:
13762 ExtraOpc = X86::NOT32r;
13763 HiOpc = X86::AND32rr;
13764 return X86::AND32rr;
13766 llvm_unreachable("Unhandled atomic-load-op opcode!");
13769 // Get pseudo CMOV opcode from the specified data type.
13770 static unsigned getPseudoCMOVOpc(EVT VT) {
13771 switch (VT.getSimpleVT().SimpleTy) {
13772 case MVT::i8: return X86::CMOV_GR8;
13773 case MVT::i16: return X86::CMOV_GR16;
13774 case MVT::i32: return X86::CMOV_GR32;
13778 llvm_unreachable("Unknown CMOV opcode!");
13781 // EmitAtomicLoadArith - emit the code sequence for pseudo atomic instructions.
13782 // They will be translated into a spin-loop or compare-exchange loop from
13785 // dst = atomic-fetch-op MI.addr, MI.val
13791 // t1 = LOAD MI.addr
13793 // t4 = phi(t1, t3 / loop)
13794 // t2 = OP MI.val, t4
13796 // LCMPXCHG [MI.addr], t2, [EAX is implicitly used & defined]
13802 MachineBasicBlock *
13803 X86TargetLowering::EmitAtomicLoadArith(MachineInstr *MI,
13804 MachineBasicBlock *MBB) const {
13805 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
13806 DebugLoc DL = MI->getDebugLoc();
13808 MachineFunction *MF = MBB->getParent();
13809 MachineRegisterInfo &MRI = MF->getRegInfo();
13811 const BasicBlock *BB = MBB->getBasicBlock();
13812 MachineFunction::iterator I = MBB;
13815 assert(MI->getNumOperands() <= X86::AddrNumOperands + 4 &&
13816 "Unexpected number of operands");
13818 assert(MI->hasOneMemOperand() &&
13819 "Expected atomic-load-op to have one memoperand");
13821 // Memory Reference
13822 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
13823 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
13825 unsigned DstReg, SrcReg;
13826 unsigned MemOpndSlot;
13828 unsigned CurOp = 0;
13830 DstReg = MI->getOperand(CurOp++).getReg();
13831 MemOpndSlot = CurOp;
13832 CurOp += X86::AddrNumOperands;
13833 SrcReg = MI->getOperand(CurOp++).getReg();
13835 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
13836 MVT::SimpleValueType VT = *RC->vt_begin();
13837 unsigned t1 = MRI.createVirtualRegister(RC);
13838 unsigned t2 = MRI.createVirtualRegister(RC);
13839 unsigned t3 = MRI.createVirtualRegister(RC);
13840 unsigned t4 = MRI.createVirtualRegister(RC);
13841 unsigned PhyReg = getX86SubSuperRegister(X86::EAX, VT);
13843 unsigned LCMPXCHGOpc = getCmpXChgOpcode(VT);
13844 unsigned LOADOpc = getLoadOpcode(VT);
13846 // For the atomic load-arith operator, we generate
13849 // t1 = LOAD [MI.addr]
13851 // t4 = phi(t1 / thisMBB, t3 / mainMBB)
13852 // t1 = OP MI.val, EAX
13854 // LCMPXCHG [MI.addr], t1, [EAX is implicitly used & defined]
13860 MachineBasicBlock *thisMBB = MBB;
13861 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
13862 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
13863 MF->insert(I, mainMBB);
13864 MF->insert(I, sinkMBB);
13866 MachineInstrBuilder MIB;
13868 // Transfer the remainder of BB and its successor edges to sinkMBB.
13869 sinkMBB->splice(sinkMBB->begin(), MBB,
13870 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
13871 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
13874 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), t1);
13875 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
13876 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
13878 NewMO.setIsKill(false);
13879 MIB.addOperand(NewMO);
13881 for (MachineInstr::mmo_iterator MMOI = MMOBegin; MMOI != MMOEnd; ++MMOI) {
13882 unsigned flags = (*MMOI)->getFlags();
13883 flags = (flags & ~MachineMemOperand::MOStore) | MachineMemOperand::MOLoad;
13884 MachineMemOperand *MMO =
13885 MF->getMachineMemOperand((*MMOI)->getPointerInfo(), flags,
13886 (*MMOI)->getSize(),
13887 (*MMOI)->getBaseAlignment(),
13888 (*MMOI)->getTBAAInfo(),
13889 (*MMOI)->getRanges());
13890 MIB.addMemOperand(MMO);
13893 thisMBB->addSuccessor(mainMBB);
13896 MachineBasicBlock *origMainMBB = mainMBB;
13899 MachineInstr *Phi = BuildMI(mainMBB, DL, TII->get(X86::PHI), t4)
13900 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(mainMBB);
13902 unsigned Opc = MI->getOpcode();
13905 llvm_unreachable("Unhandled atomic-load-op opcode!");
13906 case X86::ATOMAND8:
13907 case X86::ATOMAND16:
13908 case X86::ATOMAND32:
13909 case X86::ATOMAND64:
13911 case X86::ATOMOR16:
13912 case X86::ATOMOR32:
13913 case X86::ATOMOR64:
13914 case X86::ATOMXOR8:
13915 case X86::ATOMXOR16:
13916 case X86::ATOMXOR32:
13917 case X86::ATOMXOR64: {
13918 unsigned ARITHOpc = getNonAtomicOpcode(Opc);
13919 BuildMI(mainMBB, DL, TII->get(ARITHOpc), t2).addReg(SrcReg)
13923 case X86::ATOMNAND8:
13924 case X86::ATOMNAND16:
13925 case X86::ATOMNAND32:
13926 case X86::ATOMNAND64: {
13927 unsigned Tmp = MRI.createVirtualRegister(RC);
13929 unsigned ANDOpc = getNonAtomicOpcodeWithExtraOpc(Opc, NOTOpc);
13930 BuildMI(mainMBB, DL, TII->get(ANDOpc), Tmp).addReg(SrcReg)
13932 BuildMI(mainMBB, DL, TII->get(NOTOpc), t2).addReg(Tmp);
13935 case X86::ATOMMAX8:
13936 case X86::ATOMMAX16:
13937 case X86::ATOMMAX32:
13938 case X86::ATOMMAX64:
13939 case X86::ATOMMIN8:
13940 case X86::ATOMMIN16:
13941 case X86::ATOMMIN32:
13942 case X86::ATOMMIN64:
13943 case X86::ATOMUMAX8:
13944 case X86::ATOMUMAX16:
13945 case X86::ATOMUMAX32:
13946 case X86::ATOMUMAX64:
13947 case X86::ATOMUMIN8:
13948 case X86::ATOMUMIN16:
13949 case X86::ATOMUMIN32:
13950 case X86::ATOMUMIN64: {
13952 unsigned CMOVOpc = getNonAtomicOpcodeWithExtraOpc(Opc, CMPOpc);
13954 BuildMI(mainMBB, DL, TII->get(CMPOpc))
13958 if (Subtarget->hasCMov()) {
13959 if (VT != MVT::i8) {
13961 BuildMI(mainMBB, DL, TII->get(CMOVOpc), t2)
13965 // Promote i8 to i32 to use CMOV32
13966 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
13967 const TargetRegisterClass *RC32 =
13968 TRI->getSubClassWithSubReg(getRegClassFor(MVT::i32), X86::sub_8bit);
13969 unsigned SrcReg32 = MRI.createVirtualRegister(RC32);
13970 unsigned AccReg32 = MRI.createVirtualRegister(RC32);
13971 unsigned Tmp = MRI.createVirtualRegister(RC32);
13973 unsigned Undef = MRI.createVirtualRegister(RC32);
13974 BuildMI(mainMBB, DL, TII->get(TargetOpcode::IMPLICIT_DEF), Undef);
13976 BuildMI(mainMBB, DL, TII->get(TargetOpcode::INSERT_SUBREG), SrcReg32)
13979 .addImm(X86::sub_8bit);
13980 BuildMI(mainMBB, DL, TII->get(TargetOpcode::INSERT_SUBREG), AccReg32)
13983 .addImm(X86::sub_8bit);
13985 BuildMI(mainMBB, DL, TII->get(CMOVOpc), Tmp)
13989 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t2)
13990 .addReg(Tmp, 0, X86::sub_8bit);
13993 // Use pseudo select and lower them.
13994 assert((VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32) &&
13995 "Invalid atomic-load-op transformation!");
13996 unsigned SelOpc = getPseudoCMOVOpc(VT);
13997 X86::CondCode CC = X86::getCondFromCMovOpc(CMOVOpc);
13998 assert(CC != X86::COND_INVALID && "Invalid atomic-load-op transformation!");
13999 MIB = BuildMI(mainMBB, DL, TII->get(SelOpc), t2)
14000 .addReg(SrcReg).addReg(t4)
14002 mainMBB = EmitLoweredSelect(MIB, mainMBB);
14003 // Replace the original PHI node as mainMBB is changed after CMOV
14005 BuildMI(*origMainMBB, Phi, DL, TII->get(X86::PHI), t4)
14006 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(mainMBB);
14007 Phi->eraseFromParent();
14013 // Copy PhyReg back from virtual register.
14014 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), PhyReg)
14017 MIB = BuildMI(mainMBB, DL, TII->get(LCMPXCHGOpc));
14018 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14019 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14021 NewMO.setIsKill(false);
14022 MIB.addOperand(NewMO);
14025 MIB.setMemRefs(MMOBegin, MMOEnd);
14027 // Copy PhyReg back to virtual register.
14028 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t3)
14031 BuildMI(mainMBB, DL, TII->get(X86::JNE_4)).addMBB(origMainMBB);
14033 mainMBB->addSuccessor(origMainMBB);
14034 mainMBB->addSuccessor(sinkMBB);
14037 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
14038 TII->get(TargetOpcode::COPY), DstReg)
14041 MI->eraseFromParent();
14045 // EmitAtomicLoadArith6432 - emit the code sequence for pseudo atomic
14046 // instructions. They will be translated into a spin-loop or compare-exchange
14050 // dst = atomic-fetch-op MI.addr, MI.val
14056 // t1L = LOAD [MI.addr + 0]
14057 // t1H = LOAD [MI.addr + 4]
14059 // t4L = phi(t1L, t3L / loop)
14060 // t4H = phi(t1H, t3H / loop)
14061 // t2L = OP MI.val.lo, t4L
14062 // t2H = OP MI.val.hi, t4H
14067 // LCMPXCHG8B [MI.addr], [ECX:EBX & EDX:EAX are implicitly used and EDX:EAX is implicitly defined]
14075 MachineBasicBlock *
14076 X86TargetLowering::EmitAtomicLoadArith6432(MachineInstr *MI,
14077 MachineBasicBlock *MBB) const {
14078 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14079 DebugLoc DL = MI->getDebugLoc();
14081 MachineFunction *MF = MBB->getParent();
14082 MachineRegisterInfo &MRI = MF->getRegInfo();
14084 const BasicBlock *BB = MBB->getBasicBlock();
14085 MachineFunction::iterator I = MBB;
14088 assert(MI->getNumOperands() <= X86::AddrNumOperands + 7 &&
14089 "Unexpected number of operands");
14091 assert(MI->hasOneMemOperand() &&
14092 "Expected atomic-load-op32 to have one memoperand");
14094 // Memory Reference
14095 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
14096 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
14098 unsigned DstLoReg, DstHiReg;
14099 unsigned SrcLoReg, SrcHiReg;
14100 unsigned MemOpndSlot;
14102 unsigned CurOp = 0;
14104 DstLoReg = MI->getOperand(CurOp++).getReg();
14105 DstHiReg = MI->getOperand(CurOp++).getReg();
14106 MemOpndSlot = CurOp;
14107 CurOp += X86::AddrNumOperands;
14108 SrcLoReg = MI->getOperand(CurOp++).getReg();
14109 SrcHiReg = MI->getOperand(CurOp++).getReg();
14111 const TargetRegisterClass *RC = &X86::GR32RegClass;
14112 const TargetRegisterClass *RC8 = &X86::GR8RegClass;
14114 unsigned t1L = MRI.createVirtualRegister(RC);
14115 unsigned t1H = MRI.createVirtualRegister(RC);
14116 unsigned t2L = MRI.createVirtualRegister(RC);
14117 unsigned t2H = MRI.createVirtualRegister(RC);
14118 unsigned t3L = MRI.createVirtualRegister(RC);
14119 unsigned t3H = MRI.createVirtualRegister(RC);
14120 unsigned t4L = MRI.createVirtualRegister(RC);
14121 unsigned t4H = MRI.createVirtualRegister(RC);
14123 unsigned LCMPXCHGOpc = X86::LCMPXCHG8B;
14124 unsigned LOADOpc = X86::MOV32rm;
14126 // For the atomic load-arith operator, we generate
14129 // t1L = LOAD [MI.addr + 0]
14130 // t1H = LOAD [MI.addr + 4]
14132 // t4L = phi(t1L / thisMBB, t3L / mainMBB)
14133 // t4H = phi(t1H / thisMBB, t3H / mainMBB)
14134 // t2L = OP MI.val.lo, t4L
14135 // t2H = OP MI.val.hi, t4H
14138 // LCMPXCHG8B [MI.addr], [ECX:EBX & EDX:EAX are implicitly used and EDX:EAX is implicitly defined]
14146 MachineBasicBlock *thisMBB = MBB;
14147 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
14148 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
14149 MF->insert(I, mainMBB);
14150 MF->insert(I, sinkMBB);
14152 MachineInstrBuilder MIB;
14154 // Transfer the remainder of BB and its successor edges to sinkMBB.
14155 sinkMBB->splice(sinkMBB->begin(), MBB,
14156 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
14157 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
14161 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), t1L);
14162 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14163 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14165 NewMO.setIsKill(false);
14166 MIB.addOperand(NewMO);
14168 for (MachineInstr::mmo_iterator MMOI = MMOBegin; MMOI != MMOEnd; ++MMOI) {
14169 unsigned flags = (*MMOI)->getFlags();
14170 flags = (flags & ~MachineMemOperand::MOStore) | MachineMemOperand::MOLoad;
14171 MachineMemOperand *MMO =
14172 MF->getMachineMemOperand((*MMOI)->getPointerInfo(), flags,
14173 (*MMOI)->getSize(),
14174 (*MMOI)->getBaseAlignment(),
14175 (*MMOI)->getTBAAInfo(),
14176 (*MMOI)->getRanges());
14177 MIB.addMemOperand(MMO);
14179 MachineInstr *LowMI = MIB;
14182 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), t1H);
14183 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14184 if (i == X86::AddrDisp) {
14185 MIB.addDisp(MI->getOperand(MemOpndSlot + i), 4); // 4 == sizeof(i32)
14187 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14189 NewMO.setIsKill(false);
14190 MIB.addOperand(NewMO);
14193 MIB.setMemRefs(LowMI->memoperands_begin(), LowMI->memoperands_end());
14195 thisMBB->addSuccessor(mainMBB);
14198 MachineBasicBlock *origMainMBB = mainMBB;
14201 MachineInstr *PhiL = BuildMI(mainMBB, DL, TII->get(X86::PHI), t4L)
14202 .addReg(t1L).addMBB(thisMBB).addReg(t3L).addMBB(mainMBB);
14203 MachineInstr *PhiH = BuildMI(mainMBB, DL, TII->get(X86::PHI), t4H)
14204 .addReg(t1H).addMBB(thisMBB).addReg(t3H).addMBB(mainMBB);
14206 unsigned Opc = MI->getOpcode();
14209 llvm_unreachable("Unhandled atomic-load-op6432 opcode!");
14210 case X86::ATOMAND6432:
14211 case X86::ATOMOR6432:
14212 case X86::ATOMXOR6432:
14213 case X86::ATOMADD6432:
14214 case X86::ATOMSUB6432: {
14216 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
14217 BuildMI(mainMBB, DL, TII->get(LoOpc), t2L).addReg(t4L)
14219 BuildMI(mainMBB, DL, TII->get(HiOpc), t2H).addReg(t4H)
14223 case X86::ATOMNAND6432: {
14224 unsigned HiOpc, NOTOpc;
14225 unsigned LoOpc = getNonAtomic6432OpcodeWithExtraOpc(Opc, HiOpc, NOTOpc);
14226 unsigned TmpL = MRI.createVirtualRegister(RC);
14227 unsigned TmpH = MRI.createVirtualRegister(RC);
14228 BuildMI(mainMBB, DL, TII->get(LoOpc), TmpL).addReg(SrcLoReg)
14230 BuildMI(mainMBB, DL, TII->get(HiOpc), TmpH).addReg(SrcHiReg)
14232 BuildMI(mainMBB, DL, TII->get(NOTOpc), t2L).addReg(TmpL);
14233 BuildMI(mainMBB, DL, TII->get(NOTOpc), t2H).addReg(TmpH);
14236 case X86::ATOMMAX6432:
14237 case X86::ATOMMIN6432:
14238 case X86::ATOMUMAX6432:
14239 case X86::ATOMUMIN6432: {
14241 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
14242 unsigned cL = MRI.createVirtualRegister(RC8);
14243 unsigned cH = MRI.createVirtualRegister(RC8);
14244 unsigned cL32 = MRI.createVirtualRegister(RC);
14245 unsigned cH32 = MRI.createVirtualRegister(RC);
14246 unsigned cc = MRI.createVirtualRegister(RC);
14247 // cl := cmp src_lo, lo
14248 BuildMI(mainMBB, DL, TII->get(X86::CMP32rr))
14249 .addReg(SrcLoReg).addReg(t4L);
14250 BuildMI(mainMBB, DL, TII->get(LoOpc), cL);
14251 BuildMI(mainMBB, DL, TII->get(X86::MOVZX32rr8), cL32).addReg(cL);
14252 // ch := cmp src_hi, hi
14253 BuildMI(mainMBB, DL, TII->get(X86::CMP32rr))
14254 .addReg(SrcHiReg).addReg(t4H);
14255 BuildMI(mainMBB, DL, TII->get(HiOpc), cH);
14256 BuildMI(mainMBB, DL, TII->get(X86::MOVZX32rr8), cH32).addReg(cH);
14257 // cc := if (src_hi == hi) ? cl : ch;
14258 if (Subtarget->hasCMov()) {
14259 BuildMI(mainMBB, DL, TII->get(X86::CMOVE32rr), cc)
14260 .addReg(cH32).addReg(cL32);
14262 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), cc)
14263 .addReg(cH32).addReg(cL32)
14264 .addImm(X86::COND_E);
14265 mainMBB = EmitLoweredSelect(MIB, mainMBB);
14267 BuildMI(mainMBB, DL, TII->get(X86::TEST32rr)).addReg(cc).addReg(cc);
14268 if (Subtarget->hasCMov()) {
14269 BuildMI(mainMBB, DL, TII->get(X86::CMOVNE32rr), t2L)
14270 .addReg(SrcLoReg).addReg(t4L);
14271 BuildMI(mainMBB, DL, TII->get(X86::CMOVNE32rr), t2H)
14272 .addReg(SrcHiReg).addReg(t4H);
14274 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), t2L)
14275 .addReg(SrcLoReg).addReg(t4L)
14276 .addImm(X86::COND_NE);
14277 mainMBB = EmitLoweredSelect(MIB, mainMBB);
14278 // As the lowered CMOV won't clobber EFLAGS, we could reuse it for the
14279 // 2nd CMOV lowering.
14280 mainMBB->addLiveIn(X86::EFLAGS);
14281 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), t2H)
14282 .addReg(SrcHiReg).addReg(t4H)
14283 .addImm(X86::COND_NE);
14284 mainMBB = EmitLoweredSelect(MIB, mainMBB);
14285 // Replace the original PHI node as mainMBB is changed after CMOV
14287 BuildMI(*origMainMBB, PhiL, DL, TII->get(X86::PHI), t4L)
14288 .addReg(t1L).addMBB(thisMBB).addReg(t3L).addMBB(mainMBB);
14289 BuildMI(*origMainMBB, PhiH, DL, TII->get(X86::PHI), t4H)
14290 .addReg(t1H).addMBB(thisMBB).addReg(t3H).addMBB(mainMBB);
14291 PhiL->eraseFromParent();
14292 PhiH->eraseFromParent();
14296 case X86::ATOMSWAP6432: {
14298 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
14299 BuildMI(mainMBB, DL, TII->get(LoOpc), t2L).addReg(SrcLoReg);
14300 BuildMI(mainMBB, DL, TII->get(HiOpc), t2H).addReg(SrcHiReg);
14305 // Copy EDX:EAX back from HiReg:LoReg
14306 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EAX).addReg(t4L);
14307 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EDX).addReg(t4H);
14308 // Copy ECX:EBX from t1H:t1L
14309 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EBX).addReg(t2L);
14310 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::ECX).addReg(t2H);
14312 MIB = BuildMI(mainMBB, DL, TII->get(LCMPXCHGOpc));
14313 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14314 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14316 NewMO.setIsKill(false);
14317 MIB.addOperand(NewMO);
14319 MIB.setMemRefs(MMOBegin, MMOEnd);
14321 // Copy EDX:EAX back to t3H:t3L
14322 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t3L).addReg(X86::EAX);
14323 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t3H).addReg(X86::EDX);
14325 BuildMI(mainMBB, DL, TII->get(X86::JNE_4)).addMBB(origMainMBB);
14327 mainMBB->addSuccessor(origMainMBB);
14328 mainMBB->addSuccessor(sinkMBB);
14331 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
14332 TII->get(TargetOpcode::COPY), DstLoReg)
14334 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
14335 TII->get(TargetOpcode::COPY), DstHiReg)
14338 MI->eraseFromParent();
14342 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
14343 // or XMM0_V32I8 in AVX all of this code can be replaced with that
14344 // in the .td file.
14345 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
14346 const TargetInstrInfo *TII) {
14348 switch (MI->getOpcode()) {
14349 default: llvm_unreachable("illegal opcode!");
14350 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
14351 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
14352 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
14353 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
14354 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
14355 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
14356 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
14357 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
14360 DebugLoc dl = MI->getDebugLoc();
14361 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
14363 unsigned NumArgs = MI->getNumOperands();
14364 for (unsigned i = 1; i < NumArgs; ++i) {
14365 MachineOperand &Op = MI->getOperand(i);
14366 if (!(Op.isReg() && Op.isImplicit()))
14367 MIB.addOperand(Op);
14369 if (MI->hasOneMemOperand())
14370 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
14372 BuildMI(*BB, MI, dl,
14373 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
14374 .addReg(X86::XMM0);
14376 MI->eraseFromParent();
14380 // FIXME: Custom handling because TableGen doesn't support multiple implicit
14381 // defs in an instruction pattern
14382 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
14383 const TargetInstrInfo *TII) {
14385 switch (MI->getOpcode()) {
14386 default: llvm_unreachable("illegal opcode!");
14387 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
14388 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
14389 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
14390 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
14391 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
14392 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
14393 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
14394 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
14397 DebugLoc dl = MI->getDebugLoc();
14398 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
14400 unsigned NumArgs = MI->getNumOperands(); // remove the results
14401 for (unsigned i = 1; i < NumArgs; ++i) {
14402 MachineOperand &Op = MI->getOperand(i);
14403 if (!(Op.isReg() && Op.isImplicit()))
14404 MIB.addOperand(Op);
14406 if (MI->hasOneMemOperand())
14407 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
14409 BuildMI(*BB, MI, dl,
14410 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
14413 MI->eraseFromParent();
14417 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
14418 const TargetInstrInfo *TII,
14419 const X86Subtarget* Subtarget) {
14420 DebugLoc dl = MI->getDebugLoc();
14422 // Address into RAX/EAX, other two args into ECX, EDX.
14423 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
14424 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
14425 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
14426 for (int i = 0; i < X86::AddrNumOperands; ++i)
14427 MIB.addOperand(MI->getOperand(i));
14429 unsigned ValOps = X86::AddrNumOperands;
14430 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
14431 .addReg(MI->getOperand(ValOps).getReg());
14432 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
14433 .addReg(MI->getOperand(ValOps+1).getReg());
14435 // The instruction doesn't actually take any operands though.
14436 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
14438 MI->eraseFromParent(); // The pseudo is gone now.
14442 MachineBasicBlock *
14443 X86TargetLowering::EmitVAARG64WithCustomInserter(
14445 MachineBasicBlock *MBB) const {
14446 // Emit va_arg instruction on X86-64.
14448 // Operands to this pseudo-instruction:
14449 // 0 ) Output : destination address (reg)
14450 // 1-5) Input : va_list address (addr, i64mem)
14451 // 6 ) ArgSize : Size (in bytes) of vararg type
14452 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
14453 // 8 ) Align : Alignment of type
14454 // 9 ) EFLAGS (implicit-def)
14456 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
14457 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
14459 unsigned DestReg = MI->getOperand(0).getReg();
14460 MachineOperand &Base = MI->getOperand(1);
14461 MachineOperand &Scale = MI->getOperand(2);
14462 MachineOperand &Index = MI->getOperand(3);
14463 MachineOperand &Disp = MI->getOperand(4);
14464 MachineOperand &Segment = MI->getOperand(5);
14465 unsigned ArgSize = MI->getOperand(6).getImm();
14466 unsigned ArgMode = MI->getOperand(7).getImm();
14467 unsigned Align = MI->getOperand(8).getImm();
14469 // Memory Reference
14470 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
14471 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
14472 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
14474 // Machine Information
14475 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14476 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
14477 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
14478 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
14479 DebugLoc DL = MI->getDebugLoc();
14481 // struct va_list {
14484 // i64 overflow_area (address)
14485 // i64 reg_save_area (address)
14487 // sizeof(va_list) = 24
14488 // alignment(va_list) = 8
14490 unsigned TotalNumIntRegs = 6;
14491 unsigned TotalNumXMMRegs = 8;
14492 bool UseGPOffset = (ArgMode == 1);
14493 bool UseFPOffset = (ArgMode == 2);
14494 unsigned MaxOffset = TotalNumIntRegs * 8 +
14495 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
14497 /* Align ArgSize to a multiple of 8 */
14498 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
14499 bool NeedsAlign = (Align > 8);
14501 MachineBasicBlock *thisMBB = MBB;
14502 MachineBasicBlock *overflowMBB;
14503 MachineBasicBlock *offsetMBB;
14504 MachineBasicBlock *endMBB;
14506 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
14507 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
14508 unsigned OffsetReg = 0;
14510 if (!UseGPOffset && !UseFPOffset) {
14511 // If we only pull from the overflow region, we don't create a branch.
14512 // We don't need to alter control flow.
14513 OffsetDestReg = 0; // unused
14514 OverflowDestReg = DestReg;
14517 overflowMBB = thisMBB;
14520 // First emit code to check if gp_offset (or fp_offset) is below the bound.
14521 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
14522 // If not, pull from overflow_area. (branch to overflowMBB)
14527 // offsetMBB overflowMBB
14532 // Registers for the PHI in endMBB
14533 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
14534 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
14536 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
14537 MachineFunction *MF = MBB->getParent();
14538 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
14539 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
14540 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
14542 MachineFunction::iterator MBBIter = MBB;
14545 // Insert the new basic blocks
14546 MF->insert(MBBIter, offsetMBB);
14547 MF->insert(MBBIter, overflowMBB);
14548 MF->insert(MBBIter, endMBB);
14550 // Transfer the remainder of MBB and its successor edges to endMBB.
14551 endMBB->splice(endMBB->begin(), thisMBB,
14552 llvm::next(MachineBasicBlock::iterator(MI)),
14554 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
14556 // Make offsetMBB and overflowMBB successors of thisMBB
14557 thisMBB->addSuccessor(offsetMBB);
14558 thisMBB->addSuccessor(overflowMBB);
14560 // endMBB is a successor of both offsetMBB and overflowMBB
14561 offsetMBB->addSuccessor(endMBB);
14562 overflowMBB->addSuccessor(endMBB);
14564 // Load the offset value into a register
14565 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
14566 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
14570 .addDisp(Disp, UseFPOffset ? 4 : 0)
14571 .addOperand(Segment)
14572 .setMemRefs(MMOBegin, MMOEnd);
14574 // Check if there is enough room left to pull this argument.
14575 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
14577 .addImm(MaxOffset + 8 - ArgSizeA8);
14579 // Branch to "overflowMBB" if offset >= max
14580 // Fall through to "offsetMBB" otherwise
14581 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
14582 .addMBB(overflowMBB);
14585 // In offsetMBB, emit code to use the reg_save_area.
14587 assert(OffsetReg != 0);
14589 // Read the reg_save_area address.
14590 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
14591 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
14596 .addOperand(Segment)
14597 .setMemRefs(MMOBegin, MMOEnd);
14599 // Zero-extend the offset
14600 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
14601 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
14604 .addImm(X86::sub_32bit);
14606 // Add the offset to the reg_save_area to get the final address.
14607 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
14608 .addReg(OffsetReg64)
14609 .addReg(RegSaveReg);
14611 // Compute the offset for the next argument
14612 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
14613 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
14615 .addImm(UseFPOffset ? 16 : 8);
14617 // Store it back into the va_list.
14618 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
14622 .addDisp(Disp, UseFPOffset ? 4 : 0)
14623 .addOperand(Segment)
14624 .addReg(NextOffsetReg)
14625 .setMemRefs(MMOBegin, MMOEnd);
14628 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
14633 // Emit code to use overflow area
14636 // Load the overflow_area address into a register.
14637 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
14638 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
14643 .addOperand(Segment)
14644 .setMemRefs(MMOBegin, MMOEnd);
14646 // If we need to align it, do so. Otherwise, just copy the address
14647 // to OverflowDestReg.
14649 // Align the overflow address
14650 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
14651 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
14653 // aligned_addr = (addr + (align-1)) & ~(align-1)
14654 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
14655 .addReg(OverflowAddrReg)
14658 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
14660 .addImm(~(uint64_t)(Align-1));
14662 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
14663 .addReg(OverflowAddrReg);
14666 // Compute the next overflow address after this argument.
14667 // (the overflow address should be kept 8-byte aligned)
14668 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
14669 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
14670 .addReg(OverflowDestReg)
14671 .addImm(ArgSizeA8);
14673 // Store the new overflow address.
14674 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
14679 .addOperand(Segment)
14680 .addReg(NextAddrReg)
14681 .setMemRefs(MMOBegin, MMOEnd);
14683 // If we branched, emit the PHI to the front of endMBB.
14685 BuildMI(*endMBB, endMBB->begin(), DL,
14686 TII->get(X86::PHI), DestReg)
14687 .addReg(OffsetDestReg).addMBB(offsetMBB)
14688 .addReg(OverflowDestReg).addMBB(overflowMBB);
14691 // Erase the pseudo instruction
14692 MI->eraseFromParent();
14697 MachineBasicBlock *
14698 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
14700 MachineBasicBlock *MBB) const {
14701 // Emit code to save XMM registers to the stack. The ABI says that the
14702 // number of registers to save is given in %al, so it's theoretically
14703 // possible to do an indirect jump trick to avoid saving all of them,
14704 // however this code takes a simpler approach and just executes all
14705 // of the stores if %al is non-zero. It's less code, and it's probably
14706 // easier on the hardware branch predictor, and stores aren't all that
14707 // expensive anyway.
14709 // Create the new basic blocks. One block contains all the XMM stores,
14710 // and one block is the final destination regardless of whether any
14711 // stores were performed.
14712 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
14713 MachineFunction *F = MBB->getParent();
14714 MachineFunction::iterator MBBIter = MBB;
14716 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
14717 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
14718 F->insert(MBBIter, XMMSaveMBB);
14719 F->insert(MBBIter, EndMBB);
14721 // Transfer the remainder of MBB and its successor edges to EndMBB.
14722 EndMBB->splice(EndMBB->begin(), MBB,
14723 llvm::next(MachineBasicBlock::iterator(MI)),
14725 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
14727 // The original block will now fall through to the XMM save block.
14728 MBB->addSuccessor(XMMSaveMBB);
14729 // The XMMSaveMBB will fall through to the end block.
14730 XMMSaveMBB->addSuccessor(EndMBB);
14732 // Now add the instructions.
14733 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14734 DebugLoc DL = MI->getDebugLoc();
14736 unsigned CountReg = MI->getOperand(0).getReg();
14737 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
14738 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
14740 if (!Subtarget->isTargetWin64()) {
14741 // If %al is 0, branch around the XMM save block.
14742 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
14743 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
14744 MBB->addSuccessor(EndMBB);
14747 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
14748 // In the XMM save block, save all the XMM argument registers.
14749 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
14750 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
14751 MachineMemOperand *MMO =
14752 F->getMachineMemOperand(
14753 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
14754 MachineMemOperand::MOStore,
14755 /*Size=*/16, /*Align=*/16);
14756 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
14757 .addFrameIndex(RegSaveFrameIndex)
14758 .addImm(/*Scale=*/1)
14759 .addReg(/*IndexReg=*/0)
14760 .addImm(/*Disp=*/Offset)
14761 .addReg(/*Segment=*/0)
14762 .addReg(MI->getOperand(i).getReg())
14763 .addMemOperand(MMO);
14766 MI->eraseFromParent(); // The pseudo instruction is gone now.
14771 // The EFLAGS operand of SelectItr might be missing a kill marker
14772 // because there were multiple uses of EFLAGS, and ISel didn't know
14773 // which to mark. Figure out whether SelectItr should have had a
14774 // kill marker, and set it if it should. Returns the correct kill
14776 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
14777 MachineBasicBlock* BB,
14778 const TargetRegisterInfo* TRI) {
14779 // Scan forward through BB for a use/def of EFLAGS.
14780 MachineBasicBlock::iterator miI(llvm::next(SelectItr));
14781 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
14782 const MachineInstr& mi = *miI;
14783 if (mi.readsRegister(X86::EFLAGS))
14785 if (mi.definesRegister(X86::EFLAGS))
14786 break; // Should have kill-flag - update below.
14789 // If we hit the end of the block, check whether EFLAGS is live into a
14791 if (miI == BB->end()) {
14792 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
14793 sEnd = BB->succ_end();
14794 sItr != sEnd; ++sItr) {
14795 MachineBasicBlock* succ = *sItr;
14796 if (succ->isLiveIn(X86::EFLAGS))
14801 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
14802 // out. SelectMI should have a kill flag on EFLAGS.
14803 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
14807 MachineBasicBlock *
14808 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
14809 MachineBasicBlock *BB) const {
14810 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14811 DebugLoc DL = MI->getDebugLoc();
14813 // To "insert" a SELECT_CC instruction, we actually have to insert the
14814 // diamond control-flow pattern. The incoming instruction knows the
14815 // destination vreg to set, the condition code register to branch on, the
14816 // true/false values to select between, and a branch opcode to use.
14817 const BasicBlock *LLVM_BB = BB->getBasicBlock();
14818 MachineFunction::iterator It = BB;
14824 // cmpTY ccX, r1, r2
14826 // fallthrough --> copy0MBB
14827 MachineBasicBlock *thisMBB = BB;
14828 MachineFunction *F = BB->getParent();
14829 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
14830 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
14831 F->insert(It, copy0MBB);
14832 F->insert(It, sinkMBB);
14834 // If the EFLAGS register isn't dead in the terminator, then claim that it's
14835 // live into the sink and copy blocks.
14836 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
14837 if (!MI->killsRegister(X86::EFLAGS) &&
14838 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
14839 copy0MBB->addLiveIn(X86::EFLAGS);
14840 sinkMBB->addLiveIn(X86::EFLAGS);
14843 // Transfer the remainder of BB and its successor edges to sinkMBB.
14844 sinkMBB->splice(sinkMBB->begin(), BB,
14845 llvm::next(MachineBasicBlock::iterator(MI)),
14847 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
14849 // Add the true and fallthrough blocks as its successors.
14850 BB->addSuccessor(copy0MBB);
14851 BB->addSuccessor(sinkMBB);
14853 // Create the conditional branch instruction.
14855 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
14856 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
14859 // %FalseValue = ...
14860 // # fallthrough to sinkMBB
14861 copy0MBB->addSuccessor(sinkMBB);
14864 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
14866 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
14867 TII->get(X86::PHI), MI->getOperand(0).getReg())
14868 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
14869 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
14871 MI->eraseFromParent(); // The pseudo instruction is gone now.
14875 MachineBasicBlock *
14876 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
14877 bool Is64Bit) const {
14878 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14879 DebugLoc DL = MI->getDebugLoc();
14880 MachineFunction *MF = BB->getParent();
14881 const BasicBlock *LLVM_BB = BB->getBasicBlock();
14883 assert(getTargetMachine().Options.EnableSegmentedStacks);
14885 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
14886 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30;
14889 // ... [Till the alloca]
14890 // If stacklet is not large enough, jump to mallocMBB
14893 // Allocate by subtracting from RSP
14894 // Jump to continueMBB
14897 // Allocate by call to runtime
14901 // [rest of original BB]
14904 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
14905 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
14906 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
14908 MachineRegisterInfo &MRI = MF->getRegInfo();
14909 const TargetRegisterClass *AddrRegClass =
14910 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32);
14912 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
14913 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
14914 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
14915 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
14916 sizeVReg = MI->getOperand(1).getReg(),
14917 physSPReg = Is64Bit ? X86::RSP : X86::ESP;
14919 MachineFunction::iterator MBBIter = BB;
14922 MF->insert(MBBIter, bumpMBB);
14923 MF->insert(MBBIter, mallocMBB);
14924 MF->insert(MBBIter, continueMBB);
14926 continueMBB->splice(continueMBB->begin(), BB, llvm::next
14927 (MachineBasicBlock::iterator(MI)), BB->end());
14928 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
14930 // Add code to the main basic block to check if the stack limit has been hit,
14931 // and if so, jump to mallocMBB otherwise to bumpMBB.
14932 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
14933 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
14934 .addReg(tmpSPVReg).addReg(sizeVReg);
14935 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr))
14936 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
14937 .addReg(SPLimitVReg);
14938 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
14940 // bumpMBB simply decreases the stack pointer, since we know the current
14941 // stacklet has enough space.
14942 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
14943 .addReg(SPLimitVReg);
14944 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
14945 .addReg(SPLimitVReg);
14946 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
14948 // Calls into a routine in libgcc to allocate more space from the heap.
14949 const uint32_t *RegMask =
14950 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
14952 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
14954 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
14955 .addExternalSymbol("__morestack_allocate_stack_space")
14956 .addRegMask(RegMask)
14957 .addReg(X86::RDI, RegState::Implicit)
14958 .addReg(X86::RAX, RegState::ImplicitDefine);
14960 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
14962 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
14963 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
14964 .addExternalSymbol("__morestack_allocate_stack_space")
14965 .addRegMask(RegMask)
14966 .addReg(X86::EAX, RegState::ImplicitDefine);
14970 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
14973 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
14974 .addReg(Is64Bit ? X86::RAX : X86::EAX);
14975 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
14977 // Set up the CFG correctly.
14978 BB->addSuccessor(bumpMBB);
14979 BB->addSuccessor(mallocMBB);
14980 mallocMBB->addSuccessor(continueMBB);
14981 bumpMBB->addSuccessor(continueMBB);
14983 // Take care of the PHI nodes.
14984 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
14985 MI->getOperand(0).getReg())
14986 .addReg(mallocPtrVReg).addMBB(mallocMBB)
14987 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
14989 // Delete the original pseudo instruction.
14990 MI->eraseFromParent();
14993 return continueMBB;
14996 MachineBasicBlock *
14997 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
14998 MachineBasicBlock *BB) const {
14999 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15000 DebugLoc DL = MI->getDebugLoc();
15002 assert(!Subtarget->isTargetEnvMacho());
15004 // The lowering is pretty easy: we're just emitting the call to _alloca. The
15005 // non-trivial part is impdef of ESP.
15007 if (Subtarget->isTargetWin64()) {
15008 if (Subtarget->isTargetCygMing()) {
15009 // ___chkstk(Mingw64):
15010 // Clobbers R10, R11, RAX and EFLAGS.
15012 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
15013 .addExternalSymbol("___chkstk")
15014 .addReg(X86::RAX, RegState::Implicit)
15015 .addReg(X86::RSP, RegState::Implicit)
15016 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
15017 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
15018 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
15020 // __chkstk(MSVCRT): does not update stack pointer.
15021 // Clobbers R10, R11 and EFLAGS.
15022 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
15023 .addExternalSymbol("__chkstk")
15024 .addReg(X86::RAX, RegState::Implicit)
15025 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
15026 // RAX has the offset to be subtracted from RSP.
15027 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
15032 const char *StackProbeSymbol =
15033 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca";
15035 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
15036 .addExternalSymbol(StackProbeSymbol)
15037 .addReg(X86::EAX, RegState::Implicit)
15038 .addReg(X86::ESP, RegState::Implicit)
15039 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
15040 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
15041 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
15044 MI->eraseFromParent(); // The pseudo instruction is gone now.
15048 MachineBasicBlock *
15049 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
15050 MachineBasicBlock *BB) const {
15051 // This is pretty easy. We're taking the value that we received from
15052 // our load from the relocation, sticking it in either RDI (x86-64)
15053 // or EAX and doing an indirect call. The return value will then
15054 // be in the normal return register.
15055 const X86InstrInfo *TII
15056 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
15057 DebugLoc DL = MI->getDebugLoc();
15058 MachineFunction *F = BB->getParent();
15060 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
15061 assert(MI->getOperand(3).isGlobal() && "This should be a global");
15063 // Get a register mask for the lowered call.
15064 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
15065 // proper register mask.
15066 const uint32_t *RegMask =
15067 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
15068 if (Subtarget->is64Bit()) {
15069 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
15070 TII->get(X86::MOV64rm), X86::RDI)
15072 .addImm(0).addReg(0)
15073 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
15074 MI->getOperand(3).getTargetFlags())
15076 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
15077 addDirectMem(MIB, X86::RDI);
15078 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
15079 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
15080 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
15081 TII->get(X86::MOV32rm), X86::EAX)
15083 .addImm(0).addReg(0)
15084 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
15085 MI->getOperand(3).getTargetFlags())
15087 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
15088 addDirectMem(MIB, X86::EAX);
15089 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
15091 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
15092 TII->get(X86::MOV32rm), X86::EAX)
15093 .addReg(TII->getGlobalBaseReg(F))
15094 .addImm(0).addReg(0)
15095 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
15096 MI->getOperand(3).getTargetFlags())
15098 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
15099 addDirectMem(MIB, X86::EAX);
15100 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
15103 MI->eraseFromParent(); // The pseudo instruction is gone now.
15107 MachineBasicBlock *
15108 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
15109 MachineBasicBlock *MBB) const {
15110 DebugLoc DL = MI->getDebugLoc();
15111 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15113 MachineFunction *MF = MBB->getParent();
15114 MachineRegisterInfo &MRI = MF->getRegInfo();
15116 const BasicBlock *BB = MBB->getBasicBlock();
15117 MachineFunction::iterator I = MBB;
15120 // Memory Reference
15121 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
15122 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
15125 unsigned MemOpndSlot = 0;
15127 unsigned CurOp = 0;
15129 DstReg = MI->getOperand(CurOp++).getReg();
15130 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
15131 assert(RC->hasType(MVT::i32) && "Invalid destination!");
15132 unsigned mainDstReg = MRI.createVirtualRegister(RC);
15133 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
15135 MemOpndSlot = CurOp;
15137 MVT PVT = getPointerTy();
15138 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
15139 "Invalid Pointer Size!");
15141 // For v = setjmp(buf), we generate
15144 // buf[LabelOffset] = restoreMBB
15145 // SjLjSetup restoreMBB
15151 // v = phi(main, restore)
15156 MachineBasicBlock *thisMBB = MBB;
15157 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
15158 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
15159 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
15160 MF->insert(I, mainMBB);
15161 MF->insert(I, sinkMBB);
15162 MF->push_back(restoreMBB);
15164 MachineInstrBuilder MIB;
15166 // Transfer the remainder of BB and its successor edges to sinkMBB.
15167 sinkMBB->splice(sinkMBB->begin(), MBB,
15168 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
15169 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
15172 unsigned PtrStoreOpc = 0;
15173 unsigned LabelReg = 0;
15174 const int64_t LabelOffset = 1 * PVT.getStoreSize();
15175 Reloc::Model RM = getTargetMachine().getRelocationModel();
15176 bool UseImmLabel = (getTargetMachine().getCodeModel() == CodeModel::Small) &&
15177 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
15179 // Prepare IP either in reg or imm.
15180 if (!UseImmLabel) {
15181 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
15182 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
15183 LabelReg = MRI.createVirtualRegister(PtrRC);
15184 if (Subtarget->is64Bit()) {
15185 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
15189 .addMBB(restoreMBB)
15192 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
15193 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
15194 .addReg(XII->getGlobalBaseReg(MF))
15197 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
15201 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
15203 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
15204 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
15205 if (i == X86::AddrDisp)
15206 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
15208 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
15211 MIB.addReg(LabelReg);
15213 MIB.addMBB(restoreMBB);
15214 MIB.setMemRefs(MMOBegin, MMOEnd);
15216 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
15217 .addMBB(restoreMBB);
15219 const X86RegisterInfo *RegInfo =
15220 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
15221 MIB.addRegMask(RegInfo->getNoPreservedMask());
15222 thisMBB->addSuccessor(mainMBB);
15223 thisMBB->addSuccessor(restoreMBB);
15227 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
15228 mainMBB->addSuccessor(sinkMBB);
15231 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
15232 TII->get(X86::PHI), DstReg)
15233 .addReg(mainDstReg).addMBB(mainMBB)
15234 .addReg(restoreDstReg).addMBB(restoreMBB);
15237 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
15238 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
15239 restoreMBB->addSuccessor(sinkMBB);
15241 MI->eraseFromParent();
15245 MachineBasicBlock *
15246 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
15247 MachineBasicBlock *MBB) const {
15248 DebugLoc DL = MI->getDebugLoc();
15249 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15251 MachineFunction *MF = MBB->getParent();
15252 MachineRegisterInfo &MRI = MF->getRegInfo();
15254 // Memory Reference
15255 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
15256 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
15258 MVT PVT = getPointerTy();
15259 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
15260 "Invalid Pointer Size!");
15262 const TargetRegisterClass *RC =
15263 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
15264 unsigned Tmp = MRI.createVirtualRegister(RC);
15265 // Since FP is only updated here but NOT referenced, it's treated as GPR.
15266 const X86RegisterInfo *RegInfo =
15267 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
15268 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
15269 unsigned SP = RegInfo->getStackRegister();
15271 MachineInstrBuilder MIB;
15273 const int64_t LabelOffset = 1 * PVT.getStoreSize();
15274 const int64_t SPOffset = 2 * PVT.getStoreSize();
15276 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
15277 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
15280 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
15281 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
15282 MIB.addOperand(MI->getOperand(i));
15283 MIB.setMemRefs(MMOBegin, MMOEnd);
15285 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
15286 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
15287 if (i == X86::AddrDisp)
15288 MIB.addDisp(MI->getOperand(i), LabelOffset);
15290 MIB.addOperand(MI->getOperand(i));
15292 MIB.setMemRefs(MMOBegin, MMOEnd);
15294 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
15295 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
15296 if (i == X86::AddrDisp)
15297 MIB.addDisp(MI->getOperand(i), SPOffset);
15299 MIB.addOperand(MI->getOperand(i));
15301 MIB.setMemRefs(MMOBegin, MMOEnd);
15303 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
15305 MI->eraseFromParent();
15309 MachineBasicBlock *
15310 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
15311 MachineBasicBlock *BB) const {
15312 switch (MI->getOpcode()) {
15313 default: llvm_unreachable("Unexpected instr type to insert");
15314 case X86::TAILJMPd64:
15315 case X86::TAILJMPr64:
15316 case X86::TAILJMPm64:
15317 llvm_unreachable("TAILJMP64 would not be touched here.");
15318 case X86::TCRETURNdi64:
15319 case X86::TCRETURNri64:
15320 case X86::TCRETURNmi64:
15322 case X86::WIN_ALLOCA:
15323 return EmitLoweredWinAlloca(MI, BB);
15324 case X86::SEG_ALLOCA_32:
15325 return EmitLoweredSegAlloca(MI, BB, false);
15326 case X86::SEG_ALLOCA_64:
15327 return EmitLoweredSegAlloca(MI, BB, true);
15328 case X86::TLSCall_32:
15329 case X86::TLSCall_64:
15330 return EmitLoweredTLSCall(MI, BB);
15331 case X86::CMOV_GR8:
15332 case X86::CMOV_FR32:
15333 case X86::CMOV_FR64:
15334 case X86::CMOV_V4F32:
15335 case X86::CMOV_V2F64:
15336 case X86::CMOV_V2I64:
15337 case X86::CMOV_V8F32:
15338 case X86::CMOV_V4F64:
15339 case X86::CMOV_V4I64:
15340 case X86::CMOV_GR16:
15341 case X86::CMOV_GR32:
15342 case X86::CMOV_RFP32:
15343 case X86::CMOV_RFP64:
15344 case X86::CMOV_RFP80:
15345 return EmitLoweredSelect(MI, BB);
15347 case X86::FP32_TO_INT16_IN_MEM:
15348 case X86::FP32_TO_INT32_IN_MEM:
15349 case X86::FP32_TO_INT64_IN_MEM:
15350 case X86::FP64_TO_INT16_IN_MEM:
15351 case X86::FP64_TO_INT32_IN_MEM:
15352 case X86::FP64_TO_INT64_IN_MEM:
15353 case X86::FP80_TO_INT16_IN_MEM:
15354 case X86::FP80_TO_INT32_IN_MEM:
15355 case X86::FP80_TO_INT64_IN_MEM: {
15356 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15357 DebugLoc DL = MI->getDebugLoc();
15359 // Change the floating point control register to use "round towards zero"
15360 // mode when truncating to an integer value.
15361 MachineFunction *F = BB->getParent();
15362 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
15363 addFrameReference(BuildMI(*BB, MI, DL,
15364 TII->get(X86::FNSTCW16m)), CWFrameIdx);
15366 // Load the old value of the high byte of the control word...
15368 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
15369 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
15372 // Set the high part to be round to zero...
15373 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
15376 // Reload the modified control word now...
15377 addFrameReference(BuildMI(*BB, MI, DL,
15378 TII->get(X86::FLDCW16m)), CWFrameIdx);
15380 // Restore the memory image of control word to original value
15381 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
15384 // Get the X86 opcode to use.
15386 switch (MI->getOpcode()) {
15387 default: llvm_unreachable("illegal opcode!");
15388 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
15389 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
15390 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
15391 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
15392 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
15393 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
15394 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
15395 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
15396 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
15400 MachineOperand &Op = MI->getOperand(0);
15402 AM.BaseType = X86AddressMode::RegBase;
15403 AM.Base.Reg = Op.getReg();
15405 AM.BaseType = X86AddressMode::FrameIndexBase;
15406 AM.Base.FrameIndex = Op.getIndex();
15408 Op = MI->getOperand(1);
15410 AM.Scale = Op.getImm();
15411 Op = MI->getOperand(2);
15413 AM.IndexReg = Op.getImm();
15414 Op = MI->getOperand(3);
15415 if (Op.isGlobal()) {
15416 AM.GV = Op.getGlobal();
15418 AM.Disp = Op.getImm();
15420 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
15421 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
15423 // Reload the original control word now.
15424 addFrameReference(BuildMI(*BB, MI, DL,
15425 TII->get(X86::FLDCW16m)), CWFrameIdx);
15427 MI->eraseFromParent(); // The pseudo instruction is gone now.
15430 // String/text processing lowering.
15431 case X86::PCMPISTRM128REG:
15432 case X86::VPCMPISTRM128REG:
15433 case X86::PCMPISTRM128MEM:
15434 case X86::VPCMPISTRM128MEM:
15435 case X86::PCMPESTRM128REG:
15436 case X86::VPCMPESTRM128REG:
15437 case X86::PCMPESTRM128MEM:
15438 case X86::VPCMPESTRM128MEM:
15439 assert(Subtarget->hasSSE42() &&
15440 "Target must have SSE4.2 or AVX features enabled");
15441 return EmitPCMPSTRM(MI, BB, getTargetMachine().getInstrInfo());
15443 // String/text processing lowering.
15444 case X86::PCMPISTRIREG:
15445 case X86::VPCMPISTRIREG:
15446 case X86::PCMPISTRIMEM:
15447 case X86::VPCMPISTRIMEM:
15448 case X86::PCMPESTRIREG:
15449 case X86::VPCMPESTRIREG:
15450 case X86::PCMPESTRIMEM:
15451 case X86::VPCMPESTRIMEM:
15452 assert(Subtarget->hasSSE42() &&
15453 "Target must have SSE4.2 or AVX features enabled");
15454 return EmitPCMPSTRI(MI, BB, getTargetMachine().getInstrInfo());
15456 // Thread synchronization.
15458 return EmitMonitor(MI, BB, getTargetMachine().getInstrInfo(), Subtarget);
15462 return EmitXBegin(MI, BB, getTargetMachine().getInstrInfo());
15464 // Atomic Lowering.
15465 case X86::ATOMAND8:
15466 case X86::ATOMAND16:
15467 case X86::ATOMAND32:
15468 case X86::ATOMAND64:
15471 case X86::ATOMOR16:
15472 case X86::ATOMOR32:
15473 case X86::ATOMOR64:
15475 case X86::ATOMXOR16:
15476 case X86::ATOMXOR8:
15477 case X86::ATOMXOR32:
15478 case X86::ATOMXOR64:
15480 case X86::ATOMNAND8:
15481 case X86::ATOMNAND16:
15482 case X86::ATOMNAND32:
15483 case X86::ATOMNAND64:
15485 case X86::ATOMMAX8:
15486 case X86::ATOMMAX16:
15487 case X86::ATOMMAX32:
15488 case X86::ATOMMAX64:
15490 case X86::ATOMMIN8:
15491 case X86::ATOMMIN16:
15492 case X86::ATOMMIN32:
15493 case X86::ATOMMIN64:
15495 case X86::ATOMUMAX8:
15496 case X86::ATOMUMAX16:
15497 case X86::ATOMUMAX32:
15498 case X86::ATOMUMAX64:
15500 case X86::ATOMUMIN8:
15501 case X86::ATOMUMIN16:
15502 case X86::ATOMUMIN32:
15503 case X86::ATOMUMIN64:
15504 return EmitAtomicLoadArith(MI, BB);
15506 // This group does 64-bit operations on a 32-bit host.
15507 case X86::ATOMAND6432:
15508 case X86::ATOMOR6432:
15509 case X86::ATOMXOR6432:
15510 case X86::ATOMNAND6432:
15511 case X86::ATOMADD6432:
15512 case X86::ATOMSUB6432:
15513 case X86::ATOMMAX6432:
15514 case X86::ATOMMIN6432:
15515 case X86::ATOMUMAX6432:
15516 case X86::ATOMUMIN6432:
15517 case X86::ATOMSWAP6432:
15518 return EmitAtomicLoadArith6432(MI, BB);
15520 case X86::VASTART_SAVE_XMM_REGS:
15521 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
15523 case X86::VAARG_64:
15524 return EmitVAARG64WithCustomInserter(MI, BB);
15526 case X86::EH_SjLj_SetJmp32:
15527 case X86::EH_SjLj_SetJmp64:
15528 return emitEHSjLjSetJmp(MI, BB);
15530 case X86::EH_SjLj_LongJmp32:
15531 case X86::EH_SjLj_LongJmp64:
15532 return emitEHSjLjLongJmp(MI, BB);
15536 //===----------------------------------------------------------------------===//
15537 // X86 Optimization Hooks
15538 //===----------------------------------------------------------------------===//
15540 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
15543 const SelectionDAG &DAG,
15544 unsigned Depth) const {
15545 unsigned BitWidth = KnownZero.getBitWidth();
15546 unsigned Opc = Op.getOpcode();
15547 assert((Opc >= ISD::BUILTIN_OP_END ||
15548 Opc == ISD::INTRINSIC_WO_CHAIN ||
15549 Opc == ISD::INTRINSIC_W_CHAIN ||
15550 Opc == ISD::INTRINSIC_VOID) &&
15551 "Should use MaskedValueIsZero if you don't know whether Op"
15552 " is a target node!");
15554 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
15568 // These nodes' second result is a boolean.
15569 if (Op.getResNo() == 0)
15572 case X86ISD::SETCC:
15573 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
15575 case ISD::INTRINSIC_WO_CHAIN: {
15576 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15577 unsigned NumLoBits = 0;
15580 case Intrinsic::x86_sse_movmsk_ps:
15581 case Intrinsic::x86_avx_movmsk_ps_256:
15582 case Intrinsic::x86_sse2_movmsk_pd:
15583 case Intrinsic::x86_avx_movmsk_pd_256:
15584 case Intrinsic::x86_mmx_pmovmskb:
15585 case Intrinsic::x86_sse2_pmovmskb_128:
15586 case Intrinsic::x86_avx2_pmovmskb: {
15587 // High bits of movmskp{s|d}, pmovmskb are known zero.
15589 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
15590 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
15591 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
15592 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
15593 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
15594 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
15595 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
15596 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
15598 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
15607 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
15608 unsigned Depth) const {
15609 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
15610 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
15611 return Op.getValueType().getScalarType().getSizeInBits();
15617 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
15618 /// node is a GlobalAddress + offset.
15619 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
15620 const GlobalValue* &GA,
15621 int64_t &Offset) const {
15622 if (N->getOpcode() == X86ISD::Wrapper) {
15623 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
15624 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
15625 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
15629 return TargetLowering::isGAPlusOffset(N, GA, Offset);
15632 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
15633 /// same as extracting the high 128-bit part of 256-bit vector and then
15634 /// inserting the result into the low part of a new 256-bit vector
15635 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
15636 EVT VT = SVOp->getValueType(0);
15637 unsigned NumElems = VT.getVectorNumElements();
15639 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
15640 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
15641 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
15642 SVOp->getMaskElt(j) >= 0)
15648 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
15649 /// same as extracting the low 128-bit part of 256-bit vector and then
15650 /// inserting the result into the high part of a new 256-bit vector
15651 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
15652 EVT VT = SVOp->getValueType(0);
15653 unsigned NumElems = VT.getVectorNumElements();
15655 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
15656 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
15657 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
15658 SVOp->getMaskElt(j) >= 0)
15664 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
15665 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
15666 TargetLowering::DAGCombinerInfo &DCI,
15667 const X86Subtarget* Subtarget) {
15669 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
15670 SDValue V1 = SVOp->getOperand(0);
15671 SDValue V2 = SVOp->getOperand(1);
15672 EVT VT = SVOp->getValueType(0);
15673 unsigned NumElems = VT.getVectorNumElements();
15675 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
15676 V2.getOpcode() == ISD::CONCAT_VECTORS) {
15680 // V UNDEF BUILD_VECTOR UNDEF
15682 // CONCAT_VECTOR CONCAT_VECTOR
15685 // RESULT: V + zero extended
15687 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
15688 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
15689 V1.getOperand(1).getOpcode() != ISD::UNDEF)
15692 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
15695 // To match the shuffle mask, the first half of the mask should
15696 // be exactly the first vector, and all the rest a splat with the
15697 // first element of the second one.
15698 for (unsigned i = 0; i != NumElems/2; ++i)
15699 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
15700 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
15703 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
15704 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
15705 if (Ld->hasNUsesOfValue(1, 0)) {
15706 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
15707 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
15709 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
15710 array_lengthof(Ops),
15712 Ld->getPointerInfo(),
15713 Ld->getAlignment(),
15714 false/*isVolatile*/, true/*ReadMem*/,
15715 false/*WriteMem*/);
15717 // Make sure the newly-created LOAD is in the same position as Ld in
15718 // terms of dependency. We create a TokenFactor for Ld and ResNode,
15719 // and update uses of Ld's output chain to use the TokenFactor.
15720 if (Ld->hasAnyUseOfValue(1)) {
15721 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
15722 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
15723 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
15724 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
15725 SDValue(ResNode.getNode(), 1));
15728 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
15732 // Emit a zeroed vector and insert the desired subvector on its
15734 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
15735 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
15736 return DCI.CombineTo(N, InsV);
15739 //===--------------------------------------------------------------------===//
15740 // Combine some shuffles into subvector extracts and inserts:
15743 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
15744 if (isShuffleHigh128VectorInsertLow(SVOp)) {
15745 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
15746 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
15747 return DCI.CombineTo(N, InsV);
15750 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
15751 if (isShuffleLow128VectorInsertHigh(SVOp)) {
15752 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
15753 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
15754 return DCI.CombineTo(N, InsV);
15760 /// PerformShuffleCombine - Performs several different shuffle combines.
15761 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
15762 TargetLowering::DAGCombinerInfo &DCI,
15763 const X86Subtarget *Subtarget) {
15765 EVT VT = N->getValueType(0);
15767 // Don't create instructions with illegal types after legalize types has run.
15768 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15769 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
15772 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
15773 if (Subtarget->hasFp256() && VT.is256BitVector() &&
15774 N->getOpcode() == ISD::VECTOR_SHUFFLE)
15775 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
15777 // Only handle 128 wide vector from here on.
15778 if (!VT.is128BitVector())
15781 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
15782 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
15783 // consecutive, non-overlapping, and in the right order.
15784 SmallVector<SDValue, 16> Elts;
15785 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
15786 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
15788 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG);
15791 /// PerformTruncateCombine - Converts truncate operation to
15792 /// a sequence of vector shuffle operations.
15793 /// It is possible when we truncate 256-bit vector to 128-bit vector
15794 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
15795 TargetLowering::DAGCombinerInfo &DCI,
15796 const X86Subtarget *Subtarget) {
15800 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
15801 /// specific shuffle of a load can be folded into a single element load.
15802 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
15803 /// shuffles have been customed lowered so we need to handle those here.
15804 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
15805 TargetLowering::DAGCombinerInfo &DCI) {
15806 if (DCI.isBeforeLegalizeOps())
15809 SDValue InVec = N->getOperand(0);
15810 SDValue EltNo = N->getOperand(1);
15812 if (!isa<ConstantSDNode>(EltNo))
15815 EVT VT = InVec.getValueType();
15817 bool HasShuffleIntoBitcast = false;
15818 if (InVec.getOpcode() == ISD::BITCAST) {
15819 // Don't duplicate a load with other uses.
15820 if (!InVec.hasOneUse())
15822 EVT BCVT = InVec.getOperand(0).getValueType();
15823 if (BCVT.getVectorNumElements() != VT.getVectorNumElements())
15825 InVec = InVec.getOperand(0);
15826 HasShuffleIntoBitcast = true;
15829 if (!isTargetShuffle(InVec.getOpcode()))
15832 // Don't duplicate a load with other uses.
15833 if (!InVec.hasOneUse())
15836 SmallVector<int, 16> ShuffleMask;
15838 if (!getTargetShuffleMask(InVec.getNode(), VT.getSimpleVT(), ShuffleMask,
15842 // Select the input vector, guarding against out of range extract vector.
15843 unsigned NumElems = VT.getVectorNumElements();
15844 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
15845 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
15846 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
15847 : InVec.getOperand(1);
15849 // If inputs to shuffle are the same for both ops, then allow 2 uses
15850 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
15852 if (LdNode.getOpcode() == ISD::BITCAST) {
15853 // Don't duplicate a load with other uses.
15854 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
15857 AllowedUses = 1; // only allow 1 load use if we have a bitcast
15858 LdNode = LdNode.getOperand(0);
15861 if (!ISD::isNormalLoad(LdNode.getNode()))
15864 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
15866 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
15869 if (HasShuffleIntoBitcast) {
15870 // If there's a bitcast before the shuffle, check if the load type and
15871 // alignment is valid.
15872 unsigned Align = LN0->getAlignment();
15873 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15874 unsigned NewAlign = TLI.getDataLayout()->
15875 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
15877 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
15881 // All checks match so transform back to vector_shuffle so that DAG combiner
15882 // can finish the job
15885 // Create shuffle node taking into account the case that its a unary shuffle
15886 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1);
15887 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl,
15888 InVec.getOperand(0), Shuffle,
15890 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
15891 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
15895 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
15896 /// generation and convert it from being a bunch of shuffles and extracts
15897 /// to a simple store and scalar loads to extract the elements.
15898 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
15899 TargetLowering::DAGCombinerInfo &DCI) {
15900 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
15901 if (NewOp.getNode())
15904 SDValue InputVector = N->getOperand(0);
15905 // Detect whether we are trying to convert from mmx to i32 and the bitcast
15906 // from mmx to v2i32 has a single usage.
15907 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
15908 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
15909 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
15910 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
15911 N->getValueType(0),
15912 InputVector.getNode()->getOperand(0));
15914 // Only operate on vectors of 4 elements, where the alternative shuffling
15915 // gets to be more expensive.
15916 if (InputVector.getValueType() != MVT::v4i32)
15919 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
15920 // single use which is a sign-extend or zero-extend, and all elements are
15922 SmallVector<SDNode *, 4> Uses;
15923 unsigned ExtractedElements = 0;
15924 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
15925 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
15926 if (UI.getUse().getResNo() != InputVector.getResNo())
15929 SDNode *Extract = *UI;
15930 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
15933 if (Extract->getValueType(0) != MVT::i32)
15935 if (!Extract->hasOneUse())
15937 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
15938 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
15940 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
15943 // Record which element was extracted.
15944 ExtractedElements |=
15945 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
15947 Uses.push_back(Extract);
15950 // If not all the elements were used, this may not be worthwhile.
15951 if (ExtractedElements != 15)
15954 // Ok, we've now decided to do the transformation.
15955 SDLoc dl(InputVector);
15957 // Store the value to a temporary stack slot.
15958 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
15959 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
15960 MachinePointerInfo(), false, false, 0);
15962 // Replace each use (extract) with a load of the appropriate element.
15963 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
15964 UE = Uses.end(); UI != UE; ++UI) {
15965 SDNode *Extract = *UI;
15967 // cOMpute the element's address.
15968 SDValue Idx = Extract->getOperand(1);
15970 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
15971 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
15972 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15973 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
15975 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
15976 StackPtr, OffsetVal);
15978 // Load the scalar.
15979 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
15980 ScalarAddr, MachinePointerInfo(),
15981 false, false, false, 0);
15983 // Replace the exact with the load.
15984 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
15987 // The replacement was made in place; don't return anything.
15991 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
15992 static unsigned matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS,
15993 SDValue RHS, SelectionDAG &DAG,
15994 const X86Subtarget *Subtarget) {
15995 if (!VT.isVector())
15998 switch (VT.getSimpleVT().SimpleTy) {
16003 if (!Subtarget->hasAVX2())
16008 if (!Subtarget->hasSSE2())
16012 // SSE2 has only a small subset of the operations.
16013 bool hasUnsigned = Subtarget->hasSSE41() ||
16014 (Subtarget->hasSSE2() && VT == MVT::v16i8);
16015 bool hasSigned = Subtarget->hasSSE41() ||
16016 (Subtarget->hasSSE2() && VT == MVT::v8i16);
16018 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
16020 // Check for x CC y ? x : y.
16021 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
16022 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
16027 return hasUnsigned ? X86ISD::UMIN : 0;
16030 return hasUnsigned ? X86ISD::UMAX : 0;
16033 return hasSigned ? X86ISD::SMIN : 0;
16036 return hasSigned ? X86ISD::SMAX : 0;
16038 // Check for x CC y ? y : x -- a min/max with reversed arms.
16039 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
16040 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
16045 return hasUnsigned ? X86ISD::UMAX : 0;
16048 return hasUnsigned ? X86ISD::UMIN : 0;
16051 return hasSigned ? X86ISD::SMAX : 0;
16054 return hasSigned ? X86ISD::SMIN : 0;
16061 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
16063 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
16064 TargetLowering::DAGCombinerInfo &DCI,
16065 const X86Subtarget *Subtarget) {
16067 SDValue Cond = N->getOperand(0);
16068 // Get the LHS/RHS of the select.
16069 SDValue LHS = N->getOperand(1);
16070 SDValue RHS = N->getOperand(2);
16071 EVT VT = LHS.getValueType();
16073 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
16074 // instructions match the semantics of the common C idiom x<y?x:y but not
16075 // x<=y?x:y, because of how they handle negative zero (which can be
16076 // ignored in unsafe-math mode).
16077 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
16078 VT != MVT::f80 && DAG.getTargetLoweringInfo().isTypeLegal(VT) &&
16079 (Subtarget->hasSSE2() ||
16080 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
16081 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
16083 unsigned Opcode = 0;
16084 // Check for x CC y ? x : y.
16085 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
16086 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
16090 // Converting this to a min would handle NaNs incorrectly, and swapping
16091 // the operands would cause it to handle comparisons between positive
16092 // and negative zero incorrectly.
16093 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
16094 if (!DAG.getTarget().Options.UnsafeFPMath &&
16095 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
16097 std::swap(LHS, RHS);
16099 Opcode = X86ISD::FMIN;
16102 // Converting this to a min would handle comparisons between positive
16103 // and negative zero incorrectly.
16104 if (!DAG.getTarget().Options.UnsafeFPMath &&
16105 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
16107 Opcode = X86ISD::FMIN;
16110 // Converting this to a min would handle both negative zeros and NaNs
16111 // incorrectly, but we can swap the operands to fix both.
16112 std::swap(LHS, RHS);
16116 Opcode = X86ISD::FMIN;
16120 // Converting this to a max would handle comparisons between positive
16121 // and negative zero incorrectly.
16122 if (!DAG.getTarget().Options.UnsafeFPMath &&
16123 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
16125 Opcode = X86ISD::FMAX;
16128 // Converting this to a max would handle NaNs incorrectly, and swapping
16129 // the operands would cause it to handle comparisons between positive
16130 // and negative zero incorrectly.
16131 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
16132 if (!DAG.getTarget().Options.UnsafeFPMath &&
16133 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
16135 std::swap(LHS, RHS);
16137 Opcode = X86ISD::FMAX;
16140 // Converting this to a max would handle both negative zeros and NaNs
16141 // incorrectly, but we can swap the operands to fix both.
16142 std::swap(LHS, RHS);
16146 Opcode = X86ISD::FMAX;
16149 // Check for x CC y ? y : x -- a min/max with reversed arms.
16150 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
16151 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
16155 // Converting this to a min would handle comparisons between positive
16156 // and negative zero incorrectly, and swapping the operands would
16157 // cause it to handle NaNs incorrectly.
16158 if (!DAG.getTarget().Options.UnsafeFPMath &&
16159 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
16160 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
16162 std::swap(LHS, RHS);
16164 Opcode = X86ISD::FMIN;
16167 // Converting this to a min would handle NaNs incorrectly.
16168 if (!DAG.getTarget().Options.UnsafeFPMath &&
16169 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
16171 Opcode = X86ISD::FMIN;
16174 // Converting this to a min would handle both negative zeros and NaNs
16175 // incorrectly, but we can swap the operands to fix both.
16176 std::swap(LHS, RHS);
16180 Opcode = X86ISD::FMIN;
16184 // Converting this to a max would handle NaNs incorrectly.
16185 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
16187 Opcode = X86ISD::FMAX;
16190 // Converting this to a max would handle comparisons between positive
16191 // and negative zero incorrectly, and swapping the operands would
16192 // cause it to handle NaNs incorrectly.
16193 if (!DAG.getTarget().Options.UnsafeFPMath &&
16194 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
16195 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
16197 std::swap(LHS, RHS);
16199 Opcode = X86ISD::FMAX;
16202 // Converting this to a max would handle both negative zeros and NaNs
16203 // incorrectly, but we can swap the operands to fix both.
16204 std::swap(LHS, RHS);
16208 Opcode = X86ISD::FMAX;
16214 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
16217 // If this is a select between two integer constants, try to do some
16219 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
16220 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
16221 // Don't do this for crazy integer types.
16222 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
16223 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
16224 // so that TrueC (the true value) is larger than FalseC.
16225 bool NeedsCondInvert = false;
16227 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
16228 // Efficiently invertible.
16229 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
16230 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
16231 isa<ConstantSDNode>(Cond.getOperand(1))))) {
16232 NeedsCondInvert = true;
16233 std::swap(TrueC, FalseC);
16236 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
16237 if (FalseC->getAPIntValue() == 0 &&
16238 TrueC->getAPIntValue().isPowerOf2()) {
16239 if (NeedsCondInvert) // Invert the condition if needed.
16240 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
16241 DAG.getConstant(1, Cond.getValueType()));
16243 // Zero extend the condition if needed.
16244 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
16246 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
16247 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
16248 DAG.getConstant(ShAmt, MVT::i8));
16251 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
16252 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
16253 if (NeedsCondInvert) // Invert the condition if needed.
16254 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
16255 DAG.getConstant(1, Cond.getValueType()));
16257 // Zero extend the condition if needed.
16258 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
16259 FalseC->getValueType(0), Cond);
16260 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
16261 SDValue(FalseC, 0));
16264 // Optimize cases that will turn into an LEA instruction. This requires
16265 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
16266 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
16267 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
16268 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
16270 bool isFastMultiplier = false;
16272 switch ((unsigned char)Diff) {
16274 case 1: // result = add base, cond
16275 case 2: // result = lea base( , cond*2)
16276 case 3: // result = lea base(cond, cond*2)
16277 case 4: // result = lea base( , cond*4)
16278 case 5: // result = lea base(cond, cond*4)
16279 case 8: // result = lea base( , cond*8)
16280 case 9: // result = lea base(cond, cond*8)
16281 isFastMultiplier = true;
16286 if (isFastMultiplier) {
16287 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
16288 if (NeedsCondInvert) // Invert the condition if needed.
16289 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
16290 DAG.getConstant(1, Cond.getValueType()));
16292 // Zero extend the condition if needed.
16293 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
16295 // Scale the condition by the difference.
16297 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
16298 DAG.getConstant(Diff, Cond.getValueType()));
16300 // Add the base if non-zero.
16301 if (FalseC->getAPIntValue() != 0)
16302 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
16303 SDValue(FalseC, 0));
16310 // Canonicalize max and min:
16311 // (x > y) ? x : y -> (x >= y) ? x : y
16312 // (x < y) ? x : y -> (x <= y) ? x : y
16313 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
16314 // the need for an extra compare
16315 // against zero. e.g.
16316 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
16318 // testl %edi, %edi
16320 // cmovgl %edi, %eax
16324 // cmovsl %eax, %edi
16325 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
16326 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
16327 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
16328 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
16333 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
16334 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
16335 Cond.getOperand(0), Cond.getOperand(1), NewCC);
16336 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
16341 // Match VSELECTs into subs with unsigned saturation.
16342 if (!DCI.isBeforeLegalize() &&
16343 N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
16344 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
16345 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
16346 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
16347 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
16349 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
16350 // left side invert the predicate to simplify logic below.
16352 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
16354 CC = ISD::getSetCCInverse(CC, true);
16355 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
16359 if (Other.getNode() && Other->getNumOperands() == 2 &&
16360 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
16361 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
16362 SDValue CondRHS = Cond->getOperand(1);
16364 // Look for a general sub with unsigned saturation first.
16365 // x >= y ? x-y : 0 --> subus x, y
16366 // x > y ? x-y : 0 --> subus x, y
16367 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
16368 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
16369 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
16371 // If the RHS is a constant we have to reverse the const canonicalization.
16372 // x > C-1 ? x+-C : 0 --> subus x, C
16373 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
16374 isSplatVector(CondRHS.getNode()) && isSplatVector(OpRHS.getNode())) {
16375 APInt A = cast<ConstantSDNode>(OpRHS.getOperand(0))->getAPIntValue();
16376 if (CondRHS.getConstantOperandVal(0) == -A-1)
16377 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS,
16378 DAG.getConstant(-A, VT));
16381 // Another special case: If C was a sign bit, the sub has been
16382 // canonicalized into a xor.
16383 // FIXME: Would it be better to use ComputeMaskedBits to determine whether
16384 // it's safe to decanonicalize the xor?
16385 // x s< 0 ? x^C : 0 --> subus x, C
16386 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
16387 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
16388 isSplatVector(OpRHS.getNode())) {
16389 APInt A = cast<ConstantSDNode>(OpRHS.getOperand(0))->getAPIntValue();
16391 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
16396 // Try to match a min/max vector operation.
16397 if (!DCI.isBeforeLegalize() &&
16398 N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC)
16399 if (unsigned Op = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget))
16400 return DAG.getNode(Op, DL, N->getValueType(0), LHS, RHS);
16402 // Simplify vector selection if the selector will be produced by CMPP*/PCMP*.
16403 if (!DCI.isBeforeLegalize() && N->getOpcode() == ISD::VSELECT &&
16404 Cond.getOpcode() == ISD::SETCC) {
16406 assert(Cond.getValueType().isVector() &&
16407 "vector select expects a vector selector!");
16409 EVT IntVT = Cond.getValueType();
16410 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
16411 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
16413 if (!TValIsAllOnes && !FValIsAllZeros) {
16414 // Try invert the condition if true value is not all 1s and false value
16416 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
16417 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
16419 if (TValIsAllZeros || FValIsAllOnes) {
16420 SDValue CC = Cond.getOperand(2);
16421 ISD::CondCode NewCC =
16422 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
16423 Cond.getOperand(0).getValueType().isInteger());
16424 Cond = DAG.getSetCC(DL, IntVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
16425 std::swap(LHS, RHS);
16426 TValIsAllOnes = FValIsAllOnes;
16427 FValIsAllZeros = TValIsAllZeros;
16431 if (TValIsAllOnes || FValIsAllZeros) {
16434 if (TValIsAllOnes && FValIsAllZeros)
16436 else if (TValIsAllOnes)
16437 Ret = DAG.getNode(ISD::OR, DL, IntVT, Cond,
16438 DAG.getNode(ISD::BITCAST, DL, IntVT, RHS));
16439 else if (FValIsAllZeros)
16440 Ret = DAG.getNode(ISD::AND, DL, IntVT, Cond,
16441 DAG.getNode(ISD::BITCAST, DL, IntVT, LHS));
16443 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
16447 // If we know that this node is legal then we know that it is going to be
16448 // matched by one of the SSE/AVX BLEND instructions. These instructions only
16449 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
16450 // to simplify previous instructions.
16451 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16452 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
16453 !DCI.isBeforeLegalize() && TLI.isOperationLegal(ISD::VSELECT, VT)) {
16454 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
16456 // Don't optimize vector selects that map to mask-registers.
16460 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
16461 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
16463 APInt KnownZero, KnownOne;
16464 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
16465 DCI.isBeforeLegalizeOps());
16466 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
16467 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
16468 DCI.CommitTargetLoweringOpt(TLO);
16474 // Check whether a boolean test is testing a boolean value generated by
16475 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
16478 // Simplify the following patterns:
16479 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
16480 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
16481 // to (Op EFLAGS Cond)
16483 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
16484 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
16485 // to (Op EFLAGS !Cond)
16487 // where Op could be BRCOND or CMOV.
16489 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
16490 // Quit if not CMP and SUB with its value result used.
16491 if (Cmp.getOpcode() != X86ISD::CMP &&
16492 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
16495 // Quit if not used as a boolean value.
16496 if (CC != X86::COND_E && CC != X86::COND_NE)
16499 // Check CMP operands. One of them should be 0 or 1 and the other should be
16500 // an SetCC or extended from it.
16501 SDValue Op1 = Cmp.getOperand(0);
16502 SDValue Op2 = Cmp.getOperand(1);
16505 const ConstantSDNode* C = 0;
16506 bool needOppositeCond = (CC == X86::COND_E);
16507 bool checkAgainstTrue = false; // Is it a comparison against 1?
16509 if ((C = dyn_cast<ConstantSDNode>(Op1)))
16511 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
16513 else // Quit if all operands are not constants.
16516 if (C->getZExtValue() == 1) {
16517 needOppositeCond = !needOppositeCond;
16518 checkAgainstTrue = true;
16519 } else if (C->getZExtValue() != 0)
16520 // Quit if the constant is neither 0 or 1.
16523 bool truncatedToBoolWithAnd = false;
16524 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
16525 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
16526 SetCC.getOpcode() == ISD::TRUNCATE ||
16527 SetCC.getOpcode() == ISD::AND) {
16528 if (SetCC.getOpcode() == ISD::AND) {
16530 ConstantSDNode *CS;
16531 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
16532 CS->getZExtValue() == 1)
16534 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
16535 CS->getZExtValue() == 1)
16539 SetCC = SetCC.getOperand(OpIdx);
16540 truncatedToBoolWithAnd = true;
16542 SetCC = SetCC.getOperand(0);
16545 switch (SetCC.getOpcode()) {
16546 case X86ISD::SETCC_CARRY:
16547 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
16548 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
16549 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
16550 // truncated to i1 using 'and'.
16551 if (checkAgainstTrue && !truncatedToBoolWithAnd)
16553 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
16554 "Invalid use of SETCC_CARRY!");
16556 case X86ISD::SETCC:
16557 // Set the condition code or opposite one if necessary.
16558 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
16559 if (needOppositeCond)
16560 CC = X86::GetOppositeBranchCondition(CC);
16561 return SetCC.getOperand(1);
16562 case X86ISD::CMOV: {
16563 // Check whether false/true value has canonical one, i.e. 0 or 1.
16564 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
16565 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
16566 // Quit if true value is not a constant.
16569 // Quit if false value is not a constant.
16571 SDValue Op = SetCC.getOperand(0);
16572 // Skip 'zext' or 'trunc' node.
16573 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
16574 Op.getOpcode() == ISD::TRUNCATE)
16575 Op = Op.getOperand(0);
16576 // A special case for rdrand/rdseed, where 0 is set if false cond is
16578 if ((Op.getOpcode() != X86ISD::RDRAND &&
16579 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
16582 // Quit if false value is not the constant 0 or 1.
16583 bool FValIsFalse = true;
16584 if (FVal && FVal->getZExtValue() != 0) {
16585 if (FVal->getZExtValue() != 1)
16587 // If FVal is 1, opposite cond is needed.
16588 needOppositeCond = !needOppositeCond;
16589 FValIsFalse = false;
16591 // Quit if TVal is not the constant opposite of FVal.
16592 if (FValIsFalse && TVal->getZExtValue() != 1)
16594 if (!FValIsFalse && TVal->getZExtValue() != 0)
16596 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
16597 if (needOppositeCond)
16598 CC = X86::GetOppositeBranchCondition(CC);
16599 return SetCC.getOperand(3);
16606 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
16607 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
16608 TargetLowering::DAGCombinerInfo &DCI,
16609 const X86Subtarget *Subtarget) {
16612 // If the flag operand isn't dead, don't touch this CMOV.
16613 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
16616 SDValue FalseOp = N->getOperand(0);
16617 SDValue TrueOp = N->getOperand(1);
16618 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
16619 SDValue Cond = N->getOperand(3);
16621 if (CC == X86::COND_E || CC == X86::COND_NE) {
16622 switch (Cond.getOpcode()) {
16626 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
16627 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
16628 return (CC == X86::COND_E) ? FalseOp : TrueOp;
16634 Flags = checkBoolTestSetCCCombine(Cond, CC);
16635 if (Flags.getNode() &&
16636 // Extra check as FCMOV only supports a subset of X86 cond.
16637 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
16638 SDValue Ops[] = { FalseOp, TrueOp,
16639 DAG.getConstant(CC, MVT::i8), Flags };
16640 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(),
16641 Ops, array_lengthof(Ops));
16644 // If this is a select between two integer constants, try to do some
16645 // optimizations. Note that the operands are ordered the opposite of SELECT
16647 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
16648 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
16649 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
16650 // larger than FalseC (the false value).
16651 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
16652 CC = X86::GetOppositeBranchCondition(CC);
16653 std::swap(TrueC, FalseC);
16654 std::swap(TrueOp, FalseOp);
16657 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
16658 // This is efficient for any integer data type (including i8/i16) and
16660 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
16661 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
16662 DAG.getConstant(CC, MVT::i8), Cond);
16664 // Zero extend the condition if needed.
16665 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
16667 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
16668 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
16669 DAG.getConstant(ShAmt, MVT::i8));
16670 if (N->getNumValues() == 2) // Dead flag value?
16671 return DCI.CombineTo(N, Cond, SDValue());
16675 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
16676 // for any integer data type, including i8/i16.
16677 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
16678 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
16679 DAG.getConstant(CC, MVT::i8), Cond);
16681 // Zero extend the condition if needed.
16682 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
16683 FalseC->getValueType(0), Cond);
16684 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
16685 SDValue(FalseC, 0));
16687 if (N->getNumValues() == 2) // Dead flag value?
16688 return DCI.CombineTo(N, Cond, SDValue());
16692 // Optimize cases that will turn into an LEA instruction. This requires
16693 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
16694 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
16695 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
16696 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
16698 bool isFastMultiplier = false;
16700 switch ((unsigned char)Diff) {
16702 case 1: // result = add base, cond
16703 case 2: // result = lea base( , cond*2)
16704 case 3: // result = lea base(cond, cond*2)
16705 case 4: // result = lea base( , cond*4)
16706 case 5: // result = lea base(cond, cond*4)
16707 case 8: // result = lea base( , cond*8)
16708 case 9: // result = lea base(cond, cond*8)
16709 isFastMultiplier = true;
16714 if (isFastMultiplier) {
16715 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
16716 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
16717 DAG.getConstant(CC, MVT::i8), Cond);
16718 // Zero extend the condition if needed.
16719 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
16721 // Scale the condition by the difference.
16723 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
16724 DAG.getConstant(Diff, Cond.getValueType()));
16726 // Add the base if non-zero.
16727 if (FalseC->getAPIntValue() != 0)
16728 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
16729 SDValue(FalseC, 0));
16730 if (N->getNumValues() == 2) // Dead flag value?
16731 return DCI.CombineTo(N, Cond, SDValue());
16738 // Handle these cases:
16739 // (select (x != c), e, c) -> select (x != c), e, x),
16740 // (select (x == c), c, e) -> select (x == c), x, e)
16741 // where the c is an integer constant, and the "select" is the combination
16742 // of CMOV and CMP.
16744 // The rationale for this change is that the conditional-move from a constant
16745 // needs two instructions, however, conditional-move from a register needs
16746 // only one instruction.
16748 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
16749 // some instruction-combining opportunities. This opt needs to be
16750 // postponed as late as possible.
16752 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
16753 // the DCI.xxxx conditions are provided to postpone the optimization as
16754 // late as possible.
16756 ConstantSDNode *CmpAgainst = 0;
16757 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
16758 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
16759 !isa<ConstantSDNode>(Cond.getOperand(0))) {
16761 if (CC == X86::COND_NE &&
16762 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
16763 CC = X86::GetOppositeBranchCondition(CC);
16764 std::swap(TrueOp, FalseOp);
16767 if (CC == X86::COND_E &&
16768 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
16769 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
16770 DAG.getConstant(CC, MVT::i8), Cond };
16771 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops,
16772 array_lengthof(Ops));
16780 /// PerformMulCombine - Optimize a single multiply with constant into two
16781 /// in order to implement it with two cheaper instructions, e.g.
16782 /// LEA + SHL, LEA + LEA.
16783 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
16784 TargetLowering::DAGCombinerInfo &DCI) {
16785 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
16788 EVT VT = N->getValueType(0);
16789 if (VT != MVT::i64)
16792 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
16795 uint64_t MulAmt = C->getZExtValue();
16796 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
16799 uint64_t MulAmt1 = 0;
16800 uint64_t MulAmt2 = 0;
16801 if ((MulAmt % 9) == 0) {
16803 MulAmt2 = MulAmt / 9;
16804 } else if ((MulAmt % 5) == 0) {
16806 MulAmt2 = MulAmt / 5;
16807 } else if ((MulAmt % 3) == 0) {
16809 MulAmt2 = MulAmt / 3;
16812 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
16815 if (isPowerOf2_64(MulAmt2) &&
16816 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
16817 // If second multiplifer is pow2, issue it first. We want the multiply by
16818 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
16820 std::swap(MulAmt1, MulAmt2);
16823 if (isPowerOf2_64(MulAmt1))
16824 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
16825 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
16827 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
16828 DAG.getConstant(MulAmt1, VT));
16830 if (isPowerOf2_64(MulAmt2))
16831 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
16832 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
16834 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
16835 DAG.getConstant(MulAmt2, VT));
16837 // Do not add new nodes to DAG combiner worklist.
16838 DCI.CombineTo(N, NewMul, false);
16843 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
16844 SDValue N0 = N->getOperand(0);
16845 SDValue N1 = N->getOperand(1);
16846 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
16847 EVT VT = N0.getValueType();
16849 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
16850 // since the result of setcc_c is all zero's or all ones.
16851 if (VT.isInteger() && !VT.isVector() &&
16852 N1C && N0.getOpcode() == ISD::AND &&
16853 N0.getOperand(1).getOpcode() == ISD::Constant) {
16854 SDValue N00 = N0.getOperand(0);
16855 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
16856 ((N00.getOpcode() == ISD::ANY_EXTEND ||
16857 N00.getOpcode() == ISD::ZERO_EXTEND) &&
16858 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
16859 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
16860 APInt ShAmt = N1C->getAPIntValue();
16861 Mask = Mask.shl(ShAmt);
16863 return DAG.getNode(ISD::AND, SDLoc(N), VT,
16864 N00, DAG.getConstant(Mask, VT));
16868 // Hardware support for vector shifts is sparse which makes us scalarize the
16869 // vector operations in many cases. Also, on sandybridge ADD is faster than
16871 // (shl V, 1) -> add V,V
16872 if (isSplatVector(N1.getNode())) {
16873 assert(N0.getValueType().isVector() && "Invalid vector shift type");
16874 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1->getOperand(0));
16875 // We shift all of the values by one. In many cases we do not have
16876 // hardware support for this operation. This is better expressed as an ADD
16878 if (N1C && (1 == N1C->getZExtValue())) {
16879 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
16886 /// \brief Returns a vector of 0s if the node in input is a vector logical
16887 /// shift by a constant amount which is known to be bigger than or equal
16888 /// to the vector element size in bits.
16889 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
16890 const X86Subtarget *Subtarget) {
16891 EVT VT = N->getValueType(0);
16893 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
16894 (!Subtarget->hasInt256() ||
16895 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
16898 SDValue Amt = N->getOperand(1);
16900 if (isSplatVector(Amt.getNode())) {
16901 SDValue SclrAmt = Amt->getOperand(0);
16902 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
16903 APInt ShiftAmt = C->getAPIntValue();
16904 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
16906 // SSE2/AVX2 logical shifts always return a vector of 0s
16907 // if the shift amount is bigger than or equal to
16908 // the element size. The constant shift amount will be
16909 // encoded as a 8-bit immediate.
16910 if (ShiftAmt.trunc(8).uge(MaxAmount))
16911 return getZeroVector(VT, Subtarget, DAG, DL);
16918 /// PerformShiftCombine - Combine shifts.
16919 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
16920 TargetLowering::DAGCombinerInfo &DCI,
16921 const X86Subtarget *Subtarget) {
16922 if (N->getOpcode() == ISD::SHL) {
16923 SDValue V = PerformSHLCombine(N, DAG);
16924 if (V.getNode()) return V;
16927 if (N->getOpcode() != ISD::SRA) {
16928 // Try to fold this logical shift into a zero vector.
16929 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
16930 if (V.getNode()) return V;
16936 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
16937 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
16938 // and friends. Likewise for OR -> CMPNEQSS.
16939 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
16940 TargetLowering::DAGCombinerInfo &DCI,
16941 const X86Subtarget *Subtarget) {
16944 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
16945 // we're requiring SSE2 for both.
16946 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
16947 SDValue N0 = N->getOperand(0);
16948 SDValue N1 = N->getOperand(1);
16949 SDValue CMP0 = N0->getOperand(1);
16950 SDValue CMP1 = N1->getOperand(1);
16953 // The SETCCs should both refer to the same CMP.
16954 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
16957 SDValue CMP00 = CMP0->getOperand(0);
16958 SDValue CMP01 = CMP0->getOperand(1);
16959 EVT VT = CMP00.getValueType();
16961 if (VT == MVT::f32 || VT == MVT::f64) {
16962 bool ExpectingFlags = false;
16963 // Check for any users that want flags:
16964 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
16965 !ExpectingFlags && UI != UE; ++UI)
16966 switch (UI->getOpcode()) {
16971 ExpectingFlags = true;
16973 case ISD::CopyToReg:
16974 case ISD::SIGN_EXTEND:
16975 case ISD::ZERO_EXTEND:
16976 case ISD::ANY_EXTEND:
16980 if (!ExpectingFlags) {
16981 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
16982 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
16984 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
16985 X86::CondCode tmp = cc0;
16990 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
16991 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
16992 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
16993 X86ISD::NodeType NTOperator = is64BitFP ?
16994 X86ISD::FSETCCsd : X86ISD::FSETCCss;
16995 // FIXME: need symbolic constants for these magic numbers.
16996 // See X86ATTInstPrinter.cpp:printSSECC().
16997 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
16998 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01,
16999 DAG.getConstant(x86cc, MVT::i8));
17000 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32,
17002 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI,
17003 DAG.getConstant(1, MVT::i32));
17004 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
17005 return OneBitOfTruth;
17013 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
17014 /// so it can be folded inside ANDNP.
17015 static bool CanFoldXORWithAllOnes(const SDNode *N) {
17016 EVT VT = N->getValueType(0);
17018 // Match direct AllOnes for 128 and 256-bit vectors
17019 if (ISD::isBuildVectorAllOnes(N))
17022 // Look through a bit convert.
17023 if (N->getOpcode() == ISD::BITCAST)
17024 N = N->getOperand(0).getNode();
17026 // Sometimes the operand may come from a insert_subvector building a 256-bit
17028 if (VT.is256BitVector() &&
17029 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
17030 SDValue V1 = N->getOperand(0);
17031 SDValue V2 = N->getOperand(1);
17033 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
17034 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
17035 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
17036 ISD::isBuildVectorAllOnes(V2.getNode()))
17043 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
17044 // register. In most cases we actually compare or select YMM-sized registers
17045 // and mixing the two types creates horrible code. This method optimizes
17046 // some of the transition sequences.
17047 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
17048 TargetLowering::DAGCombinerInfo &DCI,
17049 const X86Subtarget *Subtarget) {
17050 EVT VT = N->getValueType(0);
17051 if (!VT.is256BitVector())
17054 assert((N->getOpcode() == ISD::ANY_EXTEND ||
17055 N->getOpcode() == ISD::ZERO_EXTEND ||
17056 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
17058 SDValue Narrow = N->getOperand(0);
17059 EVT NarrowVT = Narrow->getValueType(0);
17060 if (!NarrowVT.is128BitVector())
17063 if (Narrow->getOpcode() != ISD::XOR &&
17064 Narrow->getOpcode() != ISD::AND &&
17065 Narrow->getOpcode() != ISD::OR)
17068 SDValue N0 = Narrow->getOperand(0);
17069 SDValue N1 = Narrow->getOperand(1);
17072 // The Left side has to be a trunc.
17073 if (N0.getOpcode() != ISD::TRUNCATE)
17076 // The type of the truncated inputs.
17077 EVT WideVT = N0->getOperand(0)->getValueType(0);
17081 // The right side has to be a 'trunc' or a constant vector.
17082 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
17083 bool RHSConst = (isSplatVector(N1.getNode()) &&
17084 isa<ConstantSDNode>(N1->getOperand(0)));
17085 if (!RHSTrunc && !RHSConst)
17088 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17090 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
17093 // Set N0 and N1 to hold the inputs to the new wide operation.
17094 N0 = N0->getOperand(0);
17096 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
17097 N1->getOperand(0));
17098 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
17099 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, &C[0], C.size());
17100 } else if (RHSTrunc) {
17101 N1 = N1->getOperand(0);
17104 // Generate the wide operation.
17105 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
17106 unsigned Opcode = N->getOpcode();
17108 case ISD::ANY_EXTEND:
17110 case ISD::ZERO_EXTEND: {
17111 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
17112 APInt Mask = APInt::getAllOnesValue(InBits);
17113 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
17114 return DAG.getNode(ISD::AND, DL, VT,
17115 Op, DAG.getConstant(Mask, VT));
17117 case ISD::SIGN_EXTEND:
17118 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
17119 Op, DAG.getValueType(NarrowVT));
17121 llvm_unreachable("Unexpected opcode");
17125 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
17126 TargetLowering::DAGCombinerInfo &DCI,
17127 const X86Subtarget *Subtarget) {
17128 EVT VT = N->getValueType(0);
17129 if (DCI.isBeforeLegalizeOps())
17132 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
17136 // Create BLSI, and BLSR instructions
17137 // BLSI is X & (-X)
17138 // BLSR is X & (X-1)
17139 if (Subtarget->hasBMI() && (VT == MVT::i32 || VT == MVT::i64)) {
17140 SDValue N0 = N->getOperand(0);
17141 SDValue N1 = N->getOperand(1);
17144 // Check LHS for neg
17145 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1) == N1 &&
17146 isZero(N0.getOperand(0)))
17147 return DAG.getNode(X86ISD::BLSI, DL, VT, N1);
17149 // Check RHS for neg
17150 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1) == N0 &&
17151 isZero(N1.getOperand(0)))
17152 return DAG.getNode(X86ISD::BLSI, DL, VT, N0);
17154 // Check LHS for X-1
17155 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
17156 isAllOnes(N0.getOperand(1)))
17157 return DAG.getNode(X86ISD::BLSR, DL, VT, N1);
17159 // Check RHS for X-1
17160 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
17161 isAllOnes(N1.getOperand(1)))
17162 return DAG.getNode(X86ISD::BLSR, DL, VT, N0);
17167 // Want to form ANDNP nodes:
17168 // 1) In the hopes of then easily combining them with OR and AND nodes
17169 // to form PBLEND/PSIGN.
17170 // 2) To match ANDN packed intrinsics
17171 if (VT != MVT::v2i64 && VT != MVT::v4i64)
17174 SDValue N0 = N->getOperand(0);
17175 SDValue N1 = N->getOperand(1);
17178 // Check LHS for vnot
17179 if (N0.getOpcode() == ISD::XOR &&
17180 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
17181 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
17182 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
17184 // Check RHS for vnot
17185 if (N1.getOpcode() == ISD::XOR &&
17186 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
17187 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
17188 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
17193 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
17194 TargetLowering::DAGCombinerInfo &DCI,
17195 const X86Subtarget *Subtarget) {
17196 EVT VT = N->getValueType(0);
17197 if (DCI.isBeforeLegalizeOps())
17200 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
17204 SDValue N0 = N->getOperand(0);
17205 SDValue N1 = N->getOperand(1);
17207 // look for psign/blend
17208 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
17209 if (!Subtarget->hasSSSE3() ||
17210 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
17213 // Canonicalize pandn to RHS
17214 if (N0.getOpcode() == X86ISD::ANDNP)
17216 // or (and (m, y), (pandn m, x))
17217 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
17218 SDValue Mask = N1.getOperand(0);
17219 SDValue X = N1.getOperand(1);
17221 if (N0.getOperand(0) == Mask)
17222 Y = N0.getOperand(1);
17223 if (N0.getOperand(1) == Mask)
17224 Y = N0.getOperand(0);
17226 // Check to see if the mask appeared in both the AND and ANDNP and
17230 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
17231 // Look through mask bitcast.
17232 if (Mask.getOpcode() == ISD::BITCAST)
17233 Mask = Mask.getOperand(0);
17234 if (X.getOpcode() == ISD::BITCAST)
17235 X = X.getOperand(0);
17236 if (Y.getOpcode() == ISD::BITCAST)
17237 Y = Y.getOperand(0);
17239 EVT MaskVT = Mask.getValueType();
17241 // Validate that the Mask operand is a vector sra node.
17242 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
17243 // there is no psrai.b
17244 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
17245 unsigned SraAmt = ~0;
17246 if (Mask.getOpcode() == ISD::SRA) {
17247 SDValue Amt = Mask.getOperand(1);
17248 if (isSplatVector(Amt.getNode())) {
17249 SDValue SclrAmt = Amt->getOperand(0);
17250 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt))
17251 SraAmt = C->getZExtValue();
17253 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
17254 SDValue SraC = Mask.getOperand(1);
17255 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
17257 if ((SraAmt + 1) != EltBits)
17262 // Now we know we at least have a plendvb with the mask val. See if
17263 // we can form a psignb/w/d.
17264 // psign = x.type == y.type == mask.type && y = sub(0, x);
17265 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
17266 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
17267 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
17268 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
17269 "Unsupported VT for PSIGN");
17270 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
17271 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
17273 // PBLENDVB only available on SSE 4.1
17274 if (!Subtarget->hasSSE41())
17277 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
17279 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
17280 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
17281 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
17282 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
17283 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
17287 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
17290 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
17291 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
17293 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
17295 if (!N0.hasOneUse() || !N1.hasOneUse())
17298 SDValue ShAmt0 = N0.getOperand(1);
17299 if (ShAmt0.getValueType() != MVT::i8)
17301 SDValue ShAmt1 = N1.getOperand(1);
17302 if (ShAmt1.getValueType() != MVT::i8)
17304 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
17305 ShAmt0 = ShAmt0.getOperand(0);
17306 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
17307 ShAmt1 = ShAmt1.getOperand(0);
17310 unsigned Opc = X86ISD::SHLD;
17311 SDValue Op0 = N0.getOperand(0);
17312 SDValue Op1 = N1.getOperand(0);
17313 if (ShAmt0.getOpcode() == ISD::SUB) {
17314 Opc = X86ISD::SHRD;
17315 std::swap(Op0, Op1);
17316 std::swap(ShAmt0, ShAmt1);
17319 unsigned Bits = VT.getSizeInBits();
17320 if (ShAmt1.getOpcode() == ISD::SUB) {
17321 SDValue Sum = ShAmt1.getOperand(0);
17322 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
17323 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
17324 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
17325 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
17326 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
17327 return DAG.getNode(Opc, DL, VT,
17329 DAG.getNode(ISD::TRUNCATE, DL,
17332 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
17333 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
17335 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
17336 return DAG.getNode(Opc, DL, VT,
17337 N0.getOperand(0), N1.getOperand(0),
17338 DAG.getNode(ISD::TRUNCATE, DL,
17345 // Generate NEG and CMOV for integer abs.
17346 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
17347 EVT VT = N->getValueType(0);
17349 // Since X86 does not have CMOV for 8-bit integer, we don't convert
17350 // 8-bit integer abs to NEG and CMOV.
17351 if (VT.isInteger() && VT.getSizeInBits() == 8)
17354 SDValue N0 = N->getOperand(0);
17355 SDValue N1 = N->getOperand(1);
17358 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
17359 // and change it to SUB and CMOV.
17360 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
17361 N0.getOpcode() == ISD::ADD &&
17362 N0.getOperand(1) == N1 &&
17363 N1.getOpcode() == ISD::SRA &&
17364 N1.getOperand(0) == N0.getOperand(0))
17365 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
17366 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
17367 // Generate SUB & CMOV.
17368 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
17369 DAG.getConstant(0, VT), N0.getOperand(0));
17371 SDValue Ops[] = { N0.getOperand(0), Neg,
17372 DAG.getConstant(X86::COND_GE, MVT::i8),
17373 SDValue(Neg.getNode(), 1) };
17374 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue),
17375 Ops, array_lengthof(Ops));
17380 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
17381 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
17382 TargetLowering::DAGCombinerInfo &DCI,
17383 const X86Subtarget *Subtarget) {
17384 EVT VT = N->getValueType(0);
17385 if (DCI.isBeforeLegalizeOps())
17388 if (Subtarget->hasCMov()) {
17389 SDValue RV = performIntegerAbsCombine(N, DAG);
17394 // Try forming BMI if it is available.
17395 if (!Subtarget->hasBMI())
17398 if (VT != MVT::i32 && VT != MVT::i64)
17401 assert(Subtarget->hasBMI() && "Creating BLSMSK requires BMI instructions");
17403 // Create BLSMSK instructions by finding X ^ (X-1)
17404 SDValue N0 = N->getOperand(0);
17405 SDValue N1 = N->getOperand(1);
17408 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
17409 isAllOnes(N0.getOperand(1)))
17410 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N1);
17412 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
17413 isAllOnes(N1.getOperand(1)))
17414 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N0);
17419 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
17420 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
17421 TargetLowering::DAGCombinerInfo &DCI,
17422 const X86Subtarget *Subtarget) {
17423 LoadSDNode *Ld = cast<LoadSDNode>(N);
17424 EVT RegVT = Ld->getValueType(0);
17425 EVT MemVT = Ld->getMemoryVT();
17427 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17428 unsigned RegSz = RegVT.getSizeInBits();
17430 // On Sandybridge unaligned 256bit loads are inefficient.
17431 ISD::LoadExtType Ext = Ld->getExtensionType();
17432 unsigned Alignment = Ld->getAlignment();
17433 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
17434 if (RegVT.is256BitVector() && !Subtarget->hasInt256() &&
17435 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
17436 unsigned NumElems = RegVT.getVectorNumElements();
17440 SDValue Ptr = Ld->getBasePtr();
17441 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
17443 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
17445 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
17446 Ld->getPointerInfo(), Ld->isVolatile(),
17447 Ld->isNonTemporal(), Ld->isInvariant(),
17449 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
17450 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
17451 Ld->getPointerInfo(), Ld->isVolatile(),
17452 Ld->isNonTemporal(), Ld->isInvariant(),
17453 std::min(16U, Alignment));
17454 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
17456 Load2.getValue(1));
17458 SDValue NewVec = DAG.getUNDEF(RegVT);
17459 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
17460 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
17461 return DCI.CombineTo(N, NewVec, TF, true);
17464 // If this is a vector EXT Load then attempt to optimize it using a
17465 // shuffle. If SSSE3 is not available we may emit an illegal shuffle but the
17466 // expansion is still better than scalar code.
17467 // We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise we'll
17468 // emit a shuffle and a arithmetic shift.
17469 // TODO: It is possible to support ZExt by zeroing the undef values
17470 // during the shuffle phase or after the shuffle.
17471 if (RegVT.isVector() && RegVT.isInteger() && Subtarget->hasSSE2() &&
17472 (Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)) {
17473 assert(MemVT != RegVT && "Cannot extend to the same type");
17474 assert(MemVT.isVector() && "Must load a vector from memory");
17476 unsigned NumElems = RegVT.getVectorNumElements();
17477 unsigned MemSz = MemVT.getSizeInBits();
17478 assert(RegSz > MemSz && "Register size must be greater than the mem size");
17480 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256())
17483 // All sizes must be a power of two.
17484 if (!isPowerOf2_32(RegSz * MemSz * NumElems))
17487 // Attempt to load the original value using scalar loads.
17488 // Find the largest scalar type that divides the total loaded size.
17489 MVT SclrLoadTy = MVT::i8;
17490 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
17491 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
17492 MVT Tp = (MVT::SimpleValueType)tp;
17493 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
17498 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
17499 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
17501 SclrLoadTy = MVT::f64;
17503 // Calculate the number of scalar loads that we need to perform
17504 // in order to load our vector from memory.
17505 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
17506 if (Ext == ISD::SEXTLOAD && NumLoads > 1)
17509 unsigned loadRegZize = RegSz;
17510 if (Ext == ISD::SEXTLOAD && RegSz == 256)
17513 // Represent our vector as a sequence of elements which are the
17514 // largest scalar that we can load.
17515 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy,
17516 loadRegZize/SclrLoadTy.getSizeInBits());
17518 // Represent the data using the same element type that is stored in
17519 // memory. In practice, we ''widen'' MemVT.
17521 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
17522 loadRegZize/MemVT.getScalarType().getSizeInBits());
17524 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
17525 "Invalid vector type");
17527 // We can't shuffle using an illegal type.
17528 if (!TLI.isTypeLegal(WideVecVT))
17531 SmallVector<SDValue, 8> Chains;
17532 SDValue Ptr = Ld->getBasePtr();
17533 SDValue Increment = DAG.getConstant(SclrLoadTy.getSizeInBits()/8,
17534 TLI.getPointerTy());
17535 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
17537 for (unsigned i = 0; i < NumLoads; ++i) {
17538 // Perform a single load.
17539 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(),
17540 Ptr, Ld->getPointerInfo(),
17541 Ld->isVolatile(), Ld->isNonTemporal(),
17542 Ld->isInvariant(), Ld->getAlignment());
17543 Chains.push_back(ScalarLoad.getValue(1));
17544 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
17545 // another round of DAGCombining.
17547 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
17549 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
17550 ScalarLoad, DAG.getIntPtrConstant(i));
17552 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
17555 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
17558 // Bitcast the loaded value to a vector of the original element type, in
17559 // the size of the target vector type.
17560 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
17561 unsigned SizeRatio = RegSz/MemSz;
17563 if (Ext == ISD::SEXTLOAD) {
17564 // If we have SSE4.1 we can directly emit a VSEXT node.
17565 if (Subtarget->hasSSE41()) {
17566 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
17567 return DCI.CombineTo(N, Sext, TF, true);
17570 // Otherwise we'll shuffle the small elements in the high bits of the
17571 // larger type and perform an arithmetic shift. If the shift is not legal
17572 // it's better to scalarize.
17573 if (!TLI.isOperationLegalOrCustom(ISD::SRA, RegVT))
17576 // Redistribute the loaded elements into the different locations.
17577 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
17578 for (unsigned i = 0; i != NumElems; ++i)
17579 ShuffleVec[i*SizeRatio + SizeRatio-1] = i;
17581 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
17582 DAG.getUNDEF(WideVecVT),
17585 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
17587 // Build the arithmetic shift.
17588 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
17589 MemVT.getVectorElementType().getSizeInBits();
17590 Shuff = DAG.getNode(ISD::SRA, dl, RegVT, Shuff,
17591 DAG.getConstant(Amt, RegVT));
17593 return DCI.CombineTo(N, Shuff, TF, true);
17596 // Redistribute the loaded elements into the different locations.
17597 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
17598 for (unsigned i = 0; i != NumElems; ++i)
17599 ShuffleVec[i*SizeRatio] = i;
17601 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
17602 DAG.getUNDEF(WideVecVT),
17605 // Bitcast to the requested type.
17606 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
17607 // Replace the original load with the new sequence
17608 // and return the new chain.
17609 return DCI.CombineTo(N, Shuff, TF, true);
17615 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
17616 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
17617 const X86Subtarget *Subtarget) {
17618 StoreSDNode *St = cast<StoreSDNode>(N);
17619 EVT VT = St->getValue().getValueType();
17620 EVT StVT = St->getMemoryVT();
17622 SDValue StoredVal = St->getOperand(1);
17623 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17625 // If we are saving a concatenation of two XMM registers, perform two stores.
17626 // On Sandy Bridge, 256-bit memory operations are executed by two
17627 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit
17628 // memory operation.
17629 unsigned Alignment = St->getAlignment();
17630 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
17631 if (VT.is256BitVector() && !Subtarget->hasInt256() &&
17632 StVT == VT && !IsAligned) {
17633 unsigned NumElems = VT.getVectorNumElements();
17637 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
17638 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
17640 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
17641 SDValue Ptr0 = St->getBasePtr();
17642 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
17644 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
17645 St->getPointerInfo(), St->isVolatile(),
17646 St->isNonTemporal(), Alignment);
17647 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
17648 St->getPointerInfo(), St->isVolatile(),
17649 St->isNonTemporal(),
17650 std::min(16U, Alignment));
17651 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
17654 // Optimize trunc store (of multiple scalars) to shuffle and store.
17655 // First, pack all of the elements in one place. Next, store to memory
17656 // in fewer chunks.
17657 if (St->isTruncatingStore() && VT.isVector()) {
17658 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17659 unsigned NumElems = VT.getVectorNumElements();
17660 assert(StVT != VT && "Cannot truncate to the same type");
17661 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
17662 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
17664 // From, To sizes and ElemCount must be pow of two
17665 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
17666 // We are going to use the original vector elt for storing.
17667 // Accumulated smaller vector elements must be a multiple of the store size.
17668 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
17670 unsigned SizeRatio = FromSz / ToSz;
17672 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
17674 // Create a type on which we perform the shuffle
17675 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
17676 StVT.getScalarType(), NumElems*SizeRatio);
17678 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
17680 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
17681 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
17682 for (unsigned i = 0; i != NumElems; ++i)
17683 ShuffleVec[i] = i * SizeRatio;
17685 // Can't shuffle using an illegal type.
17686 if (!TLI.isTypeLegal(WideVecVT))
17689 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
17690 DAG.getUNDEF(WideVecVT),
17692 // At this point all of the data is stored at the bottom of the
17693 // register. We now need to save it to mem.
17695 // Find the largest store unit
17696 MVT StoreType = MVT::i8;
17697 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
17698 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
17699 MVT Tp = (MVT::SimpleValueType)tp;
17700 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
17704 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
17705 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
17706 (64 <= NumElems * ToSz))
17707 StoreType = MVT::f64;
17709 // Bitcast the original vector into a vector of store-size units
17710 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
17711 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
17712 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
17713 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
17714 SmallVector<SDValue, 8> Chains;
17715 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
17716 TLI.getPointerTy());
17717 SDValue Ptr = St->getBasePtr();
17719 // Perform one or more big stores into memory.
17720 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
17721 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
17722 StoreType, ShuffWide,
17723 DAG.getIntPtrConstant(i));
17724 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
17725 St->getPointerInfo(), St->isVolatile(),
17726 St->isNonTemporal(), St->getAlignment());
17727 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
17728 Chains.push_back(Ch);
17731 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
17735 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
17736 // the FP state in cases where an emms may be missing.
17737 // A preferable solution to the general problem is to figure out the right
17738 // places to insert EMMS. This qualifies as a quick hack.
17740 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
17741 if (VT.getSizeInBits() != 64)
17744 const Function *F = DAG.getMachineFunction().getFunction();
17745 bool NoImplicitFloatOps = F->getAttributes().
17746 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
17747 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
17748 && Subtarget->hasSSE2();
17749 if ((VT.isVector() ||
17750 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
17751 isa<LoadSDNode>(St->getValue()) &&
17752 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
17753 St->getChain().hasOneUse() && !St->isVolatile()) {
17754 SDNode* LdVal = St->getValue().getNode();
17755 LoadSDNode *Ld = 0;
17756 int TokenFactorIndex = -1;
17757 SmallVector<SDValue, 8> Ops;
17758 SDNode* ChainVal = St->getChain().getNode();
17759 // Must be a store of a load. We currently handle two cases: the load
17760 // is a direct child, and it's under an intervening TokenFactor. It is
17761 // possible to dig deeper under nested TokenFactors.
17762 if (ChainVal == LdVal)
17763 Ld = cast<LoadSDNode>(St->getChain());
17764 else if (St->getValue().hasOneUse() &&
17765 ChainVal->getOpcode() == ISD::TokenFactor) {
17766 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
17767 if (ChainVal->getOperand(i).getNode() == LdVal) {
17768 TokenFactorIndex = i;
17769 Ld = cast<LoadSDNode>(St->getValue());
17771 Ops.push_back(ChainVal->getOperand(i));
17775 if (!Ld || !ISD::isNormalLoad(Ld))
17778 // If this is not the MMX case, i.e. we are just turning i64 load/store
17779 // into f64 load/store, avoid the transformation if there are multiple
17780 // uses of the loaded value.
17781 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
17786 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
17787 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
17789 if (Subtarget->is64Bit() || F64IsLegal) {
17790 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
17791 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
17792 Ld->getPointerInfo(), Ld->isVolatile(),
17793 Ld->isNonTemporal(), Ld->isInvariant(),
17794 Ld->getAlignment());
17795 SDValue NewChain = NewLd.getValue(1);
17796 if (TokenFactorIndex != -1) {
17797 Ops.push_back(NewChain);
17798 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
17801 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
17802 St->getPointerInfo(),
17803 St->isVolatile(), St->isNonTemporal(),
17804 St->getAlignment());
17807 // Otherwise, lower to two pairs of 32-bit loads / stores.
17808 SDValue LoAddr = Ld->getBasePtr();
17809 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
17810 DAG.getConstant(4, MVT::i32));
17812 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
17813 Ld->getPointerInfo(),
17814 Ld->isVolatile(), Ld->isNonTemporal(),
17815 Ld->isInvariant(), Ld->getAlignment());
17816 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
17817 Ld->getPointerInfo().getWithOffset(4),
17818 Ld->isVolatile(), Ld->isNonTemporal(),
17820 MinAlign(Ld->getAlignment(), 4));
17822 SDValue NewChain = LoLd.getValue(1);
17823 if (TokenFactorIndex != -1) {
17824 Ops.push_back(LoLd);
17825 Ops.push_back(HiLd);
17826 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
17830 LoAddr = St->getBasePtr();
17831 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
17832 DAG.getConstant(4, MVT::i32));
17834 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
17835 St->getPointerInfo(),
17836 St->isVolatile(), St->isNonTemporal(),
17837 St->getAlignment());
17838 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
17839 St->getPointerInfo().getWithOffset(4),
17841 St->isNonTemporal(),
17842 MinAlign(St->getAlignment(), 4));
17843 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
17848 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
17849 /// and return the operands for the horizontal operation in LHS and RHS. A
17850 /// horizontal operation performs the binary operation on successive elements
17851 /// of its first operand, then on successive elements of its second operand,
17852 /// returning the resulting values in a vector. For example, if
17853 /// A = < float a0, float a1, float a2, float a3 >
17855 /// B = < float b0, float b1, float b2, float b3 >
17856 /// then the result of doing a horizontal operation on A and B is
17857 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
17858 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
17859 /// A horizontal-op B, for some already available A and B, and if so then LHS is
17860 /// set to A, RHS to B, and the routine returns 'true'.
17861 /// Note that the binary operation should have the property that if one of the
17862 /// operands is UNDEF then the result is UNDEF.
17863 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
17864 // Look for the following pattern: if
17865 // A = < float a0, float a1, float a2, float a3 >
17866 // B = < float b0, float b1, float b2, float b3 >
17868 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
17869 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
17870 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
17871 // which is A horizontal-op B.
17873 // At least one of the operands should be a vector shuffle.
17874 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
17875 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
17878 MVT VT = LHS.getSimpleValueType();
17880 assert((VT.is128BitVector() || VT.is256BitVector()) &&
17881 "Unsupported vector type for horizontal add/sub");
17883 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
17884 // operate independently on 128-bit lanes.
17885 unsigned NumElts = VT.getVectorNumElements();
17886 unsigned NumLanes = VT.getSizeInBits()/128;
17887 unsigned NumLaneElts = NumElts / NumLanes;
17888 assert((NumLaneElts % 2 == 0) &&
17889 "Vector type should have an even number of elements in each lane");
17890 unsigned HalfLaneElts = NumLaneElts/2;
17892 // View LHS in the form
17893 // LHS = VECTOR_SHUFFLE A, B, LMask
17894 // If LHS is not a shuffle then pretend it is the shuffle
17895 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
17896 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
17899 SmallVector<int, 16> LMask(NumElts);
17900 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
17901 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
17902 A = LHS.getOperand(0);
17903 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
17904 B = LHS.getOperand(1);
17905 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
17906 std::copy(Mask.begin(), Mask.end(), LMask.begin());
17908 if (LHS.getOpcode() != ISD::UNDEF)
17910 for (unsigned i = 0; i != NumElts; ++i)
17914 // Likewise, view RHS in the form
17915 // RHS = VECTOR_SHUFFLE C, D, RMask
17917 SmallVector<int, 16> RMask(NumElts);
17918 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
17919 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
17920 C = RHS.getOperand(0);
17921 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
17922 D = RHS.getOperand(1);
17923 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
17924 std::copy(Mask.begin(), Mask.end(), RMask.begin());
17926 if (RHS.getOpcode() != ISD::UNDEF)
17928 for (unsigned i = 0; i != NumElts; ++i)
17932 // Check that the shuffles are both shuffling the same vectors.
17933 if (!(A == C && B == D) && !(A == D && B == C))
17936 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
17937 if (!A.getNode() && !B.getNode())
17940 // If A and B occur in reverse order in RHS, then "swap" them (which means
17941 // rewriting the mask).
17943 CommuteVectorShuffleMask(RMask, NumElts);
17945 // At this point LHS and RHS are equivalent to
17946 // LHS = VECTOR_SHUFFLE A, B, LMask
17947 // RHS = VECTOR_SHUFFLE A, B, RMask
17948 // Check that the masks correspond to performing a horizontal operation.
17949 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
17950 for (unsigned i = 0; i != NumLaneElts; ++i) {
17951 int LIdx = LMask[i+l], RIdx = RMask[i+l];
17953 // Ignore any UNDEF components.
17954 if (LIdx < 0 || RIdx < 0 ||
17955 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
17956 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
17959 // Check that successive elements are being operated on. If not, this is
17960 // not a horizontal operation.
17961 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
17962 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
17963 if (!(LIdx == Index && RIdx == Index + 1) &&
17964 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
17969 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
17970 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
17974 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
17975 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
17976 const X86Subtarget *Subtarget) {
17977 EVT VT = N->getValueType(0);
17978 SDValue LHS = N->getOperand(0);
17979 SDValue RHS = N->getOperand(1);
17981 // Try to synthesize horizontal adds from adds of shuffles.
17982 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
17983 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
17984 isHorizontalBinOp(LHS, RHS, true))
17985 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
17989 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
17990 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
17991 const X86Subtarget *Subtarget) {
17992 EVT VT = N->getValueType(0);
17993 SDValue LHS = N->getOperand(0);
17994 SDValue RHS = N->getOperand(1);
17996 // Try to synthesize horizontal subs from subs of shuffles.
17997 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
17998 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
17999 isHorizontalBinOp(LHS, RHS, false))
18000 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
18004 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
18005 /// X86ISD::FXOR nodes.
18006 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
18007 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
18008 // F[X]OR(0.0, x) -> x
18009 // F[X]OR(x, 0.0) -> x
18010 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
18011 if (C->getValueAPF().isPosZero())
18012 return N->getOperand(1);
18013 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
18014 if (C->getValueAPF().isPosZero())
18015 return N->getOperand(0);
18019 /// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and
18020 /// X86ISD::FMAX nodes.
18021 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
18022 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
18024 // Only perform optimizations if UnsafeMath is used.
18025 if (!DAG.getTarget().Options.UnsafeFPMath)
18028 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
18029 // into FMINC and FMAXC, which are Commutative operations.
18030 unsigned NewOp = 0;
18031 switch (N->getOpcode()) {
18032 default: llvm_unreachable("unknown opcode");
18033 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
18034 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
18037 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
18038 N->getOperand(0), N->getOperand(1));
18041 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
18042 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
18043 // FAND(0.0, x) -> 0.0
18044 // FAND(x, 0.0) -> 0.0
18045 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
18046 if (C->getValueAPF().isPosZero())
18047 return N->getOperand(0);
18048 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
18049 if (C->getValueAPF().isPosZero())
18050 return N->getOperand(1);
18054 /// PerformFANDNCombine - Do target-specific dag combines on X86ISD::FANDN nodes
18055 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
18056 // FANDN(x, 0.0) -> 0.0
18057 // FANDN(0.0, x) -> x
18058 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
18059 if (C->getValueAPF().isPosZero())
18060 return N->getOperand(1);
18061 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
18062 if (C->getValueAPF().isPosZero())
18063 return N->getOperand(1);
18067 static SDValue PerformBTCombine(SDNode *N,
18069 TargetLowering::DAGCombinerInfo &DCI) {
18070 // BT ignores high bits in the bit index operand.
18071 SDValue Op1 = N->getOperand(1);
18072 if (Op1.hasOneUse()) {
18073 unsigned BitWidth = Op1.getValueSizeInBits();
18074 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
18075 APInt KnownZero, KnownOne;
18076 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
18077 !DCI.isBeforeLegalizeOps());
18078 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18079 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
18080 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
18081 DCI.CommitTargetLoweringOpt(TLO);
18086 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
18087 SDValue Op = N->getOperand(0);
18088 if (Op.getOpcode() == ISD::BITCAST)
18089 Op = Op.getOperand(0);
18090 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
18091 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
18092 VT.getVectorElementType().getSizeInBits() ==
18093 OpVT.getVectorElementType().getSizeInBits()) {
18094 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
18099 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
18100 const X86Subtarget *Subtarget) {
18101 EVT VT = N->getValueType(0);
18102 if (!VT.isVector())
18105 SDValue N0 = N->getOperand(0);
18106 SDValue N1 = N->getOperand(1);
18107 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
18110 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
18111 // both SSE and AVX2 since there is no sign-extended shift right
18112 // operation on a vector with 64-bit elements.
18113 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
18114 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
18115 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
18116 N0.getOpcode() == ISD::SIGN_EXTEND)) {
18117 SDValue N00 = N0.getOperand(0);
18119 // EXTLOAD has a better solution on AVX2,
18120 // it may be replaced with X86ISD::VSEXT node.
18121 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
18122 if (!ISD::isNormalLoad(N00.getNode()))
18125 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
18126 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
18128 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
18134 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
18135 TargetLowering::DAGCombinerInfo &DCI,
18136 const X86Subtarget *Subtarget) {
18137 if (!DCI.isBeforeLegalizeOps())
18140 if (!Subtarget->hasFp256())
18143 EVT VT = N->getValueType(0);
18144 if (VT.isVector() && VT.getSizeInBits() == 256) {
18145 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
18153 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
18154 const X86Subtarget* Subtarget) {
18156 EVT VT = N->getValueType(0);
18158 // Let legalize expand this if it isn't a legal type yet.
18159 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
18162 EVT ScalarVT = VT.getScalarType();
18163 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
18164 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
18167 SDValue A = N->getOperand(0);
18168 SDValue B = N->getOperand(1);
18169 SDValue C = N->getOperand(2);
18171 bool NegA = (A.getOpcode() == ISD::FNEG);
18172 bool NegB = (B.getOpcode() == ISD::FNEG);
18173 bool NegC = (C.getOpcode() == ISD::FNEG);
18175 // Negative multiplication when NegA xor NegB
18176 bool NegMul = (NegA != NegB);
18178 A = A.getOperand(0);
18180 B = B.getOperand(0);
18182 C = C.getOperand(0);
18186 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
18188 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
18190 return DAG.getNode(Opcode, dl, VT, A, B, C);
18193 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
18194 TargetLowering::DAGCombinerInfo &DCI,
18195 const X86Subtarget *Subtarget) {
18196 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
18197 // (and (i32 x86isd::setcc_carry), 1)
18198 // This eliminates the zext. This transformation is necessary because
18199 // ISD::SETCC is always legalized to i8.
18201 SDValue N0 = N->getOperand(0);
18202 EVT VT = N->getValueType(0);
18204 if (N0.getOpcode() == ISD::AND &&
18206 N0.getOperand(0).hasOneUse()) {
18207 SDValue N00 = N0.getOperand(0);
18208 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
18209 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
18210 if (!C || C->getZExtValue() != 1)
18212 return DAG.getNode(ISD::AND, dl, VT,
18213 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
18214 N00.getOperand(0), N00.getOperand(1)),
18215 DAG.getConstant(1, VT));
18219 if (VT.is256BitVector()) {
18220 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
18228 // Optimize x == -y --> x+y == 0
18229 // x != -y --> x+y != 0
18230 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG) {
18231 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
18232 SDValue LHS = N->getOperand(0);
18233 SDValue RHS = N->getOperand(1);
18235 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
18236 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
18237 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
18238 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
18239 LHS.getValueType(), RHS, LHS.getOperand(1));
18240 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
18241 addV, DAG.getConstant(0, addV.getValueType()), CC);
18243 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
18244 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
18245 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
18246 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
18247 RHS.getValueType(), LHS, RHS.getOperand(1));
18248 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
18249 addV, DAG.getConstant(0, addV.getValueType()), CC);
18254 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
18255 // as "sbb reg,reg", since it can be extended without zext and produces
18256 // an all-ones bit which is more useful than 0/1 in some cases.
18257 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG) {
18258 return DAG.getNode(ISD::AND, DL, MVT::i8,
18259 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
18260 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
18261 DAG.getConstant(1, MVT::i8));
18264 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
18265 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
18266 TargetLowering::DAGCombinerInfo &DCI,
18267 const X86Subtarget *Subtarget) {
18269 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
18270 SDValue EFLAGS = N->getOperand(1);
18272 if (CC == X86::COND_A) {
18273 // Try to convert COND_A into COND_B in an attempt to facilitate
18274 // materializing "setb reg".
18276 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
18277 // cannot take an immediate as its first operand.
18279 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
18280 EFLAGS.getValueType().isInteger() &&
18281 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
18282 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
18283 EFLAGS.getNode()->getVTList(),
18284 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
18285 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
18286 return MaterializeSETB(DL, NewEFLAGS, DAG);
18290 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
18291 // a zext and produces an all-ones bit which is more useful than 0/1 in some
18293 if (CC == X86::COND_B)
18294 return MaterializeSETB(DL, EFLAGS, DAG);
18298 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
18299 if (Flags.getNode()) {
18300 SDValue Cond = DAG.getConstant(CC, MVT::i8);
18301 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
18307 // Optimize branch condition evaluation.
18309 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
18310 TargetLowering::DAGCombinerInfo &DCI,
18311 const X86Subtarget *Subtarget) {
18313 SDValue Chain = N->getOperand(0);
18314 SDValue Dest = N->getOperand(1);
18315 SDValue EFLAGS = N->getOperand(3);
18316 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
18320 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
18321 if (Flags.getNode()) {
18322 SDValue Cond = DAG.getConstant(CC, MVT::i8);
18323 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
18330 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
18331 const X86TargetLowering *XTLI) {
18332 SDValue Op0 = N->getOperand(0);
18333 EVT InVT = Op0->getValueType(0);
18335 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
18336 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
18338 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
18339 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
18340 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
18343 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
18344 // a 32-bit target where SSE doesn't support i64->FP operations.
18345 if (Op0.getOpcode() == ISD::LOAD) {
18346 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
18347 EVT VT = Ld->getValueType(0);
18348 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
18349 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
18350 !XTLI->getSubtarget()->is64Bit() &&
18351 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
18352 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
18353 Ld->getChain(), Op0, DAG);
18354 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
18361 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
18362 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
18363 X86TargetLowering::DAGCombinerInfo &DCI) {
18364 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
18365 // the result is either zero or one (depending on the input carry bit).
18366 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
18367 if (X86::isZeroNode(N->getOperand(0)) &&
18368 X86::isZeroNode(N->getOperand(1)) &&
18369 // We don't have a good way to replace an EFLAGS use, so only do this when
18371 SDValue(N, 1).use_empty()) {
18373 EVT VT = N->getValueType(0);
18374 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
18375 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
18376 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
18377 DAG.getConstant(X86::COND_B,MVT::i8),
18379 DAG.getConstant(1, VT));
18380 return DCI.CombineTo(N, Res1, CarryOut);
18386 // fold (add Y, (sete X, 0)) -> adc 0, Y
18387 // (add Y, (setne X, 0)) -> sbb -1, Y
18388 // (sub (sete X, 0), Y) -> sbb 0, Y
18389 // (sub (setne X, 0), Y) -> adc -1, Y
18390 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
18393 // Look through ZExts.
18394 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
18395 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
18398 SDValue SetCC = Ext.getOperand(0);
18399 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
18402 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
18403 if (CC != X86::COND_E && CC != X86::COND_NE)
18406 SDValue Cmp = SetCC.getOperand(1);
18407 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
18408 !X86::isZeroNode(Cmp.getOperand(1)) ||
18409 !Cmp.getOperand(0).getValueType().isInteger())
18412 SDValue CmpOp0 = Cmp.getOperand(0);
18413 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
18414 DAG.getConstant(1, CmpOp0.getValueType()));
18416 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
18417 if (CC == X86::COND_NE)
18418 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
18419 DL, OtherVal.getValueType(), OtherVal,
18420 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
18421 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
18422 DL, OtherVal.getValueType(), OtherVal,
18423 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
18426 /// PerformADDCombine - Do target-specific dag combines on integer adds.
18427 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
18428 const X86Subtarget *Subtarget) {
18429 EVT VT = N->getValueType(0);
18430 SDValue Op0 = N->getOperand(0);
18431 SDValue Op1 = N->getOperand(1);
18433 // Try to synthesize horizontal adds from adds of shuffles.
18434 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
18435 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
18436 isHorizontalBinOp(Op0, Op1, true))
18437 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
18439 return OptimizeConditionalInDecrement(N, DAG);
18442 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
18443 const X86Subtarget *Subtarget) {
18444 SDValue Op0 = N->getOperand(0);
18445 SDValue Op1 = N->getOperand(1);
18447 // X86 can't encode an immediate LHS of a sub. See if we can push the
18448 // negation into a preceding instruction.
18449 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
18450 // If the RHS of the sub is a XOR with one use and a constant, invert the
18451 // immediate. Then add one to the LHS of the sub so we can turn
18452 // X-Y -> X+~Y+1, saving one register.
18453 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
18454 isa<ConstantSDNode>(Op1.getOperand(1))) {
18455 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
18456 EVT VT = Op0.getValueType();
18457 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
18459 DAG.getConstant(~XorC, VT));
18460 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
18461 DAG.getConstant(C->getAPIntValue()+1, VT));
18465 // Try to synthesize horizontal adds from adds of shuffles.
18466 EVT VT = N->getValueType(0);
18467 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
18468 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
18469 isHorizontalBinOp(Op0, Op1, true))
18470 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
18472 return OptimizeConditionalInDecrement(N, DAG);
18475 /// performVZEXTCombine - Performs build vector combines
18476 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
18477 TargetLowering::DAGCombinerInfo &DCI,
18478 const X86Subtarget *Subtarget) {
18479 // (vzext (bitcast (vzext (x)) -> (vzext x)
18480 SDValue In = N->getOperand(0);
18481 while (In.getOpcode() == ISD::BITCAST)
18482 In = In.getOperand(0);
18484 if (In.getOpcode() != X86ISD::VZEXT)
18487 return DAG.getNode(X86ISD::VZEXT, SDLoc(N), N->getValueType(0),
18491 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
18492 DAGCombinerInfo &DCI) const {
18493 SelectionDAG &DAG = DCI.DAG;
18494 switch (N->getOpcode()) {
18496 case ISD::EXTRACT_VECTOR_ELT:
18497 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
18499 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
18500 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
18501 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
18502 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
18503 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
18504 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
18507 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
18508 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
18509 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
18510 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
18511 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
18512 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
18513 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
18514 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
18515 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
18517 case X86ISD::FOR: return PerformFORCombine(N, DAG);
18519 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
18520 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
18521 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
18522 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
18523 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
18524 case ISD::ANY_EXTEND:
18525 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
18526 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
18527 case ISD::SIGN_EXTEND_INREG: return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
18528 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
18529 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG);
18530 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
18531 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
18532 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
18533 case X86ISD::SHUFP: // Handle all target specific shuffles
18534 case X86ISD::PALIGNR:
18535 case X86ISD::UNPCKH:
18536 case X86ISD::UNPCKL:
18537 case X86ISD::MOVHLPS:
18538 case X86ISD::MOVLHPS:
18539 case X86ISD::PSHUFD:
18540 case X86ISD::PSHUFHW:
18541 case X86ISD::PSHUFLW:
18542 case X86ISD::MOVSS:
18543 case X86ISD::MOVSD:
18544 case X86ISD::VPERMILP:
18545 case X86ISD::VPERM2X128:
18546 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
18547 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
18553 /// isTypeDesirableForOp - Return true if the target has native support for
18554 /// the specified value type and it is 'desirable' to use the type for the
18555 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
18556 /// instruction encodings are longer and some i16 instructions are slow.
18557 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
18558 if (!isTypeLegal(VT))
18560 if (VT != MVT::i16)
18567 case ISD::SIGN_EXTEND:
18568 case ISD::ZERO_EXTEND:
18569 case ISD::ANY_EXTEND:
18582 /// IsDesirableToPromoteOp - This method query the target whether it is
18583 /// beneficial for dag combiner to promote the specified node. If true, it
18584 /// should return the desired promotion type by reference.
18585 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
18586 EVT VT = Op.getValueType();
18587 if (VT != MVT::i16)
18590 bool Promote = false;
18591 bool Commute = false;
18592 switch (Op.getOpcode()) {
18595 LoadSDNode *LD = cast<LoadSDNode>(Op);
18596 // If the non-extending load has a single use and it's not live out, then it
18597 // might be folded.
18598 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
18599 Op.hasOneUse()*/) {
18600 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
18601 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
18602 // The only case where we'd want to promote LOAD (rather then it being
18603 // promoted as an operand is when it's only use is liveout.
18604 if (UI->getOpcode() != ISD::CopyToReg)
18611 case ISD::SIGN_EXTEND:
18612 case ISD::ZERO_EXTEND:
18613 case ISD::ANY_EXTEND:
18618 SDValue N0 = Op.getOperand(0);
18619 // Look out for (store (shl (load), x)).
18620 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
18633 SDValue N0 = Op.getOperand(0);
18634 SDValue N1 = Op.getOperand(1);
18635 if (!Commute && MayFoldLoad(N1))
18637 // Avoid disabling potential load folding opportunities.
18638 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
18640 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
18650 //===----------------------------------------------------------------------===//
18651 // X86 Inline Assembly Support
18652 //===----------------------------------------------------------------------===//
18655 // Helper to match a string separated by whitespace.
18656 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
18657 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
18659 for (unsigned i = 0, e = args.size(); i != e; ++i) {
18660 StringRef piece(*args[i]);
18661 if (!s.startswith(piece)) // Check if the piece matches.
18664 s = s.substr(piece.size());
18665 StringRef::size_type pos = s.find_first_not_of(" \t");
18666 if (pos == 0) // We matched a prefix.
18674 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
18677 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
18678 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
18680 std::string AsmStr = IA->getAsmString();
18682 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
18683 if (!Ty || Ty->getBitWidth() % 16 != 0)
18686 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
18687 SmallVector<StringRef, 4> AsmPieces;
18688 SplitString(AsmStr, AsmPieces, ";\n");
18690 switch (AsmPieces.size()) {
18691 default: return false;
18693 // FIXME: this should verify that we are targeting a 486 or better. If not,
18694 // we will turn this bswap into something that will be lowered to logical
18695 // ops instead of emitting the bswap asm. For now, we don't support 486 or
18696 // lower so don't worry about this.
18698 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
18699 matchAsm(AsmPieces[0], "bswapl", "$0") ||
18700 matchAsm(AsmPieces[0], "bswapq", "$0") ||
18701 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
18702 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
18703 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
18704 // No need to check constraints, nothing other than the equivalent of
18705 // "=r,0" would be valid here.
18706 return IntrinsicLowering::LowerToByteSwap(CI);
18709 // rorw $$8, ${0:w} --> llvm.bswap.i16
18710 if (CI->getType()->isIntegerTy(16) &&
18711 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
18712 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
18713 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
18715 const std::string &ConstraintsStr = IA->getConstraintString();
18716 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
18717 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
18718 if (AsmPieces.size() == 4 &&
18719 AsmPieces[0] == "~{cc}" &&
18720 AsmPieces[1] == "~{dirflag}" &&
18721 AsmPieces[2] == "~{flags}" &&
18722 AsmPieces[3] == "~{fpsr}")
18723 return IntrinsicLowering::LowerToByteSwap(CI);
18727 if (CI->getType()->isIntegerTy(32) &&
18728 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
18729 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
18730 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
18731 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
18733 const std::string &ConstraintsStr = IA->getConstraintString();
18734 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
18735 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
18736 if (AsmPieces.size() == 4 &&
18737 AsmPieces[0] == "~{cc}" &&
18738 AsmPieces[1] == "~{dirflag}" &&
18739 AsmPieces[2] == "~{flags}" &&
18740 AsmPieces[3] == "~{fpsr}")
18741 return IntrinsicLowering::LowerToByteSwap(CI);
18744 if (CI->getType()->isIntegerTy(64)) {
18745 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
18746 if (Constraints.size() >= 2 &&
18747 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
18748 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
18749 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
18750 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
18751 matchAsm(AsmPieces[1], "bswap", "%edx") &&
18752 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
18753 return IntrinsicLowering::LowerToByteSwap(CI);
18761 /// getConstraintType - Given a constraint letter, return the type of
18762 /// constraint it is for this target.
18763 X86TargetLowering::ConstraintType
18764 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
18765 if (Constraint.size() == 1) {
18766 switch (Constraint[0]) {
18777 return C_RegisterClass;
18801 return TargetLowering::getConstraintType(Constraint);
18804 /// Examine constraint type and operand type and determine a weight value.
18805 /// This object must already have been set up with the operand type
18806 /// and the current alternative constraint selected.
18807 TargetLowering::ConstraintWeight
18808 X86TargetLowering::getSingleConstraintMatchWeight(
18809 AsmOperandInfo &info, const char *constraint) const {
18810 ConstraintWeight weight = CW_Invalid;
18811 Value *CallOperandVal = info.CallOperandVal;
18812 // If we don't have a value, we can't do a match,
18813 // but allow it at the lowest weight.
18814 if (CallOperandVal == NULL)
18816 Type *type = CallOperandVal->getType();
18817 // Look at the constraint type.
18818 switch (*constraint) {
18820 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
18831 if (CallOperandVal->getType()->isIntegerTy())
18832 weight = CW_SpecificReg;
18837 if (type->isFloatingPointTy())
18838 weight = CW_SpecificReg;
18841 if (type->isX86_MMXTy() && Subtarget->hasMMX())
18842 weight = CW_SpecificReg;
18846 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
18847 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
18848 weight = CW_Register;
18851 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
18852 if (C->getZExtValue() <= 31)
18853 weight = CW_Constant;
18857 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
18858 if (C->getZExtValue() <= 63)
18859 weight = CW_Constant;
18863 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
18864 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
18865 weight = CW_Constant;
18869 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
18870 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
18871 weight = CW_Constant;
18875 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
18876 if (C->getZExtValue() <= 3)
18877 weight = CW_Constant;
18881 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
18882 if (C->getZExtValue() <= 0xff)
18883 weight = CW_Constant;
18888 if (dyn_cast<ConstantFP>(CallOperandVal)) {
18889 weight = CW_Constant;
18893 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
18894 if ((C->getSExtValue() >= -0x80000000LL) &&
18895 (C->getSExtValue() <= 0x7fffffffLL))
18896 weight = CW_Constant;
18900 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
18901 if (C->getZExtValue() <= 0xffffffff)
18902 weight = CW_Constant;
18909 /// LowerXConstraint - try to replace an X constraint, which matches anything,
18910 /// with another that has more specific requirements based on the type of the
18911 /// corresponding operand.
18912 const char *X86TargetLowering::
18913 LowerXConstraint(EVT ConstraintVT) const {
18914 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
18915 // 'f' like normal targets.
18916 if (ConstraintVT.isFloatingPoint()) {
18917 if (Subtarget->hasSSE2())
18919 if (Subtarget->hasSSE1())
18923 return TargetLowering::LowerXConstraint(ConstraintVT);
18926 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
18927 /// vector. If it is invalid, don't add anything to Ops.
18928 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
18929 std::string &Constraint,
18930 std::vector<SDValue>&Ops,
18931 SelectionDAG &DAG) const {
18932 SDValue Result(0, 0);
18934 // Only support length 1 constraints for now.
18935 if (Constraint.length() > 1) return;
18937 char ConstraintLetter = Constraint[0];
18938 switch (ConstraintLetter) {
18941 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
18942 if (C->getZExtValue() <= 31) {
18943 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
18949 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
18950 if (C->getZExtValue() <= 63) {
18951 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
18957 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
18958 if (isInt<8>(C->getSExtValue())) {
18959 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
18965 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
18966 if (C->getZExtValue() <= 255) {
18967 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
18973 // 32-bit signed value
18974 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
18975 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
18976 C->getSExtValue())) {
18977 // Widen to 64 bits here to get it sign extended.
18978 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
18981 // FIXME gcc accepts some relocatable values here too, but only in certain
18982 // memory models; it's complicated.
18987 // 32-bit unsigned value
18988 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
18989 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
18990 C->getZExtValue())) {
18991 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
18995 // FIXME gcc accepts some relocatable values here too, but only in certain
18996 // memory models; it's complicated.
19000 // Literal immediates are always ok.
19001 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
19002 // Widen to 64 bits here to get it sign extended.
19003 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
19007 // In any sort of PIC mode addresses need to be computed at runtime by
19008 // adding in a register or some sort of table lookup. These can't
19009 // be used as immediates.
19010 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
19013 // If we are in non-pic codegen mode, we allow the address of a global (with
19014 // an optional displacement) to be used with 'i'.
19015 GlobalAddressSDNode *GA = 0;
19016 int64_t Offset = 0;
19018 // Match either (GA), (GA+C), (GA+C1+C2), etc.
19020 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
19021 Offset += GA->getOffset();
19023 } else if (Op.getOpcode() == ISD::ADD) {
19024 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
19025 Offset += C->getZExtValue();
19026 Op = Op.getOperand(0);
19029 } else if (Op.getOpcode() == ISD::SUB) {
19030 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
19031 Offset += -C->getZExtValue();
19032 Op = Op.getOperand(0);
19037 // Otherwise, this isn't something we can handle, reject it.
19041 const GlobalValue *GV = GA->getGlobal();
19042 // If we require an extra load to get this address, as in PIC mode, we
19043 // can't accept it.
19044 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
19045 getTargetMachine())))
19048 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
19049 GA->getValueType(0), Offset);
19054 if (Result.getNode()) {
19055 Ops.push_back(Result);
19058 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
19061 std::pair<unsigned, const TargetRegisterClass*>
19062 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
19064 // First, see if this is a constraint that directly corresponds to an LLVM
19066 if (Constraint.size() == 1) {
19067 // GCC Constraint Letters
19068 switch (Constraint[0]) {
19070 // TODO: Slight differences here in allocation order and leaving
19071 // RIP in the class. Do they matter any more here than they do
19072 // in the normal allocation?
19073 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
19074 if (Subtarget->is64Bit()) {
19075 if (VT == MVT::i32 || VT == MVT::f32)
19076 return std::make_pair(0U, &X86::GR32RegClass);
19077 if (VT == MVT::i16)
19078 return std::make_pair(0U, &X86::GR16RegClass);
19079 if (VT == MVT::i8 || VT == MVT::i1)
19080 return std::make_pair(0U, &X86::GR8RegClass);
19081 if (VT == MVT::i64 || VT == MVT::f64)
19082 return std::make_pair(0U, &X86::GR64RegClass);
19085 // 32-bit fallthrough
19086 case 'Q': // Q_REGS
19087 if (VT == MVT::i32 || VT == MVT::f32)
19088 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
19089 if (VT == MVT::i16)
19090 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
19091 if (VT == MVT::i8 || VT == MVT::i1)
19092 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
19093 if (VT == MVT::i64)
19094 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
19096 case 'r': // GENERAL_REGS
19097 case 'l': // INDEX_REGS
19098 if (VT == MVT::i8 || VT == MVT::i1)
19099 return std::make_pair(0U, &X86::GR8RegClass);
19100 if (VT == MVT::i16)
19101 return std::make_pair(0U, &X86::GR16RegClass);
19102 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
19103 return std::make_pair(0U, &X86::GR32RegClass);
19104 return std::make_pair(0U, &X86::GR64RegClass);
19105 case 'R': // LEGACY_REGS
19106 if (VT == MVT::i8 || VT == MVT::i1)
19107 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
19108 if (VT == MVT::i16)
19109 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
19110 if (VT == MVT::i32 || !Subtarget->is64Bit())
19111 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
19112 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
19113 case 'f': // FP Stack registers.
19114 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
19115 // value to the correct fpstack register class.
19116 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
19117 return std::make_pair(0U, &X86::RFP32RegClass);
19118 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
19119 return std::make_pair(0U, &X86::RFP64RegClass);
19120 return std::make_pair(0U, &X86::RFP80RegClass);
19121 case 'y': // MMX_REGS if MMX allowed.
19122 if (!Subtarget->hasMMX()) break;
19123 return std::make_pair(0U, &X86::VR64RegClass);
19124 case 'Y': // SSE_REGS if SSE2 allowed
19125 if (!Subtarget->hasSSE2()) break;
19127 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
19128 if (!Subtarget->hasSSE1()) break;
19130 switch (VT.SimpleTy) {
19132 // Scalar SSE types.
19135 return std::make_pair(0U, &X86::FR32RegClass);
19138 return std::make_pair(0U, &X86::FR64RegClass);
19146 return std::make_pair(0U, &X86::VR128RegClass);
19154 return std::make_pair(0U, &X86::VR256RegClass);
19159 return std::make_pair(0U, &X86::VR512RegClass);
19165 // Use the default implementation in TargetLowering to convert the register
19166 // constraint into a member of a register class.
19167 std::pair<unsigned, const TargetRegisterClass*> Res;
19168 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
19170 // Not found as a standard register?
19171 if (Res.second == 0) {
19172 // Map st(0) -> st(7) -> ST0
19173 if (Constraint.size() == 7 && Constraint[0] == '{' &&
19174 tolower(Constraint[1]) == 's' &&
19175 tolower(Constraint[2]) == 't' &&
19176 Constraint[3] == '(' &&
19177 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
19178 Constraint[5] == ')' &&
19179 Constraint[6] == '}') {
19181 Res.first = X86::ST0+Constraint[4]-'0';
19182 Res.second = &X86::RFP80RegClass;
19186 // GCC allows "st(0)" to be called just plain "st".
19187 if (StringRef("{st}").equals_lower(Constraint)) {
19188 Res.first = X86::ST0;
19189 Res.second = &X86::RFP80RegClass;
19194 if (StringRef("{flags}").equals_lower(Constraint)) {
19195 Res.first = X86::EFLAGS;
19196 Res.second = &X86::CCRRegClass;
19200 // 'A' means EAX + EDX.
19201 if (Constraint == "A") {
19202 Res.first = X86::EAX;
19203 Res.second = &X86::GR32_ADRegClass;
19209 // Otherwise, check to see if this is a register class of the wrong value
19210 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
19211 // turn into {ax},{dx}.
19212 if (Res.second->hasType(VT))
19213 return Res; // Correct type already, nothing to do.
19215 // All of the single-register GCC register classes map their values onto
19216 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
19217 // really want an 8-bit or 32-bit register, map to the appropriate register
19218 // class and return the appropriate register.
19219 if (Res.second == &X86::GR16RegClass) {
19220 if (VT == MVT::i8 || VT == MVT::i1) {
19221 unsigned DestReg = 0;
19222 switch (Res.first) {
19224 case X86::AX: DestReg = X86::AL; break;
19225 case X86::DX: DestReg = X86::DL; break;
19226 case X86::CX: DestReg = X86::CL; break;
19227 case X86::BX: DestReg = X86::BL; break;
19230 Res.first = DestReg;
19231 Res.second = &X86::GR8RegClass;
19233 } else if (VT == MVT::i32 || VT == MVT::f32) {
19234 unsigned DestReg = 0;
19235 switch (Res.first) {
19237 case X86::AX: DestReg = X86::EAX; break;
19238 case X86::DX: DestReg = X86::EDX; break;
19239 case X86::CX: DestReg = X86::ECX; break;
19240 case X86::BX: DestReg = X86::EBX; break;
19241 case X86::SI: DestReg = X86::ESI; break;
19242 case X86::DI: DestReg = X86::EDI; break;
19243 case X86::BP: DestReg = X86::EBP; break;
19244 case X86::SP: DestReg = X86::ESP; break;
19247 Res.first = DestReg;
19248 Res.second = &X86::GR32RegClass;
19250 } else if (VT == MVT::i64 || VT == MVT::f64) {
19251 unsigned DestReg = 0;
19252 switch (Res.first) {
19254 case X86::AX: DestReg = X86::RAX; break;
19255 case X86::DX: DestReg = X86::RDX; break;
19256 case X86::CX: DestReg = X86::RCX; break;
19257 case X86::BX: DestReg = X86::RBX; break;
19258 case X86::SI: DestReg = X86::RSI; break;
19259 case X86::DI: DestReg = X86::RDI; break;
19260 case X86::BP: DestReg = X86::RBP; break;
19261 case X86::SP: DestReg = X86::RSP; break;
19264 Res.first = DestReg;
19265 Res.second = &X86::GR64RegClass;
19268 } else if (Res.second == &X86::FR32RegClass ||
19269 Res.second == &X86::FR64RegClass ||
19270 Res.second == &X86::VR128RegClass ||
19271 Res.second == &X86::VR256RegClass ||
19272 Res.second == &X86::FR32XRegClass ||
19273 Res.second == &X86::FR64XRegClass ||
19274 Res.second == &X86::VR128XRegClass ||
19275 Res.second == &X86::VR256XRegClass ||
19276 Res.second == &X86::VR512RegClass) {
19277 // Handle references to XMM physical registers that got mapped into the
19278 // wrong class. This can happen with constraints like {xmm0} where the
19279 // target independent register mapper will just pick the first match it can
19280 // find, ignoring the required type.
19282 if (VT == MVT::f32 || VT == MVT::i32)
19283 Res.second = &X86::FR32RegClass;
19284 else if (VT == MVT::f64 || VT == MVT::i64)
19285 Res.second = &X86::FR64RegClass;
19286 else if (X86::VR128RegClass.hasType(VT))
19287 Res.second = &X86::VR128RegClass;
19288 else if (X86::VR256RegClass.hasType(VT))
19289 Res.second = &X86::VR256RegClass;
19290 else if (X86::VR512RegClass.hasType(VT))
19291 Res.second = &X86::VR512RegClass;