1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
16 #include "X86ISelLowering.h"
18 #include "X86InstrBuilder.h"
19 #include "X86TargetMachine.h"
20 #include "X86TargetObjectFile.h"
21 #include "Utils/X86ShuffleDecode.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/GlobalAlias.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/Function.h"
28 #include "llvm/Instructions.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/LLVMContext.h"
31 #include "llvm/CodeGen/IntrinsicLowering.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineFunction.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineJumpTableInfo.h"
36 #include "llvm/CodeGen/MachineModuleInfo.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/MC/MCAsmInfo.h"
39 #include "llvm/MC/MCContext.h"
40 #include "llvm/MC/MCExpr.h"
41 #include "llvm/MC/MCSymbol.h"
42 #include "llvm/ADT/SmallSet.h"
43 #include "llvm/ADT/Statistic.h"
44 #include "llvm/ADT/StringExtras.h"
45 #include "llvm/ADT/VariadicFunction.h"
46 #include "llvm/Support/CallSite.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/MathExtras.h"
50 #include "llvm/Target/TargetOptions.h"
55 STATISTIC(NumTailCalls, "Number of tail calls");
57 // Forward declarations.
58 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
61 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
62 /// sets things up to match to an AVX VEXTRACTF128 instruction or a
63 /// simple subregister reference. Idx is an index in the 128 bits we
64 /// want. It need not be aligned to a 128-bit bounday. That makes
65 /// lowering EXTRACT_VECTOR_ELT operations easier.
66 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
67 SelectionDAG &DAG, DebugLoc dl) {
68 EVT VT = Vec.getValueType();
69 assert(VT.is256BitVector() && "Unexpected vector size!");
70 EVT ElVT = VT.getVectorElementType();
71 unsigned Factor = VT.getSizeInBits()/128;
72 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
73 VT.getVectorNumElements()/Factor);
75 // Extract from UNDEF is UNDEF.
76 if (Vec.getOpcode() == ISD::UNDEF)
77 return DAG.getUNDEF(ResultVT);
79 // Extract the relevant 128 bits. Generate an EXTRACT_SUBVECTOR
80 // we can match to VEXTRACTF128.
81 unsigned ElemsPerChunk = 128 / ElVT.getSizeInBits();
83 // This is the index of the first element of the 128-bit chunk
85 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / 128)
88 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
89 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
95 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
96 /// sets things up to match to an AVX VINSERTF128 instruction or a
97 /// simple superregister reference. Idx is an index in the 128 bits
98 /// we want. It need not be aligned to a 128-bit bounday. That makes
99 /// lowering INSERT_VECTOR_ELT operations easier.
100 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
101 unsigned IdxVal, SelectionDAG &DAG,
103 // Inserting UNDEF is Result
104 if (Vec.getOpcode() == ISD::UNDEF)
107 EVT VT = Vec.getValueType();
108 assert(VT.is128BitVector() && "Unexpected vector size!");
110 EVT ElVT = VT.getVectorElementType();
111 EVT ResultVT = Result.getValueType();
113 // Insert the relevant 128 bits.
114 unsigned ElemsPerChunk = 128/ElVT.getSizeInBits();
116 // This is the index of the first element of the 128-bit chunk
118 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/128)
121 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
122 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
126 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
127 /// instructions. This is used because creating CONCAT_VECTOR nodes of
128 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
129 /// large BUILD_VECTORS.
130 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
131 unsigned NumElems, SelectionDAG &DAG,
133 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
134 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
137 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
138 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
139 bool is64Bit = Subtarget->is64Bit();
141 if (Subtarget->isTargetEnvMacho()) {
143 return new X86_64MachoTargetObjectFile();
144 return new TargetLoweringObjectFileMachO();
147 if (Subtarget->isTargetLinux())
148 return new X86LinuxTargetObjectFile();
149 if (Subtarget->isTargetELF())
150 return new TargetLoweringObjectFileELF();
151 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
152 return new TargetLoweringObjectFileCOFF();
153 llvm_unreachable("unknown subtarget type");
156 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
157 : TargetLowering(TM, createTLOF(TM)) {
158 Subtarget = &TM.getSubtarget<X86Subtarget>();
159 X86ScalarSSEf64 = Subtarget->hasSSE2();
160 X86ScalarSSEf32 = Subtarget->hasSSE1();
161 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
163 RegInfo = TM.getRegisterInfo();
164 TD = getTargetData();
166 // Set up the TargetLowering object.
167 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
169 // X86 is weird, it always uses i8 for shift amounts and setcc results.
170 setBooleanContents(ZeroOrOneBooleanContent);
171 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
172 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
174 // For 64-bit since we have so many registers use the ILP scheduler, for
175 // 32-bit code use the register pressure specific scheduling.
176 // For Atom, always use ILP scheduling.
177 if (Subtarget->isAtom())
178 setSchedulingPreference(Sched::ILP);
179 else if (Subtarget->is64Bit())
180 setSchedulingPreference(Sched::ILP);
182 setSchedulingPreference(Sched::RegPressure);
183 setStackPointerRegisterToSaveRestore(X86StackPtr);
185 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) {
186 // Setup Windows compiler runtime calls.
187 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
188 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
189 setLibcallName(RTLIB::SREM_I64, "_allrem");
190 setLibcallName(RTLIB::UREM_I64, "_aullrem");
191 setLibcallName(RTLIB::MUL_I64, "_allmul");
192 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
193 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
194 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
195 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
196 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
198 // The _ftol2 runtime function has an unusual calling conv, which
199 // is modeled by a special pseudo-instruction.
200 setLibcallName(RTLIB::FPTOUINT_F64_I64, 0);
201 setLibcallName(RTLIB::FPTOUINT_F32_I64, 0);
202 setLibcallName(RTLIB::FPTOUINT_F64_I32, 0);
203 setLibcallName(RTLIB::FPTOUINT_F32_I32, 0);
206 if (Subtarget->isTargetDarwin()) {
207 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
208 setUseUnderscoreSetJmp(false);
209 setUseUnderscoreLongJmp(false);
210 } else if (Subtarget->isTargetMingw()) {
211 // MS runtime is weird: it exports _setjmp, but longjmp!
212 setUseUnderscoreSetJmp(true);
213 setUseUnderscoreLongJmp(false);
215 setUseUnderscoreSetJmp(true);
216 setUseUnderscoreLongJmp(true);
219 // Set up the register classes.
220 addRegisterClass(MVT::i8, &X86::GR8RegClass);
221 addRegisterClass(MVT::i16, &X86::GR16RegClass);
222 addRegisterClass(MVT::i32, &X86::GR32RegClass);
223 if (Subtarget->is64Bit())
224 addRegisterClass(MVT::i64, &X86::GR64RegClass);
226 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
228 // We don't accept any truncstore of integer registers.
229 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
230 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
231 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
232 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
233 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
234 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
236 // SETOEQ and SETUNE require checking two conditions.
237 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
238 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
239 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
240 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
241 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
242 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
244 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
246 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
247 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
248 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
250 if (Subtarget->is64Bit()) {
251 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
252 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
253 } else if (!TM.Options.UseSoftFloat) {
254 // We have an algorithm for SSE2->double, and we turn this into a
255 // 64-bit FILD followed by conditional FADD for other targets.
256 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
257 // We have an algorithm for SSE2, and we turn this into a 64-bit
258 // FILD for other targets.
259 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
262 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
264 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
265 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
267 if (!TM.Options.UseSoftFloat) {
268 // SSE has no i16 to fp conversion, only i32
269 if (X86ScalarSSEf32) {
270 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
271 // f32 and f64 cases are Legal, f80 case is not
272 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
274 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
275 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
278 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
279 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
282 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
283 // are Legal, f80 is custom lowered.
284 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
285 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
287 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
289 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
290 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
292 if (X86ScalarSSEf32) {
293 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
294 // f32 and f64 cases are Legal, f80 case is not
295 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
297 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
298 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
301 // Handle FP_TO_UINT by promoting the destination to a larger signed
303 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
304 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
305 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
307 if (Subtarget->is64Bit()) {
308 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
309 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
310 } else if (!TM.Options.UseSoftFloat) {
311 // Since AVX is a superset of SSE3, only check for SSE here.
312 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
313 // Expand FP_TO_UINT into a select.
314 // FIXME: We would like to use a Custom expander here eventually to do
315 // the optimal thing for SSE vs. the default expansion in the legalizer.
316 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
318 // With SSE3 we can use fisttpll to convert to a signed i64; without
319 // SSE, we're stuck with a fistpll.
320 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
323 if (isTargetFTOL()) {
324 // Use the _ftol2 runtime function, which has a pseudo-instruction
325 // to handle its weird calling convention.
326 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
329 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
330 if (!X86ScalarSSEf64) {
331 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
332 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
333 if (Subtarget->is64Bit()) {
334 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
335 // Without SSE, i64->f64 goes through memory.
336 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
340 // Scalar integer divide and remainder are lowered to use operations that
341 // produce two results, to match the available instructions. This exposes
342 // the two-result form to trivial CSE, which is able to combine x/y and x%y
343 // into a single instruction.
345 // Scalar integer multiply-high is also lowered to use two-result
346 // operations, to match the available instructions. However, plain multiply
347 // (low) operations are left as Legal, as there are single-result
348 // instructions for this in x86. Using the two-result multiply instructions
349 // when both high and low results are needed must be arranged by dagcombine.
350 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
352 setOperationAction(ISD::MULHS, VT, Expand);
353 setOperationAction(ISD::MULHU, VT, Expand);
354 setOperationAction(ISD::SDIV, VT, Expand);
355 setOperationAction(ISD::UDIV, VT, Expand);
356 setOperationAction(ISD::SREM, VT, Expand);
357 setOperationAction(ISD::UREM, VT, Expand);
359 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
360 setOperationAction(ISD::ADDC, VT, Custom);
361 setOperationAction(ISD::ADDE, VT, Custom);
362 setOperationAction(ISD::SUBC, VT, Custom);
363 setOperationAction(ISD::SUBE, VT, Custom);
366 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
367 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
368 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
369 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
370 if (Subtarget->is64Bit())
371 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
372 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
373 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
374 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
375 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
376 setOperationAction(ISD::FREM , MVT::f32 , Expand);
377 setOperationAction(ISD::FREM , MVT::f64 , Expand);
378 setOperationAction(ISD::FREM , MVT::f80 , Expand);
379 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
381 // Promote the i8 variants and force them on up to i32 which has a shorter
383 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
384 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
385 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
386 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
387 if (Subtarget->hasBMI()) {
388 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
389 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
390 if (Subtarget->is64Bit())
391 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
393 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
394 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
395 if (Subtarget->is64Bit())
396 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
399 if (Subtarget->hasLZCNT()) {
400 // When promoting the i8 variants, force them to i32 for a shorter
402 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
403 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
404 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
405 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
406 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
407 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
408 if (Subtarget->is64Bit())
409 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
411 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
412 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
413 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
414 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
415 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
416 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
417 if (Subtarget->is64Bit()) {
418 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
419 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
423 if (Subtarget->hasPOPCNT()) {
424 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
426 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
427 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
428 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
429 if (Subtarget->is64Bit())
430 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
433 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
434 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
436 // These should be promoted to a larger select which is supported.
437 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
438 // X86 wants to expand cmov itself.
439 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
440 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
441 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
442 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
443 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
444 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
445 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
446 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
447 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
448 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
449 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
450 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
451 if (Subtarget->is64Bit()) {
452 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
453 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
455 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
458 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
459 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
460 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
461 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
462 if (Subtarget->is64Bit())
463 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
464 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
465 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
466 if (Subtarget->is64Bit()) {
467 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
468 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
469 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
470 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
471 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
473 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
474 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
475 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
476 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
477 if (Subtarget->is64Bit()) {
478 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
479 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
480 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
483 if (Subtarget->hasSSE1())
484 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
486 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom);
487 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
489 // On X86 and X86-64, atomic operations are lowered to locked instructions.
490 // Locked instructions, in turn, have implicit fence semantics (all memory
491 // operations are flushed before issuing the locked instruction, and they
492 // are not buffered), so we can fold away the common pattern of
493 // fence-atomic-fence.
494 setShouldFoldAtomicFences(true);
496 // Expand certain atomics
497 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
499 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom);
500 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
501 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
504 if (!Subtarget->is64Bit()) {
505 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
506 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
507 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
508 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
509 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
510 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
511 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
512 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
515 if (Subtarget->hasCmpxchg16b()) {
516 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom);
519 // FIXME - use subtarget debug flags
520 if (!Subtarget->isTargetDarwin() &&
521 !Subtarget->isTargetELF() &&
522 !Subtarget->isTargetCygMing()) {
523 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
526 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
527 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
528 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
529 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
530 if (Subtarget->is64Bit()) {
531 setExceptionPointerRegister(X86::RAX);
532 setExceptionSelectorRegister(X86::RDX);
534 setExceptionPointerRegister(X86::EAX);
535 setExceptionSelectorRegister(X86::EDX);
537 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
538 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
540 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
541 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
543 setOperationAction(ISD::TRAP, MVT::Other, Legal);
545 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
546 setOperationAction(ISD::VASTART , MVT::Other, Custom);
547 setOperationAction(ISD::VAEND , MVT::Other, Expand);
548 if (Subtarget->is64Bit()) {
549 setOperationAction(ISD::VAARG , MVT::Other, Custom);
550 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
552 setOperationAction(ISD::VAARG , MVT::Other, Expand);
553 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
556 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
557 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
559 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
560 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
561 MVT::i64 : MVT::i32, Custom);
562 else if (TM.Options.EnableSegmentedStacks)
563 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
564 MVT::i64 : MVT::i32, Custom);
566 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
567 MVT::i64 : MVT::i32, Expand);
569 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
570 // f32 and f64 use SSE.
571 // Set up the FP register classes.
572 addRegisterClass(MVT::f32, &X86::FR32RegClass);
573 addRegisterClass(MVT::f64, &X86::FR64RegClass);
575 // Use ANDPD to simulate FABS.
576 setOperationAction(ISD::FABS , MVT::f64, Custom);
577 setOperationAction(ISD::FABS , MVT::f32, Custom);
579 // Use XORP to simulate FNEG.
580 setOperationAction(ISD::FNEG , MVT::f64, Custom);
581 setOperationAction(ISD::FNEG , MVT::f32, Custom);
583 // Use ANDPD and ORPD to simulate FCOPYSIGN.
584 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
585 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
587 // Lower this to FGETSIGNx86 plus an AND.
588 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
589 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
591 // We don't support sin/cos/fmod
592 setOperationAction(ISD::FSIN , MVT::f64, Expand);
593 setOperationAction(ISD::FCOS , MVT::f64, Expand);
594 setOperationAction(ISD::FSIN , MVT::f32, Expand);
595 setOperationAction(ISD::FCOS , MVT::f32, Expand);
597 // Expand FP immediates into loads from the stack, except for the special
599 addLegalFPImmediate(APFloat(+0.0)); // xorpd
600 addLegalFPImmediate(APFloat(+0.0f)); // xorps
601 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
602 // Use SSE for f32, x87 for f64.
603 // Set up the FP register classes.
604 addRegisterClass(MVT::f32, &X86::FR32RegClass);
605 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
607 // Use ANDPS to simulate FABS.
608 setOperationAction(ISD::FABS , MVT::f32, Custom);
610 // Use XORP to simulate FNEG.
611 setOperationAction(ISD::FNEG , MVT::f32, Custom);
613 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
615 // Use ANDPS and ORPS to simulate FCOPYSIGN.
616 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
617 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
619 // We don't support sin/cos/fmod
620 setOperationAction(ISD::FSIN , MVT::f32, Expand);
621 setOperationAction(ISD::FCOS , MVT::f32, Expand);
623 // Special cases we handle for FP constants.
624 addLegalFPImmediate(APFloat(+0.0f)); // xorps
625 addLegalFPImmediate(APFloat(+0.0)); // FLD0
626 addLegalFPImmediate(APFloat(+1.0)); // FLD1
627 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
628 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
630 if (!TM.Options.UnsafeFPMath) {
631 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
632 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
634 } else if (!TM.Options.UseSoftFloat) {
635 // f32 and f64 in x87.
636 // Set up the FP register classes.
637 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
638 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
640 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
641 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
642 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
643 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
645 if (!TM.Options.UnsafeFPMath) {
646 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
647 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
649 addLegalFPImmediate(APFloat(+0.0)); // FLD0
650 addLegalFPImmediate(APFloat(+1.0)); // FLD1
651 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
652 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
653 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
654 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
655 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
656 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
659 // We don't support FMA.
660 setOperationAction(ISD::FMA, MVT::f64, Expand);
661 setOperationAction(ISD::FMA, MVT::f32, Expand);
663 // Long double always uses X87.
664 if (!TM.Options.UseSoftFloat) {
665 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
666 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
667 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
669 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
670 addLegalFPImmediate(TmpFlt); // FLD0
672 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
675 APFloat TmpFlt2(+1.0);
676 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
678 addLegalFPImmediate(TmpFlt2); // FLD1
679 TmpFlt2.changeSign();
680 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
683 if (!TM.Options.UnsafeFPMath) {
684 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
685 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
688 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
689 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
690 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
691 setOperationAction(ISD::FRINT, MVT::f80, Expand);
692 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
693 setOperationAction(ISD::FMA, MVT::f80, Expand);
696 // Always use a library call for pow.
697 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
698 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
699 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
701 setOperationAction(ISD::FLOG, MVT::f80, Expand);
702 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
703 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
704 setOperationAction(ISD::FEXP, MVT::f80, Expand);
705 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
707 // First set operation action for all vector types to either promote
708 // (for widening) or expand (for scalarization). Then we will selectively
709 // turn on ones that can be effectively codegen'd.
710 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
711 VT <= MVT::LAST_VECTOR_VALUETYPE; ++VT) {
712 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
713 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
714 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
715 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
716 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
717 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
718 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
719 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
720 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
721 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
722 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
723 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
724 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
725 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
726 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
727 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
728 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
729 setOperationAction(ISD::INSERT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
730 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
731 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
732 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
733 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
734 setOperationAction(ISD::FMA, (MVT::SimpleValueType)VT, Expand);
735 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
736 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
737 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
738 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
739 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
740 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
741 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
742 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
743 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
744 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
745 setOperationAction(ISD::CTTZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand);
746 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
747 setOperationAction(ISD::CTLZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand);
748 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
749 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
750 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
751 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
752 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
753 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
754 setOperationAction(ISD::SETCC, (MVT::SimpleValueType)VT, Expand);
755 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
756 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
757 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
758 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
759 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
760 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand);
761 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand);
762 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
763 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
764 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand);
765 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand);
766 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand);
767 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand);
768 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand);
769 setOperationAction(ISD::VSELECT, (MVT::SimpleValueType)VT, Expand);
770 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
771 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
772 setTruncStoreAction((MVT::SimpleValueType)VT,
773 (MVT::SimpleValueType)InnerVT, Expand);
774 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
775 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
776 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
779 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
780 // with -msoft-float, disable use of MMX as well.
781 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
782 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
783 // No operations on x86mmx supported, everything uses intrinsics.
786 // MMX-sized vectors (other than x86mmx) are expected to be expanded
787 // into smaller operations.
788 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
789 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
790 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
791 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
792 setOperationAction(ISD::AND, MVT::v8i8, Expand);
793 setOperationAction(ISD::AND, MVT::v4i16, Expand);
794 setOperationAction(ISD::AND, MVT::v2i32, Expand);
795 setOperationAction(ISD::AND, MVT::v1i64, Expand);
796 setOperationAction(ISD::OR, MVT::v8i8, Expand);
797 setOperationAction(ISD::OR, MVT::v4i16, Expand);
798 setOperationAction(ISD::OR, MVT::v2i32, Expand);
799 setOperationAction(ISD::OR, MVT::v1i64, Expand);
800 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
801 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
802 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
803 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
804 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
805 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
806 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
807 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
808 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
809 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
810 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
811 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
812 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
813 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
814 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
815 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
816 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
818 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
819 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
821 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
822 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
823 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
824 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
825 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
826 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
827 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
828 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
829 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
830 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
831 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
832 setOperationAction(ISD::SETCC, MVT::v4f32, Custom);
835 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
836 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
838 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
839 // registers cannot be used even for integer operations.
840 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
841 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
842 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
843 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
845 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
846 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
847 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
848 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
849 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
850 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
851 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
852 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
853 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
854 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
855 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
856 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
857 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
858 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
859 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
860 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
862 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
863 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
864 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
865 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
867 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
868 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
869 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
870 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
871 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
873 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom);
874 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom);
875 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom);
876 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom);
877 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
879 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
880 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
881 MVT VT = (MVT::SimpleValueType)i;
882 // Do not attempt to custom lower non-power-of-2 vectors
883 if (!isPowerOf2_32(VT.getVectorNumElements()))
885 // Do not attempt to custom lower non-128-bit vectors
886 if (!VT.is128BitVector())
888 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
889 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
890 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
893 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
894 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
895 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
896 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
897 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
898 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
900 if (Subtarget->is64Bit()) {
901 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
902 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
905 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
906 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
907 MVT VT = (MVT::SimpleValueType)i;
909 // Do not attempt to promote non-128-bit vectors
910 if (!VT.is128BitVector())
913 setOperationAction(ISD::AND, VT, Promote);
914 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
915 setOperationAction(ISD::OR, VT, Promote);
916 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
917 setOperationAction(ISD::XOR, VT, Promote);
918 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
919 setOperationAction(ISD::LOAD, VT, Promote);
920 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
921 setOperationAction(ISD::SELECT, VT, Promote);
922 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
925 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
927 // Custom lower v2i64 and v2f64 selects.
928 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
929 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
930 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
931 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
933 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
934 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
937 if (Subtarget->hasSSE41()) {
938 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
939 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
940 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
941 setOperationAction(ISD::FRINT, MVT::f32, Legal);
942 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
943 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
944 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
945 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
946 setOperationAction(ISD::FRINT, MVT::f64, Legal);
947 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
949 // FIXME: Do we need to handle scalar-to-vector here?
950 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
952 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
953 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal);
954 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
955 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
956 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
958 // i8 and i16 vectors are custom , because the source register and source
959 // source memory operand types are not the same width. f32 vectors are
960 // custom since the immediate controlling the insert encodes additional
962 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
963 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
964 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
965 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
967 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
968 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
969 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
970 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
972 // FIXME: these should be Legal but thats only for the case where
973 // the index is constant. For now custom expand to deal with that.
974 if (Subtarget->is64Bit()) {
975 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
976 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
980 if (Subtarget->hasSSE2()) {
981 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
982 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
984 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
985 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
987 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
988 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
990 if (Subtarget->hasAVX2()) {
991 setOperationAction(ISD::SRL, MVT::v2i64, Legal);
992 setOperationAction(ISD::SRL, MVT::v4i32, Legal);
994 setOperationAction(ISD::SHL, MVT::v2i64, Legal);
995 setOperationAction(ISD::SHL, MVT::v4i32, Legal);
997 setOperationAction(ISD::SRA, MVT::v4i32, Legal);
999 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1000 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1002 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1003 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1005 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1009 if (Subtarget->hasSSE42())
1010 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
1012 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX()) {
1013 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1014 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1015 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1016 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1017 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1018 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1020 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1021 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1022 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1024 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1025 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1026 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1027 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1028 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1029 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1031 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1032 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1033 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1034 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1035 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1036 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1038 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1039 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1040 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1042 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1043 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1045 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1046 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1048 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1049 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1051 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1052 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1053 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1054 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1056 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1057 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1058 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1060 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal);
1061 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal);
1062 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal);
1063 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal);
1065 if (Subtarget->hasFMA()) {
1066 setOperationAction(ISD::FMA, MVT::v8f32, Custom);
1067 setOperationAction(ISD::FMA, MVT::v4f64, Custom);
1068 setOperationAction(ISD::FMA, MVT::v4f32, Custom);
1069 setOperationAction(ISD::FMA, MVT::v2f64, Custom);
1070 setOperationAction(ISD::FMA, MVT::f32, Custom);
1071 setOperationAction(ISD::FMA, MVT::f64, Custom);
1074 if (Subtarget->hasAVX2()) {
1075 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1076 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1077 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1078 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1080 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1081 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1082 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1083 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1085 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1086 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1087 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1088 // Don't lower v32i8 because there is no 128-bit byte mul
1090 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1092 setOperationAction(ISD::SRL, MVT::v4i64, Legal);
1093 setOperationAction(ISD::SRL, MVT::v8i32, Legal);
1095 setOperationAction(ISD::SHL, MVT::v4i64, Legal);
1096 setOperationAction(ISD::SHL, MVT::v8i32, Legal);
1098 setOperationAction(ISD::SRA, MVT::v8i32, Legal);
1100 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1101 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1102 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1103 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1105 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1106 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1107 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1108 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1110 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1111 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1112 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1113 // Don't lower v32i8 because there is no 128-bit byte mul
1115 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1116 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1118 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1119 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1121 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1124 // Custom lower several nodes for 256-bit types.
1125 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1126 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1127 MVT VT = (MVT::SimpleValueType)i;
1129 // Extract subvector is special because the value type
1130 // (result) is 128-bit but the source is 256-bit wide.
1131 if (VT.is128BitVector())
1132 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1134 // Do not attempt to custom lower other non-256-bit vectors
1135 if (!VT.is256BitVector())
1138 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1139 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1140 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1141 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1142 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1143 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1144 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1147 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1148 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1149 MVT VT = (MVT::SimpleValueType)i;
1151 // Do not attempt to promote non-256-bit vectors
1152 if (!VT.is256BitVector())
1155 setOperationAction(ISD::AND, VT, Promote);
1156 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1157 setOperationAction(ISD::OR, VT, Promote);
1158 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1159 setOperationAction(ISD::XOR, VT, Promote);
1160 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1161 setOperationAction(ISD::LOAD, VT, Promote);
1162 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1163 setOperationAction(ISD::SELECT, VT, Promote);
1164 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1168 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1169 // of this type with custom code.
1170 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1171 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1172 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1176 // We want to custom lower some of our intrinsics.
1177 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1178 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1181 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1182 // handle type legalization for these operations here.
1184 // FIXME: We really should do custom legalization for addition and
1185 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1186 // than generic legalization for 64-bit multiplication-with-overflow, though.
1187 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1188 // Add/Sub/Mul with overflow operations are custom lowered.
1190 setOperationAction(ISD::SADDO, VT, Custom);
1191 setOperationAction(ISD::UADDO, VT, Custom);
1192 setOperationAction(ISD::SSUBO, VT, Custom);
1193 setOperationAction(ISD::USUBO, VT, Custom);
1194 setOperationAction(ISD::SMULO, VT, Custom);
1195 setOperationAction(ISD::UMULO, VT, Custom);
1198 // There are no 8-bit 3-address imul/mul instructions
1199 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1200 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1202 if (!Subtarget->is64Bit()) {
1203 // These libcalls are not available in 32-bit.
1204 setLibcallName(RTLIB::SHL_I128, 0);
1205 setLibcallName(RTLIB::SRL_I128, 0);
1206 setLibcallName(RTLIB::SRA_I128, 0);
1209 // We have target-specific dag combine patterns for the following nodes:
1210 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1211 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1212 setTargetDAGCombine(ISD::VSELECT);
1213 setTargetDAGCombine(ISD::SELECT);
1214 setTargetDAGCombine(ISD::SHL);
1215 setTargetDAGCombine(ISD::SRA);
1216 setTargetDAGCombine(ISD::SRL);
1217 setTargetDAGCombine(ISD::OR);
1218 setTargetDAGCombine(ISD::AND);
1219 setTargetDAGCombine(ISD::ADD);
1220 setTargetDAGCombine(ISD::FADD);
1221 setTargetDAGCombine(ISD::FSUB);
1222 setTargetDAGCombine(ISD::FMA);
1223 setTargetDAGCombine(ISD::SUB);
1224 setTargetDAGCombine(ISD::LOAD);
1225 setTargetDAGCombine(ISD::STORE);
1226 setTargetDAGCombine(ISD::ZERO_EXTEND);
1227 setTargetDAGCombine(ISD::ANY_EXTEND);
1228 setTargetDAGCombine(ISD::SIGN_EXTEND);
1229 setTargetDAGCombine(ISD::TRUNCATE);
1230 setTargetDAGCombine(ISD::UINT_TO_FP);
1231 setTargetDAGCombine(ISD::SINT_TO_FP);
1232 setTargetDAGCombine(ISD::SETCC);
1233 setTargetDAGCombine(ISD::FP_TO_SINT);
1234 if (Subtarget->is64Bit())
1235 setTargetDAGCombine(ISD::MUL);
1236 setTargetDAGCombine(ISD::XOR);
1238 computeRegisterProperties();
1240 // On Darwin, -Os means optimize for size without hurting performance,
1241 // do not reduce the limit.
1242 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1243 maxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1244 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1245 maxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1246 maxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1247 maxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1248 setPrefLoopAlignment(4); // 2^4 bytes.
1249 benefitFromCodePlacementOpt = true;
1251 // Predictable cmov don't hurt on atom because it's in-order.
1252 predictableSelectIsExpensive = !Subtarget->isAtom();
1254 setPrefFunctionAlignment(4); // 2^4 bytes.
1258 EVT X86TargetLowering::getSetCCResultType(EVT VT) const {
1259 if (!VT.isVector()) return MVT::i8;
1260 return VT.changeVectorElementTypeToInteger();
1264 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1265 /// the desired ByVal argument alignment.
1266 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1269 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1270 if (VTy->getBitWidth() == 128)
1272 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1273 unsigned EltAlign = 0;
1274 getMaxByValAlign(ATy->getElementType(), EltAlign);
1275 if (EltAlign > MaxAlign)
1276 MaxAlign = EltAlign;
1277 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1278 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1279 unsigned EltAlign = 0;
1280 getMaxByValAlign(STy->getElementType(i), EltAlign);
1281 if (EltAlign > MaxAlign)
1282 MaxAlign = EltAlign;
1289 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1290 /// function arguments in the caller parameter area. For X86, aggregates
1291 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1292 /// are at 4-byte boundaries.
1293 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1294 if (Subtarget->is64Bit()) {
1295 // Max of 8 and alignment of type.
1296 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1303 if (Subtarget->hasSSE1())
1304 getMaxByValAlign(Ty, Align);
1308 /// getOptimalMemOpType - Returns the target specific optimal type for load
1309 /// and store operations as a result of memset, memcpy, and memmove
1310 /// lowering. If DstAlign is zero that means it's safe to destination
1311 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1312 /// means there isn't a need to check it against alignment requirement,
1313 /// probably because the source does not need to be loaded. If
1314 /// 'IsZeroVal' is true, that means it's safe to return a
1315 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
1316 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
1317 /// constant so it does not need to be loaded.
1318 /// It returns EVT::Other if the type should be determined using generic
1319 /// target-independent logic.
1321 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1322 unsigned DstAlign, unsigned SrcAlign,
1325 MachineFunction &MF) const {
1326 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
1327 // linux. This is because the stack realignment code can't handle certain
1328 // cases like PR2962. This should be removed when PR2962 is fixed.
1329 const Function *F = MF.getFunction();
1331 !F->hasFnAttr(Attribute::NoImplicitFloat)) {
1333 (Subtarget->isUnalignedMemAccessFast() ||
1334 ((DstAlign == 0 || DstAlign >= 16) &&
1335 (SrcAlign == 0 || SrcAlign >= 16))) &&
1336 Subtarget->getStackAlignment() >= 16) {
1337 if (Subtarget->getStackAlignment() >= 32) {
1338 if (Subtarget->hasAVX2())
1340 if (Subtarget->hasAVX())
1343 if (Subtarget->hasSSE2())
1345 if (Subtarget->hasSSE1())
1347 } else if (!MemcpyStrSrc && Size >= 8 &&
1348 !Subtarget->is64Bit() &&
1349 Subtarget->getStackAlignment() >= 8 &&
1350 Subtarget->hasSSE2()) {
1351 // Do not use f64 to lower memcpy if source is string constant. It's
1352 // better to use i32 to avoid the loads.
1356 if (Subtarget->is64Bit() && Size >= 8)
1361 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1362 /// current function. The returned value is a member of the
1363 /// MachineJumpTableInfo::JTEntryKind enum.
1364 unsigned X86TargetLowering::getJumpTableEncoding() const {
1365 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1367 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1368 Subtarget->isPICStyleGOT())
1369 return MachineJumpTableInfo::EK_Custom32;
1371 // Otherwise, use the normal jump table encoding heuristics.
1372 return TargetLowering::getJumpTableEncoding();
1376 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1377 const MachineBasicBlock *MBB,
1378 unsigned uid,MCContext &Ctx) const{
1379 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1380 Subtarget->isPICStyleGOT());
1381 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1383 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1384 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1387 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1389 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1390 SelectionDAG &DAG) const {
1391 if (!Subtarget->is64Bit())
1392 // This doesn't have DebugLoc associated with it, but is not really the
1393 // same as a Register.
1394 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy());
1398 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1399 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1401 const MCExpr *X86TargetLowering::
1402 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1403 MCContext &Ctx) const {
1404 // X86-64 uses RIP relative addressing based on the jump table label.
1405 if (Subtarget->isPICStyleRIPRel())
1406 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1408 // Otherwise, the reference is relative to the PIC base.
1409 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1412 // FIXME: Why this routine is here? Move to RegInfo!
1413 std::pair<const TargetRegisterClass*, uint8_t>
1414 X86TargetLowering::findRepresentativeClass(EVT VT) const{
1415 const TargetRegisterClass *RRC = 0;
1417 switch (VT.getSimpleVT().SimpleTy) {
1419 return TargetLowering::findRepresentativeClass(VT);
1420 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1421 RRC = Subtarget->is64Bit() ?
1422 (const TargetRegisterClass*)&X86::GR64RegClass :
1423 (const TargetRegisterClass*)&X86::GR32RegClass;
1426 RRC = &X86::VR64RegClass;
1428 case MVT::f32: case MVT::f64:
1429 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1430 case MVT::v4f32: case MVT::v2f64:
1431 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1433 RRC = &X86::VR128RegClass;
1436 return std::make_pair(RRC, Cost);
1439 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1440 unsigned &Offset) const {
1441 if (!Subtarget->isTargetLinux())
1444 if (Subtarget->is64Bit()) {
1445 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1447 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1460 //===----------------------------------------------------------------------===//
1461 // Return Value Calling Convention Implementation
1462 //===----------------------------------------------------------------------===//
1464 #include "X86GenCallingConv.inc"
1467 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1468 MachineFunction &MF, bool isVarArg,
1469 const SmallVectorImpl<ISD::OutputArg> &Outs,
1470 LLVMContext &Context) const {
1471 SmallVector<CCValAssign, 16> RVLocs;
1472 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1474 return CCInfo.CheckReturn(Outs, RetCC_X86);
1478 X86TargetLowering::LowerReturn(SDValue Chain,
1479 CallingConv::ID CallConv, bool isVarArg,
1480 const SmallVectorImpl<ISD::OutputArg> &Outs,
1481 const SmallVectorImpl<SDValue> &OutVals,
1482 DebugLoc dl, SelectionDAG &DAG) const {
1483 MachineFunction &MF = DAG.getMachineFunction();
1484 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1486 SmallVector<CCValAssign, 16> RVLocs;
1487 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1488 RVLocs, *DAG.getContext());
1489 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1491 // Add the regs to the liveout set for the function.
1492 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1493 for (unsigned i = 0; i != RVLocs.size(); ++i)
1494 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg()))
1495 MRI.addLiveOut(RVLocs[i].getLocReg());
1499 SmallVector<SDValue, 6> RetOps;
1500 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1501 // Operand #1 = Bytes To Pop
1502 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1505 // Copy the result values into the output registers.
1506 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1507 CCValAssign &VA = RVLocs[i];
1508 assert(VA.isRegLoc() && "Can only return in registers!");
1509 SDValue ValToCopy = OutVals[i];
1510 EVT ValVT = ValToCopy.getValueType();
1512 // Promote values to the appropriate types
1513 if (VA.getLocInfo() == CCValAssign::SExt)
1514 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
1515 else if (VA.getLocInfo() == CCValAssign::ZExt)
1516 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
1517 else if (VA.getLocInfo() == CCValAssign::AExt)
1518 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
1519 else if (VA.getLocInfo() == CCValAssign::BCvt)
1520 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
1522 // If this is x86-64, and we disabled SSE, we can't return FP values,
1523 // or SSE or MMX vectors.
1524 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1525 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1526 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1527 report_fatal_error("SSE register return with SSE disabled");
1529 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1530 // llvm-gcc has never done it right and no one has noticed, so this
1531 // should be OK for now.
1532 if (ValVT == MVT::f64 &&
1533 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1534 report_fatal_error("SSE2 register return with SSE2 disabled");
1536 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1537 // the RET instruction and handled by the FP Stackifier.
1538 if (VA.getLocReg() == X86::ST0 ||
1539 VA.getLocReg() == X86::ST1) {
1540 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1541 // change the value to the FP stack register class.
1542 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1543 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1544 RetOps.push_back(ValToCopy);
1545 // Don't emit a copytoreg.
1549 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1550 // which is returned in RAX / RDX.
1551 if (Subtarget->is64Bit()) {
1552 if (ValVT == MVT::x86mmx) {
1553 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1554 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1555 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1557 // If we don't have SSE2 available, convert to v4f32 so the generated
1558 // register is legal.
1559 if (!Subtarget->hasSSE2())
1560 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1565 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1566 Flag = Chain.getValue(1);
1569 // The x86-64 ABI for returning structs by value requires that we copy
1570 // the sret argument into %rax for the return. We saved the argument into
1571 // a virtual register in the entry block, so now we copy the value out
1573 if (Subtarget->is64Bit() &&
1574 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1575 MachineFunction &MF = DAG.getMachineFunction();
1576 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1577 unsigned Reg = FuncInfo->getSRetReturnReg();
1579 "SRetReturnReg should have been set in LowerFormalArguments().");
1580 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1582 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
1583 Flag = Chain.getValue(1);
1585 // RAX now acts like a return value.
1586 MRI.addLiveOut(X86::RAX);
1589 RetOps[0] = Chain; // Update chain.
1591 // Add the flag if we have it.
1593 RetOps.push_back(Flag);
1595 return DAG.getNode(X86ISD::RET_FLAG, dl,
1596 MVT::Other, &RetOps[0], RetOps.size());
1599 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
1600 if (N->getNumValues() != 1)
1602 if (!N->hasNUsesOfValue(1, 0))
1605 SDValue TCChain = Chain;
1606 SDNode *Copy = *N->use_begin();
1607 if (Copy->getOpcode() == ISD::CopyToReg) {
1608 // If the copy has a glue operand, we conservatively assume it isn't safe to
1609 // perform a tail call.
1610 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
1612 TCChain = Copy->getOperand(0);
1613 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
1616 bool HasRet = false;
1617 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1619 if (UI->getOpcode() != X86ISD::RET_FLAG)
1632 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
1633 ISD::NodeType ExtendKind) const {
1635 // TODO: Is this also valid on 32-bit?
1636 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
1637 ReturnMVT = MVT::i8;
1639 ReturnMVT = MVT::i32;
1641 EVT MinVT = getRegisterType(Context, ReturnMVT);
1642 return VT.bitsLT(MinVT) ? MinVT : VT;
1645 /// LowerCallResult - Lower the result values of a call into the
1646 /// appropriate copies out of appropriate physical registers.
1649 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1650 CallingConv::ID CallConv, bool isVarArg,
1651 const SmallVectorImpl<ISD::InputArg> &Ins,
1652 DebugLoc dl, SelectionDAG &DAG,
1653 SmallVectorImpl<SDValue> &InVals) const {
1655 // Assign locations to each value returned by this call.
1656 SmallVector<CCValAssign, 16> RVLocs;
1657 bool Is64Bit = Subtarget->is64Bit();
1658 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1659 getTargetMachine(), RVLocs, *DAG.getContext());
1660 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1662 // Copy all of the result registers out of their specified physreg.
1663 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1664 CCValAssign &VA = RVLocs[i];
1665 EVT CopyVT = VA.getValVT();
1667 // If this is x86-64, and we disabled SSE, we can't return FP values
1668 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1669 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
1670 report_fatal_error("SSE register return with SSE disabled");
1675 // If this is a call to a function that returns an fp value on the floating
1676 // point stack, we must guarantee the value is popped from the stack, so
1677 // a CopyFromReg is not good enough - the copy instruction may be eliminated
1678 // if the return value is not used. We use the FpPOP_RETVAL instruction
1680 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
1681 // If we prefer to use the value in xmm registers, copy it out as f80 and
1682 // use a truncate to move it from fp stack reg to xmm reg.
1683 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
1684 SDValue Ops[] = { Chain, InFlag };
1685 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT,
1686 MVT::Other, MVT::Glue, Ops, 2), 1);
1687 Val = Chain.getValue(0);
1689 // Round the f80 to the right size, which also moves it to the appropriate
1691 if (CopyVT != VA.getValVT())
1692 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1693 // This truncation won't change the value.
1694 DAG.getIntPtrConstant(1));
1696 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1697 CopyVT, InFlag).getValue(1);
1698 Val = Chain.getValue(0);
1700 InFlag = Chain.getValue(2);
1701 InVals.push_back(Val);
1708 //===----------------------------------------------------------------------===//
1709 // C & StdCall & Fast Calling Convention implementation
1710 //===----------------------------------------------------------------------===//
1711 // StdCall calling convention seems to be standard for many Windows' API
1712 // routines and around. It differs from C calling convention just a little:
1713 // callee should clean up the stack, not caller. Symbols should be also
1714 // decorated in some fancy way :) It doesn't support any vector arguments.
1715 // For info on fast calling convention see Fast Calling Convention (tail call)
1716 // implementation LowerX86_32FastCCCallTo.
1718 /// CallIsStructReturn - Determines whether a call uses struct return
1720 enum StructReturnType {
1725 static StructReturnType
1726 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1728 return NotStructReturn;
1730 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
1731 if (!Flags.isSRet())
1732 return NotStructReturn;
1733 if (Flags.isInReg())
1734 return RegStructReturn;
1735 return StackStructReturn;
1738 /// ArgsAreStructReturn - Determines whether a function uses struct
1739 /// return semantics.
1740 static StructReturnType
1741 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
1743 return NotStructReturn;
1745 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
1746 if (!Flags.isSRet())
1747 return NotStructReturn;
1748 if (Flags.isInReg())
1749 return RegStructReturn;
1750 return StackStructReturn;
1753 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1754 /// by "Src" to address "Dst" with size and alignment information specified by
1755 /// the specific parameter attribute. The copy will be passed as a byval
1756 /// function parameter.
1758 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1759 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1761 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1763 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1764 /*isVolatile*/false, /*AlwaysInline=*/true,
1765 MachinePointerInfo(), MachinePointerInfo());
1768 /// IsTailCallConvention - Return true if the calling convention is one that
1769 /// supports tail call optimization.
1770 static bool IsTailCallConvention(CallingConv::ID CC) {
1771 return (CC == CallingConv::Fast || CC == CallingConv::GHC);
1774 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
1775 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
1779 CallingConv::ID CalleeCC = CS.getCallingConv();
1780 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C)
1786 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
1787 /// a tailcall target by changing its ABI.
1788 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
1789 bool GuaranteedTailCallOpt) {
1790 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
1794 X86TargetLowering::LowerMemArgument(SDValue Chain,
1795 CallingConv::ID CallConv,
1796 const SmallVectorImpl<ISD::InputArg> &Ins,
1797 DebugLoc dl, SelectionDAG &DAG,
1798 const CCValAssign &VA,
1799 MachineFrameInfo *MFI,
1801 // Create the nodes corresponding to a load from this parameter slot.
1802 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1803 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv,
1804 getTargetMachine().Options.GuaranteedTailCallOpt);
1805 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1808 // If value is passed by pointer we have address passed instead of the value
1810 if (VA.getLocInfo() == CCValAssign::Indirect)
1811 ValVT = VA.getLocVT();
1813 ValVT = VA.getValVT();
1815 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1816 // changed with more analysis.
1817 // In case of tail call optimization mark all arguments mutable. Since they
1818 // could be overwritten by lowering of arguments in case of a tail call.
1819 if (Flags.isByVal()) {
1820 unsigned Bytes = Flags.getByValSize();
1821 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
1822 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
1823 return DAG.getFrameIndex(FI, getPointerTy());
1825 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
1826 VA.getLocMemOffset(), isImmutable);
1827 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1828 return DAG.getLoad(ValVT, dl, Chain, FIN,
1829 MachinePointerInfo::getFixedStack(FI),
1830 false, false, false, 0);
1835 X86TargetLowering::LowerFormalArguments(SDValue Chain,
1836 CallingConv::ID CallConv,
1838 const SmallVectorImpl<ISD::InputArg> &Ins,
1841 SmallVectorImpl<SDValue> &InVals)
1843 MachineFunction &MF = DAG.getMachineFunction();
1844 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1846 const Function* Fn = MF.getFunction();
1847 if (Fn->hasExternalLinkage() &&
1848 Subtarget->isTargetCygMing() &&
1849 Fn->getName() == "main")
1850 FuncInfo->setForceFramePointer(true);
1852 MachineFrameInfo *MFI = MF.getFrameInfo();
1853 bool Is64Bit = Subtarget->is64Bit();
1854 bool IsWindows = Subtarget->isTargetWindows();
1855 bool IsWin64 = Subtarget->isTargetWin64();
1857 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1858 "Var args not supported with calling convention fastcc or ghc");
1860 // Assign locations to all of the incoming arguments.
1861 SmallVector<CCValAssign, 16> ArgLocs;
1862 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1863 ArgLocs, *DAG.getContext());
1865 // Allocate shadow area for Win64
1867 CCInfo.AllocateStack(32, 8);
1870 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
1872 unsigned LastVal = ~0U;
1874 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1875 CCValAssign &VA = ArgLocs[i];
1876 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1878 assert(VA.getValNo() != LastVal &&
1879 "Don't support value assigned to multiple locs yet");
1881 LastVal = VA.getValNo();
1883 if (VA.isRegLoc()) {
1884 EVT RegVT = VA.getLocVT();
1885 const TargetRegisterClass *RC;
1886 if (RegVT == MVT::i32)
1887 RC = &X86::GR32RegClass;
1888 else if (Is64Bit && RegVT == MVT::i64)
1889 RC = &X86::GR64RegClass;
1890 else if (RegVT == MVT::f32)
1891 RC = &X86::FR32RegClass;
1892 else if (RegVT == MVT::f64)
1893 RC = &X86::FR64RegClass;
1894 else if (RegVT.is256BitVector())
1895 RC = &X86::VR256RegClass;
1896 else if (RegVT.is128BitVector())
1897 RC = &X86::VR128RegClass;
1898 else if (RegVT == MVT::x86mmx)
1899 RC = &X86::VR64RegClass;
1901 llvm_unreachable("Unknown argument type!");
1903 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1904 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1906 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1907 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1909 if (VA.getLocInfo() == CCValAssign::SExt)
1910 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1911 DAG.getValueType(VA.getValVT()));
1912 else if (VA.getLocInfo() == CCValAssign::ZExt)
1913 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1914 DAG.getValueType(VA.getValVT()));
1915 else if (VA.getLocInfo() == CCValAssign::BCvt)
1916 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
1918 if (VA.isExtInLoc()) {
1919 // Handle MMX values passed in XMM regs.
1920 if (RegVT.isVector()) {
1921 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(),
1924 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1927 assert(VA.isMemLoc());
1928 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
1931 // If value is passed via pointer - do a load.
1932 if (VA.getLocInfo() == CCValAssign::Indirect)
1933 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
1934 MachinePointerInfo(), false, false, false, 0);
1936 InVals.push_back(ArgValue);
1939 // The x86-64 ABI for returning structs by value requires that we copy
1940 // the sret argument into %rax for the return. Save the argument into
1941 // a virtual register so that we can access it from the return points.
1942 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) {
1943 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1944 unsigned Reg = FuncInfo->getSRetReturnReg();
1946 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1947 FuncInfo->setSRetReturnReg(Reg);
1949 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1950 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1953 unsigned StackSize = CCInfo.getNextStackOffset();
1954 // Align stack specially for tail calls.
1955 if (FuncIsMadeTailCallSafe(CallConv,
1956 MF.getTarget().Options.GuaranteedTailCallOpt))
1957 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1959 // If the function takes variable number of arguments, make a frame index for
1960 // the start of the first vararg value... for expansion of llvm.va_start.
1962 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
1963 CallConv != CallingConv::X86_ThisCall)) {
1964 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
1967 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1969 // FIXME: We should really autogenerate these arrays
1970 static const uint16_t GPR64ArgRegsWin64[] = {
1971 X86::RCX, X86::RDX, X86::R8, X86::R9
1973 static const uint16_t GPR64ArgRegs64Bit[] = {
1974 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1976 static const uint16_t XMMArgRegs64Bit[] = {
1977 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1978 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1980 const uint16_t *GPR64ArgRegs;
1981 unsigned NumXMMRegs = 0;
1984 // The XMM registers which might contain var arg parameters are shadowed
1985 // in their paired GPR. So we only need to save the GPR to their home
1987 TotalNumIntRegs = 4;
1988 GPR64ArgRegs = GPR64ArgRegsWin64;
1990 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1991 GPR64ArgRegs = GPR64ArgRegs64Bit;
1993 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit,
1996 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1999 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat);
2000 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2001 "SSE register cannot be used when SSE is disabled!");
2002 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat &&
2003 NoImplicitFloatOps) &&
2004 "SSE register cannot be used when SSE is disabled!");
2005 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2006 !Subtarget->hasSSE1())
2007 // Kernel mode asks for SSE to be disabled, so don't push them
2009 TotalNumXMMRegs = 0;
2012 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering();
2013 // Get to the caller-allocated home save location. Add 8 to account
2014 // for the return address.
2015 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2016 FuncInfo->setRegSaveFrameIndex(
2017 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2018 // Fixup to set vararg frame on shadow area (4 x i64).
2020 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2022 // For X86-64, if there are vararg parameters that are passed via
2023 // registers, then we must store them to their spots on the stack so
2024 // they may be loaded by deferencing the result of va_next.
2025 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2026 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
2027 FuncInfo->setRegSaveFrameIndex(
2028 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
2032 // Store the integer parameter registers.
2033 SmallVector<SDValue, 8> MemOps;
2034 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2036 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2037 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
2038 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2039 DAG.getIntPtrConstant(Offset));
2040 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
2041 &X86::GR64RegClass);
2042 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2044 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2045 MachinePointerInfo::getFixedStack(
2046 FuncInfo->getRegSaveFrameIndex(), Offset),
2048 MemOps.push_back(Store);
2052 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
2053 // Now store the XMM (fp + vector) parameter registers.
2054 SmallVector<SDValue, 11> SaveXMMOps;
2055 SaveXMMOps.push_back(Chain);
2057 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2058 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
2059 SaveXMMOps.push_back(ALVal);
2061 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2062 FuncInfo->getRegSaveFrameIndex()));
2063 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2064 FuncInfo->getVarArgsFPOffset()));
2066 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
2067 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
2068 &X86::VR128RegClass);
2069 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
2070 SaveXMMOps.push_back(Val);
2072 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2074 &SaveXMMOps[0], SaveXMMOps.size()));
2077 if (!MemOps.empty())
2078 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2079 &MemOps[0], MemOps.size());
2083 // Some CCs need callee pop.
2084 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2085 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2086 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2088 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2089 // If this is an sret function, the return should pop the hidden pointer.
2090 if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2091 argsAreStructReturn(Ins) == StackStructReturn)
2092 FuncInfo->setBytesToPopOnReturn(4);
2096 // RegSaveFrameIndex is X86-64 only.
2097 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2098 if (CallConv == CallingConv::X86_FastCall ||
2099 CallConv == CallingConv::X86_ThisCall)
2100 // fastcc functions can't have varargs.
2101 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2104 FuncInfo->setArgumentStackSize(StackSize);
2110 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2111 SDValue StackPtr, SDValue Arg,
2112 DebugLoc dl, SelectionDAG &DAG,
2113 const CCValAssign &VA,
2114 ISD::ArgFlagsTy Flags) const {
2115 unsigned LocMemOffset = VA.getLocMemOffset();
2116 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2117 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2118 if (Flags.isByVal())
2119 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2121 return DAG.getStore(Chain, dl, Arg, PtrOff,
2122 MachinePointerInfo::getStack(LocMemOffset),
2126 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2127 /// optimization is performed and it is required.
2129 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2130 SDValue &OutRetAddr, SDValue Chain,
2131 bool IsTailCall, bool Is64Bit,
2132 int FPDiff, DebugLoc dl) const {
2133 // Adjust the Return address stack slot.
2134 EVT VT = getPointerTy();
2135 OutRetAddr = getReturnAddressFrameIndex(DAG);
2137 // Load the "old" Return address.
2138 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2139 false, false, false, 0);
2140 return SDValue(OutRetAddr.getNode(), 1);
2143 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2144 /// optimization is performed and it is required (FPDiff!=0).
2146 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
2147 SDValue Chain, SDValue RetAddrFrIdx,
2148 bool Is64Bit, int FPDiff, DebugLoc dl) {
2149 // Store the return address to the appropriate stack slot.
2150 if (!FPDiff) return Chain;
2151 // Calculate the new stack slot for the return address.
2152 int SlotSize = Is64Bit ? 8 : 4;
2153 int NewReturnAddrFI =
2154 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false);
2155 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
2156 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
2157 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2158 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2164 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2165 SmallVectorImpl<SDValue> &InVals) const {
2166 SelectionDAG &DAG = CLI.DAG;
2167 DebugLoc &dl = CLI.DL;
2168 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
2169 SmallVector<SDValue, 32> &OutVals = CLI.OutVals;
2170 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
2171 SDValue Chain = CLI.Chain;
2172 SDValue Callee = CLI.Callee;
2173 CallingConv::ID CallConv = CLI.CallConv;
2174 bool &isTailCall = CLI.IsTailCall;
2175 bool isVarArg = CLI.IsVarArg;
2177 MachineFunction &MF = DAG.getMachineFunction();
2178 bool Is64Bit = Subtarget->is64Bit();
2179 bool IsWin64 = Subtarget->isTargetWin64();
2180 bool IsWindows = Subtarget->isTargetWindows();
2181 StructReturnType SR = callIsStructReturn(Outs);
2182 bool IsSibcall = false;
2184 if (MF.getTarget().Options.DisableTailCalls)
2188 // Check if it's really possible to do a tail call.
2189 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2190 isVarArg, SR != NotStructReturn,
2191 MF.getFunction()->hasStructRetAttr(),
2192 Outs, OutVals, Ins, DAG);
2194 // Sibcalls are automatically detected tailcalls which do not require
2196 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2203 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2204 "Var args not supported with calling convention fastcc or ghc");
2206 // Analyze operands of the call, assigning locations to each operand.
2207 SmallVector<CCValAssign, 16> ArgLocs;
2208 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2209 ArgLocs, *DAG.getContext());
2211 // Allocate shadow area for Win64
2213 CCInfo.AllocateStack(32, 8);
2216 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2218 // Get a count of how many bytes are to be pushed on the stack.
2219 unsigned NumBytes = CCInfo.getNextStackOffset();
2221 // This is a sibcall. The memory operands are available in caller's
2222 // own caller's stack.
2224 else if (getTargetMachine().Options.GuaranteedTailCallOpt &&
2225 IsTailCallConvention(CallConv))
2226 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2229 if (isTailCall && !IsSibcall) {
2230 // Lower arguments at fp - stackoffset + fpdiff.
2231 unsigned NumBytesCallerPushed =
2232 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
2233 FPDiff = NumBytesCallerPushed - NumBytes;
2235 // Set the delta of movement of the returnaddr stackslot.
2236 // But only set if delta is greater than previous delta.
2237 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
2238 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
2242 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
2244 SDValue RetAddrFrIdx;
2245 // Load return address for tail calls.
2246 if (isTailCall && FPDiff)
2247 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2248 Is64Bit, FPDiff, dl);
2250 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2251 SmallVector<SDValue, 8> MemOpChains;
2254 // Walk the register/memloc assignments, inserting copies/loads. In the case
2255 // of tail call optimization arguments are handle later.
2256 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2257 CCValAssign &VA = ArgLocs[i];
2258 EVT RegVT = VA.getLocVT();
2259 SDValue Arg = OutVals[i];
2260 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2261 bool isByVal = Flags.isByVal();
2263 // Promote the value if needed.
2264 switch (VA.getLocInfo()) {
2265 default: llvm_unreachable("Unknown loc info!");
2266 case CCValAssign::Full: break;
2267 case CCValAssign::SExt:
2268 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2270 case CCValAssign::ZExt:
2271 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2273 case CCValAssign::AExt:
2274 if (RegVT.is128BitVector()) {
2275 // Special case: passing MMX values in XMM registers.
2276 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2277 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2278 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2280 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2282 case CCValAssign::BCvt:
2283 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2285 case CCValAssign::Indirect: {
2286 // Store the argument.
2287 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2288 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2289 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2290 MachinePointerInfo::getFixedStack(FI),
2297 if (VA.isRegLoc()) {
2298 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2299 if (isVarArg && IsWin64) {
2300 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2301 // shadow reg if callee is a varargs function.
2302 unsigned ShadowReg = 0;
2303 switch (VA.getLocReg()) {
2304 case X86::XMM0: ShadowReg = X86::RCX; break;
2305 case X86::XMM1: ShadowReg = X86::RDX; break;
2306 case X86::XMM2: ShadowReg = X86::R8; break;
2307 case X86::XMM3: ShadowReg = X86::R9; break;
2310 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2312 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2313 assert(VA.isMemLoc());
2314 if (StackPtr.getNode() == 0)
2315 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
2316 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2317 dl, DAG, VA, Flags));
2321 if (!MemOpChains.empty())
2322 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2323 &MemOpChains[0], MemOpChains.size());
2325 if (Subtarget->isPICStyleGOT()) {
2326 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2329 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2330 DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy())));
2332 // If we are tail calling and generating PIC/GOT style code load the
2333 // address of the callee into ECX. The value in ecx is used as target of
2334 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2335 // for tail calls on PIC/GOT architectures. Normally we would just put the
2336 // address of GOT into ebx and then call target@PLT. But for tail calls
2337 // ebx would be restored (since ebx is callee saved) before jumping to the
2340 // Note: The actual moving to ECX is done further down.
2341 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2342 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2343 !G->getGlobal()->hasProtectedVisibility())
2344 Callee = LowerGlobalAddress(Callee, DAG);
2345 else if (isa<ExternalSymbolSDNode>(Callee))
2346 Callee = LowerExternalSymbol(Callee, DAG);
2350 if (Is64Bit && isVarArg && !IsWin64) {
2351 // From AMD64 ABI document:
2352 // For calls that may call functions that use varargs or stdargs
2353 // (prototype-less calls or calls to functions containing ellipsis (...) in
2354 // the declaration) %al is used as hidden argument to specify the number
2355 // of SSE registers used. The contents of %al do not need to match exactly
2356 // the number of registers, but must be an ubound on the number of SSE
2357 // registers used and is in the range 0 - 8 inclusive.
2359 // Count the number of XMM registers allocated.
2360 static const uint16_t XMMArgRegs[] = {
2361 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2362 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2364 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2365 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2366 && "SSE registers cannot be used when SSE is disabled");
2368 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2369 DAG.getConstant(NumXMMRegs, MVT::i8)));
2372 // For tail calls lower the arguments to the 'real' stack slot.
2374 // Force all the incoming stack arguments to be loaded from the stack
2375 // before any new outgoing arguments are stored to the stack, because the
2376 // outgoing stack slots may alias the incoming argument stack slots, and
2377 // the alias isn't otherwise explicit. This is slightly more conservative
2378 // than necessary, because it means that each store effectively depends
2379 // on every argument instead of just those arguments it would clobber.
2380 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2382 SmallVector<SDValue, 8> MemOpChains2;
2385 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2386 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2387 CCValAssign &VA = ArgLocs[i];
2390 assert(VA.isMemLoc());
2391 SDValue Arg = OutVals[i];
2392 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2393 // Create frame index.
2394 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2395 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2396 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2397 FIN = DAG.getFrameIndex(FI, getPointerTy());
2399 if (Flags.isByVal()) {
2400 // Copy relative to framepointer.
2401 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2402 if (StackPtr.getNode() == 0)
2403 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
2405 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2407 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2411 // Store relative to framepointer.
2412 MemOpChains2.push_back(
2413 DAG.getStore(ArgChain, dl, Arg, FIN,
2414 MachinePointerInfo::getFixedStack(FI),
2420 if (!MemOpChains2.empty())
2421 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2422 &MemOpChains2[0], MemOpChains2.size());
2424 // Store the return address to the appropriate stack slot.
2425 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
2429 // Build a sequence of copy-to-reg nodes chained together with token chain
2430 // and flag operands which copy the outgoing args into registers.
2432 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2433 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2434 RegsToPass[i].second, InFlag);
2435 InFlag = Chain.getValue(1);
2438 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2439 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2440 // In the 64-bit large code model, we have to make all calls
2441 // through a register, since the call instruction's 32-bit
2442 // pc-relative offset may not be large enough to hold the whole
2444 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2445 // If the callee is a GlobalAddress node (quite common, every direct call
2446 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2449 // We should use extra load for direct calls to dllimported functions in
2451 const GlobalValue *GV = G->getGlobal();
2452 if (!GV->hasDLLImportLinkage()) {
2453 unsigned char OpFlags = 0;
2454 bool ExtraLoad = false;
2455 unsigned WrapperKind = ISD::DELETED_NODE;
2457 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2458 // external symbols most go through the PLT in PIC mode. If the symbol
2459 // has hidden or protected visibility, or if it is static or local, then
2460 // we don't need to use the PLT - we can directly call it.
2461 if (Subtarget->isTargetELF() &&
2462 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2463 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2464 OpFlags = X86II::MO_PLT;
2465 } else if (Subtarget->isPICStyleStubAny() &&
2466 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2467 (!Subtarget->getTargetTriple().isMacOSX() ||
2468 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2469 // PC-relative references to external symbols should go through $stub,
2470 // unless we're building with the leopard linker or later, which
2471 // automatically synthesizes these stubs.
2472 OpFlags = X86II::MO_DARWIN_STUB;
2473 } else if (Subtarget->isPICStyleRIPRel() &&
2474 isa<Function>(GV) &&
2475 cast<Function>(GV)->hasFnAttr(Attribute::NonLazyBind)) {
2476 // If the function is marked as non-lazy, generate an indirect call
2477 // which loads from the GOT directly. This avoids runtime overhead
2478 // at the cost of eager binding (and one extra byte of encoding).
2479 OpFlags = X86II::MO_GOTPCREL;
2480 WrapperKind = X86ISD::WrapperRIP;
2484 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2485 G->getOffset(), OpFlags);
2487 // Add a wrapper if needed.
2488 if (WrapperKind != ISD::DELETED_NODE)
2489 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
2490 // Add extra indirection if needed.
2492 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
2493 MachinePointerInfo::getGOT(),
2494 false, false, false, 0);
2496 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2497 unsigned char OpFlags = 0;
2499 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2500 // external symbols should go through the PLT.
2501 if (Subtarget->isTargetELF() &&
2502 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2503 OpFlags = X86II::MO_PLT;
2504 } else if (Subtarget->isPICStyleStubAny() &&
2505 (!Subtarget->getTargetTriple().isMacOSX() ||
2506 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2507 // PC-relative references to external symbols should go through $stub,
2508 // unless we're building with the leopard linker or later, which
2509 // automatically synthesizes these stubs.
2510 OpFlags = X86II::MO_DARWIN_STUB;
2513 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2517 // Returns a chain & a flag for retval copy to use.
2518 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2519 SmallVector<SDValue, 8> Ops;
2521 if (!IsSibcall && isTailCall) {
2522 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2523 DAG.getIntPtrConstant(0, true), InFlag);
2524 InFlag = Chain.getValue(1);
2527 Ops.push_back(Chain);
2528 Ops.push_back(Callee);
2531 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2533 // Add argument registers to the end of the list so that they are known live
2535 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2536 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2537 RegsToPass[i].second.getValueType()));
2539 // Add a register mask operand representing the call-preserved registers.
2540 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2541 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
2542 assert(Mask && "Missing call preserved mask for calling convention");
2543 Ops.push_back(DAG.getRegisterMask(Mask));
2545 if (InFlag.getNode())
2546 Ops.push_back(InFlag);
2550 //// If this is the first return lowered for this function, add the regs
2551 //// to the liveout set for the function.
2552 // This isn't right, although it's probably harmless on x86; liveouts
2553 // should be computed from returns not tail calls. Consider a void
2554 // function making a tail call to a function returning int.
2555 return DAG.getNode(X86ISD::TC_RETURN, dl,
2556 NodeTys, &Ops[0], Ops.size());
2559 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2560 InFlag = Chain.getValue(1);
2562 // Create the CALLSEQ_END node.
2563 unsigned NumBytesForCalleeToPush;
2564 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2565 getTargetMachine().Options.GuaranteedTailCallOpt))
2566 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2567 else if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2568 SR == StackStructReturn)
2569 // If this is a call to a struct-return function, the callee
2570 // pops the hidden struct pointer, so we have to push it back.
2571 // This is common for Darwin/X86, Linux & Mingw32 targets.
2572 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
2573 NumBytesForCalleeToPush = 4;
2575 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2577 // Returns a flag for retval copy to use.
2579 Chain = DAG.getCALLSEQ_END(Chain,
2580 DAG.getIntPtrConstant(NumBytes, true),
2581 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2584 InFlag = Chain.getValue(1);
2587 // Handle result values, copying them out of physregs into vregs that we
2589 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2590 Ins, dl, DAG, InVals);
2594 //===----------------------------------------------------------------------===//
2595 // Fast Calling Convention (tail call) implementation
2596 //===----------------------------------------------------------------------===//
2598 // Like std call, callee cleans arguments, convention except that ECX is
2599 // reserved for storing the tail called function address. Only 2 registers are
2600 // free for argument passing (inreg). Tail call optimization is performed
2602 // * tailcallopt is enabled
2603 // * caller/callee are fastcc
2604 // On X86_64 architecture with GOT-style position independent code only local
2605 // (within module) calls are supported at the moment.
2606 // To keep the stack aligned according to platform abi the function
2607 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2608 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2609 // If a tail called function callee has more arguments than the caller the
2610 // caller needs to make sure that there is room to move the RETADDR to. This is
2611 // achieved by reserving an area the size of the argument delta right after the
2612 // original REtADDR, but before the saved framepointer or the spilled registers
2613 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2625 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2626 /// for a 16 byte align requirement.
2628 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2629 SelectionDAG& DAG) const {
2630 MachineFunction &MF = DAG.getMachineFunction();
2631 const TargetMachine &TM = MF.getTarget();
2632 const TargetFrameLowering &TFI = *TM.getFrameLowering();
2633 unsigned StackAlignment = TFI.getStackAlignment();
2634 uint64_t AlignMask = StackAlignment - 1;
2635 int64_t Offset = StackSize;
2636 uint64_t SlotSize = TD->getPointerSize();
2637 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2638 // Number smaller than 12 so just add the difference.
2639 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2641 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2642 Offset = ((~AlignMask) & Offset) + StackAlignment +
2643 (StackAlignment-SlotSize);
2648 /// MatchingStackOffset - Return true if the given stack call argument is
2649 /// already available in the same position (relatively) of the caller's
2650 /// incoming argument stack.
2652 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2653 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2654 const X86InstrInfo *TII) {
2655 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
2657 if (Arg.getOpcode() == ISD::CopyFromReg) {
2658 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2659 if (!TargetRegisterInfo::isVirtualRegister(VR))
2661 MachineInstr *Def = MRI->getVRegDef(VR);
2664 if (!Flags.isByVal()) {
2665 if (!TII->isLoadFromStackSlot(Def, FI))
2668 unsigned Opcode = Def->getOpcode();
2669 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
2670 Def->getOperand(1).isFI()) {
2671 FI = Def->getOperand(1).getIndex();
2672 Bytes = Flags.getByValSize();
2676 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2677 if (Flags.isByVal())
2678 // ByVal argument is passed in as a pointer but it's now being
2679 // dereferenced. e.g.
2680 // define @foo(%struct.X* %A) {
2681 // tail call @bar(%struct.X* byval %A)
2684 SDValue Ptr = Ld->getBasePtr();
2685 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2688 FI = FINode->getIndex();
2689 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
2690 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
2691 FI = FINode->getIndex();
2692 Bytes = Flags.getByValSize();
2696 assert(FI != INT_MAX);
2697 if (!MFI->isFixedObjectIndex(FI))
2699 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
2702 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2703 /// for tail call optimization. Targets which want to do tail call
2704 /// optimization should implement this function.
2706 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2707 CallingConv::ID CalleeCC,
2709 bool isCalleeStructRet,
2710 bool isCallerStructRet,
2711 const SmallVectorImpl<ISD::OutputArg> &Outs,
2712 const SmallVectorImpl<SDValue> &OutVals,
2713 const SmallVectorImpl<ISD::InputArg> &Ins,
2714 SelectionDAG& DAG) const {
2715 if (!IsTailCallConvention(CalleeCC) &&
2716 CalleeCC != CallingConv::C)
2719 // If -tailcallopt is specified, make fastcc functions tail-callable.
2720 const MachineFunction &MF = DAG.getMachineFunction();
2721 const Function *CallerF = DAG.getMachineFunction().getFunction();
2722 CallingConv::ID CallerCC = CallerF->getCallingConv();
2723 bool CCMatch = CallerCC == CalleeCC;
2725 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2726 if (IsTailCallConvention(CalleeCC) && CCMatch)
2731 // Look for obvious safe cases to perform tail call optimization that do not
2732 // require ABI changes. This is what gcc calls sibcall.
2734 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
2735 // emit a special epilogue.
2736 if (RegInfo->needsStackRealignment(MF))
2739 // Also avoid sibcall optimization if either caller or callee uses struct
2740 // return semantics.
2741 if (isCalleeStructRet || isCallerStructRet)
2744 // An stdcall caller is expected to clean up its arguments; the callee
2745 // isn't going to do that.
2746 if (!CCMatch && CallerCC==CallingConv::X86_StdCall)
2749 // Do not sibcall optimize vararg calls unless all arguments are passed via
2751 if (isVarArg && !Outs.empty()) {
2753 // Optimizing for varargs on Win64 is unlikely to be safe without
2754 // additional testing.
2755 if (Subtarget->isTargetWin64())
2758 SmallVector<CCValAssign, 16> ArgLocs;
2759 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2760 getTargetMachine(), ArgLocs, *DAG.getContext());
2762 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2763 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
2764 if (!ArgLocs[i].isRegLoc())
2768 // If the call result is in ST0 / ST1, it needs to be popped off the x87
2769 // stack. Therefore, if it's not used by the call it is not safe to optimize
2770 // this into a sibcall.
2771 bool Unused = false;
2772 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
2779 SmallVector<CCValAssign, 16> RVLocs;
2780 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(),
2781 getTargetMachine(), RVLocs, *DAG.getContext());
2782 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2783 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2784 CCValAssign &VA = RVLocs[i];
2785 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
2790 // If the calling conventions do not match, then we'd better make sure the
2791 // results are returned in the same way as what the caller expects.
2793 SmallVector<CCValAssign, 16> RVLocs1;
2794 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
2795 getTargetMachine(), RVLocs1, *DAG.getContext());
2796 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
2798 SmallVector<CCValAssign, 16> RVLocs2;
2799 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
2800 getTargetMachine(), RVLocs2, *DAG.getContext());
2801 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
2803 if (RVLocs1.size() != RVLocs2.size())
2805 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2806 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2808 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2810 if (RVLocs1[i].isRegLoc()) {
2811 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2814 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2820 // If the callee takes no arguments then go on to check the results of the
2822 if (!Outs.empty()) {
2823 // Check if stack adjustment is needed. For now, do not do this if any
2824 // argument is passed on the stack.
2825 SmallVector<CCValAssign, 16> ArgLocs;
2826 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2827 getTargetMachine(), ArgLocs, *DAG.getContext());
2829 // Allocate shadow area for Win64
2830 if (Subtarget->isTargetWin64()) {
2831 CCInfo.AllocateStack(32, 8);
2834 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2835 if (CCInfo.getNextStackOffset()) {
2836 MachineFunction &MF = DAG.getMachineFunction();
2837 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
2840 // Check if the arguments are already laid out in the right way as
2841 // the caller's fixed stack objects.
2842 MachineFrameInfo *MFI = MF.getFrameInfo();
2843 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2844 const X86InstrInfo *TII =
2845 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
2846 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2847 CCValAssign &VA = ArgLocs[i];
2848 SDValue Arg = OutVals[i];
2849 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2850 if (VA.getLocInfo() == CCValAssign::Indirect)
2852 if (!VA.isRegLoc()) {
2853 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2860 // If the tailcall address may be in a register, then make sure it's
2861 // possible to register allocate for it. In 32-bit, the call address can
2862 // only target EAX, EDX, or ECX since the tail call must be scheduled after
2863 // callee-saved registers are restored. These happen to be the same
2864 // registers used to pass 'inreg' arguments so watch out for those.
2865 if (!Subtarget->is64Bit() &&
2866 !isa<GlobalAddressSDNode>(Callee) &&
2867 !isa<ExternalSymbolSDNode>(Callee)) {
2868 unsigned NumInRegs = 0;
2869 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2870 CCValAssign &VA = ArgLocs[i];
2873 unsigned Reg = VA.getLocReg();
2876 case X86::EAX: case X86::EDX: case X86::ECX:
2877 if (++NumInRegs == 3)
2889 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
2890 const TargetLibraryInfo *libInfo) const {
2891 return X86::createFastISel(funcInfo, libInfo);
2895 //===----------------------------------------------------------------------===//
2896 // Other Lowering Hooks
2897 //===----------------------------------------------------------------------===//
2899 static bool MayFoldLoad(SDValue Op) {
2900 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
2903 static bool MayFoldIntoStore(SDValue Op) {
2904 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
2907 static bool isTargetShuffle(unsigned Opcode) {
2909 default: return false;
2910 case X86ISD::PSHUFD:
2911 case X86ISD::PSHUFHW:
2912 case X86ISD::PSHUFLW:
2914 case X86ISD::PALIGN:
2915 case X86ISD::MOVLHPS:
2916 case X86ISD::MOVLHPD:
2917 case X86ISD::MOVHLPS:
2918 case X86ISD::MOVLPS:
2919 case X86ISD::MOVLPD:
2920 case X86ISD::MOVSHDUP:
2921 case X86ISD::MOVSLDUP:
2922 case X86ISD::MOVDDUP:
2925 case X86ISD::UNPCKL:
2926 case X86ISD::UNPCKH:
2927 case X86ISD::VPERMILP:
2928 case X86ISD::VPERM2X128:
2929 case X86ISD::VPERMI:
2934 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2935 SDValue V1, SelectionDAG &DAG) {
2937 default: llvm_unreachable("Unknown x86 shuffle node");
2938 case X86ISD::MOVSHDUP:
2939 case X86ISD::MOVSLDUP:
2940 case X86ISD::MOVDDUP:
2941 return DAG.getNode(Opc, dl, VT, V1);
2945 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2946 SDValue V1, unsigned TargetMask,
2947 SelectionDAG &DAG) {
2949 default: llvm_unreachable("Unknown x86 shuffle node");
2950 case X86ISD::PSHUFD:
2951 case X86ISD::PSHUFHW:
2952 case X86ISD::PSHUFLW:
2953 case X86ISD::VPERMILP:
2954 case X86ISD::VPERMI:
2955 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
2959 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2960 SDValue V1, SDValue V2, unsigned TargetMask,
2961 SelectionDAG &DAG) {
2963 default: llvm_unreachable("Unknown x86 shuffle node");
2964 case X86ISD::PALIGN:
2966 case X86ISD::VPERM2X128:
2967 return DAG.getNode(Opc, dl, VT, V1, V2,
2968 DAG.getConstant(TargetMask, MVT::i8));
2972 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2973 SDValue V1, SDValue V2, SelectionDAG &DAG) {
2975 default: llvm_unreachable("Unknown x86 shuffle node");
2976 case X86ISD::MOVLHPS:
2977 case X86ISD::MOVLHPD:
2978 case X86ISD::MOVHLPS:
2979 case X86ISD::MOVLPS:
2980 case X86ISD::MOVLPD:
2983 case X86ISD::UNPCKL:
2984 case X86ISD::UNPCKH:
2985 return DAG.getNode(Opc, dl, VT, V1, V2);
2989 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
2990 MachineFunction &MF = DAG.getMachineFunction();
2991 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2992 int ReturnAddrIndex = FuncInfo->getRAIndex();
2994 if (ReturnAddrIndex == 0) {
2995 // Set up a frame object for the return address.
2996 uint64_t SlotSize = TD->getPointerSize();
2997 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
2999 FuncInfo->setRAIndex(ReturnAddrIndex);
3002 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3006 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3007 bool hasSymbolicDisplacement) {
3008 // Offset should fit into 32 bit immediate field.
3009 if (!isInt<32>(Offset))
3012 // If we don't have a symbolic displacement - we don't have any extra
3014 if (!hasSymbolicDisplacement)
3017 // FIXME: Some tweaks might be needed for medium code model.
3018 if (M != CodeModel::Small && M != CodeModel::Kernel)
3021 // For small code model we assume that latest object is 16MB before end of 31
3022 // bits boundary. We may also accept pretty large negative constants knowing
3023 // that all objects are in the positive half of address space.
3024 if (M == CodeModel::Small && Offset < 16*1024*1024)
3027 // For kernel code model we know that all object resist in the negative half
3028 // of 32bits address space. We may not accept negative offsets, since they may
3029 // be just off and we may accept pretty large positive ones.
3030 if (M == CodeModel::Kernel && Offset > 0)
3036 /// isCalleePop - Determines whether the callee is required to pop its
3037 /// own arguments. Callee pop is necessary to support tail calls.
3038 bool X86::isCalleePop(CallingConv::ID CallingConv,
3039 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3043 switch (CallingConv) {
3046 case CallingConv::X86_StdCall:
3048 case CallingConv::X86_FastCall:
3050 case CallingConv::X86_ThisCall:
3052 case CallingConv::Fast:
3054 case CallingConv::GHC:
3059 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3060 /// specific condition code, returning the condition code and the LHS/RHS of the
3061 /// comparison to make.
3062 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3063 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3065 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3066 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3067 // X > -1 -> X == 0, jump !sign.
3068 RHS = DAG.getConstant(0, RHS.getValueType());
3069 return X86::COND_NS;
3071 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3072 // X < 0 -> X == 0, jump on sign.
3075 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3077 RHS = DAG.getConstant(0, RHS.getValueType());
3078 return X86::COND_LE;
3082 switch (SetCCOpcode) {
3083 default: llvm_unreachable("Invalid integer condition!");
3084 case ISD::SETEQ: return X86::COND_E;
3085 case ISD::SETGT: return X86::COND_G;
3086 case ISD::SETGE: return X86::COND_GE;
3087 case ISD::SETLT: return X86::COND_L;
3088 case ISD::SETLE: return X86::COND_LE;
3089 case ISD::SETNE: return X86::COND_NE;
3090 case ISD::SETULT: return X86::COND_B;
3091 case ISD::SETUGT: return X86::COND_A;
3092 case ISD::SETULE: return X86::COND_BE;
3093 case ISD::SETUGE: return X86::COND_AE;
3097 // First determine if it is required or is profitable to flip the operands.
3099 // If LHS is a foldable load, but RHS is not, flip the condition.
3100 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3101 !ISD::isNON_EXTLoad(RHS.getNode())) {
3102 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3103 std::swap(LHS, RHS);
3106 switch (SetCCOpcode) {
3112 std::swap(LHS, RHS);
3116 // On a floating point condition, the flags are set as follows:
3118 // 0 | 0 | 0 | X > Y
3119 // 0 | 0 | 1 | X < Y
3120 // 1 | 0 | 0 | X == Y
3121 // 1 | 1 | 1 | unordered
3122 switch (SetCCOpcode) {
3123 default: llvm_unreachable("Condcode should be pre-legalized away");
3125 case ISD::SETEQ: return X86::COND_E;
3126 case ISD::SETOLT: // flipped
3128 case ISD::SETGT: return X86::COND_A;
3129 case ISD::SETOLE: // flipped
3131 case ISD::SETGE: return X86::COND_AE;
3132 case ISD::SETUGT: // flipped
3134 case ISD::SETLT: return X86::COND_B;
3135 case ISD::SETUGE: // flipped
3137 case ISD::SETLE: return X86::COND_BE;
3139 case ISD::SETNE: return X86::COND_NE;
3140 case ISD::SETUO: return X86::COND_P;
3141 case ISD::SETO: return X86::COND_NP;
3143 case ISD::SETUNE: return X86::COND_INVALID;
3147 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3148 /// code. Current x86 isa includes the following FP cmov instructions:
3149 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3150 static bool hasFPCMov(unsigned X86CC) {
3166 /// isFPImmLegal - Returns true if the target can instruction select the
3167 /// specified FP immediate natively. If false, the legalizer will
3168 /// materialize the FP immediate as a load from a constant pool.
3169 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3170 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3171 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3177 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3178 /// the specified range (L, H].
3179 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3180 return (Val < 0) || (Val >= Low && Val < Hi);
3183 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3184 /// specified value.
3185 static bool isUndefOrEqual(int Val, int CmpVal) {
3186 if (Val < 0 || Val == CmpVal)
3191 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3192 /// from position Pos and ending in Pos+Size, falls within the specified
3193 /// sequential range (L, L+Pos]. or is undef.
3194 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3195 unsigned Pos, unsigned Size, int Low) {
3196 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3197 if (!isUndefOrEqual(Mask[i], Low))
3202 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3203 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3204 /// the second operand.
3205 static bool isPSHUFDMask(ArrayRef<int> Mask, EVT VT) {
3206 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3207 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3208 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3209 return (Mask[0] < 2 && Mask[1] < 2);
3213 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3214 /// is suitable for input to PSHUFHW.
3215 static bool isPSHUFHWMask(ArrayRef<int> Mask, EVT VT, bool HasAVX2) {
3216 if (VT != MVT::v8i16 && (!HasAVX2 || VT != MVT::v16i16))
3219 // Lower quadword copied in order or undef.
3220 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3223 // Upper quadword shuffled.
3224 for (unsigned i = 4; i != 8; ++i)
3225 if (!isUndefOrInRange(Mask[i], 4, 8))
3228 if (VT == MVT::v16i16) {
3229 // Lower quadword copied in order or undef.
3230 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3233 // Upper quadword shuffled.
3234 for (unsigned i = 12; i != 16; ++i)
3235 if (!isUndefOrInRange(Mask[i], 12, 16))
3242 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3243 /// is suitable for input to PSHUFLW.
3244 static bool isPSHUFLWMask(ArrayRef<int> Mask, EVT VT, bool HasAVX2) {
3245 if (VT != MVT::v8i16 && (!HasAVX2 || VT != MVT::v16i16))
3248 // Upper quadword copied in order.
3249 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3252 // Lower quadword shuffled.
3253 for (unsigned i = 0; i != 4; ++i)
3254 if (!isUndefOrInRange(Mask[i], 0, 4))
3257 if (VT == MVT::v16i16) {
3258 // Upper quadword copied in order.
3259 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3262 // Lower quadword shuffled.
3263 for (unsigned i = 8; i != 12; ++i)
3264 if (!isUndefOrInRange(Mask[i], 8, 12))
3271 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
3272 /// is suitable for input to PALIGNR.
3273 static bool isPALIGNRMask(ArrayRef<int> Mask, EVT VT,
3274 const X86Subtarget *Subtarget) {
3275 if ((VT.getSizeInBits() == 128 && !Subtarget->hasSSSE3()) ||
3276 (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2()))
3279 unsigned NumElts = VT.getVectorNumElements();
3280 unsigned NumLanes = VT.getSizeInBits()/128;
3281 unsigned NumLaneElts = NumElts/NumLanes;
3283 // Do not handle 64-bit element shuffles with palignr.
3284 if (NumLaneElts == 2)
3287 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3289 for (i = 0; i != NumLaneElts; ++i) {
3294 // Lane is all undef, go to next lane
3295 if (i == NumLaneElts)
3298 int Start = Mask[i+l];
3300 // Make sure its in this lane in one of the sources
3301 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3302 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3305 // If not lane 0, then we must match lane 0
3306 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3309 // Correct second source to be contiguous with first source
3310 if (Start >= (int)NumElts)
3311 Start -= NumElts - NumLaneElts;
3313 // Make sure we're shifting in the right direction.
3314 if (Start <= (int)(i+l))
3319 // Check the rest of the elements to see if they are consecutive.
3320 for (++i; i != NumLaneElts; ++i) {
3321 int Idx = Mask[i+l];
3323 // Make sure its in this lane
3324 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3325 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3328 // If not lane 0, then we must match lane 0
3329 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3332 if (Idx >= (int)NumElts)
3333 Idx -= NumElts - NumLaneElts;
3335 if (!isUndefOrEqual(Idx, Start+i))
3344 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3345 /// the two vector operands have swapped position.
3346 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
3347 unsigned NumElems) {
3348 for (unsigned i = 0; i != NumElems; ++i) {
3352 else if (idx < (int)NumElems)
3353 Mask[i] = idx + NumElems;
3355 Mask[i] = idx - NumElems;
3359 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
3360 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
3361 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
3362 /// reverse of what x86 shuffles want.
3363 static bool isSHUFPMask(ArrayRef<int> Mask, EVT VT, bool HasAVX,
3364 bool Commuted = false) {
3365 if (!HasAVX && VT.getSizeInBits() == 256)
3368 unsigned NumElems = VT.getVectorNumElements();
3369 unsigned NumLanes = VT.getSizeInBits()/128;
3370 unsigned NumLaneElems = NumElems/NumLanes;
3372 if (NumLaneElems != 2 && NumLaneElems != 4)
3375 // VSHUFPSY divides the resulting vector into 4 chunks.
3376 // The sources are also splitted into 4 chunks, and each destination
3377 // chunk must come from a different source chunk.
3379 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
3380 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
3382 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
3383 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
3385 // VSHUFPDY divides the resulting vector into 4 chunks.
3386 // The sources are also splitted into 4 chunks, and each destination
3387 // chunk must come from a different source chunk.
3389 // SRC1 => X3 X2 X1 X0
3390 // SRC2 => Y3 Y2 Y1 Y0
3392 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
3394 unsigned HalfLaneElems = NumLaneElems/2;
3395 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
3396 for (unsigned i = 0; i != NumLaneElems; ++i) {
3397 int Idx = Mask[i+l];
3398 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
3399 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
3401 // For VSHUFPSY, the mask of the second half must be the same as the
3402 // first but with the appropriate offsets. This works in the same way as
3403 // VPERMILPS works with masks.
3404 if (NumElems != 8 || l == 0 || Mask[i] < 0)
3406 if (!isUndefOrEqual(Idx, Mask[i]+l))
3414 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3415 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3416 static bool isMOVHLPSMask(ArrayRef<int> Mask, EVT VT) {
3417 if (!VT.is128BitVector())
3420 unsigned NumElems = VT.getVectorNumElements();
3425 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3426 return isUndefOrEqual(Mask[0], 6) &&
3427 isUndefOrEqual(Mask[1], 7) &&
3428 isUndefOrEqual(Mask[2], 2) &&
3429 isUndefOrEqual(Mask[3], 3);
3432 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3433 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3435 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, EVT VT) {
3436 if (!VT.is128BitVector())
3439 unsigned NumElems = VT.getVectorNumElements();
3444 return isUndefOrEqual(Mask[0], 2) &&
3445 isUndefOrEqual(Mask[1], 3) &&
3446 isUndefOrEqual(Mask[2], 2) &&
3447 isUndefOrEqual(Mask[3], 3);
3450 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3451 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3452 static bool isMOVLPMask(ArrayRef<int> Mask, EVT VT) {
3453 if (!VT.is128BitVector())
3456 unsigned NumElems = VT.getVectorNumElements();
3458 if (NumElems != 2 && NumElems != 4)
3461 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3462 if (!isUndefOrEqual(Mask[i], i + NumElems))
3465 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
3466 if (!isUndefOrEqual(Mask[i], i))
3472 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3473 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3474 static bool isMOVLHPSMask(ArrayRef<int> Mask, EVT VT) {
3475 if (!VT.is128BitVector())
3478 unsigned NumElems = VT.getVectorNumElements();
3480 if (NumElems != 2 && NumElems != 4)
3483 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3484 if (!isUndefOrEqual(Mask[i], i))
3487 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3488 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
3495 // Some special combinations that can be optimized.
3498 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
3499 SelectionDAG &DAG) {
3500 EVT VT = SVOp->getValueType(0);
3501 DebugLoc dl = SVOp->getDebugLoc();
3503 if (VT != MVT::v8i32 && VT != MVT::v8f32)
3506 ArrayRef<int> Mask = SVOp->getMask();
3508 // These are the special masks that may be optimized.
3509 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
3510 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
3511 bool MatchEvenMask = true;
3512 bool MatchOddMask = true;
3513 for (int i=0; i<8; ++i) {
3514 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
3515 MatchEvenMask = false;
3516 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
3517 MatchOddMask = false;
3519 static const int CompactionMaskEven[] = {0, 2, -1, -1, 4, 6, -1, -1};
3520 static const int CompactionMaskOdd [] = {1, 3, -1, -1, 5, 7, -1, -1};
3522 const int *CompactionMask;
3524 CompactionMask = CompactionMaskEven;
3525 else if (MatchOddMask)
3526 CompactionMask = CompactionMaskOdd;
3530 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
3532 SDValue Op0 = DAG.getVectorShuffle(VT, dl, SVOp->getOperand(0),
3533 UndefNode, CompactionMask);
3534 SDValue Op1 = DAG.getVectorShuffle(VT, dl, SVOp->getOperand(1),
3535 UndefNode, CompactionMask);
3536 static const int UnpackMask[] = {0, 8, 1, 9, 4, 12, 5, 13};
3537 return DAG.getVectorShuffle(VT, dl, Op0, Op1, UnpackMask);
3540 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
3541 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
3542 static bool isUNPCKLMask(ArrayRef<int> Mask, EVT VT,
3543 bool HasAVX2, bool V2IsSplat = false) {
3544 unsigned NumElts = VT.getVectorNumElements();
3546 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3547 "Unsupported vector type for unpckh");
3549 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3550 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3553 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3554 // independently on 128-bit lanes.
3555 unsigned NumLanes = VT.getSizeInBits()/128;
3556 unsigned NumLaneElts = NumElts/NumLanes;
3558 for (unsigned l = 0; l != NumLanes; ++l) {
3559 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts;
3560 i != (l+1)*NumLaneElts;
3563 int BitI1 = Mask[i+1];
3564 if (!isUndefOrEqual(BitI, j))
3567 if (!isUndefOrEqual(BitI1, NumElts))
3570 if (!isUndefOrEqual(BitI1, j + NumElts))
3579 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
3580 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
3581 static bool isUNPCKHMask(ArrayRef<int> Mask, EVT VT,
3582 bool HasAVX2, bool V2IsSplat = false) {
3583 unsigned NumElts = VT.getVectorNumElements();
3585 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3586 "Unsupported vector type for unpckh");
3588 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3589 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3592 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3593 // independently on 128-bit lanes.
3594 unsigned NumLanes = VT.getSizeInBits()/128;
3595 unsigned NumLaneElts = NumElts/NumLanes;
3597 for (unsigned l = 0; l != NumLanes; ++l) {
3598 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2;
3599 i != (l+1)*NumLaneElts; i += 2, ++j) {
3601 int BitI1 = Mask[i+1];
3602 if (!isUndefOrEqual(BitI, j))
3605 if (isUndefOrEqual(BitI1, NumElts))
3608 if (!isUndefOrEqual(BitI1, j+NumElts))
3616 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
3617 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
3619 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, EVT VT,
3621 unsigned NumElts = VT.getVectorNumElements();
3623 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3624 "Unsupported vector type for unpckh");
3626 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3627 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3630 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
3631 // FIXME: Need a better way to get rid of this, there's no latency difference
3632 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
3633 // the former later. We should also remove the "_undef" special mask.
3634 if (NumElts == 4 && VT.getSizeInBits() == 256)
3637 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3638 // independently on 128-bit lanes.
3639 unsigned NumLanes = VT.getSizeInBits()/128;
3640 unsigned NumLaneElts = NumElts/NumLanes;
3642 for (unsigned l = 0; l != NumLanes; ++l) {
3643 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts;
3644 i != (l+1)*NumLaneElts;
3647 int BitI1 = Mask[i+1];
3649 if (!isUndefOrEqual(BitI, j))
3651 if (!isUndefOrEqual(BitI1, j))
3659 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
3660 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
3662 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, EVT VT, bool HasAVX2) {
3663 unsigned NumElts = VT.getVectorNumElements();
3665 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3666 "Unsupported vector type for unpckh");
3668 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3669 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3672 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3673 // independently on 128-bit lanes.
3674 unsigned NumLanes = VT.getSizeInBits()/128;
3675 unsigned NumLaneElts = NumElts/NumLanes;
3677 for (unsigned l = 0; l != NumLanes; ++l) {
3678 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2;
3679 i != (l+1)*NumLaneElts; i += 2, ++j) {
3681 int BitI1 = Mask[i+1];
3682 if (!isUndefOrEqual(BitI, j))
3684 if (!isUndefOrEqual(BitI1, j))
3691 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
3692 /// specifies a shuffle of elements that is suitable for input to MOVSS,
3693 /// MOVSD, and MOVD, i.e. setting the lowest element.
3694 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
3695 if (VT.getVectorElementType().getSizeInBits() < 32)
3697 if (!VT.is128BitVector())
3700 unsigned NumElts = VT.getVectorNumElements();
3702 if (!isUndefOrEqual(Mask[0], NumElts))
3705 for (unsigned i = 1; i != NumElts; ++i)
3706 if (!isUndefOrEqual(Mask[i], i))
3712 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
3713 /// as permutations between 128-bit chunks or halves. As an example: this
3715 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
3716 /// The first half comes from the second half of V1 and the second half from the
3717 /// the second half of V2.
3718 static bool isVPERM2X128Mask(ArrayRef<int> Mask, EVT VT, bool HasAVX) {
3719 if (!HasAVX || !VT.is256BitVector())
3722 // The shuffle result is divided into half A and half B. In total the two
3723 // sources have 4 halves, namely: C, D, E, F. The final values of A and
3724 // B must come from C, D, E or F.
3725 unsigned HalfSize = VT.getVectorNumElements()/2;
3726 bool MatchA = false, MatchB = false;
3728 // Check if A comes from one of C, D, E, F.
3729 for (unsigned Half = 0; Half != 4; ++Half) {
3730 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
3736 // Check if B comes from one of C, D, E, F.
3737 for (unsigned Half = 0; Half != 4; ++Half) {
3738 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
3744 return MatchA && MatchB;
3747 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
3748 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
3749 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
3750 EVT VT = SVOp->getValueType(0);
3752 unsigned HalfSize = VT.getVectorNumElements()/2;
3754 unsigned FstHalf = 0, SndHalf = 0;
3755 for (unsigned i = 0; i < HalfSize; ++i) {
3756 if (SVOp->getMaskElt(i) > 0) {
3757 FstHalf = SVOp->getMaskElt(i)/HalfSize;
3761 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
3762 if (SVOp->getMaskElt(i) > 0) {
3763 SndHalf = SVOp->getMaskElt(i)/HalfSize;
3768 return (FstHalf | (SndHalf << 4));
3771 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
3772 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
3773 /// Note that VPERMIL mask matching is different depending whether theunderlying
3774 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
3775 /// to the same elements of the low, but to the higher half of the source.
3776 /// In VPERMILPD the two lanes could be shuffled independently of each other
3777 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
3778 static bool isVPERMILPMask(ArrayRef<int> Mask, EVT VT, bool HasAVX) {
3782 unsigned NumElts = VT.getVectorNumElements();
3783 // Only match 256-bit with 32/64-bit types
3784 if (VT.getSizeInBits() != 256 || (NumElts != 4 && NumElts != 8))
3787 unsigned NumLanes = VT.getSizeInBits()/128;
3788 unsigned LaneSize = NumElts/NumLanes;
3789 for (unsigned l = 0; l != NumElts; l += LaneSize) {
3790 for (unsigned i = 0; i != LaneSize; ++i) {
3791 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
3793 if (NumElts != 8 || l == 0)
3795 // VPERMILPS handling
3798 if (!isUndefOrEqual(Mask[i+l], Mask[i]+l))
3806 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
3807 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
3808 /// element of vector 2 and the other elements to come from vector 1 in order.
3809 static bool isCommutedMOVLMask(ArrayRef<int> Mask, EVT VT,
3810 bool V2IsSplat = false, bool V2IsUndef = false) {
3811 if (!VT.is128BitVector())
3814 unsigned NumOps = VT.getVectorNumElements();
3815 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
3818 if (!isUndefOrEqual(Mask[0], 0))
3821 for (unsigned i = 1; i != NumOps; ++i)
3822 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
3823 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
3824 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
3830 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3831 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
3832 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
3833 static bool isMOVSHDUPMask(ArrayRef<int> Mask, EVT VT,
3834 const X86Subtarget *Subtarget) {
3835 if (!Subtarget->hasSSE3())
3838 unsigned NumElems = VT.getVectorNumElements();
3840 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3841 (VT.getSizeInBits() == 256 && NumElems != 8))
3844 // "i+1" is the value the indexed mask element must have
3845 for (unsigned i = 0; i != NumElems; i += 2)
3846 if (!isUndefOrEqual(Mask[i], i+1) ||
3847 !isUndefOrEqual(Mask[i+1], i+1))
3853 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3854 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
3855 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
3856 static bool isMOVSLDUPMask(ArrayRef<int> Mask, EVT VT,
3857 const X86Subtarget *Subtarget) {
3858 if (!Subtarget->hasSSE3())
3861 unsigned NumElems = VT.getVectorNumElements();
3863 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3864 (VT.getSizeInBits() == 256 && NumElems != 8))
3867 // "i" is the value the indexed mask element must have
3868 for (unsigned i = 0; i != NumElems; i += 2)
3869 if (!isUndefOrEqual(Mask[i], i) ||
3870 !isUndefOrEqual(Mask[i+1], i))
3876 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
3877 /// specifies a shuffle of elements that is suitable for input to 256-bit
3878 /// version of MOVDDUP.
3879 static bool isMOVDDUPYMask(ArrayRef<int> Mask, EVT VT, bool HasAVX) {
3880 if (!HasAVX || !VT.is256BitVector())
3883 unsigned NumElts = VT.getVectorNumElements();
3887 for (unsigned i = 0; i != NumElts/2; ++i)
3888 if (!isUndefOrEqual(Mask[i], 0))
3890 for (unsigned i = NumElts/2; i != NumElts; ++i)
3891 if (!isUndefOrEqual(Mask[i], NumElts/2))
3896 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3897 /// specifies a shuffle of elements that is suitable for input to 128-bit
3898 /// version of MOVDDUP.
3899 static bool isMOVDDUPMask(ArrayRef<int> Mask, EVT VT) {
3900 if (!VT.is128BitVector())
3903 unsigned e = VT.getVectorNumElements() / 2;
3904 for (unsigned i = 0; i != e; ++i)
3905 if (!isUndefOrEqual(Mask[i], i))
3907 for (unsigned i = 0; i != e; ++i)
3908 if (!isUndefOrEqual(Mask[e+i], i))
3913 /// isVEXTRACTF128Index - Return true if the specified
3914 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
3915 /// suitable for input to VEXTRACTF128.
3916 bool X86::isVEXTRACTF128Index(SDNode *N) {
3917 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3920 // The index should be aligned on a 128-bit boundary.
3922 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3924 unsigned VL = N->getValueType(0).getVectorNumElements();
3925 unsigned VBits = N->getValueType(0).getSizeInBits();
3926 unsigned ElSize = VBits / VL;
3927 bool Result = (Index * ElSize) % 128 == 0;
3932 /// isVINSERTF128Index - Return true if the specified INSERT_SUBVECTOR
3933 /// operand specifies a subvector insert that is suitable for input to
3935 bool X86::isVINSERTF128Index(SDNode *N) {
3936 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3939 // The index should be aligned on a 128-bit boundary.
3941 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3943 unsigned VL = N->getValueType(0).getVectorNumElements();
3944 unsigned VBits = N->getValueType(0).getSizeInBits();
3945 unsigned ElSize = VBits / VL;
3946 bool Result = (Index * ElSize) % 128 == 0;
3951 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
3952 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
3953 /// Handles 128-bit and 256-bit.
3954 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
3955 EVT VT = N->getValueType(0);
3957 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3958 "Unsupported vector type for PSHUF/SHUFP");
3960 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
3961 // independently on 128-bit lanes.
3962 unsigned NumElts = VT.getVectorNumElements();
3963 unsigned NumLanes = VT.getSizeInBits()/128;
3964 unsigned NumLaneElts = NumElts/NumLanes;
3966 assert((NumLaneElts == 2 || NumLaneElts == 4) &&
3967 "Only supports 2 or 4 elements per lane");
3969 unsigned Shift = (NumLaneElts == 4) ? 1 : 0;
3971 for (unsigned i = 0; i != NumElts; ++i) {
3972 int Elt = N->getMaskElt(i);
3973 if (Elt < 0) continue;
3974 Elt &= NumLaneElts - 1;
3975 unsigned ShAmt = (i << Shift) % 8;
3976 Mask |= Elt << ShAmt;
3982 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
3983 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
3984 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
3985 EVT VT = N->getValueType(0);
3987 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
3988 "Unsupported vector type for PSHUFHW");
3990 unsigned NumElts = VT.getVectorNumElements();
3993 for (unsigned l = 0; l != NumElts; l += 8) {
3994 // 8 nodes per lane, but we only care about the last 4.
3995 for (unsigned i = 0; i < 4; ++i) {
3996 int Elt = N->getMaskElt(l+i+4);
3997 if (Elt < 0) continue;
3998 Elt &= 0x3; // only 2-bits.
3999 Mask |= Elt << (i * 2);
4006 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4007 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4008 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4009 EVT VT = N->getValueType(0);
4011 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4012 "Unsupported vector type for PSHUFHW");
4014 unsigned NumElts = VT.getVectorNumElements();
4017 for (unsigned l = 0; l != NumElts; l += 8) {
4018 // 8 nodes per lane, but we only care about the first 4.
4019 for (unsigned i = 0; i < 4; ++i) {
4020 int Elt = N->getMaskElt(l+i);
4021 if (Elt < 0) continue;
4022 Elt &= 0x3; // only 2-bits
4023 Mask |= Elt << (i * 2);
4030 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
4031 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
4032 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4033 EVT VT = SVOp->getValueType(0);
4034 unsigned EltSize = VT.getVectorElementType().getSizeInBits() >> 3;
4036 unsigned NumElts = VT.getVectorNumElements();
4037 unsigned NumLanes = VT.getSizeInBits()/128;
4038 unsigned NumLaneElts = NumElts/NumLanes;
4042 for (i = 0; i != NumElts; ++i) {
4043 Val = SVOp->getMaskElt(i);
4047 if (Val >= (int)NumElts)
4048 Val -= NumElts - NumLaneElts;
4050 assert(Val - i > 0 && "PALIGNR imm should be positive");
4051 return (Val - i) * EltSize;
4054 /// getExtractVEXTRACTF128Immediate - Return the appropriate immediate
4055 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4057 unsigned X86::getExtractVEXTRACTF128Immediate(SDNode *N) {
4058 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4059 llvm_unreachable("Illegal extract subvector for VEXTRACTF128");
4062 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4064 EVT VecVT = N->getOperand(0).getValueType();
4065 EVT ElVT = VecVT.getVectorElementType();
4067 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
4068 return Index / NumElemsPerChunk;
4071 /// getInsertVINSERTF128Immediate - Return the appropriate immediate
4072 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4074 unsigned X86::getInsertVINSERTF128Immediate(SDNode *N) {
4075 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4076 llvm_unreachable("Illegal insert subvector for VINSERTF128");
4079 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4081 EVT VecVT = N->getValueType(0);
4082 EVT ElVT = VecVT.getVectorElementType();
4084 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
4085 return Index / NumElemsPerChunk;
4088 /// getShuffleCLImmediate - Return the appropriate immediate to shuffle
4089 /// the specified VECTOR_SHUFFLE mask with VPERMQ and VPERMPD instructions.
4090 /// Handles 256-bit.
4091 static unsigned getShuffleCLImmediate(ShuffleVectorSDNode *N) {
4092 EVT VT = N->getValueType(0);
4094 unsigned NumElts = VT.getVectorNumElements();
4096 assert((VT.is256BitVector() && NumElts == 4) &&
4097 "Unsupported vector type for VPERMQ/VPERMPD");
4100 for (unsigned i = 0; i != NumElts; ++i) {
4101 int Elt = N->getMaskElt(i);
4104 Mask |= Elt << (i*2);
4109 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4111 bool X86::isZeroNode(SDValue Elt) {
4112 return ((isa<ConstantSDNode>(Elt) &&
4113 cast<ConstantSDNode>(Elt)->isNullValue()) ||
4114 (isa<ConstantFPSDNode>(Elt) &&
4115 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
4118 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
4119 /// their permute mask.
4120 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
4121 SelectionDAG &DAG) {
4122 EVT VT = SVOp->getValueType(0);
4123 unsigned NumElems = VT.getVectorNumElements();
4124 SmallVector<int, 8> MaskVec;
4126 for (unsigned i = 0; i != NumElems; ++i) {
4127 int Idx = SVOp->getMaskElt(i);
4129 if (Idx < (int)NumElems)
4134 MaskVec.push_back(Idx);
4136 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
4137 SVOp->getOperand(0), &MaskVec[0]);
4140 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4141 /// match movhlps. The lower half elements should come from upper half of
4142 /// V1 (and in order), and the upper half elements should come from the upper
4143 /// half of V2 (and in order).
4144 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, EVT VT) {
4145 if (!VT.is128BitVector())
4147 if (VT.getVectorNumElements() != 4)
4149 for (unsigned i = 0, e = 2; i != e; ++i)
4150 if (!isUndefOrEqual(Mask[i], i+2))
4152 for (unsigned i = 2; i != 4; ++i)
4153 if (!isUndefOrEqual(Mask[i], i+4))
4158 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4159 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4161 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
4162 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4164 N = N->getOperand(0).getNode();
4165 if (!ISD::isNON_EXTLoad(N))
4168 *LD = cast<LoadSDNode>(N);
4172 // Test whether the given value is a vector value which will be legalized
4174 static bool WillBeConstantPoolLoad(SDNode *N) {
4175 if (N->getOpcode() != ISD::BUILD_VECTOR)
4178 // Check for any non-constant elements.
4179 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4180 switch (N->getOperand(i).getNode()->getOpcode()) {
4182 case ISD::ConstantFP:
4189 // Vectors of all-zeros and all-ones are materialized with special
4190 // instructions rather than being loaded.
4191 return !ISD::isBuildVectorAllZeros(N) &&
4192 !ISD::isBuildVectorAllOnes(N);
4195 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4196 /// match movlp{s|d}. The lower half elements should come from lower half of
4197 /// V1 (and in order), and the upper half elements should come from the upper
4198 /// half of V2 (and in order). And since V1 will become the source of the
4199 /// MOVLP, it must be either a vector load or a scalar load to vector.
4200 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
4201 ArrayRef<int> Mask, EVT VT) {
4202 if (!VT.is128BitVector())
4205 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
4207 // Is V2 is a vector load, don't do this transformation. We will try to use
4208 // load folding shufps op.
4209 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
4212 unsigned NumElems = VT.getVectorNumElements();
4214 if (NumElems != 2 && NumElems != 4)
4216 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4217 if (!isUndefOrEqual(Mask[i], i))
4219 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4220 if (!isUndefOrEqual(Mask[i], i+NumElems))
4225 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
4227 static bool isSplatVector(SDNode *N) {
4228 if (N->getOpcode() != ISD::BUILD_VECTOR)
4231 SDValue SplatValue = N->getOperand(0);
4232 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
4233 if (N->getOperand(i) != SplatValue)
4238 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
4239 /// to an zero vector.
4240 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
4241 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
4242 SDValue V1 = N->getOperand(0);
4243 SDValue V2 = N->getOperand(1);
4244 unsigned NumElems = N->getValueType(0).getVectorNumElements();
4245 for (unsigned i = 0; i != NumElems; ++i) {
4246 int Idx = N->getMaskElt(i);
4247 if (Idx >= (int)NumElems) {
4248 unsigned Opc = V2.getOpcode();
4249 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4251 if (Opc != ISD::BUILD_VECTOR ||
4252 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
4254 } else if (Idx >= 0) {
4255 unsigned Opc = V1.getOpcode();
4256 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
4258 if (Opc != ISD::BUILD_VECTOR ||
4259 !X86::isZeroNode(V1.getOperand(Idx)))
4266 /// getZeroVector - Returns a vector of specified type with all zero elements.
4268 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4269 SelectionDAG &DAG, DebugLoc dl) {
4270 assert(VT.isVector() && "Expected a vector type");
4271 unsigned Size = VT.getSizeInBits();
4273 // Always build SSE zero vectors as <4 x i32> bitcasted
4274 // to their dest type. This ensures they get CSE'd.
4276 if (Size == 128) { // SSE
4277 if (Subtarget->hasSSE2()) { // SSE2
4278 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4279 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4281 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4282 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4284 } else if (Size == 256) { // AVX
4285 if (Subtarget->hasAVX2()) { // AVX2
4286 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4287 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4288 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8);
4290 // 256-bit logic and arithmetic instructions in AVX are all
4291 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4292 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4293 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4294 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8);
4297 llvm_unreachable("Unexpected vector type");
4299 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4302 /// getOnesVector - Returns a vector of specified type with all bits set.
4303 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4304 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4305 /// Then bitcast to their original type, ensuring they get CSE'd.
4306 static SDValue getOnesVector(EVT VT, bool HasAVX2, SelectionDAG &DAG,
4308 assert(VT.isVector() && "Expected a vector type");
4309 unsigned Size = VT.getSizeInBits();
4311 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
4314 if (HasAVX2) { // AVX2
4315 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4316 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8);
4318 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4319 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4321 } else if (Size == 128) {
4322 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4324 llvm_unreachable("Unexpected vector type");
4326 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4329 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
4330 /// that point to V2 points to its first element.
4331 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
4332 for (unsigned i = 0; i != NumElems; ++i) {
4333 if (Mask[i] > (int)NumElems) {
4339 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4340 /// operation of specified width.
4341 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4343 unsigned NumElems = VT.getVectorNumElements();
4344 SmallVector<int, 8> Mask;
4345 Mask.push_back(NumElems);
4346 for (unsigned i = 1; i != NumElems; ++i)
4348 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4351 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4352 static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4354 unsigned NumElems = VT.getVectorNumElements();
4355 SmallVector<int, 8> Mask;
4356 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4358 Mask.push_back(i + NumElems);
4360 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4363 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4364 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4366 unsigned NumElems = VT.getVectorNumElements();
4367 SmallVector<int, 8> Mask;
4368 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4369 Mask.push_back(i + Half);
4370 Mask.push_back(i + NumElems + Half);
4372 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4375 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
4376 // a generic shuffle instruction because the target has no such instructions.
4377 // Generate shuffles which repeat i16 and i8 several times until they can be
4378 // represented by v4f32 and then be manipulated by target suported shuffles.
4379 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
4380 EVT VT = V.getValueType();
4381 int NumElems = VT.getVectorNumElements();
4382 DebugLoc dl = V.getDebugLoc();
4384 while (NumElems > 4) {
4385 if (EltNo < NumElems/2) {
4386 V = getUnpackl(DAG, dl, VT, V, V);
4388 V = getUnpackh(DAG, dl, VT, V, V);
4389 EltNo -= NumElems/2;
4396 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
4397 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
4398 EVT VT = V.getValueType();
4399 DebugLoc dl = V.getDebugLoc();
4400 unsigned Size = VT.getSizeInBits();
4403 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
4404 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
4405 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
4407 } else if (Size == 256) {
4408 // To use VPERMILPS to splat scalars, the second half of indicies must
4409 // refer to the higher part, which is a duplication of the lower one,
4410 // because VPERMILPS can only handle in-lane permutations.
4411 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
4412 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
4414 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
4415 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
4418 llvm_unreachable("Vector size not supported");
4420 return DAG.getNode(ISD::BITCAST, dl, VT, V);
4423 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
4424 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
4425 EVT SrcVT = SV->getValueType(0);
4426 SDValue V1 = SV->getOperand(0);
4427 DebugLoc dl = SV->getDebugLoc();
4429 int EltNo = SV->getSplatIndex();
4430 int NumElems = SrcVT.getVectorNumElements();
4431 unsigned Size = SrcVT.getSizeInBits();
4433 assert(((Size == 128 && NumElems > 4) || Size == 256) &&
4434 "Unknown how to promote splat for type");
4436 // Extract the 128-bit part containing the splat element and update
4437 // the splat element index when it refers to the higher register.
4439 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
4440 if (EltNo >= NumElems/2)
4441 EltNo -= NumElems/2;
4444 // All i16 and i8 vector types can't be used directly by a generic shuffle
4445 // instruction because the target has no such instruction. Generate shuffles
4446 // which repeat i16 and i8 several times until they fit in i32, and then can
4447 // be manipulated by target suported shuffles.
4448 EVT EltVT = SrcVT.getVectorElementType();
4449 if (EltVT == MVT::i8 || EltVT == MVT::i16)
4450 V1 = PromoteSplati8i16(V1, DAG, EltNo);
4452 // Recreate the 256-bit vector and place the same 128-bit vector
4453 // into the low and high part. This is necessary because we want
4454 // to use VPERM* to shuffle the vectors
4456 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
4459 return getLegalSplat(DAG, V1, EltNo);
4462 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4463 /// vector of zero or undef vector. This produces a shuffle where the low
4464 /// element of V2 is swizzled into the zero/undef vector, landing at element
4465 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4466 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4468 const X86Subtarget *Subtarget,
4469 SelectionDAG &DAG) {
4470 EVT VT = V2.getValueType();
4472 ? getZeroVector(VT, Subtarget, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT);
4473 unsigned NumElems = VT.getVectorNumElements();
4474 SmallVector<int, 16> MaskVec;
4475 for (unsigned i = 0; i != NumElems; ++i)
4476 // If this is the insertion idx, put the low elt of V2 here.
4477 MaskVec.push_back(i == Idx ? NumElems : i);
4478 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
4481 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
4482 /// target specific opcode. Returns true if the Mask could be calculated.
4483 /// Sets IsUnary to true if only uses one source.
4484 static bool getTargetShuffleMask(SDNode *N, MVT VT,
4485 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4486 unsigned NumElems = VT.getVectorNumElements();
4490 switch(N->getOpcode()) {
4492 ImmN = N->getOperand(N->getNumOperands()-1);
4493 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4495 case X86ISD::UNPCKH:
4496 DecodeUNPCKHMask(VT, Mask);
4498 case X86ISD::UNPCKL:
4499 DecodeUNPCKLMask(VT, Mask);
4501 case X86ISD::MOVHLPS:
4502 DecodeMOVHLPSMask(NumElems, Mask);
4504 case X86ISD::MOVLHPS:
4505 DecodeMOVLHPSMask(NumElems, Mask);
4507 case X86ISD::PSHUFD:
4508 case X86ISD::VPERMILP:
4509 ImmN = N->getOperand(N->getNumOperands()-1);
4510 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4513 case X86ISD::PSHUFHW:
4514 ImmN = N->getOperand(N->getNumOperands()-1);
4515 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4518 case X86ISD::PSHUFLW:
4519 ImmN = N->getOperand(N->getNumOperands()-1);
4520 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4523 case X86ISD::VPERMI:
4524 ImmN = N->getOperand(N->getNumOperands()-1);
4525 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4529 case X86ISD::MOVSD: {
4530 // The index 0 always comes from the first element of the second source,
4531 // this is why MOVSS and MOVSD are used in the first place. The other
4532 // elements come from the other positions of the first source vector
4533 Mask.push_back(NumElems);
4534 for (unsigned i = 1; i != NumElems; ++i) {
4539 case X86ISD::VPERM2X128:
4540 ImmN = N->getOperand(N->getNumOperands()-1);
4541 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4542 if (Mask.empty()) return false;
4544 case X86ISD::MOVDDUP:
4545 case X86ISD::MOVLHPD:
4546 case X86ISD::MOVLPD:
4547 case X86ISD::MOVLPS:
4548 case X86ISD::MOVSHDUP:
4549 case X86ISD::MOVSLDUP:
4550 case X86ISD::PALIGN:
4551 // Not yet implemented
4553 default: llvm_unreachable("unknown target shuffle node");
4559 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4560 /// element of the result of the vector shuffle.
4561 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
4564 return SDValue(); // Limit search depth.
4566 SDValue V = SDValue(N, 0);
4567 EVT VT = V.getValueType();
4568 unsigned Opcode = V.getOpcode();
4570 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4571 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4572 int Elt = SV->getMaskElt(Index);
4575 return DAG.getUNDEF(VT.getVectorElementType());
4577 unsigned NumElems = VT.getVectorNumElements();
4578 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
4579 : SV->getOperand(1);
4580 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
4583 // Recurse into target specific vector shuffles to find scalars.
4584 if (isTargetShuffle(Opcode)) {
4585 MVT ShufVT = V.getValueType().getSimpleVT();
4586 unsigned NumElems = ShufVT.getVectorNumElements();
4587 SmallVector<int, 16> ShuffleMask;
4591 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
4594 int Elt = ShuffleMask[Index];
4596 return DAG.getUNDEF(ShufVT.getVectorElementType());
4598 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
4600 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
4604 // Actual nodes that may contain scalar elements
4605 if (Opcode == ISD::BITCAST) {
4606 V = V.getOperand(0);
4607 EVT SrcVT = V.getValueType();
4608 unsigned NumElems = VT.getVectorNumElements();
4610 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4614 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4615 return (Index == 0) ? V.getOperand(0)
4616 : DAG.getUNDEF(VT.getVectorElementType());
4618 if (V.getOpcode() == ISD::BUILD_VECTOR)
4619 return V.getOperand(Index);
4624 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
4625 /// shuffle operation which come from a consecutively from a zero. The
4626 /// search can start in two different directions, from left or right.
4628 unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp, unsigned NumElems,
4629 bool ZerosFromLeft, SelectionDAG &DAG) {
4631 for (i = 0; i != NumElems; ++i) {
4632 unsigned Index = ZerosFromLeft ? i : NumElems-i-1;
4633 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
4634 if (!(Elt.getNode() &&
4635 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt))))
4642 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
4643 /// correspond consecutively to elements from one of the vector operands,
4644 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
4646 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
4647 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
4648 unsigned NumElems, unsigned &OpNum) {
4649 bool SeenV1 = false;
4650 bool SeenV2 = false;
4652 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
4653 int Idx = SVOp->getMaskElt(i);
4654 // Ignore undef indicies
4658 if (Idx < (int)NumElems)
4663 // Only accept consecutive elements from the same vector
4664 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
4668 OpNum = SeenV1 ? 0 : 1;
4672 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
4673 /// logical left shift of a vector.
4674 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4675 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4676 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4677 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4678 false /* check zeros from right */, DAG);
4684 // Considering the elements in the mask that are not consecutive zeros,
4685 // check if they consecutively come from only one of the source vectors.
4687 // V1 = {X, A, B, C} 0
4689 // vector_shuffle V1, V2 <1, 2, 3, X>
4691 if (!isShuffleMaskConsecutive(SVOp,
4692 0, // Mask Start Index
4693 NumElems-NumZeros, // Mask End Index(exclusive)
4694 NumZeros, // Where to start looking in the src vector
4695 NumElems, // Number of elements in vector
4696 OpSrc)) // Which source operand ?
4701 ShVal = SVOp->getOperand(OpSrc);
4705 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
4706 /// logical left shift of a vector.
4707 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4708 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4709 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4710 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4711 true /* check zeros from left */, DAG);
4717 // Considering the elements in the mask that are not consecutive zeros,
4718 // check if they consecutively come from only one of the source vectors.
4720 // 0 { A, B, X, X } = V2
4722 // vector_shuffle V1, V2 <X, X, 4, 5>
4724 if (!isShuffleMaskConsecutive(SVOp,
4725 NumZeros, // Mask Start Index
4726 NumElems, // Mask End Index(exclusive)
4727 0, // Where to start looking in the src vector
4728 NumElems, // Number of elements in vector
4729 OpSrc)) // Which source operand ?
4734 ShVal = SVOp->getOperand(OpSrc);
4738 /// isVectorShift - Returns true if the shuffle can be implemented as a
4739 /// logical left or right shift of a vector.
4740 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4741 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4742 // Although the logic below support any bitwidth size, there are no
4743 // shift instructions which handle more than 128-bit vectors.
4744 if (!SVOp->getValueType(0).is128BitVector())
4747 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
4748 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
4754 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
4756 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4757 unsigned NumNonZero, unsigned NumZero,
4759 const X86Subtarget* Subtarget,
4760 const TargetLowering &TLI) {
4764 DebugLoc dl = Op.getDebugLoc();
4767 for (unsigned i = 0; i < 16; ++i) {
4768 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4769 if (ThisIsNonZero && First) {
4771 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4773 V = DAG.getUNDEF(MVT::v8i16);
4778 SDValue ThisElt(0, 0), LastElt(0, 0);
4779 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4780 if (LastIsNonZero) {
4781 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4782 MVT::i16, Op.getOperand(i-1));
4784 if (ThisIsNonZero) {
4785 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4786 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4787 ThisElt, DAG.getConstant(8, MVT::i8));
4789 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4793 if (ThisElt.getNode())
4794 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
4795 DAG.getIntPtrConstant(i/2));
4799 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
4802 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
4804 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
4805 unsigned NumNonZero, unsigned NumZero,
4807 const X86Subtarget* Subtarget,
4808 const TargetLowering &TLI) {
4812 DebugLoc dl = Op.getDebugLoc();
4815 for (unsigned i = 0; i < 8; ++i) {
4816 bool isNonZero = (NonZeros & (1 << i)) != 0;
4820 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4822 V = DAG.getUNDEF(MVT::v8i16);
4825 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4826 MVT::v8i16, V, Op.getOperand(i),
4827 DAG.getIntPtrConstant(i));
4834 /// getVShift - Return a vector logical shift node.
4836 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
4837 unsigned NumBits, SelectionDAG &DAG,
4838 const TargetLowering &TLI, DebugLoc dl) {
4839 assert(VT.is128BitVector() && "Unknown type for VShift");
4840 EVT ShVT = MVT::v2i64;
4841 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
4842 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
4843 return DAG.getNode(ISD::BITCAST, dl, VT,
4844 DAG.getNode(Opc, dl, ShVT, SrcOp,
4845 DAG.getConstant(NumBits,
4846 TLI.getShiftAmountTy(SrcOp.getValueType()))));
4850 X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
4851 SelectionDAG &DAG) const {
4853 // Check if the scalar load can be widened into a vector load. And if
4854 // the address is "base + cst" see if the cst can be "absorbed" into
4855 // the shuffle mask.
4856 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
4857 SDValue Ptr = LD->getBasePtr();
4858 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
4860 EVT PVT = LD->getValueType(0);
4861 if (PVT != MVT::i32 && PVT != MVT::f32)
4866 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
4867 FI = FINode->getIndex();
4869 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
4870 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4871 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4872 Offset = Ptr.getConstantOperandVal(1);
4873 Ptr = Ptr.getOperand(0);
4878 // FIXME: 256-bit vector instructions don't require a strict alignment,
4879 // improve this code to support it better.
4880 unsigned RequiredAlign = VT.getSizeInBits()/8;
4881 SDValue Chain = LD->getChain();
4882 // Make sure the stack object alignment is at least 16 or 32.
4883 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4884 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
4885 if (MFI->isFixedObjectIndex(FI)) {
4886 // Can't change the alignment. FIXME: It's possible to compute
4887 // the exact stack offset and reference FI + adjust offset instead.
4888 // If someone *really* cares about this. That's the way to implement it.
4891 MFI->setObjectAlignment(FI, RequiredAlign);
4895 // (Offset % 16 or 32) must be multiple of 4. Then address is then
4896 // Ptr + (Offset & ~15).
4899 if ((Offset % RequiredAlign) & 3)
4901 int64_t StartOffset = Offset & ~(RequiredAlign-1);
4903 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(),
4904 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
4906 int EltNo = (Offset - StartOffset) >> 2;
4907 unsigned NumElems = VT.getVectorNumElements();
4909 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
4910 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
4911 LD->getPointerInfo().getWithOffset(StartOffset),
4912 false, false, false, 0);
4914 SmallVector<int, 8> Mask;
4915 for (unsigned i = 0; i != NumElems; ++i)
4916 Mask.push_back(EltNo);
4918 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
4924 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
4925 /// vector of type 'VT', see if the elements can be replaced by a single large
4926 /// load which has the same value as a build_vector whose operands are 'elts'.
4928 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
4930 /// FIXME: we'd also like to handle the case where the last elements are zero
4931 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
4932 /// There's even a handy isZeroNode for that purpose.
4933 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
4934 DebugLoc &DL, SelectionDAG &DAG) {
4935 EVT EltVT = VT.getVectorElementType();
4936 unsigned NumElems = Elts.size();
4938 LoadSDNode *LDBase = NULL;
4939 unsigned LastLoadedElt = -1U;
4941 // For each element in the initializer, see if we've found a load or an undef.
4942 // If we don't find an initial load element, or later load elements are
4943 // non-consecutive, bail out.
4944 for (unsigned i = 0; i < NumElems; ++i) {
4945 SDValue Elt = Elts[i];
4947 if (!Elt.getNode() ||
4948 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
4951 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
4953 LDBase = cast<LoadSDNode>(Elt.getNode());
4957 if (Elt.getOpcode() == ISD::UNDEF)
4960 LoadSDNode *LD = cast<LoadSDNode>(Elt);
4961 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
4966 // If we have found an entire vector of loads and undefs, then return a large
4967 // load of the entire vector width starting at the base pointer. If we found
4968 // consecutive loads for the low half, generate a vzext_load node.
4969 if (LastLoadedElt == NumElems - 1) {
4970 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
4971 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4972 LDBase->getPointerInfo(),
4973 LDBase->isVolatile(), LDBase->isNonTemporal(),
4974 LDBase->isInvariant(), 0);
4975 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4976 LDBase->getPointerInfo(),
4977 LDBase->isVolatile(), LDBase->isNonTemporal(),
4978 LDBase->isInvariant(), LDBase->getAlignment());
4980 if (NumElems == 4 && LastLoadedElt == 1 &&
4981 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
4982 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
4983 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
4985 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, 2, MVT::i64,
4986 LDBase->getPointerInfo(),
4987 LDBase->getAlignment(),
4988 false/*isVolatile*/, true/*ReadMem*/,
4990 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
4995 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
4996 /// to generate a splat value for the following cases:
4997 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
4998 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
4999 /// a scalar load, or a constant.
5000 /// The VBROADCAST node is returned when a pattern is found,
5001 /// or SDValue() otherwise.
5003 X86TargetLowering::LowerVectorBroadcast(SDValue &Op, SelectionDAG &DAG) const {
5004 if (!Subtarget->hasAVX())
5007 EVT VT = Op.getValueType();
5008 DebugLoc dl = Op.getDebugLoc();
5010 assert((VT.is128BitVector() || VT.is256BitVector()) &&
5011 "Unsupported vector type for broadcast.");
5016 switch (Op.getOpcode()) {
5018 // Unknown pattern found.
5021 case ISD::BUILD_VECTOR: {
5022 // The BUILD_VECTOR node must be a splat.
5023 if (!isSplatVector(Op.getNode()))
5026 Ld = Op.getOperand(0);
5027 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5028 Ld.getOpcode() == ISD::ConstantFP);
5030 // The suspected load node has several users. Make sure that all
5031 // of its users are from the BUILD_VECTOR node.
5032 // Constants may have multiple users.
5033 if (!ConstSplatVal && !Ld->hasNUsesOfValue(VT.getVectorNumElements(), 0))
5038 case ISD::VECTOR_SHUFFLE: {
5039 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5041 // Shuffles must have a splat mask where the first element is
5043 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5046 SDValue Sc = Op.getOperand(0);
5047 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5048 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5050 if (!Subtarget->hasAVX2())
5053 // Use the register form of the broadcast instruction available on AVX2.
5054 if (VT.is256BitVector())
5055 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5056 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5059 Ld = Sc.getOperand(0);
5060 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5061 Ld.getOpcode() == ISD::ConstantFP);
5063 // The scalar_to_vector node and the suspected
5064 // load node must have exactly one user.
5065 // Constants may have multiple users.
5066 if (!ConstSplatVal && (!Sc.hasOneUse() || !Ld.hasOneUse()))
5072 bool Is256 = VT.is256BitVector();
5074 // Handle the broadcasting a single constant scalar from the constant pool
5075 // into a vector. On Sandybridge it is still better to load a constant vector
5076 // from the constant pool and not to broadcast it from a scalar.
5077 if (ConstSplatVal && Subtarget->hasAVX2()) {
5078 EVT CVT = Ld.getValueType();
5079 assert(!CVT.isVector() && "Must not broadcast a vector type");
5080 unsigned ScalarSize = CVT.getSizeInBits();
5082 if (ScalarSize == 32 || (Is256 && ScalarSize == 64)) {
5083 const Constant *C = 0;
5084 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5085 C = CI->getConstantIntValue();
5086 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5087 C = CF->getConstantFPValue();
5089 assert(C && "Invalid constant type");
5091 SDValue CP = DAG.getConstantPool(C, getPointerTy());
5092 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5093 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
5094 MachinePointerInfo::getConstantPool(),
5095 false, false, false, Alignment);
5097 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5101 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5102 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5104 // Handle AVX2 in-register broadcasts.
5105 if (!IsLoad && Subtarget->hasAVX2() &&
5106 (ScalarSize == 32 || (Is256 && ScalarSize == 64)))
5107 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5109 // The scalar source must be a normal load.
5113 if (ScalarSize == 32 || (Is256 && ScalarSize == 64))
5114 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5116 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5117 // double since there is no vbroadcastsd xmm
5118 if (Subtarget->hasAVX2() && Ld.getValueType().isInteger()) {
5119 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5120 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5123 // Unsupported broadcast.
5128 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5129 DebugLoc dl = Op.getDebugLoc();
5131 EVT VT = Op.getValueType();
5132 EVT ExtVT = VT.getVectorElementType();
5133 unsigned NumElems = Op.getNumOperands();
5135 // Vectors containing all zeros can be matched by pxor and xorps later
5136 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5137 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
5138 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
5139 if (VT == MVT::v4i32 || VT == MVT::v8i32)
5142 return getZeroVector(VT, Subtarget, DAG, dl);
5145 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
5146 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
5147 // vpcmpeqd on 256-bit vectors.
5148 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5149 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasAVX2()))
5152 return getOnesVector(VT, Subtarget->hasAVX2(), DAG, dl);
5155 SDValue Broadcast = LowerVectorBroadcast(Op, DAG);
5156 if (Broadcast.getNode())
5159 unsigned EVTBits = ExtVT.getSizeInBits();
5161 unsigned NumZero = 0;
5162 unsigned NumNonZero = 0;
5163 unsigned NonZeros = 0;
5164 bool IsAllConstants = true;
5165 SmallSet<SDValue, 8> Values;
5166 for (unsigned i = 0; i < NumElems; ++i) {
5167 SDValue Elt = Op.getOperand(i);
5168 if (Elt.getOpcode() == ISD::UNDEF)
5171 if (Elt.getOpcode() != ISD::Constant &&
5172 Elt.getOpcode() != ISD::ConstantFP)
5173 IsAllConstants = false;
5174 if (X86::isZeroNode(Elt))
5177 NonZeros |= (1 << i);
5182 // All undef vector. Return an UNDEF. All zero vectors were handled above.
5183 if (NumNonZero == 0)
5184 return DAG.getUNDEF(VT);
5186 // Special case for single non-zero, non-undef, element.
5187 if (NumNonZero == 1) {
5188 unsigned Idx = CountTrailingZeros_32(NonZeros);
5189 SDValue Item = Op.getOperand(Idx);
5191 // If this is an insertion of an i64 value on x86-32, and if the top bits of
5192 // the value are obviously zero, truncate the value to i32 and do the
5193 // insertion that way. Only do this if the value is non-constant or if the
5194 // value is a constant being inserted into element 0. It is cheaper to do
5195 // a constant pool load than it is to do a movd + shuffle.
5196 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5197 (!IsAllConstants || Idx == 0)) {
5198 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
5200 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5201 EVT VecVT = MVT::v4i32;
5202 unsigned VecElts = 4;
5204 // Truncate the value (which may itself be a constant) to i32, and
5205 // convert it to a vector with movd (S2V+shuffle to zero extend).
5206 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5207 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5208 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5210 // Now we have our 32-bit value zero extended in the low element of
5211 // a vector. If Idx != 0, swizzle it into place.
5213 SmallVector<int, 4> Mask;
5214 Mask.push_back(Idx);
5215 for (unsigned i = 1; i != VecElts; ++i)
5217 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
5220 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5224 // If we have a constant or non-constant insertion into the low element of
5225 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5226 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5227 // depending on what the source datatype is.
5230 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5232 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5233 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5234 if (VT.is256BitVector()) {
5235 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
5236 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
5237 Item, DAG.getIntPtrConstant(0));
5239 assert(VT.is128BitVector() && "Expected an SSE value type!");
5240 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5241 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
5242 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5245 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
5246 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5247 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5248 if (VT.is256BitVector()) {
5249 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
5250 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
5252 assert(VT.is128BitVector() && "Expected an SSE value type!");
5253 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5255 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5259 // Is it a vector logical left shift?
5260 if (NumElems == 2 && Idx == 1 &&
5261 X86::isZeroNode(Op.getOperand(0)) &&
5262 !X86::isZeroNode(Op.getOperand(1))) {
5263 unsigned NumBits = VT.getSizeInBits();
5264 return getVShift(true, VT,
5265 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5266 VT, Op.getOperand(1)),
5267 NumBits/2, DAG, *this, dl);
5270 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
5273 // Otherwise, if this is a vector with i32 or f32 elements, and the element
5274 // is a non-constant being inserted into an element other than the low one,
5275 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
5276 // movd/movss) to move this into the low element, then shuffle it into
5278 if (EVTBits == 32) {
5279 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5281 // Turn it into a shuffle of zero and zero-extended scalar to vector.
5282 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
5283 SmallVector<int, 8> MaskVec;
5284 for (unsigned i = 0; i != NumElems; ++i)
5285 MaskVec.push_back(i == Idx ? 0 : 1);
5286 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
5290 // Splat is obviously ok. Let legalizer expand it to a shuffle.
5291 if (Values.size() == 1) {
5292 if (EVTBits == 32) {
5293 // Instead of a shuffle like this:
5294 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
5295 // Check if it's possible to issue this instead.
5296 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
5297 unsigned Idx = CountTrailingZeros_32(NonZeros);
5298 SDValue Item = Op.getOperand(Idx);
5299 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
5300 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
5305 // A vector full of immediates; various special cases are already
5306 // handled, so this is best done with a single constant-pool load.
5310 // For AVX-length vectors, build the individual 128-bit pieces and use
5311 // shuffles to put them in place.
5312 if (VT.is256BitVector()) {
5313 SmallVector<SDValue, 32> V;
5314 for (unsigned i = 0; i != NumElems; ++i)
5315 V.push_back(Op.getOperand(i));
5317 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
5319 // Build both the lower and upper subvector.
5320 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2);
5321 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2],
5324 // Recreate the wider vector with the lower and upper part.
5325 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
5328 // Let legalizer expand 2-wide build_vectors.
5329 if (EVTBits == 64) {
5330 if (NumNonZero == 1) {
5331 // One half is zero or undef.
5332 unsigned Idx = CountTrailingZeros_32(NonZeros);
5333 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
5334 Op.getOperand(Idx));
5335 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
5340 // If element VT is < 32 bits, convert it to inserts into a zero vector.
5341 if (EVTBits == 8 && NumElems == 16) {
5342 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
5344 if (V.getNode()) return V;
5347 if (EVTBits == 16 && NumElems == 8) {
5348 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
5350 if (V.getNode()) return V;
5353 // If element VT is == 32 bits, turn it into a number of shuffles.
5354 SmallVector<SDValue, 8> V(NumElems);
5355 if (NumElems == 4 && NumZero > 0) {
5356 for (unsigned i = 0; i < 4; ++i) {
5357 bool isZero = !(NonZeros & (1 << i));
5359 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
5361 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5364 for (unsigned i = 0; i < 2; ++i) {
5365 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
5368 V[i] = V[i*2]; // Must be a zero vector.
5371 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
5374 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
5377 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
5382 bool Reverse1 = (NonZeros & 0x3) == 2;
5383 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
5387 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
5388 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
5390 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
5393 if (Values.size() > 1 && VT.is128BitVector()) {
5394 // Check for a build vector of consecutive loads.
5395 for (unsigned i = 0; i < NumElems; ++i)
5396 V[i] = Op.getOperand(i);
5398 // Check for elements which are consecutive loads.
5399 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG);
5403 // For SSE 4.1, use insertps to put the high elements into the low element.
5404 if (getSubtarget()->hasSSE41()) {
5406 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
5407 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
5409 Result = DAG.getUNDEF(VT);
5411 for (unsigned i = 1; i < NumElems; ++i) {
5412 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
5413 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
5414 Op.getOperand(i), DAG.getIntPtrConstant(i));
5419 // Otherwise, expand into a number of unpckl*, start by extending each of
5420 // our (non-undef) elements to the full vector width with the element in the
5421 // bottom slot of the vector (which generates no code for SSE).
5422 for (unsigned i = 0; i < NumElems; ++i) {
5423 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
5424 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5426 V[i] = DAG.getUNDEF(VT);
5429 // Next, we iteratively mix elements, e.g. for v4f32:
5430 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
5431 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
5432 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
5433 unsigned EltStride = NumElems >> 1;
5434 while (EltStride != 0) {
5435 for (unsigned i = 0; i < EltStride; ++i) {
5436 // If V[i+EltStride] is undef and this is the first round of mixing,
5437 // then it is safe to just drop this shuffle: V[i] is already in the
5438 // right place, the one element (since it's the first round) being
5439 // inserted as undef can be dropped. This isn't safe for successive
5440 // rounds because they will permute elements within both vectors.
5441 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
5442 EltStride == NumElems/2)
5445 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
5454 // LowerMMXCONCAT_VECTORS - We support concatenate two MMX registers and place
5455 // them in a MMX register. This is better than doing a stack convert.
5456 static SDValue LowerMMXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5457 DebugLoc dl = Op.getDebugLoc();
5458 EVT ResVT = Op.getValueType();
5460 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 ||
5461 ResVT == MVT::v8i16 || ResVT == MVT::v16i8);
5463 SDValue InVec = DAG.getNode(ISD::BITCAST,dl, MVT::v1i64, Op.getOperand(0));
5464 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
5465 InVec = Op.getOperand(1);
5466 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
5467 unsigned NumElts = ResVT.getVectorNumElements();
5468 VecOp = DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
5469 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp,
5470 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1));
5472 InVec = DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, InVec);
5473 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
5474 Mask[0] = 0; Mask[1] = 2;
5475 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask);
5477 return DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
5480 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
5481 // to create 256-bit vectors from two other 128-bit ones.
5482 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5483 DebugLoc dl = Op.getDebugLoc();
5484 EVT ResVT = Op.getValueType();
5486 assert(ResVT.is256BitVector() && "Value type must be 256-bit wide");
5488 SDValue V1 = Op.getOperand(0);
5489 SDValue V2 = Op.getOperand(1);
5490 unsigned NumElems = ResVT.getVectorNumElements();
5492 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
5496 X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
5497 EVT ResVT = Op.getValueType();
5499 assert(Op.getNumOperands() == 2);
5500 assert((ResVT.is128BitVector() || ResVT.is256BitVector()) &&
5501 "Unsupported CONCAT_VECTORS for value type");
5503 // We support concatenate two MMX registers and place them in a MMX register.
5504 // This is better than doing a stack convert.
5505 if (ResVT.is128BitVector())
5506 return LowerMMXCONCAT_VECTORS(Op, DAG);
5508 // 256-bit AVX can use the vinsertf128 instruction to create 256-bit vectors
5509 // from two other 128-bit ones.
5510 return LowerAVXCONCAT_VECTORS(Op, DAG);
5513 // Try to lower a shuffle node into a simple blend instruction.
5514 static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
5515 const X86Subtarget *Subtarget,
5516 SelectionDAG &DAG) {
5517 SDValue V1 = SVOp->getOperand(0);
5518 SDValue V2 = SVOp->getOperand(1);
5519 DebugLoc dl = SVOp->getDebugLoc();
5520 MVT VT = SVOp->getValueType(0).getSimpleVT();
5521 unsigned NumElems = VT.getVectorNumElements();
5523 if (!Subtarget->hasSSE41())
5529 switch (VT.SimpleTy) {
5530 default: return SDValue();
5532 ISDNo = X86ISD::BLENDPW;
5537 ISDNo = X86ISD::BLENDPS;
5542 ISDNo = X86ISD::BLENDPD;
5547 if (!Subtarget->hasAVX())
5549 ISDNo = X86ISD::BLENDPS;
5554 if (!Subtarget->hasAVX())
5556 ISDNo = X86ISD::BLENDPD;
5560 assert(ISDNo && "Invalid Op Number");
5562 unsigned MaskVals = 0;
5564 for (unsigned i = 0; i != NumElems; ++i) {
5565 int EltIdx = SVOp->getMaskElt(i);
5566 if (EltIdx == (int)i || EltIdx < 0)
5568 else if (EltIdx == (int)(i + NumElems))
5569 continue; // Bit is set to zero;
5574 V1 = DAG.getNode(ISD::BITCAST, dl, OpTy, V1);
5575 V2 = DAG.getNode(ISD::BITCAST, dl, OpTy, V2);
5576 SDValue Ret = DAG.getNode(ISDNo, dl, OpTy, V1, V2,
5577 DAG.getConstant(MaskVals, MVT::i32));
5578 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
5581 // v8i16 shuffles - Prefer shuffles in the following order:
5582 // 1. [all] pshuflw, pshufhw, optional move
5583 // 2. [ssse3] 1 x pshufb
5584 // 3. [ssse3] 2 x pshufb + 1 x por
5585 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
5587 X86TargetLowering::LowerVECTOR_SHUFFLEv8i16(SDValue Op,
5588 SelectionDAG &DAG) const {
5589 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5590 SDValue V1 = SVOp->getOperand(0);
5591 SDValue V2 = SVOp->getOperand(1);
5592 DebugLoc dl = SVOp->getDebugLoc();
5593 SmallVector<int, 8> MaskVals;
5595 // Determine if more than 1 of the words in each of the low and high quadwords
5596 // of the result come from the same quadword of one of the two inputs. Undef
5597 // mask values count as coming from any quadword, for better codegen.
5598 unsigned LoQuad[] = { 0, 0, 0, 0 };
5599 unsigned HiQuad[] = { 0, 0, 0, 0 };
5600 std::bitset<4> InputQuads;
5601 for (unsigned i = 0; i < 8; ++i) {
5602 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
5603 int EltIdx = SVOp->getMaskElt(i);
5604 MaskVals.push_back(EltIdx);
5613 InputQuads.set(EltIdx / 4);
5616 int BestLoQuad = -1;
5617 unsigned MaxQuad = 1;
5618 for (unsigned i = 0; i < 4; ++i) {
5619 if (LoQuad[i] > MaxQuad) {
5621 MaxQuad = LoQuad[i];
5625 int BestHiQuad = -1;
5627 for (unsigned i = 0; i < 4; ++i) {
5628 if (HiQuad[i] > MaxQuad) {
5630 MaxQuad = HiQuad[i];
5634 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
5635 // of the two input vectors, shuffle them into one input vector so only a
5636 // single pshufb instruction is necessary. If There are more than 2 input
5637 // quads, disable the next transformation since it does not help SSSE3.
5638 bool V1Used = InputQuads[0] || InputQuads[1];
5639 bool V2Used = InputQuads[2] || InputQuads[3];
5640 if (Subtarget->hasSSSE3()) {
5641 if (InputQuads.count() == 2 && V1Used && V2Used) {
5642 BestLoQuad = InputQuads[0] ? 0 : 1;
5643 BestHiQuad = InputQuads[2] ? 2 : 3;
5645 if (InputQuads.count() > 2) {
5651 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
5652 // the shuffle mask. If a quad is scored as -1, that means that it contains
5653 // words from all 4 input quadwords.
5655 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
5657 BestLoQuad < 0 ? 0 : BestLoQuad,
5658 BestHiQuad < 0 ? 1 : BestHiQuad
5660 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
5661 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
5662 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
5663 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
5665 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
5666 // source words for the shuffle, to aid later transformations.
5667 bool AllWordsInNewV = true;
5668 bool InOrder[2] = { true, true };
5669 for (unsigned i = 0; i != 8; ++i) {
5670 int idx = MaskVals[i];
5672 InOrder[i/4] = false;
5673 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
5675 AllWordsInNewV = false;
5679 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
5680 if (AllWordsInNewV) {
5681 for (int i = 0; i != 8; ++i) {
5682 int idx = MaskVals[i];
5685 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
5686 if ((idx != i) && idx < 4)
5688 if ((idx != i) && idx > 3)
5697 // If we've eliminated the use of V2, and the new mask is a pshuflw or
5698 // pshufhw, that's as cheap as it gets. Return the new shuffle.
5699 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
5700 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
5701 unsigned TargetMask = 0;
5702 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
5703 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
5704 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
5705 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
5706 getShufflePSHUFLWImmediate(SVOp);
5707 V1 = NewV.getOperand(0);
5708 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
5712 // If we have SSSE3, and all words of the result are from 1 input vector,
5713 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
5714 // is present, fall back to case 4.
5715 if (Subtarget->hasSSSE3()) {
5716 SmallVector<SDValue,16> pshufbMask;
5718 // If we have elements from both input vectors, set the high bit of the
5719 // shuffle mask element to zero out elements that come from V2 in the V1
5720 // mask, and elements that come from V1 in the V2 mask, so that the two
5721 // results can be OR'd together.
5722 bool TwoInputs = V1Used && V2Used;
5723 for (unsigned i = 0; i != 8; ++i) {
5724 int EltIdx = MaskVals[i] * 2;
5725 int Idx0 = (TwoInputs && (EltIdx >= 16)) ? 0x80 : EltIdx;
5726 int Idx1 = (TwoInputs && (EltIdx >= 16)) ? 0x80 : EltIdx+1;
5727 pshufbMask.push_back(DAG.getConstant(Idx0, MVT::i8));
5728 pshufbMask.push_back(DAG.getConstant(Idx1, MVT::i8));
5730 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1);
5731 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5732 DAG.getNode(ISD::BUILD_VECTOR, dl,
5733 MVT::v16i8, &pshufbMask[0], 16));
5735 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5737 // Calculate the shuffle mask for the second input, shuffle it, and
5738 // OR it with the first shuffled input.
5740 for (unsigned i = 0; i != 8; ++i) {
5741 int EltIdx = MaskVals[i] * 2;
5742 int Idx0 = (EltIdx < 16) ? 0x80 : EltIdx - 16;
5743 int Idx1 = (EltIdx < 16) ? 0x80 : EltIdx - 15;
5744 pshufbMask.push_back(DAG.getConstant(Idx0, MVT::i8));
5745 pshufbMask.push_back(DAG.getConstant(Idx1, MVT::i8));
5747 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2);
5748 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5749 DAG.getNode(ISD::BUILD_VECTOR, dl,
5750 MVT::v16i8, &pshufbMask[0], 16));
5751 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5752 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5755 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
5756 // and update MaskVals with new element order.
5757 std::bitset<8> InOrder;
5758 if (BestLoQuad >= 0) {
5759 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
5760 for (int i = 0; i != 4; ++i) {
5761 int idx = MaskVals[i];
5764 } else if ((idx / 4) == BestLoQuad) {
5769 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5772 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
5773 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
5774 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
5776 getShufflePSHUFLWImmediate(SVOp), DAG);
5780 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
5781 // and update MaskVals with the new element order.
5782 if (BestHiQuad >= 0) {
5783 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
5784 for (unsigned i = 4; i != 8; ++i) {
5785 int idx = MaskVals[i];
5788 } else if ((idx / 4) == BestHiQuad) {
5789 MaskV[i] = (idx & 3) + 4;
5793 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5796 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
5797 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
5798 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
5800 getShufflePSHUFHWImmediate(SVOp), DAG);
5804 // In case BestHi & BestLo were both -1, which means each quadword has a word
5805 // from each of the four input quadwords, calculate the InOrder bitvector now
5806 // before falling through to the insert/extract cleanup.
5807 if (BestLoQuad == -1 && BestHiQuad == -1) {
5809 for (int i = 0; i != 8; ++i)
5810 if (MaskVals[i] < 0 || MaskVals[i] == i)
5814 // The other elements are put in the right place using pextrw and pinsrw.
5815 for (unsigned i = 0; i != 8; ++i) {
5818 int EltIdx = MaskVals[i];
5821 SDValue ExtOp = (EltIdx < 8) ?
5822 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
5823 DAG.getIntPtrConstant(EltIdx)) :
5824 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
5825 DAG.getIntPtrConstant(EltIdx - 8));
5826 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
5827 DAG.getIntPtrConstant(i));
5832 // v16i8 shuffles - Prefer shuffles in the following order:
5833 // 1. [ssse3] 1 x pshufb
5834 // 2. [ssse3] 2 x pshufb + 1 x por
5835 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
5837 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
5839 const X86TargetLowering &TLI) {
5840 SDValue V1 = SVOp->getOperand(0);
5841 SDValue V2 = SVOp->getOperand(1);
5842 DebugLoc dl = SVOp->getDebugLoc();
5843 ArrayRef<int> MaskVals = SVOp->getMask();
5845 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
5847 // If we have SSSE3, case 1 is generated when all result bytes come from
5848 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
5849 // present, fall back to case 3.
5851 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
5852 if (TLI.getSubtarget()->hasSSSE3()) {
5853 SmallVector<SDValue,16> pshufbMask;
5855 // If all result elements are from one input vector, then only translate
5856 // undef mask values to 0x80 (zero out result) in the pshufb mask.
5858 // Otherwise, we have elements from both input vectors, and must zero out
5859 // elements that come from V2 in the first mask, and V1 in the second mask
5860 // so that we can OR them together.
5861 for (unsigned i = 0; i != 16; ++i) {
5862 int EltIdx = MaskVals[i];
5863 if (EltIdx < 0 || EltIdx >= 16)
5865 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5867 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5868 DAG.getNode(ISD::BUILD_VECTOR, dl,
5869 MVT::v16i8, &pshufbMask[0], 16));
5873 // Calculate the shuffle mask for the second input, shuffle it, and
5874 // OR it with the first shuffled input.
5876 for (unsigned i = 0; i != 16; ++i) {
5877 int EltIdx = MaskVals[i];
5878 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
5879 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5881 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5882 DAG.getNode(ISD::BUILD_VECTOR, dl,
5883 MVT::v16i8, &pshufbMask[0], 16));
5884 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5887 // No SSSE3 - Calculate in place words and then fix all out of place words
5888 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
5889 // the 16 different words that comprise the two doublequadword input vectors.
5890 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5891 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
5893 for (int i = 0; i != 8; ++i) {
5894 int Elt0 = MaskVals[i*2];
5895 int Elt1 = MaskVals[i*2+1];
5897 // This word of the result is all undef, skip it.
5898 if (Elt0 < 0 && Elt1 < 0)
5901 // This word of the result is already in the correct place, skip it.
5902 if ((Elt0 == i*2) && (Elt1 == i*2+1))
5905 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
5906 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
5909 // If Elt0 and Elt1 are defined, are consecutive, and can be load
5910 // using a single extract together, load it and store it.
5911 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
5912 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5913 DAG.getIntPtrConstant(Elt1 / 2));
5914 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5915 DAG.getIntPtrConstant(i));
5919 // If Elt1 is defined, extract it from the appropriate source. If the
5920 // source byte is not also odd, shift the extracted word left 8 bits
5921 // otherwise clear the bottom 8 bits if we need to do an or.
5923 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5924 DAG.getIntPtrConstant(Elt1 / 2));
5925 if ((Elt1 & 1) == 0)
5926 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
5928 TLI.getShiftAmountTy(InsElt.getValueType())));
5930 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
5931 DAG.getConstant(0xFF00, MVT::i16));
5933 // If Elt0 is defined, extract it from the appropriate source. If the
5934 // source byte is not also even, shift the extracted word right 8 bits. If
5935 // Elt1 was also defined, OR the extracted values together before
5936 // inserting them in the result.
5938 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
5939 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
5940 if ((Elt0 & 1) != 0)
5941 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
5943 TLI.getShiftAmountTy(InsElt0.getValueType())));
5945 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
5946 DAG.getConstant(0x00FF, MVT::i16));
5947 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
5950 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5951 DAG.getIntPtrConstant(i));
5953 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
5956 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
5957 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
5958 /// done when every pair / quad of shuffle mask elements point to elements in
5959 /// the right sequence. e.g.
5960 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
5962 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
5963 SelectionDAG &DAG, DebugLoc dl) {
5964 MVT VT = SVOp->getValueType(0).getSimpleVT();
5965 unsigned NumElems = VT.getVectorNumElements();
5968 switch (VT.SimpleTy) {
5969 default: llvm_unreachable("Unexpected!");
5970 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
5971 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
5972 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
5973 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
5974 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
5975 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
5978 SmallVector<int, 8> MaskVec;
5979 for (unsigned i = 0; i != NumElems; i += Scale) {
5981 for (unsigned j = 0; j != Scale; ++j) {
5982 int EltIdx = SVOp->getMaskElt(i+j);
5986 StartIdx = (EltIdx / Scale);
5987 if (EltIdx != (int)(StartIdx*Scale + j))
5990 MaskVec.push_back(StartIdx);
5993 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
5994 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
5995 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
5998 /// getVZextMovL - Return a zero-extending vector move low node.
6000 static SDValue getVZextMovL(EVT VT, EVT OpVT,
6001 SDValue SrcOp, SelectionDAG &DAG,
6002 const X86Subtarget *Subtarget, DebugLoc dl) {
6003 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
6004 LoadSDNode *LD = NULL;
6005 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
6006 LD = dyn_cast<LoadSDNode>(SrcOp);
6008 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
6010 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
6011 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
6012 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
6013 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
6014 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
6016 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
6017 return DAG.getNode(ISD::BITCAST, dl, VT,
6018 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
6019 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6027 return DAG.getNode(ISD::BITCAST, dl, VT,
6028 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
6029 DAG.getNode(ISD::BITCAST, dl,
6033 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
6034 /// which could not be matched by any known target speficic shuffle
6036 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6038 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
6039 if (NewOp.getNode())
6042 EVT VT = SVOp->getValueType(0);
6044 unsigned NumElems = VT.getVectorNumElements();
6045 unsigned NumLaneElems = NumElems / 2;
6047 DebugLoc dl = SVOp->getDebugLoc();
6048 MVT EltVT = VT.getVectorElementType().getSimpleVT();
6049 EVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
6052 SmallVector<int, 16> Mask;
6053 for (unsigned l = 0; l < 2; ++l) {
6054 // Build a shuffle mask for the output, discovering on the fly which
6055 // input vectors to use as shuffle operands (recorded in InputUsed).
6056 // If building a suitable shuffle vector proves too hard, then bail
6057 // out with UseBuildVector set.
6058 bool UseBuildVector = false;
6059 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
6060 unsigned LaneStart = l * NumLaneElems;
6061 for (unsigned i = 0; i != NumLaneElems; ++i) {
6062 // The mask element. This indexes into the input.
6063 int Idx = SVOp->getMaskElt(i+LaneStart);
6065 // the mask element does not index into any input vector.
6070 // The input vector this mask element indexes into.
6071 int Input = Idx / NumLaneElems;
6073 // Turn the index into an offset from the start of the input vector.
6074 Idx -= Input * NumLaneElems;
6076 // Find or create a shuffle vector operand to hold this input.
6078 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
6079 if (InputUsed[OpNo] == Input)
6080 // This input vector is already an operand.
6082 if (InputUsed[OpNo] < 0) {
6083 // Create a new operand for this input vector.
6084 InputUsed[OpNo] = Input;
6089 if (OpNo >= array_lengthof(InputUsed)) {
6090 // More than two input vectors used! Give up on trying to create a
6091 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
6092 UseBuildVector = true;
6096 // Add the mask index for the new shuffle vector.
6097 Mask.push_back(Idx + OpNo * NumLaneElems);
6100 if (UseBuildVector) {
6101 SmallVector<SDValue, 16> SVOps;
6102 for (unsigned i = 0; i != NumLaneElems; ++i) {
6103 // The mask element. This indexes into the input.
6104 int Idx = SVOp->getMaskElt(i+LaneStart);
6106 SVOps.push_back(DAG.getUNDEF(EltVT));
6110 // The input vector this mask element indexes into.
6111 int Input = Idx / NumElems;
6113 // Turn the index into an offset from the start of the input vector.
6114 Idx -= Input * NumElems;
6116 // Extract the vector element by hand.
6117 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
6118 SVOp->getOperand(Input),
6119 DAG.getIntPtrConstant(Idx)));
6122 // Construct the output using a BUILD_VECTOR.
6123 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, &SVOps[0],
6125 } else if (InputUsed[0] < 0) {
6126 // No input vectors were used! The result is undefined.
6127 Output[l] = DAG.getUNDEF(NVT);
6129 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
6130 (InputUsed[0] % 2) * NumLaneElems,
6132 // If only one input was used, use an undefined vector for the other.
6133 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
6134 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
6135 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
6136 // At least one input vector was used. Create a new shuffle vector.
6137 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
6143 // Concatenate the result back
6144 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
6147 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
6148 /// 4 elements, and match them with several different shuffle types.
6150 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6151 SDValue V1 = SVOp->getOperand(0);
6152 SDValue V2 = SVOp->getOperand(1);
6153 DebugLoc dl = SVOp->getDebugLoc();
6154 EVT VT = SVOp->getValueType(0);
6156 assert(VT.is128BitVector() && "Unsupported vector size");
6158 std::pair<int, int> Locs[4];
6159 int Mask1[] = { -1, -1, -1, -1 };
6160 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
6164 for (unsigned i = 0; i != 4; ++i) {
6165 int Idx = PermMask[i];
6167 Locs[i] = std::make_pair(-1, -1);
6169 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
6171 Locs[i] = std::make_pair(0, NumLo);
6175 Locs[i] = std::make_pair(1, NumHi);
6177 Mask1[2+NumHi] = Idx;
6183 if (NumLo <= 2 && NumHi <= 2) {
6184 // If no more than two elements come from either vector. This can be
6185 // implemented with two shuffles. First shuffle gather the elements.
6186 // The second shuffle, which takes the first shuffle as both of its
6187 // vector operands, put the elements into the right order.
6188 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6190 int Mask2[] = { -1, -1, -1, -1 };
6192 for (unsigned i = 0; i != 4; ++i)
6193 if (Locs[i].first != -1) {
6194 unsigned Idx = (i < 2) ? 0 : 4;
6195 Idx += Locs[i].first * 2 + Locs[i].second;
6199 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
6202 if (NumLo == 3 || NumHi == 3) {
6203 // Otherwise, we must have three elements from one vector, call it X, and
6204 // one element from the other, call it Y. First, use a shufps to build an
6205 // intermediate vector with the one element from Y and the element from X
6206 // that will be in the same half in the final destination (the indexes don't
6207 // matter). Then, use a shufps to build the final vector, taking the half
6208 // containing the element from Y from the intermediate, and the other half
6211 // Normalize it so the 3 elements come from V1.
6212 CommuteVectorShuffleMask(PermMask, 4);
6216 // Find the element from V2.
6218 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
6219 int Val = PermMask[HiIndex];
6226 Mask1[0] = PermMask[HiIndex];
6228 Mask1[2] = PermMask[HiIndex^1];
6230 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6233 Mask1[0] = PermMask[0];
6234 Mask1[1] = PermMask[1];
6235 Mask1[2] = HiIndex & 1 ? 6 : 4;
6236 Mask1[3] = HiIndex & 1 ? 4 : 6;
6237 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6240 Mask1[0] = HiIndex & 1 ? 2 : 0;
6241 Mask1[1] = HiIndex & 1 ? 0 : 2;
6242 Mask1[2] = PermMask[2];
6243 Mask1[3] = PermMask[3];
6248 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
6251 // Break it into (shuffle shuffle_hi, shuffle_lo).
6252 int LoMask[] = { -1, -1, -1, -1 };
6253 int HiMask[] = { -1, -1, -1, -1 };
6255 int *MaskPtr = LoMask;
6256 unsigned MaskIdx = 0;
6259 for (unsigned i = 0; i != 4; ++i) {
6266 int Idx = PermMask[i];
6268 Locs[i] = std::make_pair(-1, -1);
6269 } else if (Idx < 4) {
6270 Locs[i] = std::make_pair(MaskIdx, LoIdx);
6271 MaskPtr[LoIdx] = Idx;
6274 Locs[i] = std::make_pair(MaskIdx, HiIdx);
6275 MaskPtr[HiIdx] = Idx;
6280 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
6281 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
6282 int MaskOps[] = { -1, -1, -1, -1 };
6283 for (unsigned i = 0; i != 4; ++i)
6284 if (Locs[i].first != -1)
6285 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
6286 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
6289 static bool MayFoldVectorLoad(SDValue V) {
6290 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6291 V = V.getOperand(0);
6292 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6293 V = V.getOperand(0);
6294 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
6295 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
6296 // BUILD_VECTOR (load), undef
6297 V = V.getOperand(0);
6303 // FIXME: the version above should always be used. Since there's
6304 // a bug where several vector shuffles can't be folded because the
6305 // DAG is not updated during lowering and a node claims to have two
6306 // uses while it only has one, use this version, and let isel match
6307 // another instruction if the load really happens to have more than
6308 // one use. Remove this version after this bug get fixed.
6309 // rdar://8434668, PR8156
6310 static bool RelaxedMayFoldVectorLoad(SDValue V) {
6311 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6312 V = V.getOperand(0);
6313 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6314 V = V.getOperand(0);
6315 if (ISD::isNormalLoad(V.getNode()))
6321 SDValue getMOVDDup(SDValue &Op, DebugLoc &dl, SDValue V1, SelectionDAG &DAG) {
6322 EVT VT = Op.getValueType();
6324 // Canonizalize to v2f64.
6325 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
6326 return DAG.getNode(ISD::BITCAST, dl, VT,
6327 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
6332 SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG,
6334 SDValue V1 = Op.getOperand(0);
6335 SDValue V2 = Op.getOperand(1);
6336 EVT VT = Op.getValueType();
6338 assert(VT != MVT::v2i64 && "unsupported shuffle type");
6340 if (HasSSE2 && VT == MVT::v2f64)
6341 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
6343 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
6344 return DAG.getNode(ISD::BITCAST, dl, VT,
6345 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
6346 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
6347 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
6351 SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) {
6352 SDValue V1 = Op.getOperand(0);
6353 SDValue V2 = Op.getOperand(1);
6354 EVT VT = Op.getValueType();
6356 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
6357 "unsupported shuffle type");
6359 if (V2.getOpcode() == ISD::UNDEF)
6363 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
6367 SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
6368 SDValue V1 = Op.getOperand(0);
6369 SDValue V2 = Op.getOperand(1);
6370 EVT VT = Op.getValueType();
6371 unsigned NumElems = VT.getVectorNumElements();
6373 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
6374 // operand of these instructions is only memory, so check if there's a
6375 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
6377 bool CanFoldLoad = false;
6379 // Trivial case, when V2 comes from a load.
6380 if (MayFoldVectorLoad(V2))
6383 // When V1 is a load, it can be folded later into a store in isel, example:
6384 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
6386 // (MOVLPSmr addr:$src1, VR128:$src2)
6387 // So, recognize this potential and also use MOVLPS or MOVLPD
6388 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
6391 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6393 if (HasSSE2 && NumElems == 2)
6394 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
6397 // If we don't care about the second element, proceed to use movss.
6398 if (SVOp->getMaskElt(1) != -1)
6399 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
6402 // movl and movlp will both match v2i64, but v2i64 is never matched by
6403 // movl earlier because we make it strict to avoid messing with the movlp load
6404 // folding logic (see the code above getMOVLP call). Match it here then,
6405 // this is horrible, but will stay like this until we move all shuffle
6406 // matching to x86 specific nodes. Note that for the 1st condition all
6407 // types are matched with movsd.
6409 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
6410 // as to remove this logic from here, as much as possible
6411 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
6412 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6413 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6416 assert(VT != MVT::v4i32 && "unsupported shuffle type");
6418 // Invert the operand order and use SHUFPS to match it.
6419 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
6420 getShuffleSHUFImmediate(SVOp), DAG);
6424 X86TargetLowering::NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG) const {
6425 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6426 EVT VT = Op.getValueType();
6427 DebugLoc dl = Op.getDebugLoc();
6428 SDValue V1 = Op.getOperand(0);
6429 SDValue V2 = Op.getOperand(1);
6431 if (isZeroShuffle(SVOp))
6432 return getZeroVector(VT, Subtarget, DAG, dl);
6434 // Handle splat operations
6435 if (SVOp->isSplat()) {
6436 unsigned NumElem = VT.getVectorNumElements();
6437 int Size = VT.getSizeInBits();
6439 // Use vbroadcast whenever the splat comes from a foldable load
6440 SDValue Broadcast = LowerVectorBroadcast(Op, DAG);
6441 if (Broadcast.getNode())
6444 // Handle splats by matching through known shuffle masks
6445 if ((Size == 128 && NumElem <= 4) ||
6446 (Size == 256 && NumElem < 8))
6449 // All remaning splats are promoted to target supported vector shuffles.
6450 return PromoteSplat(SVOp, DAG);
6453 // If the shuffle can be profitably rewritten as a narrower shuffle, then
6455 if (VT == MVT::v8i16 || VT == MVT::v16i8 ||
6456 VT == MVT::v16i16 || VT == MVT::v32i8) {
6457 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6458 if (NewOp.getNode())
6459 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
6460 } else if ((VT == MVT::v4i32 ||
6461 (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
6462 // FIXME: Figure out a cleaner way to do this.
6463 // Try to make use of movq to zero out the top part.
6464 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
6465 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6466 if (NewOp.getNode()) {
6467 EVT NewVT = NewOp.getValueType();
6468 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
6469 NewVT, true, false))
6470 return getVZextMovL(VT, NewVT, NewOp.getOperand(0),
6471 DAG, Subtarget, dl);
6473 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
6474 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6475 if (NewOp.getNode()) {
6476 EVT NewVT = NewOp.getValueType();
6477 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
6478 return getVZextMovL(VT, NewVT, NewOp.getOperand(1),
6479 DAG, Subtarget, dl);
6487 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
6488 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6489 SDValue V1 = Op.getOperand(0);
6490 SDValue V2 = Op.getOperand(1);
6491 EVT VT = Op.getValueType();
6492 DebugLoc dl = Op.getDebugLoc();
6493 unsigned NumElems = VT.getVectorNumElements();
6494 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
6495 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
6496 bool V1IsSplat = false;
6497 bool V2IsSplat = false;
6498 bool HasSSE2 = Subtarget->hasSSE2();
6499 bool HasAVX = Subtarget->hasAVX();
6500 bool HasAVX2 = Subtarget->hasAVX2();
6501 MachineFunction &MF = DAG.getMachineFunction();
6502 bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize);
6504 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
6506 if (V1IsUndef && V2IsUndef)
6507 return DAG.getUNDEF(VT);
6509 assert(!V1IsUndef && "Op 1 of shuffle should not be undef");
6511 // Vector shuffle lowering takes 3 steps:
6513 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
6514 // narrowing and commutation of operands should be handled.
6515 // 2) Matching of shuffles with known shuffle masks to x86 target specific
6517 // 3) Rewriting of unmatched masks into new generic shuffle operations,
6518 // so the shuffle can be broken into other shuffles and the legalizer can
6519 // try the lowering again.
6521 // The general idea is that no vector_shuffle operation should be left to
6522 // be matched during isel, all of them must be converted to a target specific
6525 // Normalize the input vectors. Here splats, zeroed vectors, profitable
6526 // narrowing and commutation of operands should be handled. The actual code
6527 // doesn't include all of those, work in progress...
6528 SDValue NewOp = NormalizeVectorShuffle(Op, DAG);
6529 if (NewOp.getNode())
6532 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
6534 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
6535 // unpckh_undef). Only use pshufd if speed is more important than size.
6536 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasAVX2))
6537 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6538 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasAVX2))
6539 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6541 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
6542 V2IsUndef && RelaxedMayFoldVectorLoad(V1))
6543 return getMOVDDup(Op, dl, V1, DAG);
6545 if (isMOVHLPS_v_undef_Mask(M, VT))
6546 return getMOVHighToLow(Op, dl, DAG);
6548 // Use to match splats
6549 if (HasSSE2 && isUNPCKHMask(M, VT, HasAVX2) && V2IsUndef &&
6550 (VT == MVT::v2f64 || VT == MVT::v2i64))
6551 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6553 if (isPSHUFDMask(M, VT)) {
6554 // The actual implementation will match the mask in the if above and then
6555 // during isel it can match several different instructions, not only pshufd
6556 // as its name says, sad but true, emulate the behavior for now...
6557 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
6558 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
6560 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
6562 if (HasAVX && (VT == MVT::v4f32 || VT == MVT::v2f64))
6563 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, TargetMask, DAG);
6565 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
6566 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
6568 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
6572 // Check if this can be converted into a logical shift.
6573 bool isLeft = false;
6576 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
6577 if (isShift && ShVal.hasOneUse()) {
6578 // If the shifted value has multiple uses, it may be cheaper to use
6579 // v_set0 + movlhps or movhlps, etc.
6580 EVT EltVT = VT.getVectorElementType();
6581 ShAmt *= EltVT.getSizeInBits();
6582 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6585 if (isMOVLMask(M, VT)) {
6586 if (ISD::isBuildVectorAllZeros(V1.getNode()))
6587 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
6588 if (!isMOVLPMask(M, VT)) {
6589 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
6590 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6592 if (VT == MVT::v4i32 || VT == MVT::v4f32)
6593 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6597 // FIXME: fold these into legal mask.
6598 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasAVX2))
6599 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
6601 if (isMOVHLPSMask(M, VT))
6602 return getMOVHighToLow(Op, dl, DAG);
6604 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
6605 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
6607 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
6608 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
6610 if (isMOVLPMask(M, VT))
6611 return getMOVLP(Op, dl, DAG, HasSSE2);
6613 if (ShouldXformToMOVHLPS(M, VT) ||
6614 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
6615 return CommuteVectorShuffle(SVOp, DAG);
6618 // No better options. Use a vshldq / vsrldq.
6619 EVT EltVT = VT.getVectorElementType();
6620 ShAmt *= EltVT.getSizeInBits();
6621 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6624 bool Commuted = false;
6625 // FIXME: This should also accept a bitcast of a splat? Be careful, not
6626 // 1,1,1,1 -> v8i16 though.
6627 V1IsSplat = isSplatVector(V1.getNode());
6628 V2IsSplat = isSplatVector(V2.getNode());
6630 // Canonicalize the splat or undef, if present, to be on the RHS.
6631 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
6632 CommuteVectorShuffleMask(M, NumElems);
6634 std::swap(V1IsSplat, V2IsSplat);
6638 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
6639 // Shuffling low element of v1 into undef, just return v1.
6642 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
6643 // the instruction selector will not match, so get a canonical MOVL with
6644 // swapped operands to undo the commute.
6645 return getMOVL(DAG, dl, VT, V2, V1);
6648 if (isUNPCKLMask(M, VT, HasAVX2))
6649 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6651 if (isUNPCKHMask(M, VT, HasAVX2))
6652 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6655 // Normalize mask so all entries that point to V2 points to its first
6656 // element then try to match unpck{h|l} again. If match, return a
6657 // new vector_shuffle with the corrected mask.p
6658 SmallVector<int, 8> NewMask(M.begin(), M.end());
6659 NormalizeMask(NewMask, NumElems);
6660 if (isUNPCKLMask(NewMask, VT, HasAVX2, true))
6661 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6662 if (isUNPCKHMask(NewMask, VT, HasAVX2, true))
6663 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6667 // Commute is back and try unpck* again.
6668 // FIXME: this seems wrong.
6669 CommuteVectorShuffleMask(M, NumElems);
6671 std::swap(V1IsSplat, V2IsSplat);
6674 if (isUNPCKLMask(M, VT, HasAVX2))
6675 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6677 if (isUNPCKHMask(M, VT, HasAVX2))
6678 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6681 // Normalize the node to match x86 shuffle ops if needed
6682 if (!V2IsUndef && (isSHUFPMask(M, VT, HasAVX, /* Commuted */ true)))
6683 return CommuteVectorShuffle(SVOp, DAG);
6685 // The checks below are all present in isShuffleMaskLegal, but they are
6686 // inlined here right now to enable us to directly emit target specific
6687 // nodes, and remove one by one until they don't return Op anymore.
6689 if (isPALIGNRMask(M, VT, Subtarget))
6690 return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2,
6691 getShufflePALIGNRImmediate(SVOp),
6694 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
6695 SVOp->getSplatIndex() == 0 && V2IsUndef) {
6696 if (VT == MVT::v2f64 || VT == MVT::v2i64)
6697 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6700 if (isPSHUFHWMask(M, VT, HasAVX2))
6701 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
6702 getShufflePSHUFHWImmediate(SVOp),
6705 if (isPSHUFLWMask(M, VT, HasAVX2))
6706 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
6707 getShufflePSHUFLWImmediate(SVOp),
6710 if (isSHUFPMask(M, VT, HasAVX))
6711 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
6712 getShuffleSHUFImmediate(SVOp), DAG);
6714 if (isUNPCKL_v_undef_Mask(M, VT, HasAVX2))
6715 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6716 if (isUNPCKH_v_undef_Mask(M, VT, HasAVX2))
6717 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6719 //===--------------------------------------------------------------------===//
6720 // Generate target specific nodes for 128 or 256-bit shuffles only
6721 // supported in the AVX instruction set.
6724 // Handle VMOVDDUPY permutations
6725 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasAVX))
6726 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
6728 // Handle VPERMILPS/D* permutations
6729 if (isVPERMILPMask(M, VT, HasAVX)) {
6730 if (HasAVX2 && VT == MVT::v8i32)
6731 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
6732 getShuffleSHUFImmediate(SVOp), DAG);
6733 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1,
6734 getShuffleSHUFImmediate(SVOp), DAG);
6737 // Handle VPERM2F128/VPERM2I128 permutations
6738 if (isVPERM2X128Mask(M, VT, HasAVX))
6739 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
6740 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
6742 SDValue BlendOp = LowerVECTOR_SHUFFLEtoBlend(SVOp, Subtarget, DAG);
6743 if (BlendOp.getNode())
6746 if (V2IsUndef && HasAVX2 && (VT == MVT::v8i32 || VT == MVT::v8f32)) {
6747 SmallVector<SDValue, 8> permclMask;
6748 for (unsigned i = 0; i != 8; ++i) {
6749 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MVT::i32));
6751 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32,
6753 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
6754 return DAG.getNode(X86ISD::VPERMV, dl, VT,
6755 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
6758 if (V2IsUndef && HasAVX2 && (VT == MVT::v4i64 || VT == MVT::v4f64))
6759 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1,
6760 getShuffleCLImmediate(SVOp), DAG);
6763 //===--------------------------------------------------------------------===//
6764 // Since no target specific shuffle was selected for this generic one,
6765 // lower it into other known shuffles. FIXME: this isn't true yet, but
6766 // this is the plan.
6769 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
6770 if (VT == MVT::v8i16) {
6771 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, DAG);
6772 if (NewOp.getNode())
6776 if (VT == MVT::v16i8) {
6777 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
6778 if (NewOp.getNode())
6782 // Handle all 128-bit wide vectors with 4 elements, and match them with
6783 // several different shuffle types.
6784 if (NumElems == 4 && VT.is128BitVector())
6785 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
6787 // Handle general 256-bit shuffles
6788 if (VT.is256BitVector())
6789 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
6795 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
6796 SelectionDAG &DAG) const {
6797 EVT VT = Op.getValueType();
6798 DebugLoc dl = Op.getDebugLoc();
6800 if (!Op.getOperand(0).getValueType().is128BitVector())
6803 if (VT.getSizeInBits() == 8) {
6804 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
6805 Op.getOperand(0), Op.getOperand(1));
6806 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6807 DAG.getValueType(VT));
6808 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6811 if (VT.getSizeInBits() == 16) {
6812 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6813 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
6815 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6816 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6817 DAG.getNode(ISD::BITCAST, dl,
6821 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
6822 Op.getOperand(0), Op.getOperand(1));
6823 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6824 DAG.getValueType(VT));
6825 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6828 if (VT == MVT::f32) {
6829 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
6830 // the result back to FR32 register. It's only worth matching if the
6831 // result has a single use which is a store or a bitcast to i32. And in
6832 // the case of a store, it's not worth it if the index is a constant 0,
6833 // because a MOVSSmr can be used instead, which is smaller and faster.
6834 if (!Op.hasOneUse())
6836 SDNode *User = *Op.getNode()->use_begin();
6837 if ((User->getOpcode() != ISD::STORE ||
6838 (isa<ConstantSDNode>(Op.getOperand(1)) &&
6839 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
6840 (User->getOpcode() != ISD::BITCAST ||
6841 User->getValueType(0) != MVT::i32))
6843 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6844 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
6847 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
6850 if (VT == MVT::i32 || VT == MVT::i64) {
6851 // ExtractPS/pextrq works with constant index.
6852 if (isa<ConstantSDNode>(Op.getOperand(1)))
6860 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
6861 SelectionDAG &DAG) const {
6862 if (!isa<ConstantSDNode>(Op.getOperand(1)))
6865 SDValue Vec = Op.getOperand(0);
6866 EVT VecVT = Vec.getValueType();
6868 // If this is a 256-bit vector result, first extract the 128-bit vector and
6869 // then extract the element from the 128-bit vector.
6870 if (VecVT.is256BitVector()) {
6871 DebugLoc dl = Op.getNode()->getDebugLoc();
6872 unsigned NumElems = VecVT.getVectorNumElements();
6873 SDValue Idx = Op.getOperand(1);
6874 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
6876 // Get the 128-bit vector.
6877 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
6879 if (IdxVal >= NumElems/2)
6880 IdxVal -= NumElems/2;
6881 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
6882 DAG.getConstant(IdxVal, MVT::i32));
6885 assert(VecVT.is128BitVector() && "Unexpected vector length");
6887 if (Subtarget->hasSSE41()) {
6888 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
6893 EVT VT = Op.getValueType();
6894 DebugLoc dl = Op.getDebugLoc();
6895 // TODO: handle v16i8.
6896 if (VT.getSizeInBits() == 16) {
6897 SDValue Vec = Op.getOperand(0);
6898 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6900 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6901 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6902 DAG.getNode(ISD::BITCAST, dl,
6905 // Transform it so it match pextrw which produces a 32-bit result.
6906 EVT EltVT = MVT::i32;
6907 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
6908 Op.getOperand(0), Op.getOperand(1));
6909 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
6910 DAG.getValueType(VT));
6911 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6914 if (VT.getSizeInBits() == 32) {
6915 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6919 // SHUFPS the element to the lowest double word, then movss.
6920 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
6921 EVT VVT = Op.getOperand(0).getValueType();
6922 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6923 DAG.getUNDEF(VVT), Mask);
6924 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6925 DAG.getIntPtrConstant(0));
6928 if (VT.getSizeInBits() == 64) {
6929 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
6930 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
6931 // to match extract_elt for f64.
6932 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6936 // UNPCKHPD the element to the lowest double word, then movsd.
6937 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
6938 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
6939 int Mask[2] = { 1, -1 };
6940 EVT VVT = Op.getOperand(0).getValueType();
6941 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6942 DAG.getUNDEF(VVT), Mask);
6943 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6944 DAG.getIntPtrConstant(0));
6951 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op,
6952 SelectionDAG &DAG) const {
6953 EVT VT = Op.getValueType();
6954 EVT EltVT = VT.getVectorElementType();
6955 DebugLoc dl = Op.getDebugLoc();
6957 SDValue N0 = Op.getOperand(0);
6958 SDValue N1 = Op.getOperand(1);
6959 SDValue N2 = Op.getOperand(2);
6961 if (!VT.is128BitVector())
6964 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
6965 isa<ConstantSDNode>(N2)) {
6967 if (VT == MVT::v8i16)
6968 Opc = X86ISD::PINSRW;
6969 else if (VT == MVT::v16i8)
6970 Opc = X86ISD::PINSRB;
6972 Opc = X86ISD::PINSRB;
6974 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
6976 if (N1.getValueType() != MVT::i32)
6977 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
6978 if (N2.getValueType() != MVT::i32)
6979 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
6980 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
6983 if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
6984 // Bits [7:6] of the constant are the source select. This will always be
6985 // zero here. The DAG Combiner may combine an extract_elt index into these
6986 // bits. For example (insert (extract, 3), 2) could be matched by putting
6987 // the '3' into bits [7:6] of X86ISD::INSERTPS.
6988 // Bits [5:4] of the constant are the destination select. This is the
6989 // value of the incoming immediate.
6990 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
6991 // combine either bitwise AND or insert of float 0.0 to set these bits.
6992 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
6993 // Create this as a scalar to vector..
6994 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
6995 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
6998 if ((EltVT == MVT::i32 || EltVT == MVT::i64) && isa<ConstantSDNode>(N2)) {
6999 // PINSR* works with constant index.
7006 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
7007 EVT VT = Op.getValueType();
7008 EVT EltVT = VT.getVectorElementType();
7010 DebugLoc dl = Op.getDebugLoc();
7011 SDValue N0 = Op.getOperand(0);
7012 SDValue N1 = Op.getOperand(1);
7013 SDValue N2 = Op.getOperand(2);
7015 // If this is a 256-bit vector result, first extract the 128-bit vector,
7016 // insert the element into the extracted half and then place it back.
7017 if (VT.is256BitVector()) {
7018 if (!isa<ConstantSDNode>(N2))
7021 // Get the desired 128-bit vector half.
7022 unsigned NumElems = VT.getVectorNumElements();
7023 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue();
7024 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
7026 // Insert the element into the desired half.
7027 bool Upper = IdxVal >= NumElems/2;
7028 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
7029 DAG.getConstant(Upper ? IdxVal-NumElems/2 : IdxVal, MVT::i32));
7031 // Insert the changed part back to the 256-bit vector
7032 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
7035 if (Subtarget->hasSSE41())
7036 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
7038 if (EltVT == MVT::i8)
7041 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
7042 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
7043 // as its second argument.
7044 if (N1.getValueType() != MVT::i32)
7045 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
7046 if (N2.getValueType() != MVT::i32)
7047 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
7048 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
7054 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const {
7055 LLVMContext *Context = DAG.getContext();
7056 DebugLoc dl = Op.getDebugLoc();
7057 EVT OpVT = Op.getValueType();
7059 // If this is a 256-bit vector result, first insert into a 128-bit
7060 // vector and then insert into the 256-bit vector.
7061 if (!OpVT.is128BitVector()) {
7062 // Insert into a 128-bit vector.
7063 EVT VT128 = EVT::getVectorVT(*Context,
7064 OpVT.getVectorElementType(),
7065 OpVT.getVectorNumElements() / 2);
7067 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
7069 // Insert the 128-bit vector.
7070 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
7073 if (OpVT == MVT::v1i64 &&
7074 Op.getOperand(0).getValueType() == MVT::i64)
7075 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
7077 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
7078 assert(OpVT.is128BitVector() && "Expected an SSE type!");
7079 return DAG.getNode(ISD::BITCAST, dl, OpVT,
7080 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
7083 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
7084 // a simple subregister reference or explicit instructions to grab
7085 // upper bits of a vector.
7087 X86TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
7088 if (Subtarget->hasAVX()) {
7089 DebugLoc dl = Op.getNode()->getDebugLoc();
7090 SDValue Vec = Op.getNode()->getOperand(0);
7091 SDValue Idx = Op.getNode()->getOperand(1);
7093 if (Op.getNode()->getValueType(0).is128BitVector() &&
7094 Vec.getNode()->getValueType(0).is256BitVector() &&
7095 isa<ConstantSDNode>(Idx)) {
7096 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7097 return Extract128BitVector(Vec, IdxVal, DAG, dl);
7103 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
7104 // simple superregister reference or explicit instructions to insert
7105 // the upper bits of a vector.
7107 X86TargetLowering::LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
7108 if (Subtarget->hasAVX()) {
7109 DebugLoc dl = Op.getNode()->getDebugLoc();
7110 SDValue Vec = Op.getNode()->getOperand(0);
7111 SDValue SubVec = Op.getNode()->getOperand(1);
7112 SDValue Idx = Op.getNode()->getOperand(2);
7114 if (Op.getNode()->getValueType(0).is256BitVector() &&
7115 SubVec.getNode()->getValueType(0).is128BitVector() &&
7116 isa<ConstantSDNode>(Idx)) {
7117 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7118 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
7124 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
7125 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
7126 // one of the above mentioned nodes. It has to be wrapped because otherwise
7127 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
7128 // be used to form addressing mode. These wrapped nodes will be selected
7131 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
7132 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
7134 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7136 unsigned char OpFlag = 0;
7137 unsigned WrapperKind = X86ISD::Wrapper;
7138 CodeModel::Model M = getTargetMachine().getCodeModel();
7140 if (Subtarget->isPICStyleRIPRel() &&
7141 (M == CodeModel::Small || M == CodeModel::Kernel))
7142 WrapperKind = X86ISD::WrapperRIP;
7143 else if (Subtarget->isPICStyleGOT())
7144 OpFlag = X86II::MO_GOTOFF;
7145 else if (Subtarget->isPICStyleStubPIC())
7146 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7148 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
7150 CP->getOffset(), OpFlag);
7151 DebugLoc DL = CP->getDebugLoc();
7152 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7153 // With PIC, the address is actually $g + Offset.
7155 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7156 DAG.getNode(X86ISD::GlobalBaseReg,
7157 DebugLoc(), getPointerTy()),
7164 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
7165 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
7167 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7169 unsigned char OpFlag = 0;
7170 unsigned WrapperKind = X86ISD::Wrapper;
7171 CodeModel::Model M = getTargetMachine().getCodeModel();
7173 if (Subtarget->isPICStyleRIPRel() &&
7174 (M == CodeModel::Small || M == CodeModel::Kernel))
7175 WrapperKind = X86ISD::WrapperRIP;
7176 else if (Subtarget->isPICStyleGOT())
7177 OpFlag = X86II::MO_GOTOFF;
7178 else if (Subtarget->isPICStyleStubPIC())
7179 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7181 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
7183 DebugLoc DL = JT->getDebugLoc();
7184 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7186 // With PIC, the address is actually $g + Offset.
7188 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7189 DAG.getNode(X86ISD::GlobalBaseReg,
7190 DebugLoc(), getPointerTy()),
7197 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
7198 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
7200 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7202 unsigned char OpFlag = 0;
7203 unsigned WrapperKind = X86ISD::Wrapper;
7204 CodeModel::Model M = getTargetMachine().getCodeModel();
7206 if (Subtarget->isPICStyleRIPRel() &&
7207 (M == CodeModel::Small || M == CodeModel::Kernel)) {
7208 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
7209 OpFlag = X86II::MO_GOTPCREL;
7210 WrapperKind = X86ISD::WrapperRIP;
7211 } else if (Subtarget->isPICStyleGOT()) {
7212 OpFlag = X86II::MO_GOT;
7213 } else if (Subtarget->isPICStyleStubPIC()) {
7214 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
7215 } else if (Subtarget->isPICStyleStubNoDynamic()) {
7216 OpFlag = X86II::MO_DARWIN_NONLAZY;
7219 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
7221 DebugLoc DL = Op.getDebugLoc();
7222 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7225 // With PIC, the address is actually $g + Offset.
7226 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
7227 !Subtarget->is64Bit()) {
7228 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7229 DAG.getNode(X86ISD::GlobalBaseReg,
7230 DebugLoc(), getPointerTy()),
7234 // For symbols that require a load from a stub to get the address, emit the
7236 if (isGlobalStubReference(OpFlag))
7237 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
7238 MachinePointerInfo::getGOT(), false, false, false, 0);
7244 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
7245 // Create the TargetBlockAddressAddress node.
7246 unsigned char OpFlags =
7247 Subtarget->ClassifyBlockAddressReference();
7248 CodeModel::Model M = getTargetMachine().getCodeModel();
7249 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
7250 DebugLoc dl = Op.getDebugLoc();
7251 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(),
7252 /*isTarget=*/true, OpFlags);
7254 if (Subtarget->isPICStyleRIPRel() &&
7255 (M == CodeModel::Small || M == CodeModel::Kernel))
7256 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7258 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7260 // With PIC, the address is actually $g + Offset.
7261 if (isGlobalRelativeToPICBase(OpFlags)) {
7262 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7263 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7271 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
7273 SelectionDAG &DAG) const {
7274 // Create the TargetGlobalAddress node, folding in the constant
7275 // offset if it is legal.
7276 unsigned char OpFlags =
7277 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
7278 CodeModel::Model M = getTargetMachine().getCodeModel();
7280 if (OpFlags == X86II::MO_NO_FLAG &&
7281 X86::isOffsetSuitableForCodeModel(Offset, M)) {
7282 // A direct static reference to a global.
7283 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
7286 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
7289 if (Subtarget->isPICStyleRIPRel() &&
7290 (M == CodeModel::Small || M == CodeModel::Kernel))
7291 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7293 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7295 // With PIC, the address is actually $g + Offset.
7296 if (isGlobalRelativeToPICBase(OpFlags)) {
7297 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7298 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7302 // For globals that require a load from a stub to get the address, emit the
7304 if (isGlobalStubReference(OpFlags))
7305 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
7306 MachinePointerInfo::getGOT(), false, false, false, 0);
7308 // If there was a non-zero offset that we didn't fold, create an explicit
7311 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
7312 DAG.getConstant(Offset, getPointerTy()));
7318 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
7319 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
7320 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
7321 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
7325 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
7326 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
7327 unsigned char OperandFlags, bool LocalDynamic = false) {
7328 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7329 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7330 DebugLoc dl = GA->getDebugLoc();
7331 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7332 GA->getValueType(0),
7336 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
7340 SDValue Ops[] = { Chain, TGA, *InFlag };
7341 Chain = DAG.getNode(CallType, dl, NodeTys, Ops, 3);
7343 SDValue Ops[] = { Chain, TGA };
7344 Chain = DAG.getNode(CallType, dl, NodeTys, Ops, 2);
7347 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
7348 MFI->setAdjustsStack(true);
7350 SDValue Flag = Chain.getValue(1);
7351 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
7354 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
7356 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7359 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
7360 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
7361 DAG.getNode(X86ISD::GlobalBaseReg,
7362 DebugLoc(), PtrVT), InFlag);
7363 InFlag = Chain.getValue(1);
7365 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
7368 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
7370 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7372 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
7373 X86::RAX, X86II::MO_TLSGD);
7376 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
7380 DebugLoc dl = GA->getDebugLoc();
7382 // Get the start address of the TLS block for this module.
7383 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
7384 .getInfo<X86MachineFunctionInfo>();
7385 MFI->incNumLocalDynamicTLSAccesses();
7389 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT, X86::RAX,
7390 X86II::MO_TLSLD, /*LocalDynamic=*/true);
7393 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
7394 DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), PtrVT), InFlag);
7395 InFlag = Chain.getValue(1);
7396 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
7397 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
7400 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
7404 unsigned char OperandFlags = X86II::MO_DTPOFF;
7405 unsigned WrapperKind = X86ISD::Wrapper;
7406 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7407 GA->getValueType(0),
7408 GA->getOffset(), OperandFlags);
7409 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
7411 // Add x@dtpoff with the base.
7412 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
7415 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
7416 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7417 const EVT PtrVT, TLSModel::Model model,
7418 bool is64Bit, bool isPIC) {
7419 DebugLoc dl = GA->getDebugLoc();
7421 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
7422 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
7423 is64Bit ? 257 : 256));
7425 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
7426 DAG.getIntPtrConstant(0),
7427 MachinePointerInfo(Ptr),
7428 false, false, false, 0);
7430 unsigned char OperandFlags = 0;
7431 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
7433 unsigned WrapperKind = X86ISD::Wrapper;
7434 if (model == TLSModel::LocalExec) {
7435 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
7436 } else if (model == TLSModel::InitialExec) {
7438 OperandFlags = X86II::MO_GOTTPOFF;
7439 WrapperKind = X86ISD::WrapperRIP;
7441 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
7444 llvm_unreachable("Unexpected model");
7447 // emit "addl x@ntpoff,%eax" (local exec)
7448 // or "addl x@indntpoff,%eax" (initial exec)
7449 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
7450 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7451 GA->getValueType(0),
7452 GA->getOffset(), OperandFlags);
7453 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
7455 if (model == TLSModel::InitialExec) {
7456 if (isPIC && !is64Bit) {
7457 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
7458 DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), PtrVT),
7462 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
7463 MachinePointerInfo::getGOT(), false, false, false,
7467 // The address of the thread local variable is the add of the thread
7468 // pointer with the offset of the variable.
7469 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
7473 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
7475 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
7476 const GlobalValue *GV = GA->getGlobal();
7478 if (Subtarget->isTargetELF()) {
7479 TLSModel::Model model = getTargetMachine().getTLSModel(GV);
7482 case TLSModel::GeneralDynamic:
7483 if (Subtarget->is64Bit())
7484 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
7485 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
7486 case TLSModel::LocalDynamic:
7487 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
7488 Subtarget->is64Bit());
7489 case TLSModel::InitialExec:
7490 case TLSModel::LocalExec:
7491 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
7492 Subtarget->is64Bit(),
7493 getTargetMachine().getRelocationModel() == Reloc::PIC_);
7495 llvm_unreachable("Unknown TLS model.");
7498 if (Subtarget->isTargetDarwin()) {
7499 // Darwin only has one model of TLS. Lower to that.
7500 unsigned char OpFlag = 0;
7501 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
7502 X86ISD::WrapperRIP : X86ISD::Wrapper;
7504 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7506 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
7507 !Subtarget->is64Bit();
7509 OpFlag = X86II::MO_TLVP_PIC_BASE;
7511 OpFlag = X86II::MO_TLVP;
7512 DebugLoc DL = Op.getDebugLoc();
7513 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
7514 GA->getValueType(0),
7515 GA->getOffset(), OpFlag);
7516 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7518 // With PIC32, the address is actually $g + Offset.
7520 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7521 DAG.getNode(X86ISD::GlobalBaseReg,
7522 DebugLoc(), getPointerTy()),
7525 // Lowering the machine isd will make sure everything is in the right
7527 SDValue Chain = DAG.getEntryNode();
7528 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7529 SDValue Args[] = { Chain, Offset };
7530 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2);
7532 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
7533 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7534 MFI->setAdjustsStack(true);
7536 // And our return value (tls address) is in the standard call return value
7538 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
7539 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
7543 if (Subtarget->isTargetWindows()) {
7544 // Just use the implicit TLS architecture
7545 // Need to generate someting similar to:
7546 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
7548 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
7549 // mov rcx, qword [rdx+rcx*8]
7550 // mov eax, .tls$:tlsvar
7551 // [rax+rcx] contains the address
7552 // Windows 64bit: gs:0x58
7553 // Windows 32bit: fs:__tls_array
7555 // If GV is an alias then use the aliasee for determining
7556 // thread-localness.
7557 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
7558 GV = GA->resolveAliasedGlobal(false);
7559 DebugLoc dl = GA->getDebugLoc();
7560 SDValue Chain = DAG.getEntryNode();
7562 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
7563 // %gs:0x58 (64-bit).
7564 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
7565 ? Type::getInt8PtrTy(*DAG.getContext(),
7567 : Type::getInt32PtrTy(*DAG.getContext(),
7570 SDValue ThreadPointer = DAG.getLoad(getPointerTy(), dl, Chain,
7571 Subtarget->is64Bit()
7572 ? DAG.getIntPtrConstant(0x58)
7573 : DAG.getExternalSymbol("_tls_array",
7575 MachinePointerInfo(Ptr),
7576 false, false, false, 0);
7578 // Load the _tls_index variable
7579 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
7580 if (Subtarget->is64Bit())
7581 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
7582 IDX, MachinePointerInfo(), MVT::i32,
7585 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
7586 false, false, false, 0);
7588 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
7590 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
7592 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
7593 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
7594 false, false, false, 0);
7596 // Get the offset of start of .tls section
7597 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7598 GA->getValueType(0),
7599 GA->getOffset(), X86II::MO_SECREL);
7600 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
7602 // The address of the thread local variable is the add of the thread
7603 // pointer with the offset of the variable.
7604 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
7607 llvm_unreachable("TLS not implemented for this target.");
7611 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
7612 /// and take a 2 x i32 value to shift plus a shift amount.
7613 SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const{
7614 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
7615 EVT VT = Op.getValueType();
7616 unsigned VTBits = VT.getSizeInBits();
7617 DebugLoc dl = Op.getDebugLoc();
7618 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
7619 SDValue ShOpLo = Op.getOperand(0);
7620 SDValue ShOpHi = Op.getOperand(1);
7621 SDValue ShAmt = Op.getOperand(2);
7622 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
7623 DAG.getConstant(VTBits - 1, MVT::i8))
7624 : DAG.getConstant(0, VT);
7627 if (Op.getOpcode() == ISD::SHL_PARTS) {
7628 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
7629 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
7631 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
7632 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
7635 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
7636 DAG.getConstant(VTBits, MVT::i8));
7637 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
7638 AndNode, DAG.getConstant(0, MVT::i8));
7641 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
7642 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
7643 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
7645 if (Op.getOpcode() == ISD::SHL_PARTS) {
7646 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7647 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7649 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7650 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7653 SDValue Ops[2] = { Lo, Hi };
7654 return DAG.getMergeValues(Ops, 2, dl);
7657 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
7658 SelectionDAG &DAG) const {
7659 EVT SrcVT = Op.getOperand(0).getValueType();
7661 if (SrcVT.isVector())
7664 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
7665 "Unknown SINT_TO_FP to lower!");
7667 // These are really Legal; return the operand so the caller accepts it as
7669 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
7671 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
7672 Subtarget->is64Bit()) {
7676 DebugLoc dl = Op.getDebugLoc();
7677 unsigned Size = SrcVT.getSizeInBits()/8;
7678 MachineFunction &MF = DAG.getMachineFunction();
7679 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
7680 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7681 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7683 MachinePointerInfo::getFixedStack(SSFI),
7685 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
7688 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
7690 SelectionDAG &DAG) const {
7692 DebugLoc DL = Op.getDebugLoc();
7694 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
7696 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
7698 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
7700 unsigned ByteSize = SrcVT.getSizeInBits()/8;
7702 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
7703 MachineMemOperand *MMO;
7705 int SSFI = FI->getIndex();
7707 DAG.getMachineFunction()
7708 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7709 MachineMemOperand::MOLoad, ByteSize, ByteSize);
7711 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
7712 StackSlot = StackSlot.getOperand(1);
7714 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
7715 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
7717 Tys, Ops, array_lengthof(Ops),
7721 Chain = Result.getValue(1);
7722 SDValue InFlag = Result.getValue(2);
7724 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
7725 // shouldn't be necessary except that RFP cannot be live across
7726 // multiple blocks. When stackifier is fixed, they can be uncoupled.
7727 MachineFunction &MF = DAG.getMachineFunction();
7728 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
7729 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
7730 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7731 Tys = DAG.getVTList(MVT::Other);
7733 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
7735 MachineMemOperand *MMO =
7736 DAG.getMachineFunction()
7737 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7738 MachineMemOperand::MOStore, SSFISize, SSFISize);
7740 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
7741 Ops, array_lengthof(Ops),
7742 Op.getValueType(), MMO);
7743 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
7744 MachinePointerInfo::getFixedStack(SSFI),
7745 false, false, false, 0);
7751 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
7752 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
7753 SelectionDAG &DAG) const {
7754 // This algorithm is not obvious. Here it is what we're trying to output:
7757 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
7758 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
7762 pshufd $0x4e, %xmm0, %xmm1
7767 DebugLoc dl = Op.getDebugLoc();
7768 LLVMContext *Context = DAG.getContext();
7770 // Build some magic constants.
7771 const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
7772 Constant *C0 = ConstantDataVector::get(*Context, CV0);
7773 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
7775 SmallVector<Constant*,2> CV1;
7777 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL))));
7779 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL))));
7780 Constant *C1 = ConstantVector::get(CV1);
7781 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
7783 // Load the 64-bit value into an XMM register.
7784 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
7786 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
7787 MachinePointerInfo::getConstantPool(),
7788 false, false, false, 16);
7789 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
7790 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
7793 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
7794 MachinePointerInfo::getConstantPool(),
7795 false, false, false, 16);
7796 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
7797 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
7800 if (Subtarget->hasSSE3()) {
7801 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
7802 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
7804 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
7805 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
7807 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
7808 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
7812 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
7813 DAG.getIntPtrConstant(0));
7816 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
7817 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
7818 SelectionDAG &DAG) const {
7819 DebugLoc dl = Op.getDebugLoc();
7820 // FP constant to bias correct the final result.
7821 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
7824 // Load the 32-bit value into an XMM register.
7825 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
7828 // Zero out the upper parts of the register.
7829 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
7831 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7832 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
7833 DAG.getIntPtrConstant(0));
7835 // Or the load with the bias.
7836 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
7837 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7838 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7840 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7841 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7842 MVT::v2f64, Bias)));
7843 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7844 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
7845 DAG.getIntPtrConstant(0));
7847 // Subtract the bias.
7848 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
7850 // Handle final rounding.
7851 EVT DestVT = Op.getValueType();
7853 if (DestVT.bitsLT(MVT::f64))
7854 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
7855 DAG.getIntPtrConstant(0));
7856 if (DestVT.bitsGT(MVT::f64))
7857 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
7859 // Handle final rounding.
7863 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
7864 SelectionDAG &DAG) const {
7865 SDValue N0 = Op.getOperand(0);
7866 DebugLoc dl = Op.getDebugLoc();
7868 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
7869 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
7870 // the optimization here.
7871 if (DAG.SignBitIsZero(N0))
7872 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
7874 EVT SrcVT = N0.getValueType();
7875 EVT DstVT = Op.getValueType();
7876 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
7877 return LowerUINT_TO_FP_i64(Op, DAG);
7878 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
7879 return LowerUINT_TO_FP_i32(Op, DAG);
7880 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
7883 // Make a 64-bit buffer, and use it to build an FILD.
7884 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
7885 if (SrcVT == MVT::i32) {
7886 SDValue WordOff = DAG.getConstant(4, getPointerTy());
7887 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
7888 getPointerTy(), StackSlot, WordOff);
7889 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7890 StackSlot, MachinePointerInfo(),
7892 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
7893 OffsetSlot, MachinePointerInfo(),
7895 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
7899 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
7900 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7901 StackSlot, MachinePointerInfo(),
7903 // For i64 source, we need to add the appropriate power of 2 if the input
7904 // was negative. This is the same as the optimization in
7905 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
7906 // we must be careful to do the computation in x87 extended precision, not
7907 // in SSE. (The generic code can't know it's OK to do this, or how to.)
7908 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
7909 MachineMemOperand *MMO =
7910 DAG.getMachineFunction()
7911 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7912 MachineMemOperand::MOLoad, 8, 8);
7914 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
7915 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
7916 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, 3,
7919 APInt FF(32, 0x5F800000ULL);
7921 // Check whether the sign bit is set.
7922 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
7923 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
7926 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
7927 SDValue FudgePtr = DAG.getConstantPool(
7928 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
7931 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
7932 SDValue Zero = DAG.getIntPtrConstant(0);
7933 SDValue Four = DAG.getIntPtrConstant(4);
7934 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
7936 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
7938 // Load the value out, extending it from f32 to f80.
7939 // FIXME: Avoid the extend by constructing the right constant pool?
7940 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
7941 FudgePtr, MachinePointerInfo::getConstantPool(),
7942 MVT::f32, false, false, 4);
7943 // Extend everything to 80 bits to force it to be done on x87.
7944 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
7945 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
7948 std::pair<SDValue,SDValue> X86TargetLowering::
7949 FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned, bool IsReplace) const {
7950 DebugLoc DL = Op.getDebugLoc();
7952 EVT DstTy = Op.getValueType();
7954 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
7955 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
7959 assert(DstTy.getSimpleVT() <= MVT::i64 &&
7960 DstTy.getSimpleVT() >= MVT::i16 &&
7961 "Unknown FP_TO_INT to lower!");
7963 // These are really Legal.
7964 if (DstTy == MVT::i32 &&
7965 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
7966 return std::make_pair(SDValue(), SDValue());
7967 if (Subtarget->is64Bit() &&
7968 DstTy == MVT::i64 &&
7969 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
7970 return std::make_pair(SDValue(), SDValue());
7972 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
7973 // stack slot, or into the FTOL runtime function.
7974 MachineFunction &MF = DAG.getMachineFunction();
7975 unsigned MemSize = DstTy.getSizeInBits()/8;
7976 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
7977 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7980 if (!IsSigned && isIntegerTypeFTOL(DstTy))
7981 Opc = X86ISD::WIN_FTOL;
7983 switch (DstTy.getSimpleVT().SimpleTy) {
7984 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
7985 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
7986 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
7987 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
7990 SDValue Chain = DAG.getEntryNode();
7991 SDValue Value = Op.getOperand(0);
7992 EVT TheVT = Op.getOperand(0).getValueType();
7993 // FIXME This causes a redundant load/store if the SSE-class value is already
7994 // in memory, such as if it is on the callstack.
7995 if (isScalarFPTypeInSSEReg(TheVT)) {
7996 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
7997 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
7998 MachinePointerInfo::getFixedStack(SSFI),
8000 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
8002 Chain, StackSlot, DAG.getValueType(TheVT)
8005 MachineMemOperand *MMO =
8006 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8007 MachineMemOperand::MOLoad, MemSize, MemSize);
8008 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, 3,
8010 Chain = Value.getValue(1);
8011 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
8012 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8015 MachineMemOperand *MMO =
8016 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8017 MachineMemOperand::MOStore, MemSize, MemSize);
8019 if (Opc != X86ISD::WIN_FTOL) {
8020 // Build the FP_TO_INT*_IN_MEM
8021 SDValue Ops[] = { Chain, Value, StackSlot };
8022 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
8023 Ops, 3, DstTy, MMO);
8024 return std::make_pair(FIST, StackSlot);
8026 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
8027 DAG.getVTList(MVT::Other, MVT::Glue),
8029 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
8030 MVT::i32, ftol.getValue(1));
8031 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
8032 MVT::i32, eax.getValue(2));
8033 SDValue Ops[] = { eax, edx };
8034 SDValue pair = IsReplace
8035 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops, 2)
8036 : DAG.getMergeValues(Ops, 2, DL);
8037 return std::make_pair(pair, SDValue());
8041 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
8042 SelectionDAG &DAG) const {
8043 if (Op.getValueType().isVector())
8046 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
8047 /*IsSigned=*/ true, /*IsReplace=*/ false);
8048 SDValue FIST = Vals.first, StackSlot = Vals.second;
8049 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
8050 if (FIST.getNode() == 0) return Op;
8052 if (StackSlot.getNode())
8054 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
8055 FIST, StackSlot, MachinePointerInfo(),
8056 false, false, false, 0);
8058 // The node is the result.
8062 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
8063 SelectionDAG &DAG) const {
8064 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
8065 /*IsSigned=*/ false, /*IsReplace=*/ false);
8066 SDValue FIST = Vals.first, StackSlot = Vals.second;
8067 assert(FIST.getNode() && "Unexpected failure");
8069 if (StackSlot.getNode())
8071 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
8072 FIST, StackSlot, MachinePointerInfo(),
8073 false, false, false, 0);
8075 // The node is the result.
8079 SDValue X86TargetLowering::LowerFABS(SDValue Op,
8080 SelectionDAG &DAG) const {
8081 LLVMContext *Context = DAG.getContext();
8082 DebugLoc dl = Op.getDebugLoc();
8083 EVT VT = Op.getValueType();
8086 EltVT = VT.getVectorElementType();
8088 if (EltVT == MVT::f64) {
8089 C = ConstantVector::getSplat(2,
8090 ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
8092 C = ConstantVector::getSplat(4,
8093 ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
8095 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8096 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8097 MachinePointerInfo::getConstantPool(),
8098 false, false, false, 16);
8099 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
8102 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
8103 LLVMContext *Context = DAG.getContext();
8104 DebugLoc dl = Op.getDebugLoc();
8105 EVT VT = Op.getValueType();
8107 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
8108 if (VT.isVector()) {
8109 EltVT = VT.getVectorElementType();
8110 NumElts = VT.getVectorNumElements();
8113 if (EltVT == MVT::f64)
8114 C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)));
8116 C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)));
8117 C = ConstantVector::getSplat(NumElts, C);
8118 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8119 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8120 MachinePointerInfo::getConstantPool(),
8121 false, false, false, 16);
8122 if (VT.isVector()) {
8123 MVT XORVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
8124 return DAG.getNode(ISD::BITCAST, dl, VT,
8125 DAG.getNode(ISD::XOR, dl, XORVT,
8126 DAG.getNode(ISD::BITCAST, dl, XORVT,
8128 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask)));
8131 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
8134 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
8135 LLVMContext *Context = DAG.getContext();
8136 SDValue Op0 = Op.getOperand(0);
8137 SDValue Op1 = Op.getOperand(1);
8138 DebugLoc dl = Op.getDebugLoc();
8139 EVT VT = Op.getValueType();
8140 EVT SrcVT = Op1.getValueType();
8142 // If second operand is smaller, extend it first.
8143 if (SrcVT.bitsLT(VT)) {
8144 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
8147 // And if it is bigger, shrink it first.
8148 if (SrcVT.bitsGT(VT)) {
8149 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
8153 // At this point the operands and the result should have the same
8154 // type, and that won't be f80 since that is not custom lowered.
8156 // First get the sign bit of second operand.
8157 SmallVector<Constant*,4> CV;
8158 if (SrcVT == MVT::f64) {
8159 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))));
8160 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
8162 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))));
8163 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8164 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8165 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8167 Constant *C = ConstantVector::get(CV);
8168 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8169 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
8170 MachinePointerInfo::getConstantPool(),
8171 false, false, false, 16);
8172 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
8174 // Shift sign bit right or left if the two operands have different types.
8175 if (SrcVT.bitsGT(VT)) {
8176 // Op0 is MVT::f32, Op1 is MVT::f64.
8177 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
8178 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
8179 DAG.getConstant(32, MVT::i32));
8180 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
8181 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
8182 DAG.getIntPtrConstant(0));
8185 // Clear first operand sign bit.
8187 if (VT == MVT::f64) {
8188 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
8189 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
8191 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
8192 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8193 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8194 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8196 C = ConstantVector::get(CV);
8197 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8198 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8199 MachinePointerInfo::getConstantPool(),
8200 false, false, false, 16);
8201 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
8203 // Or the value with the sign bit.
8204 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
8207 SDValue X86TargetLowering::LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) const {
8208 SDValue N0 = Op.getOperand(0);
8209 DebugLoc dl = Op.getDebugLoc();
8210 EVT VT = Op.getValueType();
8212 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
8213 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
8214 DAG.getConstant(1, VT));
8215 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
8218 /// Emit nodes that will be selected as "test Op0,Op0", or something
8220 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
8221 SelectionDAG &DAG) const {
8222 DebugLoc dl = Op.getDebugLoc();
8224 // CF and OF aren't always set the way we want. Determine which
8225 // of these we need.
8226 bool NeedCF = false;
8227 bool NeedOF = false;
8230 case X86::COND_A: case X86::COND_AE:
8231 case X86::COND_B: case X86::COND_BE:
8234 case X86::COND_G: case X86::COND_GE:
8235 case X86::COND_L: case X86::COND_LE:
8236 case X86::COND_O: case X86::COND_NO:
8241 // See if we can use the EFLAGS value from the operand instead of
8242 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
8243 // we prove that the arithmetic won't overflow, we can't use OF or CF.
8244 if (Op.getResNo() != 0 || NeedOF || NeedCF)
8245 // Emit a CMP with 0, which is the TEST pattern.
8246 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8247 DAG.getConstant(0, Op.getValueType()));
8249 unsigned Opcode = 0;
8250 unsigned NumOperands = 0;
8251 switch (Op.getNode()->getOpcode()) {
8253 // Due to an isel shortcoming, be conservative if this add is likely to be
8254 // selected as part of a load-modify-store instruction. When the root node
8255 // in a match is a store, isel doesn't know how to remap non-chain non-flag
8256 // uses of other nodes in the match, such as the ADD in this case. This
8257 // leads to the ADD being left around and reselected, with the result being
8258 // two adds in the output. Alas, even if none our users are stores, that
8259 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
8260 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
8261 // climbing the DAG back to the root, and it doesn't seem to be worth the
8263 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8264 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8265 if (UI->getOpcode() != ISD::CopyToReg &&
8266 UI->getOpcode() != ISD::SETCC &&
8267 UI->getOpcode() != ISD::STORE)
8270 if (ConstantSDNode *C =
8271 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
8272 // An add of one will be selected as an INC.
8273 if (C->getAPIntValue() == 1) {
8274 Opcode = X86ISD::INC;
8279 // An add of negative one (subtract of one) will be selected as a DEC.
8280 if (C->getAPIntValue().isAllOnesValue()) {
8281 Opcode = X86ISD::DEC;
8287 // Otherwise use a regular EFLAGS-setting add.
8288 Opcode = X86ISD::ADD;
8292 // If the primary and result isn't used, don't bother using X86ISD::AND,
8293 // because a TEST instruction will be better.
8294 bool NonFlagUse = false;
8295 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8296 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
8298 unsigned UOpNo = UI.getOperandNo();
8299 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
8300 // Look pass truncate.
8301 UOpNo = User->use_begin().getOperandNo();
8302 User = *User->use_begin();
8305 if (User->getOpcode() != ISD::BRCOND &&
8306 User->getOpcode() != ISD::SETCC &&
8307 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) {
8320 // Due to the ISEL shortcoming noted above, be conservative if this op is
8321 // likely to be selected as part of a load-modify-store instruction.
8322 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8323 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8324 if (UI->getOpcode() == ISD::STORE)
8327 // Otherwise use a regular EFLAGS-setting instruction.
8328 switch (Op.getNode()->getOpcode()) {
8329 default: llvm_unreachable("unexpected operator!");
8331 Opcode = X86ISD::SUB;
8333 case ISD::OR: Opcode = X86ISD::OR; break;
8334 case ISD::XOR: Opcode = X86ISD::XOR; break;
8335 case ISD::AND: Opcode = X86ISD::AND; break;
8347 return SDValue(Op.getNode(), 1);
8354 // Emit a CMP with 0, which is the TEST pattern.
8355 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8356 DAG.getConstant(0, Op.getValueType()));
8358 if (Opcode == X86ISD::CMP) {
8359 SDValue New = DAG.getNode(Opcode, dl, MVT::i32, Op.getOperand(0),
8361 // We can't replace usage of SUB with CMP.
8362 // The SUB node will be removed later because there is no use of it.
8363 return SDValue(New.getNode(), 0);
8366 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
8367 SmallVector<SDValue, 4> Ops;
8368 for (unsigned i = 0; i != NumOperands; ++i)
8369 Ops.push_back(Op.getOperand(i));
8371 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
8372 DAG.ReplaceAllUsesWith(Op, New);
8373 return SDValue(New.getNode(), 1);
8376 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
8378 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
8379 SelectionDAG &DAG) const {
8380 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
8381 if (C->getAPIntValue() == 0)
8382 return EmitTest(Op0, X86CC, DAG);
8384 DebugLoc dl = Op0.getDebugLoc();
8385 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
8386 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
8387 // Use SUB instead of CMP to enable CSE between SUB and CMP.
8388 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
8389 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
8391 return SDValue(Sub.getNode(), 1);
8393 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
8396 /// Convert a comparison if required by the subtarget.
8397 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
8398 SelectionDAG &DAG) const {
8399 // If the subtarget does not support the FUCOMI instruction, floating-point
8400 // comparisons have to be converted.
8401 if (Subtarget->hasCMov() ||
8402 Cmp.getOpcode() != X86ISD::CMP ||
8403 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
8404 !Cmp.getOperand(1).getValueType().isFloatingPoint())
8407 // The instruction selector will select an FUCOM instruction instead of
8408 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
8409 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
8410 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
8411 DebugLoc dl = Cmp.getDebugLoc();
8412 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
8413 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
8414 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
8415 DAG.getConstant(8, MVT::i8));
8416 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
8417 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
8420 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
8421 /// if it's possible.
8422 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
8423 DebugLoc dl, SelectionDAG &DAG) const {
8424 SDValue Op0 = And.getOperand(0);
8425 SDValue Op1 = And.getOperand(1);
8426 if (Op0.getOpcode() == ISD::TRUNCATE)
8427 Op0 = Op0.getOperand(0);
8428 if (Op1.getOpcode() == ISD::TRUNCATE)
8429 Op1 = Op1.getOperand(0);
8432 if (Op1.getOpcode() == ISD::SHL)
8433 std::swap(Op0, Op1);
8434 if (Op0.getOpcode() == ISD::SHL) {
8435 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
8436 if (And00C->getZExtValue() == 1) {
8437 // If we looked past a truncate, check that it's only truncating away
8439 unsigned BitWidth = Op0.getValueSizeInBits();
8440 unsigned AndBitWidth = And.getValueSizeInBits();
8441 if (BitWidth > AndBitWidth) {
8443 DAG.ComputeMaskedBits(Op0, Zeros, Ones);
8444 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
8448 RHS = Op0.getOperand(1);
8450 } else if (Op1.getOpcode() == ISD::Constant) {
8451 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
8452 uint64_t AndRHSVal = AndRHS->getZExtValue();
8453 SDValue AndLHS = Op0;
8455 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
8456 LHS = AndLHS.getOperand(0);
8457 RHS = AndLHS.getOperand(1);
8460 // Use BT if the immediate can't be encoded in a TEST instruction.
8461 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
8463 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
8467 if (LHS.getNode()) {
8468 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
8469 // instruction. Since the shift amount is in-range-or-undefined, we know
8470 // that doing a bittest on the i32 value is ok. We extend to i32 because
8471 // the encoding for the i16 version is larger than the i32 version.
8472 // Also promote i16 to i32 for performance / code size reason.
8473 if (LHS.getValueType() == MVT::i8 ||
8474 LHS.getValueType() == MVT::i16)
8475 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
8477 // If the operand types disagree, extend the shift amount to match. Since
8478 // BT ignores high bits (like shifts) we can use anyextend.
8479 if (LHS.getValueType() != RHS.getValueType())
8480 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
8482 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
8483 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
8484 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8485 DAG.getConstant(Cond, MVT::i8), BT);
8491 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
8493 if (Op.getValueType().isVector()) return LowerVSETCC(Op, DAG);
8495 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
8496 SDValue Op0 = Op.getOperand(0);
8497 SDValue Op1 = Op.getOperand(1);
8498 DebugLoc dl = Op.getDebugLoc();
8499 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
8501 // Optimize to BT if possible.
8502 // Lower (X & (1 << N)) == 0 to BT(X, N).
8503 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
8504 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
8505 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
8506 Op1.getOpcode() == ISD::Constant &&
8507 cast<ConstantSDNode>(Op1)->isNullValue() &&
8508 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8509 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
8510 if (NewSetCC.getNode())
8514 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
8516 if (Op1.getOpcode() == ISD::Constant &&
8517 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
8518 cast<ConstantSDNode>(Op1)->isNullValue()) &&
8519 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8521 // If the input is a setcc, then reuse the input setcc or use a new one with
8522 // the inverted condition.
8523 if (Op0.getOpcode() == X86ISD::SETCC) {
8524 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
8525 bool Invert = (CC == ISD::SETNE) ^
8526 cast<ConstantSDNode>(Op1)->isNullValue();
8527 if (!Invert) return Op0;
8529 CCode = X86::GetOppositeBranchCondition(CCode);
8530 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8531 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
8535 bool isFP = Op1.getValueType().isFloatingPoint();
8536 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
8537 if (X86CC == X86::COND_INVALID)
8540 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG);
8541 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
8542 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8543 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
8546 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
8547 // ones, and then concatenate the result back.
8548 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
8549 EVT VT = Op.getValueType();
8551 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
8552 "Unsupported value type for operation");
8554 unsigned NumElems = VT.getVectorNumElements();
8555 DebugLoc dl = Op.getDebugLoc();
8556 SDValue CC = Op.getOperand(2);
8558 // Extract the LHS vectors
8559 SDValue LHS = Op.getOperand(0);
8560 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
8561 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
8563 // Extract the RHS vectors
8564 SDValue RHS = Op.getOperand(1);
8565 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
8566 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
8568 // Issue the operation on the smaller types and concatenate the result back
8569 MVT EltVT = VT.getVectorElementType().getSimpleVT();
8570 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
8571 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
8572 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
8573 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
8577 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const {
8579 SDValue Op0 = Op.getOperand(0);
8580 SDValue Op1 = Op.getOperand(1);
8581 SDValue CC = Op.getOperand(2);
8582 EVT VT = Op.getValueType();
8583 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
8584 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
8585 DebugLoc dl = Op.getDebugLoc();
8589 EVT EltVT = Op0.getValueType().getVectorElementType();
8590 assert(EltVT == MVT::f32 || EltVT == MVT::f64); (void)EltVT;
8594 // SSE Condition code mapping:
8603 switch (SetCCOpcode) {
8606 case ISD::SETEQ: SSECC = 0; break;
8608 case ISD::SETGT: Swap = true; // Fallthrough
8610 case ISD::SETOLT: SSECC = 1; break;
8612 case ISD::SETGE: Swap = true; // Fallthrough
8614 case ISD::SETOLE: SSECC = 2; break;
8615 case ISD::SETUO: SSECC = 3; break;
8617 case ISD::SETNE: SSECC = 4; break;
8618 case ISD::SETULE: Swap = true;
8619 case ISD::SETUGE: SSECC = 5; break;
8620 case ISD::SETULT: Swap = true;
8621 case ISD::SETUGT: SSECC = 6; break;
8622 case ISD::SETO: SSECC = 7; break;
8625 std::swap(Op0, Op1);
8627 // In the two special cases we can't handle, emit two comparisons.
8629 if (SetCCOpcode == ISD::SETUEQ) {
8631 UNORD = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8632 DAG.getConstant(3, MVT::i8));
8633 EQ = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8634 DAG.getConstant(0, MVT::i8));
8635 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
8637 if (SetCCOpcode == ISD::SETONE) {
8639 ORD = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8640 DAG.getConstant(7, MVT::i8));
8641 NEQ = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8642 DAG.getConstant(4, MVT::i8));
8643 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
8645 llvm_unreachable("Illegal FP comparison");
8647 // Handle all other FP comparisons here.
8648 return DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8649 DAG.getConstant(SSECC, MVT::i8));
8652 // Break 256-bit integer vector compare into smaller ones.
8653 if (VT.is256BitVector() && !Subtarget->hasAVX2())
8654 return Lower256IntVSETCC(Op, DAG);
8656 // We are handling one of the integer comparisons here. Since SSE only has
8657 // GT and EQ comparisons for integer, swapping operands and multiple
8658 // operations may be required for some comparisons.
8660 bool Swap = false, Invert = false, FlipSigns = false;
8662 switch (SetCCOpcode) {
8664 case ISD::SETNE: Invert = true;
8665 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
8666 case ISD::SETLT: Swap = true;
8667 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
8668 case ISD::SETGE: Swap = true;
8669 case ISD::SETLE: Opc = X86ISD::PCMPGT; Invert = true; break;
8670 case ISD::SETULT: Swap = true;
8671 case ISD::SETUGT: Opc = X86ISD::PCMPGT; FlipSigns = true; break;
8672 case ISD::SETUGE: Swap = true;
8673 case ISD::SETULE: Opc = X86ISD::PCMPGT; FlipSigns = true; Invert = true; break;
8676 std::swap(Op0, Op1);
8678 // Check that the operation in question is available (most are plain SSE2,
8679 // but PCMPGTQ and PCMPEQQ have different requirements).
8680 if (Opc == X86ISD::PCMPGT && VT == MVT::v2i64 && !Subtarget->hasSSE42())
8682 if (Opc == X86ISD::PCMPEQ && VT == MVT::v2i64 && !Subtarget->hasSSE41())
8685 // Since SSE has no unsigned integer comparisons, we need to flip the sign
8686 // bits of the inputs before performing those operations.
8688 EVT EltVT = VT.getVectorElementType();
8689 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
8691 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
8692 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
8694 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
8695 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
8698 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
8700 // If the logical-not of the result is required, perform that now.
8702 Result = DAG.getNOT(dl, Result, VT);
8707 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
8708 static bool isX86LogicalCmp(SDValue Op) {
8709 unsigned Opc = Op.getNode()->getOpcode();
8710 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
8711 Opc == X86ISD::SAHF)
8713 if (Op.getResNo() == 1 &&
8714 (Opc == X86ISD::ADD ||
8715 Opc == X86ISD::SUB ||
8716 Opc == X86ISD::ADC ||
8717 Opc == X86ISD::SBB ||
8718 Opc == X86ISD::SMUL ||
8719 Opc == X86ISD::UMUL ||
8720 Opc == X86ISD::INC ||
8721 Opc == X86ISD::DEC ||
8722 Opc == X86ISD::OR ||
8723 Opc == X86ISD::XOR ||
8724 Opc == X86ISD::AND))
8727 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
8733 static bool isZero(SDValue V) {
8734 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
8735 return C && C->isNullValue();
8738 static bool isAllOnes(SDValue V) {
8739 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
8740 return C && C->isAllOnesValue();
8743 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
8744 if (V.getOpcode() != ISD::TRUNCATE)
8747 SDValue VOp0 = V.getOperand(0);
8748 unsigned InBits = VOp0.getValueSizeInBits();
8749 unsigned Bits = V.getValueSizeInBits();
8750 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
8753 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
8754 bool addTest = true;
8755 SDValue Cond = Op.getOperand(0);
8756 SDValue Op1 = Op.getOperand(1);
8757 SDValue Op2 = Op.getOperand(2);
8758 DebugLoc DL = Op.getDebugLoc();
8761 if (Cond.getOpcode() == ISD::SETCC) {
8762 SDValue NewCond = LowerSETCC(Cond, DAG);
8763 if (NewCond.getNode())
8767 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
8768 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
8769 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
8770 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
8771 if (Cond.getOpcode() == X86ISD::SETCC &&
8772 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
8773 isZero(Cond.getOperand(1).getOperand(1))) {
8774 SDValue Cmp = Cond.getOperand(1);
8776 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
8778 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
8779 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
8780 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
8782 SDValue CmpOp0 = Cmp.getOperand(0);
8783 // Apply further optimizations for special cases
8784 // (select (x != 0), -1, 0) -> neg & sbb
8785 // (select (x == 0), 0, -1) -> neg & sbb
8786 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
8787 if (YC->isNullValue() &&
8788 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
8789 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
8790 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
8791 DAG.getConstant(0, CmpOp0.getValueType()),
8793 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8794 DAG.getConstant(X86::COND_B, MVT::i8),
8795 SDValue(Neg.getNode(), 1));
8799 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
8800 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
8801 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
8803 SDValue Res = // Res = 0 or -1.
8804 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8805 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
8807 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
8808 Res = DAG.getNOT(DL, Res, Res.getValueType());
8810 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
8811 if (N2C == 0 || !N2C->isNullValue())
8812 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
8817 // Look past (and (setcc_carry (cmp ...)), 1).
8818 if (Cond.getOpcode() == ISD::AND &&
8819 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
8820 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
8821 if (C && C->getAPIntValue() == 1)
8822 Cond = Cond.getOperand(0);
8825 // If condition flag is set by a X86ISD::CMP, then use it as the condition
8826 // setting operand in place of the X86ISD::SETCC.
8827 unsigned CondOpcode = Cond.getOpcode();
8828 if (CondOpcode == X86ISD::SETCC ||
8829 CondOpcode == X86ISD::SETCC_CARRY) {
8830 CC = Cond.getOperand(0);
8832 SDValue Cmp = Cond.getOperand(1);
8833 unsigned Opc = Cmp.getOpcode();
8834 EVT VT = Op.getValueType();
8836 bool IllegalFPCMov = false;
8837 if (VT.isFloatingPoint() && !VT.isVector() &&
8838 !isScalarFPTypeInSSEReg(VT)) // FPStack?
8839 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
8841 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
8842 Opc == X86ISD::BT) { // FIXME
8846 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
8847 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
8848 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
8849 Cond.getOperand(0).getValueType() != MVT::i8)) {
8850 SDValue LHS = Cond.getOperand(0);
8851 SDValue RHS = Cond.getOperand(1);
8855 switch (CondOpcode) {
8856 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
8857 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
8858 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
8859 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
8860 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
8861 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
8862 default: llvm_unreachable("unexpected overflowing operator");
8864 if (CondOpcode == ISD::UMULO)
8865 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
8868 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
8870 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
8872 if (CondOpcode == ISD::UMULO)
8873 Cond = X86Op.getValue(2);
8875 Cond = X86Op.getValue(1);
8877 CC = DAG.getConstant(X86Cond, MVT::i8);
8882 // Look pass the truncate if the high bits are known zero.
8883 if (isTruncWithZeroHighBitsInput(Cond, DAG))
8884 Cond = Cond.getOperand(0);
8886 // We know the result of AND is compared against zero. Try to match
8888 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
8889 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
8890 if (NewSetCC.getNode()) {
8891 CC = NewSetCC.getOperand(0);
8892 Cond = NewSetCC.getOperand(1);
8899 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8900 Cond = EmitTest(Cond, X86::COND_NE, DAG);
8903 // a < b ? -1 : 0 -> RES = ~setcc_carry
8904 // a < b ? 0 : -1 -> RES = setcc_carry
8905 // a >= b ? -1 : 0 -> RES = setcc_carry
8906 // a >= b ? 0 : -1 -> RES = ~setcc_carry
8907 if (Cond.getOpcode() == X86ISD::SUB) {
8908 Cond = ConvertCmpIfNecessary(Cond, DAG);
8909 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
8911 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
8912 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
8913 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8914 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
8915 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
8916 return DAG.getNOT(DL, Res, Res.getValueType());
8921 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
8922 // condition is true.
8923 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
8924 SDValue Ops[] = { Op2, Op1, CC, Cond };
8925 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
8928 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
8929 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
8930 // from the AND / OR.
8931 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
8932 Opc = Op.getOpcode();
8933 if (Opc != ISD::OR && Opc != ISD::AND)
8935 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
8936 Op.getOperand(0).hasOneUse() &&
8937 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
8938 Op.getOperand(1).hasOneUse());
8941 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
8942 // 1 and that the SETCC node has a single use.
8943 static bool isXor1OfSetCC(SDValue Op) {
8944 if (Op.getOpcode() != ISD::XOR)
8946 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
8947 if (N1C && N1C->getAPIntValue() == 1) {
8948 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
8949 Op.getOperand(0).hasOneUse();
8954 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
8955 bool addTest = true;
8956 SDValue Chain = Op.getOperand(0);
8957 SDValue Cond = Op.getOperand(1);
8958 SDValue Dest = Op.getOperand(2);
8959 DebugLoc dl = Op.getDebugLoc();
8961 bool Inverted = false;
8963 if (Cond.getOpcode() == ISD::SETCC) {
8964 // Check for setcc([su]{add,sub,mul}o == 0).
8965 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
8966 isa<ConstantSDNode>(Cond.getOperand(1)) &&
8967 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
8968 Cond.getOperand(0).getResNo() == 1 &&
8969 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
8970 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
8971 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
8972 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
8973 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
8974 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
8976 Cond = Cond.getOperand(0);
8978 SDValue NewCond = LowerSETCC(Cond, DAG);
8979 if (NewCond.getNode())
8984 // FIXME: LowerXALUO doesn't handle these!!
8985 else if (Cond.getOpcode() == X86ISD::ADD ||
8986 Cond.getOpcode() == X86ISD::SUB ||
8987 Cond.getOpcode() == X86ISD::SMUL ||
8988 Cond.getOpcode() == X86ISD::UMUL)
8989 Cond = LowerXALUO(Cond, DAG);
8992 // Look pass (and (setcc_carry (cmp ...)), 1).
8993 if (Cond.getOpcode() == ISD::AND &&
8994 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
8995 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
8996 if (C && C->getAPIntValue() == 1)
8997 Cond = Cond.getOperand(0);
9000 // If condition flag is set by a X86ISD::CMP, then use it as the condition
9001 // setting operand in place of the X86ISD::SETCC.
9002 unsigned CondOpcode = Cond.getOpcode();
9003 if (CondOpcode == X86ISD::SETCC ||
9004 CondOpcode == X86ISD::SETCC_CARRY) {
9005 CC = Cond.getOperand(0);
9007 SDValue Cmp = Cond.getOperand(1);
9008 unsigned Opc = Cmp.getOpcode();
9009 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
9010 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
9014 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
9018 // These can only come from an arithmetic instruction with overflow,
9019 // e.g. SADDO, UADDO.
9020 Cond = Cond.getNode()->getOperand(1);
9026 CondOpcode = Cond.getOpcode();
9027 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
9028 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
9029 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
9030 Cond.getOperand(0).getValueType() != MVT::i8)) {
9031 SDValue LHS = Cond.getOperand(0);
9032 SDValue RHS = Cond.getOperand(1);
9036 switch (CondOpcode) {
9037 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
9038 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
9039 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
9040 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
9041 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
9042 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
9043 default: llvm_unreachable("unexpected overflowing operator");
9046 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
9047 if (CondOpcode == ISD::UMULO)
9048 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
9051 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
9053 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
9055 if (CondOpcode == ISD::UMULO)
9056 Cond = X86Op.getValue(2);
9058 Cond = X86Op.getValue(1);
9060 CC = DAG.getConstant(X86Cond, MVT::i8);
9064 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
9065 SDValue Cmp = Cond.getOperand(0).getOperand(1);
9066 if (CondOpc == ISD::OR) {
9067 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
9068 // two branches instead of an explicit OR instruction with a
9070 if (Cmp == Cond.getOperand(1).getOperand(1) &&
9071 isX86LogicalCmp(Cmp)) {
9072 CC = Cond.getOperand(0).getOperand(0);
9073 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
9074 Chain, Dest, CC, Cmp);
9075 CC = Cond.getOperand(1).getOperand(0);
9079 } else { // ISD::AND
9080 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
9081 // two branches instead of an explicit AND instruction with a
9082 // separate test. However, we only do this if this block doesn't
9083 // have a fall-through edge, because this requires an explicit
9084 // jmp when the condition is false.
9085 if (Cmp == Cond.getOperand(1).getOperand(1) &&
9086 isX86LogicalCmp(Cmp) &&
9087 Op.getNode()->hasOneUse()) {
9088 X86::CondCode CCode =
9089 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
9090 CCode = X86::GetOppositeBranchCondition(CCode);
9091 CC = DAG.getConstant(CCode, MVT::i8);
9092 SDNode *User = *Op.getNode()->use_begin();
9093 // Look for an unconditional branch following this conditional branch.
9094 // We need this because we need to reverse the successors in order
9095 // to implement FCMP_OEQ.
9096 if (User->getOpcode() == ISD::BR) {
9097 SDValue FalseBB = User->getOperand(1);
9099 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
9100 assert(NewBR == User);
9104 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
9105 Chain, Dest, CC, Cmp);
9106 X86::CondCode CCode =
9107 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
9108 CCode = X86::GetOppositeBranchCondition(CCode);
9109 CC = DAG.getConstant(CCode, MVT::i8);
9115 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
9116 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
9117 // It should be transformed during dag combiner except when the condition
9118 // is set by a arithmetics with overflow node.
9119 X86::CondCode CCode =
9120 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
9121 CCode = X86::GetOppositeBranchCondition(CCode);
9122 CC = DAG.getConstant(CCode, MVT::i8);
9123 Cond = Cond.getOperand(0).getOperand(1);
9125 } else if (Cond.getOpcode() == ISD::SETCC &&
9126 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
9127 // For FCMP_OEQ, we can emit
9128 // two branches instead of an explicit AND instruction with a
9129 // separate test. However, we only do this if this block doesn't
9130 // have a fall-through edge, because this requires an explicit
9131 // jmp when the condition is false.
9132 if (Op.getNode()->hasOneUse()) {
9133 SDNode *User = *Op.getNode()->use_begin();
9134 // Look for an unconditional branch following this conditional branch.
9135 // We need this because we need to reverse the successors in order
9136 // to implement FCMP_OEQ.
9137 if (User->getOpcode() == ISD::BR) {
9138 SDValue FalseBB = User->getOperand(1);
9140 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
9141 assert(NewBR == User);
9145 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
9146 Cond.getOperand(0), Cond.getOperand(1));
9147 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
9148 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
9149 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
9150 Chain, Dest, CC, Cmp);
9151 CC = DAG.getConstant(X86::COND_P, MVT::i8);
9156 } else if (Cond.getOpcode() == ISD::SETCC &&
9157 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
9158 // For FCMP_UNE, we can emit
9159 // two branches instead of an explicit AND instruction with a
9160 // separate test. However, we only do this if this block doesn't
9161 // have a fall-through edge, because this requires an explicit
9162 // jmp when the condition is false.
9163 if (Op.getNode()->hasOneUse()) {
9164 SDNode *User = *Op.getNode()->use_begin();
9165 // Look for an unconditional branch following this conditional branch.
9166 // We need this because we need to reverse the successors in order
9167 // to implement FCMP_UNE.
9168 if (User->getOpcode() == ISD::BR) {
9169 SDValue FalseBB = User->getOperand(1);
9171 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
9172 assert(NewBR == User);
9175 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
9176 Cond.getOperand(0), Cond.getOperand(1));
9177 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
9178 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
9179 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
9180 Chain, Dest, CC, Cmp);
9181 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
9191 // Look pass the truncate if the high bits are known zero.
9192 if (isTruncWithZeroHighBitsInput(Cond, DAG))
9193 Cond = Cond.getOperand(0);
9195 // We know the result of AND is compared against zero. Try to match
9197 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
9198 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
9199 if (NewSetCC.getNode()) {
9200 CC = NewSetCC.getOperand(0);
9201 Cond = NewSetCC.getOperand(1);
9208 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
9209 Cond = EmitTest(Cond, X86::COND_NE, DAG);
9211 Cond = ConvertCmpIfNecessary(Cond, DAG);
9212 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
9213 Chain, Dest, CC, Cond);
9217 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
9218 // Calls to _alloca is needed to probe the stack when allocating more than 4k
9219 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
9220 // that the guard pages used by the OS virtual memory manager are allocated in
9221 // correct sequence.
9223 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
9224 SelectionDAG &DAG) const {
9225 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() ||
9226 getTargetMachine().Options.EnableSegmentedStacks) &&
9227 "This should be used only on Windows targets or when segmented stacks "
9229 assert(!Subtarget->isTargetEnvMacho() && "Not implemented");
9230 DebugLoc dl = Op.getDebugLoc();
9233 SDValue Chain = Op.getOperand(0);
9234 SDValue Size = Op.getOperand(1);
9235 // FIXME: Ensure alignment here
9237 bool Is64Bit = Subtarget->is64Bit();
9238 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32;
9240 if (getTargetMachine().Options.EnableSegmentedStacks) {
9241 MachineFunction &MF = DAG.getMachineFunction();
9242 MachineRegisterInfo &MRI = MF.getRegInfo();
9245 // The 64 bit implementation of segmented stacks needs to clobber both r10
9246 // r11. This makes it impossible to use it along with nested parameters.
9247 const Function *F = MF.getFunction();
9249 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
9251 if (I->hasNestAttr())
9252 report_fatal_error("Cannot use segmented stacks with functions that "
9253 "have nested arguments.");
9256 const TargetRegisterClass *AddrRegClass =
9257 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
9258 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
9259 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
9260 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
9261 DAG.getRegister(Vreg, SPTy));
9262 SDValue Ops1[2] = { Value, Chain };
9263 return DAG.getMergeValues(Ops1, 2, dl);
9266 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
9268 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
9269 Flag = Chain.getValue(1);
9270 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
9272 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
9273 Flag = Chain.getValue(1);
9275 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
9277 SDValue Ops1[2] = { Chain.getValue(0), Chain };
9278 return DAG.getMergeValues(Ops1, 2, dl);
9282 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
9283 MachineFunction &MF = DAG.getMachineFunction();
9284 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
9286 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
9287 DebugLoc DL = Op.getDebugLoc();
9289 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
9290 // vastart just stores the address of the VarArgsFrameIndex slot into the
9291 // memory location argument.
9292 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
9294 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
9295 MachinePointerInfo(SV), false, false, 0);
9299 // gp_offset (0 - 6 * 8)
9300 // fp_offset (48 - 48 + 8 * 16)
9301 // overflow_arg_area (point to parameters coming in memory).
9303 SmallVector<SDValue, 8> MemOps;
9304 SDValue FIN = Op.getOperand(1);
9306 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
9307 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
9309 FIN, MachinePointerInfo(SV), false, false, 0);
9310 MemOps.push_back(Store);
9313 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9314 FIN, DAG.getIntPtrConstant(4));
9315 Store = DAG.getStore(Op.getOperand(0), DL,
9316 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
9318 FIN, MachinePointerInfo(SV, 4), false, false, 0);
9319 MemOps.push_back(Store);
9321 // Store ptr to overflow_arg_area
9322 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9323 FIN, DAG.getIntPtrConstant(4));
9324 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
9326 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
9327 MachinePointerInfo(SV, 8),
9329 MemOps.push_back(Store);
9331 // Store ptr to reg_save_area.
9332 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9333 FIN, DAG.getIntPtrConstant(8));
9334 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
9336 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
9337 MachinePointerInfo(SV, 16), false, false, 0);
9338 MemOps.push_back(Store);
9339 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
9340 &MemOps[0], MemOps.size());
9343 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
9344 assert(Subtarget->is64Bit() &&
9345 "LowerVAARG only handles 64-bit va_arg!");
9346 assert((Subtarget->isTargetLinux() ||
9347 Subtarget->isTargetDarwin()) &&
9348 "Unhandled target in LowerVAARG");
9349 assert(Op.getNode()->getNumOperands() == 4);
9350 SDValue Chain = Op.getOperand(0);
9351 SDValue SrcPtr = Op.getOperand(1);
9352 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
9353 unsigned Align = Op.getConstantOperandVal(3);
9354 DebugLoc dl = Op.getDebugLoc();
9356 EVT ArgVT = Op.getNode()->getValueType(0);
9357 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
9358 uint32_t ArgSize = getTargetData()->getTypeAllocSize(ArgTy);
9361 // Decide which area this value should be read from.
9362 // TODO: Implement the AMD64 ABI in its entirety. This simple
9363 // selection mechanism works only for the basic types.
9364 if (ArgVT == MVT::f80) {
9365 llvm_unreachable("va_arg for f80 not yet implemented");
9366 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
9367 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
9368 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
9369 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
9371 llvm_unreachable("Unhandled argument type in LowerVAARG");
9375 // Sanity Check: Make sure using fp_offset makes sense.
9376 assert(!getTargetMachine().Options.UseSoftFloat &&
9377 !(DAG.getMachineFunction()
9378 .getFunction()->hasFnAttr(Attribute::NoImplicitFloat)) &&
9379 Subtarget->hasSSE1());
9382 // Insert VAARG_64 node into the DAG
9383 // VAARG_64 returns two values: Variable Argument Address, Chain
9384 SmallVector<SDValue, 11> InstOps;
9385 InstOps.push_back(Chain);
9386 InstOps.push_back(SrcPtr);
9387 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
9388 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
9389 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
9390 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
9391 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
9392 VTs, &InstOps[0], InstOps.size(),
9394 MachinePointerInfo(SV),
9399 Chain = VAARG.getValue(1);
9401 // Load the next argument and return it
9402 return DAG.getLoad(ArgVT, dl,
9405 MachinePointerInfo(),
9406 false, false, false, 0);
9409 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
9410 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
9411 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
9412 SDValue Chain = Op.getOperand(0);
9413 SDValue DstPtr = Op.getOperand(1);
9414 SDValue SrcPtr = Op.getOperand(2);
9415 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
9416 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
9417 DebugLoc DL = Op.getDebugLoc();
9419 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
9420 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
9422 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
9425 // getTargetVShiftNOde - Handle vector element shifts where the shift amount
9426 // may or may not be a constant. Takes immediate version of shift as input.
9427 static SDValue getTargetVShiftNode(unsigned Opc, DebugLoc dl, EVT VT,
9428 SDValue SrcOp, SDValue ShAmt,
9429 SelectionDAG &DAG) {
9430 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
9432 if (isa<ConstantSDNode>(ShAmt)) {
9433 // Constant may be a TargetConstant. Use a regular constant.
9434 uint32_t ShiftAmt = cast<ConstantSDNode>(ShAmt)->getZExtValue();
9436 default: llvm_unreachable("Unknown target vector shift node");
9440 return DAG.getNode(Opc, dl, VT, SrcOp,
9441 DAG.getConstant(ShiftAmt, MVT::i32));
9445 // Change opcode to non-immediate version
9447 default: llvm_unreachable("Unknown target vector shift node");
9448 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
9449 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
9450 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
9453 // Need to build a vector containing shift amount
9454 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
9457 ShOps[1] = DAG.getConstant(0, MVT::i32);
9458 ShOps[2] = DAG.getUNDEF(MVT::i32);
9459 ShOps[3] = DAG.getUNDEF(MVT::i32);
9460 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &ShOps[0], 4);
9462 // The return type has to be a 128-bit type with the same element
9463 // type as the input type.
9464 MVT EltVT = VT.getVectorElementType().getSimpleVT();
9465 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
9467 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
9468 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
9472 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const {
9473 DebugLoc dl = Op.getDebugLoc();
9474 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9476 default: return SDValue(); // Don't custom lower most intrinsics.
9477 // Comparison intrinsics.
9478 case Intrinsic::x86_sse_comieq_ss:
9479 case Intrinsic::x86_sse_comilt_ss:
9480 case Intrinsic::x86_sse_comile_ss:
9481 case Intrinsic::x86_sse_comigt_ss:
9482 case Intrinsic::x86_sse_comige_ss:
9483 case Intrinsic::x86_sse_comineq_ss:
9484 case Intrinsic::x86_sse_ucomieq_ss:
9485 case Intrinsic::x86_sse_ucomilt_ss:
9486 case Intrinsic::x86_sse_ucomile_ss:
9487 case Intrinsic::x86_sse_ucomigt_ss:
9488 case Intrinsic::x86_sse_ucomige_ss:
9489 case Intrinsic::x86_sse_ucomineq_ss:
9490 case Intrinsic::x86_sse2_comieq_sd:
9491 case Intrinsic::x86_sse2_comilt_sd:
9492 case Intrinsic::x86_sse2_comile_sd:
9493 case Intrinsic::x86_sse2_comigt_sd:
9494 case Intrinsic::x86_sse2_comige_sd:
9495 case Intrinsic::x86_sse2_comineq_sd:
9496 case Intrinsic::x86_sse2_ucomieq_sd:
9497 case Intrinsic::x86_sse2_ucomilt_sd:
9498 case Intrinsic::x86_sse2_ucomile_sd:
9499 case Intrinsic::x86_sse2_ucomigt_sd:
9500 case Intrinsic::x86_sse2_ucomige_sd:
9501 case Intrinsic::x86_sse2_ucomineq_sd: {
9503 ISD::CondCode CC = ISD::SETCC_INVALID;
9505 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9506 case Intrinsic::x86_sse_comieq_ss:
9507 case Intrinsic::x86_sse2_comieq_sd:
9511 case Intrinsic::x86_sse_comilt_ss:
9512 case Intrinsic::x86_sse2_comilt_sd:
9516 case Intrinsic::x86_sse_comile_ss:
9517 case Intrinsic::x86_sse2_comile_sd:
9521 case Intrinsic::x86_sse_comigt_ss:
9522 case Intrinsic::x86_sse2_comigt_sd:
9526 case Intrinsic::x86_sse_comige_ss:
9527 case Intrinsic::x86_sse2_comige_sd:
9531 case Intrinsic::x86_sse_comineq_ss:
9532 case Intrinsic::x86_sse2_comineq_sd:
9536 case Intrinsic::x86_sse_ucomieq_ss:
9537 case Intrinsic::x86_sse2_ucomieq_sd:
9538 Opc = X86ISD::UCOMI;
9541 case Intrinsic::x86_sse_ucomilt_ss:
9542 case Intrinsic::x86_sse2_ucomilt_sd:
9543 Opc = X86ISD::UCOMI;
9546 case Intrinsic::x86_sse_ucomile_ss:
9547 case Intrinsic::x86_sse2_ucomile_sd:
9548 Opc = X86ISD::UCOMI;
9551 case Intrinsic::x86_sse_ucomigt_ss:
9552 case Intrinsic::x86_sse2_ucomigt_sd:
9553 Opc = X86ISD::UCOMI;
9556 case Intrinsic::x86_sse_ucomige_ss:
9557 case Intrinsic::x86_sse2_ucomige_sd:
9558 Opc = X86ISD::UCOMI;
9561 case Intrinsic::x86_sse_ucomineq_ss:
9562 case Intrinsic::x86_sse2_ucomineq_sd:
9563 Opc = X86ISD::UCOMI;
9568 SDValue LHS = Op.getOperand(1);
9569 SDValue RHS = Op.getOperand(2);
9570 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
9571 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
9572 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
9573 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9574 DAG.getConstant(X86CC, MVT::i8), Cond);
9575 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
9577 // Arithmetic intrinsics.
9578 case Intrinsic::x86_sse2_pmulu_dq:
9579 case Intrinsic::x86_avx2_pmulu_dq:
9580 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
9581 Op.getOperand(1), Op.getOperand(2));
9582 case Intrinsic::x86_sse3_hadd_ps:
9583 case Intrinsic::x86_sse3_hadd_pd:
9584 case Intrinsic::x86_avx_hadd_ps_256:
9585 case Intrinsic::x86_avx_hadd_pd_256:
9586 return DAG.getNode(X86ISD::FHADD, dl, Op.getValueType(),
9587 Op.getOperand(1), Op.getOperand(2));
9588 case Intrinsic::x86_sse3_hsub_ps:
9589 case Intrinsic::x86_sse3_hsub_pd:
9590 case Intrinsic::x86_avx_hsub_ps_256:
9591 case Intrinsic::x86_avx_hsub_pd_256:
9592 return DAG.getNode(X86ISD::FHSUB, dl, Op.getValueType(),
9593 Op.getOperand(1), Op.getOperand(2));
9594 case Intrinsic::x86_ssse3_phadd_w_128:
9595 case Intrinsic::x86_ssse3_phadd_d_128:
9596 case Intrinsic::x86_avx2_phadd_w:
9597 case Intrinsic::x86_avx2_phadd_d:
9598 return DAG.getNode(X86ISD::HADD, dl, Op.getValueType(),
9599 Op.getOperand(1), Op.getOperand(2));
9600 case Intrinsic::x86_ssse3_phsub_w_128:
9601 case Intrinsic::x86_ssse3_phsub_d_128:
9602 case Intrinsic::x86_avx2_phsub_w:
9603 case Intrinsic::x86_avx2_phsub_d:
9604 return DAG.getNode(X86ISD::HSUB, dl, Op.getValueType(),
9605 Op.getOperand(1), Op.getOperand(2));
9606 case Intrinsic::x86_avx2_psllv_d:
9607 case Intrinsic::x86_avx2_psllv_q:
9608 case Intrinsic::x86_avx2_psllv_d_256:
9609 case Intrinsic::x86_avx2_psllv_q_256:
9610 return DAG.getNode(ISD::SHL, dl, Op.getValueType(),
9611 Op.getOperand(1), Op.getOperand(2));
9612 case Intrinsic::x86_avx2_psrlv_d:
9613 case Intrinsic::x86_avx2_psrlv_q:
9614 case Intrinsic::x86_avx2_psrlv_d_256:
9615 case Intrinsic::x86_avx2_psrlv_q_256:
9616 return DAG.getNode(ISD::SRL, dl, Op.getValueType(),
9617 Op.getOperand(1), Op.getOperand(2));
9618 case Intrinsic::x86_avx2_psrav_d:
9619 case Intrinsic::x86_avx2_psrav_d_256:
9620 return DAG.getNode(ISD::SRA, dl, Op.getValueType(),
9621 Op.getOperand(1), Op.getOperand(2));
9622 case Intrinsic::x86_ssse3_pshuf_b_128:
9623 case Intrinsic::x86_avx2_pshuf_b:
9624 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
9625 Op.getOperand(1), Op.getOperand(2));
9626 case Intrinsic::x86_ssse3_psign_b_128:
9627 case Intrinsic::x86_ssse3_psign_w_128:
9628 case Intrinsic::x86_ssse3_psign_d_128:
9629 case Intrinsic::x86_avx2_psign_b:
9630 case Intrinsic::x86_avx2_psign_w:
9631 case Intrinsic::x86_avx2_psign_d:
9632 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
9633 Op.getOperand(1), Op.getOperand(2));
9634 case Intrinsic::x86_sse41_insertps:
9635 return DAG.getNode(X86ISD::INSERTPS, dl, Op.getValueType(),
9636 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
9637 case Intrinsic::x86_avx_vperm2f128_ps_256:
9638 case Intrinsic::x86_avx_vperm2f128_pd_256:
9639 case Intrinsic::x86_avx_vperm2f128_si_256:
9640 case Intrinsic::x86_avx2_vperm2i128:
9641 return DAG.getNode(X86ISD::VPERM2X128, dl, Op.getValueType(),
9642 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
9643 case Intrinsic::x86_avx2_permd:
9644 case Intrinsic::x86_avx2_permps:
9645 // Operands intentionally swapped. Mask is last operand to intrinsic,
9646 // but second operand for node/intruction.
9647 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
9648 Op.getOperand(2), Op.getOperand(1));
9650 // ptest and testp intrinsics. The intrinsic these come from are designed to
9651 // return an integer value, not just an instruction so lower it to the ptest
9652 // or testp pattern and a setcc for the result.
9653 case Intrinsic::x86_sse41_ptestz:
9654 case Intrinsic::x86_sse41_ptestc:
9655 case Intrinsic::x86_sse41_ptestnzc:
9656 case Intrinsic::x86_avx_ptestz_256:
9657 case Intrinsic::x86_avx_ptestc_256:
9658 case Intrinsic::x86_avx_ptestnzc_256:
9659 case Intrinsic::x86_avx_vtestz_ps:
9660 case Intrinsic::x86_avx_vtestc_ps:
9661 case Intrinsic::x86_avx_vtestnzc_ps:
9662 case Intrinsic::x86_avx_vtestz_pd:
9663 case Intrinsic::x86_avx_vtestc_pd:
9664 case Intrinsic::x86_avx_vtestnzc_pd:
9665 case Intrinsic::x86_avx_vtestz_ps_256:
9666 case Intrinsic::x86_avx_vtestc_ps_256:
9667 case Intrinsic::x86_avx_vtestnzc_ps_256:
9668 case Intrinsic::x86_avx_vtestz_pd_256:
9669 case Intrinsic::x86_avx_vtestc_pd_256:
9670 case Intrinsic::x86_avx_vtestnzc_pd_256: {
9671 bool IsTestPacked = false;
9674 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
9675 case Intrinsic::x86_avx_vtestz_ps:
9676 case Intrinsic::x86_avx_vtestz_pd:
9677 case Intrinsic::x86_avx_vtestz_ps_256:
9678 case Intrinsic::x86_avx_vtestz_pd_256:
9679 IsTestPacked = true; // Fallthrough
9680 case Intrinsic::x86_sse41_ptestz:
9681 case Intrinsic::x86_avx_ptestz_256:
9683 X86CC = X86::COND_E;
9685 case Intrinsic::x86_avx_vtestc_ps:
9686 case Intrinsic::x86_avx_vtestc_pd:
9687 case Intrinsic::x86_avx_vtestc_ps_256:
9688 case Intrinsic::x86_avx_vtestc_pd_256:
9689 IsTestPacked = true; // Fallthrough
9690 case Intrinsic::x86_sse41_ptestc:
9691 case Intrinsic::x86_avx_ptestc_256:
9693 X86CC = X86::COND_B;
9695 case Intrinsic::x86_avx_vtestnzc_ps:
9696 case Intrinsic::x86_avx_vtestnzc_pd:
9697 case Intrinsic::x86_avx_vtestnzc_ps_256:
9698 case Intrinsic::x86_avx_vtestnzc_pd_256:
9699 IsTestPacked = true; // Fallthrough
9700 case Intrinsic::x86_sse41_ptestnzc:
9701 case Intrinsic::x86_avx_ptestnzc_256:
9703 X86CC = X86::COND_A;
9707 SDValue LHS = Op.getOperand(1);
9708 SDValue RHS = Op.getOperand(2);
9709 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
9710 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
9711 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
9712 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
9713 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
9716 // SSE/AVX shift intrinsics
9717 case Intrinsic::x86_sse2_psll_w:
9718 case Intrinsic::x86_sse2_psll_d:
9719 case Intrinsic::x86_sse2_psll_q:
9720 case Intrinsic::x86_avx2_psll_w:
9721 case Intrinsic::x86_avx2_psll_d:
9722 case Intrinsic::x86_avx2_psll_q:
9723 return DAG.getNode(X86ISD::VSHL, dl, Op.getValueType(),
9724 Op.getOperand(1), Op.getOperand(2));
9725 case Intrinsic::x86_sse2_psrl_w:
9726 case Intrinsic::x86_sse2_psrl_d:
9727 case Intrinsic::x86_sse2_psrl_q:
9728 case Intrinsic::x86_avx2_psrl_w:
9729 case Intrinsic::x86_avx2_psrl_d:
9730 case Intrinsic::x86_avx2_psrl_q:
9731 return DAG.getNode(X86ISD::VSRL, dl, Op.getValueType(),
9732 Op.getOperand(1), Op.getOperand(2));
9733 case Intrinsic::x86_sse2_psra_w:
9734 case Intrinsic::x86_sse2_psra_d:
9735 case Intrinsic::x86_avx2_psra_w:
9736 case Intrinsic::x86_avx2_psra_d:
9737 return DAG.getNode(X86ISD::VSRA, dl, Op.getValueType(),
9738 Op.getOperand(1), Op.getOperand(2));
9739 case Intrinsic::x86_sse2_pslli_w:
9740 case Intrinsic::x86_sse2_pslli_d:
9741 case Intrinsic::x86_sse2_pslli_q:
9742 case Intrinsic::x86_avx2_pslli_w:
9743 case Intrinsic::x86_avx2_pslli_d:
9744 case Intrinsic::x86_avx2_pslli_q:
9745 return getTargetVShiftNode(X86ISD::VSHLI, dl, Op.getValueType(),
9746 Op.getOperand(1), Op.getOperand(2), DAG);
9747 case Intrinsic::x86_sse2_psrli_w:
9748 case Intrinsic::x86_sse2_psrli_d:
9749 case Intrinsic::x86_sse2_psrli_q:
9750 case Intrinsic::x86_avx2_psrli_w:
9751 case Intrinsic::x86_avx2_psrli_d:
9752 case Intrinsic::x86_avx2_psrli_q:
9753 return getTargetVShiftNode(X86ISD::VSRLI, dl, Op.getValueType(),
9754 Op.getOperand(1), Op.getOperand(2), DAG);
9755 case Intrinsic::x86_sse2_psrai_w:
9756 case Intrinsic::x86_sse2_psrai_d:
9757 case Intrinsic::x86_avx2_psrai_w:
9758 case Intrinsic::x86_avx2_psrai_d:
9759 return getTargetVShiftNode(X86ISD::VSRAI, dl, Op.getValueType(),
9760 Op.getOperand(1), Op.getOperand(2), DAG);
9761 // Fix vector shift instructions where the last operand is a non-immediate
9763 case Intrinsic::x86_mmx_pslli_w:
9764 case Intrinsic::x86_mmx_pslli_d:
9765 case Intrinsic::x86_mmx_pslli_q:
9766 case Intrinsic::x86_mmx_psrli_w:
9767 case Intrinsic::x86_mmx_psrli_d:
9768 case Intrinsic::x86_mmx_psrli_q:
9769 case Intrinsic::x86_mmx_psrai_w:
9770 case Intrinsic::x86_mmx_psrai_d: {
9771 SDValue ShAmt = Op.getOperand(2);
9772 if (isa<ConstantSDNode>(ShAmt))
9775 unsigned NewIntNo = 0;
9777 case Intrinsic::x86_mmx_pslli_w:
9778 NewIntNo = Intrinsic::x86_mmx_psll_w;
9780 case Intrinsic::x86_mmx_pslli_d:
9781 NewIntNo = Intrinsic::x86_mmx_psll_d;
9783 case Intrinsic::x86_mmx_pslli_q:
9784 NewIntNo = Intrinsic::x86_mmx_psll_q;
9786 case Intrinsic::x86_mmx_psrli_w:
9787 NewIntNo = Intrinsic::x86_mmx_psrl_w;
9789 case Intrinsic::x86_mmx_psrli_d:
9790 NewIntNo = Intrinsic::x86_mmx_psrl_d;
9792 case Intrinsic::x86_mmx_psrli_q:
9793 NewIntNo = Intrinsic::x86_mmx_psrl_q;
9795 case Intrinsic::x86_mmx_psrai_w:
9796 NewIntNo = Intrinsic::x86_mmx_psra_w;
9798 case Intrinsic::x86_mmx_psrai_d:
9799 NewIntNo = Intrinsic::x86_mmx_psra_d;
9801 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9804 // The vector shift intrinsics with scalars uses 32b shift amounts but
9805 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
9807 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, ShAmt,
9808 DAG.getConstant(0, MVT::i32));
9809 // FIXME this must be lowered to get rid of the invalid type.
9811 EVT VT = Op.getValueType();
9812 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt);
9813 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9814 DAG.getConstant(NewIntNo, MVT::i32),
9815 Op.getOperand(1), ShAmt);
9817 case Intrinsic::x86_sse42_pcmpistria128:
9818 case Intrinsic::x86_sse42_pcmpestria128:
9819 case Intrinsic::x86_sse42_pcmpistric128:
9820 case Intrinsic::x86_sse42_pcmpestric128:
9821 case Intrinsic::x86_sse42_pcmpistrio128:
9822 case Intrinsic::x86_sse42_pcmpestrio128:
9823 case Intrinsic::x86_sse42_pcmpistris128:
9824 case Intrinsic::x86_sse42_pcmpestris128:
9825 case Intrinsic::x86_sse42_pcmpistriz128:
9826 case Intrinsic::x86_sse42_pcmpestriz128: {
9830 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9831 case Intrinsic::x86_sse42_pcmpistria128:
9832 Opcode = X86ISD::PCMPISTRI;
9833 X86CC = X86::COND_A;
9835 case Intrinsic::x86_sse42_pcmpestria128:
9836 Opcode = X86ISD::PCMPESTRI;
9837 X86CC = X86::COND_A;
9839 case Intrinsic::x86_sse42_pcmpistric128:
9840 Opcode = X86ISD::PCMPISTRI;
9841 X86CC = X86::COND_B;
9843 case Intrinsic::x86_sse42_pcmpestric128:
9844 Opcode = X86ISD::PCMPESTRI;
9845 X86CC = X86::COND_B;
9847 case Intrinsic::x86_sse42_pcmpistrio128:
9848 Opcode = X86ISD::PCMPISTRI;
9849 X86CC = X86::COND_O;
9851 case Intrinsic::x86_sse42_pcmpestrio128:
9852 Opcode = X86ISD::PCMPESTRI;
9853 X86CC = X86::COND_O;
9855 case Intrinsic::x86_sse42_pcmpistris128:
9856 Opcode = X86ISD::PCMPISTRI;
9857 X86CC = X86::COND_S;
9859 case Intrinsic::x86_sse42_pcmpestris128:
9860 Opcode = X86ISD::PCMPESTRI;
9861 X86CC = X86::COND_S;
9863 case Intrinsic::x86_sse42_pcmpistriz128:
9864 Opcode = X86ISD::PCMPISTRI;
9865 X86CC = X86::COND_E;
9867 case Intrinsic::x86_sse42_pcmpestriz128:
9868 Opcode = X86ISD::PCMPESTRI;
9869 X86CC = X86::COND_E;
9872 SmallVector<SDValue, 5> NewOps;
9873 NewOps.append(Op->op_begin()+1, Op->op_end());
9874 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
9875 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps.data(), NewOps.size());
9876 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9877 DAG.getConstant(X86CC, MVT::i8),
9878 SDValue(PCMP.getNode(), 1));
9879 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
9881 case Intrinsic::x86_sse42_pcmpistri128:
9882 case Intrinsic::x86_sse42_pcmpestri128: {
9884 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
9885 Opcode = X86ISD::PCMPISTRI;
9887 Opcode = X86ISD::PCMPESTRI;
9889 SmallVector<SDValue, 5> NewOps;
9890 NewOps.append(Op->op_begin()+1, Op->op_end());
9891 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
9892 return DAG.getNode(Opcode, dl, VTs, NewOps.data(), NewOps.size());
9898 X86TargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const {
9899 DebugLoc dl = Op.getDebugLoc();
9900 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
9902 default: return SDValue(); // Don't custom lower most intrinsics.
9904 // RDRAND intrinsics.
9905 case Intrinsic::x86_rdrand_16:
9906 case Intrinsic::x86_rdrand_32:
9907 case Intrinsic::x86_rdrand_64: {
9908 // Emit the node with the right value type.
9909 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
9910 SDValue Result = DAG.getNode(X86ISD::RDRAND, dl, VTs, Op.getOperand(0));
9912 // If the value returned by RDRAND was valid (CF=1), return 1. Otherwise
9913 // return the value from Rand, which is always 0, casted to i32.
9914 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
9915 DAG.getConstant(1, Op->getValueType(1)),
9916 DAG.getConstant(X86::COND_B, MVT::i32),
9917 SDValue(Result.getNode(), 1) };
9918 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
9919 DAG.getVTList(Op->getValueType(1), MVT::Glue),
9922 // Return { result, isValid, chain }.
9923 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
9924 SDValue(Result.getNode(), 2));
9929 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
9930 SelectionDAG &DAG) const {
9931 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9932 MFI->setReturnAddressIsTaken(true);
9934 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9935 DebugLoc dl = Op.getDebugLoc();
9938 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
9940 DAG.getConstant(TD->getPointerSize(),
9941 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
9942 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9943 DAG.getNode(ISD::ADD, dl, getPointerTy(),
9945 MachinePointerInfo(), false, false, false, 0);
9948 // Just load the return address.
9949 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
9950 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9951 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
9954 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
9955 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9956 MFI->setFrameAddressIsTaken(true);
9958 EVT VT = Op.getValueType();
9959 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
9960 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9961 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
9962 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
9964 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
9965 MachinePointerInfo(),
9966 false, false, false, 0);
9970 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
9971 SelectionDAG &DAG) const {
9972 return DAG.getIntPtrConstant(2*TD->getPointerSize());
9975 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
9976 SDValue Chain = Op.getOperand(0);
9977 SDValue Offset = Op.getOperand(1);
9978 SDValue Handler = Op.getOperand(2);
9979 DebugLoc dl = Op.getDebugLoc();
9981 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
9982 Subtarget->is64Bit() ? X86::RBP : X86::EBP,
9984 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
9986 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame,
9987 DAG.getIntPtrConstant(TD->getPointerSize()));
9988 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
9989 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
9991 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
9993 return DAG.getNode(X86ISD::EH_RETURN, dl,
9995 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
9998 SDValue X86TargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
9999 SelectionDAG &DAG) const {
10000 return Op.getOperand(0);
10003 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
10004 SelectionDAG &DAG) const {
10005 SDValue Root = Op.getOperand(0);
10006 SDValue Trmp = Op.getOperand(1); // trampoline
10007 SDValue FPtr = Op.getOperand(2); // nested function
10008 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
10009 DebugLoc dl = Op.getDebugLoc();
10011 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
10013 if (Subtarget->is64Bit()) {
10014 SDValue OutChains[6];
10016 // Large code-model.
10017 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
10018 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
10020 const unsigned char N86R10 = X86_MC::getX86RegNum(X86::R10);
10021 const unsigned char N86R11 = X86_MC::getX86RegNum(X86::R11);
10023 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
10025 // Load the pointer to the nested function into R11.
10026 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
10027 SDValue Addr = Trmp;
10028 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
10029 Addr, MachinePointerInfo(TrmpAddr),
10032 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
10033 DAG.getConstant(2, MVT::i64));
10034 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
10035 MachinePointerInfo(TrmpAddr, 2),
10038 // Load the 'nest' parameter value into R10.
10039 // R10 is specified in X86CallingConv.td
10040 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
10041 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
10042 DAG.getConstant(10, MVT::i64));
10043 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
10044 Addr, MachinePointerInfo(TrmpAddr, 10),
10047 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
10048 DAG.getConstant(12, MVT::i64));
10049 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
10050 MachinePointerInfo(TrmpAddr, 12),
10053 // Jump to the nested function.
10054 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
10055 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
10056 DAG.getConstant(20, MVT::i64));
10057 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
10058 Addr, MachinePointerInfo(TrmpAddr, 20),
10061 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
10062 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
10063 DAG.getConstant(22, MVT::i64));
10064 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
10065 MachinePointerInfo(TrmpAddr, 22),
10068 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6);
10070 const Function *Func =
10071 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
10072 CallingConv::ID CC = Func->getCallingConv();
10077 llvm_unreachable("Unsupported calling convention");
10078 case CallingConv::C:
10079 case CallingConv::X86_StdCall: {
10080 // Pass 'nest' parameter in ECX.
10081 // Must be kept in sync with X86CallingConv.td
10082 NestReg = X86::ECX;
10084 // Check that ECX wasn't needed by an 'inreg' parameter.
10085 FunctionType *FTy = Func->getFunctionType();
10086 const AttrListPtr &Attrs = Func->getAttributes();
10088 if (!Attrs.isEmpty() && !Func->isVarArg()) {
10089 unsigned InRegCount = 0;
10092 for (FunctionType::param_iterator I = FTy->param_begin(),
10093 E = FTy->param_end(); I != E; ++I, ++Idx)
10094 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
10095 // FIXME: should only count parameters that are lowered to integers.
10096 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
10098 if (InRegCount > 2) {
10099 report_fatal_error("Nest register in use - reduce number of inreg"
10105 case CallingConv::X86_FastCall:
10106 case CallingConv::X86_ThisCall:
10107 case CallingConv::Fast:
10108 // Pass 'nest' parameter in EAX.
10109 // Must be kept in sync with X86CallingConv.td
10110 NestReg = X86::EAX;
10114 SDValue OutChains[4];
10115 SDValue Addr, Disp;
10117 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
10118 DAG.getConstant(10, MVT::i32));
10119 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
10121 // This is storing the opcode for MOV32ri.
10122 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
10123 const unsigned char N86Reg = X86_MC::getX86RegNum(NestReg);
10124 OutChains[0] = DAG.getStore(Root, dl,
10125 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
10126 Trmp, MachinePointerInfo(TrmpAddr),
10129 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
10130 DAG.getConstant(1, MVT::i32));
10131 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
10132 MachinePointerInfo(TrmpAddr, 1),
10135 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
10136 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
10137 DAG.getConstant(5, MVT::i32));
10138 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
10139 MachinePointerInfo(TrmpAddr, 5),
10142 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
10143 DAG.getConstant(6, MVT::i32));
10144 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
10145 MachinePointerInfo(TrmpAddr, 6),
10148 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4);
10152 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
10153 SelectionDAG &DAG) const {
10155 The rounding mode is in bits 11:10 of FPSR, and has the following
10157 00 Round to nearest
10162 FLT_ROUNDS, on the other hand, expects the following:
10169 To perform the conversion, we do:
10170 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
10173 MachineFunction &MF = DAG.getMachineFunction();
10174 const TargetMachine &TM = MF.getTarget();
10175 const TargetFrameLowering &TFI = *TM.getFrameLowering();
10176 unsigned StackAlignment = TFI.getStackAlignment();
10177 EVT VT = Op.getValueType();
10178 DebugLoc DL = Op.getDebugLoc();
10180 // Save FP Control Word to stack slot
10181 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
10182 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
10185 MachineMemOperand *MMO =
10186 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
10187 MachineMemOperand::MOStore, 2, 2);
10189 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
10190 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
10191 DAG.getVTList(MVT::Other),
10192 Ops, 2, MVT::i16, MMO);
10194 // Load FP Control Word from stack slot
10195 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
10196 MachinePointerInfo(), false, false, false, 0);
10198 // Transform as necessary
10200 DAG.getNode(ISD::SRL, DL, MVT::i16,
10201 DAG.getNode(ISD::AND, DL, MVT::i16,
10202 CWD, DAG.getConstant(0x800, MVT::i16)),
10203 DAG.getConstant(11, MVT::i8));
10205 DAG.getNode(ISD::SRL, DL, MVT::i16,
10206 DAG.getNode(ISD::AND, DL, MVT::i16,
10207 CWD, DAG.getConstant(0x400, MVT::i16)),
10208 DAG.getConstant(9, MVT::i8));
10211 DAG.getNode(ISD::AND, DL, MVT::i16,
10212 DAG.getNode(ISD::ADD, DL, MVT::i16,
10213 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
10214 DAG.getConstant(1, MVT::i16)),
10215 DAG.getConstant(3, MVT::i16));
10218 return DAG.getNode((VT.getSizeInBits() < 16 ?
10219 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
10222 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const {
10223 EVT VT = Op.getValueType();
10225 unsigned NumBits = VT.getSizeInBits();
10226 DebugLoc dl = Op.getDebugLoc();
10228 Op = Op.getOperand(0);
10229 if (VT == MVT::i8) {
10230 // Zero extend to i32 since there is not an i8 bsr.
10232 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
10235 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
10236 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
10237 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
10239 // If src is zero (i.e. bsr sets ZF), returns NumBits.
10242 DAG.getConstant(NumBits+NumBits-1, OpVT),
10243 DAG.getConstant(X86::COND_E, MVT::i8),
10246 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
10248 // Finally xor with NumBits-1.
10249 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
10252 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
10256 SDValue X86TargetLowering::LowerCTLZ_ZERO_UNDEF(SDValue Op,
10257 SelectionDAG &DAG) const {
10258 EVT VT = Op.getValueType();
10260 unsigned NumBits = VT.getSizeInBits();
10261 DebugLoc dl = Op.getDebugLoc();
10263 Op = Op.getOperand(0);
10264 if (VT == MVT::i8) {
10265 // Zero extend to i32 since there is not an i8 bsr.
10267 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
10270 // Issue a bsr (scan bits in reverse).
10271 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
10272 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
10274 // And xor with NumBits-1.
10275 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
10278 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
10282 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const {
10283 EVT VT = Op.getValueType();
10284 unsigned NumBits = VT.getSizeInBits();
10285 DebugLoc dl = Op.getDebugLoc();
10286 Op = Op.getOperand(0);
10288 // Issue a bsf (scan bits forward) which also sets EFLAGS.
10289 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
10290 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
10292 // If src is zero (i.e. bsf sets ZF), returns NumBits.
10295 DAG.getConstant(NumBits, VT),
10296 DAG.getConstant(X86::COND_E, MVT::i8),
10299 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops, array_lengthof(Ops));
10302 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
10303 // ones, and then concatenate the result back.
10304 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
10305 EVT VT = Op.getValueType();
10307 assert(VT.is256BitVector() && VT.isInteger() &&
10308 "Unsupported value type for operation");
10310 unsigned NumElems = VT.getVectorNumElements();
10311 DebugLoc dl = Op.getDebugLoc();
10313 // Extract the LHS vectors
10314 SDValue LHS = Op.getOperand(0);
10315 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
10316 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
10318 // Extract the RHS vectors
10319 SDValue RHS = Op.getOperand(1);
10320 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
10321 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
10323 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10324 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10326 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
10327 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
10328 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
10331 SDValue X86TargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) const {
10332 assert(Op.getValueType().is256BitVector() &&
10333 Op.getValueType().isInteger() &&
10334 "Only handle AVX 256-bit vector integer operation");
10335 return Lower256IntArith(Op, DAG);
10338 SDValue X86TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) const {
10339 assert(Op.getValueType().is256BitVector() &&
10340 Op.getValueType().isInteger() &&
10341 "Only handle AVX 256-bit vector integer operation");
10342 return Lower256IntArith(Op, DAG);
10345 SDValue X86TargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
10346 EVT VT = Op.getValueType();
10348 // Decompose 256-bit ops into smaller 128-bit ops.
10349 if (VT.is256BitVector() && !Subtarget->hasAVX2())
10350 return Lower256IntArith(Op, DAG);
10352 assert((VT == MVT::v2i64 || VT == MVT::v4i64) &&
10353 "Only know how to lower V2I64/V4I64 multiply");
10355 DebugLoc dl = Op.getDebugLoc();
10357 // Ahi = psrlqi(a, 32);
10358 // Bhi = psrlqi(b, 32);
10360 // AloBlo = pmuludq(a, b);
10361 // AloBhi = pmuludq(a, Bhi);
10362 // AhiBlo = pmuludq(Ahi, b);
10364 // AloBhi = psllqi(AloBhi, 32);
10365 // AhiBlo = psllqi(AhiBlo, 32);
10366 // return AloBlo + AloBhi + AhiBlo;
10368 SDValue A = Op.getOperand(0);
10369 SDValue B = Op.getOperand(1);
10371 SDValue ShAmt = DAG.getConstant(32, MVT::i32);
10373 SDValue Ahi = DAG.getNode(X86ISD::VSRLI, dl, VT, A, ShAmt);
10374 SDValue Bhi = DAG.getNode(X86ISD::VSRLI, dl, VT, B, ShAmt);
10376 // Bit cast to 32-bit vectors for MULUDQ
10377 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 : MVT::v8i32;
10378 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
10379 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
10380 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
10381 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
10383 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
10384 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
10385 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
10387 AloBhi = DAG.getNode(X86ISD::VSHLI, dl, VT, AloBhi, ShAmt);
10388 AhiBlo = DAG.getNode(X86ISD::VSHLI, dl, VT, AhiBlo, ShAmt);
10390 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
10391 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
10394 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
10396 EVT VT = Op.getValueType();
10397 DebugLoc dl = Op.getDebugLoc();
10398 SDValue R = Op.getOperand(0);
10399 SDValue Amt = Op.getOperand(1);
10400 LLVMContext *Context = DAG.getContext();
10402 if (!Subtarget->hasSSE2())
10405 // Optimize shl/srl/sra with constant shift amount.
10406 if (isSplatVector(Amt.getNode())) {
10407 SDValue SclrAmt = Amt->getOperand(0);
10408 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
10409 uint64_t ShiftAmt = C->getZExtValue();
10411 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
10412 (Subtarget->hasAVX2() &&
10413 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16))) {
10414 if (Op.getOpcode() == ISD::SHL)
10415 return DAG.getNode(X86ISD::VSHLI, dl, VT, R,
10416 DAG.getConstant(ShiftAmt, MVT::i32));
10417 if (Op.getOpcode() == ISD::SRL)
10418 return DAG.getNode(X86ISD::VSRLI, dl, VT, R,
10419 DAG.getConstant(ShiftAmt, MVT::i32));
10420 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
10421 return DAG.getNode(X86ISD::VSRAI, dl, VT, R,
10422 DAG.getConstant(ShiftAmt, MVT::i32));
10425 if (VT == MVT::v16i8) {
10426 if (Op.getOpcode() == ISD::SHL) {
10427 // Make a large shift.
10428 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, R,
10429 DAG.getConstant(ShiftAmt, MVT::i32));
10430 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
10431 // Zero out the rightmost bits.
10432 SmallVector<SDValue, 16> V(16,
10433 DAG.getConstant(uint8_t(-1U << ShiftAmt),
10435 return DAG.getNode(ISD::AND, dl, VT, SHL,
10436 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
10438 if (Op.getOpcode() == ISD::SRL) {
10439 // Make a large shift.
10440 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v8i16, R,
10441 DAG.getConstant(ShiftAmt, MVT::i32));
10442 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
10443 // Zero out the leftmost bits.
10444 SmallVector<SDValue, 16> V(16,
10445 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
10447 return DAG.getNode(ISD::AND, dl, VT, SRL,
10448 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
10450 if (Op.getOpcode() == ISD::SRA) {
10451 if (ShiftAmt == 7) {
10452 // R s>> 7 === R s< 0
10453 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
10454 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
10457 // R s>> a === ((R u>> a) ^ m) - m
10458 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
10459 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
10461 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16);
10462 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
10463 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
10466 llvm_unreachable("Unknown shift opcode.");
10469 if (Subtarget->hasAVX2() && VT == MVT::v32i8) {
10470 if (Op.getOpcode() == ISD::SHL) {
10471 // Make a large shift.
10472 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v16i16, R,
10473 DAG.getConstant(ShiftAmt, MVT::i32));
10474 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
10475 // Zero out the rightmost bits.
10476 SmallVector<SDValue, 32> V(32,
10477 DAG.getConstant(uint8_t(-1U << ShiftAmt),
10479 return DAG.getNode(ISD::AND, dl, VT, SHL,
10480 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
10482 if (Op.getOpcode() == ISD::SRL) {
10483 // Make a large shift.
10484 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v16i16, R,
10485 DAG.getConstant(ShiftAmt, MVT::i32));
10486 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
10487 // Zero out the leftmost bits.
10488 SmallVector<SDValue, 32> V(32,
10489 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
10491 return DAG.getNode(ISD::AND, dl, VT, SRL,
10492 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
10494 if (Op.getOpcode() == ISD::SRA) {
10495 if (ShiftAmt == 7) {
10496 // R s>> 7 === R s< 0
10497 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
10498 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
10501 // R s>> a === ((R u>> a) ^ m) - m
10502 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
10503 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
10505 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32);
10506 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
10507 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
10510 llvm_unreachable("Unknown shift opcode.");
10515 // Lower SHL with variable shift amount.
10516 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
10517 Op = DAG.getNode(X86ISD::VSHLI, dl, VT, Op.getOperand(1),
10518 DAG.getConstant(23, MVT::i32));
10520 const uint32_t CV[] = { 0x3f800000U, 0x3f800000U, 0x3f800000U, 0x3f800000U};
10521 Constant *C = ConstantDataVector::get(*Context, CV);
10522 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
10523 SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
10524 MachinePointerInfo::getConstantPool(),
10525 false, false, false, 16);
10527 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend);
10528 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
10529 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
10530 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
10532 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
10533 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
10536 Op = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, Op.getOperand(1),
10537 DAG.getConstant(5, MVT::i32));
10538 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
10540 // Turn 'a' into a mask suitable for VSELECT
10541 SDValue VSelM = DAG.getConstant(0x80, VT);
10542 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10543 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
10545 SDValue CM1 = DAG.getConstant(0x0f, VT);
10546 SDValue CM2 = DAG.getConstant(0x3f, VT);
10548 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
10549 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
10550 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M,
10551 DAG.getConstant(4, MVT::i32), DAG);
10552 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
10553 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
10556 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
10557 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10558 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
10560 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
10561 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
10562 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M,
10563 DAG.getConstant(2, MVT::i32), DAG);
10564 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
10565 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
10568 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
10569 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10570 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
10572 // return VSELECT(r, r+r, a);
10573 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
10574 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
10578 // Decompose 256-bit shifts into smaller 128-bit shifts.
10579 if (VT.is256BitVector()) {
10580 unsigned NumElems = VT.getVectorNumElements();
10581 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10582 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10584 // Extract the two vectors
10585 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
10586 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
10588 // Recreate the shift amount vectors
10589 SDValue Amt1, Amt2;
10590 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
10591 // Constant shift amount
10592 SmallVector<SDValue, 4> Amt1Csts;
10593 SmallVector<SDValue, 4> Amt2Csts;
10594 for (unsigned i = 0; i != NumElems/2; ++i)
10595 Amt1Csts.push_back(Amt->getOperand(i));
10596 for (unsigned i = NumElems/2; i != NumElems; ++i)
10597 Amt2Csts.push_back(Amt->getOperand(i));
10599 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
10600 &Amt1Csts[0], NumElems/2);
10601 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
10602 &Amt2Csts[0], NumElems/2);
10604 // Variable shift amount
10605 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
10606 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
10609 // Issue new vector shifts for the smaller types
10610 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
10611 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
10613 // Concatenate the result back
10614 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
10620 SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {
10621 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
10622 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
10623 // looks for this combo and may remove the "setcc" instruction if the "setcc"
10624 // has only one use.
10625 SDNode *N = Op.getNode();
10626 SDValue LHS = N->getOperand(0);
10627 SDValue RHS = N->getOperand(1);
10628 unsigned BaseOp = 0;
10630 DebugLoc DL = Op.getDebugLoc();
10631 switch (Op.getOpcode()) {
10632 default: llvm_unreachable("Unknown ovf instruction!");
10634 // A subtract of one will be selected as a INC. Note that INC doesn't
10635 // set CF, so we can't do this for UADDO.
10636 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
10638 BaseOp = X86ISD::INC;
10639 Cond = X86::COND_O;
10642 BaseOp = X86ISD::ADD;
10643 Cond = X86::COND_O;
10646 BaseOp = X86ISD::ADD;
10647 Cond = X86::COND_B;
10650 // A subtract of one will be selected as a DEC. Note that DEC doesn't
10651 // set CF, so we can't do this for USUBO.
10652 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
10654 BaseOp = X86ISD::DEC;
10655 Cond = X86::COND_O;
10658 BaseOp = X86ISD::SUB;
10659 Cond = X86::COND_O;
10662 BaseOp = X86ISD::SUB;
10663 Cond = X86::COND_B;
10666 BaseOp = X86ISD::SMUL;
10667 Cond = X86::COND_O;
10669 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
10670 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
10672 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
10675 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
10676 DAG.getConstant(X86::COND_O, MVT::i32),
10677 SDValue(Sum.getNode(), 2));
10679 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
10683 // Also sets EFLAGS.
10684 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
10685 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
10688 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
10689 DAG.getConstant(Cond, MVT::i32),
10690 SDValue(Sum.getNode(), 1));
10692 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
10695 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
10696 SelectionDAG &DAG) const {
10697 DebugLoc dl = Op.getDebugLoc();
10698 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
10699 EVT VT = Op.getValueType();
10701 if (!Subtarget->hasSSE2() || !VT.isVector())
10704 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
10705 ExtraVT.getScalarType().getSizeInBits();
10706 SDValue ShAmt = DAG.getConstant(BitsDiff, MVT::i32);
10708 switch (VT.getSimpleVT().SimpleTy) {
10709 default: return SDValue();
10712 if (!Subtarget->hasAVX())
10714 if (!Subtarget->hasAVX2()) {
10715 // needs to be split
10716 unsigned NumElems = VT.getVectorNumElements();
10718 // Extract the LHS vectors
10719 SDValue LHS = Op.getOperand(0);
10720 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
10721 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
10723 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10724 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10726 EVT ExtraEltVT = ExtraVT.getVectorElementType();
10727 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
10728 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
10730 SDValue Extra = DAG.getValueType(ExtraVT);
10732 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
10733 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
10735 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);;
10740 SDValue Tmp1 = getTargetVShiftNode(X86ISD::VSHLI, dl, VT,
10741 Op.getOperand(0), ShAmt, DAG);
10742 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, Tmp1, ShAmt, DAG);
10748 SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{
10749 DebugLoc dl = Op.getDebugLoc();
10751 // Go ahead and emit the fence on x86-64 even if we asked for no-sse2.
10752 // There isn't any reason to disable it if the target processor supports it.
10753 if (!Subtarget->hasSSE2() && !Subtarget->is64Bit()) {
10754 SDValue Chain = Op.getOperand(0);
10755 SDValue Zero = DAG.getConstant(0, MVT::i32);
10757 DAG.getRegister(X86::ESP, MVT::i32), // Base
10758 DAG.getTargetConstant(1, MVT::i8), // Scale
10759 DAG.getRegister(0, MVT::i32), // Index
10760 DAG.getTargetConstant(0, MVT::i32), // Disp
10761 DAG.getRegister(0, MVT::i32), // Segment.
10766 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
10767 array_lengthof(Ops));
10768 return SDValue(Res, 0);
10771 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue();
10773 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
10775 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10776 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
10777 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
10778 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
10780 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
10781 if (!Op1 && !Op2 && !Op3 && Op4)
10782 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0));
10784 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
10785 if (Op1 && !Op2 && !Op3 && !Op4)
10786 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0));
10788 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)),
10790 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
10793 SDValue X86TargetLowering::LowerATOMIC_FENCE(SDValue Op,
10794 SelectionDAG &DAG) const {
10795 DebugLoc dl = Op.getDebugLoc();
10796 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
10797 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
10798 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
10799 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
10801 // The only fence that needs an instruction is a sequentially-consistent
10802 // cross-thread fence.
10803 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
10804 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
10805 // no-sse2). There isn't any reason to disable it if the target processor
10807 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
10808 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
10810 SDValue Chain = Op.getOperand(0);
10811 SDValue Zero = DAG.getConstant(0, MVT::i32);
10813 DAG.getRegister(X86::ESP, MVT::i32), // Base
10814 DAG.getTargetConstant(1, MVT::i8), // Scale
10815 DAG.getRegister(0, MVT::i32), // Index
10816 DAG.getTargetConstant(0, MVT::i32), // Disp
10817 DAG.getRegister(0, MVT::i32), // Segment.
10822 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
10823 array_lengthof(Ops));
10824 return SDValue(Res, 0);
10827 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
10828 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
10832 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const {
10833 EVT T = Op.getValueType();
10834 DebugLoc DL = Op.getDebugLoc();
10837 switch(T.getSimpleVT().SimpleTy) {
10838 default: llvm_unreachable("Invalid value type!");
10839 case MVT::i8: Reg = X86::AL; size = 1; break;
10840 case MVT::i16: Reg = X86::AX; size = 2; break;
10841 case MVT::i32: Reg = X86::EAX; size = 4; break;
10843 assert(Subtarget->is64Bit() && "Node not type legal!");
10844 Reg = X86::RAX; size = 8;
10847 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
10848 Op.getOperand(2), SDValue());
10849 SDValue Ops[] = { cpIn.getValue(0),
10852 DAG.getTargetConstant(size, MVT::i8),
10853 cpIn.getValue(1) };
10854 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10855 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
10856 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
10859 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
10863 SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
10864 SelectionDAG &DAG) const {
10865 assert(Subtarget->is64Bit() && "Result not type legalized?");
10866 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10867 SDValue TheChain = Op.getOperand(0);
10868 DebugLoc dl = Op.getDebugLoc();
10869 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
10870 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
10871 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
10873 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
10874 DAG.getConstant(32, MVT::i8));
10876 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
10879 return DAG.getMergeValues(Ops, 2, dl);
10882 SDValue X86TargetLowering::LowerBITCAST(SDValue Op,
10883 SelectionDAG &DAG) const {
10884 EVT SrcVT = Op.getOperand(0).getValueType();
10885 EVT DstVT = Op.getValueType();
10886 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
10887 Subtarget->hasMMX() && "Unexpected custom BITCAST");
10888 assert((DstVT == MVT::i64 ||
10889 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
10890 "Unexpected custom BITCAST");
10891 // i64 <=> MMX conversions are Legal.
10892 if (SrcVT==MVT::i64 && DstVT.isVector())
10894 if (DstVT==MVT::i64 && SrcVT.isVector())
10896 // MMX <=> MMX conversions are Legal.
10897 if (SrcVT.isVector() && DstVT.isVector())
10899 // All other conversions need to be expanded.
10903 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const {
10904 SDNode *Node = Op.getNode();
10905 DebugLoc dl = Node->getDebugLoc();
10906 EVT T = Node->getValueType(0);
10907 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
10908 DAG.getConstant(0, T), Node->getOperand(2));
10909 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
10910 cast<AtomicSDNode>(Node)->getMemoryVT(),
10911 Node->getOperand(0),
10912 Node->getOperand(1), negOp,
10913 cast<AtomicSDNode>(Node)->getSrcValue(),
10914 cast<AtomicSDNode>(Node)->getAlignment(),
10915 cast<AtomicSDNode>(Node)->getOrdering(),
10916 cast<AtomicSDNode>(Node)->getSynchScope());
10919 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
10920 SDNode *Node = Op.getNode();
10921 DebugLoc dl = Node->getDebugLoc();
10922 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
10924 // Convert seq_cst store -> xchg
10925 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
10926 // FIXME: On 32-bit, store -> fist or movq would be more efficient
10927 // (The only way to get a 16-byte store is cmpxchg16b)
10928 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
10929 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
10930 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
10931 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
10932 cast<AtomicSDNode>(Node)->getMemoryVT(),
10933 Node->getOperand(0),
10934 Node->getOperand(1), Node->getOperand(2),
10935 cast<AtomicSDNode>(Node)->getMemOperand(),
10936 cast<AtomicSDNode>(Node)->getOrdering(),
10937 cast<AtomicSDNode>(Node)->getSynchScope());
10938 return Swap.getValue(1);
10940 // Other atomic stores have a simple pattern.
10944 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
10945 EVT VT = Op.getNode()->getValueType(0);
10947 // Let legalize expand this if it isn't a legal type yet.
10948 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
10951 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
10954 bool ExtraOp = false;
10955 switch (Op.getOpcode()) {
10956 default: llvm_unreachable("Invalid code");
10957 case ISD::ADDC: Opc = X86ISD::ADD; break;
10958 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
10959 case ISD::SUBC: Opc = X86ISD::SUB; break;
10960 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
10964 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
10966 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
10967 Op.getOperand(1), Op.getOperand(2));
10970 /// LowerOperation - Provide custom lowering hooks for some operations.
10972 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
10973 switch (Op.getOpcode()) {
10974 default: llvm_unreachable("Should not custom lower this!");
10975 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
10976 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op,DAG);
10977 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op,DAG);
10978 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
10979 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
10980 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
10981 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
10982 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
10983 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
10984 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
10985 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
10986 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
10987 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG);
10988 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
10989 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
10990 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
10991 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
10992 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
10993 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
10994 case ISD::SHL_PARTS:
10995 case ISD::SRA_PARTS:
10996 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
10997 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
10998 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
10999 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
11000 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
11001 case ISD::FABS: return LowerFABS(Op, DAG);
11002 case ISD::FNEG: return LowerFNEG(Op, DAG);
11003 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
11004 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
11005 case ISD::SETCC: return LowerSETCC(Op, DAG);
11006 case ISD::SELECT: return LowerSELECT(Op, DAG);
11007 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
11008 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
11009 case ISD::VASTART: return LowerVASTART(Op, DAG);
11010 case ISD::VAARG: return LowerVAARG(Op, DAG);
11011 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
11012 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
11013 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, DAG);
11014 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
11015 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
11016 case ISD::FRAME_TO_ARGS_OFFSET:
11017 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
11018 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
11019 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
11020 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
11021 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
11022 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
11023 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
11024 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
11025 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
11026 case ISD::MUL: return LowerMUL(Op, DAG);
11029 case ISD::SHL: return LowerShift(Op, DAG);
11035 case ISD::UMULO: return LowerXALUO(Op, DAG);
11036 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
11037 case ISD::BITCAST: return LowerBITCAST(Op, DAG);
11041 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
11042 case ISD::ADD: return LowerADD(Op, DAG);
11043 case ISD::SUB: return LowerSUB(Op, DAG);
11047 static void ReplaceATOMIC_LOAD(SDNode *Node,
11048 SmallVectorImpl<SDValue> &Results,
11049 SelectionDAG &DAG) {
11050 DebugLoc dl = Node->getDebugLoc();
11051 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
11053 // Convert wide load -> cmpxchg8b/cmpxchg16b
11054 // FIXME: On 32-bit, load -> fild or movq would be more efficient
11055 // (The only way to get a 16-byte load is cmpxchg16b)
11056 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
11057 SDValue Zero = DAG.getConstant(0, VT);
11058 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT,
11059 Node->getOperand(0),
11060 Node->getOperand(1), Zero, Zero,
11061 cast<AtomicSDNode>(Node)->getMemOperand(),
11062 cast<AtomicSDNode>(Node)->getOrdering(),
11063 cast<AtomicSDNode>(Node)->getSynchScope());
11064 Results.push_back(Swap.getValue(0));
11065 Results.push_back(Swap.getValue(1));
11068 void X86TargetLowering::
11069 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
11070 SelectionDAG &DAG, unsigned NewOp) const {
11071 DebugLoc dl = Node->getDebugLoc();
11072 assert (Node->getValueType(0) == MVT::i64 &&
11073 "Only know how to expand i64 atomics");
11075 SDValue Chain = Node->getOperand(0);
11076 SDValue In1 = Node->getOperand(1);
11077 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
11078 Node->getOperand(2), DAG.getIntPtrConstant(0));
11079 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
11080 Node->getOperand(2), DAG.getIntPtrConstant(1));
11081 SDValue Ops[] = { Chain, In1, In2L, In2H };
11082 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
11084 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64,
11085 cast<MemSDNode>(Node)->getMemOperand());
11086 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
11087 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
11088 Results.push_back(Result.getValue(2));
11091 /// ReplaceNodeResults - Replace a node with an illegal result type
11092 /// with a new node built out of custom code.
11093 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
11094 SmallVectorImpl<SDValue>&Results,
11095 SelectionDAG &DAG) const {
11096 DebugLoc dl = N->getDebugLoc();
11097 switch (N->getOpcode()) {
11099 llvm_unreachable("Do not know how to custom type legalize this operation!");
11100 case ISD::SIGN_EXTEND_INREG:
11105 // We don't want to expand or promote these.
11107 case ISD::FP_TO_SINT:
11108 case ISD::FP_TO_UINT: {
11109 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
11111 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
11114 std::pair<SDValue,SDValue> Vals =
11115 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
11116 SDValue FIST = Vals.first, StackSlot = Vals.second;
11117 if (FIST.getNode() != 0) {
11118 EVT VT = N->getValueType(0);
11119 // Return a load from the stack slot.
11120 if (StackSlot.getNode() != 0)
11121 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
11122 MachinePointerInfo(),
11123 false, false, false, 0));
11125 Results.push_back(FIST);
11129 case ISD::READCYCLECOUNTER: {
11130 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
11131 SDValue TheChain = N->getOperand(0);
11132 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
11133 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
11135 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
11137 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
11138 SDValue Ops[] = { eax, edx };
11139 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
11140 Results.push_back(edx.getValue(1));
11143 case ISD::ATOMIC_CMP_SWAP: {
11144 EVT T = N->getValueType(0);
11145 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
11146 bool Regs64bit = T == MVT::i128;
11147 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
11148 SDValue cpInL, cpInH;
11149 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
11150 DAG.getConstant(0, HalfT));
11151 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
11152 DAG.getConstant(1, HalfT));
11153 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
11154 Regs64bit ? X86::RAX : X86::EAX,
11156 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
11157 Regs64bit ? X86::RDX : X86::EDX,
11158 cpInH, cpInL.getValue(1));
11159 SDValue swapInL, swapInH;
11160 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
11161 DAG.getConstant(0, HalfT));
11162 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
11163 DAG.getConstant(1, HalfT));
11164 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
11165 Regs64bit ? X86::RBX : X86::EBX,
11166 swapInL, cpInH.getValue(1));
11167 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
11168 Regs64bit ? X86::RCX : X86::ECX,
11169 swapInH, swapInL.getValue(1));
11170 SDValue Ops[] = { swapInH.getValue(0),
11172 swapInH.getValue(1) };
11173 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
11174 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
11175 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
11176 X86ISD::LCMPXCHG8_DAG;
11177 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys,
11179 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
11180 Regs64bit ? X86::RAX : X86::EAX,
11181 HalfT, Result.getValue(1));
11182 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
11183 Regs64bit ? X86::RDX : X86::EDX,
11184 HalfT, cpOutL.getValue(2));
11185 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
11186 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2));
11187 Results.push_back(cpOutH.getValue(1));
11190 case ISD::ATOMIC_LOAD_ADD:
11191 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
11193 case ISD::ATOMIC_LOAD_AND:
11194 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
11196 case ISD::ATOMIC_LOAD_NAND:
11197 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
11199 case ISD::ATOMIC_LOAD_OR:
11200 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
11202 case ISD::ATOMIC_LOAD_SUB:
11203 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
11205 case ISD::ATOMIC_LOAD_XOR:
11206 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
11208 case ISD::ATOMIC_SWAP:
11209 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
11211 case ISD::ATOMIC_LOAD:
11212 ReplaceATOMIC_LOAD(N, Results, DAG);
11216 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
11218 default: return NULL;
11219 case X86ISD::BSF: return "X86ISD::BSF";
11220 case X86ISD::BSR: return "X86ISD::BSR";
11221 case X86ISD::SHLD: return "X86ISD::SHLD";
11222 case X86ISD::SHRD: return "X86ISD::SHRD";
11223 case X86ISD::FAND: return "X86ISD::FAND";
11224 case X86ISD::FOR: return "X86ISD::FOR";
11225 case X86ISD::FXOR: return "X86ISD::FXOR";
11226 case X86ISD::FSRL: return "X86ISD::FSRL";
11227 case X86ISD::FILD: return "X86ISD::FILD";
11228 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
11229 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
11230 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
11231 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
11232 case X86ISD::FLD: return "X86ISD::FLD";
11233 case X86ISD::FST: return "X86ISD::FST";
11234 case X86ISD::CALL: return "X86ISD::CALL";
11235 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
11236 case X86ISD::BT: return "X86ISD::BT";
11237 case X86ISD::CMP: return "X86ISD::CMP";
11238 case X86ISD::COMI: return "X86ISD::COMI";
11239 case X86ISD::UCOMI: return "X86ISD::UCOMI";
11240 case X86ISD::SETCC: return "X86ISD::SETCC";
11241 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
11242 case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd";
11243 case X86ISD::FSETCCss: return "X86ISD::FSETCCss";
11244 case X86ISD::CMOV: return "X86ISD::CMOV";
11245 case X86ISD::BRCOND: return "X86ISD::BRCOND";
11246 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
11247 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
11248 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
11249 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
11250 case X86ISD::Wrapper: return "X86ISD::Wrapper";
11251 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
11252 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
11253 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
11254 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
11255 case X86ISD::PINSRB: return "X86ISD::PINSRB";
11256 case X86ISD::PINSRW: return "X86ISD::PINSRW";
11257 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
11258 case X86ISD::ANDNP: return "X86ISD::ANDNP";
11259 case X86ISD::PSIGN: return "X86ISD::PSIGN";
11260 case X86ISD::BLENDV: return "X86ISD::BLENDV";
11261 case X86ISD::BLENDPW: return "X86ISD::BLENDPW";
11262 case X86ISD::BLENDPS: return "X86ISD::BLENDPS";
11263 case X86ISD::BLENDPD: return "X86ISD::BLENDPD";
11264 case X86ISD::HADD: return "X86ISD::HADD";
11265 case X86ISD::HSUB: return "X86ISD::HSUB";
11266 case X86ISD::FHADD: return "X86ISD::FHADD";
11267 case X86ISD::FHSUB: return "X86ISD::FHSUB";
11268 case X86ISD::FMAX: return "X86ISD::FMAX";
11269 case X86ISD::FMIN: return "X86ISD::FMIN";
11270 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
11271 case X86ISD::FRCP: return "X86ISD::FRCP";
11272 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
11273 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
11274 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
11275 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
11276 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
11277 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
11278 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
11279 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
11280 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
11281 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
11282 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
11283 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
11284 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
11285 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
11286 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
11287 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
11288 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
11289 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
11290 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
11291 case X86ISD::VSHL: return "X86ISD::VSHL";
11292 case X86ISD::VSRL: return "X86ISD::VSRL";
11293 case X86ISD::VSRA: return "X86ISD::VSRA";
11294 case X86ISD::VSHLI: return "X86ISD::VSHLI";
11295 case X86ISD::VSRLI: return "X86ISD::VSRLI";
11296 case X86ISD::VSRAI: return "X86ISD::VSRAI";
11297 case X86ISD::CMPP: return "X86ISD::CMPP";
11298 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
11299 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
11300 case X86ISD::ADD: return "X86ISD::ADD";
11301 case X86ISD::SUB: return "X86ISD::SUB";
11302 case X86ISD::ADC: return "X86ISD::ADC";
11303 case X86ISD::SBB: return "X86ISD::SBB";
11304 case X86ISD::SMUL: return "X86ISD::SMUL";
11305 case X86ISD::UMUL: return "X86ISD::UMUL";
11306 case X86ISD::INC: return "X86ISD::INC";
11307 case X86ISD::DEC: return "X86ISD::DEC";
11308 case X86ISD::OR: return "X86ISD::OR";
11309 case X86ISD::XOR: return "X86ISD::XOR";
11310 case X86ISD::AND: return "X86ISD::AND";
11311 case X86ISD::ANDN: return "X86ISD::ANDN";
11312 case X86ISD::BLSI: return "X86ISD::BLSI";
11313 case X86ISD::BLSMSK: return "X86ISD::BLSMSK";
11314 case X86ISD::BLSR: return "X86ISD::BLSR";
11315 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
11316 case X86ISD::PTEST: return "X86ISD::PTEST";
11317 case X86ISD::TESTP: return "X86ISD::TESTP";
11318 case X86ISD::PALIGN: return "X86ISD::PALIGN";
11319 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
11320 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
11321 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
11322 case X86ISD::SHUFP: return "X86ISD::SHUFP";
11323 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
11324 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
11325 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
11326 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
11327 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
11328 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
11329 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
11330 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
11331 case X86ISD::MOVSD: return "X86ISD::MOVSD";
11332 case X86ISD::MOVSS: return "X86ISD::MOVSS";
11333 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
11334 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
11335 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
11336 case X86ISD::VPERMILP: return "X86ISD::VPERMILP";
11337 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
11338 case X86ISD::VPERMV: return "X86ISD::VPERMV";
11339 case X86ISD::VPERMI: return "X86ISD::VPERMI";
11340 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
11341 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
11342 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
11343 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
11344 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
11345 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
11346 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
11347 case X86ISD::SAHF: return "X86ISD::SAHF";
11348 case X86ISD::RDRAND: return "X86ISD::RDRAND";
11349 case X86ISD::FMADD: return "X86ISD::FMADD";
11350 case X86ISD::FMSUB: return "X86ISD::FMSUB";
11351 case X86ISD::FNMADD: return "X86ISD::FNMADD";
11352 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
11353 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
11354 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
11358 // isLegalAddressingMode - Return true if the addressing mode represented
11359 // by AM is legal for this target, for a load/store of the specified type.
11360 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
11362 // X86 supports extremely general addressing modes.
11363 CodeModel::Model M = getTargetMachine().getCodeModel();
11364 Reloc::Model R = getTargetMachine().getRelocationModel();
11366 // X86 allows a sign-extended 32-bit immediate field as a displacement.
11367 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
11372 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
11374 // If a reference to this global requires an extra load, we can't fold it.
11375 if (isGlobalStubReference(GVFlags))
11378 // If BaseGV requires a register for the PIC base, we cannot also have a
11379 // BaseReg specified.
11380 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
11383 // If lower 4G is not available, then we must use rip-relative addressing.
11384 if ((M != CodeModel::Small || R != Reloc::Static) &&
11385 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
11389 switch (AM.Scale) {
11395 // These scales always work.
11400 // These scales are formed with basereg+scalereg. Only accept if there is
11405 default: // Other stuff never works.
11413 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
11414 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
11416 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
11417 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
11418 if (NumBits1 <= NumBits2)
11423 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
11424 return Imm == (int32_t)Imm;
11427 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
11428 // Can also use sub to handle negated immediates.
11429 return Imm == (int32_t)Imm;
11432 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
11433 if (!VT1.isInteger() || !VT2.isInteger())
11435 unsigned NumBits1 = VT1.getSizeInBits();
11436 unsigned NumBits2 = VT2.getSizeInBits();
11437 if (NumBits1 <= NumBits2)
11442 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
11443 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
11444 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
11447 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
11448 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
11449 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
11452 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
11453 // i16 instructions are longer (0x66 prefix) and potentially slower.
11454 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
11457 /// isShuffleMaskLegal - Targets can use this to indicate that they only
11458 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
11459 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
11460 /// are assumed to be legal.
11462 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
11464 // Very little shuffling can be done for 64-bit vectors right now.
11465 if (VT.getSizeInBits() == 64)
11468 // FIXME: pshufb, blends, shifts.
11469 return (VT.getVectorNumElements() == 2 ||
11470 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
11471 isMOVLMask(M, VT) ||
11472 isSHUFPMask(M, VT, Subtarget->hasAVX()) ||
11473 isPSHUFDMask(M, VT) ||
11474 isPSHUFHWMask(M, VT, Subtarget->hasAVX2()) ||
11475 isPSHUFLWMask(M, VT, Subtarget->hasAVX2()) ||
11476 isPALIGNRMask(M, VT, Subtarget) ||
11477 isUNPCKLMask(M, VT, Subtarget->hasAVX2()) ||
11478 isUNPCKHMask(M, VT, Subtarget->hasAVX2()) ||
11479 isUNPCKL_v_undef_Mask(M, VT, Subtarget->hasAVX2()) ||
11480 isUNPCKH_v_undef_Mask(M, VT, Subtarget->hasAVX2()));
11484 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
11486 unsigned NumElts = VT.getVectorNumElements();
11487 // FIXME: This collection of masks seems suspect.
11490 if (NumElts == 4 && VT.is128BitVector()) {
11491 return (isMOVLMask(Mask, VT) ||
11492 isCommutedMOVLMask(Mask, VT, true) ||
11493 isSHUFPMask(Mask, VT, Subtarget->hasAVX()) ||
11494 isSHUFPMask(Mask, VT, Subtarget->hasAVX(), /* Commuted */ true));
11499 //===----------------------------------------------------------------------===//
11500 // X86 Scheduler Hooks
11501 //===----------------------------------------------------------------------===//
11503 // private utility function
11504 MachineBasicBlock *
11505 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
11506 MachineBasicBlock *MBB,
11513 const TargetRegisterClass *RC,
11514 bool Invert) const {
11515 // For the atomic bitwise operator, we generate
11518 // ld t1 = [bitinstr.addr]
11519 // op t2 = t1, [bitinstr.val]
11520 // not t3 = t2 (if Invert)
11522 // lcs dest = [bitinstr.addr], t3 [EAX is implicit]
11524 // fallthrough -->nextMBB
11525 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11526 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11527 MachineFunction::iterator MBBIter = MBB;
11530 /// First build the CFG
11531 MachineFunction *F = MBB->getParent();
11532 MachineBasicBlock *thisMBB = MBB;
11533 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11534 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11535 F->insert(MBBIter, newMBB);
11536 F->insert(MBBIter, nextMBB);
11538 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11539 nextMBB->splice(nextMBB->begin(), thisMBB,
11540 llvm::next(MachineBasicBlock::iterator(bInstr)),
11542 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11544 // Update thisMBB to fall through to newMBB
11545 thisMBB->addSuccessor(newMBB);
11547 // newMBB jumps to itself and fall through to nextMBB
11548 newMBB->addSuccessor(nextMBB);
11549 newMBB->addSuccessor(newMBB);
11551 // Insert instructions into newMBB based on incoming instruction
11552 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
11553 "unexpected number of operands");
11554 DebugLoc dl = bInstr->getDebugLoc();
11555 MachineOperand& destOper = bInstr->getOperand(0);
11556 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11557 int numArgs = bInstr->getNumOperands() - 1;
11558 for (int i=0; i < numArgs; ++i)
11559 argOpers[i] = &bInstr->getOperand(i+1);
11561 // x86 address has 4 operands: base, index, scale, and displacement
11562 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11563 int valArgIndx = lastAddrIndx + 1;
11565 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
11566 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1);
11567 for (int i=0; i <= lastAddrIndx; ++i)
11568 (*MIB).addOperand(*argOpers[i]);
11570 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
11571 assert((argOpers[valArgIndx]->isReg() ||
11572 argOpers[valArgIndx]->isImm()) &&
11573 "invalid operand");
11574 if (argOpers[valArgIndx]->isReg())
11575 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2);
11577 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2);
11579 (*MIB).addOperand(*argOpers[valArgIndx]);
11581 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
11583 MIB = BuildMI(newMBB, dl, TII->get(notOpc), t3).addReg(t2);
11588 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg);
11591 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
11592 for (int i=0; i <= lastAddrIndx; ++i)
11593 (*MIB).addOperand(*argOpers[i]);
11595 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11596 (*MIB).setMemRefs(bInstr->memoperands_begin(),
11597 bInstr->memoperands_end());
11599 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
11600 MIB.addReg(EAXreg);
11603 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11605 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
11609 // private utility function: 64 bit atomics on 32 bit host.
11610 MachineBasicBlock *
11611 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
11612 MachineBasicBlock *MBB,
11617 bool Invert) const {
11618 // For the atomic bitwise operator, we generate
11619 // thisMBB (instructions are in pairs, except cmpxchg8b)
11620 // ld t1,t2 = [bitinstr.addr]
11622 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
11623 // op t5, t6 <- out1, out2, [bitinstr.val]
11624 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
11625 // neg t7, t8 < t5, t6 (if Invert)
11626 // mov ECX, EBX <- t5, t6
11627 // mov EAX, EDX <- t1, t2
11628 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
11629 // mov t3, t4 <- EAX, EDX
11631 // result in out1, out2
11632 // fallthrough -->nextMBB
11634 const TargetRegisterClass *RC = &X86::GR32RegClass;
11635 const unsigned LoadOpc = X86::MOV32rm;
11636 const unsigned NotOpc = X86::NOT32r;
11637 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11638 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11639 MachineFunction::iterator MBBIter = MBB;
11642 /// First build the CFG
11643 MachineFunction *F = MBB->getParent();
11644 MachineBasicBlock *thisMBB = MBB;
11645 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11646 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11647 F->insert(MBBIter, newMBB);
11648 F->insert(MBBIter, nextMBB);
11650 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11651 nextMBB->splice(nextMBB->begin(), thisMBB,
11652 llvm::next(MachineBasicBlock::iterator(bInstr)),
11654 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11656 // Update thisMBB to fall through to newMBB
11657 thisMBB->addSuccessor(newMBB);
11659 // newMBB jumps to itself and fall through to nextMBB
11660 newMBB->addSuccessor(nextMBB);
11661 newMBB->addSuccessor(newMBB);
11663 DebugLoc dl = bInstr->getDebugLoc();
11664 // Insert instructions into newMBB based on incoming instruction
11665 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
11666 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 14 &&
11667 "unexpected number of operands");
11668 MachineOperand& dest1Oper = bInstr->getOperand(0);
11669 MachineOperand& dest2Oper = bInstr->getOperand(1);
11670 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11671 for (int i=0; i < 2 + X86::AddrNumOperands; ++i) {
11672 argOpers[i] = &bInstr->getOperand(i+2);
11674 // We use some of the operands multiple times, so conservatively just
11675 // clear any kill flags that might be present.
11676 if (argOpers[i]->isReg() && argOpers[i]->isUse())
11677 argOpers[i]->setIsKill(false);
11680 // x86 address has 5 operands: base, index, scale, displacement, and segment.
11681 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11683 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
11684 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1);
11685 for (int i=0; i <= lastAddrIndx; ++i)
11686 (*MIB).addOperand(*argOpers[i]);
11687 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
11688 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
11689 // add 4 to displacement.
11690 for (int i=0; i <= lastAddrIndx-2; ++i)
11691 (*MIB).addOperand(*argOpers[i]);
11692 MachineOperand newOp3 = *(argOpers[3]);
11693 if (newOp3.isImm())
11694 newOp3.setImm(newOp3.getImm()+4);
11696 newOp3.setOffset(newOp3.getOffset()+4);
11697 (*MIB).addOperand(newOp3);
11698 (*MIB).addOperand(*argOpers[lastAddrIndx]);
11700 // t3/4 are defined later, at the bottom of the loop
11701 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
11702 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
11703 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg())
11704 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
11705 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
11706 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
11708 // The subsequent operations should be using the destination registers of
11709 // the PHI instructions.
11710 t1 = dest1Oper.getReg();
11711 t2 = dest2Oper.getReg();
11713 int valArgIndx = lastAddrIndx + 1;
11714 assert((argOpers[valArgIndx]->isReg() ||
11715 argOpers[valArgIndx]->isImm()) &&
11716 "invalid operand");
11717 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
11718 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
11719 if (argOpers[valArgIndx]->isReg())
11720 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5);
11722 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
11723 if (regOpcL != X86::MOV32rr)
11725 (*MIB).addOperand(*argOpers[valArgIndx]);
11726 assert(argOpers[valArgIndx + 1]->isReg() ==
11727 argOpers[valArgIndx]->isReg());
11728 assert(argOpers[valArgIndx + 1]->isImm() ==
11729 argOpers[valArgIndx]->isImm());
11730 if (argOpers[valArgIndx + 1]->isReg())
11731 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
11733 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
11734 if (regOpcH != X86::MOV32rr)
11736 (*MIB).addOperand(*argOpers[valArgIndx + 1]);
11740 t7 = F->getRegInfo().createVirtualRegister(RC);
11741 t8 = F->getRegInfo().createVirtualRegister(RC);
11742 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t7).addReg(t5);
11743 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t8).addReg(t6);
11749 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
11751 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EDX);
11754 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EBX);
11756 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::ECX);
11759 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
11760 for (int i=0; i <= lastAddrIndx; ++i)
11761 (*MIB).addOperand(*argOpers[i]);
11763 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11764 (*MIB).setMemRefs(bInstr->memoperands_begin(),
11765 bInstr->memoperands_end());
11767 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t3);
11768 MIB.addReg(X86::EAX);
11769 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t4);
11770 MIB.addReg(X86::EDX);
11773 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11775 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
11779 // private utility function
11780 MachineBasicBlock *
11781 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
11782 MachineBasicBlock *MBB,
11783 unsigned cmovOpc) const {
11784 // For the atomic min/max operator, we generate
11787 // ld t1 = [min/max.addr]
11788 // mov t2 = [min/max.val]
11790 // cmov[cond] t2 = t1
11792 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
11794 // fallthrough -->nextMBB
11796 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11797 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11798 MachineFunction::iterator MBBIter = MBB;
11801 /// First build the CFG
11802 MachineFunction *F = MBB->getParent();
11803 MachineBasicBlock *thisMBB = MBB;
11804 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11805 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11806 F->insert(MBBIter, newMBB);
11807 F->insert(MBBIter, nextMBB);
11809 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11810 nextMBB->splice(nextMBB->begin(), thisMBB,
11811 llvm::next(MachineBasicBlock::iterator(mInstr)),
11813 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11815 // Update thisMBB to fall through to newMBB
11816 thisMBB->addSuccessor(newMBB);
11818 // newMBB jumps to newMBB and fall through to nextMBB
11819 newMBB->addSuccessor(nextMBB);
11820 newMBB->addSuccessor(newMBB);
11822 DebugLoc dl = mInstr->getDebugLoc();
11823 // Insert instructions into newMBB based on incoming instruction
11824 assert(mInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
11825 "unexpected number of operands");
11826 MachineOperand& destOper = mInstr->getOperand(0);
11827 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11828 int numArgs = mInstr->getNumOperands() - 1;
11829 for (int i=0; i < numArgs; ++i)
11830 argOpers[i] = &mInstr->getOperand(i+1);
11832 // x86 address has 4 operands: base, index, scale, and displacement
11833 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11834 int valArgIndx = lastAddrIndx + 1;
11836 unsigned t1 = F->getRegInfo().createVirtualRegister(&X86::GR32RegClass);
11837 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1);
11838 for (int i=0; i <= lastAddrIndx; ++i)
11839 (*MIB).addOperand(*argOpers[i]);
11841 // We only support register and immediate values
11842 assert((argOpers[valArgIndx]->isReg() ||
11843 argOpers[valArgIndx]->isImm()) &&
11844 "invalid operand");
11846 unsigned t2 = F->getRegInfo().createVirtualRegister(&X86::GR32RegClass);
11847 if (argOpers[valArgIndx]->isReg())
11848 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t2);
11850 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
11851 (*MIB).addOperand(*argOpers[valArgIndx]);
11853 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
11856 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr));
11861 unsigned t3 = F->getRegInfo().createVirtualRegister(&X86::GR32RegClass);
11862 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3);
11866 // Cmp and exchange if none has modified the memory location
11867 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32));
11868 for (int i=0; i <= lastAddrIndx; ++i)
11869 (*MIB).addOperand(*argOpers[i]);
11871 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11872 (*MIB).setMemRefs(mInstr->memoperands_begin(),
11873 mInstr->memoperands_end());
11875 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
11876 MIB.addReg(X86::EAX);
11879 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11881 mInstr->eraseFromParent(); // The pseudo instruction is gone now.
11885 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
11886 // or XMM0_V32I8 in AVX all of this code can be replaced with that
11887 // in the .td file.
11888 MachineBasicBlock *
11889 X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB,
11890 unsigned numArgs, bool memArg) const {
11891 assert(Subtarget->hasSSE42() &&
11892 "Target must have SSE4.2 or AVX features enabled");
11894 DebugLoc dl = MI->getDebugLoc();
11895 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11897 if (!Subtarget->hasAVX()) {
11899 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm;
11901 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr;
11904 Opc = numArgs == 3 ? X86::VPCMPISTRM128rm : X86::VPCMPESTRM128rm;
11906 Opc = numArgs == 3 ? X86::VPCMPISTRM128rr : X86::VPCMPESTRM128rr;
11909 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
11910 for (unsigned i = 0; i < numArgs; ++i) {
11911 MachineOperand &Op = MI->getOperand(i+1);
11912 if (!(Op.isReg() && Op.isImplicit()))
11913 MIB.addOperand(Op);
11915 BuildMI(*BB, MI, dl,
11916 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
11917 .addReg(X86::XMM0);
11919 MI->eraseFromParent();
11923 MachineBasicBlock *
11924 X86TargetLowering::EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB) const {
11925 DebugLoc dl = MI->getDebugLoc();
11926 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11928 // Address into RAX/EAX, other two args into ECX, EDX.
11929 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
11930 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
11931 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
11932 for (int i = 0; i < X86::AddrNumOperands; ++i)
11933 MIB.addOperand(MI->getOperand(i));
11935 unsigned ValOps = X86::AddrNumOperands;
11936 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
11937 .addReg(MI->getOperand(ValOps).getReg());
11938 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
11939 .addReg(MI->getOperand(ValOps+1).getReg());
11941 // The instruction doesn't actually take any operands though.
11942 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
11944 MI->eraseFromParent(); // The pseudo is gone now.
11948 MachineBasicBlock *
11949 X86TargetLowering::EmitVAARG64WithCustomInserter(
11951 MachineBasicBlock *MBB) const {
11952 // Emit va_arg instruction on X86-64.
11954 // Operands to this pseudo-instruction:
11955 // 0 ) Output : destination address (reg)
11956 // 1-5) Input : va_list address (addr, i64mem)
11957 // 6 ) ArgSize : Size (in bytes) of vararg type
11958 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
11959 // 8 ) Align : Alignment of type
11960 // 9 ) EFLAGS (implicit-def)
11962 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
11963 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
11965 unsigned DestReg = MI->getOperand(0).getReg();
11966 MachineOperand &Base = MI->getOperand(1);
11967 MachineOperand &Scale = MI->getOperand(2);
11968 MachineOperand &Index = MI->getOperand(3);
11969 MachineOperand &Disp = MI->getOperand(4);
11970 MachineOperand &Segment = MI->getOperand(5);
11971 unsigned ArgSize = MI->getOperand(6).getImm();
11972 unsigned ArgMode = MI->getOperand(7).getImm();
11973 unsigned Align = MI->getOperand(8).getImm();
11975 // Memory Reference
11976 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
11977 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
11978 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
11980 // Machine Information
11981 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11982 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
11983 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
11984 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
11985 DebugLoc DL = MI->getDebugLoc();
11987 // struct va_list {
11990 // i64 overflow_area (address)
11991 // i64 reg_save_area (address)
11993 // sizeof(va_list) = 24
11994 // alignment(va_list) = 8
11996 unsigned TotalNumIntRegs = 6;
11997 unsigned TotalNumXMMRegs = 8;
11998 bool UseGPOffset = (ArgMode == 1);
11999 bool UseFPOffset = (ArgMode == 2);
12000 unsigned MaxOffset = TotalNumIntRegs * 8 +
12001 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
12003 /* Align ArgSize to a multiple of 8 */
12004 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
12005 bool NeedsAlign = (Align > 8);
12007 MachineBasicBlock *thisMBB = MBB;
12008 MachineBasicBlock *overflowMBB;
12009 MachineBasicBlock *offsetMBB;
12010 MachineBasicBlock *endMBB;
12012 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
12013 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
12014 unsigned OffsetReg = 0;
12016 if (!UseGPOffset && !UseFPOffset) {
12017 // If we only pull from the overflow region, we don't create a branch.
12018 // We don't need to alter control flow.
12019 OffsetDestReg = 0; // unused
12020 OverflowDestReg = DestReg;
12023 overflowMBB = thisMBB;
12026 // First emit code to check if gp_offset (or fp_offset) is below the bound.
12027 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
12028 // If not, pull from overflow_area. (branch to overflowMBB)
12033 // offsetMBB overflowMBB
12038 // Registers for the PHI in endMBB
12039 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
12040 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
12042 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
12043 MachineFunction *MF = MBB->getParent();
12044 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12045 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12046 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12048 MachineFunction::iterator MBBIter = MBB;
12051 // Insert the new basic blocks
12052 MF->insert(MBBIter, offsetMBB);
12053 MF->insert(MBBIter, overflowMBB);
12054 MF->insert(MBBIter, endMBB);
12056 // Transfer the remainder of MBB and its successor edges to endMBB.
12057 endMBB->splice(endMBB->begin(), thisMBB,
12058 llvm::next(MachineBasicBlock::iterator(MI)),
12060 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
12062 // Make offsetMBB and overflowMBB successors of thisMBB
12063 thisMBB->addSuccessor(offsetMBB);
12064 thisMBB->addSuccessor(overflowMBB);
12066 // endMBB is a successor of both offsetMBB and overflowMBB
12067 offsetMBB->addSuccessor(endMBB);
12068 overflowMBB->addSuccessor(endMBB);
12070 // Load the offset value into a register
12071 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
12072 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
12076 .addDisp(Disp, UseFPOffset ? 4 : 0)
12077 .addOperand(Segment)
12078 .setMemRefs(MMOBegin, MMOEnd);
12080 // Check if there is enough room left to pull this argument.
12081 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
12083 .addImm(MaxOffset + 8 - ArgSizeA8);
12085 // Branch to "overflowMBB" if offset >= max
12086 // Fall through to "offsetMBB" otherwise
12087 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
12088 .addMBB(overflowMBB);
12091 // In offsetMBB, emit code to use the reg_save_area.
12093 assert(OffsetReg != 0);
12095 // Read the reg_save_area address.
12096 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
12097 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
12102 .addOperand(Segment)
12103 .setMemRefs(MMOBegin, MMOEnd);
12105 // Zero-extend the offset
12106 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
12107 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
12110 .addImm(X86::sub_32bit);
12112 // Add the offset to the reg_save_area to get the final address.
12113 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
12114 .addReg(OffsetReg64)
12115 .addReg(RegSaveReg);
12117 // Compute the offset for the next argument
12118 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
12119 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
12121 .addImm(UseFPOffset ? 16 : 8);
12123 // Store it back into the va_list.
12124 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
12128 .addDisp(Disp, UseFPOffset ? 4 : 0)
12129 .addOperand(Segment)
12130 .addReg(NextOffsetReg)
12131 .setMemRefs(MMOBegin, MMOEnd);
12134 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
12139 // Emit code to use overflow area
12142 // Load the overflow_area address into a register.
12143 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
12144 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
12149 .addOperand(Segment)
12150 .setMemRefs(MMOBegin, MMOEnd);
12152 // If we need to align it, do so. Otherwise, just copy the address
12153 // to OverflowDestReg.
12155 // Align the overflow address
12156 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
12157 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
12159 // aligned_addr = (addr + (align-1)) & ~(align-1)
12160 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
12161 .addReg(OverflowAddrReg)
12164 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
12166 .addImm(~(uint64_t)(Align-1));
12168 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
12169 .addReg(OverflowAddrReg);
12172 // Compute the next overflow address after this argument.
12173 // (the overflow address should be kept 8-byte aligned)
12174 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
12175 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
12176 .addReg(OverflowDestReg)
12177 .addImm(ArgSizeA8);
12179 // Store the new overflow address.
12180 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
12185 .addOperand(Segment)
12186 .addReg(NextAddrReg)
12187 .setMemRefs(MMOBegin, MMOEnd);
12189 // If we branched, emit the PHI to the front of endMBB.
12191 BuildMI(*endMBB, endMBB->begin(), DL,
12192 TII->get(X86::PHI), DestReg)
12193 .addReg(OffsetDestReg).addMBB(offsetMBB)
12194 .addReg(OverflowDestReg).addMBB(overflowMBB);
12197 // Erase the pseudo instruction
12198 MI->eraseFromParent();
12203 MachineBasicBlock *
12204 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
12206 MachineBasicBlock *MBB) const {
12207 // Emit code to save XMM registers to the stack. The ABI says that the
12208 // number of registers to save is given in %al, so it's theoretically
12209 // possible to do an indirect jump trick to avoid saving all of them,
12210 // however this code takes a simpler approach and just executes all
12211 // of the stores if %al is non-zero. It's less code, and it's probably
12212 // easier on the hardware branch predictor, and stores aren't all that
12213 // expensive anyway.
12215 // Create the new basic blocks. One block contains all the XMM stores,
12216 // and one block is the final destination regardless of whether any
12217 // stores were performed.
12218 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
12219 MachineFunction *F = MBB->getParent();
12220 MachineFunction::iterator MBBIter = MBB;
12222 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
12223 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
12224 F->insert(MBBIter, XMMSaveMBB);
12225 F->insert(MBBIter, EndMBB);
12227 // Transfer the remainder of MBB and its successor edges to EndMBB.
12228 EndMBB->splice(EndMBB->begin(), MBB,
12229 llvm::next(MachineBasicBlock::iterator(MI)),
12231 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
12233 // The original block will now fall through to the XMM save block.
12234 MBB->addSuccessor(XMMSaveMBB);
12235 // The XMMSaveMBB will fall through to the end block.
12236 XMMSaveMBB->addSuccessor(EndMBB);
12238 // Now add the instructions.
12239 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12240 DebugLoc DL = MI->getDebugLoc();
12242 unsigned CountReg = MI->getOperand(0).getReg();
12243 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
12244 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
12246 if (!Subtarget->isTargetWin64()) {
12247 // If %al is 0, branch around the XMM save block.
12248 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
12249 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
12250 MBB->addSuccessor(EndMBB);
12253 unsigned MOVOpc = Subtarget->hasAVX() ? X86::VMOVAPSmr : X86::MOVAPSmr;
12254 // In the XMM save block, save all the XMM argument registers.
12255 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
12256 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
12257 MachineMemOperand *MMO =
12258 F->getMachineMemOperand(
12259 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
12260 MachineMemOperand::MOStore,
12261 /*Size=*/16, /*Align=*/16);
12262 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
12263 .addFrameIndex(RegSaveFrameIndex)
12264 .addImm(/*Scale=*/1)
12265 .addReg(/*IndexReg=*/0)
12266 .addImm(/*Disp=*/Offset)
12267 .addReg(/*Segment=*/0)
12268 .addReg(MI->getOperand(i).getReg())
12269 .addMemOperand(MMO);
12272 MI->eraseFromParent(); // The pseudo instruction is gone now.
12277 // The EFLAGS operand of SelectItr might be missing a kill marker
12278 // because there were multiple uses of EFLAGS, and ISel didn't know
12279 // which to mark. Figure out whether SelectItr should have had a
12280 // kill marker, and set it if it should. Returns the correct kill
12282 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
12283 MachineBasicBlock* BB,
12284 const TargetRegisterInfo* TRI) {
12285 // Scan forward through BB for a use/def of EFLAGS.
12286 MachineBasicBlock::iterator miI(llvm::next(SelectItr));
12287 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
12288 const MachineInstr& mi = *miI;
12289 if (mi.readsRegister(X86::EFLAGS))
12291 if (mi.definesRegister(X86::EFLAGS))
12292 break; // Should have kill-flag - update below.
12295 // If we hit the end of the block, check whether EFLAGS is live into a
12297 if (miI == BB->end()) {
12298 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
12299 sEnd = BB->succ_end();
12300 sItr != sEnd; ++sItr) {
12301 MachineBasicBlock* succ = *sItr;
12302 if (succ->isLiveIn(X86::EFLAGS))
12307 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
12308 // out. SelectMI should have a kill flag on EFLAGS.
12309 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
12313 MachineBasicBlock *
12314 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
12315 MachineBasicBlock *BB) const {
12316 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12317 DebugLoc DL = MI->getDebugLoc();
12319 // To "insert" a SELECT_CC instruction, we actually have to insert the
12320 // diamond control-flow pattern. The incoming instruction knows the
12321 // destination vreg to set, the condition code register to branch on, the
12322 // true/false values to select between, and a branch opcode to use.
12323 const BasicBlock *LLVM_BB = BB->getBasicBlock();
12324 MachineFunction::iterator It = BB;
12330 // cmpTY ccX, r1, r2
12332 // fallthrough --> copy0MBB
12333 MachineBasicBlock *thisMBB = BB;
12334 MachineFunction *F = BB->getParent();
12335 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
12336 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
12337 F->insert(It, copy0MBB);
12338 F->insert(It, sinkMBB);
12340 // If the EFLAGS register isn't dead in the terminator, then claim that it's
12341 // live into the sink and copy blocks.
12342 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
12343 if (!MI->killsRegister(X86::EFLAGS) &&
12344 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
12345 copy0MBB->addLiveIn(X86::EFLAGS);
12346 sinkMBB->addLiveIn(X86::EFLAGS);
12349 // Transfer the remainder of BB and its successor edges to sinkMBB.
12350 sinkMBB->splice(sinkMBB->begin(), BB,
12351 llvm::next(MachineBasicBlock::iterator(MI)),
12353 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
12355 // Add the true and fallthrough blocks as its successors.
12356 BB->addSuccessor(copy0MBB);
12357 BB->addSuccessor(sinkMBB);
12359 // Create the conditional branch instruction.
12361 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
12362 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
12365 // %FalseValue = ...
12366 // # fallthrough to sinkMBB
12367 copy0MBB->addSuccessor(sinkMBB);
12370 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
12372 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
12373 TII->get(X86::PHI), MI->getOperand(0).getReg())
12374 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
12375 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
12377 MI->eraseFromParent(); // The pseudo instruction is gone now.
12381 MachineBasicBlock *
12382 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
12383 bool Is64Bit) const {
12384 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12385 DebugLoc DL = MI->getDebugLoc();
12386 MachineFunction *MF = BB->getParent();
12387 const BasicBlock *LLVM_BB = BB->getBasicBlock();
12389 assert(getTargetMachine().Options.EnableSegmentedStacks);
12391 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
12392 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30;
12395 // ... [Till the alloca]
12396 // If stacklet is not large enough, jump to mallocMBB
12399 // Allocate by subtracting from RSP
12400 // Jump to continueMBB
12403 // Allocate by call to runtime
12407 // [rest of original BB]
12410 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12411 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12412 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12414 MachineRegisterInfo &MRI = MF->getRegInfo();
12415 const TargetRegisterClass *AddrRegClass =
12416 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32);
12418 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
12419 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
12420 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
12421 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
12422 sizeVReg = MI->getOperand(1).getReg(),
12423 physSPReg = Is64Bit ? X86::RSP : X86::ESP;
12425 MachineFunction::iterator MBBIter = BB;
12428 MF->insert(MBBIter, bumpMBB);
12429 MF->insert(MBBIter, mallocMBB);
12430 MF->insert(MBBIter, continueMBB);
12432 continueMBB->splice(continueMBB->begin(), BB, llvm::next
12433 (MachineBasicBlock::iterator(MI)), BB->end());
12434 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
12436 // Add code to the main basic block to check if the stack limit has been hit,
12437 // and if so, jump to mallocMBB otherwise to bumpMBB.
12438 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
12439 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
12440 .addReg(tmpSPVReg).addReg(sizeVReg);
12441 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr))
12442 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
12443 .addReg(SPLimitVReg);
12444 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
12446 // bumpMBB simply decreases the stack pointer, since we know the current
12447 // stacklet has enough space.
12448 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
12449 .addReg(SPLimitVReg);
12450 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
12451 .addReg(SPLimitVReg);
12452 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
12454 // Calls into a routine in libgcc to allocate more space from the heap.
12455 const uint32_t *RegMask =
12456 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
12458 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
12460 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
12461 .addExternalSymbol("__morestack_allocate_stack_space")
12462 .addRegMask(RegMask)
12463 .addReg(X86::RDI, RegState::Implicit)
12464 .addReg(X86::RAX, RegState::ImplicitDefine);
12466 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
12468 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
12469 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
12470 .addExternalSymbol("__morestack_allocate_stack_space")
12471 .addRegMask(RegMask)
12472 .addReg(X86::EAX, RegState::ImplicitDefine);
12476 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
12479 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
12480 .addReg(Is64Bit ? X86::RAX : X86::EAX);
12481 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
12483 // Set up the CFG correctly.
12484 BB->addSuccessor(bumpMBB);
12485 BB->addSuccessor(mallocMBB);
12486 mallocMBB->addSuccessor(continueMBB);
12487 bumpMBB->addSuccessor(continueMBB);
12489 // Take care of the PHI nodes.
12490 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
12491 MI->getOperand(0).getReg())
12492 .addReg(mallocPtrVReg).addMBB(mallocMBB)
12493 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
12495 // Delete the original pseudo instruction.
12496 MI->eraseFromParent();
12499 return continueMBB;
12502 MachineBasicBlock *
12503 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
12504 MachineBasicBlock *BB) const {
12505 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12506 DebugLoc DL = MI->getDebugLoc();
12508 assert(!Subtarget->isTargetEnvMacho());
12510 // The lowering is pretty easy: we're just emitting the call to _alloca. The
12511 // non-trivial part is impdef of ESP.
12513 if (Subtarget->isTargetWin64()) {
12514 if (Subtarget->isTargetCygMing()) {
12515 // ___chkstk(Mingw64):
12516 // Clobbers R10, R11, RAX and EFLAGS.
12518 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
12519 .addExternalSymbol("___chkstk")
12520 .addReg(X86::RAX, RegState::Implicit)
12521 .addReg(X86::RSP, RegState::Implicit)
12522 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
12523 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
12524 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12526 // __chkstk(MSVCRT): does not update stack pointer.
12527 // Clobbers R10, R11 and EFLAGS.
12528 // FIXME: RAX(allocated size) might be reused and not killed.
12529 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
12530 .addExternalSymbol("__chkstk")
12531 .addReg(X86::RAX, RegState::Implicit)
12532 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12533 // RAX has the offset to subtracted from RSP.
12534 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
12539 const char *StackProbeSymbol =
12540 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca";
12542 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
12543 .addExternalSymbol(StackProbeSymbol)
12544 .addReg(X86::EAX, RegState::Implicit)
12545 .addReg(X86::ESP, RegState::Implicit)
12546 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
12547 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
12548 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12551 MI->eraseFromParent(); // The pseudo instruction is gone now.
12555 MachineBasicBlock *
12556 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
12557 MachineBasicBlock *BB) const {
12558 // This is pretty easy. We're taking the value that we received from
12559 // our load from the relocation, sticking it in either RDI (x86-64)
12560 // or EAX and doing an indirect call. The return value will then
12561 // be in the normal return register.
12562 const X86InstrInfo *TII
12563 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
12564 DebugLoc DL = MI->getDebugLoc();
12565 MachineFunction *F = BB->getParent();
12567 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
12568 assert(MI->getOperand(3).isGlobal() && "This should be a global");
12570 // Get a register mask for the lowered call.
12571 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
12572 // proper register mask.
12573 const uint32_t *RegMask =
12574 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
12575 if (Subtarget->is64Bit()) {
12576 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12577 TII->get(X86::MOV64rm), X86::RDI)
12579 .addImm(0).addReg(0)
12580 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12581 MI->getOperand(3).getTargetFlags())
12583 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
12584 addDirectMem(MIB, X86::RDI);
12585 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
12586 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
12587 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12588 TII->get(X86::MOV32rm), X86::EAX)
12590 .addImm(0).addReg(0)
12591 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12592 MI->getOperand(3).getTargetFlags())
12594 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
12595 addDirectMem(MIB, X86::EAX);
12596 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
12598 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12599 TII->get(X86::MOV32rm), X86::EAX)
12600 .addReg(TII->getGlobalBaseReg(F))
12601 .addImm(0).addReg(0)
12602 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12603 MI->getOperand(3).getTargetFlags())
12605 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
12606 addDirectMem(MIB, X86::EAX);
12607 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
12610 MI->eraseFromParent(); // The pseudo instruction is gone now.
12614 MachineBasicBlock *
12615 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
12616 MachineBasicBlock *BB) const {
12617 switch (MI->getOpcode()) {
12618 default: llvm_unreachable("Unexpected instr type to insert");
12619 case X86::TAILJMPd64:
12620 case X86::TAILJMPr64:
12621 case X86::TAILJMPm64:
12622 llvm_unreachable("TAILJMP64 would not be touched here.");
12623 case X86::TCRETURNdi64:
12624 case X86::TCRETURNri64:
12625 case X86::TCRETURNmi64:
12627 case X86::WIN_ALLOCA:
12628 return EmitLoweredWinAlloca(MI, BB);
12629 case X86::SEG_ALLOCA_32:
12630 return EmitLoweredSegAlloca(MI, BB, false);
12631 case X86::SEG_ALLOCA_64:
12632 return EmitLoweredSegAlloca(MI, BB, true);
12633 case X86::TLSCall_32:
12634 case X86::TLSCall_64:
12635 return EmitLoweredTLSCall(MI, BB);
12636 case X86::CMOV_GR8:
12637 case X86::CMOV_FR32:
12638 case X86::CMOV_FR64:
12639 case X86::CMOV_V4F32:
12640 case X86::CMOV_V2F64:
12641 case X86::CMOV_V2I64:
12642 case X86::CMOV_V8F32:
12643 case X86::CMOV_V4F64:
12644 case X86::CMOV_V4I64:
12645 case X86::CMOV_GR16:
12646 case X86::CMOV_GR32:
12647 case X86::CMOV_RFP32:
12648 case X86::CMOV_RFP64:
12649 case X86::CMOV_RFP80:
12650 return EmitLoweredSelect(MI, BB);
12652 case X86::FP32_TO_INT16_IN_MEM:
12653 case X86::FP32_TO_INT32_IN_MEM:
12654 case X86::FP32_TO_INT64_IN_MEM:
12655 case X86::FP64_TO_INT16_IN_MEM:
12656 case X86::FP64_TO_INT32_IN_MEM:
12657 case X86::FP64_TO_INT64_IN_MEM:
12658 case X86::FP80_TO_INT16_IN_MEM:
12659 case X86::FP80_TO_INT32_IN_MEM:
12660 case X86::FP80_TO_INT64_IN_MEM: {
12661 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12662 DebugLoc DL = MI->getDebugLoc();
12664 // Change the floating point control register to use "round towards zero"
12665 // mode when truncating to an integer value.
12666 MachineFunction *F = BB->getParent();
12667 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
12668 addFrameReference(BuildMI(*BB, MI, DL,
12669 TII->get(X86::FNSTCW16m)), CWFrameIdx);
12671 // Load the old value of the high byte of the control word...
12673 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
12674 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
12677 // Set the high part to be round to zero...
12678 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
12681 // Reload the modified control word now...
12682 addFrameReference(BuildMI(*BB, MI, DL,
12683 TII->get(X86::FLDCW16m)), CWFrameIdx);
12685 // Restore the memory image of control word to original value
12686 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
12689 // Get the X86 opcode to use.
12691 switch (MI->getOpcode()) {
12692 default: llvm_unreachable("illegal opcode!");
12693 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
12694 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
12695 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
12696 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
12697 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
12698 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
12699 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
12700 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
12701 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
12705 MachineOperand &Op = MI->getOperand(0);
12707 AM.BaseType = X86AddressMode::RegBase;
12708 AM.Base.Reg = Op.getReg();
12710 AM.BaseType = X86AddressMode::FrameIndexBase;
12711 AM.Base.FrameIndex = Op.getIndex();
12713 Op = MI->getOperand(1);
12715 AM.Scale = Op.getImm();
12716 Op = MI->getOperand(2);
12718 AM.IndexReg = Op.getImm();
12719 Op = MI->getOperand(3);
12720 if (Op.isGlobal()) {
12721 AM.GV = Op.getGlobal();
12723 AM.Disp = Op.getImm();
12725 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
12726 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
12728 // Reload the original control word now.
12729 addFrameReference(BuildMI(*BB, MI, DL,
12730 TII->get(X86::FLDCW16m)), CWFrameIdx);
12732 MI->eraseFromParent(); // The pseudo instruction is gone now.
12735 // String/text processing lowering.
12736 case X86::PCMPISTRM128REG:
12737 case X86::VPCMPISTRM128REG:
12738 return EmitPCMP(MI, BB, 3, false /* in-mem */);
12739 case X86::PCMPISTRM128MEM:
12740 case X86::VPCMPISTRM128MEM:
12741 return EmitPCMP(MI, BB, 3, true /* in-mem */);
12742 case X86::PCMPESTRM128REG:
12743 case X86::VPCMPESTRM128REG:
12744 return EmitPCMP(MI, BB, 5, false /* in mem */);
12745 case X86::PCMPESTRM128MEM:
12746 case X86::VPCMPESTRM128MEM:
12747 return EmitPCMP(MI, BB, 5, true /* in mem */);
12749 // Thread synchronization.
12751 return EmitMonitor(MI, BB);
12753 // Atomic Lowering.
12754 case X86::ATOMAND32:
12755 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
12756 X86::AND32ri, X86::MOV32rm,
12758 X86::NOT32r, X86::EAX,
12759 &X86::GR32RegClass);
12760 case X86::ATOMOR32:
12761 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
12762 X86::OR32ri, X86::MOV32rm,
12764 X86::NOT32r, X86::EAX,
12765 &X86::GR32RegClass);
12766 case X86::ATOMXOR32:
12767 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
12768 X86::XOR32ri, X86::MOV32rm,
12770 X86::NOT32r, X86::EAX,
12771 &X86::GR32RegClass);
12772 case X86::ATOMNAND32:
12773 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
12774 X86::AND32ri, X86::MOV32rm,
12776 X86::NOT32r, X86::EAX,
12777 &X86::GR32RegClass, true);
12778 case X86::ATOMMIN32:
12779 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
12780 case X86::ATOMMAX32:
12781 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
12782 case X86::ATOMUMIN32:
12783 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
12784 case X86::ATOMUMAX32:
12785 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
12787 case X86::ATOMAND16:
12788 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
12789 X86::AND16ri, X86::MOV16rm,
12791 X86::NOT16r, X86::AX,
12792 &X86::GR16RegClass);
12793 case X86::ATOMOR16:
12794 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
12795 X86::OR16ri, X86::MOV16rm,
12797 X86::NOT16r, X86::AX,
12798 &X86::GR16RegClass);
12799 case X86::ATOMXOR16:
12800 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
12801 X86::XOR16ri, X86::MOV16rm,
12803 X86::NOT16r, X86::AX,
12804 &X86::GR16RegClass);
12805 case X86::ATOMNAND16:
12806 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
12807 X86::AND16ri, X86::MOV16rm,
12809 X86::NOT16r, X86::AX,
12810 &X86::GR16RegClass, true);
12811 case X86::ATOMMIN16:
12812 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
12813 case X86::ATOMMAX16:
12814 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
12815 case X86::ATOMUMIN16:
12816 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
12817 case X86::ATOMUMAX16:
12818 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
12820 case X86::ATOMAND8:
12821 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
12822 X86::AND8ri, X86::MOV8rm,
12824 X86::NOT8r, X86::AL,
12825 &X86::GR8RegClass);
12827 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
12828 X86::OR8ri, X86::MOV8rm,
12830 X86::NOT8r, X86::AL,
12831 &X86::GR8RegClass);
12832 case X86::ATOMXOR8:
12833 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
12834 X86::XOR8ri, X86::MOV8rm,
12836 X86::NOT8r, X86::AL,
12837 &X86::GR8RegClass);
12838 case X86::ATOMNAND8:
12839 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
12840 X86::AND8ri, X86::MOV8rm,
12842 X86::NOT8r, X86::AL,
12843 &X86::GR8RegClass, true);
12844 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
12845 // This group is for 64-bit host.
12846 case X86::ATOMAND64:
12847 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
12848 X86::AND64ri32, X86::MOV64rm,
12850 X86::NOT64r, X86::RAX,
12851 &X86::GR64RegClass);
12852 case X86::ATOMOR64:
12853 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
12854 X86::OR64ri32, X86::MOV64rm,
12856 X86::NOT64r, X86::RAX,
12857 &X86::GR64RegClass);
12858 case X86::ATOMXOR64:
12859 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
12860 X86::XOR64ri32, X86::MOV64rm,
12862 X86::NOT64r, X86::RAX,
12863 &X86::GR64RegClass);
12864 case X86::ATOMNAND64:
12865 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
12866 X86::AND64ri32, X86::MOV64rm,
12868 X86::NOT64r, X86::RAX,
12869 &X86::GR64RegClass, true);
12870 case X86::ATOMMIN64:
12871 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
12872 case X86::ATOMMAX64:
12873 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
12874 case X86::ATOMUMIN64:
12875 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
12876 case X86::ATOMUMAX64:
12877 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
12879 // This group does 64-bit operations on a 32-bit host.
12880 case X86::ATOMAND6432:
12881 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12882 X86::AND32rr, X86::AND32rr,
12883 X86::AND32ri, X86::AND32ri,
12885 case X86::ATOMOR6432:
12886 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12887 X86::OR32rr, X86::OR32rr,
12888 X86::OR32ri, X86::OR32ri,
12890 case X86::ATOMXOR6432:
12891 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12892 X86::XOR32rr, X86::XOR32rr,
12893 X86::XOR32ri, X86::XOR32ri,
12895 case X86::ATOMNAND6432:
12896 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12897 X86::AND32rr, X86::AND32rr,
12898 X86::AND32ri, X86::AND32ri,
12900 case X86::ATOMADD6432:
12901 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12902 X86::ADD32rr, X86::ADC32rr,
12903 X86::ADD32ri, X86::ADC32ri,
12905 case X86::ATOMSUB6432:
12906 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12907 X86::SUB32rr, X86::SBB32rr,
12908 X86::SUB32ri, X86::SBB32ri,
12910 case X86::ATOMSWAP6432:
12911 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12912 X86::MOV32rr, X86::MOV32rr,
12913 X86::MOV32ri, X86::MOV32ri,
12915 case X86::VASTART_SAVE_XMM_REGS:
12916 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
12918 case X86::VAARG_64:
12919 return EmitVAARG64WithCustomInserter(MI, BB);
12923 //===----------------------------------------------------------------------===//
12924 // X86 Optimization Hooks
12925 //===----------------------------------------------------------------------===//
12927 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
12930 const SelectionDAG &DAG,
12931 unsigned Depth) const {
12932 unsigned BitWidth = KnownZero.getBitWidth();
12933 unsigned Opc = Op.getOpcode();
12934 assert((Opc >= ISD::BUILTIN_OP_END ||
12935 Opc == ISD::INTRINSIC_WO_CHAIN ||
12936 Opc == ISD::INTRINSIC_W_CHAIN ||
12937 Opc == ISD::INTRINSIC_VOID) &&
12938 "Should use MaskedValueIsZero if you don't know whether Op"
12939 " is a target node!");
12941 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
12955 // These nodes' second result is a boolean.
12956 if (Op.getResNo() == 0)
12959 case X86ISD::SETCC:
12960 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
12962 case ISD::INTRINSIC_WO_CHAIN: {
12963 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
12964 unsigned NumLoBits = 0;
12967 case Intrinsic::x86_sse_movmsk_ps:
12968 case Intrinsic::x86_avx_movmsk_ps_256:
12969 case Intrinsic::x86_sse2_movmsk_pd:
12970 case Intrinsic::x86_avx_movmsk_pd_256:
12971 case Intrinsic::x86_mmx_pmovmskb:
12972 case Intrinsic::x86_sse2_pmovmskb_128:
12973 case Intrinsic::x86_avx2_pmovmskb: {
12974 // High bits of movmskp{s|d}, pmovmskb are known zero.
12976 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
12977 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
12978 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
12979 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
12980 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
12981 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
12982 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
12983 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
12985 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
12994 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
12995 unsigned Depth) const {
12996 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
12997 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
12998 return Op.getValueType().getScalarType().getSizeInBits();
13004 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
13005 /// node is a GlobalAddress + offset.
13006 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
13007 const GlobalValue* &GA,
13008 int64_t &Offset) const {
13009 if (N->getOpcode() == X86ISD::Wrapper) {
13010 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
13011 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
13012 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
13016 return TargetLowering::isGAPlusOffset(N, GA, Offset);
13019 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
13020 /// same as extracting the high 128-bit part of 256-bit vector and then
13021 /// inserting the result into the low part of a new 256-bit vector
13022 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
13023 EVT VT = SVOp->getValueType(0);
13024 unsigned NumElems = VT.getVectorNumElements();
13026 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
13027 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
13028 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
13029 SVOp->getMaskElt(j) >= 0)
13035 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
13036 /// same as extracting the low 128-bit part of 256-bit vector and then
13037 /// inserting the result into the high part of a new 256-bit vector
13038 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
13039 EVT VT = SVOp->getValueType(0);
13040 unsigned NumElems = VT.getVectorNumElements();
13042 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
13043 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
13044 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
13045 SVOp->getMaskElt(j) >= 0)
13051 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
13052 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
13053 TargetLowering::DAGCombinerInfo &DCI,
13054 const X86Subtarget* Subtarget) {
13055 DebugLoc dl = N->getDebugLoc();
13056 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
13057 SDValue V1 = SVOp->getOperand(0);
13058 SDValue V2 = SVOp->getOperand(1);
13059 EVT VT = SVOp->getValueType(0);
13060 unsigned NumElems = VT.getVectorNumElements();
13062 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
13063 V2.getOpcode() == ISD::CONCAT_VECTORS) {
13067 // V UNDEF BUILD_VECTOR UNDEF
13069 // CONCAT_VECTOR CONCAT_VECTOR
13072 // RESULT: V + zero extended
13074 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
13075 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
13076 V1.getOperand(1).getOpcode() != ISD::UNDEF)
13079 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
13082 // To match the shuffle mask, the first half of the mask should
13083 // be exactly the first vector, and all the rest a splat with the
13084 // first element of the second one.
13085 for (unsigned i = 0; i != NumElems/2; ++i)
13086 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
13087 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
13090 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
13091 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
13092 if (Ld->hasNUsesOfValue(1, 0)) {
13093 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
13094 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
13096 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2,
13098 Ld->getPointerInfo(),
13099 Ld->getAlignment(),
13100 false/*isVolatile*/, true/*ReadMem*/,
13101 false/*WriteMem*/);
13102 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
13106 // Emit a zeroed vector and insert the desired subvector on its
13108 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
13109 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
13110 return DCI.CombineTo(N, InsV);
13113 //===--------------------------------------------------------------------===//
13114 // Combine some shuffles into subvector extracts and inserts:
13117 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
13118 if (isShuffleHigh128VectorInsertLow(SVOp)) {
13119 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
13120 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
13121 return DCI.CombineTo(N, InsV);
13124 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
13125 if (isShuffleLow128VectorInsertHigh(SVOp)) {
13126 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
13127 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
13128 return DCI.CombineTo(N, InsV);
13134 /// PerformShuffleCombine - Performs several different shuffle combines.
13135 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
13136 TargetLowering::DAGCombinerInfo &DCI,
13137 const X86Subtarget *Subtarget) {
13138 DebugLoc dl = N->getDebugLoc();
13139 EVT VT = N->getValueType(0);
13141 // Don't create instructions with illegal types after legalize types has run.
13142 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13143 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
13146 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
13147 if (Subtarget->hasAVX() && VT.is256BitVector() &&
13148 N->getOpcode() == ISD::VECTOR_SHUFFLE)
13149 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
13151 // Only handle 128 wide vector from here on.
13152 if (!VT.is128BitVector())
13155 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
13156 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
13157 // consecutive, non-overlapping, and in the right order.
13158 SmallVector<SDValue, 16> Elts;
13159 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
13160 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
13162 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG);
13166 /// DCI, PerformTruncateCombine - Converts truncate operation to
13167 /// a sequence of vector shuffle operations.
13168 /// It is possible when we truncate 256-bit vector to 128-bit vector
13170 SDValue X86TargetLowering::PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
13171 DAGCombinerInfo &DCI) const {
13172 if (!DCI.isBeforeLegalizeOps())
13175 if (!Subtarget->hasAVX())
13178 EVT VT = N->getValueType(0);
13179 SDValue Op = N->getOperand(0);
13180 EVT OpVT = Op.getValueType();
13181 DebugLoc dl = N->getDebugLoc();
13183 if ((VT == MVT::v4i32) && (OpVT == MVT::v4i64)) {
13185 if (Subtarget->hasAVX2()) {
13186 // AVX2: v4i64 -> v4i32
13189 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
13191 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v8i32, Op);
13192 Op = DAG.getVectorShuffle(MVT::v8i32, dl, Op, DAG.getUNDEF(MVT::v8i32),
13195 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, Op,
13196 DAG.getIntPtrConstant(0));
13199 // AVX: v4i64 -> v4i32
13200 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op,
13201 DAG.getIntPtrConstant(0));
13203 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op,
13204 DAG.getIntPtrConstant(2));
13206 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpLo);
13207 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpHi);
13210 static const int ShufMask1[] = {0, 2, 0, 0};
13212 OpLo = DAG.getVectorShuffle(VT, dl, OpLo, DAG.getUNDEF(VT), ShufMask1);
13213 OpHi = DAG.getVectorShuffle(VT, dl, OpHi, DAG.getUNDEF(VT), ShufMask1);
13216 static const int ShufMask2[] = {0, 1, 4, 5};
13218 return DAG.getVectorShuffle(VT, dl, OpLo, OpHi, ShufMask2);
13221 if ((VT == MVT::v8i16) && (OpVT == MVT::v8i32)) {
13223 if (Subtarget->hasAVX2()) {
13224 // AVX2: v8i32 -> v8i16
13226 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v32i8, Op);
13229 SmallVector<SDValue,32> pshufbMask;
13230 for (unsigned i = 0; i < 2; ++i) {
13231 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
13232 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
13233 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
13234 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
13235 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
13236 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
13237 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
13238 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
13239 for (unsigned j = 0; j < 8; ++j)
13240 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
13242 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v32i8,
13243 &pshufbMask[0], 32);
13244 Op = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v32i8, Op, BV);
13246 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4i64, Op);
13248 static const int ShufMask[] = {0, 2, -1, -1};
13249 Op = DAG.getVectorShuffle(MVT::v4i64, dl, Op, DAG.getUNDEF(MVT::v4i64),
13252 Op = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op,
13253 DAG.getIntPtrConstant(0));
13255 return DAG.getNode(ISD::BITCAST, dl, VT, Op);
13258 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i32, Op,
13259 DAG.getIntPtrConstant(0));
13261 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i32, Op,
13262 DAG.getIntPtrConstant(4));
13264 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLo);
13265 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpHi);
13268 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
13269 -1, -1, -1, -1, -1, -1, -1, -1};
13271 OpLo = DAG.getVectorShuffle(MVT::v16i8, dl, OpLo, DAG.getUNDEF(MVT::v16i8),
13273 OpHi = DAG.getVectorShuffle(MVT::v16i8, dl, OpHi, DAG.getUNDEF(MVT::v16i8),
13276 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpLo);
13277 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpHi);
13280 static const int ShufMask2[] = {0, 1, 4, 5};
13282 SDValue res = DAG.getVectorShuffle(MVT::v4i32, dl, OpLo, OpHi, ShufMask2);
13283 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, res);
13289 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
13290 /// specific shuffle of a load can be folded into a single element load.
13291 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
13292 /// shuffles have been customed lowered so we need to handle those here.
13293 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
13294 TargetLowering::DAGCombinerInfo &DCI) {
13295 if (DCI.isBeforeLegalizeOps())
13298 SDValue InVec = N->getOperand(0);
13299 SDValue EltNo = N->getOperand(1);
13301 if (!isa<ConstantSDNode>(EltNo))
13304 EVT VT = InVec.getValueType();
13306 bool HasShuffleIntoBitcast = false;
13307 if (InVec.getOpcode() == ISD::BITCAST) {
13308 // Don't duplicate a load with other uses.
13309 if (!InVec.hasOneUse())
13311 EVT BCVT = InVec.getOperand(0).getValueType();
13312 if (BCVT.getVectorNumElements() != VT.getVectorNumElements())
13314 InVec = InVec.getOperand(0);
13315 HasShuffleIntoBitcast = true;
13318 if (!isTargetShuffle(InVec.getOpcode()))
13321 // Don't duplicate a load with other uses.
13322 if (!InVec.hasOneUse())
13325 SmallVector<int, 16> ShuffleMask;
13327 if (!getTargetShuffleMask(InVec.getNode(), VT.getSimpleVT(), ShuffleMask,
13331 // Select the input vector, guarding against out of range extract vector.
13332 unsigned NumElems = VT.getVectorNumElements();
13333 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
13334 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
13335 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
13336 : InVec.getOperand(1);
13338 // If inputs to shuffle are the same for both ops, then allow 2 uses
13339 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
13341 if (LdNode.getOpcode() == ISD::BITCAST) {
13342 // Don't duplicate a load with other uses.
13343 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
13346 AllowedUses = 1; // only allow 1 load use if we have a bitcast
13347 LdNode = LdNode.getOperand(0);
13350 if (!ISD::isNormalLoad(LdNode.getNode()))
13353 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
13355 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
13358 if (HasShuffleIntoBitcast) {
13359 // If there's a bitcast before the shuffle, check if the load type and
13360 // alignment is valid.
13361 unsigned Align = LN0->getAlignment();
13362 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13363 unsigned NewAlign = TLI.getTargetData()->
13364 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
13366 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
13370 // All checks match so transform back to vector_shuffle so that DAG combiner
13371 // can finish the job
13372 DebugLoc dl = N->getDebugLoc();
13374 // Create shuffle node taking into account the case that its a unary shuffle
13375 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1);
13376 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl,
13377 InVec.getOperand(0), Shuffle,
13379 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
13380 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
13384 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
13385 /// generation and convert it from being a bunch of shuffles and extracts
13386 /// to a simple store and scalar loads to extract the elements.
13387 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
13388 TargetLowering::DAGCombinerInfo &DCI) {
13389 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
13390 if (NewOp.getNode())
13393 SDValue InputVector = N->getOperand(0);
13395 // Only operate on vectors of 4 elements, where the alternative shuffling
13396 // gets to be more expensive.
13397 if (InputVector.getValueType() != MVT::v4i32)
13400 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
13401 // single use which is a sign-extend or zero-extend, and all elements are
13403 SmallVector<SDNode *, 4> Uses;
13404 unsigned ExtractedElements = 0;
13405 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
13406 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
13407 if (UI.getUse().getResNo() != InputVector.getResNo())
13410 SDNode *Extract = *UI;
13411 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
13414 if (Extract->getValueType(0) != MVT::i32)
13416 if (!Extract->hasOneUse())
13418 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
13419 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
13421 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
13424 // Record which element was extracted.
13425 ExtractedElements |=
13426 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
13428 Uses.push_back(Extract);
13431 // If not all the elements were used, this may not be worthwhile.
13432 if (ExtractedElements != 15)
13435 // Ok, we've now decided to do the transformation.
13436 DebugLoc dl = InputVector.getDebugLoc();
13438 // Store the value to a temporary stack slot.
13439 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
13440 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
13441 MachinePointerInfo(), false, false, 0);
13443 // Replace each use (extract) with a load of the appropriate element.
13444 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
13445 UE = Uses.end(); UI != UE; ++UI) {
13446 SDNode *Extract = *UI;
13448 // cOMpute the element's address.
13449 SDValue Idx = Extract->getOperand(1);
13451 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
13452 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
13453 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13454 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
13456 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
13457 StackPtr, OffsetVal);
13459 // Load the scalar.
13460 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
13461 ScalarAddr, MachinePointerInfo(),
13462 false, false, false, 0);
13464 // Replace the exact with the load.
13465 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
13468 // The replacement was made in place; don't return anything.
13472 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
13474 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
13475 TargetLowering::DAGCombinerInfo &DCI,
13476 const X86Subtarget *Subtarget) {
13477 DebugLoc DL = N->getDebugLoc();
13478 SDValue Cond = N->getOperand(0);
13479 // Get the LHS/RHS of the select.
13480 SDValue LHS = N->getOperand(1);
13481 SDValue RHS = N->getOperand(2);
13482 EVT VT = LHS.getValueType();
13484 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
13485 // instructions match the semantics of the common C idiom x<y?x:y but not
13486 // x<=y?x:y, because of how they handle negative zero (which can be
13487 // ignored in unsafe-math mode).
13488 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
13489 VT != MVT::f80 && DAG.getTargetLoweringInfo().isTypeLegal(VT) &&
13490 (Subtarget->hasSSE2() ||
13491 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
13492 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
13494 unsigned Opcode = 0;
13495 // Check for x CC y ? x : y.
13496 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
13497 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
13501 // Converting this to a min would handle NaNs incorrectly, and swapping
13502 // the operands would cause it to handle comparisons between positive
13503 // and negative zero incorrectly.
13504 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
13505 if (!DAG.getTarget().Options.UnsafeFPMath &&
13506 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
13508 std::swap(LHS, RHS);
13510 Opcode = X86ISD::FMIN;
13513 // Converting this to a min would handle comparisons between positive
13514 // and negative zero incorrectly.
13515 if (!DAG.getTarget().Options.UnsafeFPMath &&
13516 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
13518 Opcode = X86ISD::FMIN;
13521 // Converting this to a min would handle both negative zeros and NaNs
13522 // incorrectly, but we can swap the operands to fix both.
13523 std::swap(LHS, RHS);
13527 Opcode = X86ISD::FMIN;
13531 // Converting this to a max would handle comparisons between positive
13532 // and negative zero incorrectly.
13533 if (!DAG.getTarget().Options.UnsafeFPMath &&
13534 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
13536 Opcode = X86ISD::FMAX;
13539 // Converting this to a max would handle NaNs incorrectly, and swapping
13540 // the operands would cause it to handle comparisons between positive
13541 // and negative zero incorrectly.
13542 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
13543 if (!DAG.getTarget().Options.UnsafeFPMath &&
13544 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
13546 std::swap(LHS, RHS);
13548 Opcode = X86ISD::FMAX;
13551 // Converting this to a max would handle both negative zeros and NaNs
13552 // incorrectly, but we can swap the operands to fix both.
13553 std::swap(LHS, RHS);
13557 Opcode = X86ISD::FMAX;
13560 // Check for x CC y ? y : x -- a min/max with reversed arms.
13561 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
13562 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
13566 // Converting this to a min would handle comparisons between positive
13567 // and negative zero incorrectly, and swapping the operands would
13568 // cause it to handle NaNs incorrectly.
13569 if (!DAG.getTarget().Options.UnsafeFPMath &&
13570 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
13571 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
13573 std::swap(LHS, RHS);
13575 Opcode = X86ISD::FMIN;
13578 // Converting this to a min would handle NaNs incorrectly.
13579 if (!DAG.getTarget().Options.UnsafeFPMath &&
13580 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
13582 Opcode = X86ISD::FMIN;
13585 // Converting this to a min would handle both negative zeros and NaNs
13586 // incorrectly, but we can swap the operands to fix both.
13587 std::swap(LHS, RHS);
13591 Opcode = X86ISD::FMIN;
13595 // Converting this to a max would handle NaNs incorrectly.
13596 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
13598 Opcode = X86ISD::FMAX;
13601 // Converting this to a max would handle comparisons between positive
13602 // and negative zero incorrectly, and swapping the operands would
13603 // cause it to handle NaNs incorrectly.
13604 if (!DAG.getTarget().Options.UnsafeFPMath &&
13605 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
13606 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
13608 std::swap(LHS, RHS);
13610 Opcode = X86ISD::FMAX;
13613 // Converting this to a max would handle both negative zeros and NaNs
13614 // incorrectly, but we can swap the operands to fix both.
13615 std::swap(LHS, RHS);
13619 Opcode = X86ISD::FMAX;
13625 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
13628 // If this is a select between two integer constants, try to do some
13630 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
13631 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
13632 // Don't do this for crazy integer types.
13633 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
13634 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
13635 // so that TrueC (the true value) is larger than FalseC.
13636 bool NeedsCondInvert = false;
13638 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
13639 // Efficiently invertible.
13640 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
13641 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
13642 isa<ConstantSDNode>(Cond.getOperand(1))))) {
13643 NeedsCondInvert = true;
13644 std::swap(TrueC, FalseC);
13647 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
13648 if (FalseC->getAPIntValue() == 0 &&
13649 TrueC->getAPIntValue().isPowerOf2()) {
13650 if (NeedsCondInvert) // Invert the condition if needed.
13651 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13652 DAG.getConstant(1, Cond.getValueType()));
13654 // Zero extend the condition if needed.
13655 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
13657 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
13658 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
13659 DAG.getConstant(ShAmt, MVT::i8));
13662 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
13663 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
13664 if (NeedsCondInvert) // Invert the condition if needed.
13665 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13666 DAG.getConstant(1, Cond.getValueType()));
13668 // Zero extend the condition if needed.
13669 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
13670 FalseC->getValueType(0), Cond);
13671 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13672 SDValue(FalseC, 0));
13675 // Optimize cases that will turn into an LEA instruction. This requires
13676 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
13677 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
13678 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
13679 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
13681 bool isFastMultiplier = false;
13683 switch ((unsigned char)Diff) {
13685 case 1: // result = add base, cond
13686 case 2: // result = lea base( , cond*2)
13687 case 3: // result = lea base(cond, cond*2)
13688 case 4: // result = lea base( , cond*4)
13689 case 5: // result = lea base(cond, cond*4)
13690 case 8: // result = lea base( , cond*8)
13691 case 9: // result = lea base(cond, cond*8)
13692 isFastMultiplier = true;
13697 if (isFastMultiplier) {
13698 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
13699 if (NeedsCondInvert) // Invert the condition if needed.
13700 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13701 DAG.getConstant(1, Cond.getValueType()));
13703 // Zero extend the condition if needed.
13704 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
13706 // Scale the condition by the difference.
13708 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
13709 DAG.getConstant(Diff, Cond.getValueType()));
13711 // Add the base if non-zero.
13712 if (FalseC->getAPIntValue() != 0)
13713 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13714 SDValue(FalseC, 0));
13721 // Canonicalize max and min:
13722 // (x > y) ? x : y -> (x >= y) ? x : y
13723 // (x < y) ? x : y -> (x <= y) ? x : y
13724 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
13725 // the need for an extra compare
13726 // against zero. e.g.
13727 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
13729 // testl %edi, %edi
13731 // cmovgl %edi, %eax
13735 // cmovsl %eax, %edi
13736 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
13737 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
13738 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
13739 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
13744 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
13745 Cond = DAG.getSetCC(Cond.getDebugLoc(), Cond.getValueType(),
13746 Cond.getOperand(0), Cond.getOperand(1), NewCC);
13747 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
13752 // If we know that this node is legal then we know that it is going to be
13753 // matched by one of the SSE/AVX BLEND instructions. These instructions only
13754 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
13755 // to simplify previous instructions.
13756 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13757 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
13758 !DCI.isBeforeLegalize() && TLI.isOperationLegal(ISD::VSELECT, VT)) {
13759 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
13761 // Don't optimize vector selects that map to mask-registers.
13765 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
13766 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
13768 APInt KnownZero, KnownOne;
13769 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
13770 DCI.isBeforeLegalizeOps());
13771 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
13772 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
13773 DCI.CommitTargetLoweringOpt(TLO);
13779 // Check whether a boolean test is testing a boolean value generated by
13780 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
13783 // Simplify the following patterns:
13784 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
13785 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
13786 // to (Op EFLAGS Cond)
13788 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
13789 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
13790 // to (Op EFLAGS !Cond)
13792 // where Op could be BRCOND or CMOV.
13794 static SDValue BoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
13795 // Quit if not CMP and SUB with its value result used.
13796 if (Cmp.getOpcode() != X86ISD::CMP &&
13797 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
13800 // Quit if not used as a boolean value.
13801 if (CC != X86::COND_E && CC != X86::COND_NE)
13804 // Check CMP operands. One of them should be 0 or 1 and the other should be
13805 // an SetCC or extended from it.
13806 SDValue Op1 = Cmp.getOperand(0);
13807 SDValue Op2 = Cmp.getOperand(1);
13810 const ConstantSDNode* C = 0;
13811 bool needOppositeCond = (CC == X86::COND_E);
13813 if ((C = dyn_cast<ConstantSDNode>(Op1)))
13815 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
13817 else // Quit if all operands are not constants.
13820 if (C->getZExtValue() == 1)
13821 needOppositeCond = !needOppositeCond;
13822 else if (C->getZExtValue() != 0)
13823 // Quit if the constant is neither 0 or 1.
13826 // Skip 'zext' node.
13827 if (SetCC.getOpcode() == ISD::ZERO_EXTEND)
13828 SetCC = SetCC.getOperand(0);
13830 // Quit if not SETCC.
13831 // FIXME: So far we only handle the boolean value generated from SETCC. If
13832 // there is other ways to generate boolean values, we need handle them here
13834 if (SetCC.getOpcode() != X86ISD::SETCC)
13837 // Set the condition code or opposite one if necessary.
13838 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
13839 if (needOppositeCond)
13840 CC = X86::GetOppositeBranchCondition(CC);
13842 return SetCC.getOperand(1);
13845 static bool IsValidFCMOVCondition(X86::CondCode CC) {
13861 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
13862 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
13863 TargetLowering::DAGCombinerInfo &DCI) {
13864 DebugLoc DL = N->getDebugLoc();
13866 // If the flag operand isn't dead, don't touch this CMOV.
13867 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
13870 SDValue FalseOp = N->getOperand(0);
13871 SDValue TrueOp = N->getOperand(1);
13872 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
13873 SDValue Cond = N->getOperand(3);
13875 if (CC == X86::COND_E || CC == X86::COND_NE) {
13876 switch (Cond.getOpcode()) {
13880 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
13881 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
13882 return (CC == X86::COND_E) ? FalseOp : TrueOp;
13888 Flags = BoolTestSetCCCombine(Cond, CC);
13889 if (Flags.getNode() &&
13890 // Extra check as FCMOV only supports a subset of X86 cond.
13891 (FalseOp.getValueType() != MVT::f80 || IsValidFCMOVCondition(CC))) {
13892 SDValue Ops[] = { FalseOp, TrueOp,
13893 DAG.getConstant(CC, MVT::i8), Flags };
13894 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(),
13895 Ops, array_lengthof(Ops));
13898 // If this is a select between two integer constants, try to do some
13899 // optimizations. Note that the operands are ordered the opposite of SELECT
13901 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
13902 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
13903 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
13904 // larger than FalseC (the false value).
13905 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
13906 CC = X86::GetOppositeBranchCondition(CC);
13907 std::swap(TrueC, FalseC);
13910 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
13911 // This is efficient for any integer data type (including i8/i16) and
13913 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
13914 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13915 DAG.getConstant(CC, MVT::i8), Cond);
13917 // Zero extend the condition if needed.
13918 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
13920 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
13921 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
13922 DAG.getConstant(ShAmt, MVT::i8));
13923 if (N->getNumValues() == 2) // Dead flag value?
13924 return DCI.CombineTo(N, Cond, SDValue());
13928 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
13929 // for any integer data type, including i8/i16.
13930 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
13931 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13932 DAG.getConstant(CC, MVT::i8), Cond);
13934 // Zero extend the condition if needed.
13935 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
13936 FalseC->getValueType(0), Cond);
13937 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13938 SDValue(FalseC, 0));
13940 if (N->getNumValues() == 2) // Dead flag value?
13941 return DCI.CombineTo(N, Cond, SDValue());
13945 // Optimize cases that will turn into an LEA instruction. This requires
13946 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
13947 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
13948 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
13949 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
13951 bool isFastMultiplier = false;
13953 switch ((unsigned char)Diff) {
13955 case 1: // result = add base, cond
13956 case 2: // result = lea base( , cond*2)
13957 case 3: // result = lea base(cond, cond*2)
13958 case 4: // result = lea base( , cond*4)
13959 case 5: // result = lea base(cond, cond*4)
13960 case 8: // result = lea base( , cond*8)
13961 case 9: // result = lea base(cond, cond*8)
13962 isFastMultiplier = true;
13967 if (isFastMultiplier) {
13968 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
13969 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13970 DAG.getConstant(CC, MVT::i8), Cond);
13971 // Zero extend the condition if needed.
13972 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
13974 // Scale the condition by the difference.
13976 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
13977 DAG.getConstant(Diff, Cond.getValueType()));
13979 // Add the base if non-zero.
13980 if (FalseC->getAPIntValue() != 0)
13981 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13982 SDValue(FalseC, 0));
13983 if (N->getNumValues() == 2) // Dead flag value?
13984 return DCI.CombineTo(N, Cond, SDValue());
13994 /// PerformMulCombine - Optimize a single multiply with constant into two
13995 /// in order to implement it with two cheaper instructions, e.g.
13996 /// LEA + SHL, LEA + LEA.
13997 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
13998 TargetLowering::DAGCombinerInfo &DCI) {
13999 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
14002 EVT VT = N->getValueType(0);
14003 if (VT != MVT::i64)
14006 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
14009 uint64_t MulAmt = C->getZExtValue();
14010 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
14013 uint64_t MulAmt1 = 0;
14014 uint64_t MulAmt2 = 0;
14015 if ((MulAmt % 9) == 0) {
14017 MulAmt2 = MulAmt / 9;
14018 } else if ((MulAmt % 5) == 0) {
14020 MulAmt2 = MulAmt / 5;
14021 } else if ((MulAmt % 3) == 0) {
14023 MulAmt2 = MulAmt / 3;
14026 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
14027 DebugLoc DL = N->getDebugLoc();
14029 if (isPowerOf2_64(MulAmt2) &&
14030 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
14031 // If second multiplifer is pow2, issue it first. We want the multiply by
14032 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
14034 std::swap(MulAmt1, MulAmt2);
14037 if (isPowerOf2_64(MulAmt1))
14038 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
14039 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
14041 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
14042 DAG.getConstant(MulAmt1, VT));
14044 if (isPowerOf2_64(MulAmt2))
14045 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
14046 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
14048 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
14049 DAG.getConstant(MulAmt2, VT));
14051 // Do not add new nodes to DAG combiner worklist.
14052 DCI.CombineTo(N, NewMul, false);
14057 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
14058 SDValue N0 = N->getOperand(0);
14059 SDValue N1 = N->getOperand(1);
14060 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
14061 EVT VT = N0.getValueType();
14063 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
14064 // since the result of setcc_c is all zero's or all ones.
14065 if (VT.isInteger() && !VT.isVector() &&
14066 N1C && N0.getOpcode() == ISD::AND &&
14067 N0.getOperand(1).getOpcode() == ISD::Constant) {
14068 SDValue N00 = N0.getOperand(0);
14069 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
14070 ((N00.getOpcode() == ISD::ANY_EXTEND ||
14071 N00.getOpcode() == ISD::ZERO_EXTEND) &&
14072 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
14073 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
14074 APInt ShAmt = N1C->getAPIntValue();
14075 Mask = Mask.shl(ShAmt);
14077 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
14078 N00, DAG.getConstant(Mask, VT));
14083 // Hardware support for vector shifts is sparse which makes us scalarize the
14084 // vector operations in many cases. Also, on sandybridge ADD is faster than
14086 // (shl V, 1) -> add V,V
14087 if (isSplatVector(N1.getNode())) {
14088 assert(N0.getValueType().isVector() && "Invalid vector shift type");
14089 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1->getOperand(0));
14090 // We shift all of the values by one. In many cases we do not have
14091 // hardware support for this operation. This is better expressed as an ADD
14093 if (N1C && (1 == N1C->getZExtValue())) {
14094 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N0);
14101 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
14103 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
14104 TargetLowering::DAGCombinerInfo &DCI,
14105 const X86Subtarget *Subtarget) {
14106 EVT VT = N->getValueType(0);
14107 if (N->getOpcode() == ISD::SHL) {
14108 SDValue V = PerformSHLCombine(N, DAG);
14109 if (V.getNode()) return V;
14112 // On X86 with SSE2 support, we can transform this to a vector shift if
14113 // all elements are shifted by the same amount. We can't do this in legalize
14114 // because the a constant vector is typically transformed to a constant pool
14115 // so we have no knowledge of the shift amount.
14116 if (!Subtarget->hasSSE2())
14119 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
14120 (!Subtarget->hasAVX2() ||
14121 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
14124 SDValue ShAmtOp = N->getOperand(1);
14125 EVT EltVT = VT.getVectorElementType();
14126 DebugLoc DL = N->getDebugLoc();
14127 SDValue BaseShAmt = SDValue();
14128 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
14129 unsigned NumElts = VT.getVectorNumElements();
14131 for (; i != NumElts; ++i) {
14132 SDValue Arg = ShAmtOp.getOperand(i);
14133 if (Arg.getOpcode() == ISD::UNDEF) continue;
14137 // Handle the case where the build_vector is all undef
14138 // FIXME: Should DAG allow this?
14142 for (; i != NumElts; ++i) {
14143 SDValue Arg = ShAmtOp.getOperand(i);
14144 if (Arg.getOpcode() == ISD::UNDEF) continue;
14145 if (Arg != BaseShAmt) {
14149 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
14150 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
14151 SDValue InVec = ShAmtOp.getOperand(0);
14152 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
14153 unsigned NumElts = InVec.getValueType().getVectorNumElements();
14155 for (; i != NumElts; ++i) {
14156 SDValue Arg = InVec.getOperand(i);
14157 if (Arg.getOpcode() == ISD::UNDEF) continue;
14161 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
14162 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
14163 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex();
14164 if (C->getZExtValue() == SplatIdx)
14165 BaseShAmt = InVec.getOperand(1);
14168 if (BaseShAmt.getNode() == 0) {
14169 // Don't create instructions with illegal types after legalize
14171 if (!DAG.getTargetLoweringInfo().isTypeLegal(EltVT) &&
14172 !DCI.isBeforeLegalize())
14175 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
14176 DAG.getIntPtrConstant(0));
14181 // The shift amount is an i32.
14182 if (EltVT.bitsGT(MVT::i32))
14183 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
14184 else if (EltVT.bitsLT(MVT::i32))
14185 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt);
14187 // The shift amount is identical so we can do a vector shift.
14188 SDValue ValOp = N->getOperand(0);
14189 switch (N->getOpcode()) {
14191 llvm_unreachable("Unknown shift opcode!");
14193 switch (VT.getSimpleVT().SimpleTy) {
14194 default: return SDValue();
14201 return getTargetVShiftNode(X86ISD::VSHLI, DL, VT, ValOp, BaseShAmt, DAG);
14204 switch (VT.getSimpleVT().SimpleTy) {
14205 default: return SDValue();
14210 return getTargetVShiftNode(X86ISD::VSRAI, DL, VT, ValOp, BaseShAmt, DAG);
14213 switch (VT.getSimpleVT().SimpleTy) {
14214 default: return SDValue();
14221 return getTargetVShiftNode(X86ISD::VSRLI, DL, VT, ValOp, BaseShAmt, DAG);
14227 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
14228 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
14229 // and friends. Likewise for OR -> CMPNEQSS.
14230 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
14231 TargetLowering::DAGCombinerInfo &DCI,
14232 const X86Subtarget *Subtarget) {
14235 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
14236 // we're requiring SSE2 for both.
14237 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
14238 SDValue N0 = N->getOperand(0);
14239 SDValue N1 = N->getOperand(1);
14240 SDValue CMP0 = N0->getOperand(1);
14241 SDValue CMP1 = N1->getOperand(1);
14242 DebugLoc DL = N->getDebugLoc();
14244 // The SETCCs should both refer to the same CMP.
14245 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
14248 SDValue CMP00 = CMP0->getOperand(0);
14249 SDValue CMP01 = CMP0->getOperand(1);
14250 EVT VT = CMP00.getValueType();
14252 if (VT == MVT::f32 || VT == MVT::f64) {
14253 bool ExpectingFlags = false;
14254 // Check for any users that want flags:
14255 for (SDNode::use_iterator UI = N->use_begin(),
14257 !ExpectingFlags && UI != UE; ++UI)
14258 switch (UI->getOpcode()) {
14263 ExpectingFlags = true;
14265 case ISD::CopyToReg:
14266 case ISD::SIGN_EXTEND:
14267 case ISD::ZERO_EXTEND:
14268 case ISD::ANY_EXTEND:
14272 if (!ExpectingFlags) {
14273 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
14274 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
14276 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
14277 X86::CondCode tmp = cc0;
14282 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
14283 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
14284 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
14285 X86ISD::NodeType NTOperator = is64BitFP ?
14286 X86ISD::FSETCCsd : X86ISD::FSETCCss;
14287 // FIXME: need symbolic constants for these magic numbers.
14288 // See X86ATTInstPrinter.cpp:printSSECC().
14289 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
14290 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01,
14291 DAG.getConstant(x86cc, MVT::i8));
14292 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32,
14294 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI,
14295 DAG.getConstant(1, MVT::i32));
14296 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
14297 return OneBitOfTruth;
14305 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
14306 /// so it can be folded inside ANDNP.
14307 static bool CanFoldXORWithAllOnes(const SDNode *N) {
14308 EVT VT = N->getValueType(0);
14310 // Match direct AllOnes for 128 and 256-bit vectors
14311 if (ISD::isBuildVectorAllOnes(N))
14314 // Look through a bit convert.
14315 if (N->getOpcode() == ISD::BITCAST)
14316 N = N->getOperand(0).getNode();
14318 // Sometimes the operand may come from a insert_subvector building a 256-bit
14320 if (VT.is256BitVector() &&
14321 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
14322 SDValue V1 = N->getOperand(0);
14323 SDValue V2 = N->getOperand(1);
14325 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
14326 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
14327 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
14328 ISD::isBuildVectorAllOnes(V2.getNode()))
14335 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
14336 TargetLowering::DAGCombinerInfo &DCI,
14337 const X86Subtarget *Subtarget) {
14338 if (DCI.isBeforeLegalizeOps())
14341 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
14345 EVT VT = N->getValueType(0);
14347 // Create ANDN, BLSI, and BLSR instructions
14348 // BLSI is X & (-X)
14349 // BLSR is X & (X-1)
14350 if (Subtarget->hasBMI() && (VT == MVT::i32 || VT == MVT::i64)) {
14351 SDValue N0 = N->getOperand(0);
14352 SDValue N1 = N->getOperand(1);
14353 DebugLoc DL = N->getDebugLoc();
14355 // Check LHS for not
14356 if (N0.getOpcode() == ISD::XOR && isAllOnes(N0.getOperand(1)))
14357 return DAG.getNode(X86ISD::ANDN, DL, VT, N0.getOperand(0), N1);
14358 // Check RHS for not
14359 if (N1.getOpcode() == ISD::XOR && isAllOnes(N1.getOperand(1)))
14360 return DAG.getNode(X86ISD::ANDN, DL, VT, N1.getOperand(0), N0);
14362 // Check LHS for neg
14363 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1) == N1 &&
14364 isZero(N0.getOperand(0)))
14365 return DAG.getNode(X86ISD::BLSI, DL, VT, N1);
14367 // Check RHS for neg
14368 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1) == N0 &&
14369 isZero(N1.getOperand(0)))
14370 return DAG.getNode(X86ISD::BLSI, DL, VT, N0);
14372 // Check LHS for X-1
14373 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
14374 isAllOnes(N0.getOperand(1)))
14375 return DAG.getNode(X86ISD::BLSR, DL, VT, N1);
14377 // Check RHS for X-1
14378 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
14379 isAllOnes(N1.getOperand(1)))
14380 return DAG.getNode(X86ISD::BLSR, DL, VT, N0);
14385 // Want to form ANDNP nodes:
14386 // 1) In the hopes of then easily combining them with OR and AND nodes
14387 // to form PBLEND/PSIGN.
14388 // 2) To match ANDN packed intrinsics
14389 if (VT != MVT::v2i64 && VT != MVT::v4i64)
14392 SDValue N0 = N->getOperand(0);
14393 SDValue N1 = N->getOperand(1);
14394 DebugLoc DL = N->getDebugLoc();
14396 // Check LHS for vnot
14397 if (N0.getOpcode() == ISD::XOR &&
14398 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
14399 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
14400 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
14402 // Check RHS for vnot
14403 if (N1.getOpcode() == ISD::XOR &&
14404 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
14405 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
14406 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
14411 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
14412 TargetLowering::DAGCombinerInfo &DCI,
14413 const X86Subtarget *Subtarget) {
14414 if (DCI.isBeforeLegalizeOps())
14417 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
14421 EVT VT = N->getValueType(0);
14423 SDValue N0 = N->getOperand(0);
14424 SDValue N1 = N->getOperand(1);
14426 // look for psign/blend
14427 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
14428 if (!Subtarget->hasSSSE3() ||
14429 (VT == MVT::v4i64 && !Subtarget->hasAVX2()))
14432 // Canonicalize pandn to RHS
14433 if (N0.getOpcode() == X86ISD::ANDNP)
14435 // or (and (m, y), (pandn m, x))
14436 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
14437 SDValue Mask = N1.getOperand(0);
14438 SDValue X = N1.getOperand(1);
14440 if (N0.getOperand(0) == Mask)
14441 Y = N0.getOperand(1);
14442 if (N0.getOperand(1) == Mask)
14443 Y = N0.getOperand(0);
14445 // Check to see if the mask appeared in both the AND and ANDNP and
14449 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
14450 // Look through mask bitcast.
14451 if (Mask.getOpcode() == ISD::BITCAST)
14452 Mask = Mask.getOperand(0);
14453 if (X.getOpcode() == ISD::BITCAST)
14454 X = X.getOperand(0);
14455 if (Y.getOpcode() == ISD::BITCAST)
14456 Y = Y.getOperand(0);
14458 EVT MaskVT = Mask.getValueType();
14460 // Validate that the Mask operand is a vector sra node.
14461 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
14462 // there is no psrai.b
14463 if (Mask.getOpcode() != X86ISD::VSRAI)
14466 // Check that the SRA is all signbits.
14467 SDValue SraC = Mask.getOperand(1);
14468 unsigned SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
14469 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
14470 if ((SraAmt + 1) != EltBits)
14473 DebugLoc DL = N->getDebugLoc();
14475 // Now we know we at least have a plendvb with the mask val. See if
14476 // we can form a psignb/w/d.
14477 // psign = x.type == y.type == mask.type && y = sub(0, x);
14478 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
14479 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
14480 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
14481 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
14482 "Unsupported VT for PSIGN");
14483 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
14484 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
14486 // PBLENDVB only available on SSE 4.1
14487 if (!Subtarget->hasSSE41())
14490 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
14492 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
14493 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
14494 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
14495 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
14496 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
14500 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
14503 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
14504 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
14506 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
14508 if (!N0.hasOneUse() || !N1.hasOneUse())
14511 SDValue ShAmt0 = N0.getOperand(1);
14512 if (ShAmt0.getValueType() != MVT::i8)
14514 SDValue ShAmt1 = N1.getOperand(1);
14515 if (ShAmt1.getValueType() != MVT::i8)
14517 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
14518 ShAmt0 = ShAmt0.getOperand(0);
14519 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
14520 ShAmt1 = ShAmt1.getOperand(0);
14522 DebugLoc DL = N->getDebugLoc();
14523 unsigned Opc = X86ISD::SHLD;
14524 SDValue Op0 = N0.getOperand(0);
14525 SDValue Op1 = N1.getOperand(0);
14526 if (ShAmt0.getOpcode() == ISD::SUB) {
14527 Opc = X86ISD::SHRD;
14528 std::swap(Op0, Op1);
14529 std::swap(ShAmt0, ShAmt1);
14532 unsigned Bits = VT.getSizeInBits();
14533 if (ShAmt1.getOpcode() == ISD::SUB) {
14534 SDValue Sum = ShAmt1.getOperand(0);
14535 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
14536 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
14537 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
14538 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
14539 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
14540 return DAG.getNode(Opc, DL, VT,
14542 DAG.getNode(ISD::TRUNCATE, DL,
14545 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
14546 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
14548 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
14549 return DAG.getNode(Opc, DL, VT,
14550 N0.getOperand(0), N1.getOperand(0),
14551 DAG.getNode(ISD::TRUNCATE, DL,
14558 // Generate NEG and CMOV for integer abs.
14559 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
14560 EVT VT = N->getValueType(0);
14562 // Since X86 does not have CMOV for 8-bit integer, we don't convert
14563 // 8-bit integer abs to NEG and CMOV.
14564 if (VT.isInteger() && VT.getSizeInBits() == 8)
14567 SDValue N0 = N->getOperand(0);
14568 SDValue N1 = N->getOperand(1);
14569 DebugLoc DL = N->getDebugLoc();
14571 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
14572 // and change it to SUB and CMOV.
14573 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
14574 N0.getOpcode() == ISD::ADD &&
14575 N0.getOperand(1) == N1 &&
14576 N1.getOpcode() == ISD::SRA &&
14577 N1.getOperand(0) == N0.getOperand(0))
14578 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
14579 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
14580 // Generate SUB & CMOV.
14581 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
14582 DAG.getConstant(0, VT), N0.getOperand(0));
14584 SDValue Ops[] = { N0.getOperand(0), Neg,
14585 DAG.getConstant(X86::COND_GE, MVT::i8),
14586 SDValue(Neg.getNode(), 1) };
14587 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue),
14588 Ops, array_lengthof(Ops));
14593 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
14594 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
14595 TargetLowering::DAGCombinerInfo &DCI,
14596 const X86Subtarget *Subtarget) {
14597 if (DCI.isBeforeLegalizeOps())
14600 if (Subtarget->hasCMov()) {
14601 SDValue RV = performIntegerAbsCombine(N, DAG);
14606 // Try forming BMI if it is available.
14607 if (!Subtarget->hasBMI())
14610 EVT VT = N->getValueType(0);
14612 if (VT != MVT::i32 && VT != MVT::i64)
14615 assert(Subtarget->hasBMI() && "Creating BLSMSK requires BMI instructions");
14617 // Create BLSMSK instructions by finding X ^ (X-1)
14618 SDValue N0 = N->getOperand(0);
14619 SDValue N1 = N->getOperand(1);
14620 DebugLoc DL = N->getDebugLoc();
14622 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
14623 isAllOnes(N0.getOperand(1)))
14624 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N1);
14626 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
14627 isAllOnes(N1.getOperand(1)))
14628 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N0);
14633 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
14634 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
14635 TargetLowering::DAGCombinerInfo &DCI,
14636 const X86Subtarget *Subtarget) {
14637 LoadSDNode *Ld = cast<LoadSDNode>(N);
14638 EVT RegVT = Ld->getValueType(0);
14639 EVT MemVT = Ld->getMemoryVT();
14640 DebugLoc dl = Ld->getDebugLoc();
14641 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14643 ISD::LoadExtType Ext = Ld->getExtensionType();
14645 // If this is a vector EXT Load then attempt to optimize it using a
14646 // shuffle. We need SSE4 for the shuffles.
14647 // TODO: It is possible to support ZExt by zeroing the undef values
14648 // during the shuffle phase or after the shuffle.
14649 if (RegVT.isVector() && RegVT.isInteger() &&
14650 Ext == ISD::EXTLOAD && Subtarget->hasSSE41()) {
14651 assert(MemVT != RegVT && "Cannot extend to the same type");
14652 assert(MemVT.isVector() && "Must load a vector from memory");
14654 unsigned NumElems = RegVT.getVectorNumElements();
14655 unsigned RegSz = RegVT.getSizeInBits();
14656 unsigned MemSz = MemVT.getSizeInBits();
14657 assert(RegSz > MemSz && "Register size must be greater than the mem size");
14659 // All sizes must be a power of two.
14660 if (!isPowerOf2_32(RegSz * MemSz * NumElems))
14663 // Attempt to load the original value using scalar loads.
14664 // Find the largest scalar type that divides the total loaded size.
14665 MVT SclrLoadTy = MVT::i8;
14666 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
14667 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
14668 MVT Tp = (MVT::SimpleValueType)tp;
14669 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
14674 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
14675 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
14677 SclrLoadTy = MVT::f64;
14679 // Calculate the number of scalar loads that we need to perform
14680 // in order to load our vector from memory.
14681 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
14683 // Represent our vector as a sequence of elements which are the
14684 // largest scalar that we can load.
14685 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy,
14686 RegSz/SclrLoadTy.getSizeInBits());
14688 // Represent the data using the same element type that is stored in
14689 // memory. In practice, we ''widen'' MemVT.
14690 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
14691 RegSz/MemVT.getScalarType().getSizeInBits());
14693 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
14694 "Invalid vector type");
14696 // We can't shuffle using an illegal type.
14697 if (!TLI.isTypeLegal(WideVecVT))
14700 SmallVector<SDValue, 8> Chains;
14701 SDValue Ptr = Ld->getBasePtr();
14702 SDValue Increment = DAG.getConstant(SclrLoadTy.getSizeInBits()/8,
14703 TLI.getPointerTy());
14704 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
14706 for (unsigned i = 0; i < NumLoads; ++i) {
14707 // Perform a single load.
14708 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(),
14709 Ptr, Ld->getPointerInfo(),
14710 Ld->isVolatile(), Ld->isNonTemporal(),
14711 Ld->isInvariant(), Ld->getAlignment());
14712 Chains.push_back(ScalarLoad.getValue(1));
14713 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
14714 // another round of DAGCombining.
14716 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
14718 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
14719 ScalarLoad, DAG.getIntPtrConstant(i));
14721 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
14724 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
14727 // Bitcast the loaded value to a vector of the original element type, in
14728 // the size of the target vector type.
14729 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
14730 unsigned SizeRatio = RegSz/MemSz;
14732 // Redistribute the loaded elements into the different locations.
14733 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
14734 for (unsigned i = 0; i != NumElems; ++i)
14735 ShuffleVec[i*SizeRatio] = i;
14737 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
14738 DAG.getUNDEF(WideVecVT),
14741 // Bitcast to the requested type.
14742 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
14743 // Replace the original load with the new sequence
14744 // and return the new chain.
14745 return DCI.CombineTo(N, Shuff, TF, true);
14751 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
14752 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
14753 const X86Subtarget *Subtarget) {
14754 StoreSDNode *St = cast<StoreSDNode>(N);
14755 EVT VT = St->getValue().getValueType();
14756 EVT StVT = St->getMemoryVT();
14757 DebugLoc dl = St->getDebugLoc();
14758 SDValue StoredVal = St->getOperand(1);
14759 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14761 // If we are saving a concatenation of two XMM registers, perform two stores.
14762 // On Sandy Bridge, 256-bit memory operations are executed by two
14763 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit
14764 // memory operation.
14765 if (VT.is256BitVector() && !Subtarget->hasAVX2() &&
14766 StoredVal.getNode()->getOpcode() == ISD::CONCAT_VECTORS &&
14767 StoredVal.getNumOperands() == 2) {
14768 SDValue Value0 = StoredVal.getOperand(0);
14769 SDValue Value1 = StoredVal.getOperand(1);
14771 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
14772 SDValue Ptr0 = St->getBasePtr();
14773 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
14775 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
14776 St->getPointerInfo(), St->isVolatile(),
14777 St->isNonTemporal(), St->getAlignment());
14778 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
14779 St->getPointerInfo(), St->isVolatile(),
14780 St->isNonTemporal(), St->getAlignment());
14781 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
14784 // Optimize trunc store (of multiple scalars) to shuffle and store.
14785 // First, pack all of the elements in one place. Next, store to memory
14786 // in fewer chunks.
14787 if (St->isTruncatingStore() && VT.isVector()) {
14788 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14789 unsigned NumElems = VT.getVectorNumElements();
14790 assert(StVT != VT && "Cannot truncate to the same type");
14791 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
14792 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
14794 // From, To sizes and ElemCount must be pow of two
14795 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
14796 // We are going to use the original vector elt for storing.
14797 // Accumulated smaller vector elements must be a multiple of the store size.
14798 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
14800 unsigned SizeRatio = FromSz / ToSz;
14802 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
14804 // Create a type on which we perform the shuffle
14805 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
14806 StVT.getScalarType(), NumElems*SizeRatio);
14808 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
14810 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
14811 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
14812 for (unsigned i = 0; i != NumElems; ++i)
14813 ShuffleVec[i] = i * SizeRatio;
14815 // Can't shuffle using an illegal type.
14816 if (!TLI.isTypeLegal(WideVecVT))
14819 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
14820 DAG.getUNDEF(WideVecVT),
14822 // At this point all of the data is stored at the bottom of the
14823 // register. We now need to save it to mem.
14825 // Find the largest store unit
14826 MVT StoreType = MVT::i8;
14827 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
14828 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
14829 MVT Tp = (MVT::SimpleValueType)tp;
14830 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
14834 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
14835 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
14836 (64 <= NumElems * ToSz))
14837 StoreType = MVT::f64;
14839 // Bitcast the original vector into a vector of store-size units
14840 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
14841 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
14842 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
14843 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
14844 SmallVector<SDValue, 8> Chains;
14845 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
14846 TLI.getPointerTy());
14847 SDValue Ptr = St->getBasePtr();
14849 // Perform one or more big stores into memory.
14850 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
14851 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
14852 StoreType, ShuffWide,
14853 DAG.getIntPtrConstant(i));
14854 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
14855 St->getPointerInfo(), St->isVolatile(),
14856 St->isNonTemporal(), St->getAlignment());
14857 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
14858 Chains.push_back(Ch);
14861 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
14866 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
14867 // the FP state in cases where an emms may be missing.
14868 // A preferable solution to the general problem is to figure out the right
14869 // places to insert EMMS. This qualifies as a quick hack.
14871 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
14872 if (VT.getSizeInBits() != 64)
14875 const Function *F = DAG.getMachineFunction().getFunction();
14876 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
14877 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
14878 && Subtarget->hasSSE2();
14879 if ((VT.isVector() ||
14880 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
14881 isa<LoadSDNode>(St->getValue()) &&
14882 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
14883 St->getChain().hasOneUse() && !St->isVolatile()) {
14884 SDNode* LdVal = St->getValue().getNode();
14885 LoadSDNode *Ld = 0;
14886 int TokenFactorIndex = -1;
14887 SmallVector<SDValue, 8> Ops;
14888 SDNode* ChainVal = St->getChain().getNode();
14889 // Must be a store of a load. We currently handle two cases: the load
14890 // is a direct child, and it's under an intervening TokenFactor. It is
14891 // possible to dig deeper under nested TokenFactors.
14892 if (ChainVal == LdVal)
14893 Ld = cast<LoadSDNode>(St->getChain());
14894 else if (St->getValue().hasOneUse() &&
14895 ChainVal->getOpcode() == ISD::TokenFactor) {
14896 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
14897 if (ChainVal->getOperand(i).getNode() == LdVal) {
14898 TokenFactorIndex = i;
14899 Ld = cast<LoadSDNode>(St->getValue());
14901 Ops.push_back(ChainVal->getOperand(i));
14905 if (!Ld || !ISD::isNormalLoad(Ld))
14908 // If this is not the MMX case, i.e. we are just turning i64 load/store
14909 // into f64 load/store, avoid the transformation if there are multiple
14910 // uses of the loaded value.
14911 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
14914 DebugLoc LdDL = Ld->getDebugLoc();
14915 DebugLoc StDL = N->getDebugLoc();
14916 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
14917 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
14919 if (Subtarget->is64Bit() || F64IsLegal) {
14920 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
14921 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
14922 Ld->getPointerInfo(), Ld->isVolatile(),
14923 Ld->isNonTemporal(), Ld->isInvariant(),
14924 Ld->getAlignment());
14925 SDValue NewChain = NewLd.getValue(1);
14926 if (TokenFactorIndex != -1) {
14927 Ops.push_back(NewChain);
14928 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
14931 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
14932 St->getPointerInfo(),
14933 St->isVolatile(), St->isNonTemporal(),
14934 St->getAlignment());
14937 // Otherwise, lower to two pairs of 32-bit loads / stores.
14938 SDValue LoAddr = Ld->getBasePtr();
14939 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
14940 DAG.getConstant(4, MVT::i32));
14942 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
14943 Ld->getPointerInfo(),
14944 Ld->isVolatile(), Ld->isNonTemporal(),
14945 Ld->isInvariant(), Ld->getAlignment());
14946 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
14947 Ld->getPointerInfo().getWithOffset(4),
14948 Ld->isVolatile(), Ld->isNonTemporal(),
14950 MinAlign(Ld->getAlignment(), 4));
14952 SDValue NewChain = LoLd.getValue(1);
14953 if (TokenFactorIndex != -1) {
14954 Ops.push_back(LoLd);
14955 Ops.push_back(HiLd);
14956 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
14960 LoAddr = St->getBasePtr();
14961 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
14962 DAG.getConstant(4, MVT::i32));
14964 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
14965 St->getPointerInfo(),
14966 St->isVolatile(), St->isNonTemporal(),
14967 St->getAlignment());
14968 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
14969 St->getPointerInfo().getWithOffset(4),
14971 St->isNonTemporal(),
14972 MinAlign(St->getAlignment(), 4));
14973 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
14978 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
14979 /// and return the operands for the horizontal operation in LHS and RHS. A
14980 /// horizontal operation performs the binary operation on successive elements
14981 /// of its first operand, then on successive elements of its second operand,
14982 /// returning the resulting values in a vector. For example, if
14983 /// A = < float a0, float a1, float a2, float a3 >
14985 /// B = < float b0, float b1, float b2, float b3 >
14986 /// then the result of doing a horizontal operation on A and B is
14987 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
14988 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
14989 /// A horizontal-op B, for some already available A and B, and if so then LHS is
14990 /// set to A, RHS to B, and the routine returns 'true'.
14991 /// Note that the binary operation should have the property that if one of the
14992 /// operands is UNDEF then the result is UNDEF.
14993 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
14994 // Look for the following pattern: if
14995 // A = < float a0, float a1, float a2, float a3 >
14996 // B = < float b0, float b1, float b2, float b3 >
14998 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
14999 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
15000 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
15001 // which is A horizontal-op B.
15003 // At least one of the operands should be a vector shuffle.
15004 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
15005 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
15008 EVT VT = LHS.getValueType();
15010 assert((VT.is128BitVector() || VT.is256BitVector()) &&
15011 "Unsupported vector type for horizontal add/sub");
15013 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
15014 // operate independently on 128-bit lanes.
15015 unsigned NumElts = VT.getVectorNumElements();
15016 unsigned NumLanes = VT.getSizeInBits()/128;
15017 unsigned NumLaneElts = NumElts / NumLanes;
15018 assert((NumLaneElts % 2 == 0) &&
15019 "Vector type should have an even number of elements in each lane");
15020 unsigned HalfLaneElts = NumLaneElts/2;
15022 // View LHS in the form
15023 // LHS = VECTOR_SHUFFLE A, B, LMask
15024 // If LHS is not a shuffle then pretend it is the shuffle
15025 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
15026 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
15029 SmallVector<int, 16> LMask(NumElts);
15030 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
15031 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
15032 A = LHS.getOperand(0);
15033 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
15034 B = LHS.getOperand(1);
15035 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
15036 std::copy(Mask.begin(), Mask.end(), LMask.begin());
15038 if (LHS.getOpcode() != ISD::UNDEF)
15040 for (unsigned i = 0; i != NumElts; ++i)
15044 // Likewise, view RHS in the form
15045 // RHS = VECTOR_SHUFFLE C, D, RMask
15047 SmallVector<int, 16> RMask(NumElts);
15048 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
15049 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
15050 C = RHS.getOperand(0);
15051 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
15052 D = RHS.getOperand(1);
15053 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
15054 std::copy(Mask.begin(), Mask.end(), RMask.begin());
15056 if (RHS.getOpcode() != ISD::UNDEF)
15058 for (unsigned i = 0; i != NumElts; ++i)
15062 // Check that the shuffles are both shuffling the same vectors.
15063 if (!(A == C && B == D) && !(A == D && B == C))
15066 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
15067 if (!A.getNode() && !B.getNode())
15070 // If A and B occur in reverse order in RHS, then "swap" them (which means
15071 // rewriting the mask).
15073 CommuteVectorShuffleMask(RMask, NumElts);
15075 // At this point LHS and RHS are equivalent to
15076 // LHS = VECTOR_SHUFFLE A, B, LMask
15077 // RHS = VECTOR_SHUFFLE A, B, RMask
15078 // Check that the masks correspond to performing a horizontal operation.
15079 for (unsigned i = 0; i != NumElts; ++i) {
15080 int LIdx = LMask[i], RIdx = RMask[i];
15082 // Ignore any UNDEF components.
15083 if (LIdx < 0 || RIdx < 0 ||
15084 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
15085 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
15088 // Check that successive elements are being operated on. If not, this is
15089 // not a horizontal operation.
15090 unsigned Src = (i/HalfLaneElts) % 2; // each lane is split between srcs
15091 unsigned LaneStart = (i/NumLaneElts) * NumLaneElts;
15092 int Index = 2*(i%HalfLaneElts) + NumElts*Src + LaneStart;
15093 if (!(LIdx == Index && RIdx == Index + 1) &&
15094 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
15098 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
15099 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
15103 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
15104 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
15105 const X86Subtarget *Subtarget) {
15106 EVT VT = N->getValueType(0);
15107 SDValue LHS = N->getOperand(0);
15108 SDValue RHS = N->getOperand(1);
15110 // Try to synthesize horizontal adds from adds of shuffles.
15111 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
15112 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
15113 isHorizontalBinOp(LHS, RHS, true))
15114 return DAG.getNode(X86ISD::FHADD, N->getDebugLoc(), VT, LHS, RHS);
15118 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
15119 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
15120 const X86Subtarget *Subtarget) {
15121 EVT VT = N->getValueType(0);
15122 SDValue LHS = N->getOperand(0);
15123 SDValue RHS = N->getOperand(1);
15125 // Try to synthesize horizontal subs from subs of shuffles.
15126 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
15127 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
15128 isHorizontalBinOp(LHS, RHS, false))
15129 return DAG.getNode(X86ISD::FHSUB, N->getDebugLoc(), VT, LHS, RHS);
15133 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
15134 /// X86ISD::FXOR nodes.
15135 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
15136 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
15137 // F[X]OR(0.0, x) -> x
15138 // F[X]OR(x, 0.0) -> x
15139 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
15140 if (C->getValueAPF().isPosZero())
15141 return N->getOperand(1);
15142 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
15143 if (C->getValueAPF().isPosZero())
15144 return N->getOperand(0);
15148 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
15149 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
15150 // FAND(0.0, x) -> 0.0
15151 // FAND(x, 0.0) -> 0.0
15152 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
15153 if (C->getValueAPF().isPosZero())
15154 return N->getOperand(0);
15155 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
15156 if (C->getValueAPF().isPosZero())
15157 return N->getOperand(1);
15161 static SDValue PerformBTCombine(SDNode *N,
15163 TargetLowering::DAGCombinerInfo &DCI) {
15164 // BT ignores high bits in the bit index operand.
15165 SDValue Op1 = N->getOperand(1);
15166 if (Op1.hasOneUse()) {
15167 unsigned BitWidth = Op1.getValueSizeInBits();
15168 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
15169 APInt KnownZero, KnownOne;
15170 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
15171 !DCI.isBeforeLegalizeOps());
15172 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15173 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
15174 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
15175 DCI.CommitTargetLoweringOpt(TLO);
15180 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
15181 SDValue Op = N->getOperand(0);
15182 if (Op.getOpcode() == ISD::BITCAST)
15183 Op = Op.getOperand(0);
15184 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
15185 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
15186 VT.getVectorElementType().getSizeInBits() ==
15187 OpVT.getVectorElementType().getSizeInBits()) {
15188 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op);
15193 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
15194 TargetLowering::DAGCombinerInfo &DCI,
15195 const X86Subtarget *Subtarget) {
15196 if (!DCI.isBeforeLegalizeOps())
15199 if (!Subtarget->hasAVX())
15202 EVT VT = N->getValueType(0);
15203 SDValue Op = N->getOperand(0);
15204 EVT OpVT = Op.getValueType();
15205 DebugLoc dl = N->getDebugLoc();
15207 if ((VT == MVT::v4i64 && OpVT == MVT::v4i32) ||
15208 (VT == MVT::v8i32 && OpVT == MVT::v8i16)) {
15210 if (Subtarget->hasAVX2())
15211 return DAG.getNode(X86ISD::VSEXT_MOVL, dl, VT, Op);
15213 // Optimize vectors in AVX mode
15214 // Sign extend v8i16 to v8i32 and
15217 // Divide input vector into two parts
15218 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
15219 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
15220 // concat the vectors to original VT
15222 unsigned NumElems = OpVT.getVectorNumElements();
15223 SmallVector<int,8> ShufMask1(NumElems, -1);
15224 for (unsigned i = 0; i != NumElems/2; ++i)
15227 SDValue OpLo = DAG.getVectorShuffle(OpVT, dl, Op, DAG.getUNDEF(OpVT),
15230 SmallVector<int,8> ShufMask2(NumElems, -1);
15231 for (unsigned i = 0; i != NumElems/2; ++i)
15232 ShufMask2[i] = i + NumElems/2;
15234 SDValue OpHi = DAG.getVectorShuffle(OpVT, dl, Op, DAG.getUNDEF(OpVT),
15237 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), VT.getScalarType(),
15238 VT.getVectorNumElements()/2);
15240 OpLo = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpLo);
15241 OpHi = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpHi);
15243 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
15248 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
15249 const X86Subtarget* Subtarget) {
15250 DebugLoc dl = N->getDebugLoc();
15251 EVT VT = N->getValueType(0);
15253 EVT ScalarVT = VT.getScalarType();
15254 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) || !Subtarget->hasFMA())
15257 SDValue A = N->getOperand(0);
15258 SDValue B = N->getOperand(1);
15259 SDValue C = N->getOperand(2);
15261 bool NegA = (A.getOpcode() == ISD::FNEG);
15262 bool NegB = (B.getOpcode() == ISD::FNEG);
15263 bool NegC = (C.getOpcode() == ISD::FNEG);
15265 // Negative multiplication when NegA xor NegB
15266 bool NegMul = (NegA != NegB);
15268 A = A.getOperand(0);
15270 B = B.getOperand(0);
15272 C = C.getOperand(0);
15276 Opcode = (!NegC)? X86ISD::FMADD : X86ISD::FMSUB;
15278 Opcode = (!NegC)? X86ISD::FNMADD : X86ISD::FNMSUB;
15279 return DAG.getNode(Opcode, dl, VT, A, B, C);
15282 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
15283 TargetLowering::DAGCombinerInfo &DCI,
15284 const X86Subtarget *Subtarget) {
15285 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
15286 // (and (i32 x86isd::setcc_carry), 1)
15287 // This eliminates the zext. This transformation is necessary because
15288 // ISD::SETCC is always legalized to i8.
15289 DebugLoc dl = N->getDebugLoc();
15290 SDValue N0 = N->getOperand(0);
15291 EVT VT = N->getValueType(0);
15292 EVT OpVT = N0.getValueType();
15294 if (N0.getOpcode() == ISD::AND &&
15296 N0.getOperand(0).hasOneUse()) {
15297 SDValue N00 = N0.getOperand(0);
15298 if (N00.getOpcode() != X86ISD::SETCC_CARRY)
15300 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
15301 if (!C || C->getZExtValue() != 1)
15303 return DAG.getNode(ISD::AND, dl, VT,
15304 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
15305 N00.getOperand(0), N00.getOperand(1)),
15306 DAG.getConstant(1, VT));
15309 // Optimize vectors in AVX mode:
15312 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
15313 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
15314 // Concat upper and lower parts.
15317 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
15318 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
15319 // Concat upper and lower parts.
15321 if (!DCI.isBeforeLegalizeOps())
15324 if (!Subtarget->hasAVX())
15327 if (((VT == MVT::v8i32) && (OpVT == MVT::v8i16)) ||
15328 ((VT == MVT::v4i64) && (OpVT == MVT::v4i32))) {
15330 if (Subtarget->hasAVX2())
15331 return DAG.getNode(X86ISD::VZEXT_MOVL, dl, VT, N0);
15333 SDValue ZeroVec = getZeroVector(OpVT, Subtarget, DAG, dl);
15334 SDValue OpLo = getUnpackl(DAG, dl, OpVT, N0, ZeroVec);
15335 SDValue OpHi = getUnpackh(DAG, dl, OpVT, N0, ZeroVec);
15337 EVT HVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
15338 VT.getVectorNumElements()/2);
15340 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
15341 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
15343 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
15349 // Optimize x == -y --> x+y == 0
15350 // x != -y --> x+y != 0
15351 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG) {
15352 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
15353 SDValue LHS = N->getOperand(0);
15354 SDValue RHS = N->getOperand(1);
15356 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
15357 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
15358 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
15359 SDValue addV = DAG.getNode(ISD::ADD, N->getDebugLoc(),
15360 LHS.getValueType(), RHS, LHS.getOperand(1));
15361 return DAG.getSetCC(N->getDebugLoc(), N->getValueType(0),
15362 addV, DAG.getConstant(0, addV.getValueType()), CC);
15364 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
15365 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
15366 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
15367 SDValue addV = DAG.getNode(ISD::ADD, N->getDebugLoc(),
15368 RHS.getValueType(), LHS, RHS.getOperand(1));
15369 return DAG.getSetCC(N->getDebugLoc(), N->getValueType(0),
15370 addV, DAG.getConstant(0, addV.getValueType()), CC);
15375 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
15376 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG) {
15377 DebugLoc DL = N->getDebugLoc();
15378 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
15379 SDValue EFLAGS = N->getOperand(1);
15381 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
15382 // a zext and produces an all-ones bit which is more useful than 0/1 in some
15384 if (CC == X86::COND_B)
15385 return DAG.getNode(ISD::AND, DL, MVT::i8,
15386 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
15387 DAG.getConstant(CC, MVT::i8), EFLAGS),
15388 DAG.getConstant(1, MVT::i8));
15392 Flags = BoolTestSetCCCombine(EFLAGS, CC);
15393 if (Flags.getNode()) {
15394 SDValue Cond = DAG.getConstant(CC, MVT::i8);
15395 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
15401 // Optimize branch condition evaluation.
15403 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
15404 TargetLowering::DAGCombinerInfo &DCI,
15405 const X86Subtarget *Subtarget) {
15406 DebugLoc DL = N->getDebugLoc();
15407 SDValue Chain = N->getOperand(0);
15408 SDValue Dest = N->getOperand(1);
15409 SDValue EFLAGS = N->getOperand(3);
15410 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
15414 Flags = BoolTestSetCCCombine(EFLAGS, CC);
15415 if (Flags.getNode()) {
15416 SDValue Cond = DAG.getConstant(CC, MVT::i8);
15417 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
15424 static SDValue PerformUINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG) {
15425 SDValue Op0 = N->getOperand(0);
15426 EVT InVT = Op0->getValueType(0);
15428 // UINT_TO_FP(v4i8) -> SINT_TO_FP(ZEXT(v4i8 to v4i32))
15429 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
15430 DebugLoc dl = N->getDebugLoc();
15431 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
15432 SDValue P = DAG.getNode(ISD::ZERO_EXTEND, dl, DstVT, Op0);
15433 // Notice that we use SINT_TO_FP because we know that the high bits
15434 // are zero and SINT_TO_FP is better supported by the hardware.
15435 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
15441 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
15442 const X86TargetLowering *XTLI) {
15443 SDValue Op0 = N->getOperand(0);
15444 EVT InVT = Op0->getValueType(0);
15446 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
15447 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
15448 DebugLoc dl = N->getDebugLoc();
15449 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
15450 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
15451 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
15454 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
15455 // a 32-bit target where SSE doesn't support i64->FP operations.
15456 if (Op0.getOpcode() == ISD::LOAD) {
15457 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
15458 EVT VT = Ld->getValueType(0);
15459 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
15460 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
15461 !XTLI->getSubtarget()->is64Bit() &&
15462 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
15463 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
15464 Ld->getChain(), Op0, DAG);
15465 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
15472 static SDValue PerformFP_TO_SINTCombine(SDNode *N, SelectionDAG &DAG) {
15473 EVT VT = N->getValueType(0);
15475 // v4i8 = FP_TO_SINT() -> v4i8 = TRUNCATE (V4i32 = FP_TO_SINT()
15476 if (VT == MVT::v8i8 || VT == MVT::v4i8) {
15477 DebugLoc dl = N->getDebugLoc();
15478 MVT DstVT = VT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
15479 SDValue I = DAG.getNode(ISD::FP_TO_SINT, dl, DstVT, N->getOperand(0));
15480 return DAG.getNode(ISD::TRUNCATE, dl, VT, I);
15486 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
15487 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
15488 X86TargetLowering::DAGCombinerInfo &DCI) {
15489 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
15490 // the result is either zero or one (depending on the input carry bit).
15491 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
15492 if (X86::isZeroNode(N->getOperand(0)) &&
15493 X86::isZeroNode(N->getOperand(1)) &&
15494 // We don't have a good way to replace an EFLAGS use, so only do this when
15496 SDValue(N, 1).use_empty()) {
15497 DebugLoc DL = N->getDebugLoc();
15498 EVT VT = N->getValueType(0);
15499 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
15500 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
15501 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
15502 DAG.getConstant(X86::COND_B,MVT::i8),
15504 DAG.getConstant(1, VT));
15505 return DCI.CombineTo(N, Res1, CarryOut);
15511 // fold (add Y, (sete X, 0)) -> adc 0, Y
15512 // (add Y, (setne X, 0)) -> sbb -1, Y
15513 // (sub (sete X, 0), Y) -> sbb 0, Y
15514 // (sub (setne X, 0), Y) -> adc -1, Y
15515 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
15516 DebugLoc DL = N->getDebugLoc();
15518 // Look through ZExts.
15519 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
15520 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
15523 SDValue SetCC = Ext.getOperand(0);
15524 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
15527 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
15528 if (CC != X86::COND_E && CC != X86::COND_NE)
15531 SDValue Cmp = SetCC.getOperand(1);
15532 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
15533 !X86::isZeroNode(Cmp.getOperand(1)) ||
15534 !Cmp.getOperand(0).getValueType().isInteger())
15537 SDValue CmpOp0 = Cmp.getOperand(0);
15538 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
15539 DAG.getConstant(1, CmpOp0.getValueType()));
15541 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
15542 if (CC == X86::COND_NE)
15543 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
15544 DL, OtherVal.getValueType(), OtherVal,
15545 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
15546 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
15547 DL, OtherVal.getValueType(), OtherVal,
15548 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
15551 /// PerformADDCombine - Do target-specific dag combines on integer adds.
15552 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
15553 const X86Subtarget *Subtarget) {
15554 EVT VT = N->getValueType(0);
15555 SDValue Op0 = N->getOperand(0);
15556 SDValue Op1 = N->getOperand(1);
15558 // Try to synthesize horizontal adds from adds of shuffles.
15559 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
15560 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
15561 isHorizontalBinOp(Op0, Op1, true))
15562 return DAG.getNode(X86ISD::HADD, N->getDebugLoc(), VT, Op0, Op1);
15564 return OptimizeConditionalInDecrement(N, DAG);
15567 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
15568 const X86Subtarget *Subtarget) {
15569 SDValue Op0 = N->getOperand(0);
15570 SDValue Op1 = N->getOperand(1);
15572 // X86 can't encode an immediate LHS of a sub. See if we can push the
15573 // negation into a preceding instruction.
15574 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
15575 // If the RHS of the sub is a XOR with one use and a constant, invert the
15576 // immediate. Then add one to the LHS of the sub so we can turn
15577 // X-Y -> X+~Y+1, saving one register.
15578 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
15579 isa<ConstantSDNode>(Op1.getOperand(1))) {
15580 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
15581 EVT VT = Op0.getValueType();
15582 SDValue NewXor = DAG.getNode(ISD::XOR, Op1.getDebugLoc(), VT,
15584 DAG.getConstant(~XorC, VT));
15585 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, NewXor,
15586 DAG.getConstant(C->getAPIntValue()+1, VT));
15590 // Try to synthesize horizontal adds from adds of shuffles.
15591 EVT VT = N->getValueType(0);
15592 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
15593 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
15594 isHorizontalBinOp(Op0, Op1, true))
15595 return DAG.getNode(X86ISD::HSUB, N->getDebugLoc(), VT, Op0, Op1);
15597 return OptimizeConditionalInDecrement(N, DAG);
15600 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
15601 DAGCombinerInfo &DCI) const {
15602 SelectionDAG &DAG = DCI.DAG;
15603 switch (N->getOpcode()) {
15605 case ISD::EXTRACT_VECTOR_ELT:
15606 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
15608 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
15609 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);
15610 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
15611 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
15612 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
15613 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
15616 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
15617 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
15618 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
15619 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
15620 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
15621 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
15622 case ISD::UINT_TO_FP: return PerformUINT_TO_FPCombine(N, DAG);
15623 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
15624 case ISD::FP_TO_SINT: return PerformFP_TO_SINTCombine(N, DAG);
15625 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
15626 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
15628 case X86ISD::FOR: return PerformFORCombine(N, DAG);
15629 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
15630 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
15631 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
15632 case ISD::ANY_EXTEND:
15633 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
15634 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
15635 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG, DCI);
15636 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG);
15637 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG);
15638 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
15639 case X86ISD::SHUFP: // Handle all target specific shuffles
15640 case X86ISD::PALIGN:
15641 case X86ISD::UNPCKH:
15642 case X86ISD::UNPCKL:
15643 case X86ISD::MOVHLPS:
15644 case X86ISD::MOVLHPS:
15645 case X86ISD::PSHUFD:
15646 case X86ISD::PSHUFHW:
15647 case X86ISD::PSHUFLW:
15648 case X86ISD::MOVSS:
15649 case X86ISD::MOVSD:
15650 case X86ISD::VPERMILP:
15651 case X86ISD::VPERM2X128:
15652 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
15653 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
15659 /// isTypeDesirableForOp - Return true if the target has native support for
15660 /// the specified value type and it is 'desirable' to use the type for the
15661 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
15662 /// instruction encodings are longer and some i16 instructions are slow.
15663 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
15664 if (!isTypeLegal(VT))
15666 if (VT != MVT::i16)
15673 case ISD::SIGN_EXTEND:
15674 case ISD::ZERO_EXTEND:
15675 case ISD::ANY_EXTEND:
15688 /// IsDesirableToPromoteOp - This method query the target whether it is
15689 /// beneficial for dag combiner to promote the specified node. If true, it
15690 /// should return the desired promotion type by reference.
15691 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
15692 EVT VT = Op.getValueType();
15693 if (VT != MVT::i16)
15696 bool Promote = false;
15697 bool Commute = false;
15698 switch (Op.getOpcode()) {
15701 LoadSDNode *LD = cast<LoadSDNode>(Op);
15702 // If the non-extending load has a single use and it's not live out, then it
15703 // might be folded.
15704 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
15705 Op.hasOneUse()*/) {
15706 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
15707 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
15708 // The only case where we'd want to promote LOAD (rather then it being
15709 // promoted as an operand is when it's only use is liveout.
15710 if (UI->getOpcode() != ISD::CopyToReg)
15717 case ISD::SIGN_EXTEND:
15718 case ISD::ZERO_EXTEND:
15719 case ISD::ANY_EXTEND:
15724 SDValue N0 = Op.getOperand(0);
15725 // Look out for (store (shl (load), x)).
15726 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
15739 SDValue N0 = Op.getOperand(0);
15740 SDValue N1 = Op.getOperand(1);
15741 if (!Commute && MayFoldLoad(N1))
15743 // Avoid disabling potential load folding opportunities.
15744 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
15746 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
15756 //===----------------------------------------------------------------------===//
15757 // X86 Inline Assembly Support
15758 //===----------------------------------------------------------------------===//
15761 // Helper to match a string separated by whitespace.
15762 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
15763 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
15765 for (unsigned i = 0, e = args.size(); i != e; ++i) {
15766 StringRef piece(*args[i]);
15767 if (!s.startswith(piece)) // Check if the piece matches.
15770 s = s.substr(piece.size());
15771 StringRef::size_type pos = s.find_first_not_of(" \t");
15772 if (pos == 0) // We matched a prefix.
15780 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
15783 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
15784 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
15786 std::string AsmStr = IA->getAsmString();
15788 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
15789 if (!Ty || Ty->getBitWidth() % 16 != 0)
15792 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
15793 SmallVector<StringRef, 4> AsmPieces;
15794 SplitString(AsmStr, AsmPieces, ";\n");
15796 switch (AsmPieces.size()) {
15797 default: return false;
15799 // FIXME: this should verify that we are targeting a 486 or better. If not,
15800 // we will turn this bswap into something that will be lowered to logical
15801 // ops instead of emitting the bswap asm. For now, we don't support 486 or
15802 // lower so don't worry about this.
15804 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
15805 matchAsm(AsmPieces[0], "bswapl", "$0") ||
15806 matchAsm(AsmPieces[0], "bswapq", "$0") ||
15807 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
15808 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
15809 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
15810 // No need to check constraints, nothing other than the equivalent of
15811 // "=r,0" would be valid here.
15812 return IntrinsicLowering::LowerToByteSwap(CI);
15815 // rorw $$8, ${0:w} --> llvm.bswap.i16
15816 if (CI->getType()->isIntegerTy(16) &&
15817 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
15818 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
15819 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
15821 const std::string &ConstraintsStr = IA->getConstraintString();
15822 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
15823 std::sort(AsmPieces.begin(), AsmPieces.end());
15824 if (AsmPieces.size() == 4 &&
15825 AsmPieces[0] == "~{cc}" &&
15826 AsmPieces[1] == "~{dirflag}" &&
15827 AsmPieces[2] == "~{flags}" &&
15828 AsmPieces[3] == "~{fpsr}")
15829 return IntrinsicLowering::LowerToByteSwap(CI);
15833 if (CI->getType()->isIntegerTy(32) &&
15834 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
15835 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
15836 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
15837 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
15839 const std::string &ConstraintsStr = IA->getConstraintString();
15840 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
15841 std::sort(AsmPieces.begin(), AsmPieces.end());
15842 if (AsmPieces.size() == 4 &&
15843 AsmPieces[0] == "~{cc}" &&
15844 AsmPieces[1] == "~{dirflag}" &&
15845 AsmPieces[2] == "~{flags}" &&
15846 AsmPieces[3] == "~{fpsr}")
15847 return IntrinsicLowering::LowerToByteSwap(CI);
15850 if (CI->getType()->isIntegerTy(64)) {
15851 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
15852 if (Constraints.size() >= 2 &&
15853 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
15854 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
15855 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
15856 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
15857 matchAsm(AsmPieces[1], "bswap", "%edx") &&
15858 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
15859 return IntrinsicLowering::LowerToByteSwap(CI);
15869 /// getConstraintType - Given a constraint letter, return the type of
15870 /// constraint it is for this target.
15871 X86TargetLowering::ConstraintType
15872 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
15873 if (Constraint.size() == 1) {
15874 switch (Constraint[0]) {
15885 return C_RegisterClass;
15909 return TargetLowering::getConstraintType(Constraint);
15912 /// Examine constraint type and operand type and determine a weight value.
15913 /// This object must already have been set up with the operand type
15914 /// and the current alternative constraint selected.
15915 TargetLowering::ConstraintWeight
15916 X86TargetLowering::getSingleConstraintMatchWeight(
15917 AsmOperandInfo &info, const char *constraint) const {
15918 ConstraintWeight weight = CW_Invalid;
15919 Value *CallOperandVal = info.CallOperandVal;
15920 // If we don't have a value, we can't do a match,
15921 // but allow it at the lowest weight.
15922 if (CallOperandVal == NULL)
15924 Type *type = CallOperandVal->getType();
15925 // Look at the constraint type.
15926 switch (*constraint) {
15928 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
15939 if (CallOperandVal->getType()->isIntegerTy())
15940 weight = CW_SpecificReg;
15945 if (type->isFloatingPointTy())
15946 weight = CW_SpecificReg;
15949 if (type->isX86_MMXTy() && Subtarget->hasMMX())
15950 weight = CW_SpecificReg;
15954 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
15955 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasAVX()))
15956 weight = CW_Register;
15959 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
15960 if (C->getZExtValue() <= 31)
15961 weight = CW_Constant;
15965 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15966 if (C->getZExtValue() <= 63)
15967 weight = CW_Constant;
15971 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15972 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
15973 weight = CW_Constant;
15977 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15978 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
15979 weight = CW_Constant;
15983 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15984 if (C->getZExtValue() <= 3)
15985 weight = CW_Constant;
15989 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15990 if (C->getZExtValue() <= 0xff)
15991 weight = CW_Constant;
15996 if (dyn_cast<ConstantFP>(CallOperandVal)) {
15997 weight = CW_Constant;
16001 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
16002 if ((C->getSExtValue() >= -0x80000000LL) &&
16003 (C->getSExtValue() <= 0x7fffffffLL))
16004 weight = CW_Constant;
16008 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
16009 if (C->getZExtValue() <= 0xffffffff)
16010 weight = CW_Constant;
16017 /// LowerXConstraint - try to replace an X constraint, which matches anything,
16018 /// with another that has more specific requirements based on the type of the
16019 /// corresponding operand.
16020 const char *X86TargetLowering::
16021 LowerXConstraint(EVT ConstraintVT) const {
16022 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
16023 // 'f' like normal targets.
16024 if (ConstraintVT.isFloatingPoint()) {
16025 if (Subtarget->hasSSE2())
16027 if (Subtarget->hasSSE1())
16031 return TargetLowering::LowerXConstraint(ConstraintVT);
16034 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
16035 /// vector. If it is invalid, don't add anything to Ops.
16036 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
16037 std::string &Constraint,
16038 std::vector<SDValue>&Ops,
16039 SelectionDAG &DAG) const {
16040 SDValue Result(0, 0);
16042 // Only support length 1 constraints for now.
16043 if (Constraint.length() > 1) return;
16045 char ConstraintLetter = Constraint[0];
16046 switch (ConstraintLetter) {
16049 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
16050 if (C->getZExtValue() <= 31) {
16051 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
16057 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
16058 if (C->getZExtValue() <= 63) {
16059 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
16065 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
16066 if ((int8_t)C->getSExtValue() == C->getSExtValue()) {
16067 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
16073 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
16074 if (C->getZExtValue() <= 255) {
16075 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
16081 // 32-bit signed value
16082 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
16083 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
16084 C->getSExtValue())) {
16085 // Widen to 64 bits here to get it sign extended.
16086 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
16089 // FIXME gcc accepts some relocatable values here too, but only in certain
16090 // memory models; it's complicated.
16095 // 32-bit unsigned value
16096 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
16097 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
16098 C->getZExtValue())) {
16099 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
16103 // FIXME gcc accepts some relocatable values here too, but only in certain
16104 // memory models; it's complicated.
16108 // Literal immediates are always ok.
16109 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
16110 // Widen to 64 bits here to get it sign extended.
16111 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
16115 // In any sort of PIC mode addresses need to be computed at runtime by
16116 // adding in a register or some sort of table lookup. These can't
16117 // be used as immediates.
16118 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
16121 // If we are in non-pic codegen mode, we allow the address of a global (with
16122 // an optional displacement) to be used with 'i'.
16123 GlobalAddressSDNode *GA = 0;
16124 int64_t Offset = 0;
16126 // Match either (GA), (GA+C), (GA+C1+C2), etc.
16128 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
16129 Offset += GA->getOffset();
16131 } else if (Op.getOpcode() == ISD::ADD) {
16132 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
16133 Offset += C->getZExtValue();
16134 Op = Op.getOperand(0);
16137 } else if (Op.getOpcode() == ISD::SUB) {
16138 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
16139 Offset += -C->getZExtValue();
16140 Op = Op.getOperand(0);
16145 // Otherwise, this isn't something we can handle, reject it.
16149 const GlobalValue *GV = GA->getGlobal();
16150 // If we require an extra load to get this address, as in PIC mode, we
16151 // can't accept it.
16152 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
16153 getTargetMachine())))
16156 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(),
16157 GA->getValueType(0), Offset);
16162 if (Result.getNode()) {
16163 Ops.push_back(Result);
16166 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
16169 std::pair<unsigned, const TargetRegisterClass*>
16170 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
16172 // First, see if this is a constraint that directly corresponds to an LLVM
16174 if (Constraint.size() == 1) {
16175 // GCC Constraint Letters
16176 switch (Constraint[0]) {
16178 // TODO: Slight differences here in allocation order and leaving
16179 // RIP in the class. Do they matter any more here than they do
16180 // in the normal allocation?
16181 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
16182 if (Subtarget->is64Bit()) {
16183 if (VT == MVT::i32 || VT == MVT::f32)
16184 return std::make_pair(0U, &X86::GR32RegClass);
16185 if (VT == MVT::i16)
16186 return std::make_pair(0U, &X86::GR16RegClass);
16187 if (VT == MVT::i8 || VT == MVT::i1)
16188 return std::make_pair(0U, &X86::GR8RegClass);
16189 if (VT == MVT::i64 || VT == MVT::f64)
16190 return std::make_pair(0U, &X86::GR64RegClass);
16193 // 32-bit fallthrough
16194 case 'Q': // Q_REGS
16195 if (VT == MVT::i32 || VT == MVT::f32)
16196 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
16197 if (VT == MVT::i16)
16198 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
16199 if (VT == MVT::i8 || VT == MVT::i1)
16200 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
16201 if (VT == MVT::i64)
16202 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
16204 case 'r': // GENERAL_REGS
16205 case 'l': // INDEX_REGS
16206 if (VT == MVT::i8 || VT == MVT::i1)
16207 return std::make_pair(0U, &X86::GR8RegClass);
16208 if (VT == MVT::i16)
16209 return std::make_pair(0U, &X86::GR16RegClass);
16210 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
16211 return std::make_pair(0U, &X86::GR32RegClass);
16212 return std::make_pair(0U, &X86::GR64RegClass);
16213 case 'R': // LEGACY_REGS
16214 if (VT == MVT::i8 || VT == MVT::i1)
16215 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
16216 if (VT == MVT::i16)
16217 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
16218 if (VT == MVT::i32 || !Subtarget->is64Bit())
16219 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
16220 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
16221 case 'f': // FP Stack registers.
16222 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
16223 // value to the correct fpstack register class.
16224 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
16225 return std::make_pair(0U, &X86::RFP32RegClass);
16226 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
16227 return std::make_pair(0U, &X86::RFP64RegClass);
16228 return std::make_pair(0U, &X86::RFP80RegClass);
16229 case 'y': // MMX_REGS if MMX allowed.
16230 if (!Subtarget->hasMMX()) break;
16231 return std::make_pair(0U, &X86::VR64RegClass);
16232 case 'Y': // SSE_REGS if SSE2 allowed
16233 if (!Subtarget->hasSSE2()) break;
16235 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
16236 if (!Subtarget->hasSSE1()) break;
16238 switch (VT.getSimpleVT().SimpleTy) {
16240 // Scalar SSE types.
16243 return std::make_pair(0U, &X86::FR32RegClass);
16246 return std::make_pair(0U, &X86::FR64RegClass);
16254 return std::make_pair(0U, &X86::VR128RegClass);
16262 return std::make_pair(0U, &X86::VR256RegClass);
16268 // Use the default implementation in TargetLowering to convert the register
16269 // constraint into a member of a register class.
16270 std::pair<unsigned, const TargetRegisterClass*> Res;
16271 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
16273 // Not found as a standard register?
16274 if (Res.second == 0) {
16275 // Map st(0) -> st(7) -> ST0
16276 if (Constraint.size() == 7 && Constraint[0] == '{' &&
16277 tolower(Constraint[1]) == 's' &&
16278 tolower(Constraint[2]) == 't' &&
16279 Constraint[3] == '(' &&
16280 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
16281 Constraint[5] == ')' &&
16282 Constraint[6] == '}') {
16284 Res.first = X86::ST0+Constraint[4]-'0';
16285 Res.second = &X86::RFP80RegClass;
16289 // GCC allows "st(0)" to be called just plain "st".
16290 if (StringRef("{st}").equals_lower(Constraint)) {
16291 Res.first = X86::ST0;
16292 Res.second = &X86::RFP80RegClass;
16297 if (StringRef("{flags}").equals_lower(Constraint)) {
16298 Res.first = X86::EFLAGS;
16299 Res.second = &X86::CCRRegClass;
16303 // 'A' means EAX + EDX.
16304 if (Constraint == "A") {
16305 Res.first = X86::EAX;
16306 Res.second = &X86::GR32_ADRegClass;
16312 // Otherwise, check to see if this is a register class of the wrong value
16313 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
16314 // turn into {ax},{dx}.
16315 if (Res.second->hasType(VT))
16316 return Res; // Correct type already, nothing to do.
16318 // All of the single-register GCC register classes map their values onto
16319 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
16320 // really want an 8-bit or 32-bit register, map to the appropriate register
16321 // class and return the appropriate register.
16322 if (Res.second == &X86::GR16RegClass) {
16323 if (VT == MVT::i8) {
16324 unsigned DestReg = 0;
16325 switch (Res.first) {
16327 case X86::AX: DestReg = X86::AL; break;
16328 case X86::DX: DestReg = X86::DL; break;
16329 case X86::CX: DestReg = X86::CL; break;
16330 case X86::BX: DestReg = X86::BL; break;
16333 Res.first = DestReg;
16334 Res.second = &X86::GR8RegClass;
16336 } else if (VT == MVT::i32) {
16337 unsigned DestReg = 0;
16338 switch (Res.first) {
16340 case X86::AX: DestReg = X86::EAX; break;
16341 case X86::DX: DestReg = X86::EDX; break;
16342 case X86::CX: DestReg = X86::ECX; break;
16343 case X86::BX: DestReg = X86::EBX; break;
16344 case X86::SI: DestReg = X86::ESI; break;
16345 case X86::DI: DestReg = X86::EDI; break;
16346 case X86::BP: DestReg = X86::EBP; break;
16347 case X86::SP: DestReg = X86::ESP; break;
16350 Res.first = DestReg;
16351 Res.second = &X86::GR32RegClass;
16353 } else if (VT == MVT::i64) {
16354 unsigned DestReg = 0;
16355 switch (Res.first) {
16357 case X86::AX: DestReg = X86::RAX; break;
16358 case X86::DX: DestReg = X86::RDX; break;
16359 case X86::CX: DestReg = X86::RCX; break;
16360 case X86::BX: DestReg = X86::RBX; break;
16361 case X86::SI: DestReg = X86::RSI; break;
16362 case X86::DI: DestReg = X86::RDI; break;
16363 case X86::BP: DestReg = X86::RBP; break;
16364 case X86::SP: DestReg = X86::RSP; break;
16367 Res.first = DestReg;
16368 Res.second = &X86::GR64RegClass;
16371 } else if (Res.second == &X86::FR32RegClass ||
16372 Res.second == &X86::FR64RegClass ||
16373 Res.second == &X86::VR128RegClass) {
16374 // Handle references to XMM physical registers that got mapped into the
16375 // wrong class. This can happen with constraints like {xmm0} where the
16376 // target independent register mapper will just pick the first match it can
16377 // find, ignoring the required type.
16379 if (VT == MVT::f32 || VT == MVT::i32)
16380 Res.second = &X86::FR32RegClass;
16381 else if (VT == MVT::f64 || VT == MVT::i64)
16382 Res.second = &X86::FR64RegClass;
16383 else if (X86::VR128RegClass.hasType(VT))
16384 Res.second = &X86::VR128RegClass;
16385 else if (X86::VR256RegClass.hasType(VT))
16386 Res.second = &X86::VR256RegClass;