1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
16 #include "X86ISelLowering.h"
17 #include "Utils/X86ShuffleDecode.h"
19 #include "X86CallingConv.h"
20 #include "X86InstrBuilder.h"
21 #include "X86TargetMachine.h"
22 #include "X86TargetObjectFile.h"
23 #include "llvm/ADT/SmallSet.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/VariadicFunction.h"
27 #include "llvm/CodeGen/IntrinsicLowering.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/IR/CallingConv.h"
35 #include "llvm/IR/Constants.h"
36 #include "llvm/IR/DerivedTypes.h"
37 #include "llvm/IR/Function.h"
38 #include "llvm/IR/GlobalAlias.h"
39 #include "llvm/IR/GlobalVariable.h"
40 #include "llvm/IR/Instructions.h"
41 #include "llvm/IR/Intrinsics.h"
42 #include "llvm/IR/LLVMContext.h"
43 #include "llvm/MC/MCAsmInfo.h"
44 #include "llvm/MC/MCContext.h"
45 #include "llvm/MC/MCExpr.h"
46 #include "llvm/MC/MCSymbol.h"
47 #include "llvm/Support/CallSite.h"
48 #include "llvm/Support/Debug.h"
49 #include "llvm/Support/ErrorHandling.h"
50 #include "llvm/Support/MathExtras.h"
51 #include "llvm/Target/TargetOptions.h"
56 STATISTIC(NumTailCalls, "Number of tail calls");
58 // Forward declarations.
59 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
62 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
63 SelectionDAG &DAG, SDLoc dl,
64 unsigned vectorWidth) {
65 assert((vectorWidth == 128 || vectorWidth == 256) &&
66 "Unsupported vector width");
67 EVT VT = Vec.getValueType();
68 EVT ElVT = VT.getVectorElementType();
69 unsigned Factor = VT.getSizeInBits()/vectorWidth;
70 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
71 VT.getVectorNumElements()/Factor);
73 // Extract from UNDEF is UNDEF.
74 if (Vec.getOpcode() == ISD::UNDEF)
75 return DAG.getUNDEF(ResultVT);
77 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
78 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
80 // This is the index of the first element of the vectorWidth-bit chunk
82 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
85 // If the input is a buildvector just emit a smaller one.
86 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
87 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
88 Vec->op_begin()+NormalizedIdxVal, ElemsPerChunk);
90 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
91 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
97 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
98 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
99 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
100 /// instructions or a simple subregister reference. Idx is an index in the
101 /// 128 bits we want. It need not be aligned to a 128-bit bounday. That makes
102 /// lowering EXTRACT_VECTOR_ELT operations easier.
103 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
104 SelectionDAG &DAG, SDLoc dl) {
105 assert((Vec.getValueType().is256BitVector() ||
106 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
107 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
110 /// Generate a DAG to grab 256-bits from a 512-bit vector.
111 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
112 SelectionDAG &DAG, SDLoc dl) {
113 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
114 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
117 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
118 unsigned IdxVal, SelectionDAG &DAG,
119 SDLoc dl, unsigned vectorWidth) {
120 assert((vectorWidth == 128 || vectorWidth == 256) &&
121 "Unsupported vector width");
122 // Inserting UNDEF is Result
123 if (Vec.getOpcode() == ISD::UNDEF)
125 EVT VT = Vec.getValueType();
126 EVT ElVT = VT.getVectorElementType();
127 EVT ResultVT = Result.getValueType();
129 // Insert the relevant vectorWidth bits.
130 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
132 // This is the index of the first element of the vectorWidth-bit chunk
134 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
137 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
138 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
141 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
142 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
143 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
144 /// simple superregister reference. Idx is an index in the 128 bits
145 /// we want. It need not be aligned to a 128-bit bounday. That makes
146 /// lowering INSERT_VECTOR_ELT operations easier.
147 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
148 unsigned IdxVal, SelectionDAG &DAG,
150 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
151 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
154 static SDValue Insert256BitVector(SDValue Result, SDValue Vec,
155 unsigned IdxVal, SelectionDAG &DAG,
157 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
158 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
161 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
162 /// instructions. This is used because creating CONCAT_VECTOR nodes of
163 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
164 /// large BUILD_VECTORS.
165 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
166 unsigned NumElems, SelectionDAG &DAG,
168 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
169 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
172 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
173 unsigned NumElems, SelectionDAG &DAG,
175 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
176 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
179 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
180 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
181 bool is64Bit = Subtarget->is64Bit();
183 if (Subtarget->isTargetMacho()) {
185 return new X86_64MachoTargetObjectFile();
186 return new TargetLoweringObjectFileMachO();
189 if (Subtarget->isTargetLinux())
190 return new X86LinuxTargetObjectFile();
191 if (Subtarget->isTargetELF())
192 return new TargetLoweringObjectFileELF();
193 if (Subtarget->isTargetCOFF())
194 return new TargetLoweringObjectFileCOFF();
195 llvm_unreachable("unknown subtarget type");
198 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
199 : TargetLowering(TM, createTLOF(TM)) {
200 Subtarget = &TM.getSubtarget<X86Subtarget>();
201 X86ScalarSSEf64 = Subtarget->hasSSE2();
202 X86ScalarSSEf32 = Subtarget->hasSSE1();
203 TD = getDataLayout();
205 resetOperationActions();
208 void X86TargetLowering::resetOperationActions() {
209 const TargetMachine &TM = getTargetMachine();
210 static bool FirstTimeThrough = true;
212 // If none of the target options have changed, then we don't need to reset the
213 // operation actions.
214 if (!FirstTimeThrough && TO == TM.Options) return;
216 if (!FirstTimeThrough) {
217 // Reinitialize the actions.
219 FirstTimeThrough = false;
224 // Set up the TargetLowering object.
225 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
227 // X86 is weird, it always uses i8 for shift amounts and setcc results.
228 setBooleanContents(ZeroOrOneBooleanContent);
229 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
230 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
232 // For 64-bit since we have so many registers use the ILP scheduler, for
233 // 32-bit code use the register pressure specific scheduling.
234 // For Atom, always use ILP scheduling.
235 if (Subtarget->isAtom())
236 setSchedulingPreference(Sched::ILP);
237 else if (Subtarget->is64Bit())
238 setSchedulingPreference(Sched::ILP);
240 setSchedulingPreference(Sched::RegPressure);
241 const X86RegisterInfo *RegInfo =
242 static_cast<const X86RegisterInfo*>(TM.getRegisterInfo());
243 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
245 // Bypass expensive divides on Atom when compiling with O2
246 if (Subtarget->hasSlowDivide() && TM.getOptLevel() >= CodeGenOpt::Default) {
247 addBypassSlowDiv(32, 8);
248 if (Subtarget->is64Bit())
249 addBypassSlowDiv(64, 16);
252 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) {
253 // Setup Windows compiler runtime calls.
254 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
255 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
256 setLibcallName(RTLIB::SREM_I64, "_allrem");
257 setLibcallName(RTLIB::UREM_I64, "_aullrem");
258 setLibcallName(RTLIB::MUL_I64, "_allmul");
259 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
260 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
261 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
262 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
263 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
265 // The _ftol2 runtime function has an unusual calling conv, which
266 // is modeled by a special pseudo-instruction.
267 setLibcallName(RTLIB::FPTOUINT_F64_I64, 0);
268 setLibcallName(RTLIB::FPTOUINT_F32_I64, 0);
269 setLibcallName(RTLIB::FPTOUINT_F64_I32, 0);
270 setLibcallName(RTLIB::FPTOUINT_F32_I32, 0);
273 if (Subtarget->isTargetDarwin()) {
274 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
275 setUseUnderscoreSetJmp(false);
276 setUseUnderscoreLongJmp(false);
277 } else if (Subtarget->isTargetMingw()) {
278 // MS runtime is weird: it exports _setjmp, but longjmp!
279 setUseUnderscoreSetJmp(true);
280 setUseUnderscoreLongJmp(false);
282 setUseUnderscoreSetJmp(true);
283 setUseUnderscoreLongJmp(true);
286 // Set up the register classes.
287 addRegisterClass(MVT::i8, &X86::GR8RegClass);
288 addRegisterClass(MVT::i16, &X86::GR16RegClass);
289 addRegisterClass(MVT::i32, &X86::GR32RegClass);
290 if (Subtarget->is64Bit())
291 addRegisterClass(MVT::i64, &X86::GR64RegClass);
293 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
295 // We don't accept any truncstore of integer registers.
296 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
297 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
298 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
299 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
300 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
301 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
303 // SETOEQ and SETUNE require checking two conditions.
304 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
305 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
306 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
307 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
308 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
309 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
311 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
313 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
314 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
315 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
317 if (Subtarget->is64Bit()) {
318 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
319 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
320 } else if (!TM.Options.UseSoftFloat) {
321 // We have an algorithm for SSE2->double, and we turn this into a
322 // 64-bit FILD followed by conditional FADD for other targets.
323 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
324 // We have an algorithm for SSE2, and we turn this into a 64-bit
325 // FILD for other targets.
326 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
329 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
331 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
332 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
334 if (!TM.Options.UseSoftFloat) {
335 // SSE has no i16 to fp conversion, only i32
336 if (X86ScalarSSEf32) {
337 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
338 // f32 and f64 cases are Legal, f80 case is not
339 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
341 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
342 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
345 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
346 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
349 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
350 // are Legal, f80 is custom lowered.
351 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
352 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
354 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
356 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
357 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
359 if (X86ScalarSSEf32) {
360 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
361 // f32 and f64 cases are Legal, f80 case is not
362 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
364 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
365 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
368 // Handle FP_TO_UINT by promoting the destination to a larger signed
370 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
371 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
372 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
374 if (Subtarget->is64Bit()) {
375 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
376 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
377 } else if (!TM.Options.UseSoftFloat) {
378 // Since AVX is a superset of SSE3, only check for SSE here.
379 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
380 // Expand FP_TO_UINT into a select.
381 // FIXME: We would like to use a Custom expander here eventually to do
382 // the optimal thing for SSE vs. the default expansion in the legalizer.
383 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
385 // With SSE3 we can use fisttpll to convert to a signed i64; without
386 // SSE, we're stuck with a fistpll.
387 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
390 if (isTargetFTOL()) {
391 // Use the _ftol2 runtime function, which has a pseudo-instruction
392 // to handle its weird calling convention.
393 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
396 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
397 if (!X86ScalarSSEf64) {
398 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
399 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
400 if (Subtarget->is64Bit()) {
401 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
402 // Without SSE, i64->f64 goes through memory.
403 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
407 // Scalar integer divide and remainder are lowered to use operations that
408 // produce two results, to match the available instructions. This exposes
409 // the two-result form to trivial CSE, which is able to combine x/y and x%y
410 // into a single instruction.
412 // Scalar integer multiply-high is also lowered to use two-result
413 // operations, to match the available instructions. However, plain multiply
414 // (low) operations are left as Legal, as there are single-result
415 // instructions for this in x86. Using the two-result multiply instructions
416 // when both high and low results are needed must be arranged by dagcombine.
417 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
419 setOperationAction(ISD::MULHS, VT, Expand);
420 setOperationAction(ISD::MULHU, VT, Expand);
421 setOperationAction(ISD::SDIV, VT, Expand);
422 setOperationAction(ISD::UDIV, VT, Expand);
423 setOperationAction(ISD::SREM, VT, Expand);
424 setOperationAction(ISD::UREM, VT, Expand);
426 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
427 setOperationAction(ISD::ADDC, VT, Custom);
428 setOperationAction(ISD::ADDE, VT, Custom);
429 setOperationAction(ISD::SUBC, VT, Custom);
430 setOperationAction(ISD::SUBE, VT, Custom);
433 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
434 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
435 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
436 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
437 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
438 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
439 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
440 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
441 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
442 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
443 if (Subtarget->is64Bit())
444 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
445 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
446 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
447 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
448 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
449 setOperationAction(ISD::FREM , MVT::f32 , Expand);
450 setOperationAction(ISD::FREM , MVT::f64 , Expand);
451 setOperationAction(ISD::FREM , MVT::f80 , Expand);
452 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
454 // Promote the i8 variants and force them on up to i32 which has a shorter
456 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
457 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
458 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
459 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
460 if (Subtarget->hasBMI()) {
461 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
462 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
463 if (Subtarget->is64Bit())
464 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
466 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
467 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
468 if (Subtarget->is64Bit())
469 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
472 if (Subtarget->hasLZCNT()) {
473 // When promoting the i8 variants, force them to i32 for a shorter
475 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
476 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
477 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
478 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
479 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
480 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
481 if (Subtarget->is64Bit())
482 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
484 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
485 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
486 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
487 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
488 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
489 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
490 if (Subtarget->is64Bit()) {
491 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
492 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
496 if (Subtarget->hasPOPCNT()) {
497 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
499 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
500 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
501 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
502 if (Subtarget->is64Bit())
503 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
506 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
507 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
509 // These should be promoted to a larger select which is supported.
510 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
511 // X86 wants to expand cmov itself.
512 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
513 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
514 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
515 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
516 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
517 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
518 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
519 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
520 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
521 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
522 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
523 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
524 if (Subtarget->is64Bit()) {
525 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
526 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
528 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
529 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
530 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
531 // support continuation, user-level threading, and etc.. As a result, no
532 // other SjLj exception interfaces are implemented and please don't build
533 // your own exception handling based on them.
534 // LLVM/Clang supports zero-cost DWARF exception handling.
535 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
536 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
539 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
540 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
541 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
542 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
543 if (Subtarget->is64Bit())
544 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
545 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
546 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
547 if (Subtarget->is64Bit()) {
548 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
549 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
550 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
551 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
552 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
554 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
555 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
556 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
557 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
558 if (Subtarget->is64Bit()) {
559 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
560 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
561 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
564 if (Subtarget->hasSSE1())
565 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
567 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
569 // Expand certain atomics
570 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
572 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom);
573 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
574 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
577 if (!Subtarget->is64Bit()) {
578 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
579 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
580 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
581 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
582 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
583 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
584 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
585 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
586 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i64, Custom);
587 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i64, Custom);
588 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i64, Custom);
589 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i64, Custom);
592 if (Subtarget->hasCmpxchg16b()) {
593 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom);
596 // FIXME - use subtarget debug flags
597 if (!Subtarget->isTargetDarwin() &&
598 !Subtarget->isTargetELF() &&
599 !Subtarget->isTargetCygMing()) {
600 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
603 if (Subtarget->is64Bit()) {
604 setExceptionPointerRegister(X86::RAX);
605 setExceptionSelectorRegister(X86::RDX);
607 setExceptionPointerRegister(X86::EAX);
608 setExceptionSelectorRegister(X86::EDX);
610 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
611 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
613 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
614 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
616 setOperationAction(ISD::TRAP, MVT::Other, Legal);
617 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
619 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
620 setOperationAction(ISD::VASTART , MVT::Other, Custom);
621 setOperationAction(ISD::VAEND , MVT::Other, Expand);
622 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
623 // TargetInfo::X86_64ABIBuiltinVaList
624 setOperationAction(ISD::VAARG , MVT::Other, Custom);
625 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
627 // TargetInfo::CharPtrBuiltinVaList
628 setOperationAction(ISD::VAARG , MVT::Other, Expand);
629 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
632 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
633 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
635 if (Subtarget->isOSWindows() && !Subtarget->isTargetMacho())
636 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
637 MVT::i64 : MVT::i32, Custom);
638 else if (TM.Options.EnableSegmentedStacks)
639 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
640 MVT::i64 : MVT::i32, Custom);
642 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
643 MVT::i64 : MVT::i32, Expand);
645 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
646 // f32 and f64 use SSE.
647 // Set up the FP register classes.
648 addRegisterClass(MVT::f32, &X86::FR32RegClass);
649 addRegisterClass(MVT::f64, &X86::FR64RegClass);
651 // Use ANDPD to simulate FABS.
652 setOperationAction(ISD::FABS , MVT::f64, Custom);
653 setOperationAction(ISD::FABS , MVT::f32, Custom);
655 // Use XORP to simulate FNEG.
656 setOperationAction(ISD::FNEG , MVT::f64, Custom);
657 setOperationAction(ISD::FNEG , MVT::f32, Custom);
659 // Use ANDPD and ORPD to simulate FCOPYSIGN.
660 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
661 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
663 // Lower this to FGETSIGNx86 plus an AND.
664 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
665 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
667 // We don't support sin/cos/fmod
668 setOperationAction(ISD::FSIN , MVT::f64, Expand);
669 setOperationAction(ISD::FCOS , MVT::f64, Expand);
670 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
671 setOperationAction(ISD::FSIN , MVT::f32, Expand);
672 setOperationAction(ISD::FCOS , MVT::f32, Expand);
673 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
675 // Expand FP immediates into loads from the stack, except for the special
677 addLegalFPImmediate(APFloat(+0.0)); // xorpd
678 addLegalFPImmediate(APFloat(+0.0f)); // xorps
679 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
680 // Use SSE for f32, x87 for f64.
681 // Set up the FP register classes.
682 addRegisterClass(MVT::f32, &X86::FR32RegClass);
683 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
685 // Use ANDPS to simulate FABS.
686 setOperationAction(ISD::FABS , MVT::f32, Custom);
688 // Use XORP to simulate FNEG.
689 setOperationAction(ISD::FNEG , MVT::f32, Custom);
691 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
693 // Use ANDPS and ORPS to simulate FCOPYSIGN.
694 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
695 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
697 // We don't support sin/cos/fmod
698 setOperationAction(ISD::FSIN , MVT::f32, Expand);
699 setOperationAction(ISD::FCOS , MVT::f32, Expand);
700 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
702 // Special cases we handle for FP constants.
703 addLegalFPImmediate(APFloat(+0.0f)); // xorps
704 addLegalFPImmediate(APFloat(+0.0)); // FLD0
705 addLegalFPImmediate(APFloat(+1.0)); // FLD1
706 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
707 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
709 if (!TM.Options.UnsafeFPMath) {
710 setOperationAction(ISD::FSIN , MVT::f64, Expand);
711 setOperationAction(ISD::FCOS , MVT::f64, Expand);
712 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
714 } else if (!TM.Options.UseSoftFloat) {
715 // f32 and f64 in x87.
716 // Set up the FP register classes.
717 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
718 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
720 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
721 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
722 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
723 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
725 if (!TM.Options.UnsafeFPMath) {
726 setOperationAction(ISD::FSIN , MVT::f64, Expand);
727 setOperationAction(ISD::FSIN , MVT::f32, Expand);
728 setOperationAction(ISD::FCOS , MVT::f64, Expand);
729 setOperationAction(ISD::FCOS , MVT::f32, Expand);
730 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
731 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
733 addLegalFPImmediate(APFloat(+0.0)); // FLD0
734 addLegalFPImmediate(APFloat(+1.0)); // FLD1
735 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
736 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
737 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
738 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
739 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
740 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
743 // We don't support FMA.
744 setOperationAction(ISD::FMA, MVT::f64, Expand);
745 setOperationAction(ISD::FMA, MVT::f32, Expand);
747 // Long double always uses X87.
748 if (!TM.Options.UseSoftFloat) {
749 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
750 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
751 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
753 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
754 addLegalFPImmediate(TmpFlt); // FLD0
756 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
759 APFloat TmpFlt2(+1.0);
760 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
762 addLegalFPImmediate(TmpFlt2); // FLD1
763 TmpFlt2.changeSign();
764 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
767 if (!TM.Options.UnsafeFPMath) {
768 setOperationAction(ISD::FSIN , MVT::f80, Expand);
769 setOperationAction(ISD::FCOS , MVT::f80, Expand);
770 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
773 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
774 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
775 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
776 setOperationAction(ISD::FRINT, MVT::f80, Expand);
777 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
778 setOperationAction(ISD::FMA, MVT::f80, Expand);
781 // Always use a library call for pow.
782 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
783 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
784 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
786 setOperationAction(ISD::FLOG, MVT::f80, Expand);
787 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
788 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
789 setOperationAction(ISD::FEXP, MVT::f80, Expand);
790 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
792 // First set operation action for all vector types to either promote
793 // (for widening) or expand (for scalarization). Then we will selectively
794 // turn on ones that can be effectively codegen'd.
795 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
796 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
797 MVT VT = (MVT::SimpleValueType)i;
798 setOperationAction(ISD::ADD , VT, Expand);
799 setOperationAction(ISD::SUB , VT, Expand);
800 setOperationAction(ISD::FADD, VT, Expand);
801 setOperationAction(ISD::FNEG, VT, Expand);
802 setOperationAction(ISD::FSUB, VT, Expand);
803 setOperationAction(ISD::MUL , VT, Expand);
804 setOperationAction(ISD::FMUL, VT, Expand);
805 setOperationAction(ISD::SDIV, VT, Expand);
806 setOperationAction(ISD::UDIV, VT, Expand);
807 setOperationAction(ISD::FDIV, VT, Expand);
808 setOperationAction(ISD::SREM, VT, Expand);
809 setOperationAction(ISD::UREM, VT, Expand);
810 setOperationAction(ISD::LOAD, VT, Expand);
811 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
812 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
813 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
814 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
815 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
816 setOperationAction(ISD::FABS, VT, Expand);
817 setOperationAction(ISD::FSIN, VT, Expand);
818 setOperationAction(ISD::FSINCOS, VT, Expand);
819 setOperationAction(ISD::FCOS, VT, Expand);
820 setOperationAction(ISD::FSINCOS, VT, Expand);
821 setOperationAction(ISD::FREM, VT, Expand);
822 setOperationAction(ISD::FMA, VT, Expand);
823 setOperationAction(ISD::FPOWI, VT, Expand);
824 setOperationAction(ISD::FSQRT, VT, Expand);
825 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
826 setOperationAction(ISD::FFLOOR, VT, Expand);
827 setOperationAction(ISD::FCEIL, VT, Expand);
828 setOperationAction(ISD::FTRUNC, VT, Expand);
829 setOperationAction(ISD::FRINT, VT, Expand);
830 setOperationAction(ISD::FNEARBYINT, VT, Expand);
831 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
832 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
833 setOperationAction(ISD::SDIVREM, VT, Expand);
834 setOperationAction(ISD::UDIVREM, VT, Expand);
835 setOperationAction(ISD::FPOW, VT, Expand);
836 setOperationAction(ISD::CTPOP, VT, Expand);
837 setOperationAction(ISD::CTTZ, VT, Expand);
838 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
839 setOperationAction(ISD::CTLZ, VT, Expand);
840 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
841 setOperationAction(ISD::SHL, VT, Expand);
842 setOperationAction(ISD::SRA, VT, Expand);
843 setOperationAction(ISD::SRL, VT, Expand);
844 setOperationAction(ISD::ROTL, VT, Expand);
845 setOperationAction(ISD::ROTR, VT, Expand);
846 setOperationAction(ISD::BSWAP, VT, Expand);
847 setOperationAction(ISD::SETCC, VT, Expand);
848 setOperationAction(ISD::FLOG, VT, Expand);
849 setOperationAction(ISD::FLOG2, VT, Expand);
850 setOperationAction(ISD::FLOG10, VT, Expand);
851 setOperationAction(ISD::FEXP, VT, Expand);
852 setOperationAction(ISD::FEXP2, VT, Expand);
853 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
854 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
855 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
856 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
857 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
858 setOperationAction(ISD::TRUNCATE, VT, Expand);
859 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
860 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
861 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
862 setOperationAction(ISD::VSELECT, VT, Expand);
863 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
864 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
865 setTruncStoreAction(VT,
866 (MVT::SimpleValueType)InnerVT, Expand);
867 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
868 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
869 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
872 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
873 // with -msoft-float, disable use of MMX as well.
874 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
875 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
876 // No operations on x86mmx supported, everything uses intrinsics.
879 // MMX-sized vectors (other than x86mmx) are expected to be expanded
880 // into smaller operations.
881 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
882 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
883 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
884 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
885 setOperationAction(ISD::AND, MVT::v8i8, Expand);
886 setOperationAction(ISD::AND, MVT::v4i16, Expand);
887 setOperationAction(ISD::AND, MVT::v2i32, Expand);
888 setOperationAction(ISD::AND, MVT::v1i64, Expand);
889 setOperationAction(ISD::OR, MVT::v8i8, Expand);
890 setOperationAction(ISD::OR, MVT::v4i16, Expand);
891 setOperationAction(ISD::OR, MVT::v2i32, Expand);
892 setOperationAction(ISD::OR, MVT::v1i64, Expand);
893 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
894 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
895 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
896 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
897 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
898 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
899 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
900 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
901 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
902 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
903 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
904 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
905 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
906 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
907 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
908 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
909 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
911 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
912 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
914 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
915 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
916 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
917 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
918 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
919 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
920 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
921 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
922 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
923 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
924 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
925 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
928 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
929 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
931 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
932 // registers cannot be used even for integer operations.
933 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
934 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
935 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
936 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
938 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
939 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
940 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
941 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
942 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
943 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
944 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
945 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
946 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
947 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
948 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
949 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
950 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
951 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
952 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
953 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
954 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
955 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
957 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
958 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
959 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
960 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
962 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
963 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
964 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
965 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
966 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
968 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
969 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
970 MVT VT = (MVT::SimpleValueType)i;
971 // Do not attempt to custom lower non-power-of-2 vectors
972 if (!isPowerOf2_32(VT.getVectorNumElements()))
974 // Do not attempt to custom lower non-128-bit vectors
975 if (!VT.is128BitVector())
977 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
978 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
979 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
982 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
983 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
984 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
985 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
986 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
987 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
989 if (Subtarget->is64Bit()) {
990 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
991 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
994 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
995 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
996 MVT VT = (MVT::SimpleValueType)i;
998 // Do not attempt to promote non-128-bit vectors
999 if (!VT.is128BitVector())
1002 setOperationAction(ISD::AND, VT, Promote);
1003 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1004 setOperationAction(ISD::OR, VT, Promote);
1005 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1006 setOperationAction(ISD::XOR, VT, Promote);
1007 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1008 setOperationAction(ISD::LOAD, VT, Promote);
1009 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1010 setOperationAction(ISD::SELECT, VT, Promote);
1011 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1014 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
1016 // Custom lower v2i64 and v2f64 selects.
1017 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1018 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1019 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1020 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1022 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1023 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1025 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1026 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1027 // As there is no 64-bit GPR available, we need build a special custom
1028 // sequence to convert from v2i32 to v2f32.
1029 if (!Subtarget->is64Bit())
1030 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1032 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1033 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1035 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
1038 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1039 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1040 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1041 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1042 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1043 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1044 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1045 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1046 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1047 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1048 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1050 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1051 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1052 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1053 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1054 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1055 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1056 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1057 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1058 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1059 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1061 // FIXME: Do we need to handle scalar-to-vector here?
1062 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1064 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
1065 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal);
1066 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1067 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
1068 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
1070 // i8 and i16 vectors are custom , because the source register and source
1071 // source memory operand types are not the same width. f32 vectors are
1072 // custom since the immediate controlling the insert encodes additional
1074 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1075 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1076 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1077 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1079 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1080 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1081 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1082 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1084 // FIXME: these should be Legal but thats only for the case where
1085 // the index is constant. For now custom expand to deal with that.
1086 if (Subtarget->is64Bit()) {
1087 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1088 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1092 if (Subtarget->hasSSE2()) {
1093 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1094 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1096 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1097 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1099 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1100 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1102 // In the customized shift lowering, the legal cases in AVX2 will be
1104 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1105 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1107 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1108 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1110 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1112 setOperationAction(ISD::SDIV, MVT::v8i16, Custom);
1113 setOperationAction(ISD::SDIV, MVT::v4i32, Custom);
1116 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1117 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1118 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1119 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1120 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1121 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1122 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1124 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1125 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1126 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1128 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1129 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1130 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1131 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1132 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1133 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1134 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1135 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1136 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1137 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1138 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1139 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1141 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1142 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1143 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1144 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1145 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1146 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1147 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1148 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1149 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1150 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1151 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1152 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1154 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Custom);
1156 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1157 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1158 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1159 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1161 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1162 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1164 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1166 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1167 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1169 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1170 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1172 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1173 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1175 setOperationAction(ISD::SDIV, MVT::v16i16, Custom);
1177 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1178 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1179 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1180 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1182 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1183 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1184 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1186 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal);
1187 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal);
1188 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal);
1189 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal);
1191 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1192 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1193 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1194 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1195 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1196 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1197 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1198 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1199 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1200 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1201 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1202 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1204 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1205 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1206 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1207 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1208 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1209 setOperationAction(ISD::FMA, MVT::f32, Legal);
1210 setOperationAction(ISD::FMA, MVT::f64, Legal);
1213 if (Subtarget->hasInt256()) {
1214 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1215 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1216 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1217 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1219 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1220 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1221 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1222 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1224 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1225 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1226 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1227 // Don't lower v32i8 because there is no 128-bit byte mul
1229 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1231 setOperationAction(ISD::SDIV, MVT::v8i32, Custom);
1233 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1234 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1235 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1236 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1238 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1239 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1240 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1241 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1243 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1244 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1245 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1246 // Don't lower v32i8 because there is no 128-bit byte mul
1249 // In the customized shift lowering, the legal cases in AVX2 will be
1251 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1252 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1254 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1255 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1257 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1259 // Custom lower several nodes for 256-bit types.
1260 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1261 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1262 MVT VT = (MVT::SimpleValueType)i;
1264 // Extract subvector is special because the value type
1265 // (result) is 128-bit but the source is 256-bit wide.
1266 if (VT.is128BitVector())
1267 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1269 // Do not attempt to custom lower other non-256-bit vectors
1270 if (!VT.is256BitVector())
1273 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1274 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1275 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1276 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1277 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1278 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1279 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1282 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1283 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1284 MVT VT = (MVT::SimpleValueType)i;
1286 // Do not attempt to promote non-256-bit vectors
1287 if (!VT.is256BitVector())
1290 setOperationAction(ISD::AND, VT, Promote);
1291 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1292 setOperationAction(ISD::OR, VT, Promote);
1293 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1294 setOperationAction(ISD::XOR, VT, Promote);
1295 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1296 setOperationAction(ISD::LOAD, VT, Promote);
1297 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1298 setOperationAction(ISD::SELECT, VT, Promote);
1299 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1303 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1304 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1305 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1306 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1307 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1309 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1310 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1311 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1313 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1314 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1315 setOperationAction(ISD::XOR, MVT::i1, Legal);
1316 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, Legal);
1317 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1318 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1319 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1320 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1321 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1323 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1324 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1325 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1326 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1327 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1328 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1330 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1331 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1332 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1333 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1334 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1335 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1336 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1337 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1338 setOperationAction(ISD::SDIV, MVT::v16i32, Custom);
1340 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1341 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1342 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1343 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1344 if (Subtarget->is64Bit()) {
1345 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1346 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1347 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1348 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1350 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1351 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1352 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1353 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1354 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1355 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1356 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1357 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1359 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1360 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1361 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1362 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1363 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1364 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1365 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1366 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1367 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1368 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1369 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1370 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1372 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1373 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1374 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1375 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1376 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1377 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1379 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1380 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1382 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1384 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1385 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1386 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1387 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1388 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1389 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1390 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1392 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1393 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1395 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1396 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1398 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1400 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1401 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1403 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1404 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1406 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1407 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1409 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1410 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1411 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1412 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1413 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1414 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1416 // Custom lower several nodes.
1417 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1418 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1419 MVT VT = (MVT::SimpleValueType)i;
1421 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1422 // Extract subvector is special because the value type
1423 // (result) is 256/128-bit but the source is 512-bit wide.
1424 if (VT.is128BitVector() || VT.is256BitVector())
1425 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1427 if (VT.getVectorElementType() == MVT::i1)
1428 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1430 // Do not attempt to custom lower other non-512-bit vectors
1431 if (!VT.is512BitVector())
1434 if ( EltSize >= 32) {
1435 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1436 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1437 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1438 setOperationAction(ISD::VSELECT, VT, Legal);
1439 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1440 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1441 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1444 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1445 MVT VT = (MVT::SimpleValueType)i;
1447 // Do not attempt to promote non-256-bit vectors
1448 if (!VT.is512BitVector())
1451 setOperationAction(ISD::SELECT, VT, Promote);
1452 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1456 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1457 // of this type with custom code.
1458 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1459 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1460 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1464 // We want to custom lower some of our intrinsics.
1465 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1466 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1467 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1469 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1470 // handle type legalization for these operations here.
1472 // FIXME: We really should do custom legalization for addition and
1473 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1474 // than generic legalization for 64-bit multiplication-with-overflow, though.
1475 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1476 // Add/Sub/Mul with overflow operations are custom lowered.
1478 setOperationAction(ISD::SADDO, VT, Custom);
1479 setOperationAction(ISD::UADDO, VT, Custom);
1480 setOperationAction(ISD::SSUBO, VT, Custom);
1481 setOperationAction(ISD::USUBO, VT, Custom);
1482 setOperationAction(ISD::SMULO, VT, Custom);
1483 setOperationAction(ISD::UMULO, VT, Custom);
1486 // There are no 8-bit 3-address imul/mul instructions
1487 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1488 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1490 if (!Subtarget->is64Bit()) {
1491 // These libcalls are not available in 32-bit.
1492 setLibcallName(RTLIB::SHL_I128, 0);
1493 setLibcallName(RTLIB::SRL_I128, 0);
1494 setLibcallName(RTLIB::SRA_I128, 0);
1497 // Combine sin / cos into one node or libcall if possible.
1498 if (Subtarget->hasSinCos()) {
1499 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1500 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1501 if (Subtarget->isTargetDarwin()) {
1502 // For MacOSX, we don't want to the normal expansion of a libcall to
1503 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
1505 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1506 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1510 // We have target-specific dag combine patterns for the following nodes:
1511 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1512 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1513 setTargetDAGCombine(ISD::VSELECT);
1514 setTargetDAGCombine(ISD::SELECT);
1515 setTargetDAGCombine(ISD::SHL);
1516 setTargetDAGCombine(ISD::SRA);
1517 setTargetDAGCombine(ISD::SRL);
1518 setTargetDAGCombine(ISD::OR);
1519 setTargetDAGCombine(ISD::AND);
1520 setTargetDAGCombine(ISD::ADD);
1521 setTargetDAGCombine(ISD::FADD);
1522 setTargetDAGCombine(ISD::FSUB);
1523 setTargetDAGCombine(ISD::FMA);
1524 setTargetDAGCombine(ISD::SUB);
1525 setTargetDAGCombine(ISD::LOAD);
1526 setTargetDAGCombine(ISD::STORE);
1527 setTargetDAGCombine(ISD::ZERO_EXTEND);
1528 setTargetDAGCombine(ISD::ANY_EXTEND);
1529 setTargetDAGCombine(ISD::SIGN_EXTEND);
1530 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1531 setTargetDAGCombine(ISD::TRUNCATE);
1532 setTargetDAGCombine(ISD::SINT_TO_FP);
1533 setTargetDAGCombine(ISD::SETCC);
1534 if (Subtarget->is64Bit())
1535 setTargetDAGCombine(ISD::MUL);
1536 setTargetDAGCombine(ISD::XOR);
1538 computeRegisterProperties();
1540 // On Darwin, -Os means optimize for size without hurting performance,
1541 // do not reduce the limit.
1542 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1543 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1544 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1545 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1546 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1547 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1548 setPrefLoopAlignment(4); // 2^4 bytes.
1550 // Predictable cmov don't hurt on atom because it's in-order.
1551 PredictableSelectIsExpensive = !Subtarget->isAtom();
1553 setPrefFunctionAlignment(4); // 2^4 bytes.
1556 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1560 const TargetMachine &TM = getTargetMachine();
1561 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512())
1562 switch(VT.getVectorNumElements()) {
1563 case 8: return MVT::v8i1;
1564 case 16: return MVT::v16i1;
1567 return VT.changeVectorElementTypeToInteger();
1570 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1571 /// the desired ByVal argument alignment.
1572 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1575 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1576 if (VTy->getBitWidth() == 128)
1578 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1579 unsigned EltAlign = 0;
1580 getMaxByValAlign(ATy->getElementType(), EltAlign);
1581 if (EltAlign > MaxAlign)
1582 MaxAlign = EltAlign;
1583 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1584 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1585 unsigned EltAlign = 0;
1586 getMaxByValAlign(STy->getElementType(i), EltAlign);
1587 if (EltAlign > MaxAlign)
1588 MaxAlign = EltAlign;
1595 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1596 /// function arguments in the caller parameter area. For X86, aggregates
1597 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1598 /// are at 4-byte boundaries.
1599 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1600 if (Subtarget->is64Bit()) {
1601 // Max of 8 and alignment of type.
1602 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1609 if (Subtarget->hasSSE1())
1610 getMaxByValAlign(Ty, Align);
1614 /// getOptimalMemOpType - Returns the target specific optimal type for load
1615 /// and store operations as a result of memset, memcpy, and memmove
1616 /// lowering. If DstAlign is zero that means it's safe to destination
1617 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1618 /// means there isn't a need to check it against alignment requirement,
1619 /// probably because the source does not need to be loaded. If 'IsMemset' is
1620 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1621 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1622 /// source is constant so it does not need to be loaded.
1623 /// It returns EVT::Other if the type should be determined using generic
1624 /// target-independent logic.
1626 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1627 unsigned DstAlign, unsigned SrcAlign,
1628 bool IsMemset, bool ZeroMemset,
1630 MachineFunction &MF) const {
1631 const Function *F = MF.getFunction();
1632 if ((!IsMemset || ZeroMemset) &&
1633 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1634 Attribute::NoImplicitFloat)) {
1636 (Subtarget->isUnalignedMemAccessFast() ||
1637 ((DstAlign == 0 || DstAlign >= 16) &&
1638 (SrcAlign == 0 || SrcAlign >= 16)))) {
1640 if (Subtarget->hasInt256())
1642 if (Subtarget->hasFp256())
1645 if (Subtarget->hasSSE2())
1647 if (Subtarget->hasSSE1())
1649 } else if (!MemcpyStrSrc && Size >= 8 &&
1650 !Subtarget->is64Bit() &&
1651 Subtarget->hasSSE2()) {
1652 // Do not use f64 to lower memcpy if source is string constant. It's
1653 // better to use i32 to avoid the loads.
1657 if (Subtarget->is64Bit() && Size >= 8)
1662 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1664 return X86ScalarSSEf32;
1665 else if (VT == MVT::f64)
1666 return X86ScalarSSEf64;
1671 X86TargetLowering::allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const {
1673 *Fast = Subtarget->isUnalignedMemAccessFast();
1677 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1678 /// current function. The returned value is a member of the
1679 /// MachineJumpTableInfo::JTEntryKind enum.
1680 unsigned X86TargetLowering::getJumpTableEncoding() const {
1681 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1683 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1684 Subtarget->isPICStyleGOT())
1685 return MachineJumpTableInfo::EK_Custom32;
1687 // Otherwise, use the normal jump table encoding heuristics.
1688 return TargetLowering::getJumpTableEncoding();
1692 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1693 const MachineBasicBlock *MBB,
1694 unsigned uid,MCContext &Ctx) const{
1695 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1696 Subtarget->isPICStyleGOT());
1697 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1699 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1700 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1703 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1705 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1706 SelectionDAG &DAG) const {
1707 if (!Subtarget->is64Bit())
1708 // This doesn't have SDLoc associated with it, but is not really the
1709 // same as a Register.
1710 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1714 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1715 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1717 const MCExpr *X86TargetLowering::
1718 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1719 MCContext &Ctx) const {
1720 // X86-64 uses RIP relative addressing based on the jump table label.
1721 if (Subtarget->isPICStyleRIPRel())
1722 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1724 // Otherwise, the reference is relative to the PIC base.
1725 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1728 // FIXME: Why this routine is here? Move to RegInfo!
1729 std::pair<const TargetRegisterClass*, uint8_t>
1730 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1731 const TargetRegisterClass *RRC = 0;
1733 switch (VT.SimpleTy) {
1735 return TargetLowering::findRepresentativeClass(VT);
1736 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1737 RRC = Subtarget->is64Bit() ?
1738 (const TargetRegisterClass*)&X86::GR64RegClass :
1739 (const TargetRegisterClass*)&X86::GR32RegClass;
1742 RRC = &X86::VR64RegClass;
1744 case MVT::f32: case MVT::f64:
1745 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1746 case MVT::v4f32: case MVT::v2f64:
1747 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1749 RRC = &X86::VR128RegClass;
1752 return std::make_pair(RRC, Cost);
1755 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1756 unsigned &Offset) const {
1757 if (!Subtarget->isTargetLinux())
1760 if (Subtarget->is64Bit()) {
1761 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1763 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1775 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1776 unsigned DestAS) const {
1777 assert(SrcAS != DestAS && "Expected different address spaces!");
1779 return SrcAS < 256 && DestAS < 256;
1782 //===----------------------------------------------------------------------===//
1783 // Return Value Calling Convention Implementation
1784 //===----------------------------------------------------------------------===//
1786 #include "X86GenCallingConv.inc"
1789 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1790 MachineFunction &MF, bool isVarArg,
1791 const SmallVectorImpl<ISD::OutputArg> &Outs,
1792 LLVMContext &Context) const {
1793 SmallVector<CCValAssign, 16> RVLocs;
1794 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1796 return CCInfo.CheckReturn(Outs, RetCC_X86);
1799 const uint16_t *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1800 static const uint16_t ScratchRegs[] = { X86::R11, 0 };
1805 X86TargetLowering::LowerReturn(SDValue Chain,
1806 CallingConv::ID CallConv, bool isVarArg,
1807 const SmallVectorImpl<ISD::OutputArg> &Outs,
1808 const SmallVectorImpl<SDValue> &OutVals,
1809 SDLoc dl, SelectionDAG &DAG) const {
1810 MachineFunction &MF = DAG.getMachineFunction();
1811 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1813 SmallVector<CCValAssign, 16> RVLocs;
1814 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1815 RVLocs, *DAG.getContext());
1816 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1819 SmallVector<SDValue, 6> RetOps;
1820 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1821 // Operand #1 = Bytes To Pop
1822 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1825 // Copy the result values into the output registers.
1826 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1827 CCValAssign &VA = RVLocs[i];
1828 assert(VA.isRegLoc() && "Can only return in registers!");
1829 SDValue ValToCopy = OutVals[i];
1830 EVT ValVT = ValToCopy.getValueType();
1832 // Promote values to the appropriate types
1833 if (VA.getLocInfo() == CCValAssign::SExt)
1834 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
1835 else if (VA.getLocInfo() == CCValAssign::ZExt)
1836 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
1837 else if (VA.getLocInfo() == CCValAssign::AExt)
1838 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
1839 else if (VA.getLocInfo() == CCValAssign::BCvt)
1840 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
1842 // If this is x86-64, and we disabled SSE, we can't return FP values,
1843 // or SSE or MMX vectors.
1844 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1845 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1846 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1847 report_fatal_error("SSE register return with SSE disabled");
1849 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1850 // llvm-gcc has never done it right and no one has noticed, so this
1851 // should be OK for now.
1852 if (ValVT == MVT::f64 &&
1853 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1854 report_fatal_error("SSE2 register return with SSE2 disabled");
1856 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1857 // the RET instruction and handled by the FP Stackifier.
1858 if (VA.getLocReg() == X86::ST0 ||
1859 VA.getLocReg() == X86::ST1) {
1860 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1861 // change the value to the FP stack register class.
1862 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1863 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1864 RetOps.push_back(ValToCopy);
1865 // Don't emit a copytoreg.
1869 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1870 // which is returned in RAX / RDX.
1871 if (Subtarget->is64Bit()) {
1872 if (ValVT == MVT::x86mmx) {
1873 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1874 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1875 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1877 // If we don't have SSE2 available, convert to v4f32 so the generated
1878 // register is legal.
1879 if (!Subtarget->hasSSE2())
1880 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1885 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1886 Flag = Chain.getValue(1);
1887 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
1890 // The x86-64 ABIs require that for returning structs by value we copy
1891 // the sret argument into %rax/%eax (depending on ABI) for the return.
1892 // Win32 requires us to put the sret argument to %eax as well.
1893 // We saved the argument into a virtual register in the entry block,
1894 // so now we copy the value out and into %rax/%eax.
1895 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
1896 (Subtarget->is64Bit() || Subtarget->isTargetWindows())) {
1897 MachineFunction &MF = DAG.getMachineFunction();
1898 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1899 unsigned Reg = FuncInfo->getSRetReturnReg();
1901 "SRetReturnReg should have been set in LowerFormalArguments().");
1902 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1905 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
1906 X86::RAX : X86::EAX;
1907 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
1908 Flag = Chain.getValue(1);
1910 // RAX/EAX now acts like a return value.
1911 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
1914 RetOps[0] = Chain; // Update chain.
1916 // Add the flag if we have it.
1918 RetOps.push_back(Flag);
1920 return DAG.getNode(X86ISD::RET_FLAG, dl,
1921 MVT::Other, &RetOps[0], RetOps.size());
1924 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
1925 if (N->getNumValues() != 1)
1927 if (!N->hasNUsesOfValue(1, 0))
1930 SDValue TCChain = Chain;
1931 SDNode *Copy = *N->use_begin();
1932 if (Copy->getOpcode() == ISD::CopyToReg) {
1933 // If the copy has a glue operand, we conservatively assume it isn't safe to
1934 // perform a tail call.
1935 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
1937 TCChain = Copy->getOperand(0);
1938 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
1941 bool HasRet = false;
1942 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1944 if (UI->getOpcode() != X86ISD::RET_FLAG)
1957 X86TargetLowering::getTypeForExtArgOrReturn(MVT VT,
1958 ISD::NodeType ExtendKind) const {
1960 // TODO: Is this also valid on 32-bit?
1961 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
1962 ReturnMVT = MVT::i8;
1964 ReturnMVT = MVT::i32;
1966 MVT MinVT = getRegisterType(ReturnMVT);
1967 return VT.bitsLT(MinVT) ? MinVT : VT;
1970 /// LowerCallResult - Lower the result values of a call into the
1971 /// appropriate copies out of appropriate physical registers.
1974 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1975 CallingConv::ID CallConv, bool isVarArg,
1976 const SmallVectorImpl<ISD::InputArg> &Ins,
1977 SDLoc dl, SelectionDAG &DAG,
1978 SmallVectorImpl<SDValue> &InVals) const {
1980 // Assign locations to each value returned by this call.
1981 SmallVector<CCValAssign, 16> RVLocs;
1982 bool Is64Bit = Subtarget->is64Bit();
1983 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1984 getTargetMachine(), RVLocs, *DAG.getContext());
1985 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1987 // Copy all of the result registers out of their specified physreg.
1988 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
1989 CCValAssign &VA = RVLocs[i];
1990 EVT CopyVT = VA.getValVT();
1992 // If this is x86-64, and we disabled SSE, we can't return FP values
1993 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1994 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
1995 report_fatal_error("SSE register return with SSE disabled");
2000 // If this is a call to a function that returns an fp value on the floating
2001 // point stack, we must guarantee the value is popped from the stack, so
2002 // a CopyFromReg is not good enough - the copy instruction may be eliminated
2003 // if the return value is not used. We use the FpPOP_RETVAL instruction
2005 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
2006 // If we prefer to use the value in xmm registers, copy it out as f80 and
2007 // use a truncate to move it from fp stack reg to xmm reg.
2008 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
2009 SDValue Ops[] = { Chain, InFlag };
2010 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT,
2011 MVT::Other, MVT::Glue, Ops), 1);
2012 Val = Chain.getValue(0);
2014 // Round the f80 to the right size, which also moves it to the appropriate
2016 if (CopyVT != VA.getValVT())
2017 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2018 // This truncation won't change the value.
2019 DAG.getIntPtrConstant(1));
2021 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2022 CopyVT, InFlag).getValue(1);
2023 Val = Chain.getValue(0);
2025 InFlag = Chain.getValue(2);
2026 InVals.push_back(Val);
2032 //===----------------------------------------------------------------------===//
2033 // C & StdCall & Fast Calling Convention implementation
2034 //===----------------------------------------------------------------------===//
2035 // StdCall calling convention seems to be standard for many Windows' API
2036 // routines and around. It differs from C calling convention just a little:
2037 // callee should clean up the stack, not caller. Symbols should be also
2038 // decorated in some fancy way :) It doesn't support any vector arguments.
2039 // For info on fast calling convention see Fast Calling Convention (tail call)
2040 // implementation LowerX86_32FastCCCallTo.
2042 /// CallIsStructReturn - Determines whether a call uses struct return
2044 enum StructReturnType {
2049 static StructReturnType
2050 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2052 return NotStructReturn;
2054 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2055 if (!Flags.isSRet())
2056 return NotStructReturn;
2057 if (Flags.isInReg())
2058 return RegStructReturn;
2059 return StackStructReturn;
2062 /// ArgsAreStructReturn - Determines whether a function uses struct
2063 /// return semantics.
2064 static StructReturnType
2065 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2067 return NotStructReturn;
2069 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2070 if (!Flags.isSRet())
2071 return NotStructReturn;
2072 if (Flags.isInReg())
2073 return RegStructReturn;
2074 return StackStructReturn;
2077 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2078 /// by "Src" to address "Dst" with size and alignment information specified by
2079 /// the specific parameter attribute. The copy will be passed as a byval
2080 /// function parameter.
2082 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2083 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2085 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2087 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2088 /*isVolatile*/false, /*AlwaysInline=*/true,
2089 MachinePointerInfo(), MachinePointerInfo());
2092 /// IsTailCallConvention - Return true if the calling convention is one that
2093 /// supports tail call optimization.
2094 static bool IsTailCallConvention(CallingConv::ID CC) {
2095 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2096 CC == CallingConv::HiPE);
2099 /// \brief Return true if the calling convention is a C calling convention.
2100 static bool IsCCallConvention(CallingConv::ID CC) {
2101 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2102 CC == CallingConv::X86_64_SysV);
2105 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2106 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2110 CallingConv::ID CalleeCC = CS.getCallingConv();
2111 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2117 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
2118 /// a tailcall target by changing its ABI.
2119 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2120 bool GuaranteedTailCallOpt) {
2121 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2125 X86TargetLowering::LowerMemArgument(SDValue Chain,
2126 CallingConv::ID CallConv,
2127 const SmallVectorImpl<ISD::InputArg> &Ins,
2128 SDLoc dl, SelectionDAG &DAG,
2129 const CCValAssign &VA,
2130 MachineFrameInfo *MFI,
2132 // Create the nodes corresponding to a load from this parameter slot.
2133 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2134 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv,
2135 getTargetMachine().Options.GuaranteedTailCallOpt);
2136 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2139 // If value is passed by pointer we have address passed instead of the value
2141 if (VA.getLocInfo() == CCValAssign::Indirect)
2142 ValVT = VA.getLocVT();
2144 ValVT = VA.getValVT();
2146 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2147 // changed with more analysis.
2148 // In case of tail call optimization mark all arguments mutable. Since they
2149 // could be overwritten by lowering of arguments in case of a tail call.
2150 if (Flags.isByVal()) {
2151 unsigned Bytes = Flags.getByValSize();
2152 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2153 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2154 return DAG.getFrameIndex(FI, getPointerTy());
2156 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2157 VA.getLocMemOffset(), isImmutable);
2158 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2159 return DAG.getLoad(ValVT, dl, Chain, FIN,
2160 MachinePointerInfo::getFixedStack(FI),
2161 false, false, false, 0);
2166 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2167 CallingConv::ID CallConv,
2169 const SmallVectorImpl<ISD::InputArg> &Ins,
2172 SmallVectorImpl<SDValue> &InVals)
2174 MachineFunction &MF = DAG.getMachineFunction();
2175 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2177 const Function* Fn = MF.getFunction();
2178 if (Fn->hasExternalLinkage() &&
2179 Subtarget->isTargetCygMing() &&
2180 Fn->getName() == "main")
2181 FuncInfo->setForceFramePointer(true);
2183 MachineFrameInfo *MFI = MF.getFrameInfo();
2184 bool Is64Bit = Subtarget->is64Bit();
2185 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2187 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2188 "Var args not supported with calling convention fastcc, ghc or hipe");
2190 // Assign locations to all of the incoming arguments.
2191 SmallVector<CCValAssign, 16> ArgLocs;
2192 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2193 ArgLocs, *DAG.getContext());
2195 // Allocate shadow area for Win64
2197 CCInfo.AllocateStack(32, 8);
2199 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2201 unsigned LastVal = ~0U;
2203 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2204 CCValAssign &VA = ArgLocs[i];
2205 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2207 assert(VA.getValNo() != LastVal &&
2208 "Don't support value assigned to multiple locs yet");
2210 LastVal = VA.getValNo();
2212 if (VA.isRegLoc()) {
2213 EVT RegVT = VA.getLocVT();
2214 const TargetRegisterClass *RC;
2215 if (RegVT == MVT::i32)
2216 RC = &X86::GR32RegClass;
2217 else if (Is64Bit && RegVT == MVT::i64)
2218 RC = &X86::GR64RegClass;
2219 else if (RegVT == MVT::f32)
2220 RC = &X86::FR32RegClass;
2221 else if (RegVT == MVT::f64)
2222 RC = &X86::FR64RegClass;
2223 else if (RegVT.is512BitVector())
2224 RC = &X86::VR512RegClass;
2225 else if (RegVT.is256BitVector())
2226 RC = &X86::VR256RegClass;
2227 else if (RegVT.is128BitVector())
2228 RC = &X86::VR128RegClass;
2229 else if (RegVT == MVT::x86mmx)
2230 RC = &X86::VR64RegClass;
2231 else if (RegVT == MVT::i1)
2232 RC = &X86::VK1RegClass;
2233 else if (RegVT == MVT::v8i1)
2234 RC = &X86::VK8RegClass;
2235 else if (RegVT == MVT::v16i1)
2236 RC = &X86::VK16RegClass;
2238 llvm_unreachable("Unknown argument type!");
2240 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2241 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2243 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2244 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2246 if (VA.getLocInfo() == CCValAssign::SExt)
2247 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2248 DAG.getValueType(VA.getValVT()));
2249 else if (VA.getLocInfo() == CCValAssign::ZExt)
2250 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2251 DAG.getValueType(VA.getValVT()));
2252 else if (VA.getLocInfo() == CCValAssign::BCvt)
2253 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2255 if (VA.isExtInLoc()) {
2256 // Handle MMX values passed in XMM regs.
2257 if (RegVT.isVector())
2258 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2260 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2263 assert(VA.isMemLoc());
2264 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2267 // If value is passed via pointer - do a load.
2268 if (VA.getLocInfo() == CCValAssign::Indirect)
2269 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2270 MachinePointerInfo(), false, false, false, 0);
2272 InVals.push_back(ArgValue);
2275 // The x86-64 ABIs require that for returning structs by value we copy
2276 // the sret argument into %rax/%eax (depending on ABI) for the return.
2277 // Win32 requires us to put the sret argument to %eax as well.
2278 // Save the argument into a virtual register so that we can access it
2279 // from the return points.
2280 if (MF.getFunction()->hasStructRetAttr() &&
2281 (Subtarget->is64Bit() || Subtarget->isTargetWindows())) {
2282 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2283 unsigned Reg = FuncInfo->getSRetReturnReg();
2285 MVT PtrTy = getPointerTy();
2286 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2287 FuncInfo->setSRetReturnReg(Reg);
2289 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
2290 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2293 unsigned StackSize = CCInfo.getNextStackOffset();
2294 // Align stack specially for tail calls.
2295 if (FuncIsMadeTailCallSafe(CallConv,
2296 MF.getTarget().Options.GuaranteedTailCallOpt))
2297 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2299 // If the function takes variable number of arguments, make a frame index for
2300 // the start of the first vararg value... for expansion of llvm.va_start.
2302 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2303 CallConv != CallingConv::X86_ThisCall)) {
2304 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
2307 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
2309 // FIXME: We should really autogenerate these arrays
2310 static const uint16_t GPR64ArgRegsWin64[] = {
2311 X86::RCX, X86::RDX, X86::R8, X86::R9
2313 static const uint16_t GPR64ArgRegs64Bit[] = {
2314 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2316 static const uint16_t XMMArgRegs64Bit[] = {
2317 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2318 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2320 const uint16_t *GPR64ArgRegs;
2321 unsigned NumXMMRegs = 0;
2324 // The XMM registers which might contain var arg parameters are shadowed
2325 // in their paired GPR. So we only need to save the GPR to their home
2327 TotalNumIntRegs = 4;
2328 GPR64ArgRegs = GPR64ArgRegsWin64;
2330 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
2331 GPR64ArgRegs = GPR64ArgRegs64Bit;
2333 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit,
2336 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
2339 bool NoImplicitFloatOps = Fn->getAttributes().
2340 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2341 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2342 "SSE register cannot be used when SSE is disabled!");
2343 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat &&
2344 NoImplicitFloatOps) &&
2345 "SSE register cannot be used when SSE is disabled!");
2346 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2347 !Subtarget->hasSSE1())
2348 // Kernel mode asks for SSE to be disabled, so don't push them
2350 TotalNumXMMRegs = 0;
2353 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering();
2354 // Get to the caller-allocated home save location. Add 8 to account
2355 // for the return address.
2356 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2357 FuncInfo->setRegSaveFrameIndex(
2358 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2359 // Fixup to set vararg frame on shadow area (4 x i64).
2361 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2363 // For X86-64, if there are vararg parameters that are passed via
2364 // registers, then we must store them to their spots on the stack so
2365 // they may be loaded by deferencing the result of va_next.
2366 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2367 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
2368 FuncInfo->setRegSaveFrameIndex(
2369 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
2373 // Store the integer parameter registers.
2374 SmallVector<SDValue, 8> MemOps;
2375 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2377 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2378 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
2379 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2380 DAG.getIntPtrConstant(Offset));
2381 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
2382 &X86::GR64RegClass);
2383 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2385 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2386 MachinePointerInfo::getFixedStack(
2387 FuncInfo->getRegSaveFrameIndex(), Offset),
2389 MemOps.push_back(Store);
2393 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
2394 // Now store the XMM (fp + vector) parameter registers.
2395 SmallVector<SDValue, 11> SaveXMMOps;
2396 SaveXMMOps.push_back(Chain);
2398 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2399 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
2400 SaveXMMOps.push_back(ALVal);
2402 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2403 FuncInfo->getRegSaveFrameIndex()));
2404 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2405 FuncInfo->getVarArgsFPOffset()));
2407 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
2408 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
2409 &X86::VR128RegClass);
2410 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
2411 SaveXMMOps.push_back(Val);
2413 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2415 &SaveXMMOps[0], SaveXMMOps.size()));
2418 if (!MemOps.empty())
2419 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2420 &MemOps[0], MemOps.size());
2424 // Some CCs need callee pop.
2425 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2426 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2427 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2429 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2430 // If this is an sret function, the return should pop the hidden pointer.
2431 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2432 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2433 argsAreStructReturn(Ins) == StackStructReturn)
2434 FuncInfo->setBytesToPopOnReturn(4);
2438 // RegSaveFrameIndex is X86-64 only.
2439 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2440 if (CallConv == CallingConv::X86_FastCall ||
2441 CallConv == CallingConv::X86_ThisCall)
2442 // fastcc functions can't have varargs.
2443 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2446 FuncInfo->setArgumentStackSize(StackSize);
2452 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2453 SDValue StackPtr, SDValue Arg,
2454 SDLoc dl, SelectionDAG &DAG,
2455 const CCValAssign &VA,
2456 ISD::ArgFlagsTy Flags) const {
2457 unsigned LocMemOffset = VA.getLocMemOffset();
2458 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2459 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2460 if (Flags.isByVal())
2461 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2463 return DAG.getStore(Chain, dl, Arg, PtrOff,
2464 MachinePointerInfo::getStack(LocMemOffset),
2468 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2469 /// optimization is performed and it is required.
2471 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2472 SDValue &OutRetAddr, SDValue Chain,
2473 bool IsTailCall, bool Is64Bit,
2474 int FPDiff, SDLoc dl) const {
2475 // Adjust the Return address stack slot.
2476 EVT VT = getPointerTy();
2477 OutRetAddr = getReturnAddressFrameIndex(DAG);
2479 // Load the "old" Return address.
2480 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2481 false, false, false, 0);
2482 return SDValue(OutRetAddr.getNode(), 1);
2485 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2486 /// optimization is performed and it is required (FPDiff!=0).
2488 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
2489 SDValue Chain, SDValue RetAddrFrIdx, EVT PtrVT,
2490 unsigned SlotSize, int FPDiff, SDLoc dl) {
2491 // Store the return address to the appropriate stack slot.
2492 if (!FPDiff) return Chain;
2493 // Calculate the new stack slot for the return address.
2494 int NewReturnAddrFI =
2495 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2497 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2498 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2499 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2505 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2506 SmallVectorImpl<SDValue> &InVals) const {
2507 SelectionDAG &DAG = CLI.DAG;
2509 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2510 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2511 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2512 SDValue Chain = CLI.Chain;
2513 SDValue Callee = CLI.Callee;
2514 CallingConv::ID CallConv = CLI.CallConv;
2515 bool &isTailCall = CLI.IsTailCall;
2516 bool isVarArg = CLI.IsVarArg;
2518 MachineFunction &MF = DAG.getMachineFunction();
2519 bool Is64Bit = Subtarget->is64Bit();
2520 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2521 StructReturnType SR = callIsStructReturn(Outs);
2522 bool IsSibcall = false;
2524 if (MF.getTarget().Options.DisableTailCalls)
2528 // Check if it's really possible to do a tail call.
2529 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2530 isVarArg, SR != NotStructReturn,
2531 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2532 Outs, OutVals, Ins, DAG);
2534 // Sibcalls are automatically detected tailcalls which do not require
2536 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2543 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2544 "Var args not supported with calling convention fastcc, ghc or hipe");
2546 // Analyze operands of the call, assigning locations to each operand.
2547 SmallVector<CCValAssign, 16> ArgLocs;
2548 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2549 ArgLocs, *DAG.getContext());
2551 // Allocate shadow area for Win64
2553 CCInfo.AllocateStack(32, 8);
2555 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2557 // Get a count of how many bytes are to be pushed on the stack.
2558 unsigned NumBytes = CCInfo.getNextStackOffset();
2560 // This is a sibcall. The memory operands are available in caller's
2561 // own caller's stack.
2563 else if (getTargetMachine().Options.GuaranteedTailCallOpt &&
2564 IsTailCallConvention(CallConv))
2565 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2568 if (isTailCall && !IsSibcall) {
2569 // Lower arguments at fp - stackoffset + fpdiff.
2570 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2571 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2573 FPDiff = NumBytesCallerPushed - NumBytes;
2575 // Set the delta of movement of the returnaddr stackslot.
2576 // But only set if delta is greater than previous delta.
2577 if (FPDiff < X86Info->getTCReturnAddrDelta())
2578 X86Info->setTCReturnAddrDelta(FPDiff);
2582 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
2585 SDValue RetAddrFrIdx;
2586 // Load return address for tail calls.
2587 if (isTailCall && FPDiff)
2588 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2589 Is64Bit, FPDiff, dl);
2591 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2592 SmallVector<SDValue, 8> MemOpChains;
2595 // Walk the register/memloc assignments, inserting copies/loads. In the case
2596 // of tail call optimization arguments are handle later.
2597 const X86RegisterInfo *RegInfo =
2598 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
2599 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2600 CCValAssign &VA = ArgLocs[i];
2601 EVT RegVT = VA.getLocVT();
2602 SDValue Arg = OutVals[i];
2603 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2604 bool isByVal = Flags.isByVal();
2606 // Promote the value if needed.
2607 switch (VA.getLocInfo()) {
2608 default: llvm_unreachable("Unknown loc info!");
2609 case CCValAssign::Full: break;
2610 case CCValAssign::SExt:
2611 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2613 case CCValAssign::ZExt:
2614 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2616 case CCValAssign::AExt:
2617 if (RegVT.is128BitVector()) {
2618 // Special case: passing MMX values in XMM registers.
2619 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2620 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2621 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2623 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2625 case CCValAssign::BCvt:
2626 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2628 case CCValAssign::Indirect: {
2629 // Store the argument.
2630 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2631 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2632 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2633 MachinePointerInfo::getFixedStack(FI),
2640 if (VA.isRegLoc()) {
2641 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2642 if (isVarArg && IsWin64) {
2643 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2644 // shadow reg if callee is a varargs function.
2645 unsigned ShadowReg = 0;
2646 switch (VA.getLocReg()) {
2647 case X86::XMM0: ShadowReg = X86::RCX; break;
2648 case X86::XMM1: ShadowReg = X86::RDX; break;
2649 case X86::XMM2: ShadowReg = X86::R8; break;
2650 case X86::XMM3: ShadowReg = X86::R9; break;
2653 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2655 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2656 assert(VA.isMemLoc());
2657 if (StackPtr.getNode() == 0)
2658 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2660 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2661 dl, DAG, VA, Flags));
2665 if (!MemOpChains.empty())
2666 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2667 &MemOpChains[0], MemOpChains.size());
2669 if (Subtarget->isPICStyleGOT()) {
2670 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2673 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2674 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2676 // If we are tail calling and generating PIC/GOT style code load the
2677 // address of the callee into ECX. The value in ecx is used as target of
2678 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2679 // for tail calls on PIC/GOT architectures. Normally we would just put the
2680 // address of GOT into ebx and then call target@PLT. But for tail calls
2681 // ebx would be restored (since ebx is callee saved) before jumping to the
2684 // Note: The actual moving to ECX is done further down.
2685 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2686 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2687 !G->getGlobal()->hasProtectedVisibility())
2688 Callee = LowerGlobalAddress(Callee, DAG);
2689 else if (isa<ExternalSymbolSDNode>(Callee))
2690 Callee = LowerExternalSymbol(Callee, DAG);
2694 if (Is64Bit && isVarArg && !IsWin64) {
2695 // From AMD64 ABI document:
2696 // For calls that may call functions that use varargs or stdargs
2697 // (prototype-less calls or calls to functions containing ellipsis (...) in
2698 // the declaration) %al is used as hidden argument to specify the number
2699 // of SSE registers used. The contents of %al do not need to match exactly
2700 // the number of registers, but must be an ubound on the number of SSE
2701 // registers used and is in the range 0 - 8 inclusive.
2703 // Count the number of XMM registers allocated.
2704 static const uint16_t XMMArgRegs[] = {
2705 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2706 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2708 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2709 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2710 && "SSE registers cannot be used when SSE is disabled");
2712 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2713 DAG.getConstant(NumXMMRegs, MVT::i8)));
2716 // For tail calls lower the arguments to the 'real' stack slot.
2718 // Force all the incoming stack arguments to be loaded from the stack
2719 // before any new outgoing arguments are stored to the stack, because the
2720 // outgoing stack slots may alias the incoming argument stack slots, and
2721 // the alias isn't otherwise explicit. This is slightly more conservative
2722 // than necessary, because it means that each store effectively depends
2723 // on every argument instead of just those arguments it would clobber.
2724 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2726 SmallVector<SDValue, 8> MemOpChains2;
2729 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2730 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2731 CCValAssign &VA = ArgLocs[i];
2734 assert(VA.isMemLoc());
2735 SDValue Arg = OutVals[i];
2736 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2737 // Create frame index.
2738 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2739 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2740 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2741 FIN = DAG.getFrameIndex(FI, getPointerTy());
2743 if (Flags.isByVal()) {
2744 // Copy relative to framepointer.
2745 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2746 if (StackPtr.getNode() == 0)
2747 StackPtr = DAG.getCopyFromReg(Chain, dl,
2748 RegInfo->getStackRegister(),
2750 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2752 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2756 // Store relative to framepointer.
2757 MemOpChains2.push_back(
2758 DAG.getStore(ArgChain, dl, Arg, FIN,
2759 MachinePointerInfo::getFixedStack(FI),
2765 if (!MemOpChains2.empty())
2766 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2767 &MemOpChains2[0], MemOpChains2.size());
2769 // Store the return address to the appropriate stack slot.
2770 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
2771 getPointerTy(), RegInfo->getSlotSize(),
2775 // Build a sequence of copy-to-reg nodes chained together with token chain
2776 // and flag operands which copy the outgoing args into registers.
2778 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2779 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2780 RegsToPass[i].second, InFlag);
2781 InFlag = Chain.getValue(1);
2784 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2785 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2786 // In the 64-bit large code model, we have to make all calls
2787 // through a register, since the call instruction's 32-bit
2788 // pc-relative offset may not be large enough to hold the whole
2790 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2791 // If the callee is a GlobalAddress node (quite common, every direct call
2792 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2795 // We should use extra load for direct calls to dllimported functions in
2797 const GlobalValue *GV = G->getGlobal();
2798 if (!GV->hasDLLImportLinkage()) {
2799 unsigned char OpFlags = 0;
2800 bool ExtraLoad = false;
2801 unsigned WrapperKind = ISD::DELETED_NODE;
2803 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2804 // external symbols most go through the PLT in PIC mode. If the symbol
2805 // has hidden or protected visibility, or if it is static or local, then
2806 // we don't need to use the PLT - we can directly call it.
2807 if (Subtarget->isTargetELF() &&
2808 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2809 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2810 OpFlags = X86II::MO_PLT;
2811 } else if (Subtarget->isPICStyleStubAny() &&
2812 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2813 (!Subtarget->getTargetTriple().isMacOSX() ||
2814 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2815 // PC-relative references to external symbols should go through $stub,
2816 // unless we're building with the leopard linker or later, which
2817 // automatically synthesizes these stubs.
2818 OpFlags = X86II::MO_DARWIN_STUB;
2819 } else if (Subtarget->isPICStyleRIPRel() &&
2820 isa<Function>(GV) &&
2821 cast<Function>(GV)->getAttributes().
2822 hasAttribute(AttributeSet::FunctionIndex,
2823 Attribute::NonLazyBind)) {
2824 // If the function is marked as non-lazy, generate an indirect call
2825 // which loads from the GOT directly. This avoids runtime overhead
2826 // at the cost of eager binding (and one extra byte of encoding).
2827 OpFlags = X86II::MO_GOTPCREL;
2828 WrapperKind = X86ISD::WrapperRIP;
2832 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2833 G->getOffset(), OpFlags);
2835 // Add a wrapper if needed.
2836 if (WrapperKind != ISD::DELETED_NODE)
2837 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
2838 // Add extra indirection if needed.
2840 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
2841 MachinePointerInfo::getGOT(),
2842 false, false, false, 0);
2844 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2845 unsigned char OpFlags = 0;
2847 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2848 // external symbols should go through the PLT.
2849 if (Subtarget->isTargetELF() &&
2850 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2851 OpFlags = X86II::MO_PLT;
2852 } else if (Subtarget->isPICStyleStubAny() &&
2853 (!Subtarget->getTargetTriple().isMacOSX() ||
2854 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2855 // PC-relative references to external symbols should go through $stub,
2856 // unless we're building with the leopard linker or later, which
2857 // automatically synthesizes these stubs.
2858 OpFlags = X86II::MO_DARWIN_STUB;
2861 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2865 // Returns a chain & a flag for retval copy to use.
2866 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2867 SmallVector<SDValue, 8> Ops;
2869 if (!IsSibcall && isTailCall) {
2870 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2871 DAG.getIntPtrConstant(0, true), InFlag, dl);
2872 InFlag = Chain.getValue(1);
2875 Ops.push_back(Chain);
2876 Ops.push_back(Callee);
2879 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2881 // Add argument registers to the end of the list so that they are known live
2883 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2884 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2885 RegsToPass[i].second.getValueType()));
2887 // Add a register mask operand representing the call-preserved registers.
2888 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2889 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
2890 assert(Mask && "Missing call preserved mask for calling convention");
2891 Ops.push_back(DAG.getRegisterMask(Mask));
2893 if (InFlag.getNode())
2894 Ops.push_back(InFlag);
2898 //// If this is the first return lowered for this function, add the regs
2899 //// to the liveout set for the function.
2900 // This isn't right, although it's probably harmless on x86; liveouts
2901 // should be computed from returns not tail calls. Consider a void
2902 // function making a tail call to a function returning int.
2903 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size());
2906 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2907 InFlag = Chain.getValue(1);
2909 // Create the CALLSEQ_END node.
2910 unsigned NumBytesForCalleeToPush;
2911 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2912 getTargetMachine().Options.GuaranteedTailCallOpt))
2913 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2914 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2915 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2916 SR == StackStructReturn)
2917 // If this is a call to a struct-return function, the callee
2918 // pops the hidden struct pointer, so we have to push it back.
2919 // This is common for Darwin/X86, Linux & Mingw32 targets.
2920 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
2921 NumBytesForCalleeToPush = 4;
2923 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2925 // Returns a flag for retval copy to use.
2927 Chain = DAG.getCALLSEQ_END(Chain,
2928 DAG.getIntPtrConstant(NumBytes, true),
2929 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2932 InFlag = Chain.getValue(1);
2935 // Handle result values, copying them out of physregs into vregs that we
2937 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2938 Ins, dl, DAG, InVals);
2941 //===----------------------------------------------------------------------===//
2942 // Fast Calling Convention (tail call) implementation
2943 //===----------------------------------------------------------------------===//
2945 // Like std call, callee cleans arguments, convention except that ECX is
2946 // reserved for storing the tail called function address. Only 2 registers are
2947 // free for argument passing (inreg). Tail call optimization is performed
2949 // * tailcallopt is enabled
2950 // * caller/callee are fastcc
2951 // On X86_64 architecture with GOT-style position independent code only local
2952 // (within module) calls are supported at the moment.
2953 // To keep the stack aligned according to platform abi the function
2954 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2955 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2956 // If a tail called function callee has more arguments than the caller the
2957 // caller needs to make sure that there is room to move the RETADDR to. This is
2958 // achieved by reserving an area the size of the argument delta right after the
2959 // original REtADDR, but before the saved framepointer or the spilled registers
2960 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2972 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2973 /// for a 16 byte align requirement.
2975 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2976 SelectionDAG& DAG) const {
2977 MachineFunction &MF = DAG.getMachineFunction();
2978 const TargetMachine &TM = MF.getTarget();
2979 const X86RegisterInfo *RegInfo =
2980 static_cast<const X86RegisterInfo*>(TM.getRegisterInfo());
2981 const TargetFrameLowering &TFI = *TM.getFrameLowering();
2982 unsigned StackAlignment = TFI.getStackAlignment();
2983 uint64_t AlignMask = StackAlignment - 1;
2984 int64_t Offset = StackSize;
2985 unsigned SlotSize = RegInfo->getSlotSize();
2986 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2987 // Number smaller than 12 so just add the difference.
2988 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2990 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2991 Offset = ((~AlignMask) & Offset) + StackAlignment +
2992 (StackAlignment-SlotSize);
2997 /// MatchingStackOffset - Return true if the given stack call argument is
2998 /// already available in the same position (relatively) of the caller's
2999 /// incoming argument stack.
3001 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3002 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3003 const X86InstrInfo *TII) {
3004 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3006 if (Arg.getOpcode() == ISD::CopyFromReg) {
3007 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3008 if (!TargetRegisterInfo::isVirtualRegister(VR))
3010 MachineInstr *Def = MRI->getVRegDef(VR);
3013 if (!Flags.isByVal()) {
3014 if (!TII->isLoadFromStackSlot(Def, FI))
3017 unsigned Opcode = Def->getOpcode();
3018 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
3019 Def->getOperand(1).isFI()) {
3020 FI = Def->getOperand(1).getIndex();
3021 Bytes = Flags.getByValSize();
3025 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3026 if (Flags.isByVal())
3027 // ByVal argument is passed in as a pointer but it's now being
3028 // dereferenced. e.g.
3029 // define @foo(%struct.X* %A) {
3030 // tail call @bar(%struct.X* byval %A)
3033 SDValue Ptr = Ld->getBasePtr();
3034 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3037 FI = FINode->getIndex();
3038 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3039 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3040 FI = FINode->getIndex();
3041 Bytes = Flags.getByValSize();
3045 assert(FI != INT_MAX);
3046 if (!MFI->isFixedObjectIndex(FI))
3048 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3051 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3052 /// for tail call optimization. Targets which want to do tail call
3053 /// optimization should implement this function.
3055 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3056 CallingConv::ID CalleeCC,
3058 bool isCalleeStructRet,
3059 bool isCallerStructRet,
3061 const SmallVectorImpl<ISD::OutputArg> &Outs,
3062 const SmallVectorImpl<SDValue> &OutVals,
3063 const SmallVectorImpl<ISD::InputArg> &Ins,
3064 SelectionDAG &DAG) const {
3065 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3068 // If -tailcallopt is specified, make fastcc functions tail-callable.
3069 const MachineFunction &MF = DAG.getMachineFunction();
3070 const Function *CallerF = MF.getFunction();
3072 // If the function return type is x86_fp80 and the callee return type is not,
3073 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3074 // perform a tailcall optimization here.
3075 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3078 CallingConv::ID CallerCC = CallerF->getCallingConv();
3079 bool CCMatch = CallerCC == CalleeCC;
3080 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3081 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3083 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
3084 if (IsTailCallConvention(CalleeCC) && CCMatch)
3089 // Look for obvious safe cases to perform tail call optimization that do not
3090 // require ABI changes. This is what gcc calls sibcall.
3092 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3093 // emit a special epilogue.
3094 const X86RegisterInfo *RegInfo =
3095 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
3096 if (RegInfo->needsStackRealignment(MF))
3099 // Also avoid sibcall optimization if either caller or callee uses struct
3100 // return semantics.
3101 if (isCalleeStructRet || isCallerStructRet)
3104 // An stdcall/thiscall caller is expected to clean up its arguments; the
3105 // callee isn't going to do that.
3106 // FIXME: this is more restrictive than needed. We could produce a tailcall
3107 // when the stack adjustment matches. For example, with a thiscall that takes
3108 // only one argument.
3109 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3110 CallerCC == CallingConv::X86_ThisCall))
3113 // Do not sibcall optimize vararg calls unless all arguments are passed via
3115 if (isVarArg && !Outs.empty()) {
3117 // Optimizing for varargs on Win64 is unlikely to be safe without
3118 // additional testing.
3119 if (IsCalleeWin64 || IsCallerWin64)
3122 SmallVector<CCValAssign, 16> ArgLocs;
3123 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
3124 getTargetMachine(), ArgLocs, *DAG.getContext());
3126 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3127 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3128 if (!ArgLocs[i].isRegLoc())
3132 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3133 // stack. Therefore, if it's not used by the call it is not safe to optimize
3134 // this into a sibcall.
3135 bool Unused = false;
3136 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3143 SmallVector<CCValAssign, 16> RVLocs;
3144 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(),
3145 getTargetMachine(), RVLocs, *DAG.getContext());
3146 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3147 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3148 CCValAssign &VA = RVLocs[i];
3149 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
3154 // If the calling conventions do not match, then we'd better make sure the
3155 // results are returned in the same way as what the caller expects.
3157 SmallVector<CCValAssign, 16> RVLocs1;
3158 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
3159 getTargetMachine(), RVLocs1, *DAG.getContext());
3160 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3162 SmallVector<CCValAssign, 16> RVLocs2;
3163 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
3164 getTargetMachine(), RVLocs2, *DAG.getContext());
3165 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3167 if (RVLocs1.size() != RVLocs2.size())
3169 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3170 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3172 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3174 if (RVLocs1[i].isRegLoc()) {
3175 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3178 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3184 // If the callee takes no arguments then go on to check the results of the
3186 if (!Outs.empty()) {
3187 // Check if stack adjustment is needed. For now, do not do this if any
3188 // argument is passed on the stack.
3189 SmallVector<CCValAssign, 16> ArgLocs;
3190 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
3191 getTargetMachine(), ArgLocs, *DAG.getContext());
3193 // Allocate shadow area for Win64
3195 CCInfo.AllocateStack(32, 8);
3197 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3198 if (CCInfo.getNextStackOffset()) {
3199 MachineFunction &MF = DAG.getMachineFunction();
3200 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3203 // Check if the arguments are already laid out in the right way as
3204 // the caller's fixed stack objects.
3205 MachineFrameInfo *MFI = MF.getFrameInfo();
3206 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3207 const X86InstrInfo *TII =
3208 ((const X86TargetMachine&)getTargetMachine()).getInstrInfo();
3209 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3210 CCValAssign &VA = ArgLocs[i];
3211 SDValue Arg = OutVals[i];
3212 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3213 if (VA.getLocInfo() == CCValAssign::Indirect)
3215 if (!VA.isRegLoc()) {
3216 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3223 // If the tailcall address may be in a register, then make sure it's
3224 // possible to register allocate for it. In 32-bit, the call address can
3225 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3226 // callee-saved registers are restored. These happen to be the same
3227 // registers used to pass 'inreg' arguments so watch out for those.
3228 if (!Subtarget->is64Bit() &&
3229 ((!isa<GlobalAddressSDNode>(Callee) &&
3230 !isa<ExternalSymbolSDNode>(Callee)) ||
3231 getTargetMachine().getRelocationModel() == Reloc::PIC_)) {
3232 unsigned NumInRegs = 0;
3233 // In PIC we need an extra register to formulate the address computation
3235 unsigned MaxInRegs =
3236 (getTargetMachine().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3238 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3239 CCValAssign &VA = ArgLocs[i];
3242 unsigned Reg = VA.getLocReg();
3245 case X86::EAX: case X86::EDX: case X86::ECX:
3246 if (++NumInRegs == MaxInRegs)
3258 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3259 const TargetLibraryInfo *libInfo) const {
3260 return X86::createFastISel(funcInfo, libInfo);
3263 //===----------------------------------------------------------------------===//
3264 // Other Lowering Hooks
3265 //===----------------------------------------------------------------------===//
3267 static bool MayFoldLoad(SDValue Op) {
3268 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3271 static bool MayFoldIntoStore(SDValue Op) {
3272 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3275 static bool isTargetShuffle(unsigned Opcode) {
3277 default: return false;
3278 case X86ISD::PSHUFD:
3279 case X86ISD::PSHUFHW:
3280 case X86ISD::PSHUFLW:
3282 case X86ISD::PALIGNR:
3283 case X86ISD::MOVLHPS:
3284 case X86ISD::MOVLHPD:
3285 case X86ISD::MOVHLPS:
3286 case X86ISD::MOVLPS:
3287 case X86ISD::MOVLPD:
3288 case X86ISD::MOVSHDUP:
3289 case X86ISD::MOVSLDUP:
3290 case X86ISD::MOVDDUP:
3293 case X86ISD::UNPCKL:
3294 case X86ISD::UNPCKH:
3295 case X86ISD::VPERMILP:
3296 case X86ISD::VPERM2X128:
3297 case X86ISD::VPERMI:
3302 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3303 SDValue V1, SelectionDAG &DAG) {
3305 default: llvm_unreachable("Unknown x86 shuffle node");
3306 case X86ISD::MOVSHDUP:
3307 case X86ISD::MOVSLDUP:
3308 case X86ISD::MOVDDUP:
3309 return DAG.getNode(Opc, dl, VT, V1);
3313 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3314 SDValue V1, unsigned TargetMask,
3315 SelectionDAG &DAG) {
3317 default: llvm_unreachable("Unknown x86 shuffle node");
3318 case X86ISD::PSHUFD:
3319 case X86ISD::PSHUFHW:
3320 case X86ISD::PSHUFLW:
3321 case X86ISD::VPERMILP:
3322 case X86ISD::VPERMI:
3323 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3327 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3328 SDValue V1, SDValue V2, unsigned TargetMask,
3329 SelectionDAG &DAG) {
3331 default: llvm_unreachable("Unknown x86 shuffle node");
3332 case X86ISD::PALIGNR:
3334 case X86ISD::VPERM2X128:
3335 return DAG.getNode(Opc, dl, VT, V1, V2,
3336 DAG.getConstant(TargetMask, MVT::i8));
3340 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3341 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3343 default: llvm_unreachable("Unknown x86 shuffle node");
3344 case X86ISD::MOVLHPS:
3345 case X86ISD::MOVLHPD:
3346 case X86ISD::MOVHLPS:
3347 case X86ISD::MOVLPS:
3348 case X86ISD::MOVLPD:
3351 case X86ISD::UNPCKL:
3352 case X86ISD::UNPCKH:
3353 return DAG.getNode(Opc, dl, VT, V1, V2);
3357 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3358 MachineFunction &MF = DAG.getMachineFunction();
3359 const X86RegisterInfo *RegInfo =
3360 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
3361 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3362 int ReturnAddrIndex = FuncInfo->getRAIndex();
3364 if (ReturnAddrIndex == 0) {
3365 // Set up a frame object for the return address.
3366 unsigned SlotSize = RegInfo->getSlotSize();
3367 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3370 FuncInfo->setRAIndex(ReturnAddrIndex);
3373 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3376 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3377 bool hasSymbolicDisplacement) {
3378 // Offset should fit into 32 bit immediate field.
3379 if (!isInt<32>(Offset))
3382 // If we don't have a symbolic displacement - we don't have any extra
3384 if (!hasSymbolicDisplacement)
3387 // FIXME: Some tweaks might be needed for medium code model.
3388 if (M != CodeModel::Small && M != CodeModel::Kernel)
3391 // For small code model we assume that latest object is 16MB before end of 31
3392 // bits boundary. We may also accept pretty large negative constants knowing
3393 // that all objects are in the positive half of address space.
3394 if (M == CodeModel::Small && Offset < 16*1024*1024)
3397 // For kernel code model we know that all object resist in the negative half
3398 // of 32bits address space. We may not accept negative offsets, since they may
3399 // be just off and we may accept pretty large positive ones.
3400 if (M == CodeModel::Kernel && Offset > 0)
3406 /// isCalleePop - Determines whether the callee is required to pop its
3407 /// own arguments. Callee pop is necessary to support tail calls.
3408 bool X86::isCalleePop(CallingConv::ID CallingConv,
3409 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3413 switch (CallingConv) {
3416 case CallingConv::X86_StdCall:
3418 case CallingConv::X86_FastCall:
3420 case CallingConv::X86_ThisCall:
3422 case CallingConv::Fast:
3424 case CallingConv::GHC:
3426 case CallingConv::HiPE:
3431 /// \brief Return true if the condition is an unsigned comparison operation.
3432 static bool isX86CCUnsigned(unsigned X86CC) {
3434 default: llvm_unreachable("Invalid integer condition!");
3435 case X86::COND_E: return true;
3436 case X86::COND_G: return false;
3437 case X86::COND_GE: return false;
3438 case X86::COND_L: return false;
3439 case X86::COND_LE: return false;
3440 case X86::COND_NE: return true;
3441 case X86::COND_B: return true;
3442 case X86::COND_A: return true;
3443 case X86::COND_BE: return true;
3444 case X86::COND_AE: return true;
3446 llvm_unreachable("covered switch fell through?!");
3449 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3450 /// specific condition code, returning the condition code and the LHS/RHS of the
3451 /// comparison to make.
3452 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3453 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3455 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3456 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3457 // X > -1 -> X == 0, jump !sign.
3458 RHS = DAG.getConstant(0, RHS.getValueType());
3459 return X86::COND_NS;
3461 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3462 // X < 0 -> X == 0, jump on sign.
3465 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3467 RHS = DAG.getConstant(0, RHS.getValueType());
3468 return X86::COND_LE;
3472 switch (SetCCOpcode) {
3473 default: llvm_unreachable("Invalid integer condition!");
3474 case ISD::SETEQ: return X86::COND_E;
3475 case ISD::SETGT: return X86::COND_G;
3476 case ISD::SETGE: return X86::COND_GE;
3477 case ISD::SETLT: return X86::COND_L;
3478 case ISD::SETLE: return X86::COND_LE;
3479 case ISD::SETNE: return X86::COND_NE;
3480 case ISD::SETULT: return X86::COND_B;
3481 case ISD::SETUGT: return X86::COND_A;
3482 case ISD::SETULE: return X86::COND_BE;
3483 case ISD::SETUGE: return X86::COND_AE;
3487 // First determine if it is required or is profitable to flip the operands.
3489 // If LHS is a foldable load, but RHS is not, flip the condition.
3490 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3491 !ISD::isNON_EXTLoad(RHS.getNode())) {
3492 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3493 std::swap(LHS, RHS);
3496 switch (SetCCOpcode) {
3502 std::swap(LHS, RHS);
3506 // On a floating point condition, the flags are set as follows:
3508 // 0 | 0 | 0 | X > Y
3509 // 0 | 0 | 1 | X < Y
3510 // 1 | 0 | 0 | X == Y
3511 // 1 | 1 | 1 | unordered
3512 switch (SetCCOpcode) {
3513 default: llvm_unreachable("Condcode should be pre-legalized away");
3515 case ISD::SETEQ: return X86::COND_E;
3516 case ISD::SETOLT: // flipped
3518 case ISD::SETGT: return X86::COND_A;
3519 case ISD::SETOLE: // flipped
3521 case ISD::SETGE: return X86::COND_AE;
3522 case ISD::SETUGT: // flipped
3524 case ISD::SETLT: return X86::COND_B;
3525 case ISD::SETUGE: // flipped
3527 case ISD::SETLE: return X86::COND_BE;
3529 case ISD::SETNE: return X86::COND_NE;
3530 case ISD::SETUO: return X86::COND_P;
3531 case ISD::SETO: return X86::COND_NP;
3533 case ISD::SETUNE: return X86::COND_INVALID;
3537 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3538 /// code. Current x86 isa includes the following FP cmov instructions:
3539 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3540 static bool hasFPCMov(unsigned X86CC) {
3556 /// isFPImmLegal - Returns true if the target can instruction select the
3557 /// specified FP immediate natively. If false, the legalizer will
3558 /// materialize the FP immediate as a load from a constant pool.
3559 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3560 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3561 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3567 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3568 /// the specified range (L, H].
3569 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3570 return (Val < 0) || (Val >= Low && Val < Hi);
3573 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3574 /// specified value.
3575 static bool isUndefOrEqual(int Val, int CmpVal) {
3576 return (Val < 0 || Val == CmpVal);
3579 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3580 /// from position Pos and ending in Pos+Size, falls within the specified
3581 /// sequential range (L, L+Pos]. or is undef.
3582 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3583 unsigned Pos, unsigned Size, int Low) {
3584 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3585 if (!isUndefOrEqual(Mask[i], Low))
3590 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3591 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3592 /// the second operand.
3593 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT) {
3594 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3595 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3596 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3597 return (Mask[0] < 2 && Mask[1] < 2);
3601 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3602 /// is suitable for input to PSHUFHW.
3603 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3604 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3607 // Lower quadword copied in order or undef.
3608 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3611 // Upper quadword shuffled.
3612 for (unsigned i = 4; i != 8; ++i)
3613 if (!isUndefOrInRange(Mask[i], 4, 8))
3616 if (VT == MVT::v16i16) {
3617 // Lower quadword copied in order or undef.
3618 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3621 // Upper quadword shuffled.
3622 for (unsigned i = 12; i != 16; ++i)
3623 if (!isUndefOrInRange(Mask[i], 12, 16))
3630 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3631 /// is suitable for input to PSHUFLW.
3632 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3633 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3636 // Upper quadword copied in order.
3637 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3640 // Lower quadword shuffled.
3641 for (unsigned i = 0; i != 4; ++i)
3642 if (!isUndefOrInRange(Mask[i], 0, 4))
3645 if (VT == MVT::v16i16) {
3646 // Upper quadword copied in order.
3647 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3650 // Lower quadword shuffled.
3651 for (unsigned i = 8; i != 12; ++i)
3652 if (!isUndefOrInRange(Mask[i], 8, 12))
3659 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
3660 /// is suitable for input to PALIGNR.
3661 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
3662 const X86Subtarget *Subtarget) {
3663 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
3664 (VT.is256BitVector() && !Subtarget->hasInt256()))
3667 unsigned NumElts = VT.getVectorNumElements();
3668 unsigned NumLanes = VT.is512BitVector() ? 1: VT.getSizeInBits()/128;
3669 unsigned NumLaneElts = NumElts/NumLanes;
3671 // Do not handle 64-bit element shuffles with palignr.
3672 if (NumLaneElts == 2)
3675 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3677 for (i = 0; i != NumLaneElts; ++i) {
3682 // Lane is all undef, go to next lane
3683 if (i == NumLaneElts)
3686 int Start = Mask[i+l];
3688 // Make sure its in this lane in one of the sources
3689 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3690 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3693 // If not lane 0, then we must match lane 0
3694 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3697 // Correct second source to be contiguous with first source
3698 if (Start >= (int)NumElts)
3699 Start -= NumElts - NumLaneElts;
3701 // Make sure we're shifting in the right direction.
3702 if (Start <= (int)(i+l))
3707 // Check the rest of the elements to see if they are consecutive.
3708 for (++i; i != NumLaneElts; ++i) {
3709 int Idx = Mask[i+l];
3711 // Make sure its in this lane
3712 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3713 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3716 // If not lane 0, then we must match lane 0
3717 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3720 if (Idx >= (int)NumElts)
3721 Idx -= NumElts - NumLaneElts;
3723 if (!isUndefOrEqual(Idx, Start+i))
3732 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3733 /// the two vector operands have swapped position.
3734 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
3735 unsigned NumElems) {
3736 for (unsigned i = 0; i != NumElems; ++i) {
3740 else if (idx < (int)NumElems)
3741 Mask[i] = idx + NumElems;
3743 Mask[i] = idx - NumElems;
3747 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
3748 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
3749 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
3750 /// reverse of what x86 shuffles want.
3751 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
3753 unsigned NumElems = VT.getVectorNumElements();
3754 unsigned NumLanes = VT.getSizeInBits()/128;
3755 unsigned NumLaneElems = NumElems/NumLanes;
3757 if (NumLaneElems != 2 && NumLaneElems != 4)
3760 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3761 bool symetricMaskRequired =
3762 (VT.getSizeInBits() >= 256) && (EltSize == 32);
3764 // VSHUFPSY divides the resulting vector into 4 chunks.
3765 // The sources are also splitted into 4 chunks, and each destination
3766 // chunk must come from a different source chunk.
3768 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
3769 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
3771 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
3772 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
3774 // VSHUFPDY divides the resulting vector into 4 chunks.
3775 // The sources are also splitted into 4 chunks, and each destination
3776 // chunk must come from a different source chunk.
3778 // SRC1 => X3 X2 X1 X0
3779 // SRC2 => Y3 Y2 Y1 Y0
3781 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
3783 SmallVector<int, 4> MaskVal(NumLaneElems, -1);
3784 unsigned HalfLaneElems = NumLaneElems/2;
3785 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
3786 for (unsigned i = 0; i != NumLaneElems; ++i) {
3787 int Idx = Mask[i+l];
3788 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
3789 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
3791 // For VSHUFPSY, the mask of the second half must be the same as the
3792 // first but with the appropriate offsets. This works in the same way as
3793 // VPERMILPS works with masks.
3794 if (!symetricMaskRequired || Idx < 0)
3796 if (MaskVal[i] < 0) {
3797 MaskVal[i] = Idx - l;
3800 if ((signed)(Idx - l) != MaskVal[i])
3808 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3809 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3810 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
3811 if (!VT.is128BitVector())
3814 unsigned NumElems = VT.getVectorNumElements();
3819 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3820 return isUndefOrEqual(Mask[0], 6) &&
3821 isUndefOrEqual(Mask[1], 7) &&
3822 isUndefOrEqual(Mask[2], 2) &&
3823 isUndefOrEqual(Mask[3], 3);
3826 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3827 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3829 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
3830 if (!VT.is128BitVector())
3833 unsigned NumElems = VT.getVectorNumElements();
3838 return isUndefOrEqual(Mask[0], 2) &&
3839 isUndefOrEqual(Mask[1], 3) &&
3840 isUndefOrEqual(Mask[2], 2) &&
3841 isUndefOrEqual(Mask[3], 3);
3844 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3845 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3846 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
3847 if (!VT.is128BitVector())
3850 unsigned NumElems = VT.getVectorNumElements();
3852 if (NumElems != 2 && NumElems != 4)
3855 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3856 if (!isUndefOrEqual(Mask[i], i + NumElems))
3859 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
3860 if (!isUndefOrEqual(Mask[i], i))
3866 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3867 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3868 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
3869 if (!VT.is128BitVector())
3872 unsigned NumElems = VT.getVectorNumElements();
3874 if (NumElems != 2 && NumElems != 4)
3877 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3878 if (!isUndefOrEqual(Mask[i], i))
3881 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3882 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
3889 // Some special combinations that can be optimized.
3892 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
3893 SelectionDAG &DAG) {
3894 MVT VT = SVOp->getSimpleValueType(0);
3897 if (VT != MVT::v8i32 && VT != MVT::v8f32)
3900 ArrayRef<int> Mask = SVOp->getMask();
3902 // These are the special masks that may be optimized.
3903 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
3904 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
3905 bool MatchEvenMask = true;
3906 bool MatchOddMask = true;
3907 for (int i=0; i<8; ++i) {
3908 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
3909 MatchEvenMask = false;
3910 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
3911 MatchOddMask = false;
3914 if (!MatchEvenMask && !MatchOddMask)
3917 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
3919 SDValue Op0 = SVOp->getOperand(0);
3920 SDValue Op1 = SVOp->getOperand(1);
3922 if (MatchEvenMask) {
3923 // Shift the second operand right to 32 bits.
3924 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
3925 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
3927 // Shift the first operand left to 32 bits.
3928 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
3929 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
3931 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
3932 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
3935 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
3936 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
3937 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
3938 bool HasInt256, bool V2IsSplat = false) {
3940 assert(VT.getSizeInBits() >= 128 &&
3941 "Unsupported vector type for unpckl");
3943 // AVX defines UNPCK* to operate independently on 128-bit lanes.
3945 unsigned NumOf256BitLanes;
3946 unsigned NumElts = VT.getVectorNumElements();
3947 if (VT.is256BitVector()) {
3948 if (NumElts != 4 && NumElts != 8 &&
3949 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
3952 NumOf256BitLanes = 1;
3953 } else if (VT.is512BitVector()) {
3954 assert(VT.getScalarType().getSizeInBits() >= 32 &&
3955 "Unsupported vector type for unpckh");
3957 NumOf256BitLanes = 2;
3960 NumOf256BitLanes = 1;
3963 unsigned NumEltsInStride = NumElts/NumOf256BitLanes;
3964 unsigned NumLaneElts = NumEltsInStride/NumLanes;
3966 for (unsigned l256 = 0; l256 < NumOf256BitLanes; l256 += 1) {
3967 for (unsigned l = 0; l != NumEltsInStride; l += NumLaneElts) {
3968 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
3969 int BitI = Mask[l256*NumEltsInStride+l+i];
3970 int BitI1 = Mask[l256*NumEltsInStride+l+i+1];
3971 if (!isUndefOrEqual(BitI, j+l256*NumElts))
3973 if (V2IsSplat && !isUndefOrEqual(BitI1, NumElts))
3975 if (!isUndefOrEqual(BitI1, j+l256*NumElts+NumEltsInStride))
3983 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
3984 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
3985 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
3986 bool HasInt256, bool V2IsSplat = false) {
3987 assert(VT.getSizeInBits() >= 128 &&
3988 "Unsupported vector type for unpckh");
3990 // AVX defines UNPCK* to operate independently on 128-bit lanes.
3992 unsigned NumOf256BitLanes;
3993 unsigned NumElts = VT.getVectorNumElements();
3994 if (VT.is256BitVector()) {
3995 if (NumElts != 4 && NumElts != 8 &&
3996 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
3999 NumOf256BitLanes = 1;
4000 } else if (VT.is512BitVector()) {
4001 assert(VT.getScalarType().getSizeInBits() >= 32 &&
4002 "Unsupported vector type for unpckh");
4004 NumOf256BitLanes = 2;
4007 NumOf256BitLanes = 1;
4010 unsigned NumEltsInStride = NumElts/NumOf256BitLanes;
4011 unsigned NumLaneElts = NumEltsInStride/NumLanes;
4013 for (unsigned l256 = 0; l256 < NumOf256BitLanes; l256 += 1) {
4014 for (unsigned l = 0; l != NumEltsInStride; l += NumLaneElts) {
4015 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4016 int BitI = Mask[l256*NumEltsInStride+l+i];
4017 int BitI1 = Mask[l256*NumEltsInStride+l+i+1];
4018 if (!isUndefOrEqual(BitI, j+l256*NumElts))
4020 if (V2IsSplat && !isUndefOrEqual(BitI1, NumElts))
4022 if (!isUndefOrEqual(BitI1, j+l256*NumElts+NumEltsInStride))
4030 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
4031 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
4033 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4034 unsigned NumElts = VT.getVectorNumElements();
4035 bool Is256BitVec = VT.is256BitVector();
4037 if (VT.is512BitVector())
4039 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4040 "Unsupported vector type for unpckh");
4042 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
4043 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4046 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
4047 // FIXME: Need a better way to get rid of this, there's no latency difference
4048 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
4049 // the former later. We should also remove the "_undef" special mask.
4050 if (NumElts == 4 && Is256BitVec)
4053 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4054 // independently on 128-bit lanes.
4055 unsigned NumLanes = VT.getSizeInBits()/128;
4056 unsigned NumLaneElts = NumElts/NumLanes;
4058 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4059 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4060 int BitI = Mask[l+i];
4061 int BitI1 = Mask[l+i+1];
4063 if (!isUndefOrEqual(BitI, j))
4065 if (!isUndefOrEqual(BitI1, j))
4073 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
4074 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
4076 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4077 unsigned NumElts = VT.getVectorNumElements();
4079 if (VT.is512BitVector())
4082 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4083 "Unsupported vector type for unpckh");
4085 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4086 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4089 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4090 // independently on 128-bit lanes.
4091 unsigned NumLanes = VT.getSizeInBits()/128;
4092 unsigned NumLaneElts = NumElts/NumLanes;
4094 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4095 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4096 int BitI = Mask[l+i];
4097 int BitI1 = Mask[l+i+1];
4098 if (!isUndefOrEqual(BitI, j))
4100 if (!isUndefOrEqual(BitI1, j))
4107 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4108 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4109 /// MOVSD, and MOVD, i.e. setting the lowest element.
4110 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4111 if (VT.getVectorElementType().getSizeInBits() < 32)
4113 if (!VT.is128BitVector())
4116 unsigned NumElts = VT.getVectorNumElements();
4118 if (!isUndefOrEqual(Mask[0], NumElts))
4121 for (unsigned i = 1; i != NumElts; ++i)
4122 if (!isUndefOrEqual(Mask[i], i))
4128 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4129 /// as permutations between 128-bit chunks or halves. As an example: this
4131 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4132 /// The first half comes from the second half of V1 and the second half from the
4133 /// the second half of V2.
4134 static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4135 if (!HasFp256 || !VT.is256BitVector())
4138 // The shuffle result is divided into half A and half B. In total the two
4139 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4140 // B must come from C, D, E or F.
4141 unsigned HalfSize = VT.getVectorNumElements()/2;
4142 bool MatchA = false, MatchB = false;
4144 // Check if A comes from one of C, D, E, F.
4145 for (unsigned Half = 0; Half != 4; ++Half) {
4146 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4152 // Check if B comes from one of C, D, E, F.
4153 for (unsigned Half = 0; Half != 4; ++Half) {
4154 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4160 return MatchA && MatchB;
4163 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4164 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4165 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4166 MVT VT = SVOp->getSimpleValueType(0);
4168 unsigned HalfSize = VT.getVectorNumElements()/2;
4170 unsigned FstHalf = 0, SndHalf = 0;
4171 for (unsigned i = 0; i < HalfSize; ++i) {
4172 if (SVOp->getMaskElt(i) > 0) {
4173 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4177 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4178 if (SVOp->getMaskElt(i) > 0) {
4179 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4184 return (FstHalf | (SndHalf << 4));
4187 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4188 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
4189 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4193 unsigned NumElts = VT.getVectorNumElements();
4195 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4196 for (unsigned i = 0; i != NumElts; ++i) {
4199 Imm8 |= Mask[i] << (i*2);
4204 unsigned LaneSize = 4;
4205 SmallVector<int, 4> MaskVal(LaneSize, -1);
4207 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4208 for (unsigned i = 0; i != LaneSize; ++i) {
4209 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4213 if (MaskVal[i] < 0) {
4214 MaskVal[i] = Mask[i+l] - l;
4215 Imm8 |= MaskVal[i] << (i*2);
4218 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4225 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4226 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4227 /// Note that VPERMIL mask matching is different depending whether theunderlying
4228 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4229 /// to the same elements of the low, but to the higher half of the source.
4230 /// In VPERMILPD the two lanes could be shuffled independently of each other
4231 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4232 static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
4233 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4234 if (VT.getSizeInBits() < 256 || EltSize < 32)
4236 bool symetricMaskRequired = (EltSize == 32);
4237 unsigned NumElts = VT.getVectorNumElements();
4239 unsigned NumLanes = VT.getSizeInBits()/128;
4240 unsigned LaneSize = NumElts/NumLanes;
4241 // 2 or 4 elements in one lane
4243 SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
4244 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4245 for (unsigned i = 0; i != LaneSize; ++i) {
4246 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4248 if (symetricMaskRequired) {
4249 if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) {
4250 ExpectedMaskVal[i] = Mask[i+l] - l;
4253 if (!isUndefOrEqual(Mask[i+l], ExpectedMaskVal[i]+l))
4261 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4262 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4263 /// element of vector 2 and the other elements to come from vector 1 in order.
4264 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4265 bool V2IsSplat = false, bool V2IsUndef = false) {
4266 if (!VT.is128BitVector())
4269 unsigned NumOps = VT.getVectorNumElements();
4270 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4273 if (!isUndefOrEqual(Mask[0], 0))
4276 for (unsigned i = 1; i != NumOps; ++i)
4277 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4278 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4279 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4285 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4286 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4287 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4288 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4289 const X86Subtarget *Subtarget) {
4290 if (!Subtarget->hasSSE3())
4293 unsigned NumElems = VT.getVectorNumElements();
4295 if ((VT.is128BitVector() && NumElems != 4) ||
4296 (VT.is256BitVector() && NumElems != 8) ||
4297 (VT.is512BitVector() && NumElems != 16))
4300 // "i+1" is the value the indexed mask element must have
4301 for (unsigned i = 0; i != NumElems; i += 2)
4302 if (!isUndefOrEqual(Mask[i], i+1) ||
4303 !isUndefOrEqual(Mask[i+1], i+1))
4309 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4310 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4311 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4312 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4313 const X86Subtarget *Subtarget) {
4314 if (!Subtarget->hasSSE3())
4317 unsigned NumElems = VT.getVectorNumElements();
4319 if ((VT.is128BitVector() && NumElems != 4) ||
4320 (VT.is256BitVector() && NumElems != 8) ||
4321 (VT.is512BitVector() && NumElems != 16))
4324 // "i" is the value the indexed mask element must have
4325 for (unsigned i = 0; i != NumElems; i += 2)
4326 if (!isUndefOrEqual(Mask[i], i) ||
4327 !isUndefOrEqual(Mask[i+1], i))
4333 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4334 /// specifies a shuffle of elements that is suitable for input to 256-bit
4335 /// version of MOVDDUP.
4336 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4337 if (!HasFp256 || !VT.is256BitVector())
4340 unsigned NumElts = VT.getVectorNumElements();
4344 for (unsigned i = 0; i != NumElts/2; ++i)
4345 if (!isUndefOrEqual(Mask[i], 0))
4347 for (unsigned i = NumElts/2; i != NumElts; ++i)
4348 if (!isUndefOrEqual(Mask[i], NumElts/2))
4353 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4354 /// specifies a shuffle of elements that is suitable for input to 128-bit
4355 /// version of MOVDDUP.
4356 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4357 if (!VT.is128BitVector())
4360 unsigned e = VT.getVectorNumElements() / 2;
4361 for (unsigned i = 0; i != e; ++i)
4362 if (!isUndefOrEqual(Mask[i], i))
4364 for (unsigned i = 0; i != e; ++i)
4365 if (!isUndefOrEqual(Mask[e+i], i))
4370 /// isVEXTRACTIndex - Return true if the specified
4371 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4372 /// suitable for instruction that extract 128 or 256 bit vectors
4373 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4374 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4375 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4378 // The index should be aligned on a vecWidth-bit boundary.
4380 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4382 MVT VT = N->getSimpleValueType(0);
4383 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4384 bool Result = (Index * ElSize) % vecWidth == 0;
4389 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4390 /// operand specifies a subvector insert that is suitable for input to
4391 /// insertion of 128 or 256-bit subvectors
4392 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4393 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4394 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4396 // The index should be aligned on a vecWidth-bit boundary.
4398 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4400 MVT VT = N->getSimpleValueType(0);
4401 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4402 bool Result = (Index * ElSize) % vecWidth == 0;
4407 bool X86::isVINSERT128Index(SDNode *N) {
4408 return isVINSERTIndex(N, 128);
4411 bool X86::isVINSERT256Index(SDNode *N) {
4412 return isVINSERTIndex(N, 256);
4415 bool X86::isVEXTRACT128Index(SDNode *N) {
4416 return isVEXTRACTIndex(N, 128);
4419 bool X86::isVEXTRACT256Index(SDNode *N) {
4420 return isVEXTRACTIndex(N, 256);
4423 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4424 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4425 /// Handles 128-bit and 256-bit.
4426 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4427 MVT VT = N->getSimpleValueType(0);
4429 assert((VT.getSizeInBits() >= 128) &&
4430 "Unsupported vector type for PSHUF/SHUFP");
4432 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4433 // independently on 128-bit lanes.
4434 unsigned NumElts = VT.getVectorNumElements();
4435 unsigned NumLanes = VT.getSizeInBits()/128;
4436 unsigned NumLaneElts = NumElts/NumLanes;
4438 assert((NumLaneElts == 2 || NumLaneElts == 4 || NumLaneElts == 8) &&
4439 "Only supports 2, 4 or 8 elements per lane");
4441 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0;
4443 for (unsigned i = 0; i != NumElts; ++i) {
4444 int Elt = N->getMaskElt(i);
4445 if (Elt < 0) continue;
4446 Elt &= NumLaneElts - 1;
4447 unsigned ShAmt = (i << Shift) % 8;
4448 Mask |= Elt << ShAmt;
4454 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4455 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4456 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4457 MVT VT = N->getSimpleValueType(0);
4459 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4460 "Unsupported vector type for PSHUFHW");
4462 unsigned NumElts = VT.getVectorNumElements();
4465 for (unsigned l = 0; l != NumElts; l += 8) {
4466 // 8 nodes per lane, but we only care about the last 4.
4467 for (unsigned i = 0; i < 4; ++i) {
4468 int Elt = N->getMaskElt(l+i+4);
4469 if (Elt < 0) continue;
4470 Elt &= 0x3; // only 2-bits.
4471 Mask |= Elt << (i * 2);
4478 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4479 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4480 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4481 MVT VT = N->getSimpleValueType(0);
4483 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4484 "Unsupported vector type for PSHUFHW");
4486 unsigned NumElts = VT.getVectorNumElements();
4489 for (unsigned l = 0; l != NumElts; l += 8) {
4490 // 8 nodes per lane, but we only care about the first 4.
4491 for (unsigned i = 0; i < 4; ++i) {
4492 int Elt = N->getMaskElt(l+i);
4493 if (Elt < 0) continue;
4494 Elt &= 0x3; // only 2-bits
4495 Mask |= Elt << (i * 2);
4502 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
4503 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
4504 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4505 MVT VT = SVOp->getSimpleValueType(0);
4506 unsigned EltSize = VT.is512BitVector() ? 1 :
4507 VT.getVectorElementType().getSizeInBits() >> 3;
4509 unsigned NumElts = VT.getVectorNumElements();
4510 unsigned NumLanes = VT.is512BitVector() ? 1 : VT.getSizeInBits()/128;
4511 unsigned NumLaneElts = NumElts/NumLanes;
4515 for (i = 0; i != NumElts; ++i) {
4516 Val = SVOp->getMaskElt(i);
4520 if (Val >= (int)NumElts)
4521 Val -= NumElts - NumLaneElts;
4523 assert(Val - i > 0 && "PALIGNR imm should be positive");
4524 return (Val - i) * EltSize;
4527 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4528 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4529 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4530 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4533 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4535 MVT VecVT = N->getOperand(0).getSimpleValueType();
4536 MVT ElVT = VecVT.getVectorElementType();
4538 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4539 return Index / NumElemsPerChunk;
4542 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4543 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4544 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4545 llvm_unreachable("Illegal insert subvector for VINSERT");
4548 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4550 MVT VecVT = N->getSimpleValueType(0);
4551 MVT ElVT = VecVT.getVectorElementType();
4553 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4554 return Index / NumElemsPerChunk;
4557 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4558 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4559 /// and VINSERTI128 instructions.
4560 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4561 return getExtractVEXTRACTImmediate(N, 128);
4564 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4565 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4566 /// and VINSERTI64x4 instructions.
4567 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4568 return getExtractVEXTRACTImmediate(N, 256);
4571 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4572 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4573 /// and VINSERTI128 instructions.
4574 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4575 return getInsertVINSERTImmediate(N, 128);
4578 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4579 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4580 /// and VINSERTI64x4 instructions.
4581 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4582 return getInsertVINSERTImmediate(N, 256);
4585 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4587 bool X86::isZeroNode(SDValue Elt) {
4588 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Elt))
4589 return CN->isNullValue();
4590 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4591 return CFP->getValueAPF().isPosZero();
4595 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
4596 /// their permute mask.
4597 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
4598 SelectionDAG &DAG) {
4599 MVT VT = SVOp->getSimpleValueType(0);
4600 unsigned NumElems = VT.getVectorNumElements();
4601 SmallVector<int, 8> MaskVec;
4603 for (unsigned i = 0; i != NumElems; ++i) {
4604 int Idx = SVOp->getMaskElt(i);
4606 if (Idx < (int)NumElems)
4611 MaskVec.push_back(Idx);
4613 return DAG.getVectorShuffle(VT, SDLoc(SVOp), SVOp->getOperand(1),
4614 SVOp->getOperand(0), &MaskVec[0]);
4617 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4618 /// match movhlps. The lower half elements should come from upper half of
4619 /// V1 (and in order), and the upper half elements should come from the upper
4620 /// half of V2 (and in order).
4621 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
4622 if (!VT.is128BitVector())
4624 if (VT.getVectorNumElements() != 4)
4626 for (unsigned i = 0, e = 2; i != e; ++i)
4627 if (!isUndefOrEqual(Mask[i], i+2))
4629 for (unsigned i = 2; i != 4; ++i)
4630 if (!isUndefOrEqual(Mask[i], i+4))
4635 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4636 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4638 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
4639 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4641 N = N->getOperand(0).getNode();
4642 if (!ISD::isNON_EXTLoad(N))
4645 *LD = cast<LoadSDNode>(N);
4649 // Test whether the given value is a vector value which will be legalized
4651 static bool WillBeConstantPoolLoad(SDNode *N) {
4652 if (N->getOpcode() != ISD::BUILD_VECTOR)
4655 // Check for any non-constant elements.
4656 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4657 switch (N->getOperand(i).getNode()->getOpcode()) {
4659 case ISD::ConstantFP:
4666 // Vectors of all-zeros and all-ones are materialized with special
4667 // instructions rather than being loaded.
4668 return !ISD::isBuildVectorAllZeros(N) &&
4669 !ISD::isBuildVectorAllOnes(N);
4672 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4673 /// match movlp{s|d}. The lower half elements should come from lower half of
4674 /// V1 (and in order), and the upper half elements should come from the upper
4675 /// half of V2 (and in order). And since V1 will become the source of the
4676 /// MOVLP, it must be either a vector load or a scalar load to vector.
4677 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
4678 ArrayRef<int> Mask, MVT VT) {
4679 if (!VT.is128BitVector())
4682 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
4684 // Is V2 is a vector load, don't do this transformation. We will try to use
4685 // load folding shufps op.
4686 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
4689 unsigned NumElems = VT.getVectorNumElements();
4691 if (NumElems != 2 && NumElems != 4)
4693 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4694 if (!isUndefOrEqual(Mask[i], i))
4696 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4697 if (!isUndefOrEqual(Mask[i], i+NumElems))
4702 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
4704 static bool isSplatVector(SDNode *N) {
4705 if (N->getOpcode() != ISD::BUILD_VECTOR)
4708 SDValue SplatValue = N->getOperand(0);
4709 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
4710 if (N->getOperand(i) != SplatValue)
4715 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
4716 /// to an zero vector.
4717 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
4718 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
4719 SDValue V1 = N->getOperand(0);
4720 SDValue V2 = N->getOperand(1);
4721 unsigned NumElems = N->getValueType(0).getVectorNumElements();
4722 for (unsigned i = 0; i != NumElems; ++i) {
4723 int Idx = N->getMaskElt(i);
4724 if (Idx >= (int)NumElems) {
4725 unsigned Opc = V2.getOpcode();
4726 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4728 if (Opc != ISD::BUILD_VECTOR ||
4729 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
4731 } else if (Idx >= 0) {
4732 unsigned Opc = V1.getOpcode();
4733 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
4735 if (Opc != ISD::BUILD_VECTOR ||
4736 !X86::isZeroNode(V1.getOperand(Idx)))
4743 /// getZeroVector - Returns a vector of specified type with all zero elements.
4745 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4746 SelectionDAG &DAG, SDLoc dl) {
4747 assert(VT.isVector() && "Expected a vector type");
4749 // Always build SSE zero vectors as <4 x i32> bitcasted
4750 // to their dest type. This ensures they get CSE'd.
4752 if (VT.is128BitVector()) { // SSE
4753 if (Subtarget->hasSSE2()) { // SSE2
4754 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4755 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4757 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4758 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4760 } else if (VT.is256BitVector()) { // AVX
4761 if (Subtarget->hasInt256()) { // AVX2
4762 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4763 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4764 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops,
4765 array_lengthof(Ops));
4767 // 256-bit logic and arithmetic instructions in AVX are all
4768 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4769 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4770 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4771 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops,
4772 array_lengthof(Ops));
4774 } else if (VT.is512BitVector()) { // AVX-512
4775 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4776 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4777 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4778 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops, 16);
4780 llvm_unreachable("Unexpected vector type");
4782 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4785 /// getOnesVector - Returns a vector of specified type with all bits set.
4786 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4787 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4788 /// Then bitcast to their original type, ensuring they get CSE'd.
4789 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
4791 assert(VT.isVector() && "Expected a vector type");
4793 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
4795 if (VT.is256BitVector()) {
4796 if (HasInt256) { // AVX2
4797 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4798 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops,
4799 array_lengthof(Ops));
4801 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4802 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4804 } else if (VT.is128BitVector()) {
4805 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4807 llvm_unreachable("Unexpected vector type");
4809 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4812 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
4813 /// that point to V2 points to its first element.
4814 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
4815 for (unsigned i = 0; i != NumElems; ++i) {
4816 if (Mask[i] > (int)NumElems) {
4822 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4823 /// operation of specified width.
4824 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
4826 unsigned NumElems = VT.getVectorNumElements();
4827 SmallVector<int, 8> Mask;
4828 Mask.push_back(NumElems);
4829 for (unsigned i = 1; i != NumElems; ++i)
4831 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4834 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4835 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4837 unsigned NumElems = VT.getVectorNumElements();
4838 SmallVector<int, 8> Mask;
4839 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4841 Mask.push_back(i + NumElems);
4843 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4846 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4847 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4849 unsigned NumElems = VT.getVectorNumElements();
4850 SmallVector<int, 8> Mask;
4851 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4852 Mask.push_back(i + Half);
4853 Mask.push_back(i + NumElems + Half);
4855 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4858 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
4859 // a generic shuffle instruction because the target has no such instructions.
4860 // Generate shuffles which repeat i16 and i8 several times until they can be
4861 // represented by v4f32 and then be manipulated by target suported shuffles.
4862 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
4863 MVT VT = V.getSimpleValueType();
4864 int NumElems = VT.getVectorNumElements();
4867 while (NumElems > 4) {
4868 if (EltNo < NumElems/2) {
4869 V = getUnpackl(DAG, dl, VT, V, V);
4871 V = getUnpackh(DAG, dl, VT, V, V);
4872 EltNo -= NumElems/2;
4879 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
4880 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
4881 MVT VT = V.getSimpleValueType();
4884 if (VT.is128BitVector()) {
4885 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
4886 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
4887 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
4889 } else if (VT.is256BitVector()) {
4890 // To use VPERMILPS to splat scalars, the second half of indicies must
4891 // refer to the higher part, which is a duplication of the lower one,
4892 // because VPERMILPS can only handle in-lane permutations.
4893 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
4894 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
4896 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
4897 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
4900 llvm_unreachable("Vector size not supported");
4902 return DAG.getNode(ISD::BITCAST, dl, VT, V);
4905 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
4906 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
4907 MVT SrcVT = SV->getSimpleValueType(0);
4908 SDValue V1 = SV->getOperand(0);
4911 int EltNo = SV->getSplatIndex();
4912 int NumElems = SrcVT.getVectorNumElements();
4913 bool Is256BitVec = SrcVT.is256BitVector();
4915 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
4916 "Unknown how to promote splat for type");
4918 // Extract the 128-bit part containing the splat element and update
4919 // the splat element index when it refers to the higher register.
4921 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
4922 if (EltNo >= NumElems/2)
4923 EltNo -= NumElems/2;
4926 // All i16 and i8 vector types can't be used directly by a generic shuffle
4927 // instruction because the target has no such instruction. Generate shuffles
4928 // which repeat i16 and i8 several times until they fit in i32, and then can
4929 // be manipulated by target suported shuffles.
4930 MVT EltVT = SrcVT.getVectorElementType();
4931 if (EltVT == MVT::i8 || EltVT == MVT::i16)
4932 V1 = PromoteSplati8i16(V1, DAG, EltNo);
4934 // Recreate the 256-bit vector and place the same 128-bit vector
4935 // into the low and high part. This is necessary because we want
4936 // to use VPERM* to shuffle the vectors
4938 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
4941 return getLegalSplat(DAG, V1, EltNo);
4944 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4945 /// vector of zero or undef vector. This produces a shuffle where the low
4946 /// element of V2 is swizzled into the zero/undef vector, landing at element
4947 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4948 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4950 const X86Subtarget *Subtarget,
4951 SelectionDAG &DAG) {
4952 MVT VT = V2.getSimpleValueType();
4954 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
4955 unsigned NumElems = VT.getVectorNumElements();
4956 SmallVector<int, 16> MaskVec;
4957 for (unsigned i = 0; i != NumElems; ++i)
4958 // If this is the insertion idx, put the low elt of V2 here.
4959 MaskVec.push_back(i == Idx ? NumElems : i);
4960 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
4963 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
4964 /// target specific opcode. Returns true if the Mask could be calculated.
4965 /// Sets IsUnary to true if only uses one source.
4966 static bool getTargetShuffleMask(SDNode *N, MVT VT,
4967 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4968 unsigned NumElems = VT.getVectorNumElements();
4972 switch(N->getOpcode()) {
4974 ImmN = N->getOperand(N->getNumOperands()-1);
4975 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4977 case X86ISD::UNPCKH:
4978 DecodeUNPCKHMask(VT, Mask);
4980 case X86ISD::UNPCKL:
4981 DecodeUNPCKLMask(VT, Mask);
4983 case X86ISD::MOVHLPS:
4984 DecodeMOVHLPSMask(NumElems, Mask);
4986 case X86ISD::MOVLHPS:
4987 DecodeMOVLHPSMask(NumElems, Mask);
4989 case X86ISD::PALIGNR:
4990 ImmN = N->getOperand(N->getNumOperands()-1);
4991 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4993 case X86ISD::PSHUFD:
4994 case X86ISD::VPERMILP:
4995 ImmN = N->getOperand(N->getNumOperands()-1);
4996 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4999 case X86ISD::PSHUFHW:
5000 ImmN = N->getOperand(N->getNumOperands()-1);
5001 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5004 case X86ISD::PSHUFLW:
5005 ImmN = N->getOperand(N->getNumOperands()-1);
5006 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5009 case X86ISD::VPERMI:
5010 ImmN = N->getOperand(N->getNumOperands()-1);
5011 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5015 case X86ISD::MOVSD: {
5016 // The index 0 always comes from the first element of the second source,
5017 // this is why MOVSS and MOVSD are used in the first place. The other
5018 // elements come from the other positions of the first source vector
5019 Mask.push_back(NumElems);
5020 for (unsigned i = 1; i != NumElems; ++i) {
5025 case X86ISD::VPERM2X128:
5026 ImmN = N->getOperand(N->getNumOperands()-1);
5027 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5028 if (Mask.empty()) return false;
5030 case X86ISD::MOVDDUP:
5031 case X86ISD::MOVLHPD:
5032 case X86ISD::MOVLPD:
5033 case X86ISD::MOVLPS:
5034 case X86ISD::MOVSHDUP:
5035 case X86ISD::MOVSLDUP:
5036 // Not yet implemented
5038 default: llvm_unreachable("unknown target shuffle node");
5044 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
5045 /// element of the result of the vector shuffle.
5046 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
5049 return SDValue(); // Limit search depth.
5051 SDValue V = SDValue(N, 0);
5052 EVT VT = V.getValueType();
5053 unsigned Opcode = V.getOpcode();
5055 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5056 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5057 int Elt = SV->getMaskElt(Index);
5060 return DAG.getUNDEF(VT.getVectorElementType());
5062 unsigned NumElems = VT.getVectorNumElements();
5063 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5064 : SV->getOperand(1);
5065 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5068 // Recurse into target specific vector shuffles to find scalars.
5069 if (isTargetShuffle(Opcode)) {
5070 MVT ShufVT = V.getSimpleValueType();
5071 unsigned NumElems = ShufVT.getVectorNumElements();
5072 SmallVector<int, 16> ShuffleMask;
5075 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5078 int Elt = ShuffleMask[Index];
5080 return DAG.getUNDEF(ShufVT.getVectorElementType());
5082 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5084 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5088 // Actual nodes that may contain scalar elements
5089 if (Opcode == ISD::BITCAST) {
5090 V = V.getOperand(0);
5091 EVT SrcVT = V.getValueType();
5092 unsigned NumElems = VT.getVectorNumElements();
5094 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5098 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5099 return (Index == 0) ? V.getOperand(0)
5100 : DAG.getUNDEF(VT.getVectorElementType());
5102 if (V.getOpcode() == ISD::BUILD_VECTOR)
5103 return V.getOperand(Index);
5108 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5109 /// shuffle operation which come from a consecutively from a zero. The
5110 /// search can start in two different directions, from left or right.
5111 /// We count undefs as zeros until PreferredNum is reached.
5112 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5113 unsigned NumElems, bool ZerosFromLeft,
5115 unsigned PreferredNum = -1U) {
5116 unsigned NumZeros = 0;
5117 for (unsigned i = 0; i != NumElems; ++i) {
5118 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5119 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5123 if (X86::isZeroNode(Elt))
5125 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5126 NumZeros = std::min(NumZeros + 1, PreferredNum);
5134 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5135 /// correspond consecutively to elements from one of the vector operands,
5136 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5138 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5139 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5140 unsigned NumElems, unsigned &OpNum) {
5141 bool SeenV1 = false;
5142 bool SeenV2 = false;
5144 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5145 int Idx = SVOp->getMaskElt(i);
5146 // Ignore undef indicies
5150 if (Idx < (int)NumElems)
5155 // Only accept consecutive elements from the same vector
5156 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5160 OpNum = SeenV1 ? 0 : 1;
5164 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5165 /// logical left shift of a vector.
5166 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5167 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5169 SVOp->getSimpleValueType(0).getVectorNumElements();
5170 unsigned NumZeros = getNumOfConsecutiveZeros(
5171 SVOp, NumElems, false /* check zeros from right */, DAG,
5172 SVOp->getMaskElt(0));
5178 // Considering the elements in the mask that are not consecutive zeros,
5179 // check if they consecutively come from only one of the source vectors.
5181 // V1 = {X, A, B, C} 0
5183 // vector_shuffle V1, V2 <1, 2, 3, X>
5185 if (!isShuffleMaskConsecutive(SVOp,
5186 0, // Mask Start Index
5187 NumElems-NumZeros, // Mask End Index(exclusive)
5188 NumZeros, // Where to start looking in the src vector
5189 NumElems, // Number of elements in vector
5190 OpSrc)) // Which source operand ?
5195 ShVal = SVOp->getOperand(OpSrc);
5199 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5200 /// logical left shift of a vector.
5201 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5202 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5204 SVOp->getSimpleValueType(0).getVectorNumElements();
5205 unsigned NumZeros = getNumOfConsecutiveZeros(
5206 SVOp, NumElems, true /* check zeros from left */, DAG,
5207 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5213 // Considering the elements in the mask that are not consecutive zeros,
5214 // check if they consecutively come from only one of the source vectors.
5216 // 0 { A, B, X, X } = V2
5218 // vector_shuffle V1, V2 <X, X, 4, 5>
5220 if (!isShuffleMaskConsecutive(SVOp,
5221 NumZeros, // Mask Start Index
5222 NumElems, // Mask End Index(exclusive)
5223 0, // Where to start looking in the src vector
5224 NumElems, // Number of elements in vector
5225 OpSrc)) // Which source operand ?
5230 ShVal = SVOp->getOperand(OpSrc);
5234 /// isVectorShift - Returns true if the shuffle can be implemented as a
5235 /// logical left or right shift of a vector.
5236 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5237 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5238 // Although the logic below support any bitwidth size, there are no
5239 // shift instructions which handle more than 128-bit vectors.
5240 if (!SVOp->getSimpleValueType(0).is128BitVector())
5243 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5244 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5250 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5252 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5253 unsigned NumNonZero, unsigned NumZero,
5255 const X86Subtarget* Subtarget,
5256 const TargetLowering &TLI) {
5263 for (unsigned i = 0; i < 16; ++i) {
5264 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5265 if (ThisIsNonZero && First) {
5267 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5269 V = DAG.getUNDEF(MVT::v8i16);
5274 SDValue ThisElt(0, 0), LastElt(0, 0);
5275 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5276 if (LastIsNonZero) {
5277 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5278 MVT::i16, Op.getOperand(i-1));
5280 if (ThisIsNonZero) {
5281 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5282 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5283 ThisElt, DAG.getConstant(8, MVT::i8));
5285 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5289 if (ThisElt.getNode())
5290 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5291 DAG.getIntPtrConstant(i/2));
5295 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5298 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5300 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5301 unsigned NumNonZero, unsigned NumZero,
5303 const X86Subtarget* Subtarget,
5304 const TargetLowering &TLI) {
5311 for (unsigned i = 0; i < 8; ++i) {
5312 bool isNonZero = (NonZeros & (1 << i)) != 0;
5316 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5318 V = DAG.getUNDEF(MVT::v8i16);
5321 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5322 MVT::v8i16, V, Op.getOperand(i),
5323 DAG.getIntPtrConstant(i));
5330 /// getVShift - Return a vector logical shift node.
5332 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5333 unsigned NumBits, SelectionDAG &DAG,
5334 const TargetLowering &TLI, SDLoc dl) {
5335 assert(VT.is128BitVector() && "Unknown type for VShift");
5336 EVT ShVT = MVT::v2i64;
5337 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5338 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5339 return DAG.getNode(ISD::BITCAST, dl, VT,
5340 DAG.getNode(Opc, dl, ShVT, SrcOp,
5341 DAG.getConstant(NumBits,
5342 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5346 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5348 // Check if the scalar load can be widened into a vector load. And if
5349 // the address is "base + cst" see if the cst can be "absorbed" into
5350 // the shuffle mask.
5351 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5352 SDValue Ptr = LD->getBasePtr();
5353 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5355 EVT PVT = LD->getValueType(0);
5356 if (PVT != MVT::i32 && PVT != MVT::f32)
5361 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5362 FI = FINode->getIndex();
5364 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5365 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5366 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5367 Offset = Ptr.getConstantOperandVal(1);
5368 Ptr = Ptr.getOperand(0);
5373 // FIXME: 256-bit vector instructions don't require a strict alignment,
5374 // improve this code to support it better.
5375 unsigned RequiredAlign = VT.getSizeInBits()/8;
5376 SDValue Chain = LD->getChain();
5377 // Make sure the stack object alignment is at least 16 or 32.
5378 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5379 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5380 if (MFI->isFixedObjectIndex(FI)) {
5381 // Can't change the alignment. FIXME: It's possible to compute
5382 // the exact stack offset and reference FI + adjust offset instead.
5383 // If someone *really* cares about this. That's the way to implement it.
5386 MFI->setObjectAlignment(FI, RequiredAlign);
5390 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5391 // Ptr + (Offset & ~15).
5394 if ((Offset % RequiredAlign) & 3)
5396 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5398 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5399 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5401 int EltNo = (Offset - StartOffset) >> 2;
5402 unsigned NumElems = VT.getVectorNumElements();
5404 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5405 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5406 LD->getPointerInfo().getWithOffset(StartOffset),
5407 false, false, false, 0);
5409 SmallVector<int, 8> Mask;
5410 for (unsigned i = 0; i != NumElems; ++i)
5411 Mask.push_back(EltNo);
5413 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5419 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5420 /// vector of type 'VT', see if the elements can be replaced by a single large
5421 /// load which has the same value as a build_vector whose operands are 'elts'.
5423 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5425 /// FIXME: we'd also like to handle the case where the last elements are zero
5426 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5427 /// There's even a handy isZeroNode for that purpose.
5428 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
5429 SDLoc &DL, SelectionDAG &DAG) {
5430 EVT EltVT = VT.getVectorElementType();
5431 unsigned NumElems = Elts.size();
5433 LoadSDNode *LDBase = NULL;
5434 unsigned LastLoadedElt = -1U;
5436 // For each element in the initializer, see if we've found a load or an undef.
5437 // If we don't find an initial load element, or later load elements are
5438 // non-consecutive, bail out.
5439 for (unsigned i = 0; i < NumElems; ++i) {
5440 SDValue Elt = Elts[i];
5442 if (!Elt.getNode() ||
5443 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5446 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5448 LDBase = cast<LoadSDNode>(Elt.getNode());
5452 if (Elt.getOpcode() == ISD::UNDEF)
5455 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5456 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5461 // If we have found an entire vector of loads and undefs, then return a large
5462 // load of the entire vector width starting at the base pointer. If we found
5463 // consecutive loads for the low half, generate a vzext_load node.
5464 if (LastLoadedElt == NumElems - 1) {
5465 SDValue NewLd = SDValue();
5466 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
5467 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5468 LDBase->getPointerInfo(),
5469 LDBase->isVolatile(), LDBase->isNonTemporal(),
5470 LDBase->isInvariant(), 0);
5471 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5472 LDBase->getPointerInfo(),
5473 LDBase->isVolatile(), LDBase->isNonTemporal(),
5474 LDBase->isInvariant(), LDBase->getAlignment());
5476 if (LDBase->hasAnyUseOfValue(1)) {
5477 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5479 SDValue(NewLd.getNode(), 1));
5480 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5481 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5482 SDValue(NewLd.getNode(), 1));
5487 if (NumElems == 4 && LastLoadedElt == 1 &&
5488 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5489 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5490 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5492 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops,
5493 array_lengthof(Ops), MVT::i64,
5494 LDBase->getPointerInfo(),
5495 LDBase->getAlignment(),
5496 false/*isVolatile*/, true/*ReadMem*/,
5499 // Make sure the newly-created LOAD is in the same position as LDBase in
5500 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5501 // update uses of LDBase's output chain to use the TokenFactor.
5502 if (LDBase->hasAnyUseOfValue(1)) {
5503 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5504 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5505 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5506 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5507 SDValue(ResNode.getNode(), 1));
5510 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
5515 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
5516 /// to generate a splat value for the following cases:
5517 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
5518 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
5519 /// a scalar load, or a constant.
5520 /// The VBROADCAST node is returned when a pattern is found,
5521 /// or SDValue() otherwise.
5522 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
5523 SelectionDAG &DAG) {
5524 if (!Subtarget->hasFp256())
5527 MVT VT = Op.getSimpleValueType();
5530 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
5531 "Unsupported vector type for broadcast.");
5536 switch (Op.getOpcode()) {
5538 // Unknown pattern found.
5541 case ISD::BUILD_VECTOR: {
5542 // The BUILD_VECTOR node must be a splat.
5543 if (!isSplatVector(Op.getNode()))
5546 Ld = Op.getOperand(0);
5547 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5548 Ld.getOpcode() == ISD::ConstantFP);
5550 // The suspected load node has several users. Make sure that all
5551 // of its users are from the BUILD_VECTOR node.
5552 // Constants may have multiple users.
5553 if (!ConstSplatVal && !Ld->hasNUsesOfValue(VT.getVectorNumElements(), 0))
5558 case ISD::VECTOR_SHUFFLE: {
5559 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5561 // Shuffles must have a splat mask where the first element is
5563 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5566 SDValue Sc = Op.getOperand(0);
5567 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5568 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5570 if (!Subtarget->hasInt256())
5573 // Use the register form of the broadcast instruction available on AVX2.
5574 if (VT.getSizeInBits() >= 256)
5575 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5576 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5579 Ld = Sc.getOperand(0);
5580 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5581 Ld.getOpcode() == ISD::ConstantFP);
5583 // The scalar_to_vector node and the suspected
5584 // load node must have exactly one user.
5585 // Constants may have multiple users.
5587 // AVX-512 has register version of the broadcast
5588 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
5589 Ld.getValueType().getSizeInBits() >= 32;
5590 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
5597 bool IsGE256 = (VT.getSizeInBits() >= 256);
5599 // Handle the broadcasting a single constant scalar from the constant pool
5600 // into a vector. On Sandybridge it is still better to load a constant vector
5601 // from the constant pool and not to broadcast it from a scalar.
5602 if (ConstSplatVal && Subtarget->hasInt256()) {
5603 EVT CVT = Ld.getValueType();
5604 assert(!CVT.isVector() && "Must not broadcast a vector type");
5605 unsigned ScalarSize = CVT.getSizeInBits();
5607 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)) {
5608 const Constant *C = 0;
5609 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5610 C = CI->getConstantIntValue();
5611 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5612 C = CF->getConstantFPValue();
5614 assert(C && "Invalid constant type");
5616 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5617 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
5618 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5619 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
5620 MachinePointerInfo::getConstantPool(),
5621 false, false, false, Alignment);
5623 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5627 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5628 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5630 // Handle AVX2 in-register broadcasts.
5631 if (!IsLoad && Subtarget->hasInt256() &&
5632 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
5633 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5635 // The scalar source must be a normal load.
5639 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64))
5640 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5642 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5643 // double since there is no vbroadcastsd xmm
5644 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
5645 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5646 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5649 // Unsupported broadcast.
5653 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
5654 MVT VT = Op.getSimpleValueType();
5656 // Skip if insert_vec_elt is not supported.
5657 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5658 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
5662 unsigned NumElems = Op.getNumOperands();
5666 SmallVector<unsigned, 4> InsertIndices;
5667 SmallVector<int, 8> Mask(NumElems, -1);
5669 for (unsigned i = 0; i != NumElems; ++i) {
5670 unsigned Opc = Op.getOperand(i).getOpcode();
5672 if (Opc == ISD::UNDEF)
5675 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
5676 // Quit if more than 1 elements need inserting.
5677 if (InsertIndices.size() > 1)
5680 InsertIndices.push_back(i);
5684 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
5685 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
5687 // Quit if extracted from vector of different type.
5688 if (ExtractedFromVec.getValueType() != VT)
5691 // Quit if non-constant index.
5692 if (!isa<ConstantSDNode>(ExtIdx))
5695 if (VecIn1.getNode() == 0)
5696 VecIn1 = ExtractedFromVec;
5697 else if (VecIn1 != ExtractedFromVec) {
5698 if (VecIn2.getNode() == 0)
5699 VecIn2 = ExtractedFromVec;
5700 else if (VecIn2 != ExtractedFromVec)
5701 // Quit if more than 2 vectors to shuffle
5705 unsigned Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
5707 if (ExtractedFromVec == VecIn1)
5709 else if (ExtractedFromVec == VecIn2)
5710 Mask[i] = Idx + NumElems;
5713 if (VecIn1.getNode() == 0)
5716 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5717 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
5718 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
5719 unsigned Idx = InsertIndices[i];
5720 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
5721 DAG.getIntPtrConstant(Idx));
5727 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
5729 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
5731 MVT VT = Op.getSimpleValueType();
5732 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
5733 "Unexpected type in LowerBUILD_VECTORvXi1!");
5736 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5737 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
5738 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5739 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5740 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
5741 Ops, VT.getVectorNumElements());
5744 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5745 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
5746 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5747 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5748 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
5749 Ops, VT.getVectorNumElements());
5752 bool AllContants = true;
5753 uint64_t Immediate = 0;
5754 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5755 SDValue In = Op.getOperand(idx);
5756 if (In.getOpcode() == ISD::UNDEF)
5758 if (!isa<ConstantSDNode>(In)) {
5759 AllContants = false;
5762 if (cast<ConstantSDNode>(In)->getZExtValue())
5763 Immediate |= (1ULL << idx);
5767 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
5768 DAG.getConstant(Immediate, MVT::i16));
5769 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
5770 DAG.getIntPtrConstant(0));
5773 // Splat vector (with undefs)
5774 SDValue In = Op.getOperand(0);
5775 for (unsigned i = 1, e = Op.getNumOperands(); i != e; ++i) {
5776 if (Op.getOperand(i) != In && Op.getOperand(i).getOpcode() != ISD::UNDEF)
5777 llvm_unreachable("Unsupported predicate operation");
5780 SDValue EFLAGS, X86CC;
5781 if (In.getOpcode() == ISD::SETCC) {
5782 SDValue Op0 = In.getOperand(0);
5783 SDValue Op1 = In.getOperand(1);
5784 ISD::CondCode CC = cast<CondCodeSDNode>(In.getOperand(2))->get();
5785 bool isFP = Op1.getValueType().isFloatingPoint();
5786 unsigned X86CCVal = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
5788 assert(X86CCVal != X86::COND_INVALID && "Unsupported predicate operation");
5790 X86CC = DAG.getConstant(X86CCVal, MVT::i8);
5791 EFLAGS = EmitCmp(Op0, Op1, X86CCVal, DAG);
5792 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
5793 } else if (In.getOpcode() == X86ISD::SETCC) {
5794 X86CC = In.getOperand(0);
5795 EFLAGS = In.getOperand(1);
5804 // res = allOnes ### CMOVNE -1, %res
5807 MVT InVT = In.getSimpleValueType();
5808 SDValue Bit1 = DAG.getNode(ISD::AND, dl, InVT, In, DAG.getConstant(1, InVT));
5809 EFLAGS = EmitTest(Bit1, X86::COND_NE, DAG);
5810 X86CC = DAG.getConstant(X86::COND_NE, MVT::i8);
5813 if (VT == MVT::v16i1) {
5814 SDValue Cst1 = DAG.getConstant(-1, MVT::i16);
5815 SDValue Cst0 = DAG.getConstant(0, MVT::i16);
5816 SDValue CmovOp = DAG.getNode(X86ISD::CMOV, dl, MVT::i16,
5817 Cst0, Cst1, X86CC, EFLAGS);
5818 return DAG.getNode(ISD::BITCAST, dl, VT, CmovOp);
5821 if (VT == MVT::v8i1) {
5822 SDValue Cst1 = DAG.getConstant(-1, MVT::i32);
5823 SDValue Cst0 = DAG.getConstant(0, MVT::i32);
5824 SDValue CmovOp = DAG.getNode(X86ISD::CMOV, dl, MVT::i32,
5825 Cst0, Cst1, X86CC, EFLAGS);
5826 CmovOp = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, CmovOp);
5827 return DAG.getNode(ISD::BITCAST, dl, VT, CmovOp);
5829 llvm_unreachable("Unsupported predicate operation");
5833 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5836 MVT VT = Op.getSimpleValueType();
5837 MVT ExtVT = VT.getVectorElementType();
5838 unsigned NumElems = Op.getNumOperands();
5840 // Generate vectors for predicate vectors.
5841 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
5842 return LowerBUILD_VECTORvXi1(Op, DAG);
5844 // Vectors containing all zeros can be matched by pxor and xorps later
5845 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5846 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
5847 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
5848 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
5851 return getZeroVector(VT, Subtarget, DAG, dl);
5854 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
5855 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
5856 // vpcmpeqd on 256-bit vectors.
5857 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
5858 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
5861 if (!VT.is512BitVector())
5862 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
5865 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
5866 if (Broadcast.getNode())
5869 unsigned EVTBits = ExtVT.getSizeInBits();
5871 unsigned NumZero = 0;
5872 unsigned NumNonZero = 0;
5873 unsigned NonZeros = 0;
5874 bool IsAllConstants = true;
5875 SmallSet<SDValue, 8> Values;
5876 for (unsigned i = 0; i < NumElems; ++i) {
5877 SDValue Elt = Op.getOperand(i);
5878 if (Elt.getOpcode() == ISD::UNDEF)
5881 if (Elt.getOpcode() != ISD::Constant &&
5882 Elt.getOpcode() != ISD::ConstantFP)
5883 IsAllConstants = false;
5884 if (X86::isZeroNode(Elt))
5887 NonZeros |= (1 << i);
5892 // All undef vector. Return an UNDEF. All zero vectors were handled above.
5893 if (NumNonZero == 0)
5894 return DAG.getUNDEF(VT);
5896 // Special case for single non-zero, non-undef, element.
5897 if (NumNonZero == 1) {
5898 unsigned Idx = countTrailingZeros(NonZeros);
5899 SDValue Item = Op.getOperand(Idx);
5901 // If this is an insertion of an i64 value on x86-32, and if the top bits of
5902 // the value are obviously zero, truncate the value to i32 and do the
5903 // insertion that way. Only do this if the value is non-constant or if the
5904 // value is a constant being inserted into element 0. It is cheaper to do
5905 // a constant pool load than it is to do a movd + shuffle.
5906 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5907 (!IsAllConstants || Idx == 0)) {
5908 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
5910 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5911 EVT VecVT = MVT::v4i32;
5912 unsigned VecElts = 4;
5914 // Truncate the value (which may itself be a constant) to i32, and
5915 // convert it to a vector with movd (S2V+shuffle to zero extend).
5916 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5917 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5918 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5920 // Now we have our 32-bit value zero extended in the low element of
5921 // a vector. If Idx != 0, swizzle it into place.
5923 SmallVector<int, 4> Mask;
5924 Mask.push_back(Idx);
5925 for (unsigned i = 1; i != VecElts; ++i)
5927 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
5930 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5934 // If we have a constant or non-constant insertion into the low element of
5935 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5936 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5937 // depending on what the source datatype is.
5940 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5942 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5943 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5944 if (VT.is256BitVector() || VT.is512BitVector()) {
5945 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
5946 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
5947 Item, DAG.getIntPtrConstant(0));
5949 assert(VT.is128BitVector() && "Expected an SSE value type!");
5950 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5951 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
5952 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5955 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
5956 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5957 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5958 if (VT.is256BitVector()) {
5959 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
5960 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
5962 assert(VT.is128BitVector() && "Expected an SSE value type!");
5963 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5965 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5969 // Is it a vector logical left shift?
5970 if (NumElems == 2 && Idx == 1 &&
5971 X86::isZeroNode(Op.getOperand(0)) &&
5972 !X86::isZeroNode(Op.getOperand(1))) {
5973 unsigned NumBits = VT.getSizeInBits();
5974 return getVShift(true, VT,
5975 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5976 VT, Op.getOperand(1)),
5977 NumBits/2, DAG, *this, dl);
5980 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
5983 // Otherwise, if this is a vector with i32 or f32 elements, and the element
5984 // is a non-constant being inserted into an element other than the low one,
5985 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
5986 // movd/movss) to move this into the low element, then shuffle it into
5988 if (EVTBits == 32) {
5989 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5991 // Turn it into a shuffle of zero and zero-extended scalar to vector.
5992 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
5993 SmallVector<int, 8> MaskVec;
5994 for (unsigned i = 0; i != NumElems; ++i)
5995 MaskVec.push_back(i == Idx ? 0 : 1);
5996 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
6000 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6001 if (Values.size() == 1) {
6002 if (EVTBits == 32) {
6003 // Instead of a shuffle like this:
6004 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6005 // Check if it's possible to issue this instead.
6006 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6007 unsigned Idx = countTrailingZeros(NonZeros);
6008 SDValue Item = Op.getOperand(Idx);
6009 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6010 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6015 // A vector full of immediates; various special cases are already
6016 // handled, so this is best done with a single constant-pool load.
6020 // For AVX-length vectors, build the individual 128-bit pieces and use
6021 // shuffles to put them in place.
6022 if (VT.is256BitVector()) {
6023 SmallVector<SDValue, 32> V;
6024 for (unsigned i = 0; i != NumElems; ++i)
6025 V.push_back(Op.getOperand(i));
6027 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6029 // Build both the lower and upper subvector.
6030 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2);
6031 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2],
6034 // Recreate the wider vector with the lower and upper part.
6035 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6038 // Let legalizer expand 2-wide build_vectors.
6039 if (EVTBits == 64) {
6040 if (NumNonZero == 1) {
6041 // One half is zero or undef.
6042 unsigned Idx = countTrailingZeros(NonZeros);
6043 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6044 Op.getOperand(Idx));
6045 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6050 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6051 if (EVTBits == 8 && NumElems == 16) {
6052 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
6054 if (V.getNode()) return V;
6057 if (EVTBits == 16 && NumElems == 8) {
6058 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
6060 if (V.getNode()) return V;
6063 // If element VT is == 32 bits, turn it into a number of shuffles.
6064 SmallVector<SDValue, 8> V(NumElems);
6065 if (NumElems == 4 && NumZero > 0) {
6066 for (unsigned i = 0; i < 4; ++i) {
6067 bool isZero = !(NonZeros & (1 << i));
6069 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
6071 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6074 for (unsigned i = 0; i < 2; ++i) {
6075 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
6078 V[i] = V[i*2]; // Must be a zero vector.
6081 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
6084 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
6087 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
6092 bool Reverse1 = (NonZeros & 0x3) == 2;
6093 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
6097 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
6098 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
6100 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
6103 if (Values.size() > 1 && VT.is128BitVector()) {
6104 // Check for a build vector of consecutive loads.
6105 for (unsigned i = 0; i < NumElems; ++i)
6106 V[i] = Op.getOperand(i);
6108 // Check for elements which are consecutive loads.
6109 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG);
6113 // Check for a build vector from mostly shuffle plus few inserting.
6114 SDValue Sh = buildFromShuffleMostly(Op, DAG);
6118 // For SSE 4.1, use insertps to put the high elements into the low element.
6119 if (getSubtarget()->hasSSE41()) {
6121 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
6122 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
6124 Result = DAG.getUNDEF(VT);
6126 for (unsigned i = 1; i < NumElems; ++i) {
6127 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
6128 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
6129 Op.getOperand(i), DAG.getIntPtrConstant(i));
6134 // Otherwise, expand into a number of unpckl*, start by extending each of
6135 // our (non-undef) elements to the full vector width with the element in the
6136 // bottom slot of the vector (which generates no code for SSE).
6137 for (unsigned i = 0; i < NumElems; ++i) {
6138 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
6139 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6141 V[i] = DAG.getUNDEF(VT);
6144 // Next, we iteratively mix elements, e.g. for v4f32:
6145 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
6146 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
6147 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
6148 unsigned EltStride = NumElems >> 1;
6149 while (EltStride != 0) {
6150 for (unsigned i = 0; i < EltStride; ++i) {
6151 // If V[i+EltStride] is undef and this is the first round of mixing,
6152 // then it is safe to just drop this shuffle: V[i] is already in the
6153 // right place, the one element (since it's the first round) being
6154 // inserted as undef can be dropped. This isn't safe for successive
6155 // rounds because they will permute elements within both vectors.
6156 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
6157 EltStride == NumElems/2)
6160 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
6169 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
6170 // to create 256-bit vectors from two other 128-bit ones.
6171 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6173 MVT ResVT = Op.getSimpleValueType();
6175 assert((ResVT.is256BitVector() ||
6176 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
6178 SDValue V1 = Op.getOperand(0);
6179 SDValue V2 = Op.getOperand(1);
6180 unsigned NumElems = ResVT.getVectorNumElements();
6181 if(ResVT.is256BitVector())
6182 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6184 if (Op.getNumOperands() == 4) {
6185 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
6186 ResVT.getVectorNumElements()/2);
6187 SDValue V3 = Op.getOperand(2);
6188 SDValue V4 = Op.getOperand(3);
6189 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
6190 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
6192 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6195 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6196 MVT LLVM_ATTRIBUTE_UNUSED VT = Op.getSimpleValueType();
6197 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
6198 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
6199 Op.getNumOperands() == 4)));
6201 // AVX can use the vinsertf128 instruction to create 256-bit vectors
6202 // from two other 128-bit ones.
6204 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
6205 return LowerAVXCONCAT_VECTORS(Op, DAG);
6208 // Try to lower a shuffle node into a simple blend instruction.
6210 LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
6211 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
6212 SDValue V1 = SVOp->getOperand(0);
6213 SDValue V2 = SVOp->getOperand(1);
6215 MVT VT = SVOp->getSimpleValueType(0);
6216 MVT EltVT = VT.getVectorElementType();
6217 unsigned NumElems = VT.getVectorNumElements();
6219 // There is no blend with immediate in AVX-512.
6220 if (VT.is512BitVector())
6223 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
6225 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
6228 // Check the mask for BLEND and build the value.
6229 unsigned MaskValue = 0;
6230 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
6231 unsigned NumLanes = (NumElems-1)/8 + 1;
6232 unsigned NumElemsInLane = NumElems / NumLanes;
6234 // Blend for v16i16 should be symetric for the both lanes.
6235 for (unsigned i = 0; i < NumElemsInLane; ++i) {
6237 int SndLaneEltIdx = (NumLanes == 2) ?
6238 SVOp->getMaskElt(i + NumElemsInLane) : -1;
6239 int EltIdx = SVOp->getMaskElt(i);
6241 if ((EltIdx < 0 || EltIdx == (int)i) &&
6242 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
6245 if (((unsigned)EltIdx == (i + NumElems)) &&
6246 (SndLaneEltIdx < 0 ||
6247 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
6248 MaskValue |= (1<<i);
6253 // Convert i32 vectors to floating point if it is not AVX2.
6254 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
6256 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
6257 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
6259 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
6260 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
6263 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
6264 DAG.getConstant(MaskValue, MVT::i32));
6265 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
6268 // v8i16 shuffles - Prefer shuffles in the following order:
6269 // 1. [all] pshuflw, pshufhw, optional move
6270 // 2. [ssse3] 1 x pshufb
6271 // 3. [ssse3] 2 x pshufb + 1 x por
6272 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
6274 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
6275 SelectionDAG &DAG) {
6276 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6277 SDValue V1 = SVOp->getOperand(0);
6278 SDValue V2 = SVOp->getOperand(1);
6280 SmallVector<int, 8> MaskVals;
6282 // Determine if more than 1 of the words in each of the low and high quadwords
6283 // of the result come from the same quadword of one of the two inputs. Undef
6284 // mask values count as coming from any quadword, for better codegen.
6285 unsigned LoQuad[] = { 0, 0, 0, 0 };
6286 unsigned HiQuad[] = { 0, 0, 0, 0 };
6287 std::bitset<4> InputQuads;
6288 for (unsigned i = 0; i < 8; ++i) {
6289 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
6290 int EltIdx = SVOp->getMaskElt(i);
6291 MaskVals.push_back(EltIdx);
6300 InputQuads.set(EltIdx / 4);
6303 int BestLoQuad = -1;
6304 unsigned MaxQuad = 1;
6305 for (unsigned i = 0; i < 4; ++i) {
6306 if (LoQuad[i] > MaxQuad) {
6308 MaxQuad = LoQuad[i];
6312 int BestHiQuad = -1;
6314 for (unsigned i = 0; i < 4; ++i) {
6315 if (HiQuad[i] > MaxQuad) {
6317 MaxQuad = HiQuad[i];
6321 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
6322 // of the two input vectors, shuffle them into one input vector so only a
6323 // single pshufb instruction is necessary. If There are more than 2 input
6324 // quads, disable the next transformation since it does not help SSSE3.
6325 bool V1Used = InputQuads[0] || InputQuads[1];
6326 bool V2Used = InputQuads[2] || InputQuads[3];
6327 if (Subtarget->hasSSSE3()) {
6328 if (InputQuads.count() == 2 && V1Used && V2Used) {
6329 BestLoQuad = InputQuads[0] ? 0 : 1;
6330 BestHiQuad = InputQuads[2] ? 2 : 3;
6332 if (InputQuads.count() > 2) {
6338 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
6339 // the shuffle mask. If a quad is scored as -1, that means that it contains
6340 // words from all 4 input quadwords.
6342 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
6344 BestLoQuad < 0 ? 0 : BestLoQuad,
6345 BestHiQuad < 0 ? 1 : BestHiQuad
6347 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
6348 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
6349 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
6350 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
6352 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
6353 // source words for the shuffle, to aid later transformations.
6354 bool AllWordsInNewV = true;
6355 bool InOrder[2] = { true, true };
6356 for (unsigned i = 0; i != 8; ++i) {
6357 int idx = MaskVals[i];
6359 InOrder[i/4] = false;
6360 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
6362 AllWordsInNewV = false;
6366 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
6367 if (AllWordsInNewV) {
6368 for (int i = 0; i != 8; ++i) {
6369 int idx = MaskVals[i];
6372 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
6373 if ((idx != i) && idx < 4)
6375 if ((idx != i) && idx > 3)
6384 // If we've eliminated the use of V2, and the new mask is a pshuflw or
6385 // pshufhw, that's as cheap as it gets. Return the new shuffle.
6386 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
6387 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
6388 unsigned TargetMask = 0;
6389 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
6390 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
6391 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
6392 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
6393 getShufflePSHUFLWImmediate(SVOp);
6394 V1 = NewV.getOperand(0);
6395 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
6399 // Promote splats to a larger type which usually leads to more efficient code.
6400 // FIXME: Is this true if pshufb is available?
6401 if (SVOp->isSplat())
6402 return PromoteSplat(SVOp, DAG);
6404 // If we have SSSE3, and all words of the result are from 1 input vector,
6405 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
6406 // is present, fall back to case 4.
6407 if (Subtarget->hasSSSE3()) {
6408 SmallVector<SDValue,16> pshufbMask;
6410 // If we have elements from both input vectors, set the high bit of the
6411 // shuffle mask element to zero out elements that come from V2 in the V1
6412 // mask, and elements that come from V1 in the V2 mask, so that the two
6413 // results can be OR'd together.
6414 bool TwoInputs = V1Used && V2Used;
6415 for (unsigned i = 0; i != 8; ++i) {
6416 int EltIdx = MaskVals[i] * 2;
6417 int Idx0 = (TwoInputs && (EltIdx >= 16)) ? 0x80 : EltIdx;
6418 int Idx1 = (TwoInputs && (EltIdx >= 16)) ? 0x80 : EltIdx+1;
6419 pshufbMask.push_back(DAG.getConstant(Idx0, MVT::i8));
6420 pshufbMask.push_back(DAG.getConstant(Idx1, MVT::i8));
6422 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1);
6423 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
6424 DAG.getNode(ISD::BUILD_VECTOR, dl,
6425 MVT::v16i8, &pshufbMask[0], 16));
6427 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
6429 // Calculate the shuffle mask for the second input, shuffle it, and
6430 // OR it with the first shuffled input.
6432 for (unsigned i = 0; i != 8; ++i) {
6433 int EltIdx = MaskVals[i] * 2;
6434 int Idx0 = (EltIdx < 16) ? 0x80 : EltIdx - 16;
6435 int Idx1 = (EltIdx < 16) ? 0x80 : EltIdx - 15;
6436 pshufbMask.push_back(DAG.getConstant(Idx0, MVT::i8));
6437 pshufbMask.push_back(DAG.getConstant(Idx1, MVT::i8));
6439 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2);
6440 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
6441 DAG.getNode(ISD::BUILD_VECTOR, dl,
6442 MVT::v16i8, &pshufbMask[0], 16));
6443 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
6444 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
6447 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
6448 // and update MaskVals with new element order.
6449 std::bitset<8> InOrder;
6450 if (BestLoQuad >= 0) {
6451 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
6452 for (int i = 0; i != 4; ++i) {
6453 int idx = MaskVals[i];
6456 } else if ((idx / 4) == BestLoQuad) {
6461 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
6464 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
6465 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
6466 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
6468 getShufflePSHUFLWImmediate(SVOp), DAG);
6472 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
6473 // and update MaskVals with the new element order.
6474 if (BestHiQuad >= 0) {
6475 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
6476 for (unsigned i = 4; i != 8; ++i) {
6477 int idx = MaskVals[i];
6480 } else if ((idx / 4) == BestHiQuad) {
6481 MaskV[i] = (idx & 3) + 4;
6485 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
6488 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
6489 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
6490 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
6492 getShufflePSHUFHWImmediate(SVOp), DAG);
6496 // In case BestHi & BestLo were both -1, which means each quadword has a word
6497 // from each of the four input quadwords, calculate the InOrder bitvector now
6498 // before falling through to the insert/extract cleanup.
6499 if (BestLoQuad == -1 && BestHiQuad == -1) {
6501 for (int i = 0; i != 8; ++i)
6502 if (MaskVals[i] < 0 || MaskVals[i] == i)
6506 // The other elements are put in the right place using pextrw and pinsrw.
6507 for (unsigned i = 0; i != 8; ++i) {
6510 int EltIdx = MaskVals[i];
6513 SDValue ExtOp = (EltIdx < 8) ?
6514 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
6515 DAG.getIntPtrConstant(EltIdx)) :
6516 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
6517 DAG.getIntPtrConstant(EltIdx - 8));
6518 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
6519 DAG.getIntPtrConstant(i));
6524 // v16i8 shuffles - Prefer shuffles in the following order:
6525 // 1. [ssse3] 1 x pshufb
6526 // 2. [ssse3] 2 x pshufb + 1 x por
6527 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
6528 static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
6529 const X86Subtarget* Subtarget,
6530 SelectionDAG &DAG) {
6531 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6532 SDValue V1 = SVOp->getOperand(0);
6533 SDValue V2 = SVOp->getOperand(1);
6535 ArrayRef<int> MaskVals = SVOp->getMask();
6537 // Promote splats to a larger type which usually leads to more efficient code.
6538 // FIXME: Is this true if pshufb is available?
6539 if (SVOp->isSplat())
6540 return PromoteSplat(SVOp, DAG);
6542 // If we have SSSE3, case 1 is generated when all result bytes come from
6543 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
6544 // present, fall back to case 3.
6546 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
6547 if (Subtarget->hasSSSE3()) {
6548 SmallVector<SDValue,16> pshufbMask;
6550 // If all result elements are from one input vector, then only translate
6551 // undef mask values to 0x80 (zero out result) in the pshufb mask.
6553 // Otherwise, we have elements from both input vectors, and must zero out
6554 // elements that come from V2 in the first mask, and V1 in the second mask
6555 // so that we can OR them together.
6556 for (unsigned i = 0; i != 16; ++i) {
6557 int EltIdx = MaskVals[i];
6558 if (EltIdx < 0 || EltIdx >= 16)
6560 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
6562 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
6563 DAG.getNode(ISD::BUILD_VECTOR, dl,
6564 MVT::v16i8, &pshufbMask[0], 16));
6566 // As PSHUFB will zero elements with negative indices, it's safe to ignore
6567 // the 2nd operand if it's undefined or zero.
6568 if (V2.getOpcode() == ISD::UNDEF ||
6569 ISD::isBuildVectorAllZeros(V2.getNode()))
6572 // Calculate the shuffle mask for the second input, shuffle it, and
6573 // OR it with the first shuffled input.
6575 for (unsigned i = 0; i != 16; ++i) {
6576 int EltIdx = MaskVals[i];
6577 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
6578 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
6580 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
6581 DAG.getNode(ISD::BUILD_VECTOR, dl,
6582 MVT::v16i8, &pshufbMask[0], 16));
6583 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
6586 // No SSSE3 - Calculate in place words and then fix all out of place words
6587 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
6588 // the 16 different words that comprise the two doublequadword input vectors.
6589 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
6590 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
6592 for (int i = 0; i != 8; ++i) {
6593 int Elt0 = MaskVals[i*2];
6594 int Elt1 = MaskVals[i*2+1];
6596 // This word of the result is all undef, skip it.
6597 if (Elt0 < 0 && Elt1 < 0)
6600 // This word of the result is already in the correct place, skip it.
6601 if ((Elt0 == i*2) && (Elt1 == i*2+1))
6604 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
6605 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
6608 // If Elt0 and Elt1 are defined, are consecutive, and can be load
6609 // using a single extract together, load it and store it.
6610 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
6611 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
6612 DAG.getIntPtrConstant(Elt1 / 2));
6613 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
6614 DAG.getIntPtrConstant(i));
6618 // If Elt1 is defined, extract it from the appropriate source. If the
6619 // source byte is not also odd, shift the extracted word left 8 bits
6620 // otherwise clear the bottom 8 bits if we need to do an or.
6622 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
6623 DAG.getIntPtrConstant(Elt1 / 2));
6624 if ((Elt1 & 1) == 0)
6625 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
6627 TLI.getShiftAmountTy(InsElt.getValueType())));
6629 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
6630 DAG.getConstant(0xFF00, MVT::i16));
6632 // If Elt0 is defined, extract it from the appropriate source. If the
6633 // source byte is not also even, shift the extracted word right 8 bits. If
6634 // Elt1 was also defined, OR the extracted values together before
6635 // inserting them in the result.
6637 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
6638 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
6639 if ((Elt0 & 1) != 0)
6640 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
6642 TLI.getShiftAmountTy(InsElt0.getValueType())));
6644 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
6645 DAG.getConstant(0x00FF, MVT::i16));
6646 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
6649 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
6650 DAG.getIntPtrConstant(i));
6652 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
6655 // v32i8 shuffles - Translate to VPSHUFB if possible.
6657 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
6658 const X86Subtarget *Subtarget,
6659 SelectionDAG &DAG) {
6660 MVT VT = SVOp->getSimpleValueType(0);
6661 SDValue V1 = SVOp->getOperand(0);
6662 SDValue V2 = SVOp->getOperand(1);
6664 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
6666 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
6667 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
6668 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
6670 // VPSHUFB may be generated if
6671 // (1) one of input vector is undefined or zeroinitializer.
6672 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
6673 // And (2) the mask indexes don't cross the 128-bit lane.
6674 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
6675 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
6678 if (V1IsAllZero && !V2IsAllZero) {
6679 CommuteVectorShuffleMask(MaskVals, 32);
6682 SmallVector<SDValue, 32> pshufbMask;
6683 for (unsigned i = 0; i != 32; i++) {
6684 int EltIdx = MaskVals[i];
6685 if (EltIdx < 0 || EltIdx >= 32)
6688 if ((EltIdx >= 16 && i < 16) || (EltIdx < 16 && i >= 16))
6689 // Cross lane is not allowed.
6693 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
6695 return DAG.getNode(X86ISD::PSHUFB, dl, MVT::v32i8, V1,
6696 DAG.getNode(ISD::BUILD_VECTOR, dl,
6697 MVT::v32i8, &pshufbMask[0], 32));
6700 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
6701 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
6702 /// done when every pair / quad of shuffle mask elements point to elements in
6703 /// the right sequence. e.g.
6704 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
6706 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
6707 SelectionDAG &DAG) {
6708 MVT VT = SVOp->getSimpleValueType(0);
6710 unsigned NumElems = VT.getVectorNumElements();
6713 switch (VT.SimpleTy) {
6714 default: llvm_unreachable("Unexpected!");
6715 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
6716 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
6717 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
6718 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
6719 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
6720 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
6723 SmallVector<int, 8> MaskVec;
6724 for (unsigned i = 0; i != NumElems; i += Scale) {
6726 for (unsigned j = 0; j != Scale; ++j) {
6727 int EltIdx = SVOp->getMaskElt(i+j);
6731 StartIdx = (EltIdx / Scale);
6732 if (EltIdx != (int)(StartIdx*Scale + j))
6735 MaskVec.push_back(StartIdx);
6738 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
6739 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
6740 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
6743 /// getVZextMovL - Return a zero-extending vector move low node.
6745 static SDValue getVZextMovL(MVT VT, MVT OpVT,
6746 SDValue SrcOp, SelectionDAG &DAG,
6747 const X86Subtarget *Subtarget, SDLoc dl) {
6748 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
6749 LoadSDNode *LD = NULL;
6750 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
6751 LD = dyn_cast<LoadSDNode>(SrcOp);
6753 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
6755 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
6756 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
6757 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
6758 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
6759 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
6761 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
6762 return DAG.getNode(ISD::BITCAST, dl, VT,
6763 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
6764 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6772 return DAG.getNode(ISD::BITCAST, dl, VT,
6773 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
6774 DAG.getNode(ISD::BITCAST, dl,
6778 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
6779 /// which could not be matched by any known target speficic shuffle
6781 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6783 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
6784 if (NewOp.getNode())
6787 MVT VT = SVOp->getSimpleValueType(0);
6789 unsigned NumElems = VT.getVectorNumElements();
6790 unsigned NumLaneElems = NumElems / 2;
6793 MVT EltVT = VT.getVectorElementType();
6794 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
6797 SmallVector<int, 16> Mask;
6798 for (unsigned l = 0; l < 2; ++l) {
6799 // Build a shuffle mask for the output, discovering on the fly which
6800 // input vectors to use as shuffle operands (recorded in InputUsed).
6801 // If building a suitable shuffle vector proves too hard, then bail
6802 // out with UseBuildVector set.
6803 bool UseBuildVector = false;
6804 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
6805 unsigned LaneStart = l * NumLaneElems;
6806 for (unsigned i = 0; i != NumLaneElems; ++i) {
6807 // The mask element. This indexes into the input.
6808 int Idx = SVOp->getMaskElt(i+LaneStart);
6810 // the mask element does not index into any input vector.
6815 // The input vector this mask element indexes into.
6816 int Input = Idx / NumLaneElems;
6818 // Turn the index into an offset from the start of the input vector.
6819 Idx -= Input * NumLaneElems;
6821 // Find or create a shuffle vector operand to hold this input.
6823 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
6824 if (InputUsed[OpNo] == Input)
6825 // This input vector is already an operand.
6827 if (InputUsed[OpNo] < 0) {
6828 // Create a new operand for this input vector.
6829 InputUsed[OpNo] = Input;
6834 if (OpNo >= array_lengthof(InputUsed)) {
6835 // More than two input vectors used! Give up on trying to create a
6836 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
6837 UseBuildVector = true;
6841 // Add the mask index for the new shuffle vector.
6842 Mask.push_back(Idx + OpNo * NumLaneElems);
6845 if (UseBuildVector) {
6846 SmallVector<SDValue, 16> SVOps;
6847 for (unsigned i = 0; i != NumLaneElems; ++i) {
6848 // The mask element. This indexes into the input.
6849 int Idx = SVOp->getMaskElt(i+LaneStart);
6851 SVOps.push_back(DAG.getUNDEF(EltVT));
6855 // The input vector this mask element indexes into.
6856 int Input = Idx / NumElems;
6858 // Turn the index into an offset from the start of the input vector.
6859 Idx -= Input * NumElems;
6861 // Extract the vector element by hand.
6862 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
6863 SVOp->getOperand(Input),
6864 DAG.getIntPtrConstant(Idx)));
6867 // Construct the output using a BUILD_VECTOR.
6868 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, &SVOps[0],
6870 } else if (InputUsed[0] < 0) {
6871 // No input vectors were used! The result is undefined.
6872 Output[l] = DAG.getUNDEF(NVT);
6874 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
6875 (InputUsed[0] % 2) * NumLaneElems,
6877 // If only one input was used, use an undefined vector for the other.
6878 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
6879 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
6880 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
6881 // At least one input vector was used. Create a new shuffle vector.
6882 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
6888 // Concatenate the result back
6889 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
6892 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
6893 /// 4 elements, and match them with several different shuffle types.
6895 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6896 SDValue V1 = SVOp->getOperand(0);
6897 SDValue V2 = SVOp->getOperand(1);
6899 MVT VT = SVOp->getSimpleValueType(0);
6901 assert(VT.is128BitVector() && "Unsupported vector size");
6903 std::pair<int, int> Locs[4];
6904 int Mask1[] = { -1, -1, -1, -1 };
6905 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
6909 for (unsigned i = 0; i != 4; ++i) {
6910 int Idx = PermMask[i];
6912 Locs[i] = std::make_pair(-1, -1);
6914 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
6916 Locs[i] = std::make_pair(0, NumLo);
6920 Locs[i] = std::make_pair(1, NumHi);
6922 Mask1[2+NumHi] = Idx;
6928 if (NumLo <= 2 && NumHi <= 2) {
6929 // If no more than two elements come from either vector. This can be
6930 // implemented with two shuffles. First shuffle gather the elements.
6931 // The second shuffle, which takes the first shuffle as both of its
6932 // vector operands, put the elements into the right order.
6933 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6935 int Mask2[] = { -1, -1, -1, -1 };
6937 for (unsigned i = 0; i != 4; ++i)
6938 if (Locs[i].first != -1) {
6939 unsigned Idx = (i < 2) ? 0 : 4;
6940 Idx += Locs[i].first * 2 + Locs[i].second;
6944 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
6947 if (NumLo == 3 || NumHi == 3) {
6948 // Otherwise, we must have three elements from one vector, call it X, and
6949 // one element from the other, call it Y. First, use a shufps to build an
6950 // intermediate vector with the one element from Y and the element from X
6951 // that will be in the same half in the final destination (the indexes don't
6952 // matter). Then, use a shufps to build the final vector, taking the half
6953 // containing the element from Y from the intermediate, and the other half
6956 // Normalize it so the 3 elements come from V1.
6957 CommuteVectorShuffleMask(PermMask, 4);
6961 // Find the element from V2.
6963 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
6964 int Val = PermMask[HiIndex];
6971 Mask1[0] = PermMask[HiIndex];
6973 Mask1[2] = PermMask[HiIndex^1];
6975 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6978 Mask1[0] = PermMask[0];
6979 Mask1[1] = PermMask[1];
6980 Mask1[2] = HiIndex & 1 ? 6 : 4;
6981 Mask1[3] = HiIndex & 1 ? 4 : 6;
6982 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6985 Mask1[0] = HiIndex & 1 ? 2 : 0;
6986 Mask1[1] = HiIndex & 1 ? 0 : 2;
6987 Mask1[2] = PermMask[2];
6988 Mask1[3] = PermMask[3];
6993 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
6996 // Break it into (shuffle shuffle_hi, shuffle_lo).
6997 int LoMask[] = { -1, -1, -1, -1 };
6998 int HiMask[] = { -1, -1, -1, -1 };
7000 int *MaskPtr = LoMask;
7001 unsigned MaskIdx = 0;
7004 for (unsigned i = 0; i != 4; ++i) {
7011 int Idx = PermMask[i];
7013 Locs[i] = std::make_pair(-1, -1);
7014 } else if (Idx < 4) {
7015 Locs[i] = std::make_pair(MaskIdx, LoIdx);
7016 MaskPtr[LoIdx] = Idx;
7019 Locs[i] = std::make_pair(MaskIdx, HiIdx);
7020 MaskPtr[HiIdx] = Idx;
7025 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
7026 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
7027 int MaskOps[] = { -1, -1, -1, -1 };
7028 for (unsigned i = 0; i != 4; ++i)
7029 if (Locs[i].first != -1)
7030 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
7031 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
7034 static bool MayFoldVectorLoad(SDValue V) {
7035 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
7036 V = V.getOperand(0);
7038 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
7039 V = V.getOperand(0);
7040 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
7041 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
7042 // BUILD_VECTOR (load), undef
7043 V = V.getOperand(0);
7045 return MayFoldLoad(V);
7049 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
7050 MVT VT = Op.getSimpleValueType();
7052 // Canonizalize to v2f64.
7053 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
7054 return DAG.getNode(ISD::BITCAST, dl, VT,
7055 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
7060 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
7062 SDValue V1 = Op.getOperand(0);
7063 SDValue V2 = Op.getOperand(1);
7064 MVT VT = Op.getSimpleValueType();
7066 assert(VT != MVT::v2i64 && "unsupported shuffle type");
7068 if (HasSSE2 && VT == MVT::v2f64)
7069 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
7071 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
7072 return DAG.getNode(ISD::BITCAST, dl, VT,
7073 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
7074 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
7075 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
7079 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
7080 SDValue V1 = Op.getOperand(0);
7081 SDValue V2 = Op.getOperand(1);
7082 MVT VT = Op.getSimpleValueType();
7084 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
7085 "unsupported shuffle type");
7087 if (V2.getOpcode() == ISD::UNDEF)
7091 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
7095 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
7096 SDValue V1 = Op.getOperand(0);
7097 SDValue V2 = Op.getOperand(1);
7098 MVT VT = Op.getSimpleValueType();
7099 unsigned NumElems = VT.getVectorNumElements();
7101 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
7102 // operand of these instructions is only memory, so check if there's a
7103 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
7105 bool CanFoldLoad = false;
7107 // Trivial case, when V2 comes from a load.
7108 if (MayFoldVectorLoad(V2))
7111 // When V1 is a load, it can be folded later into a store in isel, example:
7112 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
7114 // (MOVLPSmr addr:$src1, VR128:$src2)
7115 // So, recognize this potential and also use MOVLPS or MOVLPD
7116 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
7119 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7121 if (HasSSE2 && NumElems == 2)
7122 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
7125 // If we don't care about the second element, proceed to use movss.
7126 if (SVOp->getMaskElt(1) != -1)
7127 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
7130 // movl and movlp will both match v2i64, but v2i64 is never matched by
7131 // movl earlier because we make it strict to avoid messing with the movlp load
7132 // folding logic (see the code above getMOVLP call). Match it here then,
7133 // this is horrible, but will stay like this until we move all shuffle
7134 // matching to x86 specific nodes. Note that for the 1st condition all
7135 // types are matched with movsd.
7137 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
7138 // as to remove this logic from here, as much as possible
7139 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
7140 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
7141 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
7144 assert(VT != MVT::v4i32 && "unsupported shuffle type");
7146 // Invert the operand order and use SHUFPS to match it.
7147 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
7148 getShuffleSHUFImmediate(SVOp), DAG);
7151 // Reduce a vector shuffle to zext.
7152 static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
7153 SelectionDAG &DAG) {
7154 // PMOVZX is only available from SSE41.
7155 if (!Subtarget->hasSSE41())
7158 MVT VT = Op.getSimpleValueType();
7160 // Only AVX2 support 256-bit vector integer extending.
7161 if (!Subtarget->hasInt256() && VT.is256BitVector())
7164 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7166 SDValue V1 = Op.getOperand(0);
7167 SDValue V2 = Op.getOperand(1);
7168 unsigned NumElems = VT.getVectorNumElements();
7170 // Extending is an unary operation and the element type of the source vector
7171 // won't be equal to or larger than i64.
7172 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
7173 VT.getVectorElementType() == MVT::i64)
7176 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
7177 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
7178 while ((1U << Shift) < NumElems) {
7179 if (SVOp->getMaskElt(1U << Shift) == 1)
7182 // The maximal ratio is 8, i.e. from i8 to i64.
7187 // Check the shuffle mask.
7188 unsigned Mask = (1U << Shift) - 1;
7189 for (unsigned i = 0; i != NumElems; ++i) {
7190 int EltIdx = SVOp->getMaskElt(i);
7191 if ((i & Mask) != 0 && EltIdx != -1)
7193 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
7197 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
7198 MVT NeVT = MVT::getIntegerVT(NBits);
7199 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift);
7201 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT))
7204 // Simplify the operand as it's prepared to be fed into shuffle.
7205 unsigned SignificantBits = NVT.getSizeInBits() >> Shift;
7206 if (V1.getOpcode() == ISD::BITCAST &&
7207 V1.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
7208 V1.getOperand(0).getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
7209 V1.getOperand(0).getOperand(0)
7210 .getSimpleValueType().getSizeInBits() == SignificantBits) {
7211 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
7212 SDValue V = V1.getOperand(0).getOperand(0).getOperand(0);
7213 ConstantSDNode *CIdx =
7214 dyn_cast<ConstantSDNode>(V1.getOperand(0).getOperand(0).getOperand(1));
7215 // If it's foldable, i.e. normal load with single use, we will let code
7216 // selection to fold it. Otherwise, we will short the conversion sequence.
7217 if (CIdx && CIdx->getZExtValue() == 0 &&
7218 (!ISD::isNormalLoad(V.getNode()) || !V.hasOneUse())) {
7219 MVT FullVT = V.getSimpleValueType();
7220 MVT V1VT = V1.getSimpleValueType();
7221 if (FullVT.getSizeInBits() > V1VT.getSizeInBits()) {
7222 // The "ext_vec_elt" node is wider than the result node.
7223 // In this case we should extract subvector from V.
7224 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast (extract_subvector x)).
7225 unsigned Ratio = FullVT.getSizeInBits() / V1VT.getSizeInBits();
7226 MVT SubVecVT = MVT::getVectorVT(FullVT.getVectorElementType(),
7227 FullVT.getVectorNumElements()/Ratio);
7228 V = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVecVT, V,
7229 DAG.getIntPtrConstant(0));
7231 V1 = DAG.getNode(ISD::BITCAST, DL, V1VT, V);
7235 return DAG.getNode(ISD::BITCAST, DL, VT,
7236 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
7240 NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
7241 SelectionDAG &DAG) {
7242 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7243 MVT VT = Op.getSimpleValueType();
7245 SDValue V1 = Op.getOperand(0);
7246 SDValue V2 = Op.getOperand(1);
7248 if (isZeroShuffle(SVOp))
7249 return getZeroVector(VT, Subtarget, DAG, dl);
7251 // Handle splat operations
7252 if (SVOp->isSplat()) {
7253 // Use vbroadcast whenever the splat comes from a foldable load
7254 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
7255 if (Broadcast.getNode())
7259 // Check integer expanding shuffles.
7260 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG);
7261 if (NewOp.getNode())
7264 // If the shuffle can be profitably rewritten as a narrower shuffle, then
7266 if (VT == MVT::v8i16 || VT == MVT::v16i8 ||
7267 VT == MVT::v16i16 || VT == MVT::v32i8) {
7268 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
7269 if (NewOp.getNode())
7270 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
7271 } else if ((VT == MVT::v4i32 ||
7272 (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
7273 // FIXME: Figure out a cleaner way to do this.
7274 // Try to make use of movq to zero out the top part.
7275 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
7276 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
7277 if (NewOp.getNode()) {
7278 MVT NewVT = NewOp.getSimpleValueType();
7279 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
7280 NewVT, true, false))
7281 return getVZextMovL(VT, NewVT, NewOp.getOperand(0),
7282 DAG, Subtarget, dl);
7284 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
7285 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
7286 if (NewOp.getNode()) {
7287 MVT NewVT = NewOp.getSimpleValueType();
7288 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
7289 return getVZextMovL(VT, NewVT, NewOp.getOperand(1),
7290 DAG, Subtarget, dl);
7298 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
7299 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7300 SDValue V1 = Op.getOperand(0);
7301 SDValue V2 = Op.getOperand(1);
7302 MVT VT = Op.getSimpleValueType();
7304 unsigned NumElems = VT.getVectorNumElements();
7305 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
7306 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
7307 bool V1IsSplat = false;
7308 bool V2IsSplat = false;
7309 bool HasSSE2 = Subtarget->hasSSE2();
7310 bool HasFp256 = Subtarget->hasFp256();
7311 bool HasInt256 = Subtarget->hasInt256();
7312 MachineFunction &MF = DAG.getMachineFunction();
7313 bool OptForSize = MF.getFunction()->getAttributes().
7314 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
7316 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
7318 if (V1IsUndef && V2IsUndef)
7319 return DAG.getUNDEF(VT);
7321 assert(!V1IsUndef && "Op 1 of shuffle should not be undef");
7323 // Vector shuffle lowering takes 3 steps:
7325 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
7326 // narrowing and commutation of operands should be handled.
7327 // 2) Matching of shuffles with known shuffle masks to x86 target specific
7329 // 3) Rewriting of unmatched masks into new generic shuffle operations,
7330 // so the shuffle can be broken into other shuffles and the legalizer can
7331 // try the lowering again.
7333 // The general idea is that no vector_shuffle operation should be left to
7334 // be matched during isel, all of them must be converted to a target specific
7337 // Normalize the input vectors. Here splats, zeroed vectors, profitable
7338 // narrowing and commutation of operands should be handled. The actual code
7339 // doesn't include all of those, work in progress...
7340 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
7341 if (NewOp.getNode())
7344 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
7346 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
7347 // unpckh_undef). Only use pshufd if speed is more important than size.
7348 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
7349 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
7350 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
7351 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
7353 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
7354 V2IsUndef && MayFoldVectorLoad(V1))
7355 return getMOVDDup(Op, dl, V1, DAG);
7357 if (isMOVHLPS_v_undef_Mask(M, VT))
7358 return getMOVHighToLow(Op, dl, DAG);
7360 // Use to match splats
7361 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
7362 (VT == MVT::v2f64 || VT == MVT::v2i64))
7363 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
7365 if (isPSHUFDMask(M, VT)) {
7366 // The actual implementation will match the mask in the if above and then
7367 // during isel it can match several different instructions, not only pshufd
7368 // as its name says, sad but true, emulate the behavior for now...
7369 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
7370 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
7372 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
7374 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
7375 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
7377 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
7378 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, TargetMask,
7381 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
7385 if (isPALIGNRMask(M, VT, Subtarget))
7386 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
7387 getShufflePALIGNRImmediate(SVOp),
7390 // Check if this can be converted into a logical shift.
7391 bool isLeft = false;
7394 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
7395 if (isShift && ShVal.hasOneUse()) {
7396 // If the shifted value has multiple uses, it may be cheaper to use
7397 // v_set0 + movlhps or movhlps, etc.
7398 MVT EltVT = VT.getVectorElementType();
7399 ShAmt *= EltVT.getSizeInBits();
7400 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
7403 if (isMOVLMask(M, VT)) {
7404 if (ISD::isBuildVectorAllZeros(V1.getNode()))
7405 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
7406 if (!isMOVLPMask(M, VT)) {
7407 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
7408 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
7410 if (VT == MVT::v4i32 || VT == MVT::v4f32)
7411 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
7415 // FIXME: fold these into legal mask.
7416 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
7417 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
7419 if (isMOVHLPSMask(M, VT))
7420 return getMOVHighToLow(Op, dl, DAG);
7422 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
7423 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
7425 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
7426 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
7428 if (isMOVLPMask(M, VT))
7429 return getMOVLP(Op, dl, DAG, HasSSE2);
7431 if (ShouldXformToMOVHLPS(M, VT) ||
7432 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
7433 return CommuteVectorShuffle(SVOp, DAG);
7436 // No better options. Use a vshldq / vsrldq.
7437 MVT EltVT = VT.getVectorElementType();
7438 ShAmt *= EltVT.getSizeInBits();
7439 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
7442 bool Commuted = false;
7443 // FIXME: This should also accept a bitcast of a splat? Be careful, not
7444 // 1,1,1,1 -> v8i16 though.
7445 V1IsSplat = isSplatVector(V1.getNode());
7446 V2IsSplat = isSplatVector(V2.getNode());
7448 // Canonicalize the splat or undef, if present, to be on the RHS.
7449 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
7450 CommuteVectorShuffleMask(M, NumElems);
7452 std::swap(V1IsSplat, V2IsSplat);
7456 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
7457 // Shuffling low element of v1 into undef, just return v1.
7460 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
7461 // the instruction selector will not match, so get a canonical MOVL with
7462 // swapped operands to undo the commute.
7463 return getMOVL(DAG, dl, VT, V2, V1);
7466 if (isUNPCKLMask(M, VT, HasInt256))
7467 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
7469 if (isUNPCKHMask(M, VT, HasInt256))
7470 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
7473 // Normalize mask so all entries that point to V2 points to its first
7474 // element then try to match unpck{h|l} again. If match, return a
7475 // new vector_shuffle with the corrected mask.p
7476 SmallVector<int, 8> NewMask(M.begin(), M.end());
7477 NormalizeMask(NewMask, NumElems);
7478 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
7479 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
7480 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
7481 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
7485 // Commute is back and try unpck* again.
7486 // FIXME: this seems wrong.
7487 CommuteVectorShuffleMask(M, NumElems);
7489 std::swap(V1IsSplat, V2IsSplat);
7492 if (isUNPCKLMask(M, VT, HasInt256))
7493 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
7495 if (isUNPCKHMask(M, VT, HasInt256))
7496 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
7499 // Normalize the node to match x86 shuffle ops if needed
7500 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
7501 return CommuteVectorShuffle(SVOp, DAG);
7503 // The checks below are all present in isShuffleMaskLegal, but they are
7504 // inlined here right now to enable us to directly emit target specific
7505 // nodes, and remove one by one until they don't return Op anymore.
7507 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
7508 SVOp->getSplatIndex() == 0 && V2IsUndef) {
7509 if (VT == MVT::v2f64 || VT == MVT::v2i64)
7510 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
7513 if (isPSHUFHWMask(M, VT, HasInt256))
7514 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
7515 getShufflePSHUFHWImmediate(SVOp),
7518 if (isPSHUFLWMask(M, VT, HasInt256))
7519 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
7520 getShufflePSHUFLWImmediate(SVOp),
7523 if (isSHUFPMask(M, VT))
7524 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
7525 getShuffleSHUFImmediate(SVOp), DAG);
7527 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
7528 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
7529 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
7530 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
7532 //===--------------------------------------------------------------------===//
7533 // Generate target specific nodes for 128 or 256-bit shuffles only
7534 // supported in the AVX instruction set.
7537 // Handle VMOVDDUPY permutations
7538 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
7539 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
7541 // Handle VPERMILPS/D* permutations
7542 if (isVPERMILPMask(M, VT)) {
7543 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
7544 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
7545 getShuffleSHUFImmediate(SVOp), DAG);
7546 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1,
7547 getShuffleSHUFImmediate(SVOp), DAG);
7550 // Handle VPERM2F128/VPERM2I128 permutations
7551 if (isVPERM2X128Mask(M, VT, HasFp256))
7552 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
7553 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
7555 SDValue BlendOp = LowerVECTOR_SHUFFLEtoBlend(SVOp, Subtarget, DAG);
7556 if (BlendOp.getNode())
7560 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
7561 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
7563 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
7564 VT.is512BitVector()) {
7565 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
7566 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
7567 SmallVector<SDValue, 16> permclMask;
7568 for (unsigned i = 0; i != NumElems; ++i) {
7569 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
7572 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT,
7573 &permclMask[0], NumElems);
7575 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
7576 return DAG.getNode(X86ISD::VPERMV, dl, VT,
7577 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
7578 return DAG.getNode(X86ISD::VPERMV3, dl, VT,
7579 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1, V2);
7582 //===--------------------------------------------------------------------===//
7583 // Since no target specific shuffle was selected for this generic one,
7584 // lower it into other known shuffles. FIXME: this isn't true yet, but
7585 // this is the plan.
7588 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
7589 if (VT == MVT::v8i16) {
7590 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
7591 if (NewOp.getNode())
7595 if (VT == MVT::v16i8) {
7596 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
7597 if (NewOp.getNode())
7601 if (VT == MVT::v32i8) {
7602 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
7603 if (NewOp.getNode())
7607 // Handle all 128-bit wide vectors with 4 elements, and match them with
7608 // several different shuffle types.
7609 if (NumElems == 4 && VT.is128BitVector())
7610 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
7612 // Handle general 256-bit shuffles
7613 if (VT.is256BitVector())
7614 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
7619 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
7620 MVT VT = Op.getSimpleValueType();
7623 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
7626 if (VT.getSizeInBits() == 8) {
7627 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
7628 Op.getOperand(0), Op.getOperand(1));
7629 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
7630 DAG.getValueType(VT));
7631 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7634 if (VT.getSizeInBits() == 16) {
7635 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7636 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
7638 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
7639 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7640 DAG.getNode(ISD::BITCAST, dl,
7644 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
7645 Op.getOperand(0), Op.getOperand(1));
7646 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
7647 DAG.getValueType(VT));
7648 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7651 if (VT == MVT::f32) {
7652 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
7653 // the result back to FR32 register. It's only worth matching if the
7654 // result has a single use which is a store or a bitcast to i32. And in
7655 // the case of a store, it's not worth it if the index is a constant 0,
7656 // because a MOVSSmr can be used instead, which is smaller and faster.
7657 if (!Op.hasOneUse())
7659 SDNode *User = *Op.getNode()->use_begin();
7660 if ((User->getOpcode() != ISD::STORE ||
7661 (isa<ConstantSDNode>(Op.getOperand(1)) &&
7662 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
7663 (User->getOpcode() != ISD::BITCAST ||
7664 User->getValueType(0) != MVT::i32))
7666 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7667 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
7670 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
7673 if (VT == MVT::i32 || VT == MVT::i64) {
7674 // ExtractPS/pextrq works with constant index.
7675 if (isa<ConstantSDNode>(Op.getOperand(1)))
7681 /// Extract one bit from mask vector, like v16i1 or v8i1.
7682 /// AVX-512 feature.
7683 static SDValue ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) {
7684 SDValue Vec = Op.getOperand(0);
7686 MVT VecVT = Vec.getSimpleValueType();
7687 SDValue Idx = Op.getOperand(1);
7688 MVT EltVT = Op.getSimpleValueType();
7690 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
7692 // variable index can't be handled in mask registers,
7693 // extend vector to VR512
7694 if (!isa<ConstantSDNode>(Idx)) {
7695 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
7696 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
7697 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
7698 ExtVT.getVectorElementType(), Ext, Idx);
7699 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
7702 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7704 unsigned MaxSift = VecVT.getSizeInBits() - 1;
7705 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
7706 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
7707 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
7708 DAG.getConstant(MaxSift, MVT::i8));
7710 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i1, Vec,
7711 DAG.getIntPtrConstant(0));
7715 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
7716 SelectionDAG &DAG) const {
7718 SDValue Vec = Op.getOperand(0);
7719 MVT VecVT = Vec.getSimpleValueType();
7720 SDValue Idx = Op.getOperand(1);
7722 if (Op.getSimpleValueType() == MVT::i1)
7723 return ExtractBitFromMaskVector(Op, DAG);
7725 if (!isa<ConstantSDNode>(Idx)) {
7726 if (VecVT.is512BitVector() ||
7727 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
7728 VecVT.getVectorElementType().getSizeInBits() == 32)) {
7731 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
7732 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
7733 MaskEltVT.getSizeInBits());
7735 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
7736 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
7737 getZeroVector(MaskVT, Subtarget, DAG, dl),
7738 Idx, DAG.getConstant(0, getPointerTy()));
7739 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
7740 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
7741 Perm, DAG.getConstant(0, getPointerTy()));
7746 // If this is a 256-bit vector result, first extract the 128-bit vector and
7747 // then extract the element from the 128-bit vector.
7748 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
7750 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7751 // Get the 128-bit vector.
7752 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
7753 MVT EltVT = VecVT.getVectorElementType();
7755 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
7757 //if (IdxVal >= NumElems/2)
7758 // IdxVal -= NumElems/2;
7759 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
7760 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
7761 DAG.getConstant(IdxVal, MVT::i32));
7764 assert(VecVT.is128BitVector() && "Unexpected vector length");
7766 if (Subtarget->hasSSE41()) {
7767 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
7772 MVT VT = Op.getSimpleValueType();
7773 // TODO: handle v16i8.
7774 if (VT.getSizeInBits() == 16) {
7775 SDValue Vec = Op.getOperand(0);
7776 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7778 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
7779 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7780 DAG.getNode(ISD::BITCAST, dl,
7783 // Transform it so it match pextrw which produces a 32-bit result.
7784 MVT EltVT = MVT::i32;
7785 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
7786 Op.getOperand(0), Op.getOperand(1));
7787 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
7788 DAG.getValueType(VT));
7789 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7792 if (VT.getSizeInBits() == 32) {
7793 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7797 // SHUFPS the element to the lowest double word, then movss.
7798 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
7799 MVT VVT = Op.getOperand(0).getSimpleValueType();
7800 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
7801 DAG.getUNDEF(VVT), Mask);
7802 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
7803 DAG.getIntPtrConstant(0));
7806 if (VT.getSizeInBits() == 64) {
7807 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
7808 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
7809 // to match extract_elt for f64.
7810 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7814 // UNPCKHPD the element to the lowest double word, then movsd.
7815 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
7816 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
7817 int Mask[2] = { 1, -1 };
7818 MVT VVT = Op.getOperand(0).getSimpleValueType();
7819 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
7820 DAG.getUNDEF(VVT), Mask);
7821 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
7822 DAG.getIntPtrConstant(0));
7828 static SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
7829 MVT VT = Op.getSimpleValueType();
7830 MVT EltVT = VT.getVectorElementType();
7833 SDValue N0 = Op.getOperand(0);
7834 SDValue N1 = Op.getOperand(1);
7835 SDValue N2 = Op.getOperand(2);
7837 if (!VT.is128BitVector())
7840 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
7841 isa<ConstantSDNode>(N2)) {
7843 if (VT == MVT::v8i16)
7844 Opc = X86ISD::PINSRW;
7845 else if (VT == MVT::v16i8)
7846 Opc = X86ISD::PINSRB;
7848 Opc = X86ISD::PINSRB;
7850 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
7852 if (N1.getValueType() != MVT::i32)
7853 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
7854 if (N2.getValueType() != MVT::i32)
7855 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
7856 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
7859 if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
7860 // Bits [7:6] of the constant are the source select. This will always be
7861 // zero here. The DAG Combiner may combine an extract_elt index into these
7862 // bits. For example (insert (extract, 3), 2) could be matched by putting
7863 // the '3' into bits [7:6] of X86ISD::INSERTPS.
7864 // Bits [5:4] of the constant are the destination select. This is the
7865 // value of the incoming immediate.
7866 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
7867 // combine either bitwise AND or insert of float 0.0 to set these bits.
7868 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
7869 // Create this as a scalar to vector..
7870 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
7871 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
7874 if ((EltVT == MVT::i32 || EltVT == MVT::i64) && isa<ConstantSDNode>(N2)) {
7875 // PINSR* works with constant index.
7882 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
7883 MVT VT = Op.getSimpleValueType();
7884 MVT EltVT = VT.getVectorElementType();
7887 SDValue N0 = Op.getOperand(0);
7888 SDValue N1 = Op.getOperand(1);
7889 SDValue N2 = Op.getOperand(2);
7891 // If this is a 256-bit vector result, first extract the 128-bit vector,
7892 // insert the element into the extracted half and then place it back.
7893 if (VT.is256BitVector() || VT.is512BitVector()) {
7894 if (!isa<ConstantSDNode>(N2))
7897 // Get the desired 128-bit vector half.
7898 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue();
7899 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
7901 // Insert the element into the desired half.
7902 unsigned NumEltsIn128 = 128/EltVT.getSizeInBits();
7903 unsigned IdxIn128 = IdxVal - (IdxVal/NumEltsIn128) * NumEltsIn128;
7905 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
7906 DAG.getConstant(IdxIn128, MVT::i32));
7908 // Insert the changed part back to the 256-bit vector
7909 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
7912 if (Subtarget->hasSSE41())
7913 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
7915 if (EltVT == MVT::i8)
7918 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
7919 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
7920 // as its second argument.
7921 if (N1.getValueType() != MVT::i32)
7922 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
7923 if (N2.getValueType() != MVT::i32)
7924 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
7925 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
7930 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
7932 MVT OpVT = Op.getSimpleValueType();
7934 // If this is a 256-bit vector result, first insert into a 128-bit
7935 // vector and then insert into the 256-bit vector.
7936 if (!OpVT.is128BitVector()) {
7937 // Insert into a 128-bit vector.
7938 unsigned SizeFactor = OpVT.getSizeInBits()/128;
7939 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
7940 OpVT.getVectorNumElements() / SizeFactor);
7942 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
7944 // Insert the 128-bit vector.
7945 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
7948 if (OpVT == MVT::v1i64 &&
7949 Op.getOperand(0).getValueType() == MVT::i64)
7950 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
7952 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
7953 assert(OpVT.is128BitVector() && "Expected an SSE type!");
7954 return DAG.getNode(ISD::BITCAST, dl, OpVT,
7955 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
7958 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
7959 // a simple subregister reference or explicit instructions to grab
7960 // upper bits of a vector.
7961 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
7962 SelectionDAG &DAG) {
7964 SDValue In = Op.getOperand(0);
7965 SDValue Idx = Op.getOperand(1);
7966 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7967 MVT ResVT = Op.getSimpleValueType();
7968 MVT InVT = In.getSimpleValueType();
7970 if (Subtarget->hasFp256()) {
7971 if (ResVT.is128BitVector() &&
7972 (InVT.is256BitVector() || InVT.is512BitVector()) &&
7973 isa<ConstantSDNode>(Idx)) {
7974 return Extract128BitVector(In, IdxVal, DAG, dl);
7976 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
7977 isa<ConstantSDNode>(Idx)) {
7978 return Extract256BitVector(In, IdxVal, DAG, dl);
7984 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
7985 // simple superregister reference or explicit instructions to insert
7986 // the upper bits of a vector.
7987 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
7988 SelectionDAG &DAG) {
7989 if (Subtarget->hasFp256()) {
7990 SDLoc dl(Op.getNode());
7991 SDValue Vec = Op.getNode()->getOperand(0);
7992 SDValue SubVec = Op.getNode()->getOperand(1);
7993 SDValue Idx = Op.getNode()->getOperand(2);
7995 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() ||
7996 Op.getNode()->getSimpleValueType(0).is512BitVector()) &&
7997 SubVec.getNode()->getSimpleValueType(0).is128BitVector() &&
7998 isa<ConstantSDNode>(Idx)) {
7999 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
8000 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
8003 if (Op.getNode()->getSimpleValueType(0).is512BitVector() &&
8004 SubVec.getNode()->getSimpleValueType(0).is256BitVector() &&
8005 isa<ConstantSDNode>(Idx)) {
8006 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
8007 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
8013 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
8014 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
8015 // one of the above mentioned nodes. It has to be wrapped because otherwise
8016 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
8017 // be used to form addressing mode. These wrapped nodes will be selected
8020 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
8021 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
8023 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
8025 unsigned char OpFlag = 0;
8026 unsigned WrapperKind = X86ISD::Wrapper;
8027 CodeModel::Model M = getTargetMachine().getCodeModel();
8029 if (Subtarget->isPICStyleRIPRel() &&
8030 (M == CodeModel::Small || M == CodeModel::Kernel))
8031 WrapperKind = X86ISD::WrapperRIP;
8032 else if (Subtarget->isPICStyleGOT())
8033 OpFlag = X86II::MO_GOTOFF;
8034 else if (Subtarget->isPICStyleStubPIC())
8035 OpFlag = X86II::MO_PIC_BASE_OFFSET;
8037 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
8039 CP->getOffset(), OpFlag);
8041 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
8042 // With PIC, the address is actually $g + Offset.
8044 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8045 DAG.getNode(X86ISD::GlobalBaseReg,
8046 SDLoc(), getPointerTy()),
8053 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
8054 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
8056 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
8058 unsigned char OpFlag = 0;
8059 unsigned WrapperKind = X86ISD::Wrapper;
8060 CodeModel::Model M = getTargetMachine().getCodeModel();
8062 if (Subtarget->isPICStyleRIPRel() &&
8063 (M == CodeModel::Small || M == CodeModel::Kernel))
8064 WrapperKind = X86ISD::WrapperRIP;
8065 else if (Subtarget->isPICStyleGOT())
8066 OpFlag = X86II::MO_GOTOFF;
8067 else if (Subtarget->isPICStyleStubPIC())
8068 OpFlag = X86II::MO_PIC_BASE_OFFSET;
8070 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
8073 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
8075 // With PIC, the address is actually $g + Offset.
8077 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8078 DAG.getNode(X86ISD::GlobalBaseReg,
8079 SDLoc(), getPointerTy()),
8086 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
8087 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
8089 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
8091 unsigned char OpFlag = 0;
8092 unsigned WrapperKind = X86ISD::Wrapper;
8093 CodeModel::Model M = getTargetMachine().getCodeModel();
8095 if (Subtarget->isPICStyleRIPRel() &&
8096 (M == CodeModel::Small || M == CodeModel::Kernel)) {
8097 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
8098 OpFlag = X86II::MO_GOTPCREL;
8099 WrapperKind = X86ISD::WrapperRIP;
8100 } else if (Subtarget->isPICStyleGOT()) {
8101 OpFlag = X86II::MO_GOT;
8102 } else if (Subtarget->isPICStyleStubPIC()) {
8103 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
8104 } else if (Subtarget->isPICStyleStubNoDynamic()) {
8105 OpFlag = X86II::MO_DARWIN_NONLAZY;
8108 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
8111 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
8113 // With PIC, the address is actually $g + Offset.
8114 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
8115 !Subtarget->is64Bit()) {
8116 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8117 DAG.getNode(X86ISD::GlobalBaseReg,
8118 SDLoc(), getPointerTy()),
8122 // For symbols that require a load from a stub to get the address, emit the
8124 if (isGlobalStubReference(OpFlag))
8125 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
8126 MachinePointerInfo::getGOT(), false, false, false, 0);
8132 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
8133 // Create the TargetBlockAddressAddress node.
8134 unsigned char OpFlags =
8135 Subtarget->ClassifyBlockAddressReference();
8136 CodeModel::Model M = getTargetMachine().getCodeModel();
8137 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
8138 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
8140 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
8143 if (Subtarget->isPICStyleRIPRel() &&
8144 (M == CodeModel::Small || M == CodeModel::Kernel))
8145 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
8147 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
8149 // With PIC, the address is actually $g + Offset.
8150 if (isGlobalRelativeToPICBase(OpFlags)) {
8151 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
8152 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
8160 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
8161 int64_t Offset, SelectionDAG &DAG) const {
8162 // Create the TargetGlobalAddress node, folding in the constant
8163 // offset if it is legal.
8164 unsigned char OpFlags =
8165 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
8166 CodeModel::Model M = getTargetMachine().getCodeModel();
8168 if (OpFlags == X86II::MO_NO_FLAG &&
8169 X86::isOffsetSuitableForCodeModel(Offset, M)) {
8170 // A direct static reference to a global.
8171 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
8174 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
8177 if (Subtarget->isPICStyleRIPRel() &&
8178 (M == CodeModel::Small || M == CodeModel::Kernel))
8179 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
8181 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
8183 // With PIC, the address is actually $g + Offset.
8184 if (isGlobalRelativeToPICBase(OpFlags)) {
8185 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
8186 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
8190 // For globals that require a load from a stub to get the address, emit the
8192 if (isGlobalStubReference(OpFlags))
8193 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
8194 MachinePointerInfo::getGOT(), false, false, false, 0);
8196 // If there was a non-zero offset that we didn't fold, create an explicit
8199 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
8200 DAG.getConstant(Offset, getPointerTy()));
8206 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
8207 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
8208 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
8209 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
8213 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
8214 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
8215 unsigned char OperandFlags, bool LocalDynamic = false) {
8216 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
8217 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
8219 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
8220 GA->getValueType(0),
8224 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
8228 SDValue Ops[] = { Chain, TGA, *InFlag };
8229 Chain = DAG.getNode(CallType, dl, NodeTys, Ops, array_lengthof(Ops));
8231 SDValue Ops[] = { Chain, TGA };
8232 Chain = DAG.getNode(CallType, dl, NodeTys, Ops, array_lengthof(Ops));
8235 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
8236 MFI->setAdjustsStack(true);
8238 SDValue Flag = Chain.getValue(1);
8239 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
8242 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
8244 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
8247 SDLoc dl(GA); // ? function entry point might be better
8248 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
8249 DAG.getNode(X86ISD::GlobalBaseReg,
8250 SDLoc(), PtrVT), InFlag);
8251 InFlag = Chain.getValue(1);
8253 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
8256 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
8258 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
8260 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
8261 X86::RAX, X86II::MO_TLSGD);
8264 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
8270 // Get the start address of the TLS block for this module.
8271 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
8272 .getInfo<X86MachineFunctionInfo>();
8273 MFI->incNumLocalDynamicTLSAccesses();
8277 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT, X86::RAX,
8278 X86II::MO_TLSLD, /*LocalDynamic=*/true);
8281 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
8282 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
8283 InFlag = Chain.getValue(1);
8284 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
8285 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
8288 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
8292 unsigned char OperandFlags = X86II::MO_DTPOFF;
8293 unsigned WrapperKind = X86ISD::Wrapper;
8294 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
8295 GA->getValueType(0),
8296 GA->getOffset(), OperandFlags);
8297 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
8299 // Add x@dtpoff with the base.
8300 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
8303 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
8304 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
8305 const EVT PtrVT, TLSModel::Model model,
8306 bool is64Bit, bool isPIC) {
8309 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
8310 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
8311 is64Bit ? 257 : 256));
8313 SDValue ThreadPointer =
8314 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
8315 MachinePointerInfo(Ptr), false, false, false, 0);
8317 unsigned char OperandFlags = 0;
8318 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
8320 unsigned WrapperKind = X86ISD::Wrapper;
8321 if (model == TLSModel::LocalExec) {
8322 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
8323 } else if (model == TLSModel::InitialExec) {
8325 OperandFlags = X86II::MO_GOTTPOFF;
8326 WrapperKind = X86ISD::WrapperRIP;
8328 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
8331 llvm_unreachable("Unexpected model");
8334 // emit "addl x@ntpoff,%eax" (local exec)
8335 // or "addl x@indntpoff,%eax" (initial exec)
8336 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
8338 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
8339 GA->getOffset(), OperandFlags);
8340 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
8342 if (model == TLSModel::InitialExec) {
8343 if (isPIC && !is64Bit) {
8344 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
8345 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
8349 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
8350 MachinePointerInfo::getGOT(), false, false, false, 0);
8353 // The address of the thread local variable is the add of the thread
8354 // pointer with the offset of the variable.
8355 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
8359 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
8361 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
8362 const GlobalValue *GV = GA->getGlobal();
8364 if (Subtarget->isTargetELF()) {
8365 TLSModel::Model model = getTargetMachine().getTLSModel(GV);
8368 case TLSModel::GeneralDynamic:
8369 if (Subtarget->is64Bit())
8370 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
8371 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
8372 case TLSModel::LocalDynamic:
8373 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
8374 Subtarget->is64Bit());
8375 case TLSModel::InitialExec:
8376 case TLSModel::LocalExec:
8377 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
8378 Subtarget->is64Bit(),
8379 getTargetMachine().getRelocationModel() == Reloc::PIC_);
8381 llvm_unreachable("Unknown TLS model.");
8384 if (Subtarget->isTargetDarwin()) {
8385 // Darwin only has one model of TLS. Lower to that.
8386 unsigned char OpFlag = 0;
8387 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
8388 X86ISD::WrapperRIP : X86ISD::Wrapper;
8390 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
8392 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
8393 !Subtarget->is64Bit();
8395 OpFlag = X86II::MO_TLVP_PIC_BASE;
8397 OpFlag = X86II::MO_TLVP;
8399 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
8400 GA->getValueType(0),
8401 GA->getOffset(), OpFlag);
8402 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
8404 // With PIC32, the address is actually $g + Offset.
8406 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8407 DAG.getNode(X86ISD::GlobalBaseReg,
8408 SDLoc(), getPointerTy()),
8411 // Lowering the machine isd will make sure everything is in the right
8413 SDValue Chain = DAG.getEntryNode();
8414 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
8415 SDValue Args[] = { Chain, Offset };
8416 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2);
8418 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
8419 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
8420 MFI->setAdjustsStack(true);
8422 // And our return value (tls address) is in the standard call return value
8424 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
8425 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
8429 if (Subtarget->isTargetWindows() || Subtarget->isTargetMingw()) {
8430 // Just use the implicit TLS architecture
8431 // Need to generate someting similar to:
8432 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
8434 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
8435 // mov rcx, qword [rdx+rcx*8]
8436 // mov eax, .tls$:tlsvar
8437 // [rax+rcx] contains the address
8438 // Windows 64bit: gs:0x58
8439 // Windows 32bit: fs:__tls_array
8441 // If GV is an alias then use the aliasee for determining
8442 // thread-localness.
8443 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
8444 GV = GA->resolveAliasedGlobal(false);
8446 SDValue Chain = DAG.getEntryNode();
8448 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
8449 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
8450 // use its literal value of 0x2C.
8451 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
8452 ? Type::getInt8PtrTy(*DAG.getContext(),
8454 : Type::getInt32PtrTy(*DAG.getContext(),
8457 SDValue TlsArray = Subtarget->is64Bit() ? DAG.getIntPtrConstant(0x58) :
8458 (Subtarget->isTargetMingw() ? DAG.getIntPtrConstant(0x2C) :
8459 DAG.getExternalSymbol("_tls_array", getPointerTy()));
8461 SDValue ThreadPointer = DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
8462 MachinePointerInfo(Ptr),
8463 false, false, false, 0);
8465 // Load the _tls_index variable
8466 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
8467 if (Subtarget->is64Bit())
8468 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
8469 IDX, MachinePointerInfo(), MVT::i32,
8472 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
8473 false, false, false, 0);
8475 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
8477 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
8479 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
8480 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
8481 false, false, false, 0);
8483 // Get the offset of start of .tls section
8484 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
8485 GA->getValueType(0),
8486 GA->getOffset(), X86II::MO_SECREL);
8487 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
8489 // The address of the thread local variable is the add of the thread
8490 // pointer with the offset of the variable.
8491 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
8494 llvm_unreachable("TLS not implemented for this target.");
8497 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
8498 /// and take a 2 x i32 value to shift plus a shift amount.
8499 SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const{
8500 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
8501 EVT VT = Op.getValueType();
8502 unsigned VTBits = VT.getSizeInBits();
8504 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
8505 SDValue ShOpLo = Op.getOperand(0);
8506 SDValue ShOpHi = Op.getOperand(1);
8507 SDValue ShAmt = Op.getOperand(2);
8508 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
8509 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
8511 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
8512 DAG.getConstant(VTBits - 1, MVT::i8));
8513 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
8514 DAG.getConstant(VTBits - 1, MVT::i8))
8515 : DAG.getConstant(0, VT);
8518 if (Op.getOpcode() == ISD::SHL_PARTS) {
8519 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
8520 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
8522 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
8523 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
8526 // If the shift amount is larger or equal than the width of a part we can't
8527 // rely on the results of shld/shrd. Insert a test and select the appropriate
8528 // values for large shift amounts.
8529 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
8530 DAG.getConstant(VTBits, MVT::i8));
8531 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
8532 AndNode, DAG.getConstant(0, MVT::i8));
8535 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8536 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
8537 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
8539 if (Op.getOpcode() == ISD::SHL_PARTS) {
8540 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
8541 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
8543 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
8544 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
8547 SDValue Ops[2] = { Lo, Hi };
8548 return DAG.getMergeValues(Ops, array_lengthof(Ops), dl);
8551 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
8552 SelectionDAG &DAG) const {
8553 EVT SrcVT = Op.getOperand(0).getValueType();
8555 if (SrcVT.isVector())
8558 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
8559 "Unknown SINT_TO_FP to lower!");
8561 // These are really Legal; return the operand so the caller accepts it as
8563 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
8565 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
8566 Subtarget->is64Bit()) {
8571 unsigned Size = SrcVT.getSizeInBits()/8;
8572 MachineFunction &MF = DAG.getMachineFunction();
8573 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
8574 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8575 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
8577 MachinePointerInfo::getFixedStack(SSFI),
8579 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
8582 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
8584 SelectionDAG &DAG) const {
8588 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
8590 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
8592 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
8594 unsigned ByteSize = SrcVT.getSizeInBits()/8;
8596 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
8597 MachineMemOperand *MMO;
8599 int SSFI = FI->getIndex();
8601 DAG.getMachineFunction()
8602 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8603 MachineMemOperand::MOLoad, ByteSize, ByteSize);
8605 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
8606 StackSlot = StackSlot.getOperand(1);
8608 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
8609 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
8611 Tys, Ops, array_lengthof(Ops),
8615 Chain = Result.getValue(1);
8616 SDValue InFlag = Result.getValue(2);
8618 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
8619 // shouldn't be necessary except that RFP cannot be live across
8620 // multiple blocks. When stackifier is fixed, they can be uncoupled.
8621 MachineFunction &MF = DAG.getMachineFunction();
8622 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
8623 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
8624 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8625 Tys = DAG.getVTList(MVT::Other);
8627 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
8629 MachineMemOperand *MMO =
8630 DAG.getMachineFunction()
8631 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8632 MachineMemOperand::MOStore, SSFISize, SSFISize);
8634 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
8635 Ops, array_lengthof(Ops),
8636 Op.getValueType(), MMO);
8637 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
8638 MachinePointerInfo::getFixedStack(SSFI),
8639 false, false, false, 0);
8645 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
8646 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
8647 SelectionDAG &DAG) const {
8648 // This algorithm is not obvious. Here it is what we're trying to output:
8651 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
8652 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
8656 pshufd $0x4e, %xmm0, %xmm1
8662 LLVMContext *Context = DAG.getContext();
8664 // Build some magic constants.
8665 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
8666 Constant *C0 = ConstantDataVector::get(*Context, CV0);
8667 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
8669 SmallVector<Constant*,2> CV1;
8671 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
8672 APInt(64, 0x4330000000000000ULL))));
8674 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
8675 APInt(64, 0x4530000000000000ULL))));
8676 Constant *C1 = ConstantVector::get(CV1);
8677 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
8679 // Load the 64-bit value into an XMM register.
8680 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
8682 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
8683 MachinePointerInfo::getConstantPool(),
8684 false, false, false, 16);
8685 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
8686 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
8689 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
8690 MachinePointerInfo::getConstantPool(),
8691 false, false, false, 16);
8692 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
8693 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
8696 if (Subtarget->hasSSE3()) {
8697 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
8698 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
8700 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
8701 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
8703 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
8704 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
8708 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
8709 DAG.getIntPtrConstant(0));
8712 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
8713 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
8714 SelectionDAG &DAG) const {
8716 // FP constant to bias correct the final result.
8717 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
8720 // Load the 32-bit value into an XMM register.
8721 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
8724 // Zero out the upper parts of the register.
8725 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
8727 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
8728 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
8729 DAG.getIntPtrConstant(0));
8731 // Or the load with the bias.
8732 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
8733 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
8734 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
8736 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
8737 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
8738 MVT::v2f64, Bias)));
8739 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
8740 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
8741 DAG.getIntPtrConstant(0));
8743 // Subtract the bias.
8744 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
8746 // Handle final rounding.
8747 EVT DestVT = Op.getValueType();
8749 if (DestVT.bitsLT(MVT::f64))
8750 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
8751 DAG.getIntPtrConstant(0));
8752 if (DestVT.bitsGT(MVT::f64))
8753 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
8755 // Handle final rounding.
8759 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
8760 SelectionDAG &DAG) const {
8761 SDValue N0 = Op.getOperand(0);
8762 EVT SVT = N0.getValueType();
8765 assert((SVT == MVT::v4i8 || SVT == MVT::v4i16 ||
8766 SVT == MVT::v8i8 || SVT == MVT::v8i16) &&
8767 "Custom UINT_TO_FP is not supported!");
8769 EVT NVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
8770 SVT.getVectorNumElements());
8771 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
8772 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
8775 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
8776 SelectionDAG &DAG) const {
8777 SDValue N0 = Op.getOperand(0);
8780 if (Op.getValueType().isVector())
8781 return lowerUINT_TO_FP_vec(Op, DAG);
8783 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
8784 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
8785 // the optimization here.
8786 if (DAG.SignBitIsZero(N0))
8787 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
8789 EVT SrcVT = N0.getValueType();
8790 EVT DstVT = Op.getValueType();
8791 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
8792 return LowerUINT_TO_FP_i64(Op, DAG);
8793 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
8794 return LowerUINT_TO_FP_i32(Op, DAG);
8795 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
8798 // Make a 64-bit buffer, and use it to build an FILD.
8799 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
8800 if (SrcVT == MVT::i32) {
8801 SDValue WordOff = DAG.getConstant(4, getPointerTy());
8802 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
8803 getPointerTy(), StackSlot, WordOff);
8804 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
8805 StackSlot, MachinePointerInfo(),
8807 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
8808 OffsetSlot, MachinePointerInfo(),
8810 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
8814 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
8815 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
8816 StackSlot, MachinePointerInfo(),
8818 // For i64 source, we need to add the appropriate power of 2 if the input
8819 // was negative. This is the same as the optimization in
8820 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
8821 // we must be careful to do the computation in x87 extended precision, not
8822 // in SSE. (The generic code can't know it's OK to do this, or how to.)
8823 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
8824 MachineMemOperand *MMO =
8825 DAG.getMachineFunction()
8826 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8827 MachineMemOperand::MOLoad, 8, 8);
8829 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
8830 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
8831 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
8832 array_lengthof(Ops), MVT::i64, MMO);
8834 APInt FF(32, 0x5F800000ULL);
8836 // Check whether the sign bit is set.
8837 SDValue SignSet = DAG.getSetCC(dl,
8838 getSetCCResultType(*DAG.getContext(), MVT::i64),
8839 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
8842 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
8843 SDValue FudgePtr = DAG.getConstantPool(
8844 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
8847 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
8848 SDValue Zero = DAG.getIntPtrConstant(0);
8849 SDValue Four = DAG.getIntPtrConstant(4);
8850 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
8852 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
8854 // Load the value out, extending it from f32 to f80.
8855 // FIXME: Avoid the extend by constructing the right constant pool?
8856 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
8857 FudgePtr, MachinePointerInfo::getConstantPool(),
8858 MVT::f32, false, false, 4);
8859 // Extend everything to 80 bits to force it to be done on x87.
8860 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
8861 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
8864 std::pair<SDValue,SDValue>
8865 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
8866 bool IsSigned, bool IsReplace) const {
8869 EVT DstTy = Op.getValueType();
8871 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
8872 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
8876 assert(DstTy.getSimpleVT() <= MVT::i64 &&
8877 DstTy.getSimpleVT() >= MVT::i16 &&
8878 "Unknown FP_TO_INT to lower!");
8880 // These are really Legal.
8881 if (DstTy == MVT::i32 &&
8882 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
8883 return std::make_pair(SDValue(), SDValue());
8884 if (Subtarget->is64Bit() &&
8885 DstTy == MVT::i64 &&
8886 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
8887 return std::make_pair(SDValue(), SDValue());
8889 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
8890 // stack slot, or into the FTOL runtime function.
8891 MachineFunction &MF = DAG.getMachineFunction();
8892 unsigned MemSize = DstTy.getSizeInBits()/8;
8893 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
8894 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8897 if (!IsSigned && isIntegerTypeFTOL(DstTy))
8898 Opc = X86ISD::WIN_FTOL;
8900 switch (DstTy.getSimpleVT().SimpleTy) {
8901 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
8902 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
8903 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
8904 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
8907 SDValue Chain = DAG.getEntryNode();
8908 SDValue Value = Op.getOperand(0);
8909 EVT TheVT = Op.getOperand(0).getValueType();
8910 // FIXME This causes a redundant load/store if the SSE-class value is already
8911 // in memory, such as if it is on the callstack.
8912 if (isScalarFPTypeInSSEReg(TheVT)) {
8913 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
8914 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
8915 MachinePointerInfo::getFixedStack(SSFI),
8917 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
8919 Chain, StackSlot, DAG.getValueType(TheVT)
8922 MachineMemOperand *MMO =
8923 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8924 MachineMemOperand::MOLoad, MemSize, MemSize);
8925 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops,
8926 array_lengthof(Ops), DstTy, MMO);
8927 Chain = Value.getValue(1);
8928 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
8929 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8932 MachineMemOperand *MMO =
8933 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8934 MachineMemOperand::MOStore, MemSize, MemSize);
8936 if (Opc != X86ISD::WIN_FTOL) {
8937 // Build the FP_TO_INT*_IN_MEM
8938 SDValue Ops[] = { Chain, Value, StackSlot };
8939 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
8940 Ops, array_lengthof(Ops), DstTy,
8942 return std::make_pair(FIST, StackSlot);
8944 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
8945 DAG.getVTList(MVT::Other, MVT::Glue),
8947 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
8948 MVT::i32, ftol.getValue(1));
8949 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
8950 MVT::i32, eax.getValue(2));
8951 SDValue Ops[] = { eax, edx };
8952 SDValue pair = IsReplace
8953 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops, array_lengthof(Ops))
8954 : DAG.getMergeValues(Ops, array_lengthof(Ops), DL);
8955 return std::make_pair(pair, SDValue());
8959 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
8960 const X86Subtarget *Subtarget) {
8961 MVT VT = Op->getSimpleValueType(0);
8962 SDValue In = Op->getOperand(0);
8963 MVT InVT = In.getSimpleValueType();
8966 // Optimize vectors in AVX mode:
8969 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
8970 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
8971 // Concat upper and lower parts.
8974 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
8975 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
8976 // Concat upper and lower parts.
8979 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
8980 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
8981 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
8984 if (Subtarget->hasInt256())
8985 return DAG.getNode(X86ISD::VZEXT_MOVL, dl, VT, In);
8987 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
8988 SDValue Undef = DAG.getUNDEF(InVT);
8989 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
8990 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
8991 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
8993 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
8994 VT.getVectorNumElements()/2);
8996 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
8997 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
8999 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
9002 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
9003 SelectionDAG &DAG) {
9004 MVT VT = Op->getValueType(0).getSimpleVT();
9005 SDValue In = Op->getOperand(0);
9006 MVT InVT = In.getValueType().getSimpleVT();
9008 unsigned int NumElts = VT.getVectorNumElements();
9009 if (NumElts != 8 && NumElts != 16)
9012 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
9013 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
9015 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
9016 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9017 // Now we have only mask extension
9018 assert(InVT.getVectorElementType() == MVT::i1);
9019 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
9020 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
9021 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
9022 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
9023 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
9024 MachinePointerInfo::getConstantPool(),
9025 false, false, false, Alignment);
9027 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
9028 if (VT.is512BitVector())
9030 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
9033 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
9034 SelectionDAG &DAG) {
9035 if (Subtarget->hasFp256()) {
9036 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
9044 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
9045 SelectionDAG &DAG) {
9047 MVT VT = Op.getSimpleValueType();
9048 SDValue In = Op.getOperand(0);
9049 MVT SVT = In.getSimpleValueType();
9051 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
9052 return LowerZERO_EXTEND_AVX512(Op, DAG);
9054 if (Subtarget->hasFp256()) {
9055 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
9060 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
9061 VT.getVectorNumElements() != SVT.getVectorNumElements());
9065 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
9067 MVT VT = Op.getSimpleValueType();
9068 SDValue In = Op.getOperand(0);
9069 MVT InVT = In.getSimpleValueType();
9071 if (VT == MVT::i1) {
9072 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
9073 "Invalid scalar TRUNCATE operation");
9074 In = DAG.getNode(ISD::AND, DL, InVT, In, DAG.getConstant(1, InVT));
9075 if (InVT.getSizeInBits() == 64)
9076 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::i32, In);
9077 else if (InVT.getSizeInBits() < 32)
9078 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
9079 return DAG.getNode(X86ISD::TRUNC, DL, VT, In);
9081 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
9082 "Invalid TRUNCATE operation");
9084 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
9085 if (VT.getVectorElementType().getSizeInBits() >=8)
9086 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
9088 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
9089 unsigned NumElts = InVT.getVectorNumElements();
9090 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
9091 if (InVT.getSizeInBits() < 512) {
9092 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
9093 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
9096 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
9097 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
9098 SDValue CP = DAG.getConstantPool(C, getPointerTy());
9099 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
9100 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
9101 MachinePointerInfo::getConstantPool(),
9102 false, false, false, Alignment);
9103 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
9104 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
9105 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
9108 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
9109 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
9110 if (Subtarget->hasInt256()) {
9111 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
9112 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
9113 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
9115 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
9116 DAG.getIntPtrConstant(0));
9119 // On AVX, v4i64 -> v4i32 becomes a sequence that uses PSHUFD and MOVLHPS.
9120 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
9121 DAG.getIntPtrConstant(0));
9122 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
9123 DAG.getIntPtrConstant(2));
9125 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
9126 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
9129 static const int ShufMask1[] = {0, 2, 0, 0};
9130 SDValue Undef = DAG.getUNDEF(VT);
9131 OpLo = DAG.getVectorShuffle(VT, DL, OpLo, Undef, ShufMask1);
9132 OpHi = DAG.getVectorShuffle(VT, DL, OpHi, Undef, ShufMask1);
9134 // The MOVLHPS mask:
9135 static const int ShufMask2[] = {0, 1, 4, 5};
9136 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask2);
9139 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
9140 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
9141 if (Subtarget->hasInt256()) {
9142 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
9144 SmallVector<SDValue,32> pshufbMask;
9145 for (unsigned i = 0; i < 2; ++i) {
9146 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
9147 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
9148 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
9149 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
9150 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
9151 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
9152 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
9153 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
9154 for (unsigned j = 0; j < 8; ++j)
9155 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
9157 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8,
9158 &pshufbMask[0], 32);
9159 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
9160 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
9162 static const int ShufMask[] = {0, 2, -1, -1};
9163 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
9165 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
9166 DAG.getIntPtrConstant(0));
9167 return DAG.getNode(ISD::BITCAST, DL, VT, In);
9170 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
9171 DAG.getIntPtrConstant(0));
9173 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
9174 DAG.getIntPtrConstant(4));
9176 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
9177 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
9180 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
9181 -1, -1, -1, -1, -1, -1, -1, -1};
9183 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
9184 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
9185 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
9187 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
9188 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
9190 // The MOVLHPS Mask:
9191 static const int ShufMask2[] = {0, 1, 4, 5};
9192 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
9193 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
9196 // Handle truncation of V256 to V128 using shuffles.
9197 if (!VT.is128BitVector() || !InVT.is256BitVector())
9200 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
9202 unsigned NumElems = VT.getVectorNumElements();
9203 EVT NVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
9206 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
9207 // Prepare truncation shuffle mask
9208 for (unsigned i = 0; i != NumElems; ++i)
9210 SDValue V = DAG.getVectorShuffle(NVT, DL,
9211 DAG.getNode(ISD::BITCAST, DL, NVT, In),
9212 DAG.getUNDEF(NVT), &MaskVec[0]);
9213 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
9214 DAG.getIntPtrConstant(0));
9217 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
9218 SelectionDAG &DAG) const {
9219 MVT VT = Op.getSimpleValueType();
9220 if (VT.isVector()) {
9221 if (VT == MVT::v8i16)
9222 return DAG.getNode(ISD::TRUNCATE, SDLoc(Op), VT,
9223 DAG.getNode(ISD::FP_TO_SINT, SDLoc(Op),
9224 MVT::v8i32, Op.getOperand(0)));
9228 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
9229 /*IsSigned=*/ true, /*IsReplace=*/ false);
9230 SDValue FIST = Vals.first, StackSlot = Vals.second;
9231 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
9232 if (FIST.getNode() == 0) return Op;
9234 if (StackSlot.getNode())
9236 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
9237 FIST, StackSlot, MachinePointerInfo(),
9238 false, false, false, 0);
9240 // The node is the result.
9244 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
9245 SelectionDAG &DAG) const {
9246 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
9247 /*IsSigned=*/ false, /*IsReplace=*/ false);
9248 SDValue FIST = Vals.first, StackSlot = Vals.second;
9249 assert(FIST.getNode() && "Unexpected failure");
9251 if (StackSlot.getNode())
9253 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
9254 FIST, StackSlot, MachinePointerInfo(),
9255 false, false, false, 0);
9257 // The node is the result.
9261 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
9263 MVT VT = Op.getSimpleValueType();
9264 SDValue In = Op.getOperand(0);
9265 MVT SVT = In.getSimpleValueType();
9267 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
9269 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
9270 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
9271 In, DAG.getUNDEF(SVT)));
9274 SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) const {
9275 LLVMContext *Context = DAG.getContext();
9277 MVT VT = Op.getSimpleValueType();
9279 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
9280 if (VT.isVector()) {
9281 EltVT = VT.getVectorElementType();
9282 NumElts = VT.getVectorNumElements();
9285 if (EltVT == MVT::f64)
9286 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
9287 APInt(64, ~(1ULL << 63))));
9289 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEsingle,
9290 APInt(32, ~(1U << 31))));
9291 C = ConstantVector::getSplat(NumElts, C);
9292 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy());
9293 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
9294 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9295 MachinePointerInfo::getConstantPool(),
9296 false, false, false, Alignment);
9297 if (VT.isVector()) {
9298 MVT ANDVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
9299 return DAG.getNode(ISD::BITCAST, dl, VT,
9300 DAG.getNode(ISD::AND, dl, ANDVT,
9301 DAG.getNode(ISD::BITCAST, dl, ANDVT,
9303 DAG.getNode(ISD::BITCAST, dl, ANDVT, Mask)));
9305 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
9308 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
9309 LLVMContext *Context = DAG.getContext();
9311 MVT VT = Op.getSimpleValueType();
9313 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
9314 if (VT.isVector()) {
9315 EltVT = VT.getVectorElementType();
9316 NumElts = VT.getVectorNumElements();
9319 if (EltVT == MVT::f64)
9320 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
9321 APInt(64, 1ULL << 63)));
9323 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEsingle,
9324 APInt(32, 1U << 31)));
9325 C = ConstantVector::getSplat(NumElts, C);
9326 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy());
9327 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
9328 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9329 MachinePointerInfo::getConstantPool(),
9330 false, false, false, Alignment);
9331 if (VT.isVector()) {
9332 MVT XORVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits()/64);
9333 return DAG.getNode(ISD::BITCAST, dl, VT,
9334 DAG.getNode(ISD::XOR, dl, XORVT,
9335 DAG.getNode(ISD::BITCAST, dl, XORVT,
9337 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask)));
9340 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
9343 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
9344 LLVMContext *Context = DAG.getContext();
9345 SDValue Op0 = Op.getOperand(0);
9346 SDValue Op1 = Op.getOperand(1);
9348 MVT VT = Op.getSimpleValueType();
9349 MVT SrcVT = Op1.getSimpleValueType();
9351 // If second operand is smaller, extend it first.
9352 if (SrcVT.bitsLT(VT)) {
9353 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
9356 // And if it is bigger, shrink it first.
9357 if (SrcVT.bitsGT(VT)) {
9358 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
9362 // At this point the operands and the result should have the same
9363 // type, and that won't be f80 since that is not custom lowered.
9365 // First get the sign bit of second operand.
9366 SmallVector<Constant*,4> CV;
9367 if (SrcVT == MVT::f64) {
9368 const fltSemantics &Sem = APFloat::IEEEdouble;
9369 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 1ULL << 63))));
9370 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
9372 const fltSemantics &Sem = APFloat::IEEEsingle;
9373 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 1U << 31))));
9374 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9375 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9376 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9378 Constant *C = ConstantVector::get(CV);
9379 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
9380 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
9381 MachinePointerInfo::getConstantPool(),
9382 false, false, false, 16);
9383 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
9385 // Shift sign bit right or left if the two operands have different types.
9386 if (SrcVT.bitsGT(VT)) {
9387 // Op0 is MVT::f32, Op1 is MVT::f64.
9388 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
9389 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
9390 DAG.getConstant(32, MVT::i32));
9391 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
9392 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
9393 DAG.getIntPtrConstant(0));
9396 // Clear first operand sign bit.
9398 if (VT == MVT::f64) {
9399 const fltSemantics &Sem = APFloat::IEEEdouble;
9400 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
9401 APInt(64, ~(1ULL << 63)))));
9402 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
9404 const fltSemantics &Sem = APFloat::IEEEsingle;
9405 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
9406 APInt(32, ~(1U << 31)))));
9407 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9408 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9409 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9411 C = ConstantVector::get(CV);
9412 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
9413 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9414 MachinePointerInfo::getConstantPool(),
9415 false, false, false, 16);
9416 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
9418 // Or the value with the sign bit.
9419 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
9422 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
9423 SDValue N0 = Op.getOperand(0);
9425 MVT VT = Op.getSimpleValueType();
9427 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
9428 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
9429 DAG.getConstant(1, VT));
9430 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
9433 // LowerVectorAllZeroTest - Check whether an OR'd tree is PTEST-able.
9435 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
9436 SelectionDAG &DAG) {
9437 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
9439 if (!Subtarget->hasSSE41())
9442 if (!Op->hasOneUse())
9445 SDNode *N = Op.getNode();
9448 SmallVector<SDValue, 8> Opnds;
9449 DenseMap<SDValue, unsigned> VecInMap;
9450 EVT VT = MVT::Other;
9452 // Recognize a special case where a vector is casted into wide integer to
9454 Opnds.push_back(N->getOperand(0));
9455 Opnds.push_back(N->getOperand(1));
9457 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
9458 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
9459 // BFS traverse all OR'd operands.
9460 if (I->getOpcode() == ISD::OR) {
9461 Opnds.push_back(I->getOperand(0));
9462 Opnds.push_back(I->getOperand(1));
9463 // Re-evaluate the number of nodes to be traversed.
9464 e += 2; // 2 more nodes (LHS and RHS) are pushed.
9468 // Quit if a non-EXTRACT_VECTOR_ELT
9469 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
9472 // Quit if without a constant index.
9473 SDValue Idx = I->getOperand(1);
9474 if (!isa<ConstantSDNode>(Idx))
9477 SDValue ExtractedFromVec = I->getOperand(0);
9478 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
9479 if (M == VecInMap.end()) {
9480 VT = ExtractedFromVec.getValueType();
9481 // Quit if not 128/256-bit vector.
9482 if (!VT.is128BitVector() && !VT.is256BitVector())
9484 // Quit if not the same type.
9485 if (VecInMap.begin() != VecInMap.end() &&
9486 VT != VecInMap.begin()->first.getValueType())
9488 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
9490 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
9493 assert((VT.is128BitVector() || VT.is256BitVector()) &&
9494 "Not extracted from 128-/256-bit vector.");
9496 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
9497 SmallVector<SDValue, 8> VecIns;
9499 for (DenseMap<SDValue, unsigned>::const_iterator
9500 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
9501 // Quit if not all elements are used.
9502 if (I->second != FullMask)
9504 VecIns.push_back(I->first);
9507 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
9509 // Cast all vectors into TestVT for PTEST.
9510 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
9511 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
9513 // If more than one full vectors are evaluated, OR them first before PTEST.
9514 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
9515 // Each iteration will OR 2 nodes and append the result until there is only
9516 // 1 node left, i.e. the final OR'd value of all vectors.
9517 SDValue LHS = VecIns[Slot];
9518 SDValue RHS = VecIns[Slot + 1];
9519 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
9522 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
9523 VecIns.back(), VecIns.back());
9526 /// Emit nodes that will be selected as "test Op0,Op0", or something
9528 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
9529 SelectionDAG &DAG) const {
9532 // CF and OF aren't always set the way we want. Determine which
9533 // of these we need.
9534 bool NeedCF = false;
9535 bool NeedOF = false;
9538 case X86::COND_A: case X86::COND_AE:
9539 case X86::COND_B: case X86::COND_BE:
9542 case X86::COND_G: case X86::COND_GE:
9543 case X86::COND_L: case X86::COND_LE:
9544 case X86::COND_O: case X86::COND_NO:
9549 // See if we can use the EFLAGS value from the operand instead of
9550 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
9551 // we prove that the arithmetic won't overflow, we can't use OF or CF.
9552 if (Op.getResNo() != 0 || NeedOF || NeedCF)
9553 // Emit a CMP with 0, which is the TEST pattern.
9554 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
9555 DAG.getConstant(0, Op.getValueType()));
9557 unsigned Opcode = 0;
9558 unsigned NumOperands = 0;
9560 // Truncate operations may prevent the merge of the SETCC instruction
9561 // and the arithmetic instruction before it. Attempt to truncate the operands
9562 // of the arithmetic instruction and use a reduced bit-width instruction.
9563 bool NeedTruncation = false;
9564 SDValue ArithOp = Op;
9565 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
9566 SDValue Arith = Op->getOperand(0);
9567 // Both the trunc and the arithmetic op need to have one user each.
9568 if (Arith->hasOneUse())
9569 switch (Arith.getOpcode()) {
9576 NeedTruncation = true;
9582 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
9583 // which may be the result of a CAST. We use the variable 'Op', which is the
9584 // non-casted variable when we check for possible users.
9585 switch (ArithOp.getOpcode()) {
9587 // Due to an isel shortcoming, be conservative if this add is likely to be
9588 // selected as part of a load-modify-store instruction. When the root node
9589 // in a match is a store, isel doesn't know how to remap non-chain non-flag
9590 // uses of other nodes in the match, such as the ADD in this case. This
9591 // leads to the ADD being left around and reselected, with the result being
9592 // two adds in the output. Alas, even if none our users are stores, that
9593 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
9594 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
9595 // climbing the DAG back to the root, and it doesn't seem to be worth the
9597 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
9598 UE = Op.getNode()->use_end(); UI != UE; ++UI)
9599 if (UI->getOpcode() != ISD::CopyToReg &&
9600 UI->getOpcode() != ISD::SETCC &&
9601 UI->getOpcode() != ISD::STORE)
9604 if (ConstantSDNode *C =
9605 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
9606 // An add of one will be selected as an INC.
9607 if (C->getAPIntValue() == 1) {
9608 Opcode = X86ISD::INC;
9613 // An add of negative one (subtract of one) will be selected as a DEC.
9614 if (C->getAPIntValue().isAllOnesValue()) {
9615 Opcode = X86ISD::DEC;
9621 // Otherwise use a regular EFLAGS-setting add.
9622 Opcode = X86ISD::ADD;
9626 // If the primary and result isn't used, don't bother using X86ISD::AND,
9627 // because a TEST instruction will be better.
9628 bool NonFlagUse = false;
9629 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
9630 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
9632 unsigned UOpNo = UI.getOperandNo();
9633 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
9634 // Look pass truncate.
9635 UOpNo = User->use_begin().getOperandNo();
9636 User = *User->use_begin();
9639 if (User->getOpcode() != ISD::BRCOND &&
9640 User->getOpcode() != ISD::SETCC &&
9641 !(User->getOpcode() == ISD::SELECT && UOpNo == 0)) {
9654 // Due to the ISEL shortcoming noted above, be conservative if this op is
9655 // likely to be selected as part of a load-modify-store instruction.
9656 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
9657 UE = Op.getNode()->use_end(); UI != UE; ++UI)
9658 if (UI->getOpcode() == ISD::STORE)
9661 // Otherwise use a regular EFLAGS-setting instruction.
9662 switch (ArithOp.getOpcode()) {
9663 default: llvm_unreachable("unexpected operator!");
9664 case ISD::SUB: Opcode = X86ISD::SUB; break;
9665 case ISD::XOR: Opcode = X86ISD::XOR; break;
9666 case ISD::AND: Opcode = X86ISD::AND; break;
9668 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
9669 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
9670 if (EFLAGS.getNode())
9673 Opcode = X86ISD::OR;
9687 return SDValue(Op.getNode(), 1);
9693 // If we found that truncation is beneficial, perform the truncation and
9695 if (NeedTruncation) {
9696 EVT VT = Op.getValueType();
9697 SDValue WideVal = Op->getOperand(0);
9698 EVT WideVT = WideVal.getValueType();
9699 unsigned ConvertedOp = 0;
9700 // Use a target machine opcode to prevent further DAGCombine
9701 // optimizations that may separate the arithmetic operations
9702 // from the setcc node.
9703 switch (WideVal.getOpcode()) {
9705 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
9706 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
9707 case ISD::AND: ConvertedOp = X86ISD::AND; break;
9708 case ISD::OR: ConvertedOp = X86ISD::OR; break;
9709 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
9713 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9714 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
9715 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
9716 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
9717 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
9723 // Emit a CMP with 0, which is the TEST pattern.
9724 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
9725 DAG.getConstant(0, Op.getValueType()));
9727 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
9728 SmallVector<SDValue, 4> Ops;
9729 for (unsigned i = 0; i != NumOperands; ++i)
9730 Ops.push_back(Op.getOperand(i));
9732 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
9733 DAG.ReplaceAllUsesWith(Op, New);
9734 return SDValue(New.getNode(), 1);
9737 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
9739 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
9740 SelectionDAG &DAG) const {
9742 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
9743 if (C->getAPIntValue() == 0)
9744 return EmitTest(Op0, X86CC, DAG);
9746 if (Op0.getValueType() == MVT::i1) {
9747 Op0 = DAG.getNode(ISD::XOR, dl, MVT::i1, Op0, DAG.getConstant(-1, MVT::i1));
9748 return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op0, Op0);
9752 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
9753 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
9754 // Do the comparison at i32 if it's smaller. This avoids subregister
9755 // aliasing issues. Keep the smaller reference if we're optimizing for
9756 // size, however, as that'll allow better folding of memory operations.
9757 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
9758 !DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
9759 AttributeSet::FunctionIndex, Attribute::MinSize)) {
9761 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
9762 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
9763 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
9765 // Use SUB instead of CMP to enable CSE between SUB and CMP.
9766 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
9767 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
9769 return SDValue(Sub.getNode(), 1);
9771 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
9774 /// Convert a comparison if required by the subtarget.
9775 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
9776 SelectionDAG &DAG) const {
9777 // If the subtarget does not support the FUCOMI instruction, floating-point
9778 // comparisons have to be converted.
9779 if (Subtarget->hasCMov() ||
9780 Cmp.getOpcode() != X86ISD::CMP ||
9781 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
9782 !Cmp.getOperand(1).getValueType().isFloatingPoint())
9785 // The instruction selector will select an FUCOM instruction instead of
9786 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
9787 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
9788 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
9790 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
9791 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
9792 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
9793 DAG.getConstant(8, MVT::i8));
9794 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
9795 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
9798 static bool isAllOnes(SDValue V) {
9799 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
9800 return C && C->isAllOnesValue();
9803 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
9804 /// if it's possible.
9805 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
9806 SDLoc dl, SelectionDAG &DAG) const {
9807 SDValue Op0 = And.getOperand(0);
9808 SDValue Op1 = And.getOperand(1);
9809 if (Op0.getOpcode() == ISD::TRUNCATE)
9810 Op0 = Op0.getOperand(0);
9811 if (Op1.getOpcode() == ISD::TRUNCATE)
9812 Op1 = Op1.getOperand(0);
9815 if (Op1.getOpcode() == ISD::SHL)
9816 std::swap(Op0, Op1);
9817 if (Op0.getOpcode() == ISD::SHL) {
9818 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
9819 if (And00C->getZExtValue() == 1) {
9820 // If we looked past a truncate, check that it's only truncating away
9822 unsigned BitWidth = Op0.getValueSizeInBits();
9823 unsigned AndBitWidth = And.getValueSizeInBits();
9824 if (BitWidth > AndBitWidth) {
9826 DAG.ComputeMaskedBits(Op0, Zeros, Ones);
9827 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
9831 RHS = Op0.getOperand(1);
9833 } else if (Op1.getOpcode() == ISD::Constant) {
9834 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
9835 uint64_t AndRHSVal = AndRHS->getZExtValue();
9836 SDValue AndLHS = Op0;
9838 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
9839 LHS = AndLHS.getOperand(0);
9840 RHS = AndLHS.getOperand(1);
9843 // Use BT if the immediate can't be encoded in a TEST instruction.
9844 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
9846 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
9850 if (LHS.getNode()) {
9851 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
9852 // instruction. Since the shift amount is in-range-or-undefined, we know
9853 // that doing a bittest on the i32 value is ok. We extend to i32 because
9854 // the encoding for the i16 version is larger than the i32 version.
9855 // Also promote i16 to i32 for performance / code size reason.
9856 if (LHS.getValueType() == MVT::i8 ||
9857 LHS.getValueType() == MVT::i16)
9858 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
9860 // If the operand types disagree, extend the shift amount to match. Since
9861 // BT ignores high bits (like shifts) we can use anyextend.
9862 if (LHS.getValueType() != RHS.getValueType())
9863 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
9865 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
9866 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
9867 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9868 DAG.getConstant(Cond, MVT::i8), BT);
9874 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
9876 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
9881 // SSE Condition code mapping:
9890 switch (SetCCOpcode) {
9891 default: llvm_unreachable("Unexpected SETCC condition");
9893 case ISD::SETEQ: SSECC = 0; break;
9895 case ISD::SETGT: Swap = true; // Fallthrough
9897 case ISD::SETOLT: SSECC = 1; break;
9899 case ISD::SETGE: Swap = true; // Fallthrough
9901 case ISD::SETOLE: SSECC = 2; break;
9902 case ISD::SETUO: SSECC = 3; break;
9904 case ISD::SETNE: SSECC = 4; break;
9905 case ISD::SETULE: Swap = true; // Fallthrough
9906 case ISD::SETUGE: SSECC = 5; break;
9907 case ISD::SETULT: Swap = true; // Fallthrough
9908 case ISD::SETUGT: SSECC = 6; break;
9909 case ISD::SETO: SSECC = 7; break;
9911 case ISD::SETONE: SSECC = 8; break;
9914 std::swap(Op0, Op1);
9919 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
9920 // ones, and then concatenate the result back.
9921 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
9922 MVT VT = Op.getSimpleValueType();
9924 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
9925 "Unsupported value type for operation");
9927 unsigned NumElems = VT.getVectorNumElements();
9929 SDValue CC = Op.getOperand(2);
9931 // Extract the LHS vectors
9932 SDValue LHS = Op.getOperand(0);
9933 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
9934 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
9936 // Extract the RHS vectors
9937 SDValue RHS = Op.getOperand(1);
9938 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
9939 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
9941 // Issue the operation on the smaller types and concatenate the result back
9942 MVT EltVT = VT.getVectorElementType();
9943 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
9944 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
9945 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
9946 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
9949 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG) {
9950 SDValue Op0 = Op.getOperand(0);
9951 SDValue Op1 = Op.getOperand(1);
9952 SDValue CC = Op.getOperand(2);
9953 MVT VT = Op.getSimpleValueType();
9955 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 32 &&
9956 Op.getValueType().getScalarType() == MVT::i1 &&
9957 "Cannot set masked compare for this operation");
9959 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
9962 bool Unsigned = false;
9964 switch (SetCCOpcode) {
9965 default: llvm_unreachable("Unexpected SETCC condition");
9966 case ISD::SETNE: SSECC = 4; break;
9967 case ISD::SETEQ: SSECC = 0; break;
9968 case ISD::SETUGT: Unsigned = true;
9969 case ISD::SETGT: SSECC = 6; break; // NLE
9970 case ISD::SETULT: Unsigned = true;
9971 case ISD::SETLT: SSECC = 1; break;
9972 case ISD::SETUGE: Unsigned = true;
9973 case ISD::SETGE: SSECC = 5; break; // NLT
9974 case ISD::SETULE: Unsigned = true;
9975 case ISD::SETLE: SSECC = 2; break;
9977 unsigned Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
9978 return DAG.getNode(Opc, dl, VT, Op0, Op1,
9979 DAG.getConstant(SSECC, MVT::i8));
9983 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
9984 SelectionDAG &DAG) {
9985 SDValue Op0 = Op.getOperand(0);
9986 SDValue Op1 = Op.getOperand(1);
9987 SDValue CC = Op.getOperand(2);
9988 MVT VT = Op.getSimpleValueType();
9989 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
9990 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
9995 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
9996 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
9999 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
10000 unsigned Opc = X86ISD::CMPP;
10001 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
10002 assert(VT.getVectorNumElements() <= 16);
10003 Opc = X86ISD::CMPM;
10005 // In the two special cases we can't handle, emit two comparisons.
10008 unsigned CombineOpc;
10009 if (SetCCOpcode == ISD::SETUEQ) {
10010 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
10012 assert(SetCCOpcode == ISD::SETONE);
10013 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
10016 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
10017 DAG.getConstant(CC0, MVT::i8));
10018 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
10019 DAG.getConstant(CC1, MVT::i8));
10020 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
10022 // Handle all other FP comparisons here.
10023 return DAG.getNode(Opc, dl, VT, Op0, Op1,
10024 DAG.getConstant(SSECC, MVT::i8));
10027 // Break 256-bit integer vector compare into smaller ones.
10028 if (VT.is256BitVector() && !Subtarget->hasInt256())
10029 return Lower256IntVSETCC(Op, DAG);
10031 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
10032 EVT OpVT = Op1.getValueType();
10033 if (Subtarget->hasAVX512()) {
10034 if (Op1.getValueType().is512BitVector() ||
10035 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
10036 return LowerIntVSETCC_AVX512(Op, DAG);
10038 // In AVX-512 architecture setcc returns mask with i1 elements,
10039 // But there is no compare instruction for i8 and i16 elements.
10040 // We are not talking about 512-bit operands in this case, these
10041 // types are illegal.
10043 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
10044 OpVT.getVectorElementType().getSizeInBits() >= 8))
10045 return DAG.getNode(ISD::TRUNCATE, dl, VT,
10046 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
10049 // We are handling one of the integer comparisons here. Since SSE only has
10050 // GT and EQ comparisons for integer, swapping operands and multiple
10051 // operations may be required for some comparisons.
10053 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
10055 switch (SetCCOpcode) {
10056 default: llvm_unreachable("Unexpected SETCC condition");
10057 case ISD::SETNE: Invert = true;
10058 case ISD::SETEQ: Opc = MaskResult? X86ISD::PCMPEQM: X86ISD::PCMPEQ; break;
10059 case ISD::SETLT: Swap = true;
10060 case ISD::SETGT: Opc = MaskResult? X86ISD::PCMPGTM: X86ISD::PCMPGT; break;
10061 case ISD::SETGE: Swap = true;
10062 case ISD::SETLE: Opc = MaskResult? X86ISD::PCMPGTM: X86ISD::PCMPGT;
10063 Invert = true; break;
10064 case ISD::SETULT: Swap = true;
10065 case ISD::SETUGT: Opc = MaskResult? X86ISD::PCMPGTM: X86ISD::PCMPGT;
10066 FlipSigns = true; break;
10067 case ISD::SETUGE: Swap = true;
10068 case ISD::SETULE: Opc = MaskResult? X86ISD::PCMPGTM: X86ISD::PCMPGT;
10069 FlipSigns = true; Invert = true; break;
10072 // Special case: Use min/max operations for SETULE/SETUGE
10073 MVT VET = VT.getVectorElementType();
10075 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
10076 || (Subtarget->hasSSE2() && (VET == MVT::i8));
10079 switch (SetCCOpcode) {
10081 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
10082 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
10085 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
10089 std::swap(Op0, Op1);
10091 // Check that the operation in question is available (most are plain SSE2,
10092 // but PCMPGTQ and PCMPEQQ have different requirements).
10093 if (VT == MVT::v2i64) {
10094 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
10095 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
10097 // First cast everything to the right type.
10098 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
10099 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
10101 // Since SSE has no unsigned integer comparisons, we need to flip the sign
10102 // bits of the inputs before performing those operations. The lower
10103 // compare is always unsigned.
10106 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
10108 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
10109 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
10110 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
10111 Sign, Zero, Sign, Zero);
10113 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
10114 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
10116 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
10117 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
10118 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
10120 // Create masks for only the low parts/high parts of the 64 bit integers.
10121 static const int MaskHi[] = { 1, 1, 3, 3 };
10122 static const int MaskLo[] = { 0, 0, 2, 2 };
10123 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
10124 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
10125 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
10127 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
10128 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
10131 Result = DAG.getNOT(dl, Result, MVT::v4i32);
10133 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
10136 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
10137 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
10138 // pcmpeqd + pshufd + pand.
10139 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
10141 // First cast everything to the right type.
10142 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
10143 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
10146 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
10148 // Make sure the lower and upper halves are both all-ones.
10149 static const int Mask[] = { 1, 0, 3, 2 };
10150 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
10151 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
10154 Result = DAG.getNOT(dl, Result, MVT::v4i32);
10156 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
10160 // Since SSE has no unsigned integer comparisons, we need to flip the sign
10161 // bits of the inputs before performing those operations.
10163 EVT EltVT = VT.getVectorElementType();
10164 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
10165 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
10166 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
10169 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
10171 // If the logical-not of the result is required, perform that now.
10173 Result = DAG.getNOT(dl, Result, VT);
10176 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
10181 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
10183 MVT VT = Op.getSimpleValueType();
10185 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
10187 assert((VT == MVT::i8 || (Subtarget->hasAVX512() && VT == MVT::i1))
10188 && "SetCC type must be 8-bit or 1-bit integer");
10189 SDValue Op0 = Op.getOperand(0);
10190 SDValue Op1 = Op.getOperand(1);
10192 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
10194 // Optimize to BT if possible.
10195 // Lower (X & (1 << N)) == 0 to BT(X, N).
10196 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
10197 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
10198 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
10199 Op1.getOpcode() == ISD::Constant &&
10200 cast<ConstantSDNode>(Op1)->isNullValue() &&
10201 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
10202 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
10203 if (NewSetCC.getNode())
10207 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
10209 if (Op1.getOpcode() == ISD::Constant &&
10210 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
10211 cast<ConstantSDNode>(Op1)->isNullValue()) &&
10212 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
10214 // If the input is a setcc, then reuse the input setcc or use a new one with
10215 // the inverted condition.
10216 if (Op0.getOpcode() == X86ISD::SETCC) {
10217 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
10218 bool Invert = (CC == ISD::SETNE) ^
10219 cast<ConstantSDNode>(Op1)->isNullValue();
10220 if (!Invert) return Op0;
10222 CCode = X86::GetOppositeBranchCondition(CCode);
10223 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
10224 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
10228 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
10229 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
10230 if (X86CC == X86::COND_INVALID)
10233 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG);
10234 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
10235 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
10236 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
10239 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
10240 static bool isX86LogicalCmp(SDValue Op) {
10241 unsigned Opc = Op.getNode()->getOpcode();
10242 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
10243 Opc == X86ISD::SAHF)
10245 if (Op.getResNo() == 1 &&
10246 (Opc == X86ISD::ADD ||
10247 Opc == X86ISD::SUB ||
10248 Opc == X86ISD::ADC ||
10249 Opc == X86ISD::SBB ||
10250 Opc == X86ISD::SMUL ||
10251 Opc == X86ISD::UMUL ||
10252 Opc == X86ISD::INC ||
10253 Opc == X86ISD::DEC ||
10254 Opc == X86ISD::OR ||
10255 Opc == X86ISD::XOR ||
10256 Opc == X86ISD::AND))
10259 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
10265 static bool isZero(SDValue V) {
10266 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
10267 return C && C->isNullValue();
10270 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
10271 if (V.getOpcode() != ISD::TRUNCATE)
10274 SDValue VOp0 = V.getOperand(0);
10275 unsigned InBits = VOp0.getValueSizeInBits();
10276 unsigned Bits = V.getValueSizeInBits();
10277 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
10280 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
10281 bool addTest = true;
10282 SDValue Cond = Op.getOperand(0);
10283 SDValue Op1 = Op.getOperand(1);
10284 SDValue Op2 = Op.getOperand(2);
10286 EVT VT = Op1.getValueType();
10289 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
10290 // are available. Otherwise fp cmovs get lowered into a less efficient branch
10291 // sequence later on.
10292 if (Cond.getOpcode() == ISD::SETCC &&
10293 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
10294 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
10295 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
10296 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
10297 int SSECC = translateX86FSETCC(
10298 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
10301 if (Subtarget->hasAVX512()) {
10302 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
10303 DAG.getConstant(SSECC, MVT::i8));
10304 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
10306 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
10307 DAG.getConstant(SSECC, MVT::i8));
10308 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
10309 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
10310 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
10314 if (Cond.getOpcode() == ISD::SETCC) {
10315 SDValue NewCond = LowerSETCC(Cond, DAG);
10316 if (NewCond.getNode())
10320 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
10321 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
10322 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
10323 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
10324 if (Cond.getOpcode() == X86ISD::SETCC &&
10325 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
10326 isZero(Cond.getOperand(1).getOperand(1))) {
10327 SDValue Cmp = Cond.getOperand(1);
10329 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
10331 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
10332 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
10333 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
10335 SDValue CmpOp0 = Cmp.getOperand(0);
10336 // Apply further optimizations for special cases
10337 // (select (x != 0), -1, 0) -> neg & sbb
10338 // (select (x == 0), 0, -1) -> neg & sbb
10339 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
10340 if (YC->isNullValue() &&
10341 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
10342 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
10343 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
10344 DAG.getConstant(0, CmpOp0.getValueType()),
10346 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
10347 DAG.getConstant(X86::COND_B, MVT::i8),
10348 SDValue(Neg.getNode(), 1));
10352 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
10353 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
10354 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
10356 SDValue Res = // Res = 0 or -1.
10357 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
10358 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
10360 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
10361 Res = DAG.getNOT(DL, Res, Res.getValueType());
10363 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
10364 if (N2C == 0 || !N2C->isNullValue())
10365 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
10370 // Look past (and (setcc_carry (cmp ...)), 1).
10371 if (Cond.getOpcode() == ISD::AND &&
10372 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
10373 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
10374 if (C && C->getAPIntValue() == 1)
10375 Cond = Cond.getOperand(0);
10378 // If condition flag is set by a X86ISD::CMP, then use it as the condition
10379 // setting operand in place of the X86ISD::SETCC.
10380 unsigned CondOpcode = Cond.getOpcode();
10381 if (CondOpcode == X86ISD::SETCC ||
10382 CondOpcode == X86ISD::SETCC_CARRY) {
10383 CC = Cond.getOperand(0);
10385 SDValue Cmp = Cond.getOperand(1);
10386 unsigned Opc = Cmp.getOpcode();
10387 MVT VT = Op.getSimpleValueType();
10389 bool IllegalFPCMov = false;
10390 if (VT.isFloatingPoint() && !VT.isVector() &&
10391 !isScalarFPTypeInSSEReg(VT)) // FPStack?
10392 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
10394 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
10395 Opc == X86ISD::BT) { // FIXME
10399 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
10400 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
10401 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
10402 Cond.getOperand(0).getValueType() != MVT::i8)) {
10403 SDValue LHS = Cond.getOperand(0);
10404 SDValue RHS = Cond.getOperand(1);
10405 unsigned X86Opcode;
10408 switch (CondOpcode) {
10409 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
10410 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
10411 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
10412 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
10413 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
10414 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
10415 default: llvm_unreachable("unexpected overflowing operator");
10417 if (CondOpcode == ISD::UMULO)
10418 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
10421 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
10423 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
10425 if (CondOpcode == ISD::UMULO)
10426 Cond = X86Op.getValue(2);
10428 Cond = X86Op.getValue(1);
10430 CC = DAG.getConstant(X86Cond, MVT::i8);
10435 // Look pass the truncate if the high bits are known zero.
10436 if (isTruncWithZeroHighBitsInput(Cond, DAG))
10437 Cond = Cond.getOperand(0);
10439 // We know the result of AND is compared against zero. Try to match
10441 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
10442 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
10443 if (NewSetCC.getNode()) {
10444 CC = NewSetCC.getOperand(0);
10445 Cond = NewSetCC.getOperand(1);
10452 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10453 Cond = EmitTest(Cond, X86::COND_NE, DAG);
10456 // a < b ? -1 : 0 -> RES = ~setcc_carry
10457 // a < b ? 0 : -1 -> RES = setcc_carry
10458 // a >= b ? -1 : 0 -> RES = setcc_carry
10459 // a >= b ? 0 : -1 -> RES = ~setcc_carry
10460 if (Cond.getOpcode() == X86ISD::SUB) {
10461 Cond = ConvertCmpIfNecessary(Cond, DAG);
10462 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
10464 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
10465 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
10466 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
10467 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
10468 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
10469 return DAG.getNOT(DL, Res, Res.getValueType());
10474 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
10475 // widen the cmov and push the truncate through. This avoids introducing a new
10476 // branch during isel and doesn't add any extensions.
10477 if (Op.getValueType() == MVT::i8 &&
10478 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
10479 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
10480 if (T1.getValueType() == T2.getValueType() &&
10481 // Blacklist CopyFromReg to avoid partial register stalls.
10482 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
10483 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
10484 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
10485 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
10489 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
10490 // condition is true.
10491 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
10492 SDValue Ops[] = { Op2, Op1, CC, Cond };
10493 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
10496 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, SelectionDAG &DAG) {
10497 MVT VT = Op->getSimpleValueType(0);
10498 SDValue In = Op->getOperand(0);
10499 MVT InVT = In.getSimpleValueType();
10502 unsigned int NumElts = VT.getVectorNumElements();
10503 if (NumElts != 8 && NumElts != 16)
10506 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
10507 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
10509 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
10510 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
10512 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
10513 Constant *C = ConstantInt::get(*DAG.getContext(),
10514 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
10516 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
10517 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
10518 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
10519 MachinePointerInfo::getConstantPool(),
10520 false, false, false, Alignment);
10521 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
10522 if (VT.is512BitVector())
10524 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
10527 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
10528 SelectionDAG &DAG) {
10529 MVT VT = Op->getSimpleValueType(0);
10530 SDValue In = Op->getOperand(0);
10531 MVT InVT = In.getSimpleValueType();
10534 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
10535 return LowerSIGN_EXTEND_AVX512(Op, DAG);
10537 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
10538 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
10539 (VT != MVT::v16i16 || InVT != MVT::v16i8))
10542 if (Subtarget->hasInt256())
10543 return DAG.getNode(X86ISD::VSEXT_MOVL, dl, VT, In);
10545 // Optimize vectors in AVX mode
10546 // Sign extend v8i16 to v8i32 and
10549 // Divide input vector into two parts
10550 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
10551 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
10552 // concat the vectors to original VT
10554 unsigned NumElems = InVT.getVectorNumElements();
10555 SDValue Undef = DAG.getUNDEF(InVT);
10557 SmallVector<int,8> ShufMask1(NumElems, -1);
10558 for (unsigned i = 0; i != NumElems/2; ++i)
10561 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
10563 SmallVector<int,8> ShufMask2(NumElems, -1);
10564 for (unsigned i = 0; i != NumElems/2; ++i)
10565 ShufMask2[i] = i + NumElems/2;
10567 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
10569 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
10570 VT.getVectorNumElements()/2);
10572 OpLo = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpLo);
10573 OpHi = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpHi);
10575 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
10578 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
10579 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
10580 // from the AND / OR.
10581 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
10582 Opc = Op.getOpcode();
10583 if (Opc != ISD::OR && Opc != ISD::AND)
10585 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
10586 Op.getOperand(0).hasOneUse() &&
10587 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
10588 Op.getOperand(1).hasOneUse());
10591 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
10592 // 1 and that the SETCC node has a single use.
10593 static bool isXor1OfSetCC(SDValue Op) {
10594 if (Op.getOpcode() != ISD::XOR)
10596 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
10597 if (N1C && N1C->getAPIntValue() == 1) {
10598 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
10599 Op.getOperand(0).hasOneUse();
10604 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
10605 bool addTest = true;
10606 SDValue Chain = Op.getOperand(0);
10607 SDValue Cond = Op.getOperand(1);
10608 SDValue Dest = Op.getOperand(2);
10611 bool Inverted = false;
10613 if (Cond.getOpcode() == ISD::SETCC) {
10614 // Check for setcc([su]{add,sub,mul}o == 0).
10615 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
10616 isa<ConstantSDNode>(Cond.getOperand(1)) &&
10617 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
10618 Cond.getOperand(0).getResNo() == 1 &&
10619 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
10620 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
10621 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
10622 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
10623 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
10624 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
10626 Cond = Cond.getOperand(0);
10628 SDValue NewCond = LowerSETCC(Cond, DAG);
10629 if (NewCond.getNode())
10634 // FIXME: LowerXALUO doesn't handle these!!
10635 else if (Cond.getOpcode() == X86ISD::ADD ||
10636 Cond.getOpcode() == X86ISD::SUB ||
10637 Cond.getOpcode() == X86ISD::SMUL ||
10638 Cond.getOpcode() == X86ISD::UMUL)
10639 Cond = LowerXALUO(Cond, DAG);
10642 // Look pass (and (setcc_carry (cmp ...)), 1).
10643 if (Cond.getOpcode() == ISD::AND &&
10644 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
10645 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
10646 if (C && C->getAPIntValue() == 1)
10647 Cond = Cond.getOperand(0);
10650 // If condition flag is set by a X86ISD::CMP, then use it as the condition
10651 // setting operand in place of the X86ISD::SETCC.
10652 unsigned CondOpcode = Cond.getOpcode();
10653 if (CondOpcode == X86ISD::SETCC ||
10654 CondOpcode == X86ISD::SETCC_CARRY) {
10655 CC = Cond.getOperand(0);
10657 SDValue Cmp = Cond.getOperand(1);
10658 unsigned Opc = Cmp.getOpcode();
10659 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
10660 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
10664 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
10668 // These can only come from an arithmetic instruction with overflow,
10669 // e.g. SADDO, UADDO.
10670 Cond = Cond.getNode()->getOperand(1);
10676 CondOpcode = Cond.getOpcode();
10677 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
10678 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
10679 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
10680 Cond.getOperand(0).getValueType() != MVT::i8)) {
10681 SDValue LHS = Cond.getOperand(0);
10682 SDValue RHS = Cond.getOperand(1);
10683 unsigned X86Opcode;
10686 switch (CondOpcode) {
10687 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
10688 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
10689 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
10690 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
10691 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
10692 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
10693 default: llvm_unreachable("unexpected overflowing operator");
10696 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
10697 if (CondOpcode == ISD::UMULO)
10698 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
10701 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
10703 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
10705 if (CondOpcode == ISD::UMULO)
10706 Cond = X86Op.getValue(2);
10708 Cond = X86Op.getValue(1);
10710 CC = DAG.getConstant(X86Cond, MVT::i8);
10714 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
10715 SDValue Cmp = Cond.getOperand(0).getOperand(1);
10716 if (CondOpc == ISD::OR) {
10717 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
10718 // two branches instead of an explicit OR instruction with a
10720 if (Cmp == Cond.getOperand(1).getOperand(1) &&
10721 isX86LogicalCmp(Cmp)) {
10722 CC = Cond.getOperand(0).getOperand(0);
10723 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10724 Chain, Dest, CC, Cmp);
10725 CC = Cond.getOperand(1).getOperand(0);
10729 } else { // ISD::AND
10730 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
10731 // two branches instead of an explicit AND instruction with a
10732 // separate test. However, we only do this if this block doesn't
10733 // have a fall-through edge, because this requires an explicit
10734 // jmp when the condition is false.
10735 if (Cmp == Cond.getOperand(1).getOperand(1) &&
10736 isX86LogicalCmp(Cmp) &&
10737 Op.getNode()->hasOneUse()) {
10738 X86::CondCode CCode =
10739 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
10740 CCode = X86::GetOppositeBranchCondition(CCode);
10741 CC = DAG.getConstant(CCode, MVT::i8);
10742 SDNode *User = *Op.getNode()->use_begin();
10743 // Look for an unconditional branch following this conditional branch.
10744 // We need this because we need to reverse the successors in order
10745 // to implement FCMP_OEQ.
10746 if (User->getOpcode() == ISD::BR) {
10747 SDValue FalseBB = User->getOperand(1);
10749 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
10750 assert(NewBR == User);
10754 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10755 Chain, Dest, CC, Cmp);
10756 X86::CondCode CCode =
10757 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
10758 CCode = X86::GetOppositeBranchCondition(CCode);
10759 CC = DAG.getConstant(CCode, MVT::i8);
10765 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
10766 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
10767 // It should be transformed during dag combiner except when the condition
10768 // is set by a arithmetics with overflow node.
10769 X86::CondCode CCode =
10770 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
10771 CCode = X86::GetOppositeBranchCondition(CCode);
10772 CC = DAG.getConstant(CCode, MVT::i8);
10773 Cond = Cond.getOperand(0).getOperand(1);
10775 } else if (Cond.getOpcode() == ISD::SETCC &&
10776 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
10777 // For FCMP_OEQ, we can emit
10778 // two branches instead of an explicit AND instruction with a
10779 // separate test. However, we only do this if this block doesn't
10780 // have a fall-through edge, because this requires an explicit
10781 // jmp when the condition is false.
10782 if (Op.getNode()->hasOneUse()) {
10783 SDNode *User = *Op.getNode()->use_begin();
10784 // Look for an unconditional branch following this conditional branch.
10785 // We need this because we need to reverse the successors in order
10786 // to implement FCMP_OEQ.
10787 if (User->getOpcode() == ISD::BR) {
10788 SDValue FalseBB = User->getOperand(1);
10790 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
10791 assert(NewBR == User);
10795 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
10796 Cond.getOperand(0), Cond.getOperand(1));
10797 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
10798 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10799 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10800 Chain, Dest, CC, Cmp);
10801 CC = DAG.getConstant(X86::COND_P, MVT::i8);
10806 } else if (Cond.getOpcode() == ISD::SETCC &&
10807 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
10808 // For FCMP_UNE, we can emit
10809 // two branches instead of an explicit AND instruction with a
10810 // separate test. However, we only do this if this block doesn't
10811 // have a fall-through edge, because this requires an explicit
10812 // jmp when the condition is false.
10813 if (Op.getNode()->hasOneUse()) {
10814 SDNode *User = *Op.getNode()->use_begin();
10815 // Look for an unconditional branch following this conditional branch.
10816 // We need this because we need to reverse the successors in order
10817 // to implement FCMP_UNE.
10818 if (User->getOpcode() == ISD::BR) {
10819 SDValue FalseBB = User->getOperand(1);
10821 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
10822 assert(NewBR == User);
10825 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
10826 Cond.getOperand(0), Cond.getOperand(1));
10827 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
10828 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10829 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10830 Chain, Dest, CC, Cmp);
10831 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
10841 // Look pass the truncate if the high bits are known zero.
10842 if (isTruncWithZeroHighBitsInput(Cond, DAG))
10843 Cond = Cond.getOperand(0);
10845 // We know the result of AND is compared against zero. Try to match
10847 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
10848 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
10849 if (NewSetCC.getNode()) {
10850 CC = NewSetCC.getOperand(0);
10851 Cond = NewSetCC.getOperand(1);
10858 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10859 Cond = EmitTest(Cond, X86::COND_NE, DAG);
10861 Cond = ConvertCmpIfNecessary(Cond, DAG);
10862 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10863 Chain, Dest, CC, Cond);
10866 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
10867 // Calls to _alloca is needed to probe the stack when allocating more than 4k
10868 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
10869 // that the guard pages used by the OS virtual memory manager are allocated in
10870 // correct sequence.
10872 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
10873 SelectionDAG &DAG) const {
10874 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() ||
10875 getTargetMachine().Options.EnableSegmentedStacks) &&
10876 "This should be used only on Windows targets or when segmented stacks "
10878 assert(!Subtarget->isTargetMacho() && "Not implemented");
10882 SDValue Chain = Op.getOperand(0);
10883 SDValue Size = Op.getOperand(1);
10884 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
10885 EVT VT = Op.getNode()->getValueType(0);
10887 bool Is64Bit = Subtarget->is64Bit();
10888 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32;
10890 if (getTargetMachine().Options.EnableSegmentedStacks) {
10891 MachineFunction &MF = DAG.getMachineFunction();
10892 MachineRegisterInfo &MRI = MF.getRegInfo();
10895 // The 64 bit implementation of segmented stacks needs to clobber both r10
10896 // r11. This makes it impossible to use it along with nested parameters.
10897 const Function *F = MF.getFunction();
10899 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
10901 if (I->hasNestAttr())
10902 report_fatal_error("Cannot use segmented stacks with functions that "
10903 "have nested arguments.");
10906 const TargetRegisterClass *AddrRegClass =
10907 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
10908 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
10909 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
10910 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
10911 DAG.getRegister(Vreg, SPTy));
10912 SDValue Ops1[2] = { Value, Chain };
10913 return DAG.getMergeValues(Ops1, 2, dl);
10916 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
10918 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
10919 Flag = Chain.getValue(1);
10920 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
10922 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
10924 const X86RegisterInfo *RegInfo =
10925 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
10926 unsigned SPReg = RegInfo->getStackRegister();
10927 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
10928 Chain = SP.getValue(1);
10931 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
10932 DAG.getConstant(-(uint64_t)Align, VT));
10933 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
10936 SDValue Ops1[2] = { SP, Chain };
10937 return DAG.getMergeValues(Ops1, 2, dl);
10941 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
10942 MachineFunction &MF = DAG.getMachineFunction();
10943 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
10945 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
10948 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
10949 // vastart just stores the address of the VarArgsFrameIndex slot into the
10950 // memory location argument.
10951 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
10953 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
10954 MachinePointerInfo(SV), false, false, 0);
10958 // gp_offset (0 - 6 * 8)
10959 // fp_offset (48 - 48 + 8 * 16)
10960 // overflow_arg_area (point to parameters coming in memory).
10962 SmallVector<SDValue, 8> MemOps;
10963 SDValue FIN = Op.getOperand(1);
10965 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
10966 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
10968 FIN, MachinePointerInfo(SV), false, false, 0);
10969 MemOps.push_back(Store);
10972 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10973 FIN, DAG.getIntPtrConstant(4));
10974 Store = DAG.getStore(Op.getOperand(0), DL,
10975 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
10977 FIN, MachinePointerInfo(SV, 4), false, false, 0);
10978 MemOps.push_back(Store);
10980 // Store ptr to overflow_arg_area
10981 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10982 FIN, DAG.getIntPtrConstant(4));
10983 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
10985 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
10986 MachinePointerInfo(SV, 8),
10988 MemOps.push_back(Store);
10990 // Store ptr to reg_save_area.
10991 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10992 FIN, DAG.getIntPtrConstant(8));
10993 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
10995 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
10996 MachinePointerInfo(SV, 16), false, false, 0);
10997 MemOps.push_back(Store);
10998 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
10999 &MemOps[0], MemOps.size());
11002 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
11003 assert(Subtarget->is64Bit() &&
11004 "LowerVAARG only handles 64-bit va_arg!");
11005 assert((Subtarget->isTargetLinux() ||
11006 Subtarget->isTargetDarwin()) &&
11007 "Unhandled target in LowerVAARG");
11008 assert(Op.getNode()->getNumOperands() == 4);
11009 SDValue Chain = Op.getOperand(0);
11010 SDValue SrcPtr = Op.getOperand(1);
11011 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
11012 unsigned Align = Op.getConstantOperandVal(3);
11015 EVT ArgVT = Op.getNode()->getValueType(0);
11016 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
11017 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
11020 // Decide which area this value should be read from.
11021 // TODO: Implement the AMD64 ABI in its entirety. This simple
11022 // selection mechanism works only for the basic types.
11023 if (ArgVT == MVT::f80) {
11024 llvm_unreachable("va_arg for f80 not yet implemented");
11025 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
11026 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
11027 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
11028 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
11030 llvm_unreachable("Unhandled argument type in LowerVAARG");
11033 if (ArgMode == 2) {
11034 // Sanity Check: Make sure using fp_offset makes sense.
11035 assert(!getTargetMachine().Options.UseSoftFloat &&
11036 !(DAG.getMachineFunction()
11037 .getFunction()->getAttributes()
11038 .hasAttribute(AttributeSet::FunctionIndex,
11039 Attribute::NoImplicitFloat)) &&
11040 Subtarget->hasSSE1());
11043 // Insert VAARG_64 node into the DAG
11044 // VAARG_64 returns two values: Variable Argument Address, Chain
11045 SmallVector<SDValue, 11> InstOps;
11046 InstOps.push_back(Chain);
11047 InstOps.push_back(SrcPtr);
11048 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
11049 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
11050 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
11051 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
11052 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
11053 VTs, &InstOps[0], InstOps.size(),
11055 MachinePointerInfo(SV),
11057 /*Volatile=*/false,
11059 /*WriteMem=*/true);
11060 Chain = VAARG.getValue(1);
11062 // Load the next argument and return it
11063 return DAG.getLoad(ArgVT, dl,
11066 MachinePointerInfo(),
11067 false, false, false, 0);
11070 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
11071 SelectionDAG &DAG) {
11072 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
11073 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
11074 SDValue Chain = Op.getOperand(0);
11075 SDValue DstPtr = Op.getOperand(1);
11076 SDValue SrcPtr = Op.getOperand(2);
11077 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
11078 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
11081 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
11082 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
11084 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
11087 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
11088 // amount is a constant. Takes immediate version of shift as input.
11089 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, EVT VT,
11090 SDValue SrcOp, uint64_t ShiftAmt,
11091 SelectionDAG &DAG) {
11093 // Check for ShiftAmt >= element width
11094 if (ShiftAmt >= VT.getVectorElementType().getSizeInBits()) {
11095 if (Opc == X86ISD::VSRAI)
11096 ShiftAmt = VT.getVectorElementType().getSizeInBits() - 1;
11098 return DAG.getConstant(0, VT);
11101 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
11102 && "Unknown target vector shift-by-constant node");
11104 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
11107 // getTargetVShiftNode - Handle vector element shifts where the shift amount
11108 // may or may not be a constant. Takes immediate version of shift as input.
11109 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, EVT VT,
11110 SDValue SrcOp, SDValue ShAmt,
11111 SelectionDAG &DAG) {
11112 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
11114 // Catch shift-by-constant.
11115 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
11116 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
11117 CShAmt->getZExtValue(), DAG);
11119 // Change opcode to non-immediate version
11121 default: llvm_unreachable("Unknown target vector shift node");
11122 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
11123 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
11124 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
11127 // Need to build a vector containing shift amount
11128 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
11131 ShOps[1] = DAG.getConstant(0, MVT::i32);
11132 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32);
11133 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &ShOps[0], 4);
11135 // The return type has to be a 128-bit type with the same element
11136 // type as the input type.
11137 MVT EltVT = VT.getVectorElementType().getSimpleVT();
11138 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
11140 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
11141 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
11144 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
11146 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
11148 default: return SDValue(); // Don't custom lower most intrinsics.
11149 // Comparison intrinsics.
11150 case Intrinsic::x86_sse_comieq_ss:
11151 case Intrinsic::x86_sse_comilt_ss:
11152 case Intrinsic::x86_sse_comile_ss:
11153 case Intrinsic::x86_sse_comigt_ss:
11154 case Intrinsic::x86_sse_comige_ss:
11155 case Intrinsic::x86_sse_comineq_ss:
11156 case Intrinsic::x86_sse_ucomieq_ss:
11157 case Intrinsic::x86_sse_ucomilt_ss:
11158 case Intrinsic::x86_sse_ucomile_ss:
11159 case Intrinsic::x86_sse_ucomigt_ss:
11160 case Intrinsic::x86_sse_ucomige_ss:
11161 case Intrinsic::x86_sse_ucomineq_ss:
11162 case Intrinsic::x86_sse2_comieq_sd:
11163 case Intrinsic::x86_sse2_comilt_sd:
11164 case Intrinsic::x86_sse2_comile_sd:
11165 case Intrinsic::x86_sse2_comigt_sd:
11166 case Intrinsic::x86_sse2_comige_sd:
11167 case Intrinsic::x86_sse2_comineq_sd:
11168 case Intrinsic::x86_sse2_ucomieq_sd:
11169 case Intrinsic::x86_sse2_ucomilt_sd:
11170 case Intrinsic::x86_sse2_ucomile_sd:
11171 case Intrinsic::x86_sse2_ucomigt_sd:
11172 case Intrinsic::x86_sse2_ucomige_sd:
11173 case Intrinsic::x86_sse2_ucomineq_sd: {
11177 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11178 case Intrinsic::x86_sse_comieq_ss:
11179 case Intrinsic::x86_sse2_comieq_sd:
11180 Opc = X86ISD::COMI;
11183 case Intrinsic::x86_sse_comilt_ss:
11184 case Intrinsic::x86_sse2_comilt_sd:
11185 Opc = X86ISD::COMI;
11188 case Intrinsic::x86_sse_comile_ss:
11189 case Intrinsic::x86_sse2_comile_sd:
11190 Opc = X86ISD::COMI;
11193 case Intrinsic::x86_sse_comigt_ss:
11194 case Intrinsic::x86_sse2_comigt_sd:
11195 Opc = X86ISD::COMI;
11198 case Intrinsic::x86_sse_comige_ss:
11199 case Intrinsic::x86_sse2_comige_sd:
11200 Opc = X86ISD::COMI;
11203 case Intrinsic::x86_sse_comineq_ss:
11204 case Intrinsic::x86_sse2_comineq_sd:
11205 Opc = X86ISD::COMI;
11208 case Intrinsic::x86_sse_ucomieq_ss:
11209 case Intrinsic::x86_sse2_ucomieq_sd:
11210 Opc = X86ISD::UCOMI;
11213 case Intrinsic::x86_sse_ucomilt_ss:
11214 case Intrinsic::x86_sse2_ucomilt_sd:
11215 Opc = X86ISD::UCOMI;
11218 case Intrinsic::x86_sse_ucomile_ss:
11219 case Intrinsic::x86_sse2_ucomile_sd:
11220 Opc = X86ISD::UCOMI;
11223 case Intrinsic::x86_sse_ucomigt_ss:
11224 case Intrinsic::x86_sse2_ucomigt_sd:
11225 Opc = X86ISD::UCOMI;
11228 case Intrinsic::x86_sse_ucomige_ss:
11229 case Intrinsic::x86_sse2_ucomige_sd:
11230 Opc = X86ISD::UCOMI;
11233 case Intrinsic::x86_sse_ucomineq_ss:
11234 case Intrinsic::x86_sse2_ucomineq_sd:
11235 Opc = X86ISD::UCOMI;
11240 SDValue LHS = Op.getOperand(1);
11241 SDValue RHS = Op.getOperand(2);
11242 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
11243 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
11244 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
11245 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
11246 DAG.getConstant(X86CC, MVT::i8), Cond);
11247 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
11250 // Arithmetic intrinsics.
11251 case Intrinsic::x86_sse2_pmulu_dq:
11252 case Intrinsic::x86_avx2_pmulu_dq:
11253 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
11254 Op.getOperand(1), Op.getOperand(2));
11256 // SSE2/AVX2 sub with unsigned saturation intrinsics
11257 case Intrinsic::x86_sse2_psubus_b:
11258 case Intrinsic::x86_sse2_psubus_w:
11259 case Intrinsic::x86_avx2_psubus_b:
11260 case Intrinsic::x86_avx2_psubus_w:
11261 return DAG.getNode(X86ISD::SUBUS, dl, Op.getValueType(),
11262 Op.getOperand(1), Op.getOperand(2));
11264 // SSE3/AVX horizontal add/sub intrinsics
11265 case Intrinsic::x86_sse3_hadd_ps:
11266 case Intrinsic::x86_sse3_hadd_pd:
11267 case Intrinsic::x86_avx_hadd_ps_256:
11268 case Intrinsic::x86_avx_hadd_pd_256:
11269 case Intrinsic::x86_sse3_hsub_ps:
11270 case Intrinsic::x86_sse3_hsub_pd:
11271 case Intrinsic::x86_avx_hsub_ps_256:
11272 case Intrinsic::x86_avx_hsub_pd_256:
11273 case Intrinsic::x86_ssse3_phadd_w_128:
11274 case Intrinsic::x86_ssse3_phadd_d_128:
11275 case Intrinsic::x86_avx2_phadd_w:
11276 case Intrinsic::x86_avx2_phadd_d:
11277 case Intrinsic::x86_ssse3_phsub_w_128:
11278 case Intrinsic::x86_ssse3_phsub_d_128:
11279 case Intrinsic::x86_avx2_phsub_w:
11280 case Intrinsic::x86_avx2_phsub_d: {
11283 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11284 case Intrinsic::x86_sse3_hadd_ps:
11285 case Intrinsic::x86_sse3_hadd_pd:
11286 case Intrinsic::x86_avx_hadd_ps_256:
11287 case Intrinsic::x86_avx_hadd_pd_256:
11288 Opcode = X86ISD::FHADD;
11290 case Intrinsic::x86_sse3_hsub_ps:
11291 case Intrinsic::x86_sse3_hsub_pd:
11292 case Intrinsic::x86_avx_hsub_ps_256:
11293 case Intrinsic::x86_avx_hsub_pd_256:
11294 Opcode = X86ISD::FHSUB;
11296 case Intrinsic::x86_ssse3_phadd_w_128:
11297 case Intrinsic::x86_ssse3_phadd_d_128:
11298 case Intrinsic::x86_avx2_phadd_w:
11299 case Intrinsic::x86_avx2_phadd_d:
11300 Opcode = X86ISD::HADD;
11302 case Intrinsic::x86_ssse3_phsub_w_128:
11303 case Intrinsic::x86_ssse3_phsub_d_128:
11304 case Intrinsic::x86_avx2_phsub_w:
11305 case Intrinsic::x86_avx2_phsub_d:
11306 Opcode = X86ISD::HSUB;
11309 return DAG.getNode(Opcode, dl, Op.getValueType(),
11310 Op.getOperand(1), Op.getOperand(2));
11313 // SSE2/SSE41/AVX2 integer max/min intrinsics.
11314 case Intrinsic::x86_sse2_pmaxu_b:
11315 case Intrinsic::x86_sse41_pmaxuw:
11316 case Intrinsic::x86_sse41_pmaxud:
11317 case Intrinsic::x86_avx2_pmaxu_b:
11318 case Intrinsic::x86_avx2_pmaxu_w:
11319 case Intrinsic::x86_avx2_pmaxu_d:
11320 case Intrinsic::x86_avx512_pmaxu_d:
11321 case Intrinsic::x86_avx512_pmaxu_q:
11322 case Intrinsic::x86_sse2_pminu_b:
11323 case Intrinsic::x86_sse41_pminuw:
11324 case Intrinsic::x86_sse41_pminud:
11325 case Intrinsic::x86_avx2_pminu_b:
11326 case Intrinsic::x86_avx2_pminu_w:
11327 case Intrinsic::x86_avx2_pminu_d:
11328 case Intrinsic::x86_avx512_pminu_d:
11329 case Intrinsic::x86_avx512_pminu_q:
11330 case Intrinsic::x86_sse41_pmaxsb:
11331 case Intrinsic::x86_sse2_pmaxs_w:
11332 case Intrinsic::x86_sse41_pmaxsd:
11333 case Intrinsic::x86_avx2_pmaxs_b:
11334 case Intrinsic::x86_avx2_pmaxs_w:
11335 case Intrinsic::x86_avx2_pmaxs_d:
11336 case Intrinsic::x86_avx512_pmaxs_d:
11337 case Intrinsic::x86_avx512_pmaxs_q:
11338 case Intrinsic::x86_sse41_pminsb:
11339 case Intrinsic::x86_sse2_pmins_w:
11340 case Intrinsic::x86_sse41_pminsd:
11341 case Intrinsic::x86_avx2_pmins_b:
11342 case Intrinsic::x86_avx2_pmins_w:
11343 case Intrinsic::x86_avx2_pmins_d:
11344 case Intrinsic::x86_avx512_pmins_d:
11345 case Intrinsic::x86_avx512_pmins_q: {
11348 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11349 case Intrinsic::x86_sse2_pmaxu_b:
11350 case Intrinsic::x86_sse41_pmaxuw:
11351 case Intrinsic::x86_sse41_pmaxud:
11352 case Intrinsic::x86_avx2_pmaxu_b:
11353 case Intrinsic::x86_avx2_pmaxu_w:
11354 case Intrinsic::x86_avx2_pmaxu_d:
11355 case Intrinsic::x86_avx512_pmaxu_d:
11356 case Intrinsic::x86_avx512_pmaxu_q:
11357 Opcode = X86ISD::UMAX;
11359 case Intrinsic::x86_sse2_pminu_b:
11360 case Intrinsic::x86_sse41_pminuw:
11361 case Intrinsic::x86_sse41_pminud:
11362 case Intrinsic::x86_avx2_pminu_b:
11363 case Intrinsic::x86_avx2_pminu_w:
11364 case Intrinsic::x86_avx2_pminu_d:
11365 case Intrinsic::x86_avx512_pminu_d:
11366 case Intrinsic::x86_avx512_pminu_q:
11367 Opcode = X86ISD::UMIN;
11369 case Intrinsic::x86_sse41_pmaxsb:
11370 case Intrinsic::x86_sse2_pmaxs_w:
11371 case Intrinsic::x86_sse41_pmaxsd:
11372 case Intrinsic::x86_avx2_pmaxs_b:
11373 case Intrinsic::x86_avx2_pmaxs_w:
11374 case Intrinsic::x86_avx2_pmaxs_d:
11375 case Intrinsic::x86_avx512_pmaxs_d:
11376 case Intrinsic::x86_avx512_pmaxs_q:
11377 Opcode = X86ISD::SMAX;
11379 case Intrinsic::x86_sse41_pminsb:
11380 case Intrinsic::x86_sse2_pmins_w:
11381 case Intrinsic::x86_sse41_pminsd:
11382 case Intrinsic::x86_avx2_pmins_b:
11383 case Intrinsic::x86_avx2_pmins_w:
11384 case Intrinsic::x86_avx2_pmins_d:
11385 case Intrinsic::x86_avx512_pmins_d:
11386 case Intrinsic::x86_avx512_pmins_q:
11387 Opcode = X86ISD::SMIN;
11390 return DAG.getNode(Opcode, dl, Op.getValueType(),
11391 Op.getOperand(1), Op.getOperand(2));
11394 // SSE/SSE2/AVX floating point max/min intrinsics.
11395 case Intrinsic::x86_sse_max_ps:
11396 case Intrinsic::x86_sse2_max_pd:
11397 case Intrinsic::x86_avx_max_ps_256:
11398 case Intrinsic::x86_avx_max_pd_256:
11399 case Intrinsic::x86_avx512_max_ps_512:
11400 case Intrinsic::x86_avx512_max_pd_512:
11401 case Intrinsic::x86_sse_min_ps:
11402 case Intrinsic::x86_sse2_min_pd:
11403 case Intrinsic::x86_avx_min_ps_256:
11404 case Intrinsic::x86_avx_min_pd_256:
11405 case Intrinsic::x86_avx512_min_ps_512:
11406 case Intrinsic::x86_avx512_min_pd_512: {
11409 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11410 case Intrinsic::x86_sse_max_ps:
11411 case Intrinsic::x86_sse2_max_pd:
11412 case Intrinsic::x86_avx_max_ps_256:
11413 case Intrinsic::x86_avx_max_pd_256:
11414 case Intrinsic::x86_avx512_max_ps_512:
11415 case Intrinsic::x86_avx512_max_pd_512:
11416 Opcode = X86ISD::FMAX;
11418 case Intrinsic::x86_sse_min_ps:
11419 case Intrinsic::x86_sse2_min_pd:
11420 case Intrinsic::x86_avx_min_ps_256:
11421 case Intrinsic::x86_avx_min_pd_256:
11422 case Intrinsic::x86_avx512_min_ps_512:
11423 case Intrinsic::x86_avx512_min_pd_512:
11424 Opcode = X86ISD::FMIN;
11427 return DAG.getNode(Opcode, dl, Op.getValueType(),
11428 Op.getOperand(1), Op.getOperand(2));
11431 // AVX2 variable shift intrinsics
11432 case Intrinsic::x86_avx2_psllv_d:
11433 case Intrinsic::x86_avx2_psllv_q:
11434 case Intrinsic::x86_avx2_psllv_d_256:
11435 case Intrinsic::x86_avx2_psllv_q_256:
11436 case Intrinsic::x86_avx2_psrlv_d:
11437 case Intrinsic::x86_avx2_psrlv_q:
11438 case Intrinsic::x86_avx2_psrlv_d_256:
11439 case Intrinsic::x86_avx2_psrlv_q_256:
11440 case Intrinsic::x86_avx2_psrav_d:
11441 case Intrinsic::x86_avx2_psrav_d_256: {
11444 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11445 case Intrinsic::x86_avx2_psllv_d:
11446 case Intrinsic::x86_avx2_psllv_q:
11447 case Intrinsic::x86_avx2_psllv_d_256:
11448 case Intrinsic::x86_avx2_psllv_q_256:
11451 case Intrinsic::x86_avx2_psrlv_d:
11452 case Intrinsic::x86_avx2_psrlv_q:
11453 case Intrinsic::x86_avx2_psrlv_d_256:
11454 case Intrinsic::x86_avx2_psrlv_q_256:
11457 case Intrinsic::x86_avx2_psrav_d:
11458 case Intrinsic::x86_avx2_psrav_d_256:
11462 return DAG.getNode(Opcode, dl, Op.getValueType(),
11463 Op.getOperand(1), Op.getOperand(2));
11466 case Intrinsic::x86_ssse3_pshuf_b_128:
11467 case Intrinsic::x86_avx2_pshuf_b:
11468 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
11469 Op.getOperand(1), Op.getOperand(2));
11471 case Intrinsic::x86_ssse3_psign_b_128:
11472 case Intrinsic::x86_ssse3_psign_w_128:
11473 case Intrinsic::x86_ssse3_psign_d_128:
11474 case Intrinsic::x86_avx2_psign_b:
11475 case Intrinsic::x86_avx2_psign_w:
11476 case Intrinsic::x86_avx2_psign_d:
11477 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
11478 Op.getOperand(1), Op.getOperand(2));
11480 case Intrinsic::x86_sse41_insertps:
11481 return DAG.getNode(X86ISD::INSERTPS, dl, Op.getValueType(),
11482 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
11484 case Intrinsic::x86_avx_vperm2f128_ps_256:
11485 case Intrinsic::x86_avx_vperm2f128_pd_256:
11486 case Intrinsic::x86_avx_vperm2f128_si_256:
11487 case Intrinsic::x86_avx2_vperm2i128:
11488 return DAG.getNode(X86ISD::VPERM2X128, dl, Op.getValueType(),
11489 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
11491 case Intrinsic::x86_avx2_permd:
11492 case Intrinsic::x86_avx2_permps:
11493 // Operands intentionally swapped. Mask is last operand to intrinsic,
11494 // but second operand for node/instruction.
11495 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
11496 Op.getOperand(2), Op.getOperand(1));
11498 case Intrinsic::x86_sse_sqrt_ps:
11499 case Intrinsic::x86_sse2_sqrt_pd:
11500 case Intrinsic::x86_avx_sqrt_ps_256:
11501 case Intrinsic::x86_avx_sqrt_pd_256:
11502 return DAG.getNode(ISD::FSQRT, dl, Op.getValueType(), Op.getOperand(1));
11504 // ptest and testp intrinsics. The intrinsic these come from are designed to
11505 // return an integer value, not just an instruction so lower it to the ptest
11506 // or testp pattern and a setcc for the result.
11507 case Intrinsic::x86_sse41_ptestz:
11508 case Intrinsic::x86_sse41_ptestc:
11509 case Intrinsic::x86_sse41_ptestnzc:
11510 case Intrinsic::x86_avx_ptestz_256:
11511 case Intrinsic::x86_avx_ptestc_256:
11512 case Intrinsic::x86_avx_ptestnzc_256:
11513 case Intrinsic::x86_avx_vtestz_ps:
11514 case Intrinsic::x86_avx_vtestc_ps:
11515 case Intrinsic::x86_avx_vtestnzc_ps:
11516 case Intrinsic::x86_avx_vtestz_pd:
11517 case Intrinsic::x86_avx_vtestc_pd:
11518 case Intrinsic::x86_avx_vtestnzc_pd:
11519 case Intrinsic::x86_avx_vtestz_ps_256:
11520 case Intrinsic::x86_avx_vtestc_ps_256:
11521 case Intrinsic::x86_avx_vtestnzc_ps_256:
11522 case Intrinsic::x86_avx_vtestz_pd_256:
11523 case Intrinsic::x86_avx_vtestc_pd_256:
11524 case Intrinsic::x86_avx_vtestnzc_pd_256: {
11525 bool IsTestPacked = false;
11528 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
11529 case Intrinsic::x86_avx_vtestz_ps:
11530 case Intrinsic::x86_avx_vtestz_pd:
11531 case Intrinsic::x86_avx_vtestz_ps_256:
11532 case Intrinsic::x86_avx_vtestz_pd_256:
11533 IsTestPacked = true; // Fallthrough
11534 case Intrinsic::x86_sse41_ptestz:
11535 case Intrinsic::x86_avx_ptestz_256:
11537 X86CC = X86::COND_E;
11539 case Intrinsic::x86_avx_vtestc_ps:
11540 case Intrinsic::x86_avx_vtestc_pd:
11541 case Intrinsic::x86_avx_vtestc_ps_256:
11542 case Intrinsic::x86_avx_vtestc_pd_256:
11543 IsTestPacked = true; // Fallthrough
11544 case Intrinsic::x86_sse41_ptestc:
11545 case Intrinsic::x86_avx_ptestc_256:
11547 X86CC = X86::COND_B;
11549 case Intrinsic::x86_avx_vtestnzc_ps:
11550 case Intrinsic::x86_avx_vtestnzc_pd:
11551 case Intrinsic::x86_avx_vtestnzc_ps_256:
11552 case Intrinsic::x86_avx_vtestnzc_pd_256:
11553 IsTestPacked = true; // Fallthrough
11554 case Intrinsic::x86_sse41_ptestnzc:
11555 case Intrinsic::x86_avx_ptestnzc_256:
11557 X86CC = X86::COND_A;
11561 SDValue LHS = Op.getOperand(1);
11562 SDValue RHS = Op.getOperand(2);
11563 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
11564 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
11565 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
11566 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
11567 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
11569 case Intrinsic::x86_avx512_kortestz_w:
11570 case Intrinsic::x86_avx512_kortestc_w: {
11571 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
11572 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
11573 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
11574 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
11575 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
11576 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
11577 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
11580 // SSE/AVX shift intrinsics
11581 case Intrinsic::x86_sse2_psll_w:
11582 case Intrinsic::x86_sse2_psll_d:
11583 case Intrinsic::x86_sse2_psll_q:
11584 case Intrinsic::x86_avx2_psll_w:
11585 case Intrinsic::x86_avx2_psll_d:
11586 case Intrinsic::x86_avx2_psll_q:
11587 case Intrinsic::x86_sse2_psrl_w:
11588 case Intrinsic::x86_sse2_psrl_d:
11589 case Intrinsic::x86_sse2_psrl_q:
11590 case Intrinsic::x86_avx2_psrl_w:
11591 case Intrinsic::x86_avx2_psrl_d:
11592 case Intrinsic::x86_avx2_psrl_q:
11593 case Intrinsic::x86_sse2_psra_w:
11594 case Intrinsic::x86_sse2_psra_d:
11595 case Intrinsic::x86_avx2_psra_w:
11596 case Intrinsic::x86_avx2_psra_d: {
11599 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11600 case Intrinsic::x86_sse2_psll_w:
11601 case Intrinsic::x86_sse2_psll_d:
11602 case Intrinsic::x86_sse2_psll_q:
11603 case Intrinsic::x86_avx2_psll_w:
11604 case Intrinsic::x86_avx2_psll_d:
11605 case Intrinsic::x86_avx2_psll_q:
11606 Opcode = X86ISD::VSHL;
11608 case Intrinsic::x86_sse2_psrl_w:
11609 case Intrinsic::x86_sse2_psrl_d:
11610 case Intrinsic::x86_sse2_psrl_q:
11611 case Intrinsic::x86_avx2_psrl_w:
11612 case Intrinsic::x86_avx2_psrl_d:
11613 case Intrinsic::x86_avx2_psrl_q:
11614 Opcode = X86ISD::VSRL;
11616 case Intrinsic::x86_sse2_psra_w:
11617 case Intrinsic::x86_sse2_psra_d:
11618 case Intrinsic::x86_avx2_psra_w:
11619 case Intrinsic::x86_avx2_psra_d:
11620 Opcode = X86ISD::VSRA;
11623 return DAG.getNode(Opcode, dl, Op.getValueType(),
11624 Op.getOperand(1), Op.getOperand(2));
11627 // SSE/AVX immediate shift intrinsics
11628 case Intrinsic::x86_sse2_pslli_w:
11629 case Intrinsic::x86_sse2_pslli_d:
11630 case Intrinsic::x86_sse2_pslli_q:
11631 case Intrinsic::x86_avx2_pslli_w:
11632 case Intrinsic::x86_avx2_pslli_d:
11633 case Intrinsic::x86_avx2_pslli_q:
11634 case Intrinsic::x86_sse2_psrli_w:
11635 case Intrinsic::x86_sse2_psrli_d:
11636 case Intrinsic::x86_sse2_psrli_q:
11637 case Intrinsic::x86_avx2_psrli_w:
11638 case Intrinsic::x86_avx2_psrli_d:
11639 case Intrinsic::x86_avx2_psrli_q:
11640 case Intrinsic::x86_sse2_psrai_w:
11641 case Intrinsic::x86_sse2_psrai_d:
11642 case Intrinsic::x86_avx2_psrai_w:
11643 case Intrinsic::x86_avx2_psrai_d: {
11646 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11647 case Intrinsic::x86_sse2_pslli_w:
11648 case Intrinsic::x86_sse2_pslli_d:
11649 case Intrinsic::x86_sse2_pslli_q:
11650 case Intrinsic::x86_avx2_pslli_w:
11651 case Intrinsic::x86_avx2_pslli_d:
11652 case Intrinsic::x86_avx2_pslli_q:
11653 Opcode = X86ISD::VSHLI;
11655 case Intrinsic::x86_sse2_psrli_w:
11656 case Intrinsic::x86_sse2_psrli_d:
11657 case Intrinsic::x86_sse2_psrli_q:
11658 case Intrinsic::x86_avx2_psrli_w:
11659 case Intrinsic::x86_avx2_psrli_d:
11660 case Intrinsic::x86_avx2_psrli_q:
11661 Opcode = X86ISD::VSRLI;
11663 case Intrinsic::x86_sse2_psrai_w:
11664 case Intrinsic::x86_sse2_psrai_d:
11665 case Intrinsic::x86_avx2_psrai_w:
11666 case Intrinsic::x86_avx2_psrai_d:
11667 Opcode = X86ISD::VSRAI;
11670 return getTargetVShiftNode(Opcode, dl, Op.getValueType(),
11671 Op.getOperand(1), Op.getOperand(2), DAG);
11674 case Intrinsic::x86_sse42_pcmpistria128:
11675 case Intrinsic::x86_sse42_pcmpestria128:
11676 case Intrinsic::x86_sse42_pcmpistric128:
11677 case Intrinsic::x86_sse42_pcmpestric128:
11678 case Intrinsic::x86_sse42_pcmpistrio128:
11679 case Intrinsic::x86_sse42_pcmpestrio128:
11680 case Intrinsic::x86_sse42_pcmpistris128:
11681 case Intrinsic::x86_sse42_pcmpestris128:
11682 case Intrinsic::x86_sse42_pcmpistriz128:
11683 case Intrinsic::x86_sse42_pcmpestriz128: {
11687 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11688 case Intrinsic::x86_sse42_pcmpistria128:
11689 Opcode = X86ISD::PCMPISTRI;
11690 X86CC = X86::COND_A;
11692 case Intrinsic::x86_sse42_pcmpestria128:
11693 Opcode = X86ISD::PCMPESTRI;
11694 X86CC = X86::COND_A;
11696 case Intrinsic::x86_sse42_pcmpistric128:
11697 Opcode = X86ISD::PCMPISTRI;
11698 X86CC = X86::COND_B;
11700 case Intrinsic::x86_sse42_pcmpestric128:
11701 Opcode = X86ISD::PCMPESTRI;
11702 X86CC = X86::COND_B;
11704 case Intrinsic::x86_sse42_pcmpistrio128:
11705 Opcode = X86ISD::PCMPISTRI;
11706 X86CC = X86::COND_O;
11708 case Intrinsic::x86_sse42_pcmpestrio128:
11709 Opcode = X86ISD::PCMPESTRI;
11710 X86CC = X86::COND_O;
11712 case Intrinsic::x86_sse42_pcmpistris128:
11713 Opcode = X86ISD::PCMPISTRI;
11714 X86CC = X86::COND_S;
11716 case Intrinsic::x86_sse42_pcmpestris128:
11717 Opcode = X86ISD::PCMPESTRI;
11718 X86CC = X86::COND_S;
11720 case Intrinsic::x86_sse42_pcmpistriz128:
11721 Opcode = X86ISD::PCMPISTRI;
11722 X86CC = X86::COND_E;
11724 case Intrinsic::x86_sse42_pcmpestriz128:
11725 Opcode = X86ISD::PCMPESTRI;
11726 X86CC = X86::COND_E;
11729 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
11730 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
11731 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps.data(), NewOps.size());
11732 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
11733 DAG.getConstant(X86CC, MVT::i8),
11734 SDValue(PCMP.getNode(), 1));
11735 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
11738 case Intrinsic::x86_sse42_pcmpistri128:
11739 case Intrinsic::x86_sse42_pcmpestri128: {
11741 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
11742 Opcode = X86ISD::PCMPISTRI;
11744 Opcode = X86ISD::PCMPESTRI;
11746 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
11747 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
11748 return DAG.getNode(Opcode, dl, VTs, NewOps.data(), NewOps.size());
11750 case Intrinsic::x86_fma_vfmadd_ps:
11751 case Intrinsic::x86_fma_vfmadd_pd:
11752 case Intrinsic::x86_fma_vfmsub_ps:
11753 case Intrinsic::x86_fma_vfmsub_pd:
11754 case Intrinsic::x86_fma_vfnmadd_ps:
11755 case Intrinsic::x86_fma_vfnmadd_pd:
11756 case Intrinsic::x86_fma_vfnmsub_ps:
11757 case Intrinsic::x86_fma_vfnmsub_pd:
11758 case Intrinsic::x86_fma_vfmaddsub_ps:
11759 case Intrinsic::x86_fma_vfmaddsub_pd:
11760 case Intrinsic::x86_fma_vfmsubadd_ps:
11761 case Intrinsic::x86_fma_vfmsubadd_pd:
11762 case Intrinsic::x86_fma_vfmadd_ps_256:
11763 case Intrinsic::x86_fma_vfmadd_pd_256:
11764 case Intrinsic::x86_fma_vfmsub_ps_256:
11765 case Intrinsic::x86_fma_vfmsub_pd_256:
11766 case Intrinsic::x86_fma_vfnmadd_ps_256:
11767 case Intrinsic::x86_fma_vfnmadd_pd_256:
11768 case Intrinsic::x86_fma_vfnmsub_ps_256:
11769 case Intrinsic::x86_fma_vfnmsub_pd_256:
11770 case Intrinsic::x86_fma_vfmaddsub_ps_256:
11771 case Intrinsic::x86_fma_vfmaddsub_pd_256:
11772 case Intrinsic::x86_fma_vfmsubadd_ps_256:
11773 case Intrinsic::x86_fma_vfmsubadd_pd_256:
11774 case Intrinsic::x86_fma_vfmadd_ps_512:
11775 case Intrinsic::x86_fma_vfmadd_pd_512:
11776 case Intrinsic::x86_fma_vfmsub_ps_512:
11777 case Intrinsic::x86_fma_vfmsub_pd_512:
11778 case Intrinsic::x86_fma_vfnmadd_ps_512:
11779 case Intrinsic::x86_fma_vfnmadd_pd_512:
11780 case Intrinsic::x86_fma_vfnmsub_ps_512:
11781 case Intrinsic::x86_fma_vfnmsub_pd_512:
11782 case Intrinsic::x86_fma_vfmaddsub_ps_512:
11783 case Intrinsic::x86_fma_vfmaddsub_pd_512:
11784 case Intrinsic::x86_fma_vfmsubadd_ps_512:
11785 case Intrinsic::x86_fma_vfmsubadd_pd_512: {
11788 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11789 case Intrinsic::x86_fma_vfmadd_ps:
11790 case Intrinsic::x86_fma_vfmadd_pd:
11791 case Intrinsic::x86_fma_vfmadd_ps_256:
11792 case Intrinsic::x86_fma_vfmadd_pd_256:
11793 case Intrinsic::x86_fma_vfmadd_ps_512:
11794 case Intrinsic::x86_fma_vfmadd_pd_512:
11795 Opc = X86ISD::FMADD;
11797 case Intrinsic::x86_fma_vfmsub_ps:
11798 case Intrinsic::x86_fma_vfmsub_pd:
11799 case Intrinsic::x86_fma_vfmsub_ps_256:
11800 case Intrinsic::x86_fma_vfmsub_pd_256:
11801 case Intrinsic::x86_fma_vfmsub_ps_512:
11802 case Intrinsic::x86_fma_vfmsub_pd_512:
11803 Opc = X86ISD::FMSUB;
11805 case Intrinsic::x86_fma_vfnmadd_ps:
11806 case Intrinsic::x86_fma_vfnmadd_pd:
11807 case Intrinsic::x86_fma_vfnmadd_ps_256:
11808 case Intrinsic::x86_fma_vfnmadd_pd_256:
11809 case Intrinsic::x86_fma_vfnmadd_ps_512:
11810 case Intrinsic::x86_fma_vfnmadd_pd_512:
11811 Opc = X86ISD::FNMADD;
11813 case Intrinsic::x86_fma_vfnmsub_ps:
11814 case Intrinsic::x86_fma_vfnmsub_pd:
11815 case Intrinsic::x86_fma_vfnmsub_ps_256:
11816 case Intrinsic::x86_fma_vfnmsub_pd_256:
11817 case Intrinsic::x86_fma_vfnmsub_ps_512:
11818 case Intrinsic::x86_fma_vfnmsub_pd_512:
11819 Opc = X86ISD::FNMSUB;
11821 case Intrinsic::x86_fma_vfmaddsub_ps:
11822 case Intrinsic::x86_fma_vfmaddsub_pd:
11823 case Intrinsic::x86_fma_vfmaddsub_ps_256:
11824 case Intrinsic::x86_fma_vfmaddsub_pd_256:
11825 case Intrinsic::x86_fma_vfmaddsub_ps_512:
11826 case Intrinsic::x86_fma_vfmaddsub_pd_512:
11827 Opc = X86ISD::FMADDSUB;
11829 case Intrinsic::x86_fma_vfmsubadd_ps:
11830 case Intrinsic::x86_fma_vfmsubadd_pd:
11831 case Intrinsic::x86_fma_vfmsubadd_ps_256:
11832 case Intrinsic::x86_fma_vfmsubadd_pd_256:
11833 case Intrinsic::x86_fma_vfmsubadd_ps_512:
11834 case Intrinsic::x86_fma_vfmsubadd_pd_512:
11835 Opc = X86ISD::FMSUBADD;
11839 return DAG.getNode(Opc, dl, Op.getValueType(), Op.getOperand(1),
11840 Op.getOperand(2), Op.getOperand(3));
11845 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
11846 SDValue Base, SDValue Index,
11847 SDValue ScaleOp, SDValue Chain,
11848 const X86Subtarget * Subtarget) {
11850 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
11851 assert(C && "Invalid scale type");
11852 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
11853 SDValue Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
11854 EVT MaskVT = MVT::getVectorVT(MVT::i1,
11855 Index.getValueType().getVectorNumElements());
11856 SDValue MaskInReg = DAG.getConstant(~0, MaskVT);
11857 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
11858 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
11859 SDValue Segment = DAG.getRegister(0, MVT::i32);
11860 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
11861 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
11862 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
11863 return DAG.getMergeValues(RetOps, array_lengthof(RetOps), dl);
11866 static SDValue getMGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
11867 SDValue Src, SDValue Mask, SDValue Base,
11868 SDValue Index, SDValue ScaleOp, SDValue Chain,
11869 const X86Subtarget * Subtarget) {
11871 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
11872 assert(C && "Invalid scale type");
11873 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
11874 EVT MaskVT = MVT::getVectorVT(MVT::i1,
11875 Index.getValueType().getVectorNumElements());
11876 SDValue MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
11877 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
11878 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
11879 SDValue Segment = DAG.getRegister(0, MVT::i32);
11880 if (Src.getOpcode() == ISD::UNDEF)
11881 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
11882 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
11883 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
11884 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
11885 return DAG.getMergeValues(RetOps, array_lengthof(RetOps), dl);
11888 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
11889 SDValue Src, SDValue Base, SDValue Index,
11890 SDValue ScaleOp, SDValue Chain) {
11892 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
11893 assert(C && "Invalid scale type");
11894 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
11895 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
11896 SDValue Segment = DAG.getRegister(0, MVT::i32);
11897 EVT MaskVT = MVT::getVectorVT(MVT::i1,
11898 Index.getValueType().getVectorNumElements());
11899 SDValue MaskInReg = DAG.getConstant(~0, MaskVT);
11900 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
11901 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
11902 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
11903 return SDValue(Res, 1);
11906 static SDValue getMScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
11907 SDValue Src, SDValue Mask, SDValue Base,
11908 SDValue Index, SDValue ScaleOp, SDValue Chain) {
11910 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
11911 assert(C && "Invalid scale type");
11912 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
11913 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
11914 SDValue Segment = DAG.getRegister(0, MVT::i32);
11915 EVT MaskVT = MVT::getVectorVT(MVT::i1,
11916 Index.getValueType().getVectorNumElements());
11917 SDValue MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
11918 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
11919 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
11920 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
11921 return SDValue(Res, 1);
11924 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
11925 SelectionDAG &DAG) {
11927 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11929 default: return SDValue(); // Don't custom lower most intrinsics.
11931 // RDRAND/RDSEED intrinsics.
11932 case Intrinsic::x86_rdrand_16:
11933 case Intrinsic::x86_rdrand_32:
11934 case Intrinsic::x86_rdrand_64:
11935 case Intrinsic::x86_rdseed_16:
11936 case Intrinsic::x86_rdseed_32:
11937 case Intrinsic::x86_rdseed_64: {
11938 unsigned Opcode = (IntNo == Intrinsic::x86_rdseed_16 ||
11939 IntNo == Intrinsic::x86_rdseed_32 ||
11940 IntNo == Intrinsic::x86_rdseed_64) ? X86ISD::RDSEED :
11942 // Emit the node with the right value type.
11943 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
11944 SDValue Result = DAG.getNode(Opcode, dl, VTs, Op.getOperand(0));
11946 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
11947 // Otherwise return the value from Rand, which is always 0, casted to i32.
11948 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
11949 DAG.getConstant(1, Op->getValueType(1)),
11950 DAG.getConstant(X86::COND_B, MVT::i32),
11951 SDValue(Result.getNode(), 1) };
11952 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
11953 DAG.getVTList(Op->getValueType(1), MVT::Glue),
11954 Ops, array_lengthof(Ops));
11956 // Return { result, isValid, chain }.
11957 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
11958 SDValue(Result.getNode(), 2));
11960 //int_gather(index, base, scale);
11961 case Intrinsic::x86_avx512_gather_qpd_512:
11962 case Intrinsic::x86_avx512_gather_qps_512:
11963 case Intrinsic::x86_avx512_gather_dpd_512:
11964 case Intrinsic::x86_avx512_gather_qpi_512:
11965 case Intrinsic::x86_avx512_gather_qpq_512:
11966 case Intrinsic::x86_avx512_gather_dpq_512:
11967 case Intrinsic::x86_avx512_gather_dps_512:
11968 case Intrinsic::x86_avx512_gather_dpi_512: {
11971 default: llvm_unreachable("Unexpected intrinsic!");
11972 case Intrinsic::x86_avx512_gather_qps_512: Opc = X86::VGATHERQPSZrm; break;
11973 case Intrinsic::x86_avx512_gather_qpd_512: Opc = X86::VGATHERQPDZrm; break;
11974 case Intrinsic::x86_avx512_gather_dpd_512: Opc = X86::VGATHERDPDZrm; break;
11975 case Intrinsic::x86_avx512_gather_dps_512: Opc = X86::VGATHERDPSZrm; break;
11976 case Intrinsic::x86_avx512_gather_qpi_512: Opc = X86::VPGATHERQDZrm; break;
11977 case Intrinsic::x86_avx512_gather_qpq_512: Opc = X86::VPGATHERQQZrm; break;
11978 case Intrinsic::x86_avx512_gather_dpi_512: Opc = X86::VPGATHERDDZrm; break;
11979 case Intrinsic::x86_avx512_gather_dpq_512: Opc = X86::VPGATHERDQZrm; break;
11981 SDValue Chain = Op.getOperand(0);
11982 SDValue Index = Op.getOperand(2);
11983 SDValue Base = Op.getOperand(3);
11984 SDValue Scale = Op.getOperand(4);
11985 return getGatherNode(Opc, Op, DAG, Base, Index, Scale, Chain, Subtarget);
11987 //int_gather_mask(v1, mask, index, base, scale);
11988 case Intrinsic::x86_avx512_gather_qps_mask_512:
11989 case Intrinsic::x86_avx512_gather_qpd_mask_512:
11990 case Intrinsic::x86_avx512_gather_dpd_mask_512:
11991 case Intrinsic::x86_avx512_gather_dps_mask_512:
11992 case Intrinsic::x86_avx512_gather_qpi_mask_512:
11993 case Intrinsic::x86_avx512_gather_qpq_mask_512:
11994 case Intrinsic::x86_avx512_gather_dpi_mask_512:
11995 case Intrinsic::x86_avx512_gather_dpq_mask_512: {
11998 default: llvm_unreachable("Unexpected intrinsic!");
11999 case Intrinsic::x86_avx512_gather_qps_mask_512:
12000 Opc = X86::VGATHERQPSZrm; break;
12001 case Intrinsic::x86_avx512_gather_qpd_mask_512:
12002 Opc = X86::VGATHERQPDZrm; break;
12003 case Intrinsic::x86_avx512_gather_dpd_mask_512:
12004 Opc = X86::VGATHERDPDZrm; break;
12005 case Intrinsic::x86_avx512_gather_dps_mask_512:
12006 Opc = X86::VGATHERDPSZrm; break;
12007 case Intrinsic::x86_avx512_gather_qpi_mask_512:
12008 Opc = X86::VPGATHERQDZrm; break;
12009 case Intrinsic::x86_avx512_gather_qpq_mask_512:
12010 Opc = X86::VPGATHERQQZrm; break;
12011 case Intrinsic::x86_avx512_gather_dpi_mask_512:
12012 Opc = X86::VPGATHERDDZrm; break;
12013 case Intrinsic::x86_avx512_gather_dpq_mask_512:
12014 Opc = X86::VPGATHERDQZrm; break;
12016 SDValue Chain = Op.getOperand(0);
12017 SDValue Src = Op.getOperand(2);
12018 SDValue Mask = Op.getOperand(3);
12019 SDValue Index = Op.getOperand(4);
12020 SDValue Base = Op.getOperand(5);
12021 SDValue Scale = Op.getOperand(6);
12022 return getMGatherNode(Opc, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
12025 //int_scatter(base, index, v1, scale);
12026 case Intrinsic::x86_avx512_scatter_qpd_512:
12027 case Intrinsic::x86_avx512_scatter_qps_512:
12028 case Intrinsic::x86_avx512_scatter_dpd_512:
12029 case Intrinsic::x86_avx512_scatter_qpi_512:
12030 case Intrinsic::x86_avx512_scatter_qpq_512:
12031 case Intrinsic::x86_avx512_scatter_dpq_512:
12032 case Intrinsic::x86_avx512_scatter_dps_512:
12033 case Intrinsic::x86_avx512_scatter_dpi_512: {
12036 default: llvm_unreachable("Unexpected intrinsic!");
12037 case Intrinsic::x86_avx512_scatter_qpd_512:
12038 Opc = X86::VSCATTERQPDZmr; break;
12039 case Intrinsic::x86_avx512_scatter_qps_512:
12040 Opc = X86::VSCATTERQPSZmr; break;
12041 case Intrinsic::x86_avx512_scatter_dpd_512:
12042 Opc = X86::VSCATTERDPDZmr; break;
12043 case Intrinsic::x86_avx512_scatter_dps_512:
12044 Opc = X86::VSCATTERDPSZmr; break;
12045 case Intrinsic::x86_avx512_scatter_qpi_512:
12046 Opc = X86::VPSCATTERQDZmr; break;
12047 case Intrinsic::x86_avx512_scatter_qpq_512:
12048 Opc = X86::VPSCATTERQQZmr; break;
12049 case Intrinsic::x86_avx512_scatter_dpq_512:
12050 Opc = X86::VPSCATTERDQZmr; break;
12051 case Intrinsic::x86_avx512_scatter_dpi_512:
12052 Opc = X86::VPSCATTERDDZmr; break;
12054 SDValue Chain = Op.getOperand(0);
12055 SDValue Base = Op.getOperand(2);
12056 SDValue Index = Op.getOperand(3);
12057 SDValue Src = Op.getOperand(4);
12058 SDValue Scale = Op.getOperand(5);
12059 return getScatterNode(Opc, Op, DAG, Src, Base, Index, Scale, Chain);
12061 //int_scatter_mask(base, mask, index, v1, scale);
12062 case Intrinsic::x86_avx512_scatter_qps_mask_512:
12063 case Intrinsic::x86_avx512_scatter_qpd_mask_512:
12064 case Intrinsic::x86_avx512_scatter_dpd_mask_512:
12065 case Intrinsic::x86_avx512_scatter_dps_mask_512:
12066 case Intrinsic::x86_avx512_scatter_qpi_mask_512:
12067 case Intrinsic::x86_avx512_scatter_qpq_mask_512:
12068 case Intrinsic::x86_avx512_scatter_dpi_mask_512:
12069 case Intrinsic::x86_avx512_scatter_dpq_mask_512: {
12072 default: llvm_unreachable("Unexpected intrinsic!");
12073 case Intrinsic::x86_avx512_scatter_qpd_mask_512:
12074 Opc = X86::VSCATTERQPDZmr; break;
12075 case Intrinsic::x86_avx512_scatter_qps_mask_512:
12076 Opc = X86::VSCATTERQPSZmr; break;
12077 case Intrinsic::x86_avx512_scatter_dpd_mask_512:
12078 Opc = X86::VSCATTERDPDZmr; break;
12079 case Intrinsic::x86_avx512_scatter_dps_mask_512:
12080 Opc = X86::VSCATTERDPSZmr; break;
12081 case Intrinsic::x86_avx512_scatter_qpi_mask_512:
12082 Opc = X86::VPSCATTERQDZmr; break;
12083 case Intrinsic::x86_avx512_scatter_qpq_mask_512:
12084 Opc = X86::VPSCATTERQQZmr; break;
12085 case Intrinsic::x86_avx512_scatter_dpq_mask_512:
12086 Opc = X86::VPSCATTERDQZmr; break;
12087 case Intrinsic::x86_avx512_scatter_dpi_mask_512:
12088 Opc = X86::VPSCATTERDDZmr; break;
12090 SDValue Chain = Op.getOperand(0);
12091 SDValue Base = Op.getOperand(2);
12092 SDValue Mask = Op.getOperand(3);
12093 SDValue Index = Op.getOperand(4);
12094 SDValue Src = Op.getOperand(5);
12095 SDValue Scale = Op.getOperand(6);
12096 return getMScatterNode(Opc, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
12098 // XTEST intrinsics.
12099 case Intrinsic::x86_xtest: {
12100 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
12101 SDValue InTrans = DAG.getNode(X86ISD::XTEST, dl, VTs, Op.getOperand(0));
12102 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
12103 DAG.getConstant(X86::COND_NE, MVT::i8),
12105 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
12106 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
12107 Ret, SDValue(InTrans.getNode(), 1));
12112 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
12113 SelectionDAG &DAG) const {
12114 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12115 MFI->setReturnAddressIsTaken(true);
12117 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
12119 EVT PtrVT = getPointerTy();
12122 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
12123 const X86RegisterInfo *RegInfo =
12124 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
12125 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
12126 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
12127 DAG.getNode(ISD::ADD, dl, PtrVT,
12128 FrameAddr, Offset),
12129 MachinePointerInfo(), false, false, false, 0);
12132 // Just load the return address.
12133 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
12134 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
12135 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
12138 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
12139 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12140 MFI->setFrameAddressIsTaken(true);
12142 EVT VT = Op.getValueType();
12143 SDLoc dl(Op); // FIXME probably not meaningful
12144 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
12145 const X86RegisterInfo *RegInfo =
12146 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
12147 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
12148 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
12149 (FrameReg == X86::EBP && VT == MVT::i32)) &&
12150 "Invalid Frame Register!");
12151 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
12153 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
12154 MachinePointerInfo(),
12155 false, false, false, 0);
12159 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
12160 SelectionDAG &DAG) const {
12161 const X86RegisterInfo *RegInfo =
12162 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
12163 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
12166 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
12167 SDValue Chain = Op.getOperand(0);
12168 SDValue Offset = Op.getOperand(1);
12169 SDValue Handler = Op.getOperand(2);
12172 EVT PtrVT = getPointerTy();
12173 const X86RegisterInfo *RegInfo =
12174 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
12175 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
12176 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
12177 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
12178 "Invalid Frame Register!");
12179 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
12180 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
12182 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
12183 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
12184 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
12185 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
12187 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
12189 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
12190 DAG.getRegister(StoreAddrReg, PtrVT));
12193 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
12194 SelectionDAG &DAG) const {
12196 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
12197 DAG.getVTList(MVT::i32, MVT::Other),
12198 Op.getOperand(0), Op.getOperand(1));
12201 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
12202 SelectionDAG &DAG) const {
12204 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
12205 Op.getOperand(0), Op.getOperand(1));
12208 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
12209 return Op.getOperand(0);
12212 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
12213 SelectionDAG &DAG) const {
12214 SDValue Root = Op.getOperand(0);
12215 SDValue Trmp = Op.getOperand(1); // trampoline
12216 SDValue FPtr = Op.getOperand(2); // nested function
12217 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
12220 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
12221 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
12223 if (Subtarget->is64Bit()) {
12224 SDValue OutChains[6];
12226 // Large code-model.
12227 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
12228 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
12230 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
12231 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
12233 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
12235 // Load the pointer to the nested function into R11.
12236 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
12237 SDValue Addr = Trmp;
12238 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
12239 Addr, MachinePointerInfo(TrmpAddr),
12242 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
12243 DAG.getConstant(2, MVT::i64));
12244 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
12245 MachinePointerInfo(TrmpAddr, 2),
12248 // Load the 'nest' parameter value into R10.
12249 // R10 is specified in X86CallingConv.td
12250 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
12251 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
12252 DAG.getConstant(10, MVT::i64));
12253 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
12254 Addr, MachinePointerInfo(TrmpAddr, 10),
12257 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
12258 DAG.getConstant(12, MVT::i64));
12259 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
12260 MachinePointerInfo(TrmpAddr, 12),
12263 // Jump to the nested function.
12264 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
12265 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
12266 DAG.getConstant(20, MVT::i64));
12267 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
12268 Addr, MachinePointerInfo(TrmpAddr, 20),
12271 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
12272 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
12273 DAG.getConstant(22, MVT::i64));
12274 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
12275 MachinePointerInfo(TrmpAddr, 22),
12278 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6);
12280 const Function *Func =
12281 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
12282 CallingConv::ID CC = Func->getCallingConv();
12287 llvm_unreachable("Unsupported calling convention");
12288 case CallingConv::C:
12289 case CallingConv::X86_StdCall: {
12290 // Pass 'nest' parameter in ECX.
12291 // Must be kept in sync with X86CallingConv.td
12292 NestReg = X86::ECX;
12294 // Check that ECX wasn't needed by an 'inreg' parameter.
12295 FunctionType *FTy = Func->getFunctionType();
12296 const AttributeSet &Attrs = Func->getAttributes();
12298 if (!Attrs.isEmpty() && !Func->isVarArg()) {
12299 unsigned InRegCount = 0;
12302 for (FunctionType::param_iterator I = FTy->param_begin(),
12303 E = FTy->param_end(); I != E; ++I, ++Idx)
12304 if (Attrs.hasAttribute(Idx, Attribute::InReg))
12305 // FIXME: should only count parameters that are lowered to integers.
12306 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
12308 if (InRegCount > 2) {
12309 report_fatal_error("Nest register in use - reduce number of inreg"
12315 case CallingConv::X86_FastCall:
12316 case CallingConv::X86_ThisCall:
12317 case CallingConv::Fast:
12318 // Pass 'nest' parameter in EAX.
12319 // Must be kept in sync with X86CallingConv.td
12320 NestReg = X86::EAX;
12324 SDValue OutChains[4];
12325 SDValue Addr, Disp;
12327 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
12328 DAG.getConstant(10, MVT::i32));
12329 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
12331 // This is storing the opcode for MOV32ri.
12332 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
12333 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
12334 OutChains[0] = DAG.getStore(Root, dl,
12335 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
12336 Trmp, MachinePointerInfo(TrmpAddr),
12339 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
12340 DAG.getConstant(1, MVT::i32));
12341 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
12342 MachinePointerInfo(TrmpAddr, 1),
12345 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
12346 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
12347 DAG.getConstant(5, MVT::i32));
12348 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
12349 MachinePointerInfo(TrmpAddr, 5),
12352 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
12353 DAG.getConstant(6, MVT::i32));
12354 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
12355 MachinePointerInfo(TrmpAddr, 6),
12358 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4);
12362 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
12363 SelectionDAG &DAG) const {
12365 The rounding mode is in bits 11:10 of FPSR, and has the following
12367 00 Round to nearest
12372 FLT_ROUNDS, on the other hand, expects the following:
12379 To perform the conversion, we do:
12380 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
12383 MachineFunction &MF = DAG.getMachineFunction();
12384 const TargetMachine &TM = MF.getTarget();
12385 const TargetFrameLowering &TFI = *TM.getFrameLowering();
12386 unsigned StackAlignment = TFI.getStackAlignment();
12387 EVT VT = Op.getValueType();
12390 // Save FP Control Word to stack slot
12391 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
12392 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12394 MachineMemOperand *MMO =
12395 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12396 MachineMemOperand::MOStore, 2, 2);
12398 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
12399 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
12400 DAG.getVTList(MVT::Other),
12401 Ops, array_lengthof(Ops), MVT::i16,
12404 // Load FP Control Word from stack slot
12405 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
12406 MachinePointerInfo(), false, false, false, 0);
12408 // Transform as necessary
12410 DAG.getNode(ISD::SRL, DL, MVT::i16,
12411 DAG.getNode(ISD::AND, DL, MVT::i16,
12412 CWD, DAG.getConstant(0x800, MVT::i16)),
12413 DAG.getConstant(11, MVT::i8));
12415 DAG.getNode(ISD::SRL, DL, MVT::i16,
12416 DAG.getNode(ISD::AND, DL, MVT::i16,
12417 CWD, DAG.getConstant(0x400, MVT::i16)),
12418 DAG.getConstant(9, MVT::i8));
12421 DAG.getNode(ISD::AND, DL, MVT::i16,
12422 DAG.getNode(ISD::ADD, DL, MVT::i16,
12423 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
12424 DAG.getConstant(1, MVT::i16)),
12425 DAG.getConstant(3, MVT::i16));
12427 return DAG.getNode((VT.getSizeInBits() < 16 ?
12428 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
12431 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
12432 EVT VT = Op.getValueType();
12434 unsigned NumBits = VT.getSizeInBits();
12437 Op = Op.getOperand(0);
12438 if (VT == MVT::i8) {
12439 // Zero extend to i32 since there is not an i8 bsr.
12441 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
12444 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
12445 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
12446 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
12448 // If src is zero (i.e. bsr sets ZF), returns NumBits.
12451 DAG.getConstant(NumBits+NumBits-1, OpVT),
12452 DAG.getConstant(X86::COND_E, MVT::i8),
12455 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
12457 // Finally xor with NumBits-1.
12458 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
12461 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
12465 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
12466 EVT VT = Op.getValueType();
12468 unsigned NumBits = VT.getSizeInBits();
12471 Op = Op.getOperand(0);
12472 if (VT == MVT::i8) {
12473 // Zero extend to i32 since there is not an i8 bsr.
12475 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
12478 // Issue a bsr (scan bits in reverse).
12479 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
12480 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
12482 // And xor with NumBits-1.
12483 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
12486 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
12490 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
12491 EVT VT = Op.getValueType();
12492 unsigned NumBits = VT.getSizeInBits();
12494 Op = Op.getOperand(0);
12496 // Issue a bsf (scan bits forward) which also sets EFLAGS.
12497 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
12498 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
12500 // If src is zero (i.e. bsf sets ZF), returns NumBits.
12503 DAG.getConstant(NumBits, VT),
12504 DAG.getConstant(X86::COND_E, MVT::i8),
12507 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops, array_lengthof(Ops));
12510 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
12511 // ones, and then concatenate the result back.
12512 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
12513 EVT VT = Op.getValueType();
12515 assert(VT.is256BitVector() && VT.isInteger() &&
12516 "Unsupported value type for operation");
12518 unsigned NumElems = VT.getVectorNumElements();
12521 // Extract the LHS vectors
12522 SDValue LHS = Op.getOperand(0);
12523 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
12524 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
12526 // Extract the RHS vectors
12527 SDValue RHS = Op.getOperand(1);
12528 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
12529 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
12531 MVT EltVT = VT.getVectorElementType().getSimpleVT();
12532 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
12534 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
12535 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
12536 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
12539 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
12540 assert(Op.getValueType().is256BitVector() &&
12541 Op.getValueType().isInteger() &&
12542 "Only handle AVX 256-bit vector integer operation");
12543 return Lower256IntArith(Op, DAG);
12546 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
12547 assert(Op.getValueType().is256BitVector() &&
12548 Op.getValueType().isInteger() &&
12549 "Only handle AVX 256-bit vector integer operation");
12550 return Lower256IntArith(Op, DAG);
12553 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
12554 SelectionDAG &DAG) {
12556 EVT VT = Op.getValueType();
12558 // Decompose 256-bit ops into smaller 128-bit ops.
12559 if (VT.is256BitVector() && !Subtarget->hasInt256())
12560 return Lower256IntArith(Op, DAG);
12562 SDValue A = Op.getOperand(0);
12563 SDValue B = Op.getOperand(1);
12565 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
12566 if (VT == MVT::v4i32) {
12567 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
12568 "Should not custom lower when pmuldq is available!");
12570 // Extract the odd parts.
12571 static const int UnpackMask[] = { 1, -1, 3, -1 };
12572 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
12573 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
12575 // Multiply the even parts.
12576 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
12577 // Now multiply odd parts.
12578 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
12580 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
12581 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
12583 // Merge the two vectors back together with a shuffle. This expands into 2
12585 static const int ShufMask[] = { 0, 4, 2, 6 };
12586 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
12589 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
12590 "Only know how to lower V2I64/V4I64/V8I64 multiply");
12592 // Ahi = psrlqi(a, 32);
12593 // Bhi = psrlqi(b, 32);
12595 // AloBlo = pmuludq(a, b);
12596 // AloBhi = pmuludq(a, Bhi);
12597 // AhiBlo = pmuludq(Ahi, b);
12599 // AloBhi = psllqi(AloBhi, 32);
12600 // AhiBlo = psllqi(AhiBlo, 32);
12601 // return AloBlo + AloBhi + AhiBlo;
12603 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
12604 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
12606 // Bit cast to 32-bit vectors for MULUDQ
12607 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
12608 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
12609 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
12610 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
12611 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
12612 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
12614 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
12615 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
12616 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
12618 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
12619 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
12621 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
12622 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
12625 static SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) {
12626 EVT VT = Op.getValueType();
12627 EVT EltTy = VT.getVectorElementType();
12628 unsigned NumElts = VT.getVectorNumElements();
12629 SDValue N0 = Op.getOperand(0);
12632 // Lower sdiv X, pow2-const.
12633 BuildVectorSDNode *C = dyn_cast<BuildVectorSDNode>(Op.getOperand(1));
12637 APInt SplatValue, SplatUndef;
12638 unsigned SplatBitSize;
12640 if (!C->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
12642 EltTy.getSizeInBits() < SplatBitSize)
12645 if ((SplatValue != 0) &&
12646 (SplatValue.isPowerOf2() || (-SplatValue).isPowerOf2())) {
12647 unsigned Lg2 = SplatValue.countTrailingZeros();
12648 // Splat the sign bit.
12649 SmallVector<SDValue, 16> Sz(NumElts,
12650 DAG.getConstant(EltTy.getSizeInBits() - 1,
12652 SDValue SGN = DAG.getNode(ISD::SRA, dl, VT, N0,
12653 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Sz[0],
12655 // Add (N0 < 0) ? abs2 - 1 : 0;
12656 SmallVector<SDValue, 16> Amt(NumElts,
12657 DAG.getConstant(EltTy.getSizeInBits() - Lg2,
12659 SDValue SRL = DAG.getNode(ISD::SRL, dl, VT, SGN,
12660 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Amt[0],
12662 SDValue ADD = DAG.getNode(ISD::ADD, dl, VT, N0, SRL);
12663 SmallVector<SDValue, 16> Lg2Amt(NumElts, DAG.getConstant(Lg2, EltTy));
12664 SDValue SRA = DAG.getNode(ISD::SRA, dl, VT, ADD,
12665 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Lg2Amt[0],
12668 // If we're dividing by a positive value, we're done. Otherwise, we must
12669 // negate the result.
12670 if (SplatValue.isNonNegative())
12673 SmallVector<SDValue, 16> V(NumElts, DAG.getConstant(0, EltTy));
12674 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], NumElts);
12675 return DAG.getNode(ISD::SUB, dl, VT, Zero, SRA);
12680 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
12681 const X86Subtarget *Subtarget) {
12682 EVT VT = Op.getValueType();
12684 SDValue R = Op.getOperand(0);
12685 SDValue Amt = Op.getOperand(1);
12687 // Optimize shl/srl/sra with constant shift amount.
12688 if (isSplatVector(Amt.getNode())) {
12689 SDValue SclrAmt = Amt->getOperand(0);
12690 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
12691 uint64_t ShiftAmt = C->getZExtValue();
12693 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
12694 (Subtarget->hasInt256() &&
12695 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
12696 (Subtarget->hasAVX512() &&
12697 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
12698 if (Op.getOpcode() == ISD::SHL)
12699 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
12701 if (Op.getOpcode() == ISD::SRL)
12702 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
12704 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
12705 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
12709 if (VT == MVT::v16i8) {
12710 if (Op.getOpcode() == ISD::SHL) {
12711 // Make a large shift.
12712 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
12713 MVT::v8i16, R, ShiftAmt,
12715 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
12716 // Zero out the rightmost bits.
12717 SmallVector<SDValue, 16> V(16,
12718 DAG.getConstant(uint8_t(-1U << ShiftAmt),
12720 return DAG.getNode(ISD::AND, dl, VT, SHL,
12721 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
12723 if (Op.getOpcode() == ISD::SRL) {
12724 // Make a large shift.
12725 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
12726 MVT::v8i16, R, ShiftAmt,
12728 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
12729 // Zero out the leftmost bits.
12730 SmallVector<SDValue, 16> V(16,
12731 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
12733 return DAG.getNode(ISD::AND, dl, VT, SRL,
12734 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
12736 if (Op.getOpcode() == ISD::SRA) {
12737 if (ShiftAmt == 7) {
12738 // R s>> 7 === R s< 0
12739 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
12740 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
12743 // R s>> a === ((R u>> a) ^ m) - m
12744 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
12745 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
12747 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16);
12748 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
12749 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
12752 llvm_unreachable("Unknown shift opcode.");
12755 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
12756 if (Op.getOpcode() == ISD::SHL) {
12757 // Make a large shift.
12758 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
12759 MVT::v16i16, R, ShiftAmt,
12761 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
12762 // Zero out the rightmost bits.
12763 SmallVector<SDValue, 32> V(32,
12764 DAG.getConstant(uint8_t(-1U << ShiftAmt),
12766 return DAG.getNode(ISD::AND, dl, VT, SHL,
12767 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
12769 if (Op.getOpcode() == ISD::SRL) {
12770 // Make a large shift.
12771 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
12772 MVT::v16i16, R, ShiftAmt,
12774 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
12775 // Zero out the leftmost bits.
12776 SmallVector<SDValue, 32> V(32,
12777 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
12779 return DAG.getNode(ISD::AND, dl, VT, SRL,
12780 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
12782 if (Op.getOpcode() == ISD::SRA) {
12783 if (ShiftAmt == 7) {
12784 // R s>> 7 === R s< 0
12785 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
12786 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
12789 // R s>> a === ((R u>> a) ^ m) - m
12790 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
12791 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
12793 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32);
12794 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
12795 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
12798 llvm_unreachable("Unknown shift opcode.");
12803 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
12804 if (!Subtarget->is64Bit() &&
12805 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
12806 Amt.getOpcode() == ISD::BITCAST &&
12807 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
12808 Amt = Amt.getOperand(0);
12809 unsigned Ratio = Amt.getValueType().getVectorNumElements() /
12810 VT.getVectorNumElements();
12811 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
12812 uint64_t ShiftAmt = 0;
12813 for (unsigned i = 0; i != Ratio; ++i) {
12814 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
12818 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
12820 // Check remaining shift amounts.
12821 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
12822 uint64_t ShAmt = 0;
12823 for (unsigned j = 0; j != Ratio; ++j) {
12824 ConstantSDNode *C =
12825 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
12829 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
12831 if (ShAmt != ShiftAmt)
12834 switch (Op.getOpcode()) {
12836 llvm_unreachable("Unknown shift opcode!");
12838 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
12841 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
12844 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
12852 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
12853 const X86Subtarget* Subtarget) {
12854 EVT VT = Op.getValueType();
12856 SDValue R = Op.getOperand(0);
12857 SDValue Amt = Op.getOperand(1);
12859 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
12860 VT == MVT::v4i32 || VT == MVT::v8i16 ||
12861 (Subtarget->hasInt256() &&
12862 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
12863 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
12864 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
12866 EVT EltVT = VT.getVectorElementType();
12868 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
12869 unsigned NumElts = VT.getVectorNumElements();
12871 for (i = 0; i != NumElts; ++i) {
12872 if (Amt.getOperand(i).getOpcode() == ISD::UNDEF)
12876 for (j = i; j != NumElts; ++j) {
12877 SDValue Arg = Amt.getOperand(j);
12878 if (Arg.getOpcode() == ISD::UNDEF) continue;
12879 if (Arg != Amt.getOperand(i))
12882 if (i != NumElts && j == NumElts)
12883 BaseShAmt = Amt.getOperand(i);
12885 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
12886 Amt = Amt.getOperand(0);
12887 if (Amt.getOpcode() == ISD::VECTOR_SHUFFLE &&
12888 cast<ShuffleVectorSDNode>(Amt)->isSplat()) {
12889 SDValue InVec = Amt.getOperand(0);
12890 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
12891 unsigned NumElts = InVec.getValueType().getVectorNumElements();
12893 for (; i != NumElts; ++i) {
12894 SDValue Arg = InVec.getOperand(i);
12895 if (Arg.getOpcode() == ISD::UNDEF) continue;
12899 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
12900 if (ConstantSDNode *C =
12901 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
12902 unsigned SplatIdx =
12903 cast<ShuffleVectorSDNode>(Amt)->getSplatIndex();
12904 if (C->getZExtValue() == SplatIdx)
12905 BaseShAmt = InVec.getOperand(1);
12908 if (BaseShAmt.getNode() == 0)
12909 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Amt,
12910 DAG.getIntPtrConstant(0));
12914 if (BaseShAmt.getNode()) {
12915 if (EltVT.bitsGT(MVT::i32))
12916 BaseShAmt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BaseShAmt);
12917 else if (EltVT.bitsLT(MVT::i32))
12918 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
12920 switch (Op.getOpcode()) {
12922 llvm_unreachable("Unknown shift opcode!");
12924 switch (VT.getSimpleVT().SimpleTy) {
12925 default: return SDValue();
12934 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
12937 switch (VT.getSimpleVT().SimpleTy) {
12938 default: return SDValue();
12945 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
12948 switch (VT.getSimpleVT().SimpleTy) {
12949 default: return SDValue();
12958 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
12964 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
12965 if (!Subtarget->is64Bit() &&
12966 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
12967 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
12968 Amt.getOpcode() == ISD::BITCAST &&
12969 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
12970 Amt = Amt.getOperand(0);
12971 unsigned Ratio = Amt.getValueType().getVectorNumElements() /
12972 VT.getVectorNumElements();
12973 std::vector<SDValue> Vals(Ratio);
12974 for (unsigned i = 0; i != Ratio; ++i)
12975 Vals[i] = Amt.getOperand(i);
12976 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
12977 for (unsigned j = 0; j != Ratio; ++j)
12978 if (Vals[j] != Amt.getOperand(i + j))
12981 switch (Op.getOpcode()) {
12983 llvm_unreachable("Unknown shift opcode!");
12985 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
12987 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
12989 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
12996 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
12997 SelectionDAG &DAG) {
12999 EVT VT = Op.getValueType();
13001 SDValue R = Op.getOperand(0);
13002 SDValue Amt = Op.getOperand(1);
13005 if (!Subtarget->hasSSE2())
13008 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
13012 V = LowerScalarVariableShift(Op, DAG, Subtarget);
13016 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
13018 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
13019 if (Subtarget->hasInt256()) {
13020 if (Op.getOpcode() == ISD::SRL &&
13021 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
13022 VT == MVT::v4i64 || VT == MVT::v8i32))
13024 if (Op.getOpcode() == ISD::SHL &&
13025 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
13026 VT == MVT::v4i64 || VT == MVT::v8i32))
13028 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
13032 // Lower SHL with variable shift amount.
13033 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
13034 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
13036 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
13037 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
13038 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
13039 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
13041 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
13042 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
13045 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
13046 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
13048 // Turn 'a' into a mask suitable for VSELECT
13049 SDValue VSelM = DAG.getConstant(0x80, VT);
13050 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
13051 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
13053 SDValue CM1 = DAG.getConstant(0x0f, VT);
13054 SDValue CM2 = DAG.getConstant(0x3f, VT);
13056 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
13057 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
13058 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
13059 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
13060 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
13063 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
13064 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
13065 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
13067 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
13068 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
13069 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
13070 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
13071 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
13074 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
13075 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
13076 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
13078 // return VSELECT(r, r+r, a);
13079 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
13080 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
13084 // Decompose 256-bit shifts into smaller 128-bit shifts.
13085 if (VT.is256BitVector()) {
13086 unsigned NumElems = VT.getVectorNumElements();
13087 MVT EltVT = VT.getVectorElementType().getSimpleVT();
13088 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
13090 // Extract the two vectors
13091 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
13092 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
13094 // Recreate the shift amount vectors
13095 SDValue Amt1, Amt2;
13096 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
13097 // Constant shift amount
13098 SmallVector<SDValue, 4> Amt1Csts;
13099 SmallVector<SDValue, 4> Amt2Csts;
13100 for (unsigned i = 0; i != NumElems/2; ++i)
13101 Amt1Csts.push_back(Amt->getOperand(i));
13102 for (unsigned i = NumElems/2; i != NumElems; ++i)
13103 Amt2Csts.push_back(Amt->getOperand(i));
13105 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
13106 &Amt1Csts[0], NumElems/2);
13107 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
13108 &Amt2Csts[0], NumElems/2);
13110 // Variable shift amount
13111 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
13112 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
13115 // Issue new vector shifts for the smaller types
13116 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
13117 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
13119 // Concatenate the result back
13120 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
13126 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
13127 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
13128 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
13129 // looks for this combo and may remove the "setcc" instruction if the "setcc"
13130 // has only one use.
13131 SDNode *N = Op.getNode();
13132 SDValue LHS = N->getOperand(0);
13133 SDValue RHS = N->getOperand(1);
13134 unsigned BaseOp = 0;
13137 switch (Op.getOpcode()) {
13138 default: llvm_unreachable("Unknown ovf instruction!");
13140 // A subtract of one will be selected as a INC. Note that INC doesn't
13141 // set CF, so we can't do this for UADDO.
13142 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
13144 BaseOp = X86ISD::INC;
13145 Cond = X86::COND_O;
13148 BaseOp = X86ISD::ADD;
13149 Cond = X86::COND_O;
13152 BaseOp = X86ISD::ADD;
13153 Cond = X86::COND_B;
13156 // A subtract of one will be selected as a DEC. Note that DEC doesn't
13157 // set CF, so we can't do this for USUBO.
13158 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
13160 BaseOp = X86ISD::DEC;
13161 Cond = X86::COND_O;
13164 BaseOp = X86ISD::SUB;
13165 Cond = X86::COND_O;
13168 BaseOp = X86ISD::SUB;
13169 Cond = X86::COND_B;
13172 BaseOp = X86ISD::SMUL;
13173 Cond = X86::COND_O;
13175 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
13176 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
13178 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
13181 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13182 DAG.getConstant(X86::COND_O, MVT::i32),
13183 SDValue(Sum.getNode(), 2));
13185 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
13189 // Also sets EFLAGS.
13190 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
13191 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
13194 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
13195 DAG.getConstant(Cond, MVT::i32),
13196 SDValue(Sum.getNode(), 1));
13198 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
13201 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
13202 SelectionDAG &DAG) const {
13204 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
13205 EVT VT = Op.getValueType();
13207 if (!Subtarget->hasSSE2() || !VT.isVector())
13210 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
13211 ExtraVT.getScalarType().getSizeInBits();
13213 switch (VT.getSimpleVT().SimpleTy) {
13214 default: return SDValue();
13217 if (!Subtarget->hasFp256())
13219 if (!Subtarget->hasInt256()) {
13220 // needs to be split
13221 unsigned NumElems = VT.getVectorNumElements();
13223 // Extract the LHS vectors
13224 SDValue LHS = Op.getOperand(0);
13225 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
13226 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
13228 MVT EltVT = VT.getVectorElementType().getSimpleVT();
13229 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
13231 EVT ExtraEltVT = ExtraVT.getVectorElementType();
13232 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
13233 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
13235 SDValue Extra = DAG.getValueType(ExtraVT);
13237 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
13238 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
13240 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
13245 SDValue Op0 = Op.getOperand(0);
13246 SDValue Op00 = Op0.getOperand(0);
13248 // Hopefully, this VECTOR_SHUFFLE is just a VZEXT.
13249 if (Op0.getOpcode() == ISD::BITCAST &&
13250 Op00.getOpcode() == ISD::VECTOR_SHUFFLE) {
13251 // (sext (vzext x)) -> (vsext x)
13252 Tmp1 = LowerVectorIntExtend(Op00, Subtarget, DAG);
13253 if (Tmp1.getNode()) {
13254 EVT ExtraEltVT = ExtraVT.getVectorElementType();
13255 // This folding is only valid when the in-reg type is a vector of i8,
13257 if (ExtraEltVT == MVT::i8 || ExtraEltVT == MVT::i16 ||
13258 ExtraEltVT == MVT::i32) {
13259 SDValue Tmp1Op0 = Tmp1.getOperand(0);
13260 assert(Tmp1Op0.getOpcode() == X86ISD::VZEXT &&
13261 "This optimization is invalid without a VZEXT.");
13262 return DAG.getNode(X86ISD::VSEXT, dl, VT, Tmp1Op0.getOperand(0));
13268 // If the above didn't work, then just use Shift-Left + Shift-Right.
13269 Tmp1 = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Op0, BitsDiff,
13271 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, Tmp1, BitsDiff,
13277 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
13278 SelectionDAG &DAG) {
13280 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
13281 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
13282 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
13283 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
13285 // The only fence that needs an instruction is a sequentially-consistent
13286 // cross-thread fence.
13287 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
13288 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
13289 // no-sse2). There isn't any reason to disable it if the target processor
13291 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
13292 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
13294 SDValue Chain = Op.getOperand(0);
13295 SDValue Zero = DAG.getConstant(0, MVT::i32);
13297 DAG.getRegister(X86::ESP, MVT::i32), // Base
13298 DAG.getTargetConstant(1, MVT::i8), // Scale
13299 DAG.getRegister(0, MVT::i32), // Index
13300 DAG.getTargetConstant(0, MVT::i32), // Disp
13301 DAG.getRegister(0, MVT::i32), // Segment.
13305 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
13306 return SDValue(Res, 0);
13309 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
13310 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
13313 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
13314 SelectionDAG &DAG) {
13315 EVT T = Op.getValueType();
13319 switch(T.getSimpleVT().SimpleTy) {
13320 default: llvm_unreachable("Invalid value type!");
13321 case MVT::i8: Reg = X86::AL; size = 1; break;
13322 case MVT::i16: Reg = X86::AX; size = 2; break;
13323 case MVT::i32: Reg = X86::EAX; size = 4; break;
13325 assert(Subtarget->is64Bit() && "Node not type legal!");
13326 Reg = X86::RAX; size = 8;
13329 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
13330 Op.getOperand(2), SDValue());
13331 SDValue Ops[] = { cpIn.getValue(0),
13334 DAG.getTargetConstant(size, MVT::i8),
13335 cpIn.getValue(1) };
13336 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
13337 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
13338 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
13339 Ops, array_lengthof(Ops), T, MMO);
13341 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
13345 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
13346 SelectionDAG &DAG) {
13347 assert(Subtarget->is64Bit() && "Result not type legalized?");
13348 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
13349 SDValue TheChain = Op.getOperand(0);
13351 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
13352 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
13353 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
13355 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
13356 DAG.getConstant(32, MVT::i8));
13358 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
13361 return DAG.getMergeValues(Ops, array_lengthof(Ops), dl);
13364 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
13365 SelectionDAG &DAG) {
13366 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
13367 MVT DstVT = Op.getSimpleValueType();
13368 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
13369 Subtarget->hasMMX() && "Unexpected custom BITCAST");
13370 assert((DstVT == MVT::i64 ||
13371 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
13372 "Unexpected custom BITCAST");
13373 // i64 <=> MMX conversions are Legal.
13374 if (SrcVT==MVT::i64 && DstVT.isVector())
13376 if (DstVT==MVT::i64 && SrcVT.isVector())
13378 // MMX <=> MMX conversions are Legal.
13379 if (SrcVT.isVector() && DstVT.isVector())
13381 // All other conversions need to be expanded.
13385 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
13386 SDNode *Node = Op.getNode();
13388 EVT T = Node->getValueType(0);
13389 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
13390 DAG.getConstant(0, T), Node->getOperand(2));
13391 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
13392 cast<AtomicSDNode>(Node)->getMemoryVT(),
13393 Node->getOperand(0),
13394 Node->getOperand(1), negOp,
13395 cast<AtomicSDNode>(Node)->getSrcValue(),
13396 cast<AtomicSDNode>(Node)->getAlignment(),
13397 cast<AtomicSDNode>(Node)->getOrdering(),
13398 cast<AtomicSDNode>(Node)->getSynchScope());
13401 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
13402 SDNode *Node = Op.getNode();
13404 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
13406 // Convert seq_cst store -> xchg
13407 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
13408 // FIXME: On 32-bit, store -> fist or movq would be more efficient
13409 // (The only way to get a 16-byte store is cmpxchg16b)
13410 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
13411 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
13412 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
13413 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
13414 cast<AtomicSDNode>(Node)->getMemoryVT(),
13415 Node->getOperand(0),
13416 Node->getOperand(1), Node->getOperand(2),
13417 cast<AtomicSDNode>(Node)->getMemOperand(),
13418 cast<AtomicSDNode>(Node)->getOrdering(),
13419 cast<AtomicSDNode>(Node)->getSynchScope());
13420 return Swap.getValue(1);
13422 // Other atomic stores have a simple pattern.
13426 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
13427 EVT VT = Op.getNode()->getValueType(0);
13429 // Let legalize expand this if it isn't a legal type yet.
13430 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
13433 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
13436 bool ExtraOp = false;
13437 switch (Op.getOpcode()) {
13438 default: llvm_unreachable("Invalid code");
13439 case ISD::ADDC: Opc = X86ISD::ADD; break;
13440 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
13441 case ISD::SUBC: Opc = X86ISD::SUB; break;
13442 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
13446 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
13448 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
13449 Op.getOperand(1), Op.getOperand(2));
13452 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
13453 SelectionDAG &DAG) {
13454 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
13456 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
13457 // which returns the values as { float, float } (in XMM0) or
13458 // { double, double } (which is returned in XMM0, XMM1).
13460 SDValue Arg = Op.getOperand(0);
13461 EVT ArgVT = Arg.getValueType();
13462 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
13464 TargetLowering::ArgListTy Args;
13465 TargetLowering::ArgListEntry Entry;
13469 Entry.isSExt = false;
13470 Entry.isZExt = false;
13471 Args.push_back(Entry);
13473 bool isF64 = ArgVT == MVT::f64;
13474 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
13475 // the small struct {f32, f32} is returned in (eax, edx). For f64,
13476 // the results are returned via SRet in memory.
13477 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
13478 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13479 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
13481 Type *RetTy = isF64
13482 ? (Type*)StructType::get(ArgTy, ArgTy, NULL)
13483 : (Type*)VectorType::get(ArgTy, 4);
13485 CallLoweringInfo CLI(DAG.getEntryNode(), RetTy,
13486 false, false, false, false, 0,
13487 CallingConv::C, /*isTaillCall=*/false,
13488 /*doesNotRet=*/false, /*isReturnValueUsed*/true,
13489 Callee, Args, DAG, dl);
13490 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
13493 // Returned in xmm0 and xmm1.
13494 return CallResult.first;
13496 // Returned in bits 0:31 and 32:64 xmm0.
13497 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
13498 CallResult.first, DAG.getIntPtrConstant(0));
13499 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
13500 CallResult.first, DAG.getIntPtrConstant(1));
13501 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
13502 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
13505 /// LowerOperation - Provide custom lowering hooks for some operations.
13507 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
13508 switch (Op.getOpcode()) {
13509 default: llvm_unreachable("Should not custom lower this!");
13510 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
13511 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
13512 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op, Subtarget, DAG);
13513 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
13514 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
13515 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
13516 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
13517 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
13518 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
13519 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
13520 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
13521 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
13522 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
13523 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
13524 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
13525 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
13526 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
13527 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
13528 case ISD::SHL_PARTS:
13529 case ISD::SRA_PARTS:
13530 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
13531 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
13532 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
13533 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
13534 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
13535 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
13536 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
13537 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
13538 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
13539 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
13540 case ISD::FABS: return LowerFABS(Op, DAG);
13541 case ISD::FNEG: return LowerFNEG(Op, DAG);
13542 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
13543 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
13544 case ISD::SETCC: return LowerSETCC(Op, DAG);
13545 case ISD::SELECT: return LowerSELECT(Op, DAG);
13546 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
13547 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
13548 case ISD::VASTART: return LowerVASTART(Op, DAG);
13549 case ISD::VAARG: return LowerVAARG(Op, DAG);
13550 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
13551 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
13552 case ISD::INTRINSIC_VOID:
13553 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
13554 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
13555 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
13556 case ISD::FRAME_TO_ARGS_OFFSET:
13557 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
13558 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
13559 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
13560 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
13561 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
13562 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
13563 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
13564 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
13565 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
13566 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
13567 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
13568 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
13571 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
13577 case ISD::UMULO: return LowerXALUO(Op, DAG);
13578 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
13579 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
13583 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
13584 case ISD::ADD: return LowerADD(Op, DAG);
13585 case ISD::SUB: return LowerSUB(Op, DAG);
13586 case ISD::SDIV: return LowerSDIV(Op, DAG);
13587 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
13591 static void ReplaceATOMIC_LOAD(SDNode *Node,
13592 SmallVectorImpl<SDValue> &Results,
13593 SelectionDAG &DAG) {
13595 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
13597 // Convert wide load -> cmpxchg8b/cmpxchg16b
13598 // FIXME: On 32-bit, load -> fild or movq would be more efficient
13599 // (The only way to get a 16-byte load is cmpxchg16b)
13600 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
13601 SDValue Zero = DAG.getConstant(0, VT);
13602 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT,
13603 Node->getOperand(0),
13604 Node->getOperand(1), Zero, Zero,
13605 cast<AtomicSDNode>(Node)->getMemOperand(),
13606 cast<AtomicSDNode>(Node)->getOrdering(),
13607 cast<AtomicSDNode>(Node)->getSynchScope());
13608 Results.push_back(Swap.getValue(0));
13609 Results.push_back(Swap.getValue(1));
13613 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
13614 SelectionDAG &DAG, unsigned NewOp) {
13616 assert (Node->getValueType(0) == MVT::i64 &&
13617 "Only know how to expand i64 atomics");
13619 SDValue Chain = Node->getOperand(0);
13620 SDValue In1 = Node->getOperand(1);
13621 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
13622 Node->getOperand(2), DAG.getIntPtrConstant(0));
13623 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
13624 Node->getOperand(2), DAG.getIntPtrConstant(1));
13625 SDValue Ops[] = { Chain, In1, In2L, In2H };
13626 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
13628 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, array_lengthof(Ops), MVT::i64,
13629 cast<MemSDNode>(Node)->getMemOperand());
13630 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
13631 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
13632 Results.push_back(Result.getValue(2));
13635 /// ReplaceNodeResults - Replace a node with an illegal result type
13636 /// with a new node built out of custom code.
13637 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
13638 SmallVectorImpl<SDValue>&Results,
13639 SelectionDAG &DAG) const {
13641 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13642 switch (N->getOpcode()) {
13644 llvm_unreachable("Do not know how to custom type legalize this operation!");
13645 case ISD::SIGN_EXTEND_INREG:
13650 // We don't want to expand or promote these.
13652 case ISD::FP_TO_SINT:
13653 case ISD::FP_TO_UINT: {
13654 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
13656 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
13659 std::pair<SDValue,SDValue> Vals =
13660 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
13661 SDValue FIST = Vals.first, StackSlot = Vals.second;
13662 if (FIST.getNode() != 0) {
13663 EVT VT = N->getValueType(0);
13664 // Return a load from the stack slot.
13665 if (StackSlot.getNode() != 0)
13666 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
13667 MachinePointerInfo(),
13668 false, false, false, 0));
13670 Results.push_back(FIST);
13674 case ISD::UINT_TO_FP: {
13675 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
13676 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
13677 N->getValueType(0) != MVT::v2f32)
13679 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
13681 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
13683 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
13684 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
13685 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
13686 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
13687 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
13688 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
13691 case ISD::FP_ROUND: {
13692 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
13694 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
13695 Results.push_back(V);
13698 case ISD::READCYCLECOUNTER: {
13699 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
13700 SDValue TheChain = N->getOperand(0);
13701 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
13702 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
13704 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
13706 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
13707 SDValue Ops[] = { eax, edx };
13708 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops,
13709 array_lengthof(Ops)));
13710 Results.push_back(edx.getValue(1));
13713 case ISD::ATOMIC_CMP_SWAP: {
13714 EVT T = N->getValueType(0);
13715 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
13716 bool Regs64bit = T == MVT::i128;
13717 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
13718 SDValue cpInL, cpInH;
13719 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
13720 DAG.getConstant(0, HalfT));
13721 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
13722 DAG.getConstant(1, HalfT));
13723 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
13724 Regs64bit ? X86::RAX : X86::EAX,
13726 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
13727 Regs64bit ? X86::RDX : X86::EDX,
13728 cpInH, cpInL.getValue(1));
13729 SDValue swapInL, swapInH;
13730 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
13731 DAG.getConstant(0, HalfT));
13732 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
13733 DAG.getConstant(1, HalfT));
13734 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
13735 Regs64bit ? X86::RBX : X86::EBX,
13736 swapInL, cpInH.getValue(1));
13737 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
13738 Regs64bit ? X86::RCX : X86::ECX,
13739 swapInH, swapInL.getValue(1));
13740 SDValue Ops[] = { swapInH.getValue(0),
13742 swapInH.getValue(1) };
13743 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
13744 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
13745 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
13746 X86ISD::LCMPXCHG8_DAG;
13747 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys,
13748 Ops, array_lengthof(Ops), T, MMO);
13749 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
13750 Regs64bit ? X86::RAX : X86::EAX,
13751 HalfT, Result.getValue(1));
13752 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
13753 Regs64bit ? X86::RDX : X86::EDX,
13754 HalfT, cpOutL.getValue(2));
13755 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
13756 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2));
13757 Results.push_back(cpOutH.getValue(1));
13760 case ISD::ATOMIC_LOAD_ADD:
13761 case ISD::ATOMIC_LOAD_AND:
13762 case ISD::ATOMIC_LOAD_NAND:
13763 case ISD::ATOMIC_LOAD_OR:
13764 case ISD::ATOMIC_LOAD_SUB:
13765 case ISD::ATOMIC_LOAD_XOR:
13766 case ISD::ATOMIC_LOAD_MAX:
13767 case ISD::ATOMIC_LOAD_MIN:
13768 case ISD::ATOMIC_LOAD_UMAX:
13769 case ISD::ATOMIC_LOAD_UMIN:
13770 case ISD::ATOMIC_SWAP: {
13772 switch (N->getOpcode()) {
13773 default: llvm_unreachable("Unexpected opcode");
13774 case ISD::ATOMIC_LOAD_ADD:
13775 Opc = X86ISD::ATOMADD64_DAG;
13777 case ISD::ATOMIC_LOAD_AND:
13778 Opc = X86ISD::ATOMAND64_DAG;
13780 case ISD::ATOMIC_LOAD_NAND:
13781 Opc = X86ISD::ATOMNAND64_DAG;
13783 case ISD::ATOMIC_LOAD_OR:
13784 Opc = X86ISD::ATOMOR64_DAG;
13786 case ISD::ATOMIC_LOAD_SUB:
13787 Opc = X86ISD::ATOMSUB64_DAG;
13789 case ISD::ATOMIC_LOAD_XOR:
13790 Opc = X86ISD::ATOMXOR64_DAG;
13792 case ISD::ATOMIC_LOAD_MAX:
13793 Opc = X86ISD::ATOMMAX64_DAG;
13795 case ISD::ATOMIC_LOAD_MIN:
13796 Opc = X86ISD::ATOMMIN64_DAG;
13798 case ISD::ATOMIC_LOAD_UMAX:
13799 Opc = X86ISD::ATOMUMAX64_DAG;
13801 case ISD::ATOMIC_LOAD_UMIN:
13802 Opc = X86ISD::ATOMUMIN64_DAG;
13804 case ISD::ATOMIC_SWAP:
13805 Opc = X86ISD::ATOMSWAP64_DAG;
13808 ReplaceATOMIC_BINARY_64(N, Results, DAG, Opc);
13811 case ISD::ATOMIC_LOAD:
13812 ReplaceATOMIC_LOAD(N, Results, DAG);
13816 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
13818 default: return NULL;
13819 case X86ISD::BSF: return "X86ISD::BSF";
13820 case X86ISD::BSR: return "X86ISD::BSR";
13821 case X86ISD::SHLD: return "X86ISD::SHLD";
13822 case X86ISD::SHRD: return "X86ISD::SHRD";
13823 case X86ISD::FAND: return "X86ISD::FAND";
13824 case X86ISD::FANDN: return "X86ISD::FANDN";
13825 case X86ISD::FOR: return "X86ISD::FOR";
13826 case X86ISD::FXOR: return "X86ISD::FXOR";
13827 case X86ISD::FSRL: return "X86ISD::FSRL";
13828 case X86ISD::FILD: return "X86ISD::FILD";
13829 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
13830 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
13831 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
13832 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
13833 case X86ISD::FLD: return "X86ISD::FLD";
13834 case X86ISD::FST: return "X86ISD::FST";
13835 case X86ISD::CALL: return "X86ISD::CALL";
13836 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
13837 case X86ISD::BT: return "X86ISD::BT";
13838 case X86ISD::CMP: return "X86ISD::CMP";
13839 case X86ISD::COMI: return "X86ISD::COMI";
13840 case X86ISD::UCOMI: return "X86ISD::UCOMI";
13841 case X86ISD::CMPM: return "X86ISD::CMPM";
13842 case X86ISD::CMPMU: return "X86ISD::CMPMU";
13843 case X86ISD::SETCC: return "X86ISD::SETCC";
13844 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
13845 case X86ISD::FSETCC: return "X86ISD::FSETCC";
13846 case X86ISD::CMOV: return "X86ISD::CMOV";
13847 case X86ISD::BRCOND: return "X86ISD::BRCOND";
13848 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
13849 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
13850 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
13851 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
13852 case X86ISD::Wrapper: return "X86ISD::Wrapper";
13853 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
13854 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
13855 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
13856 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
13857 case X86ISD::PINSRB: return "X86ISD::PINSRB";
13858 case X86ISD::PINSRW: return "X86ISD::PINSRW";
13859 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
13860 case X86ISD::ANDNP: return "X86ISD::ANDNP";
13861 case X86ISD::PSIGN: return "X86ISD::PSIGN";
13862 case X86ISD::BLENDV: return "X86ISD::BLENDV";
13863 case X86ISD::BLENDI: return "X86ISD::BLENDI";
13864 case X86ISD::SUBUS: return "X86ISD::SUBUS";
13865 case X86ISD::HADD: return "X86ISD::HADD";
13866 case X86ISD::HSUB: return "X86ISD::HSUB";
13867 case X86ISD::FHADD: return "X86ISD::FHADD";
13868 case X86ISD::FHSUB: return "X86ISD::FHSUB";
13869 case X86ISD::UMAX: return "X86ISD::UMAX";
13870 case X86ISD::UMIN: return "X86ISD::UMIN";
13871 case X86ISD::SMAX: return "X86ISD::SMAX";
13872 case X86ISD::SMIN: return "X86ISD::SMIN";
13873 case X86ISD::FMAX: return "X86ISD::FMAX";
13874 case X86ISD::FMIN: return "X86ISD::FMIN";
13875 case X86ISD::FMAXC: return "X86ISD::FMAXC";
13876 case X86ISD::FMINC: return "X86ISD::FMINC";
13877 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
13878 case X86ISD::FRCP: return "X86ISD::FRCP";
13879 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
13880 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
13881 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
13882 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
13883 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
13884 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
13885 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
13886 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
13887 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
13888 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
13889 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
13890 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
13891 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
13892 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
13893 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
13894 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
13895 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
13896 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
13897 case X86ISD::VSEXT_MOVL: return "X86ISD::VSEXT_MOVL";
13898 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
13899 case X86ISD::VZEXT: return "X86ISD::VZEXT";
13900 case X86ISD::VSEXT: return "X86ISD::VSEXT";
13901 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
13902 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
13903 case X86ISD::VINSERT: return "X86ISD::VINSERT";
13904 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
13905 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
13906 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
13907 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
13908 case X86ISD::VSHL: return "X86ISD::VSHL";
13909 case X86ISD::VSRL: return "X86ISD::VSRL";
13910 case X86ISD::VSRA: return "X86ISD::VSRA";
13911 case X86ISD::VSHLI: return "X86ISD::VSHLI";
13912 case X86ISD::VSRLI: return "X86ISD::VSRLI";
13913 case X86ISD::VSRAI: return "X86ISD::VSRAI";
13914 case X86ISD::CMPP: return "X86ISD::CMPP";
13915 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
13916 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
13917 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
13918 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
13919 case X86ISD::ADD: return "X86ISD::ADD";
13920 case X86ISD::SUB: return "X86ISD::SUB";
13921 case X86ISD::ADC: return "X86ISD::ADC";
13922 case X86ISD::SBB: return "X86ISD::SBB";
13923 case X86ISD::SMUL: return "X86ISD::SMUL";
13924 case X86ISD::UMUL: return "X86ISD::UMUL";
13925 case X86ISD::INC: return "X86ISD::INC";
13926 case X86ISD::DEC: return "X86ISD::DEC";
13927 case X86ISD::OR: return "X86ISD::OR";
13928 case X86ISD::XOR: return "X86ISD::XOR";
13929 case X86ISD::AND: return "X86ISD::AND";
13930 case X86ISD::BLSI: return "X86ISD::BLSI";
13931 case X86ISD::BLSMSK: return "X86ISD::BLSMSK";
13932 case X86ISD::BLSR: return "X86ISD::BLSR";
13933 case X86ISD::BZHI: return "X86ISD::BZHI";
13934 case X86ISD::BEXTR: return "X86ISD::BEXTR";
13935 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
13936 case X86ISD::PTEST: return "X86ISD::PTEST";
13937 case X86ISD::TESTP: return "X86ISD::TESTP";
13938 case X86ISD::TESTM: return "X86ISD::TESTM";
13939 case X86ISD::KORTEST: return "X86ISD::KORTEST";
13940 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
13941 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
13942 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
13943 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
13944 case X86ISD::SHUFP: return "X86ISD::SHUFP";
13945 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
13946 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
13947 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
13948 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
13949 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
13950 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
13951 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
13952 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
13953 case X86ISD::MOVSD: return "X86ISD::MOVSD";
13954 case X86ISD::MOVSS: return "X86ISD::MOVSS";
13955 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
13956 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
13957 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
13958 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
13959 case X86ISD::VPERMILP: return "X86ISD::VPERMILP";
13960 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
13961 case X86ISD::VPERMV: return "X86ISD::VPERMV";
13962 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
13963 case X86ISD::VPERMI: return "X86ISD::VPERMI";
13964 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
13965 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
13966 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
13967 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
13968 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
13969 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
13970 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
13971 case X86ISD::SAHF: return "X86ISD::SAHF";
13972 case X86ISD::RDRAND: return "X86ISD::RDRAND";
13973 case X86ISD::RDSEED: return "X86ISD::RDSEED";
13974 case X86ISD::FMADD: return "X86ISD::FMADD";
13975 case X86ISD::FMSUB: return "X86ISD::FMSUB";
13976 case X86ISD::FNMADD: return "X86ISD::FNMADD";
13977 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
13978 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
13979 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
13980 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
13981 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
13982 case X86ISD::XTEST: return "X86ISD::XTEST";
13986 // isLegalAddressingMode - Return true if the addressing mode represented
13987 // by AM is legal for this target, for a load/store of the specified type.
13988 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
13990 // X86 supports extremely general addressing modes.
13991 CodeModel::Model M = getTargetMachine().getCodeModel();
13992 Reloc::Model R = getTargetMachine().getRelocationModel();
13994 // X86 allows a sign-extended 32-bit immediate field as a displacement.
13995 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
14000 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
14002 // If a reference to this global requires an extra load, we can't fold it.
14003 if (isGlobalStubReference(GVFlags))
14006 // If BaseGV requires a register for the PIC base, we cannot also have a
14007 // BaseReg specified.
14008 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
14011 // If lower 4G is not available, then we must use rip-relative addressing.
14012 if ((M != CodeModel::Small || R != Reloc::Static) &&
14013 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
14017 switch (AM.Scale) {
14023 // These scales always work.
14028 // These scales are formed with basereg+scalereg. Only accept if there is
14033 default: // Other stuff never works.
14040 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
14041 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
14043 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
14044 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
14045 return NumBits1 > NumBits2;
14048 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
14049 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
14052 if (!isTypeLegal(EVT::getEVT(Ty1)))
14055 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
14057 // Assuming the caller doesn't have a zeroext or signext return parameter,
14058 // truncation all the way down to i1 is valid.
14062 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
14063 return isInt<32>(Imm);
14066 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
14067 // Can also use sub to handle negated immediates.
14068 return isInt<32>(Imm);
14071 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
14072 if (!VT1.isInteger() || !VT2.isInteger())
14074 unsigned NumBits1 = VT1.getSizeInBits();
14075 unsigned NumBits2 = VT2.getSizeInBits();
14076 return NumBits1 > NumBits2;
14079 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
14080 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
14081 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
14084 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
14085 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
14086 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
14089 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
14090 EVT VT1 = Val.getValueType();
14091 if (isZExtFree(VT1, VT2))
14094 if (Val.getOpcode() != ISD::LOAD)
14097 if (!VT1.isSimple() || !VT1.isInteger() ||
14098 !VT2.isSimple() || !VT2.isInteger())
14101 switch (VT1.getSimpleVT().SimpleTy) {
14106 // X86 has 8, 16, and 32-bit zero-extending loads.
14114 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
14115 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
14118 VT = VT.getScalarType();
14120 if (!VT.isSimple())
14123 switch (VT.getSimpleVT().SimpleTy) {
14134 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
14135 // i16 instructions are longer (0x66 prefix) and potentially slower.
14136 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
14139 /// isShuffleMaskLegal - Targets can use this to indicate that they only
14140 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
14141 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
14142 /// are assumed to be legal.
14144 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
14146 if (!VT.isSimple())
14149 MVT SVT = VT.getSimpleVT();
14151 // Very little shuffling can be done for 64-bit vectors right now.
14152 if (VT.getSizeInBits() == 64)
14155 // FIXME: pshufb, blends, shifts.
14156 return (SVT.getVectorNumElements() == 2 ||
14157 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
14158 isMOVLMask(M, SVT) ||
14159 isSHUFPMask(M, SVT) ||
14160 isPSHUFDMask(M, SVT) ||
14161 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
14162 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
14163 isPALIGNRMask(M, SVT, Subtarget) ||
14164 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
14165 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
14166 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
14167 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()));
14171 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
14173 if (!VT.isSimple())
14176 MVT SVT = VT.getSimpleVT();
14177 unsigned NumElts = SVT.getVectorNumElements();
14178 // FIXME: This collection of masks seems suspect.
14181 if (NumElts == 4 && SVT.is128BitVector()) {
14182 return (isMOVLMask(Mask, SVT) ||
14183 isCommutedMOVLMask(Mask, SVT, true) ||
14184 isSHUFPMask(Mask, SVT) ||
14185 isSHUFPMask(Mask, SVT, /* Commuted */ true));
14190 //===----------------------------------------------------------------------===//
14191 // X86 Scheduler Hooks
14192 //===----------------------------------------------------------------------===//
14194 /// Utility function to emit xbegin specifying the start of an RTM region.
14195 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
14196 const TargetInstrInfo *TII) {
14197 DebugLoc DL = MI->getDebugLoc();
14199 const BasicBlock *BB = MBB->getBasicBlock();
14200 MachineFunction::iterator I = MBB;
14203 // For the v = xbegin(), we generate
14214 MachineBasicBlock *thisMBB = MBB;
14215 MachineFunction *MF = MBB->getParent();
14216 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
14217 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
14218 MF->insert(I, mainMBB);
14219 MF->insert(I, sinkMBB);
14221 // Transfer the remainder of BB and its successor edges to sinkMBB.
14222 sinkMBB->splice(sinkMBB->begin(), MBB,
14223 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
14224 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
14228 // # fallthrough to mainMBB
14229 // # abortion to sinkMBB
14230 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
14231 thisMBB->addSuccessor(mainMBB);
14232 thisMBB->addSuccessor(sinkMBB);
14236 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
14237 mainMBB->addSuccessor(sinkMBB);
14240 // EAX is live into the sinkMBB
14241 sinkMBB->addLiveIn(X86::EAX);
14242 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
14243 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
14246 MI->eraseFromParent();
14250 // Get CMPXCHG opcode for the specified data type.
14251 static unsigned getCmpXChgOpcode(EVT VT) {
14252 switch (VT.getSimpleVT().SimpleTy) {
14253 case MVT::i8: return X86::LCMPXCHG8;
14254 case MVT::i16: return X86::LCMPXCHG16;
14255 case MVT::i32: return X86::LCMPXCHG32;
14256 case MVT::i64: return X86::LCMPXCHG64;
14260 llvm_unreachable("Invalid operand size!");
14263 // Get LOAD opcode for the specified data type.
14264 static unsigned getLoadOpcode(EVT VT) {
14265 switch (VT.getSimpleVT().SimpleTy) {
14266 case MVT::i8: return X86::MOV8rm;
14267 case MVT::i16: return X86::MOV16rm;
14268 case MVT::i32: return X86::MOV32rm;
14269 case MVT::i64: return X86::MOV64rm;
14273 llvm_unreachable("Invalid operand size!");
14276 // Get opcode of the non-atomic one from the specified atomic instruction.
14277 static unsigned getNonAtomicOpcode(unsigned Opc) {
14279 case X86::ATOMAND8: return X86::AND8rr;
14280 case X86::ATOMAND16: return X86::AND16rr;
14281 case X86::ATOMAND32: return X86::AND32rr;
14282 case X86::ATOMAND64: return X86::AND64rr;
14283 case X86::ATOMOR8: return X86::OR8rr;
14284 case X86::ATOMOR16: return X86::OR16rr;
14285 case X86::ATOMOR32: return X86::OR32rr;
14286 case X86::ATOMOR64: return X86::OR64rr;
14287 case X86::ATOMXOR8: return X86::XOR8rr;
14288 case X86::ATOMXOR16: return X86::XOR16rr;
14289 case X86::ATOMXOR32: return X86::XOR32rr;
14290 case X86::ATOMXOR64: return X86::XOR64rr;
14292 llvm_unreachable("Unhandled atomic-load-op opcode!");
14295 // Get opcode of the non-atomic one from the specified atomic instruction with
14297 static unsigned getNonAtomicOpcodeWithExtraOpc(unsigned Opc,
14298 unsigned &ExtraOpc) {
14300 case X86::ATOMNAND8: ExtraOpc = X86::NOT8r; return X86::AND8rr;
14301 case X86::ATOMNAND16: ExtraOpc = X86::NOT16r; return X86::AND16rr;
14302 case X86::ATOMNAND32: ExtraOpc = X86::NOT32r; return X86::AND32rr;
14303 case X86::ATOMNAND64: ExtraOpc = X86::NOT64r; return X86::AND64rr;
14304 case X86::ATOMMAX8: ExtraOpc = X86::CMP8rr; return X86::CMOVL32rr;
14305 case X86::ATOMMAX16: ExtraOpc = X86::CMP16rr; return X86::CMOVL16rr;
14306 case X86::ATOMMAX32: ExtraOpc = X86::CMP32rr; return X86::CMOVL32rr;
14307 case X86::ATOMMAX64: ExtraOpc = X86::CMP64rr; return X86::CMOVL64rr;
14308 case X86::ATOMMIN8: ExtraOpc = X86::CMP8rr; return X86::CMOVG32rr;
14309 case X86::ATOMMIN16: ExtraOpc = X86::CMP16rr; return X86::CMOVG16rr;
14310 case X86::ATOMMIN32: ExtraOpc = X86::CMP32rr; return X86::CMOVG32rr;
14311 case X86::ATOMMIN64: ExtraOpc = X86::CMP64rr; return X86::CMOVG64rr;
14312 case X86::ATOMUMAX8: ExtraOpc = X86::CMP8rr; return X86::CMOVB32rr;
14313 case X86::ATOMUMAX16: ExtraOpc = X86::CMP16rr; return X86::CMOVB16rr;
14314 case X86::ATOMUMAX32: ExtraOpc = X86::CMP32rr; return X86::CMOVB32rr;
14315 case X86::ATOMUMAX64: ExtraOpc = X86::CMP64rr; return X86::CMOVB64rr;
14316 case X86::ATOMUMIN8: ExtraOpc = X86::CMP8rr; return X86::CMOVA32rr;
14317 case X86::ATOMUMIN16: ExtraOpc = X86::CMP16rr; return X86::CMOVA16rr;
14318 case X86::ATOMUMIN32: ExtraOpc = X86::CMP32rr; return X86::CMOVA32rr;
14319 case X86::ATOMUMIN64: ExtraOpc = X86::CMP64rr; return X86::CMOVA64rr;
14321 llvm_unreachable("Unhandled atomic-load-op opcode!");
14324 // Get opcode of the non-atomic one from the specified atomic instruction for
14325 // 64-bit data type on 32-bit target.
14326 static unsigned getNonAtomic6432Opcode(unsigned Opc, unsigned &HiOpc) {
14328 case X86::ATOMAND6432: HiOpc = X86::AND32rr; return X86::AND32rr;
14329 case X86::ATOMOR6432: HiOpc = X86::OR32rr; return X86::OR32rr;
14330 case X86::ATOMXOR6432: HiOpc = X86::XOR32rr; return X86::XOR32rr;
14331 case X86::ATOMADD6432: HiOpc = X86::ADC32rr; return X86::ADD32rr;
14332 case X86::ATOMSUB6432: HiOpc = X86::SBB32rr; return X86::SUB32rr;
14333 case X86::ATOMSWAP6432: HiOpc = X86::MOV32rr; return X86::MOV32rr;
14334 case X86::ATOMMAX6432: HiOpc = X86::SETLr; return X86::SETLr;
14335 case X86::ATOMMIN6432: HiOpc = X86::SETGr; return X86::SETGr;
14336 case X86::ATOMUMAX6432: HiOpc = X86::SETBr; return X86::SETBr;
14337 case X86::ATOMUMIN6432: HiOpc = X86::SETAr; return X86::SETAr;
14339 llvm_unreachable("Unhandled atomic-load-op opcode!");
14342 // Get opcode of the non-atomic one from the specified atomic instruction for
14343 // 64-bit data type on 32-bit target with extra opcode.
14344 static unsigned getNonAtomic6432OpcodeWithExtraOpc(unsigned Opc,
14346 unsigned &ExtraOpc) {
14348 case X86::ATOMNAND6432:
14349 ExtraOpc = X86::NOT32r;
14350 HiOpc = X86::AND32rr;
14351 return X86::AND32rr;
14353 llvm_unreachable("Unhandled atomic-load-op opcode!");
14356 // Get pseudo CMOV opcode from the specified data type.
14357 static unsigned getPseudoCMOVOpc(EVT VT) {
14358 switch (VT.getSimpleVT().SimpleTy) {
14359 case MVT::i8: return X86::CMOV_GR8;
14360 case MVT::i16: return X86::CMOV_GR16;
14361 case MVT::i32: return X86::CMOV_GR32;
14365 llvm_unreachable("Unknown CMOV opcode!");
14368 // EmitAtomicLoadArith - emit the code sequence for pseudo atomic instructions.
14369 // They will be translated into a spin-loop or compare-exchange loop from
14372 // dst = atomic-fetch-op MI.addr, MI.val
14378 // t1 = LOAD MI.addr
14380 // t4 = phi(t1, t3 / loop)
14381 // t2 = OP MI.val, t4
14383 // LCMPXCHG [MI.addr], t2, [EAX is implicitly used & defined]
14389 MachineBasicBlock *
14390 X86TargetLowering::EmitAtomicLoadArith(MachineInstr *MI,
14391 MachineBasicBlock *MBB) const {
14392 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14393 DebugLoc DL = MI->getDebugLoc();
14395 MachineFunction *MF = MBB->getParent();
14396 MachineRegisterInfo &MRI = MF->getRegInfo();
14398 const BasicBlock *BB = MBB->getBasicBlock();
14399 MachineFunction::iterator I = MBB;
14402 assert(MI->getNumOperands() <= X86::AddrNumOperands + 4 &&
14403 "Unexpected number of operands");
14405 assert(MI->hasOneMemOperand() &&
14406 "Expected atomic-load-op to have one memoperand");
14408 // Memory Reference
14409 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
14410 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
14412 unsigned DstReg, SrcReg;
14413 unsigned MemOpndSlot;
14415 unsigned CurOp = 0;
14417 DstReg = MI->getOperand(CurOp++).getReg();
14418 MemOpndSlot = CurOp;
14419 CurOp += X86::AddrNumOperands;
14420 SrcReg = MI->getOperand(CurOp++).getReg();
14422 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
14423 MVT::SimpleValueType VT = *RC->vt_begin();
14424 unsigned t1 = MRI.createVirtualRegister(RC);
14425 unsigned t2 = MRI.createVirtualRegister(RC);
14426 unsigned t3 = MRI.createVirtualRegister(RC);
14427 unsigned t4 = MRI.createVirtualRegister(RC);
14428 unsigned PhyReg = getX86SubSuperRegister(X86::EAX, VT);
14430 unsigned LCMPXCHGOpc = getCmpXChgOpcode(VT);
14431 unsigned LOADOpc = getLoadOpcode(VT);
14433 // For the atomic load-arith operator, we generate
14436 // t1 = LOAD [MI.addr]
14438 // t4 = phi(t1 / thisMBB, t3 / mainMBB)
14439 // t1 = OP MI.val, EAX
14441 // LCMPXCHG [MI.addr], t1, [EAX is implicitly used & defined]
14447 MachineBasicBlock *thisMBB = MBB;
14448 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
14449 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
14450 MF->insert(I, mainMBB);
14451 MF->insert(I, sinkMBB);
14453 MachineInstrBuilder MIB;
14455 // Transfer the remainder of BB and its successor edges to sinkMBB.
14456 sinkMBB->splice(sinkMBB->begin(), MBB,
14457 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
14458 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
14461 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), t1);
14462 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14463 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14465 NewMO.setIsKill(false);
14466 MIB.addOperand(NewMO);
14468 for (MachineInstr::mmo_iterator MMOI = MMOBegin; MMOI != MMOEnd; ++MMOI) {
14469 unsigned flags = (*MMOI)->getFlags();
14470 flags = (flags & ~MachineMemOperand::MOStore) | MachineMemOperand::MOLoad;
14471 MachineMemOperand *MMO =
14472 MF->getMachineMemOperand((*MMOI)->getPointerInfo(), flags,
14473 (*MMOI)->getSize(),
14474 (*MMOI)->getBaseAlignment(),
14475 (*MMOI)->getTBAAInfo(),
14476 (*MMOI)->getRanges());
14477 MIB.addMemOperand(MMO);
14480 thisMBB->addSuccessor(mainMBB);
14483 MachineBasicBlock *origMainMBB = mainMBB;
14486 MachineInstr *Phi = BuildMI(mainMBB, DL, TII->get(X86::PHI), t4)
14487 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(mainMBB);
14489 unsigned Opc = MI->getOpcode();
14492 llvm_unreachable("Unhandled atomic-load-op opcode!");
14493 case X86::ATOMAND8:
14494 case X86::ATOMAND16:
14495 case X86::ATOMAND32:
14496 case X86::ATOMAND64:
14498 case X86::ATOMOR16:
14499 case X86::ATOMOR32:
14500 case X86::ATOMOR64:
14501 case X86::ATOMXOR8:
14502 case X86::ATOMXOR16:
14503 case X86::ATOMXOR32:
14504 case X86::ATOMXOR64: {
14505 unsigned ARITHOpc = getNonAtomicOpcode(Opc);
14506 BuildMI(mainMBB, DL, TII->get(ARITHOpc), t2).addReg(SrcReg)
14510 case X86::ATOMNAND8:
14511 case X86::ATOMNAND16:
14512 case X86::ATOMNAND32:
14513 case X86::ATOMNAND64: {
14514 unsigned Tmp = MRI.createVirtualRegister(RC);
14516 unsigned ANDOpc = getNonAtomicOpcodeWithExtraOpc(Opc, NOTOpc);
14517 BuildMI(mainMBB, DL, TII->get(ANDOpc), Tmp).addReg(SrcReg)
14519 BuildMI(mainMBB, DL, TII->get(NOTOpc), t2).addReg(Tmp);
14522 case X86::ATOMMAX8:
14523 case X86::ATOMMAX16:
14524 case X86::ATOMMAX32:
14525 case X86::ATOMMAX64:
14526 case X86::ATOMMIN8:
14527 case X86::ATOMMIN16:
14528 case X86::ATOMMIN32:
14529 case X86::ATOMMIN64:
14530 case X86::ATOMUMAX8:
14531 case X86::ATOMUMAX16:
14532 case X86::ATOMUMAX32:
14533 case X86::ATOMUMAX64:
14534 case X86::ATOMUMIN8:
14535 case X86::ATOMUMIN16:
14536 case X86::ATOMUMIN32:
14537 case X86::ATOMUMIN64: {
14539 unsigned CMOVOpc = getNonAtomicOpcodeWithExtraOpc(Opc, CMPOpc);
14541 BuildMI(mainMBB, DL, TII->get(CMPOpc))
14545 if (Subtarget->hasCMov()) {
14546 if (VT != MVT::i8) {
14548 BuildMI(mainMBB, DL, TII->get(CMOVOpc), t2)
14552 // Promote i8 to i32 to use CMOV32
14553 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
14554 const TargetRegisterClass *RC32 =
14555 TRI->getSubClassWithSubReg(getRegClassFor(MVT::i32), X86::sub_8bit);
14556 unsigned SrcReg32 = MRI.createVirtualRegister(RC32);
14557 unsigned AccReg32 = MRI.createVirtualRegister(RC32);
14558 unsigned Tmp = MRI.createVirtualRegister(RC32);
14560 unsigned Undef = MRI.createVirtualRegister(RC32);
14561 BuildMI(mainMBB, DL, TII->get(TargetOpcode::IMPLICIT_DEF), Undef);
14563 BuildMI(mainMBB, DL, TII->get(TargetOpcode::INSERT_SUBREG), SrcReg32)
14566 .addImm(X86::sub_8bit);
14567 BuildMI(mainMBB, DL, TII->get(TargetOpcode::INSERT_SUBREG), AccReg32)
14570 .addImm(X86::sub_8bit);
14572 BuildMI(mainMBB, DL, TII->get(CMOVOpc), Tmp)
14576 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t2)
14577 .addReg(Tmp, 0, X86::sub_8bit);
14580 // Use pseudo select and lower them.
14581 assert((VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32) &&
14582 "Invalid atomic-load-op transformation!");
14583 unsigned SelOpc = getPseudoCMOVOpc(VT);
14584 X86::CondCode CC = X86::getCondFromCMovOpc(CMOVOpc);
14585 assert(CC != X86::COND_INVALID && "Invalid atomic-load-op transformation!");
14586 MIB = BuildMI(mainMBB, DL, TII->get(SelOpc), t2)
14587 .addReg(SrcReg).addReg(t4)
14589 mainMBB = EmitLoweredSelect(MIB, mainMBB);
14590 // Replace the original PHI node as mainMBB is changed after CMOV
14592 BuildMI(*origMainMBB, Phi, DL, TII->get(X86::PHI), t4)
14593 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(mainMBB);
14594 Phi->eraseFromParent();
14600 // Copy PhyReg back from virtual register.
14601 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), PhyReg)
14604 MIB = BuildMI(mainMBB, DL, TII->get(LCMPXCHGOpc));
14605 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14606 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14608 NewMO.setIsKill(false);
14609 MIB.addOperand(NewMO);
14612 MIB.setMemRefs(MMOBegin, MMOEnd);
14614 // Copy PhyReg back to virtual register.
14615 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t3)
14618 BuildMI(mainMBB, DL, TII->get(X86::JNE_4)).addMBB(origMainMBB);
14620 mainMBB->addSuccessor(origMainMBB);
14621 mainMBB->addSuccessor(sinkMBB);
14624 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
14625 TII->get(TargetOpcode::COPY), DstReg)
14628 MI->eraseFromParent();
14632 // EmitAtomicLoadArith6432 - emit the code sequence for pseudo atomic
14633 // instructions. They will be translated into a spin-loop or compare-exchange
14637 // dst = atomic-fetch-op MI.addr, MI.val
14643 // t1L = LOAD [MI.addr + 0]
14644 // t1H = LOAD [MI.addr + 4]
14646 // t4L = phi(t1L, t3L / loop)
14647 // t4H = phi(t1H, t3H / loop)
14648 // t2L = OP MI.val.lo, t4L
14649 // t2H = OP MI.val.hi, t4H
14654 // LCMPXCHG8B [MI.addr], [ECX:EBX & EDX:EAX are implicitly used and EDX:EAX is implicitly defined]
14662 MachineBasicBlock *
14663 X86TargetLowering::EmitAtomicLoadArith6432(MachineInstr *MI,
14664 MachineBasicBlock *MBB) const {
14665 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14666 DebugLoc DL = MI->getDebugLoc();
14668 MachineFunction *MF = MBB->getParent();
14669 MachineRegisterInfo &MRI = MF->getRegInfo();
14671 const BasicBlock *BB = MBB->getBasicBlock();
14672 MachineFunction::iterator I = MBB;
14675 assert(MI->getNumOperands() <= X86::AddrNumOperands + 7 &&
14676 "Unexpected number of operands");
14678 assert(MI->hasOneMemOperand() &&
14679 "Expected atomic-load-op32 to have one memoperand");
14681 // Memory Reference
14682 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
14683 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
14685 unsigned DstLoReg, DstHiReg;
14686 unsigned SrcLoReg, SrcHiReg;
14687 unsigned MemOpndSlot;
14689 unsigned CurOp = 0;
14691 DstLoReg = MI->getOperand(CurOp++).getReg();
14692 DstHiReg = MI->getOperand(CurOp++).getReg();
14693 MemOpndSlot = CurOp;
14694 CurOp += X86::AddrNumOperands;
14695 SrcLoReg = MI->getOperand(CurOp++).getReg();
14696 SrcHiReg = MI->getOperand(CurOp++).getReg();
14698 const TargetRegisterClass *RC = &X86::GR32RegClass;
14699 const TargetRegisterClass *RC8 = &X86::GR8RegClass;
14701 unsigned t1L = MRI.createVirtualRegister(RC);
14702 unsigned t1H = MRI.createVirtualRegister(RC);
14703 unsigned t2L = MRI.createVirtualRegister(RC);
14704 unsigned t2H = MRI.createVirtualRegister(RC);
14705 unsigned t3L = MRI.createVirtualRegister(RC);
14706 unsigned t3H = MRI.createVirtualRegister(RC);
14707 unsigned t4L = MRI.createVirtualRegister(RC);
14708 unsigned t4H = MRI.createVirtualRegister(RC);
14710 unsigned LCMPXCHGOpc = X86::LCMPXCHG8B;
14711 unsigned LOADOpc = X86::MOV32rm;
14713 // For the atomic load-arith operator, we generate
14716 // t1L = LOAD [MI.addr + 0]
14717 // t1H = LOAD [MI.addr + 4]
14719 // t4L = phi(t1L / thisMBB, t3L / mainMBB)
14720 // t4H = phi(t1H / thisMBB, t3H / mainMBB)
14721 // t2L = OP MI.val.lo, t4L
14722 // t2H = OP MI.val.hi, t4H
14725 // LCMPXCHG8B [MI.addr], [ECX:EBX & EDX:EAX are implicitly used and EDX:EAX is implicitly defined]
14733 MachineBasicBlock *thisMBB = MBB;
14734 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
14735 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
14736 MF->insert(I, mainMBB);
14737 MF->insert(I, sinkMBB);
14739 MachineInstrBuilder MIB;
14741 // Transfer the remainder of BB and its successor edges to sinkMBB.
14742 sinkMBB->splice(sinkMBB->begin(), MBB,
14743 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
14744 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
14748 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), t1L);
14749 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14750 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14752 NewMO.setIsKill(false);
14753 MIB.addOperand(NewMO);
14755 for (MachineInstr::mmo_iterator MMOI = MMOBegin; MMOI != MMOEnd; ++MMOI) {
14756 unsigned flags = (*MMOI)->getFlags();
14757 flags = (flags & ~MachineMemOperand::MOStore) | MachineMemOperand::MOLoad;
14758 MachineMemOperand *MMO =
14759 MF->getMachineMemOperand((*MMOI)->getPointerInfo(), flags,
14760 (*MMOI)->getSize(),
14761 (*MMOI)->getBaseAlignment(),
14762 (*MMOI)->getTBAAInfo(),
14763 (*MMOI)->getRanges());
14764 MIB.addMemOperand(MMO);
14766 MachineInstr *LowMI = MIB;
14769 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), t1H);
14770 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14771 if (i == X86::AddrDisp) {
14772 MIB.addDisp(MI->getOperand(MemOpndSlot + i), 4); // 4 == sizeof(i32)
14774 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14776 NewMO.setIsKill(false);
14777 MIB.addOperand(NewMO);
14780 MIB.setMemRefs(LowMI->memoperands_begin(), LowMI->memoperands_end());
14782 thisMBB->addSuccessor(mainMBB);
14785 MachineBasicBlock *origMainMBB = mainMBB;
14788 MachineInstr *PhiL = BuildMI(mainMBB, DL, TII->get(X86::PHI), t4L)
14789 .addReg(t1L).addMBB(thisMBB).addReg(t3L).addMBB(mainMBB);
14790 MachineInstr *PhiH = BuildMI(mainMBB, DL, TII->get(X86::PHI), t4H)
14791 .addReg(t1H).addMBB(thisMBB).addReg(t3H).addMBB(mainMBB);
14793 unsigned Opc = MI->getOpcode();
14796 llvm_unreachable("Unhandled atomic-load-op6432 opcode!");
14797 case X86::ATOMAND6432:
14798 case X86::ATOMOR6432:
14799 case X86::ATOMXOR6432:
14800 case X86::ATOMADD6432:
14801 case X86::ATOMSUB6432: {
14803 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
14804 BuildMI(mainMBB, DL, TII->get(LoOpc), t2L).addReg(t4L)
14806 BuildMI(mainMBB, DL, TII->get(HiOpc), t2H).addReg(t4H)
14810 case X86::ATOMNAND6432: {
14811 unsigned HiOpc, NOTOpc;
14812 unsigned LoOpc = getNonAtomic6432OpcodeWithExtraOpc(Opc, HiOpc, NOTOpc);
14813 unsigned TmpL = MRI.createVirtualRegister(RC);
14814 unsigned TmpH = MRI.createVirtualRegister(RC);
14815 BuildMI(mainMBB, DL, TII->get(LoOpc), TmpL).addReg(SrcLoReg)
14817 BuildMI(mainMBB, DL, TII->get(HiOpc), TmpH).addReg(SrcHiReg)
14819 BuildMI(mainMBB, DL, TII->get(NOTOpc), t2L).addReg(TmpL);
14820 BuildMI(mainMBB, DL, TII->get(NOTOpc), t2H).addReg(TmpH);
14823 case X86::ATOMMAX6432:
14824 case X86::ATOMMIN6432:
14825 case X86::ATOMUMAX6432:
14826 case X86::ATOMUMIN6432: {
14828 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
14829 unsigned cL = MRI.createVirtualRegister(RC8);
14830 unsigned cH = MRI.createVirtualRegister(RC8);
14831 unsigned cL32 = MRI.createVirtualRegister(RC);
14832 unsigned cH32 = MRI.createVirtualRegister(RC);
14833 unsigned cc = MRI.createVirtualRegister(RC);
14834 // cl := cmp src_lo, lo
14835 BuildMI(mainMBB, DL, TII->get(X86::CMP32rr))
14836 .addReg(SrcLoReg).addReg(t4L);
14837 BuildMI(mainMBB, DL, TII->get(LoOpc), cL);
14838 BuildMI(mainMBB, DL, TII->get(X86::MOVZX32rr8), cL32).addReg(cL);
14839 // ch := cmp src_hi, hi
14840 BuildMI(mainMBB, DL, TII->get(X86::CMP32rr))
14841 .addReg(SrcHiReg).addReg(t4H);
14842 BuildMI(mainMBB, DL, TII->get(HiOpc), cH);
14843 BuildMI(mainMBB, DL, TII->get(X86::MOVZX32rr8), cH32).addReg(cH);
14844 // cc := if (src_hi == hi) ? cl : ch;
14845 if (Subtarget->hasCMov()) {
14846 BuildMI(mainMBB, DL, TII->get(X86::CMOVE32rr), cc)
14847 .addReg(cH32).addReg(cL32);
14849 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), cc)
14850 .addReg(cH32).addReg(cL32)
14851 .addImm(X86::COND_E);
14852 mainMBB = EmitLoweredSelect(MIB, mainMBB);
14854 BuildMI(mainMBB, DL, TII->get(X86::TEST32rr)).addReg(cc).addReg(cc);
14855 if (Subtarget->hasCMov()) {
14856 BuildMI(mainMBB, DL, TII->get(X86::CMOVNE32rr), t2L)
14857 .addReg(SrcLoReg).addReg(t4L);
14858 BuildMI(mainMBB, DL, TII->get(X86::CMOVNE32rr), t2H)
14859 .addReg(SrcHiReg).addReg(t4H);
14861 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), t2L)
14862 .addReg(SrcLoReg).addReg(t4L)
14863 .addImm(X86::COND_NE);
14864 mainMBB = EmitLoweredSelect(MIB, mainMBB);
14865 // As the lowered CMOV won't clobber EFLAGS, we could reuse it for the
14866 // 2nd CMOV lowering.
14867 mainMBB->addLiveIn(X86::EFLAGS);
14868 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), t2H)
14869 .addReg(SrcHiReg).addReg(t4H)
14870 .addImm(X86::COND_NE);
14871 mainMBB = EmitLoweredSelect(MIB, mainMBB);
14872 // Replace the original PHI node as mainMBB is changed after CMOV
14874 BuildMI(*origMainMBB, PhiL, DL, TII->get(X86::PHI), t4L)
14875 .addReg(t1L).addMBB(thisMBB).addReg(t3L).addMBB(mainMBB);
14876 BuildMI(*origMainMBB, PhiH, DL, TII->get(X86::PHI), t4H)
14877 .addReg(t1H).addMBB(thisMBB).addReg(t3H).addMBB(mainMBB);
14878 PhiL->eraseFromParent();
14879 PhiH->eraseFromParent();
14883 case X86::ATOMSWAP6432: {
14885 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
14886 BuildMI(mainMBB, DL, TII->get(LoOpc), t2L).addReg(SrcLoReg);
14887 BuildMI(mainMBB, DL, TII->get(HiOpc), t2H).addReg(SrcHiReg);
14892 // Copy EDX:EAX back from HiReg:LoReg
14893 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EAX).addReg(t4L);
14894 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EDX).addReg(t4H);
14895 // Copy ECX:EBX from t1H:t1L
14896 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EBX).addReg(t2L);
14897 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::ECX).addReg(t2H);
14899 MIB = BuildMI(mainMBB, DL, TII->get(LCMPXCHGOpc));
14900 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14901 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14903 NewMO.setIsKill(false);
14904 MIB.addOperand(NewMO);
14906 MIB.setMemRefs(MMOBegin, MMOEnd);
14908 // Copy EDX:EAX back to t3H:t3L
14909 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t3L).addReg(X86::EAX);
14910 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t3H).addReg(X86::EDX);
14912 BuildMI(mainMBB, DL, TII->get(X86::JNE_4)).addMBB(origMainMBB);
14914 mainMBB->addSuccessor(origMainMBB);
14915 mainMBB->addSuccessor(sinkMBB);
14918 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
14919 TII->get(TargetOpcode::COPY), DstLoReg)
14921 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
14922 TII->get(TargetOpcode::COPY), DstHiReg)
14925 MI->eraseFromParent();
14929 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
14930 // or XMM0_V32I8 in AVX all of this code can be replaced with that
14931 // in the .td file.
14932 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
14933 const TargetInstrInfo *TII) {
14935 switch (MI->getOpcode()) {
14936 default: llvm_unreachable("illegal opcode!");
14937 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
14938 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
14939 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
14940 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
14941 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
14942 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
14943 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
14944 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
14947 DebugLoc dl = MI->getDebugLoc();
14948 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
14950 unsigned NumArgs = MI->getNumOperands();
14951 for (unsigned i = 1; i < NumArgs; ++i) {
14952 MachineOperand &Op = MI->getOperand(i);
14953 if (!(Op.isReg() && Op.isImplicit()))
14954 MIB.addOperand(Op);
14956 if (MI->hasOneMemOperand())
14957 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
14959 BuildMI(*BB, MI, dl,
14960 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
14961 .addReg(X86::XMM0);
14963 MI->eraseFromParent();
14967 // FIXME: Custom handling because TableGen doesn't support multiple implicit
14968 // defs in an instruction pattern
14969 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
14970 const TargetInstrInfo *TII) {
14972 switch (MI->getOpcode()) {
14973 default: llvm_unreachable("illegal opcode!");
14974 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
14975 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
14976 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
14977 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
14978 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
14979 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
14980 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
14981 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
14984 DebugLoc dl = MI->getDebugLoc();
14985 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
14987 unsigned NumArgs = MI->getNumOperands(); // remove the results
14988 for (unsigned i = 1; i < NumArgs; ++i) {
14989 MachineOperand &Op = MI->getOperand(i);
14990 if (!(Op.isReg() && Op.isImplicit()))
14991 MIB.addOperand(Op);
14993 if (MI->hasOneMemOperand())
14994 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
14996 BuildMI(*BB, MI, dl,
14997 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
15000 MI->eraseFromParent();
15004 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
15005 const TargetInstrInfo *TII,
15006 const X86Subtarget* Subtarget) {
15007 DebugLoc dl = MI->getDebugLoc();
15009 // Address into RAX/EAX, other two args into ECX, EDX.
15010 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
15011 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
15012 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
15013 for (int i = 0; i < X86::AddrNumOperands; ++i)
15014 MIB.addOperand(MI->getOperand(i));
15016 unsigned ValOps = X86::AddrNumOperands;
15017 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
15018 .addReg(MI->getOperand(ValOps).getReg());
15019 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
15020 .addReg(MI->getOperand(ValOps+1).getReg());
15022 // The instruction doesn't actually take any operands though.
15023 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
15025 MI->eraseFromParent(); // The pseudo is gone now.
15029 MachineBasicBlock *
15030 X86TargetLowering::EmitVAARG64WithCustomInserter(
15032 MachineBasicBlock *MBB) const {
15033 // Emit va_arg instruction on X86-64.
15035 // Operands to this pseudo-instruction:
15036 // 0 ) Output : destination address (reg)
15037 // 1-5) Input : va_list address (addr, i64mem)
15038 // 6 ) ArgSize : Size (in bytes) of vararg type
15039 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
15040 // 8 ) Align : Alignment of type
15041 // 9 ) EFLAGS (implicit-def)
15043 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
15044 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
15046 unsigned DestReg = MI->getOperand(0).getReg();
15047 MachineOperand &Base = MI->getOperand(1);
15048 MachineOperand &Scale = MI->getOperand(2);
15049 MachineOperand &Index = MI->getOperand(3);
15050 MachineOperand &Disp = MI->getOperand(4);
15051 MachineOperand &Segment = MI->getOperand(5);
15052 unsigned ArgSize = MI->getOperand(6).getImm();
15053 unsigned ArgMode = MI->getOperand(7).getImm();
15054 unsigned Align = MI->getOperand(8).getImm();
15056 // Memory Reference
15057 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
15058 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
15059 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
15061 // Machine Information
15062 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15063 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
15064 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
15065 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
15066 DebugLoc DL = MI->getDebugLoc();
15068 // struct va_list {
15071 // i64 overflow_area (address)
15072 // i64 reg_save_area (address)
15074 // sizeof(va_list) = 24
15075 // alignment(va_list) = 8
15077 unsigned TotalNumIntRegs = 6;
15078 unsigned TotalNumXMMRegs = 8;
15079 bool UseGPOffset = (ArgMode == 1);
15080 bool UseFPOffset = (ArgMode == 2);
15081 unsigned MaxOffset = TotalNumIntRegs * 8 +
15082 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
15084 /* Align ArgSize to a multiple of 8 */
15085 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
15086 bool NeedsAlign = (Align > 8);
15088 MachineBasicBlock *thisMBB = MBB;
15089 MachineBasicBlock *overflowMBB;
15090 MachineBasicBlock *offsetMBB;
15091 MachineBasicBlock *endMBB;
15093 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
15094 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
15095 unsigned OffsetReg = 0;
15097 if (!UseGPOffset && !UseFPOffset) {
15098 // If we only pull from the overflow region, we don't create a branch.
15099 // We don't need to alter control flow.
15100 OffsetDestReg = 0; // unused
15101 OverflowDestReg = DestReg;
15104 overflowMBB = thisMBB;
15107 // First emit code to check if gp_offset (or fp_offset) is below the bound.
15108 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
15109 // If not, pull from overflow_area. (branch to overflowMBB)
15114 // offsetMBB overflowMBB
15119 // Registers for the PHI in endMBB
15120 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
15121 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
15123 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
15124 MachineFunction *MF = MBB->getParent();
15125 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
15126 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
15127 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
15129 MachineFunction::iterator MBBIter = MBB;
15132 // Insert the new basic blocks
15133 MF->insert(MBBIter, offsetMBB);
15134 MF->insert(MBBIter, overflowMBB);
15135 MF->insert(MBBIter, endMBB);
15137 // Transfer the remainder of MBB and its successor edges to endMBB.
15138 endMBB->splice(endMBB->begin(), thisMBB,
15139 llvm::next(MachineBasicBlock::iterator(MI)),
15141 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
15143 // Make offsetMBB and overflowMBB successors of thisMBB
15144 thisMBB->addSuccessor(offsetMBB);
15145 thisMBB->addSuccessor(overflowMBB);
15147 // endMBB is a successor of both offsetMBB and overflowMBB
15148 offsetMBB->addSuccessor(endMBB);
15149 overflowMBB->addSuccessor(endMBB);
15151 // Load the offset value into a register
15152 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
15153 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
15157 .addDisp(Disp, UseFPOffset ? 4 : 0)
15158 .addOperand(Segment)
15159 .setMemRefs(MMOBegin, MMOEnd);
15161 // Check if there is enough room left to pull this argument.
15162 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
15164 .addImm(MaxOffset + 8 - ArgSizeA8);
15166 // Branch to "overflowMBB" if offset >= max
15167 // Fall through to "offsetMBB" otherwise
15168 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
15169 .addMBB(overflowMBB);
15172 // In offsetMBB, emit code to use the reg_save_area.
15174 assert(OffsetReg != 0);
15176 // Read the reg_save_area address.
15177 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
15178 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
15183 .addOperand(Segment)
15184 .setMemRefs(MMOBegin, MMOEnd);
15186 // Zero-extend the offset
15187 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
15188 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
15191 .addImm(X86::sub_32bit);
15193 // Add the offset to the reg_save_area to get the final address.
15194 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
15195 .addReg(OffsetReg64)
15196 .addReg(RegSaveReg);
15198 // Compute the offset for the next argument
15199 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
15200 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
15202 .addImm(UseFPOffset ? 16 : 8);
15204 // Store it back into the va_list.
15205 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
15209 .addDisp(Disp, UseFPOffset ? 4 : 0)
15210 .addOperand(Segment)
15211 .addReg(NextOffsetReg)
15212 .setMemRefs(MMOBegin, MMOEnd);
15215 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
15220 // Emit code to use overflow area
15223 // Load the overflow_area address into a register.
15224 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
15225 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
15230 .addOperand(Segment)
15231 .setMemRefs(MMOBegin, MMOEnd);
15233 // If we need to align it, do so. Otherwise, just copy the address
15234 // to OverflowDestReg.
15236 // Align the overflow address
15237 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
15238 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
15240 // aligned_addr = (addr + (align-1)) & ~(align-1)
15241 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
15242 .addReg(OverflowAddrReg)
15245 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
15247 .addImm(~(uint64_t)(Align-1));
15249 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
15250 .addReg(OverflowAddrReg);
15253 // Compute the next overflow address after this argument.
15254 // (the overflow address should be kept 8-byte aligned)
15255 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
15256 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
15257 .addReg(OverflowDestReg)
15258 .addImm(ArgSizeA8);
15260 // Store the new overflow address.
15261 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
15266 .addOperand(Segment)
15267 .addReg(NextAddrReg)
15268 .setMemRefs(MMOBegin, MMOEnd);
15270 // If we branched, emit the PHI to the front of endMBB.
15272 BuildMI(*endMBB, endMBB->begin(), DL,
15273 TII->get(X86::PHI), DestReg)
15274 .addReg(OffsetDestReg).addMBB(offsetMBB)
15275 .addReg(OverflowDestReg).addMBB(overflowMBB);
15278 // Erase the pseudo instruction
15279 MI->eraseFromParent();
15284 MachineBasicBlock *
15285 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
15287 MachineBasicBlock *MBB) const {
15288 // Emit code to save XMM registers to the stack. The ABI says that the
15289 // number of registers to save is given in %al, so it's theoretically
15290 // possible to do an indirect jump trick to avoid saving all of them,
15291 // however this code takes a simpler approach and just executes all
15292 // of the stores if %al is non-zero. It's less code, and it's probably
15293 // easier on the hardware branch predictor, and stores aren't all that
15294 // expensive anyway.
15296 // Create the new basic blocks. One block contains all the XMM stores,
15297 // and one block is the final destination regardless of whether any
15298 // stores were performed.
15299 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
15300 MachineFunction *F = MBB->getParent();
15301 MachineFunction::iterator MBBIter = MBB;
15303 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
15304 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
15305 F->insert(MBBIter, XMMSaveMBB);
15306 F->insert(MBBIter, EndMBB);
15308 // Transfer the remainder of MBB and its successor edges to EndMBB.
15309 EndMBB->splice(EndMBB->begin(), MBB,
15310 llvm::next(MachineBasicBlock::iterator(MI)),
15312 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
15314 // The original block will now fall through to the XMM save block.
15315 MBB->addSuccessor(XMMSaveMBB);
15316 // The XMMSaveMBB will fall through to the end block.
15317 XMMSaveMBB->addSuccessor(EndMBB);
15319 // Now add the instructions.
15320 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15321 DebugLoc DL = MI->getDebugLoc();
15323 unsigned CountReg = MI->getOperand(0).getReg();
15324 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
15325 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
15327 if (!Subtarget->isTargetWin64()) {
15328 // If %al is 0, branch around the XMM save block.
15329 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
15330 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
15331 MBB->addSuccessor(EndMBB);
15334 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
15335 // In the XMM save block, save all the XMM argument registers.
15336 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
15337 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
15338 MachineMemOperand *MMO =
15339 F->getMachineMemOperand(
15340 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
15341 MachineMemOperand::MOStore,
15342 /*Size=*/16, /*Align=*/16);
15343 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
15344 .addFrameIndex(RegSaveFrameIndex)
15345 .addImm(/*Scale=*/1)
15346 .addReg(/*IndexReg=*/0)
15347 .addImm(/*Disp=*/Offset)
15348 .addReg(/*Segment=*/0)
15349 .addReg(MI->getOperand(i).getReg())
15350 .addMemOperand(MMO);
15353 MI->eraseFromParent(); // The pseudo instruction is gone now.
15358 // The EFLAGS operand of SelectItr might be missing a kill marker
15359 // because there were multiple uses of EFLAGS, and ISel didn't know
15360 // which to mark. Figure out whether SelectItr should have had a
15361 // kill marker, and set it if it should. Returns the correct kill
15363 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
15364 MachineBasicBlock* BB,
15365 const TargetRegisterInfo* TRI) {
15366 // Scan forward through BB for a use/def of EFLAGS.
15367 MachineBasicBlock::iterator miI(llvm::next(SelectItr));
15368 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
15369 const MachineInstr& mi = *miI;
15370 if (mi.readsRegister(X86::EFLAGS))
15372 if (mi.definesRegister(X86::EFLAGS))
15373 break; // Should have kill-flag - update below.
15376 // If we hit the end of the block, check whether EFLAGS is live into a
15378 if (miI == BB->end()) {
15379 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
15380 sEnd = BB->succ_end();
15381 sItr != sEnd; ++sItr) {
15382 MachineBasicBlock* succ = *sItr;
15383 if (succ->isLiveIn(X86::EFLAGS))
15388 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
15389 // out. SelectMI should have a kill flag on EFLAGS.
15390 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
15394 MachineBasicBlock *
15395 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
15396 MachineBasicBlock *BB) const {
15397 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15398 DebugLoc DL = MI->getDebugLoc();
15400 // To "insert" a SELECT_CC instruction, we actually have to insert the
15401 // diamond control-flow pattern. The incoming instruction knows the
15402 // destination vreg to set, the condition code register to branch on, the
15403 // true/false values to select between, and a branch opcode to use.
15404 const BasicBlock *LLVM_BB = BB->getBasicBlock();
15405 MachineFunction::iterator It = BB;
15411 // cmpTY ccX, r1, r2
15413 // fallthrough --> copy0MBB
15414 MachineBasicBlock *thisMBB = BB;
15415 MachineFunction *F = BB->getParent();
15416 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
15417 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
15418 F->insert(It, copy0MBB);
15419 F->insert(It, sinkMBB);
15421 // If the EFLAGS register isn't dead in the terminator, then claim that it's
15422 // live into the sink and copy blocks.
15423 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
15424 if (!MI->killsRegister(X86::EFLAGS) &&
15425 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
15426 copy0MBB->addLiveIn(X86::EFLAGS);
15427 sinkMBB->addLiveIn(X86::EFLAGS);
15430 // Transfer the remainder of BB and its successor edges to sinkMBB.
15431 sinkMBB->splice(sinkMBB->begin(), BB,
15432 llvm::next(MachineBasicBlock::iterator(MI)),
15434 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
15436 // Add the true and fallthrough blocks as its successors.
15437 BB->addSuccessor(copy0MBB);
15438 BB->addSuccessor(sinkMBB);
15440 // Create the conditional branch instruction.
15442 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
15443 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
15446 // %FalseValue = ...
15447 // # fallthrough to sinkMBB
15448 copy0MBB->addSuccessor(sinkMBB);
15451 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
15453 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
15454 TII->get(X86::PHI), MI->getOperand(0).getReg())
15455 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
15456 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
15458 MI->eraseFromParent(); // The pseudo instruction is gone now.
15462 MachineBasicBlock *
15463 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
15464 bool Is64Bit) const {
15465 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15466 DebugLoc DL = MI->getDebugLoc();
15467 MachineFunction *MF = BB->getParent();
15468 const BasicBlock *LLVM_BB = BB->getBasicBlock();
15470 assert(getTargetMachine().Options.EnableSegmentedStacks);
15472 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
15473 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30;
15476 // ... [Till the alloca]
15477 // If stacklet is not large enough, jump to mallocMBB
15480 // Allocate by subtracting from RSP
15481 // Jump to continueMBB
15484 // Allocate by call to runtime
15488 // [rest of original BB]
15491 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
15492 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
15493 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
15495 MachineRegisterInfo &MRI = MF->getRegInfo();
15496 const TargetRegisterClass *AddrRegClass =
15497 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32);
15499 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
15500 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
15501 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
15502 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
15503 sizeVReg = MI->getOperand(1).getReg(),
15504 physSPReg = Is64Bit ? X86::RSP : X86::ESP;
15506 MachineFunction::iterator MBBIter = BB;
15509 MF->insert(MBBIter, bumpMBB);
15510 MF->insert(MBBIter, mallocMBB);
15511 MF->insert(MBBIter, continueMBB);
15513 continueMBB->splice(continueMBB->begin(), BB, llvm::next
15514 (MachineBasicBlock::iterator(MI)), BB->end());
15515 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
15517 // Add code to the main basic block to check if the stack limit has been hit,
15518 // and if so, jump to mallocMBB otherwise to bumpMBB.
15519 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
15520 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
15521 .addReg(tmpSPVReg).addReg(sizeVReg);
15522 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr))
15523 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
15524 .addReg(SPLimitVReg);
15525 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
15527 // bumpMBB simply decreases the stack pointer, since we know the current
15528 // stacklet has enough space.
15529 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
15530 .addReg(SPLimitVReg);
15531 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
15532 .addReg(SPLimitVReg);
15533 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
15535 // Calls into a routine in libgcc to allocate more space from the heap.
15536 const uint32_t *RegMask =
15537 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
15539 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
15541 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
15542 .addExternalSymbol("__morestack_allocate_stack_space")
15543 .addRegMask(RegMask)
15544 .addReg(X86::RDI, RegState::Implicit)
15545 .addReg(X86::RAX, RegState::ImplicitDefine);
15547 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
15549 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
15550 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
15551 .addExternalSymbol("__morestack_allocate_stack_space")
15552 .addRegMask(RegMask)
15553 .addReg(X86::EAX, RegState::ImplicitDefine);
15557 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
15560 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
15561 .addReg(Is64Bit ? X86::RAX : X86::EAX);
15562 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
15564 // Set up the CFG correctly.
15565 BB->addSuccessor(bumpMBB);
15566 BB->addSuccessor(mallocMBB);
15567 mallocMBB->addSuccessor(continueMBB);
15568 bumpMBB->addSuccessor(continueMBB);
15570 // Take care of the PHI nodes.
15571 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
15572 MI->getOperand(0).getReg())
15573 .addReg(mallocPtrVReg).addMBB(mallocMBB)
15574 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
15576 // Delete the original pseudo instruction.
15577 MI->eraseFromParent();
15580 return continueMBB;
15583 MachineBasicBlock *
15584 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
15585 MachineBasicBlock *BB) const {
15586 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15587 DebugLoc DL = MI->getDebugLoc();
15589 assert(!Subtarget->isTargetMacho());
15591 // The lowering is pretty easy: we're just emitting the call to _alloca. The
15592 // non-trivial part is impdef of ESP.
15594 if (Subtarget->isTargetWin64()) {
15595 if (Subtarget->isTargetCygMing()) {
15596 // ___chkstk(Mingw64):
15597 // Clobbers R10, R11, RAX and EFLAGS.
15599 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
15600 .addExternalSymbol("___chkstk")
15601 .addReg(X86::RAX, RegState::Implicit)
15602 .addReg(X86::RSP, RegState::Implicit)
15603 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
15604 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
15605 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
15607 // __chkstk(MSVCRT): does not update stack pointer.
15608 // Clobbers R10, R11 and EFLAGS.
15609 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
15610 .addExternalSymbol("__chkstk")
15611 .addReg(X86::RAX, RegState::Implicit)
15612 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
15613 // RAX has the offset to be subtracted from RSP.
15614 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
15619 const char *StackProbeSymbol =
15620 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca";
15622 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
15623 .addExternalSymbol(StackProbeSymbol)
15624 .addReg(X86::EAX, RegState::Implicit)
15625 .addReg(X86::ESP, RegState::Implicit)
15626 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
15627 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
15628 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
15631 MI->eraseFromParent(); // The pseudo instruction is gone now.
15635 MachineBasicBlock *
15636 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
15637 MachineBasicBlock *BB) const {
15638 // This is pretty easy. We're taking the value that we received from
15639 // our load from the relocation, sticking it in either RDI (x86-64)
15640 // or EAX and doing an indirect call. The return value will then
15641 // be in the normal return register.
15642 const X86InstrInfo *TII
15643 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
15644 DebugLoc DL = MI->getDebugLoc();
15645 MachineFunction *F = BB->getParent();
15647 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
15648 assert(MI->getOperand(3).isGlobal() && "This should be a global");
15650 // Get a register mask for the lowered call.
15651 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
15652 // proper register mask.
15653 const uint32_t *RegMask =
15654 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
15655 if (Subtarget->is64Bit()) {
15656 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
15657 TII->get(X86::MOV64rm), X86::RDI)
15659 .addImm(0).addReg(0)
15660 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
15661 MI->getOperand(3).getTargetFlags())
15663 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
15664 addDirectMem(MIB, X86::RDI);
15665 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
15666 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
15667 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
15668 TII->get(X86::MOV32rm), X86::EAX)
15670 .addImm(0).addReg(0)
15671 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
15672 MI->getOperand(3).getTargetFlags())
15674 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
15675 addDirectMem(MIB, X86::EAX);
15676 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
15678 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
15679 TII->get(X86::MOV32rm), X86::EAX)
15680 .addReg(TII->getGlobalBaseReg(F))
15681 .addImm(0).addReg(0)
15682 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
15683 MI->getOperand(3).getTargetFlags())
15685 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
15686 addDirectMem(MIB, X86::EAX);
15687 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
15690 MI->eraseFromParent(); // The pseudo instruction is gone now.
15694 MachineBasicBlock *
15695 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
15696 MachineBasicBlock *MBB) const {
15697 DebugLoc DL = MI->getDebugLoc();
15698 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15700 MachineFunction *MF = MBB->getParent();
15701 MachineRegisterInfo &MRI = MF->getRegInfo();
15703 const BasicBlock *BB = MBB->getBasicBlock();
15704 MachineFunction::iterator I = MBB;
15707 // Memory Reference
15708 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
15709 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
15712 unsigned MemOpndSlot = 0;
15714 unsigned CurOp = 0;
15716 DstReg = MI->getOperand(CurOp++).getReg();
15717 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
15718 assert(RC->hasType(MVT::i32) && "Invalid destination!");
15719 unsigned mainDstReg = MRI.createVirtualRegister(RC);
15720 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
15722 MemOpndSlot = CurOp;
15724 MVT PVT = getPointerTy();
15725 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
15726 "Invalid Pointer Size!");
15728 // For v = setjmp(buf), we generate
15731 // buf[LabelOffset] = restoreMBB
15732 // SjLjSetup restoreMBB
15738 // v = phi(main, restore)
15743 MachineBasicBlock *thisMBB = MBB;
15744 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
15745 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
15746 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
15747 MF->insert(I, mainMBB);
15748 MF->insert(I, sinkMBB);
15749 MF->push_back(restoreMBB);
15751 MachineInstrBuilder MIB;
15753 // Transfer the remainder of BB and its successor edges to sinkMBB.
15754 sinkMBB->splice(sinkMBB->begin(), MBB,
15755 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
15756 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
15759 unsigned PtrStoreOpc = 0;
15760 unsigned LabelReg = 0;
15761 const int64_t LabelOffset = 1 * PVT.getStoreSize();
15762 Reloc::Model RM = getTargetMachine().getRelocationModel();
15763 bool UseImmLabel = (getTargetMachine().getCodeModel() == CodeModel::Small) &&
15764 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
15766 // Prepare IP either in reg or imm.
15767 if (!UseImmLabel) {
15768 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
15769 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
15770 LabelReg = MRI.createVirtualRegister(PtrRC);
15771 if (Subtarget->is64Bit()) {
15772 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
15776 .addMBB(restoreMBB)
15779 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
15780 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
15781 .addReg(XII->getGlobalBaseReg(MF))
15784 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
15788 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
15790 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
15791 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
15792 if (i == X86::AddrDisp)
15793 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
15795 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
15798 MIB.addReg(LabelReg);
15800 MIB.addMBB(restoreMBB);
15801 MIB.setMemRefs(MMOBegin, MMOEnd);
15803 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
15804 .addMBB(restoreMBB);
15806 const X86RegisterInfo *RegInfo =
15807 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
15808 MIB.addRegMask(RegInfo->getNoPreservedMask());
15809 thisMBB->addSuccessor(mainMBB);
15810 thisMBB->addSuccessor(restoreMBB);
15814 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
15815 mainMBB->addSuccessor(sinkMBB);
15818 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
15819 TII->get(X86::PHI), DstReg)
15820 .addReg(mainDstReg).addMBB(mainMBB)
15821 .addReg(restoreDstReg).addMBB(restoreMBB);
15824 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
15825 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
15826 restoreMBB->addSuccessor(sinkMBB);
15828 MI->eraseFromParent();
15832 MachineBasicBlock *
15833 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
15834 MachineBasicBlock *MBB) const {
15835 DebugLoc DL = MI->getDebugLoc();
15836 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15838 MachineFunction *MF = MBB->getParent();
15839 MachineRegisterInfo &MRI = MF->getRegInfo();
15841 // Memory Reference
15842 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
15843 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
15845 MVT PVT = getPointerTy();
15846 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
15847 "Invalid Pointer Size!");
15849 const TargetRegisterClass *RC =
15850 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
15851 unsigned Tmp = MRI.createVirtualRegister(RC);
15852 // Since FP is only updated here but NOT referenced, it's treated as GPR.
15853 const X86RegisterInfo *RegInfo =
15854 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
15855 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
15856 unsigned SP = RegInfo->getStackRegister();
15858 MachineInstrBuilder MIB;
15860 const int64_t LabelOffset = 1 * PVT.getStoreSize();
15861 const int64_t SPOffset = 2 * PVT.getStoreSize();
15863 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
15864 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
15867 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
15868 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
15869 MIB.addOperand(MI->getOperand(i));
15870 MIB.setMemRefs(MMOBegin, MMOEnd);
15872 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
15873 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
15874 if (i == X86::AddrDisp)
15875 MIB.addDisp(MI->getOperand(i), LabelOffset);
15877 MIB.addOperand(MI->getOperand(i));
15879 MIB.setMemRefs(MMOBegin, MMOEnd);
15881 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
15882 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
15883 if (i == X86::AddrDisp)
15884 MIB.addDisp(MI->getOperand(i), SPOffset);
15886 MIB.addOperand(MI->getOperand(i));
15888 MIB.setMemRefs(MMOBegin, MMOEnd);
15890 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
15892 MI->eraseFromParent();
15896 MachineBasicBlock *
15897 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
15898 MachineBasicBlock *BB) const {
15899 switch (MI->getOpcode()) {
15900 default: llvm_unreachable("Unexpected instr type to insert");
15901 case X86::TAILJMPd64:
15902 case X86::TAILJMPr64:
15903 case X86::TAILJMPm64:
15904 llvm_unreachable("TAILJMP64 would not be touched here.");
15905 case X86::TCRETURNdi64:
15906 case X86::TCRETURNri64:
15907 case X86::TCRETURNmi64:
15909 case X86::WIN_ALLOCA:
15910 return EmitLoweredWinAlloca(MI, BB);
15911 case X86::SEG_ALLOCA_32:
15912 return EmitLoweredSegAlloca(MI, BB, false);
15913 case X86::SEG_ALLOCA_64:
15914 return EmitLoweredSegAlloca(MI, BB, true);
15915 case X86::TLSCall_32:
15916 case X86::TLSCall_64:
15917 return EmitLoweredTLSCall(MI, BB);
15918 case X86::CMOV_GR8:
15919 case X86::CMOV_FR32:
15920 case X86::CMOV_FR64:
15921 case X86::CMOV_V4F32:
15922 case X86::CMOV_V2F64:
15923 case X86::CMOV_V2I64:
15924 case X86::CMOV_V8F32:
15925 case X86::CMOV_V4F64:
15926 case X86::CMOV_V4I64:
15927 case X86::CMOV_V16F32:
15928 case X86::CMOV_V8F64:
15929 case X86::CMOV_V8I64:
15930 case X86::CMOV_GR16:
15931 case X86::CMOV_GR32:
15932 case X86::CMOV_RFP32:
15933 case X86::CMOV_RFP64:
15934 case X86::CMOV_RFP80:
15935 return EmitLoweredSelect(MI, BB);
15937 case X86::FP32_TO_INT16_IN_MEM:
15938 case X86::FP32_TO_INT32_IN_MEM:
15939 case X86::FP32_TO_INT64_IN_MEM:
15940 case X86::FP64_TO_INT16_IN_MEM:
15941 case X86::FP64_TO_INT32_IN_MEM:
15942 case X86::FP64_TO_INT64_IN_MEM:
15943 case X86::FP80_TO_INT16_IN_MEM:
15944 case X86::FP80_TO_INT32_IN_MEM:
15945 case X86::FP80_TO_INT64_IN_MEM: {
15946 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15947 DebugLoc DL = MI->getDebugLoc();
15949 // Change the floating point control register to use "round towards zero"
15950 // mode when truncating to an integer value.
15951 MachineFunction *F = BB->getParent();
15952 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
15953 addFrameReference(BuildMI(*BB, MI, DL,
15954 TII->get(X86::FNSTCW16m)), CWFrameIdx);
15956 // Load the old value of the high byte of the control word...
15958 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
15959 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
15962 // Set the high part to be round to zero...
15963 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
15966 // Reload the modified control word now...
15967 addFrameReference(BuildMI(*BB, MI, DL,
15968 TII->get(X86::FLDCW16m)), CWFrameIdx);
15970 // Restore the memory image of control word to original value
15971 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
15974 // Get the X86 opcode to use.
15976 switch (MI->getOpcode()) {
15977 default: llvm_unreachable("illegal opcode!");
15978 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
15979 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
15980 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
15981 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
15982 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
15983 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
15984 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
15985 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
15986 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
15990 MachineOperand &Op = MI->getOperand(0);
15992 AM.BaseType = X86AddressMode::RegBase;
15993 AM.Base.Reg = Op.getReg();
15995 AM.BaseType = X86AddressMode::FrameIndexBase;
15996 AM.Base.FrameIndex = Op.getIndex();
15998 Op = MI->getOperand(1);
16000 AM.Scale = Op.getImm();
16001 Op = MI->getOperand(2);
16003 AM.IndexReg = Op.getImm();
16004 Op = MI->getOperand(3);
16005 if (Op.isGlobal()) {
16006 AM.GV = Op.getGlobal();
16008 AM.Disp = Op.getImm();
16010 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
16011 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
16013 // Reload the original control word now.
16014 addFrameReference(BuildMI(*BB, MI, DL,
16015 TII->get(X86::FLDCW16m)), CWFrameIdx);
16017 MI->eraseFromParent(); // The pseudo instruction is gone now.
16020 // String/text processing lowering.
16021 case X86::PCMPISTRM128REG:
16022 case X86::VPCMPISTRM128REG:
16023 case X86::PCMPISTRM128MEM:
16024 case X86::VPCMPISTRM128MEM:
16025 case X86::PCMPESTRM128REG:
16026 case X86::VPCMPESTRM128REG:
16027 case X86::PCMPESTRM128MEM:
16028 case X86::VPCMPESTRM128MEM:
16029 assert(Subtarget->hasSSE42() &&
16030 "Target must have SSE4.2 or AVX features enabled");
16031 return EmitPCMPSTRM(MI, BB, getTargetMachine().getInstrInfo());
16033 // String/text processing lowering.
16034 case X86::PCMPISTRIREG:
16035 case X86::VPCMPISTRIREG:
16036 case X86::PCMPISTRIMEM:
16037 case X86::VPCMPISTRIMEM:
16038 case X86::PCMPESTRIREG:
16039 case X86::VPCMPESTRIREG:
16040 case X86::PCMPESTRIMEM:
16041 case X86::VPCMPESTRIMEM:
16042 assert(Subtarget->hasSSE42() &&
16043 "Target must have SSE4.2 or AVX features enabled");
16044 return EmitPCMPSTRI(MI, BB, getTargetMachine().getInstrInfo());
16046 // Thread synchronization.
16048 return EmitMonitor(MI, BB, getTargetMachine().getInstrInfo(), Subtarget);
16052 return EmitXBegin(MI, BB, getTargetMachine().getInstrInfo());
16054 // Atomic Lowering.
16055 case X86::ATOMAND8:
16056 case X86::ATOMAND16:
16057 case X86::ATOMAND32:
16058 case X86::ATOMAND64:
16061 case X86::ATOMOR16:
16062 case X86::ATOMOR32:
16063 case X86::ATOMOR64:
16065 case X86::ATOMXOR16:
16066 case X86::ATOMXOR8:
16067 case X86::ATOMXOR32:
16068 case X86::ATOMXOR64:
16070 case X86::ATOMNAND8:
16071 case X86::ATOMNAND16:
16072 case X86::ATOMNAND32:
16073 case X86::ATOMNAND64:
16075 case X86::ATOMMAX8:
16076 case X86::ATOMMAX16:
16077 case X86::ATOMMAX32:
16078 case X86::ATOMMAX64:
16080 case X86::ATOMMIN8:
16081 case X86::ATOMMIN16:
16082 case X86::ATOMMIN32:
16083 case X86::ATOMMIN64:
16085 case X86::ATOMUMAX8:
16086 case X86::ATOMUMAX16:
16087 case X86::ATOMUMAX32:
16088 case X86::ATOMUMAX64:
16090 case X86::ATOMUMIN8:
16091 case X86::ATOMUMIN16:
16092 case X86::ATOMUMIN32:
16093 case X86::ATOMUMIN64:
16094 return EmitAtomicLoadArith(MI, BB);
16096 // This group does 64-bit operations on a 32-bit host.
16097 case X86::ATOMAND6432:
16098 case X86::ATOMOR6432:
16099 case X86::ATOMXOR6432:
16100 case X86::ATOMNAND6432:
16101 case X86::ATOMADD6432:
16102 case X86::ATOMSUB6432:
16103 case X86::ATOMMAX6432:
16104 case X86::ATOMMIN6432:
16105 case X86::ATOMUMAX6432:
16106 case X86::ATOMUMIN6432:
16107 case X86::ATOMSWAP6432:
16108 return EmitAtomicLoadArith6432(MI, BB);
16110 case X86::VASTART_SAVE_XMM_REGS:
16111 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
16113 case X86::VAARG_64:
16114 return EmitVAARG64WithCustomInserter(MI, BB);
16116 case X86::EH_SjLj_SetJmp32:
16117 case X86::EH_SjLj_SetJmp64:
16118 return emitEHSjLjSetJmp(MI, BB);
16120 case X86::EH_SjLj_LongJmp32:
16121 case X86::EH_SjLj_LongJmp64:
16122 return emitEHSjLjLongJmp(MI, BB);
16124 case TargetOpcode::STACKMAP:
16125 case TargetOpcode::PATCHPOINT:
16126 return emitPatchPoint(MI, BB);
16130 //===----------------------------------------------------------------------===//
16131 // X86 Optimization Hooks
16132 //===----------------------------------------------------------------------===//
16134 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
16137 const SelectionDAG &DAG,
16138 unsigned Depth) const {
16139 unsigned BitWidth = KnownZero.getBitWidth();
16140 unsigned Opc = Op.getOpcode();
16141 assert((Opc >= ISD::BUILTIN_OP_END ||
16142 Opc == ISD::INTRINSIC_WO_CHAIN ||
16143 Opc == ISD::INTRINSIC_W_CHAIN ||
16144 Opc == ISD::INTRINSIC_VOID) &&
16145 "Should use MaskedValueIsZero if you don't know whether Op"
16146 " is a target node!");
16148 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
16162 // These nodes' second result is a boolean.
16163 if (Op.getResNo() == 0)
16166 case X86ISD::SETCC:
16167 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
16169 case ISD::INTRINSIC_WO_CHAIN: {
16170 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16171 unsigned NumLoBits = 0;
16174 case Intrinsic::x86_sse_movmsk_ps:
16175 case Intrinsic::x86_avx_movmsk_ps_256:
16176 case Intrinsic::x86_sse2_movmsk_pd:
16177 case Intrinsic::x86_avx_movmsk_pd_256:
16178 case Intrinsic::x86_mmx_pmovmskb:
16179 case Intrinsic::x86_sse2_pmovmskb_128:
16180 case Intrinsic::x86_avx2_pmovmskb: {
16181 // High bits of movmskp{s|d}, pmovmskb are known zero.
16183 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16184 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
16185 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
16186 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
16187 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
16188 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
16189 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
16190 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
16192 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
16201 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
16202 unsigned Depth) const {
16203 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
16204 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
16205 return Op.getValueType().getScalarType().getSizeInBits();
16211 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
16212 /// node is a GlobalAddress + offset.
16213 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
16214 const GlobalValue* &GA,
16215 int64_t &Offset) const {
16216 if (N->getOpcode() == X86ISD::Wrapper) {
16217 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
16218 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
16219 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
16223 return TargetLowering::isGAPlusOffset(N, GA, Offset);
16226 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
16227 /// same as extracting the high 128-bit part of 256-bit vector and then
16228 /// inserting the result into the low part of a new 256-bit vector
16229 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
16230 EVT VT = SVOp->getValueType(0);
16231 unsigned NumElems = VT.getVectorNumElements();
16233 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
16234 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
16235 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
16236 SVOp->getMaskElt(j) >= 0)
16242 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
16243 /// same as extracting the low 128-bit part of 256-bit vector and then
16244 /// inserting the result into the high part of a new 256-bit vector
16245 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
16246 EVT VT = SVOp->getValueType(0);
16247 unsigned NumElems = VT.getVectorNumElements();
16249 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
16250 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
16251 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
16252 SVOp->getMaskElt(j) >= 0)
16258 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
16259 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
16260 TargetLowering::DAGCombinerInfo &DCI,
16261 const X86Subtarget* Subtarget) {
16263 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
16264 SDValue V1 = SVOp->getOperand(0);
16265 SDValue V2 = SVOp->getOperand(1);
16266 EVT VT = SVOp->getValueType(0);
16267 unsigned NumElems = VT.getVectorNumElements();
16269 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
16270 V2.getOpcode() == ISD::CONCAT_VECTORS) {
16274 // V UNDEF BUILD_VECTOR UNDEF
16276 // CONCAT_VECTOR CONCAT_VECTOR
16279 // RESULT: V + zero extended
16281 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
16282 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
16283 V1.getOperand(1).getOpcode() != ISD::UNDEF)
16286 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
16289 // To match the shuffle mask, the first half of the mask should
16290 // be exactly the first vector, and all the rest a splat with the
16291 // first element of the second one.
16292 for (unsigned i = 0; i != NumElems/2; ++i)
16293 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
16294 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
16297 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
16298 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
16299 if (Ld->hasNUsesOfValue(1, 0)) {
16300 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
16301 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
16303 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
16304 array_lengthof(Ops),
16306 Ld->getPointerInfo(),
16307 Ld->getAlignment(),
16308 false/*isVolatile*/, true/*ReadMem*/,
16309 false/*WriteMem*/);
16311 // Make sure the newly-created LOAD is in the same position as Ld in
16312 // terms of dependency. We create a TokenFactor for Ld and ResNode,
16313 // and update uses of Ld's output chain to use the TokenFactor.
16314 if (Ld->hasAnyUseOfValue(1)) {
16315 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
16316 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
16317 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
16318 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
16319 SDValue(ResNode.getNode(), 1));
16322 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
16326 // Emit a zeroed vector and insert the desired subvector on its
16328 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
16329 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
16330 return DCI.CombineTo(N, InsV);
16333 //===--------------------------------------------------------------------===//
16334 // Combine some shuffles into subvector extracts and inserts:
16337 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
16338 if (isShuffleHigh128VectorInsertLow(SVOp)) {
16339 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
16340 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
16341 return DCI.CombineTo(N, InsV);
16344 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
16345 if (isShuffleLow128VectorInsertHigh(SVOp)) {
16346 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
16347 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
16348 return DCI.CombineTo(N, InsV);
16354 /// PerformShuffleCombine - Performs several different shuffle combines.
16355 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
16356 TargetLowering::DAGCombinerInfo &DCI,
16357 const X86Subtarget *Subtarget) {
16359 EVT VT = N->getValueType(0);
16361 // Don't create instructions with illegal types after legalize types has run.
16362 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16363 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
16366 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
16367 if (Subtarget->hasFp256() && VT.is256BitVector() &&
16368 N->getOpcode() == ISD::VECTOR_SHUFFLE)
16369 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
16371 // Only handle 128 wide vector from here on.
16372 if (!VT.is128BitVector())
16375 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
16376 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
16377 // consecutive, non-overlapping, and in the right order.
16378 SmallVector<SDValue, 16> Elts;
16379 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
16380 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
16382 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG);
16385 /// PerformTruncateCombine - Converts truncate operation to
16386 /// a sequence of vector shuffle operations.
16387 /// It is possible when we truncate 256-bit vector to 128-bit vector
16388 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
16389 TargetLowering::DAGCombinerInfo &DCI,
16390 const X86Subtarget *Subtarget) {
16394 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
16395 /// specific shuffle of a load can be folded into a single element load.
16396 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
16397 /// shuffles have been customed lowered so we need to handle those here.
16398 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
16399 TargetLowering::DAGCombinerInfo &DCI) {
16400 if (DCI.isBeforeLegalizeOps())
16403 SDValue InVec = N->getOperand(0);
16404 SDValue EltNo = N->getOperand(1);
16406 if (!isa<ConstantSDNode>(EltNo))
16409 EVT VT = InVec.getValueType();
16411 bool HasShuffleIntoBitcast = false;
16412 if (InVec.getOpcode() == ISD::BITCAST) {
16413 // Don't duplicate a load with other uses.
16414 if (!InVec.hasOneUse())
16416 EVT BCVT = InVec.getOperand(0).getValueType();
16417 if (BCVT.getVectorNumElements() != VT.getVectorNumElements())
16419 InVec = InVec.getOperand(0);
16420 HasShuffleIntoBitcast = true;
16423 if (!isTargetShuffle(InVec.getOpcode()))
16426 // Don't duplicate a load with other uses.
16427 if (!InVec.hasOneUse())
16430 SmallVector<int, 16> ShuffleMask;
16432 if (!getTargetShuffleMask(InVec.getNode(), VT.getSimpleVT(), ShuffleMask,
16436 // Select the input vector, guarding against out of range extract vector.
16437 unsigned NumElems = VT.getVectorNumElements();
16438 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
16439 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
16440 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
16441 : InVec.getOperand(1);
16443 // If inputs to shuffle are the same for both ops, then allow 2 uses
16444 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
16446 if (LdNode.getOpcode() == ISD::BITCAST) {
16447 // Don't duplicate a load with other uses.
16448 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
16451 AllowedUses = 1; // only allow 1 load use if we have a bitcast
16452 LdNode = LdNode.getOperand(0);
16455 if (!ISD::isNormalLoad(LdNode.getNode()))
16458 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
16460 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
16463 if (HasShuffleIntoBitcast) {
16464 // If there's a bitcast before the shuffle, check if the load type and
16465 // alignment is valid.
16466 unsigned Align = LN0->getAlignment();
16467 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16468 unsigned NewAlign = TLI.getDataLayout()->
16469 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
16471 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
16475 // All checks match so transform back to vector_shuffle so that DAG combiner
16476 // can finish the job
16479 // Create shuffle node taking into account the case that its a unary shuffle
16480 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1);
16481 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl,
16482 InVec.getOperand(0), Shuffle,
16484 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
16485 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
16489 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
16490 /// generation and convert it from being a bunch of shuffles and extracts
16491 /// to a simple store and scalar loads to extract the elements.
16492 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
16493 TargetLowering::DAGCombinerInfo &DCI) {
16494 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
16495 if (NewOp.getNode())
16498 SDValue InputVector = N->getOperand(0);
16500 // Detect whether we are trying to convert from mmx to i32 and the bitcast
16501 // from mmx to v2i32 has a single usage.
16502 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
16503 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
16504 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
16505 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
16506 N->getValueType(0),
16507 InputVector.getNode()->getOperand(0));
16509 // Only operate on vectors of 4 elements, where the alternative shuffling
16510 // gets to be more expensive.
16511 if (InputVector.getValueType() != MVT::v4i32)
16514 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
16515 // single use which is a sign-extend or zero-extend, and all elements are
16517 SmallVector<SDNode *, 4> Uses;
16518 unsigned ExtractedElements = 0;
16519 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
16520 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
16521 if (UI.getUse().getResNo() != InputVector.getResNo())
16524 SDNode *Extract = *UI;
16525 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
16528 if (Extract->getValueType(0) != MVT::i32)
16530 if (!Extract->hasOneUse())
16532 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
16533 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
16535 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
16538 // Record which element was extracted.
16539 ExtractedElements |=
16540 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
16542 Uses.push_back(Extract);
16545 // If not all the elements were used, this may not be worthwhile.
16546 if (ExtractedElements != 15)
16549 // Ok, we've now decided to do the transformation.
16550 SDLoc dl(InputVector);
16552 // Store the value to a temporary stack slot.
16553 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
16554 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
16555 MachinePointerInfo(), false, false, 0);
16557 // Replace each use (extract) with a load of the appropriate element.
16558 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
16559 UE = Uses.end(); UI != UE; ++UI) {
16560 SDNode *Extract = *UI;
16562 // cOMpute the element's address.
16563 SDValue Idx = Extract->getOperand(1);
16565 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
16566 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
16567 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16568 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
16570 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
16571 StackPtr, OffsetVal);
16573 // Load the scalar.
16574 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
16575 ScalarAddr, MachinePointerInfo(),
16576 false, false, false, 0);
16578 // Replace the exact with the load.
16579 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
16582 // The replacement was made in place; don't return anything.
16586 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
16587 static std::pair<unsigned, bool>
16588 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
16589 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
16590 if (!VT.isVector())
16591 return std::make_pair(0, false);
16593 bool NeedSplit = false;
16594 switch (VT.getSimpleVT().SimpleTy) {
16595 default: return std::make_pair(0, false);
16599 if (!Subtarget->hasAVX2())
16601 if (!Subtarget->hasAVX())
16602 return std::make_pair(0, false);
16607 if (!Subtarget->hasSSE2())
16608 return std::make_pair(0, false);
16611 // SSE2 has only a small subset of the operations.
16612 bool hasUnsigned = Subtarget->hasSSE41() ||
16613 (Subtarget->hasSSE2() && VT == MVT::v16i8);
16614 bool hasSigned = Subtarget->hasSSE41() ||
16615 (Subtarget->hasSSE2() && VT == MVT::v8i16);
16617 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
16620 // Check for x CC y ? x : y.
16621 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
16622 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
16627 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
16630 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
16633 Opc = hasSigned ? X86ISD::SMIN : 0; break;
16636 Opc = hasSigned ? X86ISD::SMAX : 0; break;
16638 // Check for x CC y ? y : x -- a min/max with reversed arms.
16639 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
16640 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
16645 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
16648 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
16651 Opc = hasSigned ? X86ISD::SMAX : 0; break;
16654 Opc = hasSigned ? X86ISD::SMIN : 0; break;
16658 return std::make_pair(Opc, NeedSplit);
16661 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
16663 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
16664 TargetLowering::DAGCombinerInfo &DCI,
16665 const X86Subtarget *Subtarget) {
16667 SDValue Cond = N->getOperand(0);
16668 // Get the LHS/RHS of the select.
16669 SDValue LHS = N->getOperand(1);
16670 SDValue RHS = N->getOperand(2);
16671 EVT VT = LHS.getValueType();
16672 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16674 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
16675 // instructions match the semantics of the common C idiom x<y?x:y but not
16676 // x<=y?x:y, because of how they handle negative zero (which can be
16677 // ignored in unsafe-math mode).
16678 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
16679 VT != MVT::f80 && TLI.isTypeLegal(VT) &&
16680 (Subtarget->hasSSE2() ||
16681 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
16682 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
16684 unsigned Opcode = 0;
16685 // Check for x CC y ? x : y.
16686 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
16687 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
16691 // Converting this to a min would handle NaNs incorrectly, and swapping
16692 // the operands would cause it to handle comparisons between positive
16693 // and negative zero incorrectly.
16694 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
16695 if (!DAG.getTarget().Options.UnsafeFPMath &&
16696 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
16698 std::swap(LHS, RHS);
16700 Opcode = X86ISD::FMIN;
16703 // Converting this to a min would handle comparisons between positive
16704 // and negative zero incorrectly.
16705 if (!DAG.getTarget().Options.UnsafeFPMath &&
16706 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
16708 Opcode = X86ISD::FMIN;
16711 // Converting this to a min would handle both negative zeros and NaNs
16712 // incorrectly, but we can swap the operands to fix both.
16713 std::swap(LHS, RHS);
16717 Opcode = X86ISD::FMIN;
16721 // Converting this to a max would handle comparisons between positive
16722 // and negative zero incorrectly.
16723 if (!DAG.getTarget().Options.UnsafeFPMath &&
16724 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
16726 Opcode = X86ISD::FMAX;
16729 // Converting this to a max would handle NaNs incorrectly, and swapping
16730 // the operands would cause it to handle comparisons between positive
16731 // and negative zero incorrectly.
16732 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
16733 if (!DAG.getTarget().Options.UnsafeFPMath &&
16734 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
16736 std::swap(LHS, RHS);
16738 Opcode = X86ISD::FMAX;
16741 // Converting this to a max would handle both negative zeros and NaNs
16742 // incorrectly, but we can swap the operands to fix both.
16743 std::swap(LHS, RHS);
16747 Opcode = X86ISD::FMAX;
16750 // Check for x CC y ? y : x -- a min/max with reversed arms.
16751 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
16752 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
16756 // Converting this to a min would handle comparisons between positive
16757 // and negative zero incorrectly, and swapping the operands would
16758 // cause it to handle NaNs incorrectly.
16759 if (!DAG.getTarget().Options.UnsafeFPMath &&
16760 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
16761 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
16763 std::swap(LHS, RHS);
16765 Opcode = X86ISD::FMIN;
16768 // Converting this to a min would handle NaNs incorrectly.
16769 if (!DAG.getTarget().Options.UnsafeFPMath &&
16770 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
16772 Opcode = X86ISD::FMIN;
16775 // Converting this to a min would handle both negative zeros and NaNs
16776 // incorrectly, but we can swap the operands to fix both.
16777 std::swap(LHS, RHS);
16781 Opcode = X86ISD::FMIN;
16785 // Converting this to a max would handle NaNs incorrectly.
16786 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
16788 Opcode = X86ISD::FMAX;
16791 // Converting this to a max would handle comparisons between positive
16792 // and negative zero incorrectly, and swapping the operands would
16793 // cause it to handle NaNs incorrectly.
16794 if (!DAG.getTarget().Options.UnsafeFPMath &&
16795 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
16796 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
16798 std::swap(LHS, RHS);
16800 Opcode = X86ISD::FMAX;
16803 // Converting this to a max would handle both negative zeros and NaNs
16804 // incorrectly, but we can swap the operands to fix both.
16805 std::swap(LHS, RHS);
16809 Opcode = X86ISD::FMAX;
16815 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
16818 EVT CondVT = Cond.getValueType();
16819 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
16820 CondVT.getVectorElementType() == MVT::i1) {
16821 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
16822 // lowering on AVX-512. In this case we convert it to
16823 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
16824 // The same situation for all 128 and 256-bit vectors of i8 and i16
16825 EVT OpVT = LHS.getValueType();
16826 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
16827 (OpVT.getVectorElementType() == MVT::i8 ||
16828 OpVT.getVectorElementType() == MVT::i16)) {
16829 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
16830 DCI.AddToWorklist(Cond.getNode());
16831 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
16834 // If this is a select between two integer constants, try to do some
16836 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
16837 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
16838 // Don't do this for crazy integer types.
16839 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
16840 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
16841 // so that TrueC (the true value) is larger than FalseC.
16842 bool NeedsCondInvert = false;
16844 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
16845 // Efficiently invertible.
16846 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
16847 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
16848 isa<ConstantSDNode>(Cond.getOperand(1))))) {
16849 NeedsCondInvert = true;
16850 std::swap(TrueC, FalseC);
16853 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
16854 if (FalseC->getAPIntValue() == 0 &&
16855 TrueC->getAPIntValue().isPowerOf2()) {
16856 if (NeedsCondInvert) // Invert the condition if needed.
16857 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
16858 DAG.getConstant(1, Cond.getValueType()));
16860 // Zero extend the condition if needed.
16861 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
16863 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
16864 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
16865 DAG.getConstant(ShAmt, MVT::i8));
16868 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
16869 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
16870 if (NeedsCondInvert) // Invert the condition if needed.
16871 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
16872 DAG.getConstant(1, Cond.getValueType()));
16874 // Zero extend the condition if needed.
16875 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
16876 FalseC->getValueType(0), Cond);
16877 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
16878 SDValue(FalseC, 0));
16881 // Optimize cases that will turn into an LEA instruction. This requires
16882 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
16883 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
16884 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
16885 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
16887 bool isFastMultiplier = false;
16889 switch ((unsigned char)Diff) {
16891 case 1: // result = add base, cond
16892 case 2: // result = lea base( , cond*2)
16893 case 3: // result = lea base(cond, cond*2)
16894 case 4: // result = lea base( , cond*4)
16895 case 5: // result = lea base(cond, cond*4)
16896 case 8: // result = lea base( , cond*8)
16897 case 9: // result = lea base(cond, cond*8)
16898 isFastMultiplier = true;
16903 if (isFastMultiplier) {
16904 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
16905 if (NeedsCondInvert) // Invert the condition if needed.
16906 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
16907 DAG.getConstant(1, Cond.getValueType()));
16909 // Zero extend the condition if needed.
16910 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
16912 // Scale the condition by the difference.
16914 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
16915 DAG.getConstant(Diff, Cond.getValueType()));
16917 // Add the base if non-zero.
16918 if (FalseC->getAPIntValue() != 0)
16919 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
16920 SDValue(FalseC, 0));
16927 // Canonicalize max and min:
16928 // (x > y) ? x : y -> (x >= y) ? x : y
16929 // (x < y) ? x : y -> (x <= y) ? x : y
16930 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
16931 // the need for an extra compare
16932 // against zero. e.g.
16933 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
16935 // testl %edi, %edi
16937 // cmovgl %edi, %eax
16941 // cmovsl %eax, %edi
16942 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
16943 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
16944 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
16945 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
16950 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
16951 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
16952 Cond.getOperand(0), Cond.getOperand(1), NewCC);
16953 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
16958 // Early exit check
16959 if (!TLI.isTypeLegal(VT))
16962 // Match VSELECTs into subs with unsigned saturation.
16963 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
16964 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
16965 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
16966 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
16967 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
16969 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
16970 // left side invert the predicate to simplify logic below.
16972 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
16974 CC = ISD::getSetCCInverse(CC, true);
16975 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
16979 if (Other.getNode() && Other->getNumOperands() == 2 &&
16980 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
16981 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
16982 SDValue CondRHS = Cond->getOperand(1);
16984 // Look for a general sub with unsigned saturation first.
16985 // x >= y ? x-y : 0 --> subus x, y
16986 // x > y ? x-y : 0 --> subus x, y
16987 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
16988 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
16989 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
16991 // If the RHS is a constant we have to reverse the const canonicalization.
16992 // x > C-1 ? x+-C : 0 --> subus x, C
16993 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
16994 isSplatVector(CondRHS.getNode()) && isSplatVector(OpRHS.getNode())) {
16995 APInt A = cast<ConstantSDNode>(OpRHS.getOperand(0))->getAPIntValue();
16996 if (CondRHS.getConstantOperandVal(0) == -A-1)
16997 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS,
16998 DAG.getConstant(-A, VT));
17001 // Another special case: If C was a sign bit, the sub has been
17002 // canonicalized into a xor.
17003 // FIXME: Would it be better to use ComputeMaskedBits to determine whether
17004 // it's safe to decanonicalize the xor?
17005 // x s< 0 ? x^C : 0 --> subus x, C
17006 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
17007 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
17008 isSplatVector(OpRHS.getNode())) {
17009 APInt A = cast<ConstantSDNode>(OpRHS.getOperand(0))->getAPIntValue();
17011 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
17016 // Try to match a min/max vector operation.
17017 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
17018 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
17019 unsigned Opc = ret.first;
17020 bool NeedSplit = ret.second;
17022 if (Opc && NeedSplit) {
17023 unsigned NumElems = VT.getVectorNumElements();
17024 // Extract the LHS vectors
17025 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
17026 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
17028 // Extract the RHS vectors
17029 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
17030 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
17032 // Create min/max for each subvector
17033 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
17034 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
17036 // Merge the result
17037 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
17039 return DAG.getNode(Opc, DL, VT, LHS, RHS);
17042 // Simplify vector selection if the selector will be produced by CMPP*/PCMP*.
17043 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
17044 // Check if SETCC has already been promoted
17045 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT &&
17046 // Check that condition value type matches vselect operand type
17049 assert(Cond.getValueType().isVector() &&
17050 "vector select expects a vector selector!");
17052 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
17053 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
17055 if (!TValIsAllOnes && !FValIsAllZeros) {
17056 // Try invert the condition if true value is not all 1s and false value
17058 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
17059 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
17061 if (TValIsAllZeros || FValIsAllOnes) {
17062 SDValue CC = Cond.getOperand(2);
17063 ISD::CondCode NewCC =
17064 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
17065 Cond.getOperand(0).getValueType().isInteger());
17066 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
17067 std::swap(LHS, RHS);
17068 TValIsAllOnes = FValIsAllOnes;
17069 FValIsAllZeros = TValIsAllZeros;
17073 if (TValIsAllOnes || FValIsAllZeros) {
17076 if (TValIsAllOnes && FValIsAllZeros)
17078 else if (TValIsAllOnes)
17079 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
17080 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
17081 else if (FValIsAllZeros)
17082 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
17083 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
17085 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
17089 // If we know that this node is legal then we know that it is going to be
17090 // matched by one of the SSE/AVX BLEND instructions. These instructions only
17091 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
17092 // to simplify previous instructions.
17093 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
17094 !DCI.isBeforeLegalize() && TLI.isOperationLegal(ISD::VSELECT, VT)) {
17095 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
17097 // Don't optimize vector selects that map to mask-registers.
17101 // Check all uses of that condition operand to check whether it will be
17102 // consumed by non-BLEND instructions, which may depend on all bits are set
17104 for (SDNode::use_iterator I = Cond->use_begin(),
17105 E = Cond->use_end(); I != E; ++I)
17106 if (I->getOpcode() != ISD::VSELECT)
17107 // TODO: Add other opcodes eventually lowered into BLEND.
17110 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
17111 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
17113 APInt KnownZero, KnownOne;
17114 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
17115 DCI.isBeforeLegalizeOps());
17116 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
17117 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
17118 DCI.CommitTargetLoweringOpt(TLO);
17124 // Check whether a boolean test is testing a boolean value generated by
17125 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
17128 // Simplify the following patterns:
17129 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
17130 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
17131 // to (Op EFLAGS Cond)
17133 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
17134 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
17135 // to (Op EFLAGS !Cond)
17137 // where Op could be BRCOND or CMOV.
17139 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
17140 // Quit if not CMP and SUB with its value result used.
17141 if (Cmp.getOpcode() != X86ISD::CMP &&
17142 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
17145 // Quit if not used as a boolean value.
17146 if (CC != X86::COND_E && CC != X86::COND_NE)
17149 // Check CMP operands. One of them should be 0 or 1 and the other should be
17150 // an SetCC or extended from it.
17151 SDValue Op1 = Cmp.getOperand(0);
17152 SDValue Op2 = Cmp.getOperand(1);
17155 const ConstantSDNode* C = 0;
17156 bool needOppositeCond = (CC == X86::COND_E);
17157 bool checkAgainstTrue = false; // Is it a comparison against 1?
17159 if ((C = dyn_cast<ConstantSDNode>(Op1)))
17161 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
17163 else // Quit if all operands are not constants.
17166 if (C->getZExtValue() == 1) {
17167 needOppositeCond = !needOppositeCond;
17168 checkAgainstTrue = true;
17169 } else if (C->getZExtValue() != 0)
17170 // Quit if the constant is neither 0 or 1.
17173 bool truncatedToBoolWithAnd = false;
17174 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
17175 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
17176 SetCC.getOpcode() == ISD::TRUNCATE ||
17177 SetCC.getOpcode() == ISD::AND) {
17178 if (SetCC.getOpcode() == ISD::AND) {
17180 ConstantSDNode *CS;
17181 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
17182 CS->getZExtValue() == 1)
17184 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
17185 CS->getZExtValue() == 1)
17189 SetCC = SetCC.getOperand(OpIdx);
17190 truncatedToBoolWithAnd = true;
17192 SetCC = SetCC.getOperand(0);
17195 switch (SetCC.getOpcode()) {
17196 case X86ISD::SETCC_CARRY:
17197 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
17198 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
17199 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
17200 // truncated to i1 using 'and'.
17201 if (checkAgainstTrue && !truncatedToBoolWithAnd)
17203 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
17204 "Invalid use of SETCC_CARRY!");
17206 case X86ISD::SETCC:
17207 // Set the condition code or opposite one if necessary.
17208 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
17209 if (needOppositeCond)
17210 CC = X86::GetOppositeBranchCondition(CC);
17211 return SetCC.getOperand(1);
17212 case X86ISD::CMOV: {
17213 // Check whether false/true value has canonical one, i.e. 0 or 1.
17214 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
17215 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
17216 // Quit if true value is not a constant.
17219 // Quit if false value is not a constant.
17221 SDValue Op = SetCC.getOperand(0);
17222 // Skip 'zext' or 'trunc' node.
17223 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
17224 Op.getOpcode() == ISD::TRUNCATE)
17225 Op = Op.getOperand(0);
17226 // A special case for rdrand/rdseed, where 0 is set if false cond is
17228 if ((Op.getOpcode() != X86ISD::RDRAND &&
17229 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
17232 // Quit if false value is not the constant 0 or 1.
17233 bool FValIsFalse = true;
17234 if (FVal && FVal->getZExtValue() != 0) {
17235 if (FVal->getZExtValue() != 1)
17237 // If FVal is 1, opposite cond is needed.
17238 needOppositeCond = !needOppositeCond;
17239 FValIsFalse = false;
17241 // Quit if TVal is not the constant opposite of FVal.
17242 if (FValIsFalse && TVal->getZExtValue() != 1)
17244 if (!FValIsFalse && TVal->getZExtValue() != 0)
17246 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
17247 if (needOppositeCond)
17248 CC = X86::GetOppositeBranchCondition(CC);
17249 return SetCC.getOperand(3);
17256 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
17257 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
17258 TargetLowering::DAGCombinerInfo &DCI,
17259 const X86Subtarget *Subtarget) {
17262 // If the flag operand isn't dead, don't touch this CMOV.
17263 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
17266 SDValue FalseOp = N->getOperand(0);
17267 SDValue TrueOp = N->getOperand(1);
17268 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
17269 SDValue Cond = N->getOperand(3);
17271 if (CC == X86::COND_E || CC == X86::COND_NE) {
17272 switch (Cond.getOpcode()) {
17276 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
17277 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
17278 return (CC == X86::COND_E) ? FalseOp : TrueOp;
17284 Flags = checkBoolTestSetCCCombine(Cond, CC);
17285 if (Flags.getNode() &&
17286 // Extra check as FCMOV only supports a subset of X86 cond.
17287 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
17288 SDValue Ops[] = { FalseOp, TrueOp,
17289 DAG.getConstant(CC, MVT::i8), Flags };
17290 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(),
17291 Ops, array_lengthof(Ops));
17294 // If this is a select between two integer constants, try to do some
17295 // optimizations. Note that the operands are ordered the opposite of SELECT
17297 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
17298 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
17299 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
17300 // larger than FalseC (the false value).
17301 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
17302 CC = X86::GetOppositeBranchCondition(CC);
17303 std::swap(TrueC, FalseC);
17304 std::swap(TrueOp, FalseOp);
17307 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
17308 // This is efficient for any integer data type (including i8/i16) and
17310 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
17311 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
17312 DAG.getConstant(CC, MVT::i8), Cond);
17314 // Zero extend the condition if needed.
17315 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
17317 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
17318 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
17319 DAG.getConstant(ShAmt, MVT::i8));
17320 if (N->getNumValues() == 2) // Dead flag value?
17321 return DCI.CombineTo(N, Cond, SDValue());
17325 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
17326 // for any integer data type, including i8/i16.
17327 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
17328 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
17329 DAG.getConstant(CC, MVT::i8), Cond);
17331 // Zero extend the condition if needed.
17332 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
17333 FalseC->getValueType(0), Cond);
17334 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
17335 SDValue(FalseC, 0));
17337 if (N->getNumValues() == 2) // Dead flag value?
17338 return DCI.CombineTo(N, Cond, SDValue());
17342 // Optimize cases that will turn into an LEA instruction. This requires
17343 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
17344 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
17345 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
17346 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
17348 bool isFastMultiplier = false;
17350 switch ((unsigned char)Diff) {
17352 case 1: // result = add base, cond
17353 case 2: // result = lea base( , cond*2)
17354 case 3: // result = lea base(cond, cond*2)
17355 case 4: // result = lea base( , cond*4)
17356 case 5: // result = lea base(cond, cond*4)
17357 case 8: // result = lea base( , cond*8)
17358 case 9: // result = lea base(cond, cond*8)
17359 isFastMultiplier = true;
17364 if (isFastMultiplier) {
17365 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
17366 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
17367 DAG.getConstant(CC, MVT::i8), Cond);
17368 // Zero extend the condition if needed.
17369 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
17371 // Scale the condition by the difference.
17373 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
17374 DAG.getConstant(Diff, Cond.getValueType()));
17376 // Add the base if non-zero.
17377 if (FalseC->getAPIntValue() != 0)
17378 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
17379 SDValue(FalseC, 0));
17380 if (N->getNumValues() == 2) // Dead flag value?
17381 return DCI.CombineTo(N, Cond, SDValue());
17388 // Handle these cases:
17389 // (select (x != c), e, c) -> select (x != c), e, x),
17390 // (select (x == c), c, e) -> select (x == c), x, e)
17391 // where the c is an integer constant, and the "select" is the combination
17392 // of CMOV and CMP.
17394 // The rationale for this change is that the conditional-move from a constant
17395 // needs two instructions, however, conditional-move from a register needs
17396 // only one instruction.
17398 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
17399 // some instruction-combining opportunities. This opt needs to be
17400 // postponed as late as possible.
17402 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
17403 // the DCI.xxxx conditions are provided to postpone the optimization as
17404 // late as possible.
17406 ConstantSDNode *CmpAgainst = 0;
17407 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
17408 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
17409 !isa<ConstantSDNode>(Cond.getOperand(0))) {
17411 if (CC == X86::COND_NE &&
17412 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
17413 CC = X86::GetOppositeBranchCondition(CC);
17414 std::swap(TrueOp, FalseOp);
17417 if (CC == X86::COND_E &&
17418 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
17419 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
17420 DAG.getConstant(CC, MVT::i8), Cond };
17421 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops,
17422 array_lengthof(Ops));
17430 /// PerformMulCombine - Optimize a single multiply with constant into two
17431 /// in order to implement it with two cheaper instructions, e.g.
17432 /// LEA + SHL, LEA + LEA.
17433 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
17434 TargetLowering::DAGCombinerInfo &DCI) {
17435 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
17438 EVT VT = N->getValueType(0);
17439 if (VT != MVT::i64)
17442 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
17445 uint64_t MulAmt = C->getZExtValue();
17446 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
17449 uint64_t MulAmt1 = 0;
17450 uint64_t MulAmt2 = 0;
17451 if ((MulAmt % 9) == 0) {
17453 MulAmt2 = MulAmt / 9;
17454 } else if ((MulAmt % 5) == 0) {
17456 MulAmt2 = MulAmt / 5;
17457 } else if ((MulAmt % 3) == 0) {
17459 MulAmt2 = MulAmt / 3;
17462 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
17465 if (isPowerOf2_64(MulAmt2) &&
17466 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
17467 // If second multiplifer is pow2, issue it first. We want the multiply by
17468 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
17470 std::swap(MulAmt1, MulAmt2);
17473 if (isPowerOf2_64(MulAmt1))
17474 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
17475 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
17477 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
17478 DAG.getConstant(MulAmt1, VT));
17480 if (isPowerOf2_64(MulAmt2))
17481 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
17482 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
17484 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
17485 DAG.getConstant(MulAmt2, VT));
17487 // Do not add new nodes to DAG combiner worklist.
17488 DCI.CombineTo(N, NewMul, false);
17493 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
17494 SDValue N0 = N->getOperand(0);
17495 SDValue N1 = N->getOperand(1);
17496 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
17497 EVT VT = N0.getValueType();
17499 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
17500 // since the result of setcc_c is all zero's or all ones.
17501 if (VT.isInteger() && !VT.isVector() &&
17502 N1C && N0.getOpcode() == ISD::AND &&
17503 N0.getOperand(1).getOpcode() == ISD::Constant) {
17504 SDValue N00 = N0.getOperand(0);
17505 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
17506 ((N00.getOpcode() == ISD::ANY_EXTEND ||
17507 N00.getOpcode() == ISD::ZERO_EXTEND) &&
17508 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
17509 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
17510 APInt ShAmt = N1C->getAPIntValue();
17511 Mask = Mask.shl(ShAmt);
17513 return DAG.getNode(ISD::AND, SDLoc(N), VT,
17514 N00, DAG.getConstant(Mask, VT));
17518 // Hardware support for vector shifts is sparse which makes us scalarize the
17519 // vector operations in many cases. Also, on sandybridge ADD is faster than
17521 // (shl V, 1) -> add V,V
17522 if (isSplatVector(N1.getNode())) {
17523 assert(N0.getValueType().isVector() && "Invalid vector shift type");
17524 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1->getOperand(0));
17525 // We shift all of the values by one. In many cases we do not have
17526 // hardware support for this operation. This is better expressed as an ADD
17528 if (N1C && (1 == N1C->getZExtValue())) {
17529 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
17536 /// \brief Returns a vector of 0s if the node in input is a vector logical
17537 /// shift by a constant amount which is known to be bigger than or equal
17538 /// to the vector element size in bits.
17539 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
17540 const X86Subtarget *Subtarget) {
17541 EVT VT = N->getValueType(0);
17543 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
17544 (!Subtarget->hasInt256() ||
17545 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
17548 SDValue Amt = N->getOperand(1);
17550 if (isSplatVector(Amt.getNode())) {
17551 SDValue SclrAmt = Amt->getOperand(0);
17552 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
17553 APInt ShiftAmt = C->getAPIntValue();
17554 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
17556 // SSE2/AVX2 logical shifts always return a vector of 0s
17557 // if the shift amount is bigger than or equal to
17558 // the element size. The constant shift amount will be
17559 // encoded as a 8-bit immediate.
17560 if (ShiftAmt.trunc(8).uge(MaxAmount))
17561 return getZeroVector(VT, Subtarget, DAG, DL);
17568 /// PerformShiftCombine - Combine shifts.
17569 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
17570 TargetLowering::DAGCombinerInfo &DCI,
17571 const X86Subtarget *Subtarget) {
17572 if (N->getOpcode() == ISD::SHL) {
17573 SDValue V = PerformSHLCombine(N, DAG);
17574 if (V.getNode()) return V;
17577 if (N->getOpcode() != ISD::SRA) {
17578 // Try to fold this logical shift into a zero vector.
17579 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
17580 if (V.getNode()) return V;
17586 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
17587 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
17588 // and friends. Likewise for OR -> CMPNEQSS.
17589 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
17590 TargetLowering::DAGCombinerInfo &DCI,
17591 const X86Subtarget *Subtarget) {
17594 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
17595 // we're requiring SSE2 for both.
17596 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
17597 SDValue N0 = N->getOperand(0);
17598 SDValue N1 = N->getOperand(1);
17599 SDValue CMP0 = N0->getOperand(1);
17600 SDValue CMP1 = N1->getOperand(1);
17603 // The SETCCs should both refer to the same CMP.
17604 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
17607 SDValue CMP00 = CMP0->getOperand(0);
17608 SDValue CMP01 = CMP0->getOperand(1);
17609 EVT VT = CMP00.getValueType();
17611 if (VT == MVT::f32 || VT == MVT::f64) {
17612 bool ExpectingFlags = false;
17613 // Check for any users that want flags:
17614 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
17615 !ExpectingFlags && UI != UE; ++UI)
17616 switch (UI->getOpcode()) {
17621 ExpectingFlags = true;
17623 case ISD::CopyToReg:
17624 case ISD::SIGN_EXTEND:
17625 case ISD::ZERO_EXTEND:
17626 case ISD::ANY_EXTEND:
17630 if (!ExpectingFlags) {
17631 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
17632 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
17634 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
17635 X86::CondCode tmp = cc0;
17640 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
17641 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
17642 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
17643 // FIXME: need symbolic constants for these magic numbers.
17644 // See X86ATTInstPrinter.cpp:printSSECC().
17645 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
17646 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL, CMP00.getValueType(), CMP00, CMP01,
17647 DAG.getConstant(x86cc, MVT::i8));
17648 MVT IntVT = (is64BitFP ? MVT::i64 : MVT::i32);
17649 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT,
17651 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
17652 DAG.getConstant(1, IntVT));
17653 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
17654 return OneBitOfTruth;
17662 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
17663 /// so it can be folded inside ANDNP.
17664 static bool CanFoldXORWithAllOnes(const SDNode *N) {
17665 EVT VT = N->getValueType(0);
17667 // Match direct AllOnes for 128 and 256-bit vectors
17668 if (ISD::isBuildVectorAllOnes(N))
17671 // Look through a bit convert.
17672 if (N->getOpcode() == ISD::BITCAST)
17673 N = N->getOperand(0).getNode();
17675 // Sometimes the operand may come from a insert_subvector building a 256-bit
17677 if (VT.is256BitVector() &&
17678 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
17679 SDValue V1 = N->getOperand(0);
17680 SDValue V2 = N->getOperand(1);
17682 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
17683 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
17684 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
17685 ISD::isBuildVectorAllOnes(V2.getNode()))
17692 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
17693 // register. In most cases we actually compare or select YMM-sized registers
17694 // and mixing the two types creates horrible code. This method optimizes
17695 // some of the transition sequences.
17696 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
17697 TargetLowering::DAGCombinerInfo &DCI,
17698 const X86Subtarget *Subtarget) {
17699 EVT VT = N->getValueType(0);
17700 if (!VT.is256BitVector())
17703 assert((N->getOpcode() == ISD::ANY_EXTEND ||
17704 N->getOpcode() == ISD::ZERO_EXTEND ||
17705 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
17707 SDValue Narrow = N->getOperand(0);
17708 EVT NarrowVT = Narrow->getValueType(0);
17709 if (!NarrowVT.is128BitVector())
17712 if (Narrow->getOpcode() != ISD::XOR &&
17713 Narrow->getOpcode() != ISD::AND &&
17714 Narrow->getOpcode() != ISD::OR)
17717 SDValue N0 = Narrow->getOperand(0);
17718 SDValue N1 = Narrow->getOperand(1);
17721 // The Left side has to be a trunc.
17722 if (N0.getOpcode() != ISD::TRUNCATE)
17725 // The type of the truncated inputs.
17726 EVT WideVT = N0->getOperand(0)->getValueType(0);
17730 // The right side has to be a 'trunc' or a constant vector.
17731 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
17732 bool RHSConst = (isSplatVector(N1.getNode()) &&
17733 isa<ConstantSDNode>(N1->getOperand(0)));
17734 if (!RHSTrunc && !RHSConst)
17737 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17739 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
17742 // Set N0 and N1 to hold the inputs to the new wide operation.
17743 N0 = N0->getOperand(0);
17745 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
17746 N1->getOperand(0));
17747 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
17748 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, &C[0], C.size());
17749 } else if (RHSTrunc) {
17750 N1 = N1->getOperand(0);
17753 // Generate the wide operation.
17754 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
17755 unsigned Opcode = N->getOpcode();
17757 case ISD::ANY_EXTEND:
17759 case ISD::ZERO_EXTEND: {
17760 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
17761 APInt Mask = APInt::getAllOnesValue(InBits);
17762 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
17763 return DAG.getNode(ISD::AND, DL, VT,
17764 Op, DAG.getConstant(Mask, VT));
17766 case ISD::SIGN_EXTEND:
17767 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
17768 Op, DAG.getValueType(NarrowVT));
17770 llvm_unreachable("Unexpected opcode");
17774 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
17775 TargetLowering::DAGCombinerInfo &DCI,
17776 const X86Subtarget *Subtarget) {
17777 EVT VT = N->getValueType(0);
17778 if (DCI.isBeforeLegalizeOps())
17781 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
17785 // Create BLSI, BLSR, and BZHI instructions
17786 // BLSI is X & (-X)
17787 // BLSR is X & (X-1)
17788 // BZHI is X & ((1 << Y) - 1)
17789 // BEXTR is ((X >> imm) & (2**size-1))
17790 if (VT == MVT::i32 || VT == MVT::i64) {
17791 SDValue N0 = N->getOperand(0);
17792 SDValue N1 = N->getOperand(1);
17795 if (Subtarget->hasBMI()) {
17796 // Check LHS for neg
17797 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1) == N1 &&
17798 isZero(N0.getOperand(0)))
17799 return DAG.getNode(X86ISD::BLSI, DL, VT, N1);
17801 // Check RHS for neg
17802 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1) == N0 &&
17803 isZero(N1.getOperand(0)))
17804 return DAG.getNode(X86ISD::BLSI, DL, VT, N0);
17806 // Check LHS for X-1
17807 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
17808 isAllOnes(N0.getOperand(1)))
17809 return DAG.getNode(X86ISD::BLSR, DL, VT, N1);
17811 // Check RHS for X-1
17812 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
17813 isAllOnes(N1.getOperand(1)))
17814 return DAG.getNode(X86ISD::BLSR, DL, VT, N0);
17817 if (Subtarget->hasBMI2()) {
17818 // Check for (and (add (shl 1, Y), -1), X)
17819 if (N0.getOpcode() == ISD::ADD && isAllOnes(N0.getOperand(1))) {
17820 SDValue N00 = N0.getOperand(0);
17821 if (N00.getOpcode() == ISD::SHL) {
17822 SDValue N001 = N00.getOperand(1);
17823 assert(N001.getValueType() == MVT::i8 && "unexpected type");
17824 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N00.getOperand(0));
17825 if (C && C->getZExtValue() == 1)
17826 return DAG.getNode(X86ISD::BZHI, DL, VT, N1, N001);
17830 // Check for (and X, (add (shl 1, Y), -1))
17831 if (N1.getOpcode() == ISD::ADD && isAllOnes(N1.getOperand(1))) {
17832 SDValue N10 = N1.getOperand(0);
17833 if (N10.getOpcode() == ISD::SHL) {
17834 SDValue N101 = N10.getOperand(1);
17835 assert(N101.getValueType() == MVT::i8 && "unexpected type");
17836 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N10.getOperand(0));
17837 if (C && C->getZExtValue() == 1)
17838 return DAG.getNode(X86ISD::BZHI, DL, VT, N0, N101);
17843 // Check for BEXTR.
17844 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
17845 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
17846 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
17847 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
17848 if (MaskNode && ShiftNode) {
17849 uint64_t Mask = MaskNode->getZExtValue();
17850 uint64_t Shift = ShiftNode->getZExtValue();
17851 if (isMask_64(Mask)) {
17852 uint64_t MaskSize = CountPopulation_64(Mask);
17853 if (Shift + MaskSize <= VT.getSizeInBits())
17854 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
17855 DAG.getConstant(Shift | (MaskSize << 8), VT));
17863 // Want to form ANDNP nodes:
17864 // 1) In the hopes of then easily combining them with OR and AND nodes
17865 // to form PBLEND/PSIGN.
17866 // 2) To match ANDN packed intrinsics
17867 if (VT != MVT::v2i64 && VT != MVT::v4i64)
17870 SDValue N0 = N->getOperand(0);
17871 SDValue N1 = N->getOperand(1);
17874 // Check LHS for vnot
17875 if (N0.getOpcode() == ISD::XOR &&
17876 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
17877 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
17878 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
17880 // Check RHS for vnot
17881 if (N1.getOpcode() == ISD::XOR &&
17882 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
17883 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
17884 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
17889 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
17890 TargetLowering::DAGCombinerInfo &DCI,
17891 const X86Subtarget *Subtarget) {
17892 EVT VT = N->getValueType(0);
17893 if (DCI.isBeforeLegalizeOps())
17896 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
17900 SDValue N0 = N->getOperand(0);
17901 SDValue N1 = N->getOperand(1);
17903 // look for psign/blend
17904 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
17905 if (!Subtarget->hasSSSE3() ||
17906 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
17909 // Canonicalize pandn to RHS
17910 if (N0.getOpcode() == X86ISD::ANDNP)
17912 // or (and (m, y), (pandn m, x))
17913 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
17914 SDValue Mask = N1.getOperand(0);
17915 SDValue X = N1.getOperand(1);
17917 if (N0.getOperand(0) == Mask)
17918 Y = N0.getOperand(1);
17919 if (N0.getOperand(1) == Mask)
17920 Y = N0.getOperand(0);
17922 // Check to see if the mask appeared in both the AND and ANDNP and
17926 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
17927 // Look through mask bitcast.
17928 if (Mask.getOpcode() == ISD::BITCAST)
17929 Mask = Mask.getOperand(0);
17930 if (X.getOpcode() == ISD::BITCAST)
17931 X = X.getOperand(0);
17932 if (Y.getOpcode() == ISD::BITCAST)
17933 Y = Y.getOperand(0);
17935 EVT MaskVT = Mask.getValueType();
17937 // Validate that the Mask operand is a vector sra node.
17938 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
17939 // there is no psrai.b
17940 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
17941 unsigned SraAmt = ~0;
17942 if (Mask.getOpcode() == ISD::SRA) {
17943 SDValue Amt = Mask.getOperand(1);
17944 if (isSplatVector(Amt.getNode())) {
17945 SDValue SclrAmt = Amt->getOperand(0);
17946 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt))
17947 SraAmt = C->getZExtValue();
17949 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
17950 SDValue SraC = Mask.getOperand(1);
17951 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
17953 if ((SraAmt + 1) != EltBits)
17958 // Now we know we at least have a plendvb with the mask val. See if
17959 // we can form a psignb/w/d.
17960 // psign = x.type == y.type == mask.type && y = sub(0, x);
17961 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
17962 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
17963 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
17964 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
17965 "Unsupported VT for PSIGN");
17966 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
17967 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
17969 // PBLENDVB only available on SSE 4.1
17970 if (!Subtarget->hasSSE41())
17973 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
17975 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
17976 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
17977 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
17978 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
17979 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
17983 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
17986 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
17987 MachineFunction &MF = DAG.getMachineFunction();
17988 bool OptForSize = MF.getFunction()->getAttributes().
17989 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
17991 // SHLD/SHRD instructions have lower register pressure, but on some
17992 // platforms they have higher latency than the equivalent
17993 // series of shifts/or that would otherwise be generated.
17994 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
17995 // have higher latencies and we are not optimizing for size.
17996 if (!OptForSize && Subtarget->isSHLDSlow())
17999 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
18001 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
18003 if (!N0.hasOneUse() || !N1.hasOneUse())
18006 SDValue ShAmt0 = N0.getOperand(1);
18007 if (ShAmt0.getValueType() != MVT::i8)
18009 SDValue ShAmt1 = N1.getOperand(1);
18010 if (ShAmt1.getValueType() != MVT::i8)
18012 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
18013 ShAmt0 = ShAmt0.getOperand(0);
18014 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
18015 ShAmt1 = ShAmt1.getOperand(0);
18018 unsigned Opc = X86ISD::SHLD;
18019 SDValue Op0 = N0.getOperand(0);
18020 SDValue Op1 = N1.getOperand(0);
18021 if (ShAmt0.getOpcode() == ISD::SUB) {
18022 Opc = X86ISD::SHRD;
18023 std::swap(Op0, Op1);
18024 std::swap(ShAmt0, ShAmt1);
18027 unsigned Bits = VT.getSizeInBits();
18028 if (ShAmt1.getOpcode() == ISD::SUB) {
18029 SDValue Sum = ShAmt1.getOperand(0);
18030 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
18031 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
18032 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
18033 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
18034 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
18035 return DAG.getNode(Opc, DL, VT,
18037 DAG.getNode(ISD::TRUNCATE, DL,
18040 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
18041 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
18043 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
18044 return DAG.getNode(Opc, DL, VT,
18045 N0.getOperand(0), N1.getOperand(0),
18046 DAG.getNode(ISD::TRUNCATE, DL,
18053 // Generate NEG and CMOV for integer abs.
18054 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
18055 EVT VT = N->getValueType(0);
18057 // Since X86 does not have CMOV for 8-bit integer, we don't convert
18058 // 8-bit integer abs to NEG and CMOV.
18059 if (VT.isInteger() && VT.getSizeInBits() == 8)
18062 SDValue N0 = N->getOperand(0);
18063 SDValue N1 = N->getOperand(1);
18066 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
18067 // and change it to SUB and CMOV.
18068 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
18069 N0.getOpcode() == ISD::ADD &&
18070 N0.getOperand(1) == N1 &&
18071 N1.getOpcode() == ISD::SRA &&
18072 N1.getOperand(0) == N0.getOperand(0))
18073 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
18074 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
18075 // Generate SUB & CMOV.
18076 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
18077 DAG.getConstant(0, VT), N0.getOperand(0));
18079 SDValue Ops[] = { N0.getOperand(0), Neg,
18080 DAG.getConstant(X86::COND_GE, MVT::i8),
18081 SDValue(Neg.getNode(), 1) };
18082 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue),
18083 Ops, array_lengthof(Ops));
18088 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
18089 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
18090 TargetLowering::DAGCombinerInfo &DCI,
18091 const X86Subtarget *Subtarget) {
18092 EVT VT = N->getValueType(0);
18093 if (DCI.isBeforeLegalizeOps())
18096 if (Subtarget->hasCMov()) {
18097 SDValue RV = performIntegerAbsCombine(N, DAG);
18102 // Try forming BMI if it is available.
18103 if (!Subtarget->hasBMI())
18106 if (VT != MVT::i32 && VT != MVT::i64)
18109 assert(Subtarget->hasBMI() && "Creating BLSMSK requires BMI instructions");
18111 // Create BLSMSK instructions by finding X ^ (X-1)
18112 SDValue N0 = N->getOperand(0);
18113 SDValue N1 = N->getOperand(1);
18116 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
18117 isAllOnes(N0.getOperand(1)))
18118 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N1);
18120 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
18121 isAllOnes(N1.getOperand(1)))
18122 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N0);
18127 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
18128 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
18129 TargetLowering::DAGCombinerInfo &DCI,
18130 const X86Subtarget *Subtarget) {
18131 LoadSDNode *Ld = cast<LoadSDNode>(N);
18132 EVT RegVT = Ld->getValueType(0);
18133 EVT MemVT = Ld->getMemoryVT();
18135 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18136 unsigned RegSz = RegVT.getSizeInBits();
18138 // On Sandybridge unaligned 256bit loads are inefficient.
18139 ISD::LoadExtType Ext = Ld->getExtensionType();
18140 unsigned Alignment = Ld->getAlignment();
18141 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
18142 if (RegVT.is256BitVector() && !Subtarget->hasInt256() &&
18143 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
18144 unsigned NumElems = RegVT.getVectorNumElements();
18148 SDValue Ptr = Ld->getBasePtr();
18149 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
18151 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
18153 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
18154 Ld->getPointerInfo(), Ld->isVolatile(),
18155 Ld->isNonTemporal(), Ld->isInvariant(),
18157 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
18158 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
18159 Ld->getPointerInfo(), Ld->isVolatile(),
18160 Ld->isNonTemporal(), Ld->isInvariant(),
18161 std::min(16U, Alignment));
18162 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
18164 Load2.getValue(1));
18166 SDValue NewVec = DAG.getUNDEF(RegVT);
18167 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
18168 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
18169 return DCI.CombineTo(N, NewVec, TF, true);
18172 // If this is a vector EXT Load then attempt to optimize it using a
18173 // shuffle. If SSSE3 is not available we may emit an illegal shuffle but the
18174 // expansion is still better than scalar code.
18175 // We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise we'll
18176 // emit a shuffle and a arithmetic shift.
18177 // TODO: It is possible to support ZExt by zeroing the undef values
18178 // during the shuffle phase or after the shuffle.
18179 if (RegVT.isVector() && RegVT.isInteger() && Subtarget->hasSSE2() &&
18180 (Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)) {
18181 assert(MemVT != RegVT && "Cannot extend to the same type");
18182 assert(MemVT.isVector() && "Must load a vector from memory");
18184 unsigned NumElems = RegVT.getVectorNumElements();
18185 unsigned MemSz = MemVT.getSizeInBits();
18186 assert(RegSz > MemSz && "Register size must be greater than the mem size");
18188 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256())
18191 // All sizes must be a power of two.
18192 if (!isPowerOf2_32(RegSz * MemSz * NumElems))
18195 // Attempt to load the original value using scalar loads.
18196 // Find the largest scalar type that divides the total loaded size.
18197 MVT SclrLoadTy = MVT::i8;
18198 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
18199 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
18200 MVT Tp = (MVT::SimpleValueType)tp;
18201 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
18206 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
18207 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
18209 SclrLoadTy = MVT::f64;
18211 // Calculate the number of scalar loads that we need to perform
18212 // in order to load our vector from memory.
18213 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
18214 if (Ext == ISD::SEXTLOAD && NumLoads > 1)
18217 unsigned loadRegZize = RegSz;
18218 if (Ext == ISD::SEXTLOAD && RegSz == 256)
18221 // Represent our vector as a sequence of elements which are the
18222 // largest scalar that we can load.
18223 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy,
18224 loadRegZize/SclrLoadTy.getSizeInBits());
18226 // Represent the data using the same element type that is stored in
18227 // memory. In practice, we ''widen'' MemVT.
18229 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
18230 loadRegZize/MemVT.getScalarType().getSizeInBits());
18232 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
18233 "Invalid vector type");
18235 // We can't shuffle using an illegal type.
18236 if (!TLI.isTypeLegal(WideVecVT))
18239 SmallVector<SDValue, 8> Chains;
18240 SDValue Ptr = Ld->getBasePtr();
18241 SDValue Increment = DAG.getConstant(SclrLoadTy.getSizeInBits()/8,
18242 TLI.getPointerTy());
18243 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
18245 for (unsigned i = 0; i < NumLoads; ++i) {
18246 // Perform a single load.
18247 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(),
18248 Ptr, Ld->getPointerInfo(),
18249 Ld->isVolatile(), Ld->isNonTemporal(),
18250 Ld->isInvariant(), Ld->getAlignment());
18251 Chains.push_back(ScalarLoad.getValue(1));
18252 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
18253 // another round of DAGCombining.
18255 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
18257 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
18258 ScalarLoad, DAG.getIntPtrConstant(i));
18260 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
18263 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
18266 // Bitcast the loaded value to a vector of the original element type, in
18267 // the size of the target vector type.
18268 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
18269 unsigned SizeRatio = RegSz/MemSz;
18271 if (Ext == ISD::SEXTLOAD) {
18272 // If we have SSE4.1 we can directly emit a VSEXT node.
18273 if (Subtarget->hasSSE41()) {
18274 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
18275 return DCI.CombineTo(N, Sext, TF, true);
18278 // Otherwise we'll shuffle the small elements in the high bits of the
18279 // larger type and perform an arithmetic shift. If the shift is not legal
18280 // it's better to scalarize.
18281 if (!TLI.isOperationLegalOrCustom(ISD::SRA, RegVT))
18284 // Redistribute the loaded elements into the different locations.
18285 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
18286 for (unsigned i = 0; i != NumElems; ++i)
18287 ShuffleVec[i*SizeRatio + SizeRatio-1] = i;
18289 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
18290 DAG.getUNDEF(WideVecVT),
18293 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
18295 // Build the arithmetic shift.
18296 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
18297 MemVT.getVectorElementType().getSizeInBits();
18298 Shuff = DAG.getNode(ISD::SRA, dl, RegVT, Shuff,
18299 DAG.getConstant(Amt, RegVT));
18301 return DCI.CombineTo(N, Shuff, TF, true);
18304 // Redistribute the loaded elements into the different locations.
18305 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
18306 for (unsigned i = 0; i != NumElems; ++i)
18307 ShuffleVec[i*SizeRatio] = i;
18309 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
18310 DAG.getUNDEF(WideVecVT),
18313 // Bitcast to the requested type.
18314 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
18315 // Replace the original load with the new sequence
18316 // and return the new chain.
18317 return DCI.CombineTo(N, Shuff, TF, true);
18323 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
18324 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
18325 const X86Subtarget *Subtarget) {
18326 StoreSDNode *St = cast<StoreSDNode>(N);
18327 EVT VT = St->getValue().getValueType();
18328 EVT StVT = St->getMemoryVT();
18330 SDValue StoredVal = St->getOperand(1);
18331 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18333 // If we are saving a concatenation of two XMM registers, perform two stores.
18334 // On Sandy Bridge, 256-bit memory operations are executed by two
18335 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit
18336 // memory operation.
18337 unsigned Alignment = St->getAlignment();
18338 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
18339 if (VT.is256BitVector() && !Subtarget->hasInt256() &&
18340 StVT == VT && !IsAligned) {
18341 unsigned NumElems = VT.getVectorNumElements();
18345 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
18346 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
18348 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
18349 SDValue Ptr0 = St->getBasePtr();
18350 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
18352 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
18353 St->getPointerInfo(), St->isVolatile(),
18354 St->isNonTemporal(), Alignment);
18355 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
18356 St->getPointerInfo(), St->isVolatile(),
18357 St->isNonTemporal(),
18358 std::min(16U, Alignment));
18359 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
18362 // Optimize trunc store (of multiple scalars) to shuffle and store.
18363 // First, pack all of the elements in one place. Next, store to memory
18364 // in fewer chunks.
18365 if (St->isTruncatingStore() && VT.isVector()) {
18366 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18367 unsigned NumElems = VT.getVectorNumElements();
18368 assert(StVT != VT && "Cannot truncate to the same type");
18369 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
18370 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
18372 // From, To sizes and ElemCount must be pow of two
18373 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
18374 // We are going to use the original vector elt for storing.
18375 // Accumulated smaller vector elements must be a multiple of the store size.
18376 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
18378 unsigned SizeRatio = FromSz / ToSz;
18380 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
18382 // Create a type on which we perform the shuffle
18383 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
18384 StVT.getScalarType(), NumElems*SizeRatio);
18386 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
18388 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
18389 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
18390 for (unsigned i = 0; i != NumElems; ++i)
18391 ShuffleVec[i] = i * SizeRatio;
18393 // Can't shuffle using an illegal type.
18394 if (!TLI.isTypeLegal(WideVecVT))
18397 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
18398 DAG.getUNDEF(WideVecVT),
18400 // At this point all of the data is stored at the bottom of the
18401 // register. We now need to save it to mem.
18403 // Find the largest store unit
18404 MVT StoreType = MVT::i8;
18405 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
18406 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
18407 MVT Tp = (MVT::SimpleValueType)tp;
18408 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
18412 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
18413 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
18414 (64 <= NumElems * ToSz))
18415 StoreType = MVT::f64;
18417 // Bitcast the original vector into a vector of store-size units
18418 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
18419 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
18420 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
18421 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
18422 SmallVector<SDValue, 8> Chains;
18423 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
18424 TLI.getPointerTy());
18425 SDValue Ptr = St->getBasePtr();
18427 // Perform one or more big stores into memory.
18428 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
18429 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
18430 StoreType, ShuffWide,
18431 DAG.getIntPtrConstant(i));
18432 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
18433 St->getPointerInfo(), St->isVolatile(),
18434 St->isNonTemporal(), St->getAlignment());
18435 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
18436 Chains.push_back(Ch);
18439 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
18443 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
18444 // the FP state in cases where an emms may be missing.
18445 // A preferable solution to the general problem is to figure out the right
18446 // places to insert EMMS. This qualifies as a quick hack.
18448 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
18449 if (VT.getSizeInBits() != 64)
18452 const Function *F = DAG.getMachineFunction().getFunction();
18453 bool NoImplicitFloatOps = F->getAttributes().
18454 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
18455 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
18456 && Subtarget->hasSSE2();
18457 if ((VT.isVector() ||
18458 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
18459 isa<LoadSDNode>(St->getValue()) &&
18460 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
18461 St->getChain().hasOneUse() && !St->isVolatile()) {
18462 SDNode* LdVal = St->getValue().getNode();
18463 LoadSDNode *Ld = 0;
18464 int TokenFactorIndex = -1;
18465 SmallVector<SDValue, 8> Ops;
18466 SDNode* ChainVal = St->getChain().getNode();
18467 // Must be a store of a load. We currently handle two cases: the load
18468 // is a direct child, and it's under an intervening TokenFactor. It is
18469 // possible to dig deeper under nested TokenFactors.
18470 if (ChainVal == LdVal)
18471 Ld = cast<LoadSDNode>(St->getChain());
18472 else if (St->getValue().hasOneUse() &&
18473 ChainVal->getOpcode() == ISD::TokenFactor) {
18474 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
18475 if (ChainVal->getOperand(i).getNode() == LdVal) {
18476 TokenFactorIndex = i;
18477 Ld = cast<LoadSDNode>(St->getValue());
18479 Ops.push_back(ChainVal->getOperand(i));
18483 if (!Ld || !ISD::isNormalLoad(Ld))
18486 // If this is not the MMX case, i.e. we are just turning i64 load/store
18487 // into f64 load/store, avoid the transformation if there are multiple
18488 // uses of the loaded value.
18489 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
18494 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
18495 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
18497 if (Subtarget->is64Bit() || F64IsLegal) {
18498 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
18499 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
18500 Ld->getPointerInfo(), Ld->isVolatile(),
18501 Ld->isNonTemporal(), Ld->isInvariant(),
18502 Ld->getAlignment());
18503 SDValue NewChain = NewLd.getValue(1);
18504 if (TokenFactorIndex != -1) {
18505 Ops.push_back(NewChain);
18506 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
18509 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
18510 St->getPointerInfo(),
18511 St->isVolatile(), St->isNonTemporal(),
18512 St->getAlignment());
18515 // Otherwise, lower to two pairs of 32-bit loads / stores.
18516 SDValue LoAddr = Ld->getBasePtr();
18517 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
18518 DAG.getConstant(4, MVT::i32));
18520 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
18521 Ld->getPointerInfo(),
18522 Ld->isVolatile(), Ld->isNonTemporal(),
18523 Ld->isInvariant(), Ld->getAlignment());
18524 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
18525 Ld->getPointerInfo().getWithOffset(4),
18526 Ld->isVolatile(), Ld->isNonTemporal(),
18528 MinAlign(Ld->getAlignment(), 4));
18530 SDValue NewChain = LoLd.getValue(1);
18531 if (TokenFactorIndex != -1) {
18532 Ops.push_back(LoLd);
18533 Ops.push_back(HiLd);
18534 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
18538 LoAddr = St->getBasePtr();
18539 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
18540 DAG.getConstant(4, MVT::i32));
18542 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
18543 St->getPointerInfo(),
18544 St->isVolatile(), St->isNonTemporal(),
18545 St->getAlignment());
18546 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
18547 St->getPointerInfo().getWithOffset(4),
18549 St->isNonTemporal(),
18550 MinAlign(St->getAlignment(), 4));
18551 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
18556 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
18557 /// and return the operands for the horizontal operation in LHS and RHS. A
18558 /// horizontal operation performs the binary operation on successive elements
18559 /// of its first operand, then on successive elements of its second operand,
18560 /// returning the resulting values in a vector. For example, if
18561 /// A = < float a0, float a1, float a2, float a3 >
18563 /// B = < float b0, float b1, float b2, float b3 >
18564 /// then the result of doing a horizontal operation on A and B is
18565 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
18566 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
18567 /// A horizontal-op B, for some already available A and B, and if so then LHS is
18568 /// set to A, RHS to B, and the routine returns 'true'.
18569 /// Note that the binary operation should have the property that if one of the
18570 /// operands is UNDEF then the result is UNDEF.
18571 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
18572 // Look for the following pattern: if
18573 // A = < float a0, float a1, float a2, float a3 >
18574 // B = < float b0, float b1, float b2, float b3 >
18576 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
18577 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
18578 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
18579 // which is A horizontal-op B.
18581 // At least one of the operands should be a vector shuffle.
18582 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
18583 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
18586 MVT VT = LHS.getSimpleValueType();
18588 assert((VT.is128BitVector() || VT.is256BitVector()) &&
18589 "Unsupported vector type for horizontal add/sub");
18591 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
18592 // operate independently on 128-bit lanes.
18593 unsigned NumElts = VT.getVectorNumElements();
18594 unsigned NumLanes = VT.getSizeInBits()/128;
18595 unsigned NumLaneElts = NumElts / NumLanes;
18596 assert((NumLaneElts % 2 == 0) &&
18597 "Vector type should have an even number of elements in each lane");
18598 unsigned HalfLaneElts = NumLaneElts/2;
18600 // View LHS in the form
18601 // LHS = VECTOR_SHUFFLE A, B, LMask
18602 // If LHS is not a shuffle then pretend it is the shuffle
18603 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
18604 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
18607 SmallVector<int, 16> LMask(NumElts);
18608 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
18609 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
18610 A = LHS.getOperand(0);
18611 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
18612 B = LHS.getOperand(1);
18613 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
18614 std::copy(Mask.begin(), Mask.end(), LMask.begin());
18616 if (LHS.getOpcode() != ISD::UNDEF)
18618 for (unsigned i = 0; i != NumElts; ++i)
18622 // Likewise, view RHS in the form
18623 // RHS = VECTOR_SHUFFLE C, D, RMask
18625 SmallVector<int, 16> RMask(NumElts);
18626 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
18627 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
18628 C = RHS.getOperand(0);
18629 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
18630 D = RHS.getOperand(1);
18631 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
18632 std::copy(Mask.begin(), Mask.end(), RMask.begin());
18634 if (RHS.getOpcode() != ISD::UNDEF)
18636 for (unsigned i = 0; i != NumElts; ++i)
18640 // Check that the shuffles are both shuffling the same vectors.
18641 if (!(A == C && B == D) && !(A == D && B == C))
18644 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
18645 if (!A.getNode() && !B.getNode())
18648 // If A and B occur in reverse order in RHS, then "swap" them (which means
18649 // rewriting the mask).
18651 CommuteVectorShuffleMask(RMask, NumElts);
18653 // At this point LHS and RHS are equivalent to
18654 // LHS = VECTOR_SHUFFLE A, B, LMask
18655 // RHS = VECTOR_SHUFFLE A, B, RMask
18656 // Check that the masks correspond to performing a horizontal operation.
18657 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
18658 for (unsigned i = 0; i != NumLaneElts; ++i) {
18659 int LIdx = LMask[i+l], RIdx = RMask[i+l];
18661 // Ignore any UNDEF components.
18662 if (LIdx < 0 || RIdx < 0 ||
18663 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
18664 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
18667 // Check that successive elements are being operated on. If not, this is
18668 // not a horizontal operation.
18669 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
18670 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
18671 if (!(LIdx == Index && RIdx == Index + 1) &&
18672 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
18677 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
18678 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
18682 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
18683 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
18684 const X86Subtarget *Subtarget) {
18685 EVT VT = N->getValueType(0);
18686 SDValue LHS = N->getOperand(0);
18687 SDValue RHS = N->getOperand(1);
18689 // Try to synthesize horizontal adds from adds of shuffles.
18690 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
18691 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
18692 isHorizontalBinOp(LHS, RHS, true))
18693 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
18697 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
18698 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
18699 const X86Subtarget *Subtarget) {
18700 EVT VT = N->getValueType(0);
18701 SDValue LHS = N->getOperand(0);
18702 SDValue RHS = N->getOperand(1);
18704 // Try to synthesize horizontal subs from subs of shuffles.
18705 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
18706 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
18707 isHorizontalBinOp(LHS, RHS, false))
18708 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
18712 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
18713 /// X86ISD::FXOR nodes.
18714 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
18715 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
18716 // F[X]OR(0.0, x) -> x
18717 // F[X]OR(x, 0.0) -> x
18718 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
18719 if (C->getValueAPF().isPosZero())
18720 return N->getOperand(1);
18721 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
18722 if (C->getValueAPF().isPosZero())
18723 return N->getOperand(0);
18727 /// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and
18728 /// X86ISD::FMAX nodes.
18729 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
18730 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
18732 // Only perform optimizations if UnsafeMath is used.
18733 if (!DAG.getTarget().Options.UnsafeFPMath)
18736 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
18737 // into FMINC and FMAXC, which are Commutative operations.
18738 unsigned NewOp = 0;
18739 switch (N->getOpcode()) {
18740 default: llvm_unreachable("unknown opcode");
18741 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
18742 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
18745 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
18746 N->getOperand(0), N->getOperand(1));
18749 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
18750 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
18751 // FAND(0.0, x) -> 0.0
18752 // FAND(x, 0.0) -> 0.0
18753 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
18754 if (C->getValueAPF().isPosZero())
18755 return N->getOperand(0);
18756 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
18757 if (C->getValueAPF().isPosZero())
18758 return N->getOperand(1);
18762 /// PerformFANDNCombine - Do target-specific dag combines on X86ISD::FANDN nodes
18763 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
18764 // FANDN(x, 0.0) -> 0.0
18765 // FANDN(0.0, x) -> x
18766 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
18767 if (C->getValueAPF().isPosZero())
18768 return N->getOperand(1);
18769 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
18770 if (C->getValueAPF().isPosZero())
18771 return N->getOperand(1);
18775 static SDValue PerformBTCombine(SDNode *N,
18777 TargetLowering::DAGCombinerInfo &DCI) {
18778 // BT ignores high bits in the bit index operand.
18779 SDValue Op1 = N->getOperand(1);
18780 if (Op1.hasOneUse()) {
18781 unsigned BitWidth = Op1.getValueSizeInBits();
18782 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
18783 APInt KnownZero, KnownOne;
18784 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
18785 !DCI.isBeforeLegalizeOps());
18786 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18787 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
18788 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
18789 DCI.CommitTargetLoweringOpt(TLO);
18794 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
18795 SDValue Op = N->getOperand(0);
18796 if (Op.getOpcode() == ISD::BITCAST)
18797 Op = Op.getOperand(0);
18798 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
18799 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
18800 VT.getVectorElementType().getSizeInBits() ==
18801 OpVT.getVectorElementType().getSizeInBits()) {
18802 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
18807 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
18808 const X86Subtarget *Subtarget) {
18809 EVT VT = N->getValueType(0);
18810 if (!VT.isVector())
18813 SDValue N0 = N->getOperand(0);
18814 SDValue N1 = N->getOperand(1);
18815 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
18818 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
18819 // both SSE and AVX2 since there is no sign-extended shift right
18820 // operation on a vector with 64-bit elements.
18821 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
18822 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
18823 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
18824 N0.getOpcode() == ISD::SIGN_EXTEND)) {
18825 SDValue N00 = N0.getOperand(0);
18827 // EXTLOAD has a better solution on AVX2,
18828 // it may be replaced with X86ISD::VSEXT node.
18829 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
18830 if (!ISD::isNormalLoad(N00.getNode()))
18833 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
18834 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
18836 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
18842 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
18843 TargetLowering::DAGCombinerInfo &DCI,
18844 const X86Subtarget *Subtarget) {
18845 if (!DCI.isBeforeLegalizeOps())
18848 if (!Subtarget->hasFp256())
18851 EVT VT = N->getValueType(0);
18852 if (VT.isVector() && VT.getSizeInBits() == 256) {
18853 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
18861 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
18862 const X86Subtarget* Subtarget) {
18864 EVT VT = N->getValueType(0);
18866 // Let legalize expand this if it isn't a legal type yet.
18867 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
18870 EVT ScalarVT = VT.getScalarType();
18871 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
18872 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
18875 SDValue A = N->getOperand(0);
18876 SDValue B = N->getOperand(1);
18877 SDValue C = N->getOperand(2);
18879 bool NegA = (A.getOpcode() == ISD::FNEG);
18880 bool NegB = (B.getOpcode() == ISD::FNEG);
18881 bool NegC = (C.getOpcode() == ISD::FNEG);
18883 // Negative multiplication when NegA xor NegB
18884 bool NegMul = (NegA != NegB);
18886 A = A.getOperand(0);
18888 B = B.getOperand(0);
18890 C = C.getOperand(0);
18894 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
18896 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
18898 return DAG.getNode(Opcode, dl, VT, A, B, C);
18901 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
18902 TargetLowering::DAGCombinerInfo &DCI,
18903 const X86Subtarget *Subtarget) {
18904 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
18905 // (and (i32 x86isd::setcc_carry), 1)
18906 // This eliminates the zext. This transformation is necessary because
18907 // ISD::SETCC is always legalized to i8.
18909 SDValue N0 = N->getOperand(0);
18910 EVT VT = N->getValueType(0);
18912 if (N0.getOpcode() == ISD::AND &&
18914 N0.getOperand(0).hasOneUse()) {
18915 SDValue N00 = N0.getOperand(0);
18916 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
18917 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
18918 if (!C || C->getZExtValue() != 1)
18920 return DAG.getNode(ISD::AND, dl, VT,
18921 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
18922 N00.getOperand(0), N00.getOperand(1)),
18923 DAG.getConstant(1, VT));
18927 if (VT.is256BitVector()) {
18928 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
18936 // Optimize x == -y --> x+y == 0
18937 // x != -y --> x+y != 0
18938 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG) {
18939 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
18940 SDValue LHS = N->getOperand(0);
18941 SDValue RHS = N->getOperand(1);
18943 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
18944 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
18945 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
18946 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
18947 LHS.getValueType(), RHS, LHS.getOperand(1));
18948 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
18949 addV, DAG.getConstant(0, addV.getValueType()), CC);
18951 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
18952 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
18953 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
18954 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
18955 RHS.getValueType(), LHS, RHS.getOperand(1));
18956 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
18957 addV, DAG.getConstant(0, addV.getValueType()), CC);
18962 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
18963 // as "sbb reg,reg", since it can be extended without zext and produces
18964 // an all-ones bit which is more useful than 0/1 in some cases.
18965 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG) {
18966 return DAG.getNode(ISD::AND, DL, MVT::i8,
18967 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
18968 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
18969 DAG.getConstant(1, MVT::i8));
18972 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
18973 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
18974 TargetLowering::DAGCombinerInfo &DCI,
18975 const X86Subtarget *Subtarget) {
18977 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
18978 SDValue EFLAGS = N->getOperand(1);
18980 if (CC == X86::COND_A) {
18981 // Try to convert COND_A into COND_B in an attempt to facilitate
18982 // materializing "setb reg".
18984 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
18985 // cannot take an immediate as its first operand.
18987 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
18988 EFLAGS.getValueType().isInteger() &&
18989 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
18990 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
18991 EFLAGS.getNode()->getVTList(),
18992 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
18993 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
18994 return MaterializeSETB(DL, NewEFLAGS, DAG);
18998 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
18999 // a zext and produces an all-ones bit which is more useful than 0/1 in some
19001 if (CC == X86::COND_B)
19002 return MaterializeSETB(DL, EFLAGS, DAG);
19006 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
19007 if (Flags.getNode()) {
19008 SDValue Cond = DAG.getConstant(CC, MVT::i8);
19009 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
19015 // Optimize branch condition evaluation.
19017 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
19018 TargetLowering::DAGCombinerInfo &DCI,
19019 const X86Subtarget *Subtarget) {
19021 SDValue Chain = N->getOperand(0);
19022 SDValue Dest = N->getOperand(1);
19023 SDValue EFLAGS = N->getOperand(3);
19024 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
19028 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
19029 if (Flags.getNode()) {
19030 SDValue Cond = DAG.getConstant(CC, MVT::i8);
19031 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
19038 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
19039 const X86TargetLowering *XTLI) {
19040 SDValue Op0 = N->getOperand(0);
19041 EVT InVT = Op0->getValueType(0);
19043 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
19044 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
19046 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
19047 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
19048 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
19051 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
19052 // a 32-bit target where SSE doesn't support i64->FP operations.
19053 if (Op0.getOpcode() == ISD::LOAD) {
19054 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
19055 EVT VT = Ld->getValueType(0);
19056 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
19057 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
19058 !XTLI->getSubtarget()->is64Bit() &&
19060 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
19061 Ld->getChain(), Op0, DAG);
19062 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
19069 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
19070 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
19071 X86TargetLowering::DAGCombinerInfo &DCI) {
19072 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
19073 // the result is either zero or one (depending on the input carry bit).
19074 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
19075 if (X86::isZeroNode(N->getOperand(0)) &&
19076 X86::isZeroNode(N->getOperand(1)) &&
19077 // We don't have a good way to replace an EFLAGS use, so only do this when
19079 SDValue(N, 1).use_empty()) {
19081 EVT VT = N->getValueType(0);
19082 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
19083 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
19084 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
19085 DAG.getConstant(X86::COND_B,MVT::i8),
19087 DAG.getConstant(1, VT));
19088 return DCI.CombineTo(N, Res1, CarryOut);
19094 // fold (add Y, (sete X, 0)) -> adc 0, Y
19095 // (add Y, (setne X, 0)) -> sbb -1, Y
19096 // (sub (sete X, 0), Y) -> sbb 0, Y
19097 // (sub (setne X, 0), Y) -> adc -1, Y
19098 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
19101 // Look through ZExts.
19102 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
19103 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
19106 SDValue SetCC = Ext.getOperand(0);
19107 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
19110 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
19111 if (CC != X86::COND_E && CC != X86::COND_NE)
19114 SDValue Cmp = SetCC.getOperand(1);
19115 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
19116 !X86::isZeroNode(Cmp.getOperand(1)) ||
19117 !Cmp.getOperand(0).getValueType().isInteger())
19120 SDValue CmpOp0 = Cmp.getOperand(0);
19121 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
19122 DAG.getConstant(1, CmpOp0.getValueType()));
19124 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
19125 if (CC == X86::COND_NE)
19126 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
19127 DL, OtherVal.getValueType(), OtherVal,
19128 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
19129 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
19130 DL, OtherVal.getValueType(), OtherVal,
19131 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
19134 /// PerformADDCombine - Do target-specific dag combines on integer adds.
19135 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
19136 const X86Subtarget *Subtarget) {
19137 EVT VT = N->getValueType(0);
19138 SDValue Op0 = N->getOperand(0);
19139 SDValue Op1 = N->getOperand(1);
19141 // Try to synthesize horizontal adds from adds of shuffles.
19142 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
19143 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
19144 isHorizontalBinOp(Op0, Op1, true))
19145 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
19147 return OptimizeConditionalInDecrement(N, DAG);
19150 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
19151 const X86Subtarget *Subtarget) {
19152 SDValue Op0 = N->getOperand(0);
19153 SDValue Op1 = N->getOperand(1);
19155 // X86 can't encode an immediate LHS of a sub. See if we can push the
19156 // negation into a preceding instruction.
19157 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
19158 // If the RHS of the sub is a XOR with one use and a constant, invert the
19159 // immediate. Then add one to the LHS of the sub so we can turn
19160 // X-Y -> X+~Y+1, saving one register.
19161 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
19162 isa<ConstantSDNode>(Op1.getOperand(1))) {
19163 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
19164 EVT VT = Op0.getValueType();
19165 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
19167 DAG.getConstant(~XorC, VT));
19168 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
19169 DAG.getConstant(C->getAPIntValue()+1, VT));
19173 // Try to synthesize horizontal adds from adds of shuffles.
19174 EVT VT = N->getValueType(0);
19175 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
19176 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
19177 isHorizontalBinOp(Op0, Op1, true))
19178 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
19180 return OptimizeConditionalInDecrement(N, DAG);
19183 /// performVZEXTCombine - Performs build vector combines
19184 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
19185 TargetLowering::DAGCombinerInfo &DCI,
19186 const X86Subtarget *Subtarget) {
19187 // (vzext (bitcast (vzext (x)) -> (vzext x)
19188 SDValue In = N->getOperand(0);
19189 while (In.getOpcode() == ISD::BITCAST)
19190 In = In.getOperand(0);
19192 if (In.getOpcode() != X86ISD::VZEXT)
19195 return DAG.getNode(X86ISD::VZEXT, SDLoc(N), N->getValueType(0),
19199 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
19200 DAGCombinerInfo &DCI) const {
19201 SelectionDAG &DAG = DCI.DAG;
19202 switch (N->getOpcode()) {
19204 case ISD::EXTRACT_VECTOR_ELT:
19205 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
19207 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
19208 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
19209 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
19210 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
19211 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
19212 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
19215 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
19216 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
19217 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
19218 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
19219 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
19220 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
19221 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
19222 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
19223 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
19225 case X86ISD::FOR: return PerformFORCombine(N, DAG);
19227 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
19228 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
19229 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
19230 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
19231 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
19232 case ISD::ANY_EXTEND:
19233 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
19234 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
19235 case ISD::SIGN_EXTEND_INREG: return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
19236 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
19237 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG);
19238 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
19239 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
19240 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
19241 case X86ISD::SHUFP: // Handle all target specific shuffles
19242 case X86ISD::PALIGNR:
19243 case X86ISD::UNPCKH:
19244 case X86ISD::UNPCKL:
19245 case X86ISD::MOVHLPS:
19246 case X86ISD::MOVLHPS:
19247 case X86ISD::PSHUFD:
19248 case X86ISD::PSHUFHW:
19249 case X86ISD::PSHUFLW:
19250 case X86ISD::MOVSS:
19251 case X86ISD::MOVSD:
19252 case X86ISD::VPERMILP:
19253 case X86ISD::VPERM2X128:
19254 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
19255 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
19261 /// isTypeDesirableForOp - Return true if the target has native support for
19262 /// the specified value type and it is 'desirable' to use the type for the
19263 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
19264 /// instruction encodings are longer and some i16 instructions are slow.
19265 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
19266 if (!isTypeLegal(VT))
19268 if (VT != MVT::i16)
19275 case ISD::SIGN_EXTEND:
19276 case ISD::ZERO_EXTEND:
19277 case ISD::ANY_EXTEND:
19290 /// IsDesirableToPromoteOp - This method query the target whether it is
19291 /// beneficial for dag combiner to promote the specified node. If true, it
19292 /// should return the desired promotion type by reference.
19293 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
19294 EVT VT = Op.getValueType();
19295 if (VT != MVT::i16)
19298 bool Promote = false;
19299 bool Commute = false;
19300 switch (Op.getOpcode()) {
19303 LoadSDNode *LD = cast<LoadSDNode>(Op);
19304 // If the non-extending load has a single use and it's not live out, then it
19305 // might be folded.
19306 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
19307 Op.hasOneUse()*/) {
19308 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
19309 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
19310 // The only case where we'd want to promote LOAD (rather then it being
19311 // promoted as an operand is when it's only use is liveout.
19312 if (UI->getOpcode() != ISD::CopyToReg)
19319 case ISD::SIGN_EXTEND:
19320 case ISD::ZERO_EXTEND:
19321 case ISD::ANY_EXTEND:
19326 SDValue N0 = Op.getOperand(0);
19327 // Look out for (store (shl (load), x)).
19328 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
19341 SDValue N0 = Op.getOperand(0);
19342 SDValue N1 = Op.getOperand(1);
19343 if (!Commute && MayFoldLoad(N1))
19345 // Avoid disabling potential load folding opportunities.
19346 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
19348 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
19358 //===----------------------------------------------------------------------===//
19359 // X86 Inline Assembly Support
19360 //===----------------------------------------------------------------------===//
19363 // Helper to match a string separated by whitespace.
19364 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
19365 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
19367 for (unsigned i = 0, e = args.size(); i != e; ++i) {
19368 StringRef piece(*args[i]);
19369 if (!s.startswith(piece)) // Check if the piece matches.
19372 s = s.substr(piece.size());
19373 StringRef::size_type pos = s.find_first_not_of(" \t");
19374 if (pos == 0) // We matched a prefix.
19382 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
19385 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
19387 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
19388 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
19389 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
19390 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
19392 if (AsmPieces.size() == 3)
19394 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
19401 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
19402 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
19404 std::string AsmStr = IA->getAsmString();
19406 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
19407 if (!Ty || Ty->getBitWidth() % 16 != 0)
19410 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
19411 SmallVector<StringRef, 4> AsmPieces;
19412 SplitString(AsmStr, AsmPieces, ";\n");
19414 switch (AsmPieces.size()) {
19415 default: return false;
19417 // FIXME: this should verify that we are targeting a 486 or better. If not,
19418 // we will turn this bswap into something that will be lowered to logical
19419 // ops instead of emitting the bswap asm. For now, we don't support 486 or
19420 // lower so don't worry about this.
19422 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
19423 matchAsm(AsmPieces[0], "bswapl", "$0") ||
19424 matchAsm(AsmPieces[0], "bswapq", "$0") ||
19425 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
19426 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
19427 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
19428 // No need to check constraints, nothing other than the equivalent of
19429 // "=r,0" would be valid here.
19430 return IntrinsicLowering::LowerToByteSwap(CI);
19433 // rorw $$8, ${0:w} --> llvm.bswap.i16
19434 if (CI->getType()->isIntegerTy(16) &&
19435 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
19436 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
19437 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
19439 const std::string &ConstraintsStr = IA->getConstraintString();
19440 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
19441 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
19442 if (clobbersFlagRegisters(AsmPieces))
19443 return IntrinsicLowering::LowerToByteSwap(CI);
19447 if (CI->getType()->isIntegerTy(32) &&
19448 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
19449 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
19450 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
19451 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
19453 const std::string &ConstraintsStr = IA->getConstraintString();
19454 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
19455 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
19456 if (clobbersFlagRegisters(AsmPieces))
19457 return IntrinsicLowering::LowerToByteSwap(CI);
19460 if (CI->getType()->isIntegerTy(64)) {
19461 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
19462 if (Constraints.size() >= 2 &&
19463 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
19464 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
19465 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
19466 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
19467 matchAsm(AsmPieces[1], "bswap", "%edx") &&
19468 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
19469 return IntrinsicLowering::LowerToByteSwap(CI);
19477 /// getConstraintType - Given a constraint letter, return the type of
19478 /// constraint it is for this target.
19479 X86TargetLowering::ConstraintType
19480 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
19481 if (Constraint.size() == 1) {
19482 switch (Constraint[0]) {
19493 return C_RegisterClass;
19517 return TargetLowering::getConstraintType(Constraint);
19520 /// Examine constraint type and operand type and determine a weight value.
19521 /// This object must already have been set up with the operand type
19522 /// and the current alternative constraint selected.
19523 TargetLowering::ConstraintWeight
19524 X86TargetLowering::getSingleConstraintMatchWeight(
19525 AsmOperandInfo &info, const char *constraint) const {
19526 ConstraintWeight weight = CW_Invalid;
19527 Value *CallOperandVal = info.CallOperandVal;
19528 // If we don't have a value, we can't do a match,
19529 // but allow it at the lowest weight.
19530 if (CallOperandVal == NULL)
19532 Type *type = CallOperandVal->getType();
19533 // Look at the constraint type.
19534 switch (*constraint) {
19536 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
19547 if (CallOperandVal->getType()->isIntegerTy())
19548 weight = CW_SpecificReg;
19553 if (type->isFloatingPointTy())
19554 weight = CW_SpecificReg;
19557 if (type->isX86_MMXTy() && Subtarget->hasMMX())
19558 weight = CW_SpecificReg;
19562 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
19563 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
19564 weight = CW_Register;
19567 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
19568 if (C->getZExtValue() <= 31)
19569 weight = CW_Constant;
19573 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19574 if (C->getZExtValue() <= 63)
19575 weight = CW_Constant;
19579 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19580 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
19581 weight = CW_Constant;
19585 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19586 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
19587 weight = CW_Constant;
19591 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19592 if (C->getZExtValue() <= 3)
19593 weight = CW_Constant;
19597 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19598 if (C->getZExtValue() <= 0xff)
19599 weight = CW_Constant;
19604 if (dyn_cast<ConstantFP>(CallOperandVal)) {
19605 weight = CW_Constant;
19609 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19610 if ((C->getSExtValue() >= -0x80000000LL) &&
19611 (C->getSExtValue() <= 0x7fffffffLL))
19612 weight = CW_Constant;
19616 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19617 if (C->getZExtValue() <= 0xffffffff)
19618 weight = CW_Constant;
19625 /// LowerXConstraint - try to replace an X constraint, which matches anything,
19626 /// with another that has more specific requirements based on the type of the
19627 /// corresponding operand.
19628 const char *X86TargetLowering::
19629 LowerXConstraint(EVT ConstraintVT) const {
19630 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
19631 // 'f' like normal targets.
19632 if (ConstraintVT.isFloatingPoint()) {
19633 if (Subtarget->hasSSE2())
19635 if (Subtarget->hasSSE1())
19639 return TargetLowering::LowerXConstraint(ConstraintVT);
19642 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
19643 /// vector. If it is invalid, don't add anything to Ops.
19644 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
19645 std::string &Constraint,
19646 std::vector<SDValue>&Ops,
19647 SelectionDAG &DAG) const {
19648 SDValue Result(0, 0);
19650 // Only support length 1 constraints for now.
19651 if (Constraint.length() > 1) return;
19653 char ConstraintLetter = Constraint[0];
19654 switch (ConstraintLetter) {
19657 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19658 if (C->getZExtValue() <= 31) {
19659 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
19665 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19666 if (C->getZExtValue() <= 63) {
19667 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
19673 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19674 if (isInt<8>(C->getSExtValue())) {
19675 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
19681 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19682 if (C->getZExtValue() <= 255) {
19683 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
19689 // 32-bit signed value
19690 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19691 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
19692 C->getSExtValue())) {
19693 // Widen to 64 bits here to get it sign extended.
19694 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
19697 // FIXME gcc accepts some relocatable values here too, but only in certain
19698 // memory models; it's complicated.
19703 // 32-bit unsigned value
19704 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19705 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
19706 C->getZExtValue())) {
19707 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
19711 // FIXME gcc accepts some relocatable values here too, but only in certain
19712 // memory models; it's complicated.
19716 // Literal immediates are always ok.
19717 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
19718 // Widen to 64 bits here to get it sign extended.
19719 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
19723 // In any sort of PIC mode addresses need to be computed at runtime by
19724 // adding in a register or some sort of table lookup. These can't
19725 // be used as immediates.
19726 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
19729 // If we are in non-pic codegen mode, we allow the address of a global (with
19730 // an optional displacement) to be used with 'i'.
19731 GlobalAddressSDNode *GA = 0;
19732 int64_t Offset = 0;
19734 // Match either (GA), (GA+C), (GA+C1+C2), etc.
19736 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
19737 Offset += GA->getOffset();
19739 } else if (Op.getOpcode() == ISD::ADD) {
19740 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
19741 Offset += C->getZExtValue();
19742 Op = Op.getOperand(0);
19745 } else if (Op.getOpcode() == ISD::SUB) {
19746 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
19747 Offset += -C->getZExtValue();
19748 Op = Op.getOperand(0);
19753 // Otherwise, this isn't something we can handle, reject it.
19757 const GlobalValue *GV = GA->getGlobal();
19758 // If we require an extra load to get this address, as in PIC mode, we
19759 // can't accept it.
19760 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
19761 getTargetMachine())))
19764 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
19765 GA->getValueType(0), Offset);
19770 if (Result.getNode()) {
19771 Ops.push_back(Result);
19774 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
19777 std::pair<unsigned, const TargetRegisterClass*>
19778 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
19780 // First, see if this is a constraint that directly corresponds to an LLVM
19782 if (Constraint.size() == 1) {
19783 // GCC Constraint Letters
19784 switch (Constraint[0]) {
19786 // TODO: Slight differences here in allocation order and leaving
19787 // RIP in the class. Do they matter any more here than they do
19788 // in the normal allocation?
19789 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
19790 if (Subtarget->is64Bit()) {
19791 if (VT == MVT::i32 || VT == MVT::f32)
19792 return std::make_pair(0U, &X86::GR32RegClass);
19793 if (VT == MVT::i16)
19794 return std::make_pair(0U, &X86::GR16RegClass);
19795 if (VT == MVT::i8 || VT == MVT::i1)
19796 return std::make_pair(0U, &X86::GR8RegClass);
19797 if (VT == MVT::i64 || VT == MVT::f64)
19798 return std::make_pair(0U, &X86::GR64RegClass);
19801 // 32-bit fallthrough
19802 case 'Q': // Q_REGS
19803 if (VT == MVT::i32 || VT == MVT::f32)
19804 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
19805 if (VT == MVT::i16)
19806 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
19807 if (VT == MVT::i8 || VT == MVT::i1)
19808 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
19809 if (VT == MVT::i64)
19810 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
19812 case 'r': // GENERAL_REGS
19813 case 'l': // INDEX_REGS
19814 if (VT == MVT::i8 || VT == MVT::i1)
19815 return std::make_pair(0U, &X86::GR8RegClass);
19816 if (VT == MVT::i16)
19817 return std::make_pair(0U, &X86::GR16RegClass);
19818 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
19819 return std::make_pair(0U, &X86::GR32RegClass);
19820 return std::make_pair(0U, &X86::GR64RegClass);
19821 case 'R': // LEGACY_REGS
19822 if (VT == MVT::i8 || VT == MVT::i1)
19823 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
19824 if (VT == MVT::i16)
19825 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
19826 if (VT == MVT::i32 || !Subtarget->is64Bit())
19827 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
19828 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
19829 case 'f': // FP Stack registers.
19830 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
19831 // value to the correct fpstack register class.
19832 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
19833 return std::make_pair(0U, &X86::RFP32RegClass);
19834 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
19835 return std::make_pair(0U, &X86::RFP64RegClass);
19836 return std::make_pair(0U, &X86::RFP80RegClass);
19837 case 'y': // MMX_REGS if MMX allowed.
19838 if (!Subtarget->hasMMX()) break;
19839 return std::make_pair(0U, &X86::VR64RegClass);
19840 case 'Y': // SSE_REGS if SSE2 allowed
19841 if (!Subtarget->hasSSE2()) break;
19843 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
19844 if (!Subtarget->hasSSE1()) break;
19846 switch (VT.SimpleTy) {
19848 // Scalar SSE types.
19851 return std::make_pair(0U, &X86::FR32RegClass);
19854 return std::make_pair(0U, &X86::FR64RegClass);
19862 return std::make_pair(0U, &X86::VR128RegClass);
19870 return std::make_pair(0U, &X86::VR256RegClass);
19875 return std::make_pair(0U, &X86::VR512RegClass);
19881 // Use the default implementation in TargetLowering to convert the register
19882 // constraint into a member of a register class.
19883 std::pair<unsigned, const TargetRegisterClass*> Res;
19884 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
19886 // Not found as a standard register?
19887 if (Res.second == 0) {
19888 // Map st(0) -> st(7) -> ST0
19889 if (Constraint.size() == 7 && Constraint[0] == '{' &&
19890 tolower(Constraint[1]) == 's' &&
19891 tolower(Constraint[2]) == 't' &&
19892 Constraint[3] == '(' &&
19893 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
19894 Constraint[5] == ')' &&
19895 Constraint[6] == '}') {
19897 Res.first = X86::ST0+Constraint[4]-'0';
19898 Res.second = &X86::RFP80RegClass;
19902 // GCC allows "st(0)" to be called just plain "st".
19903 if (StringRef("{st}").equals_lower(Constraint)) {
19904 Res.first = X86::ST0;
19905 Res.second = &X86::RFP80RegClass;
19910 if (StringRef("{flags}").equals_lower(Constraint)) {
19911 Res.first = X86::EFLAGS;
19912 Res.second = &X86::CCRRegClass;
19916 // 'A' means EAX + EDX.
19917 if (Constraint == "A") {
19918 Res.first = X86::EAX;
19919 Res.second = &X86::GR32_ADRegClass;
19925 // Otherwise, check to see if this is a register class of the wrong value
19926 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
19927 // turn into {ax},{dx}.
19928 if (Res.second->hasType(VT))
19929 return Res; // Correct type already, nothing to do.
19931 // All of the single-register GCC register classes map their values onto
19932 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
19933 // really want an 8-bit or 32-bit register, map to the appropriate register
19934 // class and return the appropriate register.
19935 if (Res.second == &X86::GR16RegClass) {
19936 if (VT == MVT::i8 || VT == MVT::i1) {
19937 unsigned DestReg = 0;
19938 switch (Res.first) {
19940 case X86::AX: DestReg = X86::AL; break;
19941 case X86::DX: DestReg = X86::DL; break;
19942 case X86::CX: DestReg = X86::CL; break;
19943 case X86::BX: DestReg = X86::BL; break;
19946 Res.first = DestReg;
19947 Res.second = &X86::GR8RegClass;
19949 } else if (VT == MVT::i32 || VT == MVT::f32) {
19950 unsigned DestReg = 0;
19951 switch (Res.first) {
19953 case X86::AX: DestReg = X86::EAX; break;
19954 case X86::DX: DestReg = X86::EDX; break;
19955 case X86::CX: DestReg = X86::ECX; break;
19956 case X86::BX: DestReg = X86::EBX; break;
19957 case X86::SI: DestReg = X86::ESI; break;
19958 case X86::DI: DestReg = X86::EDI; break;
19959 case X86::BP: DestReg = X86::EBP; break;
19960 case X86::SP: DestReg = X86::ESP; break;
19963 Res.first = DestReg;
19964 Res.second = &X86::GR32RegClass;
19966 } else if (VT == MVT::i64 || VT == MVT::f64) {
19967 unsigned DestReg = 0;
19968 switch (Res.first) {
19970 case X86::AX: DestReg = X86::RAX; break;
19971 case X86::DX: DestReg = X86::RDX; break;
19972 case X86::CX: DestReg = X86::RCX; break;
19973 case X86::BX: DestReg = X86::RBX; break;
19974 case X86::SI: DestReg = X86::RSI; break;
19975 case X86::DI: DestReg = X86::RDI; break;
19976 case X86::BP: DestReg = X86::RBP; break;
19977 case X86::SP: DestReg = X86::RSP; break;
19980 Res.first = DestReg;
19981 Res.second = &X86::GR64RegClass;
19984 } else if (Res.second == &X86::FR32RegClass ||
19985 Res.second == &X86::FR64RegClass ||
19986 Res.second == &X86::VR128RegClass ||
19987 Res.second == &X86::VR256RegClass ||
19988 Res.second == &X86::FR32XRegClass ||
19989 Res.second == &X86::FR64XRegClass ||
19990 Res.second == &X86::VR128XRegClass ||
19991 Res.second == &X86::VR256XRegClass ||
19992 Res.second == &X86::VR512RegClass) {
19993 // Handle references to XMM physical registers that got mapped into the
19994 // wrong class. This can happen with constraints like {xmm0} where the
19995 // target independent register mapper will just pick the first match it can
19996 // find, ignoring the required type.
19998 if (VT == MVT::f32 || VT == MVT::i32)
19999 Res.second = &X86::FR32RegClass;
20000 else if (VT == MVT::f64 || VT == MVT::i64)
20001 Res.second = &X86::FR64RegClass;
20002 else if (X86::VR128RegClass.hasType(VT))
20003 Res.second = &X86::VR128RegClass;
20004 else if (X86::VR256RegClass.hasType(VT))
20005 Res.second = &X86::VR256RegClass;
20006 else if (X86::VR512RegClass.hasType(VT))
20007 Res.second = &X86::VR512RegClass;