1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
16 #include "X86ISelLowering.h"
17 #include "Utils/X86ShuffleDecode.h"
19 #include "X86CallingConv.h"
20 #include "X86InstrBuilder.h"
21 #include "X86TargetMachine.h"
22 #include "X86TargetObjectFile.h"
23 #include "llvm/ADT/SmallSet.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/VariadicFunction.h"
27 #include "llvm/CodeGen/IntrinsicLowering.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/IR/CallingConv.h"
35 #include "llvm/IR/Constants.h"
36 #include "llvm/IR/DerivedTypes.h"
37 #include "llvm/IR/Function.h"
38 #include "llvm/IR/GlobalAlias.h"
39 #include "llvm/IR/GlobalVariable.h"
40 #include "llvm/IR/Instructions.h"
41 #include "llvm/IR/Intrinsics.h"
42 #include "llvm/MC/MCAsmInfo.h"
43 #include "llvm/MC/MCContext.h"
44 #include "llvm/MC/MCExpr.h"
45 #include "llvm/MC/MCSymbol.h"
46 #include "llvm/Support/CallSite.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/MathExtras.h"
50 #include "llvm/Target/TargetOptions.h"
55 STATISTIC(NumTailCalls, "Number of tail calls");
57 // Forward declarations.
58 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
61 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
62 SelectionDAG &DAG, SDLoc dl,
63 unsigned vectorWidth) {
64 assert((vectorWidth == 128 || vectorWidth == 256) &&
65 "Unsupported vector width");
66 EVT VT = Vec.getValueType();
67 EVT ElVT = VT.getVectorElementType();
68 unsigned Factor = VT.getSizeInBits()/vectorWidth;
69 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
70 VT.getVectorNumElements()/Factor);
72 // Extract from UNDEF is UNDEF.
73 if (Vec.getOpcode() == ISD::UNDEF)
74 return DAG.getUNDEF(ResultVT);
76 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
77 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
79 // This is the index of the first element of the vectorWidth-bit chunk
81 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
84 // If the input is a buildvector just emit a smaller one.
85 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
86 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
87 Vec->op_begin()+NormalizedIdxVal, ElemsPerChunk);
89 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
90 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
96 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
97 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
98 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
99 /// instructions or a simple subregister reference. Idx is an index in the
100 /// 128 bits we want. It need not be aligned to a 128-bit bounday. That makes
101 /// lowering EXTRACT_VECTOR_ELT operations easier.
102 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
103 SelectionDAG &DAG, SDLoc dl) {
104 assert((Vec.getValueType().is256BitVector() ||
105 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
106 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
109 /// Generate a DAG to grab 256-bits from a 512-bit vector.
110 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
111 SelectionDAG &DAG, SDLoc dl) {
112 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
113 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
116 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
117 unsigned IdxVal, SelectionDAG &DAG,
118 SDLoc dl, unsigned vectorWidth) {
119 assert((vectorWidth == 128 || vectorWidth == 256) &&
120 "Unsupported vector width");
121 // Inserting UNDEF is Result
122 if (Vec.getOpcode() == ISD::UNDEF)
124 EVT VT = Vec.getValueType();
125 EVT ElVT = VT.getVectorElementType();
126 EVT ResultVT = Result.getValueType();
128 // Insert the relevant vectorWidth bits.
129 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
131 // This is the index of the first element of the vectorWidth-bit chunk
133 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
136 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
137 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
140 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
141 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
142 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
143 /// simple superregister reference. Idx is an index in the 128 bits
144 /// we want. It need not be aligned to a 128-bit bounday. That makes
145 /// lowering INSERT_VECTOR_ELT operations easier.
146 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
147 unsigned IdxVal, SelectionDAG &DAG,
149 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
150 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
153 static SDValue Insert256BitVector(SDValue Result, SDValue Vec,
154 unsigned IdxVal, SelectionDAG &DAG,
156 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
157 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
160 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
161 /// instructions. This is used because creating CONCAT_VECTOR nodes of
162 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
163 /// large BUILD_VECTORS.
164 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
165 unsigned NumElems, SelectionDAG &DAG,
167 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
168 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
171 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
172 unsigned NumElems, SelectionDAG &DAG,
174 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
175 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
178 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
179 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
180 bool is64Bit = Subtarget->is64Bit();
182 if (Subtarget->isTargetMacho()) {
184 return new X86_64MachoTargetObjectFile();
185 return new TargetLoweringObjectFileMachO();
188 if (Subtarget->isTargetLinux())
189 return new X86LinuxTargetObjectFile();
190 if (Subtarget->isTargetELF())
191 return new TargetLoweringObjectFileELF();
192 if (Subtarget->isTargetWindows())
193 return new X86WindowsTargetObjectFile();
194 if (Subtarget->isTargetCOFF())
195 return new TargetLoweringObjectFileCOFF();
196 llvm_unreachable("unknown subtarget type");
199 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
200 : TargetLowering(TM, createTLOF(TM)) {
201 Subtarget = &TM.getSubtarget<X86Subtarget>();
202 X86ScalarSSEf64 = Subtarget->hasSSE2();
203 X86ScalarSSEf32 = Subtarget->hasSSE1();
204 TD = getDataLayout();
206 resetOperationActions();
209 void X86TargetLowering::resetOperationActions() {
210 const TargetMachine &TM = getTargetMachine();
211 static bool FirstTimeThrough = true;
213 // If none of the target options have changed, then we don't need to reset the
214 // operation actions.
215 if (!FirstTimeThrough && TO == TM.Options) return;
217 if (!FirstTimeThrough) {
218 // Reinitialize the actions.
220 FirstTimeThrough = false;
225 // Set up the TargetLowering object.
226 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
228 // X86 is weird, it always uses i8 for shift amounts and setcc results.
229 setBooleanContents(ZeroOrOneBooleanContent);
230 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
231 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
233 // For 64-bit since we have so many registers use the ILP scheduler, for
234 // 32-bit code use the register pressure specific scheduling.
235 // For Atom, always use ILP scheduling.
236 if (Subtarget->isAtom())
237 setSchedulingPreference(Sched::ILP);
238 else if (Subtarget->is64Bit())
239 setSchedulingPreference(Sched::ILP);
241 setSchedulingPreference(Sched::RegPressure);
242 const X86RegisterInfo *RegInfo =
243 static_cast<const X86RegisterInfo*>(TM.getRegisterInfo());
244 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
246 // Bypass expensive divides on Atom when compiling with O2
247 if (Subtarget->hasSlowDivide() && TM.getOptLevel() >= CodeGenOpt::Default) {
248 addBypassSlowDiv(32, 8);
249 if (Subtarget->is64Bit())
250 addBypassSlowDiv(64, 16);
253 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) {
254 // Setup Windows compiler runtime calls.
255 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
256 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
257 setLibcallName(RTLIB::SREM_I64, "_allrem");
258 setLibcallName(RTLIB::UREM_I64, "_aullrem");
259 setLibcallName(RTLIB::MUL_I64, "_allmul");
260 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
261 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
262 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
263 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
264 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
266 // The _ftol2 runtime function has an unusual calling conv, which
267 // is modeled by a special pseudo-instruction.
268 setLibcallName(RTLIB::FPTOUINT_F64_I64, 0);
269 setLibcallName(RTLIB::FPTOUINT_F32_I64, 0);
270 setLibcallName(RTLIB::FPTOUINT_F64_I32, 0);
271 setLibcallName(RTLIB::FPTOUINT_F32_I32, 0);
274 if (Subtarget->isTargetDarwin()) {
275 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
276 setUseUnderscoreSetJmp(false);
277 setUseUnderscoreLongJmp(false);
278 } else if (Subtarget->isTargetMingw()) {
279 // MS runtime is weird: it exports _setjmp, but longjmp!
280 setUseUnderscoreSetJmp(true);
281 setUseUnderscoreLongJmp(false);
283 setUseUnderscoreSetJmp(true);
284 setUseUnderscoreLongJmp(true);
287 // Set up the register classes.
288 addRegisterClass(MVT::i8, &X86::GR8RegClass);
289 addRegisterClass(MVT::i16, &X86::GR16RegClass);
290 addRegisterClass(MVT::i32, &X86::GR32RegClass);
291 if (Subtarget->is64Bit())
292 addRegisterClass(MVT::i64, &X86::GR64RegClass);
294 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
296 // We don't accept any truncstore of integer registers.
297 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
298 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
299 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
300 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
301 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
302 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
304 // SETOEQ and SETUNE require checking two conditions.
305 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
306 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
307 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
308 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
309 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
310 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
312 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
314 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
315 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
316 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
318 if (Subtarget->is64Bit()) {
319 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
320 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
321 } else if (!TM.Options.UseSoftFloat) {
322 // We have an algorithm for SSE2->double, and we turn this into a
323 // 64-bit FILD followed by conditional FADD for other targets.
324 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
325 // We have an algorithm for SSE2, and we turn this into a 64-bit
326 // FILD for other targets.
327 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
330 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
332 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
333 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
335 if (!TM.Options.UseSoftFloat) {
336 // SSE has no i16 to fp conversion, only i32
337 if (X86ScalarSSEf32) {
338 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
339 // f32 and f64 cases are Legal, f80 case is not
340 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
342 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
343 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
346 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
347 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
350 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
351 // are Legal, f80 is custom lowered.
352 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
353 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
355 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
357 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
358 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
360 if (X86ScalarSSEf32) {
361 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
362 // f32 and f64 cases are Legal, f80 case is not
363 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
365 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
366 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
369 // Handle FP_TO_UINT by promoting the destination to a larger signed
371 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
372 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
373 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
375 if (Subtarget->is64Bit()) {
376 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
377 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
378 } else if (!TM.Options.UseSoftFloat) {
379 // Since AVX is a superset of SSE3, only check for SSE here.
380 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
381 // Expand FP_TO_UINT into a select.
382 // FIXME: We would like to use a Custom expander here eventually to do
383 // the optimal thing for SSE vs. the default expansion in the legalizer.
384 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
386 // With SSE3 we can use fisttpll to convert to a signed i64; without
387 // SSE, we're stuck with a fistpll.
388 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
391 if (isTargetFTOL()) {
392 // Use the _ftol2 runtime function, which has a pseudo-instruction
393 // to handle its weird calling convention.
394 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
397 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
398 if (!X86ScalarSSEf64) {
399 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
400 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
401 if (Subtarget->is64Bit()) {
402 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
403 // Without SSE, i64->f64 goes through memory.
404 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
408 // Scalar integer divide and remainder are lowered to use operations that
409 // produce two results, to match the available instructions. This exposes
410 // the two-result form to trivial CSE, which is able to combine x/y and x%y
411 // into a single instruction.
413 // Scalar integer multiply-high is also lowered to use two-result
414 // operations, to match the available instructions. However, plain multiply
415 // (low) operations are left as Legal, as there are single-result
416 // instructions for this in x86. Using the two-result multiply instructions
417 // when both high and low results are needed must be arranged by dagcombine.
418 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
420 setOperationAction(ISD::MULHS, VT, Expand);
421 setOperationAction(ISD::MULHU, VT, Expand);
422 setOperationAction(ISD::SDIV, VT, Expand);
423 setOperationAction(ISD::UDIV, VT, Expand);
424 setOperationAction(ISD::SREM, VT, Expand);
425 setOperationAction(ISD::UREM, VT, Expand);
427 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
428 setOperationAction(ISD::ADDC, VT, Custom);
429 setOperationAction(ISD::ADDE, VT, Custom);
430 setOperationAction(ISD::SUBC, VT, Custom);
431 setOperationAction(ISD::SUBE, VT, Custom);
434 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
435 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
436 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
437 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
438 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
439 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
440 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
441 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
442 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
443 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
444 if (Subtarget->is64Bit())
445 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
446 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
447 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
448 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
449 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
450 setOperationAction(ISD::FREM , MVT::f32 , Expand);
451 setOperationAction(ISD::FREM , MVT::f64 , Expand);
452 setOperationAction(ISD::FREM , MVT::f80 , Expand);
453 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
455 // Promote the i8 variants and force them on up to i32 which has a shorter
457 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
458 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
459 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
460 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
461 if (Subtarget->hasBMI()) {
462 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
463 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
464 if (Subtarget->is64Bit())
465 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
467 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
468 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
469 if (Subtarget->is64Bit())
470 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
473 if (Subtarget->hasLZCNT()) {
474 // When promoting the i8 variants, force them to i32 for a shorter
476 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
477 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
478 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
479 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
480 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
481 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
482 if (Subtarget->is64Bit())
483 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
485 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
486 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
487 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
488 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
489 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
490 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
491 if (Subtarget->is64Bit()) {
492 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
493 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
497 if (Subtarget->hasPOPCNT()) {
498 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
500 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
501 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
502 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
503 if (Subtarget->is64Bit())
504 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
507 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
508 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
510 // These should be promoted to a larger select which is supported.
511 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
512 // X86 wants to expand cmov itself.
513 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
514 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
515 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
516 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
517 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
518 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
519 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
520 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
521 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
522 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
523 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
524 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
525 if (Subtarget->is64Bit()) {
526 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
527 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
529 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
530 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
531 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
532 // support continuation, user-level threading, and etc.. As a result, no
533 // other SjLj exception interfaces are implemented and please don't build
534 // your own exception handling based on them.
535 // LLVM/Clang supports zero-cost DWARF exception handling.
536 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
537 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
540 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
541 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
542 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
543 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
544 if (Subtarget->is64Bit())
545 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
546 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
547 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
548 if (Subtarget->is64Bit()) {
549 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
550 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
551 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
552 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
553 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
555 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
556 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
557 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
558 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
559 if (Subtarget->is64Bit()) {
560 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
561 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
562 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
565 if (Subtarget->hasSSE1())
566 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
568 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
570 // Expand certain atomics
571 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
573 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom);
574 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
575 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
578 if (!Subtarget->is64Bit()) {
579 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
580 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
581 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
582 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
583 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
584 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
585 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
586 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
587 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i64, Custom);
588 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i64, Custom);
589 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i64, Custom);
590 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i64, Custom);
593 if (Subtarget->hasCmpxchg16b()) {
594 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom);
597 // FIXME - use subtarget debug flags
598 if (!Subtarget->isTargetDarwin() &&
599 !Subtarget->isTargetELF() &&
600 !Subtarget->isTargetCygMing()) {
601 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
604 if (Subtarget->is64Bit()) {
605 setExceptionPointerRegister(X86::RAX);
606 setExceptionSelectorRegister(X86::RDX);
608 setExceptionPointerRegister(X86::EAX);
609 setExceptionSelectorRegister(X86::EDX);
611 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
612 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
614 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
615 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
617 setOperationAction(ISD::TRAP, MVT::Other, Legal);
618 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
620 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
621 setOperationAction(ISD::VASTART , MVT::Other, Custom);
622 setOperationAction(ISD::VAEND , MVT::Other, Expand);
623 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
624 // TargetInfo::X86_64ABIBuiltinVaList
625 setOperationAction(ISD::VAARG , MVT::Other, Custom);
626 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
628 // TargetInfo::CharPtrBuiltinVaList
629 setOperationAction(ISD::VAARG , MVT::Other, Expand);
630 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
633 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
634 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
636 if (Subtarget->isOSWindows() && !Subtarget->isTargetMacho())
637 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
638 MVT::i64 : MVT::i32, Custom);
639 else if (TM.Options.EnableSegmentedStacks)
640 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
641 MVT::i64 : MVT::i32, Custom);
643 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
644 MVT::i64 : MVT::i32, Expand);
646 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
647 // f32 and f64 use SSE.
648 // Set up the FP register classes.
649 addRegisterClass(MVT::f32, &X86::FR32RegClass);
650 addRegisterClass(MVT::f64, &X86::FR64RegClass);
652 // Use ANDPD to simulate FABS.
653 setOperationAction(ISD::FABS , MVT::f64, Custom);
654 setOperationAction(ISD::FABS , MVT::f32, Custom);
656 // Use XORP to simulate FNEG.
657 setOperationAction(ISD::FNEG , MVT::f64, Custom);
658 setOperationAction(ISD::FNEG , MVT::f32, Custom);
660 // Use ANDPD and ORPD to simulate FCOPYSIGN.
661 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
662 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
664 // Lower this to FGETSIGNx86 plus an AND.
665 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
666 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
668 // We don't support sin/cos/fmod
669 setOperationAction(ISD::FSIN , MVT::f64, Expand);
670 setOperationAction(ISD::FCOS , MVT::f64, Expand);
671 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
672 setOperationAction(ISD::FSIN , MVT::f32, Expand);
673 setOperationAction(ISD::FCOS , MVT::f32, Expand);
674 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
676 // Expand FP immediates into loads from the stack, except for the special
678 addLegalFPImmediate(APFloat(+0.0)); // xorpd
679 addLegalFPImmediate(APFloat(+0.0f)); // xorps
680 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
681 // Use SSE for f32, x87 for f64.
682 // Set up the FP register classes.
683 addRegisterClass(MVT::f32, &X86::FR32RegClass);
684 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
686 // Use ANDPS to simulate FABS.
687 setOperationAction(ISD::FABS , MVT::f32, Custom);
689 // Use XORP to simulate FNEG.
690 setOperationAction(ISD::FNEG , MVT::f32, Custom);
692 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
694 // Use ANDPS and ORPS to simulate FCOPYSIGN.
695 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
696 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
698 // We don't support sin/cos/fmod
699 setOperationAction(ISD::FSIN , MVT::f32, Expand);
700 setOperationAction(ISD::FCOS , MVT::f32, Expand);
701 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
703 // Special cases we handle for FP constants.
704 addLegalFPImmediate(APFloat(+0.0f)); // xorps
705 addLegalFPImmediate(APFloat(+0.0)); // FLD0
706 addLegalFPImmediate(APFloat(+1.0)); // FLD1
707 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
708 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
710 if (!TM.Options.UnsafeFPMath) {
711 setOperationAction(ISD::FSIN , MVT::f64, Expand);
712 setOperationAction(ISD::FCOS , MVT::f64, Expand);
713 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
715 } else if (!TM.Options.UseSoftFloat) {
716 // f32 and f64 in x87.
717 // Set up the FP register classes.
718 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
719 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
721 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
722 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
723 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
724 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
726 if (!TM.Options.UnsafeFPMath) {
727 setOperationAction(ISD::FSIN , MVT::f64, Expand);
728 setOperationAction(ISD::FSIN , MVT::f32, Expand);
729 setOperationAction(ISD::FCOS , MVT::f64, Expand);
730 setOperationAction(ISD::FCOS , MVT::f32, Expand);
731 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
732 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
734 addLegalFPImmediate(APFloat(+0.0)); // FLD0
735 addLegalFPImmediate(APFloat(+1.0)); // FLD1
736 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
737 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
738 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
739 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
740 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
741 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
744 // We don't support FMA.
745 setOperationAction(ISD::FMA, MVT::f64, Expand);
746 setOperationAction(ISD::FMA, MVT::f32, Expand);
748 // Long double always uses X87.
749 if (!TM.Options.UseSoftFloat) {
750 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
751 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
752 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
754 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
755 addLegalFPImmediate(TmpFlt); // FLD0
757 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
760 APFloat TmpFlt2(+1.0);
761 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
763 addLegalFPImmediate(TmpFlt2); // FLD1
764 TmpFlt2.changeSign();
765 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
768 if (!TM.Options.UnsafeFPMath) {
769 setOperationAction(ISD::FSIN , MVT::f80, Expand);
770 setOperationAction(ISD::FCOS , MVT::f80, Expand);
771 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
774 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
775 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
776 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
777 setOperationAction(ISD::FRINT, MVT::f80, Expand);
778 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
779 setOperationAction(ISD::FMA, MVT::f80, Expand);
782 // Always use a library call for pow.
783 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
784 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
785 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
787 setOperationAction(ISD::FLOG, MVT::f80, Expand);
788 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
789 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
790 setOperationAction(ISD::FEXP, MVT::f80, Expand);
791 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
793 // First set operation action for all vector types to either promote
794 // (for widening) or expand (for scalarization). Then we will selectively
795 // turn on ones that can be effectively codegen'd.
796 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
797 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
798 MVT VT = (MVT::SimpleValueType)i;
799 setOperationAction(ISD::ADD , VT, Expand);
800 setOperationAction(ISD::SUB , VT, Expand);
801 setOperationAction(ISD::FADD, VT, Expand);
802 setOperationAction(ISD::FNEG, VT, Expand);
803 setOperationAction(ISD::FSUB, VT, Expand);
804 setOperationAction(ISD::MUL , VT, Expand);
805 setOperationAction(ISD::FMUL, VT, Expand);
806 setOperationAction(ISD::SDIV, VT, Expand);
807 setOperationAction(ISD::UDIV, VT, Expand);
808 setOperationAction(ISD::FDIV, VT, Expand);
809 setOperationAction(ISD::SREM, VT, Expand);
810 setOperationAction(ISD::UREM, VT, Expand);
811 setOperationAction(ISD::LOAD, VT, Expand);
812 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
813 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
814 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
815 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
816 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
817 setOperationAction(ISD::FABS, VT, Expand);
818 setOperationAction(ISD::FSIN, VT, Expand);
819 setOperationAction(ISD::FSINCOS, VT, Expand);
820 setOperationAction(ISD::FCOS, VT, Expand);
821 setOperationAction(ISD::FSINCOS, VT, Expand);
822 setOperationAction(ISD::FREM, VT, Expand);
823 setOperationAction(ISD::FMA, VT, Expand);
824 setOperationAction(ISD::FPOWI, VT, Expand);
825 setOperationAction(ISD::FSQRT, VT, Expand);
826 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
827 setOperationAction(ISD::FFLOOR, VT, Expand);
828 setOperationAction(ISD::FCEIL, VT, Expand);
829 setOperationAction(ISD::FTRUNC, VT, Expand);
830 setOperationAction(ISD::FRINT, VT, Expand);
831 setOperationAction(ISD::FNEARBYINT, VT, Expand);
832 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
833 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
834 setOperationAction(ISD::SDIVREM, VT, Expand);
835 setOperationAction(ISD::UDIVREM, VT, Expand);
836 setOperationAction(ISD::FPOW, VT, Expand);
837 setOperationAction(ISD::CTPOP, VT, Expand);
838 setOperationAction(ISD::CTTZ, VT, Expand);
839 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
840 setOperationAction(ISD::CTLZ, VT, Expand);
841 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
842 setOperationAction(ISD::SHL, VT, Expand);
843 setOperationAction(ISD::SRA, VT, Expand);
844 setOperationAction(ISD::SRL, VT, Expand);
845 setOperationAction(ISD::ROTL, VT, Expand);
846 setOperationAction(ISD::ROTR, VT, Expand);
847 setOperationAction(ISD::BSWAP, VT, Expand);
848 setOperationAction(ISD::SETCC, VT, Expand);
849 setOperationAction(ISD::FLOG, VT, Expand);
850 setOperationAction(ISD::FLOG2, VT, Expand);
851 setOperationAction(ISD::FLOG10, VT, Expand);
852 setOperationAction(ISD::FEXP, VT, Expand);
853 setOperationAction(ISD::FEXP2, VT, Expand);
854 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
855 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
856 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
857 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
858 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
859 setOperationAction(ISD::TRUNCATE, VT, Expand);
860 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
861 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
862 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
863 setOperationAction(ISD::VSELECT, VT, Expand);
864 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
865 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
866 setTruncStoreAction(VT,
867 (MVT::SimpleValueType)InnerVT, Expand);
868 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
869 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
870 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
873 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
874 // with -msoft-float, disable use of MMX as well.
875 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
876 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
877 // No operations on x86mmx supported, everything uses intrinsics.
880 // MMX-sized vectors (other than x86mmx) are expected to be expanded
881 // into smaller operations.
882 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
883 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
884 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
885 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
886 setOperationAction(ISD::AND, MVT::v8i8, Expand);
887 setOperationAction(ISD::AND, MVT::v4i16, Expand);
888 setOperationAction(ISD::AND, MVT::v2i32, Expand);
889 setOperationAction(ISD::AND, MVT::v1i64, Expand);
890 setOperationAction(ISD::OR, MVT::v8i8, Expand);
891 setOperationAction(ISD::OR, MVT::v4i16, Expand);
892 setOperationAction(ISD::OR, MVT::v2i32, Expand);
893 setOperationAction(ISD::OR, MVT::v1i64, Expand);
894 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
895 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
896 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
897 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
898 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
899 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
900 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
901 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
902 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
903 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
904 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
905 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
906 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
907 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
908 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
909 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
910 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
912 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
913 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
915 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
916 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
917 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
918 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
919 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
920 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
921 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
922 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
923 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
924 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
925 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
926 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
929 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
930 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
932 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
933 // registers cannot be used even for integer operations.
934 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
935 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
936 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
937 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
939 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
940 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
941 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
942 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
943 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
944 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
945 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
946 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
947 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
948 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
949 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
950 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
951 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
952 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
953 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
954 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
955 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
956 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
958 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
959 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
960 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
961 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
963 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
964 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
965 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
966 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
967 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
969 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
970 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
971 MVT VT = (MVT::SimpleValueType)i;
972 // Do not attempt to custom lower non-power-of-2 vectors
973 if (!isPowerOf2_32(VT.getVectorNumElements()))
975 // Do not attempt to custom lower non-128-bit vectors
976 if (!VT.is128BitVector())
978 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
979 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
980 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
983 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
984 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
985 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
986 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
987 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
988 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
990 if (Subtarget->is64Bit()) {
991 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
992 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
995 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
996 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
997 MVT VT = (MVT::SimpleValueType)i;
999 // Do not attempt to promote non-128-bit vectors
1000 if (!VT.is128BitVector())
1003 setOperationAction(ISD::AND, VT, Promote);
1004 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1005 setOperationAction(ISD::OR, VT, Promote);
1006 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1007 setOperationAction(ISD::XOR, VT, Promote);
1008 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1009 setOperationAction(ISD::LOAD, VT, Promote);
1010 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1011 setOperationAction(ISD::SELECT, VT, Promote);
1012 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1015 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
1017 // Custom lower v2i64 and v2f64 selects.
1018 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1019 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1020 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1021 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1023 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1024 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1026 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1027 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1028 // As there is no 64-bit GPR available, we need build a special custom
1029 // sequence to convert from v2i32 to v2f32.
1030 if (!Subtarget->is64Bit())
1031 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1033 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1034 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1036 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
1039 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1040 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1041 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1042 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1043 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1044 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1045 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1046 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1047 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1048 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1049 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1051 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1052 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1053 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1054 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1055 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1056 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1057 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1058 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1059 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1060 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1062 // FIXME: Do we need to handle scalar-to-vector here?
1063 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1065 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
1066 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal);
1067 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1068 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
1069 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
1071 // i8 and i16 vectors are custom , because the source register and source
1072 // source memory operand types are not the same width. f32 vectors are
1073 // custom since the immediate controlling the insert encodes additional
1075 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1076 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1077 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1078 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1080 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1081 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1082 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1083 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1085 // FIXME: these should be Legal but thats only for the case where
1086 // the index is constant. For now custom expand to deal with that.
1087 if (Subtarget->is64Bit()) {
1088 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1089 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1093 if (Subtarget->hasSSE2()) {
1094 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1095 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1097 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1098 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1100 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1101 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1103 // In the customized shift lowering, the legal cases in AVX2 will be
1105 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1106 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1108 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1109 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1111 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1113 setOperationAction(ISD::SDIV, MVT::v8i16, Custom);
1114 setOperationAction(ISD::SDIV, MVT::v4i32, Custom);
1117 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1118 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1119 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1120 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1121 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1122 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1123 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1125 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1126 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1127 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1129 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1130 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1131 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1132 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1133 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1134 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1135 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1136 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1137 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1138 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1139 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1140 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1142 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1143 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1144 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1145 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1146 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1147 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1148 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1149 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1150 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1151 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1152 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1153 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1155 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Custom);
1157 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1158 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1159 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1160 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1162 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1163 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1165 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1167 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1168 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1170 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1171 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1173 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1174 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1176 setOperationAction(ISD::SDIV, MVT::v16i16, Custom);
1178 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1179 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1180 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1181 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1183 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1184 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1185 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1187 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal);
1188 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal);
1189 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal);
1190 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal);
1192 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1193 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1194 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1195 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1196 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1197 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1198 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1199 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1200 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1201 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1202 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1203 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1205 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1206 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1207 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1208 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1209 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1210 setOperationAction(ISD::FMA, MVT::f32, Legal);
1211 setOperationAction(ISD::FMA, MVT::f64, Legal);
1214 if (Subtarget->hasInt256()) {
1215 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1216 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1217 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1218 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1220 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1221 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1222 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1223 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1225 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1226 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1227 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1228 // Don't lower v32i8 because there is no 128-bit byte mul
1230 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1232 setOperationAction(ISD::SDIV, MVT::v8i32, Custom);
1234 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1235 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1236 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1237 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1239 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1240 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1241 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1242 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1244 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1245 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1246 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1247 // Don't lower v32i8 because there is no 128-bit byte mul
1250 // In the customized shift lowering, the legal cases in AVX2 will be
1252 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1253 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1255 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1256 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1258 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1260 // Custom lower several nodes for 256-bit types.
1261 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1262 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1263 MVT VT = (MVT::SimpleValueType)i;
1265 // Extract subvector is special because the value type
1266 // (result) is 128-bit but the source is 256-bit wide.
1267 if (VT.is128BitVector())
1268 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1270 // Do not attempt to custom lower other non-256-bit vectors
1271 if (!VT.is256BitVector())
1274 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1275 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1276 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1277 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1278 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1279 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1280 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1283 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1284 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1285 MVT VT = (MVT::SimpleValueType)i;
1287 // Do not attempt to promote non-256-bit vectors
1288 if (!VT.is256BitVector())
1291 setOperationAction(ISD::AND, VT, Promote);
1292 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1293 setOperationAction(ISD::OR, VT, Promote);
1294 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1295 setOperationAction(ISD::XOR, VT, Promote);
1296 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1297 setOperationAction(ISD::LOAD, VT, Promote);
1298 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1299 setOperationAction(ISD::SELECT, VT, Promote);
1300 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1304 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1305 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1306 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1307 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1308 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1310 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1311 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1312 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1314 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1315 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1316 setOperationAction(ISD::XOR, MVT::i1, Legal);
1317 setOperationAction(ISD::OR, MVT::i1, Legal);
1318 setOperationAction(ISD::AND, MVT::i1, Legal);
1319 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, Legal);
1320 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1321 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1322 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1323 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1324 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1326 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1327 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1328 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1329 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1330 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1331 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1333 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1334 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1335 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1336 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1337 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1338 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1339 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1340 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1341 setOperationAction(ISD::SDIV, MVT::v16i32, Custom);
1343 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1344 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1345 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1346 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1347 if (Subtarget->is64Bit()) {
1348 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1349 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1350 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1351 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1353 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1354 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1355 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1356 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1357 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1358 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1359 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1360 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1362 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1363 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1364 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1365 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1366 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1367 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1368 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1369 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1370 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1371 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1372 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1373 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1374 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1376 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1377 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1378 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1379 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1380 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1381 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1383 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1384 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1386 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1388 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1389 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1390 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1391 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1392 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1393 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1394 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1396 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1397 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1399 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1400 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1402 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1404 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1405 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1407 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1408 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1410 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1411 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1413 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1414 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1415 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1416 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1417 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1418 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1420 // Custom lower several nodes.
1421 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1422 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1423 MVT VT = (MVT::SimpleValueType)i;
1425 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1426 // Extract subvector is special because the value type
1427 // (result) is 256/128-bit but the source is 512-bit wide.
1428 if (VT.is128BitVector() || VT.is256BitVector())
1429 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1431 if (VT.getVectorElementType() == MVT::i1)
1432 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1434 // Do not attempt to custom lower other non-512-bit vectors
1435 if (!VT.is512BitVector())
1438 if ( EltSize >= 32) {
1439 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1440 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1441 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1442 setOperationAction(ISD::VSELECT, VT, Legal);
1443 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1444 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1445 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1448 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1449 MVT VT = (MVT::SimpleValueType)i;
1451 // Do not attempt to promote non-256-bit vectors
1452 if (!VT.is512BitVector())
1455 setOperationAction(ISD::SELECT, VT, Promote);
1456 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1460 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1461 // of this type with custom code.
1462 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1463 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1464 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1468 // We want to custom lower some of our intrinsics.
1469 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1470 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1471 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1473 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1474 // handle type legalization for these operations here.
1476 // FIXME: We really should do custom legalization for addition and
1477 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1478 // than generic legalization for 64-bit multiplication-with-overflow, though.
1479 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1480 // Add/Sub/Mul with overflow operations are custom lowered.
1482 setOperationAction(ISD::SADDO, VT, Custom);
1483 setOperationAction(ISD::UADDO, VT, Custom);
1484 setOperationAction(ISD::SSUBO, VT, Custom);
1485 setOperationAction(ISD::USUBO, VT, Custom);
1486 setOperationAction(ISD::SMULO, VT, Custom);
1487 setOperationAction(ISD::UMULO, VT, Custom);
1490 // There are no 8-bit 3-address imul/mul instructions
1491 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1492 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1494 if (!Subtarget->is64Bit()) {
1495 // These libcalls are not available in 32-bit.
1496 setLibcallName(RTLIB::SHL_I128, 0);
1497 setLibcallName(RTLIB::SRL_I128, 0);
1498 setLibcallName(RTLIB::SRA_I128, 0);
1501 // Combine sin / cos into one node or libcall if possible.
1502 if (Subtarget->hasSinCos()) {
1503 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1504 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1505 if (Subtarget->isTargetDarwin()) {
1506 // For MacOSX, we don't want to the normal expansion of a libcall to
1507 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
1509 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1510 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1514 // We have target-specific dag combine patterns for the following nodes:
1515 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1516 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1517 setTargetDAGCombine(ISD::VSELECT);
1518 setTargetDAGCombine(ISD::SELECT);
1519 setTargetDAGCombine(ISD::SHL);
1520 setTargetDAGCombine(ISD::SRA);
1521 setTargetDAGCombine(ISD::SRL);
1522 setTargetDAGCombine(ISD::OR);
1523 setTargetDAGCombine(ISD::AND);
1524 setTargetDAGCombine(ISD::ADD);
1525 setTargetDAGCombine(ISD::FADD);
1526 setTargetDAGCombine(ISD::FSUB);
1527 setTargetDAGCombine(ISD::FMA);
1528 setTargetDAGCombine(ISD::SUB);
1529 setTargetDAGCombine(ISD::LOAD);
1530 setTargetDAGCombine(ISD::STORE);
1531 setTargetDAGCombine(ISD::ZERO_EXTEND);
1532 setTargetDAGCombine(ISD::ANY_EXTEND);
1533 setTargetDAGCombine(ISD::SIGN_EXTEND);
1534 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1535 setTargetDAGCombine(ISD::TRUNCATE);
1536 setTargetDAGCombine(ISD::SINT_TO_FP);
1537 setTargetDAGCombine(ISD::SETCC);
1538 if (Subtarget->is64Bit())
1539 setTargetDAGCombine(ISD::MUL);
1540 setTargetDAGCombine(ISD::XOR);
1542 computeRegisterProperties();
1544 // On Darwin, -Os means optimize for size without hurting performance,
1545 // do not reduce the limit.
1546 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1547 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1548 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1549 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1550 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1551 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1552 setPrefLoopAlignment(4); // 2^4 bytes.
1554 // Predictable cmov don't hurt on atom because it's in-order.
1555 PredictableSelectIsExpensive = !Subtarget->isAtom();
1557 setPrefFunctionAlignment(4); // 2^4 bytes.
1560 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1562 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1564 if (Subtarget->hasAVX512())
1565 switch(VT.getVectorNumElements()) {
1566 case 8: return MVT::v8i1;
1567 case 16: return MVT::v16i1;
1570 return VT.changeVectorElementTypeToInteger();
1573 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1574 /// the desired ByVal argument alignment.
1575 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1578 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1579 if (VTy->getBitWidth() == 128)
1581 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1582 unsigned EltAlign = 0;
1583 getMaxByValAlign(ATy->getElementType(), EltAlign);
1584 if (EltAlign > MaxAlign)
1585 MaxAlign = EltAlign;
1586 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1587 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1588 unsigned EltAlign = 0;
1589 getMaxByValAlign(STy->getElementType(i), EltAlign);
1590 if (EltAlign > MaxAlign)
1591 MaxAlign = EltAlign;
1598 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1599 /// function arguments in the caller parameter area. For X86, aggregates
1600 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1601 /// are at 4-byte boundaries.
1602 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1603 if (Subtarget->is64Bit()) {
1604 // Max of 8 and alignment of type.
1605 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1612 if (Subtarget->hasSSE1())
1613 getMaxByValAlign(Ty, Align);
1617 /// getOptimalMemOpType - Returns the target specific optimal type for load
1618 /// and store operations as a result of memset, memcpy, and memmove
1619 /// lowering. If DstAlign is zero that means it's safe to destination
1620 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1621 /// means there isn't a need to check it against alignment requirement,
1622 /// probably because the source does not need to be loaded. If 'IsMemset' is
1623 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1624 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1625 /// source is constant so it does not need to be loaded.
1626 /// It returns EVT::Other if the type should be determined using generic
1627 /// target-independent logic.
1629 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1630 unsigned DstAlign, unsigned SrcAlign,
1631 bool IsMemset, bool ZeroMemset,
1633 MachineFunction &MF) const {
1634 const Function *F = MF.getFunction();
1635 if ((!IsMemset || ZeroMemset) &&
1636 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1637 Attribute::NoImplicitFloat)) {
1639 (Subtarget->isUnalignedMemAccessFast() ||
1640 ((DstAlign == 0 || DstAlign >= 16) &&
1641 (SrcAlign == 0 || SrcAlign >= 16)))) {
1643 if (Subtarget->hasInt256())
1645 if (Subtarget->hasFp256())
1648 if (Subtarget->hasSSE2())
1650 if (Subtarget->hasSSE1())
1652 } else if (!MemcpyStrSrc && Size >= 8 &&
1653 !Subtarget->is64Bit() &&
1654 Subtarget->hasSSE2()) {
1655 // Do not use f64 to lower memcpy if source is string constant. It's
1656 // better to use i32 to avoid the loads.
1660 if (Subtarget->is64Bit() && Size >= 8)
1665 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1667 return X86ScalarSSEf32;
1668 else if (VT == MVT::f64)
1669 return X86ScalarSSEf64;
1674 X86TargetLowering::allowsUnalignedMemoryAccesses(EVT VT,
1678 *Fast = Subtarget->isUnalignedMemAccessFast();
1682 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1683 /// current function. The returned value is a member of the
1684 /// MachineJumpTableInfo::JTEntryKind enum.
1685 unsigned X86TargetLowering::getJumpTableEncoding() const {
1686 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1688 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1689 Subtarget->isPICStyleGOT())
1690 return MachineJumpTableInfo::EK_Custom32;
1692 // Otherwise, use the normal jump table encoding heuristics.
1693 return TargetLowering::getJumpTableEncoding();
1697 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1698 const MachineBasicBlock *MBB,
1699 unsigned uid,MCContext &Ctx) const{
1700 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1701 Subtarget->isPICStyleGOT());
1702 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1704 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1705 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1708 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1710 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1711 SelectionDAG &DAG) const {
1712 if (!Subtarget->is64Bit())
1713 // This doesn't have SDLoc associated with it, but is not really the
1714 // same as a Register.
1715 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1719 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1720 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1722 const MCExpr *X86TargetLowering::
1723 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1724 MCContext &Ctx) const {
1725 // X86-64 uses RIP relative addressing based on the jump table label.
1726 if (Subtarget->isPICStyleRIPRel())
1727 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1729 // Otherwise, the reference is relative to the PIC base.
1730 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1733 // FIXME: Why this routine is here? Move to RegInfo!
1734 std::pair<const TargetRegisterClass*, uint8_t>
1735 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1736 const TargetRegisterClass *RRC = 0;
1738 switch (VT.SimpleTy) {
1740 return TargetLowering::findRepresentativeClass(VT);
1741 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1742 RRC = Subtarget->is64Bit() ?
1743 (const TargetRegisterClass*)&X86::GR64RegClass :
1744 (const TargetRegisterClass*)&X86::GR32RegClass;
1747 RRC = &X86::VR64RegClass;
1749 case MVT::f32: case MVT::f64:
1750 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1751 case MVT::v4f32: case MVT::v2f64:
1752 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1754 RRC = &X86::VR128RegClass;
1757 return std::make_pair(RRC, Cost);
1760 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1761 unsigned &Offset) const {
1762 if (!Subtarget->isTargetLinux())
1765 if (Subtarget->is64Bit()) {
1766 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1768 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1780 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1781 unsigned DestAS) const {
1782 assert(SrcAS != DestAS && "Expected different address spaces!");
1784 return SrcAS < 256 && DestAS < 256;
1787 //===----------------------------------------------------------------------===//
1788 // Return Value Calling Convention Implementation
1789 //===----------------------------------------------------------------------===//
1791 #include "X86GenCallingConv.inc"
1794 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1795 MachineFunction &MF, bool isVarArg,
1796 const SmallVectorImpl<ISD::OutputArg> &Outs,
1797 LLVMContext &Context) const {
1798 SmallVector<CCValAssign, 16> RVLocs;
1799 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1801 return CCInfo.CheckReturn(Outs, RetCC_X86);
1804 const uint16_t *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1805 static const uint16_t ScratchRegs[] = { X86::R11, 0 };
1810 X86TargetLowering::LowerReturn(SDValue Chain,
1811 CallingConv::ID CallConv, bool isVarArg,
1812 const SmallVectorImpl<ISD::OutputArg> &Outs,
1813 const SmallVectorImpl<SDValue> &OutVals,
1814 SDLoc dl, SelectionDAG &DAG) const {
1815 MachineFunction &MF = DAG.getMachineFunction();
1816 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1818 SmallVector<CCValAssign, 16> RVLocs;
1819 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1820 RVLocs, *DAG.getContext());
1821 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1824 SmallVector<SDValue, 6> RetOps;
1825 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1826 // Operand #1 = Bytes To Pop
1827 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1830 // Copy the result values into the output registers.
1831 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1832 CCValAssign &VA = RVLocs[i];
1833 assert(VA.isRegLoc() && "Can only return in registers!");
1834 SDValue ValToCopy = OutVals[i];
1835 EVT ValVT = ValToCopy.getValueType();
1837 // Promote values to the appropriate types
1838 if (VA.getLocInfo() == CCValAssign::SExt)
1839 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
1840 else if (VA.getLocInfo() == CCValAssign::ZExt)
1841 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
1842 else if (VA.getLocInfo() == CCValAssign::AExt)
1843 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
1844 else if (VA.getLocInfo() == CCValAssign::BCvt)
1845 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
1847 assert(VA.getLocInfo() != CCValAssign::FPExt &&
1848 "Unexpected FP-extend for return value.");
1850 // If this is x86-64, and we disabled SSE, we can't return FP values,
1851 // or SSE or MMX vectors.
1852 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1853 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1854 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1855 report_fatal_error("SSE register return with SSE disabled");
1857 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1858 // llvm-gcc has never done it right and no one has noticed, so this
1859 // should be OK for now.
1860 if (ValVT == MVT::f64 &&
1861 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1862 report_fatal_error("SSE2 register return with SSE2 disabled");
1864 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1865 // the RET instruction and handled by the FP Stackifier.
1866 if (VA.getLocReg() == X86::ST0 ||
1867 VA.getLocReg() == X86::ST1) {
1868 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1869 // change the value to the FP stack register class.
1870 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1871 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1872 RetOps.push_back(ValToCopy);
1873 // Don't emit a copytoreg.
1877 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1878 // which is returned in RAX / RDX.
1879 if (Subtarget->is64Bit()) {
1880 if (ValVT == MVT::x86mmx) {
1881 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1882 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1883 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1885 // If we don't have SSE2 available, convert to v4f32 so the generated
1886 // register is legal.
1887 if (!Subtarget->hasSSE2())
1888 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1893 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1894 Flag = Chain.getValue(1);
1895 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
1898 // The x86-64 ABIs require that for returning structs by value we copy
1899 // the sret argument into %rax/%eax (depending on ABI) for the return.
1900 // Win32 requires us to put the sret argument to %eax as well.
1901 // We saved the argument into a virtual register in the entry block,
1902 // so now we copy the value out and into %rax/%eax.
1903 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
1904 (Subtarget->is64Bit() || Subtarget->isTargetWindows())) {
1905 MachineFunction &MF = DAG.getMachineFunction();
1906 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1907 unsigned Reg = FuncInfo->getSRetReturnReg();
1909 "SRetReturnReg should have been set in LowerFormalArguments().");
1910 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1913 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
1914 X86::RAX : X86::EAX;
1915 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
1916 Flag = Chain.getValue(1);
1918 // RAX/EAX now acts like a return value.
1919 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
1922 RetOps[0] = Chain; // Update chain.
1924 // Add the flag if we have it.
1926 RetOps.push_back(Flag);
1928 return DAG.getNode(X86ISD::RET_FLAG, dl,
1929 MVT::Other, &RetOps[0], RetOps.size());
1932 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
1933 if (N->getNumValues() != 1)
1935 if (!N->hasNUsesOfValue(1, 0))
1938 SDValue TCChain = Chain;
1939 SDNode *Copy = *N->use_begin();
1940 if (Copy->getOpcode() == ISD::CopyToReg) {
1941 // If the copy has a glue operand, we conservatively assume it isn't safe to
1942 // perform a tail call.
1943 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
1945 TCChain = Copy->getOperand(0);
1946 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
1949 bool HasRet = false;
1950 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1952 if (UI->getOpcode() != X86ISD::RET_FLAG)
1965 X86TargetLowering::getTypeForExtArgOrReturn(MVT VT,
1966 ISD::NodeType ExtendKind) const {
1968 // TODO: Is this also valid on 32-bit?
1969 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
1970 ReturnMVT = MVT::i8;
1972 ReturnMVT = MVT::i32;
1974 MVT MinVT = getRegisterType(ReturnMVT);
1975 return VT.bitsLT(MinVT) ? MinVT : VT;
1978 /// LowerCallResult - Lower the result values of a call into the
1979 /// appropriate copies out of appropriate physical registers.
1982 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1983 CallingConv::ID CallConv, bool isVarArg,
1984 const SmallVectorImpl<ISD::InputArg> &Ins,
1985 SDLoc dl, SelectionDAG &DAG,
1986 SmallVectorImpl<SDValue> &InVals) const {
1988 // Assign locations to each value returned by this call.
1989 SmallVector<CCValAssign, 16> RVLocs;
1990 bool Is64Bit = Subtarget->is64Bit();
1991 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1992 getTargetMachine(), RVLocs, *DAG.getContext());
1993 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1995 // Copy all of the result registers out of their specified physreg.
1996 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
1997 CCValAssign &VA = RVLocs[i];
1998 EVT CopyVT = VA.getValVT();
2000 // If this is x86-64, and we disabled SSE, we can't return FP values
2001 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2002 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2003 report_fatal_error("SSE register return with SSE disabled");
2008 // If this is a call to a function that returns an fp value on the floating
2009 // point stack, we must guarantee the value is popped from the stack, so
2010 // a CopyFromReg is not good enough - the copy instruction may be eliminated
2011 // if the return value is not used. We use the FpPOP_RETVAL instruction
2013 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
2014 // If we prefer to use the value in xmm registers, copy it out as f80 and
2015 // use a truncate to move it from fp stack reg to xmm reg.
2016 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
2017 SDValue Ops[] = { Chain, InFlag };
2018 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT,
2019 MVT::Other, MVT::Glue, Ops), 1);
2020 Val = Chain.getValue(0);
2022 // Round the f80 to the right size, which also moves it to the appropriate
2024 if (CopyVT != VA.getValVT())
2025 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2026 // This truncation won't change the value.
2027 DAG.getIntPtrConstant(1));
2029 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2030 CopyVT, InFlag).getValue(1);
2031 Val = Chain.getValue(0);
2033 InFlag = Chain.getValue(2);
2034 InVals.push_back(Val);
2040 //===----------------------------------------------------------------------===//
2041 // C & StdCall & Fast Calling Convention implementation
2042 //===----------------------------------------------------------------------===//
2043 // StdCall calling convention seems to be standard for many Windows' API
2044 // routines and around. It differs from C calling convention just a little:
2045 // callee should clean up the stack, not caller. Symbols should be also
2046 // decorated in some fancy way :) It doesn't support any vector arguments.
2047 // For info on fast calling convention see Fast Calling Convention (tail call)
2048 // implementation LowerX86_32FastCCCallTo.
2050 /// CallIsStructReturn - Determines whether a call uses struct return
2052 enum StructReturnType {
2057 static StructReturnType
2058 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2060 return NotStructReturn;
2062 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2063 if (!Flags.isSRet())
2064 return NotStructReturn;
2065 if (Flags.isInReg())
2066 return RegStructReturn;
2067 return StackStructReturn;
2070 /// ArgsAreStructReturn - Determines whether a function uses struct
2071 /// return semantics.
2072 static StructReturnType
2073 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2075 return NotStructReturn;
2077 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2078 if (!Flags.isSRet())
2079 return NotStructReturn;
2080 if (Flags.isInReg())
2081 return RegStructReturn;
2082 return StackStructReturn;
2085 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2086 /// by "Src" to address "Dst" with size and alignment information specified by
2087 /// the specific parameter attribute. The copy will be passed as a byval
2088 /// function parameter.
2090 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2091 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2093 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2095 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2096 /*isVolatile*/false, /*AlwaysInline=*/true,
2097 MachinePointerInfo(), MachinePointerInfo());
2100 /// IsTailCallConvention - Return true if the calling convention is one that
2101 /// supports tail call optimization.
2102 static bool IsTailCallConvention(CallingConv::ID CC) {
2103 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2104 CC == CallingConv::HiPE);
2107 /// \brief Return true if the calling convention is a C calling convention.
2108 static bool IsCCallConvention(CallingConv::ID CC) {
2109 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2110 CC == CallingConv::X86_64_SysV);
2113 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2114 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2118 CallingConv::ID CalleeCC = CS.getCallingConv();
2119 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2125 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
2126 /// a tailcall target by changing its ABI.
2127 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2128 bool GuaranteedTailCallOpt) {
2129 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2133 X86TargetLowering::LowerMemArgument(SDValue Chain,
2134 CallingConv::ID CallConv,
2135 const SmallVectorImpl<ISD::InputArg> &Ins,
2136 SDLoc dl, SelectionDAG &DAG,
2137 const CCValAssign &VA,
2138 MachineFrameInfo *MFI,
2140 // Create the nodes corresponding to a load from this parameter slot.
2141 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2142 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv,
2143 getTargetMachine().Options.GuaranteedTailCallOpt);
2144 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2147 // If value is passed by pointer we have address passed instead of the value
2149 if (VA.getLocInfo() == CCValAssign::Indirect)
2150 ValVT = VA.getLocVT();
2152 ValVT = VA.getValVT();
2154 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2155 // changed with more analysis.
2156 // In case of tail call optimization mark all arguments mutable. Since they
2157 // could be overwritten by lowering of arguments in case of a tail call.
2158 if (Flags.isByVal()) {
2159 unsigned Bytes = Flags.getByValSize();
2160 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2161 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2162 return DAG.getFrameIndex(FI, getPointerTy());
2164 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2165 VA.getLocMemOffset(), isImmutable);
2166 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2167 return DAG.getLoad(ValVT, dl, Chain, FIN,
2168 MachinePointerInfo::getFixedStack(FI),
2169 false, false, false, 0);
2174 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2175 CallingConv::ID CallConv,
2177 const SmallVectorImpl<ISD::InputArg> &Ins,
2180 SmallVectorImpl<SDValue> &InVals)
2182 MachineFunction &MF = DAG.getMachineFunction();
2183 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2185 const Function* Fn = MF.getFunction();
2186 if (Fn->hasExternalLinkage() &&
2187 Subtarget->isTargetCygMing() &&
2188 Fn->getName() == "main")
2189 FuncInfo->setForceFramePointer(true);
2191 MachineFrameInfo *MFI = MF.getFrameInfo();
2192 bool Is64Bit = Subtarget->is64Bit();
2193 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2195 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2196 "Var args not supported with calling convention fastcc, ghc or hipe");
2198 // Assign locations to all of the incoming arguments.
2199 SmallVector<CCValAssign, 16> ArgLocs;
2200 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2201 ArgLocs, *DAG.getContext());
2203 // Allocate shadow area for Win64
2205 CCInfo.AllocateStack(32, 8);
2207 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2209 unsigned LastVal = ~0U;
2211 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2212 CCValAssign &VA = ArgLocs[i];
2213 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2215 assert(VA.getValNo() != LastVal &&
2216 "Don't support value assigned to multiple locs yet");
2218 LastVal = VA.getValNo();
2220 if (VA.isRegLoc()) {
2221 EVT RegVT = VA.getLocVT();
2222 const TargetRegisterClass *RC;
2223 if (RegVT == MVT::i32)
2224 RC = &X86::GR32RegClass;
2225 else if (Is64Bit && RegVT == MVT::i64)
2226 RC = &X86::GR64RegClass;
2227 else if (RegVT == MVT::f32)
2228 RC = &X86::FR32RegClass;
2229 else if (RegVT == MVT::f64)
2230 RC = &X86::FR64RegClass;
2231 else if (RegVT.is512BitVector())
2232 RC = &X86::VR512RegClass;
2233 else if (RegVT.is256BitVector())
2234 RC = &X86::VR256RegClass;
2235 else if (RegVT.is128BitVector())
2236 RC = &X86::VR128RegClass;
2237 else if (RegVT == MVT::x86mmx)
2238 RC = &X86::VR64RegClass;
2239 else if (RegVT == MVT::i1)
2240 RC = &X86::VK1RegClass;
2241 else if (RegVT == MVT::v8i1)
2242 RC = &X86::VK8RegClass;
2243 else if (RegVT == MVT::v16i1)
2244 RC = &X86::VK16RegClass;
2246 llvm_unreachable("Unknown argument type!");
2248 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2249 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2251 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2252 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2254 if (VA.getLocInfo() == CCValAssign::SExt)
2255 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2256 DAG.getValueType(VA.getValVT()));
2257 else if (VA.getLocInfo() == CCValAssign::ZExt)
2258 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2259 DAG.getValueType(VA.getValVT()));
2260 else if (VA.getLocInfo() == CCValAssign::BCvt)
2261 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2263 if (VA.isExtInLoc()) {
2264 // Handle MMX values passed in XMM regs.
2265 if (RegVT.isVector())
2266 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2268 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2271 assert(VA.isMemLoc());
2272 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2275 // If value is passed via pointer - do a load.
2276 if (VA.getLocInfo() == CCValAssign::Indirect)
2277 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2278 MachinePointerInfo(), false, false, false, 0);
2280 InVals.push_back(ArgValue);
2283 // The x86-64 ABIs require that for returning structs by value we copy
2284 // the sret argument into %rax/%eax (depending on ABI) for the return.
2285 // Win32 requires us to put the sret argument to %eax as well.
2286 // Save the argument into a virtual register so that we can access it
2287 // from the return points.
2288 if (MF.getFunction()->hasStructRetAttr() &&
2289 (Subtarget->is64Bit() || Subtarget->isTargetWindows())) {
2290 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2291 unsigned Reg = FuncInfo->getSRetReturnReg();
2293 MVT PtrTy = getPointerTy();
2294 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2295 FuncInfo->setSRetReturnReg(Reg);
2297 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
2298 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2301 unsigned StackSize = CCInfo.getNextStackOffset();
2302 // Align stack specially for tail calls.
2303 if (FuncIsMadeTailCallSafe(CallConv,
2304 MF.getTarget().Options.GuaranteedTailCallOpt))
2305 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2307 // If the function takes variable number of arguments, make a frame index for
2308 // the start of the first vararg value... for expansion of llvm.va_start.
2310 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2311 CallConv != CallingConv::X86_ThisCall)) {
2312 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
2315 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
2317 // FIXME: We should really autogenerate these arrays
2318 static const uint16_t GPR64ArgRegsWin64[] = {
2319 X86::RCX, X86::RDX, X86::R8, X86::R9
2321 static const uint16_t GPR64ArgRegs64Bit[] = {
2322 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2324 static const uint16_t XMMArgRegs64Bit[] = {
2325 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2326 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2328 const uint16_t *GPR64ArgRegs;
2329 unsigned NumXMMRegs = 0;
2332 // The XMM registers which might contain var arg parameters are shadowed
2333 // in their paired GPR. So we only need to save the GPR to their home
2335 TotalNumIntRegs = 4;
2336 GPR64ArgRegs = GPR64ArgRegsWin64;
2338 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
2339 GPR64ArgRegs = GPR64ArgRegs64Bit;
2341 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit,
2344 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
2347 bool NoImplicitFloatOps = Fn->getAttributes().
2348 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2349 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2350 "SSE register cannot be used when SSE is disabled!");
2351 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat &&
2352 NoImplicitFloatOps) &&
2353 "SSE register cannot be used when SSE is disabled!");
2354 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2355 !Subtarget->hasSSE1())
2356 // Kernel mode asks for SSE to be disabled, so don't push them
2358 TotalNumXMMRegs = 0;
2361 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering();
2362 // Get to the caller-allocated home save location. Add 8 to account
2363 // for the return address.
2364 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2365 FuncInfo->setRegSaveFrameIndex(
2366 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2367 // Fixup to set vararg frame on shadow area (4 x i64).
2369 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2371 // For X86-64, if there are vararg parameters that are passed via
2372 // registers, then we must store them to their spots on the stack so
2373 // they may be loaded by deferencing the result of va_next.
2374 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2375 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
2376 FuncInfo->setRegSaveFrameIndex(
2377 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
2381 // Store the integer parameter registers.
2382 SmallVector<SDValue, 8> MemOps;
2383 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2385 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2386 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
2387 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2388 DAG.getIntPtrConstant(Offset));
2389 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
2390 &X86::GR64RegClass);
2391 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2393 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2394 MachinePointerInfo::getFixedStack(
2395 FuncInfo->getRegSaveFrameIndex(), Offset),
2397 MemOps.push_back(Store);
2401 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
2402 // Now store the XMM (fp + vector) parameter registers.
2403 SmallVector<SDValue, 11> SaveXMMOps;
2404 SaveXMMOps.push_back(Chain);
2406 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2407 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
2408 SaveXMMOps.push_back(ALVal);
2410 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2411 FuncInfo->getRegSaveFrameIndex()));
2412 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2413 FuncInfo->getVarArgsFPOffset()));
2415 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
2416 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
2417 &X86::VR128RegClass);
2418 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
2419 SaveXMMOps.push_back(Val);
2421 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2423 &SaveXMMOps[0], SaveXMMOps.size()));
2426 if (!MemOps.empty())
2427 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2428 &MemOps[0], MemOps.size());
2432 // Some CCs need callee pop.
2433 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2434 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2435 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2437 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2438 // If this is an sret function, the return should pop the hidden pointer.
2439 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2440 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2441 argsAreStructReturn(Ins) == StackStructReturn)
2442 FuncInfo->setBytesToPopOnReturn(4);
2446 // RegSaveFrameIndex is X86-64 only.
2447 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2448 if (CallConv == CallingConv::X86_FastCall ||
2449 CallConv == CallingConv::X86_ThisCall)
2450 // fastcc functions can't have varargs.
2451 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2454 FuncInfo->setArgumentStackSize(StackSize);
2460 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2461 SDValue StackPtr, SDValue Arg,
2462 SDLoc dl, SelectionDAG &DAG,
2463 const CCValAssign &VA,
2464 ISD::ArgFlagsTy Flags) const {
2465 unsigned LocMemOffset = VA.getLocMemOffset();
2466 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2467 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2468 if (Flags.isByVal())
2469 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2471 return DAG.getStore(Chain, dl, Arg, PtrOff,
2472 MachinePointerInfo::getStack(LocMemOffset),
2476 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2477 /// optimization is performed and it is required.
2479 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2480 SDValue &OutRetAddr, SDValue Chain,
2481 bool IsTailCall, bool Is64Bit,
2482 int FPDiff, SDLoc dl) const {
2483 // Adjust the Return address stack slot.
2484 EVT VT = getPointerTy();
2485 OutRetAddr = getReturnAddressFrameIndex(DAG);
2487 // Load the "old" Return address.
2488 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2489 false, false, false, 0);
2490 return SDValue(OutRetAddr.getNode(), 1);
2493 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2494 /// optimization is performed and it is required (FPDiff!=0).
2496 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
2497 SDValue Chain, SDValue RetAddrFrIdx, EVT PtrVT,
2498 unsigned SlotSize, int FPDiff, SDLoc dl) {
2499 // Store the return address to the appropriate stack slot.
2500 if (!FPDiff) return Chain;
2501 // Calculate the new stack slot for the return address.
2502 int NewReturnAddrFI =
2503 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2505 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2506 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2507 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2513 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2514 SmallVectorImpl<SDValue> &InVals) const {
2515 SelectionDAG &DAG = CLI.DAG;
2517 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2518 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2519 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2520 SDValue Chain = CLI.Chain;
2521 SDValue Callee = CLI.Callee;
2522 CallingConv::ID CallConv = CLI.CallConv;
2523 bool &isTailCall = CLI.IsTailCall;
2524 bool isVarArg = CLI.IsVarArg;
2526 MachineFunction &MF = DAG.getMachineFunction();
2527 bool Is64Bit = Subtarget->is64Bit();
2528 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2529 StructReturnType SR = callIsStructReturn(Outs);
2530 bool IsSibcall = false;
2532 if (MF.getTarget().Options.DisableTailCalls)
2536 // Check if it's really possible to do a tail call.
2537 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2538 isVarArg, SR != NotStructReturn,
2539 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2540 Outs, OutVals, Ins, DAG);
2542 // Sibcalls are automatically detected tailcalls which do not require
2544 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2551 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2552 "Var args not supported with calling convention fastcc, ghc or hipe");
2554 // Analyze operands of the call, assigning locations to each operand.
2555 SmallVector<CCValAssign, 16> ArgLocs;
2556 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2557 ArgLocs, *DAG.getContext());
2559 // Allocate shadow area for Win64
2561 CCInfo.AllocateStack(32, 8);
2563 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2565 // Get a count of how many bytes are to be pushed on the stack.
2566 unsigned NumBytes = CCInfo.getNextStackOffset();
2568 // This is a sibcall. The memory operands are available in caller's
2569 // own caller's stack.
2571 else if (getTargetMachine().Options.GuaranteedTailCallOpt &&
2572 IsTailCallConvention(CallConv))
2573 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2576 if (isTailCall && !IsSibcall) {
2577 // Lower arguments at fp - stackoffset + fpdiff.
2578 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2579 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2581 FPDiff = NumBytesCallerPushed - NumBytes;
2583 // Set the delta of movement of the returnaddr stackslot.
2584 // But only set if delta is greater than previous delta.
2585 if (FPDiff < X86Info->getTCReturnAddrDelta())
2586 X86Info->setTCReturnAddrDelta(FPDiff);
2589 unsigned NumBytesToPush = NumBytes;
2590 unsigned NumBytesToPop = NumBytes;
2592 // If we have an inalloca argument, all stack space has already been allocated
2593 // for us and be right at the top of the stack. We don't support multiple
2594 // arguments passed in memory when using inalloca.
2595 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2597 assert(ArgLocs.back().getLocMemOffset() == 0 &&
2598 "an inalloca argument must be the only memory argument");
2602 Chain = DAG.getCALLSEQ_START(
2603 Chain, DAG.getIntPtrConstant(NumBytesToPush, true), dl);
2605 SDValue RetAddrFrIdx;
2606 // Load return address for tail calls.
2607 if (isTailCall && FPDiff)
2608 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2609 Is64Bit, FPDiff, dl);
2611 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2612 SmallVector<SDValue, 8> MemOpChains;
2615 // Walk the register/memloc assignments, inserting copies/loads. In the case
2616 // of tail call optimization arguments are handle later.
2617 const X86RegisterInfo *RegInfo =
2618 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
2619 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2620 // Skip inalloca arguments, they have already been written.
2621 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2622 if (Flags.isInAlloca())
2625 CCValAssign &VA = ArgLocs[i];
2626 EVT RegVT = VA.getLocVT();
2627 SDValue Arg = OutVals[i];
2628 bool isByVal = Flags.isByVal();
2630 // Promote the value if needed.
2631 switch (VA.getLocInfo()) {
2632 default: llvm_unreachable("Unknown loc info!");
2633 case CCValAssign::Full: break;
2634 case CCValAssign::SExt:
2635 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2637 case CCValAssign::ZExt:
2638 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2640 case CCValAssign::AExt:
2641 if (RegVT.is128BitVector()) {
2642 // Special case: passing MMX values in XMM registers.
2643 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2644 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2645 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2647 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2649 case CCValAssign::BCvt:
2650 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2652 case CCValAssign::Indirect: {
2653 // Store the argument.
2654 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2655 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2656 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2657 MachinePointerInfo::getFixedStack(FI),
2664 if (VA.isRegLoc()) {
2665 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2666 if (isVarArg && IsWin64) {
2667 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2668 // shadow reg if callee is a varargs function.
2669 unsigned ShadowReg = 0;
2670 switch (VA.getLocReg()) {
2671 case X86::XMM0: ShadowReg = X86::RCX; break;
2672 case X86::XMM1: ShadowReg = X86::RDX; break;
2673 case X86::XMM2: ShadowReg = X86::R8; break;
2674 case X86::XMM3: ShadowReg = X86::R9; break;
2677 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2679 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2680 assert(VA.isMemLoc());
2681 if (StackPtr.getNode() == 0)
2682 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2684 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2685 dl, DAG, VA, Flags));
2689 if (!MemOpChains.empty())
2690 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2691 &MemOpChains[0], MemOpChains.size());
2693 if (Subtarget->isPICStyleGOT()) {
2694 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2697 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2698 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2700 // If we are tail calling and generating PIC/GOT style code load the
2701 // address of the callee into ECX. The value in ecx is used as target of
2702 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2703 // for tail calls on PIC/GOT architectures. Normally we would just put the
2704 // address of GOT into ebx and then call target@PLT. But for tail calls
2705 // ebx would be restored (since ebx is callee saved) before jumping to the
2708 // Note: The actual moving to ECX is done further down.
2709 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2710 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2711 !G->getGlobal()->hasProtectedVisibility())
2712 Callee = LowerGlobalAddress(Callee, DAG);
2713 else if (isa<ExternalSymbolSDNode>(Callee))
2714 Callee = LowerExternalSymbol(Callee, DAG);
2718 if (Is64Bit && isVarArg && !IsWin64) {
2719 // From AMD64 ABI document:
2720 // For calls that may call functions that use varargs or stdargs
2721 // (prototype-less calls or calls to functions containing ellipsis (...) in
2722 // the declaration) %al is used as hidden argument to specify the number
2723 // of SSE registers used. The contents of %al do not need to match exactly
2724 // the number of registers, but must be an ubound on the number of SSE
2725 // registers used and is in the range 0 - 8 inclusive.
2727 // Count the number of XMM registers allocated.
2728 static const uint16_t XMMArgRegs[] = {
2729 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2730 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2732 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2733 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2734 && "SSE registers cannot be used when SSE is disabled");
2736 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2737 DAG.getConstant(NumXMMRegs, MVT::i8)));
2740 // For tail calls lower the arguments to the 'real' stack slot.
2742 // Force all the incoming stack arguments to be loaded from the stack
2743 // before any new outgoing arguments are stored to the stack, because the
2744 // outgoing stack slots may alias the incoming argument stack slots, and
2745 // the alias isn't otherwise explicit. This is slightly more conservative
2746 // than necessary, because it means that each store effectively depends
2747 // on every argument instead of just those arguments it would clobber.
2748 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2750 SmallVector<SDValue, 8> MemOpChains2;
2753 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2754 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2755 CCValAssign &VA = ArgLocs[i];
2758 assert(VA.isMemLoc());
2759 SDValue Arg = OutVals[i];
2760 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2761 // Create frame index.
2762 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2763 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2764 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2765 FIN = DAG.getFrameIndex(FI, getPointerTy());
2767 if (Flags.isByVal()) {
2768 // Copy relative to framepointer.
2769 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2770 if (StackPtr.getNode() == 0)
2771 StackPtr = DAG.getCopyFromReg(Chain, dl,
2772 RegInfo->getStackRegister(),
2774 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2776 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2780 // Store relative to framepointer.
2781 MemOpChains2.push_back(
2782 DAG.getStore(ArgChain, dl, Arg, FIN,
2783 MachinePointerInfo::getFixedStack(FI),
2789 if (!MemOpChains2.empty())
2790 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2791 &MemOpChains2[0], MemOpChains2.size());
2793 // Store the return address to the appropriate stack slot.
2794 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
2795 getPointerTy(), RegInfo->getSlotSize(),
2799 // Build a sequence of copy-to-reg nodes chained together with token chain
2800 // and flag operands which copy the outgoing args into registers.
2802 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2803 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2804 RegsToPass[i].second, InFlag);
2805 InFlag = Chain.getValue(1);
2808 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2809 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2810 // In the 64-bit large code model, we have to make all calls
2811 // through a register, since the call instruction's 32-bit
2812 // pc-relative offset may not be large enough to hold the whole
2814 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2815 // If the callee is a GlobalAddress node (quite common, every direct call
2816 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2819 // We should use extra load for direct calls to dllimported functions in
2821 const GlobalValue *GV = G->getGlobal();
2822 if (!GV->hasDLLImportStorageClass()) {
2823 unsigned char OpFlags = 0;
2824 bool ExtraLoad = false;
2825 unsigned WrapperKind = ISD::DELETED_NODE;
2827 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2828 // external symbols most go through the PLT in PIC mode. If the symbol
2829 // has hidden or protected visibility, or if it is static or local, then
2830 // we don't need to use the PLT - we can directly call it.
2831 if (Subtarget->isTargetELF() &&
2832 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2833 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2834 OpFlags = X86II::MO_PLT;
2835 } else if (Subtarget->isPICStyleStubAny() &&
2836 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2837 (!Subtarget->getTargetTriple().isMacOSX() ||
2838 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2839 // PC-relative references to external symbols should go through $stub,
2840 // unless we're building with the leopard linker or later, which
2841 // automatically synthesizes these stubs.
2842 OpFlags = X86II::MO_DARWIN_STUB;
2843 } else if (Subtarget->isPICStyleRIPRel() &&
2844 isa<Function>(GV) &&
2845 cast<Function>(GV)->getAttributes().
2846 hasAttribute(AttributeSet::FunctionIndex,
2847 Attribute::NonLazyBind)) {
2848 // If the function is marked as non-lazy, generate an indirect call
2849 // which loads from the GOT directly. This avoids runtime overhead
2850 // at the cost of eager binding (and one extra byte of encoding).
2851 OpFlags = X86II::MO_GOTPCREL;
2852 WrapperKind = X86ISD::WrapperRIP;
2856 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2857 G->getOffset(), OpFlags);
2859 // Add a wrapper if needed.
2860 if (WrapperKind != ISD::DELETED_NODE)
2861 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
2862 // Add extra indirection if needed.
2864 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
2865 MachinePointerInfo::getGOT(),
2866 false, false, false, 0);
2868 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2869 unsigned char OpFlags = 0;
2871 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2872 // external symbols should go through the PLT.
2873 if (Subtarget->isTargetELF() &&
2874 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2875 OpFlags = X86II::MO_PLT;
2876 } else if (Subtarget->isPICStyleStubAny() &&
2877 (!Subtarget->getTargetTriple().isMacOSX() ||
2878 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2879 // PC-relative references to external symbols should go through $stub,
2880 // unless we're building with the leopard linker or later, which
2881 // automatically synthesizes these stubs.
2882 OpFlags = X86II::MO_DARWIN_STUB;
2885 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2889 // Returns a chain & a flag for retval copy to use.
2890 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2891 SmallVector<SDValue, 8> Ops;
2893 if (!IsSibcall && isTailCall) {
2894 Chain = DAG.getCALLSEQ_END(Chain,
2895 DAG.getIntPtrConstant(NumBytesToPop, true),
2896 DAG.getIntPtrConstant(0, true), InFlag, dl);
2897 InFlag = Chain.getValue(1);
2900 Ops.push_back(Chain);
2901 Ops.push_back(Callee);
2904 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2906 // Add argument registers to the end of the list so that they are known live
2908 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2909 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2910 RegsToPass[i].second.getValueType()));
2912 // Add a register mask operand representing the call-preserved registers.
2913 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2914 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
2915 assert(Mask && "Missing call preserved mask for calling convention");
2916 Ops.push_back(DAG.getRegisterMask(Mask));
2918 if (InFlag.getNode())
2919 Ops.push_back(InFlag);
2923 //// If this is the first return lowered for this function, add the regs
2924 //// to the liveout set for the function.
2925 // This isn't right, although it's probably harmless on x86; liveouts
2926 // should be computed from returns not tail calls. Consider a void
2927 // function making a tail call to a function returning int.
2928 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size());
2931 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2932 InFlag = Chain.getValue(1);
2934 // Create the CALLSEQ_END node.
2935 unsigned NumBytesForCalleeToPop;
2936 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2937 getTargetMachine().Options.GuaranteedTailCallOpt))
2938 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
2939 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2940 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2941 SR == StackStructReturn)
2942 // If this is a call to a struct-return function, the callee
2943 // pops the hidden struct pointer, so we have to push it back.
2944 // This is common for Darwin/X86, Linux & Mingw32 targets.
2945 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
2946 NumBytesForCalleeToPop = 4;
2948 NumBytesForCalleeToPop = 0; // Callee pops nothing.
2950 // Returns a flag for retval copy to use.
2952 Chain = DAG.getCALLSEQ_END(Chain,
2953 DAG.getIntPtrConstant(NumBytesToPop, true),
2954 DAG.getIntPtrConstant(NumBytesForCalleeToPop,
2957 InFlag = Chain.getValue(1);
2960 // Handle result values, copying them out of physregs into vregs that we
2962 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2963 Ins, dl, DAG, InVals);
2966 //===----------------------------------------------------------------------===//
2967 // Fast Calling Convention (tail call) implementation
2968 //===----------------------------------------------------------------------===//
2970 // Like std call, callee cleans arguments, convention except that ECX is
2971 // reserved for storing the tail called function address. Only 2 registers are
2972 // free for argument passing (inreg). Tail call optimization is performed
2974 // * tailcallopt is enabled
2975 // * caller/callee are fastcc
2976 // On X86_64 architecture with GOT-style position independent code only local
2977 // (within module) calls are supported at the moment.
2978 // To keep the stack aligned according to platform abi the function
2979 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2980 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2981 // If a tail called function callee has more arguments than the caller the
2982 // caller needs to make sure that there is room to move the RETADDR to. This is
2983 // achieved by reserving an area the size of the argument delta right after the
2984 // original REtADDR, but before the saved framepointer or the spilled registers
2985 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2997 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2998 /// for a 16 byte align requirement.
3000 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3001 SelectionDAG& DAG) const {
3002 MachineFunction &MF = DAG.getMachineFunction();
3003 const TargetMachine &TM = MF.getTarget();
3004 const X86RegisterInfo *RegInfo =
3005 static_cast<const X86RegisterInfo*>(TM.getRegisterInfo());
3006 const TargetFrameLowering &TFI = *TM.getFrameLowering();
3007 unsigned StackAlignment = TFI.getStackAlignment();
3008 uint64_t AlignMask = StackAlignment - 1;
3009 int64_t Offset = StackSize;
3010 unsigned SlotSize = RegInfo->getSlotSize();
3011 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3012 // Number smaller than 12 so just add the difference.
3013 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3015 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3016 Offset = ((~AlignMask) & Offset) + StackAlignment +
3017 (StackAlignment-SlotSize);
3022 /// MatchingStackOffset - Return true if the given stack call argument is
3023 /// already available in the same position (relatively) of the caller's
3024 /// incoming argument stack.
3026 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3027 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3028 const X86InstrInfo *TII) {
3029 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3031 if (Arg.getOpcode() == ISD::CopyFromReg) {
3032 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3033 if (!TargetRegisterInfo::isVirtualRegister(VR))
3035 MachineInstr *Def = MRI->getVRegDef(VR);
3038 if (!Flags.isByVal()) {
3039 if (!TII->isLoadFromStackSlot(Def, FI))
3042 unsigned Opcode = Def->getOpcode();
3043 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
3044 Def->getOperand(1).isFI()) {
3045 FI = Def->getOperand(1).getIndex();
3046 Bytes = Flags.getByValSize();
3050 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3051 if (Flags.isByVal())
3052 // ByVal argument is passed in as a pointer but it's now being
3053 // dereferenced. e.g.
3054 // define @foo(%struct.X* %A) {
3055 // tail call @bar(%struct.X* byval %A)
3058 SDValue Ptr = Ld->getBasePtr();
3059 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3062 FI = FINode->getIndex();
3063 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3064 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3065 FI = FINode->getIndex();
3066 Bytes = Flags.getByValSize();
3070 assert(FI != INT_MAX);
3071 if (!MFI->isFixedObjectIndex(FI))
3073 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3076 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3077 /// for tail call optimization. Targets which want to do tail call
3078 /// optimization should implement this function.
3080 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3081 CallingConv::ID CalleeCC,
3083 bool isCalleeStructRet,
3084 bool isCallerStructRet,
3086 const SmallVectorImpl<ISD::OutputArg> &Outs,
3087 const SmallVectorImpl<SDValue> &OutVals,
3088 const SmallVectorImpl<ISD::InputArg> &Ins,
3089 SelectionDAG &DAG) const {
3090 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3093 // If -tailcallopt is specified, make fastcc functions tail-callable.
3094 const MachineFunction &MF = DAG.getMachineFunction();
3095 const Function *CallerF = MF.getFunction();
3097 // If the function return type is x86_fp80 and the callee return type is not,
3098 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3099 // perform a tailcall optimization here.
3100 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3103 CallingConv::ID CallerCC = CallerF->getCallingConv();
3104 bool CCMatch = CallerCC == CalleeCC;
3105 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3106 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3108 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
3109 if (IsTailCallConvention(CalleeCC) && CCMatch)
3114 // Look for obvious safe cases to perform tail call optimization that do not
3115 // require ABI changes. This is what gcc calls sibcall.
3117 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3118 // emit a special epilogue.
3119 const X86RegisterInfo *RegInfo =
3120 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
3121 if (RegInfo->needsStackRealignment(MF))
3124 // Also avoid sibcall optimization if either caller or callee uses struct
3125 // return semantics.
3126 if (isCalleeStructRet || isCallerStructRet)
3129 // An stdcall/thiscall caller is expected to clean up its arguments; the
3130 // callee isn't going to do that.
3131 // FIXME: this is more restrictive than needed. We could produce a tailcall
3132 // when the stack adjustment matches. For example, with a thiscall that takes
3133 // only one argument.
3134 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3135 CallerCC == CallingConv::X86_ThisCall))
3138 // Do not sibcall optimize vararg calls unless all arguments are passed via
3140 if (isVarArg && !Outs.empty()) {
3142 // Optimizing for varargs on Win64 is unlikely to be safe without
3143 // additional testing.
3144 if (IsCalleeWin64 || IsCallerWin64)
3147 SmallVector<CCValAssign, 16> ArgLocs;
3148 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
3149 getTargetMachine(), ArgLocs, *DAG.getContext());
3151 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3152 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3153 if (!ArgLocs[i].isRegLoc())
3157 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3158 // stack. Therefore, if it's not used by the call it is not safe to optimize
3159 // this into a sibcall.
3160 bool Unused = false;
3161 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3168 SmallVector<CCValAssign, 16> RVLocs;
3169 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(),
3170 getTargetMachine(), RVLocs, *DAG.getContext());
3171 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3172 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3173 CCValAssign &VA = RVLocs[i];
3174 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
3179 // If the calling conventions do not match, then we'd better make sure the
3180 // results are returned in the same way as what the caller expects.
3182 SmallVector<CCValAssign, 16> RVLocs1;
3183 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
3184 getTargetMachine(), RVLocs1, *DAG.getContext());
3185 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3187 SmallVector<CCValAssign, 16> RVLocs2;
3188 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
3189 getTargetMachine(), RVLocs2, *DAG.getContext());
3190 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3192 if (RVLocs1.size() != RVLocs2.size())
3194 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3195 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3197 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3199 if (RVLocs1[i].isRegLoc()) {
3200 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3203 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3209 // If the callee takes no arguments then go on to check the results of the
3211 if (!Outs.empty()) {
3212 // Check if stack adjustment is needed. For now, do not do this if any
3213 // argument is passed on the stack.
3214 SmallVector<CCValAssign, 16> ArgLocs;
3215 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
3216 getTargetMachine(), ArgLocs, *DAG.getContext());
3218 // Allocate shadow area for Win64
3220 CCInfo.AllocateStack(32, 8);
3222 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3223 if (CCInfo.getNextStackOffset()) {
3224 MachineFunction &MF = DAG.getMachineFunction();
3225 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3228 // Check if the arguments are already laid out in the right way as
3229 // the caller's fixed stack objects.
3230 MachineFrameInfo *MFI = MF.getFrameInfo();
3231 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3232 const X86InstrInfo *TII =
3233 ((const X86TargetMachine&)getTargetMachine()).getInstrInfo();
3234 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3235 CCValAssign &VA = ArgLocs[i];
3236 SDValue Arg = OutVals[i];
3237 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3238 if (VA.getLocInfo() == CCValAssign::Indirect)
3240 if (!VA.isRegLoc()) {
3241 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3248 // If the tailcall address may be in a register, then make sure it's
3249 // possible to register allocate for it. In 32-bit, the call address can
3250 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3251 // callee-saved registers are restored. These happen to be the same
3252 // registers used to pass 'inreg' arguments so watch out for those.
3253 if (!Subtarget->is64Bit() &&
3254 ((!isa<GlobalAddressSDNode>(Callee) &&
3255 !isa<ExternalSymbolSDNode>(Callee)) ||
3256 getTargetMachine().getRelocationModel() == Reloc::PIC_)) {
3257 unsigned NumInRegs = 0;
3258 // In PIC we need an extra register to formulate the address computation
3260 unsigned MaxInRegs =
3261 (getTargetMachine().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3263 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3264 CCValAssign &VA = ArgLocs[i];
3267 unsigned Reg = VA.getLocReg();
3270 case X86::EAX: case X86::EDX: case X86::ECX:
3271 if (++NumInRegs == MaxInRegs)
3283 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3284 const TargetLibraryInfo *libInfo) const {
3285 return X86::createFastISel(funcInfo, libInfo);
3288 //===----------------------------------------------------------------------===//
3289 // Other Lowering Hooks
3290 //===----------------------------------------------------------------------===//
3292 static bool MayFoldLoad(SDValue Op) {
3293 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3296 static bool MayFoldIntoStore(SDValue Op) {
3297 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3300 static bool isTargetShuffle(unsigned Opcode) {
3302 default: return false;
3303 case X86ISD::PSHUFD:
3304 case X86ISD::PSHUFHW:
3305 case X86ISD::PSHUFLW:
3307 case X86ISD::PALIGNR:
3308 case X86ISD::MOVLHPS:
3309 case X86ISD::MOVLHPD:
3310 case X86ISD::MOVHLPS:
3311 case X86ISD::MOVLPS:
3312 case X86ISD::MOVLPD:
3313 case X86ISD::MOVSHDUP:
3314 case X86ISD::MOVSLDUP:
3315 case X86ISD::MOVDDUP:
3318 case X86ISD::UNPCKL:
3319 case X86ISD::UNPCKH:
3320 case X86ISD::VPERMILP:
3321 case X86ISD::VPERM2X128:
3322 case X86ISD::VPERMI:
3327 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3328 SDValue V1, SelectionDAG &DAG) {
3330 default: llvm_unreachable("Unknown x86 shuffle node");
3331 case X86ISD::MOVSHDUP:
3332 case X86ISD::MOVSLDUP:
3333 case X86ISD::MOVDDUP:
3334 return DAG.getNode(Opc, dl, VT, V1);
3338 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3339 SDValue V1, unsigned TargetMask,
3340 SelectionDAG &DAG) {
3342 default: llvm_unreachable("Unknown x86 shuffle node");
3343 case X86ISD::PSHUFD:
3344 case X86ISD::PSHUFHW:
3345 case X86ISD::PSHUFLW:
3346 case X86ISD::VPERMILP:
3347 case X86ISD::VPERMI:
3348 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3352 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3353 SDValue V1, SDValue V2, unsigned TargetMask,
3354 SelectionDAG &DAG) {
3356 default: llvm_unreachable("Unknown x86 shuffle node");
3357 case X86ISD::PALIGNR:
3359 case X86ISD::VPERM2X128:
3360 return DAG.getNode(Opc, dl, VT, V1, V2,
3361 DAG.getConstant(TargetMask, MVT::i8));
3365 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3366 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3368 default: llvm_unreachable("Unknown x86 shuffle node");
3369 case X86ISD::MOVLHPS:
3370 case X86ISD::MOVLHPD:
3371 case X86ISD::MOVHLPS:
3372 case X86ISD::MOVLPS:
3373 case X86ISD::MOVLPD:
3376 case X86ISD::UNPCKL:
3377 case X86ISD::UNPCKH:
3378 return DAG.getNode(Opc, dl, VT, V1, V2);
3382 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3383 MachineFunction &MF = DAG.getMachineFunction();
3384 const X86RegisterInfo *RegInfo =
3385 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
3386 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3387 int ReturnAddrIndex = FuncInfo->getRAIndex();
3389 if (ReturnAddrIndex == 0) {
3390 // Set up a frame object for the return address.
3391 unsigned SlotSize = RegInfo->getSlotSize();
3392 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3395 FuncInfo->setRAIndex(ReturnAddrIndex);
3398 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3401 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3402 bool hasSymbolicDisplacement) {
3403 // Offset should fit into 32 bit immediate field.
3404 if (!isInt<32>(Offset))
3407 // If we don't have a symbolic displacement - we don't have any extra
3409 if (!hasSymbolicDisplacement)
3412 // FIXME: Some tweaks might be needed for medium code model.
3413 if (M != CodeModel::Small && M != CodeModel::Kernel)
3416 // For small code model we assume that latest object is 16MB before end of 31
3417 // bits boundary. We may also accept pretty large negative constants knowing
3418 // that all objects are in the positive half of address space.
3419 if (M == CodeModel::Small && Offset < 16*1024*1024)
3422 // For kernel code model we know that all object resist in the negative half
3423 // of 32bits address space. We may not accept negative offsets, since they may
3424 // be just off and we may accept pretty large positive ones.
3425 if (M == CodeModel::Kernel && Offset > 0)
3431 /// isCalleePop - Determines whether the callee is required to pop its
3432 /// own arguments. Callee pop is necessary to support tail calls.
3433 bool X86::isCalleePop(CallingConv::ID CallingConv,
3434 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3438 switch (CallingConv) {
3441 case CallingConv::X86_StdCall:
3443 case CallingConv::X86_FastCall:
3445 case CallingConv::X86_ThisCall:
3447 case CallingConv::Fast:
3449 case CallingConv::GHC:
3451 case CallingConv::HiPE:
3456 /// \brief Return true if the condition is an unsigned comparison operation.
3457 static bool isX86CCUnsigned(unsigned X86CC) {
3459 default: llvm_unreachable("Invalid integer condition!");
3460 case X86::COND_E: return true;
3461 case X86::COND_G: return false;
3462 case X86::COND_GE: return false;
3463 case X86::COND_L: return false;
3464 case X86::COND_LE: return false;
3465 case X86::COND_NE: return true;
3466 case X86::COND_B: return true;
3467 case X86::COND_A: return true;
3468 case X86::COND_BE: return true;
3469 case X86::COND_AE: return true;
3471 llvm_unreachable("covered switch fell through?!");
3474 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3475 /// specific condition code, returning the condition code and the LHS/RHS of the
3476 /// comparison to make.
3477 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3478 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3480 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3481 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3482 // X > -1 -> X == 0, jump !sign.
3483 RHS = DAG.getConstant(0, RHS.getValueType());
3484 return X86::COND_NS;
3486 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3487 // X < 0 -> X == 0, jump on sign.
3490 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3492 RHS = DAG.getConstant(0, RHS.getValueType());
3493 return X86::COND_LE;
3497 switch (SetCCOpcode) {
3498 default: llvm_unreachable("Invalid integer condition!");
3499 case ISD::SETEQ: return X86::COND_E;
3500 case ISD::SETGT: return X86::COND_G;
3501 case ISD::SETGE: return X86::COND_GE;
3502 case ISD::SETLT: return X86::COND_L;
3503 case ISD::SETLE: return X86::COND_LE;
3504 case ISD::SETNE: return X86::COND_NE;
3505 case ISD::SETULT: return X86::COND_B;
3506 case ISD::SETUGT: return X86::COND_A;
3507 case ISD::SETULE: return X86::COND_BE;
3508 case ISD::SETUGE: return X86::COND_AE;
3512 // First determine if it is required or is profitable to flip the operands.
3514 // If LHS is a foldable load, but RHS is not, flip the condition.
3515 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3516 !ISD::isNON_EXTLoad(RHS.getNode())) {
3517 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3518 std::swap(LHS, RHS);
3521 switch (SetCCOpcode) {
3527 std::swap(LHS, RHS);
3531 // On a floating point condition, the flags are set as follows:
3533 // 0 | 0 | 0 | X > Y
3534 // 0 | 0 | 1 | X < Y
3535 // 1 | 0 | 0 | X == Y
3536 // 1 | 1 | 1 | unordered
3537 switch (SetCCOpcode) {
3538 default: llvm_unreachable("Condcode should be pre-legalized away");
3540 case ISD::SETEQ: return X86::COND_E;
3541 case ISD::SETOLT: // flipped
3543 case ISD::SETGT: return X86::COND_A;
3544 case ISD::SETOLE: // flipped
3546 case ISD::SETGE: return X86::COND_AE;
3547 case ISD::SETUGT: // flipped
3549 case ISD::SETLT: return X86::COND_B;
3550 case ISD::SETUGE: // flipped
3552 case ISD::SETLE: return X86::COND_BE;
3554 case ISD::SETNE: return X86::COND_NE;
3555 case ISD::SETUO: return X86::COND_P;
3556 case ISD::SETO: return X86::COND_NP;
3558 case ISD::SETUNE: return X86::COND_INVALID;
3562 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3563 /// code. Current x86 isa includes the following FP cmov instructions:
3564 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3565 static bool hasFPCMov(unsigned X86CC) {
3581 /// isFPImmLegal - Returns true if the target can instruction select the
3582 /// specified FP immediate natively. If false, the legalizer will
3583 /// materialize the FP immediate as a load from a constant pool.
3584 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3585 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3586 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3592 /// \brief Returns true if it is beneficial to convert a load of a constant
3593 /// to just the constant itself.
3594 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3596 assert(Ty->isIntegerTy());
3598 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3599 if (BitSize == 0 || BitSize > 64)
3604 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3605 /// the specified range (L, H].
3606 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3607 return (Val < 0) || (Val >= Low && Val < Hi);
3610 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3611 /// specified value.
3612 static bool isUndefOrEqual(int Val, int CmpVal) {
3613 return (Val < 0 || Val == CmpVal);
3616 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3617 /// from position Pos and ending in Pos+Size, falls within the specified
3618 /// sequential range (L, L+Pos]. or is undef.
3619 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3620 unsigned Pos, unsigned Size, int Low) {
3621 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3622 if (!isUndefOrEqual(Mask[i], Low))
3627 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3628 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3629 /// the second operand.
3630 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT) {
3631 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3632 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3633 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3634 return (Mask[0] < 2 && Mask[1] < 2);
3638 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3639 /// is suitable for input to PSHUFHW.
3640 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3641 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3644 // Lower quadword copied in order or undef.
3645 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3648 // Upper quadword shuffled.
3649 for (unsigned i = 4; i != 8; ++i)
3650 if (!isUndefOrInRange(Mask[i], 4, 8))
3653 if (VT == MVT::v16i16) {
3654 // Lower quadword copied in order or undef.
3655 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3658 // Upper quadword shuffled.
3659 for (unsigned i = 12; i != 16; ++i)
3660 if (!isUndefOrInRange(Mask[i], 12, 16))
3667 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3668 /// is suitable for input to PSHUFLW.
3669 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3670 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3673 // Upper quadword copied in order.
3674 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3677 // Lower quadword shuffled.
3678 for (unsigned i = 0; i != 4; ++i)
3679 if (!isUndefOrInRange(Mask[i], 0, 4))
3682 if (VT == MVT::v16i16) {
3683 // Upper quadword copied in order.
3684 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3687 // Lower quadword shuffled.
3688 for (unsigned i = 8; i != 12; ++i)
3689 if (!isUndefOrInRange(Mask[i], 8, 12))
3696 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
3697 /// is suitable for input to PALIGNR.
3698 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
3699 const X86Subtarget *Subtarget) {
3700 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
3701 (VT.is256BitVector() && !Subtarget->hasInt256()))
3704 unsigned NumElts = VT.getVectorNumElements();
3705 unsigned NumLanes = VT.is512BitVector() ? 1: VT.getSizeInBits()/128;
3706 unsigned NumLaneElts = NumElts/NumLanes;
3708 // Do not handle 64-bit element shuffles with palignr.
3709 if (NumLaneElts == 2)
3712 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3714 for (i = 0; i != NumLaneElts; ++i) {
3719 // Lane is all undef, go to next lane
3720 if (i == NumLaneElts)
3723 int Start = Mask[i+l];
3725 // Make sure its in this lane in one of the sources
3726 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3727 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3730 // If not lane 0, then we must match lane 0
3731 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3734 // Correct second source to be contiguous with first source
3735 if (Start >= (int)NumElts)
3736 Start -= NumElts - NumLaneElts;
3738 // Make sure we're shifting in the right direction.
3739 if (Start <= (int)(i+l))
3744 // Check the rest of the elements to see if they are consecutive.
3745 for (++i; i != NumLaneElts; ++i) {
3746 int Idx = Mask[i+l];
3748 // Make sure its in this lane
3749 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3750 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3753 // If not lane 0, then we must match lane 0
3754 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3757 if (Idx >= (int)NumElts)
3758 Idx -= NumElts - NumLaneElts;
3760 if (!isUndefOrEqual(Idx, Start+i))
3769 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3770 /// the two vector operands have swapped position.
3771 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
3772 unsigned NumElems) {
3773 for (unsigned i = 0; i != NumElems; ++i) {
3777 else if (idx < (int)NumElems)
3778 Mask[i] = idx + NumElems;
3780 Mask[i] = idx - NumElems;
3784 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
3785 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
3786 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
3787 /// reverse of what x86 shuffles want.
3788 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
3790 unsigned NumElems = VT.getVectorNumElements();
3791 unsigned NumLanes = VT.getSizeInBits()/128;
3792 unsigned NumLaneElems = NumElems/NumLanes;
3794 if (NumLaneElems != 2 && NumLaneElems != 4)
3797 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3798 bool symetricMaskRequired =
3799 (VT.getSizeInBits() >= 256) && (EltSize == 32);
3801 // VSHUFPSY divides the resulting vector into 4 chunks.
3802 // The sources are also splitted into 4 chunks, and each destination
3803 // chunk must come from a different source chunk.
3805 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
3806 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
3808 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
3809 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
3811 // VSHUFPDY divides the resulting vector into 4 chunks.
3812 // The sources are also splitted into 4 chunks, and each destination
3813 // chunk must come from a different source chunk.
3815 // SRC1 => X3 X2 X1 X0
3816 // SRC2 => Y3 Y2 Y1 Y0
3818 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
3820 SmallVector<int, 4> MaskVal(NumLaneElems, -1);
3821 unsigned HalfLaneElems = NumLaneElems/2;
3822 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
3823 for (unsigned i = 0; i != NumLaneElems; ++i) {
3824 int Idx = Mask[i+l];
3825 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
3826 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
3828 // For VSHUFPSY, the mask of the second half must be the same as the
3829 // first but with the appropriate offsets. This works in the same way as
3830 // VPERMILPS works with masks.
3831 if (!symetricMaskRequired || Idx < 0)
3833 if (MaskVal[i] < 0) {
3834 MaskVal[i] = Idx - l;
3837 if ((signed)(Idx - l) != MaskVal[i])
3845 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3846 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3847 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
3848 if (!VT.is128BitVector())
3851 unsigned NumElems = VT.getVectorNumElements();
3856 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3857 return isUndefOrEqual(Mask[0], 6) &&
3858 isUndefOrEqual(Mask[1], 7) &&
3859 isUndefOrEqual(Mask[2], 2) &&
3860 isUndefOrEqual(Mask[3], 3);
3863 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3864 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3866 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
3867 if (!VT.is128BitVector())
3870 unsigned NumElems = VT.getVectorNumElements();
3875 return isUndefOrEqual(Mask[0], 2) &&
3876 isUndefOrEqual(Mask[1], 3) &&
3877 isUndefOrEqual(Mask[2], 2) &&
3878 isUndefOrEqual(Mask[3], 3);
3881 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3882 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3883 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
3884 if (!VT.is128BitVector())
3887 unsigned NumElems = VT.getVectorNumElements();
3889 if (NumElems != 2 && NumElems != 4)
3892 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3893 if (!isUndefOrEqual(Mask[i], i + NumElems))
3896 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
3897 if (!isUndefOrEqual(Mask[i], i))
3903 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3904 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3905 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
3906 if (!VT.is128BitVector())
3909 unsigned NumElems = VT.getVectorNumElements();
3911 if (NumElems != 2 && NumElems != 4)
3914 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3915 if (!isUndefOrEqual(Mask[i], i))
3918 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3919 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
3926 // Some special combinations that can be optimized.
3929 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
3930 SelectionDAG &DAG) {
3931 MVT VT = SVOp->getSimpleValueType(0);
3934 if (VT != MVT::v8i32 && VT != MVT::v8f32)
3937 ArrayRef<int> Mask = SVOp->getMask();
3939 // These are the special masks that may be optimized.
3940 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
3941 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
3942 bool MatchEvenMask = true;
3943 bool MatchOddMask = true;
3944 for (int i=0; i<8; ++i) {
3945 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
3946 MatchEvenMask = false;
3947 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
3948 MatchOddMask = false;
3951 if (!MatchEvenMask && !MatchOddMask)
3954 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
3956 SDValue Op0 = SVOp->getOperand(0);
3957 SDValue Op1 = SVOp->getOperand(1);
3959 if (MatchEvenMask) {
3960 // Shift the second operand right to 32 bits.
3961 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
3962 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
3964 // Shift the first operand left to 32 bits.
3965 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
3966 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
3968 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
3969 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
3972 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
3973 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
3974 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
3975 bool HasInt256, bool V2IsSplat = false) {
3977 assert(VT.getSizeInBits() >= 128 &&
3978 "Unsupported vector type for unpckl");
3980 // AVX defines UNPCK* to operate independently on 128-bit lanes.
3982 unsigned NumOf256BitLanes;
3983 unsigned NumElts = VT.getVectorNumElements();
3984 if (VT.is256BitVector()) {
3985 if (NumElts != 4 && NumElts != 8 &&
3986 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
3989 NumOf256BitLanes = 1;
3990 } else if (VT.is512BitVector()) {
3991 assert(VT.getScalarType().getSizeInBits() >= 32 &&
3992 "Unsupported vector type for unpckh");
3994 NumOf256BitLanes = 2;
3997 NumOf256BitLanes = 1;
4000 unsigned NumEltsInStride = NumElts/NumOf256BitLanes;
4001 unsigned NumLaneElts = NumEltsInStride/NumLanes;
4003 for (unsigned l256 = 0; l256 < NumOf256BitLanes; l256 += 1) {
4004 for (unsigned l = 0; l != NumEltsInStride; l += NumLaneElts) {
4005 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4006 int BitI = Mask[l256*NumEltsInStride+l+i];
4007 int BitI1 = Mask[l256*NumEltsInStride+l+i+1];
4008 if (!isUndefOrEqual(BitI, j+l256*NumElts))
4010 if (V2IsSplat && !isUndefOrEqual(BitI1, NumElts))
4012 if (!isUndefOrEqual(BitI1, j+l256*NumElts+NumEltsInStride))
4020 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
4021 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
4022 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
4023 bool HasInt256, bool V2IsSplat = false) {
4024 assert(VT.getSizeInBits() >= 128 &&
4025 "Unsupported vector type for unpckh");
4027 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4029 unsigned NumOf256BitLanes;
4030 unsigned NumElts = VT.getVectorNumElements();
4031 if (VT.is256BitVector()) {
4032 if (NumElts != 4 && NumElts != 8 &&
4033 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4036 NumOf256BitLanes = 1;
4037 } else if (VT.is512BitVector()) {
4038 assert(VT.getScalarType().getSizeInBits() >= 32 &&
4039 "Unsupported vector type for unpckh");
4041 NumOf256BitLanes = 2;
4044 NumOf256BitLanes = 1;
4047 unsigned NumEltsInStride = NumElts/NumOf256BitLanes;
4048 unsigned NumLaneElts = NumEltsInStride/NumLanes;
4050 for (unsigned l256 = 0; l256 < NumOf256BitLanes; l256 += 1) {
4051 for (unsigned l = 0; l != NumEltsInStride; l += NumLaneElts) {
4052 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4053 int BitI = Mask[l256*NumEltsInStride+l+i];
4054 int BitI1 = Mask[l256*NumEltsInStride+l+i+1];
4055 if (!isUndefOrEqual(BitI, j+l256*NumElts))
4057 if (V2IsSplat && !isUndefOrEqual(BitI1, NumElts))
4059 if (!isUndefOrEqual(BitI1, j+l256*NumElts+NumEltsInStride))
4067 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
4068 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
4070 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4071 unsigned NumElts = VT.getVectorNumElements();
4072 bool Is256BitVec = VT.is256BitVector();
4074 if (VT.is512BitVector())
4076 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4077 "Unsupported vector type for unpckh");
4079 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
4080 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4083 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
4084 // FIXME: Need a better way to get rid of this, there's no latency difference
4085 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
4086 // the former later. We should also remove the "_undef" special mask.
4087 if (NumElts == 4 && Is256BitVec)
4090 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4091 // independently on 128-bit lanes.
4092 unsigned NumLanes = VT.getSizeInBits()/128;
4093 unsigned NumLaneElts = NumElts/NumLanes;
4095 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4096 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4097 int BitI = Mask[l+i];
4098 int BitI1 = Mask[l+i+1];
4100 if (!isUndefOrEqual(BitI, j))
4102 if (!isUndefOrEqual(BitI1, j))
4110 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
4111 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
4113 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4114 unsigned NumElts = VT.getVectorNumElements();
4116 if (VT.is512BitVector())
4119 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4120 "Unsupported vector type for unpckh");
4122 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4123 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4126 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4127 // independently on 128-bit lanes.
4128 unsigned NumLanes = VT.getSizeInBits()/128;
4129 unsigned NumLaneElts = NumElts/NumLanes;
4131 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4132 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4133 int BitI = Mask[l+i];
4134 int BitI1 = Mask[l+i+1];
4135 if (!isUndefOrEqual(BitI, j))
4137 if (!isUndefOrEqual(BitI1, j))
4144 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4145 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4146 /// MOVSD, and MOVD, i.e. setting the lowest element.
4147 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4148 if (VT.getVectorElementType().getSizeInBits() < 32)
4150 if (!VT.is128BitVector())
4153 unsigned NumElts = VT.getVectorNumElements();
4155 if (!isUndefOrEqual(Mask[0], NumElts))
4158 for (unsigned i = 1; i != NumElts; ++i)
4159 if (!isUndefOrEqual(Mask[i], i))
4165 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4166 /// as permutations between 128-bit chunks or halves. As an example: this
4168 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4169 /// The first half comes from the second half of V1 and the second half from the
4170 /// the second half of V2.
4171 static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4172 if (!HasFp256 || !VT.is256BitVector())
4175 // The shuffle result is divided into half A and half B. In total the two
4176 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4177 // B must come from C, D, E or F.
4178 unsigned HalfSize = VT.getVectorNumElements()/2;
4179 bool MatchA = false, MatchB = false;
4181 // Check if A comes from one of C, D, E, F.
4182 for (unsigned Half = 0; Half != 4; ++Half) {
4183 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4189 // Check if B comes from one of C, D, E, F.
4190 for (unsigned Half = 0; Half != 4; ++Half) {
4191 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4197 return MatchA && MatchB;
4200 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4201 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4202 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4203 MVT VT = SVOp->getSimpleValueType(0);
4205 unsigned HalfSize = VT.getVectorNumElements()/2;
4207 unsigned FstHalf = 0, SndHalf = 0;
4208 for (unsigned i = 0; i < HalfSize; ++i) {
4209 if (SVOp->getMaskElt(i) > 0) {
4210 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4214 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4215 if (SVOp->getMaskElt(i) > 0) {
4216 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4221 return (FstHalf | (SndHalf << 4));
4224 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4225 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
4226 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4230 unsigned NumElts = VT.getVectorNumElements();
4232 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4233 for (unsigned i = 0; i != NumElts; ++i) {
4236 Imm8 |= Mask[i] << (i*2);
4241 unsigned LaneSize = 4;
4242 SmallVector<int, 4> MaskVal(LaneSize, -1);
4244 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4245 for (unsigned i = 0; i != LaneSize; ++i) {
4246 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4250 if (MaskVal[i] < 0) {
4251 MaskVal[i] = Mask[i+l] - l;
4252 Imm8 |= MaskVal[i] << (i*2);
4255 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4262 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4263 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4264 /// Note that VPERMIL mask matching is different depending whether theunderlying
4265 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4266 /// to the same elements of the low, but to the higher half of the source.
4267 /// In VPERMILPD the two lanes could be shuffled independently of each other
4268 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4269 static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
4270 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4271 if (VT.getSizeInBits() < 256 || EltSize < 32)
4273 bool symetricMaskRequired = (EltSize == 32);
4274 unsigned NumElts = VT.getVectorNumElements();
4276 unsigned NumLanes = VT.getSizeInBits()/128;
4277 unsigned LaneSize = NumElts/NumLanes;
4278 // 2 or 4 elements in one lane
4280 SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
4281 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4282 for (unsigned i = 0; i != LaneSize; ++i) {
4283 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4285 if (symetricMaskRequired) {
4286 if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) {
4287 ExpectedMaskVal[i] = Mask[i+l] - l;
4290 if (!isUndefOrEqual(Mask[i+l], ExpectedMaskVal[i]+l))
4298 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4299 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4300 /// element of vector 2 and the other elements to come from vector 1 in order.
4301 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4302 bool V2IsSplat = false, bool V2IsUndef = false) {
4303 if (!VT.is128BitVector())
4306 unsigned NumOps = VT.getVectorNumElements();
4307 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4310 if (!isUndefOrEqual(Mask[0], 0))
4313 for (unsigned i = 1; i != NumOps; ++i)
4314 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4315 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4316 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4322 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4323 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4324 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4325 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4326 const X86Subtarget *Subtarget) {
4327 if (!Subtarget->hasSSE3())
4330 unsigned NumElems = VT.getVectorNumElements();
4332 if ((VT.is128BitVector() && NumElems != 4) ||
4333 (VT.is256BitVector() && NumElems != 8) ||
4334 (VT.is512BitVector() && NumElems != 16))
4337 // "i+1" is the value the indexed mask element must have
4338 for (unsigned i = 0; i != NumElems; i += 2)
4339 if (!isUndefOrEqual(Mask[i], i+1) ||
4340 !isUndefOrEqual(Mask[i+1], i+1))
4346 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4347 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4348 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4349 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4350 const X86Subtarget *Subtarget) {
4351 if (!Subtarget->hasSSE3())
4354 unsigned NumElems = VT.getVectorNumElements();
4356 if ((VT.is128BitVector() && NumElems != 4) ||
4357 (VT.is256BitVector() && NumElems != 8) ||
4358 (VT.is512BitVector() && NumElems != 16))
4361 // "i" is the value the indexed mask element must have
4362 for (unsigned i = 0; i != NumElems; i += 2)
4363 if (!isUndefOrEqual(Mask[i], i) ||
4364 !isUndefOrEqual(Mask[i+1], i))
4370 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4371 /// specifies a shuffle of elements that is suitable for input to 256-bit
4372 /// version of MOVDDUP.
4373 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4374 if (!HasFp256 || !VT.is256BitVector())
4377 unsigned NumElts = VT.getVectorNumElements();
4381 for (unsigned i = 0; i != NumElts/2; ++i)
4382 if (!isUndefOrEqual(Mask[i], 0))
4384 for (unsigned i = NumElts/2; i != NumElts; ++i)
4385 if (!isUndefOrEqual(Mask[i], NumElts/2))
4390 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4391 /// specifies a shuffle of elements that is suitable for input to 128-bit
4392 /// version of MOVDDUP.
4393 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4394 if (!VT.is128BitVector())
4397 unsigned e = VT.getVectorNumElements() / 2;
4398 for (unsigned i = 0; i != e; ++i)
4399 if (!isUndefOrEqual(Mask[i], i))
4401 for (unsigned i = 0; i != e; ++i)
4402 if (!isUndefOrEqual(Mask[e+i], i))
4407 /// isVEXTRACTIndex - Return true if the specified
4408 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4409 /// suitable for instruction that extract 128 or 256 bit vectors
4410 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4411 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4412 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4415 // The index should be aligned on a vecWidth-bit boundary.
4417 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4419 MVT VT = N->getSimpleValueType(0);
4420 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4421 bool Result = (Index * ElSize) % vecWidth == 0;
4426 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4427 /// operand specifies a subvector insert that is suitable for input to
4428 /// insertion of 128 or 256-bit subvectors
4429 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4430 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4431 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4433 // The index should be aligned on a vecWidth-bit boundary.
4435 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4437 MVT VT = N->getSimpleValueType(0);
4438 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4439 bool Result = (Index * ElSize) % vecWidth == 0;
4444 bool X86::isVINSERT128Index(SDNode *N) {
4445 return isVINSERTIndex(N, 128);
4448 bool X86::isVINSERT256Index(SDNode *N) {
4449 return isVINSERTIndex(N, 256);
4452 bool X86::isVEXTRACT128Index(SDNode *N) {
4453 return isVEXTRACTIndex(N, 128);
4456 bool X86::isVEXTRACT256Index(SDNode *N) {
4457 return isVEXTRACTIndex(N, 256);
4460 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4461 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4462 /// Handles 128-bit and 256-bit.
4463 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4464 MVT VT = N->getSimpleValueType(0);
4466 assert((VT.getSizeInBits() >= 128) &&
4467 "Unsupported vector type for PSHUF/SHUFP");
4469 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4470 // independently on 128-bit lanes.
4471 unsigned NumElts = VT.getVectorNumElements();
4472 unsigned NumLanes = VT.getSizeInBits()/128;
4473 unsigned NumLaneElts = NumElts/NumLanes;
4475 assert((NumLaneElts == 2 || NumLaneElts == 4 || NumLaneElts == 8) &&
4476 "Only supports 2, 4 or 8 elements per lane");
4478 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0;
4480 for (unsigned i = 0; i != NumElts; ++i) {
4481 int Elt = N->getMaskElt(i);
4482 if (Elt < 0) continue;
4483 Elt &= NumLaneElts - 1;
4484 unsigned ShAmt = (i << Shift) % 8;
4485 Mask |= Elt << ShAmt;
4491 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4492 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4493 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4494 MVT VT = N->getSimpleValueType(0);
4496 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4497 "Unsupported vector type for PSHUFHW");
4499 unsigned NumElts = VT.getVectorNumElements();
4502 for (unsigned l = 0; l != NumElts; l += 8) {
4503 // 8 nodes per lane, but we only care about the last 4.
4504 for (unsigned i = 0; i < 4; ++i) {
4505 int Elt = N->getMaskElt(l+i+4);
4506 if (Elt < 0) continue;
4507 Elt &= 0x3; // only 2-bits.
4508 Mask |= Elt << (i * 2);
4515 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4516 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4517 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4518 MVT VT = N->getSimpleValueType(0);
4520 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4521 "Unsupported vector type for PSHUFHW");
4523 unsigned NumElts = VT.getVectorNumElements();
4526 for (unsigned l = 0; l != NumElts; l += 8) {
4527 // 8 nodes per lane, but we only care about the first 4.
4528 for (unsigned i = 0; i < 4; ++i) {
4529 int Elt = N->getMaskElt(l+i);
4530 if (Elt < 0) continue;
4531 Elt &= 0x3; // only 2-bits
4532 Mask |= Elt << (i * 2);
4539 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
4540 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
4541 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4542 MVT VT = SVOp->getSimpleValueType(0);
4543 unsigned EltSize = VT.is512BitVector() ? 1 :
4544 VT.getVectorElementType().getSizeInBits() >> 3;
4546 unsigned NumElts = VT.getVectorNumElements();
4547 unsigned NumLanes = VT.is512BitVector() ? 1 : VT.getSizeInBits()/128;
4548 unsigned NumLaneElts = NumElts/NumLanes;
4552 for (i = 0; i != NumElts; ++i) {
4553 Val = SVOp->getMaskElt(i);
4557 if (Val >= (int)NumElts)
4558 Val -= NumElts - NumLaneElts;
4560 assert(Val - i > 0 && "PALIGNR imm should be positive");
4561 return (Val - i) * EltSize;
4564 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4565 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4566 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4567 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4570 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4572 MVT VecVT = N->getOperand(0).getSimpleValueType();
4573 MVT ElVT = VecVT.getVectorElementType();
4575 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4576 return Index / NumElemsPerChunk;
4579 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4580 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4581 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4582 llvm_unreachable("Illegal insert subvector for VINSERT");
4585 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4587 MVT VecVT = N->getSimpleValueType(0);
4588 MVT ElVT = VecVT.getVectorElementType();
4590 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4591 return Index / NumElemsPerChunk;
4594 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4595 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4596 /// and VINSERTI128 instructions.
4597 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4598 return getExtractVEXTRACTImmediate(N, 128);
4601 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4602 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4603 /// and VINSERTI64x4 instructions.
4604 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4605 return getExtractVEXTRACTImmediate(N, 256);
4608 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4609 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4610 /// and VINSERTI128 instructions.
4611 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4612 return getInsertVINSERTImmediate(N, 128);
4615 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4616 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4617 /// and VINSERTI64x4 instructions.
4618 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4619 return getInsertVINSERTImmediate(N, 256);
4622 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4624 bool X86::isZeroNode(SDValue Elt) {
4625 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Elt))
4626 return CN->isNullValue();
4627 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4628 return CFP->getValueAPF().isPosZero();
4632 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
4633 /// their permute mask.
4634 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
4635 SelectionDAG &DAG) {
4636 MVT VT = SVOp->getSimpleValueType(0);
4637 unsigned NumElems = VT.getVectorNumElements();
4638 SmallVector<int, 8> MaskVec;
4640 for (unsigned i = 0; i != NumElems; ++i) {
4641 int Idx = SVOp->getMaskElt(i);
4643 if (Idx < (int)NumElems)
4648 MaskVec.push_back(Idx);
4650 return DAG.getVectorShuffle(VT, SDLoc(SVOp), SVOp->getOperand(1),
4651 SVOp->getOperand(0), &MaskVec[0]);
4654 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4655 /// match movhlps. The lower half elements should come from upper half of
4656 /// V1 (and in order), and the upper half elements should come from the upper
4657 /// half of V2 (and in order).
4658 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
4659 if (!VT.is128BitVector())
4661 if (VT.getVectorNumElements() != 4)
4663 for (unsigned i = 0, e = 2; i != e; ++i)
4664 if (!isUndefOrEqual(Mask[i], i+2))
4666 for (unsigned i = 2; i != 4; ++i)
4667 if (!isUndefOrEqual(Mask[i], i+4))
4672 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4673 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4675 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
4676 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4678 N = N->getOperand(0).getNode();
4679 if (!ISD::isNON_EXTLoad(N))
4682 *LD = cast<LoadSDNode>(N);
4686 // Test whether the given value is a vector value which will be legalized
4688 static bool WillBeConstantPoolLoad(SDNode *N) {
4689 if (N->getOpcode() != ISD::BUILD_VECTOR)
4692 // Check for any non-constant elements.
4693 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4694 switch (N->getOperand(i).getNode()->getOpcode()) {
4696 case ISD::ConstantFP:
4703 // Vectors of all-zeros and all-ones are materialized with special
4704 // instructions rather than being loaded.
4705 return !ISD::isBuildVectorAllZeros(N) &&
4706 !ISD::isBuildVectorAllOnes(N);
4709 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4710 /// match movlp{s|d}. The lower half elements should come from lower half of
4711 /// V1 (and in order), and the upper half elements should come from the upper
4712 /// half of V2 (and in order). And since V1 will become the source of the
4713 /// MOVLP, it must be either a vector load or a scalar load to vector.
4714 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
4715 ArrayRef<int> Mask, MVT VT) {
4716 if (!VT.is128BitVector())
4719 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
4721 // Is V2 is a vector load, don't do this transformation. We will try to use
4722 // load folding shufps op.
4723 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
4726 unsigned NumElems = VT.getVectorNumElements();
4728 if (NumElems != 2 && NumElems != 4)
4730 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4731 if (!isUndefOrEqual(Mask[i], i))
4733 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4734 if (!isUndefOrEqual(Mask[i], i+NumElems))
4739 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
4741 static bool isSplatVector(SDNode *N) {
4742 if (N->getOpcode() != ISD::BUILD_VECTOR)
4745 SDValue SplatValue = N->getOperand(0);
4746 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
4747 if (N->getOperand(i) != SplatValue)
4752 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
4753 /// to an zero vector.
4754 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
4755 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
4756 SDValue V1 = N->getOperand(0);
4757 SDValue V2 = N->getOperand(1);
4758 unsigned NumElems = N->getValueType(0).getVectorNumElements();
4759 for (unsigned i = 0; i != NumElems; ++i) {
4760 int Idx = N->getMaskElt(i);
4761 if (Idx >= (int)NumElems) {
4762 unsigned Opc = V2.getOpcode();
4763 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4765 if (Opc != ISD::BUILD_VECTOR ||
4766 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
4768 } else if (Idx >= 0) {
4769 unsigned Opc = V1.getOpcode();
4770 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
4772 if (Opc != ISD::BUILD_VECTOR ||
4773 !X86::isZeroNode(V1.getOperand(Idx)))
4780 /// getZeroVector - Returns a vector of specified type with all zero elements.
4782 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4783 SelectionDAG &DAG, SDLoc dl) {
4784 assert(VT.isVector() && "Expected a vector type");
4786 // Always build SSE zero vectors as <4 x i32> bitcasted
4787 // to their dest type. This ensures they get CSE'd.
4789 if (VT.is128BitVector()) { // SSE
4790 if (Subtarget->hasSSE2()) { // SSE2
4791 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4792 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4794 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4795 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4797 } else if (VT.is256BitVector()) { // AVX
4798 if (Subtarget->hasInt256()) { // AVX2
4799 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4800 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4801 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops,
4802 array_lengthof(Ops));
4804 // 256-bit logic and arithmetic instructions in AVX are all
4805 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4806 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4807 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4808 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops,
4809 array_lengthof(Ops));
4811 } else if (VT.is512BitVector()) { // AVX-512
4812 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4813 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4814 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4815 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops, 16);
4816 } else if (VT.getScalarType() == MVT::i1) {
4817 assert(VT.getVectorNumElements() <= 16 && "Unexpected vector type");
4818 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
4819 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4820 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4821 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
4822 Ops, VT.getVectorNumElements());
4824 llvm_unreachable("Unexpected vector type");
4826 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4829 /// getOnesVector - Returns a vector of specified type with all bits set.
4830 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4831 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4832 /// Then bitcast to their original type, ensuring they get CSE'd.
4833 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
4835 assert(VT.isVector() && "Expected a vector type");
4837 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
4839 if (VT.is256BitVector()) {
4840 if (HasInt256) { // AVX2
4841 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4842 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops,
4843 array_lengthof(Ops));
4845 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4846 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4848 } else if (VT.is128BitVector()) {
4849 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4851 llvm_unreachable("Unexpected vector type");
4853 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4856 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
4857 /// that point to V2 points to its first element.
4858 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
4859 for (unsigned i = 0; i != NumElems; ++i) {
4860 if (Mask[i] > (int)NumElems) {
4866 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4867 /// operation of specified width.
4868 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
4870 unsigned NumElems = VT.getVectorNumElements();
4871 SmallVector<int, 8> Mask;
4872 Mask.push_back(NumElems);
4873 for (unsigned i = 1; i != NumElems; ++i)
4875 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4878 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4879 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4881 unsigned NumElems = VT.getVectorNumElements();
4882 SmallVector<int, 8> Mask;
4883 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4885 Mask.push_back(i + NumElems);
4887 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4890 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4891 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4893 unsigned NumElems = VT.getVectorNumElements();
4894 SmallVector<int, 8> Mask;
4895 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4896 Mask.push_back(i + Half);
4897 Mask.push_back(i + NumElems + Half);
4899 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4902 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
4903 // a generic shuffle instruction because the target has no such instructions.
4904 // Generate shuffles which repeat i16 and i8 several times until they can be
4905 // represented by v4f32 and then be manipulated by target suported shuffles.
4906 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
4907 MVT VT = V.getSimpleValueType();
4908 int NumElems = VT.getVectorNumElements();
4911 while (NumElems > 4) {
4912 if (EltNo < NumElems/2) {
4913 V = getUnpackl(DAG, dl, VT, V, V);
4915 V = getUnpackh(DAG, dl, VT, V, V);
4916 EltNo -= NumElems/2;
4923 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
4924 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
4925 MVT VT = V.getSimpleValueType();
4928 if (VT.is128BitVector()) {
4929 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
4930 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
4931 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
4933 } else if (VT.is256BitVector()) {
4934 // To use VPERMILPS to splat scalars, the second half of indicies must
4935 // refer to the higher part, which is a duplication of the lower one,
4936 // because VPERMILPS can only handle in-lane permutations.
4937 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
4938 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
4940 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
4941 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
4944 llvm_unreachable("Vector size not supported");
4946 return DAG.getNode(ISD::BITCAST, dl, VT, V);
4949 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
4950 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
4951 MVT SrcVT = SV->getSimpleValueType(0);
4952 SDValue V1 = SV->getOperand(0);
4955 int EltNo = SV->getSplatIndex();
4956 int NumElems = SrcVT.getVectorNumElements();
4957 bool Is256BitVec = SrcVT.is256BitVector();
4959 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
4960 "Unknown how to promote splat for type");
4962 // Extract the 128-bit part containing the splat element and update
4963 // the splat element index when it refers to the higher register.
4965 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
4966 if (EltNo >= NumElems/2)
4967 EltNo -= NumElems/2;
4970 // All i16 and i8 vector types can't be used directly by a generic shuffle
4971 // instruction because the target has no such instruction. Generate shuffles
4972 // which repeat i16 and i8 several times until they fit in i32, and then can
4973 // be manipulated by target suported shuffles.
4974 MVT EltVT = SrcVT.getVectorElementType();
4975 if (EltVT == MVT::i8 || EltVT == MVT::i16)
4976 V1 = PromoteSplati8i16(V1, DAG, EltNo);
4978 // Recreate the 256-bit vector and place the same 128-bit vector
4979 // into the low and high part. This is necessary because we want
4980 // to use VPERM* to shuffle the vectors
4982 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
4985 return getLegalSplat(DAG, V1, EltNo);
4988 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4989 /// vector of zero or undef vector. This produces a shuffle where the low
4990 /// element of V2 is swizzled into the zero/undef vector, landing at element
4991 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4992 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4994 const X86Subtarget *Subtarget,
4995 SelectionDAG &DAG) {
4996 MVT VT = V2.getSimpleValueType();
4998 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
4999 unsigned NumElems = VT.getVectorNumElements();
5000 SmallVector<int, 16> MaskVec;
5001 for (unsigned i = 0; i != NumElems; ++i)
5002 // If this is the insertion idx, put the low elt of V2 here.
5003 MaskVec.push_back(i == Idx ? NumElems : i);
5004 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
5007 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
5008 /// target specific opcode. Returns true if the Mask could be calculated.
5009 /// Sets IsUnary to true if only uses one source.
5010 static bool getTargetShuffleMask(SDNode *N, MVT VT,
5011 SmallVectorImpl<int> &Mask, bool &IsUnary) {
5012 unsigned NumElems = VT.getVectorNumElements();
5016 switch(N->getOpcode()) {
5018 ImmN = N->getOperand(N->getNumOperands()-1);
5019 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5021 case X86ISD::UNPCKH:
5022 DecodeUNPCKHMask(VT, Mask);
5024 case X86ISD::UNPCKL:
5025 DecodeUNPCKLMask(VT, Mask);
5027 case X86ISD::MOVHLPS:
5028 DecodeMOVHLPSMask(NumElems, Mask);
5030 case X86ISD::MOVLHPS:
5031 DecodeMOVLHPSMask(NumElems, Mask);
5033 case X86ISD::PALIGNR:
5034 ImmN = N->getOperand(N->getNumOperands()-1);
5035 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5037 case X86ISD::PSHUFD:
5038 case X86ISD::VPERMILP:
5039 ImmN = N->getOperand(N->getNumOperands()-1);
5040 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5043 case X86ISD::PSHUFHW:
5044 ImmN = N->getOperand(N->getNumOperands()-1);
5045 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5048 case X86ISD::PSHUFLW:
5049 ImmN = N->getOperand(N->getNumOperands()-1);
5050 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5053 case X86ISD::VPERMI:
5054 ImmN = N->getOperand(N->getNumOperands()-1);
5055 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5059 case X86ISD::MOVSD: {
5060 // The index 0 always comes from the first element of the second source,
5061 // this is why MOVSS and MOVSD are used in the first place. The other
5062 // elements come from the other positions of the first source vector
5063 Mask.push_back(NumElems);
5064 for (unsigned i = 1; i != NumElems; ++i) {
5069 case X86ISD::VPERM2X128:
5070 ImmN = N->getOperand(N->getNumOperands()-1);
5071 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5072 if (Mask.empty()) return false;
5074 case X86ISD::MOVDDUP:
5075 case X86ISD::MOVLHPD:
5076 case X86ISD::MOVLPD:
5077 case X86ISD::MOVLPS:
5078 case X86ISD::MOVSHDUP:
5079 case X86ISD::MOVSLDUP:
5080 // Not yet implemented
5082 default: llvm_unreachable("unknown target shuffle node");
5088 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
5089 /// element of the result of the vector shuffle.
5090 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
5093 return SDValue(); // Limit search depth.
5095 SDValue V = SDValue(N, 0);
5096 EVT VT = V.getValueType();
5097 unsigned Opcode = V.getOpcode();
5099 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5100 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5101 int Elt = SV->getMaskElt(Index);
5104 return DAG.getUNDEF(VT.getVectorElementType());
5106 unsigned NumElems = VT.getVectorNumElements();
5107 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5108 : SV->getOperand(1);
5109 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5112 // Recurse into target specific vector shuffles to find scalars.
5113 if (isTargetShuffle(Opcode)) {
5114 MVT ShufVT = V.getSimpleValueType();
5115 unsigned NumElems = ShufVT.getVectorNumElements();
5116 SmallVector<int, 16> ShuffleMask;
5119 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5122 int Elt = ShuffleMask[Index];
5124 return DAG.getUNDEF(ShufVT.getVectorElementType());
5126 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5128 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5132 // Actual nodes that may contain scalar elements
5133 if (Opcode == ISD::BITCAST) {
5134 V = V.getOperand(0);
5135 EVT SrcVT = V.getValueType();
5136 unsigned NumElems = VT.getVectorNumElements();
5138 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5142 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5143 return (Index == 0) ? V.getOperand(0)
5144 : DAG.getUNDEF(VT.getVectorElementType());
5146 if (V.getOpcode() == ISD::BUILD_VECTOR)
5147 return V.getOperand(Index);
5152 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5153 /// shuffle operation which come from a consecutively from a zero. The
5154 /// search can start in two different directions, from left or right.
5155 /// We count undefs as zeros until PreferredNum is reached.
5156 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5157 unsigned NumElems, bool ZerosFromLeft,
5159 unsigned PreferredNum = -1U) {
5160 unsigned NumZeros = 0;
5161 for (unsigned i = 0; i != NumElems; ++i) {
5162 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5163 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5167 if (X86::isZeroNode(Elt))
5169 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5170 NumZeros = std::min(NumZeros + 1, PreferredNum);
5178 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5179 /// correspond consecutively to elements from one of the vector operands,
5180 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5182 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5183 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5184 unsigned NumElems, unsigned &OpNum) {
5185 bool SeenV1 = false;
5186 bool SeenV2 = false;
5188 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5189 int Idx = SVOp->getMaskElt(i);
5190 // Ignore undef indicies
5194 if (Idx < (int)NumElems)
5199 // Only accept consecutive elements from the same vector
5200 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5204 OpNum = SeenV1 ? 0 : 1;
5208 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5209 /// logical left shift of a vector.
5210 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5211 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5213 SVOp->getSimpleValueType(0).getVectorNumElements();
5214 unsigned NumZeros = getNumOfConsecutiveZeros(
5215 SVOp, NumElems, false /* check zeros from right */, DAG,
5216 SVOp->getMaskElt(0));
5222 // Considering the elements in the mask that are not consecutive zeros,
5223 // check if they consecutively come from only one of the source vectors.
5225 // V1 = {X, A, B, C} 0
5227 // vector_shuffle V1, V2 <1, 2, 3, X>
5229 if (!isShuffleMaskConsecutive(SVOp,
5230 0, // Mask Start Index
5231 NumElems-NumZeros, // Mask End Index(exclusive)
5232 NumZeros, // Where to start looking in the src vector
5233 NumElems, // Number of elements in vector
5234 OpSrc)) // Which source operand ?
5239 ShVal = SVOp->getOperand(OpSrc);
5243 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5244 /// logical left shift of a vector.
5245 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5246 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5248 SVOp->getSimpleValueType(0).getVectorNumElements();
5249 unsigned NumZeros = getNumOfConsecutiveZeros(
5250 SVOp, NumElems, true /* check zeros from left */, DAG,
5251 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5257 // Considering the elements in the mask that are not consecutive zeros,
5258 // check if they consecutively come from only one of the source vectors.
5260 // 0 { A, B, X, X } = V2
5262 // vector_shuffle V1, V2 <X, X, 4, 5>
5264 if (!isShuffleMaskConsecutive(SVOp,
5265 NumZeros, // Mask Start Index
5266 NumElems, // Mask End Index(exclusive)
5267 0, // Where to start looking in the src vector
5268 NumElems, // Number of elements in vector
5269 OpSrc)) // Which source operand ?
5274 ShVal = SVOp->getOperand(OpSrc);
5278 /// isVectorShift - Returns true if the shuffle can be implemented as a
5279 /// logical left or right shift of a vector.
5280 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5281 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5282 // Although the logic below support any bitwidth size, there are no
5283 // shift instructions which handle more than 128-bit vectors.
5284 if (!SVOp->getSimpleValueType(0).is128BitVector())
5287 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5288 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5294 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5296 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5297 unsigned NumNonZero, unsigned NumZero,
5299 const X86Subtarget* Subtarget,
5300 const TargetLowering &TLI) {
5307 for (unsigned i = 0; i < 16; ++i) {
5308 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5309 if (ThisIsNonZero && First) {
5311 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5313 V = DAG.getUNDEF(MVT::v8i16);
5318 SDValue ThisElt(0, 0), LastElt(0, 0);
5319 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5320 if (LastIsNonZero) {
5321 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5322 MVT::i16, Op.getOperand(i-1));
5324 if (ThisIsNonZero) {
5325 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5326 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5327 ThisElt, DAG.getConstant(8, MVT::i8));
5329 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5333 if (ThisElt.getNode())
5334 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5335 DAG.getIntPtrConstant(i/2));
5339 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5342 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5344 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5345 unsigned NumNonZero, unsigned NumZero,
5347 const X86Subtarget* Subtarget,
5348 const TargetLowering &TLI) {
5355 for (unsigned i = 0; i < 8; ++i) {
5356 bool isNonZero = (NonZeros & (1 << i)) != 0;
5360 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5362 V = DAG.getUNDEF(MVT::v8i16);
5365 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5366 MVT::v8i16, V, Op.getOperand(i),
5367 DAG.getIntPtrConstant(i));
5374 /// getVShift - Return a vector logical shift node.
5376 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5377 unsigned NumBits, SelectionDAG &DAG,
5378 const TargetLowering &TLI, SDLoc dl) {
5379 assert(VT.is128BitVector() && "Unknown type for VShift");
5380 EVT ShVT = MVT::v2i64;
5381 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5382 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5383 return DAG.getNode(ISD::BITCAST, dl, VT,
5384 DAG.getNode(Opc, dl, ShVT, SrcOp,
5385 DAG.getConstant(NumBits,
5386 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5390 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5392 // Check if the scalar load can be widened into a vector load. And if
5393 // the address is "base + cst" see if the cst can be "absorbed" into
5394 // the shuffle mask.
5395 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5396 SDValue Ptr = LD->getBasePtr();
5397 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5399 EVT PVT = LD->getValueType(0);
5400 if (PVT != MVT::i32 && PVT != MVT::f32)
5405 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5406 FI = FINode->getIndex();
5408 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5409 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5410 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5411 Offset = Ptr.getConstantOperandVal(1);
5412 Ptr = Ptr.getOperand(0);
5417 // FIXME: 256-bit vector instructions don't require a strict alignment,
5418 // improve this code to support it better.
5419 unsigned RequiredAlign = VT.getSizeInBits()/8;
5420 SDValue Chain = LD->getChain();
5421 // Make sure the stack object alignment is at least 16 or 32.
5422 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5423 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5424 if (MFI->isFixedObjectIndex(FI)) {
5425 // Can't change the alignment. FIXME: It's possible to compute
5426 // the exact stack offset and reference FI + adjust offset instead.
5427 // If someone *really* cares about this. That's the way to implement it.
5430 MFI->setObjectAlignment(FI, RequiredAlign);
5434 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5435 // Ptr + (Offset & ~15).
5438 if ((Offset % RequiredAlign) & 3)
5440 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5442 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5443 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5445 int EltNo = (Offset - StartOffset) >> 2;
5446 unsigned NumElems = VT.getVectorNumElements();
5448 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5449 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5450 LD->getPointerInfo().getWithOffset(StartOffset),
5451 false, false, false, 0);
5453 SmallVector<int, 8> Mask;
5454 for (unsigned i = 0; i != NumElems; ++i)
5455 Mask.push_back(EltNo);
5457 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5463 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5464 /// vector of type 'VT', see if the elements can be replaced by a single large
5465 /// load which has the same value as a build_vector whose operands are 'elts'.
5467 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5469 /// FIXME: we'd also like to handle the case where the last elements are zero
5470 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5471 /// There's even a handy isZeroNode for that purpose.
5472 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
5473 SDLoc &DL, SelectionDAG &DAG,
5474 bool isAfterLegalize) {
5475 EVT EltVT = VT.getVectorElementType();
5476 unsigned NumElems = Elts.size();
5478 LoadSDNode *LDBase = NULL;
5479 unsigned LastLoadedElt = -1U;
5481 // For each element in the initializer, see if we've found a load or an undef.
5482 // If we don't find an initial load element, or later load elements are
5483 // non-consecutive, bail out.
5484 for (unsigned i = 0; i < NumElems; ++i) {
5485 SDValue Elt = Elts[i];
5487 if (!Elt.getNode() ||
5488 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5491 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5493 LDBase = cast<LoadSDNode>(Elt.getNode());
5497 if (Elt.getOpcode() == ISD::UNDEF)
5500 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5501 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5506 // If we have found an entire vector of loads and undefs, then return a large
5507 // load of the entire vector width starting at the base pointer. If we found
5508 // consecutive loads for the low half, generate a vzext_load node.
5509 if (LastLoadedElt == NumElems - 1) {
5511 if (isAfterLegalize &&
5512 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
5515 SDValue NewLd = SDValue();
5517 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
5518 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5519 LDBase->getPointerInfo(),
5520 LDBase->isVolatile(), LDBase->isNonTemporal(),
5521 LDBase->isInvariant(), 0);
5522 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5523 LDBase->getPointerInfo(),
5524 LDBase->isVolatile(), LDBase->isNonTemporal(),
5525 LDBase->isInvariant(), LDBase->getAlignment());
5527 if (LDBase->hasAnyUseOfValue(1)) {
5528 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5530 SDValue(NewLd.getNode(), 1));
5531 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5532 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5533 SDValue(NewLd.getNode(), 1));
5538 if (NumElems == 4 && LastLoadedElt == 1 &&
5539 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5540 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5541 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5543 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops,
5544 array_lengthof(Ops), MVT::i64,
5545 LDBase->getPointerInfo(),
5546 LDBase->getAlignment(),
5547 false/*isVolatile*/, true/*ReadMem*/,
5550 // Make sure the newly-created LOAD is in the same position as LDBase in
5551 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5552 // update uses of LDBase's output chain to use the TokenFactor.
5553 if (LDBase->hasAnyUseOfValue(1)) {
5554 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5555 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5556 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5557 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5558 SDValue(ResNode.getNode(), 1));
5561 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
5566 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
5567 /// to generate a splat value for the following cases:
5568 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
5569 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
5570 /// a scalar load, or a constant.
5571 /// The VBROADCAST node is returned when a pattern is found,
5572 /// or SDValue() otherwise.
5573 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
5574 SelectionDAG &DAG) {
5575 if (!Subtarget->hasFp256())
5578 MVT VT = Op.getSimpleValueType();
5581 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
5582 "Unsupported vector type for broadcast.");
5587 switch (Op.getOpcode()) {
5589 // Unknown pattern found.
5592 case ISD::BUILD_VECTOR: {
5593 // The BUILD_VECTOR node must be a splat.
5594 if (!isSplatVector(Op.getNode()))
5597 Ld = Op.getOperand(0);
5598 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5599 Ld.getOpcode() == ISD::ConstantFP);
5601 // The suspected load node has several users. Make sure that all
5602 // of its users are from the BUILD_VECTOR node.
5603 // Constants may have multiple users.
5604 if (!ConstSplatVal && !Ld->hasNUsesOfValue(VT.getVectorNumElements(), 0))
5609 case ISD::VECTOR_SHUFFLE: {
5610 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5612 // Shuffles must have a splat mask where the first element is
5614 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5617 SDValue Sc = Op.getOperand(0);
5618 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5619 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5621 if (!Subtarget->hasInt256())
5624 // Use the register form of the broadcast instruction available on AVX2.
5625 if (VT.getSizeInBits() >= 256)
5626 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5627 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5630 Ld = Sc.getOperand(0);
5631 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5632 Ld.getOpcode() == ISD::ConstantFP);
5634 // The scalar_to_vector node and the suspected
5635 // load node must have exactly one user.
5636 // Constants may have multiple users.
5638 // AVX-512 has register version of the broadcast
5639 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
5640 Ld.getValueType().getSizeInBits() >= 32;
5641 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
5648 bool IsGE256 = (VT.getSizeInBits() >= 256);
5650 // Handle the broadcasting a single constant scalar from the constant pool
5651 // into a vector. On Sandybridge it is still better to load a constant vector
5652 // from the constant pool and not to broadcast it from a scalar.
5653 if (ConstSplatVal && Subtarget->hasInt256()) {
5654 EVT CVT = Ld.getValueType();
5655 assert(!CVT.isVector() && "Must not broadcast a vector type");
5656 unsigned ScalarSize = CVT.getSizeInBits();
5658 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)) {
5659 const Constant *C = 0;
5660 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5661 C = CI->getConstantIntValue();
5662 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5663 C = CF->getConstantFPValue();
5665 assert(C && "Invalid constant type");
5667 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5668 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
5669 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5670 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
5671 MachinePointerInfo::getConstantPool(),
5672 false, false, false, Alignment);
5674 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5678 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5679 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5681 // Handle AVX2 in-register broadcasts.
5682 if (!IsLoad && Subtarget->hasInt256() &&
5683 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
5684 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5686 // The scalar source must be a normal load.
5690 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64))
5691 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5693 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5694 // double since there is no vbroadcastsd xmm
5695 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
5696 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5697 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5700 // Unsupported broadcast.
5704 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
5705 MVT VT = Op.getSimpleValueType();
5707 // Skip if insert_vec_elt is not supported.
5708 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5709 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
5713 unsigned NumElems = Op.getNumOperands();
5717 SmallVector<unsigned, 4> InsertIndices;
5718 SmallVector<int, 8> Mask(NumElems, -1);
5720 for (unsigned i = 0; i != NumElems; ++i) {
5721 unsigned Opc = Op.getOperand(i).getOpcode();
5723 if (Opc == ISD::UNDEF)
5726 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
5727 // Quit if more than 1 elements need inserting.
5728 if (InsertIndices.size() > 1)
5731 InsertIndices.push_back(i);
5735 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
5736 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
5738 // Quit if extracted from vector of different type.
5739 if (ExtractedFromVec.getValueType() != VT)
5742 // Quit if non-constant index.
5743 if (!isa<ConstantSDNode>(ExtIdx))
5746 if (VecIn1.getNode() == 0)
5747 VecIn1 = ExtractedFromVec;
5748 else if (VecIn1 != ExtractedFromVec) {
5749 if (VecIn2.getNode() == 0)
5750 VecIn2 = ExtractedFromVec;
5751 else if (VecIn2 != ExtractedFromVec)
5752 // Quit if more than 2 vectors to shuffle
5756 unsigned Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
5758 if (ExtractedFromVec == VecIn1)
5760 else if (ExtractedFromVec == VecIn2)
5761 Mask[i] = Idx + NumElems;
5764 if (VecIn1.getNode() == 0)
5767 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5768 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
5769 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
5770 unsigned Idx = InsertIndices[i];
5771 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
5772 DAG.getIntPtrConstant(Idx));
5778 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
5780 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
5782 MVT VT = Op.getSimpleValueType();
5783 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
5784 "Unexpected type in LowerBUILD_VECTORvXi1!");
5787 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5788 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
5789 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5790 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5791 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
5792 Ops, VT.getVectorNumElements());
5795 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5796 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
5797 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5798 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5799 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
5800 Ops, VT.getVectorNumElements());
5803 bool AllContants = true;
5804 uint64_t Immediate = 0;
5805 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5806 SDValue In = Op.getOperand(idx);
5807 if (In.getOpcode() == ISD::UNDEF)
5809 if (!isa<ConstantSDNode>(In)) {
5810 AllContants = false;
5813 if (cast<ConstantSDNode>(In)->getZExtValue())
5814 Immediate |= (1ULL << idx);
5818 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
5819 DAG.getConstant(Immediate, MVT::i16));
5820 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
5821 DAG.getIntPtrConstant(0));
5824 // Splat vector (with undefs)
5825 SDValue In = Op.getOperand(0);
5826 for (unsigned i = 1, e = Op.getNumOperands(); i != e; ++i) {
5827 if (Op.getOperand(i) != In && Op.getOperand(i).getOpcode() != ISD::UNDEF)
5828 llvm_unreachable("Unsupported predicate operation");
5831 SDValue EFLAGS, X86CC;
5832 if (In.getOpcode() == ISD::SETCC) {
5833 SDValue Op0 = In.getOperand(0);
5834 SDValue Op1 = In.getOperand(1);
5835 ISD::CondCode CC = cast<CondCodeSDNode>(In.getOperand(2))->get();
5836 bool isFP = Op1.getValueType().isFloatingPoint();
5837 unsigned X86CCVal = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
5839 assert(X86CCVal != X86::COND_INVALID && "Unsupported predicate operation");
5841 X86CC = DAG.getConstant(X86CCVal, MVT::i8);
5842 EFLAGS = EmitCmp(Op0, Op1, X86CCVal, DAG);
5843 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
5844 } else if (In.getOpcode() == X86ISD::SETCC) {
5845 X86CC = In.getOperand(0);
5846 EFLAGS = In.getOperand(1);
5855 // res = allOnes ### CMOVNE -1, %res
5858 MVT InVT = In.getSimpleValueType();
5859 SDValue Bit1 = DAG.getNode(ISD::AND, dl, InVT, In, DAG.getConstant(1, InVT));
5860 EFLAGS = EmitTest(Bit1, X86::COND_NE, DAG);
5861 X86CC = DAG.getConstant(X86::COND_NE, MVT::i8);
5864 if (VT == MVT::v16i1) {
5865 SDValue Cst1 = DAG.getConstant(-1, MVT::i16);
5866 SDValue Cst0 = DAG.getConstant(0, MVT::i16);
5867 SDValue CmovOp = DAG.getNode(X86ISD::CMOV, dl, MVT::i16,
5868 Cst0, Cst1, X86CC, EFLAGS);
5869 return DAG.getNode(ISD::BITCAST, dl, VT, CmovOp);
5872 if (VT == MVT::v8i1) {
5873 SDValue Cst1 = DAG.getConstant(-1, MVT::i32);
5874 SDValue Cst0 = DAG.getConstant(0, MVT::i32);
5875 SDValue CmovOp = DAG.getNode(X86ISD::CMOV, dl, MVT::i32,
5876 Cst0, Cst1, X86CC, EFLAGS);
5877 CmovOp = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, CmovOp);
5878 return DAG.getNode(ISD::BITCAST, dl, VT, CmovOp);
5880 llvm_unreachable("Unsupported predicate operation");
5884 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5887 MVT VT = Op.getSimpleValueType();
5888 MVT ExtVT = VT.getVectorElementType();
5889 unsigned NumElems = Op.getNumOperands();
5891 // Generate vectors for predicate vectors.
5892 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
5893 return LowerBUILD_VECTORvXi1(Op, DAG);
5895 // Vectors containing all zeros can be matched by pxor and xorps later
5896 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5897 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
5898 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
5899 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
5902 return getZeroVector(VT, Subtarget, DAG, dl);
5905 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
5906 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
5907 // vpcmpeqd on 256-bit vectors.
5908 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
5909 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
5912 if (!VT.is512BitVector())
5913 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
5916 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
5917 if (Broadcast.getNode())
5920 unsigned EVTBits = ExtVT.getSizeInBits();
5922 unsigned NumZero = 0;
5923 unsigned NumNonZero = 0;
5924 unsigned NonZeros = 0;
5925 bool IsAllConstants = true;
5926 SmallSet<SDValue, 8> Values;
5927 for (unsigned i = 0; i < NumElems; ++i) {
5928 SDValue Elt = Op.getOperand(i);
5929 if (Elt.getOpcode() == ISD::UNDEF)
5932 if (Elt.getOpcode() != ISD::Constant &&
5933 Elt.getOpcode() != ISD::ConstantFP)
5934 IsAllConstants = false;
5935 if (X86::isZeroNode(Elt))
5938 NonZeros |= (1 << i);
5943 // All undef vector. Return an UNDEF. All zero vectors were handled above.
5944 if (NumNonZero == 0)
5945 return DAG.getUNDEF(VT);
5947 // Special case for single non-zero, non-undef, element.
5948 if (NumNonZero == 1) {
5949 unsigned Idx = countTrailingZeros(NonZeros);
5950 SDValue Item = Op.getOperand(Idx);
5952 // If this is an insertion of an i64 value on x86-32, and if the top bits of
5953 // the value are obviously zero, truncate the value to i32 and do the
5954 // insertion that way. Only do this if the value is non-constant or if the
5955 // value is a constant being inserted into element 0. It is cheaper to do
5956 // a constant pool load than it is to do a movd + shuffle.
5957 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5958 (!IsAllConstants || Idx == 0)) {
5959 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
5961 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5962 EVT VecVT = MVT::v4i32;
5963 unsigned VecElts = 4;
5965 // Truncate the value (which may itself be a constant) to i32, and
5966 // convert it to a vector with movd (S2V+shuffle to zero extend).
5967 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5968 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5969 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5971 // Now we have our 32-bit value zero extended in the low element of
5972 // a vector. If Idx != 0, swizzle it into place.
5974 SmallVector<int, 4> Mask;
5975 Mask.push_back(Idx);
5976 for (unsigned i = 1; i != VecElts; ++i)
5978 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
5981 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5985 // If we have a constant or non-constant insertion into the low element of
5986 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5987 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5988 // depending on what the source datatype is.
5991 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5993 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5994 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5995 if (VT.is256BitVector() || VT.is512BitVector()) {
5996 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
5997 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
5998 Item, DAG.getIntPtrConstant(0));
6000 assert(VT.is128BitVector() && "Expected an SSE value type!");
6001 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6002 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6003 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6006 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6007 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6008 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6009 if (VT.is256BitVector()) {
6010 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6011 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6013 assert(VT.is128BitVector() && "Expected an SSE value type!");
6014 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6016 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6020 // Is it a vector logical left shift?
6021 if (NumElems == 2 && Idx == 1 &&
6022 X86::isZeroNode(Op.getOperand(0)) &&
6023 !X86::isZeroNode(Op.getOperand(1))) {
6024 unsigned NumBits = VT.getSizeInBits();
6025 return getVShift(true, VT,
6026 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6027 VT, Op.getOperand(1)),
6028 NumBits/2, DAG, *this, dl);
6031 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6034 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6035 // is a non-constant being inserted into an element other than the low one,
6036 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6037 // movd/movss) to move this into the low element, then shuffle it into
6039 if (EVTBits == 32) {
6040 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6042 // Turn it into a shuffle of zero and zero-extended scalar to vector.
6043 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
6044 SmallVector<int, 8> MaskVec;
6045 for (unsigned i = 0; i != NumElems; ++i)
6046 MaskVec.push_back(i == Idx ? 0 : 1);
6047 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
6051 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6052 if (Values.size() == 1) {
6053 if (EVTBits == 32) {
6054 // Instead of a shuffle like this:
6055 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6056 // Check if it's possible to issue this instead.
6057 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6058 unsigned Idx = countTrailingZeros(NonZeros);
6059 SDValue Item = Op.getOperand(Idx);
6060 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6061 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6066 // A vector full of immediates; various special cases are already
6067 // handled, so this is best done with a single constant-pool load.
6071 // For AVX-length vectors, build the individual 128-bit pieces and use
6072 // shuffles to put them in place.
6073 if (VT.is256BitVector()) {
6074 SmallVector<SDValue, 32> V;
6075 for (unsigned i = 0; i != NumElems; ++i)
6076 V.push_back(Op.getOperand(i));
6078 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6080 // Build both the lower and upper subvector.
6081 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2);
6082 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2],
6085 // Recreate the wider vector with the lower and upper part.
6086 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6089 // Let legalizer expand 2-wide build_vectors.
6090 if (EVTBits == 64) {
6091 if (NumNonZero == 1) {
6092 // One half is zero or undef.
6093 unsigned Idx = countTrailingZeros(NonZeros);
6094 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6095 Op.getOperand(Idx));
6096 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6101 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6102 if (EVTBits == 8 && NumElems == 16) {
6103 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
6105 if (V.getNode()) return V;
6108 if (EVTBits == 16 && NumElems == 8) {
6109 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
6111 if (V.getNode()) return V;
6114 // If element VT is == 32 bits, turn it into a number of shuffles.
6115 SmallVector<SDValue, 8> V(NumElems);
6116 if (NumElems == 4 && NumZero > 0) {
6117 for (unsigned i = 0; i < 4; ++i) {
6118 bool isZero = !(NonZeros & (1 << i));
6120 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
6122 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6125 for (unsigned i = 0; i < 2; ++i) {
6126 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
6129 V[i] = V[i*2]; // Must be a zero vector.
6132 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
6135 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
6138 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
6143 bool Reverse1 = (NonZeros & 0x3) == 2;
6144 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
6148 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
6149 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
6151 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
6154 if (Values.size() > 1 && VT.is128BitVector()) {
6155 // Check for a build vector of consecutive loads.
6156 for (unsigned i = 0; i < NumElems; ++i)
6157 V[i] = Op.getOperand(i);
6159 // Check for elements which are consecutive loads.
6160 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false);
6164 // Check for a build vector from mostly shuffle plus few inserting.
6165 SDValue Sh = buildFromShuffleMostly(Op, DAG);
6169 // For SSE 4.1, use insertps to put the high elements into the low element.
6170 if (getSubtarget()->hasSSE41()) {
6172 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
6173 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
6175 Result = DAG.getUNDEF(VT);
6177 for (unsigned i = 1; i < NumElems; ++i) {
6178 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
6179 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
6180 Op.getOperand(i), DAG.getIntPtrConstant(i));
6185 // Otherwise, expand into a number of unpckl*, start by extending each of
6186 // our (non-undef) elements to the full vector width with the element in the
6187 // bottom slot of the vector (which generates no code for SSE).
6188 for (unsigned i = 0; i < NumElems; ++i) {
6189 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
6190 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6192 V[i] = DAG.getUNDEF(VT);
6195 // Next, we iteratively mix elements, e.g. for v4f32:
6196 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
6197 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
6198 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
6199 unsigned EltStride = NumElems >> 1;
6200 while (EltStride != 0) {
6201 for (unsigned i = 0; i < EltStride; ++i) {
6202 // If V[i+EltStride] is undef and this is the first round of mixing,
6203 // then it is safe to just drop this shuffle: V[i] is already in the
6204 // right place, the one element (since it's the first round) being
6205 // inserted as undef can be dropped. This isn't safe for successive
6206 // rounds because they will permute elements within both vectors.
6207 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
6208 EltStride == NumElems/2)
6211 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
6220 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
6221 // to create 256-bit vectors from two other 128-bit ones.
6222 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6224 MVT ResVT = Op.getSimpleValueType();
6226 assert((ResVT.is256BitVector() ||
6227 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
6229 SDValue V1 = Op.getOperand(0);
6230 SDValue V2 = Op.getOperand(1);
6231 unsigned NumElems = ResVT.getVectorNumElements();
6232 if(ResVT.is256BitVector())
6233 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6235 if (Op.getNumOperands() == 4) {
6236 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
6237 ResVT.getVectorNumElements()/2);
6238 SDValue V3 = Op.getOperand(2);
6239 SDValue V4 = Op.getOperand(3);
6240 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
6241 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
6243 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6246 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6247 MVT LLVM_ATTRIBUTE_UNUSED VT = Op.getSimpleValueType();
6248 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
6249 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
6250 Op.getNumOperands() == 4)));
6252 // AVX can use the vinsertf128 instruction to create 256-bit vectors
6253 // from two other 128-bit ones.
6255 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
6256 return LowerAVXCONCAT_VECTORS(Op, DAG);
6259 // Try to lower a shuffle node into a simple blend instruction.
6261 LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
6262 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
6263 SDValue V1 = SVOp->getOperand(0);
6264 SDValue V2 = SVOp->getOperand(1);
6266 MVT VT = SVOp->getSimpleValueType(0);
6267 MVT EltVT = VT.getVectorElementType();
6268 unsigned NumElems = VT.getVectorNumElements();
6270 // There is no blend with immediate in AVX-512.
6271 if (VT.is512BitVector())
6274 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
6276 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
6279 // Check the mask for BLEND and build the value.
6280 unsigned MaskValue = 0;
6281 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
6282 unsigned NumLanes = (NumElems-1)/8 + 1;
6283 unsigned NumElemsInLane = NumElems / NumLanes;
6285 // Blend for v16i16 should be symetric for the both lanes.
6286 for (unsigned i = 0; i < NumElemsInLane; ++i) {
6288 int SndLaneEltIdx = (NumLanes == 2) ?
6289 SVOp->getMaskElt(i + NumElemsInLane) : -1;
6290 int EltIdx = SVOp->getMaskElt(i);
6292 if ((EltIdx < 0 || EltIdx == (int)i) &&
6293 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
6296 if (((unsigned)EltIdx == (i + NumElems)) &&
6297 (SndLaneEltIdx < 0 ||
6298 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
6299 MaskValue |= (1<<i);
6304 // Convert i32 vectors to floating point if it is not AVX2.
6305 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
6307 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
6308 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
6310 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
6311 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
6314 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
6315 DAG.getConstant(MaskValue, MVT::i32));
6316 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
6319 // v8i16 shuffles - Prefer shuffles in the following order:
6320 // 1. [all] pshuflw, pshufhw, optional move
6321 // 2. [ssse3] 1 x pshufb
6322 // 3. [ssse3] 2 x pshufb + 1 x por
6323 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
6325 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
6326 SelectionDAG &DAG) {
6327 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6328 SDValue V1 = SVOp->getOperand(0);
6329 SDValue V2 = SVOp->getOperand(1);
6331 SmallVector<int, 8> MaskVals;
6333 // Determine if more than 1 of the words in each of the low and high quadwords
6334 // of the result come from the same quadword of one of the two inputs. Undef
6335 // mask values count as coming from any quadword, for better codegen.
6336 unsigned LoQuad[] = { 0, 0, 0, 0 };
6337 unsigned HiQuad[] = { 0, 0, 0, 0 };
6338 std::bitset<4> InputQuads;
6339 for (unsigned i = 0; i < 8; ++i) {
6340 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
6341 int EltIdx = SVOp->getMaskElt(i);
6342 MaskVals.push_back(EltIdx);
6351 InputQuads.set(EltIdx / 4);
6354 int BestLoQuad = -1;
6355 unsigned MaxQuad = 1;
6356 for (unsigned i = 0; i < 4; ++i) {
6357 if (LoQuad[i] > MaxQuad) {
6359 MaxQuad = LoQuad[i];
6363 int BestHiQuad = -1;
6365 for (unsigned i = 0; i < 4; ++i) {
6366 if (HiQuad[i] > MaxQuad) {
6368 MaxQuad = HiQuad[i];
6372 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
6373 // of the two input vectors, shuffle them into one input vector so only a
6374 // single pshufb instruction is necessary. If There are more than 2 input
6375 // quads, disable the next transformation since it does not help SSSE3.
6376 bool V1Used = InputQuads[0] || InputQuads[1];
6377 bool V2Used = InputQuads[2] || InputQuads[3];
6378 if (Subtarget->hasSSSE3()) {
6379 if (InputQuads.count() == 2 && V1Used && V2Used) {
6380 BestLoQuad = InputQuads[0] ? 0 : 1;
6381 BestHiQuad = InputQuads[2] ? 2 : 3;
6383 if (InputQuads.count() > 2) {
6389 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
6390 // the shuffle mask. If a quad is scored as -1, that means that it contains
6391 // words from all 4 input quadwords.
6393 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
6395 BestLoQuad < 0 ? 0 : BestLoQuad,
6396 BestHiQuad < 0 ? 1 : BestHiQuad
6398 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
6399 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
6400 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
6401 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
6403 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
6404 // source words for the shuffle, to aid later transformations.
6405 bool AllWordsInNewV = true;
6406 bool InOrder[2] = { true, true };
6407 for (unsigned i = 0; i != 8; ++i) {
6408 int idx = MaskVals[i];
6410 InOrder[i/4] = false;
6411 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
6413 AllWordsInNewV = false;
6417 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
6418 if (AllWordsInNewV) {
6419 for (int i = 0; i != 8; ++i) {
6420 int idx = MaskVals[i];
6423 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
6424 if ((idx != i) && idx < 4)
6426 if ((idx != i) && idx > 3)
6435 // If we've eliminated the use of V2, and the new mask is a pshuflw or
6436 // pshufhw, that's as cheap as it gets. Return the new shuffle.
6437 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
6438 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
6439 unsigned TargetMask = 0;
6440 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
6441 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
6442 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
6443 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
6444 getShufflePSHUFLWImmediate(SVOp);
6445 V1 = NewV.getOperand(0);
6446 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
6450 // Promote splats to a larger type which usually leads to more efficient code.
6451 // FIXME: Is this true if pshufb is available?
6452 if (SVOp->isSplat())
6453 return PromoteSplat(SVOp, DAG);
6455 // If we have SSSE3, and all words of the result are from 1 input vector,
6456 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
6457 // is present, fall back to case 4.
6458 if (Subtarget->hasSSSE3()) {
6459 SmallVector<SDValue,16> pshufbMask;
6461 // If we have elements from both input vectors, set the high bit of the
6462 // shuffle mask element to zero out elements that come from V2 in the V1
6463 // mask, and elements that come from V1 in the V2 mask, so that the two
6464 // results can be OR'd together.
6465 bool TwoInputs = V1Used && V2Used;
6466 for (unsigned i = 0; i != 8; ++i) {
6467 int EltIdx = MaskVals[i] * 2;
6468 int Idx0 = (TwoInputs && (EltIdx >= 16)) ? 0x80 : EltIdx;
6469 int Idx1 = (TwoInputs && (EltIdx >= 16)) ? 0x80 : EltIdx+1;
6470 pshufbMask.push_back(DAG.getConstant(Idx0, MVT::i8));
6471 pshufbMask.push_back(DAG.getConstant(Idx1, MVT::i8));
6473 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1);
6474 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
6475 DAG.getNode(ISD::BUILD_VECTOR, dl,
6476 MVT::v16i8, &pshufbMask[0], 16));
6478 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
6480 // Calculate the shuffle mask for the second input, shuffle it, and
6481 // OR it with the first shuffled input.
6483 for (unsigned i = 0; i != 8; ++i) {
6484 int EltIdx = MaskVals[i] * 2;
6485 int Idx0 = (EltIdx < 16) ? 0x80 : EltIdx - 16;
6486 int Idx1 = (EltIdx < 16) ? 0x80 : EltIdx - 15;
6487 pshufbMask.push_back(DAG.getConstant(Idx0, MVT::i8));
6488 pshufbMask.push_back(DAG.getConstant(Idx1, MVT::i8));
6490 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2);
6491 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
6492 DAG.getNode(ISD::BUILD_VECTOR, dl,
6493 MVT::v16i8, &pshufbMask[0], 16));
6494 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
6495 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
6498 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
6499 // and update MaskVals with new element order.
6500 std::bitset<8> InOrder;
6501 if (BestLoQuad >= 0) {
6502 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
6503 for (int i = 0; i != 4; ++i) {
6504 int idx = MaskVals[i];
6507 } else if ((idx / 4) == BestLoQuad) {
6512 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
6515 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
6516 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
6517 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
6519 getShufflePSHUFLWImmediate(SVOp), DAG);
6523 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
6524 // and update MaskVals with the new element order.
6525 if (BestHiQuad >= 0) {
6526 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
6527 for (unsigned i = 4; i != 8; ++i) {
6528 int idx = MaskVals[i];
6531 } else if ((idx / 4) == BestHiQuad) {
6532 MaskV[i] = (idx & 3) + 4;
6536 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
6539 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
6540 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
6541 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
6543 getShufflePSHUFHWImmediate(SVOp), DAG);
6547 // In case BestHi & BestLo were both -1, which means each quadword has a word
6548 // from each of the four input quadwords, calculate the InOrder bitvector now
6549 // before falling through to the insert/extract cleanup.
6550 if (BestLoQuad == -1 && BestHiQuad == -1) {
6552 for (int i = 0; i != 8; ++i)
6553 if (MaskVals[i] < 0 || MaskVals[i] == i)
6557 // The other elements are put in the right place using pextrw and pinsrw.
6558 for (unsigned i = 0; i != 8; ++i) {
6561 int EltIdx = MaskVals[i];
6564 SDValue ExtOp = (EltIdx < 8) ?
6565 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
6566 DAG.getIntPtrConstant(EltIdx)) :
6567 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
6568 DAG.getIntPtrConstant(EltIdx - 8));
6569 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
6570 DAG.getIntPtrConstant(i));
6575 // v16i8 shuffles - Prefer shuffles in the following order:
6576 // 1. [ssse3] 1 x pshufb
6577 // 2. [ssse3] 2 x pshufb + 1 x por
6578 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
6579 static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
6580 const X86Subtarget* Subtarget,
6581 SelectionDAG &DAG) {
6582 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6583 SDValue V1 = SVOp->getOperand(0);
6584 SDValue V2 = SVOp->getOperand(1);
6586 ArrayRef<int> MaskVals = SVOp->getMask();
6588 // Promote splats to a larger type which usually leads to more efficient code.
6589 // FIXME: Is this true if pshufb is available?
6590 if (SVOp->isSplat())
6591 return PromoteSplat(SVOp, DAG);
6593 // If we have SSSE3, case 1 is generated when all result bytes come from
6594 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
6595 // present, fall back to case 3.
6597 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
6598 if (Subtarget->hasSSSE3()) {
6599 SmallVector<SDValue,16> pshufbMask;
6601 // If all result elements are from one input vector, then only translate
6602 // undef mask values to 0x80 (zero out result) in the pshufb mask.
6604 // Otherwise, we have elements from both input vectors, and must zero out
6605 // elements that come from V2 in the first mask, and V1 in the second mask
6606 // so that we can OR them together.
6607 for (unsigned i = 0; i != 16; ++i) {
6608 int EltIdx = MaskVals[i];
6609 if (EltIdx < 0 || EltIdx >= 16)
6611 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
6613 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
6614 DAG.getNode(ISD::BUILD_VECTOR, dl,
6615 MVT::v16i8, &pshufbMask[0], 16));
6617 // As PSHUFB will zero elements with negative indices, it's safe to ignore
6618 // the 2nd operand if it's undefined or zero.
6619 if (V2.getOpcode() == ISD::UNDEF ||
6620 ISD::isBuildVectorAllZeros(V2.getNode()))
6623 // Calculate the shuffle mask for the second input, shuffle it, and
6624 // OR it with the first shuffled input.
6626 for (unsigned i = 0; i != 16; ++i) {
6627 int EltIdx = MaskVals[i];
6628 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
6629 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
6631 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
6632 DAG.getNode(ISD::BUILD_VECTOR, dl,
6633 MVT::v16i8, &pshufbMask[0], 16));
6634 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
6637 // No SSSE3 - Calculate in place words and then fix all out of place words
6638 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
6639 // the 16 different words that comprise the two doublequadword input vectors.
6640 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
6641 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
6643 for (int i = 0; i != 8; ++i) {
6644 int Elt0 = MaskVals[i*2];
6645 int Elt1 = MaskVals[i*2+1];
6647 // This word of the result is all undef, skip it.
6648 if (Elt0 < 0 && Elt1 < 0)
6651 // This word of the result is already in the correct place, skip it.
6652 if ((Elt0 == i*2) && (Elt1 == i*2+1))
6655 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
6656 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
6659 // If Elt0 and Elt1 are defined, are consecutive, and can be load
6660 // using a single extract together, load it and store it.
6661 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
6662 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
6663 DAG.getIntPtrConstant(Elt1 / 2));
6664 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
6665 DAG.getIntPtrConstant(i));
6669 // If Elt1 is defined, extract it from the appropriate source. If the
6670 // source byte is not also odd, shift the extracted word left 8 bits
6671 // otherwise clear the bottom 8 bits if we need to do an or.
6673 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
6674 DAG.getIntPtrConstant(Elt1 / 2));
6675 if ((Elt1 & 1) == 0)
6676 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
6678 TLI.getShiftAmountTy(InsElt.getValueType())));
6680 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
6681 DAG.getConstant(0xFF00, MVT::i16));
6683 // If Elt0 is defined, extract it from the appropriate source. If the
6684 // source byte is not also even, shift the extracted word right 8 bits. If
6685 // Elt1 was also defined, OR the extracted values together before
6686 // inserting them in the result.
6688 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
6689 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
6690 if ((Elt0 & 1) != 0)
6691 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
6693 TLI.getShiftAmountTy(InsElt0.getValueType())));
6695 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
6696 DAG.getConstant(0x00FF, MVT::i16));
6697 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
6700 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
6701 DAG.getIntPtrConstant(i));
6703 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
6706 // v32i8 shuffles - Translate to VPSHUFB if possible.
6708 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
6709 const X86Subtarget *Subtarget,
6710 SelectionDAG &DAG) {
6711 MVT VT = SVOp->getSimpleValueType(0);
6712 SDValue V1 = SVOp->getOperand(0);
6713 SDValue V2 = SVOp->getOperand(1);
6715 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
6717 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
6718 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
6719 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
6721 // VPSHUFB may be generated if
6722 // (1) one of input vector is undefined or zeroinitializer.
6723 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
6724 // And (2) the mask indexes don't cross the 128-bit lane.
6725 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
6726 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
6729 if (V1IsAllZero && !V2IsAllZero) {
6730 CommuteVectorShuffleMask(MaskVals, 32);
6733 SmallVector<SDValue, 32> pshufbMask;
6734 for (unsigned i = 0; i != 32; i++) {
6735 int EltIdx = MaskVals[i];
6736 if (EltIdx < 0 || EltIdx >= 32)
6739 if ((EltIdx >= 16 && i < 16) || (EltIdx < 16 && i >= 16))
6740 // Cross lane is not allowed.
6744 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
6746 return DAG.getNode(X86ISD::PSHUFB, dl, MVT::v32i8, V1,
6747 DAG.getNode(ISD::BUILD_VECTOR, dl,
6748 MVT::v32i8, &pshufbMask[0], 32));
6751 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
6752 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
6753 /// done when every pair / quad of shuffle mask elements point to elements in
6754 /// the right sequence. e.g.
6755 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
6757 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
6758 SelectionDAG &DAG) {
6759 MVT VT = SVOp->getSimpleValueType(0);
6761 unsigned NumElems = VT.getVectorNumElements();
6764 switch (VT.SimpleTy) {
6765 default: llvm_unreachable("Unexpected!");
6766 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
6767 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
6768 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
6769 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
6770 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
6771 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
6774 SmallVector<int, 8> MaskVec;
6775 for (unsigned i = 0; i != NumElems; i += Scale) {
6777 for (unsigned j = 0; j != Scale; ++j) {
6778 int EltIdx = SVOp->getMaskElt(i+j);
6782 StartIdx = (EltIdx / Scale);
6783 if (EltIdx != (int)(StartIdx*Scale + j))
6786 MaskVec.push_back(StartIdx);
6789 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
6790 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
6791 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
6794 /// getVZextMovL - Return a zero-extending vector move low node.
6796 static SDValue getVZextMovL(MVT VT, MVT OpVT,
6797 SDValue SrcOp, SelectionDAG &DAG,
6798 const X86Subtarget *Subtarget, SDLoc dl) {
6799 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
6800 LoadSDNode *LD = NULL;
6801 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
6802 LD = dyn_cast<LoadSDNode>(SrcOp);
6804 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
6806 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
6807 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
6808 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
6809 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
6810 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
6812 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
6813 return DAG.getNode(ISD::BITCAST, dl, VT,
6814 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
6815 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6823 return DAG.getNode(ISD::BITCAST, dl, VT,
6824 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
6825 DAG.getNode(ISD::BITCAST, dl,
6829 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
6830 /// which could not be matched by any known target speficic shuffle
6832 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6834 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
6835 if (NewOp.getNode())
6838 MVT VT = SVOp->getSimpleValueType(0);
6840 unsigned NumElems = VT.getVectorNumElements();
6841 unsigned NumLaneElems = NumElems / 2;
6844 MVT EltVT = VT.getVectorElementType();
6845 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
6848 SmallVector<int, 16> Mask;
6849 for (unsigned l = 0; l < 2; ++l) {
6850 // Build a shuffle mask for the output, discovering on the fly which
6851 // input vectors to use as shuffle operands (recorded in InputUsed).
6852 // If building a suitable shuffle vector proves too hard, then bail
6853 // out with UseBuildVector set.
6854 bool UseBuildVector = false;
6855 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
6856 unsigned LaneStart = l * NumLaneElems;
6857 for (unsigned i = 0; i != NumLaneElems; ++i) {
6858 // The mask element. This indexes into the input.
6859 int Idx = SVOp->getMaskElt(i+LaneStart);
6861 // the mask element does not index into any input vector.
6866 // The input vector this mask element indexes into.
6867 int Input = Idx / NumLaneElems;
6869 // Turn the index into an offset from the start of the input vector.
6870 Idx -= Input * NumLaneElems;
6872 // Find or create a shuffle vector operand to hold this input.
6874 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
6875 if (InputUsed[OpNo] == Input)
6876 // This input vector is already an operand.
6878 if (InputUsed[OpNo] < 0) {
6879 // Create a new operand for this input vector.
6880 InputUsed[OpNo] = Input;
6885 if (OpNo >= array_lengthof(InputUsed)) {
6886 // More than two input vectors used! Give up on trying to create a
6887 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
6888 UseBuildVector = true;
6892 // Add the mask index for the new shuffle vector.
6893 Mask.push_back(Idx + OpNo * NumLaneElems);
6896 if (UseBuildVector) {
6897 SmallVector<SDValue, 16> SVOps;
6898 for (unsigned i = 0; i != NumLaneElems; ++i) {
6899 // The mask element. This indexes into the input.
6900 int Idx = SVOp->getMaskElt(i+LaneStart);
6902 SVOps.push_back(DAG.getUNDEF(EltVT));
6906 // The input vector this mask element indexes into.
6907 int Input = Idx / NumElems;
6909 // Turn the index into an offset from the start of the input vector.
6910 Idx -= Input * NumElems;
6912 // Extract the vector element by hand.
6913 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
6914 SVOp->getOperand(Input),
6915 DAG.getIntPtrConstant(Idx)));
6918 // Construct the output using a BUILD_VECTOR.
6919 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, &SVOps[0],
6921 } else if (InputUsed[0] < 0) {
6922 // No input vectors were used! The result is undefined.
6923 Output[l] = DAG.getUNDEF(NVT);
6925 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
6926 (InputUsed[0] % 2) * NumLaneElems,
6928 // If only one input was used, use an undefined vector for the other.
6929 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
6930 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
6931 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
6932 // At least one input vector was used. Create a new shuffle vector.
6933 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
6939 // Concatenate the result back
6940 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
6943 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
6944 /// 4 elements, and match them with several different shuffle types.
6946 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6947 SDValue V1 = SVOp->getOperand(0);
6948 SDValue V2 = SVOp->getOperand(1);
6950 MVT VT = SVOp->getSimpleValueType(0);
6952 assert(VT.is128BitVector() && "Unsupported vector size");
6954 std::pair<int, int> Locs[4];
6955 int Mask1[] = { -1, -1, -1, -1 };
6956 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
6960 for (unsigned i = 0; i != 4; ++i) {
6961 int Idx = PermMask[i];
6963 Locs[i] = std::make_pair(-1, -1);
6965 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
6967 Locs[i] = std::make_pair(0, NumLo);
6971 Locs[i] = std::make_pair(1, NumHi);
6973 Mask1[2+NumHi] = Idx;
6979 if (NumLo <= 2 && NumHi <= 2) {
6980 // If no more than two elements come from either vector. This can be
6981 // implemented with two shuffles. First shuffle gather the elements.
6982 // The second shuffle, which takes the first shuffle as both of its
6983 // vector operands, put the elements into the right order.
6984 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6986 int Mask2[] = { -1, -1, -1, -1 };
6988 for (unsigned i = 0; i != 4; ++i)
6989 if (Locs[i].first != -1) {
6990 unsigned Idx = (i < 2) ? 0 : 4;
6991 Idx += Locs[i].first * 2 + Locs[i].second;
6995 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
6998 if (NumLo == 3 || NumHi == 3) {
6999 // Otherwise, we must have three elements from one vector, call it X, and
7000 // one element from the other, call it Y. First, use a shufps to build an
7001 // intermediate vector with the one element from Y and the element from X
7002 // that will be in the same half in the final destination (the indexes don't
7003 // matter). Then, use a shufps to build the final vector, taking the half
7004 // containing the element from Y from the intermediate, and the other half
7007 // Normalize it so the 3 elements come from V1.
7008 CommuteVectorShuffleMask(PermMask, 4);
7012 // Find the element from V2.
7014 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
7015 int Val = PermMask[HiIndex];
7022 Mask1[0] = PermMask[HiIndex];
7024 Mask1[2] = PermMask[HiIndex^1];
7026 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
7029 Mask1[0] = PermMask[0];
7030 Mask1[1] = PermMask[1];
7031 Mask1[2] = HiIndex & 1 ? 6 : 4;
7032 Mask1[3] = HiIndex & 1 ? 4 : 6;
7033 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
7036 Mask1[0] = HiIndex & 1 ? 2 : 0;
7037 Mask1[1] = HiIndex & 1 ? 0 : 2;
7038 Mask1[2] = PermMask[2];
7039 Mask1[3] = PermMask[3];
7044 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
7047 // Break it into (shuffle shuffle_hi, shuffle_lo).
7048 int LoMask[] = { -1, -1, -1, -1 };
7049 int HiMask[] = { -1, -1, -1, -1 };
7051 int *MaskPtr = LoMask;
7052 unsigned MaskIdx = 0;
7055 for (unsigned i = 0; i != 4; ++i) {
7062 int Idx = PermMask[i];
7064 Locs[i] = std::make_pair(-1, -1);
7065 } else if (Idx < 4) {
7066 Locs[i] = std::make_pair(MaskIdx, LoIdx);
7067 MaskPtr[LoIdx] = Idx;
7070 Locs[i] = std::make_pair(MaskIdx, HiIdx);
7071 MaskPtr[HiIdx] = Idx;
7076 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
7077 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
7078 int MaskOps[] = { -1, -1, -1, -1 };
7079 for (unsigned i = 0; i != 4; ++i)
7080 if (Locs[i].first != -1)
7081 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
7082 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
7085 static bool MayFoldVectorLoad(SDValue V) {
7086 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
7087 V = V.getOperand(0);
7089 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
7090 V = V.getOperand(0);
7091 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
7092 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
7093 // BUILD_VECTOR (load), undef
7094 V = V.getOperand(0);
7096 return MayFoldLoad(V);
7100 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
7101 MVT VT = Op.getSimpleValueType();
7103 // Canonizalize to v2f64.
7104 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
7105 return DAG.getNode(ISD::BITCAST, dl, VT,
7106 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
7111 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
7113 SDValue V1 = Op.getOperand(0);
7114 SDValue V2 = Op.getOperand(1);
7115 MVT VT = Op.getSimpleValueType();
7117 assert(VT != MVT::v2i64 && "unsupported shuffle type");
7119 if (HasSSE2 && VT == MVT::v2f64)
7120 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
7122 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
7123 return DAG.getNode(ISD::BITCAST, dl, VT,
7124 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
7125 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
7126 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
7130 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
7131 SDValue V1 = Op.getOperand(0);
7132 SDValue V2 = Op.getOperand(1);
7133 MVT VT = Op.getSimpleValueType();
7135 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
7136 "unsupported shuffle type");
7138 if (V2.getOpcode() == ISD::UNDEF)
7142 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
7146 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
7147 SDValue V1 = Op.getOperand(0);
7148 SDValue V2 = Op.getOperand(1);
7149 MVT VT = Op.getSimpleValueType();
7150 unsigned NumElems = VT.getVectorNumElements();
7152 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
7153 // operand of these instructions is only memory, so check if there's a
7154 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
7156 bool CanFoldLoad = false;
7158 // Trivial case, when V2 comes from a load.
7159 if (MayFoldVectorLoad(V2))
7162 // When V1 is a load, it can be folded later into a store in isel, example:
7163 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
7165 // (MOVLPSmr addr:$src1, VR128:$src2)
7166 // So, recognize this potential and also use MOVLPS or MOVLPD
7167 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
7170 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7172 if (HasSSE2 && NumElems == 2)
7173 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
7176 // If we don't care about the second element, proceed to use movss.
7177 if (SVOp->getMaskElt(1) != -1)
7178 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
7181 // movl and movlp will both match v2i64, but v2i64 is never matched by
7182 // movl earlier because we make it strict to avoid messing with the movlp load
7183 // folding logic (see the code above getMOVLP call). Match it here then,
7184 // this is horrible, but will stay like this until we move all shuffle
7185 // matching to x86 specific nodes. Note that for the 1st condition all
7186 // types are matched with movsd.
7188 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
7189 // as to remove this logic from here, as much as possible
7190 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
7191 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
7192 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
7195 assert(VT != MVT::v4i32 && "unsupported shuffle type");
7197 // Invert the operand order and use SHUFPS to match it.
7198 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
7199 getShuffleSHUFImmediate(SVOp), DAG);
7202 // Reduce a vector shuffle to zext.
7203 static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
7204 SelectionDAG &DAG) {
7205 // PMOVZX is only available from SSE41.
7206 if (!Subtarget->hasSSE41())
7209 MVT VT = Op.getSimpleValueType();
7211 // Only AVX2 support 256-bit vector integer extending.
7212 if (!Subtarget->hasInt256() && VT.is256BitVector())
7215 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7217 SDValue V1 = Op.getOperand(0);
7218 SDValue V2 = Op.getOperand(1);
7219 unsigned NumElems = VT.getVectorNumElements();
7221 // Extending is an unary operation and the element type of the source vector
7222 // won't be equal to or larger than i64.
7223 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
7224 VT.getVectorElementType() == MVT::i64)
7227 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
7228 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
7229 while ((1U << Shift) < NumElems) {
7230 if (SVOp->getMaskElt(1U << Shift) == 1)
7233 // The maximal ratio is 8, i.e. from i8 to i64.
7238 // Check the shuffle mask.
7239 unsigned Mask = (1U << Shift) - 1;
7240 for (unsigned i = 0; i != NumElems; ++i) {
7241 int EltIdx = SVOp->getMaskElt(i);
7242 if ((i & Mask) != 0 && EltIdx != -1)
7244 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
7248 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
7249 MVT NeVT = MVT::getIntegerVT(NBits);
7250 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift);
7252 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT))
7255 // Simplify the operand as it's prepared to be fed into shuffle.
7256 unsigned SignificantBits = NVT.getSizeInBits() >> Shift;
7257 if (V1.getOpcode() == ISD::BITCAST &&
7258 V1.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
7259 V1.getOperand(0).getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
7260 V1.getOperand(0).getOperand(0)
7261 .getSimpleValueType().getSizeInBits() == SignificantBits) {
7262 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
7263 SDValue V = V1.getOperand(0).getOperand(0).getOperand(0);
7264 ConstantSDNode *CIdx =
7265 dyn_cast<ConstantSDNode>(V1.getOperand(0).getOperand(0).getOperand(1));
7266 // If it's foldable, i.e. normal load with single use, we will let code
7267 // selection to fold it. Otherwise, we will short the conversion sequence.
7268 if (CIdx && CIdx->getZExtValue() == 0 &&
7269 (!ISD::isNormalLoad(V.getNode()) || !V.hasOneUse())) {
7270 MVT FullVT = V.getSimpleValueType();
7271 MVT V1VT = V1.getSimpleValueType();
7272 if (FullVT.getSizeInBits() > V1VT.getSizeInBits()) {
7273 // The "ext_vec_elt" node is wider than the result node.
7274 // In this case we should extract subvector from V.
7275 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast (extract_subvector x)).
7276 unsigned Ratio = FullVT.getSizeInBits() / V1VT.getSizeInBits();
7277 MVT SubVecVT = MVT::getVectorVT(FullVT.getVectorElementType(),
7278 FullVT.getVectorNumElements()/Ratio);
7279 V = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVecVT, V,
7280 DAG.getIntPtrConstant(0));
7282 V1 = DAG.getNode(ISD::BITCAST, DL, V1VT, V);
7286 return DAG.getNode(ISD::BITCAST, DL, VT,
7287 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
7291 NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
7292 SelectionDAG &DAG) {
7293 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7294 MVT VT = Op.getSimpleValueType();
7296 SDValue V1 = Op.getOperand(0);
7297 SDValue V2 = Op.getOperand(1);
7299 if (isZeroShuffle(SVOp))
7300 return getZeroVector(VT, Subtarget, DAG, dl);
7302 // Handle splat operations
7303 if (SVOp->isSplat()) {
7304 // Use vbroadcast whenever the splat comes from a foldable load
7305 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
7306 if (Broadcast.getNode())
7310 // Check integer expanding shuffles.
7311 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG);
7312 if (NewOp.getNode())
7315 // If the shuffle can be profitably rewritten as a narrower shuffle, then
7317 if (VT == MVT::v8i16 || VT == MVT::v16i8 ||
7318 VT == MVT::v16i16 || VT == MVT::v32i8) {
7319 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
7320 if (NewOp.getNode())
7321 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
7322 } else if ((VT == MVT::v4i32 ||
7323 (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
7324 // FIXME: Figure out a cleaner way to do this.
7325 // Try to make use of movq to zero out the top part.
7326 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
7327 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
7328 if (NewOp.getNode()) {
7329 MVT NewVT = NewOp.getSimpleValueType();
7330 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
7331 NewVT, true, false))
7332 return getVZextMovL(VT, NewVT, NewOp.getOperand(0),
7333 DAG, Subtarget, dl);
7335 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
7336 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
7337 if (NewOp.getNode()) {
7338 MVT NewVT = NewOp.getSimpleValueType();
7339 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
7340 return getVZextMovL(VT, NewVT, NewOp.getOperand(1),
7341 DAG, Subtarget, dl);
7349 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
7350 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7351 SDValue V1 = Op.getOperand(0);
7352 SDValue V2 = Op.getOperand(1);
7353 MVT VT = Op.getSimpleValueType();
7355 unsigned NumElems = VT.getVectorNumElements();
7356 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
7357 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
7358 bool V1IsSplat = false;
7359 bool V2IsSplat = false;
7360 bool HasSSE2 = Subtarget->hasSSE2();
7361 bool HasFp256 = Subtarget->hasFp256();
7362 bool HasInt256 = Subtarget->hasInt256();
7363 MachineFunction &MF = DAG.getMachineFunction();
7364 bool OptForSize = MF.getFunction()->getAttributes().
7365 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
7367 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
7369 if (V1IsUndef && V2IsUndef)
7370 return DAG.getUNDEF(VT);
7372 assert(!V1IsUndef && "Op 1 of shuffle should not be undef");
7374 // Vector shuffle lowering takes 3 steps:
7376 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
7377 // narrowing and commutation of operands should be handled.
7378 // 2) Matching of shuffles with known shuffle masks to x86 target specific
7380 // 3) Rewriting of unmatched masks into new generic shuffle operations,
7381 // so the shuffle can be broken into other shuffles and the legalizer can
7382 // try the lowering again.
7384 // The general idea is that no vector_shuffle operation should be left to
7385 // be matched during isel, all of them must be converted to a target specific
7388 // Normalize the input vectors. Here splats, zeroed vectors, profitable
7389 // narrowing and commutation of operands should be handled. The actual code
7390 // doesn't include all of those, work in progress...
7391 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
7392 if (NewOp.getNode())
7395 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
7397 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
7398 // unpckh_undef). Only use pshufd if speed is more important than size.
7399 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
7400 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
7401 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
7402 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
7404 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
7405 V2IsUndef && MayFoldVectorLoad(V1))
7406 return getMOVDDup(Op, dl, V1, DAG);
7408 if (isMOVHLPS_v_undef_Mask(M, VT))
7409 return getMOVHighToLow(Op, dl, DAG);
7411 // Use to match splats
7412 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
7413 (VT == MVT::v2f64 || VT == MVT::v2i64))
7414 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
7416 if (isPSHUFDMask(M, VT)) {
7417 // The actual implementation will match the mask in the if above and then
7418 // during isel it can match several different instructions, not only pshufd
7419 // as its name says, sad but true, emulate the behavior for now...
7420 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
7421 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
7423 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
7425 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
7426 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
7428 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
7429 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, TargetMask,
7432 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
7436 if (isPALIGNRMask(M, VT, Subtarget))
7437 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
7438 getShufflePALIGNRImmediate(SVOp),
7441 // Check if this can be converted into a logical shift.
7442 bool isLeft = false;
7445 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
7446 if (isShift && ShVal.hasOneUse()) {
7447 // If the shifted value has multiple uses, it may be cheaper to use
7448 // v_set0 + movlhps or movhlps, etc.
7449 MVT EltVT = VT.getVectorElementType();
7450 ShAmt *= EltVT.getSizeInBits();
7451 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
7454 if (isMOVLMask(M, VT)) {
7455 if (ISD::isBuildVectorAllZeros(V1.getNode()))
7456 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
7457 if (!isMOVLPMask(M, VT)) {
7458 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
7459 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
7461 if (VT == MVT::v4i32 || VT == MVT::v4f32)
7462 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
7466 // FIXME: fold these into legal mask.
7467 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
7468 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
7470 if (isMOVHLPSMask(M, VT))
7471 return getMOVHighToLow(Op, dl, DAG);
7473 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
7474 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
7476 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
7477 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
7479 if (isMOVLPMask(M, VT))
7480 return getMOVLP(Op, dl, DAG, HasSSE2);
7482 if (ShouldXformToMOVHLPS(M, VT) ||
7483 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
7484 return CommuteVectorShuffle(SVOp, DAG);
7487 // No better options. Use a vshldq / vsrldq.
7488 MVT EltVT = VT.getVectorElementType();
7489 ShAmt *= EltVT.getSizeInBits();
7490 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
7493 bool Commuted = false;
7494 // FIXME: This should also accept a bitcast of a splat? Be careful, not
7495 // 1,1,1,1 -> v8i16 though.
7496 V1IsSplat = isSplatVector(V1.getNode());
7497 V2IsSplat = isSplatVector(V2.getNode());
7499 // Canonicalize the splat or undef, if present, to be on the RHS.
7500 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
7501 CommuteVectorShuffleMask(M, NumElems);
7503 std::swap(V1IsSplat, V2IsSplat);
7507 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
7508 // Shuffling low element of v1 into undef, just return v1.
7511 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
7512 // the instruction selector will not match, so get a canonical MOVL with
7513 // swapped operands to undo the commute.
7514 return getMOVL(DAG, dl, VT, V2, V1);
7517 if (isUNPCKLMask(M, VT, HasInt256))
7518 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
7520 if (isUNPCKHMask(M, VT, HasInt256))
7521 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
7524 // Normalize mask so all entries that point to V2 points to its first
7525 // element then try to match unpck{h|l} again. If match, return a
7526 // new vector_shuffle with the corrected mask.p
7527 SmallVector<int, 8> NewMask(M.begin(), M.end());
7528 NormalizeMask(NewMask, NumElems);
7529 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
7530 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
7531 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
7532 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
7536 // Commute is back and try unpck* again.
7537 // FIXME: this seems wrong.
7538 CommuteVectorShuffleMask(M, NumElems);
7540 std::swap(V1IsSplat, V2IsSplat);
7543 if (isUNPCKLMask(M, VT, HasInt256))
7544 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
7546 if (isUNPCKHMask(M, VT, HasInt256))
7547 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
7550 // Normalize the node to match x86 shuffle ops if needed
7551 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
7552 return CommuteVectorShuffle(SVOp, DAG);
7554 // The checks below are all present in isShuffleMaskLegal, but they are
7555 // inlined here right now to enable us to directly emit target specific
7556 // nodes, and remove one by one until they don't return Op anymore.
7558 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
7559 SVOp->getSplatIndex() == 0 && V2IsUndef) {
7560 if (VT == MVT::v2f64 || VT == MVT::v2i64)
7561 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
7564 if (isPSHUFHWMask(M, VT, HasInt256))
7565 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
7566 getShufflePSHUFHWImmediate(SVOp),
7569 if (isPSHUFLWMask(M, VT, HasInt256))
7570 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
7571 getShufflePSHUFLWImmediate(SVOp),
7574 if (isSHUFPMask(M, VT))
7575 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
7576 getShuffleSHUFImmediate(SVOp), DAG);
7578 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
7579 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
7580 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
7581 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
7583 //===--------------------------------------------------------------------===//
7584 // Generate target specific nodes for 128 or 256-bit shuffles only
7585 // supported in the AVX instruction set.
7588 // Handle VMOVDDUPY permutations
7589 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
7590 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
7592 // Handle VPERMILPS/D* permutations
7593 if (isVPERMILPMask(M, VT)) {
7594 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
7595 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
7596 getShuffleSHUFImmediate(SVOp), DAG);
7597 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1,
7598 getShuffleSHUFImmediate(SVOp), DAG);
7601 // Handle VPERM2F128/VPERM2I128 permutations
7602 if (isVPERM2X128Mask(M, VT, HasFp256))
7603 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
7604 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
7606 SDValue BlendOp = LowerVECTOR_SHUFFLEtoBlend(SVOp, Subtarget, DAG);
7607 if (BlendOp.getNode())
7611 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
7612 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
7614 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
7615 VT.is512BitVector()) {
7616 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
7617 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
7618 SmallVector<SDValue, 16> permclMask;
7619 for (unsigned i = 0; i != NumElems; ++i) {
7620 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
7623 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT,
7624 &permclMask[0], NumElems);
7626 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
7627 return DAG.getNode(X86ISD::VPERMV, dl, VT,
7628 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
7629 return DAG.getNode(X86ISD::VPERMV3, dl, VT, V1,
7630 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V2);
7633 //===--------------------------------------------------------------------===//
7634 // Since no target specific shuffle was selected for this generic one,
7635 // lower it into other known shuffles. FIXME: this isn't true yet, but
7636 // this is the plan.
7639 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
7640 if (VT == MVT::v8i16) {
7641 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
7642 if (NewOp.getNode())
7646 if (VT == MVT::v16i8) {
7647 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
7648 if (NewOp.getNode())
7652 if (VT == MVT::v32i8) {
7653 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
7654 if (NewOp.getNode())
7658 // Handle all 128-bit wide vectors with 4 elements, and match them with
7659 // several different shuffle types.
7660 if (NumElems == 4 && VT.is128BitVector())
7661 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
7663 // Handle general 256-bit shuffles
7664 if (VT.is256BitVector())
7665 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
7670 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
7671 MVT VT = Op.getSimpleValueType();
7674 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
7677 if (VT.getSizeInBits() == 8) {
7678 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
7679 Op.getOperand(0), Op.getOperand(1));
7680 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
7681 DAG.getValueType(VT));
7682 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7685 if (VT.getSizeInBits() == 16) {
7686 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7687 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
7689 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
7690 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7691 DAG.getNode(ISD::BITCAST, dl,
7695 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
7696 Op.getOperand(0), Op.getOperand(1));
7697 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
7698 DAG.getValueType(VT));
7699 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7702 if (VT == MVT::f32) {
7703 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
7704 // the result back to FR32 register. It's only worth matching if the
7705 // result has a single use which is a store or a bitcast to i32. And in
7706 // the case of a store, it's not worth it if the index is a constant 0,
7707 // because a MOVSSmr can be used instead, which is smaller and faster.
7708 if (!Op.hasOneUse())
7710 SDNode *User = *Op.getNode()->use_begin();
7711 if ((User->getOpcode() != ISD::STORE ||
7712 (isa<ConstantSDNode>(Op.getOperand(1)) &&
7713 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
7714 (User->getOpcode() != ISD::BITCAST ||
7715 User->getValueType(0) != MVT::i32))
7717 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7718 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
7721 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
7724 if (VT == MVT::i32 || VT == MVT::i64) {
7725 // ExtractPS/pextrq works with constant index.
7726 if (isa<ConstantSDNode>(Op.getOperand(1)))
7732 /// Extract one bit from mask vector, like v16i1 or v8i1.
7733 /// AVX-512 feature.
7734 static SDValue ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) {
7735 SDValue Vec = Op.getOperand(0);
7737 MVT VecVT = Vec.getSimpleValueType();
7738 SDValue Idx = Op.getOperand(1);
7739 MVT EltVT = Op.getSimpleValueType();
7741 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
7743 // variable index can't be handled in mask registers,
7744 // extend vector to VR512
7745 if (!isa<ConstantSDNode>(Idx)) {
7746 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
7747 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
7748 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
7749 ExtVT.getVectorElementType(), Ext, Idx);
7750 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
7753 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7754 unsigned MaxSift = VecVT.getSizeInBits() - 1;
7755 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
7756 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
7757 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
7758 DAG.getConstant(MaxSift, MVT::i8));
7759 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
7760 DAG.getIntPtrConstant(0));
7764 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
7765 SelectionDAG &DAG) const {
7767 SDValue Vec = Op.getOperand(0);
7768 MVT VecVT = Vec.getSimpleValueType();
7769 SDValue Idx = Op.getOperand(1);
7771 if (Op.getSimpleValueType() == MVT::i1)
7772 return ExtractBitFromMaskVector(Op, DAG);
7774 if (!isa<ConstantSDNode>(Idx)) {
7775 if (VecVT.is512BitVector() ||
7776 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
7777 VecVT.getVectorElementType().getSizeInBits() == 32)) {
7780 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
7781 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
7782 MaskEltVT.getSizeInBits());
7784 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
7785 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
7786 getZeroVector(MaskVT, Subtarget, DAG, dl),
7787 Idx, DAG.getConstant(0, getPointerTy()));
7788 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
7789 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
7790 Perm, DAG.getConstant(0, getPointerTy()));
7795 // If this is a 256-bit vector result, first extract the 128-bit vector and
7796 // then extract the element from the 128-bit vector.
7797 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
7799 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7800 // Get the 128-bit vector.
7801 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
7802 MVT EltVT = VecVT.getVectorElementType();
7804 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
7806 //if (IdxVal >= NumElems/2)
7807 // IdxVal -= NumElems/2;
7808 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
7809 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
7810 DAG.getConstant(IdxVal, MVT::i32));
7813 assert(VecVT.is128BitVector() && "Unexpected vector length");
7815 if (Subtarget->hasSSE41()) {
7816 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
7821 MVT VT = Op.getSimpleValueType();
7822 // TODO: handle v16i8.
7823 if (VT.getSizeInBits() == 16) {
7824 SDValue Vec = Op.getOperand(0);
7825 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7827 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
7828 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7829 DAG.getNode(ISD::BITCAST, dl,
7832 // Transform it so it match pextrw which produces a 32-bit result.
7833 MVT EltVT = MVT::i32;
7834 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
7835 Op.getOperand(0), Op.getOperand(1));
7836 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
7837 DAG.getValueType(VT));
7838 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7841 if (VT.getSizeInBits() == 32) {
7842 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7846 // SHUFPS the element to the lowest double word, then movss.
7847 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
7848 MVT VVT = Op.getOperand(0).getSimpleValueType();
7849 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
7850 DAG.getUNDEF(VVT), Mask);
7851 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
7852 DAG.getIntPtrConstant(0));
7855 if (VT.getSizeInBits() == 64) {
7856 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
7857 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
7858 // to match extract_elt for f64.
7859 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7863 // UNPCKHPD the element to the lowest double word, then movsd.
7864 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
7865 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
7866 int Mask[2] = { 1, -1 };
7867 MVT VVT = Op.getOperand(0).getSimpleValueType();
7868 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
7869 DAG.getUNDEF(VVT), Mask);
7870 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
7871 DAG.getIntPtrConstant(0));
7877 static SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
7878 MVT VT = Op.getSimpleValueType();
7879 MVT EltVT = VT.getVectorElementType();
7882 SDValue N0 = Op.getOperand(0);
7883 SDValue N1 = Op.getOperand(1);
7884 SDValue N2 = Op.getOperand(2);
7886 if (!VT.is128BitVector())
7889 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
7890 isa<ConstantSDNode>(N2)) {
7892 if (VT == MVT::v8i16)
7893 Opc = X86ISD::PINSRW;
7894 else if (VT == MVT::v16i8)
7895 Opc = X86ISD::PINSRB;
7897 Opc = X86ISD::PINSRB;
7899 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
7901 if (N1.getValueType() != MVT::i32)
7902 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
7903 if (N2.getValueType() != MVT::i32)
7904 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
7905 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
7908 if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
7909 // Bits [7:6] of the constant are the source select. This will always be
7910 // zero here. The DAG Combiner may combine an extract_elt index into these
7911 // bits. For example (insert (extract, 3), 2) could be matched by putting
7912 // the '3' into bits [7:6] of X86ISD::INSERTPS.
7913 // Bits [5:4] of the constant are the destination select. This is the
7914 // value of the incoming immediate.
7915 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
7916 // combine either bitwise AND or insert of float 0.0 to set these bits.
7917 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
7918 // Create this as a scalar to vector..
7919 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
7920 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
7923 if ((EltVT == MVT::i32 || EltVT == MVT::i64) && isa<ConstantSDNode>(N2)) {
7924 // PINSR* works with constant index.
7931 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
7932 MVT VT = Op.getSimpleValueType();
7933 MVT EltVT = VT.getVectorElementType();
7936 SDValue N0 = Op.getOperand(0);
7937 SDValue N1 = Op.getOperand(1);
7938 SDValue N2 = Op.getOperand(2);
7940 // If this is a 256-bit vector result, first extract the 128-bit vector,
7941 // insert the element into the extracted half and then place it back.
7942 if (VT.is256BitVector() || VT.is512BitVector()) {
7943 if (!isa<ConstantSDNode>(N2))
7946 // Get the desired 128-bit vector half.
7947 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue();
7948 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
7950 // Insert the element into the desired half.
7951 unsigned NumEltsIn128 = 128/EltVT.getSizeInBits();
7952 unsigned IdxIn128 = IdxVal - (IdxVal/NumEltsIn128) * NumEltsIn128;
7954 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
7955 DAG.getConstant(IdxIn128, MVT::i32));
7957 // Insert the changed part back to the 256-bit vector
7958 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
7961 if (Subtarget->hasSSE41())
7962 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
7964 if (EltVT == MVT::i8)
7967 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
7968 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
7969 // as its second argument.
7970 if (N1.getValueType() != MVT::i32)
7971 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
7972 if (N2.getValueType() != MVT::i32)
7973 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
7974 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
7979 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
7981 MVT OpVT = Op.getSimpleValueType();
7983 // If this is a 256-bit vector result, first insert into a 128-bit
7984 // vector and then insert into the 256-bit vector.
7985 if (!OpVT.is128BitVector()) {
7986 // Insert into a 128-bit vector.
7987 unsigned SizeFactor = OpVT.getSizeInBits()/128;
7988 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
7989 OpVT.getVectorNumElements() / SizeFactor);
7991 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
7993 // Insert the 128-bit vector.
7994 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
7997 if (OpVT == MVT::v1i64 &&
7998 Op.getOperand(0).getValueType() == MVT::i64)
7999 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
8001 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
8002 assert(OpVT.is128BitVector() && "Expected an SSE type!");
8003 return DAG.getNode(ISD::BITCAST, dl, OpVT,
8004 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
8007 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
8008 // a simple subregister reference or explicit instructions to grab
8009 // upper bits of a vector.
8010 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
8011 SelectionDAG &DAG) {
8013 SDValue In = Op.getOperand(0);
8014 SDValue Idx = Op.getOperand(1);
8015 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
8016 MVT ResVT = Op.getSimpleValueType();
8017 MVT InVT = In.getSimpleValueType();
8019 if (Subtarget->hasFp256()) {
8020 if (ResVT.is128BitVector() &&
8021 (InVT.is256BitVector() || InVT.is512BitVector()) &&
8022 isa<ConstantSDNode>(Idx)) {
8023 return Extract128BitVector(In, IdxVal, DAG, dl);
8025 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
8026 isa<ConstantSDNode>(Idx)) {
8027 return Extract256BitVector(In, IdxVal, DAG, dl);
8033 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
8034 // simple superregister reference or explicit instructions to insert
8035 // the upper bits of a vector.
8036 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
8037 SelectionDAG &DAG) {
8038 if (Subtarget->hasFp256()) {
8039 SDLoc dl(Op.getNode());
8040 SDValue Vec = Op.getNode()->getOperand(0);
8041 SDValue SubVec = Op.getNode()->getOperand(1);
8042 SDValue Idx = Op.getNode()->getOperand(2);
8044 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() ||
8045 Op.getNode()->getSimpleValueType(0).is512BitVector()) &&
8046 SubVec.getNode()->getSimpleValueType(0).is128BitVector() &&
8047 isa<ConstantSDNode>(Idx)) {
8048 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
8049 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
8052 if (Op.getNode()->getSimpleValueType(0).is512BitVector() &&
8053 SubVec.getNode()->getSimpleValueType(0).is256BitVector() &&
8054 isa<ConstantSDNode>(Idx)) {
8055 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
8056 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
8062 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
8063 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
8064 // one of the above mentioned nodes. It has to be wrapped because otherwise
8065 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
8066 // be used to form addressing mode. These wrapped nodes will be selected
8069 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
8070 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
8072 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
8074 unsigned char OpFlag = 0;
8075 unsigned WrapperKind = X86ISD::Wrapper;
8076 CodeModel::Model M = getTargetMachine().getCodeModel();
8078 if (Subtarget->isPICStyleRIPRel() &&
8079 (M == CodeModel::Small || M == CodeModel::Kernel))
8080 WrapperKind = X86ISD::WrapperRIP;
8081 else if (Subtarget->isPICStyleGOT())
8082 OpFlag = X86II::MO_GOTOFF;
8083 else if (Subtarget->isPICStyleStubPIC())
8084 OpFlag = X86II::MO_PIC_BASE_OFFSET;
8086 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
8088 CP->getOffset(), OpFlag);
8090 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
8091 // With PIC, the address is actually $g + Offset.
8093 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8094 DAG.getNode(X86ISD::GlobalBaseReg,
8095 SDLoc(), getPointerTy()),
8102 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
8103 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
8105 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
8107 unsigned char OpFlag = 0;
8108 unsigned WrapperKind = X86ISD::Wrapper;
8109 CodeModel::Model M = getTargetMachine().getCodeModel();
8111 if (Subtarget->isPICStyleRIPRel() &&
8112 (M == CodeModel::Small || M == CodeModel::Kernel))
8113 WrapperKind = X86ISD::WrapperRIP;
8114 else if (Subtarget->isPICStyleGOT())
8115 OpFlag = X86II::MO_GOTOFF;
8116 else if (Subtarget->isPICStyleStubPIC())
8117 OpFlag = X86II::MO_PIC_BASE_OFFSET;
8119 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
8122 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
8124 // With PIC, the address is actually $g + Offset.
8126 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8127 DAG.getNode(X86ISD::GlobalBaseReg,
8128 SDLoc(), getPointerTy()),
8135 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
8136 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
8138 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
8140 unsigned char OpFlag = 0;
8141 unsigned WrapperKind = X86ISD::Wrapper;
8142 CodeModel::Model M = getTargetMachine().getCodeModel();
8144 if (Subtarget->isPICStyleRIPRel() &&
8145 (M == CodeModel::Small || M == CodeModel::Kernel)) {
8146 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
8147 OpFlag = X86II::MO_GOTPCREL;
8148 WrapperKind = X86ISD::WrapperRIP;
8149 } else if (Subtarget->isPICStyleGOT()) {
8150 OpFlag = X86II::MO_GOT;
8151 } else if (Subtarget->isPICStyleStubPIC()) {
8152 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
8153 } else if (Subtarget->isPICStyleStubNoDynamic()) {
8154 OpFlag = X86II::MO_DARWIN_NONLAZY;
8157 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
8160 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
8162 // With PIC, the address is actually $g + Offset.
8163 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
8164 !Subtarget->is64Bit()) {
8165 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8166 DAG.getNode(X86ISD::GlobalBaseReg,
8167 SDLoc(), getPointerTy()),
8171 // For symbols that require a load from a stub to get the address, emit the
8173 if (isGlobalStubReference(OpFlag))
8174 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
8175 MachinePointerInfo::getGOT(), false, false, false, 0);
8181 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
8182 // Create the TargetBlockAddressAddress node.
8183 unsigned char OpFlags =
8184 Subtarget->ClassifyBlockAddressReference();
8185 CodeModel::Model M = getTargetMachine().getCodeModel();
8186 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
8187 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
8189 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
8192 if (Subtarget->isPICStyleRIPRel() &&
8193 (M == CodeModel::Small || M == CodeModel::Kernel))
8194 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
8196 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
8198 // With PIC, the address is actually $g + Offset.
8199 if (isGlobalRelativeToPICBase(OpFlags)) {
8200 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
8201 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
8209 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
8210 int64_t Offset, SelectionDAG &DAG) const {
8211 // Create the TargetGlobalAddress node, folding in the constant
8212 // offset if it is legal.
8213 unsigned char OpFlags =
8214 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
8215 CodeModel::Model M = getTargetMachine().getCodeModel();
8217 if (OpFlags == X86II::MO_NO_FLAG &&
8218 X86::isOffsetSuitableForCodeModel(Offset, M)) {
8219 // A direct static reference to a global.
8220 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
8223 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
8226 if (Subtarget->isPICStyleRIPRel() &&
8227 (M == CodeModel::Small || M == CodeModel::Kernel))
8228 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
8230 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
8232 // With PIC, the address is actually $g + Offset.
8233 if (isGlobalRelativeToPICBase(OpFlags)) {
8234 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
8235 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
8239 // For globals that require a load from a stub to get the address, emit the
8241 if (isGlobalStubReference(OpFlags))
8242 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
8243 MachinePointerInfo::getGOT(), false, false, false, 0);
8245 // If there was a non-zero offset that we didn't fold, create an explicit
8248 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
8249 DAG.getConstant(Offset, getPointerTy()));
8255 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
8256 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
8257 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
8258 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
8262 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
8263 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
8264 unsigned char OperandFlags, bool LocalDynamic = false) {
8265 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
8266 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
8268 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
8269 GA->getValueType(0),
8273 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
8277 SDValue Ops[] = { Chain, TGA, *InFlag };
8278 Chain = DAG.getNode(CallType, dl, NodeTys, Ops, array_lengthof(Ops));
8280 SDValue Ops[] = { Chain, TGA };
8281 Chain = DAG.getNode(CallType, dl, NodeTys, Ops, array_lengthof(Ops));
8284 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
8285 MFI->setAdjustsStack(true);
8287 SDValue Flag = Chain.getValue(1);
8288 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
8291 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
8293 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
8296 SDLoc dl(GA); // ? function entry point might be better
8297 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
8298 DAG.getNode(X86ISD::GlobalBaseReg,
8299 SDLoc(), PtrVT), InFlag);
8300 InFlag = Chain.getValue(1);
8302 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
8305 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
8307 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
8309 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
8310 X86::RAX, X86II::MO_TLSGD);
8313 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
8319 // Get the start address of the TLS block for this module.
8320 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
8321 .getInfo<X86MachineFunctionInfo>();
8322 MFI->incNumLocalDynamicTLSAccesses();
8326 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT, X86::RAX,
8327 X86II::MO_TLSLD, /*LocalDynamic=*/true);
8330 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
8331 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
8332 InFlag = Chain.getValue(1);
8333 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
8334 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
8337 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
8341 unsigned char OperandFlags = X86II::MO_DTPOFF;
8342 unsigned WrapperKind = X86ISD::Wrapper;
8343 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
8344 GA->getValueType(0),
8345 GA->getOffset(), OperandFlags);
8346 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
8348 // Add x@dtpoff with the base.
8349 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
8352 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
8353 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
8354 const EVT PtrVT, TLSModel::Model model,
8355 bool is64Bit, bool isPIC) {
8358 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
8359 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
8360 is64Bit ? 257 : 256));
8362 SDValue ThreadPointer =
8363 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
8364 MachinePointerInfo(Ptr), false, false, false, 0);
8366 unsigned char OperandFlags = 0;
8367 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
8369 unsigned WrapperKind = X86ISD::Wrapper;
8370 if (model == TLSModel::LocalExec) {
8371 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
8372 } else if (model == TLSModel::InitialExec) {
8374 OperandFlags = X86II::MO_GOTTPOFF;
8375 WrapperKind = X86ISD::WrapperRIP;
8377 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
8380 llvm_unreachable("Unexpected model");
8383 // emit "addl x@ntpoff,%eax" (local exec)
8384 // or "addl x@indntpoff,%eax" (initial exec)
8385 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
8387 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
8388 GA->getOffset(), OperandFlags);
8389 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
8391 if (model == TLSModel::InitialExec) {
8392 if (isPIC && !is64Bit) {
8393 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
8394 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
8398 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
8399 MachinePointerInfo::getGOT(), false, false, false, 0);
8402 // The address of the thread local variable is the add of the thread
8403 // pointer with the offset of the variable.
8404 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
8408 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
8410 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
8411 const GlobalValue *GV = GA->getGlobal();
8413 if (Subtarget->isTargetELF()) {
8414 TLSModel::Model model = getTargetMachine().getTLSModel(GV);
8417 case TLSModel::GeneralDynamic:
8418 if (Subtarget->is64Bit())
8419 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
8420 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
8421 case TLSModel::LocalDynamic:
8422 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
8423 Subtarget->is64Bit());
8424 case TLSModel::InitialExec:
8425 case TLSModel::LocalExec:
8426 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
8427 Subtarget->is64Bit(),
8428 getTargetMachine().getRelocationModel() == Reloc::PIC_);
8430 llvm_unreachable("Unknown TLS model.");
8433 if (Subtarget->isTargetDarwin()) {
8434 // Darwin only has one model of TLS. Lower to that.
8435 unsigned char OpFlag = 0;
8436 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
8437 X86ISD::WrapperRIP : X86ISD::Wrapper;
8439 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
8441 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
8442 !Subtarget->is64Bit();
8444 OpFlag = X86II::MO_TLVP_PIC_BASE;
8446 OpFlag = X86II::MO_TLVP;
8448 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
8449 GA->getValueType(0),
8450 GA->getOffset(), OpFlag);
8451 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
8453 // With PIC32, the address is actually $g + Offset.
8455 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8456 DAG.getNode(X86ISD::GlobalBaseReg,
8457 SDLoc(), getPointerTy()),
8460 // Lowering the machine isd will make sure everything is in the right
8462 SDValue Chain = DAG.getEntryNode();
8463 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
8464 SDValue Args[] = { Chain, Offset };
8465 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2);
8467 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
8468 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
8469 MFI->setAdjustsStack(true);
8471 // And our return value (tls address) is in the standard call return value
8473 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
8474 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
8478 if (Subtarget->isTargetWindows() || Subtarget->isTargetMingw()) {
8479 // Just use the implicit TLS architecture
8480 // Need to generate someting similar to:
8481 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
8483 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
8484 // mov rcx, qword [rdx+rcx*8]
8485 // mov eax, .tls$:tlsvar
8486 // [rax+rcx] contains the address
8487 // Windows 64bit: gs:0x58
8488 // Windows 32bit: fs:__tls_array
8490 // If GV is an alias then use the aliasee for determining
8491 // thread-localness.
8492 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
8493 GV = GA->resolveAliasedGlobal(false);
8495 SDValue Chain = DAG.getEntryNode();
8497 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
8498 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
8499 // use its literal value of 0x2C.
8500 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
8501 ? Type::getInt8PtrTy(*DAG.getContext(),
8503 : Type::getInt32PtrTy(*DAG.getContext(),
8506 SDValue TlsArray = Subtarget->is64Bit() ? DAG.getIntPtrConstant(0x58) :
8507 (Subtarget->isTargetMingw() ? DAG.getIntPtrConstant(0x2C) :
8508 DAG.getExternalSymbol("_tls_array", getPointerTy()));
8510 SDValue ThreadPointer = DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
8511 MachinePointerInfo(Ptr),
8512 false, false, false, 0);
8514 // Load the _tls_index variable
8515 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
8516 if (Subtarget->is64Bit())
8517 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
8518 IDX, MachinePointerInfo(), MVT::i32,
8521 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
8522 false, false, false, 0);
8524 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
8526 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
8528 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
8529 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
8530 false, false, false, 0);
8532 // Get the offset of start of .tls section
8533 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
8534 GA->getValueType(0),
8535 GA->getOffset(), X86II::MO_SECREL);
8536 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
8538 // The address of the thread local variable is the add of the thread
8539 // pointer with the offset of the variable.
8540 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
8543 llvm_unreachable("TLS not implemented for this target.");
8546 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
8547 /// and take a 2 x i32 value to shift plus a shift amount.
8548 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
8549 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
8550 MVT VT = Op.getSimpleValueType();
8551 unsigned VTBits = VT.getSizeInBits();
8553 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
8554 SDValue ShOpLo = Op.getOperand(0);
8555 SDValue ShOpHi = Op.getOperand(1);
8556 SDValue ShAmt = Op.getOperand(2);
8557 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
8558 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
8560 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
8561 DAG.getConstant(VTBits - 1, MVT::i8));
8562 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
8563 DAG.getConstant(VTBits - 1, MVT::i8))
8564 : DAG.getConstant(0, VT);
8567 if (Op.getOpcode() == ISD::SHL_PARTS) {
8568 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
8569 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
8571 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
8572 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
8575 // If the shift amount is larger or equal than the width of a part we can't
8576 // rely on the results of shld/shrd. Insert a test and select the appropriate
8577 // values for large shift amounts.
8578 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
8579 DAG.getConstant(VTBits, MVT::i8));
8580 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
8581 AndNode, DAG.getConstant(0, MVT::i8));
8584 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8585 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
8586 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
8588 if (Op.getOpcode() == ISD::SHL_PARTS) {
8589 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
8590 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
8592 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
8593 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
8596 SDValue Ops[2] = { Lo, Hi };
8597 return DAG.getMergeValues(Ops, array_lengthof(Ops), dl);
8600 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
8601 SelectionDAG &DAG) const {
8602 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
8604 if (SrcVT.isVector())
8607 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
8608 "Unknown SINT_TO_FP to lower!");
8610 // These are really Legal; return the operand so the caller accepts it as
8612 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
8614 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
8615 Subtarget->is64Bit()) {
8620 unsigned Size = SrcVT.getSizeInBits()/8;
8621 MachineFunction &MF = DAG.getMachineFunction();
8622 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
8623 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8624 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
8626 MachinePointerInfo::getFixedStack(SSFI),
8628 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
8631 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
8633 SelectionDAG &DAG) const {
8637 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
8639 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
8641 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
8643 unsigned ByteSize = SrcVT.getSizeInBits()/8;
8645 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
8646 MachineMemOperand *MMO;
8648 int SSFI = FI->getIndex();
8650 DAG.getMachineFunction()
8651 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8652 MachineMemOperand::MOLoad, ByteSize, ByteSize);
8654 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
8655 StackSlot = StackSlot.getOperand(1);
8657 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
8658 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
8660 Tys, Ops, array_lengthof(Ops),
8664 Chain = Result.getValue(1);
8665 SDValue InFlag = Result.getValue(2);
8667 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
8668 // shouldn't be necessary except that RFP cannot be live across
8669 // multiple blocks. When stackifier is fixed, they can be uncoupled.
8670 MachineFunction &MF = DAG.getMachineFunction();
8671 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
8672 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
8673 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8674 Tys = DAG.getVTList(MVT::Other);
8676 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
8678 MachineMemOperand *MMO =
8679 DAG.getMachineFunction()
8680 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8681 MachineMemOperand::MOStore, SSFISize, SSFISize);
8683 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
8684 Ops, array_lengthof(Ops),
8685 Op.getValueType(), MMO);
8686 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
8687 MachinePointerInfo::getFixedStack(SSFI),
8688 false, false, false, 0);
8694 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
8695 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
8696 SelectionDAG &DAG) const {
8697 // This algorithm is not obvious. Here it is what we're trying to output:
8700 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
8701 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
8705 pshufd $0x4e, %xmm0, %xmm1
8711 LLVMContext *Context = DAG.getContext();
8713 // Build some magic constants.
8714 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
8715 Constant *C0 = ConstantDataVector::get(*Context, CV0);
8716 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
8718 SmallVector<Constant*,2> CV1;
8720 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
8721 APInt(64, 0x4330000000000000ULL))));
8723 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
8724 APInt(64, 0x4530000000000000ULL))));
8725 Constant *C1 = ConstantVector::get(CV1);
8726 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
8728 // Load the 64-bit value into an XMM register.
8729 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
8731 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
8732 MachinePointerInfo::getConstantPool(),
8733 false, false, false, 16);
8734 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
8735 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
8738 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
8739 MachinePointerInfo::getConstantPool(),
8740 false, false, false, 16);
8741 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
8742 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
8745 if (Subtarget->hasSSE3()) {
8746 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
8747 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
8749 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
8750 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
8752 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
8753 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
8757 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
8758 DAG.getIntPtrConstant(0));
8761 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
8762 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
8763 SelectionDAG &DAG) const {
8765 // FP constant to bias correct the final result.
8766 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
8769 // Load the 32-bit value into an XMM register.
8770 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
8773 // Zero out the upper parts of the register.
8774 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
8776 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
8777 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
8778 DAG.getIntPtrConstant(0));
8780 // Or the load with the bias.
8781 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
8782 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
8783 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
8785 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
8786 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
8787 MVT::v2f64, Bias)));
8788 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
8789 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
8790 DAG.getIntPtrConstant(0));
8792 // Subtract the bias.
8793 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
8795 // Handle final rounding.
8796 EVT DestVT = Op.getValueType();
8798 if (DestVT.bitsLT(MVT::f64))
8799 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
8800 DAG.getIntPtrConstant(0));
8801 if (DestVT.bitsGT(MVT::f64))
8802 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
8804 // Handle final rounding.
8808 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
8809 SelectionDAG &DAG) const {
8810 SDValue N0 = Op.getOperand(0);
8811 MVT SVT = N0.getSimpleValueType();
8814 assert((SVT == MVT::v4i8 || SVT == MVT::v4i16 ||
8815 SVT == MVT::v8i8 || SVT == MVT::v8i16) &&
8816 "Custom UINT_TO_FP is not supported!");
8818 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
8819 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
8820 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
8823 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
8824 SelectionDAG &DAG) const {
8825 SDValue N0 = Op.getOperand(0);
8828 if (Op.getValueType().isVector())
8829 return lowerUINT_TO_FP_vec(Op, DAG);
8831 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
8832 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
8833 // the optimization here.
8834 if (DAG.SignBitIsZero(N0))
8835 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
8837 MVT SrcVT = N0.getSimpleValueType();
8838 MVT DstVT = Op.getSimpleValueType();
8839 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
8840 return LowerUINT_TO_FP_i64(Op, DAG);
8841 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
8842 return LowerUINT_TO_FP_i32(Op, DAG);
8843 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
8846 // Make a 64-bit buffer, and use it to build an FILD.
8847 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
8848 if (SrcVT == MVT::i32) {
8849 SDValue WordOff = DAG.getConstant(4, getPointerTy());
8850 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
8851 getPointerTy(), StackSlot, WordOff);
8852 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
8853 StackSlot, MachinePointerInfo(),
8855 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
8856 OffsetSlot, MachinePointerInfo(),
8858 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
8862 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
8863 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
8864 StackSlot, MachinePointerInfo(),
8866 // For i64 source, we need to add the appropriate power of 2 if the input
8867 // was negative. This is the same as the optimization in
8868 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
8869 // we must be careful to do the computation in x87 extended precision, not
8870 // in SSE. (The generic code can't know it's OK to do this, or how to.)
8871 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
8872 MachineMemOperand *MMO =
8873 DAG.getMachineFunction()
8874 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8875 MachineMemOperand::MOLoad, 8, 8);
8877 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
8878 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
8879 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
8880 array_lengthof(Ops), MVT::i64, MMO);
8882 APInt FF(32, 0x5F800000ULL);
8884 // Check whether the sign bit is set.
8885 SDValue SignSet = DAG.getSetCC(dl,
8886 getSetCCResultType(*DAG.getContext(), MVT::i64),
8887 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
8890 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
8891 SDValue FudgePtr = DAG.getConstantPool(
8892 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
8895 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
8896 SDValue Zero = DAG.getIntPtrConstant(0);
8897 SDValue Four = DAG.getIntPtrConstant(4);
8898 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
8900 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
8902 // Load the value out, extending it from f32 to f80.
8903 // FIXME: Avoid the extend by constructing the right constant pool?
8904 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
8905 FudgePtr, MachinePointerInfo::getConstantPool(),
8906 MVT::f32, false, false, 4);
8907 // Extend everything to 80 bits to force it to be done on x87.
8908 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
8909 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
8912 std::pair<SDValue,SDValue>
8913 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
8914 bool IsSigned, bool IsReplace) const {
8917 EVT DstTy = Op.getValueType();
8919 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
8920 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
8924 assert(DstTy.getSimpleVT() <= MVT::i64 &&
8925 DstTy.getSimpleVT() >= MVT::i16 &&
8926 "Unknown FP_TO_INT to lower!");
8928 // These are really Legal.
8929 if (DstTy == MVT::i32 &&
8930 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
8931 return std::make_pair(SDValue(), SDValue());
8932 if (Subtarget->is64Bit() &&
8933 DstTy == MVT::i64 &&
8934 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
8935 return std::make_pair(SDValue(), SDValue());
8937 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
8938 // stack slot, or into the FTOL runtime function.
8939 MachineFunction &MF = DAG.getMachineFunction();
8940 unsigned MemSize = DstTy.getSizeInBits()/8;
8941 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
8942 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8945 if (!IsSigned && isIntegerTypeFTOL(DstTy))
8946 Opc = X86ISD::WIN_FTOL;
8948 switch (DstTy.getSimpleVT().SimpleTy) {
8949 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
8950 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
8951 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
8952 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
8955 SDValue Chain = DAG.getEntryNode();
8956 SDValue Value = Op.getOperand(0);
8957 EVT TheVT = Op.getOperand(0).getValueType();
8958 // FIXME This causes a redundant load/store if the SSE-class value is already
8959 // in memory, such as if it is on the callstack.
8960 if (isScalarFPTypeInSSEReg(TheVT)) {
8961 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
8962 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
8963 MachinePointerInfo::getFixedStack(SSFI),
8965 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
8967 Chain, StackSlot, DAG.getValueType(TheVT)
8970 MachineMemOperand *MMO =
8971 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8972 MachineMemOperand::MOLoad, MemSize, MemSize);
8973 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops,
8974 array_lengthof(Ops), DstTy, MMO);
8975 Chain = Value.getValue(1);
8976 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
8977 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8980 MachineMemOperand *MMO =
8981 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8982 MachineMemOperand::MOStore, MemSize, MemSize);
8984 if (Opc != X86ISD::WIN_FTOL) {
8985 // Build the FP_TO_INT*_IN_MEM
8986 SDValue Ops[] = { Chain, Value, StackSlot };
8987 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
8988 Ops, array_lengthof(Ops), DstTy,
8990 return std::make_pair(FIST, StackSlot);
8992 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
8993 DAG.getVTList(MVT::Other, MVT::Glue),
8995 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
8996 MVT::i32, ftol.getValue(1));
8997 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
8998 MVT::i32, eax.getValue(2));
8999 SDValue Ops[] = { eax, edx };
9000 SDValue pair = IsReplace
9001 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops, array_lengthof(Ops))
9002 : DAG.getMergeValues(Ops, array_lengthof(Ops), DL);
9003 return std::make_pair(pair, SDValue());
9007 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
9008 const X86Subtarget *Subtarget) {
9009 MVT VT = Op->getSimpleValueType(0);
9010 SDValue In = Op->getOperand(0);
9011 MVT InVT = In.getSimpleValueType();
9014 // Optimize vectors in AVX mode:
9017 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
9018 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
9019 // Concat upper and lower parts.
9022 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
9023 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
9024 // Concat upper and lower parts.
9027 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
9028 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
9029 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
9032 if (Subtarget->hasInt256())
9033 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
9035 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
9036 SDValue Undef = DAG.getUNDEF(InVT);
9037 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
9038 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
9039 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
9041 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
9042 VT.getVectorNumElements()/2);
9044 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
9045 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
9047 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
9050 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
9051 SelectionDAG &DAG) {
9052 MVT VT = Op->getSimpleValueType(0);
9053 SDValue In = Op->getOperand(0);
9054 MVT InVT = In.getSimpleValueType();
9056 unsigned int NumElts = VT.getVectorNumElements();
9057 if (NumElts != 8 && NumElts != 16)
9060 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
9061 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
9063 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
9064 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9065 // Now we have only mask extension
9066 assert(InVT.getVectorElementType() == MVT::i1);
9067 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
9068 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
9069 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
9070 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
9071 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
9072 MachinePointerInfo::getConstantPool(),
9073 false, false, false, Alignment);
9075 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
9076 if (VT.is512BitVector())
9078 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
9081 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
9082 SelectionDAG &DAG) {
9083 if (Subtarget->hasFp256()) {
9084 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
9092 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
9093 SelectionDAG &DAG) {
9095 MVT VT = Op.getSimpleValueType();
9096 SDValue In = Op.getOperand(0);
9097 MVT SVT = In.getSimpleValueType();
9099 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
9100 return LowerZERO_EXTEND_AVX512(Op, DAG);
9102 if (Subtarget->hasFp256()) {
9103 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
9108 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
9109 VT.getVectorNumElements() != SVT.getVectorNumElements());
9113 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
9115 MVT VT = Op.getSimpleValueType();
9116 SDValue In = Op.getOperand(0);
9117 MVT InVT = In.getSimpleValueType();
9119 if (VT == MVT::i1) {
9120 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
9121 "Invalid scalar TRUNCATE operation");
9122 if (InVT == MVT::i32)
9124 if (InVT.getSizeInBits() == 64)
9125 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::i32, In);
9126 else if (InVT.getSizeInBits() < 32)
9127 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
9128 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
9130 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
9131 "Invalid TRUNCATE operation");
9133 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
9134 if (VT.getVectorElementType().getSizeInBits() >=8)
9135 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
9137 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
9138 unsigned NumElts = InVT.getVectorNumElements();
9139 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
9140 if (InVT.getSizeInBits() < 512) {
9141 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
9142 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
9146 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
9147 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
9148 SDValue CP = DAG.getConstantPool(C, getPointerTy());
9149 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
9150 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
9151 MachinePointerInfo::getConstantPool(),
9152 false, false, false, Alignment);
9153 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
9154 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
9155 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
9158 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
9159 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
9160 if (Subtarget->hasInt256()) {
9161 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
9162 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
9163 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
9165 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
9166 DAG.getIntPtrConstant(0));
9169 // On AVX, v4i64 -> v4i32 becomes a sequence that uses PSHUFD and MOVLHPS.
9170 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
9171 DAG.getIntPtrConstant(0));
9172 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
9173 DAG.getIntPtrConstant(2));
9175 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
9176 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
9179 static const int ShufMask1[] = {0, 2, 0, 0};
9180 SDValue Undef = DAG.getUNDEF(VT);
9181 OpLo = DAG.getVectorShuffle(VT, DL, OpLo, Undef, ShufMask1);
9182 OpHi = DAG.getVectorShuffle(VT, DL, OpHi, Undef, ShufMask1);
9184 // The MOVLHPS mask:
9185 static const int ShufMask2[] = {0, 1, 4, 5};
9186 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask2);
9189 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
9190 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
9191 if (Subtarget->hasInt256()) {
9192 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
9194 SmallVector<SDValue,32> pshufbMask;
9195 for (unsigned i = 0; i < 2; ++i) {
9196 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
9197 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
9198 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
9199 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
9200 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
9201 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
9202 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
9203 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
9204 for (unsigned j = 0; j < 8; ++j)
9205 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
9207 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8,
9208 &pshufbMask[0], 32);
9209 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
9210 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
9212 static const int ShufMask[] = {0, 2, -1, -1};
9213 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
9215 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
9216 DAG.getIntPtrConstant(0));
9217 return DAG.getNode(ISD::BITCAST, DL, VT, In);
9220 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
9221 DAG.getIntPtrConstant(0));
9223 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
9224 DAG.getIntPtrConstant(4));
9226 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
9227 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
9230 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
9231 -1, -1, -1, -1, -1, -1, -1, -1};
9233 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
9234 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
9235 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
9237 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
9238 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
9240 // The MOVLHPS Mask:
9241 static const int ShufMask2[] = {0, 1, 4, 5};
9242 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
9243 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
9246 // Handle truncation of V256 to V128 using shuffles.
9247 if (!VT.is128BitVector() || !InVT.is256BitVector())
9250 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
9252 unsigned NumElems = VT.getVectorNumElements();
9253 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
9255 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
9256 // Prepare truncation shuffle mask
9257 for (unsigned i = 0; i != NumElems; ++i)
9259 SDValue V = DAG.getVectorShuffle(NVT, DL,
9260 DAG.getNode(ISD::BITCAST, DL, NVT, In),
9261 DAG.getUNDEF(NVT), &MaskVec[0]);
9262 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
9263 DAG.getIntPtrConstant(0));
9266 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
9267 SelectionDAG &DAG) const {
9268 MVT VT = Op.getSimpleValueType();
9269 if (VT.isVector()) {
9270 if (VT == MVT::v8i16)
9271 return DAG.getNode(ISD::TRUNCATE, SDLoc(Op), VT,
9272 DAG.getNode(ISD::FP_TO_SINT, SDLoc(Op),
9273 MVT::v8i32, Op.getOperand(0)));
9277 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
9278 /*IsSigned=*/ true, /*IsReplace=*/ false);
9279 SDValue FIST = Vals.first, StackSlot = Vals.second;
9280 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
9281 if (FIST.getNode() == 0) return Op;
9283 if (StackSlot.getNode())
9285 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
9286 FIST, StackSlot, MachinePointerInfo(),
9287 false, false, false, 0);
9289 // The node is the result.
9293 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
9294 SelectionDAG &DAG) const {
9295 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
9296 /*IsSigned=*/ false, /*IsReplace=*/ false);
9297 SDValue FIST = Vals.first, StackSlot = Vals.second;
9298 assert(FIST.getNode() && "Unexpected failure");
9300 if (StackSlot.getNode())
9302 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
9303 FIST, StackSlot, MachinePointerInfo(),
9304 false, false, false, 0);
9306 // The node is the result.
9310 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
9312 MVT VT = Op.getSimpleValueType();
9313 SDValue In = Op.getOperand(0);
9314 MVT SVT = In.getSimpleValueType();
9316 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
9318 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
9319 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
9320 In, DAG.getUNDEF(SVT)));
9323 static SDValue LowerFABS(SDValue Op, SelectionDAG &DAG) {
9324 LLVMContext *Context = DAG.getContext();
9326 MVT VT = Op.getSimpleValueType();
9328 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
9329 if (VT.isVector()) {
9330 EltVT = VT.getVectorElementType();
9331 NumElts = VT.getVectorNumElements();
9334 if (EltVT == MVT::f64)
9335 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
9336 APInt(64, ~(1ULL << 63))));
9338 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEsingle,
9339 APInt(32, ~(1U << 31))));
9340 C = ConstantVector::getSplat(NumElts, C);
9341 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9342 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
9343 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
9344 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9345 MachinePointerInfo::getConstantPool(),
9346 false, false, false, Alignment);
9347 if (VT.isVector()) {
9348 MVT ANDVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
9349 return DAG.getNode(ISD::BITCAST, dl, VT,
9350 DAG.getNode(ISD::AND, dl, ANDVT,
9351 DAG.getNode(ISD::BITCAST, dl, ANDVT,
9353 DAG.getNode(ISD::BITCAST, dl, ANDVT, Mask)));
9355 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
9358 static SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG) {
9359 LLVMContext *Context = DAG.getContext();
9361 MVT VT = Op.getSimpleValueType();
9363 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
9364 if (VT.isVector()) {
9365 EltVT = VT.getVectorElementType();
9366 NumElts = VT.getVectorNumElements();
9369 if (EltVT == MVT::f64)
9370 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
9371 APInt(64, 1ULL << 63)));
9373 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEsingle,
9374 APInt(32, 1U << 31)));
9375 C = ConstantVector::getSplat(NumElts, C);
9376 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9377 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
9378 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
9379 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9380 MachinePointerInfo::getConstantPool(),
9381 false, false, false, Alignment);
9382 if (VT.isVector()) {
9383 MVT XORVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits()/64);
9384 return DAG.getNode(ISD::BITCAST, dl, VT,
9385 DAG.getNode(ISD::XOR, dl, XORVT,
9386 DAG.getNode(ISD::BITCAST, dl, XORVT,
9388 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask)));
9391 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
9394 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
9395 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9396 LLVMContext *Context = DAG.getContext();
9397 SDValue Op0 = Op.getOperand(0);
9398 SDValue Op1 = Op.getOperand(1);
9400 MVT VT = Op.getSimpleValueType();
9401 MVT SrcVT = Op1.getSimpleValueType();
9403 // If second operand is smaller, extend it first.
9404 if (SrcVT.bitsLT(VT)) {
9405 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
9408 // And if it is bigger, shrink it first.
9409 if (SrcVT.bitsGT(VT)) {
9410 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
9414 // At this point the operands and the result should have the same
9415 // type, and that won't be f80 since that is not custom lowered.
9417 // First get the sign bit of second operand.
9418 SmallVector<Constant*,4> CV;
9419 if (SrcVT == MVT::f64) {
9420 const fltSemantics &Sem = APFloat::IEEEdouble;
9421 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 1ULL << 63))));
9422 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
9424 const fltSemantics &Sem = APFloat::IEEEsingle;
9425 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 1U << 31))));
9426 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9427 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9428 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9430 Constant *C = ConstantVector::get(CV);
9431 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
9432 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
9433 MachinePointerInfo::getConstantPool(),
9434 false, false, false, 16);
9435 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
9437 // Shift sign bit right or left if the two operands have different types.
9438 if (SrcVT.bitsGT(VT)) {
9439 // Op0 is MVT::f32, Op1 is MVT::f64.
9440 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
9441 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
9442 DAG.getConstant(32, MVT::i32));
9443 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
9444 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
9445 DAG.getIntPtrConstant(0));
9448 // Clear first operand sign bit.
9450 if (VT == MVT::f64) {
9451 const fltSemantics &Sem = APFloat::IEEEdouble;
9452 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
9453 APInt(64, ~(1ULL << 63)))));
9454 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
9456 const fltSemantics &Sem = APFloat::IEEEsingle;
9457 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
9458 APInt(32, ~(1U << 31)))));
9459 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9460 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9461 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9463 C = ConstantVector::get(CV);
9464 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
9465 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9466 MachinePointerInfo::getConstantPool(),
9467 false, false, false, 16);
9468 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
9470 // Or the value with the sign bit.
9471 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
9474 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
9475 SDValue N0 = Op.getOperand(0);
9477 MVT VT = Op.getSimpleValueType();
9479 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
9480 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
9481 DAG.getConstant(1, VT));
9482 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
9485 // LowerVectorAllZeroTest - Check whether an OR'd tree is PTEST-able.
9487 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
9488 SelectionDAG &DAG) {
9489 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
9491 if (!Subtarget->hasSSE41())
9494 if (!Op->hasOneUse())
9497 SDNode *N = Op.getNode();
9500 SmallVector<SDValue, 8> Opnds;
9501 DenseMap<SDValue, unsigned> VecInMap;
9502 EVT VT = MVT::Other;
9504 // Recognize a special case where a vector is casted into wide integer to
9506 Opnds.push_back(N->getOperand(0));
9507 Opnds.push_back(N->getOperand(1));
9509 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
9510 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
9511 // BFS traverse all OR'd operands.
9512 if (I->getOpcode() == ISD::OR) {
9513 Opnds.push_back(I->getOperand(0));
9514 Opnds.push_back(I->getOperand(1));
9515 // Re-evaluate the number of nodes to be traversed.
9516 e += 2; // 2 more nodes (LHS and RHS) are pushed.
9520 // Quit if a non-EXTRACT_VECTOR_ELT
9521 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
9524 // Quit if without a constant index.
9525 SDValue Idx = I->getOperand(1);
9526 if (!isa<ConstantSDNode>(Idx))
9529 SDValue ExtractedFromVec = I->getOperand(0);
9530 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
9531 if (M == VecInMap.end()) {
9532 VT = ExtractedFromVec.getValueType();
9533 // Quit if not 128/256-bit vector.
9534 if (!VT.is128BitVector() && !VT.is256BitVector())
9536 // Quit if not the same type.
9537 if (VecInMap.begin() != VecInMap.end() &&
9538 VT != VecInMap.begin()->first.getValueType())
9540 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
9542 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
9545 assert((VT.is128BitVector() || VT.is256BitVector()) &&
9546 "Not extracted from 128-/256-bit vector.");
9548 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
9549 SmallVector<SDValue, 8> VecIns;
9551 for (DenseMap<SDValue, unsigned>::const_iterator
9552 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
9553 // Quit if not all elements are used.
9554 if (I->second != FullMask)
9556 VecIns.push_back(I->first);
9559 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
9561 // Cast all vectors into TestVT for PTEST.
9562 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
9563 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
9565 // If more than one full vectors are evaluated, OR them first before PTEST.
9566 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
9567 // Each iteration will OR 2 nodes and append the result until there is only
9568 // 1 node left, i.e. the final OR'd value of all vectors.
9569 SDValue LHS = VecIns[Slot];
9570 SDValue RHS = VecIns[Slot + 1];
9571 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
9574 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
9575 VecIns.back(), VecIns.back());
9578 /// Emit nodes that will be selected as "test Op0,Op0", or something
9580 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
9581 SelectionDAG &DAG) const {
9584 if (Op.getValueType() == MVT::i1)
9585 // KORTEST instruction should be selected
9586 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
9587 DAG.getConstant(0, Op.getValueType()));
9589 // CF and OF aren't always set the way we want. Determine which
9590 // of these we need.
9591 bool NeedCF = false;
9592 bool NeedOF = false;
9595 case X86::COND_A: case X86::COND_AE:
9596 case X86::COND_B: case X86::COND_BE:
9599 case X86::COND_G: case X86::COND_GE:
9600 case X86::COND_L: case X86::COND_LE:
9601 case X86::COND_O: case X86::COND_NO:
9605 // See if we can use the EFLAGS value from the operand instead of
9606 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
9607 // we prove that the arithmetic won't overflow, we can't use OF or CF.
9608 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
9609 // Emit a CMP with 0, which is the TEST pattern.
9610 //if (Op.getValueType() == MVT::i1)
9611 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
9612 // DAG.getConstant(0, MVT::i1));
9613 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
9614 DAG.getConstant(0, Op.getValueType()));
9616 unsigned Opcode = 0;
9617 unsigned NumOperands = 0;
9619 // Truncate operations may prevent the merge of the SETCC instruction
9620 // and the arithmetic instruction before it. Attempt to truncate the operands
9621 // of the arithmetic instruction and use a reduced bit-width instruction.
9622 bool NeedTruncation = false;
9623 SDValue ArithOp = Op;
9624 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
9625 SDValue Arith = Op->getOperand(0);
9626 // Both the trunc and the arithmetic op need to have one user each.
9627 if (Arith->hasOneUse())
9628 switch (Arith.getOpcode()) {
9635 NeedTruncation = true;
9641 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
9642 // which may be the result of a CAST. We use the variable 'Op', which is the
9643 // non-casted variable when we check for possible users.
9644 switch (ArithOp.getOpcode()) {
9646 // Due to an isel shortcoming, be conservative if this add is likely to be
9647 // selected as part of a load-modify-store instruction. When the root node
9648 // in a match is a store, isel doesn't know how to remap non-chain non-flag
9649 // uses of other nodes in the match, such as the ADD in this case. This
9650 // leads to the ADD being left around and reselected, with the result being
9651 // two adds in the output. Alas, even if none our users are stores, that
9652 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
9653 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
9654 // climbing the DAG back to the root, and it doesn't seem to be worth the
9656 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
9657 UE = Op.getNode()->use_end(); UI != UE; ++UI)
9658 if (UI->getOpcode() != ISD::CopyToReg &&
9659 UI->getOpcode() != ISD::SETCC &&
9660 UI->getOpcode() != ISD::STORE)
9663 if (ConstantSDNode *C =
9664 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
9665 // An add of one will be selected as an INC.
9666 if (C->getAPIntValue() == 1) {
9667 Opcode = X86ISD::INC;
9672 // An add of negative one (subtract of one) will be selected as a DEC.
9673 if (C->getAPIntValue().isAllOnesValue()) {
9674 Opcode = X86ISD::DEC;
9680 // Otherwise use a regular EFLAGS-setting add.
9681 Opcode = X86ISD::ADD;
9685 // If the primary and result isn't used, don't bother using X86ISD::AND,
9686 // because a TEST instruction will be better.
9687 bool NonFlagUse = false;
9688 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
9689 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
9691 unsigned UOpNo = UI.getOperandNo();
9692 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
9693 // Look pass truncate.
9694 UOpNo = User->use_begin().getOperandNo();
9695 User = *User->use_begin();
9698 if (User->getOpcode() != ISD::BRCOND &&
9699 User->getOpcode() != ISD::SETCC &&
9700 !(User->getOpcode() == ISD::SELECT && UOpNo == 0)) {
9713 // Due to the ISEL shortcoming noted above, be conservative if this op is
9714 // likely to be selected as part of a load-modify-store instruction.
9715 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
9716 UE = Op.getNode()->use_end(); UI != UE; ++UI)
9717 if (UI->getOpcode() == ISD::STORE)
9720 // Otherwise use a regular EFLAGS-setting instruction.
9721 switch (ArithOp.getOpcode()) {
9722 default: llvm_unreachable("unexpected operator!");
9723 case ISD::SUB: Opcode = X86ISD::SUB; break;
9724 case ISD::XOR: Opcode = X86ISD::XOR; break;
9725 case ISD::AND: Opcode = X86ISD::AND; break;
9727 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
9728 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
9729 if (EFLAGS.getNode())
9732 Opcode = X86ISD::OR;
9746 return SDValue(Op.getNode(), 1);
9752 // If we found that truncation is beneficial, perform the truncation and
9754 if (NeedTruncation) {
9755 EVT VT = Op.getValueType();
9756 SDValue WideVal = Op->getOperand(0);
9757 EVT WideVT = WideVal.getValueType();
9758 unsigned ConvertedOp = 0;
9759 // Use a target machine opcode to prevent further DAGCombine
9760 // optimizations that may separate the arithmetic operations
9761 // from the setcc node.
9762 switch (WideVal.getOpcode()) {
9764 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
9765 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
9766 case ISD::AND: ConvertedOp = X86ISD::AND; break;
9767 case ISD::OR: ConvertedOp = X86ISD::OR; break;
9768 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
9772 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9773 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
9774 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
9775 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
9776 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
9782 // Emit a CMP with 0, which is the TEST pattern.
9783 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
9784 DAG.getConstant(0, Op.getValueType()));
9786 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
9787 SmallVector<SDValue, 4> Ops;
9788 for (unsigned i = 0; i != NumOperands; ++i)
9789 Ops.push_back(Op.getOperand(i));
9791 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
9792 DAG.ReplaceAllUsesWith(Op, New);
9793 return SDValue(New.getNode(), 1);
9796 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
9798 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
9799 SelectionDAG &DAG) const {
9801 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
9802 if (C->getAPIntValue() == 0)
9803 return EmitTest(Op0, X86CC, DAG);
9805 if (Op0.getValueType() == MVT::i1) {
9807 Op0 = DAG.getNode(ISD::XOR, dl, MVT::i1, Op0,
9808 DAG.getConstant(-1, MVT::i1));
9809 return EmitTest(Op0, X86CC, DAG);
9813 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
9814 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
9815 // Do the comparison at i32 if it's smaller. This avoids subregister
9816 // aliasing issues. Keep the smaller reference if we're optimizing for
9817 // size, however, as that'll allow better folding of memory operations.
9818 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
9819 !DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
9820 AttributeSet::FunctionIndex, Attribute::MinSize)) {
9822 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
9823 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
9824 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
9826 // Use SUB instead of CMP to enable CSE between SUB and CMP.
9827 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
9828 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
9830 return SDValue(Sub.getNode(), 1);
9832 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
9835 /// Convert a comparison if required by the subtarget.
9836 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
9837 SelectionDAG &DAG) const {
9838 // If the subtarget does not support the FUCOMI instruction, floating-point
9839 // comparisons have to be converted.
9840 if (Subtarget->hasCMov() ||
9841 Cmp.getOpcode() != X86ISD::CMP ||
9842 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
9843 !Cmp.getOperand(1).getValueType().isFloatingPoint())
9846 // The instruction selector will select an FUCOM instruction instead of
9847 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
9848 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
9849 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
9851 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
9852 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
9853 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
9854 DAG.getConstant(8, MVT::i8));
9855 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
9856 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
9859 static bool isAllOnes(SDValue V) {
9860 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
9861 return C && C->isAllOnesValue();
9864 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
9865 /// if it's possible.
9866 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
9867 SDLoc dl, SelectionDAG &DAG) const {
9868 SDValue Op0 = And.getOperand(0);
9869 SDValue Op1 = And.getOperand(1);
9870 if (Op0.getOpcode() == ISD::TRUNCATE)
9871 Op0 = Op0.getOperand(0);
9872 if (Op1.getOpcode() == ISD::TRUNCATE)
9873 Op1 = Op1.getOperand(0);
9876 if (Op1.getOpcode() == ISD::SHL)
9877 std::swap(Op0, Op1);
9878 if (Op0.getOpcode() == ISD::SHL) {
9879 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
9880 if (And00C->getZExtValue() == 1) {
9881 // If we looked past a truncate, check that it's only truncating away
9883 unsigned BitWidth = Op0.getValueSizeInBits();
9884 unsigned AndBitWidth = And.getValueSizeInBits();
9885 if (BitWidth > AndBitWidth) {
9887 DAG.ComputeMaskedBits(Op0, Zeros, Ones);
9888 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
9892 RHS = Op0.getOperand(1);
9894 } else if (Op1.getOpcode() == ISD::Constant) {
9895 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
9896 uint64_t AndRHSVal = AndRHS->getZExtValue();
9897 SDValue AndLHS = Op0;
9899 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
9900 LHS = AndLHS.getOperand(0);
9901 RHS = AndLHS.getOperand(1);
9904 // Use BT if the immediate can't be encoded in a TEST instruction.
9905 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
9907 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
9911 if (LHS.getNode()) {
9912 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
9913 // instruction. Since the shift amount is in-range-or-undefined, we know
9914 // that doing a bittest on the i32 value is ok. We extend to i32 because
9915 // the encoding for the i16 version is larger than the i32 version.
9916 // Also promote i16 to i32 for performance / code size reason.
9917 if (LHS.getValueType() == MVT::i8 ||
9918 LHS.getValueType() == MVT::i16)
9919 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
9921 // If the operand types disagree, extend the shift amount to match. Since
9922 // BT ignores high bits (like shifts) we can use anyextend.
9923 if (LHS.getValueType() != RHS.getValueType())
9924 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
9926 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
9927 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
9928 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9929 DAG.getConstant(Cond, MVT::i8), BT);
9935 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
9937 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
9942 // SSE Condition code mapping:
9951 switch (SetCCOpcode) {
9952 default: llvm_unreachable("Unexpected SETCC condition");
9954 case ISD::SETEQ: SSECC = 0; break;
9956 case ISD::SETGT: Swap = true; // Fallthrough
9958 case ISD::SETOLT: SSECC = 1; break;
9960 case ISD::SETGE: Swap = true; // Fallthrough
9962 case ISD::SETOLE: SSECC = 2; break;
9963 case ISD::SETUO: SSECC = 3; break;
9965 case ISD::SETNE: SSECC = 4; break;
9966 case ISD::SETULE: Swap = true; // Fallthrough
9967 case ISD::SETUGE: SSECC = 5; break;
9968 case ISD::SETULT: Swap = true; // Fallthrough
9969 case ISD::SETUGT: SSECC = 6; break;
9970 case ISD::SETO: SSECC = 7; break;
9972 case ISD::SETONE: SSECC = 8; break;
9975 std::swap(Op0, Op1);
9980 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
9981 // ones, and then concatenate the result back.
9982 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
9983 MVT VT = Op.getSimpleValueType();
9985 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
9986 "Unsupported value type for operation");
9988 unsigned NumElems = VT.getVectorNumElements();
9990 SDValue CC = Op.getOperand(2);
9992 // Extract the LHS vectors
9993 SDValue LHS = Op.getOperand(0);
9994 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
9995 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
9997 // Extract the RHS vectors
9998 SDValue RHS = Op.getOperand(1);
9999 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
10000 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
10002 // Issue the operation on the smaller types and concatenate the result back
10003 MVT EltVT = VT.getVectorElementType();
10004 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10005 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
10006 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
10007 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
10010 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
10011 const X86Subtarget *Subtarget) {
10012 SDValue Op0 = Op.getOperand(0);
10013 SDValue Op1 = Op.getOperand(1);
10014 SDValue CC = Op.getOperand(2);
10015 MVT VT = Op.getSimpleValueType();
10018 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 32 &&
10019 Op.getValueType().getScalarType() == MVT::i1 &&
10020 "Cannot set masked compare for this operation");
10022 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
10024 bool Unsigned = false;
10027 switch (SetCCOpcode) {
10028 default: llvm_unreachable("Unexpected SETCC condition");
10029 case ISD::SETNE: SSECC = 4; break;
10030 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
10031 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
10032 case ISD::SETLT: Swap = true; //fall-through
10033 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
10034 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
10035 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
10036 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
10037 case ISD::SETULE: Unsigned = true; //fall-through
10038 case ISD::SETLE: SSECC = 2; break;
10042 std::swap(Op0, Op1);
10044 return DAG.getNode(Opc, dl, VT, Op0, Op1);
10045 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
10046 return DAG.getNode(Opc, dl, VT, Op0, Op1,
10047 DAG.getConstant(SSECC, MVT::i8));
10050 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
10051 SelectionDAG &DAG) {
10052 SDValue Op0 = Op.getOperand(0);
10053 SDValue Op1 = Op.getOperand(1);
10054 SDValue CC = Op.getOperand(2);
10055 MVT VT = Op.getSimpleValueType();
10056 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
10057 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
10062 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
10063 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
10066 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
10067 unsigned Opc = X86ISD::CMPP;
10068 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
10069 assert(VT.getVectorNumElements() <= 16);
10070 Opc = X86ISD::CMPM;
10072 // In the two special cases we can't handle, emit two comparisons.
10075 unsigned CombineOpc;
10076 if (SetCCOpcode == ISD::SETUEQ) {
10077 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
10079 assert(SetCCOpcode == ISD::SETONE);
10080 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
10083 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
10084 DAG.getConstant(CC0, MVT::i8));
10085 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
10086 DAG.getConstant(CC1, MVT::i8));
10087 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
10089 // Handle all other FP comparisons here.
10090 return DAG.getNode(Opc, dl, VT, Op0, Op1,
10091 DAG.getConstant(SSECC, MVT::i8));
10094 // Break 256-bit integer vector compare into smaller ones.
10095 if (VT.is256BitVector() && !Subtarget->hasInt256())
10096 return Lower256IntVSETCC(Op, DAG);
10098 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
10099 EVT OpVT = Op1.getValueType();
10100 if (Subtarget->hasAVX512()) {
10101 if (Op1.getValueType().is512BitVector() ||
10102 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
10103 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
10105 // In AVX-512 architecture setcc returns mask with i1 elements,
10106 // But there is no compare instruction for i8 and i16 elements.
10107 // We are not talking about 512-bit operands in this case, these
10108 // types are illegal.
10110 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
10111 OpVT.getVectorElementType().getSizeInBits() >= 8))
10112 return DAG.getNode(ISD::TRUNCATE, dl, VT,
10113 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
10116 // We are handling one of the integer comparisons here. Since SSE only has
10117 // GT and EQ comparisons for integer, swapping operands and multiple
10118 // operations may be required for some comparisons.
10120 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
10122 switch (SetCCOpcode) {
10123 default: llvm_unreachable("Unexpected SETCC condition");
10124 case ISD::SETNE: Invert = true;
10125 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
10126 case ISD::SETLT: Swap = true;
10127 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
10128 case ISD::SETGE: Swap = true;
10129 case ISD::SETLE: Opc = X86ISD::PCMPGT;
10130 Invert = true; break;
10131 case ISD::SETULT: Swap = true;
10132 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
10133 FlipSigns = true; break;
10134 case ISD::SETUGE: Swap = true;
10135 case ISD::SETULE: Opc = X86ISD::PCMPGT;
10136 FlipSigns = true; Invert = true; break;
10139 // Special case: Use min/max operations for SETULE/SETUGE
10140 MVT VET = VT.getVectorElementType();
10142 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
10143 || (Subtarget->hasSSE2() && (VET == MVT::i8));
10146 switch (SetCCOpcode) {
10148 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
10149 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
10152 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
10156 std::swap(Op0, Op1);
10158 // Check that the operation in question is available (most are plain SSE2,
10159 // but PCMPGTQ and PCMPEQQ have different requirements).
10160 if (VT == MVT::v2i64) {
10161 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
10162 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
10164 // First cast everything to the right type.
10165 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
10166 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
10168 // Since SSE has no unsigned integer comparisons, we need to flip the sign
10169 // bits of the inputs before performing those operations. The lower
10170 // compare is always unsigned.
10173 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
10175 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
10176 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
10177 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
10178 Sign, Zero, Sign, Zero);
10180 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
10181 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
10183 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
10184 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
10185 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
10187 // Create masks for only the low parts/high parts of the 64 bit integers.
10188 static const int MaskHi[] = { 1, 1, 3, 3 };
10189 static const int MaskLo[] = { 0, 0, 2, 2 };
10190 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
10191 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
10192 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
10194 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
10195 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
10198 Result = DAG.getNOT(dl, Result, MVT::v4i32);
10200 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
10203 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
10204 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
10205 // pcmpeqd + pshufd + pand.
10206 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
10208 // First cast everything to the right type.
10209 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
10210 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
10213 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
10215 // Make sure the lower and upper halves are both all-ones.
10216 static const int Mask[] = { 1, 0, 3, 2 };
10217 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
10218 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
10221 Result = DAG.getNOT(dl, Result, MVT::v4i32);
10223 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
10227 // Since SSE has no unsigned integer comparisons, we need to flip the sign
10228 // bits of the inputs before performing those operations.
10230 EVT EltVT = VT.getVectorElementType();
10231 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
10232 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
10233 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
10236 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
10238 // If the logical-not of the result is required, perform that now.
10240 Result = DAG.getNOT(dl, Result, VT);
10243 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
10248 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
10250 MVT VT = Op.getSimpleValueType();
10252 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
10254 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
10255 && "SetCC type must be 8-bit or 1-bit integer");
10256 SDValue Op0 = Op.getOperand(0);
10257 SDValue Op1 = Op.getOperand(1);
10259 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
10261 // Optimize to BT if possible.
10262 // Lower (X & (1 << N)) == 0 to BT(X, N).
10263 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
10264 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
10265 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
10266 Op1.getOpcode() == ISD::Constant &&
10267 cast<ConstantSDNode>(Op1)->isNullValue() &&
10268 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
10269 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
10270 if (NewSetCC.getNode())
10274 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
10276 if (Op1.getOpcode() == ISD::Constant &&
10277 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
10278 cast<ConstantSDNode>(Op1)->isNullValue()) &&
10279 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
10281 // If the input is a setcc, then reuse the input setcc or use a new one with
10282 // the inverted condition.
10283 if (Op0.getOpcode() == X86ISD::SETCC) {
10284 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
10285 bool Invert = (CC == ISD::SETNE) ^
10286 cast<ConstantSDNode>(Op1)->isNullValue();
10290 CCode = X86::GetOppositeBranchCondition(CCode);
10291 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
10292 DAG.getConstant(CCode, MVT::i8),
10293 Op0.getOperand(1));
10295 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
10300 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
10301 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
10302 if (X86CC == X86::COND_INVALID)
10305 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG);
10306 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
10307 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
10308 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
10310 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
10314 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
10315 static bool isX86LogicalCmp(SDValue Op) {
10316 unsigned Opc = Op.getNode()->getOpcode();
10317 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
10318 Opc == X86ISD::SAHF)
10320 if (Op.getResNo() == 1 &&
10321 (Opc == X86ISD::ADD ||
10322 Opc == X86ISD::SUB ||
10323 Opc == X86ISD::ADC ||
10324 Opc == X86ISD::SBB ||
10325 Opc == X86ISD::SMUL ||
10326 Opc == X86ISD::UMUL ||
10327 Opc == X86ISD::INC ||
10328 Opc == X86ISD::DEC ||
10329 Opc == X86ISD::OR ||
10330 Opc == X86ISD::XOR ||
10331 Opc == X86ISD::AND))
10334 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
10340 static bool isZero(SDValue V) {
10341 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
10342 return C && C->isNullValue();
10345 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
10346 if (V.getOpcode() != ISD::TRUNCATE)
10349 SDValue VOp0 = V.getOperand(0);
10350 unsigned InBits = VOp0.getValueSizeInBits();
10351 unsigned Bits = V.getValueSizeInBits();
10352 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
10355 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
10356 bool addTest = true;
10357 SDValue Cond = Op.getOperand(0);
10358 SDValue Op1 = Op.getOperand(1);
10359 SDValue Op2 = Op.getOperand(2);
10361 EVT VT = Op1.getValueType();
10364 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
10365 // are available. Otherwise fp cmovs get lowered into a less efficient branch
10366 // sequence later on.
10367 if (Cond.getOpcode() == ISD::SETCC &&
10368 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
10369 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
10370 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
10371 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
10372 int SSECC = translateX86FSETCC(
10373 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
10376 if (Subtarget->hasAVX512()) {
10377 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
10378 DAG.getConstant(SSECC, MVT::i8));
10379 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
10381 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
10382 DAG.getConstant(SSECC, MVT::i8));
10383 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
10384 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
10385 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
10389 if (Cond.getOpcode() == ISD::SETCC) {
10390 SDValue NewCond = LowerSETCC(Cond, DAG);
10391 if (NewCond.getNode())
10395 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
10396 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
10397 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
10398 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
10399 if (Cond.getOpcode() == X86ISD::SETCC &&
10400 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
10401 isZero(Cond.getOperand(1).getOperand(1))) {
10402 SDValue Cmp = Cond.getOperand(1);
10404 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
10406 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
10407 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
10408 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
10410 SDValue CmpOp0 = Cmp.getOperand(0);
10411 // Apply further optimizations for special cases
10412 // (select (x != 0), -1, 0) -> neg & sbb
10413 // (select (x == 0), 0, -1) -> neg & sbb
10414 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
10415 if (YC->isNullValue() &&
10416 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
10417 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
10418 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
10419 DAG.getConstant(0, CmpOp0.getValueType()),
10421 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
10422 DAG.getConstant(X86::COND_B, MVT::i8),
10423 SDValue(Neg.getNode(), 1));
10427 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
10428 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
10429 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
10431 SDValue Res = // Res = 0 or -1.
10432 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
10433 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
10435 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
10436 Res = DAG.getNOT(DL, Res, Res.getValueType());
10438 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
10439 if (N2C == 0 || !N2C->isNullValue())
10440 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
10445 // Look past (and (setcc_carry (cmp ...)), 1).
10446 if (Cond.getOpcode() == ISD::AND &&
10447 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
10448 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
10449 if (C && C->getAPIntValue() == 1)
10450 Cond = Cond.getOperand(0);
10453 // If condition flag is set by a X86ISD::CMP, then use it as the condition
10454 // setting operand in place of the X86ISD::SETCC.
10455 unsigned CondOpcode = Cond.getOpcode();
10456 if (CondOpcode == X86ISD::SETCC ||
10457 CondOpcode == X86ISD::SETCC_CARRY) {
10458 CC = Cond.getOperand(0);
10460 SDValue Cmp = Cond.getOperand(1);
10461 unsigned Opc = Cmp.getOpcode();
10462 MVT VT = Op.getSimpleValueType();
10464 bool IllegalFPCMov = false;
10465 if (VT.isFloatingPoint() && !VT.isVector() &&
10466 !isScalarFPTypeInSSEReg(VT)) // FPStack?
10467 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
10469 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
10470 Opc == X86ISD::BT) { // FIXME
10474 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
10475 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
10476 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
10477 Cond.getOperand(0).getValueType() != MVT::i8)) {
10478 SDValue LHS = Cond.getOperand(0);
10479 SDValue RHS = Cond.getOperand(1);
10480 unsigned X86Opcode;
10483 switch (CondOpcode) {
10484 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
10485 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
10486 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
10487 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
10488 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
10489 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
10490 default: llvm_unreachable("unexpected overflowing operator");
10492 if (CondOpcode == ISD::UMULO)
10493 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
10496 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
10498 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
10500 if (CondOpcode == ISD::UMULO)
10501 Cond = X86Op.getValue(2);
10503 Cond = X86Op.getValue(1);
10505 CC = DAG.getConstant(X86Cond, MVT::i8);
10510 // Look pass the truncate if the high bits are known zero.
10511 if (isTruncWithZeroHighBitsInput(Cond, DAG))
10512 Cond = Cond.getOperand(0);
10514 // We know the result of AND is compared against zero. Try to match
10516 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
10517 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
10518 if (NewSetCC.getNode()) {
10519 CC = NewSetCC.getOperand(0);
10520 Cond = NewSetCC.getOperand(1);
10527 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10528 Cond = EmitTest(Cond, X86::COND_NE, DAG);
10531 // a < b ? -1 : 0 -> RES = ~setcc_carry
10532 // a < b ? 0 : -1 -> RES = setcc_carry
10533 // a >= b ? -1 : 0 -> RES = setcc_carry
10534 // a >= b ? 0 : -1 -> RES = ~setcc_carry
10535 if (Cond.getOpcode() == X86ISD::SUB) {
10536 Cond = ConvertCmpIfNecessary(Cond, DAG);
10537 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
10539 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
10540 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
10541 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
10542 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
10543 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
10544 return DAG.getNOT(DL, Res, Res.getValueType());
10549 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
10550 // widen the cmov and push the truncate through. This avoids introducing a new
10551 // branch during isel and doesn't add any extensions.
10552 if (Op.getValueType() == MVT::i8 &&
10553 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
10554 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
10555 if (T1.getValueType() == T2.getValueType() &&
10556 // Blacklist CopyFromReg to avoid partial register stalls.
10557 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
10558 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
10559 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
10560 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
10564 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
10565 // condition is true.
10566 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
10567 SDValue Ops[] = { Op2, Op1, CC, Cond };
10568 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
10571 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, SelectionDAG &DAG) {
10572 MVT VT = Op->getSimpleValueType(0);
10573 SDValue In = Op->getOperand(0);
10574 MVT InVT = In.getSimpleValueType();
10577 unsigned int NumElts = VT.getVectorNumElements();
10578 if (NumElts != 8 && NumElts != 16)
10581 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
10582 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
10584 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
10585 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
10587 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
10588 Constant *C = ConstantInt::get(*DAG.getContext(),
10589 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
10591 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
10592 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
10593 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
10594 MachinePointerInfo::getConstantPool(),
10595 false, false, false, Alignment);
10596 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
10597 if (VT.is512BitVector())
10599 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
10602 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
10603 SelectionDAG &DAG) {
10604 MVT VT = Op->getSimpleValueType(0);
10605 SDValue In = Op->getOperand(0);
10606 MVT InVT = In.getSimpleValueType();
10609 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
10610 return LowerSIGN_EXTEND_AVX512(Op, DAG);
10612 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
10613 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
10614 (VT != MVT::v16i16 || InVT != MVT::v16i8))
10617 if (Subtarget->hasInt256())
10618 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
10620 // Optimize vectors in AVX mode
10621 // Sign extend v8i16 to v8i32 and
10624 // Divide input vector into two parts
10625 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
10626 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
10627 // concat the vectors to original VT
10629 unsigned NumElems = InVT.getVectorNumElements();
10630 SDValue Undef = DAG.getUNDEF(InVT);
10632 SmallVector<int,8> ShufMask1(NumElems, -1);
10633 for (unsigned i = 0; i != NumElems/2; ++i)
10636 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
10638 SmallVector<int,8> ShufMask2(NumElems, -1);
10639 for (unsigned i = 0; i != NumElems/2; ++i)
10640 ShufMask2[i] = i + NumElems/2;
10642 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
10644 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
10645 VT.getVectorNumElements()/2);
10647 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
10648 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
10650 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
10653 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
10654 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
10655 // from the AND / OR.
10656 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
10657 Opc = Op.getOpcode();
10658 if (Opc != ISD::OR && Opc != ISD::AND)
10660 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
10661 Op.getOperand(0).hasOneUse() &&
10662 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
10663 Op.getOperand(1).hasOneUse());
10666 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
10667 // 1 and that the SETCC node has a single use.
10668 static bool isXor1OfSetCC(SDValue Op) {
10669 if (Op.getOpcode() != ISD::XOR)
10671 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
10672 if (N1C && N1C->getAPIntValue() == 1) {
10673 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
10674 Op.getOperand(0).hasOneUse();
10679 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
10680 bool addTest = true;
10681 SDValue Chain = Op.getOperand(0);
10682 SDValue Cond = Op.getOperand(1);
10683 SDValue Dest = Op.getOperand(2);
10686 bool Inverted = false;
10688 if (Cond.getOpcode() == ISD::SETCC) {
10689 // Check for setcc([su]{add,sub,mul}o == 0).
10690 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
10691 isa<ConstantSDNode>(Cond.getOperand(1)) &&
10692 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
10693 Cond.getOperand(0).getResNo() == 1 &&
10694 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
10695 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
10696 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
10697 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
10698 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
10699 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
10701 Cond = Cond.getOperand(0);
10703 SDValue NewCond = LowerSETCC(Cond, DAG);
10704 if (NewCond.getNode())
10709 // FIXME: LowerXALUO doesn't handle these!!
10710 else if (Cond.getOpcode() == X86ISD::ADD ||
10711 Cond.getOpcode() == X86ISD::SUB ||
10712 Cond.getOpcode() == X86ISD::SMUL ||
10713 Cond.getOpcode() == X86ISD::UMUL)
10714 Cond = LowerXALUO(Cond, DAG);
10717 // Look pass (and (setcc_carry (cmp ...)), 1).
10718 if (Cond.getOpcode() == ISD::AND &&
10719 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
10720 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
10721 if (C && C->getAPIntValue() == 1)
10722 Cond = Cond.getOperand(0);
10725 // If condition flag is set by a X86ISD::CMP, then use it as the condition
10726 // setting operand in place of the X86ISD::SETCC.
10727 unsigned CondOpcode = Cond.getOpcode();
10728 if (CondOpcode == X86ISD::SETCC ||
10729 CondOpcode == X86ISD::SETCC_CARRY) {
10730 CC = Cond.getOperand(0);
10732 SDValue Cmp = Cond.getOperand(1);
10733 unsigned Opc = Cmp.getOpcode();
10734 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
10735 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
10739 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
10743 // These can only come from an arithmetic instruction with overflow,
10744 // e.g. SADDO, UADDO.
10745 Cond = Cond.getNode()->getOperand(1);
10751 CondOpcode = Cond.getOpcode();
10752 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
10753 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
10754 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
10755 Cond.getOperand(0).getValueType() != MVT::i8)) {
10756 SDValue LHS = Cond.getOperand(0);
10757 SDValue RHS = Cond.getOperand(1);
10758 unsigned X86Opcode;
10761 // Keep this in sync with LowerXALUO, otherwise we might create redundant
10762 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
10764 switch (CondOpcode) {
10765 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
10767 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
10769 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
10772 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
10773 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
10775 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
10777 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
10780 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
10781 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
10782 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
10783 default: llvm_unreachable("unexpected overflowing operator");
10786 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
10787 if (CondOpcode == ISD::UMULO)
10788 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
10791 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
10793 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
10795 if (CondOpcode == ISD::UMULO)
10796 Cond = X86Op.getValue(2);
10798 Cond = X86Op.getValue(1);
10800 CC = DAG.getConstant(X86Cond, MVT::i8);
10804 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
10805 SDValue Cmp = Cond.getOperand(0).getOperand(1);
10806 if (CondOpc == ISD::OR) {
10807 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
10808 // two branches instead of an explicit OR instruction with a
10810 if (Cmp == Cond.getOperand(1).getOperand(1) &&
10811 isX86LogicalCmp(Cmp)) {
10812 CC = Cond.getOperand(0).getOperand(0);
10813 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10814 Chain, Dest, CC, Cmp);
10815 CC = Cond.getOperand(1).getOperand(0);
10819 } else { // ISD::AND
10820 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
10821 // two branches instead of an explicit AND instruction with a
10822 // separate test. However, we only do this if this block doesn't
10823 // have a fall-through edge, because this requires an explicit
10824 // jmp when the condition is false.
10825 if (Cmp == Cond.getOperand(1).getOperand(1) &&
10826 isX86LogicalCmp(Cmp) &&
10827 Op.getNode()->hasOneUse()) {
10828 X86::CondCode CCode =
10829 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
10830 CCode = X86::GetOppositeBranchCondition(CCode);
10831 CC = DAG.getConstant(CCode, MVT::i8);
10832 SDNode *User = *Op.getNode()->use_begin();
10833 // Look for an unconditional branch following this conditional branch.
10834 // We need this because we need to reverse the successors in order
10835 // to implement FCMP_OEQ.
10836 if (User->getOpcode() == ISD::BR) {
10837 SDValue FalseBB = User->getOperand(1);
10839 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
10840 assert(NewBR == User);
10844 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10845 Chain, Dest, CC, Cmp);
10846 X86::CondCode CCode =
10847 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
10848 CCode = X86::GetOppositeBranchCondition(CCode);
10849 CC = DAG.getConstant(CCode, MVT::i8);
10855 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
10856 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
10857 // It should be transformed during dag combiner except when the condition
10858 // is set by a arithmetics with overflow node.
10859 X86::CondCode CCode =
10860 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
10861 CCode = X86::GetOppositeBranchCondition(CCode);
10862 CC = DAG.getConstant(CCode, MVT::i8);
10863 Cond = Cond.getOperand(0).getOperand(1);
10865 } else if (Cond.getOpcode() == ISD::SETCC &&
10866 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
10867 // For FCMP_OEQ, we can emit
10868 // two branches instead of an explicit AND instruction with a
10869 // separate test. However, we only do this if this block doesn't
10870 // have a fall-through edge, because this requires an explicit
10871 // jmp when the condition is false.
10872 if (Op.getNode()->hasOneUse()) {
10873 SDNode *User = *Op.getNode()->use_begin();
10874 // Look for an unconditional branch following this conditional branch.
10875 // We need this because we need to reverse the successors in order
10876 // to implement FCMP_OEQ.
10877 if (User->getOpcode() == ISD::BR) {
10878 SDValue FalseBB = User->getOperand(1);
10880 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
10881 assert(NewBR == User);
10885 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
10886 Cond.getOperand(0), Cond.getOperand(1));
10887 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
10888 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10889 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10890 Chain, Dest, CC, Cmp);
10891 CC = DAG.getConstant(X86::COND_P, MVT::i8);
10896 } else if (Cond.getOpcode() == ISD::SETCC &&
10897 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
10898 // For FCMP_UNE, we can emit
10899 // two branches instead of an explicit AND instruction with a
10900 // separate test. However, we only do this if this block doesn't
10901 // have a fall-through edge, because this requires an explicit
10902 // jmp when the condition is false.
10903 if (Op.getNode()->hasOneUse()) {
10904 SDNode *User = *Op.getNode()->use_begin();
10905 // Look for an unconditional branch following this conditional branch.
10906 // We need this because we need to reverse the successors in order
10907 // to implement FCMP_UNE.
10908 if (User->getOpcode() == ISD::BR) {
10909 SDValue FalseBB = User->getOperand(1);
10911 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
10912 assert(NewBR == User);
10915 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
10916 Cond.getOperand(0), Cond.getOperand(1));
10917 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
10918 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10919 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10920 Chain, Dest, CC, Cmp);
10921 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
10931 // Look pass the truncate if the high bits are known zero.
10932 if (isTruncWithZeroHighBitsInput(Cond, DAG))
10933 Cond = Cond.getOperand(0);
10935 // We know the result of AND is compared against zero. Try to match
10937 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
10938 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
10939 if (NewSetCC.getNode()) {
10940 CC = NewSetCC.getOperand(0);
10941 Cond = NewSetCC.getOperand(1);
10948 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10949 Cond = EmitTest(Cond, X86::COND_NE, DAG);
10951 Cond = ConvertCmpIfNecessary(Cond, DAG);
10952 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10953 Chain, Dest, CC, Cond);
10956 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
10957 // Calls to _alloca is needed to probe the stack when allocating more than 4k
10958 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
10959 // that the guard pages used by the OS virtual memory manager are allocated in
10960 // correct sequence.
10962 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
10963 SelectionDAG &DAG) const {
10964 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() ||
10965 getTargetMachine().Options.EnableSegmentedStacks) &&
10966 "This should be used only on Windows targets or when segmented stacks "
10968 assert(!Subtarget->isTargetMacho() && "Not implemented");
10972 SDValue Chain = Op.getOperand(0);
10973 SDValue Size = Op.getOperand(1);
10974 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
10975 EVT VT = Op.getNode()->getValueType(0);
10977 bool Is64Bit = Subtarget->is64Bit();
10978 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32;
10980 if (getTargetMachine().Options.EnableSegmentedStacks) {
10981 MachineFunction &MF = DAG.getMachineFunction();
10982 MachineRegisterInfo &MRI = MF.getRegInfo();
10985 // The 64 bit implementation of segmented stacks needs to clobber both r10
10986 // r11. This makes it impossible to use it along with nested parameters.
10987 const Function *F = MF.getFunction();
10989 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
10991 if (I->hasNestAttr())
10992 report_fatal_error("Cannot use segmented stacks with functions that "
10993 "have nested arguments.");
10996 const TargetRegisterClass *AddrRegClass =
10997 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
10998 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
10999 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
11000 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
11001 DAG.getRegister(Vreg, SPTy));
11002 SDValue Ops1[2] = { Value, Chain };
11003 return DAG.getMergeValues(Ops1, 2, dl);
11006 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
11008 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
11009 Flag = Chain.getValue(1);
11010 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
11012 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
11014 const X86RegisterInfo *RegInfo =
11015 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
11016 unsigned SPReg = RegInfo->getStackRegister();
11017 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
11018 Chain = SP.getValue(1);
11021 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
11022 DAG.getConstant(-(uint64_t)Align, VT));
11023 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
11026 SDValue Ops1[2] = { SP, Chain };
11027 return DAG.getMergeValues(Ops1, 2, dl);
11031 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
11032 MachineFunction &MF = DAG.getMachineFunction();
11033 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
11035 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
11038 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
11039 // vastart just stores the address of the VarArgsFrameIndex slot into the
11040 // memory location argument.
11041 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
11043 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
11044 MachinePointerInfo(SV), false, false, 0);
11048 // gp_offset (0 - 6 * 8)
11049 // fp_offset (48 - 48 + 8 * 16)
11050 // overflow_arg_area (point to parameters coming in memory).
11052 SmallVector<SDValue, 8> MemOps;
11053 SDValue FIN = Op.getOperand(1);
11055 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
11056 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
11058 FIN, MachinePointerInfo(SV), false, false, 0);
11059 MemOps.push_back(Store);
11062 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11063 FIN, DAG.getIntPtrConstant(4));
11064 Store = DAG.getStore(Op.getOperand(0), DL,
11065 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
11067 FIN, MachinePointerInfo(SV, 4), false, false, 0);
11068 MemOps.push_back(Store);
11070 // Store ptr to overflow_arg_area
11071 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11072 FIN, DAG.getIntPtrConstant(4));
11073 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
11075 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
11076 MachinePointerInfo(SV, 8),
11078 MemOps.push_back(Store);
11080 // Store ptr to reg_save_area.
11081 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11082 FIN, DAG.getIntPtrConstant(8));
11083 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
11085 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
11086 MachinePointerInfo(SV, 16), false, false, 0);
11087 MemOps.push_back(Store);
11088 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
11089 &MemOps[0], MemOps.size());
11092 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
11093 assert(Subtarget->is64Bit() &&
11094 "LowerVAARG only handles 64-bit va_arg!");
11095 assert((Subtarget->isTargetLinux() ||
11096 Subtarget->isTargetDarwin()) &&
11097 "Unhandled target in LowerVAARG");
11098 assert(Op.getNode()->getNumOperands() == 4);
11099 SDValue Chain = Op.getOperand(0);
11100 SDValue SrcPtr = Op.getOperand(1);
11101 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
11102 unsigned Align = Op.getConstantOperandVal(3);
11105 EVT ArgVT = Op.getNode()->getValueType(0);
11106 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
11107 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
11110 // Decide which area this value should be read from.
11111 // TODO: Implement the AMD64 ABI in its entirety. This simple
11112 // selection mechanism works only for the basic types.
11113 if (ArgVT == MVT::f80) {
11114 llvm_unreachable("va_arg for f80 not yet implemented");
11115 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
11116 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
11117 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
11118 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
11120 llvm_unreachable("Unhandled argument type in LowerVAARG");
11123 if (ArgMode == 2) {
11124 // Sanity Check: Make sure using fp_offset makes sense.
11125 assert(!getTargetMachine().Options.UseSoftFloat &&
11126 !(DAG.getMachineFunction()
11127 .getFunction()->getAttributes()
11128 .hasAttribute(AttributeSet::FunctionIndex,
11129 Attribute::NoImplicitFloat)) &&
11130 Subtarget->hasSSE1());
11133 // Insert VAARG_64 node into the DAG
11134 // VAARG_64 returns two values: Variable Argument Address, Chain
11135 SmallVector<SDValue, 11> InstOps;
11136 InstOps.push_back(Chain);
11137 InstOps.push_back(SrcPtr);
11138 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
11139 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
11140 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
11141 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
11142 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
11143 VTs, &InstOps[0], InstOps.size(),
11145 MachinePointerInfo(SV),
11147 /*Volatile=*/false,
11149 /*WriteMem=*/true);
11150 Chain = VAARG.getValue(1);
11152 // Load the next argument and return it
11153 return DAG.getLoad(ArgVT, dl,
11156 MachinePointerInfo(),
11157 false, false, false, 0);
11160 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
11161 SelectionDAG &DAG) {
11162 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
11163 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
11164 SDValue Chain = Op.getOperand(0);
11165 SDValue DstPtr = Op.getOperand(1);
11166 SDValue SrcPtr = Op.getOperand(2);
11167 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
11168 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
11171 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
11172 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
11174 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
11177 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
11178 // amount is a constant. Takes immediate version of shift as input.
11179 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
11180 SDValue SrcOp, uint64_t ShiftAmt,
11181 SelectionDAG &DAG) {
11182 MVT ElementType = VT.getVectorElementType();
11184 // Check for ShiftAmt >= element width
11185 if (ShiftAmt >= ElementType.getSizeInBits()) {
11186 if (Opc == X86ISD::VSRAI)
11187 ShiftAmt = ElementType.getSizeInBits() - 1;
11189 return DAG.getConstant(0, VT);
11192 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
11193 && "Unknown target vector shift-by-constant node");
11195 // Fold this packed vector shift into a build vector if SrcOp is a
11196 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
11197 if (VT == SrcOp.getSimpleValueType() &&
11198 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
11199 SmallVector<SDValue, 8> Elts;
11200 unsigned NumElts = SrcOp->getNumOperands();
11201 ConstantSDNode *ND;
11204 default: llvm_unreachable(0);
11205 case X86ISD::VSHLI:
11206 for (unsigned i=0; i!=NumElts; ++i) {
11207 SDValue CurrentOp = SrcOp->getOperand(i);
11208 if (CurrentOp->getOpcode() == ISD::UNDEF) {
11209 Elts.push_back(CurrentOp);
11212 ND = cast<ConstantSDNode>(CurrentOp);
11213 const APInt &C = ND->getAPIntValue();
11214 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), ElementType));
11217 case X86ISD::VSRLI:
11218 for (unsigned i=0; i!=NumElts; ++i) {
11219 SDValue CurrentOp = SrcOp->getOperand(i);
11220 if (CurrentOp->getOpcode() == ISD::UNDEF) {
11221 Elts.push_back(CurrentOp);
11224 ND = cast<ConstantSDNode>(CurrentOp);
11225 const APInt &C = ND->getAPIntValue();
11226 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), ElementType));
11229 case X86ISD::VSRAI:
11230 for (unsigned i=0; i!=NumElts; ++i) {
11231 SDValue CurrentOp = SrcOp->getOperand(i);
11232 if (CurrentOp->getOpcode() == ISD::UNDEF) {
11233 Elts.push_back(CurrentOp);
11236 ND = cast<ConstantSDNode>(CurrentOp);
11237 const APInt &C = ND->getAPIntValue();
11238 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), ElementType));
11243 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Elts[0], NumElts);
11246 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
11249 // getTargetVShiftNode - Handle vector element shifts where the shift amount
11250 // may or may not be a constant. Takes immediate version of shift as input.
11251 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
11252 SDValue SrcOp, SDValue ShAmt,
11253 SelectionDAG &DAG) {
11254 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
11256 // Catch shift-by-constant.
11257 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
11258 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
11259 CShAmt->getZExtValue(), DAG);
11261 // Change opcode to non-immediate version
11263 default: llvm_unreachable("Unknown target vector shift node");
11264 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
11265 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
11266 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
11269 // Need to build a vector containing shift amount
11270 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
11273 ShOps[1] = DAG.getConstant(0, MVT::i32);
11274 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32);
11275 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &ShOps[0], 4);
11277 // The return type has to be a 128-bit type with the same element
11278 // type as the input type.
11279 MVT EltVT = VT.getVectorElementType();
11280 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
11282 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
11283 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
11286 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
11288 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
11290 default: return SDValue(); // Don't custom lower most intrinsics.
11291 // Comparison intrinsics.
11292 case Intrinsic::x86_sse_comieq_ss:
11293 case Intrinsic::x86_sse_comilt_ss:
11294 case Intrinsic::x86_sse_comile_ss:
11295 case Intrinsic::x86_sse_comigt_ss:
11296 case Intrinsic::x86_sse_comige_ss:
11297 case Intrinsic::x86_sse_comineq_ss:
11298 case Intrinsic::x86_sse_ucomieq_ss:
11299 case Intrinsic::x86_sse_ucomilt_ss:
11300 case Intrinsic::x86_sse_ucomile_ss:
11301 case Intrinsic::x86_sse_ucomigt_ss:
11302 case Intrinsic::x86_sse_ucomige_ss:
11303 case Intrinsic::x86_sse_ucomineq_ss:
11304 case Intrinsic::x86_sse2_comieq_sd:
11305 case Intrinsic::x86_sse2_comilt_sd:
11306 case Intrinsic::x86_sse2_comile_sd:
11307 case Intrinsic::x86_sse2_comigt_sd:
11308 case Intrinsic::x86_sse2_comige_sd:
11309 case Intrinsic::x86_sse2_comineq_sd:
11310 case Intrinsic::x86_sse2_ucomieq_sd:
11311 case Intrinsic::x86_sse2_ucomilt_sd:
11312 case Intrinsic::x86_sse2_ucomile_sd:
11313 case Intrinsic::x86_sse2_ucomigt_sd:
11314 case Intrinsic::x86_sse2_ucomige_sd:
11315 case Intrinsic::x86_sse2_ucomineq_sd: {
11319 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11320 case Intrinsic::x86_sse_comieq_ss:
11321 case Intrinsic::x86_sse2_comieq_sd:
11322 Opc = X86ISD::COMI;
11325 case Intrinsic::x86_sse_comilt_ss:
11326 case Intrinsic::x86_sse2_comilt_sd:
11327 Opc = X86ISD::COMI;
11330 case Intrinsic::x86_sse_comile_ss:
11331 case Intrinsic::x86_sse2_comile_sd:
11332 Opc = X86ISD::COMI;
11335 case Intrinsic::x86_sse_comigt_ss:
11336 case Intrinsic::x86_sse2_comigt_sd:
11337 Opc = X86ISD::COMI;
11340 case Intrinsic::x86_sse_comige_ss:
11341 case Intrinsic::x86_sse2_comige_sd:
11342 Opc = X86ISD::COMI;
11345 case Intrinsic::x86_sse_comineq_ss:
11346 case Intrinsic::x86_sse2_comineq_sd:
11347 Opc = X86ISD::COMI;
11350 case Intrinsic::x86_sse_ucomieq_ss:
11351 case Intrinsic::x86_sse2_ucomieq_sd:
11352 Opc = X86ISD::UCOMI;
11355 case Intrinsic::x86_sse_ucomilt_ss:
11356 case Intrinsic::x86_sse2_ucomilt_sd:
11357 Opc = X86ISD::UCOMI;
11360 case Intrinsic::x86_sse_ucomile_ss:
11361 case Intrinsic::x86_sse2_ucomile_sd:
11362 Opc = X86ISD::UCOMI;
11365 case Intrinsic::x86_sse_ucomigt_ss:
11366 case Intrinsic::x86_sse2_ucomigt_sd:
11367 Opc = X86ISD::UCOMI;
11370 case Intrinsic::x86_sse_ucomige_ss:
11371 case Intrinsic::x86_sse2_ucomige_sd:
11372 Opc = X86ISD::UCOMI;
11375 case Intrinsic::x86_sse_ucomineq_ss:
11376 case Intrinsic::x86_sse2_ucomineq_sd:
11377 Opc = X86ISD::UCOMI;
11382 SDValue LHS = Op.getOperand(1);
11383 SDValue RHS = Op.getOperand(2);
11384 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
11385 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
11386 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
11387 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
11388 DAG.getConstant(X86CC, MVT::i8), Cond);
11389 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
11392 // Arithmetic intrinsics.
11393 case Intrinsic::x86_sse2_pmulu_dq:
11394 case Intrinsic::x86_avx2_pmulu_dq:
11395 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
11396 Op.getOperand(1), Op.getOperand(2));
11398 // SSE2/AVX2 sub with unsigned saturation intrinsics
11399 case Intrinsic::x86_sse2_psubus_b:
11400 case Intrinsic::x86_sse2_psubus_w:
11401 case Intrinsic::x86_avx2_psubus_b:
11402 case Intrinsic::x86_avx2_psubus_w:
11403 return DAG.getNode(X86ISD::SUBUS, dl, Op.getValueType(),
11404 Op.getOperand(1), Op.getOperand(2));
11406 // SSE3/AVX horizontal add/sub intrinsics
11407 case Intrinsic::x86_sse3_hadd_ps:
11408 case Intrinsic::x86_sse3_hadd_pd:
11409 case Intrinsic::x86_avx_hadd_ps_256:
11410 case Intrinsic::x86_avx_hadd_pd_256:
11411 case Intrinsic::x86_sse3_hsub_ps:
11412 case Intrinsic::x86_sse3_hsub_pd:
11413 case Intrinsic::x86_avx_hsub_ps_256:
11414 case Intrinsic::x86_avx_hsub_pd_256:
11415 case Intrinsic::x86_ssse3_phadd_w_128:
11416 case Intrinsic::x86_ssse3_phadd_d_128:
11417 case Intrinsic::x86_avx2_phadd_w:
11418 case Intrinsic::x86_avx2_phadd_d:
11419 case Intrinsic::x86_ssse3_phsub_w_128:
11420 case Intrinsic::x86_ssse3_phsub_d_128:
11421 case Intrinsic::x86_avx2_phsub_w:
11422 case Intrinsic::x86_avx2_phsub_d: {
11425 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11426 case Intrinsic::x86_sse3_hadd_ps:
11427 case Intrinsic::x86_sse3_hadd_pd:
11428 case Intrinsic::x86_avx_hadd_ps_256:
11429 case Intrinsic::x86_avx_hadd_pd_256:
11430 Opcode = X86ISD::FHADD;
11432 case Intrinsic::x86_sse3_hsub_ps:
11433 case Intrinsic::x86_sse3_hsub_pd:
11434 case Intrinsic::x86_avx_hsub_ps_256:
11435 case Intrinsic::x86_avx_hsub_pd_256:
11436 Opcode = X86ISD::FHSUB;
11438 case Intrinsic::x86_ssse3_phadd_w_128:
11439 case Intrinsic::x86_ssse3_phadd_d_128:
11440 case Intrinsic::x86_avx2_phadd_w:
11441 case Intrinsic::x86_avx2_phadd_d:
11442 Opcode = X86ISD::HADD;
11444 case Intrinsic::x86_ssse3_phsub_w_128:
11445 case Intrinsic::x86_ssse3_phsub_d_128:
11446 case Intrinsic::x86_avx2_phsub_w:
11447 case Intrinsic::x86_avx2_phsub_d:
11448 Opcode = X86ISD::HSUB;
11451 return DAG.getNode(Opcode, dl, Op.getValueType(),
11452 Op.getOperand(1), Op.getOperand(2));
11455 // SSE2/SSE41/AVX2 integer max/min intrinsics.
11456 case Intrinsic::x86_sse2_pmaxu_b:
11457 case Intrinsic::x86_sse41_pmaxuw:
11458 case Intrinsic::x86_sse41_pmaxud:
11459 case Intrinsic::x86_avx2_pmaxu_b:
11460 case Intrinsic::x86_avx2_pmaxu_w:
11461 case Intrinsic::x86_avx2_pmaxu_d:
11462 case Intrinsic::x86_sse2_pminu_b:
11463 case Intrinsic::x86_sse41_pminuw:
11464 case Intrinsic::x86_sse41_pminud:
11465 case Intrinsic::x86_avx2_pminu_b:
11466 case Intrinsic::x86_avx2_pminu_w:
11467 case Intrinsic::x86_avx2_pminu_d:
11468 case Intrinsic::x86_sse41_pmaxsb:
11469 case Intrinsic::x86_sse2_pmaxs_w:
11470 case Intrinsic::x86_sse41_pmaxsd:
11471 case Intrinsic::x86_avx2_pmaxs_b:
11472 case Intrinsic::x86_avx2_pmaxs_w:
11473 case Intrinsic::x86_avx2_pmaxs_d:
11474 case Intrinsic::x86_sse41_pminsb:
11475 case Intrinsic::x86_sse2_pmins_w:
11476 case Intrinsic::x86_sse41_pminsd:
11477 case Intrinsic::x86_avx2_pmins_b:
11478 case Intrinsic::x86_avx2_pmins_w:
11479 case Intrinsic::x86_avx2_pmins_d: {
11482 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11483 case Intrinsic::x86_sse2_pmaxu_b:
11484 case Intrinsic::x86_sse41_pmaxuw:
11485 case Intrinsic::x86_sse41_pmaxud:
11486 case Intrinsic::x86_avx2_pmaxu_b:
11487 case Intrinsic::x86_avx2_pmaxu_w:
11488 case Intrinsic::x86_avx2_pmaxu_d:
11489 Opcode = X86ISD::UMAX;
11491 case Intrinsic::x86_sse2_pminu_b:
11492 case Intrinsic::x86_sse41_pminuw:
11493 case Intrinsic::x86_sse41_pminud:
11494 case Intrinsic::x86_avx2_pminu_b:
11495 case Intrinsic::x86_avx2_pminu_w:
11496 case Intrinsic::x86_avx2_pminu_d:
11497 Opcode = X86ISD::UMIN;
11499 case Intrinsic::x86_sse41_pmaxsb:
11500 case Intrinsic::x86_sse2_pmaxs_w:
11501 case Intrinsic::x86_sse41_pmaxsd:
11502 case Intrinsic::x86_avx2_pmaxs_b:
11503 case Intrinsic::x86_avx2_pmaxs_w:
11504 case Intrinsic::x86_avx2_pmaxs_d:
11505 Opcode = X86ISD::SMAX;
11507 case Intrinsic::x86_sse41_pminsb:
11508 case Intrinsic::x86_sse2_pmins_w:
11509 case Intrinsic::x86_sse41_pminsd:
11510 case Intrinsic::x86_avx2_pmins_b:
11511 case Intrinsic::x86_avx2_pmins_w:
11512 case Intrinsic::x86_avx2_pmins_d:
11513 Opcode = X86ISD::SMIN;
11516 return DAG.getNode(Opcode, dl, Op.getValueType(),
11517 Op.getOperand(1), Op.getOperand(2));
11520 // SSE/SSE2/AVX floating point max/min intrinsics.
11521 case Intrinsic::x86_sse_max_ps:
11522 case Intrinsic::x86_sse2_max_pd:
11523 case Intrinsic::x86_avx_max_ps_256:
11524 case Intrinsic::x86_avx_max_pd_256:
11525 case Intrinsic::x86_sse_min_ps:
11526 case Intrinsic::x86_sse2_min_pd:
11527 case Intrinsic::x86_avx_min_ps_256:
11528 case Intrinsic::x86_avx_min_pd_256: {
11531 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11532 case Intrinsic::x86_sse_max_ps:
11533 case Intrinsic::x86_sse2_max_pd:
11534 case Intrinsic::x86_avx_max_ps_256:
11535 case Intrinsic::x86_avx_max_pd_256:
11536 Opcode = X86ISD::FMAX;
11538 case Intrinsic::x86_sse_min_ps:
11539 case Intrinsic::x86_sse2_min_pd:
11540 case Intrinsic::x86_avx_min_ps_256:
11541 case Intrinsic::x86_avx_min_pd_256:
11542 Opcode = X86ISD::FMIN;
11545 return DAG.getNode(Opcode, dl, Op.getValueType(),
11546 Op.getOperand(1), Op.getOperand(2));
11549 // AVX2 variable shift intrinsics
11550 case Intrinsic::x86_avx2_psllv_d:
11551 case Intrinsic::x86_avx2_psllv_q:
11552 case Intrinsic::x86_avx2_psllv_d_256:
11553 case Intrinsic::x86_avx2_psllv_q_256:
11554 case Intrinsic::x86_avx2_psrlv_d:
11555 case Intrinsic::x86_avx2_psrlv_q:
11556 case Intrinsic::x86_avx2_psrlv_d_256:
11557 case Intrinsic::x86_avx2_psrlv_q_256:
11558 case Intrinsic::x86_avx2_psrav_d:
11559 case Intrinsic::x86_avx2_psrav_d_256: {
11562 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11563 case Intrinsic::x86_avx2_psllv_d:
11564 case Intrinsic::x86_avx2_psllv_q:
11565 case Intrinsic::x86_avx2_psllv_d_256:
11566 case Intrinsic::x86_avx2_psllv_q_256:
11569 case Intrinsic::x86_avx2_psrlv_d:
11570 case Intrinsic::x86_avx2_psrlv_q:
11571 case Intrinsic::x86_avx2_psrlv_d_256:
11572 case Intrinsic::x86_avx2_psrlv_q_256:
11575 case Intrinsic::x86_avx2_psrav_d:
11576 case Intrinsic::x86_avx2_psrav_d_256:
11580 return DAG.getNode(Opcode, dl, Op.getValueType(),
11581 Op.getOperand(1), Op.getOperand(2));
11584 case Intrinsic::x86_ssse3_pshuf_b_128:
11585 case Intrinsic::x86_avx2_pshuf_b:
11586 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
11587 Op.getOperand(1), Op.getOperand(2));
11589 case Intrinsic::x86_ssse3_psign_b_128:
11590 case Intrinsic::x86_ssse3_psign_w_128:
11591 case Intrinsic::x86_ssse3_psign_d_128:
11592 case Intrinsic::x86_avx2_psign_b:
11593 case Intrinsic::x86_avx2_psign_w:
11594 case Intrinsic::x86_avx2_psign_d:
11595 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
11596 Op.getOperand(1), Op.getOperand(2));
11598 case Intrinsic::x86_sse41_insertps:
11599 return DAG.getNode(X86ISD::INSERTPS, dl, Op.getValueType(),
11600 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
11602 case Intrinsic::x86_avx_vperm2f128_ps_256:
11603 case Intrinsic::x86_avx_vperm2f128_pd_256:
11604 case Intrinsic::x86_avx_vperm2f128_si_256:
11605 case Intrinsic::x86_avx2_vperm2i128:
11606 return DAG.getNode(X86ISD::VPERM2X128, dl, Op.getValueType(),
11607 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
11609 case Intrinsic::x86_avx2_permd:
11610 case Intrinsic::x86_avx2_permps:
11611 // Operands intentionally swapped. Mask is last operand to intrinsic,
11612 // but second operand for node/instruction.
11613 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
11614 Op.getOperand(2), Op.getOperand(1));
11616 case Intrinsic::x86_sse_sqrt_ps:
11617 case Intrinsic::x86_sse2_sqrt_pd:
11618 case Intrinsic::x86_avx_sqrt_ps_256:
11619 case Intrinsic::x86_avx_sqrt_pd_256:
11620 return DAG.getNode(ISD::FSQRT, dl, Op.getValueType(), Op.getOperand(1));
11622 // ptest and testp intrinsics. The intrinsic these come from are designed to
11623 // return an integer value, not just an instruction so lower it to the ptest
11624 // or testp pattern and a setcc for the result.
11625 case Intrinsic::x86_sse41_ptestz:
11626 case Intrinsic::x86_sse41_ptestc:
11627 case Intrinsic::x86_sse41_ptestnzc:
11628 case Intrinsic::x86_avx_ptestz_256:
11629 case Intrinsic::x86_avx_ptestc_256:
11630 case Intrinsic::x86_avx_ptestnzc_256:
11631 case Intrinsic::x86_avx_vtestz_ps:
11632 case Intrinsic::x86_avx_vtestc_ps:
11633 case Intrinsic::x86_avx_vtestnzc_ps:
11634 case Intrinsic::x86_avx_vtestz_pd:
11635 case Intrinsic::x86_avx_vtestc_pd:
11636 case Intrinsic::x86_avx_vtestnzc_pd:
11637 case Intrinsic::x86_avx_vtestz_ps_256:
11638 case Intrinsic::x86_avx_vtestc_ps_256:
11639 case Intrinsic::x86_avx_vtestnzc_ps_256:
11640 case Intrinsic::x86_avx_vtestz_pd_256:
11641 case Intrinsic::x86_avx_vtestc_pd_256:
11642 case Intrinsic::x86_avx_vtestnzc_pd_256: {
11643 bool IsTestPacked = false;
11646 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
11647 case Intrinsic::x86_avx_vtestz_ps:
11648 case Intrinsic::x86_avx_vtestz_pd:
11649 case Intrinsic::x86_avx_vtestz_ps_256:
11650 case Intrinsic::x86_avx_vtestz_pd_256:
11651 IsTestPacked = true; // Fallthrough
11652 case Intrinsic::x86_sse41_ptestz:
11653 case Intrinsic::x86_avx_ptestz_256:
11655 X86CC = X86::COND_E;
11657 case Intrinsic::x86_avx_vtestc_ps:
11658 case Intrinsic::x86_avx_vtestc_pd:
11659 case Intrinsic::x86_avx_vtestc_ps_256:
11660 case Intrinsic::x86_avx_vtestc_pd_256:
11661 IsTestPacked = true; // Fallthrough
11662 case Intrinsic::x86_sse41_ptestc:
11663 case Intrinsic::x86_avx_ptestc_256:
11665 X86CC = X86::COND_B;
11667 case Intrinsic::x86_avx_vtestnzc_ps:
11668 case Intrinsic::x86_avx_vtestnzc_pd:
11669 case Intrinsic::x86_avx_vtestnzc_ps_256:
11670 case Intrinsic::x86_avx_vtestnzc_pd_256:
11671 IsTestPacked = true; // Fallthrough
11672 case Intrinsic::x86_sse41_ptestnzc:
11673 case Intrinsic::x86_avx_ptestnzc_256:
11675 X86CC = X86::COND_A;
11679 SDValue LHS = Op.getOperand(1);
11680 SDValue RHS = Op.getOperand(2);
11681 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
11682 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
11683 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
11684 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
11685 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
11687 case Intrinsic::x86_avx512_kortestz_w:
11688 case Intrinsic::x86_avx512_kortestc_w: {
11689 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
11690 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
11691 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
11692 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
11693 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
11694 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
11695 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
11698 // SSE/AVX shift intrinsics
11699 case Intrinsic::x86_sse2_psll_w:
11700 case Intrinsic::x86_sse2_psll_d:
11701 case Intrinsic::x86_sse2_psll_q:
11702 case Intrinsic::x86_avx2_psll_w:
11703 case Intrinsic::x86_avx2_psll_d:
11704 case Intrinsic::x86_avx2_psll_q:
11705 case Intrinsic::x86_sse2_psrl_w:
11706 case Intrinsic::x86_sse2_psrl_d:
11707 case Intrinsic::x86_sse2_psrl_q:
11708 case Intrinsic::x86_avx2_psrl_w:
11709 case Intrinsic::x86_avx2_psrl_d:
11710 case Intrinsic::x86_avx2_psrl_q:
11711 case Intrinsic::x86_sse2_psra_w:
11712 case Intrinsic::x86_sse2_psra_d:
11713 case Intrinsic::x86_avx2_psra_w:
11714 case Intrinsic::x86_avx2_psra_d: {
11717 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11718 case Intrinsic::x86_sse2_psll_w:
11719 case Intrinsic::x86_sse2_psll_d:
11720 case Intrinsic::x86_sse2_psll_q:
11721 case Intrinsic::x86_avx2_psll_w:
11722 case Intrinsic::x86_avx2_psll_d:
11723 case Intrinsic::x86_avx2_psll_q:
11724 Opcode = X86ISD::VSHL;
11726 case Intrinsic::x86_sse2_psrl_w:
11727 case Intrinsic::x86_sse2_psrl_d:
11728 case Intrinsic::x86_sse2_psrl_q:
11729 case Intrinsic::x86_avx2_psrl_w:
11730 case Intrinsic::x86_avx2_psrl_d:
11731 case Intrinsic::x86_avx2_psrl_q:
11732 Opcode = X86ISD::VSRL;
11734 case Intrinsic::x86_sse2_psra_w:
11735 case Intrinsic::x86_sse2_psra_d:
11736 case Intrinsic::x86_avx2_psra_w:
11737 case Intrinsic::x86_avx2_psra_d:
11738 Opcode = X86ISD::VSRA;
11741 return DAG.getNode(Opcode, dl, Op.getValueType(),
11742 Op.getOperand(1), Op.getOperand(2));
11745 // SSE/AVX immediate shift intrinsics
11746 case Intrinsic::x86_sse2_pslli_w:
11747 case Intrinsic::x86_sse2_pslli_d:
11748 case Intrinsic::x86_sse2_pslli_q:
11749 case Intrinsic::x86_avx2_pslli_w:
11750 case Intrinsic::x86_avx2_pslli_d:
11751 case Intrinsic::x86_avx2_pslli_q:
11752 case Intrinsic::x86_sse2_psrli_w:
11753 case Intrinsic::x86_sse2_psrli_d:
11754 case Intrinsic::x86_sse2_psrli_q:
11755 case Intrinsic::x86_avx2_psrli_w:
11756 case Intrinsic::x86_avx2_psrli_d:
11757 case Intrinsic::x86_avx2_psrli_q:
11758 case Intrinsic::x86_sse2_psrai_w:
11759 case Intrinsic::x86_sse2_psrai_d:
11760 case Intrinsic::x86_avx2_psrai_w:
11761 case Intrinsic::x86_avx2_psrai_d: {
11764 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11765 case Intrinsic::x86_sse2_pslli_w:
11766 case Intrinsic::x86_sse2_pslli_d:
11767 case Intrinsic::x86_sse2_pslli_q:
11768 case Intrinsic::x86_avx2_pslli_w:
11769 case Intrinsic::x86_avx2_pslli_d:
11770 case Intrinsic::x86_avx2_pslli_q:
11771 Opcode = X86ISD::VSHLI;
11773 case Intrinsic::x86_sse2_psrli_w:
11774 case Intrinsic::x86_sse2_psrli_d:
11775 case Intrinsic::x86_sse2_psrli_q:
11776 case Intrinsic::x86_avx2_psrli_w:
11777 case Intrinsic::x86_avx2_psrli_d:
11778 case Intrinsic::x86_avx2_psrli_q:
11779 Opcode = X86ISD::VSRLI;
11781 case Intrinsic::x86_sse2_psrai_w:
11782 case Intrinsic::x86_sse2_psrai_d:
11783 case Intrinsic::x86_avx2_psrai_w:
11784 case Intrinsic::x86_avx2_psrai_d:
11785 Opcode = X86ISD::VSRAI;
11788 return getTargetVShiftNode(Opcode, dl, Op.getSimpleValueType(),
11789 Op.getOperand(1), Op.getOperand(2), DAG);
11792 case Intrinsic::x86_sse42_pcmpistria128:
11793 case Intrinsic::x86_sse42_pcmpestria128:
11794 case Intrinsic::x86_sse42_pcmpistric128:
11795 case Intrinsic::x86_sse42_pcmpestric128:
11796 case Intrinsic::x86_sse42_pcmpistrio128:
11797 case Intrinsic::x86_sse42_pcmpestrio128:
11798 case Intrinsic::x86_sse42_pcmpistris128:
11799 case Intrinsic::x86_sse42_pcmpestris128:
11800 case Intrinsic::x86_sse42_pcmpistriz128:
11801 case Intrinsic::x86_sse42_pcmpestriz128: {
11805 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11806 case Intrinsic::x86_sse42_pcmpistria128:
11807 Opcode = X86ISD::PCMPISTRI;
11808 X86CC = X86::COND_A;
11810 case Intrinsic::x86_sse42_pcmpestria128:
11811 Opcode = X86ISD::PCMPESTRI;
11812 X86CC = X86::COND_A;
11814 case Intrinsic::x86_sse42_pcmpistric128:
11815 Opcode = X86ISD::PCMPISTRI;
11816 X86CC = X86::COND_B;
11818 case Intrinsic::x86_sse42_pcmpestric128:
11819 Opcode = X86ISD::PCMPESTRI;
11820 X86CC = X86::COND_B;
11822 case Intrinsic::x86_sse42_pcmpistrio128:
11823 Opcode = X86ISD::PCMPISTRI;
11824 X86CC = X86::COND_O;
11826 case Intrinsic::x86_sse42_pcmpestrio128:
11827 Opcode = X86ISD::PCMPESTRI;
11828 X86CC = X86::COND_O;
11830 case Intrinsic::x86_sse42_pcmpistris128:
11831 Opcode = X86ISD::PCMPISTRI;
11832 X86CC = X86::COND_S;
11834 case Intrinsic::x86_sse42_pcmpestris128:
11835 Opcode = X86ISD::PCMPESTRI;
11836 X86CC = X86::COND_S;
11838 case Intrinsic::x86_sse42_pcmpistriz128:
11839 Opcode = X86ISD::PCMPISTRI;
11840 X86CC = X86::COND_E;
11842 case Intrinsic::x86_sse42_pcmpestriz128:
11843 Opcode = X86ISD::PCMPESTRI;
11844 X86CC = X86::COND_E;
11847 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
11848 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
11849 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps.data(), NewOps.size());
11850 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
11851 DAG.getConstant(X86CC, MVT::i8),
11852 SDValue(PCMP.getNode(), 1));
11853 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
11856 case Intrinsic::x86_sse42_pcmpistri128:
11857 case Intrinsic::x86_sse42_pcmpestri128: {
11859 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
11860 Opcode = X86ISD::PCMPISTRI;
11862 Opcode = X86ISD::PCMPESTRI;
11864 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
11865 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
11866 return DAG.getNode(Opcode, dl, VTs, NewOps.data(), NewOps.size());
11868 case Intrinsic::x86_fma_vfmadd_ps:
11869 case Intrinsic::x86_fma_vfmadd_pd:
11870 case Intrinsic::x86_fma_vfmsub_ps:
11871 case Intrinsic::x86_fma_vfmsub_pd:
11872 case Intrinsic::x86_fma_vfnmadd_ps:
11873 case Intrinsic::x86_fma_vfnmadd_pd:
11874 case Intrinsic::x86_fma_vfnmsub_ps:
11875 case Intrinsic::x86_fma_vfnmsub_pd:
11876 case Intrinsic::x86_fma_vfmaddsub_ps:
11877 case Intrinsic::x86_fma_vfmaddsub_pd:
11878 case Intrinsic::x86_fma_vfmsubadd_ps:
11879 case Intrinsic::x86_fma_vfmsubadd_pd:
11880 case Intrinsic::x86_fma_vfmadd_ps_256:
11881 case Intrinsic::x86_fma_vfmadd_pd_256:
11882 case Intrinsic::x86_fma_vfmsub_ps_256:
11883 case Intrinsic::x86_fma_vfmsub_pd_256:
11884 case Intrinsic::x86_fma_vfnmadd_ps_256:
11885 case Intrinsic::x86_fma_vfnmadd_pd_256:
11886 case Intrinsic::x86_fma_vfnmsub_ps_256:
11887 case Intrinsic::x86_fma_vfnmsub_pd_256:
11888 case Intrinsic::x86_fma_vfmaddsub_ps_256:
11889 case Intrinsic::x86_fma_vfmaddsub_pd_256:
11890 case Intrinsic::x86_fma_vfmsubadd_ps_256:
11891 case Intrinsic::x86_fma_vfmsubadd_pd_256:
11892 case Intrinsic::x86_fma_vfmadd_ps_512:
11893 case Intrinsic::x86_fma_vfmadd_pd_512:
11894 case Intrinsic::x86_fma_vfmsub_ps_512:
11895 case Intrinsic::x86_fma_vfmsub_pd_512:
11896 case Intrinsic::x86_fma_vfnmadd_ps_512:
11897 case Intrinsic::x86_fma_vfnmadd_pd_512:
11898 case Intrinsic::x86_fma_vfnmsub_ps_512:
11899 case Intrinsic::x86_fma_vfnmsub_pd_512:
11900 case Intrinsic::x86_fma_vfmaddsub_ps_512:
11901 case Intrinsic::x86_fma_vfmaddsub_pd_512:
11902 case Intrinsic::x86_fma_vfmsubadd_ps_512:
11903 case Intrinsic::x86_fma_vfmsubadd_pd_512: {
11906 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11907 case Intrinsic::x86_fma_vfmadd_ps:
11908 case Intrinsic::x86_fma_vfmadd_pd:
11909 case Intrinsic::x86_fma_vfmadd_ps_256:
11910 case Intrinsic::x86_fma_vfmadd_pd_256:
11911 case Intrinsic::x86_fma_vfmadd_ps_512:
11912 case Intrinsic::x86_fma_vfmadd_pd_512:
11913 Opc = X86ISD::FMADD;
11915 case Intrinsic::x86_fma_vfmsub_ps:
11916 case Intrinsic::x86_fma_vfmsub_pd:
11917 case Intrinsic::x86_fma_vfmsub_ps_256:
11918 case Intrinsic::x86_fma_vfmsub_pd_256:
11919 case Intrinsic::x86_fma_vfmsub_ps_512:
11920 case Intrinsic::x86_fma_vfmsub_pd_512:
11921 Opc = X86ISD::FMSUB;
11923 case Intrinsic::x86_fma_vfnmadd_ps:
11924 case Intrinsic::x86_fma_vfnmadd_pd:
11925 case Intrinsic::x86_fma_vfnmadd_ps_256:
11926 case Intrinsic::x86_fma_vfnmadd_pd_256:
11927 case Intrinsic::x86_fma_vfnmadd_ps_512:
11928 case Intrinsic::x86_fma_vfnmadd_pd_512:
11929 Opc = X86ISD::FNMADD;
11931 case Intrinsic::x86_fma_vfnmsub_ps:
11932 case Intrinsic::x86_fma_vfnmsub_pd:
11933 case Intrinsic::x86_fma_vfnmsub_ps_256:
11934 case Intrinsic::x86_fma_vfnmsub_pd_256:
11935 case Intrinsic::x86_fma_vfnmsub_ps_512:
11936 case Intrinsic::x86_fma_vfnmsub_pd_512:
11937 Opc = X86ISD::FNMSUB;
11939 case Intrinsic::x86_fma_vfmaddsub_ps:
11940 case Intrinsic::x86_fma_vfmaddsub_pd:
11941 case Intrinsic::x86_fma_vfmaddsub_ps_256:
11942 case Intrinsic::x86_fma_vfmaddsub_pd_256:
11943 case Intrinsic::x86_fma_vfmaddsub_ps_512:
11944 case Intrinsic::x86_fma_vfmaddsub_pd_512:
11945 Opc = X86ISD::FMADDSUB;
11947 case Intrinsic::x86_fma_vfmsubadd_ps:
11948 case Intrinsic::x86_fma_vfmsubadd_pd:
11949 case Intrinsic::x86_fma_vfmsubadd_ps_256:
11950 case Intrinsic::x86_fma_vfmsubadd_pd_256:
11951 case Intrinsic::x86_fma_vfmsubadd_ps_512:
11952 case Intrinsic::x86_fma_vfmsubadd_pd_512:
11953 Opc = X86ISD::FMSUBADD;
11957 return DAG.getNode(Opc, dl, Op.getValueType(), Op.getOperand(1),
11958 Op.getOperand(2), Op.getOperand(3));
11963 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
11964 SDValue Base, SDValue Index,
11965 SDValue ScaleOp, SDValue Chain,
11966 const X86Subtarget * Subtarget) {
11968 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
11969 assert(C && "Invalid scale type");
11970 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
11971 SDValue Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
11972 EVT MaskVT = MVT::getVectorVT(MVT::i1,
11973 Index.getSimpleValueType().getVectorNumElements());
11974 SDValue MaskInReg = DAG.getConstant(~0, MaskVT);
11975 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
11976 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
11977 SDValue Segment = DAG.getRegister(0, MVT::i32);
11978 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
11979 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
11980 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
11981 return DAG.getMergeValues(RetOps, array_lengthof(RetOps), dl);
11984 static SDValue getMGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
11985 SDValue Src, SDValue Mask, SDValue Base,
11986 SDValue Index, SDValue ScaleOp, SDValue Chain,
11987 const X86Subtarget * Subtarget) {
11989 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
11990 assert(C && "Invalid scale type");
11991 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
11992 EVT MaskVT = MVT::getVectorVT(MVT::i1,
11993 Index.getSimpleValueType().getVectorNumElements());
11994 SDValue MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
11995 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
11996 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
11997 SDValue Segment = DAG.getRegister(0, MVT::i32);
11998 if (Src.getOpcode() == ISD::UNDEF)
11999 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
12000 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
12001 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
12002 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
12003 return DAG.getMergeValues(RetOps, array_lengthof(RetOps), dl);
12006 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
12007 SDValue Src, SDValue Base, SDValue Index,
12008 SDValue ScaleOp, SDValue Chain) {
12010 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
12011 assert(C && "Invalid scale type");
12012 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
12013 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
12014 SDValue Segment = DAG.getRegister(0, MVT::i32);
12015 EVT MaskVT = MVT::getVectorVT(MVT::i1,
12016 Index.getSimpleValueType().getVectorNumElements());
12017 SDValue MaskInReg = DAG.getConstant(~0, MaskVT);
12018 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
12019 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
12020 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
12021 return SDValue(Res, 1);
12024 static SDValue getMScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
12025 SDValue Src, SDValue Mask, SDValue Base,
12026 SDValue Index, SDValue ScaleOp, SDValue Chain) {
12028 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
12029 assert(C && "Invalid scale type");
12030 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
12031 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
12032 SDValue Segment = DAG.getRegister(0, MVT::i32);
12033 EVT MaskVT = MVT::getVectorVT(MVT::i1,
12034 Index.getSimpleValueType().getVectorNumElements());
12035 SDValue MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
12036 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
12037 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
12038 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
12039 return SDValue(Res, 1);
12042 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
12043 SelectionDAG &DAG) {
12045 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12047 default: return SDValue(); // Don't custom lower most intrinsics.
12049 // RDRAND/RDSEED intrinsics.
12050 case Intrinsic::x86_rdrand_16:
12051 case Intrinsic::x86_rdrand_32:
12052 case Intrinsic::x86_rdrand_64:
12053 case Intrinsic::x86_rdseed_16:
12054 case Intrinsic::x86_rdseed_32:
12055 case Intrinsic::x86_rdseed_64: {
12056 unsigned Opcode = (IntNo == Intrinsic::x86_rdseed_16 ||
12057 IntNo == Intrinsic::x86_rdseed_32 ||
12058 IntNo == Intrinsic::x86_rdseed_64) ? X86ISD::RDSEED :
12060 // Emit the node with the right value type.
12061 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
12062 SDValue Result = DAG.getNode(Opcode, dl, VTs, Op.getOperand(0));
12064 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
12065 // Otherwise return the value from Rand, which is always 0, casted to i32.
12066 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
12067 DAG.getConstant(1, Op->getValueType(1)),
12068 DAG.getConstant(X86::COND_B, MVT::i32),
12069 SDValue(Result.getNode(), 1) };
12070 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
12071 DAG.getVTList(Op->getValueType(1), MVT::Glue),
12072 Ops, array_lengthof(Ops));
12074 // Return { result, isValid, chain }.
12075 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
12076 SDValue(Result.getNode(), 2));
12078 //int_gather(index, base, scale);
12079 case Intrinsic::x86_avx512_gather_qpd_512:
12080 case Intrinsic::x86_avx512_gather_qps_512:
12081 case Intrinsic::x86_avx512_gather_dpd_512:
12082 case Intrinsic::x86_avx512_gather_qpi_512:
12083 case Intrinsic::x86_avx512_gather_qpq_512:
12084 case Intrinsic::x86_avx512_gather_dpq_512:
12085 case Intrinsic::x86_avx512_gather_dps_512:
12086 case Intrinsic::x86_avx512_gather_dpi_512: {
12089 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
12090 case Intrinsic::x86_avx512_gather_qps_512: Opc = X86::VGATHERQPSZrm; break;
12091 case Intrinsic::x86_avx512_gather_qpd_512: Opc = X86::VGATHERQPDZrm; break;
12092 case Intrinsic::x86_avx512_gather_dpd_512: Opc = X86::VGATHERDPDZrm; break;
12093 case Intrinsic::x86_avx512_gather_dps_512: Opc = X86::VGATHERDPSZrm; break;
12094 case Intrinsic::x86_avx512_gather_qpi_512: Opc = X86::VPGATHERQDZrm; break;
12095 case Intrinsic::x86_avx512_gather_qpq_512: Opc = X86::VPGATHERQQZrm; break;
12096 case Intrinsic::x86_avx512_gather_dpi_512: Opc = X86::VPGATHERDDZrm; break;
12097 case Intrinsic::x86_avx512_gather_dpq_512: Opc = X86::VPGATHERDQZrm; break;
12099 SDValue Chain = Op.getOperand(0);
12100 SDValue Index = Op.getOperand(2);
12101 SDValue Base = Op.getOperand(3);
12102 SDValue Scale = Op.getOperand(4);
12103 return getGatherNode(Opc, Op, DAG, Base, Index, Scale, Chain, Subtarget);
12105 //int_gather_mask(v1, mask, index, base, scale);
12106 case Intrinsic::x86_avx512_gather_qps_mask_512:
12107 case Intrinsic::x86_avx512_gather_qpd_mask_512:
12108 case Intrinsic::x86_avx512_gather_dpd_mask_512:
12109 case Intrinsic::x86_avx512_gather_dps_mask_512:
12110 case Intrinsic::x86_avx512_gather_qpi_mask_512:
12111 case Intrinsic::x86_avx512_gather_qpq_mask_512:
12112 case Intrinsic::x86_avx512_gather_dpi_mask_512:
12113 case Intrinsic::x86_avx512_gather_dpq_mask_512: {
12116 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
12117 case Intrinsic::x86_avx512_gather_qps_mask_512:
12118 Opc = X86::VGATHERQPSZrm; break;
12119 case Intrinsic::x86_avx512_gather_qpd_mask_512:
12120 Opc = X86::VGATHERQPDZrm; break;
12121 case Intrinsic::x86_avx512_gather_dpd_mask_512:
12122 Opc = X86::VGATHERDPDZrm; break;
12123 case Intrinsic::x86_avx512_gather_dps_mask_512:
12124 Opc = X86::VGATHERDPSZrm; break;
12125 case Intrinsic::x86_avx512_gather_qpi_mask_512:
12126 Opc = X86::VPGATHERQDZrm; break;
12127 case Intrinsic::x86_avx512_gather_qpq_mask_512:
12128 Opc = X86::VPGATHERQQZrm; break;
12129 case Intrinsic::x86_avx512_gather_dpi_mask_512:
12130 Opc = X86::VPGATHERDDZrm; break;
12131 case Intrinsic::x86_avx512_gather_dpq_mask_512:
12132 Opc = X86::VPGATHERDQZrm; break;
12134 SDValue Chain = Op.getOperand(0);
12135 SDValue Src = Op.getOperand(2);
12136 SDValue Mask = Op.getOperand(3);
12137 SDValue Index = Op.getOperand(4);
12138 SDValue Base = Op.getOperand(5);
12139 SDValue Scale = Op.getOperand(6);
12140 return getMGatherNode(Opc, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
12143 //int_scatter(base, index, v1, scale);
12144 case Intrinsic::x86_avx512_scatter_qpd_512:
12145 case Intrinsic::x86_avx512_scatter_qps_512:
12146 case Intrinsic::x86_avx512_scatter_dpd_512:
12147 case Intrinsic::x86_avx512_scatter_qpi_512:
12148 case Intrinsic::x86_avx512_scatter_qpq_512:
12149 case Intrinsic::x86_avx512_scatter_dpq_512:
12150 case Intrinsic::x86_avx512_scatter_dps_512:
12151 case Intrinsic::x86_avx512_scatter_dpi_512: {
12154 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
12155 case Intrinsic::x86_avx512_scatter_qpd_512:
12156 Opc = X86::VSCATTERQPDZmr; break;
12157 case Intrinsic::x86_avx512_scatter_qps_512:
12158 Opc = X86::VSCATTERQPSZmr; break;
12159 case Intrinsic::x86_avx512_scatter_dpd_512:
12160 Opc = X86::VSCATTERDPDZmr; break;
12161 case Intrinsic::x86_avx512_scatter_dps_512:
12162 Opc = X86::VSCATTERDPSZmr; break;
12163 case Intrinsic::x86_avx512_scatter_qpi_512:
12164 Opc = X86::VPSCATTERQDZmr; break;
12165 case Intrinsic::x86_avx512_scatter_qpq_512:
12166 Opc = X86::VPSCATTERQQZmr; break;
12167 case Intrinsic::x86_avx512_scatter_dpq_512:
12168 Opc = X86::VPSCATTERDQZmr; break;
12169 case Intrinsic::x86_avx512_scatter_dpi_512:
12170 Opc = X86::VPSCATTERDDZmr; break;
12172 SDValue Chain = Op.getOperand(0);
12173 SDValue Base = Op.getOperand(2);
12174 SDValue Index = Op.getOperand(3);
12175 SDValue Src = Op.getOperand(4);
12176 SDValue Scale = Op.getOperand(5);
12177 return getScatterNode(Opc, Op, DAG, Src, Base, Index, Scale, Chain);
12179 //int_scatter_mask(base, mask, index, v1, scale);
12180 case Intrinsic::x86_avx512_scatter_qps_mask_512:
12181 case Intrinsic::x86_avx512_scatter_qpd_mask_512:
12182 case Intrinsic::x86_avx512_scatter_dpd_mask_512:
12183 case Intrinsic::x86_avx512_scatter_dps_mask_512:
12184 case Intrinsic::x86_avx512_scatter_qpi_mask_512:
12185 case Intrinsic::x86_avx512_scatter_qpq_mask_512:
12186 case Intrinsic::x86_avx512_scatter_dpi_mask_512:
12187 case Intrinsic::x86_avx512_scatter_dpq_mask_512: {
12190 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
12191 case Intrinsic::x86_avx512_scatter_qpd_mask_512:
12192 Opc = X86::VSCATTERQPDZmr; break;
12193 case Intrinsic::x86_avx512_scatter_qps_mask_512:
12194 Opc = X86::VSCATTERQPSZmr; break;
12195 case Intrinsic::x86_avx512_scatter_dpd_mask_512:
12196 Opc = X86::VSCATTERDPDZmr; break;
12197 case Intrinsic::x86_avx512_scatter_dps_mask_512:
12198 Opc = X86::VSCATTERDPSZmr; break;
12199 case Intrinsic::x86_avx512_scatter_qpi_mask_512:
12200 Opc = X86::VPSCATTERQDZmr; break;
12201 case Intrinsic::x86_avx512_scatter_qpq_mask_512:
12202 Opc = X86::VPSCATTERQQZmr; break;
12203 case Intrinsic::x86_avx512_scatter_dpq_mask_512:
12204 Opc = X86::VPSCATTERDQZmr; break;
12205 case Intrinsic::x86_avx512_scatter_dpi_mask_512:
12206 Opc = X86::VPSCATTERDDZmr; break;
12208 SDValue Chain = Op.getOperand(0);
12209 SDValue Base = Op.getOperand(2);
12210 SDValue Mask = Op.getOperand(3);
12211 SDValue Index = Op.getOperand(4);
12212 SDValue Src = Op.getOperand(5);
12213 SDValue Scale = Op.getOperand(6);
12214 return getMScatterNode(Opc, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
12216 // XTEST intrinsics.
12217 case Intrinsic::x86_xtest: {
12218 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
12219 SDValue InTrans = DAG.getNode(X86ISD::XTEST, dl, VTs, Op.getOperand(0));
12220 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
12221 DAG.getConstant(X86::COND_NE, MVT::i8),
12223 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
12224 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
12225 Ret, SDValue(InTrans.getNode(), 1));
12230 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
12231 SelectionDAG &DAG) const {
12232 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12233 MFI->setReturnAddressIsTaken(true);
12235 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
12238 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
12240 EVT PtrVT = getPointerTy();
12243 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
12244 const X86RegisterInfo *RegInfo =
12245 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
12246 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
12247 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
12248 DAG.getNode(ISD::ADD, dl, PtrVT,
12249 FrameAddr, Offset),
12250 MachinePointerInfo(), false, false, false, 0);
12253 // Just load the return address.
12254 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
12255 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
12256 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
12259 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
12260 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12261 MFI->setFrameAddressIsTaken(true);
12263 EVT VT = Op.getValueType();
12264 SDLoc dl(Op); // FIXME probably not meaningful
12265 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
12266 const X86RegisterInfo *RegInfo =
12267 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
12268 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
12269 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
12270 (FrameReg == X86::EBP && VT == MVT::i32)) &&
12271 "Invalid Frame Register!");
12272 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
12274 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
12275 MachinePointerInfo(),
12276 false, false, false, 0);
12280 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
12281 SelectionDAG &DAG) const {
12282 const X86RegisterInfo *RegInfo =
12283 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
12284 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
12287 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
12288 SDValue Chain = Op.getOperand(0);
12289 SDValue Offset = Op.getOperand(1);
12290 SDValue Handler = Op.getOperand(2);
12293 EVT PtrVT = getPointerTy();
12294 const X86RegisterInfo *RegInfo =
12295 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
12296 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
12297 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
12298 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
12299 "Invalid Frame Register!");
12300 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
12301 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
12303 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
12304 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
12305 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
12306 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
12308 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
12310 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
12311 DAG.getRegister(StoreAddrReg, PtrVT));
12314 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
12315 SelectionDAG &DAG) const {
12317 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
12318 DAG.getVTList(MVT::i32, MVT::Other),
12319 Op.getOperand(0), Op.getOperand(1));
12322 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
12323 SelectionDAG &DAG) const {
12325 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
12326 Op.getOperand(0), Op.getOperand(1));
12329 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
12330 return Op.getOperand(0);
12333 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
12334 SelectionDAG &DAG) const {
12335 SDValue Root = Op.getOperand(0);
12336 SDValue Trmp = Op.getOperand(1); // trampoline
12337 SDValue FPtr = Op.getOperand(2); // nested function
12338 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
12341 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
12342 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
12344 if (Subtarget->is64Bit()) {
12345 SDValue OutChains[6];
12347 // Large code-model.
12348 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
12349 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
12351 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
12352 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
12354 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
12356 // Load the pointer to the nested function into R11.
12357 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
12358 SDValue Addr = Trmp;
12359 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
12360 Addr, MachinePointerInfo(TrmpAddr),
12363 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
12364 DAG.getConstant(2, MVT::i64));
12365 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
12366 MachinePointerInfo(TrmpAddr, 2),
12369 // Load the 'nest' parameter value into R10.
12370 // R10 is specified in X86CallingConv.td
12371 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
12372 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
12373 DAG.getConstant(10, MVT::i64));
12374 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
12375 Addr, MachinePointerInfo(TrmpAddr, 10),
12378 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
12379 DAG.getConstant(12, MVT::i64));
12380 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
12381 MachinePointerInfo(TrmpAddr, 12),
12384 // Jump to the nested function.
12385 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
12386 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
12387 DAG.getConstant(20, MVT::i64));
12388 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
12389 Addr, MachinePointerInfo(TrmpAddr, 20),
12392 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
12393 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
12394 DAG.getConstant(22, MVT::i64));
12395 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
12396 MachinePointerInfo(TrmpAddr, 22),
12399 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6);
12401 const Function *Func =
12402 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
12403 CallingConv::ID CC = Func->getCallingConv();
12408 llvm_unreachable("Unsupported calling convention");
12409 case CallingConv::C:
12410 case CallingConv::X86_StdCall: {
12411 // Pass 'nest' parameter in ECX.
12412 // Must be kept in sync with X86CallingConv.td
12413 NestReg = X86::ECX;
12415 // Check that ECX wasn't needed by an 'inreg' parameter.
12416 FunctionType *FTy = Func->getFunctionType();
12417 const AttributeSet &Attrs = Func->getAttributes();
12419 if (!Attrs.isEmpty() && !Func->isVarArg()) {
12420 unsigned InRegCount = 0;
12423 for (FunctionType::param_iterator I = FTy->param_begin(),
12424 E = FTy->param_end(); I != E; ++I, ++Idx)
12425 if (Attrs.hasAttribute(Idx, Attribute::InReg))
12426 // FIXME: should only count parameters that are lowered to integers.
12427 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
12429 if (InRegCount > 2) {
12430 report_fatal_error("Nest register in use - reduce number of inreg"
12436 case CallingConv::X86_FastCall:
12437 case CallingConv::X86_ThisCall:
12438 case CallingConv::Fast:
12439 // Pass 'nest' parameter in EAX.
12440 // Must be kept in sync with X86CallingConv.td
12441 NestReg = X86::EAX;
12445 SDValue OutChains[4];
12446 SDValue Addr, Disp;
12448 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
12449 DAG.getConstant(10, MVT::i32));
12450 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
12452 // This is storing the opcode for MOV32ri.
12453 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
12454 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
12455 OutChains[0] = DAG.getStore(Root, dl,
12456 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
12457 Trmp, MachinePointerInfo(TrmpAddr),
12460 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
12461 DAG.getConstant(1, MVT::i32));
12462 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
12463 MachinePointerInfo(TrmpAddr, 1),
12466 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
12467 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
12468 DAG.getConstant(5, MVT::i32));
12469 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
12470 MachinePointerInfo(TrmpAddr, 5),
12473 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
12474 DAG.getConstant(6, MVT::i32));
12475 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
12476 MachinePointerInfo(TrmpAddr, 6),
12479 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4);
12483 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
12484 SelectionDAG &DAG) const {
12486 The rounding mode is in bits 11:10 of FPSR, and has the following
12488 00 Round to nearest
12493 FLT_ROUNDS, on the other hand, expects the following:
12500 To perform the conversion, we do:
12501 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
12504 MachineFunction &MF = DAG.getMachineFunction();
12505 const TargetMachine &TM = MF.getTarget();
12506 const TargetFrameLowering &TFI = *TM.getFrameLowering();
12507 unsigned StackAlignment = TFI.getStackAlignment();
12508 MVT VT = Op.getSimpleValueType();
12511 // Save FP Control Word to stack slot
12512 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
12513 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12515 MachineMemOperand *MMO =
12516 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12517 MachineMemOperand::MOStore, 2, 2);
12519 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
12520 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
12521 DAG.getVTList(MVT::Other),
12522 Ops, array_lengthof(Ops), MVT::i16,
12525 // Load FP Control Word from stack slot
12526 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
12527 MachinePointerInfo(), false, false, false, 0);
12529 // Transform as necessary
12531 DAG.getNode(ISD::SRL, DL, MVT::i16,
12532 DAG.getNode(ISD::AND, DL, MVT::i16,
12533 CWD, DAG.getConstant(0x800, MVT::i16)),
12534 DAG.getConstant(11, MVT::i8));
12536 DAG.getNode(ISD::SRL, DL, MVT::i16,
12537 DAG.getNode(ISD::AND, DL, MVT::i16,
12538 CWD, DAG.getConstant(0x400, MVT::i16)),
12539 DAG.getConstant(9, MVT::i8));
12542 DAG.getNode(ISD::AND, DL, MVT::i16,
12543 DAG.getNode(ISD::ADD, DL, MVT::i16,
12544 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
12545 DAG.getConstant(1, MVT::i16)),
12546 DAG.getConstant(3, MVT::i16));
12548 return DAG.getNode((VT.getSizeInBits() < 16 ?
12549 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
12552 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
12553 MVT VT = Op.getSimpleValueType();
12555 unsigned NumBits = VT.getSizeInBits();
12558 Op = Op.getOperand(0);
12559 if (VT == MVT::i8) {
12560 // Zero extend to i32 since there is not an i8 bsr.
12562 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
12565 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
12566 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
12567 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
12569 // If src is zero (i.e. bsr sets ZF), returns NumBits.
12572 DAG.getConstant(NumBits+NumBits-1, OpVT),
12573 DAG.getConstant(X86::COND_E, MVT::i8),
12576 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
12578 // Finally xor with NumBits-1.
12579 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
12582 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
12586 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
12587 MVT VT = Op.getSimpleValueType();
12589 unsigned NumBits = VT.getSizeInBits();
12592 Op = Op.getOperand(0);
12593 if (VT == MVT::i8) {
12594 // Zero extend to i32 since there is not an i8 bsr.
12596 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
12599 // Issue a bsr (scan bits in reverse).
12600 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
12601 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
12603 // And xor with NumBits-1.
12604 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
12607 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
12611 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
12612 MVT VT = Op.getSimpleValueType();
12613 unsigned NumBits = VT.getSizeInBits();
12615 Op = Op.getOperand(0);
12617 // Issue a bsf (scan bits forward) which also sets EFLAGS.
12618 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
12619 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
12621 // If src is zero (i.e. bsf sets ZF), returns NumBits.
12624 DAG.getConstant(NumBits, VT),
12625 DAG.getConstant(X86::COND_E, MVT::i8),
12628 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops, array_lengthof(Ops));
12631 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
12632 // ones, and then concatenate the result back.
12633 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
12634 MVT VT = Op.getSimpleValueType();
12636 assert(VT.is256BitVector() && VT.isInteger() &&
12637 "Unsupported value type for operation");
12639 unsigned NumElems = VT.getVectorNumElements();
12642 // Extract the LHS vectors
12643 SDValue LHS = Op.getOperand(0);
12644 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
12645 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
12647 // Extract the RHS vectors
12648 SDValue RHS = Op.getOperand(1);
12649 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
12650 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
12652 MVT EltVT = VT.getVectorElementType();
12653 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
12655 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
12656 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
12657 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
12660 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
12661 assert(Op.getSimpleValueType().is256BitVector() &&
12662 Op.getSimpleValueType().isInteger() &&
12663 "Only handle AVX 256-bit vector integer operation");
12664 return Lower256IntArith(Op, DAG);
12667 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
12668 assert(Op.getSimpleValueType().is256BitVector() &&
12669 Op.getSimpleValueType().isInteger() &&
12670 "Only handle AVX 256-bit vector integer operation");
12671 return Lower256IntArith(Op, DAG);
12674 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
12675 SelectionDAG &DAG) {
12677 MVT VT = Op.getSimpleValueType();
12679 // Decompose 256-bit ops into smaller 128-bit ops.
12680 if (VT.is256BitVector() && !Subtarget->hasInt256())
12681 return Lower256IntArith(Op, DAG);
12683 SDValue A = Op.getOperand(0);
12684 SDValue B = Op.getOperand(1);
12686 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
12687 if (VT == MVT::v4i32) {
12688 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
12689 "Should not custom lower when pmuldq is available!");
12691 // Extract the odd parts.
12692 static const int UnpackMask[] = { 1, -1, 3, -1 };
12693 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
12694 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
12696 // Multiply the even parts.
12697 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
12698 // Now multiply odd parts.
12699 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
12701 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
12702 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
12704 // Merge the two vectors back together with a shuffle. This expands into 2
12706 static const int ShufMask[] = { 0, 4, 2, 6 };
12707 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
12710 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
12711 "Only know how to lower V2I64/V4I64/V8I64 multiply");
12713 // Ahi = psrlqi(a, 32);
12714 // Bhi = psrlqi(b, 32);
12716 // AloBlo = pmuludq(a, b);
12717 // AloBhi = pmuludq(a, Bhi);
12718 // AhiBlo = pmuludq(Ahi, b);
12720 // AloBhi = psllqi(AloBhi, 32);
12721 // AhiBlo = psllqi(AhiBlo, 32);
12722 // return AloBlo + AloBhi + AhiBlo;
12724 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
12725 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
12727 // Bit cast to 32-bit vectors for MULUDQ
12728 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
12729 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
12730 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
12731 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
12732 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
12733 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
12735 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
12736 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
12737 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
12739 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
12740 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
12742 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
12743 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
12746 static SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) {
12747 MVT VT = Op.getSimpleValueType();
12748 MVT EltTy = VT.getVectorElementType();
12749 unsigned NumElts = VT.getVectorNumElements();
12750 SDValue N0 = Op.getOperand(0);
12753 // Lower sdiv X, pow2-const.
12754 BuildVectorSDNode *C = dyn_cast<BuildVectorSDNode>(Op.getOperand(1));
12758 APInt SplatValue, SplatUndef;
12759 unsigned SplatBitSize;
12761 if (!C->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
12763 EltTy.getSizeInBits() < SplatBitSize)
12766 if ((SplatValue != 0) &&
12767 (SplatValue.isPowerOf2() || (-SplatValue).isPowerOf2())) {
12768 unsigned Lg2 = SplatValue.countTrailingZeros();
12769 // Splat the sign bit.
12770 SmallVector<SDValue, 16> Sz(NumElts,
12771 DAG.getConstant(EltTy.getSizeInBits() - 1,
12773 SDValue SGN = DAG.getNode(ISD::SRA, dl, VT, N0,
12774 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Sz[0],
12776 // Add (N0 < 0) ? abs2 - 1 : 0;
12777 SmallVector<SDValue, 16> Amt(NumElts,
12778 DAG.getConstant(EltTy.getSizeInBits() - Lg2,
12780 SDValue SRL = DAG.getNode(ISD::SRL, dl, VT, SGN,
12781 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Amt[0],
12783 SDValue ADD = DAG.getNode(ISD::ADD, dl, VT, N0, SRL);
12784 SmallVector<SDValue, 16> Lg2Amt(NumElts, DAG.getConstant(Lg2, EltTy));
12785 SDValue SRA = DAG.getNode(ISD::SRA, dl, VT, ADD,
12786 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Lg2Amt[0],
12789 // If we're dividing by a positive value, we're done. Otherwise, we must
12790 // negate the result.
12791 if (SplatValue.isNonNegative())
12794 SmallVector<SDValue, 16> V(NumElts, DAG.getConstant(0, EltTy));
12795 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], NumElts);
12796 return DAG.getNode(ISD::SUB, dl, VT, Zero, SRA);
12801 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
12802 const X86Subtarget *Subtarget) {
12803 MVT VT = Op.getSimpleValueType();
12805 SDValue R = Op.getOperand(0);
12806 SDValue Amt = Op.getOperand(1);
12808 // Optimize shl/srl/sra with constant shift amount.
12809 if (isSplatVector(Amt.getNode())) {
12810 SDValue SclrAmt = Amt->getOperand(0);
12811 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
12812 uint64_t ShiftAmt = C->getZExtValue();
12814 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
12815 (Subtarget->hasInt256() &&
12816 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
12817 (Subtarget->hasAVX512() &&
12818 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
12819 if (Op.getOpcode() == ISD::SHL)
12820 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
12822 if (Op.getOpcode() == ISD::SRL)
12823 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
12825 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
12826 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
12830 if (VT == MVT::v16i8) {
12831 if (Op.getOpcode() == ISD::SHL) {
12832 // Make a large shift.
12833 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
12834 MVT::v8i16, R, ShiftAmt,
12836 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
12837 // Zero out the rightmost bits.
12838 SmallVector<SDValue, 16> V(16,
12839 DAG.getConstant(uint8_t(-1U << ShiftAmt),
12841 return DAG.getNode(ISD::AND, dl, VT, SHL,
12842 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
12844 if (Op.getOpcode() == ISD::SRL) {
12845 // Make a large shift.
12846 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
12847 MVT::v8i16, R, ShiftAmt,
12849 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
12850 // Zero out the leftmost bits.
12851 SmallVector<SDValue, 16> V(16,
12852 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
12854 return DAG.getNode(ISD::AND, dl, VT, SRL,
12855 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
12857 if (Op.getOpcode() == ISD::SRA) {
12858 if (ShiftAmt == 7) {
12859 // R s>> 7 === R s< 0
12860 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
12861 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
12864 // R s>> a === ((R u>> a) ^ m) - m
12865 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
12866 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
12868 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16);
12869 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
12870 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
12873 llvm_unreachable("Unknown shift opcode.");
12876 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
12877 if (Op.getOpcode() == ISD::SHL) {
12878 // Make a large shift.
12879 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
12880 MVT::v16i16, R, ShiftAmt,
12882 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
12883 // Zero out the rightmost bits.
12884 SmallVector<SDValue, 32> V(32,
12885 DAG.getConstant(uint8_t(-1U << ShiftAmt),
12887 return DAG.getNode(ISD::AND, dl, VT, SHL,
12888 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
12890 if (Op.getOpcode() == ISD::SRL) {
12891 // Make a large shift.
12892 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
12893 MVT::v16i16, R, ShiftAmt,
12895 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
12896 // Zero out the leftmost bits.
12897 SmallVector<SDValue, 32> V(32,
12898 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
12900 return DAG.getNode(ISD::AND, dl, VT, SRL,
12901 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
12903 if (Op.getOpcode() == ISD::SRA) {
12904 if (ShiftAmt == 7) {
12905 // R s>> 7 === R s< 0
12906 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
12907 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
12910 // R s>> a === ((R u>> a) ^ m) - m
12911 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
12912 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
12914 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32);
12915 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
12916 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
12919 llvm_unreachable("Unknown shift opcode.");
12924 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
12925 if (!Subtarget->is64Bit() &&
12926 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
12927 Amt.getOpcode() == ISD::BITCAST &&
12928 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
12929 Amt = Amt.getOperand(0);
12930 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
12931 VT.getVectorNumElements();
12932 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
12933 uint64_t ShiftAmt = 0;
12934 for (unsigned i = 0; i != Ratio; ++i) {
12935 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
12939 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
12941 // Check remaining shift amounts.
12942 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
12943 uint64_t ShAmt = 0;
12944 for (unsigned j = 0; j != Ratio; ++j) {
12945 ConstantSDNode *C =
12946 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
12950 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
12952 if (ShAmt != ShiftAmt)
12955 switch (Op.getOpcode()) {
12957 llvm_unreachable("Unknown shift opcode!");
12959 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
12962 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
12965 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
12973 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
12974 const X86Subtarget* Subtarget) {
12975 MVT VT = Op.getSimpleValueType();
12977 SDValue R = Op.getOperand(0);
12978 SDValue Amt = Op.getOperand(1);
12980 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
12981 VT == MVT::v4i32 || VT == MVT::v8i16 ||
12982 (Subtarget->hasInt256() &&
12983 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
12984 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
12985 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
12987 EVT EltVT = VT.getVectorElementType();
12989 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
12990 unsigned NumElts = VT.getVectorNumElements();
12992 for (i = 0; i != NumElts; ++i) {
12993 if (Amt.getOperand(i).getOpcode() == ISD::UNDEF)
12997 for (j = i; j != NumElts; ++j) {
12998 SDValue Arg = Amt.getOperand(j);
12999 if (Arg.getOpcode() == ISD::UNDEF) continue;
13000 if (Arg != Amt.getOperand(i))
13003 if (i != NumElts && j == NumElts)
13004 BaseShAmt = Amt.getOperand(i);
13006 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
13007 Amt = Amt.getOperand(0);
13008 if (Amt.getOpcode() == ISD::VECTOR_SHUFFLE &&
13009 cast<ShuffleVectorSDNode>(Amt)->isSplat()) {
13010 SDValue InVec = Amt.getOperand(0);
13011 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
13012 unsigned NumElts = InVec.getValueType().getVectorNumElements();
13014 for (; i != NumElts; ++i) {
13015 SDValue Arg = InVec.getOperand(i);
13016 if (Arg.getOpcode() == ISD::UNDEF) continue;
13020 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
13021 if (ConstantSDNode *C =
13022 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
13023 unsigned SplatIdx =
13024 cast<ShuffleVectorSDNode>(Amt)->getSplatIndex();
13025 if (C->getZExtValue() == SplatIdx)
13026 BaseShAmt = InVec.getOperand(1);
13029 if (BaseShAmt.getNode() == 0)
13030 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Amt,
13031 DAG.getIntPtrConstant(0));
13035 if (BaseShAmt.getNode()) {
13036 if (EltVT.bitsGT(MVT::i32))
13037 BaseShAmt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BaseShAmt);
13038 else if (EltVT.bitsLT(MVT::i32))
13039 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
13041 switch (Op.getOpcode()) {
13043 llvm_unreachable("Unknown shift opcode!");
13045 switch (VT.SimpleTy) {
13046 default: return SDValue();
13055 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
13058 switch (VT.SimpleTy) {
13059 default: return SDValue();
13066 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
13069 switch (VT.SimpleTy) {
13070 default: return SDValue();
13079 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
13085 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
13086 if (!Subtarget->is64Bit() &&
13087 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
13088 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
13089 Amt.getOpcode() == ISD::BITCAST &&
13090 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
13091 Amt = Amt.getOperand(0);
13092 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
13093 VT.getVectorNumElements();
13094 std::vector<SDValue> Vals(Ratio);
13095 for (unsigned i = 0; i != Ratio; ++i)
13096 Vals[i] = Amt.getOperand(i);
13097 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
13098 for (unsigned j = 0; j != Ratio; ++j)
13099 if (Vals[j] != Amt.getOperand(i + j))
13102 switch (Op.getOpcode()) {
13104 llvm_unreachable("Unknown shift opcode!");
13106 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
13108 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
13110 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
13117 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
13118 SelectionDAG &DAG) {
13120 MVT VT = Op.getSimpleValueType();
13122 SDValue R = Op.getOperand(0);
13123 SDValue Amt = Op.getOperand(1);
13126 if (!Subtarget->hasSSE2())
13129 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
13133 V = LowerScalarVariableShift(Op, DAG, Subtarget);
13137 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
13139 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
13140 if (Subtarget->hasInt256()) {
13141 if (Op.getOpcode() == ISD::SRL &&
13142 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
13143 VT == MVT::v4i64 || VT == MVT::v8i32))
13145 if (Op.getOpcode() == ISD::SHL &&
13146 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
13147 VT == MVT::v4i64 || VT == MVT::v8i32))
13149 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
13153 // Lower SHL with variable shift amount.
13154 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
13155 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
13157 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
13158 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
13159 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
13160 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
13162 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
13163 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
13166 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
13167 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
13169 // Turn 'a' into a mask suitable for VSELECT
13170 SDValue VSelM = DAG.getConstant(0x80, VT);
13171 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
13172 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
13174 SDValue CM1 = DAG.getConstant(0x0f, VT);
13175 SDValue CM2 = DAG.getConstant(0x3f, VT);
13177 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
13178 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
13179 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
13180 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
13181 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
13184 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
13185 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
13186 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
13188 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
13189 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
13190 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
13191 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
13192 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
13195 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
13196 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
13197 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
13199 // return VSELECT(r, r+r, a);
13200 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
13201 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
13205 // Decompose 256-bit shifts into smaller 128-bit shifts.
13206 if (VT.is256BitVector()) {
13207 unsigned NumElems = VT.getVectorNumElements();
13208 MVT EltVT = VT.getVectorElementType();
13209 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
13211 // Extract the two vectors
13212 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
13213 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
13215 // Recreate the shift amount vectors
13216 SDValue Amt1, Amt2;
13217 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
13218 // Constant shift amount
13219 SmallVector<SDValue, 4> Amt1Csts;
13220 SmallVector<SDValue, 4> Amt2Csts;
13221 for (unsigned i = 0; i != NumElems/2; ++i)
13222 Amt1Csts.push_back(Amt->getOperand(i));
13223 for (unsigned i = NumElems/2; i != NumElems; ++i)
13224 Amt2Csts.push_back(Amt->getOperand(i));
13226 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
13227 &Amt1Csts[0], NumElems/2);
13228 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
13229 &Amt2Csts[0], NumElems/2);
13231 // Variable shift amount
13232 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
13233 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
13236 // Issue new vector shifts for the smaller types
13237 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
13238 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
13240 // Concatenate the result back
13241 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
13247 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
13248 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
13249 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
13250 // looks for this combo and may remove the "setcc" instruction if the "setcc"
13251 // has only one use.
13252 SDNode *N = Op.getNode();
13253 SDValue LHS = N->getOperand(0);
13254 SDValue RHS = N->getOperand(1);
13255 unsigned BaseOp = 0;
13258 switch (Op.getOpcode()) {
13259 default: llvm_unreachable("Unknown ovf instruction!");
13261 // A subtract of one will be selected as a INC. Note that INC doesn't
13262 // set CF, so we can't do this for UADDO.
13263 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
13265 BaseOp = X86ISD::INC;
13266 Cond = X86::COND_O;
13269 BaseOp = X86ISD::ADD;
13270 Cond = X86::COND_O;
13273 BaseOp = X86ISD::ADD;
13274 Cond = X86::COND_B;
13277 // A subtract of one will be selected as a DEC. Note that DEC doesn't
13278 // set CF, so we can't do this for USUBO.
13279 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
13281 BaseOp = X86ISD::DEC;
13282 Cond = X86::COND_O;
13285 BaseOp = X86ISD::SUB;
13286 Cond = X86::COND_O;
13289 BaseOp = X86ISD::SUB;
13290 Cond = X86::COND_B;
13293 BaseOp = X86ISD::SMUL;
13294 Cond = X86::COND_O;
13296 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
13297 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
13299 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
13302 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13303 DAG.getConstant(X86::COND_O, MVT::i32),
13304 SDValue(Sum.getNode(), 2));
13306 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
13310 // Also sets EFLAGS.
13311 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
13312 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
13315 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
13316 DAG.getConstant(Cond, MVT::i32),
13317 SDValue(Sum.getNode(), 1));
13319 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
13322 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
13323 SelectionDAG &DAG) const {
13325 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
13326 MVT VT = Op.getSimpleValueType();
13328 if (!Subtarget->hasSSE2() || !VT.isVector())
13331 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
13332 ExtraVT.getScalarType().getSizeInBits();
13334 switch (VT.SimpleTy) {
13335 default: return SDValue();
13338 if (!Subtarget->hasFp256())
13340 if (!Subtarget->hasInt256()) {
13341 // needs to be split
13342 unsigned NumElems = VT.getVectorNumElements();
13344 // Extract the LHS vectors
13345 SDValue LHS = Op.getOperand(0);
13346 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
13347 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
13349 MVT EltVT = VT.getVectorElementType();
13350 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
13352 EVT ExtraEltVT = ExtraVT.getVectorElementType();
13353 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
13354 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
13356 SDValue Extra = DAG.getValueType(ExtraVT);
13358 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
13359 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
13361 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
13366 SDValue Op0 = Op.getOperand(0);
13367 SDValue Op00 = Op0.getOperand(0);
13369 // Hopefully, this VECTOR_SHUFFLE is just a VZEXT.
13370 if (Op0.getOpcode() == ISD::BITCAST &&
13371 Op00.getOpcode() == ISD::VECTOR_SHUFFLE) {
13372 // (sext (vzext x)) -> (vsext x)
13373 Tmp1 = LowerVectorIntExtend(Op00, Subtarget, DAG);
13374 if (Tmp1.getNode()) {
13375 EVT ExtraEltVT = ExtraVT.getVectorElementType();
13376 // This folding is only valid when the in-reg type is a vector of i8,
13378 if (ExtraEltVT == MVT::i8 || ExtraEltVT == MVT::i16 ||
13379 ExtraEltVT == MVT::i32) {
13380 SDValue Tmp1Op0 = Tmp1.getOperand(0);
13381 assert(Tmp1Op0.getOpcode() == X86ISD::VZEXT &&
13382 "This optimization is invalid without a VZEXT.");
13383 return DAG.getNode(X86ISD::VSEXT, dl, VT, Tmp1Op0.getOperand(0));
13389 // If the above didn't work, then just use Shift-Left + Shift-Right.
13390 Tmp1 = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Op0, BitsDiff,
13392 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, Tmp1, BitsDiff,
13398 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
13399 SelectionDAG &DAG) {
13401 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
13402 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
13403 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
13404 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
13406 // The only fence that needs an instruction is a sequentially-consistent
13407 // cross-thread fence.
13408 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
13409 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
13410 // no-sse2). There isn't any reason to disable it if the target processor
13412 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
13413 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
13415 SDValue Chain = Op.getOperand(0);
13416 SDValue Zero = DAG.getConstant(0, MVT::i32);
13418 DAG.getRegister(X86::ESP, MVT::i32), // Base
13419 DAG.getTargetConstant(1, MVT::i8), // Scale
13420 DAG.getRegister(0, MVT::i32), // Index
13421 DAG.getTargetConstant(0, MVT::i32), // Disp
13422 DAG.getRegister(0, MVT::i32), // Segment.
13426 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
13427 return SDValue(Res, 0);
13430 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
13431 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
13434 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
13435 SelectionDAG &DAG) {
13436 MVT T = Op.getSimpleValueType();
13440 switch(T.SimpleTy) {
13441 default: llvm_unreachable("Invalid value type!");
13442 case MVT::i8: Reg = X86::AL; size = 1; break;
13443 case MVT::i16: Reg = X86::AX; size = 2; break;
13444 case MVT::i32: Reg = X86::EAX; size = 4; break;
13446 assert(Subtarget->is64Bit() && "Node not type legal!");
13447 Reg = X86::RAX; size = 8;
13450 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
13451 Op.getOperand(2), SDValue());
13452 SDValue Ops[] = { cpIn.getValue(0),
13455 DAG.getTargetConstant(size, MVT::i8),
13456 cpIn.getValue(1) };
13457 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
13458 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
13459 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
13460 Ops, array_lengthof(Ops), T, MMO);
13462 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
13466 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
13467 SelectionDAG &DAG) {
13468 assert(Subtarget->is64Bit() && "Result not type legalized?");
13469 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
13470 SDValue TheChain = Op.getOperand(0);
13472 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
13473 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
13474 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
13476 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
13477 DAG.getConstant(32, MVT::i8));
13479 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
13482 return DAG.getMergeValues(Ops, array_lengthof(Ops), dl);
13485 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
13486 SelectionDAG &DAG) {
13487 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
13488 MVT DstVT = Op.getSimpleValueType();
13489 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
13490 Subtarget->hasMMX() && "Unexpected custom BITCAST");
13491 assert((DstVT == MVT::i64 ||
13492 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
13493 "Unexpected custom BITCAST");
13494 // i64 <=> MMX conversions are Legal.
13495 if (SrcVT==MVT::i64 && DstVT.isVector())
13497 if (DstVT==MVT::i64 && SrcVT.isVector())
13499 // MMX <=> MMX conversions are Legal.
13500 if (SrcVT.isVector() && DstVT.isVector())
13502 // All other conversions need to be expanded.
13506 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
13507 SDNode *Node = Op.getNode();
13509 EVT T = Node->getValueType(0);
13510 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
13511 DAG.getConstant(0, T), Node->getOperand(2));
13512 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
13513 cast<AtomicSDNode>(Node)->getMemoryVT(),
13514 Node->getOperand(0),
13515 Node->getOperand(1), negOp,
13516 cast<AtomicSDNode>(Node)->getSrcValue(),
13517 cast<AtomicSDNode>(Node)->getAlignment(),
13518 cast<AtomicSDNode>(Node)->getOrdering(),
13519 cast<AtomicSDNode>(Node)->getSynchScope());
13522 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
13523 SDNode *Node = Op.getNode();
13525 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
13527 // Convert seq_cst store -> xchg
13528 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
13529 // FIXME: On 32-bit, store -> fist or movq would be more efficient
13530 // (The only way to get a 16-byte store is cmpxchg16b)
13531 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
13532 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
13533 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
13534 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
13535 cast<AtomicSDNode>(Node)->getMemoryVT(),
13536 Node->getOperand(0),
13537 Node->getOperand(1), Node->getOperand(2),
13538 cast<AtomicSDNode>(Node)->getMemOperand(),
13539 cast<AtomicSDNode>(Node)->getOrdering(),
13540 cast<AtomicSDNode>(Node)->getSynchScope());
13541 return Swap.getValue(1);
13543 // Other atomic stores have a simple pattern.
13547 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
13548 EVT VT = Op.getNode()->getSimpleValueType(0);
13550 // Let legalize expand this if it isn't a legal type yet.
13551 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
13554 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
13557 bool ExtraOp = false;
13558 switch (Op.getOpcode()) {
13559 default: llvm_unreachable("Invalid code");
13560 case ISD::ADDC: Opc = X86ISD::ADD; break;
13561 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
13562 case ISD::SUBC: Opc = X86ISD::SUB; break;
13563 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
13567 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
13569 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
13570 Op.getOperand(1), Op.getOperand(2));
13573 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
13574 SelectionDAG &DAG) {
13575 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
13577 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
13578 // which returns the values as { float, float } (in XMM0) or
13579 // { double, double } (which is returned in XMM0, XMM1).
13581 SDValue Arg = Op.getOperand(0);
13582 EVT ArgVT = Arg.getValueType();
13583 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
13585 TargetLowering::ArgListTy Args;
13586 TargetLowering::ArgListEntry Entry;
13590 Entry.isSExt = false;
13591 Entry.isZExt = false;
13592 Args.push_back(Entry);
13594 bool isF64 = ArgVT == MVT::f64;
13595 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
13596 // the small struct {f32, f32} is returned in (eax, edx). For f64,
13597 // the results are returned via SRet in memory.
13598 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
13599 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13600 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
13602 Type *RetTy = isF64
13603 ? (Type*)StructType::get(ArgTy, ArgTy, NULL)
13604 : (Type*)VectorType::get(ArgTy, 4);
13606 CallLoweringInfo CLI(DAG.getEntryNode(), RetTy,
13607 false, false, false, false, 0,
13608 CallingConv::C, /*isTaillCall=*/false,
13609 /*doesNotRet=*/false, /*isReturnValueUsed*/true,
13610 Callee, Args, DAG, dl);
13611 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
13614 // Returned in xmm0 and xmm1.
13615 return CallResult.first;
13617 // Returned in bits 0:31 and 32:64 xmm0.
13618 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
13619 CallResult.first, DAG.getIntPtrConstant(0));
13620 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
13621 CallResult.first, DAG.getIntPtrConstant(1));
13622 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
13623 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
13626 /// LowerOperation - Provide custom lowering hooks for some operations.
13628 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
13629 switch (Op.getOpcode()) {
13630 default: llvm_unreachable("Should not custom lower this!");
13631 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
13632 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
13633 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op, Subtarget, DAG);
13634 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
13635 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
13636 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
13637 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
13638 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
13639 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
13640 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
13641 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
13642 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
13643 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
13644 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
13645 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
13646 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
13647 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
13648 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
13649 case ISD::SHL_PARTS:
13650 case ISD::SRA_PARTS:
13651 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
13652 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
13653 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
13654 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
13655 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
13656 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
13657 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
13658 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
13659 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
13660 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
13661 case ISD::FABS: return LowerFABS(Op, DAG);
13662 case ISD::FNEG: return LowerFNEG(Op, DAG);
13663 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
13664 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
13665 case ISD::SETCC: return LowerSETCC(Op, DAG);
13666 case ISD::SELECT: return LowerSELECT(Op, DAG);
13667 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
13668 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
13669 case ISD::VASTART: return LowerVASTART(Op, DAG);
13670 case ISD::VAARG: return LowerVAARG(Op, DAG);
13671 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
13672 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
13673 case ISD::INTRINSIC_VOID:
13674 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
13675 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
13676 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
13677 case ISD::FRAME_TO_ARGS_OFFSET:
13678 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
13679 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
13680 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
13681 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
13682 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
13683 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
13684 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
13685 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
13686 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
13687 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
13688 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
13689 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
13692 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
13698 case ISD::UMULO: return LowerXALUO(Op, DAG);
13699 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
13700 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
13704 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
13705 case ISD::ADD: return LowerADD(Op, DAG);
13706 case ISD::SUB: return LowerSUB(Op, DAG);
13707 case ISD::SDIV: return LowerSDIV(Op, DAG);
13708 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
13712 static void ReplaceATOMIC_LOAD(SDNode *Node,
13713 SmallVectorImpl<SDValue> &Results,
13714 SelectionDAG &DAG) {
13716 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
13718 // Convert wide load -> cmpxchg8b/cmpxchg16b
13719 // FIXME: On 32-bit, load -> fild or movq would be more efficient
13720 // (The only way to get a 16-byte load is cmpxchg16b)
13721 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
13722 SDValue Zero = DAG.getConstant(0, VT);
13723 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT,
13724 Node->getOperand(0),
13725 Node->getOperand(1), Zero, Zero,
13726 cast<AtomicSDNode>(Node)->getMemOperand(),
13727 cast<AtomicSDNode>(Node)->getOrdering(),
13728 cast<AtomicSDNode>(Node)->getSynchScope());
13729 Results.push_back(Swap.getValue(0));
13730 Results.push_back(Swap.getValue(1));
13734 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
13735 SelectionDAG &DAG, unsigned NewOp) {
13737 assert (Node->getValueType(0) == MVT::i64 &&
13738 "Only know how to expand i64 atomics");
13740 SDValue Chain = Node->getOperand(0);
13741 SDValue In1 = Node->getOperand(1);
13742 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
13743 Node->getOperand(2), DAG.getIntPtrConstant(0));
13744 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
13745 Node->getOperand(2), DAG.getIntPtrConstant(1));
13746 SDValue Ops[] = { Chain, In1, In2L, In2H };
13747 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
13749 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, array_lengthof(Ops), MVT::i64,
13750 cast<MemSDNode>(Node)->getMemOperand());
13751 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
13752 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
13753 Results.push_back(Result.getValue(2));
13756 /// ReplaceNodeResults - Replace a node with an illegal result type
13757 /// with a new node built out of custom code.
13758 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
13759 SmallVectorImpl<SDValue>&Results,
13760 SelectionDAG &DAG) const {
13762 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13763 switch (N->getOpcode()) {
13765 llvm_unreachable("Do not know how to custom type legalize this operation!");
13766 case ISD::SIGN_EXTEND_INREG:
13771 // We don't want to expand or promote these.
13773 case ISD::FP_TO_SINT:
13774 case ISD::FP_TO_UINT: {
13775 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
13777 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
13780 std::pair<SDValue,SDValue> Vals =
13781 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
13782 SDValue FIST = Vals.first, StackSlot = Vals.second;
13783 if (FIST.getNode() != 0) {
13784 EVT VT = N->getValueType(0);
13785 // Return a load from the stack slot.
13786 if (StackSlot.getNode() != 0)
13787 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
13788 MachinePointerInfo(),
13789 false, false, false, 0));
13791 Results.push_back(FIST);
13795 case ISD::UINT_TO_FP: {
13796 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
13797 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
13798 N->getValueType(0) != MVT::v2f32)
13800 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
13802 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
13804 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
13805 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
13806 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
13807 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
13808 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
13809 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
13812 case ISD::FP_ROUND: {
13813 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
13815 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
13816 Results.push_back(V);
13819 case ISD::READCYCLECOUNTER: {
13820 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
13821 SDValue TheChain = N->getOperand(0);
13822 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
13823 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
13825 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
13827 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
13828 SDValue Ops[] = { eax, edx };
13829 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops,
13830 array_lengthof(Ops)));
13831 Results.push_back(edx.getValue(1));
13834 case ISD::ATOMIC_CMP_SWAP: {
13835 EVT T = N->getValueType(0);
13836 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
13837 bool Regs64bit = T == MVT::i128;
13838 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
13839 SDValue cpInL, cpInH;
13840 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
13841 DAG.getConstant(0, HalfT));
13842 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
13843 DAG.getConstant(1, HalfT));
13844 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
13845 Regs64bit ? X86::RAX : X86::EAX,
13847 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
13848 Regs64bit ? X86::RDX : X86::EDX,
13849 cpInH, cpInL.getValue(1));
13850 SDValue swapInL, swapInH;
13851 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
13852 DAG.getConstant(0, HalfT));
13853 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
13854 DAG.getConstant(1, HalfT));
13855 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
13856 Regs64bit ? X86::RBX : X86::EBX,
13857 swapInL, cpInH.getValue(1));
13858 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
13859 Regs64bit ? X86::RCX : X86::ECX,
13860 swapInH, swapInL.getValue(1));
13861 SDValue Ops[] = { swapInH.getValue(0),
13863 swapInH.getValue(1) };
13864 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
13865 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
13866 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
13867 X86ISD::LCMPXCHG8_DAG;
13868 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys,
13869 Ops, array_lengthof(Ops), T, MMO);
13870 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
13871 Regs64bit ? X86::RAX : X86::EAX,
13872 HalfT, Result.getValue(1));
13873 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
13874 Regs64bit ? X86::RDX : X86::EDX,
13875 HalfT, cpOutL.getValue(2));
13876 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
13877 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2));
13878 Results.push_back(cpOutH.getValue(1));
13881 case ISD::ATOMIC_LOAD_ADD:
13882 case ISD::ATOMIC_LOAD_AND:
13883 case ISD::ATOMIC_LOAD_NAND:
13884 case ISD::ATOMIC_LOAD_OR:
13885 case ISD::ATOMIC_LOAD_SUB:
13886 case ISD::ATOMIC_LOAD_XOR:
13887 case ISD::ATOMIC_LOAD_MAX:
13888 case ISD::ATOMIC_LOAD_MIN:
13889 case ISD::ATOMIC_LOAD_UMAX:
13890 case ISD::ATOMIC_LOAD_UMIN:
13891 case ISD::ATOMIC_SWAP: {
13893 switch (N->getOpcode()) {
13894 default: llvm_unreachable("Unexpected opcode");
13895 case ISD::ATOMIC_LOAD_ADD:
13896 Opc = X86ISD::ATOMADD64_DAG;
13898 case ISD::ATOMIC_LOAD_AND:
13899 Opc = X86ISD::ATOMAND64_DAG;
13901 case ISD::ATOMIC_LOAD_NAND:
13902 Opc = X86ISD::ATOMNAND64_DAG;
13904 case ISD::ATOMIC_LOAD_OR:
13905 Opc = X86ISD::ATOMOR64_DAG;
13907 case ISD::ATOMIC_LOAD_SUB:
13908 Opc = X86ISD::ATOMSUB64_DAG;
13910 case ISD::ATOMIC_LOAD_XOR:
13911 Opc = X86ISD::ATOMXOR64_DAG;
13913 case ISD::ATOMIC_LOAD_MAX:
13914 Opc = X86ISD::ATOMMAX64_DAG;
13916 case ISD::ATOMIC_LOAD_MIN:
13917 Opc = X86ISD::ATOMMIN64_DAG;
13919 case ISD::ATOMIC_LOAD_UMAX:
13920 Opc = X86ISD::ATOMUMAX64_DAG;
13922 case ISD::ATOMIC_LOAD_UMIN:
13923 Opc = X86ISD::ATOMUMIN64_DAG;
13925 case ISD::ATOMIC_SWAP:
13926 Opc = X86ISD::ATOMSWAP64_DAG;
13929 ReplaceATOMIC_BINARY_64(N, Results, DAG, Opc);
13932 case ISD::ATOMIC_LOAD:
13933 ReplaceATOMIC_LOAD(N, Results, DAG);
13937 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
13939 default: return NULL;
13940 case X86ISD::BSF: return "X86ISD::BSF";
13941 case X86ISD::BSR: return "X86ISD::BSR";
13942 case X86ISD::SHLD: return "X86ISD::SHLD";
13943 case X86ISD::SHRD: return "X86ISD::SHRD";
13944 case X86ISD::FAND: return "X86ISD::FAND";
13945 case X86ISD::FANDN: return "X86ISD::FANDN";
13946 case X86ISD::FOR: return "X86ISD::FOR";
13947 case X86ISD::FXOR: return "X86ISD::FXOR";
13948 case X86ISD::FSRL: return "X86ISD::FSRL";
13949 case X86ISD::FILD: return "X86ISD::FILD";
13950 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
13951 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
13952 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
13953 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
13954 case X86ISD::FLD: return "X86ISD::FLD";
13955 case X86ISD::FST: return "X86ISD::FST";
13956 case X86ISD::CALL: return "X86ISD::CALL";
13957 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
13958 case X86ISD::BT: return "X86ISD::BT";
13959 case X86ISD::CMP: return "X86ISD::CMP";
13960 case X86ISD::COMI: return "X86ISD::COMI";
13961 case X86ISD::UCOMI: return "X86ISD::UCOMI";
13962 case X86ISD::CMPM: return "X86ISD::CMPM";
13963 case X86ISD::CMPMU: return "X86ISD::CMPMU";
13964 case X86ISD::SETCC: return "X86ISD::SETCC";
13965 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
13966 case X86ISD::FSETCC: return "X86ISD::FSETCC";
13967 case X86ISD::CMOV: return "X86ISD::CMOV";
13968 case X86ISD::BRCOND: return "X86ISD::BRCOND";
13969 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
13970 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
13971 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
13972 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
13973 case X86ISD::Wrapper: return "X86ISD::Wrapper";
13974 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
13975 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
13976 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
13977 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
13978 case X86ISD::PINSRB: return "X86ISD::PINSRB";
13979 case X86ISD::PINSRW: return "X86ISD::PINSRW";
13980 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
13981 case X86ISD::ANDNP: return "X86ISD::ANDNP";
13982 case X86ISD::PSIGN: return "X86ISD::PSIGN";
13983 case X86ISD::BLENDV: return "X86ISD::BLENDV";
13984 case X86ISD::BLENDI: return "X86ISD::BLENDI";
13985 case X86ISD::SUBUS: return "X86ISD::SUBUS";
13986 case X86ISD::HADD: return "X86ISD::HADD";
13987 case X86ISD::HSUB: return "X86ISD::HSUB";
13988 case X86ISD::FHADD: return "X86ISD::FHADD";
13989 case X86ISD::FHSUB: return "X86ISD::FHSUB";
13990 case X86ISD::UMAX: return "X86ISD::UMAX";
13991 case X86ISD::UMIN: return "X86ISD::UMIN";
13992 case X86ISD::SMAX: return "X86ISD::SMAX";
13993 case X86ISD::SMIN: return "X86ISD::SMIN";
13994 case X86ISD::FMAX: return "X86ISD::FMAX";
13995 case X86ISD::FMIN: return "X86ISD::FMIN";
13996 case X86ISD::FMAXC: return "X86ISD::FMAXC";
13997 case X86ISD::FMINC: return "X86ISD::FMINC";
13998 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
13999 case X86ISD::FRCP: return "X86ISD::FRCP";
14000 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
14001 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
14002 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
14003 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
14004 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
14005 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
14006 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
14007 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
14008 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
14009 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
14010 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
14011 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
14012 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
14013 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
14014 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
14015 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
14016 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
14017 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
14018 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
14019 case X86ISD::VZEXT: return "X86ISD::VZEXT";
14020 case X86ISD::VSEXT: return "X86ISD::VSEXT";
14021 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
14022 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
14023 case X86ISD::VINSERT: return "X86ISD::VINSERT";
14024 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
14025 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
14026 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
14027 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
14028 case X86ISD::VSHL: return "X86ISD::VSHL";
14029 case X86ISD::VSRL: return "X86ISD::VSRL";
14030 case X86ISD::VSRA: return "X86ISD::VSRA";
14031 case X86ISD::VSHLI: return "X86ISD::VSHLI";
14032 case X86ISD::VSRLI: return "X86ISD::VSRLI";
14033 case X86ISD::VSRAI: return "X86ISD::VSRAI";
14034 case X86ISD::CMPP: return "X86ISD::CMPP";
14035 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
14036 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
14037 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
14038 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
14039 case X86ISD::ADD: return "X86ISD::ADD";
14040 case X86ISD::SUB: return "X86ISD::SUB";
14041 case X86ISD::ADC: return "X86ISD::ADC";
14042 case X86ISD::SBB: return "X86ISD::SBB";
14043 case X86ISD::SMUL: return "X86ISD::SMUL";
14044 case X86ISD::UMUL: return "X86ISD::UMUL";
14045 case X86ISD::INC: return "X86ISD::INC";
14046 case X86ISD::DEC: return "X86ISD::DEC";
14047 case X86ISD::OR: return "X86ISD::OR";
14048 case X86ISD::XOR: return "X86ISD::XOR";
14049 case X86ISD::AND: return "X86ISD::AND";
14050 case X86ISD::BZHI: return "X86ISD::BZHI";
14051 case X86ISD::BEXTR: return "X86ISD::BEXTR";
14052 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
14053 case X86ISD::PTEST: return "X86ISD::PTEST";
14054 case X86ISD::TESTP: return "X86ISD::TESTP";
14055 case X86ISD::TESTM: return "X86ISD::TESTM";
14056 case X86ISD::TESTNM: return "X86ISD::TESTNM";
14057 case X86ISD::KORTEST: return "X86ISD::KORTEST";
14058 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
14059 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
14060 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
14061 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
14062 case X86ISD::SHUFP: return "X86ISD::SHUFP";
14063 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
14064 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
14065 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
14066 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
14067 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
14068 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
14069 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
14070 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
14071 case X86ISD::MOVSD: return "X86ISD::MOVSD";
14072 case X86ISD::MOVSS: return "X86ISD::MOVSS";
14073 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
14074 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
14075 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
14076 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
14077 case X86ISD::VPERMILP: return "X86ISD::VPERMILP";
14078 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
14079 case X86ISD::VPERMV: return "X86ISD::VPERMV";
14080 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
14081 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
14082 case X86ISD::VPERMI: return "X86ISD::VPERMI";
14083 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
14084 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
14085 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
14086 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
14087 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
14088 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
14089 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
14090 case X86ISD::SAHF: return "X86ISD::SAHF";
14091 case X86ISD::RDRAND: return "X86ISD::RDRAND";
14092 case X86ISD::RDSEED: return "X86ISD::RDSEED";
14093 case X86ISD::FMADD: return "X86ISD::FMADD";
14094 case X86ISD::FMSUB: return "X86ISD::FMSUB";
14095 case X86ISD::FNMADD: return "X86ISD::FNMADD";
14096 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
14097 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
14098 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
14099 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
14100 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
14101 case X86ISD::XTEST: return "X86ISD::XTEST";
14105 // isLegalAddressingMode - Return true if the addressing mode represented
14106 // by AM is legal for this target, for a load/store of the specified type.
14107 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
14109 // X86 supports extremely general addressing modes.
14110 CodeModel::Model M = getTargetMachine().getCodeModel();
14111 Reloc::Model R = getTargetMachine().getRelocationModel();
14113 // X86 allows a sign-extended 32-bit immediate field as a displacement.
14114 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
14119 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
14121 // If a reference to this global requires an extra load, we can't fold it.
14122 if (isGlobalStubReference(GVFlags))
14125 // If BaseGV requires a register for the PIC base, we cannot also have a
14126 // BaseReg specified.
14127 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
14130 // If lower 4G is not available, then we must use rip-relative addressing.
14131 if ((M != CodeModel::Small || R != Reloc::Static) &&
14132 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
14136 switch (AM.Scale) {
14142 // These scales always work.
14147 // These scales are formed with basereg+scalereg. Only accept if there is
14152 default: // Other stuff never works.
14159 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
14160 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
14162 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
14163 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
14164 return NumBits1 > NumBits2;
14167 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
14168 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
14171 if (!isTypeLegal(EVT::getEVT(Ty1)))
14174 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
14176 // Assuming the caller doesn't have a zeroext or signext return parameter,
14177 // truncation all the way down to i1 is valid.
14181 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
14182 return isInt<32>(Imm);
14185 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
14186 // Can also use sub to handle negated immediates.
14187 return isInt<32>(Imm);
14190 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
14191 if (!VT1.isInteger() || !VT2.isInteger())
14193 unsigned NumBits1 = VT1.getSizeInBits();
14194 unsigned NumBits2 = VT2.getSizeInBits();
14195 return NumBits1 > NumBits2;
14198 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
14199 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
14200 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
14203 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
14204 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
14205 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
14208 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
14209 EVT VT1 = Val.getValueType();
14210 if (isZExtFree(VT1, VT2))
14213 if (Val.getOpcode() != ISD::LOAD)
14216 if (!VT1.isSimple() || !VT1.isInteger() ||
14217 !VT2.isSimple() || !VT2.isInteger())
14220 switch (VT1.getSimpleVT().SimpleTy) {
14225 // X86 has 8, 16, and 32-bit zero-extending loads.
14233 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
14234 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
14237 VT = VT.getScalarType();
14239 if (!VT.isSimple())
14242 switch (VT.getSimpleVT().SimpleTy) {
14253 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
14254 // i16 instructions are longer (0x66 prefix) and potentially slower.
14255 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
14258 /// isShuffleMaskLegal - Targets can use this to indicate that they only
14259 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
14260 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
14261 /// are assumed to be legal.
14263 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
14265 if (!VT.isSimple())
14268 MVT SVT = VT.getSimpleVT();
14270 // Very little shuffling can be done for 64-bit vectors right now.
14271 if (VT.getSizeInBits() == 64)
14274 // FIXME: pshufb, blends, shifts.
14275 return (SVT.getVectorNumElements() == 2 ||
14276 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
14277 isMOVLMask(M, SVT) ||
14278 isSHUFPMask(M, SVT) ||
14279 isPSHUFDMask(M, SVT) ||
14280 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
14281 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
14282 isPALIGNRMask(M, SVT, Subtarget) ||
14283 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
14284 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
14285 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
14286 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()));
14290 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
14292 if (!VT.isSimple())
14295 MVT SVT = VT.getSimpleVT();
14296 unsigned NumElts = SVT.getVectorNumElements();
14297 // FIXME: This collection of masks seems suspect.
14300 if (NumElts == 4 && SVT.is128BitVector()) {
14301 return (isMOVLMask(Mask, SVT) ||
14302 isCommutedMOVLMask(Mask, SVT, true) ||
14303 isSHUFPMask(Mask, SVT) ||
14304 isSHUFPMask(Mask, SVT, /* Commuted */ true));
14309 //===----------------------------------------------------------------------===//
14310 // X86 Scheduler Hooks
14311 //===----------------------------------------------------------------------===//
14313 /// Utility function to emit xbegin specifying the start of an RTM region.
14314 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
14315 const TargetInstrInfo *TII) {
14316 DebugLoc DL = MI->getDebugLoc();
14318 const BasicBlock *BB = MBB->getBasicBlock();
14319 MachineFunction::iterator I = MBB;
14322 // For the v = xbegin(), we generate
14333 MachineBasicBlock *thisMBB = MBB;
14334 MachineFunction *MF = MBB->getParent();
14335 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
14336 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
14337 MF->insert(I, mainMBB);
14338 MF->insert(I, sinkMBB);
14340 // Transfer the remainder of BB and its successor edges to sinkMBB.
14341 sinkMBB->splice(sinkMBB->begin(), MBB,
14342 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
14343 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
14347 // # fallthrough to mainMBB
14348 // # abortion to sinkMBB
14349 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
14350 thisMBB->addSuccessor(mainMBB);
14351 thisMBB->addSuccessor(sinkMBB);
14355 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
14356 mainMBB->addSuccessor(sinkMBB);
14359 // EAX is live into the sinkMBB
14360 sinkMBB->addLiveIn(X86::EAX);
14361 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
14362 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
14365 MI->eraseFromParent();
14369 // Get CMPXCHG opcode for the specified data type.
14370 static unsigned getCmpXChgOpcode(EVT VT) {
14371 switch (VT.getSimpleVT().SimpleTy) {
14372 case MVT::i8: return X86::LCMPXCHG8;
14373 case MVT::i16: return X86::LCMPXCHG16;
14374 case MVT::i32: return X86::LCMPXCHG32;
14375 case MVT::i64: return X86::LCMPXCHG64;
14379 llvm_unreachable("Invalid operand size!");
14382 // Get LOAD opcode for the specified data type.
14383 static unsigned getLoadOpcode(EVT VT) {
14384 switch (VT.getSimpleVT().SimpleTy) {
14385 case MVT::i8: return X86::MOV8rm;
14386 case MVT::i16: return X86::MOV16rm;
14387 case MVT::i32: return X86::MOV32rm;
14388 case MVT::i64: return X86::MOV64rm;
14392 llvm_unreachable("Invalid operand size!");
14395 // Get opcode of the non-atomic one from the specified atomic instruction.
14396 static unsigned getNonAtomicOpcode(unsigned Opc) {
14398 case X86::ATOMAND8: return X86::AND8rr;
14399 case X86::ATOMAND16: return X86::AND16rr;
14400 case X86::ATOMAND32: return X86::AND32rr;
14401 case X86::ATOMAND64: return X86::AND64rr;
14402 case X86::ATOMOR8: return X86::OR8rr;
14403 case X86::ATOMOR16: return X86::OR16rr;
14404 case X86::ATOMOR32: return X86::OR32rr;
14405 case X86::ATOMOR64: return X86::OR64rr;
14406 case X86::ATOMXOR8: return X86::XOR8rr;
14407 case X86::ATOMXOR16: return X86::XOR16rr;
14408 case X86::ATOMXOR32: return X86::XOR32rr;
14409 case X86::ATOMXOR64: return X86::XOR64rr;
14411 llvm_unreachable("Unhandled atomic-load-op opcode!");
14414 // Get opcode of the non-atomic one from the specified atomic instruction with
14416 static unsigned getNonAtomicOpcodeWithExtraOpc(unsigned Opc,
14417 unsigned &ExtraOpc) {
14419 case X86::ATOMNAND8: ExtraOpc = X86::NOT8r; return X86::AND8rr;
14420 case X86::ATOMNAND16: ExtraOpc = X86::NOT16r; return X86::AND16rr;
14421 case X86::ATOMNAND32: ExtraOpc = X86::NOT32r; return X86::AND32rr;
14422 case X86::ATOMNAND64: ExtraOpc = X86::NOT64r; return X86::AND64rr;
14423 case X86::ATOMMAX8: ExtraOpc = X86::CMP8rr; return X86::CMOVL32rr;
14424 case X86::ATOMMAX16: ExtraOpc = X86::CMP16rr; return X86::CMOVL16rr;
14425 case X86::ATOMMAX32: ExtraOpc = X86::CMP32rr; return X86::CMOVL32rr;
14426 case X86::ATOMMAX64: ExtraOpc = X86::CMP64rr; return X86::CMOVL64rr;
14427 case X86::ATOMMIN8: ExtraOpc = X86::CMP8rr; return X86::CMOVG32rr;
14428 case X86::ATOMMIN16: ExtraOpc = X86::CMP16rr; return X86::CMOVG16rr;
14429 case X86::ATOMMIN32: ExtraOpc = X86::CMP32rr; return X86::CMOVG32rr;
14430 case X86::ATOMMIN64: ExtraOpc = X86::CMP64rr; return X86::CMOVG64rr;
14431 case X86::ATOMUMAX8: ExtraOpc = X86::CMP8rr; return X86::CMOVB32rr;
14432 case X86::ATOMUMAX16: ExtraOpc = X86::CMP16rr; return X86::CMOVB16rr;
14433 case X86::ATOMUMAX32: ExtraOpc = X86::CMP32rr; return X86::CMOVB32rr;
14434 case X86::ATOMUMAX64: ExtraOpc = X86::CMP64rr; return X86::CMOVB64rr;
14435 case X86::ATOMUMIN8: ExtraOpc = X86::CMP8rr; return X86::CMOVA32rr;
14436 case X86::ATOMUMIN16: ExtraOpc = X86::CMP16rr; return X86::CMOVA16rr;
14437 case X86::ATOMUMIN32: ExtraOpc = X86::CMP32rr; return X86::CMOVA32rr;
14438 case X86::ATOMUMIN64: ExtraOpc = X86::CMP64rr; return X86::CMOVA64rr;
14440 llvm_unreachable("Unhandled atomic-load-op opcode!");
14443 // Get opcode of the non-atomic one from the specified atomic instruction for
14444 // 64-bit data type on 32-bit target.
14445 static unsigned getNonAtomic6432Opcode(unsigned Opc, unsigned &HiOpc) {
14447 case X86::ATOMAND6432: HiOpc = X86::AND32rr; return X86::AND32rr;
14448 case X86::ATOMOR6432: HiOpc = X86::OR32rr; return X86::OR32rr;
14449 case X86::ATOMXOR6432: HiOpc = X86::XOR32rr; return X86::XOR32rr;
14450 case X86::ATOMADD6432: HiOpc = X86::ADC32rr; return X86::ADD32rr;
14451 case X86::ATOMSUB6432: HiOpc = X86::SBB32rr; return X86::SUB32rr;
14452 case X86::ATOMSWAP6432: HiOpc = X86::MOV32rr; return X86::MOV32rr;
14453 case X86::ATOMMAX6432: HiOpc = X86::SETLr; return X86::SETLr;
14454 case X86::ATOMMIN6432: HiOpc = X86::SETGr; return X86::SETGr;
14455 case X86::ATOMUMAX6432: HiOpc = X86::SETBr; return X86::SETBr;
14456 case X86::ATOMUMIN6432: HiOpc = X86::SETAr; return X86::SETAr;
14458 llvm_unreachable("Unhandled atomic-load-op opcode!");
14461 // Get opcode of the non-atomic one from the specified atomic instruction for
14462 // 64-bit data type on 32-bit target with extra opcode.
14463 static unsigned getNonAtomic6432OpcodeWithExtraOpc(unsigned Opc,
14465 unsigned &ExtraOpc) {
14467 case X86::ATOMNAND6432:
14468 ExtraOpc = X86::NOT32r;
14469 HiOpc = X86::AND32rr;
14470 return X86::AND32rr;
14472 llvm_unreachable("Unhandled atomic-load-op opcode!");
14475 // Get pseudo CMOV opcode from the specified data type.
14476 static unsigned getPseudoCMOVOpc(EVT VT) {
14477 switch (VT.getSimpleVT().SimpleTy) {
14478 case MVT::i8: return X86::CMOV_GR8;
14479 case MVT::i16: return X86::CMOV_GR16;
14480 case MVT::i32: return X86::CMOV_GR32;
14484 llvm_unreachable("Unknown CMOV opcode!");
14487 // EmitAtomicLoadArith - emit the code sequence for pseudo atomic instructions.
14488 // They will be translated into a spin-loop or compare-exchange loop from
14491 // dst = atomic-fetch-op MI.addr, MI.val
14497 // t1 = LOAD MI.addr
14499 // t4 = phi(t1, t3 / loop)
14500 // t2 = OP MI.val, t4
14502 // LCMPXCHG [MI.addr], t2, [EAX is implicitly used & defined]
14508 MachineBasicBlock *
14509 X86TargetLowering::EmitAtomicLoadArith(MachineInstr *MI,
14510 MachineBasicBlock *MBB) const {
14511 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14512 DebugLoc DL = MI->getDebugLoc();
14514 MachineFunction *MF = MBB->getParent();
14515 MachineRegisterInfo &MRI = MF->getRegInfo();
14517 const BasicBlock *BB = MBB->getBasicBlock();
14518 MachineFunction::iterator I = MBB;
14521 assert(MI->getNumOperands() <= X86::AddrNumOperands + 4 &&
14522 "Unexpected number of operands");
14524 assert(MI->hasOneMemOperand() &&
14525 "Expected atomic-load-op to have one memoperand");
14527 // Memory Reference
14528 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
14529 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
14531 unsigned DstReg, SrcReg;
14532 unsigned MemOpndSlot;
14534 unsigned CurOp = 0;
14536 DstReg = MI->getOperand(CurOp++).getReg();
14537 MemOpndSlot = CurOp;
14538 CurOp += X86::AddrNumOperands;
14539 SrcReg = MI->getOperand(CurOp++).getReg();
14541 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
14542 MVT::SimpleValueType VT = *RC->vt_begin();
14543 unsigned t1 = MRI.createVirtualRegister(RC);
14544 unsigned t2 = MRI.createVirtualRegister(RC);
14545 unsigned t3 = MRI.createVirtualRegister(RC);
14546 unsigned t4 = MRI.createVirtualRegister(RC);
14547 unsigned PhyReg = getX86SubSuperRegister(X86::EAX, VT);
14549 unsigned LCMPXCHGOpc = getCmpXChgOpcode(VT);
14550 unsigned LOADOpc = getLoadOpcode(VT);
14552 // For the atomic load-arith operator, we generate
14555 // t1 = LOAD [MI.addr]
14557 // t4 = phi(t1 / thisMBB, t3 / mainMBB)
14558 // t1 = OP MI.val, EAX
14560 // LCMPXCHG [MI.addr], t1, [EAX is implicitly used & defined]
14566 MachineBasicBlock *thisMBB = MBB;
14567 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
14568 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
14569 MF->insert(I, mainMBB);
14570 MF->insert(I, sinkMBB);
14572 MachineInstrBuilder MIB;
14574 // Transfer the remainder of BB and its successor edges to sinkMBB.
14575 sinkMBB->splice(sinkMBB->begin(), MBB,
14576 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
14577 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
14580 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), t1);
14581 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14582 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14584 NewMO.setIsKill(false);
14585 MIB.addOperand(NewMO);
14587 for (MachineInstr::mmo_iterator MMOI = MMOBegin; MMOI != MMOEnd; ++MMOI) {
14588 unsigned flags = (*MMOI)->getFlags();
14589 flags = (flags & ~MachineMemOperand::MOStore) | MachineMemOperand::MOLoad;
14590 MachineMemOperand *MMO =
14591 MF->getMachineMemOperand((*MMOI)->getPointerInfo(), flags,
14592 (*MMOI)->getSize(),
14593 (*MMOI)->getBaseAlignment(),
14594 (*MMOI)->getTBAAInfo(),
14595 (*MMOI)->getRanges());
14596 MIB.addMemOperand(MMO);
14599 thisMBB->addSuccessor(mainMBB);
14602 MachineBasicBlock *origMainMBB = mainMBB;
14605 MachineInstr *Phi = BuildMI(mainMBB, DL, TII->get(X86::PHI), t4)
14606 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(mainMBB);
14608 unsigned Opc = MI->getOpcode();
14611 llvm_unreachable("Unhandled atomic-load-op opcode!");
14612 case X86::ATOMAND8:
14613 case X86::ATOMAND16:
14614 case X86::ATOMAND32:
14615 case X86::ATOMAND64:
14617 case X86::ATOMOR16:
14618 case X86::ATOMOR32:
14619 case X86::ATOMOR64:
14620 case X86::ATOMXOR8:
14621 case X86::ATOMXOR16:
14622 case X86::ATOMXOR32:
14623 case X86::ATOMXOR64: {
14624 unsigned ARITHOpc = getNonAtomicOpcode(Opc);
14625 BuildMI(mainMBB, DL, TII->get(ARITHOpc), t2).addReg(SrcReg)
14629 case X86::ATOMNAND8:
14630 case X86::ATOMNAND16:
14631 case X86::ATOMNAND32:
14632 case X86::ATOMNAND64: {
14633 unsigned Tmp = MRI.createVirtualRegister(RC);
14635 unsigned ANDOpc = getNonAtomicOpcodeWithExtraOpc(Opc, NOTOpc);
14636 BuildMI(mainMBB, DL, TII->get(ANDOpc), Tmp).addReg(SrcReg)
14638 BuildMI(mainMBB, DL, TII->get(NOTOpc), t2).addReg(Tmp);
14641 case X86::ATOMMAX8:
14642 case X86::ATOMMAX16:
14643 case X86::ATOMMAX32:
14644 case X86::ATOMMAX64:
14645 case X86::ATOMMIN8:
14646 case X86::ATOMMIN16:
14647 case X86::ATOMMIN32:
14648 case X86::ATOMMIN64:
14649 case X86::ATOMUMAX8:
14650 case X86::ATOMUMAX16:
14651 case X86::ATOMUMAX32:
14652 case X86::ATOMUMAX64:
14653 case X86::ATOMUMIN8:
14654 case X86::ATOMUMIN16:
14655 case X86::ATOMUMIN32:
14656 case X86::ATOMUMIN64: {
14658 unsigned CMOVOpc = getNonAtomicOpcodeWithExtraOpc(Opc, CMPOpc);
14660 BuildMI(mainMBB, DL, TII->get(CMPOpc))
14664 if (Subtarget->hasCMov()) {
14665 if (VT != MVT::i8) {
14667 BuildMI(mainMBB, DL, TII->get(CMOVOpc), t2)
14671 // Promote i8 to i32 to use CMOV32
14672 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
14673 const TargetRegisterClass *RC32 =
14674 TRI->getSubClassWithSubReg(getRegClassFor(MVT::i32), X86::sub_8bit);
14675 unsigned SrcReg32 = MRI.createVirtualRegister(RC32);
14676 unsigned AccReg32 = MRI.createVirtualRegister(RC32);
14677 unsigned Tmp = MRI.createVirtualRegister(RC32);
14679 unsigned Undef = MRI.createVirtualRegister(RC32);
14680 BuildMI(mainMBB, DL, TII->get(TargetOpcode::IMPLICIT_DEF), Undef);
14682 BuildMI(mainMBB, DL, TII->get(TargetOpcode::INSERT_SUBREG), SrcReg32)
14685 .addImm(X86::sub_8bit);
14686 BuildMI(mainMBB, DL, TII->get(TargetOpcode::INSERT_SUBREG), AccReg32)
14689 .addImm(X86::sub_8bit);
14691 BuildMI(mainMBB, DL, TII->get(CMOVOpc), Tmp)
14695 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t2)
14696 .addReg(Tmp, 0, X86::sub_8bit);
14699 // Use pseudo select and lower them.
14700 assert((VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32) &&
14701 "Invalid atomic-load-op transformation!");
14702 unsigned SelOpc = getPseudoCMOVOpc(VT);
14703 X86::CondCode CC = X86::getCondFromCMovOpc(CMOVOpc);
14704 assert(CC != X86::COND_INVALID && "Invalid atomic-load-op transformation!");
14705 MIB = BuildMI(mainMBB, DL, TII->get(SelOpc), t2)
14706 .addReg(SrcReg).addReg(t4)
14708 mainMBB = EmitLoweredSelect(MIB, mainMBB);
14709 // Replace the original PHI node as mainMBB is changed after CMOV
14711 BuildMI(*origMainMBB, Phi, DL, TII->get(X86::PHI), t4)
14712 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(mainMBB);
14713 Phi->eraseFromParent();
14719 // Copy PhyReg back from virtual register.
14720 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), PhyReg)
14723 MIB = BuildMI(mainMBB, DL, TII->get(LCMPXCHGOpc));
14724 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14725 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14727 NewMO.setIsKill(false);
14728 MIB.addOperand(NewMO);
14731 MIB.setMemRefs(MMOBegin, MMOEnd);
14733 // Copy PhyReg back to virtual register.
14734 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t3)
14737 BuildMI(mainMBB, DL, TII->get(X86::JNE_4)).addMBB(origMainMBB);
14739 mainMBB->addSuccessor(origMainMBB);
14740 mainMBB->addSuccessor(sinkMBB);
14743 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
14744 TII->get(TargetOpcode::COPY), DstReg)
14747 MI->eraseFromParent();
14751 // EmitAtomicLoadArith6432 - emit the code sequence for pseudo atomic
14752 // instructions. They will be translated into a spin-loop or compare-exchange
14756 // dst = atomic-fetch-op MI.addr, MI.val
14762 // t1L = LOAD [MI.addr + 0]
14763 // t1H = LOAD [MI.addr + 4]
14765 // t4L = phi(t1L, t3L / loop)
14766 // t4H = phi(t1H, t3H / loop)
14767 // t2L = OP MI.val.lo, t4L
14768 // t2H = OP MI.val.hi, t4H
14773 // LCMPXCHG8B [MI.addr], [ECX:EBX & EDX:EAX are implicitly used and EDX:EAX is implicitly defined]
14781 MachineBasicBlock *
14782 X86TargetLowering::EmitAtomicLoadArith6432(MachineInstr *MI,
14783 MachineBasicBlock *MBB) const {
14784 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14785 DebugLoc DL = MI->getDebugLoc();
14787 MachineFunction *MF = MBB->getParent();
14788 MachineRegisterInfo &MRI = MF->getRegInfo();
14790 const BasicBlock *BB = MBB->getBasicBlock();
14791 MachineFunction::iterator I = MBB;
14794 assert(MI->getNumOperands() <= X86::AddrNumOperands + 7 &&
14795 "Unexpected number of operands");
14797 assert(MI->hasOneMemOperand() &&
14798 "Expected atomic-load-op32 to have one memoperand");
14800 // Memory Reference
14801 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
14802 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
14804 unsigned DstLoReg, DstHiReg;
14805 unsigned SrcLoReg, SrcHiReg;
14806 unsigned MemOpndSlot;
14808 unsigned CurOp = 0;
14810 DstLoReg = MI->getOperand(CurOp++).getReg();
14811 DstHiReg = MI->getOperand(CurOp++).getReg();
14812 MemOpndSlot = CurOp;
14813 CurOp += X86::AddrNumOperands;
14814 SrcLoReg = MI->getOperand(CurOp++).getReg();
14815 SrcHiReg = MI->getOperand(CurOp++).getReg();
14817 const TargetRegisterClass *RC = &X86::GR32RegClass;
14818 const TargetRegisterClass *RC8 = &X86::GR8RegClass;
14820 unsigned t1L = MRI.createVirtualRegister(RC);
14821 unsigned t1H = MRI.createVirtualRegister(RC);
14822 unsigned t2L = MRI.createVirtualRegister(RC);
14823 unsigned t2H = MRI.createVirtualRegister(RC);
14824 unsigned t3L = MRI.createVirtualRegister(RC);
14825 unsigned t3H = MRI.createVirtualRegister(RC);
14826 unsigned t4L = MRI.createVirtualRegister(RC);
14827 unsigned t4H = MRI.createVirtualRegister(RC);
14829 unsigned LCMPXCHGOpc = X86::LCMPXCHG8B;
14830 unsigned LOADOpc = X86::MOV32rm;
14832 // For the atomic load-arith operator, we generate
14835 // t1L = LOAD [MI.addr + 0]
14836 // t1H = LOAD [MI.addr + 4]
14838 // t4L = phi(t1L / thisMBB, t3L / mainMBB)
14839 // t4H = phi(t1H / thisMBB, t3H / mainMBB)
14840 // t2L = OP MI.val.lo, t4L
14841 // t2H = OP MI.val.hi, t4H
14844 // LCMPXCHG8B [MI.addr], [ECX:EBX & EDX:EAX are implicitly used and EDX:EAX is implicitly defined]
14852 MachineBasicBlock *thisMBB = MBB;
14853 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
14854 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
14855 MF->insert(I, mainMBB);
14856 MF->insert(I, sinkMBB);
14858 MachineInstrBuilder MIB;
14860 // Transfer the remainder of BB and its successor edges to sinkMBB.
14861 sinkMBB->splice(sinkMBB->begin(), MBB,
14862 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
14863 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
14867 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), t1L);
14868 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14869 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14871 NewMO.setIsKill(false);
14872 MIB.addOperand(NewMO);
14874 for (MachineInstr::mmo_iterator MMOI = MMOBegin; MMOI != MMOEnd; ++MMOI) {
14875 unsigned flags = (*MMOI)->getFlags();
14876 flags = (flags & ~MachineMemOperand::MOStore) | MachineMemOperand::MOLoad;
14877 MachineMemOperand *MMO =
14878 MF->getMachineMemOperand((*MMOI)->getPointerInfo(), flags,
14879 (*MMOI)->getSize(),
14880 (*MMOI)->getBaseAlignment(),
14881 (*MMOI)->getTBAAInfo(),
14882 (*MMOI)->getRanges());
14883 MIB.addMemOperand(MMO);
14885 MachineInstr *LowMI = MIB;
14888 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), t1H);
14889 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14890 if (i == X86::AddrDisp) {
14891 MIB.addDisp(MI->getOperand(MemOpndSlot + i), 4); // 4 == sizeof(i32)
14893 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14895 NewMO.setIsKill(false);
14896 MIB.addOperand(NewMO);
14899 MIB.setMemRefs(LowMI->memoperands_begin(), LowMI->memoperands_end());
14901 thisMBB->addSuccessor(mainMBB);
14904 MachineBasicBlock *origMainMBB = mainMBB;
14907 MachineInstr *PhiL = BuildMI(mainMBB, DL, TII->get(X86::PHI), t4L)
14908 .addReg(t1L).addMBB(thisMBB).addReg(t3L).addMBB(mainMBB);
14909 MachineInstr *PhiH = BuildMI(mainMBB, DL, TII->get(X86::PHI), t4H)
14910 .addReg(t1H).addMBB(thisMBB).addReg(t3H).addMBB(mainMBB);
14912 unsigned Opc = MI->getOpcode();
14915 llvm_unreachable("Unhandled atomic-load-op6432 opcode!");
14916 case X86::ATOMAND6432:
14917 case X86::ATOMOR6432:
14918 case X86::ATOMXOR6432:
14919 case X86::ATOMADD6432:
14920 case X86::ATOMSUB6432: {
14922 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
14923 BuildMI(mainMBB, DL, TII->get(LoOpc), t2L).addReg(t4L)
14925 BuildMI(mainMBB, DL, TII->get(HiOpc), t2H).addReg(t4H)
14929 case X86::ATOMNAND6432: {
14930 unsigned HiOpc, NOTOpc;
14931 unsigned LoOpc = getNonAtomic6432OpcodeWithExtraOpc(Opc, HiOpc, NOTOpc);
14932 unsigned TmpL = MRI.createVirtualRegister(RC);
14933 unsigned TmpH = MRI.createVirtualRegister(RC);
14934 BuildMI(mainMBB, DL, TII->get(LoOpc), TmpL).addReg(SrcLoReg)
14936 BuildMI(mainMBB, DL, TII->get(HiOpc), TmpH).addReg(SrcHiReg)
14938 BuildMI(mainMBB, DL, TII->get(NOTOpc), t2L).addReg(TmpL);
14939 BuildMI(mainMBB, DL, TII->get(NOTOpc), t2H).addReg(TmpH);
14942 case X86::ATOMMAX6432:
14943 case X86::ATOMMIN6432:
14944 case X86::ATOMUMAX6432:
14945 case X86::ATOMUMIN6432: {
14947 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
14948 unsigned cL = MRI.createVirtualRegister(RC8);
14949 unsigned cH = MRI.createVirtualRegister(RC8);
14950 unsigned cL32 = MRI.createVirtualRegister(RC);
14951 unsigned cH32 = MRI.createVirtualRegister(RC);
14952 unsigned cc = MRI.createVirtualRegister(RC);
14953 // cl := cmp src_lo, lo
14954 BuildMI(mainMBB, DL, TII->get(X86::CMP32rr))
14955 .addReg(SrcLoReg).addReg(t4L);
14956 BuildMI(mainMBB, DL, TII->get(LoOpc), cL);
14957 BuildMI(mainMBB, DL, TII->get(X86::MOVZX32rr8), cL32).addReg(cL);
14958 // ch := cmp src_hi, hi
14959 BuildMI(mainMBB, DL, TII->get(X86::CMP32rr))
14960 .addReg(SrcHiReg).addReg(t4H);
14961 BuildMI(mainMBB, DL, TII->get(HiOpc), cH);
14962 BuildMI(mainMBB, DL, TII->get(X86::MOVZX32rr8), cH32).addReg(cH);
14963 // cc := if (src_hi == hi) ? cl : ch;
14964 if (Subtarget->hasCMov()) {
14965 BuildMI(mainMBB, DL, TII->get(X86::CMOVE32rr), cc)
14966 .addReg(cH32).addReg(cL32);
14968 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), cc)
14969 .addReg(cH32).addReg(cL32)
14970 .addImm(X86::COND_E);
14971 mainMBB = EmitLoweredSelect(MIB, mainMBB);
14973 BuildMI(mainMBB, DL, TII->get(X86::TEST32rr)).addReg(cc).addReg(cc);
14974 if (Subtarget->hasCMov()) {
14975 BuildMI(mainMBB, DL, TII->get(X86::CMOVNE32rr), t2L)
14976 .addReg(SrcLoReg).addReg(t4L);
14977 BuildMI(mainMBB, DL, TII->get(X86::CMOVNE32rr), t2H)
14978 .addReg(SrcHiReg).addReg(t4H);
14980 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), t2L)
14981 .addReg(SrcLoReg).addReg(t4L)
14982 .addImm(X86::COND_NE);
14983 mainMBB = EmitLoweredSelect(MIB, mainMBB);
14984 // As the lowered CMOV won't clobber EFLAGS, we could reuse it for the
14985 // 2nd CMOV lowering.
14986 mainMBB->addLiveIn(X86::EFLAGS);
14987 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), t2H)
14988 .addReg(SrcHiReg).addReg(t4H)
14989 .addImm(X86::COND_NE);
14990 mainMBB = EmitLoweredSelect(MIB, mainMBB);
14991 // Replace the original PHI node as mainMBB is changed after CMOV
14993 BuildMI(*origMainMBB, PhiL, DL, TII->get(X86::PHI), t4L)
14994 .addReg(t1L).addMBB(thisMBB).addReg(t3L).addMBB(mainMBB);
14995 BuildMI(*origMainMBB, PhiH, DL, TII->get(X86::PHI), t4H)
14996 .addReg(t1H).addMBB(thisMBB).addReg(t3H).addMBB(mainMBB);
14997 PhiL->eraseFromParent();
14998 PhiH->eraseFromParent();
15002 case X86::ATOMSWAP6432: {
15004 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
15005 BuildMI(mainMBB, DL, TII->get(LoOpc), t2L).addReg(SrcLoReg);
15006 BuildMI(mainMBB, DL, TII->get(HiOpc), t2H).addReg(SrcHiReg);
15011 // Copy EDX:EAX back from HiReg:LoReg
15012 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EAX).addReg(t4L);
15013 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EDX).addReg(t4H);
15014 // Copy ECX:EBX from t1H:t1L
15015 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EBX).addReg(t2L);
15016 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::ECX).addReg(t2H);
15018 MIB = BuildMI(mainMBB, DL, TII->get(LCMPXCHGOpc));
15019 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
15020 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
15022 NewMO.setIsKill(false);
15023 MIB.addOperand(NewMO);
15025 MIB.setMemRefs(MMOBegin, MMOEnd);
15027 // Copy EDX:EAX back to t3H:t3L
15028 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t3L).addReg(X86::EAX);
15029 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t3H).addReg(X86::EDX);
15031 BuildMI(mainMBB, DL, TII->get(X86::JNE_4)).addMBB(origMainMBB);
15033 mainMBB->addSuccessor(origMainMBB);
15034 mainMBB->addSuccessor(sinkMBB);
15037 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
15038 TII->get(TargetOpcode::COPY), DstLoReg)
15040 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
15041 TII->get(TargetOpcode::COPY), DstHiReg)
15044 MI->eraseFromParent();
15048 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
15049 // or XMM0_V32I8 in AVX all of this code can be replaced with that
15050 // in the .td file.
15051 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
15052 const TargetInstrInfo *TII) {
15054 switch (MI->getOpcode()) {
15055 default: llvm_unreachable("illegal opcode!");
15056 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
15057 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
15058 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
15059 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
15060 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
15061 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
15062 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
15063 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
15066 DebugLoc dl = MI->getDebugLoc();
15067 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
15069 unsigned NumArgs = MI->getNumOperands();
15070 for (unsigned i = 1; i < NumArgs; ++i) {
15071 MachineOperand &Op = MI->getOperand(i);
15072 if (!(Op.isReg() && Op.isImplicit()))
15073 MIB.addOperand(Op);
15075 if (MI->hasOneMemOperand())
15076 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
15078 BuildMI(*BB, MI, dl,
15079 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
15080 .addReg(X86::XMM0);
15082 MI->eraseFromParent();
15086 // FIXME: Custom handling because TableGen doesn't support multiple implicit
15087 // defs in an instruction pattern
15088 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
15089 const TargetInstrInfo *TII) {
15091 switch (MI->getOpcode()) {
15092 default: llvm_unreachable("illegal opcode!");
15093 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
15094 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
15095 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
15096 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
15097 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
15098 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
15099 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
15100 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
15103 DebugLoc dl = MI->getDebugLoc();
15104 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
15106 unsigned NumArgs = MI->getNumOperands(); // remove the results
15107 for (unsigned i = 1; i < NumArgs; ++i) {
15108 MachineOperand &Op = MI->getOperand(i);
15109 if (!(Op.isReg() && Op.isImplicit()))
15110 MIB.addOperand(Op);
15112 if (MI->hasOneMemOperand())
15113 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
15115 BuildMI(*BB, MI, dl,
15116 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
15119 MI->eraseFromParent();
15123 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
15124 const TargetInstrInfo *TII,
15125 const X86Subtarget* Subtarget) {
15126 DebugLoc dl = MI->getDebugLoc();
15128 // Address into RAX/EAX, other two args into ECX, EDX.
15129 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
15130 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
15131 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
15132 for (int i = 0; i < X86::AddrNumOperands; ++i)
15133 MIB.addOperand(MI->getOperand(i));
15135 unsigned ValOps = X86::AddrNumOperands;
15136 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
15137 .addReg(MI->getOperand(ValOps).getReg());
15138 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
15139 .addReg(MI->getOperand(ValOps+1).getReg());
15141 // The instruction doesn't actually take any operands though.
15142 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
15144 MI->eraseFromParent(); // The pseudo is gone now.
15148 MachineBasicBlock *
15149 X86TargetLowering::EmitVAARG64WithCustomInserter(
15151 MachineBasicBlock *MBB) const {
15152 // Emit va_arg instruction on X86-64.
15154 // Operands to this pseudo-instruction:
15155 // 0 ) Output : destination address (reg)
15156 // 1-5) Input : va_list address (addr, i64mem)
15157 // 6 ) ArgSize : Size (in bytes) of vararg type
15158 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
15159 // 8 ) Align : Alignment of type
15160 // 9 ) EFLAGS (implicit-def)
15162 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
15163 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
15165 unsigned DestReg = MI->getOperand(0).getReg();
15166 MachineOperand &Base = MI->getOperand(1);
15167 MachineOperand &Scale = MI->getOperand(2);
15168 MachineOperand &Index = MI->getOperand(3);
15169 MachineOperand &Disp = MI->getOperand(4);
15170 MachineOperand &Segment = MI->getOperand(5);
15171 unsigned ArgSize = MI->getOperand(6).getImm();
15172 unsigned ArgMode = MI->getOperand(7).getImm();
15173 unsigned Align = MI->getOperand(8).getImm();
15175 // Memory Reference
15176 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
15177 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
15178 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
15180 // Machine Information
15181 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15182 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
15183 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
15184 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
15185 DebugLoc DL = MI->getDebugLoc();
15187 // struct va_list {
15190 // i64 overflow_area (address)
15191 // i64 reg_save_area (address)
15193 // sizeof(va_list) = 24
15194 // alignment(va_list) = 8
15196 unsigned TotalNumIntRegs = 6;
15197 unsigned TotalNumXMMRegs = 8;
15198 bool UseGPOffset = (ArgMode == 1);
15199 bool UseFPOffset = (ArgMode == 2);
15200 unsigned MaxOffset = TotalNumIntRegs * 8 +
15201 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
15203 /* Align ArgSize to a multiple of 8 */
15204 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
15205 bool NeedsAlign = (Align > 8);
15207 MachineBasicBlock *thisMBB = MBB;
15208 MachineBasicBlock *overflowMBB;
15209 MachineBasicBlock *offsetMBB;
15210 MachineBasicBlock *endMBB;
15212 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
15213 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
15214 unsigned OffsetReg = 0;
15216 if (!UseGPOffset && !UseFPOffset) {
15217 // If we only pull from the overflow region, we don't create a branch.
15218 // We don't need to alter control flow.
15219 OffsetDestReg = 0; // unused
15220 OverflowDestReg = DestReg;
15223 overflowMBB = thisMBB;
15226 // First emit code to check if gp_offset (or fp_offset) is below the bound.
15227 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
15228 // If not, pull from overflow_area. (branch to overflowMBB)
15233 // offsetMBB overflowMBB
15238 // Registers for the PHI in endMBB
15239 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
15240 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
15242 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
15243 MachineFunction *MF = MBB->getParent();
15244 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
15245 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
15246 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
15248 MachineFunction::iterator MBBIter = MBB;
15251 // Insert the new basic blocks
15252 MF->insert(MBBIter, offsetMBB);
15253 MF->insert(MBBIter, overflowMBB);
15254 MF->insert(MBBIter, endMBB);
15256 // Transfer the remainder of MBB and its successor edges to endMBB.
15257 endMBB->splice(endMBB->begin(), thisMBB,
15258 llvm::next(MachineBasicBlock::iterator(MI)),
15260 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
15262 // Make offsetMBB and overflowMBB successors of thisMBB
15263 thisMBB->addSuccessor(offsetMBB);
15264 thisMBB->addSuccessor(overflowMBB);
15266 // endMBB is a successor of both offsetMBB and overflowMBB
15267 offsetMBB->addSuccessor(endMBB);
15268 overflowMBB->addSuccessor(endMBB);
15270 // Load the offset value into a register
15271 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
15272 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
15276 .addDisp(Disp, UseFPOffset ? 4 : 0)
15277 .addOperand(Segment)
15278 .setMemRefs(MMOBegin, MMOEnd);
15280 // Check if there is enough room left to pull this argument.
15281 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
15283 .addImm(MaxOffset + 8 - ArgSizeA8);
15285 // Branch to "overflowMBB" if offset >= max
15286 // Fall through to "offsetMBB" otherwise
15287 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
15288 .addMBB(overflowMBB);
15291 // In offsetMBB, emit code to use the reg_save_area.
15293 assert(OffsetReg != 0);
15295 // Read the reg_save_area address.
15296 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
15297 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
15302 .addOperand(Segment)
15303 .setMemRefs(MMOBegin, MMOEnd);
15305 // Zero-extend the offset
15306 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
15307 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
15310 .addImm(X86::sub_32bit);
15312 // Add the offset to the reg_save_area to get the final address.
15313 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
15314 .addReg(OffsetReg64)
15315 .addReg(RegSaveReg);
15317 // Compute the offset for the next argument
15318 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
15319 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
15321 .addImm(UseFPOffset ? 16 : 8);
15323 // Store it back into the va_list.
15324 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
15328 .addDisp(Disp, UseFPOffset ? 4 : 0)
15329 .addOperand(Segment)
15330 .addReg(NextOffsetReg)
15331 .setMemRefs(MMOBegin, MMOEnd);
15334 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
15339 // Emit code to use overflow area
15342 // Load the overflow_area address into a register.
15343 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
15344 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
15349 .addOperand(Segment)
15350 .setMemRefs(MMOBegin, MMOEnd);
15352 // If we need to align it, do so. Otherwise, just copy the address
15353 // to OverflowDestReg.
15355 // Align the overflow address
15356 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
15357 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
15359 // aligned_addr = (addr + (align-1)) & ~(align-1)
15360 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
15361 .addReg(OverflowAddrReg)
15364 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
15366 .addImm(~(uint64_t)(Align-1));
15368 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
15369 .addReg(OverflowAddrReg);
15372 // Compute the next overflow address after this argument.
15373 // (the overflow address should be kept 8-byte aligned)
15374 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
15375 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
15376 .addReg(OverflowDestReg)
15377 .addImm(ArgSizeA8);
15379 // Store the new overflow address.
15380 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
15385 .addOperand(Segment)
15386 .addReg(NextAddrReg)
15387 .setMemRefs(MMOBegin, MMOEnd);
15389 // If we branched, emit the PHI to the front of endMBB.
15391 BuildMI(*endMBB, endMBB->begin(), DL,
15392 TII->get(X86::PHI), DestReg)
15393 .addReg(OffsetDestReg).addMBB(offsetMBB)
15394 .addReg(OverflowDestReg).addMBB(overflowMBB);
15397 // Erase the pseudo instruction
15398 MI->eraseFromParent();
15403 MachineBasicBlock *
15404 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
15406 MachineBasicBlock *MBB) const {
15407 // Emit code to save XMM registers to the stack. The ABI says that the
15408 // number of registers to save is given in %al, so it's theoretically
15409 // possible to do an indirect jump trick to avoid saving all of them,
15410 // however this code takes a simpler approach and just executes all
15411 // of the stores if %al is non-zero. It's less code, and it's probably
15412 // easier on the hardware branch predictor, and stores aren't all that
15413 // expensive anyway.
15415 // Create the new basic blocks. One block contains all the XMM stores,
15416 // and one block is the final destination regardless of whether any
15417 // stores were performed.
15418 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
15419 MachineFunction *F = MBB->getParent();
15420 MachineFunction::iterator MBBIter = MBB;
15422 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
15423 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
15424 F->insert(MBBIter, XMMSaveMBB);
15425 F->insert(MBBIter, EndMBB);
15427 // Transfer the remainder of MBB and its successor edges to EndMBB.
15428 EndMBB->splice(EndMBB->begin(), MBB,
15429 llvm::next(MachineBasicBlock::iterator(MI)),
15431 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
15433 // The original block will now fall through to the XMM save block.
15434 MBB->addSuccessor(XMMSaveMBB);
15435 // The XMMSaveMBB will fall through to the end block.
15436 XMMSaveMBB->addSuccessor(EndMBB);
15438 // Now add the instructions.
15439 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15440 DebugLoc DL = MI->getDebugLoc();
15442 unsigned CountReg = MI->getOperand(0).getReg();
15443 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
15444 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
15446 if (!Subtarget->isTargetWin64()) {
15447 // If %al is 0, branch around the XMM save block.
15448 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
15449 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
15450 MBB->addSuccessor(EndMBB);
15453 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
15454 // that was just emitted, but clearly shouldn't be "saved".
15455 assert((MI->getNumOperands() <= 3 ||
15456 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
15457 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
15458 && "Expected last argument to be EFLAGS");
15459 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
15460 // In the XMM save block, save all the XMM argument registers.
15461 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
15462 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
15463 MachineMemOperand *MMO =
15464 F->getMachineMemOperand(
15465 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
15466 MachineMemOperand::MOStore,
15467 /*Size=*/16, /*Align=*/16);
15468 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
15469 .addFrameIndex(RegSaveFrameIndex)
15470 .addImm(/*Scale=*/1)
15471 .addReg(/*IndexReg=*/0)
15472 .addImm(/*Disp=*/Offset)
15473 .addReg(/*Segment=*/0)
15474 .addReg(MI->getOperand(i).getReg())
15475 .addMemOperand(MMO);
15478 MI->eraseFromParent(); // The pseudo instruction is gone now.
15483 // The EFLAGS operand of SelectItr might be missing a kill marker
15484 // because there were multiple uses of EFLAGS, and ISel didn't know
15485 // which to mark. Figure out whether SelectItr should have had a
15486 // kill marker, and set it if it should. Returns the correct kill
15488 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
15489 MachineBasicBlock* BB,
15490 const TargetRegisterInfo* TRI) {
15491 // Scan forward through BB for a use/def of EFLAGS.
15492 MachineBasicBlock::iterator miI(llvm::next(SelectItr));
15493 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
15494 const MachineInstr& mi = *miI;
15495 if (mi.readsRegister(X86::EFLAGS))
15497 if (mi.definesRegister(X86::EFLAGS))
15498 break; // Should have kill-flag - update below.
15501 // If we hit the end of the block, check whether EFLAGS is live into a
15503 if (miI == BB->end()) {
15504 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
15505 sEnd = BB->succ_end();
15506 sItr != sEnd; ++sItr) {
15507 MachineBasicBlock* succ = *sItr;
15508 if (succ->isLiveIn(X86::EFLAGS))
15513 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
15514 // out. SelectMI should have a kill flag on EFLAGS.
15515 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
15519 MachineBasicBlock *
15520 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
15521 MachineBasicBlock *BB) const {
15522 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15523 DebugLoc DL = MI->getDebugLoc();
15525 // To "insert" a SELECT_CC instruction, we actually have to insert the
15526 // diamond control-flow pattern. The incoming instruction knows the
15527 // destination vreg to set, the condition code register to branch on, the
15528 // true/false values to select between, and a branch opcode to use.
15529 const BasicBlock *LLVM_BB = BB->getBasicBlock();
15530 MachineFunction::iterator It = BB;
15536 // cmpTY ccX, r1, r2
15538 // fallthrough --> copy0MBB
15539 MachineBasicBlock *thisMBB = BB;
15540 MachineFunction *F = BB->getParent();
15541 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
15542 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
15543 F->insert(It, copy0MBB);
15544 F->insert(It, sinkMBB);
15546 // If the EFLAGS register isn't dead in the terminator, then claim that it's
15547 // live into the sink and copy blocks.
15548 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
15549 if (!MI->killsRegister(X86::EFLAGS) &&
15550 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
15551 copy0MBB->addLiveIn(X86::EFLAGS);
15552 sinkMBB->addLiveIn(X86::EFLAGS);
15555 // Transfer the remainder of BB and its successor edges to sinkMBB.
15556 sinkMBB->splice(sinkMBB->begin(), BB,
15557 llvm::next(MachineBasicBlock::iterator(MI)),
15559 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
15561 // Add the true and fallthrough blocks as its successors.
15562 BB->addSuccessor(copy0MBB);
15563 BB->addSuccessor(sinkMBB);
15565 // Create the conditional branch instruction.
15567 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
15568 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
15571 // %FalseValue = ...
15572 // # fallthrough to sinkMBB
15573 copy0MBB->addSuccessor(sinkMBB);
15576 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
15578 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
15579 TII->get(X86::PHI), MI->getOperand(0).getReg())
15580 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
15581 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
15583 MI->eraseFromParent(); // The pseudo instruction is gone now.
15587 MachineBasicBlock *
15588 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
15589 bool Is64Bit) const {
15590 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15591 DebugLoc DL = MI->getDebugLoc();
15592 MachineFunction *MF = BB->getParent();
15593 const BasicBlock *LLVM_BB = BB->getBasicBlock();
15595 assert(getTargetMachine().Options.EnableSegmentedStacks);
15597 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
15598 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30;
15601 // ... [Till the alloca]
15602 // If stacklet is not large enough, jump to mallocMBB
15605 // Allocate by subtracting from RSP
15606 // Jump to continueMBB
15609 // Allocate by call to runtime
15613 // [rest of original BB]
15616 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
15617 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
15618 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
15620 MachineRegisterInfo &MRI = MF->getRegInfo();
15621 const TargetRegisterClass *AddrRegClass =
15622 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32);
15624 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
15625 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
15626 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
15627 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
15628 sizeVReg = MI->getOperand(1).getReg(),
15629 physSPReg = Is64Bit ? X86::RSP : X86::ESP;
15631 MachineFunction::iterator MBBIter = BB;
15634 MF->insert(MBBIter, bumpMBB);
15635 MF->insert(MBBIter, mallocMBB);
15636 MF->insert(MBBIter, continueMBB);
15638 continueMBB->splice(continueMBB->begin(), BB, llvm::next
15639 (MachineBasicBlock::iterator(MI)), BB->end());
15640 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
15642 // Add code to the main basic block to check if the stack limit has been hit,
15643 // and if so, jump to mallocMBB otherwise to bumpMBB.
15644 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
15645 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
15646 .addReg(tmpSPVReg).addReg(sizeVReg);
15647 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr))
15648 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
15649 .addReg(SPLimitVReg);
15650 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
15652 // bumpMBB simply decreases the stack pointer, since we know the current
15653 // stacklet has enough space.
15654 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
15655 .addReg(SPLimitVReg);
15656 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
15657 .addReg(SPLimitVReg);
15658 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
15660 // Calls into a routine in libgcc to allocate more space from the heap.
15661 const uint32_t *RegMask =
15662 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
15664 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
15666 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
15667 .addExternalSymbol("__morestack_allocate_stack_space")
15668 .addRegMask(RegMask)
15669 .addReg(X86::RDI, RegState::Implicit)
15670 .addReg(X86::RAX, RegState::ImplicitDefine);
15672 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
15674 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
15675 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
15676 .addExternalSymbol("__morestack_allocate_stack_space")
15677 .addRegMask(RegMask)
15678 .addReg(X86::EAX, RegState::ImplicitDefine);
15682 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
15685 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
15686 .addReg(Is64Bit ? X86::RAX : X86::EAX);
15687 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
15689 // Set up the CFG correctly.
15690 BB->addSuccessor(bumpMBB);
15691 BB->addSuccessor(mallocMBB);
15692 mallocMBB->addSuccessor(continueMBB);
15693 bumpMBB->addSuccessor(continueMBB);
15695 // Take care of the PHI nodes.
15696 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
15697 MI->getOperand(0).getReg())
15698 .addReg(mallocPtrVReg).addMBB(mallocMBB)
15699 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
15701 // Delete the original pseudo instruction.
15702 MI->eraseFromParent();
15705 return continueMBB;
15708 MachineBasicBlock *
15709 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
15710 MachineBasicBlock *BB) const {
15711 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15712 DebugLoc DL = MI->getDebugLoc();
15714 assert(!Subtarget->isTargetMacho());
15716 // The lowering is pretty easy: we're just emitting the call to _alloca. The
15717 // non-trivial part is impdef of ESP.
15719 if (Subtarget->isTargetWin64()) {
15720 if (Subtarget->isTargetCygMing()) {
15721 // ___chkstk(Mingw64):
15722 // Clobbers R10, R11, RAX and EFLAGS.
15724 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
15725 .addExternalSymbol("___chkstk")
15726 .addReg(X86::RAX, RegState::Implicit)
15727 .addReg(X86::RSP, RegState::Implicit)
15728 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
15729 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
15730 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
15732 // __chkstk(MSVCRT): does not update stack pointer.
15733 // Clobbers R10, R11 and EFLAGS.
15734 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
15735 .addExternalSymbol("__chkstk")
15736 .addReg(X86::RAX, RegState::Implicit)
15737 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
15738 // RAX has the offset to be subtracted from RSP.
15739 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
15744 const char *StackProbeSymbol =
15745 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca";
15747 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
15748 .addExternalSymbol(StackProbeSymbol)
15749 .addReg(X86::EAX, RegState::Implicit)
15750 .addReg(X86::ESP, RegState::Implicit)
15751 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
15752 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
15753 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
15756 MI->eraseFromParent(); // The pseudo instruction is gone now.
15760 MachineBasicBlock *
15761 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
15762 MachineBasicBlock *BB) const {
15763 // This is pretty easy. We're taking the value that we received from
15764 // our load from the relocation, sticking it in either RDI (x86-64)
15765 // or EAX and doing an indirect call. The return value will then
15766 // be in the normal return register.
15767 const X86InstrInfo *TII
15768 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
15769 DebugLoc DL = MI->getDebugLoc();
15770 MachineFunction *F = BB->getParent();
15772 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
15773 assert(MI->getOperand(3).isGlobal() && "This should be a global");
15775 // Get a register mask for the lowered call.
15776 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
15777 // proper register mask.
15778 const uint32_t *RegMask =
15779 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
15780 if (Subtarget->is64Bit()) {
15781 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
15782 TII->get(X86::MOV64rm), X86::RDI)
15784 .addImm(0).addReg(0)
15785 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
15786 MI->getOperand(3).getTargetFlags())
15788 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
15789 addDirectMem(MIB, X86::RDI);
15790 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
15791 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
15792 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
15793 TII->get(X86::MOV32rm), X86::EAX)
15795 .addImm(0).addReg(0)
15796 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
15797 MI->getOperand(3).getTargetFlags())
15799 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
15800 addDirectMem(MIB, X86::EAX);
15801 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
15803 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
15804 TII->get(X86::MOV32rm), X86::EAX)
15805 .addReg(TII->getGlobalBaseReg(F))
15806 .addImm(0).addReg(0)
15807 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
15808 MI->getOperand(3).getTargetFlags())
15810 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
15811 addDirectMem(MIB, X86::EAX);
15812 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
15815 MI->eraseFromParent(); // The pseudo instruction is gone now.
15819 MachineBasicBlock *
15820 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
15821 MachineBasicBlock *MBB) const {
15822 DebugLoc DL = MI->getDebugLoc();
15823 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15825 MachineFunction *MF = MBB->getParent();
15826 MachineRegisterInfo &MRI = MF->getRegInfo();
15828 const BasicBlock *BB = MBB->getBasicBlock();
15829 MachineFunction::iterator I = MBB;
15832 // Memory Reference
15833 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
15834 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
15837 unsigned MemOpndSlot = 0;
15839 unsigned CurOp = 0;
15841 DstReg = MI->getOperand(CurOp++).getReg();
15842 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
15843 assert(RC->hasType(MVT::i32) && "Invalid destination!");
15844 unsigned mainDstReg = MRI.createVirtualRegister(RC);
15845 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
15847 MemOpndSlot = CurOp;
15849 MVT PVT = getPointerTy();
15850 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
15851 "Invalid Pointer Size!");
15853 // For v = setjmp(buf), we generate
15856 // buf[LabelOffset] = restoreMBB
15857 // SjLjSetup restoreMBB
15863 // v = phi(main, restore)
15868 MachineBasicBlock *thisMBB = MBB;
15869 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
15870 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
15871 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
15872 MF->insert(I, mainMBB);
15873 MF->insert(I, sinkMBB);
15874 MF->push_back(restoreMBB);
15876 MachineInstrBuilder MIB;
15878 // Transfer the remainder of BB and its successor edges to sinkMBB.
15879 sinkMBB->splice(sinkMBB->begin(), MBB,
15880 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
15881 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
15884 unsigned PtrStoreOpc = 0;
15885 unsigned LabelReg = 0;
15886 const int64_t LabelOffset = 1 * PVT.getStoreSize();
15887 Reloc::Model RM = getTargetMachine().getRelocationModel();
15888 bool UseImmLabel = (getTargetMachine().getCodeModel() == CodeModel::Small) &&
15889 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
15891 // Prepare IP either in reg or imm.
15892 if (!UseImmLabel) {
15893 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
15894 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
15895 LabelReg = MRI.createVirtualRegister(PtrRC);
15896 if (Subtarget->is64Bit()) {
15897 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
15901 .addMBB(restoreMBB)
15904 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
15905 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
15906 .addReg(XII->getGlobalBaseReg(MF))
15909 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
15913 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
15915 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
15916 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
15917 if (i == X86::AddrDisp)
15918 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
15920 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
15923 MIB.addReg(LabelReg);
15925 MIB.addMBB(restoreMBB);
15926 MIB.setMemRefs(MMOBegin, MMOEnd);
15928 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
15929 .addMBB(restoreMBB);
15931 const X86RegisterInfo *RegInfo =
15932 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
15933 MIB.addRegMask(RegInfo->getNoPreservedMask());
15934 thisMBB->addSuccessor(mainMBB);
15935 thisMBB->addSuccessor(restoreMBB);
15939 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
15940 mainMBB->addSuccessor(sinkMBB);
15943 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
15944 TII->get(X86::PHI), DstReg)
15945 .addReg(mainDstReg).addMBB(mainMBB)
15946 .addReg(restoreDstReg).addMBB(restoreMBB);
15949 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
15950 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
15951 restoreMBB->addSuccessor(sinkMBB);
15953 MI->eraseFromParent();
15957 MachineBasicBlock *
15958 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
15959 MachineBasicBlock *MBB) const {
15960 DebugLoc DL = MI->getDebugLoc();
15961 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15963 MachineFunction *MF = MBB->getParent();
15964 MachineRegisterInfo &MRI = MF->getRegInfo();
15966 // Memory Reference
15967 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
15968 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
15970 MVT PVT = getPointerTy();
15971 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
15972 "Invalid Pointer Size!");
15974 const TargetRegisterClass *RC =
15975 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
15976 unsigned Tmp = MRI.createVirtualRegister(RC);
15977 // Since FP is only updated here but NOT referenced, it's treated as GPR.
15978 const X86RegisterInfo *RegInfo =
15979 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
15980 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
15981 unsigned SP = RegInfo->getStackRegister();
15983 MachineInstrBuilder MIB;
15985 const int64_t LabelOffset = 1 * PVT.getStoreSize();
15986 const int64_t SPOffset = 2 * PVT.getStoreSize();
15988 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
15989 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
15992 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
15993 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
15994 MIB.addOperand(MI->getOperand(i));
15995 MIB.setMemRefs(MMOBegin, MMOEnd);
15997 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
15998 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
15999 if (i == X86::AddrDisp)
16000 MIB.addDisp(MI->getOperand(i), LabelOffset);
16002 MIB.addOperand(MI->getOperand(i));
16004 MIB.setMemRefs(MMOBegin, MMOEnd);
16006 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
16007 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
16008 if (i == X86::AddrDisp)
16009 MIB.addDisp(MI->getOperand(i), SPOffset);
16011 MIB.addOperand(MI->getOperand(i));
16013 MIB.setMemRefs(MMOBegin, MMOEnd);
16015 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
16017 MI->eraseFromParent();
16021 // Replace 213-type (isel default) FMA3 instructions with 231-type for
16022 // accumulator loops. Writing back to the accumulator allows the coalescer
16023 // to remove extra copies in the loop.
16024 MachineBasicBlock *
16025 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
16026 MachineBasicBlock *MBB) const {
16027 MachineOperand &AddendOp = MI->getOperand(3);
16029 // Bail out early if the addend isn't a register - we can't switch these.
16030 if (!AddendOp.isReg())
16033 MachineFunction &MF = *MBB->getParent();
16034 MachineRegisterInfo &MRI = MF.getRegInfo();
16036 // Check whether the addend is defined by a PHI:
16037 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
16038 MachineInstr &AddendDef = *MRI.def_begin(AddendOp.getReg());
16039 if (!AddendDef.isPHI())
16042 // Look for the following pattern:
16044 // %addend = phi [%entry, 0], [%loop, %result]
16046 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
16050 // %addend = phi [%entry, 0], [%loop, %result]
16052 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
16054 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
16055 assert(AddendDef.getOperand(i).isReg());
16056 MachineOperand PHISrcOp = AddendDef.getOperand(i);
16057 MachineInstr &PHISrcInst = *MRI.def_begin(PHISrcOp.getReg());
16058 if (&PHISrcInst == MI) {
16059 // Found a matching instruction.
16060 unsigned NewFMAOpc = 0;
16061 switch (MI->getOpcode()) {
16062 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
16063 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
16064 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
16065 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
16066 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
16067 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
16068 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
16069 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
16070 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
16071 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
16072 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
16073 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
16074 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
16075 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
16076 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
16077 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
16078 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
16079 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
16080 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
16081 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
16082 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
16083 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
16084 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
16085 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
16086 default: llvm_unreachable("Unrecognized FMA variant.");
16089 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
16090 MachineInstrBuilder MIB =
16091 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
16092 .addOperand(MI->getOperand(0))
16093 .addOperand(MI->getOperand(3))
16094 .addOperand(MI->getOperand(2))
16095 .addOperand(MI->getOperand(1));
16096 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
16097 MI->eraseFromParent();
16104 MachineBasicBlock *
16105 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
16106 MachineBasicBlock *BB) const {
16107 switch (MI->getOpcode()) {
16108 default: llvm_unreachable("Unexpected instr type to insert");
16109 case X86::TAILJMPd64:
16110 case X86::TAILJMPr64:
16111 case X86::TAILJMPm64:
16112 llvm_unreachable("TAILJMP64 would not be touched here.");
16113 case X86::TCRETURNdi64:
16114 case X86::TCRETURNri64:
16115 case X86::TCRETURNmi64:
16117 case X86::WIN_ALLOCA:
16118 return EmitLoweredWinAlloca(MI, BB);
16119 case X86::SEG_ALLOCA_32:
16120 return EmitLoweredSegAlloca(MI, BB, false);
16121 case X86::SEG_ALLOCA_64:
16122 return EmitLoweredSegAlloca(MI, BB, true);
16123 case X86::TLSCall_32:
16124 case X86::TLSCall_64:
16125 return EmitLoweredTLSCall(MI, BB);
16126 case X86::CMOV_GR8:
16127 case X86::CMOV_FR32:
16128 case X86::CMOV_FR64:
16129 case X86::CMOV_V4F32:
16130 case X86::CMOV_V2F64:
16131 case X86::CMOV_V2I64:
16132 case X86::CMOV_V8F32:
16133 case X86::CMOV_V4F64:
16134 case X86::CMOV_V4I64:
16135 case X86::CMOV_V16F32:
16136 case X86::CMOV_V8F64:
16137 case X86::CMOV_V8I64:
16138 case X86::CMOV_GR16:
16139 case X86::CMOV_GR32:
16140 case X86::CMOV_RFP32:
16141 case X86::CMOV_RFP64:
16142 case X86::CMOV_RFP80:
16143 return EmitLoweredSelect(MI, BB);
16145 case X86::FP32_TO_INT16_IN_MEM:
16146 case X86::FP32_TO_INT32_IN_MEM:
16147 case X86::FP32_TO_INT64_IN_MEM:
16148 case X86::FP64_TO_INT16_IN_MEM:
16149 case X86::FP64_TO_INT32_IN_MEM:
16150 case X86::FP64_TO_INT64_IN_MEM:
16151 case X86::FP80_TO_INT16_IN_MEM:
16152 case X86::FP80_TO_INT32_IN_MEM:
16153 case X86::FP80_TO_INT64_IN_MEM: {
16154 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
16155 DebugLoc DL = MI->getDebugLoc();
16157 // Change the floating point control register to use "round towards zero"
16158 // mode when truncating to an integer value.
16159 MachineFunction *F = BB->getParent();
16160 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
16161 addFrameReference(BuildMI(*BB, MI, DL,
16162 TII->get(X86::FNSTCW16m)), CWFrameIdx);
16164 // Load the old value of the high byte of the control word...
16166 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
16167 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
16170 // Set the high part to be round to zero...
16171 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
16174 // Reload the modified control word now...
16175 addFrameReference(BuildMI(*BB, MI, DL,
16176 TII->get(X86::FLDCW16m)), CWFrameIdx);
16178 // Restore the memory image of control word to original value
16179 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
16182 // Get the X86 opcode to use.
16184 switch (MI->getOpcode()) {
16185 default: llvm_unreachable("illegal opcode!");
16186 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
16187 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
16188 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
16189 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
16190 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
16191 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
16192 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
16193 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
16194 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
16198 MachineOperand &Op = MI->getOperand(0);
16200 AM.BaseType = X86AddressMode::RegBase;
16201 AM.Base.Reg = Op.getReg();
16203 AM.BaseType = X86AddressMode::FrameIndexBase;
16204 AM.Base.FrameIndex = Op.getIndex();
16206 Op = MI->getOperand(1);
16208 AM.Scale = Op.getImm();
16209 Op = MI->getOperand(2);
16211 AM.IndexReg = Op.getImm();
16212 Op = MI->getOperand(3);
16213 if (Op.isGlobal()) {
16214 AM.GV = Op.getGlobal();
16216 AM.Disp = Op.getImm();
16218 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
16219 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
16221 // Reload the original control word now.
16222 addFrameReference(BuildMI(*BB, MI, DL,
16223 TII->get(X86::FLDCW16m)), CWFrameIdx);
16225 MI->eraseFromParent(); // The pseudo instruction is gone now.
16228 // String/text processing lowering.
16229 case X86::PCMPISTRM128REG:
16230 case X86::VPCMPISTRM128REG:
16231 case X86::PCMPISTRM128MEM:
16232 case X86::VPCMPISTRM128MEM:
16233 case X86::PCMPESTRM128REG:
16234 case X86::VPCMPESTRM128REG:
16235 case X86::PCMPESTRM128MEM:
16236 case X86::VPCMPESTRM128MEM:
16237 assert(Subtarget->hasSSE42() &&
16238 "Target must have SSE4.2 or AVX features enabled");
16239 return EmitPCMPSTRM(MI, BB, getTargetMachine().getInstrInfo());
16241 // String/text processing lowering.
16242 case X86::PCMPISTRIREG:
16243 case X86::VPCMPISTRIREG:
16244 case X86::PCMPISTRIMEM:
16245 case X86::VPCMPISTRIMEM:
16246 case X86::PCMPESTRIREG:
16247 case X86::VPCMPESTRIREG:
16248 case X86::PCMPESTRIMEM:
16249 case X86::VPCMPESTRIMEM:
16250 assert(Subtarget->hasSSE42() &&
16251 "Target must have SSE4.2 or AVX features enabled");
16252 return EmitPCMPSTRI(MI, BB, getTargetMachine().getInstrInfo());
16254 // Thread synchronization.
16256 return EmitMonitor(MI, BB, getTargetMachine().getInstrInfo(), Subtarget);
16260 return EmitXBegin(MI, BB, getTargetMachine().getInstrInfo());
16262 // Atomic Lowering.
16263 case X86::ATOMAND8:
16264 case X86::ATOMAND16:
16265 case X86::ATOMAND32:
16266 case X86::ATOMAND64:
16269 case X86::ATOMOR16:
16270 case X86::ATOMOR32:
16271 case X86::ATOMOR64:
16273 case X86::ATOMXOR16:
16274 case X86::ATOMXOR8:
16275 case X86::ATOMXOR32:
16276 case X86::ATOMXOR64:
16278 case X86::ATOMNAND8:
16279 case X86::ATOMNAND16:
16280 case X86::ATOMNAND32:
16281 case X86::ATOMNAND64:
16283 case X86::ATOMMAX8:
16284 case X86::ATOMMAX16:
16285 case X86::ATOMMAX32:
16286 case X86::ATOMMAX64:
16288 case X86::ATOMMIN8:
16289 case X86::ATOMMIN16:
16290 case X86::ATOMMIN32:
16291 case X86::ATOMMIN64:
16293 case X86::ATOMUMAX8:
16294 case X86::ATOMUMAX16:
16295 case X86::ATOMUMAX32:
16296 case X86::ATOMUMAX64:
16298 case X86::ATOMUMIN8:
16299 case X86::ATOMUMIN16:
16300 case X86::ATOMUMIN32:
16301 case X86::ATOMUMIN64:
16302 return EmitAtomicLoadArith(MI, BB);
16304 // This group does 64-bit operations on a 32-bit host.
16305 case X86::ATOMAND6432:
16306 case X86::ATOMOR6432:
16307 case X86::ATOMXOR6432:
16308 case X86::ATOMNAND6432:
16309 case X86::ATOMADD6432:
16310 case X86::ATOMSUB6432:
16311 case X86::ATOMMAX6432:
16312 case X86::ATOMMIN6432:
16313 case X86::ATOMUMAX6432:
16314 case X86::ATOMUMIN6432:
16315 case X86::ATOMSWAP6432:
16316 return EmitAtomicLoadArith6432(MI, BB);
16318 case X86::VASTART_SAVE_XMM_REGS:
16319 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
16321 case X86::VAARG_64:
16322 return EmitVAARG64WithCustomInserter(MI, BB);
16324 case X86::EH_SjLj_SetJmp32:
16325 case X86::EH_SjLj_SetJmp64:
16326 return emitEHSjLjSetJmp(MI, BB);
16328 case X86::EH_SjLj_LongJmp32:
16329 case X86::EH_SjLj_LongJmp64:
16330 return emitEHSjLjLongJmp(MI, BB);
16332 case TargetOpcode::STACKMAP:
16333 case TargetOpcode::PATCHPOINT:
16334 return emitPatchPoint(MI, BB);
16336 case X86::VFMADDPDr213r:
16337 case X86::VFMADDPSr213r:
16338 case X86::VFMADDSDr213r:
16339 case X86::VFMADDSSr213r:
16340 case X86::VFMSUBPDr213r:
16341 case X86::VFMSUBPSr213r:
16342 case X86::VFMSUBSDr213r:
16343 case X86::VFMSUBSSr213r:
16344 case X86::VFNMADDPDr213r:
16345 case X86::VFNMADDPSr213r:
16346 case X86::VFNMADDSDr213r:
16347 case X86::VFNMADDSSr213r:
16348 case X86::VFNMSUBPDr213r:
16349 case X86::VFNMSUBPSr213r:
16350 case X86::VFNMSUBSDr213r:
16351 case X86::VFNMSUBSSr213r:
16352 case X86::VFMADDPDr213rY:
16353 case X86::VFMADDPSr213rY:
16354 case X86::VFMSUBPDr213rY:
16355 case X86::VFMSUBPSr213rY:
16356 case X86::VFNMADDPDr213rY:
16357 case X86::VFNMADDPSr213rY:
16358 case X86::VFNMSUBPDr213rY:
16359 case X86::VFNMSUBPSr213rY:
16360 return emitFMA3Instr(MI, BB);
16364 //===----------------------------------------------------------------------===//
16365 // X86 Optimization Hooks
16366 //===----------------------------------------------------------------------===//
16368 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
16371 const SelectionDAG &DAG,
16372 unsigned Depth) const {
16373 unsigned BitWidth = KnownZero.getBitWidth();
16374 unsigned Opc = Op.getOpcode();
16375 assert((Opc >= ISD::BUILTIN_OP_END ||
16376 Opc == ISD::INTRINSIC_WO_CHAIN ||
16377 Opc == ISD::INTRINSIC_W_CHAIN ||
16378 Opc == ISD::INTRINSIC_VOID) &&
16379 "Should use MaskedValueIsZero if you don't know whether Op"
16380 " is a target node!");
16382 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
16396 // These nodes' second result is a boolean.
16397 if (Op.getResNo() == 0)
16400 case X86ISD::SETCC:
16401 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
16403 case ISD::INTRINSIC_WO_CHAIN: {
16404 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16405 unsigned NumLoBits = 0;
16408 case Intrinsic::x86_sse_movmsk_ps:
16409 case Intrinsic::x86_avx_movmsk_ps_256:
16410 case Intrinsic::x86_sse2_movmsk_pd:
16411 case Intrinsic::x86_avx_movmsk_pd_256:
16412 case Intrinsic::x86_mmx_pmovmskb:
16413 case Intrinsic::x86_sse2_pmovmskb_128:
16414 case Intrinsic::x86_avx2_pmovmskb: {
16415 // High bits of movmskp{s|d}, pmovmskb are known zero.
16417 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16418 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
16419 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
16420 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
16421 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
16422 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
16423 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
16424 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
16426 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
16435 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
16436 unsigned Depth) const {
16437 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
16438 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
16439 return Op.getValueType().getScalarType().getSizeInBits();
16445 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
16446 /// node is a GlobalAddress + offset.
16447 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
16448 const GlobalValue* &GA,
16449 int64_t &Offset) const {
16450 if (N->getOpcode() == X86ISD::Wrapper) {
16451 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
16452 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
16453 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
16457 return TargetLowering::isGAPlusOffset(N, GA, Offset);
16460 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
16461 /// same as extracting the high 128-bit part of 256-bit vector and then
16462 /// inserting the result into the low part of a new 256-bit vector
16463 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
16464 EVT VT = SVOp->getValueType(0);
16465 unsigned NumElems = VT.getVectorNumElements();
16467 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
16468 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
16469 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
16470 SVOp->getMaskElt(j) >= 0)
16476 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
16477 /// same as extracting the low 128-bit part of 256-bit vector and then
16478 /// inserting the result into the high part of a new 256-bit vector
16479 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
16480 EVT VT = SVOp->getValueType(0);
16481 unsigned NumElems = VT.getVectorNumElements();
16483 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
16484 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
16485 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
16486 SVOp->getMaskElt(j) >= 0)
16492 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
16493 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
16494 TargetLowering::DAGCombinerInfo &DCI,
16495 const X86Subtarget* Subtarget) {
16497 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
16498 SDValue V1 = SVOp->getOperand(0);
16499 SDValue V2 = SVOp->getOperand(1);
16500 EVT VT = SVOp->getValueType(0);
16501 unsigned NumElems = VT.getVectorNumElements();
16503 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
16504 V2.getOpcode() == ISD::CONCAT_VECTORS) {
16508 // V UNDEF BUILD_VECTOR UNDEF
16510 // CONCAT_VECTOR CONCAT_VECTOR
16513 // RESULT: V + zero extended
16515 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
16516 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
16517 V1.getOperand(1).getOpcode() != ISD::UNDEF)
16520 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
16523 // To match the shuffle mask, the first half of the mask should
16524 // be exactly the first vector, and all the rest a splat with the
16525 // first element of the second one.
16526 for (unsigned i = 0; i != NumElems/2; ++i)
16527 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
16528 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
16531 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
16532 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
16533 if (Ld->hasNUsesOfValue(1, 0)) {
16534 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
16535 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
16537 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
16538 array_lengthof(Ops),
16540 Ld->getPointerInfo(),
16541 Ld->getAlignment(),
16542 false/*isVolatile*/, true/*ReadMem*/,
16543 false/*WriteMem*/);
16545 // Make sure the newly-created LOAD is in the same position as Ld in
16546 // terms of dependency. We create a TokenFactor for Ld and ResNode,
16547 // and update uses of Ld's output chain to use the TokenFactor.
16548 if (Ld->hasAnyUseOfValue(1)) {
16549 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
16550 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
16551 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
16552 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
16553 SDValue(ResNode.getNode(), 1));
16556 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
16560 // Emit a zeroed vector and insert the desired subvector on its
16562 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
16563 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
16564 return DCI.CombineTo(N, InsV);
16567 //===--------------------------------------------------------------------===//
16568 // Combine some shuffles into subvector extracts and inserts:
16571 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
16572 if (isShuffleHigh128VectorInsertLow(SVOp)) {
16573 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
16574 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
16575 return DCI.CombineTo(N, InsV);
16578 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
16579 if (isShuffleLow128VectorInsertHigh(SVOp)) {
16580 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
16581 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
16582 return DCI.CombineTo(N, InsV);
16588 /// PerformShuffleCombine - Performs several different shuffle combines.
16589 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
16590 TargetLowering::DAGCombinerInfo &DCI,
16591 const X86Subtarget *Subtarget) {
16593 EVT VT = N->getValueType(0);
16595 // Don't create instructions with illegal types after legalize types has run.
16596 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16597 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
16600 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
16601 if (Subtarget->hasFp256() && VT.is256BitVector() &&
16602 N->getOpcode() == ISD::VECTOR_SHUFFLE)
16603 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
16605 // Only handle 128 wide vector from here on.
16606 if (!VT.is128BitVector())
16609 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
16610 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
16611 // consecutive, non-overlapping, and in the right order.
16612 SmallVector<SDValue, 16> Elts;
16613 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
16614 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
16616 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
16619 /// PerformTruncateCombine - Converts truncate operation to
16620 /// a sequence of vector shuffle operations.
16621 /// It is possible when we truncate 256-bit vector to 128-bit vector
16622 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
16623 TargetLowering::DAGCombinerInfo &DCI,
16624 const X86Subtarget *Subtarget) {
16628 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
16629 /// specific shuffle of a load can be folded into a single element load.
16630 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
16631 /// shuffles have been customed lowered so we need to handle those here.
16632 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
16633 TargetLowering::DAGCombinerInfo &DCI) {
16634 if (DCI.isBeforeLegalizeOps())
16637 SDValue InVec = N->getOperand(0);
16638 SDValue EltNo = N->getOperand(1);
16640 if (!isa<ConstantSDNode>(EltNo))
16643 EVT VT = InVec.getValueType();
16645 bool HasShuffleIntoBitcast = false;
16646 if (InVec.getOpcode() == ISD::BITCAST) {
16647 // Don't duplicate a load with other uses.
16648 if (!InVec.hasOneUse())
16650 EVT BCVT = InVec.getOperand(0).getValueType();
16651 if (BCVT.getVectorNumElements() != VT.getVectorNumElements())
16653 InVec = InVec.getOperand(0);
16654 HasShuffleIntoBitcast = true;
16657 if (!isTargetShuffle(InVec.getOpcode()))
16660 // Don't duplicate a load with other uses.
16661 if (!InVec.hasOneUse())
16664 SmallVector<int, 16> ShuffleMask;
16666 if (!getTargetShuffleMask(InVec.getNode(), VT.getSimpleVT(), ShuffleMask,
16670 // Select the input vector, guarding against out of range extract vector.
16671 unsigned NumElems = VT.getVectorNumElements();
16672 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
16673 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
16674 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
16675 : InVec.getOperand(1);
16677 // If inputs to shuffle are the same for both ops, then allow 2 uses
16678 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
16680 if (LdNode.getOpcode() == ISD::BITCAST) {
16681 // Don't duplicate a load with other uses.
16682 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
16685 AllowedUses = 1; // only allow 1 load use if we have a bitcast
16686 LdNode = LdNode.getOperand(0);
16689 if (!ISD::isNormalLoad(LdNode.getNode()))
16692 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
16694 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
16697 if (HasShuffleIntoBitcast) {
16698 // If there's a bitcast before the shuffle, check if the load type and
16699 // alignment is valid.
16700 unsigned Align = LN0->getAlignment();
16701 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16702 unsigned NewAlign = TLI.getDataLayout()->
16703 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
16705 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
16709 // All checks match so transform back to vector_shuffle so that DAG combiner
16710 // can finish the job
16713 // Create shuffle node taking into account the case that its a unary shuffle
16714 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1);
16715 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl,
16716 InVec.getOperand(0), Shuffle,
16718 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
16719 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
16723 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
16724 /// generation and convert it from being a bunch of shuffles and extracts
16725 /// to a simple store and scalar loads to extract the elements.
16726 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
16727 TargetLowering::DAGCombinerInfo &DCI) {
16728 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
16729 if (NewOp.getNode())
16732 SDValue InputVector = N->getOperand(0);
16734 // Detect whether we are trying to convert from mmx to i32 and the bitcast
16735 // from mmx to v2i32 has a single usage.
16736 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
16737 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
16738 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
16739 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
16740 N->getValueType(0),
16741 InputVector.getNode()->getOperand(0));
16743 // Only operate on vectors of 4 elements, where the alternative shuffling
16744 // gets to be more expensive.
16745 if (InputVector.getValueType() != MVT::v4i32)
16748 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
16749 // single use which is a sign-extend or zero-extend, and all elements are
16751 SmallVector<SDNode *, 4> Uses;
16752 unsigned ExtractedElements = 0;
16753 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
16754 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
16755 if (UI.getUse().getResNo() != InputVector.getResNo())
16758 SDNode *Extract = *UI;
16759 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
16762 if (Extract->getValueType(0) != MVT::i32)
16764 if (!Extract->hasOneUse())
16766 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
16767 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
16769 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
16772 // Record which element was extracted.
16773 ExtractedElements |=
16774 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
16776 Uses.push_back(Extract);
16779 // If not all the elements were used, this may not be worthwhile.
16780 if (ExtractedElements != 15)
16783 // Ok, we've now decided to do the transformation.
16784 SDLoc dl(InputVector);
16786 // Store the value to a temporary stack slot.
16787 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
16788 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
16789 MachinePointerInfo(), false, false, 0);
16791 // Replace each use (extract) with a load of the appropriate element.
16792 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
16793 UE = Uses.end(); UI != UE; ++UI) {
16794 SDNode *Extract = *UI;
16796 // cOMpute the element's address.
16797 SDValue Idx = Extract->getOperand(1);
16799 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
16800 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
16801 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16802 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
16804 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
16805 StackPtr, OffsetVal);
16807 // Load the scalar.
16808 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
16809 ScalarAddr, MachinePointerInfo(),
16810 false, false, false, 0);
16812 // Replace the exact with the load.
16813 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
16816 // The replacement was made in place; don't return anything.
16820 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
16821 static std::pair<unsigned, bool>
16822 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
16823 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
16824 if (!VT.isVector())
16825 return std::make_pair(0, false);
16827 bool NeedSplit = false;
16828 switch (VT.getSimpleVT().SimpleTy) {
16829 default: return std::make_pair(0, false);
16833 if (!Subtarget->hasAVX2())
16835 if (!Subtarget->hasAVX())
16836 return std::make_pair(0, false);
16841 if (!Subtarget->hasSSE2())
16842 return std::make_pair(0, false);
16845 // SSE2 has only a small subset of the operations.
16846 bool hasUnsigned = Subtarget->hasSSE41() ||
16847 (Subtarget->hasSSE2() && VT == MVT::v16i8);
16848 bool hasSigned = Subtarget->hasSSE41() ||
16849 (Subtarget->hasSSE2() && VT == MVT::v8i16);
16851 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
16854 // Check for x CC y ? x : y.
16855 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
16856 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
16861 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
16864 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
16867 Opc = hasSigned ? X86ISD::SMIN : 0; break;
16870 Opc = hasSigned ? X86ISD::SMAX : 0; break;
16872 // Check for x CC y ? y : x -- a min/max with reversed arms.
16873 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
16874 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
16879 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
16882 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
16885 Opc = hasSigned ? X86ISD::SMAX : 0; break;
16888 Opc = hasSigned ? X86ISD::SMIN : 0; break;
16892 return std::make_pair(Opc, NeedSplit);
16895 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
16897 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
16898 TargetLowering::DAGCombinerInfo &DCI,
16899 const X86Subtarget *Subtarget) {
16901 SDValue Cond = N->getOperand(0);
16902 // Get the LHS/RHS of the select.
16903 SDValue LHS = N->getOperand(1);
16904 SDValue RHS = N->getOperand(2);
16905 EVT VT = LHS.getValueType();
16906 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16908 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
16909 // instructions match the semantics of the common C idiom x<y?x:y but not
16910 // x<=y?x:y, because of how they handle negative zero (which can be
16911 // ignored in unsafe-math mode).
16912 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
16913 VT != MVT::f80 && TLI.isTypeLegal(VT) &&
16914 (Subtarget->hasSSE2() ||
16915 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
16916 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
16918 unsigned Opcode = 0;
16919 // Check for x CC y ? x : y.
16920 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
16921 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
16925 // Converting this to a min would handle NaNs incorrectly, and swapping
16926 // the operands would cause it to handle comparisons between positive
16927 // and negative zero incorrectly.
16928 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
16929 if (!DAG.getTarget().Options.UnsafeFPMath &&
16930 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
16932 std::swap(LHS, RHS);
16934 Opcode = X86ISD::FMIN;
16937 // Converting this to a min would handle comparisons between positive
16938 // and negative zero incorrectly.
16939 if (!DAG.getTarget().Options.UnsafeFPMath &&
16940 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
16942 Opcode = X86ISD::FMIN;
16945 // Converting this to a min would handle both negative zeros and NaNs
16946 // incorrectly, but we can swap the operands to fix both.
16947 std::swap(LHS, RHS);
16951 Opcode = X86ISD::FMIN;
16955 // Converting this to a max would handle comparisons between positive
16956 // and negative zero incorrectly.
16957 if (!DAG.getTarget().Options.UnsafeFPMath &&
16958 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
16960 Opcode = X86ISD::FMAX;
16963 // Converting this to a max would handle NaNs incorrectly, and swapping
16964 // the operands would cause it to handle comparisons between positive
16965 // and negative zero incorrectly.
16966 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
16967 if (!DAG.getTarget().Options.UnsafeFPMath &&
16968 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
16970 std::swap(LHS, RHS);
16972 Opcode = X86ISD::FMAX;
16975 // Converting this to a max would handle both negative zeros and NaNs
16976 // incorrectly, but we can swap the operands to fix both.
16977 std::swap(LHS, RHS);
16981 Opcode = X86ISD::FMAX;
16984 // Check for x CC y ? y : x -- a min/max with reversed arms.
16985 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
16986 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
16990 // Converting this to a min would handle comparisons between positive
16991 // and negative zero incorrectly, and swapping the operands would
16992 // cause it to handle NaNs incorrectly.
16993 if (!DAG.getTarget().Options.UnsafeFPMath &&
16994 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
16995 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
16997 std::swap(LHS, RHS);
16999 Opcode = X86ISD::FMIN;
17002 // Converting this to a min would handle NaNs incorrectly.
17003 if (!DAG.getTarget().Options.UnsafeFPMath &&
17004 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
17006 Opcode = X86ISD::FMIN;
17009 // Converting this to a min would handle both negative zeros and NaNs
17010 // incorrectly, but we can swap the operands to fix both.
17011 std::swap(LHS, RHS);
17015 Opcode = X86ISD::FMIN;
17019 // Converting this to a max would handle NaNs incorrectly.
17020 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
17022 Opcode = X86ISD::FMAX;
17025 // Converting this to a max would handle comparisons between positive
17026 // and negative zero incorrectly, and swapping the operands would
17027 // cause it to handle NaNs incorrectly.
17028 if (!DAG.getTarget().Options.UnsafeFPMath &&
17029 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
17030 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
17032 std::swap(LHS, RHS);
17034 Opcode = X86ISD::FMAX;
17037 // Converting this to a max would handle both negative zeros and NaNs
17038 // incorrectly, but we can swap the operands to fix both.
17039 std::swap(LHS, RHS);
17043 Opcode = X86ISD::FMAX;
17049 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
17052 EVT CondVT = Cond.getValueType();
17053 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
17054 CondVT.getVectorElementType() == MVT::i1) {
17055 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
17056 // lowering on AVX-512. In this case we convert it to
17057 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
17058 // The same situation for all 128 and 256-bit vectors of i8 and i16
17059 EVT OpVT = LHS.getValueType();
17060 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
17061 (OpVT.getVectorElementType() == MVT::i8 ||
17062 OpVT.getVectorElementType() == MVT::i16)) {
17063 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
17064 DCI.AddToWorklist(Cond.getNode());
17065 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
17068 // If this is a select between two integer constants, try to do some
17070 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
17071 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
17072 // Don't do this for crazy integer types.
17073 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
17074 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
17075 // so that TrueC (the true value) is larger than FalseC.
17076 bool NeedsCondInvert = false;
17078 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
17079 // Efficiently invertible.
17080 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
17081 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
17082 isa<ConstantSDNode>(Cond.getOperand(1))))) {
17083 NeedsCondInvert = true;
17084 std::swap(TrueC, FalseC);
17087 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
17088 if (FalseC->getAPIntValue() == 0 &&
17089 TrueC->getAPIntValue().isPowerOf2()) {
17090 if (NeedsCondInvert) // Invert the condition if needed.
17091 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
17092 DAG.getConstant(1, Cond.getValueType()));
17094 // Zero extend the condition if needed.
17095 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
17097 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
17098 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
17099 DAG.getConstant(ShAmt, MVT::i8));
17102 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
17103 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
17104 if (NeedsCondInvert) // Invert the condition if needed.
17105 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
17106 DAG.getConstant(1, Cond.getValueType()));
17108 // Zero extend the condition if needed.
17109 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
17110 FalseC->getValueType(0), Cond);
17111 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
17112 SDValue(FalseC, 0));
17115 // Optimize cases that will turn into an LEA instruction. This requires
17116 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
17117 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
17118 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
17119 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
17121 bool isFastMultiplier = false;
17123 switch ((unsigned char)Diff) {
17125 case 1: // result = add base, cond
17126 case 2: // result = lea base( , cond*2)
17127 case 3: // result = lea base(cond, cond*2)
17128 case 4: // result = lea base( , cond*4)
17129 case 5: // result = lea base(cond, cond*4)
17130 case 8: // result = lea base( , cond*8)
17131 case 9: // result = lea base(cond, cond*8)
17132 isFastMultiplier = true;
17137 if (isFastMultiplier) {
17138 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
17139 if (NeedsCondInvert) // Invert the condition if needed.
17140 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
17141 DAG.getConstant(1, Cond.getValueType()));
17143 // Zero extend the condition if needed.
17144 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
17146 // Scale the condition by the difference.
17148 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
17149 DAG.getConstant(Diff, Cond.getValueType()));
17151 // Add the base if non-zero.
17152 if (FalseC->getAPIntValue() != 0)
17153 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
17154 SDValue(FalseC, 0));
17161 // Canonicalize max and min:
17162 // (x > y) ? x : y -> (x >= y) ? x : y
17163 // (x < y) ? x : y -> (x <= y) ? x : y
17164 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
17165 // the need for an extra compare
17166 // against zero. e.g.
17167 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
17169 // testl %edi, %edi
17171 // cmovgl %edi, %eax
17175 // cmovsl %eax, %edi
17176 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
17177 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
17178 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
17179 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
17184 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
17185 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
17186 Cond.getOperand(0), Cond.getOperand(1), NewCC);
17187 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
17192 // Early exit check
17193 if (!TLI.isTypeLegal(VT))
17196 // Match VSELECTs into subs with unsigned saturation.
17197 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
17198 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
17199 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
17200 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
17201 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
17203 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
17204 // left side invert the predicate to simplify logic below.
17206 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
17208 CC = ISD::getSetCCInverse(CC, true);
17209 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
17213 if (Other.getNode() && Other->getNumOperands() == 2 &&
17214 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
17215 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
17216 SDValue CondRHS = Cond->getOperand(1);
17218 // Look for a general sub with unsigned saturation first.
17219 // x >= y ? x-y : 0 --> subus x, y
17220 // x > y ? x-y : 0 --> subus x, y
17221 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
17222 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
17223 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
17225 // If the RHS is a constant we have to reverse the const canonicalization.
17226 // x > C-1 ? x+-C : 0 --> subus x, C
17227 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
17228 isSplatVector(CondRHS.getNode()) && isSplatVector(OpRHS.getNode())) {
17229 APInt A = cast<ConstantSDNode>(OpRHS.getOperand(0))->getAPIntValue();
17230 if (CondRHS.getConstantOperandVal(0) == -A-1)
17231 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS,
17232 DAG.getConstant(-A, VT));
17235 // Another special case: If C was a sign bit, the sub has been
17236 // canonicalized into a xor.
17237 // FIXME: Would it be better to use ComputeMaskedBits to determine whether
17238 // it's safe to decanonicalize the xor?
17239 // x s< 0 ? x^C : 0 --> subus x, C
17240 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
17241 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
17242 isSplatVector(OpRHS.getNode())) {
17243 APInt A = cast<ConstantSDNode>(OpRHS.getOperand(0))->getAPIntValue();
17245 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
17250 // Try to match a min/max vector operation.
17251 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
17252 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
17253 unsigned Opc = ret.first;
17254 bool NeedSplit = ret.second;
17256 if (Opc && NeedSplit) {
17257 unsigned NumElems = VT.getVectorNumElements();
17258 // Extract the LHS vectors
17259 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
17260 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
17262 // Extract the RHS vectors
17263 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
17264 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
17266 // Create min/max for each subvector
17267 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
17268 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
17270 // Merge the result
17271 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
17273 return DAG.getNode(Opc, DL, VT, LHS, RHS);
17276 // Simplify vector selection if the selector will be produced by CMPP*/PCMP*.
17277 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
17278 // Check if SETCC has already been promoted
17279 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT &&
17280 // Check that condition value type matches vselect operand type
17283 assert(Cond.getValueType().isVector() &&
17284 "vector select expects a vector selector!");
17286 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
17287 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
17289 if (!TValIsAllOnes && !FValIsAllZeros) {
17290 // Try invert the condition if true value is not all 1s and false value
17292 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
17293 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
17295 if (TValIsAllZeros || FValIsAllOnes) {
17296 SDValue CC = Cond.getOperand(2);
17297 ISD::CondCode NewCC =
17298 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
17299 Cond.getOperand(0).getValueType().isInteger());
17300 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
17301 std::swap(LHS, RHS);
17302 TValIsAllOnes = FValIsAllOnes;
17303 FValIsAllZeros = TValIsAllZeros;
17307 if (TValIsAllOnes || FValIsAllZeros) {
17310 if (TValIsAllOnes && FValIsAllZeros)
17312 else if (TValIsAllOnes)
17313 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
17314 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
17315 else if (FValIsAllZeros)
17316 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
17317 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
17319 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
17323 // Try to fold this VSELECT into a MOVSS/MOVSD
17324 if (N->getOpcode() == ISD::VSELECT &&
17325 Cond.getOpcode() == ISD::BUILD_VECTOR && !DCI.isBeforeLegalize()) {
17326 if (VT == MVT::v4i32 || VT == MVT::v4f32 ||
17327 (Subtarget->hasSSE2() && (VT == MVT::v2i64 || VT == MVT::v2f64))) {
17328 bool CanFold = false;
17329 unsigned NumElems = Cond.getNumOperands();
17333 if (isZero(Cond.getOperand(0))) {
17336 // fold (vselect <0,-1,-1,-1>, A, B) -> (movss A, B)
17337 // fold (vselect <0,-1> -> (movsd A, B)
17338 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
17339 CanFold = isAllOnes(Cond.getOperand(i));
17340 } else if (isAllOnes(Cond.getOperand(0))) {
17344 // fold (vselect <-1,0,0,0>, A, B) -> (movss B, A)
17345 // fold (vselect <-1,0> -> (movsd B, A)
17346 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
17347 CanFold = isZero(Cond.getOperand(i));
17351 if (VT == MVT::v4i32 || VT == MVT::v4f32)
17352 return getTargetShuffleNode(X86ISD::MOVSS, DL, VT, A, B, DAG);
17353 return getTargetShuffleNode(X86ISD::MOVSD, DL, VT, A, B, DAG);
17356 if (Subtarget->hasSSE2() && (VT == MVT::v4i32 || VT == MVT::v4f32)) {
17357 // fold (v4i32: vselect <0,0,-1,-1>, A, B) ->
17358 // (v4i32 (bitcast (movsd (v2i64 (bitcast A)),
17359 // (v2i64 (bitcast B)))))
17361 // fold (v4f32: vselect <0,0,-1,-1>, A, B) ->
17362 // (v4f32 (bitcast (movsd (v2f64 (bitcast A)),
17363 // (v2f64 (bitcast B)))))
17365 // fold (v4i32: vselect <-1,-1,0,0>, A, B) ->
17366 // (v4i32 (bitcast (movsd (v2i64 (bitcast B)),
17367 // (v2i64 (bitcast A)))))
17369 // fold (v4f32: vselect <-1,-1,0,0>, A, B) ->
17370 // (v4f32 (bitcast (movsd (v2f64 (bitcast B)),
17371 // (v2f64 (bitcast A)))))
17373 CanFold = (isZero(Cond.getOperand(0)) &&
17374 isZero(Cond.getOperand(1)) &&
17375 isAllOnes(Cond.getOperand(2)) &&
17376 isAllOnes(Cond.getOperand(3)));
17378 if (!CanFold && isAllOnes(Cond.getOperand(0)) &&
17379 isAllOnes(Cond.getOperand(1)) &&
17380 isZero(Cond.getOperand(2)) &&
17381 isZero(Cond.getOperand(3))) {
17383 std::swap(LHS, RHS);
17387 EVT NVT = (VT == MVT::v4i32) ? MVT::v2i64 : MVT::v2f64;
17388 SDValue NewA = DAG.getNode(ISD::BITCAST, DL, NVT, LHS);
17389 SDValue NewB = DAG.getNode(ISD::BITCAST, DL, NVT, RHS);
17390 SDValue Select = getTargetShuffleNode(X86ISD::MOVSD, DL, NVT, NewA,
17392 return DAG.getNode(ISD::BITCAST, DL, VT, Select);
17398 // If we know that this node is legal then we know that it is going to be
17399 // matched by one of the SSE/AVX BLEND instructions. These instructions only
17400 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
17401 // to simplify previous instructions.
17402 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
17403 !DCI.isBeforeLegalize() && TLI.isOperationLegal(ISD::VSELECT, VT)) {
17404 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
17406 // Don't optimize vector selects that map to mask-registers.
17410 // Check all uses of that condition operand to check whether it will be
17411 // consumed by non-BLEND instructions, which may depend on all bits are set
17413 for (SDNode::use_iterator I = Cond->use_begin(),
17414 E = Cond->use_end(); I != E; ++I)
17415 if (I->getOpcode() != ISD::VSELECT)
17416 // TODO: Add other opcodes eventually lowered into BLEND.
17419 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
17420 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
17422 APInt KnownZero, KnownOne;
17423 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
17424 DCI.isBeforeLegalizeOps());
17425 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
17426 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
17427 DCI.CommitTargetLoweringOpt(TLO);
17433 // Check whether a boolean test is testing a boolean value generated by
17434 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
17437 // Simplify the following patterns:
17438 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
17439 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
17440 // to (Op EFLAGS Cond)
17442 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
17443 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
17444 // to (Op EFLAGS !Cond)
17446 // where Op could be BRCOND or CMOV.
17448 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
17449 // Quit if not CMP and SUB with its value result used.
17450 if (Cmp.getOpcode() != X86ISD::CMP &&
17451 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
17454 // Quit if not used as a boolean value.
17455 if (CC != X86::COND_E && CC != X86::COND_NE)
17458 // Check CMP operands. One of them should be 0 or 1 and the other should be
17459 // an SetCC or extended from it.
17460 SDValue Op1 = Cmp.getOperand(0);
17461 SDValue Op2 = Cmp.getOperand(1);
17464 const ConstantSDNode* C = 0;
17465 bool needOppositeCond = (CC == X86::COND_E);
17466 bool checkAgainstTrue = false; // Is it a comparison against 1?
17468 if ((C = dyn_cast<ConstantSDNode>(Op1)))
17470 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
17472 else // Quit if all operands are not constants.
17475 if (C->getZExtValue() == 1) {
17476 needOppositeCond = !needOppositeCond;
17477 checkAgainstTrue = true;
17478 } else if (C->getZExtValue() != 0)
17479 // Quit if the constant is neither 0 or 1.
17482 bool truncatedToBoolWithAnd = false;
17483 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
17484 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
17485 SetCC.getOpcode() == ISD::TRUNCATE ||
17486 SetCC.getOpcode() == ISD::AND) {
17487 if (SetCC.getOpcode() == ISD::AND) {
17489 ConstantSDNode *CS;
17490 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
17491 CS->getZExtValue() == 1)
17493 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
17494 CS->getZExtValue() == 1)
17498 SetCC = SetCC.getOperand(OpIdx);
17499 truncatedToBoolWithAnd = true;
17501 SetCC = SetCC.getOperand(0);
17504 switch (SetCC.getOpcode()) {
17505 case X86ISD::SETCC_CARRY:
17506 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
17507 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
17508 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
17509 // truncated to i1 using 'and'.
17510 if (checkAgainstTrue && !truncatedToBoolWithAnd)
17512 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
17513 "Invalid use of SETCC_CARRY!");
17515 case X86ISD::SETCC:
17516 // Set the condition code or opposite one if necessary.
17517 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
17518 if (needOppositeCond)
17519 CC = X86::GetOppositeBranchCondition(CC);
17520 return SetCC.getOperand(1);
17521 case X86ISD::CMOV: {
17522 // Check whether false/true value has canonical one, i.e. 0 or 1.
17523 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
17524 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
17525 // Quit if true value is not a constant.
17528 // Quit if false value is not a constant.
17530 SDValue Op = SetCC.getOperand(0);
17531 // Skip 'zext' or 'trunc' node.
17532 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
17533 Op.getOpcode() == ISD::TRUNCATE)
17534 Op = Op.getOperand(0);
17535 // A special case for rdrand/rdseed, where 0 is set if false cond is
17537 if ((Op.getOpcode() != X86ISD::RDRAND &&
17538 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
17541 // Quit if false value is not the constant 0 or 1.
17542 bool FValIsFalse = true;
17543 if (FVal && FVal->getZExtValue() != 0) {
17544 if (FVal->getZExtValue() != 1)
17546 // If FVal is 1, opposite cond is needed.
17547 needOppositeCond = !needOppositeCond;
17548 FValIsFalse = false;
17550 // Quit if TVal is not the constant opposite of FVal.
17551 if (FValIsFalse && TVal->getZExtValue() != 1)
17553 if (!FValIsFalse && TVal->getZExtValue() != 0)
17555 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
17556 if (needOppositeCond)
17557 CC = X86::GetOppositeBranchCondition(CC);
17558 return SetCC.getOperand(3);
17565 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
17566 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
17567 TargetLowering::DAGCombinerInfo &DCI,
17568 const X86Subtarget *Subtarget) {
17571 // If the flag operand isn't dead, don't touch this CMOV.
17572 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
17575 SDValue FalseOp = N->getOperand(0);
17576 SDValue TrueOp = N->getOperand(1);
17577 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
17578 SDValue Cond = N->getOperand(3);
17580 if (CC == X86::COND_E || CC == X86::COND_NE) {
17581 switch (Cond.getOpcode()) {
17585 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
17586 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
17587 return (CC == X86::COND_E) ? FalseOp : TrueOp;
17593 Flags = checkBoolTestSetCCCombine(Cond, CC);
17594 if (Flags.getNode() &&
17595 // Extra check as FCMOV only supports a subset of X86 cond.
17596 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
17597 SDValue Ops[] = { FalseOp, TrueOp,
17598 DAG.getConstant(CC, MVT::i8), Flags };
17599 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(),
17600 Ops, array_lengthof(Ops));
17603 // If this is a select between two integer constants, try to do some
17604 // optimizations. Note that the operands are ordered the opposite of SELECT
17606 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
17607 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
17608 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
17609 // larger than FalseC (the false value).
17610 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
17611 CC = X86::GetOppositeBranchCondition(CC);
17612 std::swap(TrueC, FalseC);
17613 std::swap(TrueOp, FalseOp);
17616 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
17617 // This is efficient for any integer data type (including i8/i16) and
17619 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
17620 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
17621 DAG.getConstant(CC, MVT::i8), Cond);
17623 // Zero extend the condition if needed.
17624 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
17626 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
17627 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
17628 DAG.getConstant(ShAmt, MVT::i8));
17629 if (N->getNumValues() == 2) // Dead flag value?
17630 return DCI.CombineTo(N, Cond, SDValue());
17634 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
17635 // for any integer data type, including i8/i16.
17636 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
17637 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
17638 DAG.getConstant(CC, MVT::i8), Cond);
17640 // Zero extend the condition if needed.
17641 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
17642 FalseC->getValueType(0), Cond);
17643 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
17644 SDValue(FalseC, 0));
17646 if (N->getNumValues() == 2) // Dead flag value?
17647 return DCI.CombineTo(N, Cond, SDValue());
17651 // Optimize cases that will turn into an LEA instruction. This requires
17652 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
17653 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
17654 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
17655 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
17657 bool isFastMultiplier = false;
17659 switch ((unsigned char)Diff) {
17661 case 1: // result = add base, cond
17662 case 2: // result = lea base( , cond*2)
17663 case 3: // result = lea base(cond, cond*2)
17664 case 4: // result = lea base( , cond*4)
17665 case 5: // result = lea base(cond, cond*4)
17666 case 8: // result = lea base( , cond*8)
17667 case 9: // result = lea base(cond, cond*8)
17668 isFastMultiplier = true;
17673 if (isFastMultiplier) {
17674 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
17675 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
17676 DAG.getConstant(CC, MVT::i8), Cond);
17677 // Zero extend the condition if needed.
17678 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
17680 // Scale the condition by the difference.
17682 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
17683 DAG.getConstant(Diff, Cond.getValueType()));
17685 // Add the base if non-zero.
17686 if (FalseC->getAPIntValue() != 0)
17687 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
17688 SDValue(FalseC, 0));
17689 if (N->getNumValues() == 2) // Dead flag value?
17690 return DCI.CombineTo(N, Cond, SDValue());
17697 // Handle these cases:
17698 // (select (x != c), e, c) -> select (x != c), e, x),
17699 // (select (x == c), c, e) -> select (x == c), x, e)
17700 // where the c is an integer constant, and the "select" is the combination
17701 // of CMOV and CMP.
17703 // The rationale for this change is that the conditional-move from a constant
17704 // needs two instructions, however, conditional-move from a register needs
17705 // only one instruction.
17707 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
17708 // some instruction-combining opportunities. This opt needs to be
17709 // postponed as late as possible.
17711 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
17712 // the DCI.xxxx conditions are provided to postpone the optimization as
17713 // late as possible.
17715 ConstantSDNode *CmpAgainst = 0;
17716 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
17717 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
17718 !isa<ConstantSDNode>(Cond.getOperand(0))) {
17720 if (CC == X86::COND_NE &&
17721 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
17722 CC = X86::GetOppositeBranchCondition(CC);
17723 std::swap(TrueOp, FalseOp);
17726 if (CC == X86::COND_E &&
17727 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
17728 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
17729 DAG.getConstant(CC, MVT::i8), Cond };
17730 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops,
17731 array_lengthof(Ops));
17739 /// PerformMulCombine - Optimize a single multiply with constant into two
17740 /// in order to implement it with two cheaper instructions, e.g.
17741 /// LEA + SHL, LEA + LEA.
17742 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
17743 TargetLowering::DAGCombinerInfo &DCI) {
17744 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
17747 EVT VT = N->getValueType(0);
17748 if (VT != MVT::i64)
17751 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
17754 uint64_t MulAmt = C->getZExtValue();
17755 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
17758 uint64_t MulAmt1 = 0;
17759 uint64_t MulAmt2 = 0;
17760 if ((MulAmt % 9) == 0) {
17762 MulAmt2 = MulAmt / 9;
17763 } else if ((MulAmt % 5) == 0) {
17765 MulAmt2 = MulAmt / 5;
17766 } else if ((MulAmt % 3) == 0) {
17768 MulAmt2 = MulAmt / 3;
17771 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
17774 if (isPowerOf2_64(MulAmt2) &&
17775 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
17776 // If second multiplifer is pow2, issue it first. We want the multiply by
17777 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
17779 std::swap(MulAmt1, MulAmt2);
17782 if (isPowerOf2_64(MulAmt1))
17783 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
17784 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
17786 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
17787 DAG.getConstant(MulAmt1, VT));
17789 if (isPowerOf2_64(MulAmt2))
17790 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
17791 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
17793 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
17794 DAG.getConstant(MulAmt2, VT));
17796 // Do not add new nodes to DAG combiner worklist.
17797 DCI.CombineTo(N, NewMul, false);
17802 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
17803 SDValue N0 = N->getOperand(0);
17804 SDValue N1 = N->getOperand(1);
17805 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
17806 EVT VT = N0.getValueType();
17808 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
17809 // since the result of setcc_c is all zero's or all ones.
17810 if (VT.isInteger() && !VT.isVector() &&
17811 N1C && N0.getOpcode() == ISD::AND &&
17812 N0.getOperand(1).getOpcode() == ISD::Constant) {
17813 SDValue N00 = N0.getOperand(0);
17814 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
17815 ((N00.getOpcode() == ISD::ANY_EXTEND ||
17816 N00.getOpcode() == ISD::ZERO_EXTEND) &&
17817 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
17818 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
17819 APInt ShAmt = N1C->getAPIntValue();
17820 Mask = Mask.shl(ShAmt);
17822 return DAG.getNode(ISD::AND, SDLoc(N), VT,
17823 N00, DAG.getConstant(Mask, VT));
17827 // Hardware support for vector shifts is sparse which makes us scalarize the
17828 // vector operations in many cases. Also, on sandybridge ADD is faster than
17830 // (shl V, 1) -> add V,V
17831 if (isSplatVector(N1.getNode())) {
17832 assert(N0.getValueType().isVector() && "Invalid vector shift type");
17833 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1->getOperand(0));
17834 // We shift all of the values by one. In many cases we do not have
17835 // hardware support for this operation. This is better expressed as an ADD
17837 if (N1C && (1 == N1C->getZExtValue())) {
17838 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
17845 /// \brief Returns a vector of 0s if the node in input is a vector logical
17846 /// shift by a constant amount which is known to be bigger than or equal
17847 /// to the vector element size in bits.
17848 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
17849 const X86Subtarget *Subtarget) {
17850 EVT VT = N->getValueType(0);
17852 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
17853 (!Subtarget->hasInt256() ||
17854 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
17857 SDValue Amt = N->getOperand(1);
17859 if (isSplatVector(Amt.getNode())) {
17860 SDValue SclrAmt = Amt->getOperand(0);
17861 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
17862 APInt ShiftAmt = C->getAPIntValue();
17863 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
17865 // SSE2/AVX2 logical shifts always return a vector of 0s
17866 // if the shift amount is bigger than or equal to
17867 // the element size. The constant shift amount will be
17868 // encoded as a 8-bit immediate.
17869 if (ShiftAmt.trunc(8).uge(MaxAmount))
17870 return getZeroVector(VT, Subtarget, DAG, DL);
17877 /// PerformShiftCombine - Combine shifts.
17878 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
17879 TargetLowering::DAGCombinerInfo &DCI,
17880 const X86Subtarget *Subtarget) {
17881 if (N->getOpcode() == ISD::SHL) {
17882 SDValue V = PerformSHLCombine(N, DAG);
17883 if (V.getNode()) return V;
17886 if (N->getOpcode() != ISD::SRA) {
17887 // Try to fold this logical shift into a zero vector.
17888 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
17889 if (V.getNode()) return V;
17895 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
17896 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
17897 // and friends. Likewise for OR -> CMPNEQSS.
17898 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
17899 TargetLowering::DAGCombinerInfo &DCI,
17900 const X86Subtarget *Subtarget) {
17903 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
17904 // we're requiring SSE2 for both.
17905 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
17906 SDValue N0 = N->getOperand(0);
17907 SDValue N1 = N->getOperand(1);
17908 SDValue CMP0 = N0->getOperand(1);
17909 SDValue CMP1 = N1->getOperand(1);
17912 // The SETCCs should both refer to the same CMP.
17913 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
17916 SDValue CMP00 = CMP0->getOperand(0);
17917 SDValue CMP01 = CMP0->getOperand(1);
17918 EVT VT = CMP00.getValueType();
17920 if (VT == MVT::f32 || VT == MVT::f64) {
17921 bool ExpectingFlags = false;
17922 // Check for any users that want flags:
17923 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
17924 !ExpectingFlags && UI != UE; ++UI)
17925 switch (UI->getOpcode()) {
17930 ExpectingFlags = true;
17932 case ISD::CopyToReg:
17933 case ISD::SIGN_EXTEND:
17934 case ISD::ZERO_EXTEND:
17935 case ISD::ANY_EXTEND:
17939 if (!ExpectingFlags) {
17940 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
17941 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
17943 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
17944 X86::CondCode tmp = cc0;
17949 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
17950 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
17951 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
17952 // FIXME: need symbolic constants for these magic numbers.
17953 // See X86ATTInstPrinter.cpp:printSSECC().
17954 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
17955 if (Subtarget->hasAVX512()) {
17956 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
17957 CMP01, DAG.getConstant(x86cc, MVT::i8));
17958 if (N->getValueType(0) != MVT::i1)
17959 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
17963 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
17964 CMP00.getValueType(), CMP00, CMP01,
17965 DAG.getConstant(x86cc, MVT::i8));
17966 MVT IntVT = (is64BitFP ? MVT::i64 : MVT::i32);
17967 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT,
17969 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
17970 DAG.getConstant(1, IntVT));
17971 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
17972 return OneBitOfTruth;
17980 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
17981 /// so it can be folded inside ANDNP.
17982 static bool CanFoldXORWithAllOnes(const SDNode *N) {
17983 EVT VT = N->getValueType(0);
17985 // Match direct AllOnes for 128 and 256-bit vectors
17986 if (ISD::isBuildVectorAllOnes(N))
17989 // Look through a bit convert.
17990 if (N->getOpcode() == ISD::BITCAST)
17991 N = N->getOperand(0).getNode();
17993 // Sometimes the operand may come from a insert_subvector building a 256-bit
17995 if (VT.is256BitVector() &&
17996 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
17997 SDValue V1 = N->getOperand(0);
17998 SDValue V2 = N->getOperand(1);
18000 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
18001 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
18002 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
18003 ISD::isBuildVectorAllOnes(V2.getNode()))
18010 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
18011 // register. In most cases we actually compare or select YMM-sized registers
18012 // and mixing the two types creates horrible code. This method optimizes
18013 // some of the transition sequences.
18014 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
18015 TargetLowering::DAGCombinerInfo &DCI,
18016 const X86Subtarget *Subtarget) {
18017 EVT VT = N->getValueType(0);
18018 if (!VT.is256BitVector())
18021 assert((N->getOpcode() == ISD::ANY_EXTEND ||
18022 N->getOpcode() == ISD::ZERO_EXTEND ||
18023 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
18025 SDValue Narrow = N->getOperand(0);
18026 EVT NarrowVT = Narrow->getValueType(0);
18027 if (!NarrowVT.is128BitVector())
18030 if (Narrow->getOpcode() != ISD::XOR &&
18031 Narrow->getOpcode() != ISD::AND &&
18032 Narrow->getOpcode() != ISD::OR)
18035 SDValue N0 = Narrow->getOperand(0);
18036 SDValue N1 = Narrow->getOperand(1);
18039 // The Left side has to be a trunc.
18040 if (N0.getOpcode() != ISD::TRUNCATE)
18043 // The type of the truncated inputs.
18044 EVT WideVT = N0->getOperand(0)->getValueType(0);
18048 // The right side has to be a 'trunc' or a constant vector.
18049 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
18050 bool RHSConst = (isSplatVector(N1.getNode()) &&
18051 isa<ConstantSDNode>(N1->getOperand(0)));
18052 if (!RHSTrunc && !RHSConst)
18055 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18057 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
18060 // Set N0 and N1 to hold the inputs to the new wide operation.
18061 N0 = N0->getOperand(0);
18063 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
18064 N1->getOperand(0));
18065 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
18066 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, &C[0], C.size());
18067 } else if (RHSTrunc) {
18068 N1 = N1->getOperand(0);
18071 // Generate the wide operation.
18072 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
18073 unsigned Opcode = N->getOpcode();
18075 case ISD::ANY_EXTEND:
18077 case ISD::ZERO_EXTEND: {
18078 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
18079 APInt Mask = APInt::getAllOnesValue(InBits);
18080 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
18081 return DAG.getNode(ISD::AND, DL, VT,
18082 Op, DAG.getConstant(Mask, VT));
18084 case ISD::SIGN_EXTEND:
18085 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
18086 Op, DAG.getValueType(NarrowVT));
18088 llvm_unreachable("Unexpected opcode");
18092 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
18093 TargetLowering::DAGCombinerInfo &DCI,
18094 const X86Subtarget *Subtarget) {
18095 EVT VT = N->getValueType(0);
18096 if (DCI.isBeforeLegalizeOps())
18099 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
18103 // Create BEXTR and BZHI instructions
18104 // BZHI is X & ((1 << Y) - 1)
18105 // BEXTR is ((X >> imm) & (2**size-1))
18106 if (VT == MVT::i32 || VT == MVT::i64) {
18107 SDValue N0 = N->getOperand(0);
18108 SDValue N1 = N->getOperand(1);
18111 if (Subtarget->hasBMI2()) {
18112 // Check for (and (add (shl 1, Y), -1), X)
18113 if (N0.getOpcode() == ISD::ADD && isAllOnes(N0.getOperand(1))) {
18114 SDValue N00 = N0.getOperand(0);
18115 if (N00.getOpcode() == ISD::SHL) {
18116 SDValue N001 = N00.getOperand(1);
18117 assert(N001.getValueType() == MVT::i8 && "unexpected type");
18118 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N00.getOperand(0));
18119 if (C && C->getZExtValue() == 1)
18120 return DAG.getNode(X86ISD::BZHI, DL, VT, N1, N001);
18124 // Check for (and X, (add (shl 1, Y), -1))
18125 if (N1.getOpcode() == ISD::ADD && isAllOnes(N1.getOperand(1))) {
18126 SDValue N10 = N1.getOperand(0);
18127 if (N10.getOpcode() == ISD::SHL) {
18128 SDValue N101 = N10.getOperand(1);
18129 assert(N101.getValueType() == MVT::i8 && "unexpected type");
18130 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N10.getOperand(0));
18131 if (C && C->getZExtValue() == 1)
18132 return DAG.getNode(X86ISD::BZHI, DL, VT, N0, N101);
18137 // Check for BEXTR.
18138 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
18139 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
18140 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
18141 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
18142 if (MaskNode && ShiftNode) {
18143 uint64_t Mask = MaskNode->getZExtValue();
18144 uint64_t Shift = ShiftNode->getZExtValue();
18145 if (isMask_64(Mask)) {
18146 uint64_t MaskSize = CountPopulation_64(Mask);
18147 if (Shift + MaskSize <= VT.getSizeInBits())
18148 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
18149 DAG.getConstant(Shift | (MaskSize << 8), VT));
18157 // Want to form ANDNP nodes:
18158 // 1) In the hopes of then easily combining them with OR and AND nodes
18159 // to form PBLEND/PSIGN.
18160 // 2) To match ANDN packed intrinsics
18161 if (VT != MVT::v2i64 && VT != MVT::v4i64)
18164 SDValue N0 = N->getOperand(0);
18165 SDValue N1 = N->getOperand(1);
18168 // Check LHS for vnot
18169 if (N0.getOpcode() == ISD::XOR &&
18170 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
18171 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
18172 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
18174 // Check RHS for vnot
18175 if (N1.getOpcode() == ISD::XOR &&
18176 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
18177 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
18178 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
18183 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
18184 TargetLowering::DAGCombinerInfo &DCI,
18185 const X86Subtarget *Subtarget) {
18186 if (DCI.isBeforeLegalizeOps())
18189 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
18193 SDValue N0 = N->getOperand(0);
18194 SDValue N1 = N->getOperand(1);
18195 EVT VT = N->getValueType(0);
18197 // look for psign/blend
18198 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
18199 if (!Subtarget->hasSSSE3() ||
18200 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
18203 // Canonicalize pandn to RHS
18204 if (N0.getOpcode() == X86ISD::ANDNP)
18206 // or (and (m, y), (pandn m, x))
18207 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
18208 SDValue Mask = N1.getOperand(0);
18209 SDValue X = N1.getOperand(1);
18211 if (N0.getOperand(0) == Mask)
18212 Y = N0.getOperand(1);
18213 if (N0.getOperand(1) == Mask)
18214 Y = N0.getOperand(0);
18216 // Check to see if the mask appeared in both the AND and ANDNP and
18220 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
18221 // Look through mask bitcast.
18222 if (Mask.getOpcode() == ISD::BITCAST)
18223 Mask = Mask.getOperand(0);
18224 if (X.getOpcode() == ISD::BITCAST)
18225 X = X.getOperand(0);
18226 if (Y.getOpcode() == ISD::BITCAST)
18227 Y = Y.getOperand(0);
18229 EVT MaskVT = Mask.getValueType();
18231 // Validate that the Mask operand is a vector sra node.
18232 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
18233 // there is no psrai.b
18234 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
18235 unsigned SraAmt = ~0;
18236 if (Mask.getOpcode() == ISD::SRA) {
18237 SDValue Amt = Mask.getOperand(1);
18238 if (isSplatVector(Amt.getNode())) {
18239 SDValue SclrAmt = Amt->getOperand(0);
18240 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt))
18241 SraAmt = C->getZExtValue();
18243 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
18244 SDValue SraC = Mask.getOperand(1);
18245 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
18247 if ((SraAmt + 1) != EltBits)
18252 // Now we know we at least have a plendvb with the mask val. See if
18253 // we can form a psignb/w/d.
18254 // psign = x.type == y.type == mask.type && y = sub(0, x);
18255 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
18256 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
18257 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
18258 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
18259 "Unsupported VT for PSIGN");
18260 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
18261 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
18263 // PBLENDVB only available on SSE 4.1
18264 if (!Subtarget->hasSSE41())
18267 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
18269 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
18270 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
18271 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
18272 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
18273 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
18277 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
18280 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
18281 MachineFunction &MF = DAG.getMachineFunction();
18282 bool OptForSize = MF.getFunction()->getAttributes().
18283 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
18285 // SHLD/SHRD instructions have lower register pressure, but on some
18286 // platforms they have higher latency than the equivalent
18287 // series of shifts/or that would otherwise be generated.
18288 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
18289 // have higher latencies and we are not optimizing for size.
18290 if (!OptForSize && Subtarget->isSHLDSlow())
18293 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
18295 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
18297 if (!N0.hasOneUse() || !N1.hasOneUse())
18300 SDValue ShAmt0 = N0.getOperand(1);
18301 if (ShAmt0.getValueType() != MVT::i8)
18303 SDValue ShAmt1 = N1.getOperand(1);
18304 if (ShAmt1.getValueType() != MVT::i8)
18306 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
18307 ShAmt0 = ShAmt0.getOperand(0);
18308 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
18309 ShAmt1 = ShAmt1.getOperand(0);
18312 unsigned Opc = X86ISD::SHLD;
18313 SDValue Op0 = N0.getOperand(0);
18314 SDValue Op1 = N1.getOperand(0);
18315 if (ShAmt0.getOpcode() == ISD::SUB) {
18316 Opc = X86ISD::SHRD;
18317 std::swap(Op0, Op1);
18318 std::swap(ShAmt0, ShAmt1);
18321 unsigned Bits = VT.getSizeInBits();
18322 if (ShAmt1.getOpcode() == ISD::SUB) {
18323 SDValue Sum = ShAmt1.getOperand(0);
18324 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
18325 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
18326 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
18327 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
18328 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
18329 return DAG.getNode(Opc, DL, VT,
18331 DAG.getNode(ISD::TRUNCATE, DL,
18334 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
18335 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
18337 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
18338 return DAG.getNode(Opc, DL, VT,
18339 N0.getOperand(0), N1.getOperand(0),
18340 DAG.getNode(ISD::TRUNCATE, DL,
18347 // Generate NEG and CMOV for integer abs.
18348 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
18349 EVT VT = N->getValueType(0);
18351 // Since X86 does not have CMOV for 8-bit integer, we don't convert
18352 // 8-bit integer abs to NEG and CMOV.
18353 if (VT.isInteger() && VT.getSizeInBits() == 8)
18356 SDValue N0 = N->getOperand(0);
18357 SDValue N1 = N->getOperand(1);
18360 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
18361 // and change it to SUB and CMOV.
18362 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
18363 N0.getOpcode() == ISD::ADD &&
18364 N0.getOperand(1) == N1 &&
18365 N1.getOpcode() == ISD::SRA &&
18366 N1.getOperand(0) == N0.getOperand(0))
18367 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
18368 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
18369 // Generate SUB & CMOV.
18370 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
18371 DAG.getConstant(0, VT), N0.getOperand(0));
18373 SDValue Ops[] = { N0.getOperand(0), Neg,
18374 DAG.getConstant(X86::COND_GE, MVT::i8),
18375 SDValue(Neg.getNode(), 1) };
18376 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue),
18377 Ops, array_lengthof(Ops));
18382 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
18383 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
18384 TargetLowering::DAGCombinerInfo &DCI,
18385 const X86Subtarget *Subtarget) {
18386 if (DCI.isBeforeLegalizeOps())
18389 if (Subtarget->hasCMov()) {
18390 SDValue RV = performIntegerAbsCombine(N, DAG);
18398 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
18399 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
18400 TargetLowering::DAGCombinerInfo &DCI,
18401 const X86Subtarget *Subtarget) {
18402 LoadSDNode *Ld = cast<LoadSDNode>(N);
18403 EVT RegVT = Ld->getValueType(0);
18404 EVT MemVT = Ld->getMemoryVT();
18406 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18407 unsigned RegSz = RegVT.getSizeInBits();
18409 // On Sandybridge unaligned 256bit loads are inefficient.
18410 ISD::LoadExtType Ext = Ld->getExtensionType();
18411 unsigned Alignment = Ld->getAlignment();
18412 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
18413 if (RegVT.is256BitVector() && !Subtarget->hasInt256() &&
18414 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
18415 unsigned NumElems = RegVT.getVectorNumElements();
18419 SDValue Ptr = Ld->getBasePtr();
18420 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
18422 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
18424 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
18425 Ld->getPointerInfo(), Ld->isVolatile(),
18426 Ld->isNonTemporal(), Ld->isInvariant(),
18428 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
18429 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
18430 Ld->getPointerInfo(), Ld->isVolatile(),
18431 Ld->isNonTemporal(), Ld->isInvariant(),
18432 std::min(16U, Alignment));
18433 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
18435 Load2.getValue(1));
18437 SDValue NewVec = DAG.getUNDEF(RegVT);
18438 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
18439 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
18440 return DCI.CombineTo(N, NewVec, TF, true);
18443 // If this is a vector EXT Load then attempt to optimize it using a
18444 // shuffle. If SSSE3 is not available we may emit an illegal shuffle but the
18445 // expansion is still better than scalar code.
18446 // We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise we'll
18447 // emit a shuffle and a arithmetic shift.
18448 // TODO: It is possible to support ZExt by zeroing the undef values
18449 // during the shuffle phase or after the shuffle.
18450 if (RegVT.isVector() && RegVT.isInteger() && Subtarget->hasSSE2() &&
18451 (Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)) {
18452 assert(MemVT != RegVT && "Cannot extend to the same type");
18453 assert(MemVT.isVector() && "Must load a vector from memory");
18455 unsigned NumElems = RegVT.getVectorNumElements();
18456 unsigned MemSz = MemVT.getSizeInBits();
18457 assert(RegSz > MemSz && "Register size must be greater than the mem size");
18459 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256())
18462 // All sizes must be a power of two.
18463 if (!isPowerOf2_32(RegSz * MemSz * NumElems))
18466 // Attempt to load the original value using scalar loads.
18467 // Find the largest scalar type that divides the total loaded size.
18468 MVT SclrLoadTy = MVT::i8;
18469 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
18470 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
18471 MVT Tp = (MVT::SimpleValueType)tp;
18472 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
18477 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
18478 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
18480 SclrLoadTy = MVT::f64;
18482 // Calculate the number of scalar loads that we need to perform
18483 // in order to load our vector from memory.
18484 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
18485 if (Ext == ISD::SEXTLOAD && NumLoads > 1)
18488 unsigned loadRegZize = RegSz;
18489 if (Ext == ISD::SEXTLOAD && RegSz == 256)
18492 // Represent our vector as a sequence of elements which are the
18493 // largest scalar that we can load.
18494 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy,
18495 loadRegZize/SclrLoadTy.getSizeInBits());
18497 // Represent the data using the same element type that is stored in
18498 // memory. In practice, we ''widen'' MemVT.
18500 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
18501 loadRegZize/MemVT.getScalarType().getSizeInBits());
18503 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
18504 "Invalid vector type");
18506 // We can't shuffle using an illegal type.
18507 if (!TLI.isTypeLegal(WideVecVT))
18510 SmallVector<SDValue, 8> Chains;
18511 SDValue Ptr = Ld->getBasePtr();
18512 SDValue Increment = DAG.getConstant(SclrLoadTy.getSizeInBits()/8,
18513 TLI.getPointerTy());
18514 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
18516 for (unsigned i = 0; i < NumLoads; ++i) {
18517 // Perform a single load.
18518 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(),
18519 Ptr, Ld->getPointerInfo(),
18520 Ld->isVolatile(), Ld->isNonTemporal(),
18521 Ld->isInvariant(), Ld->getAlignment());
18522 Chains.push_back(ScalarLoad.getValue(1));
18523 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
18524 // another round of DAGCombining.
18526 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
18528 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
18529 ScalarLoad, DAG.getIntPtrConstant(i));
18531 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
18534 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
18537 // Bitcast the loaded value to a vector of the original element type, in
18538 // the size of the target vector type.
18539 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
18540 unsigned SizeRatio = RegSz/MemSz;
18542 if (Ext == ISD::SEXTLOAD) {
18543 // If we have SSE4.1 we can directly emit a VSEXT node.
18544 if (Subtarget->hasSSE41()) {
18545 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
18546 return DCI.CombineTo(N, Sext, TF, true);
18549 // Otherwise we'll shuffle the small elements in the high bits of the
18550 // larger type and perform an arithmetic shift. If the shift is not legal
18551 // it's better to scalarize.
18552 if (!TLI.isOperationLegalOrCustom(ISD::SRA, RegVT))
18555 // Redistribute the loaded elements into the different locations.
18556 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
18557 for (unsigned i = 0; i != NumElems; ++i)
18558 ShuffleVec[i*SizeRatio + SizeRatio-1] = i;
18560 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
18561 DAG.getUNDEF(WideVecVT),
18564 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
18566 // Build the arithmetic shift.
18567 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
18568 MemVT.getVectorElementType().getSizeInBits();
18569 Shuff = DAG.getNode(ISD::SRA, dl, RegVT, Shuff,
18570 DAG.getConstant(Amt, RegVT));
18572 return DCI.CombineTo(N, Shuff, TF, true);
18575 // Redistribute the loaded elements into the different locations.
18576 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
18577 for (unsigned i = 0; i != NumElems; ++i)
18578 ShuffleVec[i*SizeRatio] = i;
18580 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
18581 DAG.getUNDEF(WideVecVT),
18584 // Bitcast to the requested type.
18585 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
18586 // Replace the original load with the new sequence
18587 // and return the new chain.
18588 return DCI.CombineTo(N, Shuff, TF, true);
18594 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
18595 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
18596 const X86Subtarget *Subtarget) {
18597 StoreSDNode *St = cast<StoreSDNode>(N);
18598 EVT VT = St->getValue().getValueType();
18599 EVT StVT = St->getMemoryVT();
18601 SDValue StoredVal = St->getOperand(1);
18602 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18604 // If we are saving a concatenation of two XMM registers, perform two stores.
18605 // On Sandy Bridge, 256-bit memory operations are executed by two
18606 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit
18607 // memory operation.
18608 unsigned Alignment = St->getAlignment();
18609 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
18610 if (VT.is256BitVector() && !Subtarget->hasInt256() &&
18611 StVT == VT && !IsAligned) {
18612 unsigned NumElems = VT.getVectorNumElements();
18616 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
18617 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
18619 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
18620 SDValue Ptr0 = St->getBasePtr();
18621 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
18623 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
18624 St->getPointerInfo(), St->isVolatile(),
18625 St->isNonTemporal(), Alignment);
18626 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
18627 St->getPointerInfo(), St->isVolatile(),
18628 St->isNonTemporal(),
18629 std::min(16U, Alignment));
18630 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
18633 // Optimize trunc store (of multiple scalars) to shuffle and store.
18634 // First, pack all of the elements in one place. Next, store to memory
18635 // in fewer chunks.
18636 if (St->isTruncatingStore() && VT.isVector()) {
18637 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18638 unsigned NumElems = VT.getVectorNumElements();
18639 assert(StVT != VT && "Cannot truncate to the same type");
18640 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
18641 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
18643 // From, To sizes and ElemCount must be pow of two
18644 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
18645 // We are going to use the original vector elt for storing.
18646 // Accumulated smaller vector elements must be a multiple of the store size.
18647 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
18649 unsigned SizeRatio = FromSz / ToSz;
18651 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
18653 // Create a type on which we perform the shuffle
18654 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
18655 StVT.getScalarType(), NumElems*SizeRatio);
18657 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
18659 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
18660 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
18661 for (unsigned i = 0; i != NumElems; ++i)
18662 ShuffleVec[i] = i * SizeRatio;
18664 // Can't shuffle using an illegal type.
18665 if (!TLI.isTypeLegal(WideVecVT))
18668 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
18669 DAG.getUNDEF(WideVecVT),
18671 // At this point all of the data is stored at the bottom of the
18672 // register. We now need to save it to mem.
18674 // Find the largest store unit
18675 MVT StoreType = MVT::i8;
18676 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
18677 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
18678 MVT Tp = (MVT::SimpleValueType)tp;
18679 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
18683 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
18684 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
18685 (64 <= NumElems * ToSz))
18686 StoreType = MVT::f64;
18688 // Bitcast the original vector into a vector of store-size units
18689 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
18690 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
18691 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
18692 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
18693 SmallVector<SDValue, 8> Chains;
18694 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
18695 TLI.getPointerTy());
18696 SDValue Ptr = St->getBasePtr();
18698 // Perform one or more big stores into memory.
18699 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
18700 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
18701 StoreType, ShuffWide,
18702 DAG.getIntPtrConstant(i));
18703 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
18704 St->getPointerInfo(), St->isVolatile(),
18705 St->isNonTemporal(), St->getAlignment());
18706 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
18707 Chains.push_back(Ch);
18710 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
18714 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
18715 // the FP state in cases where an emms may be missing.
18716 // A preferable solution to the general problem is to figure out the right
18717 // places to insert EMMS. This qualifies as a quick hack.
18719 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
18720 if (VT.getSizeInBits() != 64)
18723 const Function *F = DAG.getMachineFunction().getFunction();
18724 bool NoImplicitFloatOps = F->getAttributes().
18725 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
18726 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
18727 && Subtarget->hasSSE2();
18728 if ((VT.isVector() ||
18729 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
18730 isa<LoadSDNode>(St->getValue()) &&
18731 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
18732 St->getChain().hasOneUse() && !St->isVolatile()) {
18733 SDNode* LdVal = St->getValue().getNode();
18734 LoadSDNode *Ld = 0;
18735 int TokenFactorIndex = -1;
18736 SmallVector<SDValue, 8> Ops;
18737 SDNode* ChainVal = St->getChain().getNode();
18738 // Must be a store of a load. We currently handle two cases: the load
18739 // is a direct child, and it's under an intervening TokenFactor. It is
18740 // possible to dig deeper under nested TokenFactors.
18741 if (ChainVal == LdVal)
18742 Ld = cast<LoadSDNode>(St->getChain());
18743 else if (St->getValue().hasOneUse() &&
18744 ChainVal->getOpcode() == ISD::TokenFactor) {
18745 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
18746 if (ChainVal->getOperand(i).getNode() == LdVal) {
18747 TokenFactorIndex = i;
18748 Ld = cast<LoadSDNode>(St->getValue());
18750 Ops.push_back(ChainVal->getOperand(i));
18754 if (!Ld || !ISD::isNormalLoad(Ld))
18757 // If this is not the MMX case, i.e. we are just turning i64 load/store
18758 // into f64 load/store, avoid the transformation if there are multiple
18759 // uses of the loaded value.
18760 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
18765 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
18766 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
18768 if (Subtarget->is64Bit() || F64IsLegal) {
18769 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
18770 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
18771 Ld->getPointerInfo(), Ld->isVolatile(),
18772 Ld->isNonTemporal(), Ld->isInvariant(),
18773 Ld->getAlignment());
18774 SDValue NewChain = NewLd.getValue(1);
18775 if (TokenFactorIndex != -1) {
18776 Ops.push_back(NewChain);
18777 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
18780 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
18781 St->getPointerInfo(),
18782 St->isVolatile(), St->isNonTemporal(),
18783 St->getAlignment());
18786 // Otherwise, lower to two pairs of 32-bit loads / stores.
18787 SDValue LoAddr = Ld->getBasePtr();
18788 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
18789 DAG.getConstant(4, MVT::i32));
18791 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
18792 Ld->getPointerInfo(),
18793 Ld->isVolatile(), Ld->isNonTemporal(),
18794 Ld->isInvariant(), Ld->getAlignment());
18795 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
18796 Ld->getPointerInfo().getWithOffset(4),
18797 Ld->isVolatile(), Ld->isNonTemporal(),
18799 MinAlign(Ld->getAlignment(), 4));
18801 SDValue NewChain = LoLd.getValue(1);
18802 if (TokenFactorIndex != -1) {
18803 Ops.push_back(LoLd);
18804 Ops.push_back(HiLd);
18805 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
18809 LoAddr = St->getBasePtr();
18810 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
18811 DAG.getConstant(4, MVT::i32));
18813 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
18814 St->getPointerInfo(),
18815 St->isVolatile(), St->isNonTemporal(),
18816 St->getAlignment());
18817 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
18818 St->getPointerInfo().getWithOffset(4),
18820 St->isNonTemporal(),
18821 MinAlign(St->getAlignment(), 4));
18822 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
18827 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
18828 /// and return the operands for the horizontal operation in LHS and RHS. A
18829 /// horizontal operation performs the binary operation on successive elements
18830 /// of its first operand, then on successive elements of its second operand,
18831 /// returning the resulting values in a vector. For example, if
18832 /// A = < float a0, float a1, float a2, float a3 >
18834 /// B = < float b0, float b1, float b2, float b3 >
18835 /// then the result of doing a horizontal operation on A and B is
18836 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
18837 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
18838 /// A horizontal-op B, for some already available A and B, and if so then LHS is
18839 /// set to A, RHS to B, and the routine returns 'true'.
18840 /// Note that the binary operation should have the property that if one of the
18841 /// operands is UNDEF then the result is UNDEF.
18842 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
18843 // Look for the following pattern: if
18844 // A = < float a0, float a1, float a2, float a3 >
18845 // B = < float b0, float b1, float b2, float b3 >
18847 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
18848 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
18849 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
18850 // which is A horizontal-op B.
18852 // At least one of the operands should be a vector shuffle.
18853 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
18854 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
18857 MVT VT = LHS.getSimpleValueType();
18859 assert((VT.is128BitVector() || VT.is256BitVector()) &&
18860 "Unsupported vector type for horizontal add/sub");
18862 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
18863 // operate independently on 128-bit lanes.
18864 unsigned NumElts = VT.getVectorNumElements();
18865 unsigned NumLanes = VT.getSizeInBits()/128;
18866 unsigned NumLaneElts = NumElts / NumLanes;
18867 assert((NumLaneElts % 2 == 0) &&
18868 "Vector type should have an even number of elements in each lane");
18869 unsigned HalfLaneElts = NumLaneElts/2;
18871 // View LHS in the form
18872 // LHS = VECTOR_SHUFFLE A, B, LMask
18873 // If LHS is not a shuffle then pretend it is the shuffle
18874 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
18875 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
18878 SmallVector<int, 16> LMask(NumElts);
18879 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
18880 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
18881 A = LHS.getOperand(0);
18882 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
18883 B = LHS.getOperand(1);
18884 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
18885 std::copy(Mask.begin(), Mask.end(), LMask.begin());
18887 if (LHS.getOpcode() != ISD::UNDEF)
18889 for (unsigned i = 0; i != NumElts; ++i)
18893 // Likewise, view RHS in the form
18894 // RHS = VECTOR_SHUFFLE C, D, RMask
18896 SmallVector<int, 16> RMask(NumElts);
18897 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
18898 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
18899 C = RHS.getOperand(0);
18900 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
18901 D = RHS.getOperand(1);
18902 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
18903 std::copy(Mask.begin(), Mask.end(), RMask.begin());
18905 if (RHS.getOpcode() != ISD::UNDEF)
18907 for (unsigned i = 0; i != NumElts; ++i)
18911 // Check that the shuffles are both shuffling the same vectors.
18912 if (!(A == C && B == D) && !(A == D && B == C))
18915 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
18916 if (!A.getNode() && !B.getNode())
18919 // If A and B occur in reverse order in RHS, then "swap" them (which means
18920 // rewriting the mask).
18922 CommuteVectorShuffleMask(RMask, NumElts);
18924 // At this point LHS and RHS are equivalent to
18925 // LHS = VECTOR_SHUFFLE A, B, LMask
18926 // RHS = VECTOR_SHUFFLE A, B, RMask
18927 // Check that the masks correspond to performing a horizontal operation.
18928 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
18929 for (unsigned i = 0; i != NumLaneElts; ++i) {
18930 int LIdx = LMask[i+l], RIdx = RMask[i+l];
18932 // Ignore any UNDEF components.
18933 if (LIdx < 0 || RIdx < 0 ||
18934 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
18935 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
18938 // Check that successive elements are being operated on. If not, this is
18939 // not a horizontal operation.
18940 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
18941 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
18942 if (!(LIdx == Index && RIdx == Index + 1) &&
18943 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
18948 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
18949 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
18953 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
18954 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
18955 const X86Subtarget *Subtarget) {
18956 EVT VT = N->getValueType(0);
18957 SDValue LHS = N->getOperand(0);
18958 SDValue RHS = N->getOperand(1);
18960 // Try to synthesize horizontal adds from adds of shuffles.
18961 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
18962 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
18963 isHorizontalBinOp(LHS, RHS, true))
18964 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
18968 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
18969 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
18970 const X86Subtarget *Subtarget) {
18971 EVT VT = N->getValueType(0);
18972 SDValue LHS = N->getOperand(0);
18973 SDValue RHS = N->getOperand(1);
18975 // Try to synthesize horizontal subs from subs of shuffles.
18976 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
18977 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
18978 isHorizontalBinOp(LHS, RHS, false))
18979 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
18983 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
18984 /// X86ISD::FXOR nodes.
18985 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
18986 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
18987 // F[X]OR(0.0, x) -> x
18988 // F[X]OR(x, 0.0) -> x
18989 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
18990 if (C->getValueAPF().isPosZero())
18991 return N->getOperand(1);
18992 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
18993 if (C->getValueAPF().isPosZero())
18994 return N->getOperand(0);
18998 /// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and
18999 /// X86ISD::FMAX nodes.
19000 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
19001 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
19003 // Only perform optimizations if UnsafeMath is used.
19004 if (!DAG.getTarget().Options.UnsafeFPMath)
19007 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
19008 // into FMINC and FMAXC, which are Commutative operations.
19009 unsigned NewOp = 0;
19010 switch (N->getOpcode()) {
19011 default: llvm_unreachable("unknown opcode");
19012 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
19013 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
19016 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
19017 N->getOperand(0), N->getOperand(1));
19020 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
19021 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
19022 // FAND(0.0, x) -> 0.0
19023 // FAND(x, 0.0) -> 0.0
19024 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
19025 if (C->getValueAPF().isPosZero())
19026 return N->getOperand(0);
19027 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
19028 if (C->getValueAPF().isPosZero())
19029 return N->getOperand(1);
19033 /// PerformFANDNCombine - Do target-specific dag combines on X86ISD::FANDN nodes
19034 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
19035 // FANDN(x, 0.0) -> 0.0
19036 // FANDN(0.0, x) -> x
19037 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
19038 if (C->getValueAPF().isPosZero())
19039 return N->getOperand(1);
19040 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
19041 if (C->getValueAPF().isPosZero())
19042 return N->getOperand(1);
19046 static SDValue PerformBTCombine(SDNode *N,
19048 TargetLowering::DAGCombinerInfo &DCI) {
19049 // BT ignores high bits in the bit index operand.
19050 SDValue Op1 = N->getOperand(1);
19051 if (Op1.hasOneUse()) {
19052 unsigned BitWidth = Op1.getValueSizeInBits();
19053 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
19054 APInt KnownZero, KnownOne;
19055 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
19056 !DCI.isBeforeLegalizeOps());
19057 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19058 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
19059 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
19060 DCI.CommitTargetLoweringOpt(TLO);
19065 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
19066 SDValue Op = N->getOperand(0);
19067 if (Op.getOpcode() == ISD::BITCAST)
19068 Op = Op.getOperand(0);
19069 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
19070 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
19071 VT.getVectorElementType().getSizeInBits() ==
19072 OpVT.getVectorElementType().getSizeInBits()) {
19073 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
19078 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
19079 const X86Subtarget *Subtarget) {
19080 EVT VT = N->getValueType(0);
19081 if (!VT.isVector())
19084 SDValue N0 = N->getOperand(0);
19085 SDValue N1 = N->getOperand(1);
19086 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
19089 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
19090 // both SSE and AVX2 since there is no sign-extended shift right
19091 // operation on a vector with 64-bit elements.
19092 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
19093 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
19094 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
19095 N0.getOpcode() == ISD::SIGN_EXTEND)) {
19096 SDValue N00 = N0.getOperand(0);
19098 // EXTLOAD has a better solution on AVX2,
19099 // it may be replaced with X86ISD::VSEXT node.
19100 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
19101 if (!ISD::isNormalLoad(N00.getNode()))
19104 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
19105 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
19107 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
19113 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
19114 TargetLowering::DAGCombinerInfo &DCI,
19115 const X86Subtarget *Subtarget) {
19116 if (!DCI.isBeforeLegalizeOps())
19119 if (!Subtarget->hasFp256())
19122 EVT VT = N->getValueType(0);
19123 if (VT.isVector() && VT.getSizeInBits() == 256) {
19124 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
19132 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
19133 const X86Subtarget* Subtarget) {
19135 EVT VT = N->getValueType(0);
19137 // Let legalize expand this if it isn't a legal type yet.
19138 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
19141 EVT ScalarVT = VT.getScalarType();
19142 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
19143 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
19146 SDValue A = N->getOperand(0);
19147 SDValue B = N->getOperand(1);
19148 SDValue C = N->getOperand(2);
19150 bool NegA = (A.getOpcode() == ISD::FNEG);
19151 bool NegB = (B.getOpcode() == ISD::FNEG);
19152 bool NegC = (C.getOpcode() == ISD::FNEG);
19154 // Negative multiplication when NegA xor NegB
19155 bool NegMul = (NegA != NegB);
19157 A = A.getOperand(0);
19159 B = B.getOperand(0);
19161 C = C.getOperand(0);
19165 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
19167 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
19169 return DAG.getNode(Opcode, dl, VT, A, B, C);
19172 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
19173 TargetLowering::DAGCombinerInfo &DCI,
19174 const X86Subtarget *Subtarget) {
19175 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
19176 // (and (i32 x86isd::setcc_carry), 1)
19177 // This eliminates the zext. This transformation is necessary because
19178 // ISD::SETCC is always legalized to i8.
19180 SDValue N0 = N->getOperand(0);
19181 EVT VT = N->getValueType(0);
19183 if (N0.getOpcode() == ISD::AND &&
19185 N0.getOperand(0).hasOneUse()) {
19186 SDValue N00 = N0.getOperand(0);
19187 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
19188 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
19189 if (!C || C->getZExtValue() != 1)
19191 return DAG.getNode(ISD::AND, dl, VT,
19192 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
19193 N00.getOperand(0), N00.getOperand(1)),
19194 DAG.getConstant(1, VT));
19198 if (N0.getOpcode() == ISD::TRUNCATE &&
19200 N0.getOperand(0).hasOneUse()) {
19201 SDValue N00 = N0.getOperand(0);
19202 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
19203 return DAG.getNode(ISD::AND, dl, VT,
19204 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
19205 N00.getOperand(0), N00.getOperand(1)),
19206 DAG.getConstant(1, VT));
19209 if (VT.is256BitVector()) {
19210 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
19218 // Optimize x == -y --> x+y == 0
19219 // x != -y --> x+y != 0
19220 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
19221 const X86Subtarget* Subtarget) {
19222 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
19223 SDValue LHS = N->getOperand(0);
19224 SDValue RHS = N->getOperand(1);
19225 EVT VT = N->getValueType(0);
19228 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
19229 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
19230 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
19231 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
19232 LHS.getValueType(), RHS, LHS.getOperand(1));
19233 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
19234 addV, DAG.getConstant(0, addV.getValueType()), CC);
19236 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
19237 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
19238 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
19239 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
19240 RHS.getValueType(), LHS, RHS.getOperand(1));
19241 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
19242 addV, DAG.getConstant(0, addV.getValueType()), CC);
19245 if (VT.getScalarType() == MVT::i1) {
19246 bool IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
19247 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
19248 bool IsVZero0 = ISD::isBuildVectorAllZeros(LHS.getNode());
19249 if (!IsSEXT0 && !IsVZero0)
19251 bool IsSEXT1 = (RHS.getOpcode() == ISD::SIGN_EXTEND) &&
19252 (RHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
19253 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
19255 if (!IsSEXT1 && !IsVZero1)
19258 if (IsSEXT0 && IsVZero1) {
19259 assert(VT == LHS.getOperand(0).getValueType() && "Uexpected operand type");
19260 if (CC == ISD::SETEQ)
19261 return DAG.getNOT(DL, LHS.getOperand(0), VT);
19262 return LHS.getOperand(0);
19264 if (IsSEXT1 && IsVZero0) {
19265 assert(VT == RHS.getOperand(0).getValueType() && "Uexpected operand type");
19266 if (CC == ISD::SETEQ)
19267 return DAG.getNOT(DL, RHS.getOperand(0), VT);
19268 return RHS.getOperand(0);
19275 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
19276 // as "sbb reg,reg", since it can be extended without zext and produces
19277 // an all-ones bit which is more useful than 0/1 in some cases.
19278 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
19281 return DAG.getNode(ISD::AND, DL, VT,
19282 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
19283 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
19284 DAG.getConstant(1, VT));
19285 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
19286 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
19287 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
19288 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS));
19291 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
19292 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
19293 TargetLowering::DAGCombinerInfo &DCI,
19294 const X86Subtarget *Subtarget) {
19296 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
19297 SDValue EFLAGS = N->getOperand(1);
19299 if (CC == X86::COND_A) {
19300 // Try to convert COND_A into COND_B in an attempt to facilitate
19301 // materializing "setb reg".
19303 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
19304 // cannot take an immediate as its first operand.
19306 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
19307 EFLAGS.getValueType().isInteger() &&
19308 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
19309 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
19310 EFLAGS.getNode()->getVTList(),
19311 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
19312 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
19313 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
19317 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
19318 // a zext and produces an all-ones bit which is more useful than 0/1 in some
19320 if (CC == X86::COND_B)
19321 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
19325 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
19326 if (Flags.getNode()) {
19327 SDValue Cond = DAG.getConstant(CC, MVT::i8);
19328 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
19334 // Optimize branch condition evaluation.
19336 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
19337 TargetLowering::DAGCombinerInfo &DCI,
19338 const X86Subtarget *Subtarget) {
19340 SDValue Chain = N->getOperand(0);
19341 SDValue Dest = N->getOperand(1);
19342 SDValue EFLAGS = N->getOperand(3);
19343 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
19347 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
19348 if (Flags.getNode()) {
19349 SDValue Cond = DAG.getConstant(CC, MVT::i8);
19350 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
19357 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
19358 const X86TargetLowering *XTLI) {
19359 SDValue Op0 = N->getOperand(0);
19360 EVT InVT = Op0->getValueType(0);
19362 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
19363 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
19365 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
19366 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
19367 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
19370 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
19371 // a 32-bit target where SSE doesn't support i64->FP operations.
19372 if (Op0.getOpcode() == ISD::LOAD) {
19373 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
19374 EVT VT = Ld->getValueType(0);
19375 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
19376 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
19377 !XTLI->getSubtarget()->is64Bit() &&
19379 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
19380 Ld->getChain(), Op0, DAG);
19381 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
19388 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
19389 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
19390 X86TargetLowering::DAGCombinerInfo &DCI) {
19391 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
19392 // the result is either zero or one (depending on the input carry bit).
19393 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
19394 if (X86::isZeroNode(N->getOperand(0)) &&
19395 X86::isZeroNode(N->getOperand(1)) &&
19396 // We don't have a good way to replace an EFLAGS use, so only do this when
19398 SDValue(N, 1).use_empty()) {
19400 EVT VT = N->getValueType(0);
19401 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
19402 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
19403 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
19404 DAG.getConstant(X86::COND_B,MVT::i8),
19406 DAG.getConstant(1, VT));
19407 return DCI.CombineTo(N, Res1, CarryOut);
19413 // fold (add Y, (sete X, 0)) -> adc 0, Y
19414 // (add Y, (setne X, 0)) -> sbb -1, Y
19415 // (sub (sete X, 0), Y) -> sbb 0, Y
19416 // (sub (setne X, 0), Y) -> adc -1, Y
19417 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
19420 // Look through ZExts.
19421 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
19422 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
19425 SDValue SetCC = Ext.getOperand(0);
19426 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
19429 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
19430 if (CC != X86::COND_E && CC != X86::COND_NE)
19433 SDValue Cmp = SetCC.getOperand(1);
19434 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
19435 !X86::isZeroNode(Cmp.getOperand(1)) ||
19436 !Cmp.getOperand(0).getValueType().isInteger())
19439 SDValue CmpOp0 = Cmp.getOperand(0);
19440 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
19441 DAG.getConstant(1, CmpOp0.getValueType()));
19443 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
19444 if (CC == X86::COND_NE)
19445 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
19446 DL, OtherVal.getValueType(), OtherVal,
19447 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
19448 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
19449 DL, OtherVal.getValueType(), OtherVal,
19450 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
19453 /// PerformADDCombine - Do target-specific dag combines on integer adds.
19454 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
19455 const X86Subtarget *Subtarget) {
19456 EVT VT = N->getValueType(0);
19457 SDValue Op0 = N->getOperand(0);
19458 SDValue Op1 = N->getOperand(1);
19460 // Try to synthesize horizontal adds from adds of shuffles.
19461 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
19462 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
19463 isHorizontalBinOp(Op0, Op1, true))
19464 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
19466 return OptimizeConditionalInDecrement(N, DAG);
19469 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
19470 const X86Subtarget *Subtarget) {
19471 SDValue Op0 = N->getOperand(0);
19472 SDValue Op1 = N->getOperand(1);
19474 // X86 can't encode an immediate LHS of a sub. See if we can push the
19475 // negation into a preceding instruction.
19476 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
19477 // If the RHS of the sub is a XOR with one use and a constant, invert the
19478 // immediate. Then add one to the LHS of the sub so we can turn
19479 // X-Y -> X+~Y+1, saving one register.
19480 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
19481 isa<ConstantSDNode>(Op1.getOperand(1))) {
19482 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
19483 EVT VT = Op0.getValueType();
19484 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
19486 DAG.getConstant(~XorC, VT));
19487 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
19488 DAG.getConstant(C->getAPIntValue()+1, VT));
19492 // Try to synthesize horizontal adds from adds of shuffles.
19493 EVT VT = N->getValueType(0);
19494 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
19495 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
19496 isHorizontalBinOp(Op0, Op1, true))
19497 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
19499 return OptimizeConditionalInDecrement(N, DAG);
19502 /// performVZEXTCombine - Performs build vector combines
19503 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
19504 TargetLowering::DAGCombinerInfo &DCI,
19505 const X86Subtarget *Subtarget) {
19506 // (vzext (bitcast (vzext (x)) -> (vzext x)
19507 SDValue In = N->getOperand(0);
19508 while (In.getOpcode() == ISD::BITCAST)
19509 In = In.getOperand(0);
19511 if (In.getOpcode() != X86ISD::VZEXT)
19514 return DAG.getNode(X86ISD::VZEXT, SDLoc(N), N->getValueType(0),
19518 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
19519 DAGCombinerInfo &DCI) const {
19520 SelectionDAG &DAG = DCI.DAG;
19521 switch (N->getOpcode()) {
19523 case ISD::EXTRACT_VECTOR_ELT:
19524 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
19526 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
19527 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
19528 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
19529 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
19530 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
19531 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
19534 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
19535 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
19536 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
19537 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
19538 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
19539 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
19540 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
19541 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
19542 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
19544 case X86ISD::FOR: return PerformFORCombine(N, DAG);
19546 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
19547 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
19548 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
19549 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
19550 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
19551 case ISD::ANY_EXTEND:
19552 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
19553 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
19554 case ISD::SIGN_EXTEND_INREG: return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
19555 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
19556 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
19557 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
19558 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
19559 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
19560 case X86ISD::SHUFP: // Handle all target specific shuffles
19561 case X86ISD::PALIGNR:
19562 case X86ISD::UNPCKH:
19563 case X86ISD::UNPCKL:
19564 case X86ISD::MOVHLPS:
19565 case X86ISD::MOVLHPS:
19566 case X86ISD::PSHUFD:
19567 case X86ISD::PSHUFHW:
19568 case X86ISD::PSHUFLW:
19569 case X86ISD::MOVSS:
19570 case X86ISD::MOVSD:
19571 case X86ISD::VPERMILP:
19572 case X86ISD::VPERM2X128:
19573 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
19574 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
19580 /// isTypeDesirableForOp - Return true if the target has native support for
19581 /// the specified value type and it is 'desirable' to use the type for the
19582 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
19583 /// instruction encodings are longer and some i16 instructions are slow.
19584 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
19585 if (!isTypeLegal(VT))
19587 if (VT != MVT::i16)
19594 case ISD::SIGN_EXTEND:
19595 case ISD::ZERO_EXTEND:
19596 case ISD::ANY_EXTEND:
19609 /// IsDesirableToPromoteOp - This method query the target whether it is
19610 /// beneficial for dag combiner to promote the specified node. If true, it
19611 /// should return the desired promotion type by reference.
19612 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
19613 EVT VT = Op.getValueType();
19614 if (VT != MVT::i16)
19617 bool Promote = false;
19618 bool Commute = false;
19619 switch (Op.getOpcode()) {
19622 LoadSDNode *LD = cast<LoadSDNode>(Op);
19623 // If the non-extending load has a single use and it's not live out, then it
19624 // might be folded.
19625 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
19626 Op.hasOneUse()*/) {
19627 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
19628 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
19629 // The only case where we'd want to promote LOAD (rather then it being
19630 // promoted as an operand is when it's only use is liveout.
19631 if (UI->getOpcode() != ISD::CopyToReg)
19638 case ISD::SIGN_EXTEND:
19639 case ISD::ZERO_EXTEND:
19640 case ISD::ANY_EXTEND:
19645 SDValue N0 = Op.getOperand(0);
19646 // Look out for (store (shl (load), x)).
19647 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
19660 SDValue N0 = Op.getOperand(0);
19661 SDValue N1 = Op.getOperand(1);
19662 if (!Commute && MayFoldLoad(N1))
19664 // Avoid disabling potential load folding opportunities.
19665 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
19667 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
19677 //===----------------------------------------------------------------------===//
19678 // X86 Inline Assembly Support
19679 //===----------------------------------------------------------------------===//
19682 // Helper to match a string separated by whitespace.
19683 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
19684 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
19686 for (unsigned i = 0, e = args.size(); i != e; ++i) {
19687 StringRef piece(*args[i]);
19688 if (!s.startswith(piece)) // Check if the piece matches.
19691 s = s.substr(piece.size());
19692 StringRef::size_type pos = s.find_first_not_of(" \t");
19693 if (pos == 0) // We matched a prefix.
19701 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
19704 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
19706 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
19707 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
19708 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
19709 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
19711 if (AsmPieces.size() == 3)
19713 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
19720 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
19721 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
19723 std::string AsmStr = IA->getAsmString();
19725 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
19726 if (!Ty || Ty->getBitWidth() % 16 != 0)
19729 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
19730 SmallVector<StringRef, 4> AsmPieces;
19731 SplitString(AsmStr, AsmPieces, ";\n");
19733 switch (AsmPieces.size()) {
19734 default: return false;
19736 // FIXME: this should verify that we are targeting a 486 or better. If not,
19737 // we will turn this bswap into something that will be lowered to logical
19738 // ops instead of emitting the bswap asm. For now, we don't support 486 or
19739 // lower so don't worry about this.
19741 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
19742 matchAsm(AsmPieces[0], "bswapl", "$0") ||
19743 matchAsm(AsmPieces[0], "bswapq", "$0") ||
19744 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
19745 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
19746 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
19747 // No need to check constraints, nothing other than the equivalent of
19748 // "=r,0" would be valid here.
19749 return IntrinsicLowering::LowerToByteSwap(CI);
19752 // rorw $$8, ${0:w} --> llvm.bswap.i16
19753 if (CI->getType()->isIntegerTy(16) &&
19754 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
19755 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
19756 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
19758 const std::string &ConstraintsStr = IA->getConstraintString();
19759 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
19760 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
19761 if (clobbersFlagRegisters(AsmPieces))
19762 return IntrinsicLowering::LowerToByteSwap(CI);
19766 if (CI->getType()->isIntegerTy(32) &&
19767 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
19768 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
19769 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
19770 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
19772 const std::string &ConstraintsStr = IA->getConstraintString();
19773 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
19774 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
19775 if (clobbersFlagRegisters(AsmPieces))
19776 return IntrinsicLowering::LowerToByteSwap(CI);
19779 if (CI->getType()->isIntegerTy(64)) {
19780 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
19781 if (Constraints.size() >= 2 &&
19782 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
19783 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
19784 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
19785 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
19786 matchAsm(AsmPieces[1], "bswap", "%edx") &&
19787 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
19788 return IntrinsicLowering::LowerToByteSwap(CI);
19796 /// getConstraintType - Given a constraint letter, return the type of
19797 /// constraint it is for this target.
19798 X86TargetLowering::ConstraintType
19799 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
19800 if (Constraint.size() == 1) {
19801 switch (Constraint[0]) {
19812 return C_RegisterClass;
19836 return TargetLowering::getConstraintType(Constraint);
19839 /// Examine constraint type and operand type and determine a weight value.
19840 /// This object must already have been set up with the operand type
19841 /// and the current alternative constraint selected.
19842 TargetLowering::ConstraintWeight
19843 X86TargetLowering::getSingleConstraintMatchWeight(
19844 AsmOperandInfo &info, const char *constraint) const {
19845 ConstraintWeight weight = CW_Invalid;
19846 Value *CallOperandVal = info.CallOperandVal;
19847 // If we don't have a value, we can't do a match,
19848 // but allow it at the lowest weight.
19849 if (CallOperandVal == NULL)
19851 Type *type = CallOperandVal->getType();
19852 // Look at the constraint type.
19853 switch (*constraint) {
19855 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
19866 if (CallOperandVal->getType()->isIntegerTy())
19867 weight = CW_SpecificReg;
19872 if (type->isFloatingPointTy())
19873 weight = CW_SpecificReg;
19876 if (type->isX86_MMXTy() && Subtarget->hasMMX())
19877 weight = CW_SpecificReg;
19881 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
19882 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
19883 weight = CW_Register;
19886 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
19887 if (C->getZExtValue() <= 31)
19888 weight = CW_Constant;
19892 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19893 if (C->getZExtValue() <= 63)
19894 weight = CW_Constant;
19898 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19899 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
19900 weight = CW_Constant;
19904 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19905 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
19906 weight = CW_Constant;
19910 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19911 if (C->getZExtValue() <= 3)
19912 weight = CW_Constant;
19916 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19917 if (C->getZExtValue() <= 0xff)
19918 weight = CW_Constant;
19923 if (dyn_cast<ConstantFP>(CallOperandVal)) {
19924 weight = CW_Constant;
19928 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19929 if ((C->getSExtValue() >= -0x80000000LL) &&
19930 (C->getSExtValue() <= 0x7fffffffLL))
19931 weight = CW_Constant;
19935 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19936 if (C->getZExtValue() <= 0xffffffff)
19937 weight = CW_Constant;
19944 /// LowerXConstraint - try to replace an X constraint, which matches anything,
19945 /// with another that has more specific requirements based on the type of the
19946 /// corresponding operand.
19947 const char *X86TargetLowering::
19948 LowerXConstraint(EVT ConstraintVT) const {
19949 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
19950 // 'f' like normal targets.
19951 if (ConstraintVT.isFloatingPoint()) {
19952 if (Subtarget->hasSSE2())
19954 if (Subtarget->hasSSE1())
19958 return TargetLowering::LowerXConstraint(ConstraintVT);
19961 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
19962 /// vector. If it is invalid, don't add anything to Ops.
19963 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
19964 std::string &Constraint,
19965 std::vector<SDValue>&Ops,
19966 SelectionDAG &DAG) const {
19967 SDValue Result(0, 0);
19969 // Only support length 1 constraints for now.
19970 if (Constraint.length() > 1) return;
19972 char ConstraintLetter = Constraint[0];
19973 switch (ConstraintLetter) {
19976 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19977 if (C->getZExtValue() <= 31) {
19978 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
19984 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19985 if (C->getZExtValue() <= 63) {
19986 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
19992 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19993 if (isInt<8>(C->getSExtValue())) {
19994 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
20000 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
20001 if (C->getZExtValue() <= 255) {
20002 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
20008 // 32-bit signed value
20009 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
20010 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
20011 C->getSExtValue())) {
20012 // Widen to 64 bits here to get it sign extended.
20013 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
20016 // FIXME gcc accepts some relocatable values here too, but only in certain
20017 // memory models; it's complicated.
20022 // 32-bit unsigned value
20023 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
20024 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
20025 C->getZExtValue())) {
20026 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
20030 // FIXME gcc accepts some relocatable values here too, but only in certain
20031 // memory models; it's complicated.
20035 // Literal immediates are always ok.
20036 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
20037 // Widen to 64 bits here to get it sign extended.
20038 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
20042 // In any sort of PIC mode addresses need to be computed at runtime by
20043 // adding in a register or some sort of table lookup. These can't
20044 // be used as immediates.
20045 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
20048 // If we are in non-pic codegen mode, we allow the address of a global (with
20049 // an optional displacement) to be used with 'i'.
20050 GlobalAddressSDNode *GA = 0;
20051 int64_t Offset = 0;
20053 // Match either (GA), (GA+C), (GA+C1+C2), etc.
20055 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
20056 Offset += GA->getOffset();
20058 } else if (Op.getOpcode() == ISD::ADD) {
20059 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
20060 Offset += C->getZExtValue();
20061 Op = Op.getOperand(0);
20064 } else if (Op.getOpcode() == ISD::SUB) {
20065 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
20066 Offset += -C->getZExtValue();
20067 Op = Op.getOperand(0);
20072 // Otherwise, this isn't something we can handle, reject it.
20076 const GlobalValue *GV = GA->getGlobal();
20077 // If we require an extra load to get this address, as in PIC mode, we
20078 // can't accept it.
20079 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
20080 getTargetMachine())))
20083 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
20084 GA->getValueType(0), Offset);
20089 if (Result.getNode()) {
20090 Ops.push_back(Result);
20093 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
20096 std::pair<unsigned, const TargetRegisterClass*>
20097 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
20099 // First, see if this is a constraint that directly corresponds to an LLVM
20101 if (Constraint.size() == 1) {
20102 // GCC Constraint Letters
20103 switch (Constraint[0]) {
20105 // TODO: Slight differences here in allocation order and leaving
20106 // RIP in the class. Do they matter any more here than they do
20107 // in the normal allocation?
20108 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
20109 if (Subtarget->is64Bit()) {
20110 if (VT == MVT::i32 || VT == MVT::f32)
20111 return std::make_pair(0U, &X86::GR32RegClass);
20112 if (VT == MVT::i16)
20113 return std::make_pair(0U, &X86::GR16RegClass);
20114 if (VT == MVT::i8 || VT == MVT::i1)
20115 return std::make_pair(0U, &X86::GR8RegClass);
20116 if (VT == MVT::i64 || VT == MVT::f64)
20117 return std::make_pair(0U, &X86::GR64RegClass);
20120 // 32-bit fallthrough
20121 case 'Q': // Q_REGS
20122 if (VT == MVT::i32 || VT == MVT::f32)
20123 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
20124 if (VT == MVT::i16)
20125 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
20126 if (VT == MVT::i8 || VT == MVT::i1)
20127 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
20128 if (VT == MVT::i64)
20129 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
20131 case 'r': // GENERAL_REGS
20132 case 'l': // INDEX_REGS
20133 if (VT == MVT::i8 || VT == MVT::i1)
20134 return std::make_pair(0U, &X86::GR8RegClass);
20135 if (VT == MVT::i16)
20136 return std::make_pair(0U, &X86::GR16RegClass);
20137 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
20138 return std::make_pair(0U, &X86::GR32RegClass);
20139 return std::make_pair(0U, &X86::GR64RegClass);
20140 case 'R': // LEGACY_REGS
20141 if (VT == MVT::i8 || VT == MVT::i1)
20142 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
20143 if (VT == MVT::i16)
20144 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
20145 if (VT == MVT::i32 || !Subtarget->is64Bit())
20146 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
20147 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
20148 case 'f': // FP Stack registers.
20149 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
20150 // value to the correct fpstack register class.
20151 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
20152 return std::make_pair(0U, &X86::RFP32RegClass);
20153 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
20154 return std::make_pair(0U, &X86::RFP64RegClass);
20155 return std::make_pair(0U, &X86::RFP80RegClass);
20156 case 'y': // MMX_REGS if MMX allowed.
20157 if (!Subtarget->hasMMX()) break;
20158 return std::make_pair(0U, &X86::VR64RegClass);
20159 case 'Y': // SSE_REGS if SSE2 allowed
20160 if (!Subtarget->hasSSE2()) break;
20162 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
20163 if (!Subtarget->hasSSE1()) break;
20165 switch (VT.SimpleTy) {
20167 // Scalar SSE types.
20170 return std::make_pair(0U, &X86::FR32RegClass);
20173 return std::make_pair(0U, &X86::FR64RegClass);
20181 return std::make_pair(0U, &X86::VR128RegClass);
20189 return std::make_pair(0U, &X86::VR256RegClass);
20194 return std::make_pair(0U, &X86::VR512RegClass);
20200 // Use the default implementation in TargetLowering to convert the register
20201 // constraint into a member of a register class.
20202 std::pair<unsigned, const TargetRegisterClass*> Res;
20203 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
20205 // Not found as a standard register?
20206 if (Res.second == 0) {
20207 // Map st(0) -> st(7) -> ST0
20208 if (Constraint.size() == 7 && Constraint[0] == '{' &&
20209 tolower(Constraint[1]) == 's' &&
20210 tolower(Constraint[2]) == 't' &&
20211 Constraint[3] == '(' &&
20212 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
20213 Constraint[5] == ')' &&
20214 Constraint[6] == '}') {
20216 Res.first = X86::ST0+Constraint[4]-'0';
20217 Res.second = &X86::RFP80RegClass;
20221 // GCC allows "st(0)" to be called just plain "st".
20222 if (StringRef("{st}").equals_lower(Constraint)) {
20223 Res.first = X86::ST0;
20224 Res.second = &X86::RFP80RegClass;
20229 if (StringRef("{flags}").equals_lower(Constraint)) {
20230 Res.first = X86::EFLAGS;
20231 Res.second = &X86::CCRRegClass;
20235 // 'A' means EAX + EDX.
20236 if (Constraint == "A") {
20237 Res.first = X86::EAX;
20238 Res.second = &X86::GR32_ADRegClass;
20244 // Otherwise, check to see if this is a register class of the wrong value
20245 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
20246 // turn into {ax},{dx}.
20247 if (Res.second->hasType(VT))
20248 return Res; // Correct type already, nothing to do.
20250 // All of the single-register GCC register classes map their values onto
20251 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
20252 // really want an 8-bit or 32-bit register, map to the appropriate register
20253 // class and return the appropriate register.
20254 if (Res.second == &X86::GR16RegClass) {
20255 if (VT == MVT::i8 || VT == MVT::i1) {
20256 unsigned DestReg = 0;
20257 switch (Res.first) {
20259 case X86::AX: DestReg = X86::AL; break;
20260 case X86::DX: DestReg = X86::DL; break;
20261 case X86::CX: DestReg = X86::CL; break;
20262 case X86::BX: DestReg = X86::BL; break;
20265 Res.first = DestReg;
20266 Res.second = &X86::GR8RegClass;
20268 } else if (VT == MVT::i32 || VT == MVT::f32) {
20269 unsigned DestReg = 0;
20270 switch (Res.first) {
20272 case X86::AX: DestReg = X86::EAX; break;
20273 case X86::DX: DestReg = X86::EDX; break;
20274 case X86::CX: DestReg = X86::ECX; break;
20275 case X86::BX: DestReg = X86::EBX; break;
20276 case X86::SI: DestReg = X86::ESI; break;
20277 case X86::DI: DestReg = X86::EDI; break;
20278 case X86::BP: DestReg = X86::EBP; break;
20279 case X86::SP: DestReg = X86::ESP; break;
20282 Res.first = DestReg;
20283 Res.second = &X86::GR32RegClass;
20285 } else if (VT == MVT::i64 || VT == MVT::f64) {
20286 unsigned DestReg = 0;
20287 switch (Res.first) {
20289 case X86::AX: DestReg = X86::RAX; break;
20290 case X86::DX: DestReg = X86::RDX; break;
20291 case X86::CX: DestReg = X86::RCX; break;
20292 case X86::BX: DestReg = X86::RBX; break;
20293 case X86::SI: DestReg = X86::RSI; break;
20294 case X86::DI: DestReg = X86::RDI; break;
20295 case X86::BP: DestReg = X86::RBP; break;
20296 case X86::SP: DestReg = X86::RSP; break;
20299 Res.first = DestReg;
20300 Res.second = &X86::GR64RegClass;
20303 } else if (Res.second == &X86::FR32RegClass ||
20304 Res.second == &X86::FR64RegClass ||
20305 Res.second == &X86::VR128RegClass ||
20306 Res.second == &X86::VR256RegClass ||
20307 Res.second == &X86::FR32XRegClass ||
20308 Res.second == &X86::FR64XRegClass ||
20309 Res.second == &X86::VR128XRegClass ||
20310 Res.second == &X86::VR256XRegClass ||
20311 Res.second == &X86::VR512RegClass) {
20312 // Handle references to XMM physical registers that got mapped into the
20313 // wrong class. This can happen with constraints like {xmm0} where the
20314 // target independent register mapper will just pick the first match it can
20315 // find, ignoring the required type.
20317 if (VT == MVT::f32 || VT == MVT::i32)
20318 Res.second = &X86::FR32RegClass;
20319 else if (VT == MVT::f64 || VT == MVT::i64)
20320 Res.second = &X86::FR64RegClass;
20321 else if (X86::VR128RegClass.hasType(VT))
20322 Res.second = &X86::VR128RegClass;
20323 else if (X86::VR256RegClass.hasType(VT))
20324 Res.second = &X86::VR256RegClass;
20325 else if (X86::VR512RegClass.hasType(VT))
20326 Res.second = &X86::VR512RegClass;