1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
17 #include "X86InstrBuilder.h"
18 #include "X86ISelLowering.h"
19 #include "X86MCTargetExpr.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/GlobalAlias.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/Function.h"
28 #include "llvm/Instructions.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/LLVMContext.h"
31 #include "llvm/CodeGen/MachineFrameInfo.h"
32 #include "llvm/CodeGen/MachineFunction.h"
33 #include "llvm/CodeGen/MachineInstrBuilder.h"
34 #include "llvm/CodeGen/MachineJumpTableInfo.h"
35 #include "llvm/CodeGen/MachineModuleInfo.h"
36 #include "llvm/CodeGen/MachineRegisterInfo.h"
37 #include "llvm/CodeGen/PseudoSourceValue.h"
38 #include "llvm/MC/MCAsmInfo.h"
39 #include "llvm/MC/MCContext.h"
40 #include "llvm/MC/MCSymbol.h"
41 #include "llvm/ADT/BitVector.h"
42 #include "llvm/ADT/SmallSet.h"
43 #include "llvm/ADT/Statistic.h"
44 #include "llvm/ADT/StringExtras.h"
45 #include "llvm/ADT/VectorExtras.h"
46 #include "llvm/Support/CommandLine.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/Dwarf.h"
49 #include "llvm/Support/ErrorHandling.h"
50 #include "llvm/Support/MathExtras.h"
51 #include "llvm/Support/raw_ostream.h"
53 using namespace dwarf;
55 STATISTIC(NumTailCalls, "Number of tail calls");
58 DisableMMX("disable-mmx", cl::Hidden, cl::desc("Disable use of MMX"));
60 // Disable16Bit - 16-bit operations typically have a larger encoding than
61 // corresponding 32-bit instructions, and 16-bit code is slow on some
62 // processors. This is an experimental flag to disable 16-bit operations
63 // (which forces them to be Legalized to 32-bit operations).
65 Disable16Bit("disable-16bit", cl::Hidden,
66 cl::desc("Disable use of 16-bit instructions"));
68 // Forward declarations.
69 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
72 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
73 switch (TM.getSubtarget<X86Subtarget>().TargetType) {
74 default: llvm_unreachable("unknown subtarget type");
75 case X86Subtarget::isDarwin:
76 if (TM.getSubtarget<X86Subtarget>().is64Bit())
77 return new X8664_MachoTargetObjectFile();
78 return new TargetLoweringObjectFileMachO();
79 case X86Subtarget::isELF:
80 if (TM.getSubtarget<X86Subtarget>().is64Bit())
81 return new X8664_ELFTargetObjectFile(TM);
82 return new X8632_ELFTargetObjectFile(TM);
83 case X86Subtarget::isMingw:
84 case X86Subtarget::isCygwin:
85 case X86Subtarget::isWindows:
86 return new TargetLoweringObjectFileCOFF();
90 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
91 : TargetLowering(TM, createTLOF(TM)) {
92 Subtarget = &TM.getSubtarget<X86Subtarget>();
93 X86ScalarSSEf64 = Subtarget->hasSSE2();
94 X86ScalarSSEf32 = Subtarget->hasSSE1();
95 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
97 RegInfo = TM.getRegisterInfo();
100 // Set up the TargetLowering object.
102 // X86 is weird, it always uses i8 for shift amounts and setcc results.
103 setShiftAmountType(MVT::i8);
104 setBooleanContents(ZeroOrOneBooleanContent);
105 setSchedulingPreference(SchedulingForRegPressure);
106 setStackPointerRegisterToSaveRestore(X86StackPtr);
108 if (Subtarget->isTargetDarwin()) {
109 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
110 setUseUnderscoreSetJmp(false);
111 setUseUnderscoreLongJmp(false);
112 } else if (Subtarget->isTargetMingw()) {
113 // MS runtime is weird: it exports _setjmp, but longjmp!
114 setUseUnderscoreSetJmp(true);
115 setUseUnderscoreLongJmp(false);
117 setUseUnderscoreSetJmp(true);
118 setUseUnderscoreLongJmp(true);
121 // Set up the register classes.
122 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
124 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
125 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
126 if (Subtarget->is64Bit())
127 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
129 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
131 // We don't accept any truncstore of integer registers.
132 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
134 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
135 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
137 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
138 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
139 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
141 // SETOEQ and SETUNE require checking two conditions.
142 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
143 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
144 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
145 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
146 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
147 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
149 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
151 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
152 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
153 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
155 if (Subtarget->is64Bit()) {
156 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
157 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
158 } else if (!UseSoftFloat) {
159 if (X86ScalarSSEf64) {
160 // We have an impenetrably clever algorithm for ui64->double only.
161 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
163 // We have an algorithm for SSE2, and we turn this into a 64-bit
164 // FILD for other targets.
165 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
168 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
170 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
171 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
174 // SSE has no i16 to fp conversion, only i32
175 if (X86ScalarSSEf32) {
176 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
177 // f32 and f64 cases are Legal, f80 case is not
178 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
180 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
181 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
184 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
185 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
188 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
189 // are Legal, f80 is custom lowered.
190 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
191 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
193 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
195 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
196 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
198 if (X86ScalarSSEf32) {
199 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
200 // f32 and f64 cases are Legal, f80 case is not
201 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
203 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
204 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
207 // Handle FP_TO_UINT by promoting the destination to a larger signed
209 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
210 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
211 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
213 if (Subtarget->is64Bit()) {
214 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
215 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
216 } else if (!UseSoftFloat) {
217 if (X86ScalarSSEf32 && !Subtarget->hasSSE3())
218 // Expand FP_TO_UINT into a select.
219 // FIXME: We would like to use a Custom expander here eventually to do
220 // the optimal thing for SSE vs. the default expansion in the legalizer.
221 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
223 // With SSE3 we can use fisttpll to convert to a signed i64; without
224 // SSE, we're stuck with a fistpll.
225 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
228 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
229 if (!X86ScalarSSEf64) {
230 setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand);
231 setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand);
234 // Scalar integer divide and remainder are lowered to use operations that
235 // produce two results, to match the available instructions. This exposes
236 // the two-result form to trivial CSE, which is able to combine x/y and x%y
237 // into a single instruction.
239 // Scalar integer multiply-high is also lowered to use two-result
240 // operations, to match the available instructions. However, plain multiply
241 // (low) operations are left as Legal, as there are single-result
242 // instructions for this in x86. Using the two-result multiply instructions
243 // when both high and low results are needed must be arranged by dagcombine.
244 setOperationAction(ISD::MULHS , MVT::i8 , Expand);
245 setOperationAction(ISD::MULHU , MVT::i8 , Expand);
246 setOperationAction(ISD::SDIV , MVT::i8 , Expand);
247 setOperationAction(ISD::UDIV , MVT::i8 , Expand);
248 setOperationAction(ISD::SREM , MVT::i8 , Expand);
249 setOperationAction(ISD::UREM , MVT::i8 , Expand);
250 setOperationAction(ISD::MULHS , MVT::i16 , Expand);
251 setOperationAction(ISD::MULHU , MVT::i16 , Expand);
252 setOperationAction(ISD::SDIV , MVT::i16 , Expand);
253 setOperationAction(ISD::UDIV , MVT::i16 , Expand);
254 setOperationAction(ISD::SREM , MVT::i16 , Expand);
255 setOperationAction(ISD::UREM , MVT::i16 , Expand);
256 setOperationAction(ISD::MULHS , MVT::i32 , Expand);
257 setOperationAction(ISD::MULHU , MVT::i32 , Expand);
258 setOperationAction(ISD::SDIV , MVT::i32 , Expand);
259 setOperationAction(ISD::UDIV , MVT::i32 , Expand);
260 setOperationAction(ISD::SREM , MVT::i32 , Expand);
261 setOperationAction(ISD::UREM , MVT::i32 , Expand);
262 setOperationAction(ISD::MULHS , MVT::i64 , Expand);
263 setOperationAction(ISD::MULHU , MVT::i64 , Expand);
264 setOperationAction(ISD::SDIV , MVT::i64 , Expand);
265 setOperationAction(ISD::UDIV , MVT::i64 , Expand);
266 setOperationAction(ISD::SREM , MVT::i64 , Expand);
267 setOperationAction(ISD::UREM , MVT::i64 , Expand);
269 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
270 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
271 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
272 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
273 if (Subtarget->is64Bit())
274 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
275 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
276 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
277 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
278 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
279 setOperationAction(ISD::FREM , MVT::f32 , Expand);
280 setOperationAction(ISD::FREM , MVT::f64 , Expand);
281 setOperationAction(ISD::FREM , MVT::f80 , Expand);
282 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
284 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
285 setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
286 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
287 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
289 setOperationAction(ISD::CTTZ , MVT::i16 , Expand);
290 setOperationAction(ISD::CTLZ , MVT::i16 , Expand);
292 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
293 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
295 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
296 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
297 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
298 if (Subtarget->is64Bit()) {
299 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
300 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
301 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
304 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
305 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
307 // These should be promoted to a larger select which is supported.
308 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
309 // X86 wants to expand cmov itself.
310 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
312 setOperationAction(ISD::SELECT , MVT::i16 , Expand);
314 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
315 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
316 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
317 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
318 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
319 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
321 setOperationAction(ISD::SETCC , MVT::i16 , Expand);
323 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
324 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
325 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
326 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
327 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
328 if (Subtarget->is64Bit()) {
329 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
330 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
332 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
335 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
336 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
337 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
338 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
339 if (Subtarget->is64Bit())
340 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
341 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
342 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
343 if (Subtarget->is64Bit()) {
344 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
345 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
346 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
347 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
348 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
350 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
351 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
352 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
353 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
354 if (Subtarget->is64Bit()) {
355 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
356 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
357 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
360 if (Subtarget->hasSSE1())
361 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
363 if (!Subtarget->hasSSE2())
364 setOperationAction(ISD::MEMBARRIER , MVT::Other, Expand);
366 // Expand certain atomics
367 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Custom);
368 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Custom);
369 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
370 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom);
372 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i8, Custom);
373 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i16, Custom);
374 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Custom);
375 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
377 if (!Subtarget->is64Bit()) {
378 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
379 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
380 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
381 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
382 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
383 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
384 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
387 // FIXME - use subtarget debug flags
388 if (!Subtarget->isTargetDarwin() &&
389 !Subtarget->isTargetELF() &&
390 !Subtarget->isTargetCygMing()) {
391 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
394 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
395 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
396 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
397 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
398 if (Subtarget->is64Bit()) {
399 setExceptionPointerRegister(X86::RAX);
400 setExceptionSelectorRegister(X86::RDX);
402 setExceptionPointerRegister(X86::EAX);
403 setExceptionSelectorRegister(X86::EDX);
405 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
406 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
408 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
410 setOperationAction(ISD::TRAP, MVT::Other, Legal);
412 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
413 setOperationAction(ISD::VASTART , MVT::Other, Custom);
414 setOperationAction(ISD::VAEND , MVT::Other, Expand);
415 if (Subtarget->is64Bit()) {
416 setOperationAction(ISD::VAARG , MVT::Other, Custom);
417 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
419 setOperationAction(ISD::VAARG , MVT::Other, Expand);
420 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
423 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
424 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
425 if (Subtarget->is64Bit())
426 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
427 if (Subtarget->isTargetCygMing())
428 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
430 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
432 if (!UseSoftFloat && X86ScalarSSEf64) {
433 // f32 and f64 use SSE.
434 // Set up the FP register classes.
435 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
436 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
438 // Use ANDPD to simulate FABS.
439 setOperationAction(ISD::FABS , MVT::f64, Custom);
440 setOperationAction(ISD::FABS , MVT::f32, Custom);
442 // Use XORP to simulate FNEG.
443 setOperationAction(ISD::FNEG , MVT::f64, Custom);
444 setOperationAction(ISD::FNEG , MVT::f32, Custom);
446 // Use ANDPD and ORPD to simulate FCOPYSIGN.
447 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
448 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
450 // We don't support sin/cos/fmod
451 setOperationAction(ISD::FSIN , MVT::f64, Expand);
452 setOperationAction(ISD::FCOS , MVT::f64, Expand);
453 setOperationAction(ISD::FSIN , MVT::f32, Expand);
454 setOperationAction(ISD::FCOS , MVT::f32, Expand);
456 // Expand FP immediates into loads from the stack, except for the special
458 addLegalFPImmediate(APFloat(+0.0)); // xorpd
459 addLegalFPImmediate(APFloat(+0.0f)); // xorps
460 } else if (!UseSoftFloat && X86ScalarSSEf32) {
461 // Use SSE for f32, x87 for f64.
462 // Set up the FP register classes.
463 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
464 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
466 // Use ANDPS to simulate FABS.
467 setOperationAction(ISD::FABS , MVT::f32, Custom);
469 // Use XORP to simulate FNEG.
470 setOperationAction(ISD::FNEG , MVT::f32, Custom);
472 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
474 // Use ANDPS and ORPS to simulate FCOPYSIGN.
475 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
476 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
478 // We don't support sin/cos/fmod
479 setOperationAction(ISD::FSIN , MVT::f32, Expand);
480 setOperationAction(ISD::FCOS , MVT::f32, Expand);
482 // Special cases we handle for FP constants.
483 addLegalFPImmediate(APFloat(+0.0f)); // xorps
484 addLegalFPImmediate(APFloat(+0.0)); // FLD0
485 addLegalFPImmediate(APFloat(+1.0)); // FLD1
486 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
487 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
490 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
491 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
493 } else if (!UseSoftFloat) {
494 // f32 and f64 in x87.
495 // Set up the FP register classes.
496 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
497 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
499 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
500 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
501 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
502 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
505 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
506 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
508 addLegalFPImmediate(APFloat(+0.0)); // FLD0
509 addLegalFPImmediate(APFloat(+1.0)); // FLD1
510 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
511 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
512 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
513 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
514 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
515 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
518 // Long double always uses X87.
520 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
521 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
522 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
525 APFloat TmpFlt(+0.0);
526 TmpFlt.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
528 addLegalFPImmediate(TmpFlt); // FLD0
530 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
531 APFloat TmpFlt2(+1.0);
532 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
534 addLegalFPImmediate(TmpFlt2); // FLD1
535 TmpFlt2.changeSign();
536 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
540 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
541 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
545 // Always use a library call for pow.
546 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
547 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
548 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
550 setOperationAction(ISD::FLOG, MVT::f80, Expand);
551 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
552 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
553 setOperationAction(ISD::FEXP, MVT::f80, Expand);
554 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
556 // First set operation action for all vector types to either promote
557 // (for widening) or expand (for scalarization). Then we will selectively
558 // turn on ones that can be effectively codegen'd.
559 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
560 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
561 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
562 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
563 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
564 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
565 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
566 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
567 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
568 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
569 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
570 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
571 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
572 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
573 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
574 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
575 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
576 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
577 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
578 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
579 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
580 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
581 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
582 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
583 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
584 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
585 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
586 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
587 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
588 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
589 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
590 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
591 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
592 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
593 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
594 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
595 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
596 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
597 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
598 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
599 setOperationAction(ISD::VSETCC, (MVT::SimpleValueType)VT, Expand);
600 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
601 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
602 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
603 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
604 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
605 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand);
606 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand);
607 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
608 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
609 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand);
610 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand);
611 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand);
612 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand);
613 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand);
614 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
615 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
616 setTruncStoreAction((MVT::SimpleValueType)VT,
617 (MVT::SimpleValueType)InnerVT, Expand);
618 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
619 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
620 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
623 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
624 // with -msoft-float, disable use of MMX as well.
625 if (!UseSoftFloat && !DisableMMX && Subtarget->hasMMX()) {
626 addRegisterClass(MVT::v8i8, X86::VR64RegisterClass);
627 addRegisterClass(MVT::v4i16, X86::VR64RegisterClass);
628 addRegisterClass(MVT::v2i32, X86::VR64RegisterClass);
629 addRegisterClass(MVT::v2f32, X86::VR64RegisterClass);
630 addRegisterClass(MVT::v1i64, X86::VR64RegisterClass);
632 setOperationAction(ISD::ADD, MVT::v8i8, Legal);
633 setOperationAction(ISD::ADD, MVT::v4i16, Legal);
634 setOperationAction(ISD::ADD, MVT::v2i32, Legal);
635 setOperationAction(ISD::ADD, MVT::v1i64, Legal);
637 setOperationAction(ISD::SUB, MVT::v8i8, Legal);
638 setOperationAction(ISD::SUB, MVT::v4i16, Legal);
639 setOperationAction(ISD::SUB, MVT::v2i32, Legal);
640 setOperationAction(ISD::SUB, MVT::v1i64, Legal);
642 setOperationAction(ISD::MULHS, MVT::v4i16, Legal);
643 setOperationAction(ISD::MUL, MVT::v4i16, Legal);
645 setOperationAction(ISD::AND, MVT::v8i8, Promote);
646 AddPromotedToType (ISD::AND, MVT::v8i8, MVT::v1i64);
647 setOperationAction(ISD::AND, MVT::v4i16, Promote);
648 AddPromotedToType (ISD::AND, MVT::v4i16, MVT::v1i64);
649 setOperationAction(ISD::AND, MVT::v2i32, Promote);
650 AddPromotedToType (ISD::AND, MVT::v2i32, MVT::v1i64);
651 setOperationAction(ISD::AND, MVT::v1i64, Legal);
653 setOperationAction(ISD::OR, MVT::v8i8, Promote);
654 AddPromotedToType (ISD::OR, MVT::v8i8, MVT::v1i64);
655 setOperationAction(ISD::OR, MVT::v4i16, Promote);
656 AddPromotedToType (ISD::OR, MVT::v4i16, MVT::v1i64);
657 setOperationAction(ISD::OR, MVT::v2i32, Promote);
658 AddPromotedToType (ISD::OR, MVT::v2i32, MVT::v1i64);
659 setOperationAction(ISD::OR, MVT::v1i64, Legal);
661 setOperationAction(ISD::XOR, MVT::v8i8, Promote);
662 AddPromotedToType (ISD::XOR, MVT::v8i8, MVT::v1i64);
663 setOperationAction(ISD::XOR, MVT::v4i16, Promote);
664 AddPromotedToType (ISD::XOR, MVT::v4i16, MVT::v1i64);
665 setOperationAction(ISD::XOR, MVT::v2i32, Promote);
666 AddPromotedToType (ISD::XOR, MVT::v2i32, MVT::v1i64);
667 setOperationAction(ISD::XOR, MVT::v1i64, Legal);
669 setOperationAction(ISD::LOAD, MVT::v8i8, Promote);
670 AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v1i64);
671 setOperationAction(ISD::LOAD, MVT::v4i16, Promote);
672 AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v1i64);
673 setOperationAction(ISD::LOAD, MVT::v2i32, Promote);
674 AddPromotedToType (ISD::LOAD, MVT::v2i32, MVT::v1i64);
675 setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
676 AddPromotedToType (ISD::LOAD, MVT::v2f32, MVT::v1i64);
677 setOperationAction(ISD::LOAD, MVT::v1i64, Legal);
679 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom);
680 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom);
681 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Custom);
682 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f32, Custom);
683 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom);
685 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
686 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
687 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom);
688 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1i64, Custom);
690 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f32, Custom);
691 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Custom);
692 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom);
693 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom);
695 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i16, Custom);
697 setOperationAction(ISD::SELECT, MVT::v8i8, Promote);
698 setOperationAction(ISD::SELECT, MVT::v4i16, Promote);
699 setOperationAction(ISD::SELECT, MVT::v2i32, Promote);
700 setOperationAction(ISD::SELECT, MVT::v1i64, Custom);
701 setOperationAction(ISD::VSETCC, MVT::v8i8, Custom);
702 setOperationAction(ISD::VSETCC, MVT::v4i16, Custom);
703 setOperationAction(ISD::VSETCC, MVT::v2i32, Custom);
706 if (!UseSoftFloat && Subtarget->hasSSE1()) {
707 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
709 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
710 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
711 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
712 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
713 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
714 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
715 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
716 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
717 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
718 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
719 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
720 setOperationAction(ISD::VSETCC, MVT::v4f32, Custom);
723 if (!UseSoftFloat && Subtarget->hasSSE2()) {
724 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
726 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
727 // registers cannot be used even for integer operations.
728 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
729 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
730 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
731 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
733 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
734 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
735 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
736 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
737 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
738 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
739 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
740 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
741 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
742 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
743 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
744 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
745 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
746 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
747 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
748 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
750 setOperationAction(ISD::VSETCC, MVT::v2f64, Custom);
751 setOperationAction(ISD::VSETCC, MVT::v16i8, Custom);
752 setOperationAction(ISD::VSETCC, MVT::v8i16, Custom);
753 setOperationAction(ISD::VSETCC, MVT::v4i32, Custom);
755 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
756 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
757 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
758 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
759 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
761 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom);
762 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom);
763 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom);
764 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom);
765 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
767 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
768 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
769 EVT VT = (MVT::SimpleValueType)i;
770 // Do not attempt to custom lower non-power-of-2 vectors
771 if (!isPowerOf2_32(VT.getVectorNumElements()))
773 // Do not attempt to custom lower non-128-bit vectors
774 if (!VT.is128BitVector())
776 setOperationAction(ISD::BUILD_VECTOR,
777 VT.getSimpleVT().SimpleTy, Custom);
778 setOperationAction(ISD::VECTOR_SHUFFLE,
779 VT.getSimpleVT().SimpleTy, Custom);
780 setOperationAction(ISD::EXTRACT_VECTOR_ELT,
781 VT.getSimpleVT().SimpleTy, Custom);
784 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
785 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
786 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
787 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
788 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
789 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
791 if (Subtarget->is64Bit()) {
792 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
793 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
796 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
797 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) {
798 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
801 // Do not attempt to promote non-128-bit vectors
802 if (!VT.is128BitVector()) {
805 setOperationAction(ISD::AND, SVT, Promote);
806 AddPromotedToType (ISD::AND, SVT, MVT::v2i64);
807 setOperationAction(ISD::OR, SVT, Promote);
808 AddPromotedToType (ISD::OR, SVT, MVT::v2i64);
809 setOperationAction(ISD::XOR, SVT, Promote);
810 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64);
811 setOperationAction(ISD::LOAD, SVT, Promote);
812 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64);
813 setOperationAction(ISD::SELECT, SVT, Promote);
814 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64);
817 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
819 // Custom lower v2i64 and v2f64 selects.
820 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
821 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
822 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
823 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
825 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
826 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
827 if (!DisableMMX && Subtarget->hasMMX()) {
828 setOperationAction(ISD::FP_TO_SINT, MVT::v2i32, Custom);
829 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
833 if (Subtarget->hasSSE41()) {
834 // FIXME: Do we need to handle scalar-to-vector here?
835 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
837 // i8 and i16 vectors are custom , because the source register and source
838 // source memory operand types are not the same width. f32 vectors are
839 // custom since the immediate controlling the insert encodes additional
841 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
842 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
843 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
844 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
846 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
847 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
848 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
849 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
851 if (Subtarget->is64Bit()) {
852 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal);
853 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
857 if (Subtarget->hasSSE42()) {
858 setOperationAction(ISD::VSETCC, MVT::v2i64, Custom);
861 if (!UseSoftFloat && Subtarget->hasAVX()) {
862 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass);
863 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass);
864 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass);
865 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass);
867 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
868 setOperationAction(ISD::LOAD, MVT::v8i32, Legal);
869 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
870 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
871 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
872 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
873 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
874 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
875 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
876 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
877 //setOperationAction(ISD::BUILD_VECTOR, MVT::v8f32, Custom);
878 //setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Custom);
879 //setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8f32, Custom);
880 //setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
881 //setOperationAction(ISD::VSETCC, MVT::v8f32, Custom);
883 // Operations to consider commented out -v16i16 v32i8
884 //setOperationAction(ISD::ADD, MVT::v16i16, Legal);
885 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
886 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
887 //setOperationAction(ISD::SUB, MVT::v32i8, Legal);
888 //setOperationAction(ISD::SUB, MVT::v16i16, Legal);
889 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
890 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
891 //setOperationAction(ISD::MUL, MVT::v16i16, Legal);
892 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
893 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
894 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
895 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
896 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
897 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
899 setOperationAction(ISD::VSETCC, MVT::v4f64, Custom);
900 // setOperationAction(ISD::VSETCC, MVT::v32i8, Custom);
901 // setOperationAction(ISD::VSETCC, MVT::v16i16, Custom);
902 setOperationAction(ISD::VSETCC, MVT::v8i32, Custom);
904 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v32i8, Custom);
905 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i16, Custom);
906 // setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i16, Custom);
907 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i32, Custom);
908 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8f32, Custom);
910 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f64, Custom);
911 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i64, Custom);
912 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f64, Custom);
913 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i64, Custom);
914 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f64, Custom);
915 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f64, Custom);
918 // Not sure we want to do this since there are no 256-bit integer
921 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
922 // This includes 256-bit vectors
923 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; ++i) {
924 EVT VT = (MVT::SimpleValueType)i;
926 // Do not attempt to custom lower non-power-of-2 vectors
927 if (!isPowerOf2_32(VT.getVectorNumElements()))
930 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
931 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
932 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
935 if (Subtarget->is64Bit()) {
936 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i64, Custom);
937 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i64, Custom);
942 // Not sure we want to do this since there are no 256-bit integer
945 // Promote v32i8, v16i16, v8i32 load, select, and, or, xor to v4i64.
946 // Including 256-bit vectors
947 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; i++) {
948 EVT VT = (MVT::SimpleValueType)i;
950 if (!VT.is256BitVector()) {
953 setOperationAction(ISD::AND, VT, Promote);
954 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
955 setOperationAction(ISD::OR, VT, Promote);
956 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
957 setOperationAction(ISD::XOR, VT, Promote);
958 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
959 setOperationAction(ISD::LOAD, VT, Promote);
960 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
961 setOperationAction(ISD::SELECT, VT, Promote);
962 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
965 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
969 // We want to custom lower some of our intrinsics.
970 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
972 // Add/Sub/Mul with overflow operations are custom lowered.
973 setOperationAction(ISD::SADDO, MVT::i32, Custom);
974 setOperationAction(ISD::SADDO, MVT::i64, Custom);
975 setOperationAction(ISD::UADDO, MVT::i32, Custom);
976 setOperationAction(ISD::UADDO, MVT::i64, Custom);
977 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
978 setOperationAction(ISD::SSUBO, MVT::i64, Custom);
979 setOperationAction(ISD::USUBO, MVT::i32, Custom);
980 setOperationAction(ISD::USUBO, MVT::i64, Custom);
981 setOperationAction(ISD::SMULO, MVT::i32, Custom);
982 setOperationAction(ISD::SMULO, MVT::i64, Custom);
984 if (!Subtarget->is64Bit()) {
985 // These libcalls are not available in 32-bit.
986 setLibcallName(RTLIB::SHL_I128, 0);
987 setLibcallName(RTLIB::SRL_I128, 0);
988 setLibcallName(RTLIB::SRA_I128, 0);
991 // We have target-specific dag combine patterns for the following nodes:
992 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
993 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
994 setTargetDAGCombine(ISD::BUILD_VECTOR);
995 setTargetDAGCombine(ISD::SELECT);
996 setTargetDAGCombine(ISD::SHL);
997 setTargetDAGCombine(ISD::SRA);
998 setTargetDAGCombine(ISD::SRL);
999 setTargetDAGCombine(ISD::OR);
1000 setTargetDAGCombine(ISD::STORE);
1001 setTargetDAGCombine(ISD::MEMBARRIER);
1002 setTargetDAGCombine(ISD::ZERO_EXTEND);
1003 if (Subtarget->is64Bit())
1004 setTargetDAGCombine(ISD::MUL);
1006 computeRegisterProperties();
1008 // FIXME: These should be based on subtarget info. Plus, the values should
1009 // be smaller when we are in optimizing for size mode.
1010 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1011 maxStoresPerMemcpy = 16; // For @llvm.memcpy -> sequence of stores
1012 maxStoresPerMemmove = 3; // For @llvm.memmove -> sequence of stores
1013 setPrefLoopAlignment(16);
1014 benefitFromCodePlacementOpt = true;
1018 MVT::SimpleValueType X86TargetLowering::getSetCCResultType(EVT VT) const {
1023 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1024 /// the desired ByVal argument alignment.
1025 static void getMaxByValAlign(const Type *Ty, unsigned &MaxAlign) {
1028 if (const VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1029 if (VTy->getBitWidth() == 128)
1031 } else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1032 unsigned EltAlign = 0;
1033 getMaxByValAlign(ATy->getElementType(), EltAlign);
1034 if (EltAlign > MaxAlign)
1035 MaxAlign = EltAlign;
1036 } else if (const StructType *STy = dyn_cast<StructType>(Ty)) {
1037 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1038 unsigned EltAlign = 0;
1039 getMaxByValAlign(STy->getElementType(i), EltAlign);
1040 if (EltAlign > MaxAlign)
1041 MaxAlign = EltAlign;
1049 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1050 /// function arguments in the caller parameter area. For X86, aggregates
1051 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1052 /// are at 4-byte boundaries.
1053 unsigned X86TargetLowering::getByValTypeAlignment(const Type *Ty) const {
1054 if (Subtarget->is64Bit()) {
1055 // Max of 8 and alignment of type.
1056 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1063 if (Subtarget->hasSSE1())
1064 getMaxByValAlign(Ty, Align);
1068 /// getOptimalMemOpType - Returns the target specific optimal type for load
1069 /// and store operations as a result of memset, memcpy, and memmove
1070 /// lowering. It returns MVT::iAny if SelectionDAG should be responsible for
1073 X86TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned Align,
1074 bool isSrcConst, bool isSrcStr,
1075 SelectionDAG &DAG) const {
1076 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
1077 // linux. This is because the stack realignment code can't handle certain
1078 // cases like PR2962. This should be removed when PR2962 is fixed.
1079 const Function *F = DAG.getMachineFunction().getFunction();
1080 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
1081 if (!NoImplicitFloatOps && Subtarget->getStackAlignment() >= 16) {
1082 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE2() && Size >= 16)
1084 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE1() && Size >= 16)
1087 if (Subtarget->is64Bit() && Size >= 8)
1092 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1093 /// current function. The returned value is a member of the
1094 /// MachineJumpTableInfo::JTEntryKind enum.
1095 unsigned X86TargetLowering::getJumpTableEncoding() const {
1096 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1098 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1099 Subtarget->isPICStyleGOT())
1100 return MachineJumpTableInfo::EK_Custom32;
1102 // Otherwise, use the normal jump table encoding heuristics.
1103 return TargetLowering::getJumpTableEncoding();
1106 /// getPICBaseSymbol - Return the X86-32 PIC base.
1108 X86TargetLowering::getPICBaseSymbol(const MachineFunction *MF,
1109 MCContext &Ctx) const {
1110 const MCAsmInfo &MAI = *getTargetMachine().getMCAsmInfo();
1111 return Ctx.GetOrCreateTemporarySymbol(Twine(MAI.getPrivateGlobalPrefix())+
1112 Twine(MF->getFunctionNumber())+"$pb");
1117 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1118 const MachineBasicBlock *MBB,
1119 unsigned uid,MCContext &Ctx) const{
1120 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1121 Subtarget->isPICStyleGOT());
1122 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1124 return X86MCTargetExpr::Create(MBB->getSymbol(),
1125 X86MCTargetExpr::GOTOFF, Ctx);
1128 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1130 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1131 SelectionDAG &DAG) const {
1132 if (!Subtarget->is64Bit())
1133 // This doesn't have DebugLoc associated with it, but is not really the
1134 // same as a Register.
1135 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc::getUnknownLoc(),
1140 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1141 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1143 const MCExpr *X86TargetLowering::
1144 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1145 MCContext &Ctx) const {
1146 // X86-64 uses RIP relative addressing based on the jump table label.
1147 if (Subtarget->isPICStyleRIPRel())
1148 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1150 // Otherwise, the reference is relative to the PIC base.
1151 return MCSymbolRefExpr::Create(getPICBaseSymbol(MF, Ctx), Ctx);
1154 /// getFunctionAlignment - Return the Log2 alignment of this function.
1155 unsigned X86TargetLowering::getFunctionAlignment(const Function *F) const {
1156 return F->hasFnAttr(Attribute::OptimizeForSize) ? 0 : 4;
1159 //===----------------------------------------------------------------------===//
1160 // Return Value Calling Convention Implementation
1161 //===----------------------------------------------------------------------===//
1163 #include "X86GenCallingConv.inc"
1166 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
1167 const SmallVectorImpl<EVT> &OutTys,
1168 const SmallVectorImpl<ISD::ArgFlagsTy> &ArgsFlags,
1169 SelectionDAG &DAG) {
1170 SmallVector<CCValAssign, 16> RVLocs;
1171 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1172 RVLocs, *DAG.getContext());
1173 return CCInfo.CheckReturn(OutTys, ArgsFlags, RetCC_X86);
1177 X86TargetLowering::LowerReturn(SDValue Chain,
1178 CallingConv::ID CallConv, bool isVarArg,
1179 const SmallVectorImpl<ISD::OutputArg> &Outs,
1180 DebugLoc dl, SelectionDAG &DAG) {
1182 SmallVector<CCValAssign, 16> RVLocs;
1183 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1184 RVLocs, *DAG.getContext());
1185 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1187 // Add the regs to the liveout set for the function.
1188 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1189 for (unsigned i = 0; i != RVLocs.size(); ++i)
1190 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg()))
1191 MRI.addLiveOut(RVLocs[i].getLocReg());
1195 SmallVector<SDValue, 6> RetOps;
1196 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1197 // Operand #1 = Bytes To Pop
1198 RetOps.push_back(DAG.getTargetConstant(getBytesToPopOnReturn(), MVT::i16));
1200 // Copy the result values into the output registers.
1201 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1202 CCValAssign &VA = RVLocs[i];
1203 assert(VA.isRegLoc() && "Can only return in registers!");
1204 SDValue ValToCopy = Outs[i].Val;
1206 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1207 // the RET instruction and handled by the FP Stackifier.
1208 if (VA.getLocReg() == X86::ST0 ||
1209 VA.getLocReg() == X86::ST1) {
1210 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1211 // change the value to the FP stack register class.
1212 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1213 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1214 RetOps.push_back(ValToCopy);
1215 // Don't emit a copytoreg.
1219 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1220 // which is returned in RAX / RDX.
1221 if (Subtarget->is64Bit()) {
1222 EVT ValVT = ValToCopy.getValueType();
1223 if (ValVT.isVector() && ValVT.getSizeInBits() == 64) {
1224 ValToCopy = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, ValToCopy);
1225 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1)
1226 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, ValToCopy);
1230 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1231 Flag = Chain.getValue(1);
1234 // The x86-64 ABI for returning structs by value requires that we copy
1235 // the sret argument into %rax for the return. We saved the argument into
1236 // a virtual register in the entry block, so now we copy the value out
1238 if (Subtarget->is64Bit() &&
1239 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1240 MachineFunction &MF = DAG.getMachineFunction();
1241 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1242 unsigned Reg = FuncInfo->getSRetReturnReg();
1244 Reg = MRI.createVirtualRegister(getRegClassFor(MVT::i64));
1245 FuncInfo->setSRetReturnReg(Reg);
1247 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1249 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
1250 Flag = Chain.getValue(1);
1252 // RAX now acts like a return value.
1253 MRI.addLiveOut(X86::RAX);
1256 RetOps[0] = Chain; // Update chain.
1258 // Add the flag if we have it.
1260 RetOps.push_back(Flag);
1262 return DAG.getNode(X86ISD::RET_FLAG, dl,
1263 MVT::Other, &RetOps[0], RetOps.size());
1266 /// LowerCallResult - Lower the result values of a call into the
1267 /// appropriate copies out of appropriate physical registers.
1270 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1271 CallingConv::ID CallConv, bool isVarArg,
1272 const SmallVectorImpl<ISD::InputArg> &Ins,
1273 DebugLoc dl, SelectionDAG &DAG,
1274 SmallVectorImpl<SDValue> &InVals) {
1276 // Assign locations to each value returned by this call.
1277 SmallVector<CCValAssign, 16> RVLocs;
1278 bool Is64Bit = Subtarget->is64Bit();
1279 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1280 RVLocs, *DAG.getContext());
1281 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1283 // Copy all of the result registers out of their specified physreg.
1284 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1285 CCValAssign &VA = RVLocs[i];
1286 EVT CopyVT = VA.getValVT();
1288 // If this is x86-64, and we disabled SSE, we can't return FP values
1289 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1290 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
1291 llvm_report_error("SSE register return with SSE disabled");
1294 // If this is a call to a function that returns an fp value on the floating
1295 // point stack, but where we prefer to use the value in xmm registers, copy
1296 // it out as F80 and use a truncate to move it from fp stack reg to xmm reg.
1297 if ((VA.getLocReg() == X86::ST0 ||
1298 VA.getLocReg() == X86::ST1) &&
1299 isScalarFPTypeInSSEReg(VA.getValVT())) {
1304 if (Is64Bit && CopyVT.isVector() && CopyVT.getSizeInBits() == 64) {
1305 // For x86-64, MMX values are returned in XMM0 / XMM1 except for v1i64.
1306 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1307 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1308 MVT::v2i64, InFlag).getValue(1);
1309 Val = Chain.getValue(0);
1310 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64,
1311 Val, DAG.getConstant(0, MVT::i64));
1313 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1314 MVT::i64, InFlag).getValue(1);
1315 Val = Chain.getValue(0);
1317 Val = DAG.getNode(ISD::BIT_CONVERT, dl, CopyVT, Val);
1319 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1320 CopyVT, InFlag).getValue(1);
1321 Val = Chain.getValue(0);
1323 InFlag = Chain.getValue(2);
1325 if (CopyVT != VA.getValVT()) {
1326 // Round the F80 the right size, which also moves to the appropriate xmm
1328 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1329 // This truncation won't change the value.
1330 DAG.getIntPtrConstant(1));
1333 InVals.push_back(Val);
1340 //===----------------------------------------------------------------------===//
1341 // C & StdCall & Fast Calling Convention implementation
1342 //===----------------------------------------------------------------------===//
1343 // StdCall calling convention seems to be standard for many Windows' API
1344 // routines and around. It differs from C calling convention just a little:
1345 // callee should clean up the stack, not caller. Symbols should be also
1346 // decorated in some fancy way :) It doesn't support any vector arguments.
1347 // For info on fast calling convention see Fast Calling Convention (tail call)
1348 // implementation LowerX86_32FastCCCallTo.
1350 /// CallIsStructReturn - Determines whether a call uses struct return
1352 static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1356 return Outs[0].Flags.isSRet();
1359 /// ArgsAreStructReturn - Determines whether a function uses struct
1360 /// return semantics.
1362 ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
1366 return Ins[0].Flags.isSRet();
1369 /// IsCalleePop - Determines whether the callee is required to pop its
1370 /// own arguments. Callee pop is necessary to support tail calls.
1371 bool X86TargetLowering::IsCalleePop(bool IsVarArg, CallingConv::ID CallingConv){
1375 switch (CallingConv) {
1378 case CallingConv::X86_StdCall:
1379 return !Subtarget->is64Bit();
1380 case CallingConv::X86_FastCall:
1381 return !Subtarget->is64Bit();
1382 case CallingConv::Fast:
1383 return GuaranteedTailCallOpt;
1384 case CallingConv::GHC:
1385 return GuaranteedTailCallOpt;
1389 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the
1390 /// given CallingConvention value.
1391 CCAssignFn *X86TargetLowering::CCAssignFnForNode(CallingConv::ID CC) const {
1392 if (Subtarget->is64Bit()) {
1393 if (CC == CallingConv::GHC)
1394 return CC_X86_64_GHC;
1395 else if (Subtarget->isTargetWin64())
1396 return CC_X86_Win64_C;
1401 if (CC == CallingConv::X86_FastCall)
1402 return CC_X86_32_FastCall;
1403 else if (CC == CallingConv::Fast)
1404 return CC_X86_32_FastCC;
1405 else if (CC == CallingConv::GHC)
1406 return CC_X86_32_GHC;
1411 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1412 /// by "Src" to address "Dst" with size and alignment information specified by
1413 /// the specific parameter attribute. The copy will be passed as a byval
1414 /// function parameter.
1416 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1417 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1419 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1420 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1421 /*AlwaysInline=*/true, NULL, 0, NULL, 0);
1424 /// IsTailCallConvention - Return true if the calling convention is one that
1425 /// supports tail call optimization.
1426 static bool IsTailCallConvention(CallingConv::ID CC) {
1427 return (CC == CallingConv::Fast || CC == CallingConv::GHC);
1430 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
1431 /// a tailcall target by changing its ABI.
1432 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC) {
1433 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
1437 X86TargetLowering::LowerMemArgument(SDValue Chain,
1438 CallingConv::ID CallConv,
1439 const SmallVectorImpl<ISD::InputArg> &Ins,
1440 DebugLoc dl, SelectionDAG &DAG,
1441 const CCValAssign &VA,
1442 MachineFrameInfo *MFI,
1444 // Create the nodes corresponding to a load from this parameter slot.
1445 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1446 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv);
1447 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1450 // If value is passed by pointer we have address passed instead of the value
1452 if (VA.getLocInfo() == CCValAssign::Indirect)
1453 ValVT = VA.getLocVT();
1455 ValVT = VA.getValVT();
1457 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1458 // changed with more analysis.
1459 // In case of tail call optimization mark all arguments mutable. Since they
1460 // could be overwritten by lowering of arguments in case of a tail call.
1461 if (Flags.isByVal()) {
1462 int FI = MFI->CreateFixedObject(Flags.getByValSize(),
1463 VA.getLocMemOffset(), isImmutable, false);
1464 return DAG.getFrameIndex(FI, getPointerTy());
1466 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
1467 VA.getLocMemOffset(), isImmutable, false);
1468 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1469 return DAG.getLoad(ValVT, dl, Chain, FIN,
1470 PseudoSourceValue::getFixedStack(FI), 0,
1476 X86TargetLowering::LowerFormalArguments(SDValue Chain,
1477 CallingConv::ID CallConv,
1479 const SmallVectorImpl<ISD::InputArg> &Ins,
1482 SmallVectorImpl<SDValue> &InVals) {
1483 MachineFunction &MF = DAG.getMachineFunction();
1484 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1486 const Function* Fn = MF.getFunction();
1487 if (Fn->hasExternalLinkage() &&
1488 Subtarget->isTargetCygMing() &&
1489 Fn->getName() == "main")
1490 FuncInfo->setForceFramePointer(true);
1492 MachineFrameInfo *MFI = MF.getFrameInfo();
1493 bool Is64Bit = Subtarget->is64Bit();
1494 bool IsWin64 = Subtarget->isTargetWin64();
1496 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1497 "Var args not supported with calling convention fastcc or ghc");
1499 // Assign locations to all of the incoming arguments.
1500 SmallVector<CCValAssign, 16> ArgLocs;
1501 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1502 ArgLocs, *DAG.getContext());
1503 CCInfo.AnalyzeFormalArguments(Ins, CCAssignFnForNode(CallConv));
1505 unsigned LastVal = ~0U;
1507 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1508 CCValAssign &VA = ArgLocs[i];
1509 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1511 assert(VA.getValNo() != LastVal &&
1512 "Don't support value assigned to multiple locs yet");
1513 LastVal = VA.getValNo();
1515 if (VA.isRegLoc()) {
1516 EVT RegVT = VA.getLocVT();
1517 TargetRegisterClass *RC = NULL;
1518 if (RegVT == MVT::i32)
1519 RC = X86::GR32RegisterClass;
1520 else if (Is64Bit && RegVT == MVT::i64)
1521 RC = X86::GR64RegisterClass;
1522 else if (RegVT == MVT::f32)
1523 RC = X86::FR32RegisterClass;
1524 else if (RegVT == MVT::f64)
1525 RC = X86::FR64RegisterClass;
1526 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1527 RC = X86::VR128RegisterClass;
1528 else if (RegVT.isVector() && RegVT.getSizeInBits() == 64)
1529 RC = X86::VR64RegisterClass;
1531 llvm_unreachable("Unknown argument type!");
1533 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1534 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1536 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1537 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1539 if (VA.getLocInfo() == CCValAssign::SExt)
1540 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1541 DAG.getValueType(VA.getValVT()));
1542 else if (VA.getLocInfo() == CCValAssign::ZExt)
1543 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1544 DAG.getValueType(VA.getValVT()));
1545 else if (VA.getLocInfo() == CCValAssign::BCvt)
1546 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
1548 if (VA.isExtInLoc()) {
1549 // Handle MMX values passed in XMM regs.
1550 if (RegVT.isVector()) {
1551 ArgValue = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64,
1552 ArgValue, DAG.getConstant(0, MVT::i64));
1553 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
1555 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1558 assert(VA.isMemLoc());
1559 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
1562 // If value is passed via pointer - do a load.
1563 if (VA.getLocInfo() == CCValAssign::Indirect)
1564 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue, NULL, 0,
1567 InVals.push_back(ArgValue);
1570 // The x86-64 ABI for returning structs by value requires that we copy
1571 // the sret argument into %rax for the return. Save the argument into
1572 // a virtual register so that we can access it from the return points.
1573 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) {
1574 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1575 unsigned Reg = FuncInfo->getSRetReturnReg();
1577 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1578 FuncInfo->setSRetReturnReg(Reg);
1580 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1581 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1584 unsigned StackSize = CCInfo.getNextStackOffset();
1585 // Align stack specially for tail calls.
1586 if (FuncIsMadeTailCallSafe(CallConv))
1587 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1589 // If the function takes variable number of arguments, make a frame index for
1590 // the start of the first vararg value... for expansion of llvm.va_start.
1592 if (Is64Bit || CallConv != CallingConv::X86_FastCall) {
1593 VarArgsFrameIndex = MFI->CreateFixedObject(1, StackSize, true, false);
1596 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1598 // FIXME: We should really autogenerate these arrays
1599 static const unsigned GPR64ArgRegsWin64[] = {
1600 X86::RCX, X86::RDX, X86::R8, X86::R9
1602 static const unsigned XMMArgRegsWin64[] = {
1603 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
1605 static const unsigned GPR64ArgRegs64Bit[] = {
1606 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1608 static const unsigned XMMArgRegs64Bit[] = {
1609 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1610 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1612 const unsigned *GPR64ArgRegs, *XMMArgRegs;
1615 TotalNumIntRegs = 4; TotalNumXMMRegs = 4;
1616 GPR64ArgRegs = GPR64ArgRegsWin64;
1617 XMMArgRegs = XMMArgRegsWin64;
1619 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1620 GPR64ArgRegs = GPR64ArgRegs64Bit;
1621 XMMArgRegs = XMMArgRegs64Bit;
1623 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1625 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs,
1628 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat);
1629 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
1630 "SSE register cannot be used when SSE is disabled!");
1631 assert(!(NumXMMRegs && UseSoftFloat && NoImplicitFloatOps) &&
1632 "SSE register cannot be used when SSE is disabled!");
1633 if (UseSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1())
1634 // Kernel mode asks for SSE to be disabled, so don't push them
1636 TotalNumXMMRegs = 0;
1638 // For X86-64, if there are vararg parameters that are passed via
1639 // registers, then we must store them to their spots on the stack so they
1640 // may be loaded by deferencing the result of va_next.
1641 VarArgsGPOffset = NumIntRegs * 8;
1642 VarArgsFPOffset = TotalNumIntRegs * 8 + NumXMMRegs * 16;
1643 RegSaveFrameIndex = MFI->CreateStackObject(TotalNumIntRegs * 8 +
1644 TotalNumXMMRegs * 16, 16,
1647 // Store the integer parameter registers.
1648 SmallVector<SDValue, 8> MemOps;
1649 SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
1650 unsigned Offset = VarArgsGPOffset;
1651 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
1652 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
1653 DAG.getIntPtrConstant(Offset));
1654 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
1655 X86::GR64RegisterClass);
1656 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
1658 DAG.getStore(Val.getValue(1), dl, Val, FIN,
1659 PseudoSourceValue::getFixedStack(RegSaveFrameIndex),
1660 Offset, false, false, 0);
1661 MemOps.push_back(Store);
1665 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
1666 // Now store the XMM (fp + vector) parameter registers.
1667 SmallVector<SDValue, 11> SaveXMMOps;
1668 SaveXMMOps.push_back(Chain);
1670 unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass);
1671 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
1672 SaveXMMOps.push_back(ALVal);
1674 SaveXMMOps.push_back(DAG.getIntPtrConstant(RegSaveFrameIndex));
1675 SaveXMMOps.push_back(DAG.getIntPtrConstant(VarArgsFPOffset));
1677 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
1678 unsigned VReg = MF.addLiveIn(XMMArgRegs[NumXMMRegs],
1679 X86::VR128RegisterClass);
1680 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
1681 SaveXMMOps.push_back(Val);
1683 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
1685 &SaveXMMOps[0], SaveXMMOps.size()));
1688 if (!MemOps.empty())
1689 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1690 &MemOps[0], MemOps.size());
1694 // Some CCs need callee pop.
1695 if (IsCalleePop(isVarArg, CallConv)) {
1696 BytesToPopOnReturn = StackSize; // Callee pops everything.
1698 BytesToPopOnReturn = 0; // Callee pops nothing.
1699 // If this is an sret function, the return should pop the hidden pointer.
1700 if (!Is64Bit && !IsTailCallConvention(CallConv) && ArgsAreStructReturn(Ins))
1701 BytesToPopOnReturn = 4;
1705 RegSaveFrameIndex = 0xAAAAAAA; // RegSaveFrameIndex is X86-64 only.
1706 if (CallConv == CallingConv::X86_FastCall)
1707 VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs.
1710 FuncInfo->setBytesToPopOnReturn(BytesToPopOnReturn);
1716 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
1717 SDValue StackPtr, SDValue Arg,
1718 DebugLoc dl, SelectionDAG &DAG,
1719 const CCValAssign &VA,
1720 ISD::ArgFlagsTy Flags) {
1721 const unsigned FirstStackArgOffset = (Subtarget->isTargetWin64() ? 32 : 0);
1722 unsigned LocMemOffset = FirstStackArgOffset + VA.getLocMemOffset();
1723 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1724 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1725 if (Flags.isByVal()) {
1726 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
1728 return DAG.getStore(Chain, dl, Arg, PtrOff,
1729 PseudoSourceValue::getStack(), LocMemOffset,
1733 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
1734 /// optimization is performed and it is required.
1736 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
1737 SDValue &OutRetAddr, SDValue Chain,
1738 bool IsTailCall, bool Is64Bit,
1739 int FPDiff, DebugLoc dl) {
1740 // Adjust the Return address stack slot.
1741 EVT VT = getPointerTy();
1742 OutRetAddr = getReturnAddressFrameIndex(DAG);
1744 // Load the "old" Return address.
1745 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, NULL, 0, false, false, 0);
1746 return SDValue(OutRetAddr.getNode(), 1);
1749 /// EmitTailCallStoreRetAddr - Emit a store of the return adress if tail call
1750 /// optimization is performed and it is required (FPDiff!=0).
1752 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
1753 SDValue Chain, SDValue RetAddrFrIdx,
1754 bool Is64Bit, int FPDiff, DebugLoc dl) {
1755 // Store the return address to the appropriate stack slot.
1756 if (!FPDiff) return Chain;
1757 // Calculate the new stack slot for the return address.
1758 int SlotSize = Is64Bit ? 8 : 4;
1759 int NewReturnAddrFI =
1760 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false, false);
1761 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
1762 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
1763 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
1764 PseudoSourceValue::getFixedStack(NewReturnAddrFI), 0,
1770 X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
1771 CallingConv::ID CallConv, bool isVarArg,
1773 const SmallVectorImpl<ISD::OutputArg> &Outs,
1774 const SmallVectorImpl<ISD::InputArg> &Ins,
1775 DebugLoc dl, SelectionDAG &DAG,
1776 SmallVectorImpl<SDValue> &InVals) {
1777 MachineFunction &MF = DAG.getMachineFunction();
1778 bool Is64Bit = Subtarget->is64Bit();
1779 bool IsStructRet = CallIsStructReturn(Outs);
1780 bool IsSibcall = false;
1783 // Check if it's really possible to do a tail call.
1784 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
1785 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
1788 // Sibcalls are automatically detected tailcalls which do not require
1790 if (!GuaranteedTailCallOpt && isTailCall)
1797 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1798 "Var args not supported with calling convention fastcc or ghc");
1800 // Analyze operands of the call, assigning locations to each operand.
1801 SmallVector<CCValAssign, 16> ArgLocs;
1802 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1803 ArgLocs, *DAG.getContext());
1804 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CallConv));
1806 // Get a count of how many bytes are to be pushed on the stack.
1807 unsigned NumBytes = CCInfo.getNextStackOffset();
1809 // This is a sibcall. The memory operands are available in caller's
1810 // own caller's stack.
1812 else if (GuaranteedTailCallOpt && IsTailCallConvention(CallConv))
1813 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
1816 if (isTailCall && !IsSibcall) {
1817 // Lower arguments at fp - stackoffset + fpdiff.
1818 unsigned NumBytesCallerPushed =
1819 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
1820 FPDiff = NumBytesCallerPushed - NumBytes;
1822 // Set the delta of movement of the returnaddr stackslot.
1823 // But only set if delta is greater than previous delta.
1824 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
1825 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
1829 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
1831 SDValue RetAddrFrIdx;
1832 // Load return adress for tail calls.
1833 if (isTailCall && FPDiff)
1834 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
1835 Is64Bit, FPDiff, dl);
1837 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
1838 SmallVector<SDValue, 8> MemOpChains;
1841 // Walk the register/memloc assignments, inserting copies/loads. In the case
1842 // of tail call optimization arguments are handle later.
1843 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1844 CCValAssign &VA = ArgLocs[i];
1845 EVT RegVT = VA.getLocVT();
1846 SDValue Arg = Outs[i].Val;
1847 ISD::ArgFlagsTy Flags = Outs[i].Flags;
1848 bool isByVal = Flags.isByVal();
1850 // Promote the value if needed.
1851 switch (VA.getLocInfo()) {
1852 default: llvm_unreachable("Unknown loc info!");
1853 case CCValAssign::Full: break;
1854 case CCValAssign::SExt:
1855 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
1857 case CCValAssign::ZExt:
1858 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
1860 case CCValAssign::AExt:
1861 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) {
1862 // Special case: passing MMX values in XMM registers.
1863 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, Arg);
1864 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
1865 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
1867 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
1869 case CCValAssign::BCvt:
1870 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, RegVT, Arg);
1872 case CCValAssign::Indirect: {
1873 // Store the argument.
1874 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
1875 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
1876 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
1877 PseudoSourceValue::getFixedStack(FI), 0,
1884 if (VA.isRegLoc()) {
1885 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1886 } else if (!IsSibcall && (!isTailCall || isByVal)) {
1887 assert(VA.isMemLoc());
1888 if (StackPtr.getNode() == 0)
1889 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
1890 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
1891 dl, DAG, VA, Flags));
1895 if (!MemOpChains.empty())
1896 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1897 &MemOpChains[0], MemOpChains.size());
1899 // Build a sequence of copy-to-reg nodes chained together with token chain
1900 // and flag operands which copy the outgoing args into registers.
1902 // Tail call byval lowering might overwrite argument registers so in case of
1903 // tail call optimization the copies to registers are lowered later.
1905 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1906 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1907 RegsToPass[i].second, InFlag);
1908 InFlag = Chain.getValue(1);
1911 if (Subtarget->isPICStyleGOT()) {
1912 // ELF / PIC requires GOT in the EBX register before function calls via PLT
1915 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX,
1916 DAG.getNode(X86ISD::GlobalBaseReg,
1917 DebugLoc::getUnknownLoc(),
1920 InFlag = Chain.getValue(1);
1922 // If we are tail calling and generating PIC/GOT style code load the
1923 // address of the callee into ECX. The value in ecx is used as target of
1924 // the tail jump. This is done to circumvent the ebx/callee-saved problem
1925 // for tail calls on PIC/GOT architectures. Normally we would just put the
1926 // address of GOT into ebx and then call target@PLT. But for tail calls
1927 // ebx would be restored (since ebx is callee saved) before jumping to the
1930 // Note: The actual moving to ECX is done further down.
1931 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
1932 if (G && !G->getGlobal()->hasHiddenVisibility() &&
1933 !G->getGlobal()->hasProtectedVisibility())
1934 Callee = LowerGlobalAddress(Callee, DAG);
1935 else if (isa<ExternalSymbolSDNode>(Callee))
1936 Callee = LowerExternalSymbol(Callee, DAG);
1940 if (Is64Bit && isVarArg) {
1941 // From AMD64 ABI document:
1942 // For calls that may call functions that use varargs or stdargs
1943 // (prototype-less calls or calls to functions containing ellipsis (...) in
1944 // the declaration) %al is used as hidden argument to specify the number
1945 // of SSE registers used. The contents of %al do not need to match exactly
1946 // the number of registers, but must be an ubound on the number of SSE
1947 // registers used and is in the range 0 - 8 inclusive.
1949 // FIXME: Verify this on Win64
1950 // Count the number of XMM registers allocated.
1951 static const unsigned XMMArgRegs[] = {
1952 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1953 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1955 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
1956 assert((Subtarget->hasSSE1() || !NumXMMRegs)
1957 && "SSE registers cannot be used when SSE is disabled");
1959 Chain = DAG.getCopyToReg(Chain, dl, X86::AL,
1960 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
1961 InFlag = Chain.getValue(1);
1965 // For tail calls lower the arguments to the 'real' stack slot.
1967 // Force all the incoming stack arguments to be loaded from the stack
1968 // before any new outgoing arguments are stored to the stack, because the
1969 // outgoing stack slots may alias the incoming argument stack slots, and
1970 // the alias isn't otherwise explicit. This is slightly more conservative
1971 // than necessary, because it means that each store effectively depends
1972 // on every argument instead of just those arguments it would clobber.
1973 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
1975 SmallVector<SDValue, 8> MemOpChains2;
1978 // Do not flag preceeding copytoreg stuff together with the following stuff.
1980 if (GuaranteedTailCallOpt) {
1981 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1982 CCValAssign &VA = ArgLocs[i];
1985 assert(VA.isMemLoc());
1986 SDValue Arg = Outs[i].Val;
1987 ISD::ArgFlagsTy Flags = Outs[i].Flags;
1988 // Create frame index.
1989 int32_t Offset = VA.getLocMemOffset()+FPDiff;
1990 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
1991 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true, false);
1992 FIN = DAG.getFrameIndex(FI, getPointerTy());
1994 if (Flags.isByVal()) {
1995 // Copy relative to framepointer.
1996 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
1997 if (StackPtr.getNode() == 0)
1998 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
2000 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2002 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2006 // Store relative to framepointer.
2007 MemOpChains2.push_back(
2008 DAG.getStore(ArgChain, dl, Arg, FIN,
2009 PseudoSourceValue::getFixedStack(FI), 0,
2015 if (!MemOpChains2.empty())
2016 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2017 &MemOpChains2[0], MemOpChains2.size());
2019 // Copy arguments to their registers.
2020 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2021 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2022 RegsToPass[i].second, InFlag);
2023 InFlag = Chain.getValue(1);
2027 // Store the return address to the appropriate stack slot.
2028 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
2032 bool WasGlobalOrExternal = false;
2033 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2034 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2035 // In the 64-bit large code model, we have to make all calls
2036 // through a register, since the call instruction's 32-bit
2037 // pc-relative offset may not be large enough to hold the whole
2039 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2040 WasGlobalOrExternal = true;
2041 // If the callee is a GlobalAddress node (quite common, every direct call
2042 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2045 // We should use extra load for direct calls to dllimported functions in
2047 GlobalValue *GV = G->getGlobal();
2048 if (!GV->hasDLLImportLinkage()) {
2049 unsigned char OpFlags = 0;
2051 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2052 // external symbols most go through the PLT in PIC mode. If the symbol
2053 // has hidden or protected visibility, or if it is static or local, then
2054 // we don't need to use the PLT - we can directly call it.
2055 if (Subtarget->isTargetELF() &&
2056 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2057 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2058 OpFlags = X86II::MO_PLT;
2059 } else if (Subtarget->isPICStyleStubAny() &&
2060 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2061 Subtarget->getDarwinVers() < 9) {
2062 // PC-relative references to external symbols should go through $stub,
2063 // unless we're building with the leopard linker or later, which
2064 // automatically synthesizes these stubs.
2065 OpFlags = X86II::MO_DARWIN_STUB;
2068 Callee = DAG.getTargetGlobalAddress(GV, getPointerTy(),
2069 G->getOffset(), OpFlags);
2071 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2072 WasGlobalOrExternal = true;
2073 unsigned char OpFlags = 0;
2075 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to external
2076 // symbols should go through the PLT.
2077 if (Subtarget->isTargetELF() &&
2078 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2079 OpFlags = X86II::MO_PLT;
2080 } else if (Subtarget->isPICStyleStubAny() &&
2081 Subtarget->getDarwinVers() < 9) {
2082 // PC-relative references to external symbols should go through $stub,
2083 // unless we're building with the leopard linker or later, which
2084 // automatically synthesizes these stubs.
2085 OpFlags = X86II::MO_DARWIN_STUB;
2088 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2092 // Returns a chain & a flag for retval copy to use.
2093 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
2094 SmallVector<SDValue, 8> Ops;
2096 if (!IsSibcall && isTailCall) {
2097 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2098 DAG.getIntPtrConstant(0, true), InFlag);
2099 InFlag = Chain.getValue(1);
2102 Ops.push_back(Chain);
2103 Ops.push_back(Callee);
2106 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2108 // Add argument registers to the end of the list so that they are known live
2110 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2111 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2112 RegsToPass[i].second.getValueType()));
2114 // Add an implicit use GOT pointer in EBX.
2115 if (!isTailCall && Subtarget->isPICStyleGOT())
2116 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
2118 // Add an implicit use of AL for x86 vararg functions.
2119 if (Is64Bit && isVarArg)
2120 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
2122 if (InFlag.getNode())
2123 Ops.push_back(InFlag);
2126 // If this is the first return lowered for this function, add the regs
2127 // to the liveout set for the function.
2128 if (MF.getRegInfo().liveout_empty()) {
2129 SmallVector<CCValAssign, 16> RVLocs;
2130 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs,
2132 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2133 for (unsigned i = 0; i != RVLocs.size(); ++i)
2134 if (RVLocs[i].isRegLoc())
2135 MF.getRegInfo().addLiveOut(RVLocs[i].getLocReg());
2137 return DAG.getNode(X86ISD::TC_RETURN, dl,
2138 NodeTys, &Ops[0], Ops.size());
2141 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2142 InFlag = Chain.getValue(1);
2144 // Create the CALLSEQ_END node.
2145 unsigned NumBytesForCalleeToPush;
2146 if (IsCalleePop(isVarArg, CallConv))
2147 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2148 else if (!Is64Bit && !IsTailCallConvention(CallConv) && IsStructRet)
2149 // If this is a call to a struct-return function, the callee
2150 // pops the hidden struct pointer, so we have to push it back.
2151 // This is common for Darwin/X86, Linux & Mingw32 targets.
2152 NumBytesForCalleeToPush = 4;
2154 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2156 // Returns a flag for retval copy to use.
2158 Chain = DAG.getCALLSEQ_END(Chain,
2159 DAG.getIntPtrConstant(NumBytes, true),
2160 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2163 InFlag = Chain.getValue(1);
2166 // Handle result values, copying them out of physregs into vregs that we
2168 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2169 Ins, dl, DAG, InVals);
2173 //===----------------------------------------------------------------------===//
2174 // Fast Calling Convention (tail call) implementation
2175 //===----------------------------------------------------------------------===//
2177 // Like std call, callee cleans arguments, convention except that ECX is
2178 // reserved for storing the tail called function address. Only 2 registers are
2179 // free for argument passing (inreg). Tail call optimization is performed
2181 // * tailcallopt is enabled
2182 // * caller/callee are fastcc
2183 // On X86_64 architecture with GOT-style position independent code only local
2184 // (within module) calls are supported at the moment.
2185 // To keep the stack aligned according to platform abi the function
2186 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2187 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2188 // If a tail called function callee has more arguments than the caller the
2189 // caller needs to make sure that there is room to move the RETADDR to. This is
2190 // achieved by reserving an area the size of the argument delta right after the
2191 // original REtADDR, but before the saved framepointer or the spilled registers
2192 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2204 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2205 /// for a 16 byte align requirement.
2206 unsigned X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2207 SelectionDAG& DAG) {
2208 MachineFunction &MF = DAG.getMachineFunction();
2209 const TargetMachine &TM = MF.getTarget();
2210 const TargetFrameInfo &TFI = *TM.getFrameInfo();
2211 unsigned StackAlignment = TFI.getStackAlignment();
2212 uint64_t AlignMask = StackAlignment - 1;
2213 int64_t Offset = StackSize;
2214 uint64_t SlotSize = TD->getPointerSize();
2215 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2216 // Number smaller than 12 so just add the difference.
2217 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2219 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2220 Offset = ((~AlignMask) & Offset) + StackAlignment +
2221 (StackAlignment-SlotSize);
2226 /// MatchingStackOffset - Return true if the given stack call argument is
2227 /// already available in the same position (relatively) of the caller's
2228 /// incoming argument stack.
2230 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2231 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2232 const X86InstrInfo *TII) {
2233 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
2235 if (Arg.getOpcode() == ISD::CopyFromReg) {
2236 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2237 if (!VR || TargetRegisterInfo::isPhysicalRegister(VR))
2239 MachineInstr *Def = MRI->getVRegDef(VR);
2242 if (!Flags.isByVal()) {
2243 if (!TII->isLoadFromStackSlot(Def, FI))
2246 unsigned Opcode = Def->getOpcode();
2247 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
2248 Def->getOperand(1).isFI()) {
2249 FI = Def->getOperand(1).getIndex();
2250 Bytes = Flags.getByValSize();
2254 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2255 if (Flags.isByVal())
2256 // ByVal argument is passed in as a pointer but it's now being
2257 // dereferenced. e.g.
2258 // define @foo(%struct.X* %A) {
2259 // tail call @bar(%struct.X* byval %A)
2262 SDValue Ptr = Ld->getBasePtr();
2263 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2266 FI = FINode->getIndex();
2270 assert(FI != INT_MAX);
2271 if (!MFI->isFixedObjectIndex(FI))
2273 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
2276 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2277 /// for tail call optimization. Targets which want to do tail call
2278 /// optimization should implement this function.
2280 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2281 CallingConv::ID CalleeCC,
2283 bool isCalleeStructRet,
2284 bool isCallerStructRet,
2285 const SmallVectorImpl<ISD::OutputArg> &Outs,
2286 const SmallVectorImpl<ISD::InputArg> &Ins,
2287 SelectionDAG& DAG) const {
2288 if (!IsTailCallConvention(CalleeCC) &&
2289 CalleeCC != CallingConv::C)
2292 // If -tailcallopt is specified, make fastcc functions tail-callable.
2293 const Function *CallerF = DAG.getMachineFunction().getFunction();
2294 if (GuaranteedTailCallOpt) {
2295 if (IsTailCallConvention(CalleeCC) &&
2296 CallerF->getCallingConv() == CalleeCC)
2301 // Look for obvious safe cases to perform tail call optimization that does not
2302 // requite ABI changes. This is what gcc calls sibcall.
2304 // Do not sibcall optimize vararg calls for now.
2308 // Also avoid sibcall optimization if either caller or callee uses struct
2309 // return semantics.
2310 if (isCalleeStructRet || isCallerStructRet)
2313 // If the callee takes no arguments then go on to check the results of the
2315 if (!Outs.empty()) {
2316 // Check if stack adjustment is needed. For now, do not do this if any
2317 // argument is passed on the stack.
2318 SmallVector<CCValAssign, 16> ArgLocs;
2319 CCState CCInfo(CalleeCC, isVarArg, getTargetMachine(),
2320 ArgLocs, *DAG.getContext());
2321 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CalleeCC));
2322 if (CCInfo.getNextStackOffset()) {
2323 MachineFunction &MF = DAG.getMachineFunction();
2324 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
2326 if (Subtarget->isTargetWin64())
2327 // Win64 ABI has additional complications.
2330 // Check if the arguments are already laid out in the right way as
2331 // the caller's fixed stack objects.
2332 MachineFrameInfo *MFI = MF.getFrameInfo();
2333 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2334 const X86InstrInfo *TII =
2335 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
2336 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2337 CCValAssign &VA = ArgLocs[i];
2338 EVT RegVT = VA.getLocVT();
2339 SDValue Arg = Outs[i].Val;
2340 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2341 if (VA.getLocInfo() == CCValAssign::Indirect)
2343 if (!VA.isRegLoc()) {
2344 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2356 X86TargetLowering::createFastISel(MachineFunction &mf, MachineModuleInfo *mmo,
2358 DenseMap<const Value *, unsigned> &vm,
2359 DenseMap<const BasicBlock*, MachineBasicBlock*> &bm,
2360 DenseMap<const AllocaInst *, int> &am
2362 , SmallSet<Instruction*, 8> &cil
2365 return X86::createFastISel(mf, mmo, dw, vm, bm, am
2373 //===----------------------------------------------------------------------===//
2374 // Other Lowering Hooks
2375 //===----------------------------------------------------------------------===//
2378 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) {
2379 MachineFunction &MF = DAG.getMachineFunction();
2380 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2381 int ReturnAddrIndex = FuncInfo->getRAIndex();
2383 if (ReturnAddrIndex == 0) {
2384 // Set up a frame object for the return address.
2385 uint64_t SlotSize = TD->getPointerSize();
2386 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
2388 FuncInfo->setRAIndex(ReturnAddrIndex);
2391 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
2395 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
2396 bool hasSymbolicDisplacement) {
2397 // Offset should fit into 32 bit immediate field.
2398 if (!isInt32(Offset))
2401 // If we don't have a symbolic displacement - we don't have any extra
2403 if (!hasSymbolicDisplacement)
2406 // FIXME: Some tweaks might be needed for medium code model.
2407 if (M != CodeModel::Small && M != CodeModel::Kernel)
2410 // For small code model we assume that latest object is 16MB before end of 31
2411 // bits boundary. We may also accept pretty large negative constants knowing
2412 // that all objects are in the positive half of address space.
2413 if (M == CodeModel::Small && Offset < 16*1024*1024)
2416 // For kernel code model we know that all object resist in the negative half
2417 // of 32bits address space. We may not accept negative offsets, since they may
2418 // be just off and we may accept pretty large positive ones.
2419 if (M == CodeModel::Kernel && Offset > 0)
2425 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
2426 /// specific condition code, returning the condition code and the LHS/RHS of the
2427 /// comparison to make.
2428 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
2429 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
2431 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
2432 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
2433 // X > -1 -> X == 0, jump !sign.
2434 RHS = DAG.getConstant(0, RHS.getValueType());
2435 return X86::COND_NS;
2436 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
2437 // X < 0 -> X == 0, jump on sign.
2439 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
2441 RHS = DAG.getConstant(0, RHS.getValueType());
2442 return X86::COND_LE;
2446 switch (SetCCOpcode) {
2447 default: llvm_unreachable("Invalid integer condition!");
2448 case ISD::SETEQ: return X86::COND_E;
2449 case ISD::SETGT: return X86::COND_G;
2450 case ISD::SETGE: return X86::COND_GE;
2451 case ISD::SETLT: return X86::COND_L;
2452 case ISD::SETLE: return X86::COND_LE;
2453 case ISD::SETNE: return X86::COND_NE;
2454 case ISD::SETULT: return X86::COND_B;
2455 case ISD::SETUGT: return X86::COND_A;
2456 case ISD::SETULE: return X86::COND_BE;
2457 case ISD::SETUGE: return X86::COND_AE;
2461 // First determine if it is required or is profitable to flip the operands.
2463 // If LHS is a foldable load, but RHS is not, flip the condition.
2464 if ((ISD::isNON_EXTLoad(LHS.getNode()) && LHS.hasOneUse()) &&
2465 !(ISD::isNON_EXTLoad(RHS.getNode()) && RHS.hasOneUse())) {
2466 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
2467 std::swap(LHS, RHS);
2470 switch (SetCCOpcode) {
2476 std::swap(LHS, RHS);
2480 // On a floating point condition, the flags are set as follows:
2482 // 0 | 0 | 0 | X > Y
2483 // 0 | 0 | 1 | X < Y
2484 // 1 | 0 | 0 | X == Y
2485 // 1 | 1 | 1 | unordered
2486 switch (SetCCOpcode) {
2487 default: llvm_unreachable("Condcode should be pre-legalized away");
2489 case ISD::SETEQ: return X86::COND_E;
2490 case ISD::SETOLT: // flipped
2492 case ISD::SETGT: return X86::COND_A;
2493 case ISD::SETOLE: // flipped
2495 case ISD::SETGE: return X86::COND_AE;
2496 case ISD::SETUGT: // flipped
2498 case ISD::SETLT: return X86::COND_B;
2499 case ISD::SETUGE: // flipped
2501 case ISD::SETLE: return X86::COND_BE;
2503 case ISD::SETNE: return X86::COND_NE;
2504 case ISD::SETUO: return X86::COND_P;
2505 case ISD::SETO: return X86::COND_NP;
2507 case ISD::SETUNE: return X86::COND_INVALID;
2511 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
2512 /// code. Current x86 isa includes the following FP cmov instructions:
2513 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
2514 static bool hasFPCMov(unsigned X86CC) {
2530 /// isFPImmLegal - Returns true if the target can instruction select the
2531 /// specified FP immediate natively. If false, the legalizer will
2532 /// materialize the FP immediate as a load from a constant pool.
2533 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
2534 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
2535 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
2541 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
2542 /// the specified range (L, H].
2543 static bool isUndefOrInRange(int Val, int Low, int Hi) {
2544 return (Val < 0) || (Val >= Low && Val < Hi);
2547 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
2548 /// specified value.
2549 static bool isUndefOrEqual(int Val, int CmpVal) {
2550 if (Val < 0 || Val == CmpVal)
2555 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
2556 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
2557 /// the second operand.
2558 static bool isPSHUFDMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2559 if (VT == MVT::v4f32 || VT == MVT::v4i32 || VT == MVT::v4i16)
2560 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
2561 if (VT == MVT::v2f64 || VT == MVT::v2i64)
2562 return (Mask[0] < 2 && Mask[1] < 2);
2566 bool X86::isPSHUFDMask(ShuffleVectorSDNode *N) {
2567 SmallVector<int, 8> M;
2569 return ::isPSHUFDMask(M, N->getValueType(0));
2572 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
2573 /// is suitable for input to PSHUFHW.
2574 static bool isPSHUFHWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2575 if (VT != MVT::v8i16)
2578 // Lower quadword copied in order or undef.
2579 for (int i = 0; i != 4; ++i)
2580 if (Mask[i] >= 0 && Mask[i] != i)
2583 // Upper quadword shuffled.
2584 for (int i = 4; i != 8; ++i)
2585 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7))
2591 bool X86::isPSHUFHWMask(ShuffleVectorSDNode *N) {
2592 SmallVector<int, 8> M;
2594 return ::isPSHUFHWMask(M, N->getValueType(0));
2597 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
2598 /// is suitable for input to PSHUFLW.
2599 static bool isPSHUFLWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2600 if (VT != MVT::v8i16)
2603 // Upper quadword copied in order.
2604 for (int i = 4; i != 8; ++i)
2605 if (Mask[i] >= 0 && Mask[i] != i)
2608 // Lower quadword shuffled.
2609 for (int i = 0; i != 4; ++i)
2616 bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) {
2617 SmallVector<int, 8> M;
2619 return ::isPSHUFLWMask(M, N->getValueType(0));
2622 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
2623 /// is suitable for input to PALIGNR.
2624 static bool isPALIGNRMask(const SmallVectorImpl<int> &Mask, EVT VT,
2626 int i, e = VT.getVectorNumElements();
2628 // Do not handle v2i64 / v2f64 shuffles with palignr.
2629 if (e < 4 || !hasSSSE3)
2632 for (i = 0; i != e; ++i)
2636 // All undef, not a palignr.
2640 // Determine if it's ok to perform a palignr with only the LHS, since we
2641 // don't have access to the actual shuffle elements to see if RHS is undef.
2642 bool Unary = Mask[i] < (int)e;
2643 bool NeedsUnary = false;
2645 int s = Mask[i] - i;
2647 // Check the rest of the elements to see if they are consecutive.
2648 for (++i; i != e; ++i) {
2653 Unary = Unary && (m < (int)e);
2654 NeedsUnary = NeedsUnary || (m < s);
2656 if (NeedsUnary && !Unary)
2658 if (Unary && m != ((s+i) & (e-1)))
2660 if (!Unary && m != (s+i))
2666 bool X86::isPALIGNRMask(ShuffleVectorSDNode *N) {
2667 SmallVector<int, 8> M;
2669 return ::isPALIGNRMask(M, N->getValueType(0), true);
2672 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
2673 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
2674 static bool isSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2675 int NumElems = VT.getVectorNumElements();
2676 if (NumElems != 2 && NumElems != 4)
2679 int Half = NumElems / 2;
2680 for (int i = 0; i < Half; ++i)
2681 if (!isUndefOrInRange(Mask[i], 0, NumElems))
2683 for (int i = Half; i < NumElems; ++i)
2684 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
2690 bool X86::isSHUFPMask(ShuffleVectorSDNode *N) {
2691 SmallVector<int, 8> M;
2693 return ::isSHUFPMask(M, N->getValueType(0));
2696 /// isCommutedSHUFP - Returns true if the shuffle mask is exactly
2697 /// the reverse of what x86 shuffles want. x86 shuffles requires the lower
2698 /// half elements to come from vector 1 (which would equal the dest.) and
2699 /// the upper half to come from vector 2.
2700 static bool isCommutedSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2701 int NumElems = VT.getVectorNumElements();
2703 if (NumElems != 2 && NumElems != 4)
2706 int Half = NumElems / 2;
2707 for (int i = 0; i < Half; ++i)
2708 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
2710 for (int i = Half; i < NumElems; ++i)
2711 if (!isUndefOrInRange(Mask[i], 0, NumElems))
2716 static bool isCommutedSHUFP(ShuffleVectorSDNode *N) {
2717 SmallVector<int, 8> M;
2719 return isCommutedSHUFPMask(M, N->getValueType(0));
2722 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
2723 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
2724 bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) {
2725 if (N->getValueType(0).getVectorNumElements() != 4)
2728 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
2729 return isUndefOrEqual(N->getMaskElt(0), 6) &&
2730 isUndefOrEqual(N->getMaskElt(1), 7) &&
2731 isUndefOrEqual(N->getMaskElt(2), 2) &&
2732 isUndefOrEqual(N->getMaskElt(3), 3);
2735 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
2736 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
2738 bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) {
2739 unsigned NumElems = N->getValueType(0).getVectorNumElements();
2744 return isUndefOrEqual(N->getMaskElt(0), 2) &&
2745 isUndefOrEqual(N->getMaskElt(1), 3) &&
2746 isUndefOrEqual(N->getMaskElt(2), 2) &&
2747 isUndefOrEqual(N->getMaskElt(3), 3);
2750 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
2751 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
2752 bool X86::isMOVLPMask(ShuffleVectorSDNode *N) {
2753 unsigned NumElems = N->getValueType(0).getVectorNumElements();
2755 if (NumElems != 2 && NumElems != 4)
2758 for (unsigned i = 0; i < NumElems/2; ++i)
2759 if (!isUndefOrEqual(N->getMaskElt(i), i + NumElems))
2762 for (unsigned i = NumElems/2; i < NumElems; ++i)
2763 if (!isUndefOrEqual(N->getMaskElt(i), i))
2769 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
2770 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
2771 bool X86::isMOVLHPSMask(ShuffleVectorSDNode *N) {
2772 unsigned NumElems = N->getValueType(0).getVectorNumElements();
2774 if (NumElems != 2 && NumElems != 4)
2777 for (unsigned i = 0; i < NumElems/2; ++i)
2778 if (!isUndefOrEqual(N->getMaskElt(i), i))
2781 for (unsigned i = 0; i < NumElems/2; ++i)
2782 if (!isUndefOrEqual(N->getMaskElt(i + NumElems/2), i + NumElems))
2788 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
2789 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
2790 static bool isUNPCKLMask(const SmallVectorImpl<int> &Mask, EVT VT,
2791 bool V2IsSplat = false) {
2792 int NumElts = VT.getVectorNumElements();
2793 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2796 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) {
2798 int BitI1 = Mask[i+1];
2799 if (!isUndefOrEqual(BitI, j))
2802 if (!isUndefOrEqual(BitI1, NumElts))
2805 if (!isUndefOrEqual(BitI1, j + NumElts))
2812 bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
2813 SmallVector<int, 8> M;
2815 return ::isUNPCKLMask(M, N->getValueType(0), V2IsSplat);
2818 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
2819 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
2820 static bool isUNPCKHMask(const SmallVectorImpl<int> &Mask, EVT VT,
2821 bool V2IsSplat = false) {
2822 int NumElts = VT.getVectorNumElements();
2823 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2826 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) {
2828 int BitI1 = Mask[i+1];
2829 if (!isUndefOrEqual(BitI, j + NumElts/2))
2832 if (isUndefOrEqual(BitI1, NumElts))
2835 if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts))
2842 bool X86::isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
2843 SmallVector<int, 8> M;
2845 return ::isUNPCKHMask(M, N->getValueType(0), V2IsSplat);
2848 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
2849 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
2851 static bool isUNPCKL_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
2852 int NumElems = VT.getVectorNumElements();
2853 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2856 for (int i = 0, j = 0; i != NumElems; i += 2, ++j) {
2858 int BitI1 = Mask[i+1];
2859 if (!isUndefOrEqual(BitI, j))
2861 if (!isUndefOrEqual(BitI1, j))
2867 bool X86::isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N) {
2868 SmallVector<int, 8> M;
2870 return ::isUNPCKL_v_undef_Mask(M, N->getValueType(0));
2873 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
2874 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
2876 static bool isUNPCKH_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
2877 int NumElems = VT.getVectorNumElements();
2878 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2881 for (int i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) {
2883 int BitI1 = Mask[i+1];
2884 if (!isUndefOrEqual(BitI, j))
2886 if (!isUndefOrEqual(BitI1, j))
2892 bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N) {
2893 SmallVector<int, 8> M;
2895 return ::isUNPCKH_v_undef_Mask(M, N->getValueType(0));
2898 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
2899 /// specifies a shuffle of elements that is suitable for input to MOVSS,
2900 /// MOVSD, and MOVD, i.e. setting the lowest element.
2901 static bool isMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2902 if (VT.getVectorElementType().getSizeInBits() < 32)
2905 int NumElts = VT.getVectorNumElements();
2907 if (!isUndefOrEqual(Mask[0], NumElts))
2910 for (int i = 1; i < NumElts; ++i)
2911 if (!isUndefOrEqual(Mask[i], i))
2917 bool X86::isMOVLMask(ShuffleVectorSDNode *N) {
2918 SmallVector<int, 8> M;
2920 return ::isMOVLMask(M, N->getValueType(0));
2923 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
2924 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
2925 /// element of vector 2 and the other elements to come from vector 1 in order.
2926 static bool isCommutedMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT,
2927 bool V2IsSplat = false, bool V2IsUndef = false) {
2928 int NumOps = VT.getVectorNumElements();
2929 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
2932 if (!isUndefOrEqual(Mask[0], 0))
2935 for (int i = 1; i < NumOps; ++i)
2936 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
2937 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
2938 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
2944 static bool isCommutedMOVL(ShuffleVectorSDNode *N, bool V2IsSplat = false,
2945 bool V2IsUndef = false) {
2946 SmallVector<int, 8> M;
2948 return isCommutedMOVLMask(M, N->getValueType(0), V2IsSplat, V2IsUndef);
2951 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2952 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
2953 bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N) {
2954 if (N->getValueType(0).getVectorNumElements() != 4)
2957 // Expect 1, 1, 3, 3
2958 for (unsigned i = 0; i < 2; ++i) {
2959 int Elt = N->getMaskElt(i);
2960 if (Elt >= 0 && Elt != 1)
2965 for (unsigned i = 2; i < 4; ++i) {
2966 int Elt = N->getMaskElt(i);
2967 if (Elt >= 0 && Elt != 3)
2972 // Don't use movshdup if it can be done with a shufps.
2973 // FIXME: verify that matching u, u, 3, 3 is what we want.
2977 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2978 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
2979 bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N) {
2980 if (N->getValueType(0).getVectorNumElements() != 4)
2983 // Expect 0, 0, 2, 2
2984 for (unsigned i = 0; i < 2; ++i)
2985 if (N->getMaskElt(i) > 0)
2989 for (unsigned i = 2; i < 4; ++i) {
2990 int Elt = N->getMaskElt(i);
2991 if (Elt >= 0 && Elt != 2)
2996 // Don't use movsldup if it can be done with a shufps.
3000 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3001 /// specifies a shuffle of elements that is suitable for input to MOVDDUP.
3002 bool X86::isMOVDDUPMask(ShuffleVectorSDNode *N) {
3003 int e = N->getValueType(0).getVectorNumElements() / 2;
3005 for (int i = 0; i < e; ++i)
3006 if (!isUndefOrEqual(N->getMaskElt(i), i))
3008 for (int i = 0; i < e; ++i)
3009 if (!isUndefOrEqual(N->getMaskElt(e+i), i))
3014 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
3015 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
3016 unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
3017 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3018 int NumOperands = SVOp->getValueType(0).getVectorNumElements();
3020 unsigned Shift = (NumOperands == 4) ? 2 : 1;
3022 for (int i = 0; i < NumOperands; ++i) {
3023 int Val = SVOp->getMaskElt(NumOperands-i-1);
3024 if (Val < 0) Val = 0;
3025 if (Val >= NumOperands) Val -= NumOperands;
3027 if (i != NumOperands - 1)
3033 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
3034 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
3035 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
3036 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3038 // 8 nodes, but we only care about the last 4.
3039 for (unsigned i = 7; i >= 4; --i) {
3040 int Val = SVOp->getMaskElt(i);
3049 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
3050 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
3051 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
3052 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3054 // 8 nodes, but we only care about the first 4.
3055 for (int i = 3; i >= 0; --i) {
3056 int Val = SVOp->getMaskElt(i);
3065 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
3066 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
3067 unsigned X86::getShufflePALIGNRImmediate(SDNode *N) {
3068 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3069 EVT VVT = N->getValueType(0);
3070 unsigned EltSize = VVT.getVectorElementType().getSizeInBits() >> 3;
3074 for (i = 0, e = VVT.getVectorNumElements(); i != e; ++i) {
3075 Val = SVOp->getMaskElt(i);
3079 return (Val - i) * EltSize;
3082 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
3084 bool X86::isZeroNode(SDValue Elt) {
3085 return ((isa<ConstantSDNode>(Elt) &&
3086 cast<ConstantSDNode>(Elt)->getZExtValue() == 0) ||
3087 (isa<ConstantFPSDNode>(Elt) &&
3088 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
3091 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
3092 /// their permute mask.
3093 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
3094 SelectionDAG &DAG) {
3095 EVT VT = SVOp->getValueType(0);
3096 unsigned NumElems = VT.getVectorNumElements();
3097 SmallVector<int, 8> MaskVec;
3099 for (unsigned i = 0; i != NumElems; ++i) {
3100 int idx = SVOp->getMaskElt(i);
3102 MaskVec.push_back(idx);
3103 else if (idx < (int)NumElems)
3104 MaskVec.push_back(idx + NumElems);
3106 MaskVec.push_back(idx - NumElems);
3108 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
3109 SVOp->getOperand(0), &MaskVec[0]);
3112 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3113 /// the two vector operands have swapped position.
3114 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, EVT VT) {
3115 unsigned NumElems = VT.getVectorNumElements();
3116 for (unsigned i = 0; i != NumElems; ++i) {
3120 else if (idx < (int)NumElems)
3121 Mask[i] = idx + NumElems;
3123 Mask[i] = idx - NumElems;
3127 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
3128 /// match movhlps. The lower half elements should come from upper half of
3129 /// V1 (and in order), and the upper half elements should come from the upper
3130 /// half of V2 (and in order).
3131 static bool ShouldXformToMOVHLPS(ShuffleVectorSDNode *Op) {
3132 if (Op->getValueType(0).getVectorNumElements() != 4)
3134 for (unsigned i = 0, e = 2; i != e; ++i)
3135 if (!isUndefOrEqual(Op->getMaskElt(i), i+2))
3137 for (unsigned i = 2; i != 4; ++i)
3138 if (!isUndefOrEqual(Op->getMaskElt(i), i+4))
3143 /// isScalarLoadToVector - Returns true if the node is a scalar load that
3144 /// is promoted to a vector. It also returns the LoadSDNode by reference if
3146 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
3147 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
3149 N = N->getOperand(0).getNode();
3150 if (!ISD::isNON_EXTLoad(N))
3153 *LD = cast<LoadSDNode>(N);
3157 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
3158 /// match movlp{s|d}. The lower half elements should come from lower half of
3159 /// V1 (and in order), and the upper half elements should come from the upper
3160 /// half of V2 (and in order). And since V1 will become the source of the
3161 /// MOVLP, it must be either a vector load or a scalar load to vector.
3162 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
3163 ShuffleVectorSDNode *Op) {
3164 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
3166 // Is V2 is a vector load, don't do this transformation. We will try to use
3167 // load folding shufps op.
3168 if (ISD::isNON_EXTLoad(V2))
3171 unsigned NumElems = Op->getValueType(0).getVectorNumElements();
3173 if (NumElems != 2 && NumElems != 4)
3175 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3176 if (!isUndefOrEqual(Op->getMaskElt(i), i))
3178 for (unsigned i = NumElems/2; i != NumElems; ++i)
3179 if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems))
3184 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
3186 static bool isSplatVector(SDNode *N) {
3187 if (N->getOpcode() != ISD::BUILD_VECTOR)
3190 SDValue SplatValue = N->getOperand(0);
3191 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
3192 if (N->getOperand(i) != SplatValue)
3197 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
3198 /// to an zero vector.
3199 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
3200 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
3201 SDValue V1 = N->getOperand(0);
3202 SDValue V2 = N->getOperand(1);
3203 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3204 for (unsigned i = 0; i != NumElems; ++i) {
3205 int Idx = N->getMaskElt(i);
3206 if (Idx >= (int)NumElems) {
3207 unsigned Opc = V2.getOpcode();
3208 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
3210 if (Opc != ISD::BUILD_VECTOR ||
3211 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
3213 } else if (Idx >= 0) {
3214 unsigned Opc = V1.getOpcode();
3215 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
3217 if (Opc != ISD::BUILD_VECTOR ||
3218 !X86::isZeroNode(V1.getOperand(Idx)))
3225 /// getZeroVector - Returns a vector of specified type with all zero elements.
3227 static SDValue getZeroVector(EVT VT, bool HasSSE2, SelectionDAG &DAG,
3229 assert(VT.isVector() && "Expected a vector type");
3231 // Always build zero vectors as <4 x i32> or <2 x i32> bitcasted to their dest
3232 // type. This ensures they get CSE'd.
3234 if (VT.getSizeInBits() == 64) { // MMX
3235 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
3236 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
3237 } else if (HasSSE2) { // SSE2
3238 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
3239 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
3241 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
3242 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
3244 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
3247 /// getOnesVector - Returns a vector of specified type with all bits set.
3249 static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
3250 assert(VT.isVector() && "Expected a vector type");
3252 // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest
3253 // type. This ensures they get CSE'd.
3254 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
3256 if (VT.getSizeInBits() == 64) // MMX
3257 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
3259 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
3260 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
3264 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
3265 /// that point to V2 points to its first element.
3266 static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
3267 EVT VT = SVOp->getValueType(0);
3268 unsigned NumElems = VT.getVectorNumElements();
3270 bool Changed = false;
3271 SmallVector<int, 8> MaskVec;
3272 SVOp->getMask(MaskVec);
3274 for (unsigned i = 0; i != NumElems; ++i) {
3275 if (MaskVec[i] > (int)NumElems) {
3276 MaskVec[i] = NumElems;
3281 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(0),
3282 SVOp->getOperand(1), &MaskVec[0]);
3283 return SDValue(SVOp, 0);
3286 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
3287 /// operation of specified width.
3288 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3290 unsigned NumElems = VT.getVectorNumElements();
3291 SmallVector<int, 8> Mask;
3292 Mask.push_back(NumElems);
3293 for (unsigned i = 1; i != NumElems; ++i)
3295 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3298 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
3299 static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3301 unsigned NumElems = VT.getVectorNumElements();
3302 SmallVector<int, 8> Mask;
3303 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
3305 Mask.push_back(i + NumElems);
3307 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3310 /// getUnpackhMask - Returns a vector_shuffle node for an unpackh operation.
3311 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3313 unsigned NumElems = VT.getVectorNumElements();
3314 unsigned Half = NumElems/2;
3315 SmallVector<int, 8> Mask;
3316 for (unsigned i = 0; i != Half; ++i) {
3317 Mask.push_back(i + Half);
3318 Mask.push_back(i + NumElems + Half);
3320 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3323 /// PromoteSplat - Promote a splat of v4f32, v8i16 or v16i8 to v4i32.
3324 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG,
3326 if (SV->getValueType(0).getVectorNumElements() <= 4)
3327 return SDValue(SV, 0);
3329 EVT PVT = MVT::v4f32;
3330 EVT VT = SV->getValueType(0);
3331 DebugLoc dl = SV->getDebugLoc();
3332 SDValue V1 = SV->getOperand(0);
3333 int NumElems = VT.getVectorNumElements();
3334 int EltNo = SV->getSplatIndex();
3336 // unpack elements to the correct location
3337 while (NumElems > 4) {
3338 if (EltNo < NumElems/2) {
3339 V1 = getUnpackl(DAG, dl, VT, V1, V1);
3341 V1 = getUnpackh(DAG, dl, VT, V1, V1);
3342 EltNo -= NumElems/2;
3347 // Perform the splat.
3348 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
3349 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, PVT, V1);
3350 V1 = DAG.getVectorShuffle(PVT, dl, V1, DAG.getUNDEF(PVT), &SplatMask[0]);
3351 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, V1);
3354 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
3355 /// vector of zero or undef vector. This produces a shuffle where the low
3356 /// element of V2 is swizzled into the zero/undef vector, landing at element
3357 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
3358 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
3359 bool isZero, bool HasSSE2,
3360 SelectionDAG &DAG) {
3361 EVT VT = V2.getValueType();
3363 ? getZeroVector(VT, HasSSE2, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT);
3364 unsigned NumElems = VT.getVectorNumElements();
3365 SmallVector<int, 16> MaskVec;
3366 for (unsigned i = 0; i != NumElems; ++i)
3367 // If this is the insertion idx, put the low elt of V2 here.
3368 MaskVec.push_back(i == Idx ? NumElems : i);
3369 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
3372 /// getNumOfConsecutiveZeros - Return the number of elements in a result of
3373 /// a shuffle that is zero.
3375 unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp, int NumElems,
3376 bool Low, SelectionDAG &DAG) {
3377 unsigned NumZeros = 0;
3378 for (int i = 0; i < NumElems; ++i) {
3379 unsigned Index = Low ? i : NumElems-i-1;
3380 int Idx = SVOp->getMaskElt(Index);
3385 SDValue Elt = DAG.getShuffleScalarElt(SVOp, Index);
3386 if (Elt.getNode() && X86::isZeroNode(Elt))
3394 /// isVectorShift - Returns true if the shuffle can be implemented as a
3395 /// logical left or right shift of a vector.
3396 /// FIXME: split into pslldqi, psrldqi, palignr variants.
3397 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
3398 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
3399 int NumElems = SVOp->getValueType(0).getVectorNumElements();
3402 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, true, DAG);
3405 NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, false, DAG);
3409 bool SeenV1 = false;
3410 bool SeenV2 = false;
3411 for (int i = NumZeros; i < NumElems; ++i) {
3412 int Val = isLeft ? (i - NumZeros) : i;
3413 int Idx = SVOp->getMaskElt(isLeft ? i : (i - NumZeros));
3425 if (SeenV1 && SeenV2)
3428 ShVal = SeenV1 ? SVOp->getOperand(0) : SVOp->getOperand(1);
3434 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
3436 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
3437 unsigned NumNonZero, unsigned NumZero,
3438 SelectionDAG &DAG, TargetLowering &TLI) {
3442 DebugLoc dl = Op.getDebugLoc();
3445 for (unsigned i = 0; i < 16; ++i) {
3446 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
3447 if (ThisIsNonZero && First) {
3449 V = getZeroVector(MVT::v8i16, true, DAG, dl);
3451 V = DAG.getUNDEF(MVT::v8i16);
3456 SDValue ThisElt(0, 0), LastElt(0, 0);
3457 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
3458 if (LastIsNonZero) {
3459 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
3460 MVT::i16, Op.getOperand(i-1));
3462 if (ThisIsNonZero) {
3463 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
3464 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
3465 ThisElt, DAG.getConstant(8, MVT::i8));
3467 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
3471 if (ThisElt.getNode())
3472 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
3473 DAG.getIntPtrConstant(i/2));
3477 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V);
3480 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
3482 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
3483 unsigned NumNonZero, unsigned NumZero,
3484 SelectionDAG &DAG, TargetLowering &TLI) {
3488 DebugLoc dl = Op.getDebugLoc();
3491 for (unsigned i = 0; i < 8; ++i) {
3492 bool isNonZero = (NonZeros & (1 << i)) != 0;
3496 V = getZeroVector(MVT::v8i16, true, DAG, dl);
3498 V = DAG.getUNDEF(MVT::v8i16);
3501 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
3502 MVT::v8i16, V, Op.getOperand(i),
3503 DAG.getIntPtrConstant(i));
3510 /// getVShift - Return a vector logical shift node.
3512 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
3513 unsigned NumBits, SelectionDAG &DAG,
3514 const TargetLowering &TLI, DebugLoc dl) {
3515 bool isMMX = VT.getSizeInBits() == 64;
3516 EVT ShVT = isMMX ? MVT::v1i64 : MVT::v2i64;
3517 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL;
3518 SrcOp = DAG.getNode(ISD::BIT_CONVERT, dl, ShVT, SrcOp);
3519 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
3520 DAG.getNode(Opc, dl, ShVT, SrcOp,
3521 DAG.getConstant(NumBits, TLI.getShiftAmountTy())));
3525 X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
3526 SelectionDAG &DAG) {
3528 // Check if the scalar load can be widened into a vector load. And if
3529 // the address is "base + cst" see if the cst can be "absorbed" into
3530 // the shuffle mask.
3531 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
3532 SDValue Ptr = LD->getBasePtr();
3533 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
3535 EVT PVT = LD->getValueType(0);
3536 if (PVT != MVT::i32 && PVT != MVT::f32)
3541 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
3542 FI = FINode->getIndex();
3544 } else if (Ptr.getOpcode() == ISD::ADD &&
3545 isa<ConstantSDNode>(Ptr.getOperand(1)) &&
3546 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
3547 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
3548 Offset = Ptr.getConstantOperandVal(1);
3549 Ptr = Ptr.getOperand(0);
3554 SDValue Chain = LD->getChain();
3555 // Make sure the stack object alignment is at least 16.
3556 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
3557 if (DAG.InferPtrAlignment(Ptr) < 16) {
3558 if (MFI->isFixedObjectIndex(FI)) {
3559 // Can't change the alignment. FIXME: It's possible to compute
3560 // the exact stack offset and reference FI + adjust offset instead.
3561 // If someone *really* cares about this. That's the way to implement it.
3564 MFI->setObjectAlignment(FI, 16);
3568 // (Offset % 16) must be multiple of 4. Then address is then
3569 // Ptr + (Offset & ~15).
3572 if ((Offset % 16) & 3)
3574 int64_t StartOffset = Offset & ~15;
3576 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(),
3577 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
3579 int EltNo = (Offset - StartOffset) >> 2;
3580 int Mask[4] = { EltNo, EltNo, EltNo, EltNo };
3581 EVT VT = (PVT == MVT::i32) ? MVT::v4i32 : MVT::v4f32;
3582 SDValue V1 = DAG.getLoad(VT, dl, Chain, Ptr,LD->getSrcValue(),0,
3584 // Canonicalize it to a v4i32 shuffle.
3585 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32, V1);
3586 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
3587 DAG.getVectorShuffle(MVT::v4i32, dl, V1,
3588 DAG.getUNDEF(MVT::v4i32), &Mask[0]));
3595 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
3596 DebugLoc dl = Op.getDebugLoc();
3597 // All zero's are handled with pxor, all one's are handled with pcmpeqd.
3598 if (ISD::isBuildVectorAllZeros(Op.getNode())
3599 || ISD::isBuildVectorAllOnes(Op.getNode())) {
3600 // Canonicalize this to either <4 x i32> or <2 x i32> (SSE vs MMX) to
3601 // 1) ensure the zero vectors are CSE'd, and 2) ensure that i64 scalars are
3602 // eliminated on x86-32 hosts.
3603 if (Op.getValueType() == MVT::v4i32 || Op.getValueType() == MVT::v2i32)
3606 if (ISD::isBuildVectorAllOnes(Op.getNode()))
3607 return getOnesVector(Op.getValueType(), DAG, dl);
3608 return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG, dl);
3611 EVT VT = Op.getValueType();
3612 EVT ExtVT = VT.getVectorElementType();
3613 unsigned EVTBits = ExtVT.getSizeInBits();
3615 unsigned NumElems = Op.getNumOperands();
3616 unsigned NumZero = 0;
3617 unsigned NumNonZero = 0;
3618 unsigned NonZeros = 0;
3619 bool IsAllConstants = true;
3620 SmallSet<SDValue, 8> Values;
3621 for (unsigned i = 0; i < NumElems; ++i) {
3622 SDValue Elt = Op.getOperand(i);
3623 if (Elt.getOpcode() == ISD::UNDEF)
3626 if (Elt.getOpcode() != ISD::Constant &&
3627 Elt.getOpcode() != ISD::ConstantFP)
3628 IsAllConstants = false;
3629 if (X86::isZeroNode(Elt))
3632 NonZeros |= (1 << i);
3637 if (NumNonZero == 0) {
3638 // All undef vector. Return an UNDEF. All zero vectors were handled above.
3639 return DAG.getUNDEF(VT);
3642 // Special case for single non-zero, non-undef, element.
3643 if (NumNonZero == 1) {
3644 unsigned Idx = CountTrailingZeros_32(NonZeros);
3645 SDValue Item = Op.getOperand(Idx);
3647 // If this is an insertion of an i64 value on x86-32, and if the top bits of
3648 // the value are obviously zero, truncate the value to i32 and do the
3649 // insertion that way. Only do this if the value is non-constant or if the
3650 // value is a constant being inserted into element 0. It is cheaper to do
3651 // a constant pool load than it is to do a movd + shuffle.
3652 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
3653 (!IsAllConstants || Idx == 0)) {
3654 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
3655 // Handle MMX and SSE both.
3656 EVT VecVT = VT == MVT::v2i64 ? MVT::v4i32 : MVT::v2i32;
3657 unsigned VecElts = VT == MVT::v2i64 ? 4 : 2;
3659 // Truncate the value (which may itself be a constant) to i32, and
3660 // convert it to a vector with movd (S2V+shuffle to zero extend).
3661 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
3662 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
3663 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
3664 Subtarget->hasSSE2(), DAG);
3666 // Now we have our 32-bit value zero extended in the low element of
3667 // a vector. If Idx != 0, swizzle it into place.
3669 SmallVector<int, 4> Mask;
3670 Mask.push_back(Idx);
3671 for (unsigned i = 1; i != VecElts; ++i)
3673 Item = DAG.getVectorShuffle(VecVT, dl, Item,
3674 DAG.getUNDEF(Item.getValueType()),
3677 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Item);
3681 // If we have a constant or non-constant insertion into the low element of
3682 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
3683 // the rest of the elements. This will be matched as movd/movq/movss/movsd
3684 // depending on what the source datatype is.
3687 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
3688 } else if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
3689 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
3690 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
3691 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
3692 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget->hasSSE2(),
3694 } else if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
3695 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
3696 EVT MiddleVT = VT.getSizeInBits() == 64 ? MVT::v2i32 : MVT::v4i32;
3697 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MiddleVT, Item);
3698 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
3699 Subtarget->hasSSE2(), DAG);
3700 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Item);
3704 // Is it a vector logical left shift?
3705 if (NumElems == 2 && Idx == 1 &&
3706 X86::isZeroNode(Op.getOperand(0)) &&
3707 !X86::isZeroNode(Op.getOperand(1))) {
3708 unsigned NumBits = VT.getSizeInBits();
3709 return getVShift(true, VT,
3710 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
3711 VT, Op.getOperand(1)),
3712 NumBits/2, DAG, *this, dl);
3715 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
3718 // Otherwise, if this is a vector with i32 or f32 elements, and the element
3719 // is a non-constant being inserted into an element other than the low one,
3720 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
3721 // movd/movss) to move this into the low element, then shuffle it into
3723 if (EVTBits == 32) {
3724 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
3726 // Turn it into a shuffle of zero and zero-extended scalar to vector.
3727 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
3728 Subtarget->hasSSE2(), DAG);
3729 SmallVector<int, 8> MaskVec;
3730 for (unsigned i = 0; i < NumElems; i++)
3731 MaskVec.push_back(i == Idx ? 0 : 1);
3732 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
3736 // Splat is obviously ok. Let legalizer expand it to a shuffle.
3737 if (Values.size() == 1) {
3738 if (EVTBits == 32) {
3739 // Instead of a shuffle like this:
3740 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
3741 // Check if it's possible to issue this instead.
3742 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
3743 unsigned Idx = CountTrailingZeros_32(NonZeros);
3744 SDValue Item = Op.getOperand(Idx);
3745 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
3746 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
3751 // A vector full of immediates; various special cases are already
3752 // handled, so this is best done with a single constant-pool load.
3756 // Let legalizer expand 2-wide build_vectors.
3757 if (EVTBits == 64) {
3758 if (NumNonZero == 1) {
3759 // One half is zero or undef.
3760 unsigned Idx = CountTrailingZeros_32(NonZeros);
3761 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
3762 Op.getOperand(Idx));
3763 return getShuffleVectorZeroOrUndef(V2, Idx, true,
3764 Subtarget->hasSSE2(), DAG);
3769 // If element VT is < 32 bits, convert it to inserts into a zero vector.
3770 if (EVTBits == 8 && NumElems == 16) {
3771 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
3773 if (V.getNode()) return V;
3776 if (EVTBits == 16 && NumElems == 8) {
3777 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
3779 if (V.getNode()) return V;
3782 // If element VT is == 32 bits, turn it into a number of shuffles.
3783 SmallVector<SDValue, 8> V;
3785 if (NumElems == 4 && NumZero > 0) {
3786 for (unsigned i = 0; i < 4; ++i) {
3787 bool isZero = !(NonZeros & (1 << i));
3789 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
3791 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
3794 for (unsigned i = 0; i < 2; ++i) {
3795 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
3798 V[i] = V[i*2]; // Must be a zero vector.
3801 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
3804 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
3807 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
3812 SmallVector<int, 8> MaskVec;
3813 bool Reverse = (NonZeros & 0x3) == 2;
3814 for (unsigned i = 0; i < 2; ++i)
3815 MaskVec.push_back(Reverse ? 1-i : i);
3816 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
3817 for (unsigned i = 0; i < 2; ++i)
3818 MaskVec.push_back(Reverse ? 1-i+NumElems : i+NumElems);
3819 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
3822 if (Values.size() > 2) {
3823 // If we have SSE 4.1, Expand into a number of inserts unless the number of
3824 // values to be inserted is equal to the number of elements, in which case
3825 // use the unpack code below in the hopes of matching the consecutive elts
3826 // load merge pattern for shuffles.
3827 // FIXME: We could probably just check that here directly.
3828 if (Values.size() < NumElems && VT.getSizeInBits() == 128 &&
3829 getSubtarget()->hasSSE41()) {
3830 V[0] = DAG.getUNDEF(VT);
3831 for (unsigned i = 0; i < NumElems; ++i)
3832 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
3833 V[0] = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, V[0],
3834 Op.getOperand(i), DAG.getIntPtrConstant(i));
3837 // Expand into a number of unpckl*.
3839 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
3840 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
3841 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
3842 for (unsigned i = 0; i < NumElems; ++i)
3843 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
3845 while (NumElems != 0) {
3846 for (unsigned i = 0; i < NumElems; ++i)
3847 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + NumElems]);
3857 X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
3858 // We support concatenate two MMX registers and place them in a MMX
3859 // register. This is better than doing a stack convert.
3860 DebugLoc dl = Op.getDebugLoc();
3861 EVT ResVT = Op.getValueType();
3862 assert(Op.getNumOperands() == 2);
3863 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 ||
3864 ResVT == MVT::v8i16 || ResVT == MVT::v16i8);
3866 SDValue InVec = DAG.getNode(ISD::BIT_CONVERT,dl, MVT::v1i64, Op.getOperand(0));
3867 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
3868 InVec = Op.getOperand(1);
3869 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
3870 unsigned NumElts = ResVT.getVectorNumElements();
3871 VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, ResVT, VecOp);
3872 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp,
3873 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1));
3875 InVec = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v1i64, InVec);
3876 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
3877 Mask[0] = 0; Mask[1] = 2;
3878 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask);
3880 return DAG.getNode(ISD::BIT_CONVERT, dl, ResVT, VecOp);
3883 // v8i16 shuffles - Prefer shuffles in the following order:
3884 // 1. [all] pshuflw, pshufhw, optional move
3885 // 2. [ssse3] 1 x pshufb
3886 // 3. [ssse3] 2 x pshufb + 1 x por
3887 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
3889 SDValue LowerVECTOR_SHUFFLEv8i16(ShuffleVectorSDNode *SVOp,
3890 SelectionDAG &DAG, X86TargetLowering &TLI) {
3891 SDValue V1 = SVOp->getOperand(0);
3892 SDValue V2 = SVOp->getOperand(1);
3893 DebugLoc dl = SVOp->getDebugLoc();
3894 SmallVector<int, 8> MaskVals;
3896 // Determine if more than 1 of the words in each of the low and high quadwords
3897 // of the result come from the same quadword of one of the two inputs. Undef
3898 // mask values count as coming from any quadword, for better codegen.
3899 SmallVector<unsigned, 4> LoQuad(4);
3900 SmallVector<unsigned, 4> HiQuad(4);
3901 BitVector InputQuads(4);
3902 for (unsigned i = 0; i < 8; ++i) {
3903 SmallVectorImpl<unsigned> &Quad = i < 4 ? LoQuad : HiQuad;
3904 int EltIdx = SVOp->getMaskElt(i);
3905 MaskVals.push_back(EltIdx);
3914 InputQuads.set(EltIdx / 4);
3917 int BestLoQuad = -1;
3918 unsigned MaxQuad = 1;
3919 for (unsigned i = 0; i < 4; ++i) {
3920 if (LoQuad[i] > MaxQuad) {
3922 MaxQuad = LoQuad[i];
3926 int BestHiQuad = -1;
3928 for (unsigned i = 0; i < 4; ++i) {
3929 if (HiQuad[i] > MaxQuad) {
3931 MaxQuad = HiQuad[i];
3935 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
3936 // of the two input vectors, shuffle them into one input vector so only a
3937 // single pshufb instruction is necessary. If There are more than 2 input
3938 // quads, disable the next transformation since it does not help SSSE3.
3939 bool V1Used = InputQuads[0] || InputQuads[1];
3940 bool V2Used = InputQuads[2] || InputQuads[3];
3941 if (TLI.getSubtarget()->hasSSSE3()) {
3942 if (InputQuads.count() == 2 && V1Used && V2Used) {
3943 BestLoQuad = InputQuads.find_first();
3944 BestHiQuad = InputQuads.find_next(BestLoQuad);
3946 if (InputQuads.count() > 2) {
3952 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
3953 // the shuffle mask. If a quad is scored as -1, that means that it contains
3954 // words from all 4 input quadwords.
3956 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
3957 SmallVector<int, 8> MaskV;
3958 MaskV.push_back(BestLoQuad < 0 ? 0 : BestLoQuad);
3959 MaskV.push_back(BestHiQuad < 0 ? 1 : BestHiQuad);
3960 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
3961 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V1),
3962 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V2), &MaskV[0]);
3963 NewV = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, NewV);
3965 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
3966 // source words for the shuffle, to aid later transformations.
3967 bool AllWordsInNewV = true;
3968 bool InOrder[2] = { true, true };
3969 for (unsigned i = 0; i != 8; ++i) {
3970 int idx = MaskVals[i];
3972 InOrder[i/4] = false;
3973 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
3975 AllWordsInNewV = false;
3979 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
3980 if (AllWordsInNewV) {
3981 for (int i = 0; i != 8; ++i) {
3982 int idx = MaskVals[i];
3985 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
3986 if ((idx != i) && idx < 4)
3988 if ((idx != i) && idx > 3)
3997 // If we've eliminated the use of V2, and the new mask is a pshuflw or
3998 // pshufhw, that's as cheap as it gets. Return the new shuffle.
3999 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
4000 return DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
4001 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
4005 // If we have SSSE3, and all words of the result are from 1 input vector,
4006 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
4007 // is present, fall back to case 4.
4008 if (TLI.getSubtarget()->hasSSSE3()) {
4009 SmallVector<SDValue,16> pshufbMask;
4011 // If we have elements from both input vectors, set the high bit of the
4012 // shuffle mask element to zero out elements that come from V2 in the V1
4013 // mask, and elements that come from V1 in the V2 mask, so that the two
4014 // results can be OR'd together.
4015 bool TwoInputs = V1Used && V2Used;
4016 for (unsigned i = 0; i != 8; ++i) {
4017 int EltIdx = MaskVals[i] * 2;
4018 if (TwoInputs && (EltIdx >= 16)) {
4019 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4020 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4023 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
4024 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8));
4026 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V1);
4027 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
4028 DAG.getNode(ISD::BUILD_VECTOR, dl,
4029 MVT::v16i8, &pshufbMask[0], 16));
4031 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
4033 // Calculate the shuffle mask for the second input, shuffle it, and
4034 // OR it with the first shuffled input.
4036 for (unsigned i = 0; i != 8; ++i) {
4037 int EltIdx = MaskVals[i] * 2;
4039 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4040 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4043 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
4044 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8));
4046 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V2);
4047 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
4048 DAG.getNode(ISD::BUILD_VECTOR, dl,
4049 MVT::v16i8, &pshufbMask[0], 16));
4050 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
4051 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
4054 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
4055 // and update MaskVals with new element order.
4056 BitVector InOrder(8);
4057 if (BestLoQuad >= 0) {
4058 SmallVector<int, 8> MaskV;
4059 for (int i = 0; i != 4; ++i) {
4060 int idx = MaskVals[i];
4062 MaskV.push_back(-1);
4064 } else if ((idx / 4) == BestLoQuad) {
4065 MaskV.push_back(idx & 3);
4068 MaskV.push_back(-1);
4071 for (unsigned i = 4; i != 8; ++i)
4073 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
4077 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
4078 // and update MaskVals with the new element order.
4079 if (BestHiQuad >= 0) {
4080 SmallVector<int, 8> MaskV;
4081 for (unsigned i = 0; i != 4; ++i)
4083 for (unsigned i = 4; i != 8; ++i) {
4084 int idx = MaskVals[i];
4086 MaskV.push_back(-1);
4088 } else if ((idx / 4) == BestHiQuad) {
4089 MaskV.push_back((idx & 3) + 4);
4092 MaskV.push_back(-1);
4095 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
4099 // In case BestHi & BestLo were both -1, which means each quadword has a word
4100 // from each of the four input quadwords, calculate the InOrder bitvector now
4101 // before falling through to the insert/extract cleanup.
4102 if (BestLoQuad == -1 && BestHiQuad == -1) {
4104 for (int i = 0; i != 8; ++i)
4105 if (MaskVals[i] < 0 || MaskVals[i] == i)
4109 // The other elements are put in the right place using pextrw and pinsrw.
4110 for (unsigned i = 0; i != 8; ++i) {
4113 int EltIdx = MaskVals[i];
4116 SDValue ExtOp = (EltIdx < 8)
4117 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
4118 DAG.getIntPtrConstant(EltIdx))
4119 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
4120 DAG.getIntPtrConstant(EltIdx - 8));
4121 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
4122 DAG.getIntPtrConstant(i));
4127 // v16i8 shuffles - Prefer shuffles in the following order:
4128 // 1. [ssse3] 1 x pshufb
4129 // 2. [ssse3] 2 x pshufb + 1 x por
4130 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
4132 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
4133 SelectionDAG &DAG, X86TargetLowering &TLI) {
4134 SDValue V1 = SVOp->getOperand(0);
4135 SDValue V2 = SVOp->getOperand(1);
4136 DebugLoc dl = SVOp->getDebugLoc();
4137 SmallVector<int, 16> MaskVals;
4138 SVOp->getMask(MaskVals);
4140 // If we have SSSE3, case 1 is generated when all result bytes come from
4141 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
4142 // present, fall back to case 3.
4143 // FIXME: kill V2Only once shuffles are canonizalized by getNode.
4146 for (unsigned i = 0; i < 16; ++i) {
4147 int EltIdx = MaskVals[i];
4156 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
4157 if (TLI.getSubtarget()->hasSSSE3()) {
4158 SmallVector<SDValue,16> pshufbMask;
4160 // If all result elements are from one input vector, then only translate
4161 // undef mask values to 0x80 (zero out result) in the pshufb mask.
4163 // Otherwise, we have elements from both input vectors, and must zero out
4164 // elements that come from V2 in the first mask, and V1 in the second mask
4165 // so that we can OR them together.
4166 bool TwoInputs = !(V1Only || V2Only);
4167 for (unsigned i = 0; i != 16; ++i) {
4168 int EltIdx = MaskVals[i];
4169 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) {
4170 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4173 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
4175 // If all the elements are from V2, assign it to V1 and return after
4176 // building the first pshufb.
4179 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
4180 DAG.getNode(ISD::BUILD_VECTOR, dl,
4181 MVT::v16i8, &pshufbMask[0], 16));
4185 // Calculate the shuffle mask for the second input, shuffle it, and
4186 // OR it with the first shuffled input.
4188 for (unsigned i = 0; i != 16; ++i) {
4189 int EltIdx = MaskVals[i];
4191 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4194 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
4196 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
4197 DAG.getNode(ISD::BUILD_VECTOR, dl,
4198 MVT::v16i8, &pshufbMask[0], 16));
4199 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
4202 // No SSSE3 - Calculate in place words and then fix all out of place words
4203 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
4204 // the 16 different words that comprise the two doublequadword input vectors.
4205 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
4206 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V2);
4207 SDValue NewV = V2Only ? V2 : V1;
4208 for (int i = 0; i != 8; ++i) {
4209 int Elt0 = MaskVals[i*2];
4210 int Elt1 = MaskVals[i*2+1];
4212 // This word of the result is all undef, skip it.
4213 if (Elt0 < 0 && Elt1 < 0)
4216 // This word of the result is already in the correct place, skip it.
4217 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1))
4219 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17))
4222 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
4223 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
4226 // If Elt0 and Elt1 are defined, are consecutive, and can be load
4227 // using a single extract together, load it and store it.
4228 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
4229 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
4230 DAG.getIntPtrConstant(Elt1 / 2));
4231 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
4232 DAG.getIntPtrConstant(i));
4236 // If Elt1 is defined, extract it from the appropriate source. If the
4237 // source byte is not also odd, shift the extracted word left 8 bits
4238 // otherwise clear the bottom 8 bits if we need to do an or.
4240 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
4241 DAG.getIntPtrConstant(Elt1 / 2));
4242 if ((Elt1 & 1) == 0)
4243 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
4244 DAG.getConstant(8, TLI.getShiftAmountTy()));
4246 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
4247 DAG.getConstant(0xFF00, MVT::i16));
4249 // If Elt0 is defined, extract it from the appropriate source. If the
4250 // source byte is not also even, shift the extracted word right 8 bits. If
4251 // Elt1 was also defined, OR the extracted values together before
4252 // inserting them in the result.
4254 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
4255 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
4256 if ((Elt0 & 1) != 0)
4257 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
4258 DAG.getConstant(8, TLI.getShiftAmountTy()));
4260 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
4261 DAG.getConstant(0x00FF, MVT::i16));
4262 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
4265 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
4266 DAG.getIntPtrConstant(i));
4268 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, NewV);
4271 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
4272 /// ones, or rewriting v4i32 / v2f32 as 2 wide ones if possible. This can be
4273 /// done when every pair / quad of shuffle mask elements point to elements in
4274 /// the right sequence. e.g.
4275 /// vector_shuffle <>, <>, < 3, 4, | 10, 11, | 0, 1, | 14, 15>
4277 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
4279 TargetLowering &TLI, DebugLoc dl) {
4280 EVT VT = SVOp->getValueType(0);
4281 SDValue V1 = SVOp->getOperand(0);
4282 SDValue V2 = SVOp->getOperand(1);
4283 unsigned NumElems = VT.getVectorNumElements();
4284 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
4285 EVT MaskVT = MVT::getIntVectorWithNumElements(NewWidth);
4286 EVT MaskEltVT = MaskVT.getVectorElementType();
4288 switch (VT.getSimpleVT().SimpleTy) {
4289 default: assert(false && "Unexpected!");
4290 case MVT::v4f32: NewVT = MVT::v2f64; break;
4291 case MVT::v4i32: NewVT = MVT::v2i64; break;
4292 case MVT::v8i16: NewVT = MVT::v4i32; break;
4293 case MVT::v16i8: NewVT = MVT::v4i32; break;
4296 if (NewWidth == 2) {
4302 int Scale = NumElems / NewWidth;
4303 SmallVector<int, 8> MaskVec;
4304 for (unsigned i = 0; i < NumElems; i += Scale) {
4306 for (int j = 0; j < Scale; ++j) {
4307 int EltIdx = SVOp->getMaskElt(i+j);
4311 StartIdx = EltIdx - (EltIdx % Scale);
4312 if (EltIdx != StartIdx + j)
4316 MaskVec.push_back(-1);
4318 MaskVec.push_back(StartIdx / Scale);
4321 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V1);
4322 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V2);
4323 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
4326 /// getVZextMovL - Return a zero-extending vector move low node.
4328 static SDValue getVZextMovL(EVT VT, EVT OpVT,
4329 SDValue SrcOp, SelectionDAG &DAG,
4330 const X86Subtarget *Subtarget, DebugLoc dl) {
4331 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
4332 LoadSDNode *LD = NULL;
4333 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
4334 LD = dyn_cast<LoadSDNode>(SrcOp);
4336 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
4338 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
4339 if ((ExtVT.SimpleTy != MVT::i64 || Subtarget->is64Bit()) &&
4340 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
4341 SrcOp.getOperand(0).getOpcode() == ISD::BIT_CONVERT &&
4342 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
4344 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
4345 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4346 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
4347 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
4355 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4356 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
4357 DAG.getNode(ISD::BIT_CONVERT, dl,
4361 /// LowerVECTOR_SHUFFLE_4wide - Handle all 4 wide cases with a number of
4364 LowerVECTOR_SHUFFLE_4wide(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
4365 SDValue V1 = SVOp->getOperand(0);
4366 SDValue V2 = SVOp->getOperand(1);
4367 DebugLoc dl = SVOp->getDebugLoc();
4368 EVT VT = SVOp->getValueType(0);
4370 SmallVector<std::pair<int, int>, 8> Locs;
4372 SmallVector<int, 8> Mask1(4U, -1);
4373 SmallVector<int, 8> PermMask;
4374 SVOp->getMask(PermMask);
4378 for (unsigned i = 0; i != 4; ++i) {
4379 int Idx = PermMask[i];
4381 Locs[i] = std::make_pair(-1, -1);
4383 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
4385 Locs[i] = std::make_pair(0, NumLo);
4389 Locs[i] = std::make_pair(1, NumHi);
4391 Mask1[2+NumHi] = Idx;
4397 if (NumLo <= 2 && NumHi <= 2) {
4398 // If no more than two elements come from either vector. This can be
4399 // implemented with two shuffles. First shuffle gather the elements.
4400 // The second shuffle, which takes the first shuffle as both of its
4401 // vector operands, put the elements into the right order.
4402 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
4404 SmallVector<int, 8> Mask2(4U, -1);
4406 for (unsigned i = 0; i != 4; ++i) {
4407 if (Locs[i].first == -1)
4410 unsigned Idx = (i < 2) ? 0 : 4;
4411 Idx += Locs[i].first * 2 + Locs[i].second;
4416 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
4417 } else if (NumLo == 3 || NumHi == 3) {
4418 // Otherwise, we must have three elements from one vector, call it X, and
4419 // one element from the other, call it Y. First, use a shufps to build an
4420 // intermediate vector with the one element from Y and the element from X
4421 // that will be in the same half in the final destination (the indexes don't
4422 // matter). Then, use a shufps to build the final vector, taking the half
4423 // containing the element from Y from the intermediate, and the other half
4426 // Normalize it so the 3 elements come from V1.
4427 CommuteVectorShuffleMask(PermMask, VT);
4431 // Find the element from V2.
4433 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
4434 int Val = PermMask[HiIndex];
4441 Mask1[0] = PermMask[HiIndex];
4443 Mask1[2] = PermMask[HiIndex^1];
4445 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
4448 Mask1[0] = PermMask[0];
4449 Mask1[1] = PermMask[1];
4450 Mask1[2] = HiIndex & 1 ? 6 : 4;
4451 Mask1[3] = HiIndex & 1 ? 4 : 6;
4452 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
4454 Mask1[0] = HiIndex & 1 ? 2 : 0;
4455 Mask1[1] = HiIndex & 1 ? 0 : 2;
4456 Mask1[2] = PermMask[2];
4457 Mask1[3] = PermMask[3];
4462 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
4466 // Break it into (shuffle shuffle_hi, shuffle_lo).
4468 SmallVector<int,8> LoMask(4U, -1);
4469 SmallVector<int,8> HiMask(4U, -1);
4471 SmallVector<int,8> *MaskPtr = &LoMask;
4472 unsigned MaskIdx = 0;
4475 for (unsigned i = 0; i != 4; ++i) {
4482 int Idx = PermMask[i];
4484 Locs[i] = std::make_pair(-1, -1);
4485 } else if (Idx < 4) {
4486 Locs[i] = std::make_pair(MaskIdx, LoIdx);
4487 (*MaskPtr)[LoIdx] = Idx;
4490 Locs[i] = std::make_pair(MaskIdx, HiIdx);
4491 (*MaskPtr)[HiIdx] = Idx;
4496 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
4497 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
4498 SmallVector<int, 8> MaskOps;
4499 for (unsigned i = 0; i != 4; ++i) {
4500 if (Locs[i].first == -1) {
4501 MaskOps.push_back(-1);
4503 unsigned Idx = Locs[i].first * 4 + Locs[i].second;
4504 MaskOps.push_back(Idx);
4507 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
4511 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
4512 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
4513 SDValue V1 = Op.getOperand(0);
4514 SDValue V2 = Op.getOperand(1);
4515 EVT VT = Op.getValueType();
4516 DebugLoc dl = Op.getDebugLoc();
4517 unsigned NumElems = VT.getVectorNumElements();
4518 bool isMMX = VT.getSizeInBits() == 64;
4519 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
4520 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
4521 bool V1IsSplat = false;
4522 bool V2IsSplat = false;
4524 if (isZeroShuffle(SVOp))
4525 return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
4527 // Promote splats to v4f32.
4528 if (SVOp->isSplat()) {
4529 if (isMMX || NumElems < 4)
4531 return PromoteSplat(SVOp, DAG, Subtarget->hasSSE2());
4534 // If the shuffle can be profitably rewritten as a narrower shuffle, then
4536 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
4537 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
4538 if (NewOp.getNode())
4539 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4540 LowerVECTOR_SHUFFLE(NewOp, DAG));
4541 } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
4542 // FIXME: Figure out a cleaner way to do this.
4543 // Try to make use of movq to zero out the top part.
4544 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
4545 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
4546 if (NewOp.getNode()) {
4547 if (isCommutedMOVL(cast<ShuffleVectorSDNode>(NewOp), true, false))
4548 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(0),
4549 DAG, Subtarget, dl);
4551 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
4552 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
4553 if (NewOp.getNode() && X86::isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)))
4554 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1),
4555 DAG, Subtarget, dl);
4559 if (X86::isPSHUFDMask(SVOp))
4562 // Check if this can be converted into a logical shift.
4563 bool isLeft = false;
4566 bool isShift = getSubtarget()->hasSSE2() &&
4567 isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
4568 if (isShift && ShVal.hasOneUse()) {
4569 // If the shifted value has multiple uses, it may be cheaper to use
4570 // v_set0 + movlhps or movhlps, etc.
4571 EVT EltVT = VT.getVectorElementType();
4572 ShAmt *= EltVT.getSizeInBits();
4573 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
4576 if (X86::isMOVLMask(SVOp)) {
4579 if (ISD::isBuildVectorAllZeros(V1.getNode()))
4580 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
4585 // FIXME: fold these into legal mask.
4586 if (!isMMX && (X86::isMOVSHDUPMask(SVOp) ||
4587 X86::isMOVSLDUPMask(SVOp) ||
4588 X86::isMOVHLPSMask(SVOp) ||
4589 X86::isMOVLHPSMask(SVOp) ||
4590 X86::isMOVLPMask(SVOp)))
4593 if (ShouldXformToMOVHLPS(SVOp) ||
4594 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp))
4595 return CommuteVectorShuffle(SVOp, DAG);
4598 // No better options. Use a vshl / vsrl.
4599 EVT EltVT = VT.getVectorElementType();
4600 ShAmt *= EltVT.getSizeInBits();
4601 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
4604 bool Commuted = false;
4605 // FIXME: This should also accept a bitcast of a splat? Be careful, not
4606 // 1,1,1,1 -> v8i16 though.
4607 V1IsSplat = isSplatVector(V1.getNode());
4608 V2IsSplat = isSplatVector(V2.getNode());
4610 // Canonicalize the splat or undef, if present, to be on the RHS.
4611 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
4612 Op = CommuteVectorShuffle(SVOp, DAG);
4613 SVOp = cast<ShuffleVectorSDNode>(Op);
4614 V1 = SVOp->getOperand(0);
4615 V2 = SVOp->getOperand(1);
4616 std::swap(V1IsSplat, V2IsSplat);
4617 std::swap(V1IsUndef, V2IsUndef);
4621 if (isCommutedMOVL(SVOp, V2IsSplat, V2IsUndef)) {
4622 // Shuffling low element of v1 into undef, just return v1.
4625 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
4626 // the instruction selector will not match, so get a canonical MOVL with
4627 // swapped operands to undo the commute.
4628 return getMOVL(DAG, dl, VT, V2, V1);
4631 if (X86::isUNPCKL_v_undef_Mask(SVOp) ||
4632 X86::isUNPCKH_v_undef_Mask(SVOp) ||
4633 X86::isUNPCKLMask(SVOp) ||
4634 X86::isUNPCKHMask(SVOp))
4638 // Normalize mask so all entries that point to V2 points to its first
4639 // element then try to match unpck{h|l} again. If match, return a
4640 // new vector_shuffle with the corrected mask.
4641 SDValue NewMask = NormalizeMask(SVOp, DAG);
4642 ShuffleVectorSDNode *NSVOp = cast<ShuffleVectorSDNode>(NewMask);
4643 if (NSVOp != SVOp) {
4644 if (X86::isUNPCKLMask(NSVOp, true)) {
4646 } else if (X86::isUNPCKHMask(NSVOp, true)) {
4653 // Commute is back and try unpck* again.
4654 // FIXME: this seems wrong.
4655 SDValue NewOp = CommuteVectorShuffle(SVOp, DAG);
4656 ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp);
4657 if (X86::isUNPCKL_v_undef_Mask(NewSVOp) ||
4658 X86::isUNPCKH_v_undef_Mask(NewSVOp) ||
4659 X86::isUNPCKLMask(NewSVOp) ||
4660 X86::isUNPCKHMask(NewSVOp))
4664 // FIXME: for mmx, bitcast v2i32 to v4i16 for shuffle.
4666 // Normalize the node to match x86 shuffle ops if needed
4667 if (!isMMX && V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(SVOp))
4668 return CommuteVectorShuffle(SVOp, DAG);
4670 // Check for legal shuffle and return?
4671 SmallVector<int, 16> PermMask;
4672 SVOp->getMask(PermMask);
4673 if (isShuffleMaskLegal(PermMask, VT))
4676 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
4677 if (VT == MVT::v8i16) {
4678 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(SVOp, DAG, *this);
4679 if (NewOp.getNode())
4683 if (VT == MVT::v16i8) {
4684 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
4685 if (NewOp.getNode())
4689 // Handle all 4 wide cases with a number of shuffles except for MMX.
4690 if (NumElems == 4 && !isMMX)
4691 return LowerVECTOR_SHUFFLE_4wide(SVOp, DAG);
4697 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
4698 SelectionDAG &DAG) {
4699 EVT VT = Op.getValueType();
4700 DebugLoc dl = Op.getDebugLoc();
4701 if (VT.getSizeInBits() == 8) {
4702 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
4703 Op.getOperand(0), Op.getOperand(1));
4704 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
4705 DAG.getValueType(VT));
4706 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
4707 } else if (VT.getSizeInBits() == 16) {
4708 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4709 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
4711 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
4712 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4713 DAG.getNode(ISD::BIT_CONVERT, dl,
4717 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
4718 Op.getOperand(0), Op.getOperand(1));
4719 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
4720 DAG.getValueType(VT));
4721 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
4722 } else if (VT == MVT::f32) {
4723 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
4724 // the result back to FR32 register. It's only worth matching if the
4725 // result has a single use which is a store or a bitcast to i32. And in
4726 // the case of a store, it's not worth it if the index is a constant 0,
4727 // because a MOVSSmr can be used instead, which is smaller and faster.
4728 if (!Op.hasOneUse())
4730 SDNode *User = *Op.getNode()->use_begin();
4731 if ((User->getOpcode() != ISD::STORE ||
4732 (isa<ConstantSDNode>(Op.getOperand(1)) &&
4733 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
4734 (User->getOpcode() != ISD::BIT_CONVERT ||
4735 User->getValueType(0) != MVT::i32))
4737 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4738 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32,
4741 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Extract);
4742 } else if (VT == MVT::i32) {
4743 // ExtractPS works with constant index.
4744 if (isa<ConstantSDNode>(Op.getOperand(1)))
4752 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
4753 if (!isa<ConstantSDNode>(Op.getOperand(1)))
4756 if (Subtarget->hasSSE41()) {
4757 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
4762 EVT VT = Op.getValueType();
4763 DebugLoc dl = Op.getDebugLoc();
4764 // TODO: handle v16i8.
4765 if (VT.getSizeInBits() == 16) {
4766 SDValue Vec = Op.getOperand(0);
4767 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4769 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
4770 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4771 DAG.getNode(ISD::BIT_CONVERT, dl,
4774 // Transform it so it match pextrw which produces a 32-bit result.
4775 EVT EltVT = MVT::i32;
4776 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
4777 Op.getOperand(0), Op.getOperand(1));
4778 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
4779 DAG.getValueType(VT));
4780 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
4781 } else if (VT.getSizeInBits() == 32) {
4782 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4786 // SHUFPS the element to the lowest double word, then movss.
4787 int Mask[4] = { Idx, -1, -1, -1 };
4788 EVT VVT = Op.getOperand(0).getValueType();
4789 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
4790 DAG.getUNDEF(VVT), Mask);
4791 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
4792 DAG.getIntPtrConstant(0));
4793 } else if (VT.getSizeInBits() == 64) {
4794 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
4795 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
4796 // to match extract_elt for f64.
4797 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4801 // UNPCKHPD the element to the lowest double word, then movsd.
4802 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
4803 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
4804 int Mask[2] = { 1, -1 };
4805 EVT VVT = Op.getOperand(0).getValueType();
4806 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
4807 DAG.getUNDEF(VVT), Mask);
4808 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
4809 DAG.getIntPtrConstant(0));
4816 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG){
4817 EVT VT = Op.getValueType();
4818 EVT EltVT = VT.getVectorElementType();
4819 DebugLoc dl = Op.getDebugLoc();
4821 SDValue N0 = Op.getOperand(0);
4822 SDValue N1 = Op.getOperand(1);
4823 SDValue N2 = Op.getOperand(2);
4825 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
4826 isa<ConstantSDNode>(N2)) {
4828 if (VT == MVT::v8i16)
4829 Opc = X86ISD::PINSRW;
4830 else if (VT == MVT::v4i16)
4831 Opc = X86ISD::MMX_PINSRW;
4832 else if (VT == MVT::v16i8)
4833 Opc = X86ISD::PINSRB;
4835 Opc = X86ISD::PINSRB;
4837 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
4839 if (N1.getValueType() != MVT::i32)
4840 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
4841 if (N2.getValueType() != MVT::i32)
4842 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
4843 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
4844 } else if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
4845 // Bits [7:6] of the constant are the source select. This will always be
4846 // zero here. The DAG Combiner may combine an extract_elt index into these
4847 // bits. For example (insert (extract, 3), 2) could be matched by putting
4848 // the '3' into bits [7:6] of X86ISD::INSERTPS.
4849 // Bits [5:4] of the constant are the destination select. This is the
4850 // value of the incoming immediate.
4851 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
4852 // combine either bitwise AND or insert of float 0.0 to set these bits.
4853 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
4854 // Create this as a scalar to vector..
4855 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
4856 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
4857 } else if (EltVT == MVT::i32 && isa<ConstantSDNode>(N2)) {
4858 // PINSR* works with constant index.
4865 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
4866 EVT VT = Op.getValueType();
4867 EVT EltVT = VT.getVectorElementType();
4869 if (Subtarget->hasSSE41())
4870 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
4872 if (EltVT == MVT::i8)
4875 DebugLoc dl = Op.getDebugLoc();
4876 SDValue N0 = Op.getOperand(0);
4877 SDValue N1 = Op.getOperand(1);
4878 SDValue N2 = Op.getOperand(2);
4880 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
4881 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
4882 // as its second argument.
4883 if (N1.getValueType() != MVT::i32)
4884 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
4885 if (N2.getValueType() != MVT::i32)
4886 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
4887 return DAG.getNode(VT == MVT::v8i16 ? X86ISD::PINSRW : X86ISD::MMX_PINSRW,
4888 dl, VT, N0, N1, N2);
4894 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
4895 DebugLoc dl = Op.getDebugLoc();
4896 if (Op.getValueType() == MVT::v2f32)
4897 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f32,
4898 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i32,
4899 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32,
4900 Op.getOperand(0))));
4902 if (Op.getValueType() == MVT::v1i64 && Op.getOperand(0).getValueType() == MVT::i64)
4903 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
4905 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
4906 EVT VT = MVT::v2i32;
4907 switch (Op.getValueType().getSimpleVT().SimpleTy) {
4914 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(),
4915 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, AnyExt));
4918 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
4919 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
4920 // one of the above mentioned nodes. It has to be wrapped because otherwise
4921 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
4922 // be used to form addressing mode. These wrapped nodes will be selected
4925 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
4926 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
4928 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
4930 unsigned char OpFlag = 0;
4931 unsigned WrapperKind = X86ISD::Wrapper;
4932 CodeModel::Model M = getTargetMachine().getCodeModel();
4934 if (Subtarget->isPICStyleRIPRel() &&
4935 (M == CodeModel::Small || M == CodeModel::Kernel))
4936 WrapperKind = X86ISD::WrapperRIP;
4937 else if (Subtarget->isPICStyleGOT())
4938 OpFlag = X86II::MO_GOTOFF;
4939 else if (Subtarget->isPICStyleStubPIC())
4940 OpFlag = X86II::MO_PIC_BASE_OFFSET;
4942 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
4944 CP->getOffset(), OpFlag);
4945 DebugLoc DL = CP->getDebugLoc();
4946 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
4947 // With PIC, the address is actually $g + Offset.
4949 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
4950 DAG.getNode(X86ISD::GlobalBaseReg,
4951 DebugLoc::getUnknownLoc(), getPointerTy()),
4958 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) {
4959 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
4961 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
4963 unsigned char OpFlag = 0;
4964 unsigned WrapperKind = X86ISD::Wrapper;
4965 CodeModel::Model M = getTargetMachine().getCodeModel();
4967 if (Subtarget->isPICStyleRIPRel() &&
4968 (M == CodeModel::Small || M == CodeModel::Kernel))
4969 WrapperKind = X86ISD::WrapperRIP;
4970 else if (Subtarget->isPICStyleGOT())
4971 OpFlag = X86II::MO_GOTOFF;
4972 else if (Subtarget->isPICStyleStubPIC())
4973 OpFlag = X86II::MO_PIC_BASE_OFFSET;
4975 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
4977 DebugLoc DL = JT->getDebugLoc();
4978 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
4980 // With PIC, the address is actually $g + Offset.
4982 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
4983 DAG.getNode(X86ISD::GlobalBaseReg,
4984 DebugLoc::getUnknownLoc(), getPointerTy()),
4992 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) {
4993 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
4995 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
4997 unsigned char OpFlag = 0;
4998 unsigned WrapperKind = X86ISD::Wrapper;
4999 CodeModel::Model M = getTargetMachine().getCodeModel();
5001 if (Subtarget->isPICStyleRIPRel() &&
5002 (M == CodeModel::Small || M == CodeModel::Kernel))
5003 WrapperKind = X86ISD::WrapperRIP;
5004 else if (Subtarget->isPICStyleGOT())
5005 OpFlag = X86II::MO_GOTOFF;
5006 else if (Subtarget->isPICStyleStubPIC())
5007 OpFlag = X86II::MO_PIC_BASE_OFFSET;
5009 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
5011 DebugLoc DL = Op.getDebugLoc();
5012 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
5015 // With PIC, the address is actually $g + Offset.
5016 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
5017 !Subtarget->is64Bit()) {
5018 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
5019 DAG.getNode(X86ISD::GlobalBaseReg,
5020 DebugLoc::getUnknownLoc(),
5029 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) {
5030 // Create the TargetBlockAddressAddress node.
5031 unsigned char OpFlags =
5032 Subtarget->ClassifyBlockAddressReference();
5033 CodeModel::Model M = getTargetMachine().getCodeModel();
5034 BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
5035 DebugLoc dl = Op.getDebugLoc();
5036 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(),
5037 /*isTarget=*/true, OpFlags);
5039 if (Subtarget->isPICStyleRIPRel() &&
5040 (M == CodeModel::Small || M == CodeModel::Kernel))
5041 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
5043 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
5045 // With PIC, the address is actually $g + Offset.
5046 if (isGlobalRelativeToPICBase(OpFlags)) {
5047 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
5048 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
5056 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
5058 SelectionDAG &DAG) const {
5059 // Create the TargetGlobalAddress node, folding in the constant
5060 // offset if it is legal.
5061 unsigned char OpFlags =
5062 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
5063 CodeModel::Model M = getTargetMachine().getCodeModel();
5065 if (OpFlags == X86II::MO_NO_FLAG &&
5066 X86::isOffsetSuitableForCodeModel(Offset, M)) {
5067 // A direct static reference to a global.
5068 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), Offset);
5071 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), 0, OpFlags);
5074 if (Subtarget->isPICStyleRIPRel() &&
5075 (M == CodeModel::Small || M == CodeModel::Kernel))
5076 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
5078 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
5080 // With PIC, the address is actually $g + Offset.
5081 if (isGlobalRelativeToPICBase(OpFlags)) {
5082 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
5083 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
5087 // For globals that require a load from a stub to get the address, emit the
5089 if (isGlobalStubReference(OpFlags))
5090 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
5091 PseudoSourceValue::getGOT(), 0, false, false, 0);
5093 // If there was a non-zero offset that we didn't fold, create an explicit
5096 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
5097 DAG.getConstant(Offset, getPointerTy()));
5103 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) {
5104 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
5105 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
5106 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
5110 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
5111 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
5112 unsigned char OperandFlags) {
5113 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5114 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
5115 DebugLoc dl = GA->getDebugLoc();
5116 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
5117 GA->getValueType(0),
5121 SDValue Ops[] = { Chain, TGA, *InFlag };
5122 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3);
5124 SDValue Ops[] = { Chain, TGA };
5125 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2);
5128 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
5129 MFI->setHasCalls(true);
5131 SDValue Flag = Chain.getValue(1);
5132 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
5135 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
5137 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
5140 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
5141 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
5142 DAG.getNode(X86ISD::GlobalBaseReg,
5143 DebugLoc::getUnknownLoc(),
5145 InFlag = Chain.getValue(1);
5147 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
5150 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
5152 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
5154 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
5155 X86::RAX, X86II::MO_TLSGD);
5158 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
5159 // "local exec" model.
5160 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
5161 const EVT PtrVT, TLSModel::Model model,
5163 DebugLoc dl = GA->getDebugLoc();
5164 // Get the Thread Pointer
5165 SDValue Base = DAG.getNode(X86ISD::SegmentBaseAddress,
5166 DebugLoc::getUnknownLoc(), PtrVT,
5167 DAG.getRegister(is64Bit? X86::FS : X86::GS,
5170 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Base,
5171 NULL, 0, false, false, 0);
5173 unsigned char OperandFlags = 0;
5174 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
5176 unsigned WrapperKind = X86ISD::Wrapper;
5177 if (model == TLSModel::LocalExec) {
5178 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
5179 } else if (is64Bit) {
5180 assert(model == TLSModel::InitialExec);
5181 OperandFlags = X86II::MO_GOTTPOFF;
5182 WrapperKind = X86ISD::WrapperRIP;
5184 assert(model == TLSModel::InitialExec);
5185 OperandFlags = X86II::MO_INDNTPOFF;
5188 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
5190 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0),
5191 GA->getOffset(), OperandFlags);
5192 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
5194 if (model == TLSModel::InitialExec)
5195 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
5196 PseudoSourceValue::getGOT(), 0, false, false, 0);
5198 // The address of the thread local variable is the add of the thread
5199 // pointer with the offset of the variable.
5200 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
5204 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) {
5205 // TODO: implement the "local dynamic" model
5206 // TODO: implement the "initial exec"model for pic executables
5207 assert(Subtarget->isTargetELF() &&
5208 "TLS not implemented for non-ELF targets");
5209 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
5210 const GlobalValue *GV = GA->getGlobal();
5212 // If GV is an alias then use the aliasee for determining
5213 // thread-localness.
5214 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
5215 GV = GA->resolveAliasedGlobal(false);
5217 TLSModel::Model model = getTLSModel(GV,
5218 getTargetMachine().getRelocationModel());
5221 case TLSModel::GeneralDynamic:
5222 case TLSModel::LocalDynamic: // not implemented
5223 if (Subtarget->is64Bit())
5224 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
5225 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
5227 case TLSModel::InitialExec:
5228 case TLSModel::LocalExec:
5229 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
5230 Subtarget->is64Bit());
5233 llvm_unreachable("Unreachable");
5238 /// LowerShift - Lower SRA_PARTS and friends, which return two i32 values and
5239 /// take a 2 x i32 value to shift plus a shift amount.
5240 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) {
5241 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
5242 EVT VT = Op.getValueType();
5243 unsigned VTBits = VT.getSizeInBits();
5244 DebugLoc dl = Op.getDebugLoc();
5245 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
5246 SDValue ShOpLo = Op.getOperand(0);
5247 SDValue ShOpHi = Op.getOperand(1);
5248 SDValue ShAmt = Op.getOperand(2);
5249 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
5250 DAG.getConstant(VTBits - 1, MVT::i8))
5251 : DAG.getConstant(0, VT);
5254 if (Op.getOpcode() == ISD::SHL_PARTS) {
5255 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
5256 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
5258 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
5259 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
5262 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
5263 DAG.getConstant(VTBits, MVT::i8));
5264 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
5265 AndNode, DAG.getConstant(0, MVT::i8));
5268 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
5269 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
5270 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
5272 if (Op.getOpcode() == ISD::SHL_PARTS) {
5273 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
5274 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
5276 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
5277 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
5280 SDValue Ops[2] = { Lo, Hi };
5281 return DAG.getMergeValues(Ops, 2, dl);
5284 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
5285 EVT SrcVT = Op.getOperand(0).getValueType();
5287 if (SrcVT.isVector()) {
5288 if (SrcVT == MVT::v2i32 && Op.getValueType() == MVT::v2f64) {
5294 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
5295 "Unknown SINT_TO_FP to lower!");
5297 // These are really Legal; return the operand so the caller accepts it as
5299 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
5301 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
5302 Subtarget->is64Bit()) {
5306 DebugLoc dl = Op.getDebugLoc();
5307 unsigned Size = SrcVT.getSizeInBits()/8;
5308 MachineFunction &MF = DAG.getMachineFunction();
5309 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
5310 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5311 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
5313 PseudoSourceValue::getFixedStack(SSFI), 0,
5315 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
5318 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
5320 SelectionDAG &DAG) {
5322 DebugLoc dl = Op.getDebugLoc();
5324 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
5326 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag);
5328 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
5329 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
5330 SDValue Result = DAG.getNode(useSSE ? X86ISD::FILD_FLAG : X86ISD::FILD, dl,
5331 Tys, Ops, array_lengthof(Ops));
5334 Chain = Result.getValue(1);
5335 SDValue InFlag = Result.getValue(2);
5337 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
5338 // shouldn't be necessary except that RFP cannot be live across
5339 // multiple blocks. When stackifier is fixed, they can be uncoupled.
5340 MachineFunction &MF = DAG.getMachineFunction();
5341 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
5342 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5343 Tys = DAG.getVTList(MVT::Other);
5345 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
5347 Chain = DAG.getNode(X86ISD::FST, dl, Tys, Ops, array_lengthof(Ops));
5348 Result = DAG.getLoad(Op.getValueType(), dl, Chain, StackSlot,
5349 PseudoSourceValue::getFixedStack(SSFI), 0,
5356 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
5357 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) {
5358 // This algorithm is not obvious. Here it is in C code, more or less:
5360 double uint64_to_double( uint32_t hi, uint32_t lo ) {
5361 static const __m128i exp = { 0x4330000045300000ULL, 0 };
5362 static const __m128d bias = { 0x1.0p84, 0x1.0p52 };
5364 // Copy ints to xmm registers.
5365 __m128i xh = _mm_cvtsi32_si128( hi );
5366 __m128i xl = _mm_cvtsi32_si128( lo );
5368 // Combine into low half of a single xmm register.
5369 __m128i x = _mm_unpacklo_epi32( xh, xl );
5373 // Merge in appropriate exponents to give the integer bits the right
5375 x = _mm_unpacklo_epi32( x, exp );
5377 // Subtract away the biases to deal with the IEEE-754 double precision
5379 d = _mm_sub_pd( (__m128d) x, bias );
5381 // All conversions up to here are exact. The correctly rounded result is
5382 // calculated using the current rounding mode using the following
5384 d = _mm_add_sd( d, _mm_unpackhi_pd( d, d ) );
5385 _mm_store_sd( &sd, d ); // Because we are returning doubles in XMM, this
5386 // store doesn't really need to be here (except
5387 // maybe to zero the other double)
5392 DebugLoc dl = Op.getDebugLoc();
5393 LLVMContext *Context = DAG.getContext();
5395 // Build some magic constants.
5396 std::vector<Constant*> CV0;
5397 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x45300000)));
5398 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x43300000)));
5399 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
5400 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
5401 Constant *C0 = ConstantVector::get(CV0);
5402 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
5404 std::vector<Constant*> CV1;
5406 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL))));
5408 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL))));
5409 Constant *C1 = ConstantVector::get(CV1);
5410 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
5412 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
5413 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
5415 DAG.getIntPtrConstant(1)));
5416 SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
5417 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
5419 DAG.getIntPtrConstant(0)));
5420 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, XR1, XR2);
5421 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
5422 PseudoSourceValue::getConstantPool(), 0,
5424 SDValue Unpck2 = getUnpackl(DAG, dl, MVT::v4i32, Unpck1, CLod0);
5425 SDValue XR2F = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Unpck2);
5426 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
5427 PseudoSourceValue::getConstantPool(), 0,
5429 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
5431 // Add the halves; easiest way is to swap them into another reg first.
5432 int ShufMask[2] = { 1, -1 };
5433 SDValue Shuf = DAG.getVectorShuffle(MVT::v2f64, dl, Sub,
5434 DAG.getUNDEF(MVT::v2f64), ShufMask);
5435 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuf, Sub);
5436 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Add,
5437 DAG.getIntPtrConstant(0));
5440 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
5441 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) {
5442 DebugLoc dl = Op.getDebugLoc();
5443 // FP constant to bias correct the final result.
5444 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
5447 // Load the 32-bit value into an XMM register.
5448 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
5449 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
5451 DAG.getIntPtrConstant(0)));
5453 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
5454 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Load),
5455 DAG.getIntPtrConstant(0));
5457 // Or the load with the bias.
5458 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
5459 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
5460 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5462 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
5463 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5464 MVT::v2f64, Bias)));
5465 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
5466 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Or),
5467 DAG.getIntPtrConstant(0));
5469 // Subtract the bias.
5470 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
5472 // Handle final rounding.
5473 EVT DestVT = Op.getValueType();
5475 if (DestVT.bitsLT(MVT::f64)) {
5476 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
5477 DAG.getIntPtrConstant(0));
5478 } else if (DestVT.bitsGT(MVT::f64)) {
5479 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
5482 // Handle final rounding.
5486 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
5487 SDValue N0 = Op.getOperand(0);
5488 DebugLoc dl = Op.getDebugLoc();
5490 // Now not UINT_TO_FP is legal (it's marked custom), dag combiner won't
5491 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
5492 // the optimization here.
5493 if (DAG.SignBitIsZero(N0))
5494 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
5496 EVT SrcVT = N0.getValueType();
5497 if (SrcVT == MVT::i64) {
5498 // We only handle SSE2 f64 target here; caller can expand the rest.
5499 if (Op.getValueType() != MVT::f64 || !X86ScalarSSEf64)
5502 return LowerUINT_TO_FP_i64(Op, DAG);
5503 } else if (SrcVT == MVT::i32 && X86ScalarSSEf64) {
5504 return LowerUINT_TO_FP_i32(Op, DAG);
5507 assert(SrcVT == MVT::i32 && "Unknown UINT_TO_FP to lower!");
5509 // Make a 64-bit buffer, and use it to build an FILD.
5510 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
5511 SDValue WordOff = DAG.getConstant(4, getPointerTy());
5512 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
5513 getPointerTy(), StackSlot, WordOff);
5514 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
5515 StackSlot, NULL, 0, false, false, 0);
5516 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
5517 OffsetSlot, NULL, 0, false, false, 0);
5518 return BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
5521 std::pair<SDValue,SDValue> X86TargetLowering::
5522 FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) {
5523 DebugLoc dl = Op.getDebugLoc();
5525 EVT DstTy = Op.getValueType();
5528 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
5532 assert(DstTy.getSimpleVT() <= MVT::i64 &&
5533 DstTy.getSimpleVT() >= MVT::i16 &&
5534 "Unknown FP_TO_SINT to lower!");
5536 // These are really Legal.
5537 if (DstTy == MVT::i32 &&
5538 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
5539 return std::make_pair(SDValue(), SDValue());
5540 if (Subtarget->is64Bit() &&
5541 DstTy == MVT::i64 &&
5542 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
5543 return std::make_pair(SDValue(), SDValue());
5545 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
5547 MachineFunction &MF = DAG.getMachineFunction();
5548 unsigned MemSize = DstTy.getSizeInBits()/8;
5549 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
5550 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5553 switch (DstTy.getSimpleVT().SimpleTy) {
5554 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
5555 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
5556 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
5557 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
5560 SDValue Chain = DAG.getEntryNode();
5561 SDValue Value = Op.getOperand(0);
5562 if (isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) {
5563 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
5564 Chain = DAG.getStore(Chain, dl, Value, StackSlot,
5565 PseudoSourceValue::getFixedStack(SSFI), 0,
5567 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
5569 Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType())
5571 Value = DAG.getNode(X86ISD::FLD, dl, Tys, Ops, 3);
5572 Chain = Value.getValue(1);
5573 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
5574 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5577 // Build the FP_TO_INT*_IN_MEM
5578 SDValue Ops[] = { Chain, Value, StackSlot };
5579 SDValue FIST = DAG.getNode(Opc, dl, MVT::Other, Ops, 3);
5581 return std::make_pair(FIST, StackSlot);
5584 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) {
5585 if (Op.getValueType().isVector()) {
5586 if (Op.getValueType() == MVT::v2i32 &&
5587 Op.getOperand(0).getValueType() == MVT::v2f64) {
5593 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true);
5594 SDValue FIST = Vals.first, StackSlot = Vals.second;
5595 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
5596 if (FIST.getNode() == 0) return Op;
5599 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
5600 FIST, StackSlot, NULL, 0, false, false, 0);
5603 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) {
5604 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false);
5605 SDValue FIST = Vals.first, StackSlot = Vals.second;
5606 assert(FIST.getNode() && "Unexpected failure");
5609 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
5610 FIST, StackSlot, NULL, 0, false, false, 0);
5613 SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) {
5614 LLVMContext *Context = DAG.getContext();
5615 DebugLoc dl = Op.getDebugLoc();
5616 EVT VT = Op.getValueType();
5619 EltVT = VT.getVectorElementType();
5620 std::vector<Constant*> CV;
5621 if (EltVT == MVT::f64) {
5622 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))));
5626 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))));
5632 Constant *C = ConstantVector::get(CV);
5633 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5634 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5635 PseudoSourceValue::getConstantPool(), 0,
5637 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
5640 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) {
5641 LLVMContext *Context = DAG.getContext();
5642 DebugLoc dl = Op.getDebugLoc();
5643 EVT VT = Op.getValueType();
5646 EltVT = VT.getVectorElementType();
5647 std::vector<Constant*> CV;
5648 if (EltVT == MVT::f64) {
5649 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)));
5653 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)));
5659 Constant *C = ConstantVector::get(CV);
5660 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5661 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5662 PseudoSourceValue::getConstantPool(), 0,
5664 if (VT.isVector()) {
5665 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
5666 DAG.getNode(ISD::XOR, dl, MVT::v2i64,
5667 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
5669 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, Mask)));
5671 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
5675 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
5676 LLVMContext *Context = DAG.getContext();
5677 SDValue Op0 = Op.getOperand(0);
5678 SDValue Op1 = Op.getOperand(1);
5679 DebugLoc dl = Op.getDebugLoc();
5680 EVT VT = Op.getValueType();
5681 EVT SrcVT = Op1.getValueType();
5683 // If second operand is smaller, extend it first.
5684 if (SrcVT.bitsLT(VT)) {
5685 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
5688 // And if it is bigger, shrink it first.
5689 if (SrcVT.bitsGT(VT)) {
5690 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
5694 // At this point the operands and the result should have the same
5695 // type, and that won't be f80 since that is not custom lowered.
5697 // First get the sign bit of second operand.
5698 std::vector<Constant*> CV;
5699 if (SrcVT == MVT::f64) {
5700 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))));
5701 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
5703 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))));
5704 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5705 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5706 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5708 Constant *C = ConstantVector::get(CV);
5709 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5710 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
5711 PseudoSourceValue::getConstantPool(), 0,
5713 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
5715 // Shift sign bit right or left if the two operands have different types.
5716 if (SrcVT.bitsGT(VT)) {
5717 // Op0 is MVT::f32, Op1 is MVT::f64.
5718 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
5719 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
5720 DAG.getConstant(32, MVT::i32));
5721 SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4f32, SignBit);
5722 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
5723 DAG.getIntPtrConstant(0));
5726 // Clear first operand sign bit.
5728 if (VT == MVT::f64) {
5729 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
5730 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
5732 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
5733 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5734 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5735 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5737 C = ConstantVector::get(CV);
5738 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5739 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5740 PseudoSourceValue::getConstantPool(), 0,
5742 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
5744 // Or the value with the sign bit.
5745 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
5748 /// Emit nodes that will be selected as "test Op0,Op0", or something
5750 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
5751 SelectionDAG &DAG) {
5752 DebugLoc dl = Op.getDebugLoc();
5754 // CF and OF aren't always set the way we want. Determine which
5755 // of these we need.
5756 bool NeedCF = false;
5757 bool NeedOF = false;
5759 case X86::COND_A: case X86::COND_AE:
5760 case X86::COND_B: case X86::COND_BE:
5763 case X86::COND_G: case X86::COND_GE:
5764 case X86::COND_L: case X86::COND_LE:
5765 case X86::COND_O: case X86::COND_NO:
5771 // See if we can use the EFLAGS value from the operand instead of
5772 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
5773 // we prove that the arithmetic won't overflow, we can't use OF or CF.
5774 if (Op.getResNo() == 0 && !NeedOF && !NeedCF) {
5775 unsigned Opcode = 0;
5776 unsigned NumOperands = 0;
5777 switch (Op.getNode()->getOpcode()) {
5779 // Due to an isel shortcoming, be conservative if this add is likely to
5780 // be selected as part of a load-modify-store instruction. When the root
5781 // node in a match is a store, isel doesn't know how to remap non-chain
5782 // non-flag uses of other nodes in the match, such as the ADD in this
5783 // case. This leads to the ADD being left around and reselected, with
5784 // the result being two adds in the output.
5785 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
5786 UE = Op.getNode()->use_end(); UI != UE; ++UI)
5787 if (UI->getOpcode() == ISD::STORE)
5789 if (ConstantSDNode *C =
5790 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
5791 // An add of one will be selected as an INC.
5792 if (C->getAPIntValue() == 1) {
5793 Opcode = X86ISD::INC;
5797 // An add of negative one (subtract of one) will be selected as a DEC.
5798 if (C->getAPIntValue().isAllOnesValue()) {
5799 Opcode = X86ISD::DEC;
5804 // Otherwise use a regular EFLAGS-setting add.
5805 Opcode = X86ISD::ADD;
5809 // If the primary and result isn't used, don't bother using X86ISD::AND,
5810 // because a TEST instruction will be better.
5811 bool NonFlagUse = false;
5812 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
5813 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
5815 unsigned UOpNo = UI.getOperandNo();
5816 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
5817 // Look pass truncate.
5818 UOpNo = User->use_begin().getOperandNo();
5819 User = *User->use_begin();
5821 if (User->getOpcode() != ISD::BRCOND &&
5822 User->getOpcode() != ISD::SETCC &&
5823 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) {
5835 // Due to the ISEL shortcoming noted above, be conservative if this op is
5836 // likely to be selected as part of a load-modify-store instruction.
5837 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
5838 UE = Op.getNode()->use_end(); UI != UE; ++UI)
5839 if (UI->getOpcode() == ISD::STORE)
5841 // Otherwise use a regular EFLAGS-setting instruction.
5842 switch (Op.getNode()->getOpcode()) {
5843 case ISD::SUB: Opcode = X86ISD::SUB; break;
5844 case ISD::OR: Opcode = X86ISD::OR; break;
5845 case ISD::XOR: Opcode = X86ISD::XOR; break;
5846 case ISD::AND: Opcode = X86ISD::AND; break;
5847 default: llvm_unreachable("unexpected operator!");
5858 return SDValue(Op.getNode(), 1);
5864 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
5865 SmallVector<SDValue, 4> Ops;
5866 for (unsigned i = 0; i != NumOperands; ++i)
5867 Ops.push_back(Op.getOperand(i));
5868 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
5869 DAG.ReplaceAllUsesWith(Op, New);
5870 return SDValue(New.getNode(), 1);
5874 // Otherwise just emit a CMP with 0, which is the TEST pattern.
5875 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
5876 DAG.getConstant(0, Op.getValueType()));
5879 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
5881 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
5882 SelectionDAG &DAG) {
5883 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
5884 if (C->getAPIntValue() == 0)
5885 return EmitTest(Op0, X86CC, DAG);
5887 DebugLoc dl = Op0.getDebugLoc();
5888 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
5891 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
5892 /// if it's possible.
5893 static SDValue LowerToBT(SDValue And, ISD::CondCode CC,
5894 DebugLoc dl, SelectionDAG &DAG) {
5895 SDValue Op0 = And.getOperand(0);
5896 SDValue Op1 = And.getOperand(1);
5897 if (Op0.getOpcode() == ISD::TRUNCATE)
5898 Op0 = Op0.getOperand(0);
5899 if (Op1.getOpcode() == ISD::TRUNCATE)
5900 Op1 = Op1.getOperand(0);
5903 if (Op1.getOpcode() == ISD::SHL) {
5904 if (ConstantSDNode *And10C = dyn_cast<ConstantSDNode>(Op1.getOperand(0)))
5905 if (And10C->getZExtValue() == 1) {
5907 RHS = Op1.getOperand(1);
5909 } else if (Op0.getOpcode() == ISD::SHL) {
5910 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
5911 if (And00C->getZExtValue() == 1) {
5913 RHS = Op0.getOperand(1);
5915 } else if (Op1.getOpcode() == ISD::Constant) {
5916 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
5917 SDValue AndLHS = Op0;
5918 if (AndRHS->getZExtValue() == 1 && AndLHS.getOpcode() == ISD::SRL) {
5919 LHS = AndLHS.getOperand(0);
5920 RHS = AndLHS.getOperand(1);
5924 if (LHS.getNode()) {
5925 // If LHS is i8, promote it to i16 with any_extend. There is no i8 BT
5926 // instruction. Since the shift amount is in-range-or-undefined, we know
5927 // that doing a bittest on the i16 value is ok. We extend to i32 because
5928 // the encoding for the i16 version is larger than the i32 version.
5929 if (LHS.getValueType() == MVT::i8)
5930 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
5932 // If the operand types disagree, extend the shift amount to match. Since
5933 // BT ignores high bits (like shifts) we can use anyextend.
5934 if (LHS.getValueType() != RHS.getValueType())
5935 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
5937 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
5938 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
5939 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
5940 DAG.getConstant(Cond, MVT::i8), BT);
5946 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) {
5947 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
5948 SDValue Op0 = Op.getOperand(0);
5949 SDValue Op1 = Op.getOperand(1);
5950 DebugLoc dl = Op.getDebugLoc();
5951 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
5953 // Optimize to BT if possible.
5954 // Lower (X & (1 << N)) == 0 to BT(X, N).
5955 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
5956 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
5957 if (Op0.getOpcode() == ISD::AND &&
5959 Op1.getOpcode() == ISD::Constant &&
5960 cast<ConstantSDNode>(Op1)->getZExtValue() == 0 &&
5961 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
5962 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
5963 if (NewSetCC.getNode())
5967 // Look for "(setcc) == / != 1" to avoid unncessary setcc.
5968 if (Op0.getOpcode() == X86ISD::SETCC &&
5969 Op1.getOpcode() == ISD::Constant &&
5970 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
5971 cast<ConstantSDNode>(Op1)->isNullValue()) &&
5972 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
5973 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
5974 bool Invert = (CC == ISD::SETNE) ^
5975 cast<ConstantSDNode>(Op1)->isNullValue();
5977 CCode = X86::GetOppositeBranchCondition(CCode);
5978 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
5979 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
5982 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
5983 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
5984 if (X86CC == X86::COND_INVALID)
5987 SDValue Cond = EmitCmp(Op0, Op1, X86CC, DAG);
5989 // Use sbb x, x to materialize carry bit into a GPR.
5990 if (X86CC == X86::COND_B)
5991 return DAG.getNode(ISD::AND, dl, MVT::i8,
5992 DAG.getNode(X86ISD::SETCC_CARRY, dl, MVT::i8,
5993 DAG.getConstant(X86CC, MVT::i8), Cond),
5994 DAG.getConstant(1, MVT::i8));
5996 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
5997 DAG.getConstant(X86CC, MVT::i8), Cond);
6000 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
6002 SDValue Op0 = Op.getOperand(0);
6003 SDValue Op1 = Op.getOperand(1);
6004 SDValue CC = Op.getOperand(2);
6005 EVT VT = Op.getValueType();
6006 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
6007 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
6008 DebugLoc dl = Op.getDebugLoc();
6012 EVT VT0 = Op0.getValueType();
6013 assert(VT0 == MVT::v4f32 || VT0 == MVT::v2f64);
6014 unsigned Opc = VT0 == MVT::v4f32 ? X86ISD::CMPPS : X86ISD::CMPPD;
6017 switch (SetCCOpcode) {
6020 case ISD::SETEQ: SSECC = 0; break;
6022 case ISD::SETGT: Swap = true; // Fallthrough
6024 case ISD::SETOLT: SSECC = 1; break;
6026 case ISD::SETGE: Swap = true; // Fallthrough
6028 case ISD::SETOLE: SSECC = 2; break;
6029 case ISD::SETUO: SSECC = 3; break;
6031 case ISD::SETNE: SSECC = 4; break;
6032 case ISD::SETULE: Swap = true;
6033 case ISD::SETUGE: SSECC = 5; break;
6034 case ISD::SETULT: Swap = true;
6035 case ISD::SETUGT: SSECC = 6; break;
6036 case ISD::SETO: SSECC = 7; break;
6039 std::swap(Op0, Op1);
6041 // In the two special cases we can't handle, emit two comparisons.
6043 if (SetCCOpcode == ISD::SETUEQ) {
6045 UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8));
6046 EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8));
6047 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
6049 else if (SetCCOpcode == ISD::SETONE) {
6051 ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8));
6052 NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8));
6053 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
6055 llvm_unreachable("Illegal FP comparison");
6057 // Handle all other FP comparisons here.
6058 return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8));
6061 // We are handling one of the integer comparisons here. Since SSE only has
6062 // GT and EQ comparisons for integer, swapping operands and multiple
6063 // operations may be required for some comparisons.
6064 unsigned Opc = 0, EQOpc = 0, GTOpc = 0;
6065 bool Swap = false, Invert = false, FlipSigns = false;
6067 switch (VT.getSimpleVT().SimpleTy) {
6070 case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break;
6072 case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break;
6074 case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break;
6075 case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break;
6078 switch (SetCCOpcode) {
6080 case ISD::SETNE: Invert = true;
6081 case ISD::SETEQ: Opc = EQOpc; break;
6082 case ISD::SETLT: Swap = true;
6083 case ISD::SETGT: Opc = GTOpc; break;
6084 case ISD::SETGE: Swap = true;
6085 case ISD::SETLE: Opc = GTOpc; Invert = true; break;
6086 case ISD::SETULT: Swap = true;
6087 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break;
6088 case ISD::SETUGE: Swap = true;
6089 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break;
6092 std::swap(Op0, Op1);
6094 // Since SSE has no unsigned integer comparisons, we need to flip the sign
6095 // bits of the inputs before performing those operations.
6097 EVT EltVT = VT.getVectorElementType();
6098 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
6100 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
6101 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
6103 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
6104 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
6107 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
6109 // If the logical-not of the result is required, perform that now.
6111 Result = DAG.getNOT(dl, Result, VT);
6116 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
6117 static bool isX86LogicalCmp(SDValue Op) {
6118 unsigned Opc = Op.getNode()->getOpcode();
6119 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI)
6121 if (Op.getResNo() == 1 &&
6122 (Opc == X86ISD::ADD ||
6123 Opc == X86ISD::SUB ||
6124 Opc == X86ISD::SMUL ||
6125 Opc == X86ISD::UMUL ||
6126 Opc == X86ISD::INC ||
6127 Opc == X86ISD::DEC ||
6128 Opc == X86ISD::OR ||
6129 Opc == X86ISD::XOR ||
6130 Opc == X86ISD::AND))
6136 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) {
6137 bool addTest = true;
6138 SDValue Cond = Op.getOperand(0);
6139 DebugLoc dl = Op.getDebugLoc();
6142 if (Cond.getOpcode() == ISD::SETCC) {
6143 SDValue NewCond = LowerSETCC(Cond, DAG);
6144 if (NewCond.getNode())
6148 // (select (x == 0), -1, 0) -> (sign_bit (x - 1))
6149 SDValue Op1 = Op.getOperand(1);
6150 SDValue Op2 = Op.getOperand(2);
6151 if (Cond.getOpcode() == X86ISD::SETCC &&
6152 cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue() == X86::COND_E) {
6153 SDValue Cmp = Cond.getOperand(1);
6154 if (Cmp.getOpcode() == X86ISD::CMP) {
6155 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op1);
6156 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
6157 ConstantSDNode *RHSC =
6158 dyn_cast<ConstantSDNode>(Cmp.getOperand(1).getNode());
6159 if (N1C && N1C->isAllOnesValue() &&
6160 N2C && N2C->isNullValue() &&
6161 RHSC && RHSC->isNullValue()) {
6162 SDValue CmpOp0 = Cmp.getOperand(0);
6163 Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
6164 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
6165 return DAG.getNode(X86ISD::SETCC_CARRY, dl, Op.getValueType(),
6166 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
6171 // Look pass (and (setcc_carry (cmp ...)), 1).
6172 if (Cond.getOpcode() == ISD::AND &&
6173 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
6174 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
6175 if (C && C->getAPIntValue() == 1)
6176 Cond = Cond.getOperand(0);
6179 // If condition flag is set by a X86ISD::CMP, then use it as the condition
6180 // setting operand in place of the X86ISD::SETCC.
6181 if (Cond.getOpcode() == X86ISD::SETCC ||
6182 Cond.getOpcode() == X86ISD::SETCC_CARRY) {
6183 CC = Cond.getOperand(0);
6185 SDValue Cmp = Cond.getOperand(1);
6186 unsigned Opc = Cmp.getOpcode();
6187 EVT VT = Op.getValueType();
6189 bool IllegalFPCMov = false;
6190 if (VT.isFloatingPoint() && !VT.isVector() &&
6191 !isScalarFPTypeInSSEReg(VT)) // FPStack?
6192 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
6194 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
6195 Opc == X86ISD::BT) { // FIXME
6202 // Look pass the truncate.
6203 if (Cond.getOpcode() == ISD::TRUNCATE)
6204 Cond = Cond.getOperand(0);
6206 // We know the result of AND is compared against zero. Try to match
6208 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
6209 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
6210 if (NewSetCC.getNode()) {
6211 CC = NewSetCC.getOperand(0);
6212 Cond = NewSetCC.getOperand(1);
6219 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
6220 Cond = EmitTest(Cond, X86::COND_NE, DAG);
6223 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
6224 // condition is true.
6225 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
6226 SDValue Ops[] = { Op2, Op1, CC, Cond };
6227 return DAG.getNode(X86ISD::CMOV, dl, VTs, Ops, array_lengthof(Ops));
6230 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
6231 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
6232 // from the AND / OR.
6233 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
6234 Opc = Op.getOpcode();
6235 if (Opc != ISD::OR && Opc != ISD::AND)
6237 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
6238 Op.getOperand(0).hasOneUse() &&
6239 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
6240 Op.getOperand(1).hasOneUse());
6243 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
6244 // 1 and that the SETCC node has a single use.
6245 static bool isXor1OfSetCC(SDValue Op) {
6246 if (Op.getOpcode() != ISD::XOR)
6248 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
6249 if (N1C && N1C->getAPIntValue() == 1) {
6250 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
6251 Op.getOperand(0).hasOneUse();
6256 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) {
6257 bool addTest = true;
6258 SDValue Chain = Op.getOperand(0);
6259 SDValue Cond = Op.getOperand(1);
6260 SDValue Dest = Op.getOperand(2);
6261 DebugLoc dl = Op.getDebugLoc();
6264 if (Cond.getOpcode() == ISD::SETCC) {
6265 SDValue NewCond = LowerSETCC(Cond, DAG);
6266 if (NewCond.getNode())
6270 // FIXME: LowerXALUO doesn't handle these!!
6271 else if (Cond.getOpcode() == X86ISD::ADD ||
6272 Cond.getOpcode() == X86ISD::SUB ||
6273 Cond.getOpcode() == X86ISD::SMUL ||
6274 Cond.getOpcode() == X86ISD::UMUL)
6275 Cond = LowerXALUO(Cond, DAG);
6278 // Look pass (and (setcc_carry (cmp ...)), 1).
6279 if (Cond.getOpcode() == ISD::AND &&
6280 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
6281 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
6282 if (C && C->getAPIntValue() == 1)
6283 Cond = Cond.getOperand(0);
6286 // If condition flag is set by a X86ISD::CMP, then use it as the condition
6287 // setting operand in place of the X86ISD::SETCC.
6288 if (Cond.getOpcode() == X86ISD::SETCC ||
6289 Cond.getOpcode() == X86ISD::SETCC_CARRY) {
6290 CC = Cond.getOperand(0);
6292 SDValue Cmp = Cond.getOperand(1);
6293 unsigned Opc = Cmp.getOpcode();
6294 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
6295 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
6299 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
6303 // These can only come from an arithmetic instruction with overflow,
6304 // e.g. SADDO, UADDO.
6305 Cond = Cond.getNode()->getOperand(1);
6312 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
6313 SDValue Cmp = Cond.getOperand(0).getOperand(1);
6314 if (CondOpc == ISD::OR) {
6315 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
6316 // two branches instead of an explicit OR instruction with a
6318 if (Cmp == Cond.getOperand(1).getOperand(1) &&
6319 isX86LogicalCmp(Cmp)) {
6320 CC = Cond.getOperand(0).getOperand(0);
6321 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
6322 Chain, Dest, CC, Cmp);
6323 CC = Cond.getOperand(1).getOperand(0);
6327 } else { // ISD::AND
6328 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
6329 // two branches instead of an explicit AND instruction with a
6330 // separate test. However, we only do this if this block doesn't
6331 // have a fall-through edge, because this requires an explicit
6332 // jmp when the condition is false.
6333 if (Cmp == Cond.getOperand(1).getOperand(1) &&
6334 isX86LogicalCmp(Cmp) &&
6335 Op.getNode()->hasOneUse()) {
6336 X86::CondCode CCode =
6337 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
6338 CCode = X86::GetOppositeBranchCondition(CCode);
6339 CC = DAG.getConstant(CCode, MVT::i8);
6340 SDValue User = SDValue(*Op.getNode()->use_begin(), 0);
6341 // Look for an unconditional branch following this conditional branch.
6342 // We need this because we need to reverse the successors in order
6343 // to implement FCMP_OEQ.
6344 if (User.getOpcode() == ISD::BR) {
6345 SDValue FalseBB = User.getOperand(1);
6347 DAG.UpdateNodeOperands(User, User.getOperand(0), Dest);
6348 assert(NewBR == User);
6351 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
6352 Chain, Dest, CC, Cmp);
6353 X86::CondCode CCode =
6354 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
6355 CCode = X86::GetOppositeBranchCondition(CCode);
6356 CC = DAG.getConstant(CCode, MVT::i8);
6362 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
6363 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
6364 // It should be transformed during dag combiner except when the condition
6365 // is set by a arithmetics with overflow node.
6366 X86::CondCode CCode =
6367 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
6368 CCode = X86::GetOppositeBranchCondition(CCode);
6369 CC = DAG.getConstant(CCode, MVT::i8);
6370 Cond = Cond.getOperand(0).getOperand(1);
6376 // Look pass the truncate.
6377 if (Cond.getOpcode() == ISD::TRUNCATE)
6378 Cond = Cond.getOperand(0);
6380 // We know the result of AND is compared against zero. Try to match
6382 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
6383 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
6384 if (NewSetCC.getNode()) {
6385 CC = NewSetCC.getOperand(0);
6386 Cond = NewSetCC.getOperand(1);
6393 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
6394 Cond = EmitTest(Cond, X86::COND_NE, DAG);
6396 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
6397 Chain, Dest, CC, Cond);
6401 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
6402 // Calls to _alloca is needed to probe the stack when allocating more than 4k
6403 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
6404 // that the guard pages used by the OS virtual memory manager are allocated in
6405 // correct sequence.
6407 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
6408 SelectionDAG &DAG) {
6409 assert(Subtarget->isTargetCygMing() &&
6410 "This should be used only on Cygwin/Mingw targets");
6411 DebugLoc dl = Op.getDebugLoc();
6414 SDValue Chain = Op.getOperand(0);
6415 SDValue Size = Op.getOperand(1);
6416 // FIXME: Ensure alignment here
6420 EVT IntPtr = getPointerTy();
6421 EVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32;
6423 Chain = DAG.getCopyToReg(Chain, dl, X86::EAX, Size, Flag);
6424 Flag = Chain.getValue(1);
6426 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
6428 Chain = DAG.getNode(X86ISD::MINGW_ALLOCA, dl, NodeTys, Chain, Flag);
6429 Flag = Chain.getValue(1);
6431 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
6433 SDValue Ops1[2] = { Chain.getValue(0), Chain };
6434 return DAG.getMergeValues(Ops1, 2, dl);
6438 X86TargetLowering::EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl,
6440 SDValue Dst, SDValue Src,
6441 SDValue Size, unsigned Align,
6443 uint64_t DstSVOff) {
6444 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
6446 // If not DWORD aligned or size is more than the threshold, call the library.
6447 // The libc version is likely to be faster for these cases. It can use the
6448 // address value and run time information about the CPU.
6449 if ((Align & 3) != 0 ||
6451 ConstantSize->getZExtValue() >
6452 getSubtarget()->getMaxInlineSizeThreshold()) {
6453 SDValue InFlag(0, 0);
6455 // Check to see if there is a specialized entry-point for memory zeroing.
6456 ConstantSDNode *V = dyn_cast<ConstantSDNode>(Src);
6458 if (const char *bzeroEntry = V &&
6459 V->isNullValue() ? Subtarget->getBZeroEntry() : 0) {
6460 EVT IntPtr = getPointerTy();
6461 const Type *IntPtrTy = TD->getIntPtrType(*DAG.getContext());
6462 TargetLowering::ArgListTy Args;
6463 TargetLowering::ArgListEntry Entry;
6465 Entry.Ty = IntPtrTy;
6466 Args.push_back(Entry);
6468 Args.push_back(Entry);
6469 std::pair<SDValue,SDValue> CallResult =
6470 LowerCallTo(Chain, Type::getVoidTy(*DAG.getContext()),
6471 false, false, false, false,
6472 0, CallingConv::C, false, /*isReturnValueUsed=*/false,
6473 DAG.getExternalSymbol(bzeroEntry, IntPtr), Args, DAG, dl);
6474 return CallResult.second;
6477 // Otherwise have the target-independent code call memset.
6481 uint64_t SizeVal = ConstantSize->getZExtValue();
6482 SDValue InFlag(0, 0);
6485 ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Src);
6486 unsigned BytesLeft = 0;
6487 bool TwoRepStos = false;
6490 uint64_t Val = ValC->getZExtValue() & 255;
6492 // If the value is a constant, then we can potentially use larger sets.
6493 switch (Align & 3) {
6494 case 2: // WORD aligned
6497 Val = (Val << 8) | Val;
6499 case 0: // DWORD aligned
6502 Val = (Val << 8) | Val;
6503 Val = (Val << 16) | Val;
6504 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) { // QWORD aligned
6507 Val = (Val << 32) | Val;
6510 default: // Byte aligned
6513 Count = DAG.getIntPtrConstant(SizeVal);
6517 if (AVT.bitsGT(MVT::i8)) {
6518 unsigned UBytes = AVT.getSizeInBits() / 8;
6519 Count = DAG.getIntPtrConstant(SizeVal / UBytes);
6520 BytesLeft = SizeVal % UBytes;
6523 Chain = DAG.getCopyToReg(Chain, dl, ValReg, DAG.getConstant(Val, AVT),
6525 InFlag = Chain.getValue(1);
6528 Count = DAG.getIntPtrConstant(SizeVal);
6529 Chain = DAG.getCopyToReg(Chain, dl, X86::AL, Src, InFlag);
6530 InFlag = Chain.getValue(1);
6533 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RCX :
6536 InFlag = Chain.getValue(1);
6537 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RDI :
6540 InFlag = Chain.getValue(1);
6542 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6543 SDValue Ops[] = { Chain, DAG.getValueType(AVT), InFlag };
6544 Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, Ops, array_lengthof(Ops));
6547 InFlag = Chain.getValue(1);
6549 EVT CVT = Count.getValueType();
6550 SDValue Left = DAG.getNode(ISD::AND, dl, CVT, Count,
6551 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT));
6552 Chain = DAG.getCopyToReg(Chain, dl, (CVT == MVT::i64) ? X86::RCX :
6555 InFlag = Chain.getValue(1);
6556 Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6557 SDValue Ops[] = { Chain, DAG.getValueType(MVT::i8), InFlag };
6558 Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, Ops, array_lengthof(Ops));
6559 } else if (BytesLeft) {
6560 // Handle the last 1 - 7 bytes.
6561 unsigned Offset = SizeVal - BytesLeft;
6562 EVT AddrVT = Dst.getValueType();
6563 EVT SizeVT = Size.getValueType();
6565 Chain = DAG.getMemset(Chain, dl,
6566 DAG.getNode(ISD::ADD, dl, AddrVT, Dst,
6567 DAG.getConstant(Offset, AddrVT)),
6569 DAG.getConstant(BytesLeft, SizeVT),
6570 Align, DstSV, DstSVOff + Offset);
6573 // TODO: Use a Tokenfactor, as in memcpy, instead of a single chain.
6578 X86TargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
6579 SDValue Chain, SDValue Dst, SDValue Src,
6580 SDValue Size, unsigned Align,
6582 const Value *DstSV, uint64_t DstSVOff,
6583 const Value *SrcSV, uint64_t SrcSVOff) {
6584 // This requires the copy size to be a constant, preferrably
6585 // within a subtarget-specific limit.
6586 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
6589 uint64_t SizeVal = ConstantSize->getZExtValue();
6590 if (!AlwaysInline && SizeVal > getSubtarget()->getMaxInlineSizeThreshold())
6593 /// If not DWORD aligned, call the library.
6594 if ((Align & 3) != 0)
6599 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) // QWORD aligned
6602 unsigned UBytes = AVT.getSizeInBits() / 8;
6603 unsigned CountVal = SizeVal / UBytes;
6604 SDValue Count = DAG.getIntPtrConstant(CountVal);
6605 unsigned BytesLeft = SizeVal % UBytes;
6607 SDValue InFlag(0, 0);
6608 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RCX :
6611 InFlag = Chain.getValue(1);
6612 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RDI :
6615 InFlag = Chain.getValue(1);
6616 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RSI :
6619 InFlag = Chain.getValue(1);
6621 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6622 SDValue Ops[] = { Chain, DAG.getValueType(AVT), InFlag };
6623 SDValue RepMovs = DAG.getNode(X86ISD::REP_MOVS, dl, Tys, Ops,
6624 array_lengthof(Ops));
6626 SmallVector<SDValue, 4> Results;
6627 Results.push_back(RepMovs);
6629 // Handle the last 1 - 7 bytes.
6630 unsigned Offset = SizeVal - BytesLeft;
6631 EVT DstVT = Dst.getValueType();
6632 EVT SrcVT = Src.getValueType();
6633 EVT SizeVT = Size.getValueType();
6634 Results.push_back(DAG.getMemcpy(Chain, dl,
6635 DAG.getNode(ISD::ADD, dl, DstVT, Dst,
6636 DAG.getConstant(Offset, DstVT)),
6637 DAG.getNode(ISD::ADD, dl, SrcVT, Src,
6638 DAG.getConstant(Offset, SrcVT)),
6639 DAG.getConstant(BytesLeft, SizeVT),
6640 Align, AlwaysInline,
6641 DstSV, DstSVOff + Offset,
6642 SrcSV, SrcSVOff + Offset));
6645 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
6646 &Results[0], Results.size());
6649 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) {
6650 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
6651 DebugLoc dl = Op.getDebugLoc();
6653 if (!Subtarget->is64Bit()) {
6654 // vastart just stores the address of the VarArgsFrameIndex slot into the
6655 // memory location argument.
6656 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
6657 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0,
6662 // gp_offset (0 - 6 * 8)
6663 // fp_offset (48 - 48 + 8 * 16)
6664 // overflow_arg_area (point to parameters coming in memory).
6666 SmallVector<SDValue, 8> MemOps;
6667 SDValue FIN = Op.getOperand(1);
6669 SDValue Store = DAG.getStore(Op.getOperand(0), dl,
6670 DAG.getConstant(VarArgsGPOffset, MVT::i32),
6671 FIN, SV, 0, false, false, 0);
6672 MemOps.push_back(Store);
6675 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6676 FIN, DAG.getIntPtrConstant(4));
6677 Store = DAG.getStore(Op.getOperand(0), dl,
6678 DAG.getConstant(VarArgsFPOffset, MVT::i32),
6679 FIN, SV, 0, false, false, 0);
6680 MemOps.push_back(Store);
6682 // Store ptr to overflow_arg_area
6683 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6684 FIN, DAG.getIntPtrConstant(4));
6685 SDValue OVFIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
6686 Store = DAG.getStore(Op.getOperand(0), dl, OVFIN, FIN, SV, 0,
6688 MemOps.push_back(Store);
6690 // Store ptr to reg_save_area.
6691 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6692 FIN, DAG.getIntPtrConstant(8));
6693 SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
6694 Store = DAG.getStore(Op.getOperand(0), dl, RSFIN, FIN, SV, 0,
6696 MemOps.push_back(Store);
6697 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
6698 &MemOps[0], MemOps.size());
6701 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) {
6702 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
6703 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_arg!");
6704 SDValue Chain = Op.getOperand(0);
6705 SDValue SrcPtr = Op.getOperand(1);
6706 SDValue SrcSV = Op.getOperand(2);
6708 llvm_report_error("VAArgInst is not yet implemented for x86-64!");
6712 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) {
6713 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
6714 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
6715 SDValue Chain = Op.getOperand(0);
6716 SDValue DstPtr = Op.getOperand(1);
6717 SDValue SrcPtr = Op.getOperand(2);
6718 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
6719 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
6720 DebugLoc dl = Op.getDebugLoc();
6722 return DAG.getMemcpy(Chain, dl, DstPtr, SrcPtr,
6723 DAG.getIntPtrConstant(24), 8, false,
6724 DstSV, 0, SrcSV, 0);
6728 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
6729 DebugLoc dl = Op.getDebugLoc();
6730 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6732 default: return SDValue(); // Don't custom lower most intrinsics.
6733 // Comparison intrinsics.
6734 case Intrinsic::x86_sse_comieq_ss:
6735 case Intrinsic::x86_sse_comilt_ss:
6736 case Intrinsic::x86_sse_comile_ss:
6737 case Intrinsic::x86_sse_comigt_ss:
6738 case Intrinsic::x86_sse_comige_ss:
6739 case Intrinsic::x86_sse_comineq_ss:
6740 case Intrinsic::x86_sse_ucomieq_ss:
6741 case Intrinsic::x86_sse_ucomilt_ss:
6742 case Intrinsic::x86_sse_ucomile_ss:
6743 case Intrinsic::x86_sse_ucomigt_ss:
6744 case Intrinsic::x86_sse_ucomige_ss:
6745 case Intrinsic::x86_sse_ucomineq_ss:
6746 case Intrinsic::x86_sse2_comieq_sd:
6747 case Intrinsic::x86_sse2_comilt_sd:
6748 case Intrinsic::x86_sse2_comile_sd:
6749 case Intrinsic::x86_sse2_comigt_sd:
6750 case Intrinsic::x86_sse2_comige_sd:
6751 case Intrinsic::x86_sse2_comineq_sd:
6752 case Intrinsic::x86_sse2_ucomieq_sd:
6753 case Intrinsic::x86_sse2_ucomilt_sd:
6754 case Intrinsic::x86_sse2_ucomile_sd:
6755 case Intrinsic::x86_sse2_ucomigt_sd:
6756 case Intrinsic::x86_sse2_ucomige_sd:
6757 case Intrinsic::x86_sse2_ucomineq_sd: {
6759 ISD::CondCode CC = ISD::SETCC_INVALID;
6762 case Intrinsic::x86_sse_comieq_ss:
6763 case Intrinsic::x86_sse2_comieq_sd:
6767 case Intrinsic::x86_sse_comilt_ss:
6768 case Intrinsic::x86_sse2_comilt_sd:
6772 case Intrinsic::x86_sse_comile_ss:
6773 case Intrinsic::x86_sse2_comile_sd:
6777 case Intrinsic::x86_sse_comigt_ss:
6778 case Intrinsic::x86_sse2_comigt_sd:
6782 case Intrinsic::x86_sse_comige_ss:
6783 case Intrinsic::x86_sse2_comige_sd:
6787 case Intrinsic::x86_sse_comineq_ss:
6788 case Intrinsic::x86_sse2_comineq_sd:
6792 case Intrinsic::x86_sse_ucomieq_ss:
6793 case Intrinsic::x86_sse2_ucomieq_sd:
6794 Opc = X86ISD::UCOMI;
6797 case Intrinsic::x86_sse_ucomilt_ss:
6798 case Intrinsic::x86_sse2_ucomilt_sd:
6799 Opc = X86ISD::UCOMI;
6802 case Intrinsic::x86_sse_ucomile_ss:
6803 case Intrinsic::x86_sse2_ucomile_sd:
6804 Opc = X86ISD::UCOMI;
6807 case Intrinsic::x86_sse_ucomigt_ss:
6808 case Intrinsic::x86_sse2_ucomigt_sd:
6809 Opc = X86ISD::UCOMI;
6812 case Intrinsic::x86_sse_ucomige_ss:
6813 case Intrinsic::x86_sse2_ucomige_sd:
6814 Opc = X86ISD::UCOMI;
6817 case Intrinsic::x86_sse_ucomineq_ss:
6818 case Intrinsic::x86_sse2_ucomineq_sd:
6819 Opc = X86ISD::UCOMI;
6824 SDValue LHS = Op.getOperand(1);
6825 SDValue RHS = Op.getOperand(2);
6826 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
6827 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
6828 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
6829 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
6830 DAG.getConstant(X86CC, MVT::i8), Cond);
6831 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
6833 // ptest intrinsics. The intrinsic these come from are designed to return
6834 // an integer value, not just an instruction so lower it to the ptest
6835 // pattern and a setcc for the result.
6836 case Intrinsic::x86_sse41_ptestz:
6837 case Intrinsic::x86_sse41_ptestc:
6838 case Intrinsic::x86_sse41_ptestnzc:{
6841 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
6842 case Intrinsic::x86_sse41_ptestz:
6844 X86CC = X86::COND_E;
6846 case Intrinsic::x86_sse41_ptestc:
6848 X86CC = X86::COND_B;
6850 case Intrinsic::x86_sse41_ptestnzc:
6852 X86CC = X86::COND_A;
6856 SDValue LHS = Op.getOperand(1);
6857 SDValue RHS = Op.getOperand(2);
6858 SDValue Test = DAG.getNode(X86ISD::PTEST, dl, MVT::i32, LHS, RHS);
6859 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
6860 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
6861 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
6864 // Fix vector shift instructions where the last operand is a non-immediate
6866 case Intrinsic::x86_sse2_pslli_w:
6867 case Intrinsic::x86_sse2_pslli_d:
6868 case Intrinsic::x86_sse2_pslli_q:
6869 case Intrinsic::x86_sse2_psrli_w:
6870 case Intrinsic::x86_sse2_psrli_d:
6871 case Intrinsic::x86_sse2_psrli_q:
6872 case Intrinsic::x86_sse2_psrai_w:
6873 case Intrinsic::x86_sse2_psrai_d:
6874 case Intrinsic::x86_mmx_pslli_w:
6875 case Intrinsic::x86_mmx_pslli_d:
6876 case Intrinsic::x86_mmx_pslli_q:
6877 case Intrinsic::x86_mmx_psrli_w:
6878 case Intrinsic::x86_mmx_psrli_d:
6879 case Intrinsic::x86_mmx_psrli_q:
6880 case Intrinsic::x86_mmx_psrai_w:
6881 case Intrinsic::x86_mmx_psrai_d: {
6882 SDValue ShAmt = Op.getOperand(2);
6883 if (isa<ConstantSDNode>(ShAmt))
6886 unsigned NewIntNo = 0;
6887 EVT ShAmtVT = MVT::v4i32;
6889 case Intrinsic::x86_sse2_pslli_w:
6890 NewIntNo = Intrinsic::x86_sse2_psll_w;
6892 case Intrinsic::x86_sse2_pslli_d:
6893 NewIntNo = Intrinsic::x86_sse2_psll_d;
6895 case Intrinsic::x86_sse2_pslli_q:
6896 NewIntNo = Intrinsic::x86_sse2_psll_q;
6898 case Intrinsic::x86_sse2_psrli_w:
6899 NewIntNo = Intrinsic::x86_sse2_psrl_w;
6901 case Intrinsic::x86_sse2_psrli_d:
6902 NewIntNo = Intrinsic::x86_sse2_psrl_d;
6904 case Intrinsic::x86_sse2_psrli_q:
6905 NewIntNo = Intrinsic::x86_sse2_psrl_q;
6907 case Intrinsic::x86_sse2_psrai_w:
6908 NewIntNo = Intrinsic::x86_sse2_psra_w;
6910 case Intrinsic::x86_sse2_psrai_d:
6911 NewIntNo = Intrinsic::x86_sse2_psra_d;
6914 ShAmtVT = MVT::v2i32;
6916 case Intrinsic::x86_mmx_pslli_w:
6917 NewIntNo = Intrinsic::x86_mmx_psll_w;
6919 case Intrinsic::x86_mmx_pslli_d:
6920 NewIntNo = Intrinsic::x86_mmx_psll_d;
6922 case Intrinsic::x86_mmx_pslli_q:
6923 NewIntNo = Intrinsic::x86_mmx_psll_q;
6925 case Intrinsic::x86_mmx_psrli_w:
6926 NewIntNo = Intrinsic::x86_mmx_psrl_w;
6928 case Intrinsic::x86_mmx_psrli_d:
6929 NewIntNo = Intrinsic::x86_mmx_psrl_d;
6931 case Intrinsic::x86_mmx_psrli_q:
6932 NewIntNo = Intrinsic::x86_mmx_psrl_q;
6934 case Intrinsic::x86_mmx_psrai_w:
6935 NewIntNo = Intrinsic::x86_mmx_psra_w;
6937 case Intrinsic::x86_mmx_psrai_d:
6938 NewIntNo = Intrinsic::x86_mmx_psra_d;
6940 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
6946 // The vector shift intrinsics with scalars uses 32b shift amounts but
6947 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
6951 ShOps[1] = DAG.getConstant(0, MVT::i32);
6952 if (ShAmtVT == MVT::v4i32) {
6953 ShOps[2] = DAG.getUNDEF(MVT::i32);
6954 ShOps[3] = DAG.getUNDEF(MVT::i32);
6955 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 4);
6957 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2);
6960 EVT VT = Op.getValueType();
6961 ShAmt = DAG.getNode(ISD::BIT_CONVERT, dl, VT, ShAmt);
6962 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6963 DAG.getConstant(NewIntNo, MVT::i32),
6964 Op.getOperand(1), ShAmt);
6969 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) {
6970 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6971 DebugLoc dl = Op.getDebugLoc();
6974 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
6976 DAG.getConstant(TD->getPointerSize(),
6977 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
6978 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
6979 DAG.getNode(ISD::ADD, dl, getPointerTy(),
6981 NULL, 0, false, false, 0);
6984 // Just load the return address.
6985 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
6986 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
6987 RetAddrFI, NULL, 0, false, false, 0);
6990 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
6991 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
6992 MFI->setFrameAddressIsTaken(true);
6993 EVT VT = Op.getValueType();
6994 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
6995 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6996 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
6997 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
6999 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0,
7004 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
7005 SelectionDAG &DAG) {
7006 return DAG.getIntPtrConstant(2*TD->getPointerSize());
7009 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG)
7011 MachineFunction &MF = DAG.getMachineFunction();
7012 SDValue Chain = Op.getOperand(0);
7013 SDValue Offset = Op.getOperand(1);
7014 SDValue Handler = Op.getOperand(2);
7015 DebugLoc dl = Op.getDebugLoc();
7017 SDValue Frame = DAG.getRegister(Subtarget->is64Bit() ? X86::RBP : X86::EBP,
7019 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
7021 SDValue StoreAddr = DAG.getNode(ISD::SUB, dl, getPointerTy(), Frame,
7022 DAG.getIntPtrConstant(-TD->getPointerSize()));
7023 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
7024 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, NULL, 0, false, false, 0);
7025 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
7026 MF.getRegInfo().addLiveOut(StoreAddrReg);
7028 return DAG.getNode(X86ISD::EH_RETURN, dl,
7030 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
7033 SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op,
7034 SelectionDAG &DAG) {
7035 SDValue Root = Op.getOperand(0);
7036 SDValue Trmp = Op.getOperand(1); // trampoline
7037 SDValue FPtr = Op.getOperand(2); // nested function
7038 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
7039 DebugLoc dl = Op.getDebugLoc();
7041 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
7043 if (Subtarget->is64Bit()) {
7044 SDValue OutChains[6];
7046 // Large code-model.
7047 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
7048 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
7050 const unsigned char N86R10 = RegInfo->getX86RegNum(X86::R10);
7051 const unsigned char N86R11 = RegInfo->getX86RegNum(X86::R11);
7053 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
7055 // Load the pointer to the nested function into R11.
7056 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
7057 SDValue Addr = Trmp;
7058 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
7059 Addr, TrmpAddr, 0, false, false, 0);
7061 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
7062 DAG.getConstant(2, MVT::i64));
7063 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr, TrmpAddr, 2,
7066 // Load the 'nest' parameter value into R10.
7067 // R10 is specified in X86CallingConv.td
7068 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
7069 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
7070 DAG.getConstant(10, MVT::i64));
7071 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
7072 Addr, TrmpAddr, 10, false, false, 0);
7074 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
7075 DAG.getConstant(12, MVT::i64));
7076 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 12,
7079 // Jump to the nested function.
7080 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
7081 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
7082 DAG.getConstant(20, MVT::i64));
7083 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
7084 Addr, TrmpAddr, 20, false, false, 0);
7086 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
7087 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
7088 DAG.getConstant(22, MVT::i64));
7089 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
7090 TrmpAddr, 22, false, false, 0);
7093 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6) };
7094 return DAG.getMergeValues(Ops, 2, dl);
7096 const Function *Func =
7097 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
7098 CallingConv::ID CC = Func->getCallingConv();
7103 llvm_unreachable("Unsupported calling convention");
7104 case CallingConv::C:
7105 case CallingConv::X86_StdCall: {
7106 // Pass 'nest' parameter in ECX.
7107 // Must be kept in sync with X86CallingConv.td
7110 // Check that ECX wasn't needed by an 'inreg' parameter.
7111 const FunctionType *FTy = Func->getFunctionType();
7112 const AttrListPtr &Attrs = Func->getAttributes();
7114 if (!Attrs.isEmpty() && !Func->isVarArg()) {
7115 unsigned InRegCount = 0;
7118 for (FunctionType::param_iterator I = FTy->param_begin(),
7119 E = FTy->param_end(); I != E; ++I, ++Idx)
7120 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
7121 // FIXME: should only count parameters that are lowered to integers.
7122 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
7124 if (InRegCount > 2) {
7125 llvm_report_error("Nest register in use - reduce number of inreg parameters!");
7130 case CallingConv::X86_FastCall:
7131 case CallingConv::Fast:
7132 // Pass 'nest' parameter in EAX.
7133 // Must be kept in sync with X86CallingConv.td
7138 SDValue OutChains[4];
7141 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
7142 DAG.getConstant(10, MVT::i32));
7143 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
7145 // This is storing the opcode for MOV32ri.
7146 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
7147 const unsigned char N86Reg = RegInfo->getX86RegNum(NestReg);
7148 OutChains[0] = DAG.getStore(Root, dl,
7149 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
7150 Trmp, TrmpAddr, 0, false, false, 0);
7152 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
7153 DAG.getConstant(1, MVT::i32));
7154 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 1,
7157 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
7158 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
7159 DAG.getConstant(5, MVT::i32));
7160 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
7161 TrmpAddr, 5, false, false, 1);
7163 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
7164 DAG.getConstant(6, MVT::i32));
7165 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr, TrmpAddr, 6,
7169 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4) };
7170 return DAG.getMergeValues(Ops, 2, dl);
7174 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) {
7176 The rounding mode is in bits 11:10 of FPSR, and has the following
7183 FLT_ROUNDS, on the other hand, expects the following:
7190 To perform the conversion, we do:
7191 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
7194 MachineFunction &MF = DAG.getMachineFunction();
7195 const TargetMachine &TM = MF.getTarget();
7196 const TargetFrameInfo &TFI = *TM.getFrameInfo();
7197 unsigned StackAlignment = TFI.getStackAlignment();
7198 EVT VT = Op.getValueType();
7199 DebugLoc dl = Op.getDebugLoc();
7201 // Save FP Control Word to stack slot
7202 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
7203 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7205 SDValue Chain = DAG.getNode(X86ISD::FNSTCW16m, dl, MVT::Other,
7206 DAG.getEntryNode(), StackSlot);
7208 // Load FP Control Word from stack slot
7209 SDValue CWD = DAG.getLoad(MVT::i16, dl, Chain, StackSlot, NULL, 0,
7212 // Transform as necessary
7214 DAG.getNode(ISD::SRL, dl, MVT::i16,
7215 DAG.getNode(ISD::AND, dl, MVT::i16,
7216 CWD, DAG.getConstant(0x800, MVT::i16)),
7217 DAG.getConstant(11, MVT::i8));
7219 DAG.getNode(ISD::SRL, dl, MVT::i16,
7220 DAG.getNode(ISD::AND, dl, MVT::i16,
7221 CWD, DAG.getConstant(0x400, MVT::i16)),
7222 DAG.getConstant(9, MVT::i8));
7225 DAG.getNode(ISD::AND, dl, MVT::i16,
7226 DAG.getNode(ISD::ADD, dl, MVT::i16,
7227 DAG.getNode(ISD::OR, dl, MVT::i16, CWD1, CWD2),
7228 DAG.getConstant(1, MVT::i16)),
7229 DAG.getConstant(3, MVT::i16));
7232 return DAG.getNode((VT.getSizeInBits() < 16 ?
7233 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
7236 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
7237 EVT VT = Op.getValueType();
7239 unsigned NumBits = VT.getSizeInBits();
7240 DebugLoc dl = Op.getDebugLoc();
7242 Op = Op.getOperand(0);
7243 if (VT == MVT::i8) {
7244 // Zero extend to i32 since there is not an i8 bsr.
7246 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
7249 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
7250 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
7251 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
7253 // If src is zero (i.e. bsr sets ZF), returns NumBits.
7256 DAG.getConstant(NumBits+NumBits-1, OpVT),
7257 DAG.getConstant(X86::COND_E, MVT::i8),
7260 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
7262 // Finally xor with NumBits-1.
7263 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
7266 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
7270 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
7271 EVT VT = Op.getValueType();
7273 unsigned NumBits = VT.getSizeInBits();
7274 DebugLoc dl = Op.getDebugLoc();
7276 Op = Op.getOperand(0);
7277 if (VT == MVT::i8) {
7279 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
7282 // Issue a bsf (scan bits forward) which also sets EFLAGS.
7283 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
7284 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
7286 // If src is zero (i.e. bsf sets ZF), returns NumBits.
7289 DAG.getConstant(NumBits, OpVT),
7290 DAG.getConstant(X86::COND_E, MVT::i8),
7293 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
7296 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
7300 SDValue X86TargetLowering::LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) {
7301 EVT VT = Op.getValueType();
7302 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply");
7303 DebugLoc dl = Op.getDebugLoc();
7305 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32);
7306 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32);
7307 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b );
7308 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi );
7309 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b );
7311 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 );
7312 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 );
7313 // return AloBlo + AloBhi + AhiBlo;
7315 SDValue A = Op.getOperand(0);
7316 SDValue B = Op.getOperand(1);
7318 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7319 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
7320 A, DAG.getConstant(32, MVT::i32));
7321 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7322 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
7323 B, DAG.getConstant(32, MVT::i32));
7324 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7325 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
7327 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7328 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
7330 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7331 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
7333 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7334 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
7335 AloBhi, DAG.getConstant(32, MVT::i32));
7336 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7337 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
7338 AhiBlo, DAG.getConstant(32, MVT::i32));
7339 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
7340 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
7345 SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) {
7346 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
7347 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
7348 // looks for this combo and may remove the "setcc" instruction if the "setcc"
7349 // has only one use.
7350 SDNode *N = Op.getNode();
7351 SDValue LHS = N->getOperand(0);
7352 SDValue RHS = N->getOperand(1);
7353 unsigned BaseOp = 0;
7355 DebugLoc dl = Op.getDebugLoc();
7357 switch (Op.getOpcode()) {
7358 default: llvm_unreachable("Unknown ovf instruction!");
7360 // A subtract of one will be selected as a INC. Note that INC doesn't
7361 // set CF, so we can't do this for UADDO.
7362 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
7363 if (C->getAPIntValue() == 1) {
7364 BaseOp = X86ISD::INC;
7368 BaseOp = X86ISD::ADD;
7372 BaseOp = X86ISD::ADD;
7376 // A subtract of one will be selected as a DEC. Note that DEC doesn't
7377 // set CF, so we can't do this for USUBO.
7378 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
7379 if (C->getAPIntValue() == 1) {
7380 BaseOp = X86ISD::DEC;
7384 BaseOp = X86ISD::SUB;
7388 BaseOp = X86ISD::SUB;
7392 BaseOp = X86ISD::SMUL;
7396 BaseOp = X86ISD::UMUL;
7401 // Also sets EFLAGS.
7402 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
7403 SDValue Sum = DAG.getNode(BaseOp, dl, VTs, LHS, RHS);
7406 DAG.getNode(X86ISD::SETCC, dl, N->getValueType(1),
7407 DAG.getConstant(Cond, MVT::i32), SDValue(Sum.getNode(), 1));
7409 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SetCC);
7413 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) {
7414 EVT T = Op.getValueType();
7415 DebugLoc dl = Op.getDebugLoc();
7418 switch(T.getSimpleVT().SimpleTy) {
7420 assert(false && "Invalid value type!");
7421 case MVT::i8: Reg = X86::AL; size = 1; break;
7422 case MVT::i16: Reg = X86::AX; size = 2; break;
7423 case MVT::i32: Reg = X86::EAX; size = 4; break;
7425 assert(Subtarget->is64Bit() && "Node not type legal!");
7426 Reg = X86::RAX; size = 8;
7429 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), dl, Reg,
7430 Op.getOperand(2), SDValue());
7431 SDValue Ops[] = { cpIn.getValue(0),
7434 DAG.getTargetConstant(size, MVT::i8),
7436 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
7437 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG_DAG, dl, Tys, Ops, 5);
7439 DAG.getCopyFromReg(Result.getValue(0), dl, Reg, T, Result.getValue(1));
7443 SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
7444 SelectionDAG &DAG) {
7445 assert(Subtarget->is64Bit() && "Result not type legalized?");
7446 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
7447 SDValue TheChain = Op.getOperand(0);
7448 DebugLoc dl = Op.getDebugLoc();
7449 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
7450 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
7451 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
7453 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
7454 DAG.getConstant(32, MVT::i8));
7456 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
7459 return DAG.getMergeValues(Ops, 2, dl);
7462 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
7463 SDNode *Node = Op.getNode();
7464 DebugLoc dl = Node->getDebugLoc();
7465 EVT T = Node->getValueType(0);
7466 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
7467 DAG.getConstant(0, T), Node->getOperand(2));
7468 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
7469 cast<AtomicSDNode>(Node)->getMemoryVT(),
7470 Node->getOperand(0),
7471 Node->getOperand(1), negOp,
7472 cast<AtomicSDNode>(Node)->getSrcValue(),
7473 cast<AtomicSDNode>(Node)->getAlignment());
7476 /// LowerOperation - Provide custom lowering hooks for some operations.
7478 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
7479 switch (Op.getOpcode()) {
7480 default: llvm_unreachable("Should not custom lower this!");
7481 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
7482 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
7483 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
7484 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
7485 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
7486 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
7487 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
7488 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
7489 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
7490 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
7491 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
7492 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
7493 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
7494 case ISD::SHL_PARTS:
7495 case ISD::SRA_PARTS:
7496 case ISD::SRL_PARTS: return LowerShift(Op, DAG);
7497 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
7498 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
7499 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
7500 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
7501 case ISD::FABS: return LowerFABS(Op, DAG);
7502 case ISD::FNEG: return LowerFNEG(Op, DAG);
7503 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
7504 case ISD::SETCC: return LowerSETCC(Op, DAG);
7505 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
7506 case ISD::SELECT: return LowerSELECT(Op, DAG);
7507 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
7508 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
7509 case ISD::VASTART: return LowerVASTART(Op, DAG);
7510 case ISD::VAARG: return LowerVAARG(Op, DAG);
7511 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
7512 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
7513 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
7514 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
7515 case ISD::FRAME_TO_ARGS_OFFSET:
7516 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
7517 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
7518 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
7519 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
7520 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
7521 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
7522 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
7523 case ISD::MUL: return LowerMUL_V2I64(Op, DAG);
7529 case ISD::UMULO: return LowerXALUO(Op, DAG);
7530 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
7534 void X86TargetLowering::
7535 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
7536 SelectionDAG &DAG, unsigned NewOp) {
7537 EVT T = Node->getValueType(0);
7538 DebugLoc dl = Node->getDebugLoc();
7539 assert (T == MVT::i64 && "Only know how to expand i64 atomics");
7541 SDValue Chain = Node->getOperand(0);
7542 SDValue In1 = Node->getOperand(1);
7543 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
7544 Node->getOperand(2), DAG.getIntPtrConstant(0));
7545 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
7546 Node->getOperand(2), DAG.getIntPtrConstant(1));
7547 SDValue Ops[] = { Chain, In1, In2L, In2H };
7548 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
7550 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64,
7551 cast<MemSDNode>(Node)->getMemOperand());
7552 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
7553 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
7554 Results.push_back(Result.getValue(2));
7557 /// ReplaceNodeResults - Replace a node with an illegal result type
7558 /// with a new node built out of custom code.
7559 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
7560 SmallVectorImpl<SDValue>&Results,
7561 SelectionDAG &DAG) {
7562 DebugLoc dl = N->getDebugLoc();
7563 switch (N->getOpcode()) {
7565 assert(false && "Do not know how to custom type legalize this operation!");
7567 case ISD::FP_TO_SINT: {
7568 std::pair<SDValue,SDValue> Vals =
7569 FP_TO_INTHelper(SDValue(N, 0), DAG, true);
7570 SDValue FIST = Vals.first, StackSlot = Vals.second;
7571 if (FIST.getNode() != 0) {
7572 EVT VT = N->getValueType(0);
7573 // Return a load from the stack slot.
7574 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot, NULL, 0,
7579 case ISD::READCYCLECOUNTER: {
7580 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
7581 SDValue TheChain = N->getOperand(0);
7582 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
7583 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
7585 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
7587 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
7588 SDValue Ops[] = { eax, edx };
7589 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
7590 Results.push_back(edx.getValue(1));
7593 case ISD::ATOMIC_CMP_SWAP: {
7594 EVT T = N->getValueType(0);
7595 assert (T == MVT::i64 && "Only know how to expand i64 Cmp and Swap");
7596 SDValue cpInL, cpInH;
7597 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
7598 DAG.getConstant(0, MVT::i32));
7599 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
7600 DAG.getConstant(1, MVT::i32));
7601 cpInL = DAG.getCopyToReg(N->getOperand(0), dl, X86::EAX, cpInL, SDValue());
7602 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, X86::EDX, cpInH,
7604 SDValue swapInL, swapInH;
7605 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
7606 DAG.getConstant(0, MVT::i32));
7607 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
7608 DAG.getConstant(1, MVT::i32));
7609 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, X86::EBX, swapInL,
7611 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, X86::ECX, swapInH,
7612 swapInL.getValue(1));
7613 SDValue Ops[] = { swapInH.getValue(0),
7615 swapInH.getValue(1) };
7616 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
7617 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG8_DAG, dl, Tys, Ops, 3);
7618 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, X86::EAX,
7619 MVT::i32, Result.getValue(1));
7620 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, X86::EDX,
7621 MVT::i32, cpOutL.getValue(2));
7622 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
7623 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
7624 Results.push_back(cpOutH.getValue(1));
7627 case ISD::ATOMIC_LOAD_ADD:
7628 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
7630 case ISD::ATOMIC_LOAD_AND:
7631 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
7633 case ISD::ATOMIC_LOAD_NAND:
7634 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
7636 case ISD::ATOMIC_LOAD_OR:
7637 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
7639 case ISD::ATOMIC_LOAD_SUB:
7640 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
7642 case ISD::ATOMIC_LOAD_XOR:
7643 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
7645 case ISD::ATOMIC_SWAP:
7646 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
7651 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
7653 default: return NULL;
7654 case X86ISD::BSF: return "X86ISD::BSF";
7655 case X86ISD::BSR: return "X86ISD::BSR";
7656 case X86ISD::SHLD: return "X86ISD::SHLD";
7657 case X86ISD::SHRD: return "X86ISD::SHRD";
7658 case X86ISD::FAND: return "X86ISD::FAND";
7659 case X86ISD::FOR: return "X86ISD::FOR";
7660 case X86ISD::FXOR: return "X86ISD::FXOR";
7661 case X86ISD::FSRL: return "X86ISD::FSRL";
7662 case X86ISD::FILD: return "X86ISD::FILD";
7663 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
7664 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
7665 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
7666 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
7667 case X86ISD::FLD: return "X86ISD::FLD";
7668 case X86ISD::FST: return "X86ISD::FST";
7669 case X86ISD::CALL: return "X86ISD::CALL";
7670 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
7671 case X86ISD::BT: return "X86ISD::BT";
7672 case X86ISD::CMP: return "X86ISD::CMP";
7673 case X86ISD::COMI: return "X86ISD::COMI";
7674 case X86ISD::UCOMI: return "X86ISD::UCOMI";
7675 case X86ISD::SETCC: return "X86ISD::SETCC";
7676 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
7677 case X86ISD::CMOV: return "X86ISD::CMOV";
7678 case X86ISD::BRCOND: return "X86ISD::BRCOND";
7679 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
7680 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
7681 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
7682 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
7683 case X86ISD::Wrapper: return "X86ISD::Wrapper";
7684 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
7685 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
7686 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
7687 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
7688 case X86ISD::PINSRB: return "X86ISD::PINSRB";
7689 case X86ISD::PINSRW: return "X86ISD::PINSRW";
7690 case X86ISD::MMX_PINSRW: return "X86ISD::MMX_PINSRW";
7691 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
7692 case X86ISD::FMAX: return "X86ISD::FMAX";
7693 case X86ISD::FMIN: return "X86ISD::FMIN";
7694 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
7695 case X86ISD::FRCP: return "X86ISD::FRCP";
7696 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
7697 case X86ISD::SegmentBaseAddress: return "X86ISD::SegmentBaseAddress";
7698 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
7699 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
7700 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
7701 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
7702 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
7703 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
7704 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
7705 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
7706 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
7707 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
7708 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
7709 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
7710 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
7711 case X86ISD::VSHL: return "X86ISD::VSHL";
7712 case X86ISD::VSRL: return "X86ISD::VSRL";
7713 case X86ISD::CMPPD: return "X86ISD::CMPPD";
7714 case X86ISD::CMPPS: return "X86ISD::CMPPS";
7715 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB";
7716 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW";
7717 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD";
7718 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ";
7719 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB";
7720 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW";
7721 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD";
7722 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ";
7723 case X86ISD::ADD: return "X86ISD::ADD";
7724 case X86ISD::SUB: return "X86ISD::SUB";
7725 case X86ISD::SMUL: return "X86ISD::SMUL";
7726 case X86ISD::UMUL: return "X86ISD::UMUL";
7727 case X86ISD::INC: return "X86ISD::INC";
7728 case X86ISD::DEC: return "X86ISD::DEC";
7729 case X86ISD::OR: return "X86ISD::OR";
7730 case X86ISD::XOR: return "X86ISD::XOR";
7731 case X86ISD::AND: return "X86ISD::AND";
7732 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
7733 case X86ISD::PTEST: return "X86ISD::PTEST";
7734 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
7735 case X86ISD::MINGW_ALLOCA: return "X86ISD::MINGW_ALLOCA";
7739 // isLegalAddressingMode - Return true if the addressing mode represented
7740 // by AM is legal for this target, for a load/store of the specified type.
7741 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
7742 const Type *Ty) const {
7743 // X86 supports extremely general addressing modes.
7744 CodeModel::Model M = getTargetMachine().getCodeModel();
7746 // X86 allows a sign-extended 32-bit immediate field as a displacement.
7747 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
7752 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
7754 // If a reference to this global requires an extra load, we can't fold it.
7755 if (isGlobalStubReference(GVFlags))
7758 // If BaseGV requires a register for the PIC base, we cannot also have a
7759 // BaseReg specified.
7760 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
7763 // If lower 4G is not available, then we must use rip-relative addressing.
7764 if (Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
7774 // These scales always work.
7779 // These scales are formed with basereg+scalereg. Only accept if there is
7784 default: // Other stuff never works.
7792 bool X86TargetLowering::isTruncateFree(const Type *Ty1, const Type *Ty2) const {
7793 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
7795 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
7796 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
7797 if (NumBits1 <= NumBits2)
7802 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
7803 if (!VT1.isInteger() || !VT2.isInteger())
7805 unsigned NumBits1 = VT1.getSizeInBits();
7806 unsigned NumBits2 = VT2.getSizeInBits();
7807 if (NumBits1 <= NumBits2)
7812 bool X86TargetLowering::isZExtFree(const Type *Ty1, const Type *Ty2) const {
7813 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
7814 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
7817 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
7818 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
7819 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
7822 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
7823 // i16 instructions are longer (0x66 prefix) and potentially slower.
7824 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
7827 /// isShuffleMaskLegal - Targets can use this to indicate that they only
7828 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
7829 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
7830 /// are assumed to be legal.
7832 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
7834 // Only do shuffles on 128-bit vector types for now.
7835 if (VT.getSizeInBits() == 64)
7838 // FIXME: pshufb, blends, shifts.
7839 return (VT.getVectorNumElements() == 2 ||
7840 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
7841 isMOVLMask(M, VT) ||
7842 isSHUFPMask(M, VT) ||
7843 isPSHUFDMask(M, VT) ||
7844 isPSHUFHWMask(M, VT) ||
7845 isPSHUFLWMask(M, VT) ||
7846 isPALIGNRMask(M, VT, Subtarget->hasSSSE3()) ||
7847 isUNPCKLMask(M, VT) ||
7848 isUNPCKHMask(M, VT) ||
7849 isUNPCKL_v_undef_Mask(M, VT) ||
7850 isUNPCKH_v_undef_Mask(M, VT));
7854 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
7856 unsigned NumElts = VT.getVectorNumElements();
7857 // FIXME: This collection of masks seems suspect.
7860 if (NumElts == 4 && VT.getSizeInBits() == 128) {
7861 return (isMOVLMask(Mask, VT) ||
7862 isCommutedMOVLMask(Mask, VT, true) ||
7863 isSHUFPMask(Mask, VT) ||
7864 isCommutedSHUFPMask(Mask, VT));
7869 //===----------------------------------------------------------------------===//
7870 // X86 Scheduler Hooks
7871 //===----------------------------------------------------------------------===//
7873 // private utility function
7875 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
7876 MachineBasicBlock *MBB,
7884 TargetRegisterClass *RC,
7885 bool invSrc) const {
7886 // For the atomic bitwise operator, we generate
7889 // ld t1 = [bitinstr.addr]
7890 // op t2 = t1, [bitinstr.val]
7892 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
7894 // fallthrough -->nextMBB
7895 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7896 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
7897 MachineFunction::iterator MBBIter = MBB;
7900 /// First build the CFG
7901 MachineFunction *F = MBB->getParent();
7902 MachineBasicBlock *thisMBB = MBB;
7903 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
7904 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
7905 F->insert(MBBIter, newMBB);
7906 F->insert(MBBIter, nextMBB);
7908 // Move all successors to thisMBB to nextMBB
7909 nextMBB->transferSuccessors(thisMBB);
7911 // Update thisMBB to fall through to newMBB
7912 thisMBB->addSuccessor(newMBB);
7914 // newMBB jumps to itself and fall through to nextMBB
7915 newMBB->addSuccessor(nextMBB);
7916 newMBB->addSuccessor(newMBB);
7918 // Insert instructions into newMBB based on incoming instruction
7919 assert(bInstr->getNumOperands() < X86AddrNumOperands + 4 &&
7920 "unexpected number of operands");
7921 DebugLoc dl = bInstr->getDebugLoc();
7922 MachineOperand& destOper = bInstr->getOperand(0);
7923 MachineOperand* argOpers[2 + X86AddrNumOperands];
7924 int numArgs = bInstr->getNumOperands() - 1;
7925 for (int i=0; i < numArgs; ++i)
7926 argOpers[i] = &bInstr->getOperand(i+1);
7928 // x86 address has 4 operands: base, index, scale, and displacement
7929 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3]
7930 int valArgIndx = lastAddrIndx + 1;
7932 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
7933 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1);
7934 for (int i=0; i <= lastAddrIndx; ++i)
7935 (*MIB).addOperand(*argOpers[i]);
7937 unsigned tt = F->getRegInfo().createVirtualRegister(RC);
7939 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1);
7944 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
7945 assert((argOpers[valArgIndx]->isReg() ||
7946 argOpers[valArgIndx]->isImm()) &&
7948 if (argOpers[valArgIndx]->isReg())
7949 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2);
7951 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2);
7953 (*MIB).addOperand(*argOpers[valArgIndx]);
7955 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), EAXreg);
7958 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
7959 for (int i=0; i <= lastAddrIndx; ++i)
7960 (*MIB).addOperand(*argOpers[i]);
7962 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
7963 (*MIB).setMemRefs(bInstr->memoperands_begin(),
7964 bInstr->memoperands_end());
7966 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), destOper.getReg());
7970 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
7972 F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now.
7976 // private utility function: 64 bit atomics on 32 bit host.
7978 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
7979 MachineBasicBlock *MBB,
7984 bool invSrc) const {
7985 // For the atomic bitwise operator, we generate
7986 // thisMBB (instructions are in pairs, except cmpxchg8b)
7987 // ld t1,t2 = [bitinstr.addr]
7989 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
7990 // op t5, t6 <- out1, out2, [bitinstr.val]
7991 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
7992 // mov ECX, EBX <- t5, t6
7993 // mov EAX, EDX <- t1, t2
7994 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
7995 // mov t3, t4 <- EAX, EDX
7997 // result in out1, out2
7998 // fallthrough -->nextMBB
8000 const TargetRegisterClass *RC = X86::GR32RegisterClass;
8001 const unsigned LoadOpc = X86::MOV32rm;
8002 const unsigned copyOpc = X86::MOV32rr;
8003 const unsigned NotOpc = X86::NOT32r;
8004 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8005 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
8006 MachineFunction::iterator MBBIter = MBB;
8009 /// First build the CFG
8010 MachineFunction *F = MBB->getParent();
8011 MachineBasicBlock *thisMBB = MBB;
8012 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
8013 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
8014 F->insert(MBBIter, newMBB);
8015 F->insert(MBBIter, nextMBB);
8017 // Move all successors to thisMBB to nextMBB
8018 nextMBB->transferSuccessors(thisMBB);
8020 // Update thisMBB to fall through to newMBB
8021 thisMBB->addSuccessor(newMBB);
8023 // newMBB jumps to itself and fall through to nextMBB
8024 newMBB->addSuccessor(nextMBB);
8025 newMBB->addSuccessor(newMBB);
8027 DebugLoc dl = bInstr->getDebugLoc();
8028 // Insert instructions into newMBB based on incoming instruction
8029 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
8030 assert(bInstr->getNumOperands() < X86AddrNumOperands + 14 &&
8031 "unexpected number of operands");
8032 MachineOperand& dest1Oper = bInstr->getOperand(0);
8033 MachineOperand& dest2Oper = bInstr->getOperand(1);
8034 MachineOperand* argOpers[2 + X86AddrNumOperands];
8035 for (int i=0; i < 2 + X86AddrNumOperands; ++i)
8036 argOpers[i] = &bInstr->getOperand(i+2);
8038 // x86 address has 5 operands: base, index, scale, displacement, and segment.
8039 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3]
8041 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
8042 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1);
8043 for (int i=0; i <= lastAddrIndx; ++i)
8044 (*MIB).addOperand(*argOpers[i]);
8045 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
8046 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
8047 // add 4 to displacement.
8048 for (int i=0; i <= lastAddrIndx-2; ++i)
8049 (*MIB).addOperand(*argOpers[i]);
8050 MachineOperand newOp3 = *(argOpers[3]);
8052 newOp3.setImm(newOp3.getImm()+4);
8054 newOp3.setOffset(newOp3.getOffset()+4);
8055 (*MIB).addOperand(newOp3);
8056 (*MIB).addOperand(*argOpers[lastAddrIndx]);
8058 // t3/4 are defined later, at the bottom of the loop
8059 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
8060 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
8061 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg())
8062 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
8063 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
8064 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
8066 // The subsequent operations should be using the destination registers of
8067 //the PHI instructions.
8069 t1 = F->getRegInfo().createVirtualRegister(RC);
8070 t2 = F->getRegInfo().createVirtualRegister(RC);
8071 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t1).addReg(dest1Oper.getReg());
8072 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t2).addReg(dest2Oper.getReg());
8074 t1 = dest1Oper.getReg();
8075 t2 = dest2Oper.getReg();
8078 int valArgIndx = lastAddrIndx + 1;
8079 assert((argOpers[valArgIndx]->isReg() ||
8080 argOpers[valArgIndx]->isImm()) &&
8082 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
8083 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
8084 if (argOpers[valArgIndx]->isReg())
8085 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5);
8087 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
8088 if (regOpcL != X86::MOV32rr)
8090 (*MIB).addOperand(*argOpers[valArgIndx]);
8091 assert(argOpers[valArgIndx + 1]->isReg() ==
8092 argOpers[valArgIndx]->isReg());
8093 assert(argOpers[valArgIndx + 1]->isImm() ==
8094 argOpers[valArgIndx]->isImm());
8095 if (argOpers[valArgIndx + 1]->isReg())
8096 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
8098 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
8099 if (regOpcH != X86::MOV32rr)
8101 (*MIB).addOperand(*argOpers[valArgIndx + 1]);
8103 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EAX);
8105 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EDX);
8108 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EBX);
8110 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::ECX);
8113 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
8114 for (int i=0; i <= lastAddrIndx; ++i)
8115 (*MIB).addOperand(*argOpers[i]);
8117 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
8118 (*MIB).setMemRefs(bInstr->memoperands_begin(),
8119 bInstr->memoperands_end());
8121 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), t3);
8122 MIB.addReg(X86::EAX);
8123 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), t4);
8124 MIB.addReg(X86::EDX);
8127 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
8129 F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now.
8133 // private utility function
8135 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
8136 MachineBasicBlock *MBB,
8137 unsigned cmovOpc) const {
8138 // For the atomic min/max operator, we generate
8141 // ld t1 = [min/max.addr]
8142 // mov t2 = [min/max.val]
8144 // cmov[cond] t2 = t1
8146 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
8148 // fallthrough -->nextMBB
8150 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8151 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
8152 MachineFunction::iterator MBBIter = MBB;
8155 /// First build the CFG
8156 MachineFunction *F = MBB->getParent();
8157 MachineBasicBlock *thisMBB = MBB;
8158 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
8159 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
8160 F->insert(MBBIter, newMBB);
8161 F->insert(MBBIter, nextMBB);
8163 // Move all successors of thisMBB to nextMBB
8164 nextMBB->transferSuccessors(thisMBB);
8166 // Update thisMBB to fall through to newMBB
8167 thisMBB->addSuccessor(newMBB);
8169 // newMBB jumps to newMBB and fall through to nextMBB
8170 newMBB->addSuccessor(nextMBB);
8171 newMBB->addSuccessor(newMBB);
8173 DebugLoc dl = mInstr->getDebugLoc();
8174 // Insert instructions into newMBB based on incoming instruction
8175 assert(mInstr->getNumOperands() < X86AddrNumOperands + 4 &&
8176 "unexpected number of operands");
8177 MachineOperand& destOper = mInstr->getOperand(0);
8178 MachineOperand* argOpers[2 + X86AddrNumOperands];
8179 int numArgs = mInstr->getNumOperands() - 1;
8180 for (int i=0; i < numArgs; ++i)
8181 argOpers[i] = &mInstr->getOperand(i+1);
8183 // x86 address has 4 operands: base, index, scale, and displacement
8184 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3]
8185 int valArgIndx = lastAddrIndx + 1;
8187 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
8188 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1);
8189 for (int i=0; i <= lastAddrIndx; ++i)
8190 (*MIB).addOperand(*argOpers[i]);
8192 // We only support register and immediate values
8193 assert((argOpers[valArgIndx]->isReg() ||
8194 argOpers[valArgIndx]->isImm()) &&
8197 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
8198 if (argOpers[valArgIndx]->isReg())
8199 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
8201 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
8202 (*MIB).addOperand(*argOpers[valArgIndx]);
8204 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), X86::EAX);
8207 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr));
8212 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
8213 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3);
8217 // Cmp and exchange if none has modified the memory location
8218 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32));
8219 for (int i=0; i <= lastAddrIndx; ++i)
8220 (*MIB).addOperand(*argOpers[i]);
8222 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
8223 (*MIB).setMemRefs(mInstr->memoperands_begin(),
8224 mInstr->memoperands_end());
8226 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), destOper.getReg());
8227 MIB.addReg(X86::EAX);
8230 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
8232 F->DeleteMachineInstr(mInstr); // The pseudo instruction is gone now.
8236 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
8237 // all of this code can be replaced with that in the .td file.
8239 X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB,
8240 unsigned numArgs, bool memArg) const {
8242 MachineFunction *F = BB->getParent();
8243 DebugLoc dl = MI->getDebugLoc();
8244 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8248 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm;
8250 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr;
8252 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(Opc));
8254 for (unsigned i = 0; i < numArgs; ++i) {
8255 MachineOperand &Op = MI->getOperand(i+1);
8257 if (!(Op.isReg() && Op.isImplicit()))
8261 BuildMI(BB, dl, TII->get(X86::MOVAPSrr), MI->getOperand(0).getReg())
8264 F->DeleteMachineInstr(MI);
8270 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
8272 MachineBasicBlock *MBB) const {
8273 // Emit code to save XMM registers to the stack. The ABI says that the
8274 // number of registers to save is given in %al, so it's theoretically
8275 // possible to do an indirect jump trick to avoid saving all of them,
8276 // however this code takes a simpler approach and just executes all
8277 // of the stores if %al is non-zero. It's less code, and it's probably
8278 // easier on the hardware branch predictor, and stores aren't all that
8279 // expensive anyway.
8281 // Create the new basic blocks. One block contains all the XMM stores,
8282 // and one block is the final destination regardless of whether any
8283 // stores were performed.
8284 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
8285 MachineFunction *F = MBB->getParent();
8286 MachineFunction::iterator MBBIter = MBB;
8288 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
8289 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
8290 F->insert(MBBIter, XMMSaveMBB);
8291 F->insert(MBBIter, EndMBB);
8294 // Move any original successors of MBB to the end block.
8295 EndMBB->transferSuccessors(MBB);
8296 // The original block will now fall through to the XMM save block.
8297 MBB->addSuccessor(XMMSaveMBB);
8298 // The XMMSaveMBB will fall through to the end block.
8299 XMMSaveMBB->addSuccessor(EndMBB);
8301 // Now add the instructions.
8302 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8303 DebugLoc DL = MI->getDebugLoc();
8305 unsigned CountReg = MI->getOperand(0).getReg();
8306 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
8307 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
8309 if (!Subtarget->isTargetWin64()) {
8310 // If %al is 0, branch around the XMM save block.
8311 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
8312 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
8313 MBB->addSuccessor(EndMBB);
8316 // In the XMM save block, save all the XMM argument registers.
8317 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
8318 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
8319 MachineMemOperand *MMO =
8320 F->getMachineMemOperand(
8321 PseudoSourceValue::getFixedStack(RegSaveFrameIndex),
8322 MachineMemOperand::MOStore, Offset,
8323 /*Size=*/16, /*Align=*/16);
8324 BuildMI(XMMSaveMBB, DL, TII->get(X86::MOVAPSmr))
8325 .addFrameIndex(RegSaveFrameIndex)
8326 .addImm(/*Scale=*/1)
8327 .addReg(/*IndexReg=*/0)
8328 .addImm(/*Disp=*/Offset)
8329 .addReg(/*Segment=*/0)
8330 .addReg(MI->getOperand(i).getReg())
8331 .addMemOperand(MMO);
8334 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
8340 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
8341 MachineBasicBlock *BB,
8342 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
8343 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8344 DebugLoc DL = MI->getDebugLoc();
8346 // To "insert" a SELECT_CC instruction, we actually have to insert the
8347 // diamond control-flow pattern. The incoming instruction knows the
8348 // destination vreg to set, the condition code register to branch on, the
8349 // true/false values to select between, and a branch opcode to use.
8350 const BasicBlock *LLVM_BB = BB->getBasicBlock();
8351 MachineFunction::iterator It = BB;
8357 // cmpTY ccX, r1, r2
8359 // fallthrough --> copy0MBB
8360 MachineBasicBlock *thisMBB = BB;
8361 MachineFunction *F = BB->getParent();
8362 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
8363 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
8365 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
8366 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
8367 F->insert(It, copy0MBB);
8368 F->insert(It, sinkMBB);
8369 // Update machine-CFG edges by first adding all successors of the current
8370 // block to the new block which will contain the Phi node for the select.
8371 // Also inform sdisel of the edge changes.
8372 for (MachineBasicBlock::succ_iterator I = BB->succ_begin(),
8373 E = BB->succ_end(); I != E; ++I) {
8374 EM->insert(std::make_pair(*I, sinkMBB));
8375 sinkMBB->addSuccessor(*I);
8377 // Next, remove all successors of the current block, and add the true
8378 // and fallthrough blocks as its successors.
8379 while (!BB->succ_empty())
8380 BB->removeSuccessor(BB->succ_begin());
8381 // Add the true and fallthrough blocks as its successors.
8382 BB->addSuccessor(copy0MBB);
8383 BB->addSuccessor(sinkMBB);
8386 // %FalseValue = ...
8387 // # fallthrough to sinkMBB
8390 // Update machine-CFG edges
8391 BB->addSuccessor(sinkMBB);
8394 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
8397 BuildMI(BB, DL, TII->get(X86::PHI), MI->getOperand(0).getReg())
8398 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
8399 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
8401 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
8406 X86TargetLowering::EmitLoweredMingwAlloca(MachineInstr *MI,
8407 MachineBasicBlock *BB,
8408 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
8409 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8410 DebugLoc DL = MI->getDebugLoc();
8411 MachineFunction *F = BB->getParent();
8413 // The lowering is pretty easy: we're just emitting the call to _alloca. The
8414 // non-trivial part is impdef of ESP.
8415 // FIXME: The code should be tweaked as soon as we'll try to do codegen for
8418 BuildMI(BB, DL, TII->get(X86::CALLpcrel32))
8419 .addExternalSymbol("_alloca")
8420 .addReg(X86::EAX, RegState::Implicit)
8421 .addReg(X86::ESP, RegState::Implicit)
8422 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
8423 .addReg(X86::ESP, RegState::Define | RegState::Implicit);
8425 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
8430 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
8431 MachineBasicBlock *BB,
8432 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
8433 switch (MI->getOpcode()) {
8434 default: assert(false && "Unexpected instr type to insert");
8435 case X86::MINGW_ALLOCA:
8436 return EmitLoweredMingwAlloca(MI, BB, EM);
8438 case X86::CMOV_V1I64:
8439 case X86::CMOV_FR32:
8440 case X86::CMOV_FR64:
8441 case X86::CMOV_V4F32:
8442 case X86::CMOV_V2F64:
8443 case X86::CMOV_V2I64:
8444 case X86::CMOV_GR16:
8445 case X86::CMOV_GR32:
8446 case X86::CMOV_RFP32:
8447 case X86::CMOV_RFP64:
8448 case X86::CMOV_RFP80:
8449 return EmitLoweredSelect(MI, BB, EM);
8451 case X86::FP32_TO_INT16_IN_MEM:
8452 case X86::FP32_TO_INT32_IN_MEM:
8453 case X86::FP32_TO_INT64_IN_MEM:
8454 case X86::FP64_TO_INT16_IN_MEM:
8455 case X86::FP64_TO_INT32_IN_MEM:
8456 case X86::FP64_TO_INT64_IN_MEM:
8457 case X86::FP80_TO_INT16_IN_MEM:
8458 case X86::FP80_TO_INT32_IN_MEM:
8459 case X86::FP80_TO_INT64_IN_MEM: {
8460 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8461 DebugLoc DL = MI->getDebugLoc();
8463 // Change the floating point control register to use "round towards zero"
8464 // mode when truncating to an integer value.
8465 MachineFunction *F = BB->getParent();
8466 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
8467 addFrameReference(BuildMI(BB, DL, TII->get(X86::FNSTCW16m)), CWFrameIdx);
8469 // Load the old value of the high byte of the control word...
8471 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
8472 addFrameReference(BuildMI(BB, DL, TII->get(X86::MOV16rm), OldCW),
8475 // Set the high part to be round to zero...
8476 addFrameReference(BuildMI(BB, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
8479 // Reload the modified control word now...
8480 addFrameReference(BuildMI(BB, DL, TII->get(X86::FLDCW16m)), CWFrameIdx);
8482 // Restore the memory image of control word to original value
8483 addFrameReference(BuildMI(BB, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
8486 // Get the X86 opcode to use.
8488 switch (MI->getOpcode()) {
8489 default: llvm_unreachable("illegal opcode!");
8490 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
8491 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
8492 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
8493 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
8494 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
8495 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
8496 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
8497 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
8498 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
8502 MachineOperand &Op = MI->getOperand(0);
8504 AM.BaseType = X86AddressMode::RegBase;
8505 AM.Base.Reg = Op.getReg();
8507 AM.BaseType = X86AddressMode::FrameIndexBase;
8508 AM.Base.FrameIndex = Op.getIndex();
8510 Op = MI->getOperand(1);
8512 AM.Scale = Op.getImm();
8513 Op = MI->getOperand(2);
8515 AM.IndexReg = Op.getImm();
8516 Op = MI->getOperand(3);
8517 if (Op.isGlobal()) {
8518 AM.GV = Op.getGlobal();
8520 AM.Disp = Op.getImm();
8522 addFullAddress(BuildMI(BB, DL, TII->get(Opc)), AM)
8523 .addReg(MI->getOperand(X86AddrNumOperands).getReg());
8525 // Reload the original control word now.
8526 addFrameReference(BuildMI(BB, DL, TII->get(X86::FLDCW16m)), CWFrameIdx);
8528 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
8531 // DBG_VALUE. Only the frame index case is done here.
8532 case X86::DBG_VALUE: {
8533 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8534 DebugLoc DL = MI->getDebugLoc();
8536 MachineFunction *F = BB->getParent();
8537 AM.BaseType = X86AddressMode::FrameIndexBase;
8538 AM.Base.FrameIndex = MI->getOperand(0).getImm();
8539 addFullAddress(BuildMI(BB, DL, TII->get(X86::DBG_VALUE)), AM).
8540 addImm(MI->getOperand(1).getImm()).
8541 addMetadata(MI->getOperand(2).getMetadata());
8542 F->DeleteMachineInstr(MI); // Remove pseudo.
8546 // String/text processing lowering.
8547 case X86::PCMPISTRM128REG:
8548 return EmitPCMP(MI, BB, 3, false /* in-mem */);
8549 case X86::PCMPISTRM128MEM:
8550 return EmitPCMP(MI, BB, 3, true /* in-mem */);
8551 case X86::PCMPESTRM128REG:
8552 return EmitPCMP(MI, BB, 5, false /* in mem */);
8553 case X86::PCMPESTRM128MEM:
8554 return EmitPCMP(MI, BB, 5, true /* in mem */);
8557 case X86::ATOMAND32:
8558 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
8559 X86::AND32ri, X86::MOV32rm,
8560 X86::LCMPXCHG32, X86::MOV32rr,
8561 X86::NOT32r, X86::EAX,
8562 X86::GR32RegisterClass);
8564 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
8565 X86::OR32ri, X86::MOV32rm,
8566 X86::LCMPXCHG32, X86::MOV32rr,
8567 X86::NOT32r, X86::EAX,
8568 X86::GR32RegisterClass);
8569 case X86::ATOMXOR32:
8570 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
8571 X86::XOR32ri, X86::MOV32rm,
8572 X86::LCMPXCHG32, X86::MOV32rr,
8573 X86::NOT32r, X86::EAX,
8574 X86::GR32RegisterClass);
8575 case X86::ATOMNAND32:
8576 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
8577 X86::AND32ri, X86::MOV32rm,
8578 X86::LCMPXCHG32, X86::MOV32rr,
8579 X86::NOT32r, X86::EAX,
8580 X86::GR32RegisterClass, true);
8581 case X86::ATOMMIN32:
8582 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
8583 case X86::ATOMMAX32:
8584 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
8585 case X86::ATOMUMIN32:
8586 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
8587 case X86::ATOMUMAX32:
8588 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
8590 case X86::ATOMAND16:
8591 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
8592 X86::AND16ri, X86::MOV16rm,
8593 X86::LCMPXCHG16, X86::MOV16rr,
8594 X86::NOT16r, X86::AX,
8595 X86::GR16RegisterClass);
8597 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
8598 X86::OR16ri, X86::MOV16rm,
8599 X86::LCMPXCHG16, X86::MOV16rr,
8600 X86::NOT16r, X86::AX,
8601 X86::GR16RegisterClass);
8602 case X86::ATOMXOR16:
8603 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
8604 X86::XOR16ri, X86::MOV16rm,
8605 X86::LCMPXCHG16, X86::MOV16rr,
8606 X86::NOT16r, X86::AX,
8607 X86::GR16RegisterClass);
8608 case X86::ATOMNAND16:
8609 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
8610 X86::AND16ri, X86::MOV16rm,
8611 X86::LCMPXCHG16, X86::MOV16rr,
8612 X86::NOT16r, X86::AX,
8613 X86::GR16RegisterClass, true);
8614 case X86::ATOMMIN16:
8615 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
8616 case X86::ATOMMAX16:
8617 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
8618 case X86::ATOMUMIN16:
8619 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
8620 case X86::ATOMUMAX16:
8621 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
8624 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
8625 X86::AND8ri, X86::MOV8rm,
8626 X86::LCMPXCHG8, X86::MOV8rr,
8627 X86::NOT8r, X86::AL,
8628 X86::GR8RegisterClass);
8630 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
8631 X86::OR8ri, X86::MOV8rm,
8632 X86::LCMPXCHG8, X86::MOV8rr,
8633 X86::NOT8r, X86::AL,
8634 X86::GR8RegisterClass);
8636 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
8637 X86::XOR8ri, X86::MOV8rm,
8638 X86::LCMPXCHG8, X86::MOV8rr,
8639 X86::NOT8r, X86::AL,
8640 X86::GR8RegisterClass);
8641 case X86::ATOMNAND8:
8642 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
8643 X86::AND8ri, X86::MOV8rm,
8644 X86::LCMPXCHG8, X86::MOV8rr,
8645 X86::NOT8r, X86::AL,
8646 X86::GR8RegisterClass, true);
8647 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
8648 // This group is for 64-bit host.
8649 case X86::ATOMAND64:
8650 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
8651 X86::AND64ri32, X86::MOV64rm,
8652 X86::LCMPXCHG64, X86::MOV64rr,
8653 X86::NOT64r, X86::RAX,
8654 X86::GR64RegisterClass);
8656 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
8657 X86::OR64ri32, X86::MOV64rm,
8658 X86::LCMPXCHG64, X86::MOV64rr,
8659 X86::NOT64r, X86::RAX,
8660 X86::GR64RegisterClass);
8661 case X86::ATOMXOR64:
8662 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
8663 X86::XOR64ri32, X86::MOV64rm,
8664 X86::LCMPXCHG64, X86::MOV64rr,
8665 X86::NOT64r, X86::RAX,
8666 X86::GR64RegisterClass);
8667 case X86::ATOMNAND64:
8668 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
8669 X86::AND64ri32, X86::MOV64rm,
8670 X86::LCMPXCHG64, X86::MOV64rr,
8671 X86::NOT64r, X86::RAX,
8672 X86::GR64RegisterClass, true);
8673 case X86::ATOMMIN64:
8674 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
8675 case X86::ATOMMAX64:
8676 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
8677 case X86::ATOMUMIN64:
8678 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
8679 case X86::ATOMUMAX64:
8680 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
8682 // This group does 64-bit operations on a 32-bit host.
8683 case X86::ATOMAND6432:
8684 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8685 X86::AND32rr, X86::AND32rr,
8686 X86::AND32ri, X86::AND32ri,
8688 case X86::ATOMOR6432:
8689 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8690 X86::OR32rr, X86::OR32rr,
8691 X86::OR32ri, X86::OR32ri,
8693 case X86::ATOMXOR6432:
8694 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8695 X86::XOR32rr, X86::XOR32rr,
8696 X86::XOR32ri, X86::XOR32ri,
8698 case X86::ATOMNAND6432:
8699 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8700 X86::AND32rr, X86::AND32rr,
8701 X86::AND32ri, X86::AND32ri,
8703 case X86::ATOMADD6432:
8704 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8705 X86::ADD32rr, X86::ADC32rr,
8706 X86::ADD32ri, X86::ADC32ri,
8708 case X86::ATOMSUB6432:
8709 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8710 X86::SUB32rr, X86::SBB32rr,
8711 X86::SUB32ri, X86::SBB32ri,
8713 case X86::ATOMSWAP6432:
8714 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8715 X86::MOV32rr, X86::MOV32rr,
8716 X86::MOV32ri, X86::MOV32ri,
8718 case X86::VASTART_SAVE_XMM_REGS:
8719 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
8723 //===----------------------------------------------------------------------===//
8724 // X86 Optimization Hooks
8725 //===----------------------------------------------------------------------===//
8727 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
8731 const SelectionDAG &DAG,
8732 unsigned Depth) const {
8733 unsigned Opc = Op.getOpcode();
8734 assert((Opc >= ISD::BUILTIN_OP_END ||
8735 Opc == ISD::INTRINSIC_WO_CHAIN ||
8736 Opc == ISD::INTRINSIC_W_CHAIN ||
8737 Opc == ISD::INTRINSIC_VOID) &&
8738 "Should use MaskedValueIsZero if you don't know whether Op"
8739 " is a target node!");
8741 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
8753 // These nodes' second result is a boolean.
8754 if (Op.getResNo() == 0)
8758 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
8759 Mask.getBitWidth() - 1);
8764 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
8765 /// node is a GlobalAddress + offset.
8766 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
8767 GlobalValue* &GA, int64_t &Offset) const{
8768 if (N->getOpcode() == X86ISD::Wrapper) {
8769 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
8770 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
8771 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
8775 return TargetLowering::isGAPlusOffset(N, GA, Offset);
8778 static bool EltsFromConsecutiveLoads(ShuffleVectorSDNode *N, unsigned NumElems,
8779 EVT EltVT, LoadSDNode *&LDBase,
8780 unsigned &LastLoadedElt,
8781 SelectionDAG &DAG, MachineFrameInfo *MFI,
8782 const TargetLowering &TLI) {
8784 LastLoadedElt = -1U;
8785 for (unsigned i = 0; i < NumElems; ++i) {
8786 if (N->getMaskElt(i) < 0) {
8792 SDValue Elt = DAG.getShuffleScalarElt(N, i);
8793 if (!Elt.getNode() ||
8794 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
8797 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
8799 LDBase = cast<LoadSDNode>(Elt.getNode());
8803 if (Elt.getOpcode() == ISD::UNDEF)
8806 LoadSDNode *LD = cast<LoadSDNode>(Elt);
8807 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
8814 /// PerformShuffleCombine - Combine a vector_shuffle that is equal to
8815 /// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load
8816 /// if the load addresses are consecutive, non-overlapping, and in the right
8817 /// order. In the case of v2i64, it will see if it can rewrite the
8818 /// shuffle to be an appropriate build vector so it can take advantage of
8819 // performBuildVectorCombine.
8820 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
8821 const TargetLowering &TLI) {
8822 DebugLoc dl = N->getDebugLoc();
8823 EVT VT = N->getValueType(0);
8824 EVT EltVT = VT.getVectorElementType();
8825 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
8826 unsigned NumElems = VT.getVectorNumElements();
8828 if (VT.getSizeInBits() != 128)
8831 // Try to combine a vector_shuffle into a 128-bit load.
8832 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
8833 LoadSDNode *LD = NULL;
8834 unsigned LastLoadedElt;
8835 if (!EltsFromConsecutiveLoads(SVN, NumElems, EltVT, LD, LastLoadedElt, DAG,
8839 if (LastLoadedElt == NumElems - 1) {
8840 if (DAG.InferPtrAlignment(LD->getBasePtr()) >= 16)
8841 return DAG.getLoad(VT, dl, LD->getChain(), LD->getBasePtr(),
8842 LD->getSrcValue(), LD->getSrcValueOffset(),
8843 LD->isVolatile(), LD->isNonTemporal(), 0);
8844 return DAG.getLoad(VT, dl, LD->getChain(), LD->getBasePtr(),
8845 LD->getSrcValue(), LD->getSrcValueOffset(),
8846 LD->isVolatile(), LD->isNonTemporal(),
8847 LD->getAlignment());
8848 } else if (NumElems == 4 && LastLoadedElt == 1) {
8849 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
8850 SDValue Ops[] = { LD->getChain(), LD->getBasePtr() };
8851 SDValue ResNode = DAG.getNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2);
8852 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, ResNode);
8857 /// PerformShuffleCombine - Detect vector gather/scatter index generation
8858 /// and convert it from being a bunch of shuffles and extracts to a simple
8859 /// store and scalar loads to extract the elements.
8860 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
8861 const TargetLowering &TLI) {
8862 SDValue InputVector = N->getOperand(0);
8864 // Only operate on vectors of 4 elements, where the alternative shuffling
8865 // gets to be more expensive.
8866 if (InputVector.getValueType() != MVT::v4i32)
8869 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
8870 // single use which is a sign-extend or zero-extend, and all elements are
8872 SmallVector<SDNode *, 4> Uses;
8873 unsigned ExtractedElements = 0;
8874 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
8875 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
8876 if (UI.getUse().getResNo() != InputVector.getResNo())
8879 SDNode *Extract = *UI;
8880 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
8883 if (Extract->getValueType(0) != MVT::i32)
8885 if (!Extract->hasOneUse())
8887 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
8888 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
8890 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
8893 // Record which element was extracted.
8894 ExtractedElements |=
8895 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
8897 Uses.push_back(Extract);
8900 // If not all the elements were used, this may not be worthwhile.
8901 if (ExtractedElements != 15)
8904 // Ok, we've now decided to do the transformation.
8905 DebugLoc dl = InputVector.getDebugLoc();
8907 // Store the value to a temporary stack slot.
8908 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
8909 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr, NULL, 0,
8912 // Replace each use (extract) with a load of the appropriate element.
8913 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
8914 UE = Uses.end(); UI != UE; ++UI) {
8915 SDNode *Extract = *UI;
8917 // Compute the element's address.
8918 SDValue Idx = Extract->getOperand(1);
8920 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
8921 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
8922 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
8924 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), OffsetVal, StackPtr);
8927 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch, ScalarAddr,
8928 NULL, 0, false, false, 0);
8930 // Replace the exact with the load.
8931 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
8934 // The replacement was made in place; don't return anything.
8938 /// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
8939 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
8940 const X86Subtarget *Subtarget) {
8941 DebugLoc DL = N->getDebugLoc();
8942 SDValue Cond = N->getOperand(0);
8943 // Get the LHS/RHS of the select.
8944 SDValue LHS = N->getOperand(1);
8945 SDValue RHS = N->getOperand(2);
8947 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
8948 // instructions match the semantics of the common C idiom x<y?x:y but not
8949 // x<=y?x:y, because of how they handle negative zero (which can be
8950 // ignored in unsafe-math mode).
8951 if (Subtarget->hasSSE2() &&
8952 (LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64) &&
8953 Cond.getOpcode() == ISD::SETCC) {
8954 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
8956 unsigned Opcode = 0;
8957 // Check for x CC y ? x : y.
8958 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
8959 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
8963 // Converting this to a min would handle NaNs incorrectly, and swapping
8964 // the operands would cause it to handle comparisons between positive
8965 // and negative zero incorrectly.
8966 if (!FiniteOnlyFPMath() &&
8967 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))) {
8968 if (!UnsafeFPMath &&
8969 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
8971 std::swap(LHS, RHS);
8973 Opcode = X86ISD::FMIN;
8976 // Converting this to a min would handle comparisons between positive
8977 // and negative zero incorrectly.
8978 if (!UnsafeFPMath &&
8979 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
8981 Opcode = X86ISD::FMIN;
8984 // Converting this to a min would handle both negative zeros and NaNs
8985 // incorrectly, but we can swap the operands to fix both.
8986 std::swap(LHS, RHS);
8990 Opcode = X86ISD::FMIN;
8994 // Converting this to a max would handle comparisons between positive
8995 // and negative zero incorrectly.
8996 if (!UnsafeFPMath &&
8997 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(LHS))
8999 Opcode = X86ISD::FMAX;
9002 // Converting this to a max would handle NaNs incorrectly, and swapping
9003 // the operands would cause it to handle comparisons between positive
9004 // and negative zero incorrectly.
9005 if (!FiniteOnlyFPMath() &&
9006 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))) {
9007 if (!UnsafeFPMath &&
9008 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
9010 std::swap(LHS, RHS);
9012 Opcode = X86ISD::FMAX;
9015 // Converting this to a max would handle both negative zeros and NaNs
9016 // incorrectly, but we can swap the operands to fix both.
9017 std::swap(LHS, RHS);
9021 Opcode = X86ISD::FMAX;
9024 // Check for x CC y ? y : x -- a min/max with reversed arms.
9025 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
9026 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
9030 // Converting this to a min would handle comparisons between positive
9031 // and negative zero incorrectly, and swapping the operands would
9032 // cause it to handle NaNs incorrectly.
9033 if (!UnsafeFPMath &&
9034 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
9035 if (!FiniteOnlyFPMath() &&
9036 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
9038 std::swap(LHS, RHS);
9040 Opcode = X86ISD::FMIN;
9043 // Converting this to a min would handle NaNs incorrectly.
9044 if (!UnsafeFPMath &&
9045 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
9047 Opcode = X86ISD::FMIN;
9050 // Converting this to a min would handle both negative zeros and NaNs
9051 // incorrectly, but we can swap the operands to fix both.
9052 std::swap(LHS, RHS);
9056 Opcode = X86ISD::FMIN;
9060 // Converting this to a max would handle NaNs incorrectly.
9061 if (!FiniteOnlyFPMath() &&
9062 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
9064 Opcode = X86ISD::FMAX;
9067 // Converting this to a max would handle comparisons between positive
9068 // and negative zero incorrectly, and swapping the operands would
9069 // cause it to handle NaNs incorrectly.
9070 if (!UnsafeFPMath &&
9071 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
9072 if (!FiniteOnlyFPMath() &&
9073 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
9075 std::swap(LHS, RHS);
9077 Opcode = X86ISD::FMAX;
9080 // Converting this to a max would handle both negative zeros and NaNs
9081 // incorrectly, but we can swap the operands to fix both.
9082 std::swap(LHS, RHS);
9086 Opcode = X86ISD::FMAX;
9092 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
9095 // If this is a select between two integer constants, try to do some
9097 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
9098 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
9099 // Don't do this for crazy integer types.
9100 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
9101 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
9102 // so that TrueC (the true value) is larger than FalseC.
9103 bool NeedsCondInvert = false;
9105 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
9106 // Efficiently invertible.
9107 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
9108 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
9109 isa<ConstantSDNode>(Cond.getOperand(1))))) {
9110 NeedsCondInvert = true;
9111 std::swap(TrueC, FalseC);
9114 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
9115 if (FalseC->getAPIntValue() == 0 &&
9116 TrueC->getAPIntValue().isPowerOf2()) {
9117 if (NeedsCondInvert) // Invert the condition if needed.
9118 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
9119 DAG.getConstant(1, Cond.getValueType()));
9121 // Zero extend the condition if needed.
9122 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
9124 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
9125 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
9126 DAG.getConstant(ShAmt, MVT::i8));
9129 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
9130 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
9131 if (NeedsCondInvert) // Invert the condition if needed.
9132 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
9133 DAG.getConstant(1, Cond.getValueType()));
9135 // Zero extend the condition if needed.
9136 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
9137 FalseC->getValueType(0), Cond);
9138 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
9139 SDValue(FalseC, 0));
9142 // Optimize cases that will turn into an LEA instruction. This requires
9143 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
9144 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
9145 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
9146 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
9148 bool isFastMultiplier = false;
9150 switch ((unsigned char)Diff) {
9152 case 1: // result = add base, cond
9153 case 2: // result = lea base( , cond*2)
9154 case 3: // result = lea base(cond, cond*2)
9155 case 4: // result = lea base( , cond*4)
9156 case 5: // result = lea base(cond, cond*4)
9157 case 8: // result = lea base( , cond*8)
9158 case 9: // result = lea base(cond, cond*8)
9159 isFastMultiplier = true;
9164 if (isFastMultiplier) {
9165 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
9166 if (NeedsCondInvert) // Invert the condition if needed.
9167 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
9168 DAG.getConstant(1, Cond.getValueType()));
9170 // Zero extend the condition if needed.
9171 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
9173 // Scale the condition by the difference.
9175 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
9176 DAG.getConstant(Diff, Cond.getValueType()));
9178 // Add the base if non-zero.
9179 if (FalseC->getAPIntValue() != 0)
9180 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
9181 SDValue(FalseC, 0));
9191 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
9192 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
9193 TargetLowering::DAGCombinerInfo &DCI) {
9194 DebugLoc DL = N->getDebugLoc();
9196 // If the flag operand isn't dead, don't touch this CMOV.
9197 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
9200 // If this is a select between two integer constants, try to do some
9201 // optimizations. Note that the operands are ordered the opposite of SELECT
9203 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
9204 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
9205 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
9206 // larger than FalseC (the false value).
9207 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
9209 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
9210 CC = X86::GetOppositeBranchCondition(CC);
9211 std::swap(TrueC, FalseC);
9214 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
9215 // This is efficient for any integer data type (including i8/i16) and
9217 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
9218 SDValue Cond = N->getOperand(3);
9219 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
9220 DAG.getConstant(CC, MVT::i8), Cond);
9222 // Zero extend the condition if needed.
9223 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
9225 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
9226 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
9227 DAG.getConstant(ShAmt, MVT::i8));
9228 if (N->getNumValues() == 2) // Dead flag value?
9229 return DCI.CombineTo(N, Cond, SDValue());
9233 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
9234 // for any integer data type, including i8/i16.
9235 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
9236 SDValue Cond = N->getOperand(3);
9237 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
9238 DAG.getConstant(CC, MVT::i8), Cond);
9240 // Zero extend the condition if needed.
9241 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
9242 FalseC->getValueType(0), Cond);
9243 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
9244 SDValue(FalseC, 0));
9246 if (N->getNumValues() == 2) // Dead flag value?
9247 return DCI.CombineTo(N, Cond, SDValue());
9251 // Optimize cases that will turn into an LEA instruction. This requires
9252 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
9253 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
9254 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
9255 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
9257 bool isFastMultiplier = false;
9259 switch ((unsigned char)Diff) {
9261 case 1: // result = add base, cond
9262 case 2: // result = lea base( , cond*2)
9263 case 3: // result = lea base(cond, cond*2)
9264 case 4: // result = lea base( , cond*4)
9265 case 5: // result = lea base(cond, cond*4)
9266 case 8: // result = lea base( , cond*8)
9267 case 9: // result = lea base(cond, cond*8)
9268 isFastMultiplier = true;
9273 if (isFastMultiplier) {
9274 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
9275 SDValue Cond = N->getOperand(3);
9276 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
9277 DAG.getConstant(CC, MVT::i8), Cond);
9278 // Zero extend the condition if needed.
9279 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
9281 // Scale the condition by the difference.
9283 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
9284 DAG.getConstant(Diff, Cond.getValueType()));
9286 // Add the base if non-zero.
9287 if (FalseC->getAPIntValue() != 0)
9288 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
9289 SDValue(FalseC, 0));
9290 if (N->getNumValues() == 2) // Dead flag value?
9291 return DCI.CombineTo(N, Cond, SDValue());
9301 /// PerformMulCombine - Optimize a single multiply with constant into two
9302 /// in order to implement it with two cheaper instructions, e.g.
9303 /// LEA + SHL, LEA + LEA.
9304 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
9305 TargetLowering::DAGCombinerInfo &DCI) {
9306 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
9309 EVT VT = N->getValueType(0);
9313 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
9316 uint64_t MulAmt = C->getZExtValue();
9317 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
9320 uint64_t MulAmt1 = 0;
9321 uint64_t MulAmt2 = 0;
9322 if ((MulAmt % 9) == 0) {
9324 MulAmt2 = MulAmt / 9;
9325 } else if ((MulAmt % 5) == 0) {
9327 MulAmt2 = MulAmt / 5;
9328 } else if ((MulAmt % 3) == 0) {
9330 MulAmt2 = MulAmt / 3;
9333 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
9334 DebugLoc DL = N->getDebugLoc();
9336 if (isPowerOf2_64(MulAmt2) &&
9337 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
9338 // If second multiplifer is pow2, issue it first. We want the multiply by
9339 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
9341 std::swap(MulAmt1, MulAmt2);
9344 if (isPowerOf2_64(MulAmt1))
9345 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
9346 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
9348 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
9349 DAG.getConstant(MulAmt1, VT));
9351 if (isPowerOf2_64(MulAmt2))
9352 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
9353 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
9355 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
9356 DAG.getConstant(MulAmt2, VT));
9358 // Do not add new nodes to DAG combiner worklist.
9359 DCI.CombineTo(N, NewMul, false);
9364 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
9365 SDValue N0 = N->getOperand(0);
9366 SDValue N1 = N->getOperand(1);
9367 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
9368 EVT VT = N0.getValueType();
9370 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
9371 // since the result of setcc_c is all zero's or all ones.
9372 if (N1C && N0.getOpcode() == ISD::AND &&
9373 N0.getOperand(1).getOpcode() == ISD::Constant) {
9374 SDValue N00 = N0.getOperand(0);
9375 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
9376 ((N00.getOpcode() == ISD::ANY_EXTEND ||
9377 N00.getOpcode() == ISD::ZERO_EXTEND) &&
9378 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
9379 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
9380 APInt ShAmt = N1C->getAPIntValue();
9381 Mask = Mask.shl(ShAmt);
9383 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
9384 N00, DAG.getConstant(Mask, VT));
9391 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
9393 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
9394 const X86Subtarget *Subtarget) {
9395 EVT VT = N->getValueType(0);
9396 if (!VT.isVector() && VT.isInteger() &&
9397 N->getOpcode() == ISD::SHL)
9398 return PerformSHLCombine(N, DAG);
9400 // On X86 with SSE2 support, we can transform this to a vector shift if
9401 // all elements are shifted by the same amount. We can't do this in legalize
9402 // because the a constant vector is typically transformed to a constant pool
9403 // so we have no knowledge of the shift amount.
9404 if (!Subtarget->hasSSE2())
9407 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
9410 SDValue ShAmtOp = N->getOperand(1);
9411 EVT EltVT = VT.getVectorElementType();
9412 DebugLoc DL = N->getDebugLoc();
9413 SDValue BaseShAmt = SDValue();
9414 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
9415 unsigned NumElts = VT.getVectorNumElements();
9417 for (; i != NumElts; ++i) {
9418 SDValue Arg = ShAmtOp.getOperand(i);
9419 if (Arg.getOpcode() == ISD::UNDEF) continue;
9423 for (; i != NumElts; ++i) {
9424 SDValue Arg = ShAmtOp.getOperand(i);
9425 if (Arg.getOpcode() == ISD::UNDEF) continue;
9426 if (Arg != BaseShAmt) {
9430 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
9431 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
9432 SDValue InVec = ShAmtOp.getOperand(0);
9433 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
9434 unsigned NumElts = InVec.getValueType().getVectorNumElements();
9436 for (; i != NumElts; ++i) {
9437 SDValue Arg = InVec.getOperand(i);
9438 if (Arg.getOpcode() == ISD::UNDEF) continue;
9442 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
9443 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
9444 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex();
9445 if (C->getZExtValue() == SplatIdx)
9446 BaseShAmt = InVec.getOperand(1);
9449 if (BaseShAmt.getNode() == 0)
9450 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
9451 DAG.getIntPtrConstant(0));
9455 // The shift amount is an i32.
9456 if (EltVT.bitsGT(MVT::i32))
9457 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
9458 else if (EltVT.bitsLT(MVT::i32))
9459 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt);
9461 // The shift amount is identical so we can do a vector shift.
9462 SDValue ValOp = N->getOperand(0);
9463 switch (N->getOpcode()) {
9465 llvm_unreachable("Unknown shift opcode!");
9468 if (VT == MVT::v2i64)
9469 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9470 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
9472 if (VT == MVT::v4i32)
9473 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9474 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
9476 if (VT == MVT::v8i16)
9477 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9478 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
9482 if (VT == MVT::v4i32)
9483 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9484 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32),
9486 if (VT == MVT::v8i16)
9487 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9488 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
9492 if (VT == MVT::v2i64)
9493 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9494 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
9496 if (VT == MVT::v4i32)
9497 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9498 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32),
9500 if (VT == MVT::v8i16)
9501 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9502 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
9509 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
9510 const X86Subtarget *Subtarget) {
9511 EVT VT = N->getValueType(0);
9512 if (VT != MVT::i64 || !Subtarget->is64Bit())
9515 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
9516 SDValue N0 = N->getOperand(0);
9517 SDValue N1 = N->getOperand(1);
9518 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
9520 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
9523 SDValue ShAmt0 = N0.getOperand(1);
9524 if (ShAmt0.getValueType() != MVT::i8)
9526 SDValue ShAmt1 = N1.getOperand(1);
9527 if (ShAmt1.getValueType() != MVT::i8)
9529 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
9530 ShAmt0 = ShAmt0.getOperand(0);
9531 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
9532 ShAmt1 = ShAmt1.getOperand(0);
9534 DebugLoc DL = N->getDebugLoc();
9535 unsigned Opc = X86ISD::SHLD;
9536 SDValue Op0 = N0.getOperand(0);
9537 SDValue Op1 = N1.getOperand(0);
9538 if (ShAmt0.getOpcode() == ISD::SUB) {
9540 std::swap(Op0, Op1);
9541 std::swap(ShAmt0, ShAmt1);
9544 if (ShAmt1.getOpcode() == ISD::SUB) {
9545 SDValue Sum = ShAmt1.getOperand(0);
9546 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
9547 if (SumC->getSExtValue() == 64 &&
9548 ShAmt1.getOperand(1) == ShAmt0)
9549 return DAG.getNode(Opc, DL, VT,
9551 DAG.getNode(ISD::TRUNCATE, DL,
9554 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
9555 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
9557 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == 64)
9558 return DAG.getNode(Opc, DL, VT,
9559 N0.getOperand(0), N1.getOperand(0),
9560 DAG.getNode(ISD::TRUNCATE, DL,
9567 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
9568 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
9569 const X86Subtarget *Subtarget) {
9570 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
9571 // the FP state in cases where an emms may be missing.
9572 // A preferable solution to the general problem is to figure out the right
9573 // places to insert EMMS. This qualifies as a quick hack.
9575 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
9576 StoreSDNode *St = cast<StoreSDNode>(N);
9577 EVT VT = St->getValue().getValueType();
9578 if (VT.getSizeInBits() != 64)
9581 const Function *F = DAG.getMachineFunction().getFunction();
9582 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
9583 bool F64IsLegal = !UseSoftFloat && !NoImplicitFloatOps
9584 && Subtarget->hasSSE2();
9585 if ((VT.isVector() ||
9586 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
9587 isa<LoadSDNode>(St->getValue()) &&
9588 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
9589 St->getChain().hasOneUse() && !St->isVolatile()) {
9590 SDNode* LdVal = St->getValue().getNode();
9592 int TokenFactorIndex = -1;
9593 SmallVector<SDValue, 8> Ops;
9594 SDNode* ChainVal = St->getChain().getNode();
9595 // Must be a store of a load. We currently handle two cases: the load
9596 // is a direct child, and it's under an intervening TokenFactor. It is
9597 // possible to dig deeper under nested TokenFactors.
9598 if (ChainVal == LdVal)
9599 Ld = cast<LoadSDNode>(St->getChain());
9600 else if (St->getValue().hasOneUse() &&
9601 ChainVal->getOpcode() == ISD::TokenFactor) {
9602 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) {
9603 if (ChainVal->getOperand(i).getNode() == LdVal) {
9604 TokenFactorIndex = i;
9605 Ld = cast<LoadSDNode>(St->getValue());
9607 Ops.push_back(ChainVal->getOperand(i));
9611 if (!Ld || !ISD::isNormalLoad(Ld))
9614 // If this is not the MMX case, i.e. we are just turning i64 load/store
9615 // into f64 load/store, avoid the transformation if there are multiple
9616 // uses of the loaded value.
9617 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
9620 DebugLoc LdDL = Ld->getDebugLoc();
9621 DebugLoc StDL = N->getDebugLoc();
9622 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
9623 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
9625 if (Subtarget->is64Bit() || F64IsLegal) {
9626 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
9627 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(),
9628 Ld->getBasePtr(), Ld->getSrcValue(),
9629 Ld->getSrcValueOffset(), Ld->isVolatile(),
9630 Ld->isNonTemporal(), Ld->getAlignment());
9631 SDValue NewChain = NewLd.getValue(1);
9632 if (TokenFactorIndex != -1) {
9633 Ops.push_back(NewChain);
9634 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
9637 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
9638 St->getSrcValue(), St->getSrcValueOffset(),
9639 St->isVolatile(), St->isNonTemporal(),
9640 St->getAlignment());
9643 // Otherwise, lower to two pairs of 32-bit loads / stores.
9644 SDValue LoAddr = Ld->getBasePtr();
9645 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
9646 DAG.getConstant(4, MVT::i32));
9648 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
9649 Ld->getSrcValue(), Ld->getSrcValueOffset(),
9650 Ld->isVolatile(), Ld->isNonTemporal(),
9651 Ld->getAlignment());
9652 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
9653 Ld->getSrcValue(), Ld->getSrcValueOffset()+4,
9654 Ld->isVolatile(), Ld->isNonTemporal(),
9655 MinAlign(Ld->getAlignment(), 4));
9657 SDValue NewChain = LoLd.getValue(1);
9658 if (TokenFactorIndex != -1) {
9659 Ops.push_back(LoLd);
9660 Ops.push_back(HiLd);
9661 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
9665 LoAddr = St->getBasePtr();
9666 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
9667 DAG.getConstant(4, MVT::i32));
9669 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
9670 St->getSrcValue(), St->getSrcValueOffset(),
9671 St->isVolatile(), St->isNonTemporal(),
9672 St->getAlignment());
9673 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
9675 St->getSrcValueOffset() + 4,
9677 St->isNonTemporal(),
9678 MinAlign(St->getAlignment(), 4));
9679 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
9684 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
9685 /// X86ISD::FXOR nodes.
9686 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
9687 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
9688 // F[X]OR(0.0, x) -> x
9689 // F[X]OR(x, 0.0) -> x
9690 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
9691 if (C->getValueAPF().isPosZero())
9692 return N->getOperand(1);
9693 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
9694 if (C->getValueAPF().isPosZero())
9695 return N->getOperand(0);
9699 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
9700 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
9701 // FAND(0.0, x) -> 0.0
9702 // FAND(x, 0.0) -> 0.0
9703 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
9704 if (C->getValueAPF().isPosZero())
9705 return N->getOperand(0);
9706 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
9707 if (C->getValueAPF().isPosZero())
9708 return N->getOperand(1);
9712 static SDValue PerformBTCombine(SDNode *N,
9714 TargetLowering::DAGCombinerInfo &DCI) {
9715 // BT ignores high bits in the bit index operand.
9716 SDValue Op1 = N->getOperand(1);
9717 if (Op1.hasOneUse()) {
9718 unsigned BitWidth = Op1.getValueSizeInBits();
9719 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
9720 APInt KnownZero, KnownOne;
9721 TargetLowering::TargetLoweringOpt TLO(DAG);
9722 TargetLowering &TLI = DAG.getTargetLoweringInfo();
9723 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
9724 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
9725 DCI.CommitTargetLoweringOpt(TLO);
9730 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
9731 SDValue Op = N->getOperand(0);
9732 if (Op.getOpcode() == ISD::BIT_CONVERT)
9733 Op = Op.getOperand(0);
9734 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
9735 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
9736 VT.getVectorElementType().getSizeInBits() ==
9737 OpVT.getVectorElementType().getSizeInBits()) {
9738 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, Op);
9743 // On X86 and X86-64, atomic operations are lowered to locked instructions.
9744 // Locked instructions, in turn, have implicit fence semantics (all memory
9745 // operations are flushed before issuing the locked instruction, and the
9746 // are not buffered), so we can fold away the common pattern of
9747 // fence-atomic-fence.
9748 static SDValue PerformMEMBARRIERCombine(SDNode* N, SelectionDAG &DAG) {
9749 SDValue atomic = N->getOperand(0);
9750 switch (atomic.getOpcode()) {
9751 case ISD::ATOMIC_CMP_SWAP:
9752 case ISD::ATOMIC_SWAP:
9753 case ISD::ATOMIC_LOAD_ADD:
9754 case ISD::ATOMIC_LOAD_SUB:
9755 case ISD::ATOMIC_LOAD_AND:
9756 case ISD::ATOMIC_LOAD_OR:
9757 case ISD::ATOMIC_LOAD_XOR:
9758 case ISD::ATOMIC_LOAD_NAND:
9759 case ISD::ATOMIC_LOAD_MIN:
9760 case ISD::ATOMIC_LOAD_MAX:
9761 case ISD::ATOMIC_LOAD_UMIN:
9762 case ISD::ATOMIC_LOAD_UMAX:
9768 SDValue fence = atomic.getOperand(0);
9769 if (fence.getOpcode() != ISD::MEMBARRIER)
9772 switch (atomic.getOpcode()) {
9773 case ISD::ATOMIC_CMP_SWAP:
9774 return DAG.UpdateNodeOperands(atomic, fence.getOperand(0),
9775 atomic.getOperand(1), atomic.getOperand(2),
9776 atomic.getOperand(3));
9777 case ISD::ATOMIC_SWAP:
9778 case ISD::ATOMIC_LOAD_ADD:
9779 case ISD::ATOMIC_LOAD_SUB:
9780 case ISD::ATOMIC_LOAD_AND:
9781 case ISD::ATOMIC_LOAD_OR:
9782 case ISD::ATOMIC_LOAD_XOR:
9783 case ISD::ATOMIC_LOAD_NAND:
9784 case ISD::ATOMIC_LOAD_MIN:
9785 case ISD::ATOMIC_LOAD_MAX:
9786 case ISD::ATOMIC_LOAD_UMIN:
9787 case ISD::ATOMIC_LOAD_UMAX:
9788 return DAG.UpdateNodeOperands(atomic, fence.getOperand(0),
9789 atomic.getOperand(1), atomic.getOperand(2));
9795 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG) {
9796 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
9797 // (and (i32 x86isd::setcc_carry), 1)
9798 // This eliminates the zext. This transformation is necessary because
9799 // ISD::SETCC is always legalized to i8.
9800 DebugLoc dl = N->getDebugLoc();
9801 SDValue N0 = N->getOperand(0);
9802 EVT VT = N->getValueType(0);
9803 if (N0.getOpcode() == ISD::AND &&
9805 N0.getOperand(0).hasOneUse()) {
9806 SDValue N00 = N0.getOperand(0);
9807 if (N00.getOpcode() != X86ISD::SETCC_CARRY)
9809 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
9810 if (!C || C->getZExtValue() != 1)
9812 return DAG.getNode(ISD::AND, dl, VT,
9813 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
9814 N00.getOperand(0), N00.getOperand(1)),
9815 DAG.getConstant(1, VT));
9821 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
9822 DAGCombinerInfo &DCI) const {
9823 SelectionDAG &DAG = DCI.DAG;
9824 switch (N->getOpcode()) {
9826 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, *this);
9827 case ISD::EXTRACT_VECTOR_ELT:
9828 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, *this);
9829 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget);
9830 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);
9831 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
9834 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget);
9835 case ISD::OR: return PerformOrCombine(N, DAG, Subtarget);
9836 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
9838 case X86ISD::FOR: return PerformFORCombine(N, DAG);
9839 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
9840 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
9841 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
9842 case ISD::MEMBARRIER: return PerformMEMBARRIERCombine(N, DAG);
9843 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG);
9849 //===----------------------------------------------------------------------===//
9850 // X86 Inline Assembly Support
9851 //===----------------------------------------------------------------------===//
9853 static bool LowerToBSwap(CallInst *CI) {
9854 // FIXME: this should verify that we are targetting a 486 or better. If not,
9855 // we will turn this bswap into something that will be lowered to logical ops
9856 // instead of emitting the bswap asm. For now, we don't support 486 or lower
9857 // so don't worry about this.
9859 // Verify this is a simple bswap.
9860 if (CI->getNumOperands() != 2 ||
9861 CI->getType() != CI->getOperand(1)->getType() ||
9862 !CI->getType()->isIntegerTy())
9865 const IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
9866 if (!Ty || Ty->getBitWidth() % 16 != 0)
9869 // Okay, we can do this xform, do so now.
9870 const Type *Tys[] = { Ty };
9871 Module *M = CI->getParent()->getParent()->getParent();
9872 Constant *Int = Intrinsic::getDeclaration(M, Intrinsic::bswap, Tys, 1);
9874 Value *Op = CI->getOperand(1);
9875 Op = CallInst::Create(Int, Op, CI->getName(), CI);
9877 CI->replaceAllUsesWith(Op);
9878 CI->eraseFromParent();
9882 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
9883 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
9884 std::vector<InlineAsm::ConstraintInfo> Constraints = IA->ParseConstraints();
9886 std::string AsmStr = IA->getAsmString();
9888 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
9889 SmallVector<StringRef, 4> AsmPieces;
9890 SplitString(AsmStr, AsmPieces, "\n"); // ; as separator?
9892 switch (AsmPieces.size()) {
9893 default: return false;
9895 AsmStr = AsmPieces[0];
9897 SplitString(AsmStr, AsmPieces, " \t"); // Split with whitespace.
9900 if (AsmPieces.size() == 2 &&
9901 (AsmPieces[0] == "bswap" ||
9902 AsmPieces[0] == "bswapq" ||
9903 AsmPieces[0] == "bswapl") &&
9904 (AsmPieces[1] == "$0" ||
9905 AsmPieces[1] == "${0:q}")) {
9906 // No need to check constraints, nothing other than the equivalent of
9907 // "=r,0" would be valid here.
9908 return LowerToBSwap(CI);
9910 // rorw $$8, ${0:w} --> llvm.bswap.i16
9911 if (CI->getType()->isIntegerTy(16) &&
9912 AsmPieces.size() == 3 &&
9913 (AsmPieces[0] == "rorw" || AsmPieces[0] == "rolw") &&
9914 AsmPieces[1] == "$$8," &&
9915 AsmPieces[2] == "${0:w}" &&
9916 IA->getConstraintString().compare(0, 5, "=r,0,") == 0) {
9918 const std::string &Constraints = IA->getConstraintString();
9919 SplitString(StringRef(Constraints).substr(5), AsmPieces, ",");
9920 std::sort(AsmPieces.begin(), AsmPieces.end());
9921 if (AsmPieces.size() == 4 &&
9922 AsmPieces[0] == "~{cc}" &&
9923 AsmPieces[1] == "~{dirflag}" &&
9924 AsmPieces[2] == "~{flags}" &&
9925 AsmPieces[3] == "~{fpsr}") {
9926 return LowerToBSwap(CI);
9931 if (CI->getType()->isIntegerTy(64) &&
9932 Constraints.size() >= 2 &&
9933 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
9934 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
9935 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
9936 SmallVector<StringRef, 4> Words;
9937 SplitString(AsmPieces[0], Words, " \t");
9938 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%eax") {
9940 SplitString(AsmPieces[1], Words, " \t");
9941 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%edx") {
9943 SplitString(AsmPieces[2], Words, " \t,");
9944 if (Words.size() == 3 && Words[0] == "xchgl" && Words[1] == "%eax" &&
9945 Words[2] == "%edx") {
9946 return LowerToBSwap(CI);
9958 /// getConstraintType - Given a constraint letter, return the type of
9959 /// constraint it is for this target.
9960 X86TargetLowering::ConstraintType
9961 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
9962 if (Constraint.size() == 1) {
9963 switch (Constraint[0]) {
9975 return C_RegisterClass;
9983 return TargetLowering::getConstraintType(Constraint);
9986 /// LowerXConstraint - try to replace an X constraint, which matches anything,
9987 /// with another that has more specific requirements based on the type of the
9988 /// corresponding operand.
9989 const char *X86TargetLowering::
9990 LowerXConstraint(EVT ConstraintVT) const {
9991 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
9992 // 'f' like normal targets.
9993 if (ConstraintVT.isFloatingPoint()) {
9994 if (Subtarget->hasSSE2())
9996 if (Subtarget->hasSSE1())
10000 return TargetLowering::LowerXConstraint(ConstraintVT);
10003 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
10004 /// vector. If it is invalid, don't add anything to Ops.
10005 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
10008 std::vector<SDValue>&Ops,
10009 SelectionDAG &DAG) const {
10010 SDValue Result(0, 0);
10012 switch (Constraint) {
10015 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
10016 if (C->getZExtValue() <= 31) {
10017 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
10023 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
10024 if (C->getZExtValue() <= 63) {
10025 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
10031 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
10032 if ((int8_t)C->getSExtValue() == C->getSExtValue()) {
10033 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
10039 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
10040 if (C->getZExtValue() <= 255) {
10041 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
10047 // 32-bit signed value
10048 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
10049 const ConstantInt *CI = C->getConstantIntValue();
10050 if (CI->isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
10051 C->getSExtValue())) {
10052 // Widen to 64 bits here to get it sign extended.
10053 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
10056 // FIXME gcc accepts some relocatable values here too, but only in certain
10057 // memory models; it's complicated.
10062 // 32-bit unsigned value
10063 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
10064 const ConstantInt *CI = C->getConstantIntValue();
10065 if (CI->isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
10066 C->getZExtValue())) {
10067 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
10071 // FIXME gcc accepts some relocatable values here too, but only in certain
10072 // memory models; it's complicated.
10076 // Literal immediates are always ok.
10077 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
10078 // Widen to 64 bits here to get it sign extended.
10079 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
10083 // If we are in non-pic codegen mode, we allow the address of a global (with
10084 // an optional displacement) to be used with 'i'.
10085 GlobalAddressSDNode *GA = 0;
10086 int64_t Offset = 0;
10088 // Match either (GA), (GA+C), (GA+C1+C2), etc.
10090 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
10091 Offset += GA->getOffset();
10093 } else if (Op.getOpcode() == ISD::ADD) {
10094 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
10095 Offset += C->getZExtValue();
10096 Op = Op.getOperand(0);
10099 } else if (Op.getOpcode() == ISD::SUB) {
10100 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
10101 Offset += -C->getZExtValue();
10102 Op = Op.getOperand(0);
10107 // Otherwise, this isn't something we can handle, reject it.
10111 GlobalValue *GV = GA->getGlobal();
10112 // If we require an extra load to get this address, as in PIC mode, we
10113 // can't accept it.
10114 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
10115 getTargetMachine())))
10119 Op = LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
10121 Op = DAG.getTargetGlobalAddress(GV, GA->getValueType(0), Offset);
10127 if (Result.getNode()) {
10128 Ops.push_back(Result);
10131 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, hasMemory,
10135 std::vector<unsigned> X86TargetLowering::
10136 getRegClassForInlineAsmConstraint(const std::string &Constraint,
10138 if (Constraint.size() == 1) {
10139 // FIXME: not handling fp-stack yet!
10140 switch (Constraint[0]) { // GCC X86 Constraint Letters
10141 default: break; // Unknown constraint letter
10142 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
10143 if (Subtarget->is64Bit()) {
10144 if (VT == MVT::i32)
10145 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX,
10146 X86::ESI, X86::EDI, X86::R8D, X86::R9D,
10147 X86::R10D,X86::R11D,X86::R12D,
10148 X86::R13D,X86::R14D,X86::R15D,
10149 X86::EBP, X86::ESP, 0);
10150 else if (VT == MVT::i16)
10151 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX,
10152 X86::SI, X86::DI, X86::R8W,X86::R9W,
10153 X86::R10W,X86::R11W,X86::R12W,
10154 X86::R13W,X86::R14W,X86::R15W,
10155 X86::BP, X86::SP, 0);
10156 else if (VT == MVT::i8)
10157 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL,
10158 X86::SIL, X86::DIL, X86::R8B,X86::R9B,
10159 X86::R10B,X86::R11B,X86::R12B,
10160 X86::R13B,X86::R14B,X86::R15B,
10161 X86::BPL, X86::SPL, 0);
10163 else if (VT == MVT::i64)
10164 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX,
10165 X86::RSI, X86::RDI, X86::R8, X86::R9,
10166 X86::R10, X86::R11, X86::R12,
10167 X86::R13, X86::R14, X86::R15,
10168 X86::RBP, X86::RSP, 0);
10172 // 32-bit fallthrough
10173 case 'Q': // Q_REGS
10174 if (VT == MVT::i32)
10175 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0);
10176 else if (VT == MVT::i16)
10177 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0);
10178 else if (VT == MVT::i8)
10179 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0);
10180 else if (VT == MVT::i64)
10181 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 0);
10186 return std::vector<unsigned>();
10189 std::pair<unsigned, const TargetRegisterClass*>
10190 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
10192 // First, see if this is a constraint that directly corresponds to an LLVM
10194 if (Constraint.size() == 1) {
10195 // GCC Constraint Letters
10196 switch (Constraint[0]) {
10198 case 'r': // GENERAL_REGS
10199 case 'l': // INDEX_REGS
10201 return std::make_pair(0U, X86::GR8RegisterClass);
10202 if (VT == MVT::i16)
10203 return std::make_pair(0U, X86::GR16RegisterClass);
10204 if (VT == MVT::i32 || !Subtarget->is64Bit())
10205 return std::make_pair(0U, X86::GR32RegisterClass);
10206 return std::make_pair(0U, X86::GR64RegisterClass);
10207 case 'R': // LEGACY_REGS
10209 return std::make_pair(0U, X86::GR8_NOREXRegisterClass);
10210 if (VT == MVT::i16)
10211 return std::make_pair(0U, X86::GR16_NOREXRegisterClass);
10212 if (VT == MVT::i32 || !Subtarget->is64Bit())
10213 return std::make_pair(0U, X86::GR32_NOREXRegisterClass);
10214 return std::make_pair(0U, X86::GR64_NOREXRegisterClass);
10215 case 'f': // FP Stack registers.
10216 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
10217 // value to the correct fpstack register class.
10218 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
10219 return std::make_pair(0U, X86::RFP32RegisterClass);
10220 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
10221 return std::make_pair(0U, X86::RFP64RegisterClass);
10222 return std::make_pair(0U, X86::RFP80RegisterClass);
10223 case 'y': // MMX_REGS if MMX allowed.
10224 if (!Subtarget->hasMMX()) break;
10225 return std::make_pair(0U, X86::VR64RegisterClass);
10226 case 'Y': // SSE_REGS if SSE2 allowed
10227 if (!Subtarget->hasSSE2()) break;
10229 case 'x': // SSE_REGS if SSE1 allowed
10230 if (!Subtarget->hasSSE1()) break;
10232 switch (VT.getSimpleVT().SimpleTy) {
10234 // Scalar SSE types.
10237 return std::make_pair(0U, X86::FR32RegisterClass);
10240 return std::make_pair(0U, X86::FR64RegisterClass);
10248 return std::make_pair(0U, X86::VR128RegisterClass);
10254 // Use the default implementation in TargetLowering to convert the register
10255 // constraint into a member of a register class.
10256 std::pair<unsigned, const TargetRegisterClass*> Res;
10257 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
10259 // Not found as a standard register?
10260 if (Res.second == 0) {
10261 // Map st(0) -> st(7) -> ST0
10262 if (Constraint.size() == 7 && Constraint[0] == '{' &&
10263 tolower(Constraint[1]) == 's' &&
10264 tolower(Constraint[2]) == 't' &&
10265 Constraint[3] == '(' &&
10266 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
10267 Constraint[5] == ')' &&
10268 Constraint[6] == '}') {
10270 Res.first = X86::ST0+Constraint[4]-'0';
10271 Res.second = X86::RFP80RegisterClass;
10275 // GCC allows "st(0)" to be called just plain "st".
10276 if (StringRef("{st}").equals_lower(Constraint)) {
10277 Res.first = X86::ST0;
10278 Res.second = X86::RFP80RegisterClass;
10283 if (StringRef("{flags}").equals_lower(Constraint)) {
10284 Res.first = X86::EFLAGS;
10285 Res.second = X86::CCRRegisterClass;
10289 // 'A' means EAX + EDX.
10290 if (Constraint == "A") {
10291 Res.first = X86::EAX;
10292 Res.second = X86::GR32_ADRegisterClass;
10298 // Otherwise, check to see if this is a register class of the wrong value
10299 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
10300 // turn into {ax},{dx}.
10301 if (Res.second->hasType(VT))
10302 return Res; // Correct type already, nothing to do.
10304 // All of the single-register GCC register classes map their values onto
10305 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
10306 // really want an 8-bit or 32-bit register, map to the appropriate register
10307 // class and return the appropriate register.
10308 if (Res.second == X86::GR16RegisterClass) {
10309 if (VT == MVT::i8) {
10310 unsigned DestReg = 0;
10311 switch (Res.first) {
10313 case X86::AX: DestReg = X86::AL; break;
10314 case X86::DX: DestReg = X86::DL; break;
10315 case X86::CX: DestReg = X86::CL; break;
10316 case X86::BX: DestReg = X86::BL; break;
10319 Res.first = DestReg;
10320 Res.second = X86::GR8RegisterClass;
10322 } else if (VT == MVT::i32) {
10323 unsigned DestReg = 0;
10324 switch (Res.first) {
10326 case X86::AX: DestReg = X86::EAX; break;
10327 case X86::DX: DestReg = X86::EDX; break;
10328 case X86::CX: DestReg = X86::ECX; break;
10329 case X86::BX: DestReg = X86::EBX; break;
10330 case X86::SI: DestReg = X86::ESI; break;
10331 case X86::DI: DestReg = X86::EDI; break;
10332 case X86::BP: DestReg = X86::EBP; break;
10333 case X86::SP: DestReg = X86::ESP; break;
10336 Res.first = DestReg;
10337 Res.second = X86::GR32RegisterClass;
10339 } else if (VT == MVT::i64) {
10340 unsigned DestReg = 0;
10341 switch (Res.first) {
10343 case X86::AX: DestReg = X86::RAX; break;
10344 case X86::DX: DestReg = X86::RDX; break;
10345 case X86::CX: DestReg = X86::RCX; break;
10346 case X86::BX: DestReg = X86::RBX; break;
10347 case X86::SI: DestReg = X86::RSI; break;
10348 case X86::DI: DestReg = X86::RDI; break;
10349 case X86::BP: DestReg = X86::RBP; break;
10350 case X86::SP: DestReg = X86::RSP; break;
10353 Res.first = DestReg;
10354 Res.second = X86::GR64RegisterClass;
10357 } else if (Res.second == X86::FR32RegisterClass ||
10358 Res.second == X86::FR64RegisterClass ||
10359 Res.second == X86::VR128RegisterClass) {
10360 // Handle references to XMM physical registers that got mapped into the
10361 // wrong class. This can happen with constraints like {xmm0} where the
10362 // target independent register mapper will just pick the first match it can
10363 // find, ignoring the required type.
10364 if (VT == MVT::f32)
10365 Res.second = X86::FR32RegisterClass;
10366 else if (VT == MVT::f64)
10367 Res.second = X86::FR64RegisterClass;
10368 else if (X86::VR128RegisterClass->hasType(VT))
10369 Res.second = X86::VR128RegisterClass;