1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
17 #include "X86InstrBuilder.h"
18 #include "X86ISelLowering.h"
19 #include "X86TargetMachine.h"
20 #include "X86TargetObjectFile.h"
21 #include "llvm/CallingConv.h"
22 #include "llvm/Constants.h"
23 #include "llvm/DerivedTypes.h"
24 #include "llvm/GlobalAlias.h"
25 #include "llvm/GlobalVariable.h"
26 #include "llvm/Function.h"
27 #include "llvm/Instructions.h"
28 #include "llvm/Intrinsics.h"
29 #include "llvm/LLVMContext.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/CodeGen/MachineModuleInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/PseudoSourceValue.h"
37 #include "llvm/MC/MCAsmInfo.h"
38 #include "llvm/MC/MCContext.h"
39 #include "llvm/MC/MCExpr.h"
40 #include "llvm/MC/MCSymbol.h"
41 #include "llvm/ADT/BitVector.h"
42 #include "llvm/ADT/SmallSet.h"
43 #include "llvm/ADT/Statistic.h"
44 #include "llvm/ADT/StringExtras.h"
45 #include "llvm/ADT/VectorExtras.h"
46 #include "llvm/Support/CommandLine.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/Dwarf.h"
49 #include "llvm/Support/ErrorHandling.h"
50 #include "llvm/Support/MathExtras.h"
51 #include "llvm/Support/raw_ostream.h"
53 using namespace dwarf;
55 STATISTIC(NumTailCalls, "Number of tail calls");
58 DisableMMX("disable-mmx", cl::Hidden, cl::desc("Disable use of MMX"));
60 // Forward declarations.
61 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
64 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
65 switch (TM.getSubtarget<X86Subtarget>().TargetType) {
66 default: llvm_unreachable("unknown subtarget type");
67 case X86Subtarget::isDarwin:
68 if (TM.getSubtarget<X86Subtarget>().is64Bit())
69 return new X8664_MachoTargetObjectFile();
70 return new TargetLoweringObjectFileMachO();
71 case X86Subtarget::isELF:
72 if (TM.getSubtarget<X86Subtarget>().is64Bit())
73 return new X8664_ELFTargetObjectFile(TM);
74 return new X8632_ELFTargetObjectFile(TM);
75 case X86Subtarget::isMingw:
76 case X86Subtarget::isCygwin:
77 case X86Subtarget::isWindows:
78 return new TargetLoweringObjectFileCOFF();
82 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
83 : TargetLowering(TM, createTLOF(TM)) {
84 Subtarget = &TM.getSubtarget<X86Subtarget>();
85 X86ScalarSSEf64 = Subtarget->hasSSE2();
86 X86ScalarSSEf32 = Subtarget->hasSSE1();
87 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
89 RegInfo = TM.getRegisterInfo();
92 // Set up the TargetLowering object.
94 // X86 is weird, it always uses i8 for shift amounts and setcc results.
95 setShiftAmountType(MVT::i8);
96 setBooleanContents(ZeroOrOneBooleanContent);
97 setSchedulingPreference(Sched::RegPressure);
98 setStackPointerRegisterToSaveRestore(X86StackPtr);
100 if (Subtarget->isTargetDarwin()) {
101 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
102 setUseUnderscoreSetJmp(false);
103 setUseUnderscoreLongJmp(false);
104 } else if (Subtarget->isTargetMingw()) {
105 // MS runtime is weird: it exports _setjmp, but longjmp!
106 setUseUnderscoreSetJmp(true);
107 setUseUnderscoreLongJmp(false);
109 setUseUnderscoreSetJmp(true);
110 setUseUnderscoreLongJmp(true);
113 // Set up the register classes.
114 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
115 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
116 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
117 if (Subtarget->is64Bit())
118 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
120 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
122 // We don't accept any truncstore of integer registers.
123 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
124 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
125 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
126 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
127 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
128 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
130 // SETOEQ and SETUNE require checking two conditions.
131 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
132 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
133 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
134 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
135 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
136 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
138 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
140 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
141 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
142 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
144 if (Subtarget->is64Bit()) {
145 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
146 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
147 } else if (!UseSoftFloat) {
148 // We have an algorithm for SSE2->double, and we turn this into a
149 // 64-bit FILD followed by conditional FADD for other targets.
150 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
151 // We have an algorithm for SSE2, and we turn this into a 64-bit
152 // FILD for other targets.
153 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
156 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
158 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
159 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
162 // SSE has no i16 to fp conversion, only i32
163 if (X86ScalarSSEf32) {
164 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
165 // f32 and f64 cases are Legal, f80 case is not
166 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
168 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
169 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
172 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
173 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
176 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
177 // are Legal, f80 is custom lowered.
178 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
179 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
181 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
183 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
184 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
186 if (X86ScalarSSEf32) {
187 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
188 // f32 and f64 cases are Legal, f80 case is not
189 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
191 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
192 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
195 // Handle FP_TO_UINT by promoting the destination to a larger signed
197 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
198 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
199 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
201 if (Subtarget->is64Bit()) {
202 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
203 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
204 } else if (!UseSoftFloat) {
205 if (X86ScalarSSEf32 && !Subtarget->hasSSE3())
206 // Expand FP_TO_UINT into a select.
207 // FIXME: We would like to use a Custom expander here eventually to do
208 // the optimal thing for SSE vs. the default expansion in the legalizer.
209 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
211 // With SSE3 we can use fisttpll to convert to a signed i64; without
212 // SSE, we're stuck with a fistpll.
213 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
216 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
217 if (!X86ScalarSSEf64) {
218 setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand);
219 setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand);
220 if (Subtarget->is64Bit()) {
221 setOperationAction(ISD::BIT_CONVERT , MVT::f64 , Expand);
222 // Without SSE, i64->f64 goes through memory; i64->MMX is Legal.
223 if (Subtarget->hasMMX() && !DisableMMX)
224 setOperationAction(ISD::BIT_CONVERT , MVT::i64 , Custom);
226 setOperationAction(ISD::BIT_CONVERT , MVT::i64 , Expand);
230 // Scalar integer divide and remainder are lowered to use operations that
231 // produce two results, to match the available instructions. This exposes
232 // the two-result form to trivial CSE, which is able to combine x/y and x%y
233 // into a single instruction.
235 // Scalar integer multiply-high is also lowered to use two-result
236 // operations, to match the available instructions. However, plain multiply
237 // (low) operations are left as Legal, as there are single-result
238 // instructions for this in x86. Using the two-result multiply instructions
239 // when both high and low results are needed must be arranged by dagcombine.
240 setOperationAction(ISD::MULHS , MVT::i8 , Expand);
241 setOperationAction(ISD::MULHU , MVT::i8 , Expand);
242 setOperationAction(ISD::SDIV , MVT::i8 , Expand);
243 setOperationAction(ISD::UDIV , MVT::i8 , Expand);
244 setOperationAction(ISD::SREM , MVT::i8 , Expand);
245 setOperationAction(ISD::UREM , MVT::i8 , Expand);
246 setOperationAction(ISD::MULHS , MVT::i16 , Expand);
247 setOperationAction(ISD::MULHU , MVT::i16 , Expand);
248 setOperationAction(ISD::SDIV , MVT::i16 , Expand);
249 setOperationAction(ISD::UDIV , MVT::i16 , Expand);
250 setOperationAction(ISD::SREM , MVT::i16 , Expand);
251 setOperationAction(ISD::UREM , MVT::i16 , Expand);
252 setOperationAction(ISD::MULHS , MVT::i32 , Expand);
253 setOperationAction(ISD::MULHU , MVT::i32 , Expand);
254 setOperationAction(ISD::SDIV , MVT::i32 , Expand);
255 setOperationAction(ISD::UDIV , MVT::i32 , Expand);
256 setOperationAction(ISD::SREM , MVT::i32 , Expand);
257 setOperationAction(ISD::UREM , MVT::i32 , Expand);
258 setOperationAction(ISD::MULHS , MVT::i64 , Expand);
259 setOperationAction(ISD::MULHU , MVT::i64 , Expand);
260 setOperationAction(ISD::SDIV , MVT::i64 , Expand);
261 setOperationAction(ISD::UDIV , MVT::i64 , Expand);
262 setOperationAction(ISD::SREM , MVT::i64 , Expand);
263 setOperationAction(ISD::UREM , MVT::i64 , Expand);
265 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
266 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
267 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
268 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
269 if (Subtarget->is64Bit())
270 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
271 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
272 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
273 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
274 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
275 setOperationAction(ISD::FREM , MVT::f32 , Expand);
276 setOperationAction(ISD::FREM , MVT::f64 , Expand);
277 setOperationAction(ISD::FREM , MVT::f80 , Expand);
278 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
280 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
281 setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
282 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
283 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
284 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
285 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
286 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
287 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
288 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
289 if (Subtarget->is64Bit()) {
290 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
291 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
292 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
295 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
296 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
298 // These should be promoted to a larger select which is supported.
299 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
300 // X86 wants to expand cmov itself.
301 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
302 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
303 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
304 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
305 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
306 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
307 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
308 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
309 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
310 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
311 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
312 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
313 if (Subtarget->is64Bit()) {
314 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
315 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
317 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
320 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
321 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
322 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
323 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
324 if (Subtarget->is64Bit())
325 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
326 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
327 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
328 if (Subtarget->is64Bit()) {
329 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
330 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
331 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
332 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
333 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
335 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
336 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
337 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
338 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
339 if (Subtarget->is64Bit()) {
340 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
341 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
342 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
345 if (Subtarget->hasSSE1())
346 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
348 if (!Subtarget->hasSSE2())
349 setOperationAction(ISD::MEMBARRIER , MVT::Other, Expand);
350 // On X86 and X86-64, atomic operations are lowered to locked instructions.
351 // Locked instructions, in turn, have implicit fence semantics (all memory
352 // operations are flushed before issuing the locked instruction, and they
353 // are not buffered), so we can fold away the common pattern of
354 // fence-atomic-fence.
355 setShouldFoldAtomicFences(true);
357 // Expand certain atomics
358 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Custom);
359 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Custom);
360 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
361 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom);
363 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i8, Custom);
364 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i16, Custom);
365 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Custom);
366 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
368 if (!Subtarget->is64Bit()) {
369 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
370 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
371 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
372 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
373 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
374 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
375 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
378 // FIXME - use subtarget debug flags
379 if (!Subtarget->isTargetDarwin() &&
380 !Subtarget->isTargetELF() &&
381 !Subtarget->isTargetCygMing()) {
382 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
385 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
386 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
387 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
388 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
389 if (Subtarget->is64Bit()) {
390 setExceptionPointerRegister(X86::RAX);
391 setExceptionSelectorRegister(X86::RDX);
393 setExceptionPointerRegister(X86::EAX);
394 setExceptionSelectorRegister(X86::EDX);
396 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
397 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
399 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
401 setOperationAction(ISD::TRAP, MVT::Other, Legal);
403 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
404 setOperationAction(ISD::VASTART , MVT::Other, Custom);
405 setOperationAction(ISD::VAEND , MVT::Other, Expand);
406 if (Subtarget->is64Bit()) {
407 setOperationAction(ISD::VAARG , MVT::Other, Custom);
408 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
410 setOperationAction(ISD::VAARG , MVT::Other, Expand);
411 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
414 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
415 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
416 if (Subtarget->is64Bit())
417 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
418 if (Subtarget->isTargetCygMing())
419 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
421 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
423 if (!UseSoftFloat && X86ScalarSSEf64) {
424 // f32 and f64 use SSE.
425 // Set up the FP register classes.
426 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
427 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
429 // Use ANDPD to simulate FABS.
430 setOperationAction(ISD::FABS , MVT::f64, Custom);
431 setOperationAction(ISD::FABS , MVT::f32, Custom);
433 // Use XORP to simulate FNEG.
434 setOperationAction(ISD::FNEG , MVT::f64, Custom);
435 setOperationAction(ISD::FNEG , MVT::f32, Custom);
437 // Use ANDPD and ORPD to simulate FCOPYSIGN.
438 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
439 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
441 // We don't support sin/cos/fmod
442 setOperationAction(ISD::FSIN , MVT::f64, Expand);
443 setOperationAction(ISD::FCOS , MVT::f64, Expand);
444 setOperationAction(ISD::FSIN , MVT::f32, Expand);
445 setOperationAction(ISD::FCOS , MVT::f32, Expand);
447 // Expand FP immediates into loads from the stack, except for the special
449 addLegalFPImmediate(APFloat(+0.0)); // xorpd
450 addLegalFPImmediate(APFloat(+0.0f)); // xorps
451 } else if (!UseSoftFloat && X86ScalarSSEf32) {
452 // Use SSE for f32, x87 for f64.
453 // Set up the FP register classes.
454 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
455 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
457 // Use ANDPS to simulate FABS.
458 setOperationAction(ISD::FABS , MVT::f32, Custom);
460 // Use XORP to simulate FNEG.
461 setOperationAction(ISD::FNEG , MVT::f32, Custom);
463 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
465 // Use ANDPS and ORPS to simulate FCOPYSIGN.
466 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
467 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
469 // We don't support sin/cos/fmod
470 setOperationAction(ISD::FSIN , MVT::f32, Expand);
471 setOperationAction(ISD::FCOS , MVT::f32, Expand);
473 // Special cases we handle for FP constants.
474 addLegalFPImmediate(APFloat(+0.0f)); // xorps
475 addLegalFPImmediate(APFloat(+0.0)); // FLD0
476 addLegalFPImmediate(APFloat(+1.0)); // FLD1
477 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
478 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
481 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
482 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
484 } else if (!UseSoftFloat) {
485 // f32 and f64 in x87.
486 // Set up the FP register classes.
487 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
488 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
490 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
491 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
492 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
493 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
496 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
497 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
499 addLegalFPImmediate(APFloat(+0.0)); // FLD0
500 addLegalFPImmediate(APFloat(+1.0)); // FLD1
501 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
502 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
503 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
504 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
505 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
506 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
509 // Long double always uses X87.
511 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
512 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
513 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
516 APFloat TmpFlt(+0.0);
517 TmpFlt.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
519 addLegalFPImmediate(TmpFlt); // FLD0
521 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
522 APFloat TmpFlt2(+1.0);
523 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
525 addLegalFPImmediate(TmpFlt2); // FLD1
526 TmpFlt2.changeSign();
527 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
531 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
532 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
536 // Always use a library call for pow.
537 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
538 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
539 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
541 setOperationAction(ISD::FLOG, MVT::f80, Expand);
542 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
543 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
544 setOperationAction(ISD::FEXP, MVT::f80, Expand);
545 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
547 // First set operation action for all vector types to either promote
548 // (for widening) or expand (for scalarization). Then we will selectively
549 // turn on ones that can be effectively codegen'd.
550 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
551 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
552 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
553 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
554 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
555 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
556 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
557 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
558 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
559 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
560 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
561 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
562 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
563 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
564 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
565 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
566 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
567 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
568 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
569 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
570 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
571 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
572 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
573 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
574 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
575 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
576 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
577 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
578 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
579 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
580 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
581 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
582 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
583 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
584 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
585 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
586 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
587 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
588 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
589 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
590 setOperationAction(ISD::VSETCC, (MVT::SimpleValueType)VT, Expand);
591 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
592 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
593 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
594 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
595 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
596 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand);
597 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand);
598 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
599 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
600 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand);
601 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand);
602 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand);
603 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand);
604 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand);
605 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
606 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
607 setTruncStoreAction((MVT::SimpleValueType)VT,
608 (MVT::SimpleValueType)InnerVT, Expand);
609 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
610 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
611 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
614 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
615 // with -msoft-float, disable use of MMX as well.
616 if (!UseSoftFloat && !DisableMMX && Subtarget->hasMMX()) {
617 addRegisterClass(MVT::v8i8, X86::VR64RegisterClass, false);
618 addRegisterClass(MVT::v4i16, X86::VR64RegisterClass, false);
619 addRegisterClass(MVT::v2i32, X86::VR64RegisterClass, false);
620 addRegisterClass(MVT::v2f32, X86::VR64RegisterClass, false);
621 addRegisterClass(MVT::v1i64, X86::VR64RegisterClass, false);
623 setOperationAction(ISD::ADD, MVT::v8i8, Legal);
624 setOperationAction(ISD::ADD, MVT::v4i16, Legal);
625 setOperationAction(ISD::ADD, MVT::v2i32, Legal);
626 setOperationAction(ISD::ADD, MVT::v1i64, Legal);
628 setOperationAction(ISD::SUB, MVT::v8i8, Legal);
629 setOperationAction(ISD::SUB, MVT::v4i16, Legal);
630 setOperationAction(ISD::SUB, MVT::v2i32, Legal);
631 setOperationAction(ISD::SUB, MVT::v1i64, Legal);
633 setOperationAction(ISD::MULHS, MVT::v4i16, Legal);
634 setOperationAction(ISD::MUL, MVT::v4i16, Legal);
636 setOperationAction(ISD::AND, MVT::v8i8, Promote);
637 AddPromotedToType (ISD::AND, MVT::v8i8, MVT::v1i64);
638 setOperationAction(ISD::AND, MVT::v4i16, Promote);
639 AddPromotedToType (ISD::AND, MVT::v4i16, MVT::v1i64);
640 setOperationAction(ISD::AND, MVT::v2i32, Promote);
641 AddPromotedToType (ISD::AND, MVT::v2i32, MVT::v1i64);
642 setOperationAction(ISD::AND, MVT::v1i64, Legal);
644 setOperationAction(ISD::OR, MVT::v8i8, Promote);
645 AddPromotedToType (ISD::OR, MVT::v8i8, MVT::v1i64);
646 setOperationAction(ISD::OR, MVT::v4i16, Promote);
647 AddPromotedToType (ISD::OR, MVT::v4i16, MVT::v1i64);
648 setOperationAction(ISD::OR, MVT::v2i32, Promote);
649 AddPromotedToType (ISD::OR, MVT::v2i32, MVT::v1i64);
650 setOperationAction(ISD::OR, MVT::v1i64, Legal);
652 setOperationAction(ISD::XOR, MVT::v8i8, Promote);
653 AddPromotedToType (ISD::XOR, MVT::v8i8, MVT::v1i64);
654 setOperationAction(ISD::XOR, MVT::v4i16, Promote);
655 AddPromotedToType (ISD::XOR, MVT::v4i16, MVT::v1i64);
656 setOperationAction(ISD::XOR, MVT::v2i32, Promote);
657 AddPromotedToType (ISD::XOR, MVT::v2i32, MVT::v1i64);
658 setOperationAction(ISD::XOR, MVT::v1i64, Legal);
660 setOperationAction(ISD::LOAD, MVT::v8i8, Promote);
661 AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v1i64);
662 setOperationAction(ISD::LOAD, MVT::v4i16, Promote);
663 AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v1i64);
664 setOperationAction(ISD::LOAD, MVT::v2i32, Promote);
665 AddPromotedToType (ISD::LOAD, MVT::v2i32, MVT::v1i64);
666 setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
667 AddPromotedToType (ISD::LOAD, MVT::v2f32, MVT::v1i64);
668 setOperationAction(ISD::LOAD, MVT::v1i64, Legal);
670 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom);
671 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom);
672 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Custom);
673 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f32, Custom);
674 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom);
676 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
677 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
678 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom);
679 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1i64, Custom);
681 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f32, Custom);
682 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Custom);
683 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom);
684 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom);
686 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i16, Custom);
688 setOperationAction(ISD::SELECT, MVT::v8i8, Promote);
689 setOperationAction(ISD::SELECT, MVT::v4i16, Promote);
690 setOperationAction(ISD::SELECT, MVT::v2i32, Promote);
691 setOperationAction(ISD::SELECT, MVT::v1i64, Custom);
692 setOperationAction(ISD::VSETCC, MVT::v8i8, Custom);
693 setOperationAction(ISD::VSETCC, MVT::v4i16, Custom);
694 setOperationAction(ISD::VSETCC, MVT::v2i32, Custom);
696 if (!X86ScalarSSEf64 && Subtarget->is64Bit()) {
697 setOperationAction(ISD::BIT_CONVERT, MVT::v8i8, Custom);
698 setOperationAction(ISD::BIT_CONVERT, MVT::v4i16, Custom);
699 setOperationAction(ISD::BIT_CONVERT, MVT::v2i32, Custom);
700 setOperationAction(ISD::BIT_CONVERT, MVT::v2f32, Custom);
701 setOperationAction(ISD::BIT_CONVERT, MVT::v1i64, Custom);
705 if (!UseSoftFloat && Subtarget->hasSSE1()) {
706 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
708 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
709 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
710 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
711 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
712 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
713 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
714 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
715 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
716 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
717 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
718 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
719 setOperationAction(ISD::VSETCC, MVT::v4f32, Custom);
722 if (!UseSoftFloat && Subtarget->hasSSE2()) {
723 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
725 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
726 // registers cannot be used even for integer operations.
727 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
728 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
729 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
730 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
732 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
733 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
734 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
735 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
736 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
737 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
738 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
739 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
740 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
741 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
742 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
743 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
744 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
745 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
746 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
747 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
749 setOperationAction(ISD::VSETCC, MVT::v2f64, Custom);
750 setOperationAction(ISD::VSETCC, MVT::v16i8, Custom);
751 setOperationAction(ISD::VSETCC, MVT::v8i16, Custom);
752 setOperationAction(ISD::VSETCC, MVT::v4i32, Custom);
754 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
755 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
756 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
757 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
758 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
760 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom);
761 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom);
762 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom);
763 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom);
764 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
766 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
767 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
768 EVT VT = (MVT::SimpleValueType)i;
769 // Do not attempt to custom lower non-power-of-2 vectors
770 if (!isPowerOf2_32(VT.getVectorNumElements()))
772 // Do not attempt to custom lower non-128-bit vectors
773 if (!VT.is128BitVector())
775 setOperationAction(ISD::BUILD_VECTOR,
776 VT.getSimpleVT().SimpleTy, Custom);
777 setOperationAction(ISD::VECTOR_SHUFFLE,
778 VT.getSimpleVT().SimpleTy, Custom);
779 setOperationAction(ISD::EXTRACT_VECTOR_ELT,
780 VT.getSimpleVT().SimpleTy, Custom);
783 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
784 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
785 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
786 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
787 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
788 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
790 if (Subtarget->is64Bit()) {
791 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
792 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
795 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
796 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) {
797 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
800 // Do not attempt to promote non-128-bit vectors
801 if (!VT.is128BitVector()) {
805 setOperationAction(ISD::AND, SVT, Promote);
806 AddPromotedToType (ISD::AND, SVT, MVT::v2i64);
807 setOperationAction(ISD::OR, SVT, Promote);
808 AddPromotedToType (ISD::OR, SVT, MVT::v2i64);
809 setOperationAction(ISD::XOR, SVT, Promote);
810 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64);
811 setOperationAction(ISD::LOAD, SVT, Promote);
812 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64);
813 setOperationAction(ISD::SELECT, SVT, Promote);
814 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64);
817 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
819 // Custom lower v2i64 and v2f64 selects.
820 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
821 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
822 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
823 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
825 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
826 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
827 if (!DisableMMX && Subtarget->hasMMX()) {
828 setOperationAction(ISD::FP_TO_SINT, MVT::v2i32, Custom);
829 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
833 if (Subtarget->hasSSE41()) {
834 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
835 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
836 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
837 setOperationAction(ISD::FRINT, MVT::f32, Legal);
838 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
839 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
840 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
841 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
842 setOperationAction(ISD::FRINT, MVT::f64, Legal);
843 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
845 // FIXME: Do we need to handle scalar-to-vector here?
846 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
848 // i8 and i16 vectors are custom , because the source register and source
849 // source memory operand types are not the same width. f32 vectors are
850 // custom since the immediate controlling the insert encodes additional
852 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
853 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
854 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
855 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
857 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
858 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
859 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
860 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
862 if (Subtarget->is64Bit()) {
863 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal);
864 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
868 if (Subtarget->hasSSE42()) {
869 setOperationAction(ISD::VSETCC, MVT::v2i64, Custom);
872 if (!UseSoftFloat && Subtarget->hasAVX()) {
873 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass);
874 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass);
875 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass);
876 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass);
878 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
879 setOperationAction(ISD::LOAD, MVT::v8i32, Legal);
880 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
881 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
882 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
883 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
884 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
885 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
886 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
887 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
888 //setOperationAction(ISD::BUILD_VECTOR, MVT::v8f32, Custom);
889 //setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Custom);
890 //setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8f32, Custom);
891 //setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
892 //setOperationAction(ISD::VSETCC, MVT::v8f32, Custom);
894 // Operations to consider commented out -v16i16 v32i8
895 //setOperationAction(ISD::ADD, MVT::v16i16, Legal);
896 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
897 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
898 //setOperationAction(ISD::SUB, MVT::v32i8, Legal);
899 //setOperationAction(ISD::SUB, MVT::v16i16, Legal);
900 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
901 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
902 //setOperationAction(ISD::MUL, MVT::v16i16, Legal);
903 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
904 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
905 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
906 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
907 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
908 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
910 setOperationAction(ISD::VSETCC, MVT::v4f64, Custom);
911 // setOperationAction(ISD::VSETCC, MVT::v32i8, Custom);
912 // setOperationAction(ISD::VSETCC, MVT::v16i16, Custom);
913 setOperationAction(ISD::VSETCC, MVT::v8i32, Custom);
915 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v32i8, Custom);
916 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i16, Custom);
917 // setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i16, Custom);
918 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i32, Custom);
919 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8f32, Custom);
921 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f64, Custom);
922 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i64, Custom);
923 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f64, Custom);
924 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i64, Custom);
925 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f64, Custom);
926 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f64, Custom);
929 // Not sure we want to do this since there are no 256-bit integer
932 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
933 // This includes 256-bit vectors
934 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; ++i) {
935 EVT VT = (MVT::SimpleValueType)i;
937 // Do not attempt to custom lower non-power-of-2 vectors
938 if (!isPowerOf2_32(VT.getVectorNumElements()))
941 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
942 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
943 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
946 if (Subtarget->is64Bit()) {
947 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i64, Custom);
948 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i64, Custom);
953 // Not sure we want to do this since there are no 256-bit integer
956 // Promote v32i8, v16i16, v8i32 load, select, and, or, xor to v4i64.
957 // Including 256-bit vectors
958 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; i++) {
959 EVT VT = (MVT::SimpleValueType)i;
961 if (!VT.is256BitVector()) {
964 setOperationAction(ISD::AND, VT, Promote);
965 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
966 setOperationAction(ISD::OR, VT, Promote);
967 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
968 setOperationAction(ISD::XOR, VT, Promote);
969 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
970 setOperationAction(ISD::LOAD, VT, Promote);
971 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
972 setOperationAction(ISD::SELECT, VT, Promote);
973 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
976 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
980 // We want to custom lower some of our intrinsics.
981 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
983 // Add/Sub/Mul with overflow operations are custom lowered.
984 setOperationAction(ISD::SADDO, MVT::i32, Custom);
985 setOperationAction(ISD::UADDO, MVT::i32, Custom);
986 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
987 setOperationAction(ISD::USUBO, MVT::i32, Custom);
988 setOperationAction(ISD::SMULO, MVT::i32, Custom);
990 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
991 // handle type legalization for these operations here.
993 // FIXME: We really should do custom legalization for addition and
994 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
995 // than generic legalization for 64-bit multiplication-with-overflow, though.
996 if (Subtarget->is64Bit()) {
997 setOperationAction(ISD::SADDO, MVT::i64, Custom);
998 setOperationAction(ISD::UADDO, MVT::i64, Custom);
999 setOperationAction(ISD::SSUBO, MVT::i64, Custom);
1000 setOperationAction(ISD::USUBO, MVT::i64, Custom);
1001 setOperationAction(ISD::SMULO, MVT::i64, Custom);
1004 if (!Subtarget->is64Bit()) {
1005 // These libcalls are not available in 32-bit.
1006 setLibcallName(RTLIB::SHL_I128, 0);
1007 setLibcallName(RTLIB::SRL_I128, 0);
1008 setLibcallName(RTLIB::SRA_I128, 0);
1011 // We have target-specific dag combine patterns for the following nodes:
1012 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1013 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1014 setTargetDAGCombine(ISD::BUILD_VECTOR);
1015 setTargetDAGCombine(ISD::SELECT);
1016 setTargetDAGCombine(ISD::SHL);
1017 setTargetDAGCombine(ISD::SRA);
1018 setTargetDAGCombine(ISD::SRL);
1019 setTargetDAGCombine(ISD::OR);
1020 setTargetDAGCombine(ISD::STORE);
1021 setTargetDAGCombine(ISD::ZERO_EXTEND);
1022 if (Subtarget->is64Bit())
1023 setTargetDAGCombine(ISD::MUL);
1025 computeRegisterProperties();
1027 // FIXME: These should be based on subtarget info. Plus, the values should
1028 // be smaller when we are in optimizing for size mode.
1029 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1030 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1031 maxStoresPerMemmove = 3; // For @llvm.memmove -> sequence of stores
1032 setPrefLoopAlignment(16);
1033 benefitFromCodePlacementOpt = true;
1037 MVT::SimpleValueType X86TargetLowering::getSetCCResultType(EVT VT) const {
1042 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1043 /// the desired ByVal argument alignment.
1044 static void getMaxByValAlign(const Type *Ty, unsigned &MaxAlign) {
1047 if (const VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1048 if (VTy->getBitWidth() == 128)
1050 } else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1051 unsigned EltAlign = 0;
1052 getMaxByValAlign(ATy->getElementType(), EltAlign);
1053 if (EltAlign > MaxAlign)
1054 MaxAlign = EltAlign;
1055 } else if (const StructType *STy = dyn_cast<StructType>(Ty)) {
1056 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1057 unsigned EltAlign = 0;
1058 getMaxByValAlign(STy->getElementType(i), EltAlign);
1059 if (EltAlign > MaxAlign)
1060 MaxAlign = EltAlign;
1068 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1069 /// function arguments in the caller parameter area. For X86, aggregates
1070 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1071 /// are at 4-byte boundaries.
1072 unsigned X86TargetLowering::getByValTypeAlignment(const Type *Ty) const {
1073 if (Subtarget->is64Bit()) {
1074 // Max of 8 and alignment of type.
1075 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1082 if (Subtarget->hasSSE1())
1083 getMaxByValAlign(Ty, Align);
1087 /// getOptimalMemOpType - Returns the target specific optimal type for load
1088 /// and store operations as a result of memset, memcpy, and memmove
1089 /// lowering. If DstAlign is zero that means it's safe to destination
1090 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1091 /// means there isn't a need to check it against alignment requirement,
1092 /// probably because the source does not need to be loaded. If
1093 /// 'NonScalarIntSafe' is true, that means it's safe to return a
1094 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
1095 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
1096 /// constant so it does not need to be loaded.
1097 /// It returns EVT::Other if the type should be determined using generic
1098 /// target-independent logic.
1100 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1101 unsigned DstAlign, unsigned SrcAlign,
1102 bool NonScalarIntSafe,
1104 MachineFunction &MF) const {
1105 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
1106 // linux. This is because the stack realignment code can't handle certain
1107 // cases like PR2962. This should be removed when PR2962 is fixed.
1108 const Function *F = MF.getFunction();
1109 if (NonScalarIntSafe &&
1110 !F->hasFnAttr(Attribute::NoImplicitFloat)) {
1112 (Subtarget->isUnalignedMemAccessFast() ||
1113 ((DstAlign == 0 || DstAlign >= 16) &&
1114 (SrcAlign == 0 || SrcAlign >= 16))) &&
1115 Subtarget->getStackAlignment() >= 16) {
1116 if (Subtarget->hasSSE2())
1118 if (Subtarget->hasSSE1())
1120 } else if (!MemcpyStrSrc && Size >= 8 &&
1121 !Subtarget->is64Bit() &&
1122 Subtarget->getStackAlignment() >= 8 &&
1123 Subtarget->hasSSE2()) {
1124 // Do not use f64 to lower memcpy if source is string constant. It's
1125 // better to use i32 to avoid the loads.
1129 if (Subtarget->is64Bit() && Size >= 8)
1134 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1135 /// current function. The returned value is a member of the
1136 /// MachineJumpTableInfo::JTEntryKind enum.
1137 unsigned X86TargetLowering::getJumpTableEncoding() const {
1138 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1140 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1141 Subtarget->isPICStyleGOT())
1142 return MachineJumpTableInfo::EK_Custom32;
1144 // Otherwise, use the normal jump table encoding heuristics.
1145 return TargetLowering::getJumpTableEncoding();
1148 /// getPICBaseSymbol - Return the X86-32 PIC base.
1150 X86TargetLowering::getPICBaseSymbol(const MachineFunction *MF,
1151 MCContext &Ctx) const {
1152 const MCAsmInfo &MAI = *getTargetMachine().getMCAsmInfo();
1153 return Ctx.GetOrCreateSymbol(Twine(MAI.getPrivateGlobalPrefix())+
1154 Twine(MF->getFunctionNumber())+"$pb");
1159 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1160 const MachineBasicBlock *MBB,
1161 unsigned uid,MCContext &Ctx) const{
1162 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1163 Subtarget->isPICStyleGOT());
1164 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1166 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1167 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1170 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1172 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1173 SelectionDAG &DAG) const {
1174 if (!Subtarget->is64Bit())
1175 // This doesn't have DebugLoc associated with it, but is not really the
1176 // same as a Register.
1177 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy());
1181 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1182 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1184 const MCExpr *X86TargetLowering::
1185 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1186 MCContext &Ctx) const {
1187 // X86-64 uses RIP relative addressing based on the jump table label.
1188 if (Subtarget->isPICStyleRIPRel())
1189 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1191 // Otherwise, the reference is relative to the PIC base.
1192 return MCSymbolRefExpr::Create(getPICBaseSymbol(MF, Ctx), Ctx);
1195 /// getFunctionAlignment - Return the Log2 alignment of this function.
1196 unsigned X86TargetLowering::getFunctionAlignment(const Function *F) const {
1197 return F->hasFnAttr(Attribute::OptimizeForSize) ? 0 : 4;
1200 //===----------------------------------------------------------------------===//
1201 // Return Value Calling Convention Implementation
1202 //===----------------------------------------------------------------------===//
1204 #include "X86GenCallingConv.inc"
1207 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
1208 const SmallVectorImpl<EVT> &OutTys,
1209 const SmallVectorImpl<ISD::ArgFlagsTy> &ArgsFlags,
1210 SelectionDAG &DAG) const {
1211 SmallVector<CCValAssign, 16> RVLocs;
1212 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1213 RVLocs, *DAG.getContext());
1214 return CCInfo.CheckReturn(OutTys, ArgsFlags, RetCC_X86);
1218 X86TargetLowering::LowerReturn(SDValue Chain,
1219 CallingConv::ID CallConv, bool isVarArg,
1220 const SmallVectorImpl<ISD::OutputArg> &Outs,
1221 DebugLoc dl, SelectionDAG &DAG) const {
1222 MachineFunction &MF = DAG.getMachineFunction();
1223 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1225 SmallVector<CCValAssign, 16> RVLocs;
1226 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1227 RVLocs, *DAG.getContext());
1228 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1230 // Add the regs to the liveout set for the function.
1231 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1232 for (unsigned i = 0; i != RVLocs.size(); ++i)
1233 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg()))
1234 MRI.addLiveOut(RVLocs[i].getLocReg());
1238 SmallVector<SDValue, 6> RetOps;
1239 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1240 // Operand #1 = Bytes To Pop
1241 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1244 // Copy the result values into the output registers.
1245 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1246 CCValAssign &VA = RVLocs[i];
1247 assert(VA.isRegLoc() && "Can only return in registers!");
1248 SDValue ValToCopy = Outs[i].Val;
1250 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1251 // the RET instruction and handled by the FP Stackifier.
1252 if (VA.getLocReg() == X86::ST0 ||
1253 VA.getLocReg() == X86::ST1) {
1254 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1255 // change the value to the FP stack register class.
1256 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1257 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1258 RetOps.push_back(ValToCopy);
1259 // Don't emit a copytoreg.
1263 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1264 // which is returned in RAX / RDX.
1265 if (Subtarget->is64Bit()) {
1266 EVT ValVT = ValToCopy.getValueType();
1267 if (ValVT.isVector() && ValVT.getSizeInBits() == 64) {
1268 ValToCopy = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, ValToCopy);
1269 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1)
1270 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, ValToCopy);
1274 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1275 Flag = Chain.getValue(1);
1278 // The x86-64 ABI for returning structs by value requires that we copy
1279 // the sret argument into %rax for the return. We saved the argument into
1280 // a virtual register in the entry block, so now we copy the value out
1282 if (Subtarget->is64Bit() &&
1283 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1284 MachineFunction &MF = DAG.getMachineFunction();
1285 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1286 unsigned Reg = FuncInfo->getSRetReturnReg();
1288 "SRetReturnReg should have been set in LowerFormalArguments().");
1289 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1291 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
1292 Flag = Chain.getValue(1);
1294 // RAX now acts like a return value.
1295 MRI.addLiveOut(X86::RAX);
1298 RetOps[0] = Chain; // Update chain.
1300 // Add the flag if we have it.
1302 RetOps.push_back(Flag);
1304 return DAG.getNode(X86ISD::RET_FLAG, dl,
1305 MVT::Other, &RetOps[0], RetOps.size());
1308 /// LowerCallResult - Lower the result values of a call into the
1309 /// appropriate copies out of appropriate physical registers.
1312 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1313 CallingConv::ID CallConv, bool isVarArg,
1314 const SmallVectorImpl<ISD::InputArg> &Ins,
1315 DebugLoc dl, SelectionDAG &DAG,
1316 SmallVectorImpl<SDValue> &InVals) const {
1318 // Assign locations to each value returned by this call.
1319 SmallVector<CCValAssign, 16> RVLocs;
1320 bool Is64Bit = Subtarget->is64Bit();
1321 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1322 RVLocs, *DAG.getContext());
1323 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1325 // Copy all of the result registers out of their specified physreg.
1326 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1327 CCValAssign &VA = RVLocs[i];
1328 EVT CopyVT = VA.getValVT();
1330 // If this is x86-64, and we disabled SSE, we can't return FP values
1331 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1332 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
1333 report_fatal_error("SSE register return with SSE disabled");
1336 // If this is a call to a function that returns an fp value on the floating
1337 // point stack, but where we prefer to use the value in xmm registers, copy
1338 // it out as F80 and use a truncate to move it from fp stack reg to xmm reg.
1339 if ((VA.getLocReg() == X86::ST0 ||
1340 VA.getLocReg() == X86::ST1) &&
1341 isScalarFPTypeInSSEReg(VA.getValVT())) {
1346 if (Is64Bit && CopyVT.isVector() && CopyVT.getSizeInBits() == 64) {
1347 // For x86-64, MMX values are returned in XMM0 / XMM1 except for v1i64.
1348 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1349 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1350 MVT::v2i64, InFlag).getValue(1);
1351 Val = Chain.getValue(0);
1352 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64,
1353 Val, DAG.getConstant(0, MVT::i64));
1355 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1356 MVT::i64, InFlag).getValue(1);
1357 Val = Chain.getValue(0);
1359 Val = DAG.getNode(ISD::BIT_CONVERT, dl, CopyVT, Val);
1361 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1362 CopyVT, InFlag).getValue(1);
1363 Val = Chain.getValue(0);
1365 InFlag = Chain.getValue(2);
1367 if (CopyVT != VA.getValVT()) {
1368 // Round the F80 the right size, which also moves to the appropriate xmm
1370 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1371 // This truncation won't change the value.
1372 DAG.getIntPtrConstant(1));
1375 InVals.push_back(Val);
1382 //===----------------------------------------------------------------------===//
1383 // C & StdCall & Fast Calling Convention implementation
1384 //===----------------------------------------------------------------------===//
1385 // StdCall calling convention seems to be standard for many Windows' API
1386 // routines and around. It differs from C calling convention just a little:
1387 // callee should clean up the stack, not caller. Symbols should be also
1388 // decorated in some fancy way :) It doesn't support any vector arguments.
1389 // For info on fast calling convention see Fast Calling Convention (tail call)
1390 // implementation LowerX86_32FastCCCallTo.
1392 /// CallIsStructReturn - Determines whether a call uses struct return
1394 static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1398 return Outs[0].Flags.isSRet();
1401 /// ArgsAreStructReturn - Determines whether a function uses struct
1402 /// return semantics.
1404 ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
1408 return Ins[0].Flags.isSRet();
1411 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the
1412 /// given CallingConvention value.
1413 CCAssignFn *X86TargetLowering::CCAssignFnForNode(CallingConv::ID CC) const {
1414 if (Subtarget->is64Bit()) {
1415 if (CC == CallingConv::GHC)
1416 return CC_X86_64_GHC;
1417 else if (Subtarget->isTargetWin64())
1418 return CC_X86_Win64_C;
1423 if (CC == CallingConv::X86_FastCall)
1424 return CC_X86_32_FastCall;
1425 else if (CC == CallingConv::X86_ThisCall)
1426 return CC_X86_32_ThisCall;
1427 else if (CC == CallingConv::Fast)
1428 return CC_X86_32_FastCC;
1429 else if (CC == CallingConv::GHC)
1430 return CC_X86_32_GHC;
1435 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1436 /// by "Src" to address "Dst" with size and alignment information specified by
1437 /// the specific parameter attribute. The copy will be passed as a byval
1438 /// function parameter.
1440 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1441 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1443 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1444 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1445 /*isVolatile*/false, /*AlwaysInline=*/true,
1449 /// IsTailCallConvention - Return true if the calling convention is one that
1450 /// supports tail call optimization.
1451 static bool IsTailCallConvention(CallingConv::ID CC) {
1452 return (CC == CallingConv::Fast || CC == CallingConv::GHC);
1455 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
1456 /// a tailcall target by changing its ABI.
1457 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC) {
1458 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
1462 X86TargetLowering::LowerMemArgument(SDValue Chain,
1463 CallingConv::ID CallConv,
1464 const SmallVectorImpl<ISD::InputArg> &Ins,
1465 DebugLoc dl, SelectionDAG &DAG,
1466 const CCValAssign &VA,
1467 MachineFrameInfo *MFI,
1469 // Create the nodes corresponding to a load from this parameter slot.
1470 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1471 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv);
1472 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1475 // If value is passed by pointer we have address passed instead of the value
1477 if (VA.getLocInfo() == CCValAssign::Indirect)
1478 ValVT = VA.getLocVT();
1480 ValVT = VA.getValVT();
1482 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1483 // changed with more analysis.
1484 // In case of tail call optimization mark all arguments mutable. Since they
1485 // could be overwritten by lowering of arguments in case of a tail call.
1486 if (Flags.isByVal()) {
1487 int FI = MFI->CreateFixedObject(Flags.getByValSize(),
1488 VA.getLocMemOffset(), isImmutable);
1489 return DAG.getFrameIndex(FI, getPointerTy());
1491 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
1492 VA.getLocMemOffset(), isImmutable);
1493 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1494 return DAG.getLoad(ValVT, dl, Chain, FIN,
1495 PseudoSourceValue::getFixedStack(FI), 0,
1501 X86TargetLowering::LowerFormalArguments(SDValue Chain,
1502 CallingConv::ID CallConv,
1504 const SmallVectorImpl<ISD::InputArg> &Ins,
1507 SmallVectorImpl<SDValue> &InVals)
1509 MachineFunction &MF = DAG.getMachineFunction();
1510 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1512 const Function* Fn = MF.getFunction();
1513 if (Fn->hasExternalLinkage() &&
1514 Subtarget->isTargetCygMing() &&
1515 Fn->getName() == "main")
1516 FuncInfo->setForceFramePointer(true);
1518 MachineFrameInfo *MFI = MF.getFrameInfo();
1519 bool Is64Bit = Subtarget->is64Bit();
1520 bool IsWin64 = Subtarget->isTargetWin64();
1522 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1523 "Var args not supported with calling convention fastcc or ghc");
1525 // Assign locations to all of the incoming arguments.
1526 SmallVector<CCValAssign, 16> ArgLocs;
1527 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1528 ArgLocs, *DAG.getContext());
1529 CCInfo.AnalyzeFormalArguments(Ins, CCAssignFnForNode(CallConv));
1531 unsigned LastVal = ~0U;
1533 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1534 CCValAssign &VA = ArgLocs[i];
1535 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1537 assert(VA.getValNo() != LastVal &&
1538 "Don't support value assigned to multiple locs yet");
1539 LastVal = VA.getValNo();
1541 if (VA.isRegLoc()) {
1542 EVT RegVT = VA.getLocVT();
1543 TargetRegisterClass *RC = NULL;
1544 if (RegVT == MVT::i32)
1545 RC = X86::GR32RegisterClass;
1546 else if (Is64Bit && RegVT == MVT::i64)
1547 RC = X86::GR64RegisterClass;
1548 else if (RegVT == MVT::f32)
1549 RC = X86::FR32RegisterClass;
1550 else if (RegVT == MVT::f64)
1551 RC = X86::FR64RegisterClass;
1552 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1553 RC = X86::VR128RegisterClass;
1554 else if (RegVT.isVector() && RegVT.getSizeInBits() == 64)
1555 RC = X86::VR64RegisterClass;
1557 llvm_unreachable("Unknown argument type!");
1559 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1560 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1562 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1563 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1565 if (VA.getLocInfo() == CCValAssign::SExt)
1566 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1567 DAG.getValueType(VA.getValVT()));
1568 else if (VA.getLocInfo() == CCValAssign::ZExt)
1569 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1570 DAG.getValueType(VA.getValVT()));
1571 else if (VA.getLocInfo() == CCValAssign::BCvt)
1572 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
1574 if (VA.isExtInLoc()) {
1575 // Handle MMX values passed in XMM regs.
1576 if (RegVT.isVector()) {
1577 ArgValue = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64,
1578 ArgValue, DAG.getConstant(0, MVT::i64));
1579 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
1581 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1584 assert(VA.isMemLoc());
1585 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
1588 // If value is passed via pointer - do a load.
1589 if (VA.getLocInfo() == CCValAssign::Indirect)
1590 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue, NULL, 0,
1593 InVals.push_back(ArgValue);
1596 // The x86-64 ABI for returning structs by value requires that we copy
1597 // the sret argument into %rax for the return. Save the argument into
1598 // a virtual register so that we can access it from the return points.
1599 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) {
1600 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1601 unsigned Reg = FuncInfo->getSRetReturnReg();
1603 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1604 FuncInfo->setSRetReturnReg(Reg);
1606 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1607 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1610 unsigned StackSize = CCInfo.getNextStackOffset();
1611 // Align stack specially for tail calls.
1612 if (FuncIsMadeTailCallSafe(CallConv))
1613 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1615 // If the function takes variable number of arguments, make a frame index for
1616 // the start of the first vararg value... for expansion of llvm.va_start.
1618 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
1619 CallConv != CallingConv::X86_ThisCall)) {
1620 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
1623 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1625 // FIXME: We should really autogenerate these arrays
1626 static const unsigned GPR64ArgRegsWin64[] = {
1627 X86::RCX, X86::RDX, X86::R8, X86::R9
1629 static const unsigned XMMArgRegsWin64[] = {
1630 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
1632 static const unsigned GPR64ArgRegs64Bit[] = {
1633 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1635 static const unsigned XMMArgRegs64Bit[] = {
1636 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1637 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1639 const unsigned *GPR64ArgRegs, *XMMArgRegs;
1642 TotalNumIntRegs = 4; TotalNumXMMRegs = 4;
1643 GPR64ArgRegs = GPR64ArgRegsWin64;
1644 XMMArgRegs = XMMArgRegsWin64;
1646 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1647 GPR64ArgRegs = GPR64ArgRegs64Bit;
1648 XMMArgRegs = XMMArgRegs64Bit;
1650 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1652 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs,
1655 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat);
1656 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
1657 "SSE register cannot be used when SSE is disabled!");
1658 assert(!(NumXMMRegs && UseSoftFloat && NoImplicitFloatOps) &&
1659 "SSE register cannot be used when SSE is disabled!");
1660 if (UseSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1())
1661 // Kernel mode asks for SSE to be disabled, so don't push them
1663 TotalNumXMMRegs = 0;
1665 // For X86-64, if there are vararg parameters that are passed via
1666 // registers, then we must store them to their spots on the stack so they
1667 // may be loaded by deferencing the result of va_next.
1668 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
1669 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
1670 FuncInfo->setRegSaveFrameIndex(
1671 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
1674 // Store the integer parameter registers.
1675 SmallVector<SDValue, 8> MemOps;
1676 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
1678 unsigned Offset = FuncInfo->getVarArgsGPOffset();
1679 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
1680 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
1681 DAG.getIntPtrConstant(Offset));
1682 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
1683 X86::GR64RegisterClass);
1684 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
1686 DAG.getStore(Val.getValue(1), dl, Val, FIN,
1687 PseudoSourceValue::getFixedStack(
1688 FuncInfo->getRegSaveFrameIndex()),
1689 Offset, false, false, 0);
1690 MemOps.push_back(Store);
1694 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
1695 // Now store the XMM (fp + vector) parameter registers.
1696 SmallVector<SDValue, 11> SaveXMMOps;
1697 SaveXMMOps.push_back(Chain);
1699 unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass);
1700 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
1701 SaveXMMOps.push_back(ALVal);
1703 SaveXMMOps.push_back(DAG.getIntPtrConstant(
1704 FuncInfo->getRegSaveFrameIndex()));
1705 SaveXMMOps.push_back(DAG.getIntPtrConstant(
1706 FuncInfo->getVarArgsFPOffset()));
1708 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
1709 unsigned VReg = MF.addLiveIn(XMMArgRegs[NumXMMRegs],
1710 X86::VR128RegisterClass);
1711 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
1712 SaveXMMOps.push_back(Val);
1714 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
1716 &SaveXMMOps[0], SaveXMMOps.size()));
1719 if (!MemOps.empty())
1720 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1721 &MemOps[0], MemOps.size());
1725 // Some CCs need callee pop.
1726 if (Subtarget->IsCalleePop(isVarArg, CallConv)) {
1727 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
1729 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
1730 // If this is an sret function, the return should pop the hidden pointer.
1731 if (!Is64Bit && !IsTailCallConvention(CallConv) && ArgsAreStructReturn(Ins))
1732 FuncInfo->setBytesToPopOnReturn(4);
1736 // RegSaveFrameIndex is X86-64 only.
1737 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
1738 if (CallConv == CallingConv::X86_FastCall ||
1739 CallConv == CallingConv::X86_ThisCall)
1740 // fastcc functions can't have varargs.
1741 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
1748 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
1749 SDValue StackPtr, SDValue Arg,
1750 DebugLoc dl, SelectionDAG &DAG,
1751 const CCValAssign &VA,
1752 ISD::ArgFlagsTy Flags) const {
1753 const unsigned FirstStackArgOffset = (Subtarget->isTargetWin64() ? 32 : 0);
1754 unsigned LocMemOffset = FirstStackArgOffset + VA.getLocMemOffset();
1755 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1756 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1757 if (Flags.isByVal()) {
1758 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
1760 return DAG.getStore(Chain, dl, Arg, PtrOff,
1761 PseudoSourceValue::getStack(), LocMemOffset,
1765 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
1766 /// optimization is performed and it is required.
1768 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
1769 SDValue &OutRetAddr, SDValue Chain,
1770 bool IsTailCall, bool Is64Bit,
1771 int FPDiff, DebugLoc dl) const {
1772 // Adjust the Return address stack slot.
1773 EVT VT = getPointerTy();
1774 OutRetAddr = getReturnAddressFrameIndex(DAG);
1776 // Load the "old" Return address.
1777 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, NULL, 0, false, false, 0);
1778 return SDValue(OutRetAddr.getNode(), 1);
1781 /// EmitTailCallStoreRetAddr - Emit a store of the return adress if tail call
1782 /// optimization is performed and it is required (FPDiff!=0).
1784 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
1785 SDValue Chain, SDValue RetAddrFrIdx,
1786 bool Is64Bit, int FPDiff, DebugLoc dl) {
1787 // Store the return address to the appropriate stack slot.
1788 if (!FPDiff) return Chain;
1789 // Calculate the new stack slot for the return address.
1790 int SlotSize = Is64Bit ? 8 : 4;
1791 int NewReturnAddrFI =
1792 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false);
1793 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
1794 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
1795 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
1796 PseudoSourceValue::getFixedStack(NewReturnAddrFI), 0,
1802 X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
1803 CallingConv::ID CallConv, bool isVarArg,
1805 const SmallVectorImpl<ISD::OutputArg> &Outs,
1806 const SmallVectorImpl<ISD::InputArg> &Ins,
1807 DebugLoc dl, SelectionDAG &DAG,
1808 SmallVectorImpl<SDValue> &InVals) const {
1809 MachineFunction &MF = DAG.getMachineFunction();
1810 bool Is64Bit = Subtarget->is64Bit();
1811 bool IsStructRet = CallIsStructReturn(Outs);
1812 bool IsSibcall = false;
1815 // Check if it's really possible to do a tail call.
1816 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
1817 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
1820 // Sibcalls are automatically detected tailcalls which do not require
1822 if (!GuaranteedTailCallOpt && isTailCall)
1829 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1830 "Var args not supported with calling convention fastcc or ghc");
1832 // Analyze operands of the call, assigning locations to each operand.
1833 SmallVector<CCValAssign, 16> ArgLocs;
1834 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1835 ArgLocs, *DAG.getContext());
1836 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CallConv));
1838 // Get a count of how many bytes are to be pushed on the stack.
1839 unsigned NumBytes = CCInfo.getNextStackOffset();
1841 // This is a sibcall. The memory operands are available in caller's
1842 // own caller's stack.
1844 else if (GuaranteedTailCallOpt && IsTailCallConvention(CallConv))
1845 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
1848 if (isTailCall && !IsSibcall) {
1849 // Lower arguments at fp - stackoffset + fpdiff.
1850 unsigned NumBytesCallerPushed =
1851 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
1852 FPDiff = NumBytesCallerPushed - NumBytes;
1854 // Set the delta of movement of the returnaddr stackslot.
1855 // But only set if delta is greater than previous delta.
1856 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
1857 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
1861 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
1863 SDValue RetAddrFrIdx;
1864 // Load return adress for tail calls.
1865 if (isTailCall && FPDiff)
1866 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
1867 Is64Bit, FPDiff, dl);
1869 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
1870 SmallVector<SDValue, 8> MemOpChains;
1873 // Walk the register/memloc assignments, inserting copies/loads. In the case
1874 // of tail call optimization arguments are handle later.
1875 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1876 CCValAssign &VA = ArgLocs[i];
1877 EVT RegVT = VA.getLocVT();
1878 SDValue Arg = Outs[i].Val;
1879 ISD::ArgFlagsTy Flags = Outs[i].Flags;
1880 bool isByVal = Flags.isByVal();
1882 // Promote the value if needed.
1883 switch (VA.getLocInfo()) {
1884 default: llvm_unreachable("Unknown loc info!");
1885 case CCValAssign::Full: break;
1886 case CCValAssign::SExt:
1887 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
1889 case CCValAssign::ZExt:
1890 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
1892 case CCValAssign::AExt:
1893 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) {
1894 // Special case: passing MMX values in XMM registers.
1895 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, Arg);
1896 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
1897 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
1899 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
1901 case CCValAssign::BCvt:
1902 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, RegVT, Arg);
1904 case CCValAssign::Indirect: {
1905 // Store the argument.
1906 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
1907 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
1908 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
1909 PseudoSourceValue::getFixedStack(FI), 0,
1916 if (VA.isRegLoc()) {
1917 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1918 } else if (!IsSibcall && (!isTailCall || isByVal)) {
1919 assert(VA.isMemLoc());
1920 if (StackPtr.getNode() == 0)
1921 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
1922 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
1923 dl, DAG, VA, Flags));
1927 if (!MemOpChains.empty())
1928 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1929 &MemOpChains[0], MemOpChains.size());
1931 // Build a sequence of copy-to-reg nodes chained together with token chain
1932 // and flag operands which copy the outgoing args into registers.
1934 // Tail call byval lowering might overwrite argument registers so in case of
1935 // tail call optimization the copies to registers are lowered later.
1937 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1938 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1939 RegsToPass[i].second, InFlag);
1940 InFlag = Chain.getValue(1);
1943 if (Subtarget->isPICStyleGOT()) {
1944 // ELF / PIC requires GOT in the EBX register before function calls via PLT
1947 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX,
1948 DAG.getNode(X86ISD::GlobalBaseReg,
1949 DebugLoc(), getPointerTy()),
1951 InFlag = Chain.getValue(1);
1953 // If we are tail calling and generating PIC/GOT style code load the
1954 // address of the callee into ECX. The value in ecx is used as target of
1955 // the tail jump. This is done to circumvent the ebx/callee-saved problem
1956 // for tail calls on PIC/GOT architectures. Normally we would just put the
1957 // address of GOT into ebx and then call target@PLT. But for tail calls
1958 // ebx would be restored (since ebx is callee saved) before jumping to the
1961 // Note: The actual moving to ECX is done further down.
1962 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
1963 if (G && !G->getGlobal()->hasHiddenVisibility() &&
1964 !G->getGlobal()->hasProtectedVisibility())
1965 Callee = LowerGlobalAddress(Callee, DAG);
1966 else if (isa<ExternalSymbolSDNode>(Callee))
1967 Callee = LowerExternalSymbol(Callee, DAG);
1971 if (Is64Bit && isVarArg) {
1972 // From AMD64 ABI document:
1973 // For calls that may call functions that use varargs or stdargs
1974 // (prototype-less calls or calls to functions containing ellipsis (...) in
1975 // the declaration) %al is used as hidden argument to specify the number
1976 // of SSE registers used. The contents of %al do not need to match exactly
1977 // the number of registers, but must be an ubound on the number of SSE
1978 // registers used and is in the range 0 - 8 inclusive.
1980 // FIXME: Verify this on Win64
1981 // Count the number of XMM registers allocated.
1982 static const unsigned XMMArgRegs[] = {
1983 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1984 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1986 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
1987 assert((Subtarget->hasSSE1() || !NumXMMRegs)
1988 && "SSE registers cannot be used when SSE is disabled");
1990 Chain = DAG.getCopyToReg(Chain, dl, X86::AL,
1991 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
1992 InFlag = Chain.getValue(1);
1996 // For tail calls lower the arguments to the 'real' stack slot.
1998 // Force all the incoming stack arguments to be loaded from the stack
1999 // before any new outgoing arguments are stored to the stack, because the
2000 // outgoing stack slots may alias the incoming argument stack slots, and
2001 // the alias isn't otherwise explicit. This is slightly more conservative
2002 // than necessary, because it means that each store effectively depends
2003 // on every argument instead of just those arguments it would clobber.
2004 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2006 SmallVector<SDValue, 8> MemOpChains2;
2009 // Do not flag preceeding copytoreg stuff together with the following stuff.
2011 if (GuaranteedTailCallOpt) {
2012 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2013 CCValAssign &VA = ArgLocs[i];
2016 assert(VA.isMemLoc());
2017 SDValue Arg = Outs[i].Val;
2018 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2019 // Create frame index.
2020 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2021 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2022 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2023 FIN = DAG.getFrameIndex(FI, getPointerTy());
2025 if (Flags.isByVal()) {
2026 // Copy relative to framepointer.
2027 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2028 if (StackPtr.getNode() == 0)
2029 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
2031 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2033 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2037 // Store relative to framepointer.
2038 MemOpChains2.push_back(
2039 DAG.getStore(ArgChain, dl, Arg, FIN,
2040 PseudoSourceValue::getFixedStack(FI), 0,
2046 if (!MemOpChains2.empty())
2047 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2048 &MemOpChains2[0], MemOpChains2.size());
2050 // Copy arguments to their registers.
2051 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2052 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2053 RegsToPass[i].second, InFlag);
2054 InFlag = Chain.getValue(1);
2058 // Store the return address to the appropriate stack slot.
2059 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
2063 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2064 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2065 // In the 64-bit large code model, we have to make all calls
2066 // through a register, since the call instruction's 32-bit
2067 // pc-relative offset may not be large enough to hold the whole
2069 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2070 // If the callee is a GlobalAddress node (quite common, every direct call
2071 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2074 // We should use extra load for direct calls to dllimported functions in
2076 const GlobalValue *GV = G->getGlobal();
2077 if (!GV->hasDLLImportLinkage()) {
2078 unsigned char OpFlags = 0;
2080 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2081 // external symbols most go through the PLT in PIC mode. If the symbol
2082 // has hidden or protected visibility, or if it is static or local, then
2083 // we don't need to use the PLT - we can directly call it.
2084 if (Subtarget->isTargetELF() &&
2085 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2086 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2087 OpFlags = X86II::MO_PLT;
2088 } else if (Subtarget->isPICStyleStubAny() &&
2089 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2090 Subtarget->getDarwinVers() < 9) {
2091 // PC-relative references to external symbols should go through $stub,
2092 // unless we're building with the leopard linker or later, which
2093 // automatically synthesizes these stubs.
2094 OpFlags = X86II::MO_DARWIN_STUB;
2097 Callee = DAG.getTargetGlobalAddress(GV, getPointerTy(),
2098 G->getOffset(), OpFlags);
2100 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2101 unsigned char OpFlags = 0;
2103 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to external
2104 // symbols should go through the PLT.
2105 if (Subtarget->isTargetELF() &&
2106 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2107 OpFlags = X86II::MO_PLT;
2108 } else if (Subtarget->isPICStyleStubAny() &&
2109 Subtarget->getDarwinVers() < 9) {
2110 // PC-relative references to external symbols should go through $stub,
2111 // unless we're building with the leopard linker or later, which
2112 // automatically synthesizes these stubs.
2113 OpFlags = X86II::MO_DARWIN_STUB;
2116 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2120 // Returns a chain & a flag for retval copy to use.
2121 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
2122 SmallVector<SDValue, 8> Ops;
2124 if (!IsSibcall && isTailCall) {
2125 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2126 DAG.getIntPtrConstant(0, true), InFlag);
2127 InFlag = Chain.getValue(1);
2130 Ops.push_back(Chain);
2131 Ops.push_back(Callee);
2134 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2136 // Add argument registers to the end of the list so that they are known live
2138 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2139 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2140 RegsToPass[i].second.getValueType()));
2142 // Add an implicit use GOT pointer in EBX.
2143 if (!isTailCall && Subtarget->isPICStyleGOT())
2144 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
2146 // Add an implicit use of AL for x86 vararg functions.
2147 if (Is64Bit && isVarArg)
2148 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
2150 if (InFlag.getNode())
2151 Ops.push_back(InFlag);
2155 //// If this is the first return lowered for this function, add the regs
2156 //// to the liveout set for the function.
2157 // This isn't right, although it's probably harmless on x86; liveouts
2158 // should be computed from returns not tail calls. Consider a void
2159 // function making a tail call to a function returning int.
2160 return DAG.getNode(X86ISD::TC_RETURN, dl,
2161 NodeTys, &Ops[0], Ops.size());
2164 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2165 InFlag = Chain.getValue(1);
2167 // Create the CALLSEQ_END node.
2168 unsigned NumBytesForCalleeToPush;
2169 if (Subtarget->IsCalleePop(isVarArg, CallConv))
2170 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2171 else if (!Is64Bit && !IsTailCallConvention(CallConv) && IsStructRet)
2172 // If this is a call to a struct-return function, the callee
2173 // pops the hidden struct pointer, so we have to push it back.
2174 // This is common for Darwin/X86, Linux & Mingw32 targets.
2175 NumBytesForCalleeToPush = 4;
2177 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2179 // Returns a flag for retval copy to use.
2181 Chain = DAG.getCALLSEQ_END(Chain,
2182 DAG.getIntPtrConstant(NumBytes, true),
2183 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2186 InFlag = Chain.getValue(1);
2189 // Handle result values, copying them out of physregs into vregs that we
2191 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2192 Ins, dl, DAG, InVals);
2196 //===----------------------------------------------------------------------===//
2197 // Fast Calling Convention (tail call) implementation
2198 //===----------------------------------------------------------------------===//
2200 // Like std call, callee cleans arguments, convention except that ECX is
2201 // reserved for storing the tail called function address. Only 2 registers are
2202 // free for argument passing (inreg). Tail call optimization is performed
2204 // * tailcallopt is enabled
2205 // * caller/callee are fastcc
2206 // On X86_64 architecture with GOT-style position independent code only local
2207 // (within module) calls are supported at the moment.
2208 // To keep the stack aligned according to platform abi the function
2209 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2210 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2211 // If a tail called function callee has more arguments than the caller the
2212 // caller needs to make sure that there is room to move the RETADDR to. This is
2213 // achieved by reserving an area the size of the argument delta right after the
2214 // original REtADDR, but before the saved framepointer or the spilled registers
2215 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2227 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2228 /// for a 16 byte align requirement.
2230 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2231 SelectionDAG& DAG) const {
2232 MachineFunction &MF = DAG.getMachineFunction();
2233 const TargetMachine &TM = MF.getTarget();
2234 const TargetFrameInfo &TFI = *TM.getFrameInfo();
2235 unsigned StackAlignment = TFI.getStackAlignment();
2236 uint64_t AlignMask = StackAlignment - 1;
2237 int64_t Offset = StackSize;
2238 uint64_t SlotSize = TD->getPointerSize();
2239 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2240 // Number smaller than 12 so just add the difference.
2241 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2243 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2244 Offset = ((~AlignMask) & Offset) + StackAlignment +
2245 (StackAlignment-SlotSize);
2250 /// MatchingStackOffset - Return true if the given stack call argument is
2251 /// already available in the same position (relatively) of the caller's
2252 /// incoming argument stack.
2254 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2255 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2256 const X86InstrInfo *TII) {
2257 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
2259 if (Arg.getOpcode() == ISD::CopyFromReg) {
2260 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2261 if (!VR || TargetRegisterInfo::isPhysicalRegister(VR))
2263 MachineInstr *Def = MRI->getVRegDef(VR);
2266 if (!Flags.isByVal()) {
2267 if (!TII->isLoadFromStackSlot(Def, FI))
2270 unsigned Opcode = Def->getOpcode();
2271 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
2272 Def->getOperand(1).isFI()) {
2273 FI = Def->getOperand(1).getIndex();
2274 Bytes = Flags.getByValSize();
2278 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2279 if (Flags.isByVal())
2280 // ByVal argument is passed in as a pointer but it's now being
2281 // dereferenced. e.g.
2282 // define @foo(%struct.X* %A) {
2283 // tail call @bar(%struct.X* byval %A)
2286 SDValue Ptr = Ld->getBasePtr();
2287 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2290 FI = FINode->getIndex();
2294 assert(FI != INT_MAX);
2295 if (!MFI->isFixedObjectIndex(FI))
2297 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
2300 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2301 /// for tail call optimization. Targets which want to do tail call
2302 /// optimization should implement this function.
2304 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2305 CallingConv::ID CalleeCC,
2307 bool isCalleeStructRet,
2308 bool isCallerStructRet,
2309 const SmallVectorImpl<ISD::OutputArg> &Outs,
2310 const SmallVectorImpl<ISD::InputArg> &Ins,
2311 SelectionDAG& DAG) const {
2312 if (!IsTailCallConvention(CalleeCC) &&
2313 CalleeCC != CallingConv::C)
2316 // If -tailcallopt is specified, make fastcc functions tail-callable.
2317 const MachineFunction &MF = DAG.getMachineFunction();
2318 const Function *CallerF = DAG.getMachineFunction().getFunction();
2319 CallingConv::ID CallerCC = CallerF->getCallingConv();
2320 bool CCMatch = CallerCC == CalleeCC;
2322 if (GuaranteedTailCallOpt) {
2323 if (IsTailCallConvention(CalleeCC) && CCMatch)
2328 // Look for obvious safe cases to perform tail call optimization that do not
2329 // require ABI changes. This is what gcc calls sibcall.
2331 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
2332 // emit a special epilogue.
2333 if (RegInfo->needsStackRealignment(MF))
2336 // Do not sibcall optimize vararg calls unless the call site is not passing any
2338 if (isVarArg && !Outs.empty())
2341 // Also avoid sibcall optimization if either caller or callee uses struct
2342 // return semantics.
2343 if (isCalleeStructRet || isCallerStructRet)
2346 // If the call result is in ST0 / ST1, it needs to be popped off the x87 stack.
2347 // Therefore if it's not used by the call it is not safe to optimize this into
2349 bool Unused = false;
2350 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
2357 SmallVector<CCValAssign, 16> RVLocs;
2358 CCState CCInfo(CalleeCC, false, getTargetMachine(),
2359 RVLocs, *DAG.getContext());
2360 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2361 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2362 CCValAssign &VA = RVLocs[i];
2363 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
2368 // If the calling conventions do not match, then we'd better make sure the
2369 // results are returned in the same way as what the caller expects.
2371 SmallVector<CCValAssign, 16> RVLocs1;
2372 CCState CCInfo1(CalleeCC, false, getTargetMachine(),
2373 RVLocs1, *DAG.getContext());
2374 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
2376 SmallVector<CCValAssign, 16> RVLocs2;
2377 CCState CCInfo2(CallerCC, false, getTargetMachine(),
2378 RVLocs2, *DAG.getContext());
2379 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
2381 if (RVLocs1.size() != RVLocs2.size())
2383 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2384 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2386 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2388 if (RVLocs1[i].isRegLoc()) {
2389 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2392 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2398 // If the callee takes no arguments then go on to check the results of the
2400 if (!Outs.empty()) {
2401 // Check if stack adjustment is needed. For now, do not do this if any
2402 // argument is passed on the stack.
2403 SmallVector<CCValAssign, 16> ArgLocs;
2404 CCState CCInfo(CalleeCC, isVarArg, getTargetMachine(),
2405 ArgLocs, *DAG.getContext());
2406 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CalleeCC));
2407 if (CCInfo.getNextStackOffset()) {
2408 MachineFunction &MF = DAG.getMachineFunction();
2409 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
2411 if (Subtarget->isTargetWin64())
2412 // Win64 ABI has additional complications.
2415 // Check if the arguments are already laid out in the right way as
2416 // the caller's fixed stack objects.
2417 MachineFrameInfo *MFI = MF.getFrameInfo();
2418 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2419 const X86InstrInfo *TII =
2420 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
2421 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2422 CCValAssign &VA = ArgLocs[i];
2423 SDValue Arg = Outs[i].Val;
2424 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2425 if (VA.getLocInfo() == CCValAssign::Indirect)
2427 if (!VA.isRegLoc()) {
2428 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2435 // If the tailcall address may be in a register, then make sure it's
2436 // possible to register allocate for it. In 32-bit, the call address can
2437 // only target EAX, EDX, or ECX since the tail call must be scheduled after
2438 // callee-saved registers are restored. In 64-bit, it's RAX, RCX, RDX, RSI,
2439 // RDI, R8, R9, R11.
2440 if (!isa<GlobalAddressSDNode>(Callee) &&
2441 !isa<ExternalSymbolSDNode>(Callee)) {
2442 unsigned Limit = Subtarget->is64Bit() ? 8 : 3;
2443 unsigned NumInRegs = 0;
2444 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2445 CCValAssign &VA = ArgLocs[i];
2446 if (VA.isRegLoc()) {
2447 if (++NumInRegs == Limit)
2458 X86TargetLowering::createFastISel(MachineFunction &mf,
2459 DenseMap<const Value *, unsigned> &vm,
2460 DenseMap<const BasicBlock*, MachineBasicBlock*> &bm,
2461 DenseMap<const AllocaInst *, int> &am,
2462 std::vector<std::pair<MachineInstr*, unsigned> > &pn
2464 , SmallSet<const Instruction *, 8> &cil
2467 return X86::createFastISel(mf, vm, bm, am, pn
2475 //===----------------------------------------------------------------------===//
2476 // Other Lowering Hooks
2477 //===----------------------------------------------------------------------===//
2480 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
2481 MachineFunction &MF = DAG.getMachineFunction();
2482 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2483 int ReturnAddrIndex = FuncInfo->getRAIndex();
2485 if (ReturnAddrIndex == 0) {
2486 // Set up a frame object for the return address.
2487 uint64_t SlotSize = TD->getPointerSize();
2488 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
2490 FuncInfo->setRAIndex(ReturnAddrIndex);
2493 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
2497 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
2498 bool hasSymbolicDisplacement) {
2499 // Offset should fit into 32 bit immediate field.
2500 if (!isInt<32>(Offset))
2503 // If we don't have a symbolic displacement - we don't have any extra
2505 if (!hasSymbolicDisplacement)
2508 // FIXME: Some tweaks might be needed for medium code model.
2509 if (M != CodeModel::Small && M != CodeModel::Kernel)
2512 // For small code model we assume that latest object is 16MB before end of 31
2513 // bits boundary. We may also accept pretty large negative constants knowing
2514 // that all objects are in the positive half of address space.
2515 if (M == CodeModel::Small && Offset < 16*1024*1024)
2518 // For kernel code model we know that all object resist in the negative half
2519 // of 32bits address space. We may not accept negative offsets, since they may
2520 // be just off and we may accept pretty large positive ones.
2521 if (M == CodeModel::Kernel && Offset > 0)
2527 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
2528 /// specific condition code, returning the condition code and the LHS/RHS of the
2529 /// comparison to make.
2530 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
2531 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
2533 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
2534 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
2535 // X > -1 -> X == 0, jump !sign.
2536 RHS = DAG.getConstant(0, RHS.getValueType());
2537 return X86::COND_NS;
2538 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
2539 // X < 0 -> X == 0, jump on sign.
2541 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
2543 RHS = DAG.getConstant(0, RHS.getValueType());
2544 return X86::COND_LE;
2548 switch (SetCCOpcode) {
2549 default: llvm_unreachable("Invalid integer condition!");
2550 case ISD::SETEQ: return X86::COND_E;
2551 case ISD::SETGT: return X86::COND_G;
2552 case ISD::SETGE: return X86::COND_GE;
2553 case ISD::SETLT: return X86::COND_L;
2554 case ISD::SETLE: return X86::COND_LE;
2555 case ISD::SETNE: return X86::COND_NE;
2556 case ISD::SETULT: return X86::COND_B;
2557 case ISD::SETUGT: return X86::COND_A;
2558 case ISD::SETULE: return X86::COND_BE;
2559 case ISD::SETUGE: return X86::COND_AE;
2563 // First determine if it is required or is profitable to flip the operands.
2565 // If LHS is a foldable load, but RHS is not, flip the condition.
2566 if ((ISD::isNON_EXTLoad(LHS.getNode()) && LHS.hasOneUse()) &&
2567 !(ISD::isNON_EXTLoad(RHS.getNode()) && RHS.hasOneUse())) {
2568 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
2569 std::swap(LHS, RHS);
2572 switch (SetCCOpcode) {
2578 std::swap(LHS, RHS);
2582 // On a floating point condition, the flags are set as follows:
2584 // 0 | 0 | 0 | X > Y
2585 // 0 | 0 | 1 | X < Y
2586 // 1 | 0 | 0 | X == Y
2587 // 1 | 1 | 1 | unordered
2588 switch (SetCCOpcode) {
2589 default: llvm_unreachable("Condcode should be pre-legalized away");
2591 case ISD::SETEQ: return X86::COND_E;
2592 case ISD::SETOLT: // flipped
2594 case ISD::SETGT: return X86::COND_A;
2595 case ISD::SETOLE: // flipped
2597 case ISD::SETGE: return X86::COND_AE;
2598 case ISD::SETUGT: // flipped
2600 case ISD::SETLT: return X86::COND_B;
2601 case ISD::SETUGE: // flipped
2603 case ISD::SETLE: return X86::COND_BE;
2605 case ISD::SETNE: return X86::COND_NE;
2606 case ISD::SETUO: return X86::COND_P;
2607 case ISD::SETO: return X86::COND_NP;
2609 case ISD::SETUNE: return X86::COND_INVALID;
2613 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
2614 /// code. Current x86 isa includes the following FP cmov instructions:
2615 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
2616 static bool hasFPCMov(unsigned X86CC) {
2632 /// isFPImmLegal - Returns true if the target can instruction select the
2633 /// specified FP immediate natively. If false, the legalizer will
2634 /// materialize the FP immediate as a load from a constant pool.
2635 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
2636 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
2637 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
2643 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
2644 /// the specified range (L, H].
2645 static bool isUndefOrInRange(int Val, int Low, int Hi) {
2646 return (Val < 0) || (Val >= Low && Val < Hi);
2649 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
2650 /// specified value.
2651 static bool isUndefOrEqual(int Val, int CmpVal) {
2652 if (Val < 0 || Val == CmpVal)
2657 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
2658 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
2659 /// the second operand.
2660 static bool isPSHUFDMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2661 if (VT == MVT::v4f32 || VT == MVT::v4i32 || VT == MVT::v4i16)
2662 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
2663 if (VT == MVT::v2f64 || VT == MVT::v2i64)
2664 return (Mask[0] < 2 && Mask[1] < 2);
2668 bool X86::isPSHUFDMask(ShuffleVectorSDNode *N) {
2669 SmallVector<int, 8> M;
2671 return ::isPSHUFDMask(M, N->getValueType(0));
2674 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
2675 /// is suitable for input to PSHUFHW.
2676 static bool isPSHUFHWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2677 if (VT != MVT::v8i16)
2680 // Lower quadword copied in order or undef.
2681 for (int i = 0; i != 4; ++i)
2682 if (Mask[i] >= 0 && Mask[i] != i)
2685 // Upper quadword shuffled.
2686 for (int i = 4; i != 8; ++i)
2687 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7))
2693 bool X86::isPSHUFHWMask(ShuffleVectorSDNode *N) {
2694 SmallVector<int, 8> M;
2696 return ::isPSHUFHWMask(M, N->getValueType(0));
2699 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
2700 /// is suitable for input to PSHUFLW.
2701 static bool isPSHUFLWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2702 if (VT != MVT::v8i16)
2705 // Upper quadword copied in order.
2706 for (int i = 4; i != 8; ++i)
2707 if (Mask[i] >= 0 && Mask[i] != i)
2710 // Lower quadword shuffled.
2711 for (int i = 0; i != 4; ++i)
2718 bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) {
2719 SmallVector<int, 8> M;
2721 return ::isPSHUFLWMask(M, N->getValueType(0));
2724 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
2725 /// is suitable for input to PALIGNR.
2726 static bool isPALIGNRMask(const SmallVectorImpl<int> &Mask, EVT VT,
2728 int i, e = VT.getVectorNumElements();
2730 // Do not handle v2i64 / v2f64 shuffles with palignr.
2731 if (e < 4 || !hasSSSE3)
2734 for (i = 0; i != e; ++i)
2738 // All undef, not a palignr.
2742 // Determine if it's ok to perform a palignr with only the LHS, since we
2743 // don't have access to the actual shuffle elements to see if RHS is undef.
2744 bool Unary = Mask[i] < (int)e;
2745 bool NeedsUnary = false;
2747 int s = Mask[i] - i;
2749 // Check the rest of the elements to see if they are consecutive.
2750 for (++i; i != e; ++i) {
2755 Unary = Unary && (m < (int)e);
2756 NeedsUnary = NeedsUnary || (m < s);
2758 if (NeedsUnary && !Unary)
2760 if (Unary && m != ((s+i) & (e-1)))
2762 if (!Unary && m != (s+i))
2768 bool X86::isPALIGNRMask(ShuffleVectorSDNode *N) {
2769 SmallVector<int, 8> M;
2771 return ::isPALIGNRMask(M, N->getValueType(0), true);
2774 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
2775 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
2776 static bool isSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2777 int NumElems = VT.getVectorNumElements();
2778 if (NumElems != 2 && NumElems != 4)
2781 int Half = NumElems / 2;
2782 for (int i = 0; i < Half; ++i)
2783 if (!isUndefOrInRange(Mask[i], 0, NumElems))
2785 for (int i = Half; i < NumElems; ++i)
2786 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
2792 bool X86::isSHUFPMask(ShuffleVectorSDNode *N) {
2793 SmallVector<int, 8> M;
2795 return ::isSHUFPMask(M, N->getValueType(0));
2798 /// isCommutedSHUFP - Returns true if the shuffle mask is exactly
2799 /// the reverse of what x86 shuffles want. x86 shuffles requires the lower
2800 /// half elements to come from vector 1 (which would equal the dest.) and
2801 /// the upper half to come from vector 2.
2802 static bool isCommutedSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2803 int NumElems = VT.getVectorNumElements();
2805 if (NumElems != 2 && NumElems != 4)
2808 int Half = NumElems / 2;
2809 for (int i = 0; i < Half; ++i)
2810 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
2812 for (int i = Half; i < NumElems; ++i)
2813 if (!isUndefOrInRange(Mask[i], 0, NumElems))
2818 static bool isCommutedSHUFP(ShuffleVectorSDNode *N) {
2819 SmallVector<int, 8> M;
2821 return isCommutedSHUFPMask(M, N->getValueType(0));
2824 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
2825 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
2826 bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) {
2827 if (N->getValueType(0).getVectorNumElements() != 4)
2830 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
2831 return isUndefOrEqual(N->getMaskElt(0), 6) &&
2832 isUndefOrEqual(N->getMaskElt(1), 7) &&
2833 isUndefOrEqual(N->getMaskElt(2), 2) &&
2834 isUndefOrEqual(N->getMaskElt(3), 3);
2837 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
2838 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
2840 bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) {
2841 unsigned NumElems = N->getValueType(0).getVectorNumElements();
2846 return isUndefOrEqual(N->getMaskElt(0), 2) &&
2847 isUndefOrEqual(N->getMaskElt(1), 3) &&
2848 isUndefOrEqual(N->getMaskElt(2), 2) &&
2849 isUndefOrEqual(N->getMaskElt(3), 3);
2852 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
2853 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
2854 bool X86::isMOVLPMask(ShuffleVectorSDNode *N) {
2855 unsigned NumElems = N->getValueType(0).getVectorNumElements();
2857 if (NumElems != 2 && NumElems != 4)
2860 for (unsigned i = 0; i < NumElems/2; ++i)
2861 if (!isUndefOrEqual(N->getMaskElt(i), i + NumElems))
2864 for (unsigned i = NumElems/2; i < NumElems; ++i)
2865 if (!isUndefOrEqual(N->getMaskElt(i), i))
2871 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
2872 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
2873 bool X86::isMOVLHPSMask(ShuffleVectorSDNode *N) {
2874 unsigned NumElems = N->getValueType(0).getVectorNumElements();
2876 if (NumElems != 2 && NumElems != 4)
2879 for (unsigned i = 0; i < NumElems/2; ++i)
2880 if (!isUndefOrEqual(N->getMaskElt(i), i))
2883 for (unsigned i = 0; i < NumElems/2; ++i)
2884 if (!isUndefOrEqual(N->getMaskElt(i + NumElems/2), i + NumElems))
2890 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
2891 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
2892 static bool isUNPCKLMask(const SmallVectorImpl<int> &Mask, EVT VT,
2893 bool V2IsSplat = false) {
2894 int NumElts = VT.getVectorNumElements();
2895 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2898 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) {
2900 int BitI1 = Mask[i+1];
2901 if (!isUndefOrEqual(BitI, j))
2904 if (!isUndefOrEqual(BitI1, NumElts))
2907 if (!isUndefOrEqual(BitI1, j + NumElts))
2914 bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
2915 SmallVector<int, 8> M;
2917 return ::isUNPCKLMask(M, N->getValueType(0), V2IsSplat);
2920 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
2921 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
2922 static bool isUNPCKHMask(const SmallVectorImpl<int> &Mask, EVT VT,
2923 bool V2IsSplat = false) {
2924 int NumElts = VT.getVectorNumElements();
2925 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2928 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) {
2930 int BitI1 = Mask[i+1];
2931 if (!isUndefOrEqual(BitI, j + NumElts/2))
2934 if (isUndefOrEqual(BitI1, NumElts))
2937 if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts))
2944 bool X86::isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
2945 SmallVector<int, 8> M;
2947 return ::isUNPCKHMask(M, N->getValueType(0), V2IsSplat);
2950 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
2951 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
2953 static bool isUNPCKL_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
2954 int NumElems = VT.getVectorNumElements();
2955 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2958 for (int i = 0, j = 0; i != NumElems; i += 2, ++j) {
2960 int BitI1 = Mask[i+1];
2961 if (!isUndefOrEqual(BitI, j))
2963 if (!isUndefOrEqual(BitI1, j))
2969 bool X86::isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N) {
2970 SmallVector<int, 8> M;
2972 return ::isUNPCKL_v_undef_Mask(M, N->getValueType(0));
2975 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
2976 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
2978 static bool isUNPCKH_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
2979 int NumElems = VT.getVectorNumElements();
2980 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2983 for (int i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) {
2985 int BitI1 = Mask[i+1];
2986 if (!isUndefOrEqual(BitI, j))
2988 if (!isUndefOrEqual(BitI1, j))
2994 bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N) {
2995 SmallVector<int, 8> M;
2997 return ::isUNPCKH_v_undef_Mask(M, N->getValueType(0));
3000 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
3001 /// specifies a shuffle of elements that is suitable for input to MOVSS,
3002 /// MOVSD, and MOVD, i.e. setting the lowest element.
3003 static bool isMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3004 if (VT.getVectorElementType().getSizeInBits() < 32)
3007 int NumElts = VT.getVectorNumElements();
3009 if (!isUndefOrEqual(Mask[0], NumElts))
3012 for (int i = 1; i < NumElts; ++i)
3013 if (!isUndefOrEqual(Mask[i], i))
3019 bool X86::isMOVLMask(ShuffleVectorSDNode *N) {
3020 SmallVector<int, 8> M;
3022 return ::isMOVLMask(M, N->getValueType(0));
3025 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
3026 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
3027 /// element of vector 2 and the other elements to come from vector 1 in order.
3028 static bool isCommutedMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT,
3029 bool V2IsSplat = false, bool V2IsUndef = false) {
3030 int NumOps = VT.getVectorNumElements();
3031 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
3034 if (!isUndefOrEqual(Mask[0], 0))
3037 for (int i = 1; i < NumOps; ++i)
3038 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
3039 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
3040 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
3046 static bool isCommutedMOVL(ShuffleVectorSDNode *N, bool V2IsSplat = false,
3047 bool V2IsUndef = false) {
3048 SmallVector<int, 8> M;
3050 return isCommutedMOVLMask(M, N->getValueType(0), V2IsSplat, V2IsUndef);
3053 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3054 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
3055 bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N) {
3056 if (N->getValueType(0).getVectorNumElements() != 4)
3059 // Expect 1, 1, 3, 3
3060 for (unsigned i = 0; i < 2; ++i) {
3061 int Elt = N->getMaskElt(i);
3062 if (Elt >= 0 && Elt != 1)
3067 for (unsigned i = 2; i < 4; ++i) {
3068 int Elt = N->getMaskElt(i);
3069 if (Elt >= 0 && Elt != 3)
3074 // Don't use movshdup if it can be done with a shufps.
3075 // FIXME: verify that matching u, u, 3, 3 is what we want.
3079 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3080 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
3081 bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N) {
3082 if (N->getValueType(0).getVectorNumElements() != 4)
3085 // Expect 0, 0, 2, 2
3086 for (unsigned i = 0; i < 2; ++i)
3087 if (N->getMaskElt(i) > 0)
3091 for (unsigned i = 2; i < 4; ++i) {
3092 int Elt = N->getMaskElt(i);
3093 if (Elt >= 0 && Elt != 2)
3098 // Don't use movsldup if it can be done with a shufps.
3102 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3103 /// specifies a shuffle of elements that is suitable for input to MOVDDUP.
3104 bool X86::isMOVDDUPMask(ShuffleVectorSDNode *N) {
3105 int e = N->getValueType(0).getVectorNumElements() / 2;
3107 for (int i = 0; i < e; ++i)
3108 if (!isUndefOrEqual(N->getMaskElt(i), i))
3110 for (int i = 0; i < e; ++i)
3111 if (!isUndefOrEqual(N->getMaskElt(e+i), i))
3116 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
3117 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
3118 unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
3119 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3120 int NumOperands = SVOp->getValueType(0).getVectorNumElements();
3122 unsigned Shift = (NumOperands == 4) ? 2 : 1;
3124 for (int i = 0; i < NumOperands; ++i) {
3125 int Val = SVOp->getMaskElt(NumOperands-i-1);
3126 if (Val < 0) Val = 0;
3127 if (Val >= NumOperands) Val -= NumOperands;
3129 if (i != NumOperands - 1)
3135 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
3136 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
3137 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
3138 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3140 // 8 nodes, but we only care about the last 4.
3141 for (unsigned i = 7; i >= 4; --i) {
3142 int Val = SVOp->getMaskElt(i);
3151 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
3152 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
3153 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
3154 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3156 // 8 nodes, but we only care about the first 4.
3157 for (int i = 3; i >= 0; --i) {
3158 int Val = SVOp->getMaskElt(i);
3167 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
3168 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
3169 unsigned X86::getShufflePALIGNRImmediate(SDNode *N) {
3170 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3171 EVT VVT = N->getValueType(0);
3172 unsigned EltSize = VVT.getVectorElementType().getSizeInBits() >> 3;
3176 for (i = 0, e = VVT.getVectorNumElements(); i != e; ++i) {
3177 Val = SVOp->getMaskElt(i);
3181 return (Val - i) * EltSize;
3184 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
3186 bool X86::isZeroNode(SDValue Elt) {
3187 return ((isa<ConstantSDNode>(Elt) &&
3188 cast<ConstantSDNode>(Elt)->isNullValue()) ||
3189 (isa<ConstantFPSDNode>(Elt) &&
3190 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
3193 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
3194 /// their permute mask.
3195 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
3196 SelectionDAG &DAG) {
3197 EVT VT = SVOp->getValueType(0);
3198 unsigned NumElems = VT.getVectorNumElements();
3199 SmallVector<int, 8> MaskVec;
3201 for (unsigned i = 0; i != NumElems; ++i) {
3202 int idx = SVOp->getMaskElt(i);
3204 MaskVec.push_back(idx);
3205 else if (idx < (int)NumElems)
3206 MaskVec.push_back(idx + NumElems);
3208 MaskVec.push_back(idx - NumElems);
3210 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
3211 SVOp->getOperand(0), &MaskVec[0]);
3214 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3215 /// the two vector operands have swapped position.
3216 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, EVT VT) {
3217 unsigned NumElems = VT.getVectorNumElements();
3218 for (unsigned i = 0; i != NumElems; ++i) {
3222 else if (idx < (int)NumElems)
3223 Mask[i] = idx + NumElems;
3225 Mask[i] = idx - NumElems;
3229 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
3230 /// match movhlps. The lower half elements should come from upper half of
3231 /// V1 (and in order), and the upper half elements should come from the upper
3232 /// half of V2 (and in order).
3233 static bool ShouldXformToMOVHLPS(ShuffleVectorSDNode *Op) {
3234 if (Op->getValueType(0).getVectorNumElements() != 4)
3236 for (unsigned i = 0, e = 2; i != e; ++i)
3237 if (!isUndefOrEqual(Op->getMaskElt(i), i+2))
3239 for (unsigned i = 2; i != 4; ++i)
3240 if (!isUndefOrEqual(Op->getMaskElt(i), i+4))
3245 /// isScalarLoadToVector - Returns true if the node is a scalar load that
3246 /// is promoted to a vector. It also returns the LoadSDNode by reference if
3248 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
3249 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
3251 N = N->getOperand(0).getNode();
3252 if (!ISD::isNON_EXTLoad(N))
3255 *LD = cast<LoadSDNode>(N);
3259 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
3260 /// match movlp{s|d}. The lower half elements should come from lower half of
3261 /// V1 (and in order), and the upper half elements should come from the upper
3262 /// half of V2 (and in order). And since V1 will become the source of the
3263 /// MOVLP, it must be either a vector load or a scalar load to vector.
3264 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
3265 ShuffleVectorSDNode *Op) {
3266 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
3268 // Is V2 is a vector load, don't do this transformation. We will try to use
3269 // load folding shufps op.
3270 if (ISD::isNON_EXTLoad(V2))
3273 unsigned NumElems = Op->getValueType(0).getVectorNumElements();
3275 if (NumElems != 2 && NumElems != 4)
3277 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3278 if (!isUndefOrEqual(Op->getMaskElt(i), i))
3280 for (unsigned i = NumElems/2; i != NumElems; ++i)
3281 if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems))
3286 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
3288 static bool isSplatVector(SDNode *N) {
3289 if (N->getOpcode() != ISD::BUILD_VECTOR)
3292 SDValue SplatValue = N->getOperand(0);
3293 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
3294 if (N->getOperand(i) != SplatValue)
3299 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
3300 /// to an zero vector.
3301 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
3302 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
3303 SDValue V1 = N->getOperand(0);
3304 SDValue V2 = N->getOperand(1);
3305 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3306 for (unsigned i = 0; i != NumElems; ++i) {
3307 int Idx = N->getMaskElt(i);
3308 if (Idx >= (int)NumElems) {
3309 unsigned Opc = V2.getOpcode();
3310 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
3312 if (Opc != ISD::BUILD_VECTOR ||
3313 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
3315 } else if (Idx >= 0) {
3316 unsigned Opc = V1.getOpcode();
3317 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
3319 if (Opc != ISD::BUILD_VECTOR ||
3320 !X86::isZeroNode(V1.getOperand(Idx)))
3327 /// getZeroVector - Returns a vector of specified type with all zero elements.
3329 static SDValue getZeroVector(EVT VT, bool HasSSE2, SelectionDAG &DAG,
3331 assert(VT.isVector() && "Expected a vector type");
3333 // Always build zero vectors as <4 x i32> or <2 x i32> bitcasted to their dest
3334 // type. This ensures they get CSE'd.
3336 if (VT.getSizeInBits() == 64) { // MMX
3337 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
3338 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
3339 } else if (HasSSE2) { // SSE2
3340 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
3341 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
3343 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
3344 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
3346 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
3349 /// getOnesVector - Returns a vector of specified type with all bits set.
3351 static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
3352 assert(VT.isVector() && "Expected a vector type");
3354 // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest
3355 // type. This ensures they get CSE'd.
3356 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
3358 if (VT.getSizeInBits() == 64) // MMX
3359 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
3361 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
3362 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
3366 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
3367 /// that point to V2 points to its first element.
3368 static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
3369 EVT VT = SVOp->getValueType(0);
3370 unsigned NumElems = VT.getVectorNumElements();
3372 bool Changed = false;
3373 SmallVector<int, 8> MaskVec;
3374 SVOp->getMask(MaskVec);
3376 for (unsigned i = 0; i != NumElems; ++i) {
3377 if (MaskVec[i] > (int)NumElems) {
3378 MaskVec[i] = NumElems;
3383 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(0),
3384 SVOp->getOperand(1), &MaskVec[0]);
3385 return SDValue(SVOp, 0);
3388 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
3389 /// operation of specified width.
3390 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3392 unsigned NumElems = VT.getVectorNumElements();
3393 SmallVector<int, 8> Mask;
3394 Mask.push_back(NumElems);
3395 for (unsigned i = 1; i != NumElems; ++i)
3397 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3400 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
3401 static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3403 unsigned NumElems = VT.getVectorNumElements();
3404 SmallVector<int, 8> Mask;
3405 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
3407 Mask.push_back(i + NumElems);
3409 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3412 /// getUnpackhMask - Returns a vector_shuffle node for an unpackh operation.
3413 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3415 unsigned NumElems = VT.getVectorNumElements();
3416 unsigned Half = NumElems/2;
3417 SmallVector<int, 8> Mask;
3418 for (unsigned i = 0; i != Half; ++i) {
3419 Mask.push_back(i + Half);
3420 Mask.push_back(i + NumElems + Half);
3422 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3425 /// PromoteSplat - Promote a splat of v4f32, v8i16 or v16i8 to v4i32.
3426 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG,
3428 if (SV->getValueType(0).getVectorNumElements() <= 4)
3429 return SDValue(SV, 0);
3431 EVT PVT = MVT::v4f32;
3432 EVT VT = SV->getValueType(0);
3433 DebugLoc dl = SV->getDebugLoc();
3434 SDValue V1 = SV->getOperand(0);
3435 int NumElems = VT.getVectorNumElements();
3436 int EltNo = SV->getSplatIndex();
3438 // unpack elements to the correct location
3439 while (NumElems > 4) {
3440 if (EltNo < NumElems/2) {
3441 V1 = getUnpackl(DAG, dl, VT, V1, V1);
3443 V1 = getUnpackh(DAG, dl, VT, V1, V1);
3444 EltNo -= NumElems/2;
3449 // Perform the splat.
3450 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
3451 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, PVT, V1);
3452 V1 = DAG.getVectorShuffle(PVT, dl, V1, DAG.getUNDEF(PVT), &SplatMask[0]);
3453 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, V1);
3456 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
3457 /// vector of zero or undef vector. This produces a shuffle where the low
3458 /// element of V2 is swizzled into the zero/undef vector, landing at element
3459 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
3460 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
3461 bool isZero, bool HasSSE2,
3462 SelectionDAG &DAG) {
3463 EVT VT = V2.getValueType();
3465 ? getZeroVector(VT, HasSSE2, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT);
3466 unsigned NumElems = VT.getVectorNumElements();
3467 SmallVector<int, 16> MaskVec;
3468 for (unsigned i = 0; i != NumElems; ++i)
3469 // If this is the insertion idx, put the low elt of V2 here.
3470 MaskVec.push_back(i == Idx ? NumElems : i);
3471 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
3474 /// getNumOfConsecutiveZeros - Return the number of elements in a result of
3475 /// a shuffle that is zero.
3477 unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp, int NumElems,
3478 bool Low, SelectionDAG &DAG) {
3479 unsigned NumZeros = 0;
3480 for (int i = 0; i < NumElems; ++i) {
3481 unsigned Index = Low ? i : NumElems-i-1;
3482 int Idx = SVOp->getMaskElt(Index);
3487 SDValue Elt = DAG.getShuffleScalarElt(SVOp, Index);
3488 if (Elt.getNode() && X86::isZeroNode(Elt))
3496 /// isVectorShift - Returns true if the shuffle can be implemented as a
3497 /// logical left or right shift of a vector.
3498 /// FIXME: split into pslldqi, psrldqi, palignr variants.
3499 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
3500 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
3501 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
3504 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, true, DAG);
3507 NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, false, DAG);
3511 bool SeenV1 = false;
3512 bool SeenV2 = false;
3513 for (unsigned i = NumZeros; i < NumElems; ++i) {
3514 unsigned Val = isLeft ? (i - NumZeros) : i;
3515 int Idx_ = SVOp->getMaskElt(isLeft ? i : (i - NumZeros));
3518 unsigned Idx = (unsigned) Idx_;
3528 if (SeenV1 && SeenV2)
3531 ShVal = SeenV1 ? SVOp->getOperand(0) : SVOp->getOperand(1);
3537 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
3539 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
3540 unsigned NumNonZero, unsigned NumZero,
3542 const TargetLowering &TLI) {
3546 DebugLoc dl = Op.getDebugLoc();
3549 for (unsigned i = 0; i < 16; ++i) {
3550 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
3551 if (ThisIsNonZero && First) {
3553 V = getZeroVector(MVT::v8i16, true, DAG, dl);
3555 V = DAG.getUNDEF(MVT::v8i16);
3560 SDValue ThisElt(0, 0), LastElt(0, 0);
3561 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
3562 if (LastIsNonZero) {
3563 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
3564 MVT::i16, Op.getOperand(i-1));
3566 if (ThisIsNonZero) {
3567 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
3568 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
3569 ThisElt, DAG.getConstant(8, MVT::i8));
3571 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
3575 if (ThisElt.getNode())
3576 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
3577 DAG.getIntPtrConstant(i/2));
3581 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V);
3584 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
3586 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
3587 unsigned NumNonZero, unsigned NumZero,
3589 const TargetLowering &TLI) {
3593 DebugLoc dl = Op.getDebugLoc();
3596 for (unsigned i = 0; i < 8; ++i) {
3597 bool isNonZero = (NonZeros & (1 << i)) != 0;
3601 V = getZeroVector(MVT::v8i16, true, DAG, dl);
3603 V = DAG.getUNDEF(MVT::v8i16);
3606 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
3607 MVT::v8i16, V, Op.getOperand(i),
3608 DAG.getIntPtrConstant(i));
3615 /// getVShift - Return a vector logical shift node.
3617 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
3618 unsigned NumBits, SelectionDAG &DAG,
3619 const TargetLowering &TLI, DebugLoc dl) {
3620 bool isMMX = VT.getSizeInBits() == 64;
3621 EVT ShVT = isMMX ? MVT::v1i64 : MVT::v2i64;
3622 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL;
3623 SrcOp = DAG.getNode(ISD::BIT_CONVERT, dl, ShVT, SrcOp);
3624 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
3625 DAG.getNode(Opc, dl, ShVT, SrcOp,
3626 DAG.getConstant(NumBits, TLI.getShiftAmountTy())));
3630 X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
3631 SelectionDAG &DAG) const {
3633 // Check if the scalar load can be widened into a vector load. And if
3634 // the address is "base + cst" see if the cst can be "absorbed" into
3635 // the shuffle mask.
3636 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
3637 SDValue Ptr = LD->getBasePtr();
3638 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
3640 EVT PVT = LD->getValueType(0);
3641 if (PVT != MVT::i32 && PVT != MVT::f32)
3646 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
3647 FI = FINode->getIndex();
3649 } else if (Ptr.getOpcode() == ISD::ADD &&
3650 isa<ConstantSDNode>(Ptr.getOperand(1)) &&
3651 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
3652 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
3653 Offset = Ptr.getConstantOperandVal(1);
3654 Ptr = Ptr.getOperand(0);
3659 SDValue Chain = LD->getChain();
3660 // Make sure the stack object alignment is at least 16.
3661 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
3662 if (DAG.InferPtrAlignment(Ptr) < 16) {
3663 if (MFI->isFixedObjectIndex(FI)) {
3664 // Can't change the alignment. FIXME: It's possible to compute
3665 // the exact stack offset and reference FI + adjust offset instead.
3666 // If someone *really* cares about this. That's the way to implement it.
3669 MFI->setObjectAlignment(FI, 16);
3673 // (Offset % 16) must be multiple of 4. Then address is then
3674 // Ptr + (Offset & ~15).
3677 if ((Offset % 16) & 3)
3679 int64_t StartOffset = Offset & ~15;
3681 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(),
3682 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
3684 int EltNo = (Offset - StartOffset) >> 2;
3685 int Mask[4] = { EltNo, EltNo, EltNo, EltNo };
3686 EVT VT = (PVT == MVT::i32) ? MVT::v4i32 : MVT::v4f32;
3687 SDValue V1 = DAG.getLoad(VT, dl, Chain, Ptr,LD->getSrcValue(),0,
3689 // Canonicalize it to a v4i32 shuffle.
3690 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32, V1);
3691 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
3692 DAG.getVectorShuffle(MVT::v4i32, dl, V1,
3693 DAG.getUNDEF(MVT::v4i32), &Mask[0]));
3699 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
3700 /// vector of type 'VT', see if the elements can be replaced by a single large
3701 /// load which has the same value as a build_vector whose operands are 'elts'.
3703 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
3705 /// FIXME: we'd also like to handle the case where the last elements are zero
3706 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
3707 /// There's even a handy isZeroNode for that purpose.
3708 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
3709 DebugLoc &dl, SelectionDAG &DAG) {
3710 EVT EltVT = VT.getVectorElementType();
3711 unsigned NumElems = Elts.size();
3713 LoadSDNode *LDBase = NULL;
3714 unsigned LastLoadedElt = -1U;
3716 // For each element in the initializer, see if we've found a load or an undef.
3717 // If we don't find an initial load element, or later load elements are
3718 // non-consecutive, bail out.
3719 for (unsigned i = 0; i < NumElems; ++i) {
3720 SDValue Elt = Elts[i];
3722 if (!Elt.getNode() ||
3723 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
3726 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
3728 LDBase = cast<LoadSDNode>(Elt.getNode());
3732 if (Elt.getOpcode() == ISD::UNDEF)
3735 LoadSDNode *LD = cast<LoadSDNode>(Elt);
3736 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
3741 // If we have found an entire vector of loads and undefs, then return a large
3742 // load of the entire vector width starting at the base pointer. If we found
3743 // consecutive loads for the low half, generate a vzext_load node.
3744 if (LastLoadedElt == NumElems - 1) {
3745 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
3746 return DAG.getLoad(VT, dl, LDBase->getChain(), LDBase->getBasePtr(),
3747 LDBase->getSrcValue(), LDBase->getSrcValueOffset(),
3748 LDBase->isVolatile(), LDBase->isNonTemporal(), 0);
3749 return DAG.getLoad(VT, dl, LDBase->getChain(), LDBase->getBasePtr(),
3750 LDBase->getSrcValue(), LDBase->getSrcValueOffset(),
3751 LDBase->isVolatile(), LDBase->isNonTemporal(),
3752 LDBase->getAlignment());
3753 } else if (NumElems == 4 && LastLoadedElt == 1) {
3754 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
3755 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
3756 SDValue ResNode = DAG.getNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2);
3757 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, ResNode);
3763 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
3764 DebugLoc dl = Op.getDebugLoc();
3765 // All zero's are handled with pxor, all one's are handled with pcmpeqd.
3766 if (ISD::isBuildVectorAllZeros(Op.getNode())
3767 || ISD::isBuildVectorAllOnes(Op.getNode())) {
3768 // Canonicalize this to either <4 x i32> or <2 x i32> (SSE vs MMX) to
3769 // 1) ensure the zero vectors are CSE'd, and 2) ensure that i64 scalars are
3770 // eliminated on x86-32 hosts.
3771 if (Op.getValueType() == MVT::v4i32 || Op.getValueType() == MVT::v2i32)
3774 if (ISD::isBuildVectorAllOnes(Op.getNode()))
3775 return getOnesVector(Op.getValueType(), DAG, dl);
3776 return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG, dl);
3779 EVT VT = Op.getValueType();
3780 EVT ExtVT = VT.getVectorElementType();
3781 unsigned EVTBits = ExtVT.getSizeInBits();
3783 unsigned NumElems = Op.getNumOperands();
3784 unsigned NumZero = 0;
3785 unsigned NumNonZero = 0;
3786 unsigned NonZeros = 0;
3787 bool IsAllConstants = true;
3788 SmallSet<SDValue, 8> Values;
3789 for (unsigned i = 0; i < NumElems; ++i) {
3790 SDValue Elt = Op.getOperand(i);
3791 if (Elt.getOpcode() == ISD::UNDEF)
3794 if (Elt.getOpcode() != ISD::Constant &&
3795 Elt.getOpcode() != ISD::ConstantFP)
3796 IsAllConstants = false;
3797 if (X86::isZeroNode(Elt))
3800 NonZeros |= (1 << i);
3805 if (NumNonZero == 0) {
3806 // All undef vector. Return an UNDEF. All zero vectors were handled above.
3807 return DAG.getUNDEF(VT);
3810 // Special case for single non-zero, non-undef, element.
3811 if (NumNonZero == 1) {
3812 unsigned Idx = CountTrailingZeros_32(NonZeros);
3813 SDValue Item = Op.getOperand(Idx);
3815 // If this is an insertion of an i64 value on x86-32, and if the top bits of
3816 // the value are obviously zero, truncate the value to i32 and do the
3817 // insertion that way. Only do this if the value is non-constant or if the
3818 // value is a constant being inserted into element 0. It is cheaper to do
3819 // a constant pool load than it is to do a movd + shuffle.
3820 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
3821 (!IsAllConstants || Idx == 0)) {
3822 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
3823 // Handle MMX and SSE both.
3824 EVT VecVT = VT == MVT::v2i64 ? MVT::v4i32 : MVT::v2i32;
3825 unsigned VecElts = VT == MVT::v2i64 ? 4 : 2;
3827 // Truncate the value (which may itself be a constant) to i32, and
3828 // convert it to a vector with movd (S2V+shuffle to zero extend).
3829 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
3830 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
3831 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
3832 Subtarget->hasSSE2(), DAG);
3834 // Now we have our 32-bit value zero extended in the low element of
3835 // a vector. If Idx != 0, swizzle it into place.
3837 SmallVector<int, 4> Mask;
3838 Mask.push_back(Idx);
3839 for (unsigned i = 1; i != VecElts; ++i)
3841 Item = DAG.getVectorShuffle(VecVT, dl, Item,
3842 DAG.getUNDEF(Item.getValueType()),
3845 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Item);
3849 // If we have a constant or non-constant insertion into the low element of
3850 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
3851 // the rest of the elements. This will be matched as movd/movq/movss/movsd
3852 // depending on what the source datatype is.
3855 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
3856 } else if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
3857 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
3858 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
3859 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
3860 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget->hasSSE2(),
3862 } else if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
3863 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
3864 EVT MiddleVT = VT.getSizeInBits() == 64 ? MVT::v2i32 : MVT::v4i32;
3865 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MiddleVT, Item);
3866 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
3867 Subtarget->hasSSE2(), DAG);
3868 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Item);
3872 // Is it a vector logical left shift?
3873 if (NumElems == 2 && Idx == 1 &&
3874 X86::isZeroNode(Op.getOperand(0)) &&
3875 !X86::isZeroNode(Op.getOperand(1))) {
3876 unsigned NumBits = VT.getSizeInBits();
3877 return getVShift(true, VT,
3878 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
3879 VT, Op.getOperand(1)),
3880 NumBits/2, DAG, *this, dl);
3883 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
3886 // Otherwise, if this is a vector with i32 or f32 elements, and the element
3887 // is a non-constant being inserted into an element other than the low one,
3888 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
3889 // movd/movss) to move this into the low element, then shuffle it into
3891 if (EVTBits == 32) {
3892 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
3894 // Turn it into a shuffle of zero and zero-extended scalar to vector.
3895 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
3896 Subtarget->hasSSE2(), DAG);
3897 SmallVector<int, 8> MaskVec;
3898 for (unsigned i = 0; i < NumElems; i++)
3899 MaskVec.push_back(i == Idx ? 0 : 1);
3900 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
3904 // Splat is obviously ok. Let legalizer expand it to a shuffle.
3905 if (Values.size() == 1) {
3906 if (EVTBits == 32) {
3907 // Instead of a shuffle like this:
3908 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
3909 // Check if it's possible to issue this instead.
3910 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
3911 unsigned Idx = CountTrailingZeros_32(NonZeros);
3912 SDValue Item = Op.getOperand(Idx);
3913 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
3914 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
3919 // A vector full of immediates; various special cases are already
3920 // handled, so this is best done with a single constant-pool load.
3924 // Let legalizer expand 2-wide build_vectors.
3925 if (EVTBits == 64) {
3926 if (NumNonZero == 1) {
3927 // One half is zero or undef.
3928 unsigned Idx = CountTrailingZeros_32(NonZeros);
3929 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
3930 Op.getOperand(Idx));
3931 return getShuffleVectorZeroOrUndef(V2, Idx, true,
3932 Subtarget->hasSSE2(), DAG);
3937 // If element VT is < 32 bits, convert it to inserts into a zero vector.
3938 if (EVTBits == 8 && NumElems == 16) {
3939 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
3941 if (V.getNode()) return V;
3944 if (EVTBits == 16 && NumElems == 8) {
3945 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
3947 if (V.getNode()) return V;
3950 // If element VT is == 32 bits, turn it into a number of shuffles.
3951 SmallVector<SDValue, 8> V;
3953 if (NumElems == 4 && NumZero > 0) {
3954 for (unsigned i = 0; i < 4; ++i) {
3955 bool isZero = !(NonZeros & (1 << i));
3957 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
3959 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
3962 for (unsigned i = 0; i < 2; ++i) {
3963 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
3966 V[i] = V[i*2]; // Must be a zero vector.
3969 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
3972 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
3975 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
3980 SmallVector<int, 8> MaskVec;
3981 bool Reverse = (NonZeros & 0x3) == 2;
3982 for (unsigned i = 0; i < 2; ++i)
3983 MaskVec.push_back(Reverse ? 1-i : i);
3984 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
3985 for (unsigned i = 0; i < 2; ++i)
3986 MaskVec.push_back(Reverse ? 1-i+NumElems : i+NumElems);
3987 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
3990 if (Values.size() > 1 && VT.getSizeInBits() == 128) {
3991 // Check for a build vector of consecutive loads.
3992 for (unsigned i = 0; i < NumElems; ++i)
3993 V[i] = Op.getOperand(i);
3995 // Check for elements which are consecutive loads.
3996 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG);
4000 // For SSE 4.1, use inserts into undef.
4001 if (getSubtarget()->hasSSE41()) {
4002 V[0] = DAG.getUNDEF(VT);
4003 for (unsigned i = 0; i < NumElems; ++i)
4004 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
4005 V[0] = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, V[0],
4006 Op.getOperand(i), DAG.getIntPtrConstant(i));
4010 // Otherwise, expand into a number of unpckl*
4012 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
4013 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
4014 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
4015 for (unsigned i = 0; i < NumElems; ++i)
4016 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
4018 while (NumElems != 0) {
4019 for (unsigned i = 0; i < NumElems; ++i)
4020 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + NumElems]);
4029 X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
4030 // We support concatenate two MMX registers and place them in a MMX
4031 // register. This is better than doing a stack convert.
4032 DebugLoc dl = Op.getDebugLoc();
4033 EVT ResVT = Op.getValueType();
4034 assert(Op.getNumOperands() == 2);
4035 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 ||
4036 ResVT == MVT::v8i16 || ResVT == MVT::v16i8);
4038 SDValue InVec = DAG.getNode(ISD::BIT_CONVERT,dl, MVT::v1i64, Op.getOperand(0));
4039 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
4040 InVec = Op.getOperand(1);
4041 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
4042 unsigned NumElts = ResVT.getVectorNumElements();
4043 VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, ResVT, VecOp);
4044 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp,
4045 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1));
4047 InVec = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v1i64, InVec);
4048 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
4049 Mask[0] = 0; Mask[1] = 2;
4050 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask);
4052 return DAG.getNode(ISD::BIT_CONVERT, dl, ResVT, VecOp);
4055 // v8i16 shuffles - Prefer shuffles in the following order:
4056 // 1. [all] pshuflw, pshufhw, optional move
4057 // 2. [ssse3] 1 x pshufb
4058 // 3. [ssse3] 2 x pshufb + 1 x por
4059 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
4061 SDValue LowerVECTOR_SHUFFLEv8i16(ShuffleVectorSDNode *SVOp,
4063 const X86TargetLowering &TLI) {
4064 SDValue V1 = SVOp->getOperand(0);
4065 SDValue V2 = SVOp->getOperand(1);
4066 DebugLoc dl = SVOp->getDebugLoc();
4067 SmallVector<int, 8> MaskVals;
4069 // Determine if more than 1 of the words in each of the low and high quadwords
4070 // of the result come from the same quadword of one of the two inputs. Undef
4071 // mask values count as coming from any quadword, for better codegen.
4072 SmallVector<unsigned, 4> LoQuad(4);
4073 SmallVector<unsigned, 4> HiQuad(4);
4074 BitVector InputQuads(4);
4075 for (unsigned i = 0; i < 8; ++i) {
4076 SmallVectorImpl<unsigned> &Quad = i < 4 ? LoQuad : HiQuad;
4077 int EltIdx = SVOp->getMaskElt(i);
4078 MaskVals.push_back(EltIdx);
4087 InputQuads.set(EltIdx / 4);
4090 int BestLoQuad = -1;
4091 unsigned MaxQuad = 1;
4092 for (unsigned i = 0; i < 4; ++i) {
4093 if (LoQuad[i] > MaxQuad) {
4095 MaxQuad = LoQuad[i];
4099 int BestHiQuad = -1;
4101 for (unsigned i = 0; i < 4; ++i) {
4102 if (HiQuad[i] > MaxQuad) {
4104 MaxQuad = HiQuad[i];
4108 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
4109 // of the two input vectors, shuffle them into one input vector so only a
4110 // single pshufb instruction is necessary. If There are more than 2 input
4111 // quads, disable the next transformation since it does not help SSSE3.
4112 bool V1Used = InputQuads[0] || InputQuads[1];
4113 bool V2Used = InputQuads[2] || InputQuads[3];
4114 if (TLI.getSubtarget()->hasSSSE3()) {
4115 if (InputQuads.count() == 2 && V1Used && V2Used) {
4116 BestLoQuad = InputQuads.find_first();
4117 BestHiQuad = InputQuads.find_next(BestLoQuad);
4119 if (InputQuads.count() > 2) {
4125 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
4126 // the shuffle mask. If a quad is scored as -1, that means that it contains
4127 // words from all 4 input quadwords.
4129 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
4130 SmallVector<int, 8> MaskV;
4131 MaskV.push_back(BestLoQuad < 0 ? 0 : BestLoQuad);
4132 MaskV.push_back(BestHiQuad < 0 ? 1 : BestHiQuad);
4133 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
4134 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V1),
4135 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V2), &MaskV[0]);
4136 NewV = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, NewV);
4138 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
4139 // source words for the shuffle, to aid later transformations.
4140 bool AllWordsInNewV = true;
4141 bool InOrder[2] = { true, true };
4142 for (unsigned i = 0; i != 8; ++i) {
4143 int idx = MaskVals[i];
4145 InOrder[i/4] = false;
4146 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
4148 AllWordsInNewV = false;
4152 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
4153 if (AllWordsInNewV) {
4154 for (int i = 0; i != 8; ++i) {
4155 int idx = MaskVals[i];
4158 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
4159 if ((idx != i) && idx < 4)
4161 if ((idx != i) && idx > 3)
4170 // If we've eliminated the use of V2, and the new mask is a pshuflw or
4171 // pshufhw, that's as cheap as it gets. Return the new shuffle.
4172 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
4173 return DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
4174 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
4178 // If we have SSSE3, and all words of the result are from 1 input vector,
4179 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
4180 // is present, fall back to case 4.
4181 if (TLI.getSubtarget()->hasSSSE3()) {
4182 SmallVector<SDValue,16> pshufbMask;
4184 // If we have elements from both input vectors, set the high bit of the
4185 // shuffle mask element to zero out elements that come from V2 in the V1
4186 // mask, and elements that come from V1 in the V2 mask, so that the two
4187 // results can be OR'd together.
4188 bool TwoInputs = V1Used && V2Used;
4189 for (unsigned i = 0; i != 8; ++i) {
4190 int EltIdx = MaskVals[i] * 2;
4191 if (TwoInputs && (EltIdx >= 16)) {
4192 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4193 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4196 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
4197 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8));
4199 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V1);
4200 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
4201 DAG.getNode(ISD::BUILD_VECTOR, dl,
4202 MVT::v16i8, &pshufbMask[0], 16));
4204 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
4206 // Calculate the shuffle mask for the second input, shuffle it, and
4207 // OR it with the first shuffled input.
4209 for (unsigned i = 0; i != 8; ++i) {
4210 int EltIdx = MaskVals[i] * 2;
4212 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4213 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4216 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
4217 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8));
4219 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V2);
4220 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
4221 DAG.getNode(ISD::BUILD_VECTOR, dl,
4222 MVT::v16i8, &pshufbMask[0], 16));
4223 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
4224 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
4227 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
4228 // and update MaskVals with new element order.
4229 BitVector InOrder(8);
4230 if (BestLoQuad >= 0) {
4231 SmallVector<int, 8> MaskV;
4232 for (int i = 0; i != 4; ++i) {
4233 int idx = MaskVals[i];
4235 MaskV.push_back(-1);
4237 } else if ((idx / 4) == BestLoQuad) {
4238 MaskV.push_back(idx & 3);
4241 MaskV.push_back(-1);
4244 for (unsigned i = 4; i != 8; ++i)
4246 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
4250 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
4251 // and update MaskVals with the new element order.
4252 if (BestHiQuad >= 0) {
4253 SmallVector<int, 8> MaskV;
4254 for (unsigned i = 0; i != 4; ++i)
4256 for (unsigned i = 4; i != 8; ++i) {
4257 int idx = MaskVals[i];
4259 MaskV.push_back(-1);
4261 } else if ((idx / 4) == BestHiQuad) {
4262 MaskV.push_back((idx & 3) + 4);
4265 MaskV.push_back(-1);
4268 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
4272 // In case BestHi & BestLo were both -1, which means each quadword has a word
4273 // from each of the four input quadwords, calculate the InOrder bitvector now
4274 // before falling through to the insert/extract cleanup.
4275 if (BestLoQuad == -1 && BestHiQuad == -1) {
4277 for (int i = 0; i != 8; ++i)
4278 if (MaskVals[i] < 0 || MaskVals[i] == i)
4282 // The other elements are put in the right place using pextrw and pinsrw.
4283 for (unsigned i = 0; i != 8; ++i) {
4286 int EltIdx = MaskVals[i];
4289 SDValue ExtOp = (EltIdx < 8)
4290 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
4291 DAG.getIntPtrConstant(EltIdx))
4292 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
4293 DAG.getIntPtrConstant(EltIdx - 8));
4294 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
4295 DAG.getIntPtrConstant(i));
4300 // v16i8 shuffles - Prefer shuffles in the following order:
4301 // 1. [ssse3] 1 x pshufb
4302 // 2. [ssse3] 2 x pshufb + 1 x por
4303 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
4305 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
4307 const X86TargetLowering &TLI) {
4308 SDValue V1 = SVOp->getOperand(0);
4309 SDValue V2 = SVOp->getOperand(1);
4310 DebugLoc dl = SVOp->getDebugLoc();
4311 SmallVector<int, 16> MaskVals;
4312 SVOp->getMask(MaskVals);
4314 // If we have SSSE3, case 1 is generated when all result bytes come from
4315 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
4316 // present, fall back to case 3.
4317 // FIXME: kill V2Only once shuffles are canonizalized by getNode.
4320 for (unsigned i = 0; i < 16; ++i) {
4321 int EltIdx = MaskVals[i];
4330 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
4331 if (TLI.getSubtarget()->hasSSSE3()) {
4332 SmallVector<SDValue,16> pshufbMask;
4334 // If all result elements are from one input vector, then only translate
4335 // undef mask values to 0x80 (zero out result) in the pshufb mask.
4337 // Otherwise, we have elements from both input vectors, and must zero out
4338 // elements that come from V2 in the first mask, and V1 in the second mask
4339 // so that we can OR them together.
4340 bool TwoInputs = !(V1Only || V2Only);
4341 for (unsigned i = 0; i != 16; ++i) {
4342 int EltIdx = MaskVals[i];
4343 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) {
4344 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4347 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
4349 // If all the elements are from V2, assign it to V1 and return after
4350 // building the first pshufb.
4353 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
4354 DAG.getNode(ISD::BUILD_VECTOR, dl,
4355 MVT::v16i8, &pshufbMask[0], 16));
4359 // Calculate the shuffle mask for the second input, shuffle it, and
4360 // OR it with the first shuffled input.
4362 for (unsigned i = 0; i != 16; ++i) {
4363 int EltIdx = MaskVals[i];
4365 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4368 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
4370 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
4371 DAG.getNode(ISD::BUILD_VECTOR, dl,
4372 MVT::v16i8, &pshufbMask[0], 16));
4373 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
4376 // No SSSE3 - Calculate in place words and then fix all out of place words
4377 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
4378 // the 16 different words that comprise the two doublequadword input vectors.
4379 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
4380 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V2);
4381 SDValue NewV = V2Only ? V2 : V1;
4382 for (int i = 0; i != 8; ++i) {
4383 int Elt0 = MaskVals[i*2];
4384 int Elt1 = MaskVals[i*2+1];
4386 // This word of the result is all undef, skip it.
4387 if (Elt0 < 0 && Elt1 < 0)
4390 // This word of the result is already in the correct place, skip it.
4391 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1))
4393 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17))
4396 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
4397 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
4400 // If Elt0 and Elt1 are defined, are consecutive, and can be load
4401 // using a single extract together, load it and store it.
4402 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
4403 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
4404 DAG.getIntPtrConstant(Elt1 / 2));
4405 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
4406 DAG.getIntPtrConstant(i));
4410 // If Elt1 is defined, extract it from the appropriate source. If the
4411 // source byte is not also odd, shift the extracted word left 8 bits
4412 // otherwise clear the bottom 8 bits if we need to do an or.
4414 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
4415 DAG.getIntPtrConstant(Elt1 / 2));
4416 if ((Elt1 & 1) == 0)
4417 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
4418 DAG.getConstant(8, TLI.getShiftAmountTy()));
4420 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
4421 DAG.getConstant(0xFF00, MVT::i16));
4423 // If Elt0 is defined, extract it from the appropriate source. If the
4424 // source byte is not also even, shift the extracted word right 8 bits. If
4425 // Elt1 was also defined, OR the extracted values together before
4426 // inserting them in the result.
4428 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
4429 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
4430 if ((Elt0 & 1) != 0)
4431 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
4432 DAG.getConstant(8, TLI.getShiftAmountTy()));
4434 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
4435 DAG.getConstant(0x00FF, MVT::i16));
4436 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
4439 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
4440 DAG.getIntPtrConstant(i));
4442 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, NewV);
4445 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
4446 /// ones, or rewriting v4i32 / v2f32 as 2 wide ones if possible. This can be
4447 /// done when every pair / quad of shuffle mask elements point to elements in
4448 /// the right sequence. e.g.
4449 /// vector_shuffle <>, <>, < 3, 4, | 10, 11, | 0, 1, | 14, 15>
4451 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
4453 const TargetLowering &TLI, DebugLoc dl) {
4454 EVT VT = SVOp->getValueType(0);
4455 SDValue V1 = SVOp->getOperand(0);
4456 SDValue V2 = SVOp->getOperand(1);
4457 unsigned NumElems = VT.getVectorNumElements();
4458 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
4459 EVT MaskVT = MVT::getIntVectorWithNumElements(NewWidth);
4461 switch (VT.getSimpleVT().SimpleTy) {
4462 default: assert(false && "Unexpected!");
4463 case MVT::v4f32: NewVT = MVT::v2f64; break;
4464 case MVT::v4i32: NewVT = MVT::v2i64; break;
4465 case MVT::v8i16: NewVT = MVT::v4i32; break;
4466 case MVT::v16i8: NewVT = MVT::v4i32; break;
4469 if (NewWidth == 2) {
4475 int Scale = NumElems / NewWidth;
4476 SmallVector<int, 8> MaskVec;
4477 for (unsigned i = 0; i < NumElems; i += Scale) {
4479 for (int j = 0; j < Scale; ++j) {
4480 int EltIdx = SVOp->getMaskElt(i+j);
4484 StartIdx = EltIdx - (EltIdx % Scale);
4485 if (EltIdx != StartIdx + j)
4489 MaskVec.push_back(-1);
4491 MaskVec.push_back(StartIdx / Scale);
4494 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V1);
4495 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V2);
4496 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
4499 /// getVZextMovL - Return a zero-extending vector move low node.
4501 static SDValue getVZextMovL(EVT VT, EVT OpVT,
4502 SDValue SrcOp, SelectionDAG &DAG,
4503 const X86Subtarget *Subtarget, DebugLoc dl) {
4504 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
4505 LoadSDNode *LD = NULL;
4506 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
4507 LD = dyn_cast<LoadSDNode>(SrcOp);
4509 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
4511 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
4512 if ((ExtVT.SimpleTy != MVT::i64 || Subtarget->is64Bit()) &&
4513 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
4514 SrcOp.getOperand(0).getOpcode() == ISD::BIT_CONVERT &&
4515 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
4517 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
4518 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4519 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
4520 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
4528 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4529 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
4530 DAG.getNode(ISD::BIT_CONVERT, dl,
4534 /// LowerVECTOR_SHUFFLE_4wide - Handle all 4 wide cases with a number of
4537 LowerVECTOR_SHUFFLE_4wide(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
4538 SDValue V1 = SVOp->getOperand(0);
4539 SDValue V2 = SVOp->getOperand(1);
4540 DebugLoc dl = SVOp->getDebugLoc();
4541 EVT VT = SVOp->getValueType(0);
4543 SmallVector<std::pair<int, int>, 8> Locs;
4545 SmallVector<int, 8> Mask1(4U, -1);
4546 SmallVector<int, 8> PermMask;
4547 SVOp->getMask(PermMask);
4551 for (unsigned i = 0; i != 4; ++i) {
4552 int Idx = PermMask[i];
4554 Locs[i] = std::make_pair(-1, -1);
4556 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
4558 Locs[i] = std::make_pair(0, NumLo);
4562 Locs[i] = std::make_pair(1, NumHi);
4564 Mask1[2+NumHi] = Idx;
4570 if (NumLo <= 2 && NumHi <= 2) {
4571 // If no more than two elements come from either vector. This can be
4572 // implemented with two shuffles. First shuffle gather the elements.
4573 // The second shuffle, which takes the first shuffle as both of its
4574 // vector operands, put the elements into the right order.
4575 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
4577 SmallVector<int, 8> Mask2(4U, -1);
4579 for (unsigned i = 0; i != 4; ++i) {
4580 if (Locs[i].first == -1)
4583 unsigned Idx = (i < 2) ? 0 : 4;
4584 Idx += Locs[i].first * 2 + Locs[i].second;
4589 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
4590 } else if (NumLo == 3 || NumHi == 3) {
4591 // Otherwise, we must have three elements from one vector, call it X, and
4592 // one element from the other, call it Y. First, use a shufps to build an
4593 // intermediate vector with the one element from Y and the element from X
4594 // that will be in the same half in the final destination (the indexes don't
4595 // matter). Then, use a shufps to build the final vector, taking the half
4596 // containing the element from Y from the intermediate, and the other half
4599 // Normalize it so the 3 elements come from V1.
4600 CommuteVectorShuffleMask(PermMask, VT);
4604 // Find the element from V2.
4606 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
4607 int Val = PermMask[HiIndex];
4614 Mask1[0] = PermMask[HiIndex];
4616 Mask1[2] = PermMask[HiIndex^1];
4618 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
4621 Mask1[0] = PermMask[0];
4622 Mask1[1] = PermMask[1];
4623 Mask1[2] = HiIndex & 1 ? 6 : 4;
4624 Mask1[3] = HiIndex & 1 ? 4 : 6;
4625 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
4627 Mask1[0] = HiIndex & 1 ? 2 : 0;
4628 Mask1[1] = HiIndex & 1 ? 0 : 2;
4629 Mask1[2] = PermMask[2];
4630 Mask1[3] = PermMask[3];
4635 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
4639 // Break it into (shuffle shuffle_hi, shuffle_lo).
4641 SmallVector<int,8> LoMask(4U, -1);
4642 SmallVector<int,8> HiMask(4U, -1);
4644 SmallVector<int,8> *MaskPtr = &LoMask;
4645 unsigned MaskIdx = 0;
4648 for (unsigned i = 0; i != 4; ++i) {
4655 int Idx = PermMask[i];
4657 Locs[i] = std::make_pair(-1, -1);
4658 } else if (Idx < 4) {
4659 Locs[i] = std::make_pair(MaskIdx, LoIdx);
4660 (*MaskPtr)[LoIdx] = Idx;
4663 Locs[i] = std::make_pair(MaskIdx, HiIdx);
4664 (*MaskPtr)[HiIdx] = Idx;
4669 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
4670 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
4671 SmallVector<int, 8> MaskOps;
4672 for (unsigned i = 0; i != 4; ++i) {
4673 if (Locs[i].first == -1) {
4674 MaskOps.push_back(-1);
4676 unsigned Idx = Locs[i].first * 4 + Locs[i].second;
4677 MaskOps.push_back(Idx);
4680 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
4684 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
4685 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
4686 SDValue V1 = Op.getOperand(0);
4687 SDValue V2 = Op.getOperand(1);
4688 EVT VT = Op.getValueType();
4689 DebugLoc dl = Op.getDebugLoc();
4690 unsigned NumElems = VT.getVectorNumElements();
4691 bool isMMX = VT.getSizeInBits() == 64;
4692 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
4693 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
4694 bool V1IsSplat = false;
4695 bool V2IsSplat = false;
4697 if (isZeroShuffle(SVOp))
4698 return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
4700 // Promote splats to v4f32.
4701 if (SVOp->isSplat()) {
4702 if (isMMX || NumElems < 4)
4704 return PromoteSplat(SVOp, DAG, Subtarget->hasSSE2());
4707 // If the shuffle can be profitably rewritten as a narrower shuffle, then
4709 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
4710 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
4711 if (NewOp.getNode())
4712 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4713 LowerVECTOR_SHUFFLE(NewOp, DAG));
4714 } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
4715 // FIXME: Figure out a cleaner way to do this.
4716 // Try to make use of movq to zero out the top part.
4717 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
4718 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
4719 if (NewOp.getNode()) {
4720 if (isCommutedMOVL(cast<ShuffleVectorSDNode>(NewOp), true, false))
4721 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(0),
4722 DAG, Subtarget, dl);
4724 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
4725 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
4726 if (NewOp.getNode() && X86::isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)))
4727 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1),
4728 DAG, Subtarget, dl);
4732 if (X86::isPSHUFDMask(SVOp))
4735 // Check if this can be converted into a logical shift.
4736 bool isLeft = false;
4739 bool isShift = getSubtarget()->hasSSE2() &&
4740 isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
4741 if (isShift && ShVal.hasOneUse()) {
4742 // If the shifted value has multiple uses, it may be cheaper to use
4743 // v_set0 + movlhps or movhlps, etc.
4744 EVT EltVT = VT.getVectorElementType();
4745 ShAmt *= EltVT.getSizeInBits();
4746 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
4749 if (X86::isMOVLMask(SVOp)) {
4752 if (ISD::isBuildVectorAllZeros(V1.getNode()))
4753 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
4758 // FIXME: fold these into legal mask.
4759 if (!isMMX && (X86::isMOVSHDUPMask(SVOp) ||
4760 X86::isMOVSLDUPMask(SVOp) ||
4761 X86::isMOVHLPSMask(SVOp) ||
4762 X86::isMOVLHPSMask(SVOp) ||
4763 X86::isMOVLPMask(SVOp)))
4766 if (ShouldXformToMOVHLPS(SVOp) ||
4767 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp))
4768 return CommuteVectorShuffle(SVOp, DAG);
4771 // No better options. Use a vshl / vsrl.
4772 EVT EltVT = VT.getVectorElementType();
4773 ShAmt *= EltVT.getSizeInBits();
4774 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
4777 bool Commuted = false;
4778 // FIXME: This should also accept a bitcast of a splat? Be careful, not
4779 // 1,1,1,1 -> v8i16 though.
4780 V1IsSplat = isSplatVector(V1.getNode());
4781 V2IsSplat = isSplatVector(V2.getNode());
4783 // Canonicalize the splat or undef, if present, to be on the RHS.
4784 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
4785 Op = CommuteVectorShuffle(SVOp, DAG);
4786 SVOp = cast<ShuffleVectorSDNode>(Op);
4787 V1 = SVOp->getOperand(0);
4788 V2 = SVOp->getOperand(1);
4789 std::swap(V1IsSplat, V2IsSplat);
4790 std::swap(V1IsUndef, V2IsUndef);
4794 if (isCommutedMOVL(SVOp, V2IsSplat, V2IsUndef)) {
4795 // Shuffling low element of v1 into undef, just return v1.
4798 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
4799 // the instruction selector will not match, so get a canonical MOVL with
4800 // swapped operands to undo the commute.
4801 return getMOVL(DAG, dl, VT, V2, V1);
4804 if (X86::isUNPCKL_v_undef_Mask(SVOp) ||
4805 X86::isUNPCKH_v_undef_Mask(SVOp) ||
4806 X86::isUNPCKLMask(SVOp) ||
4807 X86::isUNPCKHMask(SVOp))
4811 // Normalize mask so all entries that point to V2 points to its first
4812 // element then try to match unpck{h|l} again. If match, return a
4813 // new vector_shuffle with the corrected mask.
4814 SDValue NewMask = NormalizeMask(SVOp, DAG);
4815 ShuffleVectorSDNode *NSVOp = cast<ShuffleVectorSDNode>(NewMask);
4816 if (NSVOp != SVOp) {
4817 if (X86::isUNPCKLMask(NSVOp, true)) {
4819 } else if (X86::isUNPCKHMask(NSVOp, true)) {
4826 // Commute is back and try unpck* again.
4827 // FIXME: this seems wrong.
4828 SDValue NewOp = CommuteVectorShuffle(SVOp, DAG);
4829 ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp);
4830 if (X86::isUNPCKL_v_undef_Mask(NewSVOp) ||
4831 X86::isUNPCKH_v_undef_Mask(NewSVOp) ||
4832 X86::isUNPCKLMask(NewSVOp) ||
4833 X86::isUNPCKHMask(NewSVOp))
4837 // FIXME: for mmx, bitcast v2i32 to v4i16 for shuffle.
4839 // Normalize the node to match x86 shuffle ops if needed
4840 if (!isMMX && V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(SVOp))
4841 return CommuteVectorShuffle(SVOp, DAG);
4843 // Check for legal shuffle and return?
4844 SmallVector<int, 16> PermMask;
4845 SVOp->getMask(PermMask);
4846 if (isShuffleMaskLegal(PermMask, VT))
4849 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
4850 if (VT == MVT::v8i16) {
4851 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(SVOp, DAG, *this);
4852 if (NewOp.getNode())
4856 if (VT == MVT::v16i8) {
4857 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
4858 if (NewOp.getNode())
4862 // Handle all 4 wide cases with a number of shuffles except for MMX.
4863 if (NumElems == 4 && !isMMX)
4864 return LowerVECTOR_SHUFFLE_4wide(SVOp, DAG);
4870 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
4871 SelectionDAG &DAG) const {
4872 EVT VT = Op.getValueType();
4873 DebugLoc dl = Op.getDebugLoc();
4874 if (VT.getSizeInBits() == 8) {
4875 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
4876 Op.getOperand(0), Op.getOperand(1));
4877 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
4878 DAG.getValueType(VT));
4879 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
4880 } else if (VT.getSizeInBits() == 16) {
4881 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4882 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
4884 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
4885 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4886 DAG.getNode(ISD::BIT_CONVERT, dl,
4890 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
4891 Op.getOperand(0), Op.getOperand(1));
4892 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
4893 DAG.getValueType(VT));
4894 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
4895 } else if (VT == MVT::f32) {
4896 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
4897 // the result back to FR32 register. It's only worth matching if the
4898 // result has a single use which is a store or a bitcast to i32. And in
4899 // the case of a store, it's not worth it if the index is a constant 0,
4900 // because a MOVSSmr can be used instead, which is smaller and faster.
4901 if (!Op.hasOneUse())
4903 SDNode *User = *Op.getNode()->use_begin();
4904 if ((User->getOpcode() != ISD::STORE ||
4905 (isa<ConstantSDNode>(Op.getOperand(1)) &&
4906 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
4907 (User->getOpcode() != ISD::BIT_CONVERT ||
4908 User->getValueType(0) != MVT::i32))
4910 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4911 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32,
4914 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Extract);
4915 } else if (VT == MVT::i32) {
4916 // ExtractPS works with constant index.
4917 if (isa<ConstantSDNode>(Op.getOperand(1)))
4925 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
4926 SelectionDAG &DAG) const {
4927 if (!isa<ConstantSDNode>(Op.getOperand(1)))
4930 if (Subtarget->hasSSE41()) {
4931 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
4936 EVT VT = Op.getValueType();
4937 DebugLoc dl = Op.getDebugLoc();
4938 // TODO: handle v16i8.
4939 if (VT.getSizeInBits() == 16) {
4940 SDValue Vec = Op.getOperand(0);
4941 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4943 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
4944 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4945 DAG.getNode(ISD::BIT_CONVERT, dl,
4948 // Transform it so it match pextrw which produces a 32-bit result.
4949 EVT EltVT = MVT::i32;
4950 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
4951 Op.getOperand(0), Op.getOperand(1));
4952 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
4953 DAG.getValueType(VT));
4954 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
4955 } else if (VT.getSizeInBits() == 32) {
4956 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4960 // SHUFPS the element to the lowest double word, then movss.
4961 int Mask[4] = { Idx, -1, -1, -1 };
4962 EVT VVT = Op.getOperand(0).getValueType();
4963 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
4964 DAG.getUNDEF(VVT), Mask);
4965 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
4966 DAG.getIntPtrConstant(0));
4967 } else if (VT.getSizeInBits() == 64) {
4968 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
4969 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
4970 // to match extract_elt for f64.
4971 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4975 // UNPCKHPD the element to the lowest double word, then movsd.
4976 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
4977 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
4978 int Mask[2] = { 1, -1 };
4979 EVT VVT = Op.getOperand(0).getValueType();
4980 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
4981 DAG.getUNDEF(VVT), Mask);
4982 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
4983 DAG.getIntPtrConstant(0));
4990 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op,
4991 SelectionDAG &DAG) const {
4992 EVT VT = Op.getValueType();
4993 EVT EltVT = VT.getVectorElementType();
4994 DebugLoc dl = Op.getDebugLoc();
4996 SDValue N0 = Op.getOperand(0);
4997 SDValue N1 = Op.getOperand(1);
4998 SDValue N2 = Op.getOperand(2);
5000 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
5001 isa<ConstantSDNode>(N2)) {
5003 if (VT == MVT::v8i16)
5004 Opc = X86ISD::PINSRW;
5005 else if (VT == MVT::v4i16)
5006 Opc = X86ISD::MMX_PINSRW;
5007 else if (VT == MVT::v16i8)
5008 Opc = X86ISD::PINSRB;
5010 Opc = X86ISD::PINSRB;
5012 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
5014 if (N1.getValueType() != MVT::i32)
5015 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
5016 if (N2.getValueType() != MVT::i32)
5017 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
5018 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
5019 } else if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
5020 // Bits [7:6] of the constant are the source select. This will always be
5021 // zero here. The DAG Combiner may combine an extract_elt index into these
5022 // bits. For example (insert (extract, 3), 2) could be matched by putting
5023 // the '3' into bits [7:6] of X86ISD::INSERTPS.
5024 // Bits [5:4] of the constant are the destination select. This is the
5025 // value of the incoming immediate.
5026 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
5027 // combine either bitwise AND or insert of float 0.0 to set these bits.
5028 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
5029 // Create this as a scalar to vector..
5030 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
5031 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
5032 } else if (EltVT == MVT::i32 && isa<ConstantSDNode>(N2)) {
5033 // PINSR* works with constant index.
5040 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
5041 EVT VT = Op.getValueType();
5042 EVT EltVT = VT.getVectorElementType();
5044 if (Subtarget->hasSSE41())
5045 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
5047 if (EltVT == MVT::i8)
5050 DebugLoc dl = Op.getDebugLoc();
5051 SDValue N0 = Op.getOperand(0);
5052 SDValue N1 = Op.getOperand(1);
5053 SDValue N2 = Op.getOperand(2);
5055 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
5056 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
5057 // as its second argument.
5058 if (N1.getValueType() != MVT::i32)
5059 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
5060 if (N2.getValueType() != MVT::i32)
5061 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
5062 return DAG.getNode(VT == MVT::v8i16 ? X86ISD::PINSRW : X86ISD::MMX_PINSRW,
5063 dl, VT, N0, N1, N2);
5069 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5070 DebugLoc dl = Op.getDebugLoc();
5071 if (Op.getValueType() == MVT::v2f32)
5072 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f32,
5073 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i32,
5074 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32,
5075 Op.getOperand(0))));
5077 if (Op.getValueType() == MVT::v1i64 && Op.getOperand(0).getValueType() == MVT::i64)
5078 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
5080 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
5081 EVT VT = MVT::v2i32;
5082 switch (Op.getValueType().getSimpleVT().SimpleTy) {
5089 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(),
5090 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, AnyExt));
5093 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
5094 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
5095 // one of the above mentioned nodes. It has to be wrapped because otherwise
5096 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
5097 // be used to form addressing mode. These wrapped nodes will be selected
5100 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
5101 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
5103 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
5105 unsigned char OpFlag = 0;
5106 unsigned WrapperKind = X86ISD::Wrapper;
5107 CodeModel::Model M = getTargetMachine().getCodeModel();
5109 if (Subtarget->isPICStyleRIPRel() &&
5110 (M == CodeModel::Small || M == CodeModel::Kernel))
5111 WrapperKind = X86ISD::WrapperRIP;
5112 else if (Subtarget->isPICStyleGOT())
5113 OpFlag = X86II::MO_GOTOFF;
5114 else if (Subtarget->isPICStyleStubPIC())
5115 OpFlag = X86II::MO_PIC_BASE_OFFSET;
5117 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
5119 CP->getOffset(), OpFlag);
5120 DebugLoc DL = CP->getDebugLoc();
5121 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
5122 // With PIC, the address is actually $g + Offset.
5124 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
5125 DAG.getNode(X86ISD::GlobalBaseReg,
5126 DebugLoc(), getPointerTy()),
5133 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
5134 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
5136 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
5138 unsigned char OpFlag = 0;
5139 unsigned WrapperKind = X86ISD::Wrapper;
5140 CodeModel::Model M = getTargetMachine().getCodeModel();
5142 if (Subtarget->isPICStyleRIPRel() &&
5143 (M == CodeModel::Small || M == CodeModel::Kernel))
5144 WrapperKind = X86ISD::WrapperRIP;
5145 else if (Subtarget->isPICStyleGOT())
5146 OpFlag = X86II::MO_GOTOFF;
5147 else if (Subtarget->isPICStyleStubPIC())
5148 OpFlag = X86II::MO_PIC_BASE_OFFSET;
5150 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
5152 DebugLoc DL = JT->getDebugLoc();
5153 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
5155 // With PIC, the address is actually $g + Offset.
5157 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
5158 DAG.getNode(X86ISD::GlobalBaseReg,
5159 DebugLoc(), getPointerTy()),
5167 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
5168 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
5170 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
5172 unsigned char OpFlag = 0;
5173 unsigned WrapperKind = X86ISD::Wrapper;
5174 CodeModel::Model M = getTargetMachine().getCodeModel();
5176 if (Subtarget->isPICStyleRIPRel() &&
5177 (M == CodeModel::Small || M == CodeModel::Kernel))
5178 WrapperKind = X86ISD::WrapperRIP;
5179 else if (Subtarget->isPICStyleGOT())
5180 OpFlag = X86II::MO_GOTOFF;
5181 else if (Subtarget->isPICStyleStubPIC())
5182 OpFlag = X86II::MO_PIC_BASE_OFFSET;
5184 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
5186 DebugLoc DL = Op.getDebugLoc();
5187 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
5190 // With PIC, the address is actually $g + Offset.
5191 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
5192 !Subtarget->is64Bit()) {
5193 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
5194 DAG.getNode(X86ISD::GlobalBaseReg,
5195 DebugLoc(), getPointerTy()),
5203 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
5204 // Create the TargetBlockAddressAddress node.
5205 unsigned char OpFlags =
5206 Subtarget->ClassifyBlockAddressReference();
5207 CodeModel::Model M = getTargetMachine().getCodeModel();
5208 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
5209 DebugLoc dl = Op.getDebugLoc();
5210 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(),
5211 /*isTarget=*/true, OpFlags);
5213 if (Subtarget->isPICStyleRIPRel() &&
5214 (M == CodeModel::Small || M == CodeModel::Kernel))
5215 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
5217 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
5219 // With PIC, the address is actually $g + Offset.
5220 if (isGlobalRelativeToPICBase(OpFlags)) {
5221 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
5222 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
5230 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
5232 SelectionDAG &DAG) const {
5233 // Create the TargetGlobalAddress node, folding in the constant
5234 // offset if it is legal.
5235 unsigned char OpFlags =
5236 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
5237 CodeModel::Model M = getTargetMachine().getCodeModel();
5239 if (OpFlags == X86II::MO_NO_FLAG &&
5240 X86::isOffsetSuitableForCodeModel(Offset, M)) {
5241 // A direct static reference to a global.
5242 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), Offset);
5245 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), 0, OpFlags);
5248 if (Subtarget->isPICStyleRIPRel() &&
5249 (M == CodeModel::Small || M == CodeModel::Kernel))
5250 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
5252 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
5254 // With PIC, the address is actually $g + Offset.
5255 if (isGlobalRelativeToPICBase(OpFlags)) {
5256 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
5257 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
5261 // For globals that require a load from a stub to get the address, emit the
5263 if (isGlobalStubReference(OpFlags))
5264 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
5265 PseudoSourceValue::getGOT(), 0, false, false, 0);
5267 // If there was a non-zero offset that we didn't fold, create an explicit
5270 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
5271 DAG.getConstant(Offset, getPointerTy()));
5277 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
5278 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
5279 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
5280 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
5284 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
5285 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
5286 unsigned char OperandFlags) {
5287 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5288 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
5289 DebugLoc dl = GA->getDebugLoc();
5290 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
5291 GA->getValueType(0),
5295 SDValue Ops[] = { Chain, TGA, *InFlag };
5296 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3);
5298 SDValue Ops[] = { Chain, TGA };
5299 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2);
5302 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
5303 MFI->setAdjustsStack(true);
5305 SDValue Flag = Chain.getValue(1);
5306 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
5309 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
5311 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
5314 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
5315 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
5316 DAG.getNode(X86ISD::GlobalBaseReg,
5317 DebugLoc(), PtrVT), InFlag);
5318 InFlag = Chain.getValue(1);
5320 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
5323 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
5325 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
5327 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
5328 X86::RAX, X86II::MO_TLSGD);
5331 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
5332 // "local exec" model.
5333 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
5334 const EVT PtrVT, TLSModel::Model model,
5336 DebugLoc dl = GA->getDebugLoc();
5337 // Get the Thread Pointer
5338 SDValue Base = DAG.getNode(X86ISD::SegmentBaseAddress,
5340 DAG.getRegister(is64Bit? X86::FS : X86::GS,
5343 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Base,
5344 NULL, 0, false, false, 0);
5346 unsigned char OperandFlags = 0;
5347 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
5349 unsigned WrapperKind = X86ISD::Wrapper;
5350 if (model == TLSModel::LocalExec) {
5351 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
5352 } else if (is64Bit) {
5353 assert(model == TLSModel::InitialExec);
5354 OperandFlags = X86II::MO_GOTTPOFF;
5355 WrapperKind = X86ISD::WrapperRIP;
5357 assert(model == TLSModel::InitialExec);
5358 OperandFlags = X86II::MO_INDNTPOFF;
5361 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
5363 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0),
5364 GA->getOffset(), OperandFlags);
5365 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
5367 if (model == TLSModel::InitialExec)
5368 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
5369 PseudoSourceValue::getGOT(), 0, false, false, 0);
5371 // The address of the thread local variable is the add of the thread
5372 // pointer with the offset of the variable.
5373 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
5377 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
5379 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
5380 const GlobalValue *GV = GA->getGlobal();
5382 if (Subtarget->isTargetELF()) {
5383 // TODO: implement the "local dynamic" model
5384 // TODO: implement the "initial exec"model for pic executables
5386 // If GV is an alias then use the aliasee for determining
5387 // thread-localness.
5388 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
5389 GV = GA->resolveAliasedGlobal(false);
5391 TLSModel::Model model
5392 = getTLSModel(GV, getTargetMachine().getRelocationModel());
5395 case TLSModel::GeneralDynamic:
5396 case TLSModel::LocalDynamic: // not implemented
5397 if (Subtarget->is64Bit())
5398 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
5399 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
5401 case TLSModel::InitialExec:
5402 case TLSModel::LocalExec:
5403 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
5404 Subtarget->is64Bit());
5406 } else if (Subtarget->isTargetDarwin()) {
5407 // Darwin only has one model of TLS. Lower to that.
5408 unsigned char OpFlag = 0;
5409 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
5410 X86ISD::WrapperRIP : X86ISD::Wrapper;
5412 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
5414 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
5415 !Subtarget->is64Bit();
5417 OpFlag = X86II::MO_TLVP_PIC_BASE;
5419 OpFlag = X86II::MO_TLVP;
5421 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(),
5423 GA->getOffset(), OpFlag);
5425 DebugLoc DL = Op.getDebugLoc();
5426 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
5428 // With PIC32, the address is actually $g + Offset.
5430 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
5431 DAG.getNode(X86ISD::GlobalBaseReg,
5432 DebugLoc(), getPointerTy()),
5435 // Lowering the machine isd will make sure everything is in the right
5437 SDValue Args[] = { Offset };
5438 SDValue Chain = DAG.getNode(X86ISD::TLSCALL, DL, MVT::Other, Args, 1);
5440 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
5441 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5442 MFI->setAdjustsStack(true);
5444 // And our return value (tls address) is in the standard call return value
5446 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
5447 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy());
5451 "TLS not implemented for this target.");
5453 llvm_unreachable("Unreachable");
5458 /// LowerShift - Lower SRA_PARTS and friends, which return two i32 values and
5459 /// take a 2 x i32 value to shift plus a shift amount.
5460 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
5461 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
5462 EVT VT = Op.getValueType();
5463 unsigned VTBits = VT.getSizeInBits();
5464 DebugLoc dl = Op.getDebugLoc();
5465 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
5466 SDValue ShOpLo = Op.getOperand(0);
5467 SDValue ShOpHi = Op.getOperand(1);
5468 SDValue ShAmt = Op.getOperand(2);
5469 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
5470 DAG.getConstant(VTBits - 1, MVT::i8))
5471 : DAG.getConstant(0, VT);
5474 if (Op.getOpcode() == ISD::SHL_PARTS) {
5475 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
5476 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
5478 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
5479 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
5482 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
5483 DAG.getConstant(VTBits, MVT::i8));
5484 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
5485 AndNode, DAG.getConstant(0, MVT::i8));
5488 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
5489 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
5490 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
5492 if (Op.getOpcode() == ISD::SHL_PARTS) {
5493 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
5494 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
5496 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
5497 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
5500 SDValue Ops[2] = { Lo, Hi };
5501 return DAG.getMergeValues(Ops, 2, dl);
5504 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
5505 SelectionDAG &DAG) const {
5506 EVT SrcVT = Op.getOperand(0).getValueType();
5508 if (SrcVT.isVector()) {
5509 if (SrcVT == MVT::v2i32 && Op.getValueType() == MVT::v2f64) {
5515 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
5516 "Unknown SINT_TO_FP to lower!");
5518 // These are really Legal; return the operand so the caller accepts it as
5520 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
5522 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
5523 Subtarget->is64Bit()) {
5527 DebugLoc dl = Op.getDebugLoc();
5528 unsigned Size = SrcVT.getSizeInBits()/8;
5529 MachineFunction &MF = DAG.getMachineFunction();
5530 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
5531 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5532 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
5534 PseudoSourceValue::getFixedStack(SSFI), 0,
5536 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
5539 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
5541 SelectionDAG &DAG) const {
5543 DebugLoc dl = Op.getDebugLoc();
5545 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
5547 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag);
5549 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
5550 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
5551 SDValue Result = DAG.getNode(useSSE ? X86ISD::FILD_FLAG : X86ISD::FILD, dl,
5552 Tys, Ops, array_lengthof(Ops));
5555 Chain = Result.getValue(1);
5556 SDValue InFlag = Result.getValue(2);
5558 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
5559 // shouldn't be necessary except that RFP cannot be live across
5560 // multiple blocks. When stackifier is fixed, they can be uncoupled.
5561 MachineFunction &MF = DAG.getMachineFunction();
5562 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
5563 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5564 Tys = DAG.getVTList(MVT::Other);
5566 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
5568 Chain = DAG.getNode(X86ISD::FST, dl, Tys, Ops, array_lengthof(Ops));
5569 Result = DAG.getLoad(Op.getValueType(), dl, Chain, StackSlot,
5570 PseudoSourceValue::getFixedStack(SSFI), 0,
5577 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
5578 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
5579 SelectionDAG &DAG) const {
5580 // This algorithm is not obvious. Here it is in C code, more or less:
5582 double uint64_to_double( uint32_t hi, uint32_t lo ) {
5583 static const __m128i exp = { 0x4330000045300000ULL, 0 };
5584 static const __m128d bias = { 0x1.0p84, 0x1.0p52 };
5586 // Copy ints to xmm registers.
5587 __m128i xh = _mm_cvtsi32_si128( hi );
5588 __m128i xl = _mm_cvtsi32_si128( lo );
5590 // Combine into low half of a single xmm register.
5591 __m128i x = _mm_unpacklo_epi32( xh, xl );
5595 // Merge in appropriate exponents to give the integer bits the right
5597 x = _mm_unpacklo_epi32( x, exp );
5599 // Subtract away the biases to deal with the IEEE-754 double precision
5601 d = _mm_sub_pd( (__m128d) x, bias );
5603 // All conversions up to here are exact. The correctly rounded result is
5604 // calculated using the current rounding mode using the following
5606 d = _mm_add_sd( d, _mm_unpackhi_pd( d, d ) );
5607 _mm_store_sd( &sd, d ); // Because we are returning doubles in XMM, this
5608 // store doesn't really need to be here (except
5609 // maybe to zero the other double)
5614 DebugLoc dl = Op.getDebugLoc();
5615 LLVMContext *Context = DAG.getContext();
5617 // Build some magic constants.
5618 std::vector<Constant*> CV0;
5619 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x45300000)));
5620 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x43300000)));
5621 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
5622 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
5623 Constant *C0 = ConstantVector::get(CV0);
5624 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
5626 std::vector<Constant*> CV1;
5628 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL))));
5630 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL))));
5631 Constant *C1 = ConstantVector::get(CV1);
5632 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
5634 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
5635 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
5637 DAG.getIntPtrConstant(1)));
5638 SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
5639 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
5641 DAG.getIntPtrConstant(0)));
5642 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, XR1, XR2);
5643 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
5644 PseudoSourceValue::getConstantPool(), 0,
5646 SDValue Unpck2 = getUnpackl(DAG, dl, MVT::v4i32, Unpck1, CLod0);
5647 SDValue XR2F = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Unpck2);
5648 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
5649 PseudoSourceValue::getConstantPool(), 0,
5651 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
5653 // Add the halves; easiest way is to swap them into another reg first.
5654 int ShufMask[2] = { 1, -1 };
5655 SDValue Shuf = DAG.getVectorShuffle(MVT::v2f64, dl, Sub,
5656 DAG.getUNDEF(MVT::v2f64), ShufMask);
5657 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuf, Sub);
5658 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Add,
5659 DAG.getIntPtrConstant(0));
5662 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
5663 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
5664 SelectionDAG &DAG) const {
5665 DebugLoc dl = Op.getDebugLoc();
5666 // FP constant to bias correct the final result.
5667 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
5670 // Load the 32-bit value into an XMM register.
5671 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
5672 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
5674 DAG.getIntPtrConstant(0)));
5676 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
5677 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Load),
5678 DAG.getIntPtrConstant(0));
5680 // Or the load with the bias.
5681 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
5682 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
5683 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5685 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
5686 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5687 MVT::v2f64, Bias)));
5688 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
5689 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Or),
5690 DAG.getIntPtrConstant(0));
5692 // Subtract the bias.
5693 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
5695 // Handle final rounding.
5696 EVT DestVT = Op.getValueType();
5698 if (DestVT.bitsLT(MVT::f64)) {
5699 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
5700 DAG.getIntPtrConstant(0));
5701 } else if (DestVT.bitsGT(MVT::f64)) {
5702 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
5705 // Handle final rounding.
5709 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
5710 SelectionDAG &DAG) const {
5711 SDValue N0 = Op.getOperand(0);
5712 DebugLoc dl = Op.getDebugLoc();
5714 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
5715 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
5716 // the optimization here.
5717 if (DAG.SignBitIsZero(N0))
5718 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
5720 EVT SrcVT = N0.getValueType();
5721 EVT DstVT = Op.getValueType();
5722 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
5723 return LowerUINT_TO_FP_i64(Op, DAG);
5724 else if (SrcVT == MVT::i32 && X86ScalarSSEf64)
5725 return LowerUINT_TO_FP_i32(Op, DAG);
5727 // Make a 64-bit buffer, and use it to build an FILD.
5728 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
5729 if (SrcVT == MVT::i32) {
5730 SDValue WordOff = DAG.getConstant(4, getPointerTy());
5731 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
5732 getPointerTy(), StackSlot, WordOff);
5733 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
5734 StackSlot, NULL, 0, false, false, 0);
5735 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
5736 OffsetSlot, NULL, 0, false, false, 0);
5737 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
5741 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
5742 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
5743 StackSlot, NULL, 0, false, false, 0);
5744 // For i64 source, we need to add the appropriate power of 2 if the input
5745 // was negative. This is the same as the optimization in
5746 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
5747 // we must be careful to do the computation in x87 extended precision, not
5748 // in SSE. (The generic code can't know it's OK to do this, or how to.)
5749 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
5750 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
5751 SDValue Fild = DAG.getNode(X86ISD::FILD, dl, Tys, Ops, 3);
5753 APInt FF(32, 0x5F800000ULL);
5755 // Check whether the sign bit is set.
5756 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
5757 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
5760 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
5761 SDValue FudgePtr = DAG.getConstantPool(
5762 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
5765 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
5766 SDValue Zero = DAG.getIntPtrConstant(0);
5767 SDValue Four = DAG.getIntPtrConstant(4);
5768 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
5770 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
5772 // Load the value out, extending it from f32 to f80.
5773 // FIXME: Avoid the extend by constructing the right constant pool?
5774 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
5775 FudgePtr, PseudoSourceValue::getConstantPool(),
5776 0, MVT::f32, false, false, 4);
5777 // Extend everything to 80 bits to force it to be done on x87.
5778 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
5779 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
5782 std::pair<SDValue,SDValue> X86TargetLowering::
5783 FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) const {
5784 DebugLoc dl = Op.getDebugLoc();
5786 EVT DstTy = Op.getValueType();
5789 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
5793 assert(DstTy.getSimpleVT() <= MVT::i64 &&
5794 DstTy.getSimpleVT() >= MVT::i16 &&
5795 "Unknown FP_TO_SINT to lower!");
5797 // These are really Legal.
5798 if (DstTy == MVT::i32 &&
5799 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
5800 return std::make_pair(SDValue(), SDValue());
5801 if (Subtarget->is64Bit() &&
5802 DstTy == MVT::i64 &&
5803 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
5804 return std::make_pair(SDValue(), SDValue());
5806 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
5808 MachineFunction &MF = DAG.getMachineFunction();
5809 unsigned MemSize = DstTy.getSizeInBits()/8;
5810 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
5811 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5814 switch (DstTy.getSimpleVT().SimpleTy) {
5815 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
5816 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
5817 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
5818 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
5821 SDValue Chain = DAG.getEntryNode();
5822 SDValue Value = Op.getOperand(0);
5823 if (isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) {
5824 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
5825 Chain = DAG.getStore(Chain, dl, Value, StackSlot,
5826 PseudoSourceValue::getFixedStack(SSFI), 0,
5828 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
5830 Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType())
5832 Value = DAG.getNode(X86ISD::FLD, dl, Tys, Ops, 3);
5833 Chain = Value.getValue(1);
5834 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
5835 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5838 // Build the FP_TO_INT*_IN_MEM
5839 SDValue Ops[] = { Chain, Value, StackSlot };
5840 SDValue FIST = DAG.getNode(Opc, dl, MVT::Other, Ops, 3);
5842 return std::make_pair(FIST, StackSlot);
5845 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
5846 SelectionDAG &DAG) const {
5847 if (Op.getValueType().isVector()) {
5848 if (Op.getValueType() == MVT::v2i32 &&
5849 Op.getOperand(0).getValueType() == MVT::v2f64) {
5855 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true);
5856 SDValue FIST = Vals.first, StackSlot = Vals.second;
5857 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
5858 if (FIST.getNode() == 0) return Op;
5861 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
5862 FIST, StackSlot, NULL, 0, false, false, 0);
5865 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
5866 SelectionDAG &DAG) const {
5867 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false);
5868 SDValue FIST = Vals.first, StackSlot = Vals.second;
5869 assert(FIST.getNode() && "Unexpected failure");
5872 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
5873 FIST, StackSlot, NULL, 0, false, false, 0);
5876 SDValue X86TargetLowering::LowerFABS(SDValue Op,
5877 SelectionDAG &DAG) const {
5878 LLVMContext *Context = DAG.getContext();
5879 DebugLoc dl = Op.getDebugLoc();
5880 EVT VT = Op.getValueType();
5883 EltVT = VT.getVectorElementType();
5884 std::vector<Constant*> CV;
5885 if (EltVT == MVT::f64) {
5886 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))));
5890 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))));
5896 Constant *C = ConstantVector::get(CV);
5897 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5898 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5899 PseudoSourceValue::getConstantPool(), 0,
5901 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
5904 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
5905 LLVMContext *Context = DAG.getContext();
5906 DebugLoc dl = Op.getDebugLoc();
5907 EVT VT = Op.getValueType();
5910 EltVT = VT.getVectorElementType();
5911 std::vector<Constant*> CV;
5912 if (EltVT == MVT::f64) {
5913 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)));
5917 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)));
5923 Constant *C = ConstantVector::get(CV);
5924 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5925 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5926 PseudoSourceValue::getConstantPool(), 0,
5928 if (VT.isVector()) {
5929 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
5930 DAG.getNode(ISD::XOR, dl, MVT::v2i64,
5931 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
5933 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, Mask)));
5935 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
5939 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
5940 LLVMContext *Context = DAG.getContext();
5941 SDValue Op0 = Op.getOperand(0);
5942 SDValue Op1 = Op.getOperand(1);
5943 DebugLoc dl = Op.getDebugLoc();
5944 EVT VT = Op.getValueType();
5945 EVT SrcVT = Op1.getValueType();
5947 // If second operand is smaller, extend it first.
5948 if (SrcVT.bitsLT(VT)) {
5949 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
5952 // And if it is bigger, shrink it first.
5953 if (SrcVT.bitsGT(VT)) {
5954 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
5958 // At this point the operands and the result should have the same
5959 // type, and that won't be f80 since that is not custom lowered.
5961 // First get the sign bit of second operand.
5962 std::vector<Constant*> CV;
5963 if (SrcVT == MVT::f64) {
5964 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))));
5965 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
5967 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))));
5968 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5969 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5970 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5972 Constant *C = ConstantVector::get(CV);
5973 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5974 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
5975 PseudoSourceValue::getConstantPool(), 0,
5977 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
5979 // Shift sign bit right or left if the two operands have different types.
5980 if (SrcVT.bitsGT(VT)) {
5981 // Op0 is MVT::f32, Op1 is MVT::f64.
5982 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
5983 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
5984 DAG.getConstant(32, MVT::i32));
5985 SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4f32, SignBit);
5986 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
5987 DAG.getIntPtrConstant(0));
5990 // Clear first operand sign bit.
5992 if (VT == MVT::f64) {
5993 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
5994 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
5996 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
5997 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5998 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5999 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
6001 C = ConstantVector::get(CV);
6002 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
6003 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
6004 PseudoSourceValue::getConstantPool(), 0,
6006 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
6008 // Or the value with the sign bit.
6009 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
6012 /// Emit nodes that will be selected as "test Op0,Op0", or something
6014 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
6015 SelectionDAG &DAG) const {
6016 DebugLoc dl = Op.getDebugLoc();
6018 // CF and OF aren't always set the way we want. Determine which
6019 // of these we need.
6020 bool NeedCF = false;
6021 bool NeedOF = false;
6024 case X86::COND_A: case X86::COND_AE:
6025 case X86::COND_B: case X86::COND_BE:
6028 case X86::COND_G: case X86::COND_GE:
6029 case X86::COND_L: case X86::COND_LE:
6030 case X86::COND_O: case X86::COND_NO:
6035 // See if we can use the EFLAGS value from the operand instead of
6036 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
6037 // we prove that the arithmetic won't overflow, we can't use OF or CF.
6038 if (Op.getResNo() != 0 || NeedOF || NeedCF)
6039 // Emit a CMP with 0, which is the TEST pattern.
6040 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
6041 DAG.getConstant(0, Op.getValueType()));
6043 unsigned Opcode = 0;
6044 unsigned NumOperands = 0;
6045 switch (Op.getNode()->getOpcode()) {
6047 // Due to an isel shortcoming, be conservative if this add is likely to be
6048 // selected as part of a load-modify-store instruction. When the root node
6049 // in a match is a store, isel doesn't know how to remap non-chain non-flag
6050 // uses of other nodes in the match, such as the ADD in this case. This
6051 // leads to the ADD being left around and reselected, with the result being
6052 // two adds in the output. Alas, even if none our users are stores, that
6053 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
6054 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
6055 // climbing the DAG back to the root, and it doesn't seem to be worth the
6057 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
6058 UE = Op.getNode()->use_end(); UI != UE; ++UI)
6059 if (UI->getOpcode() != ISD::CopyToReg && UI->getOpcode() != ISD::SETCC)
6062 if (ConstantSDNode *C =
6063 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
6064 // An add of one will be selected as an INC.
6065 if (C->getAPIntValue() == 1) {
6066 Opcode = X86ISD::INC;
6071 // An add of negative one (subtract of one) will be selected as a DEC.
6072 if (C->getAPIntValue().isAllOnesValue()) {
6073 Opcode = X86ISD::DEC;
6079 // Otherwise use a regular EFLAGS-setting add.
6080 Opcode = X86ISD::ADD;
6084 // If the primary and result isn't used, don't bother using X86ISD::AND,
6085 // because a TEST instruction will be better.
6086 bool NonFlagUse = false;
6087 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
6088 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
6090 unsigned UOpNo = UI.getOperandNo();
6091 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
6092 // Look pass truncate.
6093 UOpNo = User->use_begin().getOperandNo();
6094 User = *User->use_begin();
6097 if (User->getOpcode() != ISD::BRCOND &&
6098 User->getOpcode() != ISD::SETCC &&
6099 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) {
6112 // Due to the ISEL shortcoming noted above, be conservative if this op is
6113 // likely to be selected as part of a load-modify-store instruction.
6114 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
6115 UE = Op.getNode()->use_end(); UI != UE; ++UI)
6116 if (UI->getOpcode() == ISD::STORE)
6119 // Otherwise use a regular EFLAGS-setting instruction.
6120 switch (Op.getNode()->getOpcode()) {
6121 default: llvm_unreachable("unexpected operator!");
6122 case ISD::SUB: Opcode = X86ISD::SUB; break;
6123 case ISD::OR: Opcode = X86ISD::OR; break;
6124 case ISD::XOR: Opcode = X86ISD::XOR; break;
6125 case ISD::AND: Opcode = X86ISD::AND; break;
6137 return SDValue(Op.getNode(), 1);
6144 // Emit a CMP with 0, which is the TEST pattern.
6145 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
6146 DAG.getConstant(0, Op.getValueType()));
6148 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
6149 SmallVector<SDValue, 4> Ops;
6150 for (unsigned i = 0; i != NumOperands; ++i)
6151 Ops.push_back(Op.getOperand(i));
6153 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
6154 DAG.ReplaceAllUsesWith(Op, New);
6155 return SDValue(New.getNode(), 1);
6158 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
6160 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
6161 SelectionDAG &DAG) const {
6162 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
6163 if (C->getAPIntValue() == 0)
6164 return EmitTest(Op0, X86CC, DAG);
6166 DebugLoc dl = Op0.getDebugLoc();
6167 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
6170 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
6171 /// if it's possible.
6172 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
6173 DebugLoc dl, SelectionDAG &DAG) const {
6174 SDValue Op0 = And.getOperand(0);
6175 SDValue Op1 = And.getOperand(1);
6176 if (Op0.getOpcode() == ISD::TRUNCATE)
6177 Op0 = Op0.getOperand(0);
6178 if (Op1.getOpcode() == ISD::TRUNCATE)
6179 Op1 = Op1.getOperand(0);
6182 if (Op1.getOpcode() == ISD::SHL)
6183 std::swap(Op0, Op1);
6184 if (Op0.getOpcode() == ISD::SHL) {
6185 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
6186 if (And00C->getZExtValue() == 1) {
6187 // If we looked past a truncate, check that it's only truncating away
6189 unsigned BitWidth = Op0.getValueSizeInBits();
6190 unsigned AndBitWidth = And.getValueSizeInBits();
6191 if (BitWidth > AndBitWidth) {
6192 APInt Mask = APInt::getAllOnesValue(BitWidth), Zeros, Ones;
6193 DAG.ComputeMaskedBits(Op0, Mask, Zeros, Ones);
6194 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
6198 RHS = Op0.getOperand(1);
6200 } else if (Op1.getOpcode() == ISD::Constant) {
6201 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
6202 SDValue AndLHS = Op0;
6203 if (AndRHS->getZExtValue() == 1 && AndLHS.getOpcode() == ISD::SRL) {
6204 LHS = AndLHS.getOperand(0);
6205 RHS = AndLHS.getOperand(1);
6209 if (LHS.getNode()) {
6210 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
6211 // instruction. Since the shift amount is in-range-or-undefined, we know
6212 // that doing a bittest on the i32 value is ok. We extend to i32 because
6213 // the encoding for the i16 version is larger than the i32 version.
6214 // Also promote i16 to i32 for performance / code size reason.
6215 if (LHS.getValueType() == MVT::i8 ||
6216 LHS.getValueType() == MVT::i16)
6217 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
6219 // If the operand types disagree, extend the shift amount to match. Since
6220 // BT ignores high bits (like shifts) we can use anyextend.
6221 if (LHS.getValueType() != RHS.getValueType())
6222 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
6224 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
6225 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
6226 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
6227 DAG.getConstant(Cond, MVT::i8), BT);
6233 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
6234 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
6235 SDValue Op0 = Op.getOperand(0);
6236 SDValue Op1 = Op.getOperand(1);
6237 DebugLoc dl = Op.getDebugLoc();
6238 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
6240 // Optimize to BT if possible.
6241 // Lower (X & (1 << N)) == 0 to BT(X, N).
6242 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
6243 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
6244 if (Op0.getOpcode() == ISD::AND &&
6246 Op1.getOpcode() == ISD::Constant &&
6247 cast<ConstantSDNode>(Op1)->isNullValue() &&
6248 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
6249 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
6250 if (NewSetCC.getNode())
6254 // Look for "(setcc) == / != 1" to avoid unncessary setcc.
6255 if (Op0.getOpcode() == X86ISD::SETCC &&
6256 Op1.getOpcode() == ISD::Constant &&
6257 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
6258 cast<ConstantSDNode>(Op1)->isNullValue()) &&
6259 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
6260 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
6261 bool Invert = (CC == ISD::SETNE) ^
6262 cast<ConstantSDNode>(Op1)->isNullValue();
6264 CCode = X86::GetOppositeBranchCondition(CCode);
6265 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
6266 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
6269 bool isFP = Op1.getValueType().isFloatingPoint();
6270 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
6271 if (X86CC == X86::COND_INVALID)
6274 SDValue Cond = EmitCmp(Op0, Op1, X86CC, DAG);
6276 // Use sbb x, x to materialize carry bit into a GPR.
6277 if (X86CC == X86::COND_B)
6278 return DAG.getNode(ISD::AND, dl, MVT::i8,
6279 DAG.getNode(X86ISD::SETCC_CARRY, dl, MVT::i8,
6280 DAG.getConstant(X86CC, MVT::i8), Cond),
6281 DAG.getConstant(1, MVT::i8));
6283 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
6284 DAG.getConstant(X86CC, MVT::i8), Cond);
6287 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const {
6289 SDValue Op0 = Op.getOperand(0);
6290 SDValue Op1 = Op.getOperand(1);
6291 SDValue CC = Op.getOperand(2);
6292 EVT VT = Op.getValueType();
6293 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
6294 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
6295 DebugLoc dl = Op.getDebugLoc();
6299 EVT VT0 = Op0.getValueType();
6300 assert(VT0 == MVT::v4f32 || VT0 == MVT::v2f64);
6301 unsigned Opc = VT0 == MVT::v4f32 ? X86ISD::CMPPS : X86ISD::CMPPD;
6304 switch (SetCCOpcode) {
6307 case ISD::SETEQ: SSECC = 0; break;
6309 case ISD::SETGT: Swap = true; // Fallthrough
6311 case ISD::SETOLT: SSECC = 1; break;
6313 case ISD::SETGE: Swap = true; // Fallthrough
6315 case ISD::SETOLE: SSECC = 2; break;
6316 case ISD::SETUO: SSECC = 3; break;
6318 case ISD::SETNE: SSECC = 4; break;
6319 case ISD::SETULE: Swap = true;
6320 case ISD::SETUGE: SSECC = 5; break;
6321 case ISD::SETULT: Swap = true;
6322 case ISD::SETUGT: SSECC = 6; break;
6323 case ISD::SETO: SSECC = 7; break;
6326 std::swap(Op0, Op1);
6328 // In the two special cases we can't handle, emit two comparisons.
6330 if (SetCCOpcode == ISD::SETUEQ) {
6332 UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8));
6333 EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8));
6334 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
6336 else if (SetCCOpcode == ISD::SETONE) {
6338 ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8));
6339 NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8));
6340 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
6342 llvm_unreachable("Illegal FP comparison");
6344 // Handle all other FP comparisons here.
6345 return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8));
6348 // We are handling one of the integer comparisons here. Since SSE only has
6349 // GT and EQ comparisons for integer, swapping operands and multiple
6350 // operations may be required for some comparisons.
6351 unsigned Opc = 0, EQOpc = 0, GTOpc = 0;
6352 bool Swap = false, Invert = false, FlipSigns = false;
6354 switch (VT.getSimpleVT().SimpleTy) {
6357 case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break;
6359 case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break;
6361 case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break;
6362 case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break;
6365 switch (SetCCOpcode) {
6367 case ISD::SETNE: Invert = true;
6368 case ISD::SETEQ: Opc = EQOpc; break;
6369 case ISD::SETLT: Swap = true;
6370 case ISD::SETGT: Opc = GTOpc; break;
6371 case ISD::SETGE: Swap = true;
6372 case ISD::SETLE: Opc = GTOpc; Invert = true; break;
6373 case ISD::SETULT: Swap = true;
6374 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break;
6375 case ISD::SETUGE: Swap = true;
6376 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break;
6379 std::swap(Op0, Op1);
6381 // Since SSE has no unsigned integer comparisons, we need to flip the sign
6382 // bits of the inputs before performing those operations.
6384 EVT EltVT = VT.getVectorElementType();
6385 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
6387 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
6388 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
6390 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
6391 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
6394 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
6396 // If the logical-not of the result is required, perform that now.
6398 Result = DAG.getNOT(dl, Result, VT);
6403 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
6404 static bool isX86LogicalCmp(SDValue Op) {
6405 unsigned Opc = Op.getNode()->getOpcode();
6406 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI)
6408 if (Op.getResNo() == 1 &&
6409 (Opc == X86ISD::ADD ||
6410 Opc == X86ISD::SUB ||
6411 Opc == X86ISD::SMUL ||
6412 Opc == X86ISD::UMUL ||
6413 Opc == X86ISD::INC ||
6414 Opc == X86ISD::DEC ||
6415 Opc == X86ISD::OR ||
6416 Opc == X86ISD::XOR ||
6417 Opc == X86ISD::AND))
6423 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
6424 bool addTest = true;
6425 SDValue Cond = Op.getOperand(0);
6426 DebugLoc dl = Op.getDebugLoc();
6429 if (Cond.getOpcode() == ISD::SETCC) {
6430 SDValue NewCond = LowerSETCC(Cond, DAG);
6431 if (NewCond.getNode())
6435 // (select (x == 0), -1, 0) -> (sign_bit (x - 1))
6436 SDValue Op1 = Op.getOperand(1);
6437 SDValue Op2 = Op.getOperand(2);
6438 if (Cond.getOpcode() == X86ISD::SETCC &&
6439 cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue() == X86::COND_E) {
6440 SDValue Cmp = Cond.getOperand(1);
6441 if (Cmp.getOpcode() == X86ISD::CMP) {
6442 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op1);
6443 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
6444 ConstantSDNode *RHSC =
6445 dyn_cast<ConstantSDNode>(Cmp.getOperand(1).getNode());
6446 if (N1C && N1C->isAllOnesValue() &&
6447 N2C && N2C->isNullValue() &&
6448 RHSC && RHSC->isNullValue()) {
6449 SDValue CmpOp0 = Cmp.getOperand(0);
6450 Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
6451 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
6452 return DAG.getNode(X86ISD::SETCC_CARRY, dl, Op.getValueType(),
6453 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
6458 // Look pass (and (setcc_carry (cmp ...)), 1).
6459 if (Cond.getOpcode() == ISD::AND &&
6460 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
6461 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
6462 if (C && C->getAPIntValue() == 1)
6463 Cond = Cond.getOperand(0);
6466 // If condition flag is set by a X86ISD::CMP, then use it as the condition
6467 // setting operand in place of the X86ISD::SETCC.
6468 if (Cond.getOpcode() == X86ISD::SETCC ||
6469 Cond.getOpcode() == X86ISD::SETCC_CARRY) {
6470 CC = Cond.getOperand(0);
6472 SDValue Cmp = Cond.getOperand(1);
6473 unsigned Opc = Cmp.getOpcode();
6474 EVT VT = Op.getValueType();
6476 bool IllegalFPCMov = false;
6477 if (VT.isFloatingPoint() && !VT.isVector() &&
6478 !isScalarFPTypeInSSEReg(VT)) // FPStack?
6479 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
6481 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
6482 Opc == X86ISD::BT) { // FIXME
6489 // Look pass the truncate.
6490 if (Cond.getOpcode() == ISD::TRUNCATE)
6491 Cond = Cond.getOperand(0);
6493 // We know the result of AND is compared against zero. Try to match
6495 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
6496 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
6497 if (NewSetCC.getNode()) {
6498 CC = NewSetCC.getOperand(0);
6499 Cond = NewSetCC.getOperand(1);
6506 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
6507 Cond = EmitTest(Cond, X86::COND_NE, DAG);
6510 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
6511 // condition is true.
6512 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
6513 SDValue Ops[] = { Op2, Op1, CC, Cond };
6514 return DAG.getNode(X86ISD::CMOV, dl, VTs, Ops, array_lengthof(Ops));
6517 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
6518 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
6519 // from the AND / OR.
6520 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
6521 Opc = Op.getOpcode();
6522 if (Opc != ISD::OR && Opc != ISD::AND)
6524 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
6525 Op.getOperand(0).hasOneUse() &&
6526 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
6527 Op.getOperand(1).hasOneUse());
6530 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
6531 // 1 and that the SETCC node has a single use.
6532 static bool isXor1OfSetCC(SDValue Op) {
6533 if (Op.getOpcode() != ISD::XOR)
6535 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
6536 if (N1C && N1C->getAPIntValue() == 1) {
6537 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
6538 Op.getOperand(0).hasOneUse();
6543 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
6544 bool addTest = true;
6545 SDValue Chain = Op.getOperand(0);
6546 SDValue Cond = Op.getOperand(1);
6547 SDValue Dest = Op.getOperand(2);
6548 DebugLoc dl = Op.getDebugLoc();
6551 if (Cond.getOpcode() == ISD::SETCC) {
6552 SDValue NewCond = LowerSETCC(Cond, DAG);
6553 if (NewCond.getNode())
6557 // FIXME: LowerXALUO doesn't handle these!!
6558 else if (Cond.getOpcode() == X86ISD::ADD ||
6559 Cond.getOpcode() == X86ISD::SUB ||
6560 Cond.getOpcode() == X86ISD::SMUL ||
6561 Cond.getOpcode() == X86ISD::UMUL)
6562 Cond = LowerXALUO(Cond, DAG);
6565 // Look pass (and (setcc_carry (cmp ...)), 1).
6566 if (Cond.getOpcode() == ISD::AND &&
6567 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
6568 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
6569 if (C && C->getAPIntValue() == 1)
6570 Cond = Cond.getOperand(0);
6573 // If condition flag is set by a X86ISD::CMP, then use it as the condition
6574 // setting operand in place of the X86ISD::SETCC.
6575 if (Cond.getOpcode() == X86ISD::SETCC ||
6576 Cond.getOpcode() == X86ISD::SETCC_CARRY) {
6577 CC = Cond.getOperand(0);
6579 SDValue Cmp = Cond.getOperand(1);
6580 unsigned Opc = Cmp.getOpcode();
6581 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
6582 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
6586 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
6590 // These can only come from an arithmetic instruction with overflow,
6591 // e.g. SADDO, UADDO.
6592 Cond = Cond.getNode()->getOperand(1);
6599 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
6600 SDValue Cmp = Cond.getOperand(0).getOperand(1);
6601 if (CondOpc == ISD::OR) {
6602 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
6603 // two branches instead of an explicit OR instruction with a
6605 if (Cmp == Cond.getOperand(1).getOperand(1) &&
6606 isX86LogicalCmp(Cmp)) {
6607 CC = Cond.getOperand(0).getOperand(0);
6608 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
6609 Chain, Dest, CC, Cmp);
6610 CC = Cond.getOperand(1).getOperand(0);
6614 } else { // ISD::AND
6615 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
6616 // two branches instead of an explicit AND instruction with a
6617 // separate test. However, we only do this if this block doesn't
6618 // have a fall-through edge, because this requires an explicit
6619 // jmp when the condition is false.
6620 if (Cmp == Cond.getOperand(1).getOperand(1) &&
6621 isX86LogicalCmp(Cmp) &&
6622 Op.getNode()->hasOneUse()) {
6623 X86::CondCode CCode =
6624 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
6625 CCode = X86::GetOppositeBranchCondition(CCode);
6626 CC = DAG.getConstant(CCode, MVT::i8);
6627 SDNode *User = *Op.getNode()->use_begin();
6628 // Look for an unconditional branch following this conditional branch.
6629 // We need this because we need to reverse the successors in order
6630 // to implement FCMP_OEQ.
6631 if (User->getOpcode() == ISD::BR) {
6632 SDValue FalseBB = User->getOperand(1);
6634 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
6635 assert(NewBR == User);
6639 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
6640 Chain, Dest, CC, Cmp);
6641 X86::CondCode CCode =
6642 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
6643 CCode = X86::GetOppositeBranchCondition(CCode);
6644 CC = DAG.getConstant(CCode, MVT::i8);
6650 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
6651 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
6652 // It should be transformed during dag combiner except when the condition
6653 // is set by a arithmetics with overflow node.
6654 X86::CondCode CCode =
6655 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
6656 CCode = X86::GetOppositeBranchCondition(CCode);
6657 CC = DAG.getConstant(CCode, MVT::i8);
6658 Cond = Cond.getOperand(0).getOperand(1);
6664 // Look pass the truncate.
6665 if (Cond.getOpcode() == ISD::TRUNCATE)
6666 Cond = Cond.getOperand(0);
6668 // We know the result of AND is compared against zero. Try to match
6670 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
6671 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
6672 if (NewSetCC.getNode()) {
6673 CC = NewSetCC.getOperand(0);
6674 Cond = NewSetCC.getOperand(1);
6681 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
6682 Cond = EmitTest(Cond, X86::COND_NE, DAG);
6684 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
6685 Chain, Dest, CC, Cond);
6689 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
6690 // Calls to _alloca is needed to probe the stack when allocating more than 4k
6691 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
6692 // that the guard pages used by the OS virtual memory manager are allocated in
6693 // correct sequence.
6695 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
6696 SelectionDAG &DAG) const {
6697 assert(Subtarget->isTargetCygMing() &&
6698 "This should be used only on Cygwin/Mingw targets");
6699 DebugLoc dl = Op.getDebugLoc();
6702 SDValue Chain = Op.getOperand(0);
6703 SDValue Size = Op.getOperand(1);
6704 // FIXME: Ensure alignment here
6708 EVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32;
6710 Chain = DAG.getCopyToReg(Chain, dl, X86::EAX, Size, Flag);
6711 Flag = Chain.getValue(1);
6713 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
6715 Chain = DAG.getNode(X86ISD::MINGW_ALLOCA, dl, NodeTys, Chain, Flag);
6716 Flag = Chain.getValue(1);
6718 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
6720 SDValue Ops1[2] = { Chain.getValue(0), Chain };
6721 return DAG.getMergeValues(Ops1, 2, dl);
6724 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
6725 MachineFunction &MF = DAG.getMachineFunction();
6726 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
6728 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
6729 DebugLoc dl = Op.getDebugLoc();
6731 if (!Subtarget->is64Bit()) {
6732 // vastart just stores the address of the VarArgsFrameIndex slot into the
6733 // memory location argument.
6734 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
6736 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0,
6741 // gp_offset (0 - 6 * 8)
6742 // fp_offset (48 - 48 + 8 * 16)
6743 // overflow_arg_area (point to parameters coming in memory).
6745 SmallVector<SDValue, 8> MemOps;
6746 SDValue FIN = Op.getOperand(1);
6748 SDValue Store = DAG.getStore(Op.getOperand(0), dl,
6749 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
6751 FIN, SV, 0, false, false, 0);
6752 MemOps.push_back(Store);
6755 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6756 FIN, DAG.getIntPtrConstant(4));
6757 Store = DAG.getStore(Op.getOperand(0), dl,
6758 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
6760 FIN, SV, 0, false, false, 0);
6761 MemOps.push_back(Store);
6763 // Store ptr to overflow_arg_area
6764 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6765 FIN, DAG.getIntPtrConstant(4));
6766 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
6768 Store = DAG.getStore(Op.getOperand(0), dl, OVFIN, FIN, SV, 0,
6770 MemOps.push_back(Store);
6772 // Store ptr to reg_save_area.
6773 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6774 FIN, DAG.getIntPtrConstant(8));
6775 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
6777 Store = DAG.getStore(Op.getOperand(0), dl, RSFIN, FIN, SV, 0,
6779 MemOps.push_back(Store);
6780 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
6781 &MemOps[0], MemOps.size());
6784 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
6785 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
6786 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_arg!");
6788 report_fatal_error("VAArgInst is not yet implemented for x86-64!");
6792 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
6793 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
6794 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
6795 SDValue Chain = Op.getOperand(0);
6796 SDValue DstPtr = Op.getOperand(1);
6797 SDValue SrcPtr = Op.getOperand(2);
6798 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
6799 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
6800 DebugLoc dl = Op.getDebugLoc();
6802 return DAG.getMemcpy(Chain, dl, DstPtr, SrcPtr,
6803 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
6804 false, DstSV, 0, SrcSV, 0);
6808 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const {
6809 DebugLoc dl = Op.getDebugLoc();
6810 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6812 default: return SDValue(); // Don't custom lower most intrinsics.
6813 // Comparison intrinsics.
6814 case Intrinsic::x86_sse_comieq_ss:
6815 case Intrinsic::x86_sse_comilt_ss:
6816 case Intrinsic::x86_sse_comile_ss:
6817 case Intrinsic::x86_sse_comigt_ss:
6818 case Intrinsic::x86_sse_comige_ss:
6819 case Intrinsic::x86_sse_comineq_ss:
6820 case Intrinsic::x86_sse_ucomieq_ss:
6821 case Intrinsic::x86_sse_ucomilt_ss:
6822 case Intrinsic::x86_sse_ucomile_ss:
6823 case Intrinsic::x86_sse_ucomigt_ss:
6824 case Intrinsic::x86_sse_ucomige_ss:
6825 case Intrinsic::x86_sse_ucomineq_ss:
6826 case Intrinsic::x86_sse2_comieq_sd:
6827 case Intrinsic::x86_sse2_comilt_sd:
6828 case Intrinsic::x86_sse2_comile_sd:
6829 case Intrinsic::x86_sse2_comigt_sd:
6830 case Intrinsic::x86_sse2_comige_sd:
6831 case Intrinsic::x86_sse2_comineq_sd:
6832 case Intrinsic::x86_sse2_ucomieq_sd:
6833 case Intrinsic::x86_sse2_ucomilt_sd:
6834 case Intrinsic::x86_sse2_ucomile_sd:
6835 case Intrinsic::x86_sse2_ucomigt_sd:
6836 case Intrinsic::x86_sse2_ucomige_sd:
6837 case Intrinsic::x86_sse2_ucomineq_sd: {
6839 ISD::CondCode CC = ISD::SETCC_INVALID;
6842 case Intrinsic::x86_sse_comieq_ss:
6843 case Intrinsic::x86_sse2_comieq_sd:
6847 case Intrinsic::x86_sse_comilt_ss:
6848 case Intrinsic::x86_sse2_comilt_sd:
6852 case Intrinsic::x86_sse_comile_ss:
6853 case Intrinsic::x86_sse2_comile_sd:
6857 case Intrinsic::x86_sse_comigt_ss:
6858 case Intrinsic::x86_sse2_comigt_sd:
6862 case Intrinsic::x86_sse_comige_ss:
6863 case Intrinsic::x86_sse2_comige_sd:
6867 case Intrinsic::x86_sse_comineq_ss:
6868 case Intrinsic::x86_sse2_comineq_sd:
6872 case Intrinsic::x86_sse_ucomieq_ss:
6873 case Intrinsic::x86_sse2_ucomieq_sd:
6874 Opc = X86ISD::UCOMI;
6877 case Intrinsic::x86_sse_ucomilt_ss:
6878 case Intrinsic::x86_sse2_ucomilt_sd:
6879 Opc = X86ISD::UCOMI;
6882 case Intrinsic::x86_sse_ucomile_ss:
6883 case Intrinsic::x86_sse2_ucomile_sd:
6884 Opc = X86ISD::UCOMI;
6887 case Intrinsic::x86_sse_ucomigt_ss:
6888 case Intrinsic::x86_sse2_ucomigt_sd:
6889 Opc = X86ISD::UCOMI;
6892 case Intrinsic::x86_sse_ucomige_ss:
6893 case Intrinsic::x86_sse2_ucomige_sd:
6894 Opc = X86ISD::UCOMI;
6897 case Intrinsic::x86_sse_ucomineq_ss:
6898 case Intrinsic::x86_sse2_ucomineq_sd:
6899 Opc = X86ISD::UCOMI;
6904 SDValue LHS = Op.getOperand(1);
6905 SDValue RHS = Op.getOperand(2);
6906 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
6907 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
6908 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
6909 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
6910 DAG.getConstant(X86CC, MVT::i8), Cond);
6911 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
6913 // ptest intrinsics. The intrinsic these come from are designed to return
6914 // an integer value, not just an instruction so lower it to the ptest
6915 // pattern and a setcc for the result.
6916 case Intrinsic::x86_sse41_ptestz:
6917 case Intrinsic::x86_sse41_ptestc:
6918 case Intrinsic::x86_sse41_ptestnzc:{
6921 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
6922 case Intrinsic::x86_sse41_ptestz:
6924 X86CC = X86::COND_E;
6926 case Intrinsic::x86_sse41_ptestc:
6928 X86CC = X86::COND_B;
6930 case Intrinsic::x86_sse41_ptestnzc:
6932 X86CC = X86::COND_A;
6936 SDValue LHS = Op.getOperand(1);
6937 SDValue RHS = Op.getOperand(2);
6938 SDValue Test = DAG.getNode(X86ISD::PTEST, dl, MVT::i32, LHS, RHS);
6939 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
6940 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
6941 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
6944 // Fix vector shift instructions where the last operand is a non-immediate
6946 case Intrinsic::x86_sse2_pslli_w:
6947 case Intrinsic::x86_sse2_pslli_d:
6948 case Intrinsic::x86_sse2_pslli_q:
6949 case Intrinsic::x86_sse2_psrli_w:
6950 case Intrinsic::x86_sse2_psrli_d:
6951 case Intrinsic::x86_sse2_psrli_q:
6952 case Intrinsic::x86_sse2_psrai_w:
6953 case Intrinsic::x86_sse2_psrai_d:
6954 case Intrinsic::x86_mmx_pslli_w:
6955 case Intrinsic::x86_mmx_pslli_d:
6956 case Intrinsic::x86_mmx_pslli_q:
6957 case Intrinsic::x86_mmx_psrli_w:
6958 case Intrinsic::x86_mmx_psrli_d:
6959 case Intrinsic::x86_mmx_psrli_q:
6960 case Intrinsic::x86_mmx_psrai_w:
6961 case Intrinsic::x86_mmx_psrai_d: {
6962 SDValue ShAmt = Op.getOperand(2);
6963 if (isa<ConstantSDNode>(ShAmt))
6966 unsigned NewIntNo = 0;
6967 EVT ShAmtVT = MVT::v4i32;
6969 case Intrinsic::x86_sse2_pslli_w:
6970 NewIntNo = Intrinsic::x86_sse2_psll_w;
6972 case Intrinsic::x86_sse2_pslli_d:
6973 NewIntNo = Intrinsic::x86_sse2_psll_d;
6975 case Intrinsic::x86_sse2_pslli_q:
6976 NewIntNo = Intrinsic::x86_sse2_psll_q;
6978 case Intrinsic::x86_sse2_psrli_w:
6979 NewIntNo = Intrinsic::x86_sse2_psrl_w;
6981 case Intrinsic::x86_sse2_psrli_d:
6982 NewIntNo = Intrinsic::x86_sse2_psrl_d;
6984 case Intrinsic::x86_sse2_psrli_q:
6985 NewIntNo = Intrinsic::x86_sse2_psrl_q;
6987 case Intrinsic::x86_sse2_psrai_w:
6988 NewIntNo = Intrinsic::x86_sse2_psra_w;
6990 case Intrinsic::x86_sse2_psrai_d:
6991 NewIntNo = Intrinsic::x86_sse2_psra_d;
6994 ShAmtVT = MVT::v2i32;
6996 case Intrinsic::x86_mmx_pslli_w:
6997 NewIntNo = Intrinsic::x86_mmx_psll_w;
6999 case Intrinsic::x86_mmx_pslli_d:
7000 NewIntNo = Intrinsic::x86_mmx_psll_d;
7002 case Intrinsic::x86_mmx_pslli_q:
7003 NewIntNo = Intrinsic::x86_mmx_psll_q;
7005 case Intrinsic::x86_mmx_psrli_w:
7006 NewIntNo = Intrinsic::x86_mmx_psrl_w;
7008 case Intrinsic::x86_mmx_psrli_d:
7009 NewIntNo = Intrinsic::x86_mmx_psrl_d;
7011 case Intrinsic::x86_mmx_psrli_q:
7012 NewIntNo = Intrinsic::x86_mmx_psrl_q;
7014 case Intrinsic::x86_mmx_psrai_w:
7015 NewIntNo = Intrinsic::x86_mmx_psra_w;
7017 case Intrinsic::x86_mmx_psrai_d:
7018 NewIntNo = Intrinsic::x86_mmx_psra_d;
7020 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
7026 // The vector shift intrinsics with scalars uses 32b shift amounts but
7027 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
7031 ShOps[1] = DAG.getConstant(0, MVT::i32);
7032 if (ShAmtVT == MVT::v4i32) {
7033 ShOps[2] = DAG.getUNDEF(MVT::i32);
7034 ShOps[3] = DAG.getUNDEF(MVT::i32);
7035 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 4);
7037 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2);
7040 EVT VT = Op.getValueType();
7041 ShAmt = DAG.getNode(ISD::BIT_CONVERT, dl, VT, ShAmt);
7042 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7043 DAG.getConstant(NewIntNo, MVT::i32),
7044 Op.getOperand(1), ShAmt);
7049 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
7050 SelectionDAG &DAG) const {
7051 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7052 MFI->setReturnAddressIsTaken(true);
7054 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
7055 DebugLoc dl = Op.getDebugLoc();
7058 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
7060 DAG.getConstant(TD->getPointerSize(),
7061 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
7062 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
7063 DAG.getNode(ISD::ADD, dl, getPointerTy(),
7065 NULL, 0, false, false, 0);
7068 // Just load the return address.
7069 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
7070 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
7071 RetAddrFI, NULL, 0, false, false, 0);
7074 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
7075 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7076 MFI->setFrameAddressIsTaken(true);
7078 EVT VT = Op.getValueType();
7079 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
7080 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
7081 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
7082 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
7084 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0,
7089 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
7090 SelectionDAG &DAG) const {
7091 return DAG.getIntPtrConstant(2*TD->getPointerSize());
7094 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
7095 MachineFunction &MF = DAG.getMachineFunction();
7096 SDValue Chain = Op.getOperand(0);
7097 SDValue Offset = Op.getOperand(1);
7098 SDValue Handler = Op.getOperand(2);
7099 DebugLoc dl = Op.getDebugLoc();
7101 SDValue Frame = DAG.getRegister(Subtarget->is64Bit() ? X86::RBP : X86::EBP,
7103 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
7105 SDValue StoreAddr = DAG.getNode(ISD::SUB, dl, getPointerTy(), Frame,
7106 DAG.getIntPtrConstant(-TD->getPointerSize()));
7107 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
7108 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, NULL, 0, false, false, 0);
7109 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
7110 MF.getRegInfo().addLiveOut(StoreAddrReg);
7112 return DAG.getNode(X86ISD::EH_RETURN, dl,
7114 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
7117 SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op,
7118 SelectionDAG &DAG) const {
7119 SDValue Root = Op.getOperand(0);
7120 SDValue Trmp = Op.getOperand(1); // trampoline
7121 SDValue FPtr = Op.getOperand(2); // nested function
7122 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
7123 DebugLoc dl = Op.getDebugLoc();
7125 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
7127 if (Subtarget->is64Bit()) {
7128 SDValue OutChains[6];
7130 // Large code-model.
7131 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
7132 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
7134 const unsigned char N86R10 = RegInfo->getX86RegNum(X86::R10);
7135 const unsigned char N86R11 = RegInfo->getX86RegNum(X86::R11);
7137 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
7139 // Load the pointer to the nested function into R11.
7140 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
7141 SDValue Addr = Trmp;
7142 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
7143 Addr, TrmpAddr, 0, false, false, 0);
7145 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
7146 DAG.getConstant(2, MVT::i64));
7147 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr, TrmpAddr, 2,
7150 // Load the 'nest' parameter value into R10.
7151 // R10 is specified in X86CallingConv.td
7152 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
7153 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
7154 DAG.getConstant(10, MVT::i64));
7155 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
7156 Addr, TrmpAddr, 10, false, false, 0);
7158 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
7159 DAG.getConstant(12, MVT::i64));
7160 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 12,
7163 // Jump to the nested function.
7164 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
7165 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
7166 DAG.getConstant(20, MVT::i64));
7167 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
7168 Addr, TrmpAddr, 20, false, false, 0);
7170 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
7171 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
7172 DAG.getConstant(22, MVT::i64));
7173 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
7174 TrmpAddr, 22, false, false, 0);
7177 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6) };
7178 return DAG.getMergeValues(Ops, 2, dl);
7180 const Function *Func =
7181 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
7182 CallingConv::ID CC = Func->getCallingConv();
7187 llvm_unreachable("Unsupported calling convention");
7188 case CallingConv::C:
7189 case CallingConv::X86_StdCall: {
7190 // Pass 'nest' parameter in ECX.
7191 // Must be kept in sync with X86CallingConv.td
7194 // Check that ECX wasn't needed by an 'inreg' parameter.
7195 const FunctionType *FTy = Func->getFunctionType();
7196 const AttrListPtr &Attrs = Func->getAttributes();
7198 if (!Attrs.isEmpty() && !Func->isVarArg()) {
7199 unsigned InRegCount = 0;
7202 for (FunctionType::param_iterator I = FTy->param_begin(),
7203 E = FTy->param_end(); I != E; ++I, ++Idx)
7204 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
7205 // FIXME: should only count parameters that are lowered to integers.
7206 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
7208 if (InRegCount > 2) {
7209 report_fatal_error("Nest register in use - reduce number of inreg parameters!");
7214 case CallingConv::X86_FastCall:
7215 case CallingConv::X86_ThisCall:
7216 case CallingConv::Fast:
7217 // Pass 'nest' parameter in EAX.
7218 // Must be kept in sync with X86CallingConv.td
7223 SDValue OutChains[4];
7226 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
7227 DAG.getConstant(10, MVT::i32));
7228 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
7230 // This is storing the opcode for MOV32ri.
7231 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
7232 const unsigned char N86Reg = RegInfo->getX86RegNum(NestReg);
7233 OutChains[0] = DAG.getStore(Root, dl,
7234 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
7235 Trmp, TrmpAddr, 0, false, false, 0);
7237 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
7238 DAG.getConstant(1, MVT::i32));
7239 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 1,
7242 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
7243 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
7244 DAG.getConstant(5, MVT::i32));
7245 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
7246 TrmpAddr, 5, false, false, 1);
7248 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
7249 DAG.getConstant(6, MVT::i32));
7250 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr, TrmpAddr, 6,
7254 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4) };
7255 return DAG.getMergeValues(Ops, 2, dl);
7259 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
7260 SelectionDAG &DAG) const {
7262 The rounding mode is in bits 11:10 of FPSR, and has the following
7269 FLT_ROUNDS, on the other hand, expects the following:
7276 To perform the conversion, we do:
7277 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
7280 MachineFunction &MF = DAG.getMachineFunction();
7281 const TargetMachine &TM = MF.getTarget();
7282 const TargetFrameInfo &TFI = *TM.getFrameInfo();
7283 unsigned StackAlignment = TFI.getStackAlignment();
7284 EVT VT = Op.getValueType();
7285 DebugLoc dl = Op.getDebugLoc();
7287 // Save FP Control Word to stack slot
7288 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
7289 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7291 SDValue Chain = DAG.getNode(X86ISD::FNSTCW16m, dl, MVT::Other,
7292 DAG.getEntryNode(), StackSlot);
7294 // Load FP Control Word from stack slot
7295 SDValue CWD = DAG.getLoad(MVT::i16, dl, Chain, StackSlot, NULL, 0,
7298 // Transform as necessary
7300 DAG.getNode(ISD::SRL, dl, MVT::i16,
7301 DAG.getNode(ISD::AND, dl, MVT::i16,
7302 CWD, DAG.getConstant(0x800, MVT::i16)),
7303 DAG.getConstant(11, MVT::i8));
7305 DAG.getNode(ISD::SRL, dl, MVT::i16,
7306 DAG.getNode(ISD::AND, dl, MVT::i16,
7307 CWD, DAG.getConstant(0x400, MVT::i16)),
7308 DAG.getConstant(9, MVT::i8));
7311 DAG.getNode(ISD::AND, dl, MVT::i16,
7312 DAG.getNode(ISD::ADD, dl, MVT::i16,
7313 DAG.getNode(ISD::OR, dl, MVT::i16, CWD1, CWD2),
7314 DAG.getConstant(1, MVT::i16)),
7315 DAG.getConstant(3, MVT::i16));
7318 return DAG.getNode((VT.getSizeInBits() < 16 ?
7319 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
7322 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const {
7323 EVT VT = Op.getValueType();
7325 unsigned NumBits = VT.getSizeInBits();
7326 DebugLoc dl = Op.getDebugLoc();
7328 Op = Op.getOperand(0);
7329 if (VT == MVT::i8) {
7330 // Zero extend to i32 since there is not an i8 bsr.
7332 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
7335 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
7336 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
7337 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
7339 // If src is zero (i.e. bsr sets ZF), returns NumBits.
7342 DAG.getConstant(NumBits+NumBits-1, OpVT),
7343 DAG.getConstant(X86::COND_E, MVT::i8),
7346 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
7348 // Finally xor with NumBits-1.
7349 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
7352 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
7356 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const {
7357 EVT VT = Op.getValueType();
7359 unsigned NumBits = VT.getSizeInBits();
7360 DebugLoc dl = Op.getDebugLoc();
7362 Op = Op.getOperand(0);
7363 if (VT == MVT::i8) {
7365 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
7368 // Issue a bsf (scan bits forward) which also sets EFLAGS.
7369 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
7370 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
7372 // If src is zero (i.e. bsf sets ZF), returns NumBits.
7375 DAG.getConstant(NumBits, OpVT),
7376 DAG.getConstant(X86::COND_E, MVT::i8),
7379 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
7382 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
7386 SDValue X86TargetLowering::LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) const {
7387 EVT VT = Op.getValueType();
7388 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply");
7389 DebugLoc dl = Op.getDebugLoc();
7391 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32);
7392 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32);
7393 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b );
7394 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi );
7395 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b );
7397 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 );
7398 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 );
7399 // return AloBlo + AloBhi + AhiBlo;
7401 SDValue A = Op.getOperand(0);
7402 SDValue B = Op.getOperand(1);
7404 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7405 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
7406 A, DAG.getConstant(32, MVT::i32));
7407 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7408 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
7409 B, DAG.getConstant(32, MVT::i32));
7410 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7411 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
7413 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7414 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
7416 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7417 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
7419 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7420 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
7421 AloBhi, DAG.getConstant(32, MVT::i32));
7422 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7423 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
7424 AhiBlo, DAG.getConstant(32, MVT::i32));
7425 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
7426 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
7431 SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {
7432 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
7433 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
7434 // looks for this combo and may remove the "setcc" instruction if the "setcc"
7435 // has only one use.
7436 SDNode *N = Op.getNode();
7437 SDValue LHS = N->getOperand(0);
7438 SDValue RHS = N->getOperand(1);
7439 unsigned BaseOp = 0;
7441 DebugLoc dl = Op.getDebugLoc();
7443 switch (Op.getOpcode()) {
7444 default: llvm_unreachable("Unknown ovf instruction!");
7446 // A subtract of one will be selected as a INC. Note that INC doesn't
7447 // set CF, so we can't do this for UADDO.
7448 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
7449 if (C->getAPIntValue() == 1) {
7450 BaseOp = X86ISD::INC;
7454 BaseOp = X86ISD::ADD;
7458 BaseOp = X86ISD::ADD;
7462 // A subtract of one will be selected as a DEC. Note that DEC doesn't
7463 // set CF, so we can't do this for USUBO.
7464 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
7465 if (C->getAPIntValue() == 1) {
7466 BaseOp = X86ISD::DEC;
7470 BaseOp = X86ISD::SUB;
7474 BaseOp = X86ISD::SUB;
7478 BaseOp = X86ISD::SMUL;
7482 BaseOp = X86ISD::UMUL;
7487 // Also sets EFLAGS.
7488 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
7489 SDValue Sum = DAG.getNode(BaseOp, dl, VTs, LHS, RHS);
7492 DAG.getNode(X86ISD::SETCC, dl, N->getValueType(1),
7493 DAG.getConstant(Cond, MVT::i32), SDValue(Sum.getNode(), 1));
7495 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SetCC);
7499 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const {
7500 EVT T = Op.getValueType();
7501 DebugLoc dl = Op.getDebugLoc();
7504 switch(T.getSimpleVT().SimpleTy) {
7506 assert(false && "Invalid value type!");
7507 case MVT::i8: Reg = X86::AL; size = 1; break;
7508 case MVT::i16: Reg = X86::AX; size = 2; break;
7509 case MVT::i32: Reg = X86::EAX; size = 4; break;
7511 assert(Subtarget->is64Bit() && "Node not type legal!");
7512 Reg = X86::RAX; size = 8;
7515 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), dl, Reg,
7516 Op.getOperand(2), SDValue());
7517 SDValue Ops[] = { cpIn.getValue(0),
7520 DAG.getTargetConstant(size, MVT::i8),
7522 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
7523 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG_DAG, dl, Tys, Ops, 5);
7525 DAG.getCopyFromReg(Result.getValue(0), dl, Reg, T, Result.getValue(1));
7529 SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
7530 SelectionDAG &DAG) const {
7531 assert(Subtarget->is64Bit() && "Result not type legalized?");
7532 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
7533 SDValue TheChain = Op.getOperand(0);
7534 DebugLoc dl = Op.getDebugLoc();
7535 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
7536 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
7537 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
7539 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
7540 DAG.getConstant(32, MVT::i8));
7542 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
7545 return DAG.getMergeValues(Ops, 2, dl);
7548 SDValue X86TargetLowering::LowerBIT_CONVERT(SDValue Op,
7549 SelectionDAG &DAG) const {
7550 EVT SrcVT = Op.getOperand(0).getValueType();
7551 EVT DstVT = Op.getValueType();
7552 assert((Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
7553 Subtarget->hasMMX() && !DisableMMX) &&
7554 "Unexpected custom BIT_CONVERT");
7555 assert((DstVT == MVT::i64 ||
7556 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
7557 "Unexpected custom BIT_CONVERT");
7558 // i64 <=> MMX conversions are Legal.
7559 if (SrcVT==MVT::i64 && DstVT.isVector())
7561 if (DstVT==MVT::i64 && SrcVT.isVector())
7563 // MMX <=> MMX conversions are Legal.
7564 if (SrcVT.isVector() && DstVT.isVector())
7566 // All other conversions need to be expanded.
7569 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const {
7570 SDNode *Node = Op.getNode();
7571 DebugLoc dl = Node->getDebugLoc();
7572 EVT T = Node->getValueType(0);
7573 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
7574 DAG.getConstant(0, T), Node->getOperand(2));
7575 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
7576 cast<AtomicSDNode>(Node)->getMemoryVT(),
7577 Node->getOperand(0),
7578 Node->getOperand(1), negOp,
7579 cast<AtomicSDNode>(Node)->getSrcValue(),
7580 cast<AtomicSDNode>(Node)->getAlignment());
7583 /// LowerOperation - Provide custom lowering hooks for some operations.
7585 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
7586 switch (Op.getOpcode()) {
7587 default: llvm_unreachable("Should not custom lower this!");
7588 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
7589 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
7590 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
7591 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
7592 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
7593 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
7594 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
7595 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
7596 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
7597 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
7598 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
7599 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
7600 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
7601 case ISD::SHL_PARTS:
7602 case ISD::SRA_PARTS:
7603 case ISD::SRL_PARTS: return LowerShift(Op, DAG);
7604 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
7605 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
7606 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
7607 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
7608 case ISD::FABS: return LowerFABS(Op, DAG);
7609 case ISD::FNEG: return LowerFNEG(Op, DAG);
7610 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
7611 case ISD::SETCC: return LowerSETCC(Op, DAG);
7612 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
7613 case ISD::SELECT: return LowerSELECT(Op, DAG);
7614 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
7615 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
7616 case ISD::VASTART: return LowerVASTART(Op, DAG);
7617 case ISD::VAARG: return LowerVAARG(Op, DAG);
7618 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
7619 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
7620 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
7621 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
7622 case ISD::FRAME_TO_ARGS_OFFSET:
7623 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
7624 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
7625 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
7626 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
7627 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
7628 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
7629 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
7630 case ISD::MUL: return LowerMUL_V2I64(Op, DAG);
7636 case ISD::UMULO: return LowerXALUO(Op, DAG);
7637 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
7638 case ISD::BIT_CONVERT: return LowerBIT_CONVERT(Op, DAG);
7642 void X86TargetLowering::
7643 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
7644 SelectionDAG &DAG, unsigned NewOp) const {
7645 EVT T = Node->getValueType(0);
7646 DebugLoc dl = Node->getDebugLoc();
7647 assert (T == MVT::i64 && "Only know how to expand i64 atomics");
7649 SDValue Chain = Node->getOperand(0);
7650 SDValue In1 = Node->getOperand(1);
7651 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
7652 Node->getOperand(2), DAG.getIntPtrConstant(0));
7653 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
7654 Node->getOperand(2), DAG.getIntPtrConstant(1));
7655 SDValue Ops[] = { Chain, In1, In2L, In2H };
7656 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
7658 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64,
7659 cast<MemSDNode>(Node)->getMemOperand());
7660 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
7661 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
7662 Results.push_back(Result.getValue(2));
7665 /// ReplaceNodeResults - Replace a node with an illegal result type
7666 /// with a new node built out of custom code.
7667 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
7668 SmallVectorImpl<SDValue>&Results,
7669 SelectionDAG &DAG) const {
7670 DebugLoc dl = N->getDebugLoc();
7671 switch (N->getOpcode()) {
7673 assert(false && "Do not know how to custom type legalize this operation!");
7675 case ISD::FP_TO_SINT: {
7676 std::pair<SDValue,SDValue> Vals =
7677 FP_TO_INTHelper(SDValue(N, 0), DAG, true);
7678 SDValue FIST = Vals.first, StackSlot = Vals.second;
7679 if (FIST.getNode() != 0) {
7680 EVT VT = N->getValueType(0);
7681 // Return a load from the stack slot.
7682 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot, NULL, 0,
7687 case ISD::READCYCLECOUNTER: {
7688 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
7689 SDValue TheChain = N->getOperand(0);
7690 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
7691 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
7693 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
7695 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
7696 SDValue Ops[] = { eax, edx };
7697 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
7698 Results.push_back(edx.getValue(1));
7701 case ISD::ATOMIC_CMP_SWAP: {
7702 EVT T = N->getValueType(0);
7703 assert (T == MVT::i64 && "Only know how to expand i64 Cmp and Swap");
7704 SDValue cpInL, cpInH;
7705 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
7706 DAG.getConstant(0, MVT::i32));
7707 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
7708 DAG.getConstant(1, MVT::i32));
7709 cpInL = DAG.getCopyToReg(N->getOperand(0), dl, X86::EAX, cpInL, SDValue());
7710 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, X86::EDX, cpInH,
7712 SDValue swapInL, swapInH;
7713 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
7714 DAG.getConstant(0, MVT::i32));
7715 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
7716 DAG.getConstant(1, MVT::i32));
7717 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, X86::EBX, swapInL,
7719 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, X86::ECX, swapInH,
7720 swapInL.getValue(1));
7721 SDValue Ops[] = { swapInH.getValue(0),
7723 swapInH.getValue(1) };
7724 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
7725 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG8_DAG, dl, Tys, Ops, 3);
7726 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, X86::EAX,
7727 MVT::i32, Result.getValue(1));
7728 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, X86::EDX,
7729 MVT::i32, cpOutL.getValue(2));
7730 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
7731 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
7732 Results.push_back(cpOutH.getValue(1));
7735 case ISD::ATOMIC_LOAD_ADD:
7736 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
7738 case ISD::ATOMIC_LOAD_AND:
7739 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
7741 case ISD::ATOMIC_LOAD_NAND:
7742 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
7744 case ISD::ATOMIC_LOAD_OR:
7745 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
7747 case ISD::ATOMIC_LOAD_SUB:
7748 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
7750 case ISD::ATOMIC_LOAD_XOR:
7751 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
7753 case ISD::ATOMIC_SWAP:
7754 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
7759 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
7761 default: return NULL;
7762 case X86ISD::BSF: return "X86ISD::BSF";
7763 case X86ISD::BSR: return "X86ISD::BSR";
7764 case X86ISD::SHLD: return "X86ISD::SHLD";
7765 case X86ISD::SHRD: return "X86ISD::SHRD";
7766 case X86ISD::FAND: return "X86ISD::FAND";
7767 case X86ISD::FOR: return "X86ISD::FOR";
7768 case X86ISD::FXOR: return "X86ISD::FXOR";
7769 case X86ISD::FSRL: return "X86ISD::FSRL";
7770 case X86ISD::FILD: return "X86ISD::FILD";
7771 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
7772 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
7773 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
7774 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
7775 case X86ISD::FLD: return "X86ISD::FLD";
7776 case X86ISD::FST: return "X86ISD::FST";
7777 case X86ISD::CALL: return "X86ISD::CALL";
7778 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
7779 case X86ISD::BT: return "X86ISD::BT";
7780 case X86ISD::CMP: return "X86ISD::CMP";
7781 case X86ISD::COMI: return "X86ISD::COMI";
7782 case X86ISD::UCOMI: return "X86ISD::UCOMI";
7783 case X86ISD::SETCC: return "X86ISD::SETCC";
7784 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
7785 case X86ISD::CMOV: return "X86ISD::CMOV";
7786 case X86ISD::BRCOND: return "X86ISD::BRCOND";
7787 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
7788 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
7789 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
7790 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
7791 case X86ISD::Wrapper: return "X86ISD::Wrapper";
7792 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
7793 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
7794 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
7795 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
7796 case X86ISD::PINSRB: return "X86ISD::PINSRB";
7797 case X86ISD::PINSRW: return "X86ISD::PINSRW";
7798 case X86ISD::MMX_PINSRW: return "X86ISD::MMX_PINSRW";
7799 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
7800 case X86ISD::FMAX: return "X86ISD::FMAX";
7801 case X86ISD::FMIN: return "X86ISD::FMIN";
7802 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
7803 case X86ISD::FRCP: return "X86ISD::FRCP";
7804 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
7805 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
7806 case X86ISD::SegmentBaseAddress: return "X86ISD::SegmentBaseAddress";
7807 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
7808 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
7809 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
7810 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
7811 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
7812 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
7813 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
7814 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
7815 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
7816 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
7817 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
7818 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
7819 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
7820 case X86ISD::VSHL: return "X86ISD::VSHL";
7821 case X86ISD::VSRL: return "X86ISD::VSRL";
7822 case X86ISD::CMPPD: return "X86ISD::CMPPD";
7823 case X86ISD::CMPPS: return "X86ISD::CMPPS";
7824 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB";
7825 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW";
7826 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD";
7827 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ";
7828 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB";
7829 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW";
7830 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD";
7831 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ";
7832 case X86ISD::ADD: return "X86ISD::ADD";
7833 case X86ISD::SUB: return "X86ISD::SUB";
7834 case X86ISD::SMUL: return "X86ISD::SMUL";
7835 case X86ISD::UMUL: return "X86ISD::UMUL";
7836 case X86ISD::INC: return "X86ISD::INC";
7837 case X86ISD::DEC: return "X86ISD::DEC";
7838 case X86ISD::OR: return "X86ISD::OR";
7839 case X86ISD::XOR: return "X86ISD::XOR";
7840 case X86ISD::AND: return "X86ISD::AND";
7841 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
7842 case X86ISD::PTEST: return "X86ISD::PTEST";
7843 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
7844 case X86ISD::MINGW_ALLOCA: return "X86ISD::MINGW_ALLOCA";
7848 // isLegalAddressingMode - Return true if the addressing mode represented
7849 // by AM is legal for this target, for a load/store of the specified type.
7850 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
7851 const Type *Ty) const {
7852 // X86 supports extremely general addressing modes.
7853 CodeModel::Model M = getTargetMachine().getCodeModel();
7855 // X86 allows a sign-extended 32-bit immediate field as a displacement.
7856 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
7861 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
7863 // If a reference to this global requires an extra load, we can't fold it.
7864 if (isGlobalStubReference(GVFlags))
7867 // If BaseGV requires a register for the PIC base, we cannot also have a
7868 // BaseReg specified.
7869 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
7872 // If lower 4G is not available, then we must use rip-relative addressing.
7873 if (Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
7883 // These scales always work.
7888 // These scales are formed with basereg+scalereg. Only accept if there is
7893 default: // Other stuff never works.
7901 bool X86TargetLowering::isTruncateFree(const Type *Ty1, const Type *Ty2) const {
7902 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
7904 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
7905 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
7906 if (NumBits1 <= NumBits2)
7911 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
7912 if (!VT1.isInteger() || !VT2.isInteger())
7914 unsigned NumBits1 = VT1.getSizeInBits();
7915 unsigned NumBits2 = VT2.getSizeInBits();
7916 if (NumBits1 <= NumBits2)
7921 bool X86TargetLowering::isZExtFree(const Type *Ty1, const Type *Ty2) const {
7922 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
7923 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
7926 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
7927 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
7928 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
7931 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
7932 // i16 instructions are longer (0x66 prefix) and potentially slower.
7933 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
7936 /// isShuffleMaskLegal - Targets can use this to indicate that they only
7937 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
7938 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
7939 /// are assumed to be legal.
7941 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
7943 // Very little shuffling can be done for 64-bit vectors right now.
7944 if (VT.getSizeInBits() == 64)
7945 return isPALIGNRMask(M, VT, Subtarget->hasSSSE3());
7947 // FIXME: pshufb, blends, shifts.
7948 return (VT.getVectorNumElements() == 2 ||
7949 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
7950 isMOVLMask(M, VT) ||
7951 isSHUFPMask(M, VT) ||
7952 isPSHUFDMask(M, VT) ||
7953 isPSHUFHWMask(M, VT) ||
7954 isPSHUFLWMask(M, VT) ||
7955 isPALIGNRMask(M, VT, Subtarget->hasSSSE3()) ||
7956 isUNPCKLMask(M, VT) ||
7957 isUNPCKHMask(M, VT) ||
7958 isUNPCKL_v_undef_Mask(M, VT) ||
7959 isUNPCKH_v_undef_Mask(M, VT));
7963 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
7965 unsigned NumElts = VT.getVectorNumElements();
7966 // FIXME: This collection of masks seems suspect.
7969 if (NumElts == 4 && VT.getSizeInBits() == 128) {
7970 return (isMOVLMask(Mask, VT) ||
7971 isCommutedMOVLMask(Mask, VT, true) ||
7972 isSHUFPMask(Mask, VT) ||
7973 isCommutedSHUFPMask(Mask, VT));
7978 //===----------------------------------------------------------------------===//
7979 // X86 Scheduler Hooks
7980 //===----------------------------------------------------------------------===//
7982 // private utility function
7984 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
7985 MachineBasicBlock *MBB,
7993 TargetRegisterClass *RC,
7994 bool invSrc) const {
7995 // For the atomic bitwise operator, we generate
7998 // ld t1 = [bitinstr.addr]
7999 // op t2 = t1, [bitinstr.val]
8001 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
8003 // fallthrough -->nextMBB
8004 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8005 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
8006 MachineFunction::iterator MBBIter = MBB;
8009 /// First build the CFG
8010 MachineFunction *F = MBB->getParent();
8011 MachineBasicBlock *thisMBB = MBB;
8012 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
8013 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
8014 F->insert(MBBIter, newMBB);
8015 F->insert(MBBIter, nextMBB);
8017 // Move all successors to thisMBB to nextMBB
8018 nextMBB->transferSuccessors(thisMBB);
8020 // Update thisMBB to fall through to newMBB
8021 thisMBB->addSuccessor(newMBB);
8023 // newMBB jumps to itself and fall through to nextMBB
8024 newMBB->addSuccessor(nextMBB);
8025 newMBB->addSuccessor(newMBB);
8027 // Insert instructions into newMBB based on incoming instruction
8028 assert(bInstr->getNumOperands() < X86AddrNumOperands + 4 &&
8029 "unexpected number of operands");
8030 DebugLoc dl = bInstr->getDebugLoc();
8031 MachineOperand& destOper = bInstr->getOperand(0);
8032 MachineOperand* argOpers[2 + X86AddrNumOperands];
8033 int numArgs = bInstr->getNumOperands() - 1;
8034 for (int i=0; i < numArgs; ++i)
8035 argOpers[i] = &bInstr->getOperand(i+1);
8037 // x86 address has 4 operands: base, index, scale, and displacement
8038 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3]
8039 int valArgIndx = lastAddrIndx + 1;
8041 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
8042 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1);
8043 for (int i=0; i <= lastAddrIndx; ++i)
8044 (*MIB).addOperand(*argOpers[i]);
8046 unsigned tt = F->getRegInfo().createVirtualRegister(RC);
8048 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1);
8053 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
8054 assert((argOpers[valArgIndx]->isReg() ||
8055 argOpers[valArgIndx]->isImm()) &&
8057 if (argOpers[valArgIndx]->isReg())
8058 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2);
8060 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2);
8062 (*MIB).addOperand(*argOpers[valArgIndx]);
8064 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), EAXreg);
8067 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
8068 for (int i=0; i <= lastAddrIndx; ++i)
8069 (*MIB).addOperand(*argOpers[i]);
8071 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
8072 (*MIB).setMemRefs(bInstr->memoperands_begin(),
8073 bInstr->memoperands_end());
8075 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), destOper.getReg());
8079 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
8081 F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now.
8085 // private utility function: 64 bit atomics on 32 bit host.
8087 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
8088 MachineBasicBlock *MBB,
8093 bool invSrc) const {
8094 // For the atomic bitwise operator, we generate
8095 // thisMBB (instructions are in pairs, except cmpxchg8b)
8096 // ld t1,t2 = [bitinstr.addr]
8098 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
8099 // op t5, t6 <- out1, out2, [bitinstr.val]
8100 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
8101 // mov ECX, EBX <- t5, t6
8102 // mov EAX, EDX <- t1, t2
8103 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
8104 // mov t3, t4 <- EAX, EDX
8106 // result in out1, out2
8107 // fallthrough -->nextMBB
8109 const TargetRegisterClass *RC = X86::GR32RegisterClass;
8110 const unsigned LoadOpc = X86::MOV32rm;
8111 const unsigned copyOpc = X86::MOV32rr;
8112 const unsigned NotOpc = X86::NOT32r;
8113 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8114 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
8115 MachineFunction::iterator MBBIter = MBB;
8118 /// First build the CFG
8119 MachineFunction *F = MBB->getParent();
8120 MachineBasicBlock *thisMBB = MBB;
8121 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
8122 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
8123 F->insert(MBBIter, newMBB);
8124 F->insert(MBBIter, nextMBB);
8126 // Move all successors to thisMBB to nextMBB
8127 nextMBB->transferSuccessors(thisMBB);
8129 // Update thisMBB to fall through to newMBB
8130 thisMBB->addSuccessor(newMBB);
8132 // newMBB jumps to itself and fall through to nextMBB
8133 newMBB->addSuccessor(nextMBB);
8134 newMBB->addSuccessor(newMBB);
8136 DebugLoc dl = bInstr->getDebugLoc();
8137 // Insert instructions into newMBB based on incoming instruction
8138 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
8139 assert(bInstr->getNumOperands() < X86AddrNumOperands + 14 &&
8140 "unexpected number of operands");
8141 MachineOperand& dest1Oper = bInstr->getOperand(0);
8142 MachineOperand& dest2Oper = bInstr->getOperand(1);
8143 MachineOperand* argOpers[2 + X86AddrNumOperands];
8144 for (int i=0; i < 2 + X86AddrNumOperands; ++i) {
8145 argOpers[i] = &bInstr->getOperand(i+2);
8147 // We use some of the operands multiple times, so conservatively just
8148 // clear any kill flags that might be present.
8149 if (argOpers[i]->isReg() && argOpers[i]->isUse())
8150 argOpers[i]->setIsKill(false);
8153 // x86 address has 5 operands: base, index, scale, displacement, and segment.
8154 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3]
8156 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
8157 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1);
8158 for (int i=0; i <= lastAddrIndx; ++i)
8159 (*MIB).addOperand(*argOpers[i]);
8160 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
8161 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
8162 // add 4 to displacement.
8163 for (int i=0; i <= lastAddrIndx-2; ++i)
8164 (*MIB).addOperand(*argOpers[i]);
8165 MachineOperand newOp3 = *(argOpers[3]);
8167 newOp3.setImm(newOp3.getImm()+4);
8169 newOp3.setOffset(newOp3.getOffset()+4);
8170 (*MIB).addOperand(newOp3);
8171 (*MIB).addOperand(*argOpers[lastAddrIndx]);
8173 // t3/4 are defined later, at the bottom of the loop
8174 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
8175 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
8176 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg())
8177 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
8178 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
8179 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
8181 // The subsequent operations should be using the destination registers of
8182 //the PHI instructions.
8184 t1 = F->getRegInfo().createVirtualRegister(RC);
8185 t2 = F->getRegInfo().createVirtualRegister(RC);
8186 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t1).addReg(dest1Oper.getReg());
8187 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t2).addReg(dest2Oper.getReg());
8189 t1 = dest1Oper.getReg();
8190 t2 = dest2Oper.getReg();
8193 int valArgIndx = lastAddrIndx + 1;
8194 assert((argOpers[valArgIndx]->isReg() ||
8195 argOpers[valArgIndx]->isImm()) &&
8197 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
8198 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
8199 if (argOpers[valArgIndx]->isReg())
8200 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5);
8202 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
8203 if (regOpcL != X86::MOV32rr)
8205 (*MIB).addOperand(*argOpers[valArgIndx]);
8206 assert(argOpers[valArgIndx + 1]->isReg() ==
8207 argOpers[valArgIndx]->isReg());
8208 assert(argOpers[valArgIndx + 1]->isImm() ==
8209 argOpers[valArgIndx]->isImm());
8210 if (argOpers[valArgIndx + 1]->isReg())
8211 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
8213 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
8214 if (regOpcH != X86::MOV32rr)
8216 (*MIB).addOperand(*argOpers[valArgIndx + 1]);
8218 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EAX);
8220 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EDX);
8223 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EBX);
8225 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::ECX);
8228 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
8229 for (int i=0; i <= lastAddrIndx; ++i)
8230 (*MIB).addOperand(*argOpers[i]);
8232 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
8233 (*MIB).setMemRefs(bInstr->memoperands_begin(),
8234 bInstr->memoperands_end());
8236 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), t3);
8237 MIB.addReg(X86::EAX);
8238 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), t4);
8239 MIB.addReg(X86::EDX);
8242 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
8244 F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now.
8248 // private utility function
8250 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
8251 MachineBasicBlock *MBB,
8252 unsigned cmovOpc) const {
8253 // For the atomic min/max operator, we generate
8256 // ld t1 = [min/max.addr]
8257 // mov t2 = [min/max.val]
8259 // cmov[cond] t2 = t1
8261 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
8263 // fallthrough -->nextMBB
8265 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8266 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
8267 MachineFunction::iterator MBBIter = MBB;
8270 /// First build the CFG
8271 MachineFunction *F = MBB->getParent();
8272 MachineBasicBlock *thisMBB = MBB;
8273 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
8274 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
8275 F->insert(MBBIter, newMBB);
8276 F->insert(MBBIter, nextMBB);
8278 // Move all successors of thisMBB to nextMBB
8279 nextMBB->transferSuccessors(thisMBB);
8281 // Update thisMBB to fall through to newMBB
8282 thisMBB->addSuccessor(newMBB);
8284 // newMBB jumps to newMBB and fall through to nextMBB
8285 newMBB->addSuccessor(nextMBB);
8286 newMBB->addSuccessor(newMBB);
8288 DebugLoc dl = mInstr->getDebugLoc();
8289 // Insert instructions into newMBB based on incoming instruction
8290 assert(mInstr->getNumOperands() < X86AddrNumOperands + 4 &&
8291 "unexpected number of operands");
8292 MachineOperand& destOper = mInstr->getOperand(0);
8293 MachineOperand* argOpers[2 + X86AddrNumOperands];
8294 int numArgs = mInstr->getNumOperands() - 1;
8295 for (int i=0; i < numArgs; ++i)
8296 argOpers[i] = &mInstr->getOperand(i+1);
8298 // x86 address has 4 operands: base, index, scale, and displacement
8299 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3]
8300 int valArgIndx = lastAddrIndx + 1;
8302 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
8303 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1);
8304 for (int i=0; i <= lastAddrIndx; ++i)
8305 (*MIB).addOperand(*argOpers[i]);
8307 // We only support register and immediate values
8308 assert((argOpers[valArgIndx]->isReg() ||
8309 argOpers[valArgIndx]->isImm()) &&
8312 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
8313 if (argOpers[valArgIndx]->isReg())
8314 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
8316 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
8317 (*MIB).addOperand(*argOpers[valArgIndx]);
8319 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), X86::EAX);
8322 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr));
8327 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
8328 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3);
8332 // Cmp and exchange if none has modified the memory location
8333 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32));
8334 for (int i=0; i <= lastAddrIndx; ++i)
8335 (*MIB).addOperand(*argOpers[i]);
8337 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
8338 (*MIB).setMemRefs(mInstr->memoperands_begin(),
8339 mInstr->memoperands_end());
8341 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), destOper.getReg());
8342 MIB.addReg(X86::EAX);
8345 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
8347 F->DeleteMachineInstr(mInstr); // The pseudo instruction is gone now.
8351 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
8352 // all of this code can be replaced with that in the .td file.
8354 X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB,
8355 unsigned numArgs, bool memArg) const {
8357 MachineFunction *F = BB->getParent();
8358 DebugLoc dl = MI->getDebugLoc();
8359 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8363 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm;
8365 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr;
8367 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(Opc));
8369 for (unsigned i = 0; i < numArgs; ++i) {
8370 MachineOperand &Op = MI->getOperand(i+1);
8372 if (!(Op.isReg() && Op.isImplicit()))
8376 BuildMI(BB, dl, TII->get(X86::MOVAPSrr), MI->getOperand(0).getReg())
8379 F->DeleteMachineInstr(MI);
8385 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
8387 MachineBasicBlock *MBB) const {
8388 // Emit code to save XMM registers to the stack. The ABI says that the
8389 // number of registers to save is given in %al, so it's theoretically
8390 // possible to do an indirect jump trick to avoid saving all of them,
8391 // however this code takes a simpler approach and just executes all
8392 // of the stores if %al is non-zero. It's less code, and it's probably
8393 // easier on the hardware branch predictor, and stores aren't all that
8394 // expensive anyway.
8396 // Create the new basic blocks. One block contains all the XMM stores,
8397 // and one block is the final destination regardless of whether any
8398 // stores were performed.
8399 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
8400 MachineFunction *F = MBB->getParent();
8401 MachineFunction::iterator MBBIter = MBB;
8403 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
8404 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
8405 F->insert(MBBIter, XMMSaveMBB);
8406 F->insert(MBBIter, EndMBB);
8409 // Move any original successors of MBB to the end block.
8410 EndMBB->transferSuccessors(MBB);
8411 // The original block will now fall through to the XMM save block.
8412 MBB->addSuccessor(XMMSaveMBB);
8413 // The XMMSaveMBB will fall through to the end block.
8414 XMMSaveMBB->addSuccessor(EndMBB);
8416 // Now add the instructions.
8417 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8418 DebugLoc DL = MI->getDebugLoc();
8420 unsigned CountReg = MI->getOperand(0).getReg();
8421 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
8422 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
8424 if (!Subtarget->isTargetWin64()) {
8425 // If %al is 0, branch around the XMM save block.
8426 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
8427 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
8428 MBB->addSuccessor(EndMBB);
8431 // In the XMM save block, save all the XMM argument registers.
8432 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
8433 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
8434 MachineMemOperand *MMO =
8435 F->getMachineMemOperand(
8436 PseudoSourceValue::getFixedStack(RegSaveFrameIndex),
8437 MachineMemOperand::MOStore, Offset,
8438 /*Size=*/16, /*Align=*/16);
8439 BuildMI(XMMSaveMBB, DL, TII->get(X86::MOVAPSmr))
8440 .addFrameIndex(RegSaveFrameIndex)
8441 .addImm(/*Scale=*/1)
8442 .addReg(/*IndexReg=*/0)
8443 .addImm(/*Disp=*/Offset)
8444 .addReg(/*Segment=*/0)
8445 .addReg(MI->getOperand(i).getReg())
8446 .addMemOperand(MMO);
8449 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
8455 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
8456 MachineBasicBlock *BB) const {
8457 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8458 DebugLoc DL = MI->getDebugLoc();
8460 // To "insert" a SELECT_CC instruction, we actually have to insert the
8461 // diamond control-flow pattern. The incoming instruction knows the
8462 // destination vreg to set, the condition code register to branch on, the
8463 // true/false values to select between, and a branch opcode to use.
8464 const BasicBlock *LLVM_BB = BB->getBasicBlock();
8465 MachineFunction::iterator It = BB;
8471 // cmpTY ccX, r1, r2
8473 // fallthrough --> copy0MBB
8474 MachineBasicBlock *thisMBB = BB;
8475 MachineFunction *F = BB->getParent();
8476 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
8477 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
8479 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
8481 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
8482 F->insert(It, copy0MBB);
8483 F->insert(It, sinkMBB);
8485 // Update machine-CFG edges by first adding all successors of the current
8486 // block to the new block which will contain the Phi node for the select.
8487 for (MachineBasicBlock::succ_iterator I = BB->succ_begin(),
8488 E = BB->succ_end(); I != E; ++I)
8489 sinkMBB->addSuccessor(*I);
8491 // Next, remove all successors of the current block, and add the true
8492 // and fallthrough blocks as its successors.
8493 while (!BB->succ_empty())
8494 BB->removeSuccessor(BB->succ_begin());
8496 // Add the true and fallthrough blocks as its successors.
8497 BB->addSuccessor(copy0MBB);
8498 BB->addSuccessor(sinkMBB);
8500 // If the EFLAGS register isn't dead in the terminator, then claim that it's
8501 // live into the sink and copy blocks.
8502 const MachineFunction *MF = BB->getParent();
8503 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
8504 BitVector ReservedRegs = TRI->getReservedRegs(*MF);
8505 const MachineInstr *Term = BB->getFirstTerminator();
8507 for (unsigned I = 0, E = Term->getNumOperands(); I != E; ++I) {
8508 const MachineOperand &MO = Term->getOperand(I);
8509 if (!MO.isReg() || MO.isKill() || MO.isDead()) continue;
8510 unsigned Reg = MO.getReg();
8511 if (Reg != X86::EFLAGS) continue;
8512 copy0MBB->addLiveIn(Reg);
8513 sinkMBB->addLiveIn(Reg);
8517 // %FalseValue = ...
8518 // # fallthrough to sinkMBB
8519 copy0MBB->addSuccessor(sinkMBB);
8522 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
8524 BuildMI(sinkMBB, DL, TII->get(X86::PHI), MI->getOperand(0).getReg())
8525 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
8526 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
8528 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
8533 X86TargetLowering::EmitLoweredMingwAlloca(MachineInstr *MI,
8534 MachineBasicBlock *BB) const {
8535 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8536 DebugLoc DL = MI->getDebugLoc();
8537 MachineFunction *F = BB->getParent();
8539 // The lowering is pretty easy: we're just emitting the call to _alloca. The
8540 // non-trivial part is impdef of ESP.
8541 // FIXME: The code should be tweaked as soon as we'll try to do codegen for
8544 BuildMI(BB, DL, TII->get(X86::CALLpcrel32))
8545 .addExternalSymbol("_alloca")
8546 .addReg(X86::EAX, RegState::Implicit)
8547 .addReg(X86::ESP, RegState::Implicit)
8548 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
8549 .addReg(X86::ESP, RegState::Define | RegState::Implicit);
8551 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
8556 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
8557 MachineBasicBlock *BB) const {
8558 // This is pretty easy. We're taking the value that we received from
8559 // our load from the relocation, sticking it in either RDI (x86-64)
8560 // or EAX and doing an indirect call. The return value will then
8561 // be in the normal return register.
8562 const X86InstrInfo *TII
8563 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
8564 DebugLoc DL = MI->getDebugLoc();
8565 MachineFunction *F = BB->getParent();
8567 assert(MI->getOperand(3).isGlobal() && "This should be a global");
8569 if (Subtarget->is64Bit()) {
8570 MachineInstrBuilder MIB = BuildMI(BB, DL, TII->get(X86::MOV64rm), X86::RDI)
8572 .addImm(0).addReg(0)
8573 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
8574 MI->getOperand(3).getTargetFlags())
8576 MIB = BuildMI(BB, DL, TII->get(X86::CALL64m));
8577 addDirectMem(MIB, X86::RDI).addReg(0);
8578 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
8579 MachineInstrBuilder MIB = BuildMI(BB, DL, TII->get(X86::MOV32rm), X86::EAX)
8581 .addImm(0).addReg(0)
8582 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
8583 MI->getOperand(3).getTargetFlags())
8585 MIB = BuildMI(BB, DL, TII->get(X86::CALL32m));
8586 addDirectMem(MIB, X86::EAX).addReg(0);
8588 MachineInstrBuilder MIB = BuildMI(BB, DL, TII->get(X86::MOV32rm), X86::EAX)
8589 .addReg(TII->getGlobalBaseReg(F))
8590 .addImm(0).addReg(0)
8591 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
8592 MI->getOperand(3).getTargetFlags())
8594 MIB = BuildMI(BB, DL, TII->get(X86::CALL32m));
8595 addDirectMem(MIB, X86::EAX).addReg(0);
8598 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
8603 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
8604 MachineBasicBlock *BB) const {
8605 switch (MI->getOpcode()) {
8606 default: assert(false && "Unexpected instr type to insert");
8607 case X86::MINGW_ALLOCA:
8608 return EmitLoweredMingwAlloca(MI, BB);
8609 case X86::TLSCall_32:
8610 case X86::TLSCall_64:
8611 return EmitLoweredTLSCall(MI, BB);
8613 case X86::CMOV_V1I64:
8614 case X86::CMOV_FR32:
8615 case X86::CMOV_FR64:
8616 case X86::CMOV_V4F32:
8617 case X86::CMOV_V2F64:
8618 case X86::CMOV_V2I64:
8619 case X86::CMOV_GR16:
8620 case X86::CMOV_GR32:
8621 case X86::CMOV_RFP32:
8622 case X86::CMOV_RFP64:
8623 case X86::CMOV_RFP80:
8624 return EmitLoweredSelect(MI, BB);
8626 case X86::FP32_TO_INT16_IN_MEM:
8627 case X86::FP32_TO_INT32_IN_MEM:
8628 case X86::FP32_TO_INT64_IN_MEM:
8629 case X86::FP64_TO_INT16_IN_MEM:
8630 case X86::FP64_TO_INT32_IN_MEM:
8631 case X86::FP64_TO_INT64_IN_MEM:
8632 case X86::FP80_TO_INT16_IN_MEM:
8633 case X86::FP80_TO_INT32_IN_MEM:
8634 case X86::FP80_TO_INT64_IN_MEM: {
8635 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8636 DebugLoc DL = MI->getDebugLoc();
8638 // Change the floating point control register to use "round towards zero"
8639 // mode when truncating to an integer value.
8640 MachineFunction *F = BB->getParent();
8641 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
8642 addFrameReference(BuildMI(BB, DL, TII->get(X86::FNSTCW16m)), CWFrameIdx);
8644 // Load the old value of the high byte of the control word...
8646 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
8647 addFrameReference(BuildMI(BB, DL, TII->get(X86::MOV16rm), OldCW),
8650 // Set the high part to be round to zero...
8651 addFrameReference(BuildMI(BB, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
8654 // Reload the modified control word now...
8655 addFrameReference(BuildMI(BB, DL, TII->get(X86::FLDCW16m)), CWFrameIdx);
8657 // Restore the memory image of control word to original value
8658 addFrameReference(BuildMI(BB, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
8661 // Get the X86 opcode to use.
8663 switch (MI->getOpcode()) {
8664 default: llvm_unreachable("illegal opcode!");
8665 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
8666 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
8667 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
8668 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
8669 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
8670 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
8671 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
8672 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
8673 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
8677 MachineOperand &Op = MI->getOperand(0);
8679 AM.BaseType = X86AddressMode::RegBase;
8680 AM.Base.Reg = Op.getReg();
8682 AM.BaseType = X86AddressMode::FrameIndexBase;
8683 AM.Base.FrameIndex = Op.getIndex();
8685 Op = MI->getOperand(1);
8687 AM.Scale = Op.getImm();
8688 Op = MI->getOperand(2);
8690 AM.IndexReg = Op.getImm();
8691 Op = MI->getOperand(3);
8692 if (Op.isGlobal()) {
8693 AM.GV = Op.getGlobal();
8695 AM.Disp = Op.getImm();
8697 addFullAddress(BuildMI(BB, DL, TII->get(Opc)), AM)
8698 .addReg(MI->getOperand(X86AddrNumOperands).getReg());
8700 // Reload the original control word now.
8701 addFrameReference(BuildMI(BB, DL, TII->get(X86::FLDCW16m)), CWFrameIdx);
8703 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
8706 // String/text processing lowering.
8707 case X86::PCMPISTRM128REG:
8708 return EmitPCMP(MI, BB, 3, false /* in-mem */);
8709 case X86::PCMPISTRM128MEM:
8710 return EmitPCMP(MI, BB, 3, true /* in-mem */);
8711 case X86::PCMPESTRM128REG:
8712 return EmitPCMP(MI, BB, 5, false /* in mem */);
8713 case X86::PCMPESTRM128MEM:
8714 return EmitPCMP(MI, BB, 5, true /* in mem */);
8717 case X86::ATOMAND32:
8718 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
8719 X86::AND32ri, X86::MOV32rm,
8720 X86::LCMPXCHG32, X86::MOV32rr,
8721 X86::NOT32r, X86::EAX,
8722 X86::GR32RegisterClass);
8724 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
8725 X86::OR32ri, X86::MOV32rm,
8726 X86::LCMPXCHG32, X86::MOV32rr,
8727 X86::NOT32r, X86::EAX,
8728 X86::GR32RegisterClass);
8729 case X86::ATOMXOR32:
8730 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
8731 X86::XOR32ri, X86::MOV32rm,
8732 X86::LCMPXCHG32, X86::MOV32rr,
8733 X86::NOT32r, X86::EAX,
8734 X86::GR32RegisterClass);
8735 case X86::ATOMNAND32:
8736 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
8737 X86::AND32ri, X86::MOV32rm,
8738 X86::LCMPXCHG32, X86::MOV32rr,
8739 X86::NOT32r, X86::EAX,
8740 X86::GR32RegisterClass, true);
8741 case X86::ATOMMIN32:
8742 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
8743 case X86::ATOMMAX32:
8744 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
8745 case X86::ATOMUMIN32:
8746 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
8747 case X86::ATOMUMAX32:
8748 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
8750 case X86::ATOMAND16:
8751 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
8752 X86::AND16ri, X86::MOV16rm,
8753 X86::LCMPXCHG16, X86::MOV16rr,
8754 X86::NOT16r, X86::AX,
8755 X86::GR16RegisterClass);
8757 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
8758 X86::OR16ri, X86::MOV16rm,
8759 X86::LCMPXCHG16, X86::MOV16rr,
8760 X86::NOT16r, X86::AX,
8761 X86::GR16RegisterClass);
8762 case X86::ATOMXOR16:
8763 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
8764 X86::XOR16ri, X86::MOV16rm,
8765 X86::LCMPXCHG16, X86::MOV16rr,
8766 X86::NOT16r, X86::AX,
8767 X86::GR16RegisterClass);
8768 case X86::ATOMNAND16:
8769 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
8770 X86::AND16ri, X86::MOV16rm,
8771 X86::LCMPXCHG16, X86::MOV16rr,
8772 X86::NOT16r, X86::AX,
8773 X86::GR16RegisterClass, true);
8774 case X86::ATOMMIN16:
8775 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
8776 case X86::ATOMMAX16:
8777 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
8778 case X86::ATOMUMIN16:
8779 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
8780 case X86::ATOMUMAX16:
8781 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
8784 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
8785 X86::AND8ri, X86::MOV8rm,
8786 X86::LCMPXCHG8, X86::MOV8rr,
8787 X86::NOT8r, X86::AL,
8788 X86::GR8RegisterClass);
8790 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
8791 X86::OR8ri, X86::MOV8rm,
8792 X86::LCMPXCHG8, X86::MOV8rr,
8793 X86::NOT8r, X86::AL,
8794 X86::GR8RegisterClass);
8796 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
8797 X86::XOR8ri, X86::MOV8rm,
8798 X86::LCMPXCHG8, X86::MOV8rr,
8799 X86::NOT8r, X86::AL,
8800 X86::GR8RegisterClass);
8801 case X86::ATOMNAND8:
8802 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
8803 X86::AND8ri, X86::MOV8rm,
8804 X86::LCMPXCHG8, X86::MOV8rr,
8805 X86::NOT8r, X86::AL,
8806 X86::GR8RegisterClass, true);
8807 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
8808 // This group is for 64-bit host.
8809 case X86::ATOMAND64:
8810 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
8811 X86::AND64ri32, X86::MOV64rm,
8812 X86::LCMPXCHG64, X86::MOV64rr,
8813 X86::NOT64r, X86::RAX,
8814 X86::GR64RegisterClass);
8816 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
8817 X86::OR64ri32, X86::MOV64rm,
8818 X86::LCMPXCHG64, X86::MOV64rr,
8819 X86::NOT64r, X86::RAX,
8820 X86::GR64RegisterClass);
8821 case X86::ATOMXOR64:
8822 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
8823 X86::XOR64ri32, X86::MOV64rm,
8824 X86::LCMPXCHG64, X86::MOV64rr,
8825 X86::NOT64r, X86::RAX,
8826 X86::GR64RegisterClass);
8827 case X86::ATOMNAND64:
8828 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
8829 X86::AND64ri32, X86::MOV64rm,
8830 X86::LCMPXCHG64, X86::MOV64rr,
8831 X86::NOT64r, X86::RAX,
8832 X86::GR64RegisterClass, true);
8833 case X86::ATOMMIN64:
8834 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
8835 case X86::ATOMMAX64:
8836 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
8837 case X86::ATOMUMIN64:
8838 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
8839 case X86::ATOMUMAX64:
8840 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
8842 // This group does 64-bit operations on a 32-bit host.
8843 case X86::ATOMAND6432:
8844 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8845 X86::AND32rr, X86::AND32rr,
8846 X86::AND32ri, X86::AND32ri,
8848 case X86::ATOMOR6432:
8849 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8850 X86::OR32rr, X86::OR32rr,
8851 X86::OR32ri, X86::OR32ri,
8853 case X86::ATOMXOR6432:
8854 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8855 X86::XOR32rr, X86::XOR32rr,
8856 X86::XOR32ri, X86::XOR32ri,
8858 case X86::ATOMNAND6432:
8859 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8860 X86::AND32rr, X86::AND32rr,
8861 X86::AND32ri, X86::AND32ri,
8863 case X86::ATOMADD6432:
8864 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8865 X86::ADD32rr, X86::ADC32rr,
8866 X86::ADD32ri, X86::ADC32ri,
8868 case X86::ATOMSUB6432:
8869 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8870 X86::SUB32rr, X86::SBB32rr,
8871 X86::SUB32ri, X86::SBB32ri,
8873 case X86::ATOMSWAP6432:
8874 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8875 X86::MOV32rr, X86::MOV32rr,
8876 X86::MOV32ri, X86::MOV32ri,
8878 case X86::VASTART_SAVE_XMM_REGS:
8879 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
8883 //===----------------------------------------------------------------------===//
8884 // X86 Optimization Hooks
8885 //===----------------------------------------------------------------------===//
8887 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
8891 const SelectionDAG &DAG,
8892 unsigned Depth) const {
8893 unsigned Opc = Op.getOpcode();
8894 assert((Opc >= ISD::BUILTIN_OP_END ||
8895 Opc == ISD::INTRINSIC_WO_CHAIN ||
8896 Opc == ISD::INTRINSIC_W_CHAIN ||
8897 Opc == ISD::INTRINSIC_VOID) &&
8898 "Should use MaskedValueIsZero if you don't know whether Op"
8899 " is a target node!");
8901 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
8913 // These nodes' second result is a boolean.
8914 if (Op.getResNo() == 0)
8918 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
8919 Mask.getBitWidth() - 1);
8924 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
8925 /// node is a GlobalAddress + offset.
8926 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
8927 const GlobalValue* &GA,
8928 int64_t &Offset) const {
8929 if (N->getOpcode() == X86ISD::Wrapper) {
8930 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
8931 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
8932 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
8936 return TargetLowering::isGAPlusOffset(N, GA, Offset);
8939 /// PerformShuffleCombine - Combine a vector_shuffle that is equal to
8940 /// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load
8941 /// if the load addresses are consecutive, non-overlapping, and in the right
8943 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
8944 const TargetLowering &TLI) {
8945 DebugLoc dl = N->getDebugLoc();
8946 EVT VT = N->getValueType(0);
8947 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
8949 if (VT.getSizeInBits() != 128)
8952 SmallVector<SDValue, 16> Elts;
8953 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
8954 Elts.push_back(DAG.getShuffleScalarElt(SVN, i));
8956 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG);
8959 /// PerformShuffleCombine - Detect vector gather/scatter index generation
8960 /// and convert it from being a bunch of shuffles and extracts to a simple
8961 /// store and scalar loads to extract the elements.
8962 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
8963 const TargetLowering &TLI) {
8964 SDValue InputVector = N->getOperand(0);
8966 // Only operate on vectors of 4 elements, where the alternative shuffling
8967 // gets to be more expensive.
8968 if (InputVector.getValueType() != MVT::v4i32)
8971 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
8972 // single use which is a sign-extend or zero-extend, and all elements are
8974 SmallVector<SDNode *, 4> Uses;
8975 unsigned ExtractedElements = 0;
8976 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
8977 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
8978 if (UI.getUse().getResNo() != InputVector.getResNo())
8981 SDNode *Extract = *UI;
8982 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
8985 if (Extract->getValueType(0) != MVT::i32)
8987 if (!Extract->hasOneUse())
8989 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
8990 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
8992 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
8995 // Record which element was extracted.
8996 ExtractedElements |=
8997 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
8999 Uses.push_back(Extract);
9002 // If not all the elements were used, this may not be worthwhile.
9003 if (ExtractedElements != 15)
9006 // Ok, we've now decided to do the transformation.
9007 DebugLoc dl = InputVector.getDebugLoc();
9009 // Store the value to a temporary stack slot.
9010 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
9011 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr, NULL, 0,
9014 // Replace each use (extract) with a load of the appropriate element.
9015 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
9016 UE = Uses.end(); UI != UE; ++UI) {
9017 SDNode *Extract = *UI;
9019 // Compute the element's address.
9020 SDValue Idx = Extract->getOperand(1);
9022 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
9023 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
9024 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
9026 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), OffsetVal, StackPtr);
9029 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch, ScalarAddr,
9030 NULL, 0, false, false, 0);
9032 // Replace the exact with the load.
9033 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
9036 // The replacement was made in place; don't return anything.
9040 /// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
9041 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
9042 const X86Subtarget *Subtarget) {
9043 DebugLoc DL = N->getDebugLoc();
9044 SDValue Cond = N->getOperand(0);
9045 // Get the LHS/RHS of the select.
9046 SDValue LHS = N->getOperand(1);
9047 SDValue RHS = N->getOperand(2);
9049 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
9050 // instructions match the semantics of the common C idiom x<y?x:y but not
9051 // x<=y?x:y, because of how they handle negative zero (which can be
9052 // ignored in unsafe-math mode).
9053 if (Subtarget->hasSSE2() &&
9054 (LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64) &&
9055 Cond.getOpcode() == ISD::SETCC) {
9056 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
9058 unsigned Opcode = 0;
9059 // Check for x CC y ? x : y.
9060 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
9061 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
9065 // Converting this to a min would handle NaNs incorrectly, and swapping
9066 // the operands would cause it to handle comparisons between positive
9067 // and negative zero incorrectly.
9068 if (!FiniteOnlyFPMath() &&
9069 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))) {
9070 if (!UnsafeFPMath &&
9071 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
9073 std::swap(LHS, RHS);
9075 Opcode = X86ISD::FMIN;
9078 // Converting this to a min would handle comparisons between positive
9079 // and negative zero incorrectly.
9080 if (!UnsafeFPMath &&
9081 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
9083 Opcode = X86ISD::FMIN;
9086 // Converting this to a min would handle both negative zeros and NaNs
9087 // incorrectly, but we can swap the operands to fix both.
9088 std::swap(LHS, RHS);
9092 Opcode = X86ISD::FMIN;
9096 // Converting this to a max would handle comparisons between positive
9097 // and negative zero incorrectly.
9098 if (!UnsafeFPMath &&
9099 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(LHS))
9101 Opcode = X86ISD::FMAX;
9104 // Converting this to a max would handle NaNs incorrectly, and swapping
9105 // the operands would cause it to handle comparisons between positive
9106 // and negative zero incorrectly.
9107 if (!FiniteOnlyFPMath() &&
9108 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))) {
9109 if (!UnsafeFPMath &&
9110 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
9112 std::swap(LHS, RHS);
9114 Opcode = X86ISD::FMAX;
9117 // Converting this to a max would handle both negative zeros and NaNs
9118 // incorrectly, but we can swap the operands to fix both.
9119 std::swap(LHS, RHS);
9123 Opcode = X86ISD::FMAX;
9126 // Check for x CC y ? y : x -- a min/max with reversed arms.
9127 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
9128 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
9132 // Converting this to a min would handle comparisons between positive
9133 // and negative zero incorrectly, and swapping the operands would
9134 // cause it to handle NaNs incorrectly.
9135 if (!UnsafeFPMath &&
9136 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
9137 if (!FiniteOnlyFPMath() &&
9138 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
9140 std::swap(LHS, RHS);
9142 Opcode = X86ISD::FMIN;
9145 // Converting this to a min would handle NaNs incorrectly.
9146 if (!UnsafeFPMath &&
9147 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
9149 Opcode = X86ISD::FMIN;
9152 // Converting this to a min would handle both negative zeros and NaNs
9153 // incorrectly, but we can swap the operands to fix both.
9154 std::swap(LHS, RHS);
9158 Opcode = X86ISD::FMIN;
9162 // Converting this to a max would handle NaNs incorrectly.
9163 if (!FiniteOnlyFPMath() &&
9164 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
9166 Opcode = X86ISD::FMAX;
9169 // Converting this to a max would handle comparisons between positive
9170 // and negative zero incorrectly, and swapping the operands would
9171 // cause it to handle NaNs incorrectly.
9172 if (!UnsafeFPMath &&
9173 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
9174 if (!FiniteOnlyFPMath() &&
9175 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
9177 std::swap(LHS, RHS);
9179 Opcode = X86ISD::FMAX;
9182 // Converting this to a max would handle both negative zeros and NaNs
9183 // incorrectly, but we can swap the operands to fix both.
9184 std::swap(LHS, RHS);
9188 Opcode = X86ISD::FMAX;
9194 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
9197 // If this is a select between two integer constants, try to do some
9199 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
9200 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
9201 // Don't do this for crazy integer types.
9202 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
9203 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
9204 // so that TrueC (the true value) is larger than FalseC.
9205 bool NeedsCondInvert = false;
9207 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
9208 // Efficiently invertible.
9209 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
9210 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
9211 isa<ConstantSDNode>(Cond.getOperand(1))))) {
9212 NeedsCondInvert = true;
9213 std::swap(TrueC, FalseC);
9216 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
9217 if (FalseC->getAPIntValue() == 0 &&
9218 TrueC->getAPIntValue().isPowerOf2()) {
9219 if (NeedsCondInvert) // Invert the condition if needed.
9220 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
9221 DAG.getConstant(1, Cond.getValueType()));
9223 // Zero extend the condition if needed.
9224 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
9226 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
9227 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
9228 DAG.getConstant(ShAmt, MVT::i8));
9231 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
9232 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
9233 if (NeedsCondInvert) // Invert the condition if needed.
9234 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
9235 DAG.getConstant(1, Cond.getValueType()));
9237 // Zero extend the condition if needed.
9238 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
9239 FalseC->getValueType(0), Cond);
9240 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
9241 SDValue(FalseC, 0));
9244 // Optimize cases that will turn into an LEA instruction. This requires
9245 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
9246 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
9247 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
9248 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
9250 bool isFastMultiplier = false;
9252 switch ((unsigned char)Diff) {
9254 case 1: // result = add base, cond
9255 case 2: // result = lea base( , cond*2)
9256 case 3: // result = lea base(cond, cond*2)
9257 case 4: // result = lea base( , cond*4)
9258 case 5: // result = lea base(cond, cond*4)
9259 case 8: // result = lea base( , cond*8)
9260 case 9: // result = lea base(cond, cond*8)
9261 isFastMultiplier = true;
9266 if (isFastMultiplier) {
9267 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
9268 if (NeedsCondInvert) // Invert the condition if needed.
9269 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
9270 DAG.getConstant(1, Cond.getValueType()));
9272 // Zero extend the condition if needed.
9273 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
9275 // Scale the condition by the difference.
9277 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
9278 DAG.getConstant(Diff, Cond.getValueType()));
9280 // Add the base if non-zero.
9281 if (FalseC->getAPIntValue() != 0)
9282 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
9283 SDValue(FalseC, 0));
9293 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
9294 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
9295 TargetLowering::DAGCombinerInfo &DCI) {
9296 DebugLoc DL = N->getDebugLoc();
9298 // If the flag operand isn't dead, don't touch this CMOV.
9299 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
9302 // If this is a select between two integer constants, try to do some
9303 // optimizations. Note that the operands are ordered the opposite of SELECT
9305 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
9306 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
9307 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
9308 // larger than FalseC (the false value).
9309 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
9311 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
9312 CC = X86::GetOppositeBranchCondition(CC);
9313 std::swap(TrueC, FalseC);
9316 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
9317 // This is efficient for any integer data type (including i8/i16) and
9319 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
9320 SDValue Cond = N->getOperand(3);
9321 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
9322 DAG.getConstant(CC, MVT::i8), Cond);
9324 // Zero extend the condition if needed.
9325 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
9327 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
9328 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
9329 DAG.getConstant(ShAmt, MVT::i8));
9330 if (N->getNumValues() == 2) // Dead flag value?
9331 return DCI.CombineTo(N, Cond, SDValue());
9335 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
9336 // for any integer data type, including i8/i16.
9337 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
9338 SDValue Cond = N->getOperand(3);
9339 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
9340 DAG.getConstant(CC, MVT::i8), Cond);
9342 // Zero extend the condition if needed.
9343 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
9344 FalseC->getValueType(0), Cond);
9345 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
9346 SDValue(FalseC, 0));
9348 if (N->getNumValues() == 2) // Dead flag value?
9349 return DCI.CombineTo(N, Cond, SDValue());
9353 // Optimize cases that will turn into an LEA instruction. This requires
9354 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
9355 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
9356 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
9357 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
9359 bool isFastMultiplier = false;
9361 switch ((unsigned char)Diff) {
9363 case 1: // result = add base, cond
9364 case 2: // result = lea base( , cond*2)
9365 case 3: // result = lea base(cond, cond*2)
9366 case 4: // result = lea base( , cond*4)
9367 case 5: // result = lea base(cond, cond*4)
9368 case 8: // result = lea base( , cond*8)
9369 case 9: // result = lea base(cond, cond*8)
9370 isFastMultiplier = true;
9375 if (isFastMultiplier) {
9376 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
9377 SDValue Cond = N->getOperand(3);
9378 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
9379 DAG.getConstant(CC, MVT::i8), Cond);
9380 // Zero extend the condition if needed.
9381 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
9383 // Scale the condition by the difference.
9385 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
9386 DAG.getConstant(Diff, Cond.getValueType()));
9388 // Add the base if non-zero.
9389 if (FalseC->getAPIntValue() != 0)
9390 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
9391 SDValue(FalseC, 0));
9392 if (N->getNumValues() == 2) // Dead flag value?
9393 return DCI.CombineTo(N, Cond, SDValue());
9403 /// PerformMulCombine - Optimize a single multiply with constant into two
9404 /// in order to implement it with two cheaper instructions, e.g.
9405 /// LEA + SHL, LEA + LEA.
9406 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
9407 TargetLowering::DAGCombinerInfo &DCI) {
9408 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
9411 EVT VT = N->getValueType(0);
9415 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
9418 uint64_t MulAmt = C->getZExtValue();
9419 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
9422 uint64_t MulAmt1 = 0;
9423 uint64_t MulAmt2 = 0;
9424 if ((MulAmt % 9) == 0) {
9426 MulAmt2 = MulAmt / 9;
9427 } else if ((MulAmt % 5) == 0) {
9429 MulAmt2 = MulAmt / 5;
9430 } else if ((MulAmt % 3) == 0) {
9432 MulAmt2 = MulAmt / 3;
9435 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
9436 DebugLoc DL = N->getDebugLoc();
9438 if (isPowerOf2_64(MulAmt2) &&
9439 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
9440 // If second multiplifer is pow2, issue it first. We want the multiply by
9441 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
9443 std::swap(MulAmt1, MulAmt2);
9446 if (isPowerOf2_64(MulAmt1))
9447 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
9448 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
9450 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
9451 DAG.getConstant(MulAmt1, VT));
9453 if (isPowerOf2_64(MulAmt2))
9454 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
9455 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
9457 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
9458 DAG.getConstant(MulAmt2, VT));
9460 // Do not add new nodes to DAG combiner worklist.
9461 DCI.CombineTo(N, NewMul, false);
9466 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
9467 SDValue N0 = N->getOperand(0);
9468 SDValue N1 = N->getOperand(1);
9469 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
9470 EVT VT = N0.getValueType();
9472 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
9473 // since the result of setcc_c is all zero's or all ones.
9474 if (N1C && N0.getOpcode() == ISD::AND &&
9475 N0.getOperand(1).getOpcode() == ISD::Constant) {
9476 SDValue N00 = N0.getOperand(0);
9477 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
9478 ((N00.getOpcode() == ISD::ANY_EXTEND ||
9479 N00.getOpcode() == ISD::ZERO_EXTEND) &&
9480 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
9481 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
9482 APInt ShAmt = N1C->getAPIntValue();
9483 Mask = Mask.shl(ShAmt);
9485 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
9486 N00, DAG.getConstant(Mask, VT));
9493 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
9495 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
9496 const X86Subtarget *Subtarget) {
9497 EVT VT = N->getValueType(0);
9498 if (!VT.isVector() && VT.isInteger() &&
9499 N->getOpcode() == ISD::SHL)
9500 return PerformSHLCombine(N, DAG);
9502 // On X86 with SSE2 support, we can transform this to a vector shift if
9503 // all elements are shifted by the same amount. We can't do this in legalize
9504 // because the a constant vector is typically transformed to a constant pool
9505 // so we have no knowledge of the shift amount.
9506 if (!Subtarget->hasSSE2())
9509 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
9512 SDValue ShAmtOp = N->getOperand(1);
9513 EVT EltVT = VT.getVectorElementType();
9514 DebugLoc DL = N->getDebugLoc();
9515 SDValue BaseShAmt = SDValue();
9516 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
9517 unsigned NumElts = VT.getVectorNumElements();
9519 for (; i != NumElts; ++i) {
9520 SDValue Arg = ShAmtOp.getOperand(i);
9521 if (Arg.getOpcode() == ISD::UNDEF) continue;
9525 for (; i != NumElts; ++i) {
9526 SDValue Arg = ShAmtOp.getOperand(i);
9527 if (Arg.getOpcode() == ISD::UNDEF) continue;
9528 if (Arg != BaseShAmt) {
9532 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
9533 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
9534 SDValue InVec = ShAmtOp.getOperand(0);
9535 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
9536 unsigned NumElts = InVec.getValueType().getVectorNumElements();
9538 for (; i != NumElts; ++i) {
9539 SDValue Arg = InVec.getOperand(i);
9540 if (Arg.getOpcode() == ISD::UNDEF) continue;
9544 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
9545 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
9546 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex();
9547 if (C->getZExtValue() == SplatIdx)
9548 BaseShAmt = InVec.getOperand(1);
9551 if (BaseShAmt.getNode() == 0)
9552 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
9553 DAG.getIntPtrConstant(0));
9557 // The shift amount is an i32.
9558 if (EltVT.bitsGT(MVT::i32))
9559 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
9560 else if (EltVT.bitsLT(MVT::i32))
9561 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt);
9563 // The shift amount is identical so we can do a vector shift.
9564 SDValue ValOp = N->getOperand(0);
9565 switch (N->getOpcode()) {
9567 llvm_unreachable("Unknown shift opcode!");
9570 if (VT == MVT::v2i64)
9571 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9572 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
9574 if (VT == MVT::v4i32)
9575 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9576 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
9578 if (VT == MVT::v8i16)
9579 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9580 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
9584 if (VT == MVT::v4i32)
9585 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9586 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32),
9588 if (VT == MVT::v8i16)
9589 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9590 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
9594 if (VT == MVT::v2i64)
9595 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9596 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
9598 if (VT == MVT::v4i32)
9599 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9600 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32),
9602 if (VT == MVT::v8i16)
9603 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9604 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
9611 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
9612 TargetLowering::DAGCombinerInfo &DCI,
9613 const X86Subtarget *Subtarget) {
9614 if (DCI.isBeforeLegalizeOps())
9617 EVT VT = N->getValueType(0);
9618 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
9621 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
9622 SDValue N0 = N->getOperand(0);
9623 SDValue N1 = N->getOperand(1);
9624 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
9626 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
9628 if (!N0.hasOneUse() || !N1.hasOneUse())
9631 SDValue ShAmt0 = N0.getOperand(1);
9632 if (ShAmt0.getValueType() != MVT::i8)
9634 SDValue ShAmt1 = N1.getOperand(1);
9635 if (ShAmt1.getValueType() != MVT::i8)
9637 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
9638 ShAmt0 = ShAmt0.getOperand(0);
9639 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
9640 ShAmt1 = ShAmt1.getOperand(0);
9642 DebugLoc DL = N->getDebugLoc();
9643 unsigned Opc = X86ISD::SHLD;
9644 SDValue Op0 = N0.getOperand(0);
9645 SDValue Op1 = N1.getOperand(0);
9646 if (ShAmt0.getOpcode() == ISD::SUB) {
9648 std::swap(Op0, Op1);
9649 std::swap(ShAmt0, ShAmt1);
9652 unsigned Bits = VT.getSizeInBits();
9653 if (ShAmt1.getOpcode() == ISD::SUB) {
9654 SDValue Sum = ShAmt1.getOperand(0);
9655 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
9656 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
9657 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
9658 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
9659 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
9660 return DAG.getNode(Opc, DL, VT,
9662 DAG.getNode(ISD::TRUNCATE, DL,
9665 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
9666 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
9668 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
9669 return DAG.getNode(Opc, DL, VT,
9670 N0.getOperand(0), N1.getOperand(0),
9671 DAG.getNode(ISD::TRUNCATE, DL,
9678 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
9679 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
9680 const X86Subtarget *Subtarget) {
9681 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
9682 // the FP state in cases where an emms may be missing.
9683 // A preferable solution to the general problem is to figure out the right
9684 // places to insert EMMS. This qualifies as a quick hack.
9686 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
9687 StoreSDNode *St = cast<StoreSDNode>(N);
9688 EVT VT = St->getValue().getValueType();
9689 if (VT.getSizeInBits() != 64)
9692 const Function *F = DAG.getMachineFunction().getFunction();
9693 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
9694 bool F64IsLegal = !UseSoftFloat && !NoImplicitFloatOps
9695 && Subtarget->hasSSE2();
9696 if ((VT.isVector() ||
9697 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
9698 isa<LoadSDNode>(St->getValue()) &&
9699 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
9700 St->getChain().hasOneUse() && !St->isVolatile()) {
9701 SDNode* LdVal = St->getValue().getNode();
9703 int TokenFactorIndex = -1;
9704 SmallVector<SDValue, 8> Ops;
9705 SDNode* ChainVal = St->getChain().getNode();
9706 // Must be a store of a load. We currently handle two cases: the load
9707 // is a direct child, and it's under an intervening TokenFactor. It is
9708 // possible to dig deeper under nested TokenFactors.
9709 if (ChainVal == LdVal)
9710 Ld = cast<LoadSDNode>(St->getChain());
9711 else if (St->getValue().hasOneUse() &&
9712 ChainVal->getOpcode() == ISD::TokenFactor) {
9713 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) {
9714 if (ChainVal->getOperand(i).getNode() == LdVal) {
9715 TokenFactorIndex = i;
9716 Ld = cast<LoadSDNode>(St->getValue());
9718 Ops.push_back(ChainVal->getOperand(i));
9722 if (!Ld || !ISD::isNormalLoad(Ld))
9725 // If this is not the MMX case, i.e. we are just turning i64 load/store
9726 // into f64 load/store, avoid the transformation if there are multiple
9727 // uses of the loaded value.
9728 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
9731 DebugLoc LdDL = Ld->getDebugLoc();
9732 DebugLoc StDL = N->getDebugLoc();
9733 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
9734 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
9736 if (Subtarget->is64Bit() || F64IsLegal) {
9737 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
9738 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(),
9739 Ld->getBasePtr(), Ld->getSrcValue(),
9740 Ld->getSrcValueOffset(), Ld->isVolatile(),
9741 Ld->isNonTemporal(), Ld->getAlignment());
9742 SDValue NewChain = NewLd.getValue(1);
9743 if (TokenFactorIndex != -1) {
9744 Ops.push_back(NewChain);
9745 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
9748 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
9749 St->getSrcValue(), St->getSrcValueOffset(),
9750 St->isVolatile(), St->isNonTemporal(),
9751 St->getAlignment());
9754 // Otherwise, lower to two pairs of 32-bit loads / stores.
9755 SDValue LoAddr = Ld->getBasePtr();
9756 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
9757 DAG.getConstant(4, MVT::i32));
9759 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
9760 Ld->getSrcValue(), Ld->getSrcValueOffset(),
9761 Ld->isVolatile(), Ld->isNonTemporal(),
9762 Ld->getAlignment());
9763 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
9764 Ld->getSrcValue(), Ld->getSrcValueOffset()+4,
9765 Ld->isVolatile(), Ld->isNonTemporal(),
9766 MinAlign(Ld->getAlignment(), 4));
9768 SDValue NewChain = LoLd.getValue(1);
9769 if (TokenFactorIndex != -1) {
9770 Ops.push_back(LoLd);
9771 Ops.push_back(HiLd);
9772 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
9776 LoAddr = St->getBasePtr();
9777 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
9778 DAG.getConstant(4, MVT::i32));
9780 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
9781 St->getSrcValue(), St->getSrcValueOffset(),
9782 St->isVolatile(), St->isNonTemporal(),
9783 St->getAlignment());
9784 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
9786 St->getSrcValueOffset() + 4,
9788 St->isNonTemporal(),
9789 MinAlign(St->getAlignment(), 4));
9790 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
9795 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
9796 /// X86ISD::FXOR nodes.
9797 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
9798 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
9799 // F[X]OR(0.0, x) -> x
9800 // F[X]OR(x, 0.0) -> x
9801 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
9802 if (C->getValueAPF().isPosZero())
9803 return N->getOperand(1);
9804 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
9805 if (C->getValueAPF().isPosZero())
9806 return N->getOperand(0);
9810 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
9811 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
9812 // FAND(0.0, x) -> 0.0
9813 // FAND(x, 0.0) -> 0.0
9814 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
9815 if (C->getValueAPF().isPosZero())
9816 return N->getOperand(0);
9817 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
9818 if (C->getValueAPF().isPosZero())
9819 return N->getOperand(1);
9823 static SDValue PerformBTCombine(SDNode *N,
9825 TargetLowering::DAGCombinerInfo &DCI) {
9826 // BT ignores high bits in the bit index operand.
9827 SDValue Op1 = N->getOperand(1);
9828 if (Op1.hasOneUse()) {
9829 unsigned BitWidth = Op1.getValueSizeInBits();
9830 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
9831 APInt KnownZero, KnownOne;
9832 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
9833 !DCI.isBeforeLegalizeOps());
9834 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9835 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
9836 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
9837 DCI.CommitTargetLoweringOpt(TLO);
9842 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
9843 SDValue Op = N->getOperand(0);
9844 if (Op.getOpcode() == ISD::BIT_CONVERT)
9845 Op = Op.getOperand(0);
9846 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
9847 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
9848 VT.getVectorElementType().getSizeInBits() ==
9849 OpVT.getVectorElementType().getSizeInBits()) {
9850 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, Op);
9855 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG) {
9856 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
9857 // (and (i32 x86isd::setcc_carry), 1)
9858 // This eliminates the zext. This transformation is necessary because
9859 // ISD::SETCC is always legalized to i8.
9860 DebugLoc dl = N->getDebugLoc();
9861 SDValue N0 = N->getOperand(0);
9862 EVT VT = N->getValueType(0);
9863 if (N0.getOpcode() == ISD::AND &&
9865 N0.getOperand(0).hasOneUse()) {
9866 SDValue N00 = N0.getOperand(0);
9867 if (N00.getOpcode() != X86ISD::SETCC_CARRY)
9869 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
9870 if (!C || C->getZExtValue() != 1)
9872 return DAG.getNode(ISD::AND, dl, VT,
9873 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
9874 N00.getOperand(0), N00.getOperand(1)),
9875 DAG.getConstant(1, VT));
9881 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
9882 DAGCombinerInfo &DCI) const {
9883 SelectionDAG &DAG = DCI.DAG;
9884 switch (N->getOpcode()) {
9886 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, *this);
9887 case ISD::EXTRACT_VECTOR_ELT:
9888 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, *this);
9889 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget);
9890 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);
9891 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
9894 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget);
9895 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
9896 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
9898 case X86ISD::FOR: return PerformFORCombine(N, DAG);
9899 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
9900 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
9901 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
9902 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG);
9908 /// isTypeDesirableForOp - Return true if the target has native support for
9909 /// the specified value type and it is 'desirable' to use the type for the
9910 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
9911 /// instruction encodings are longer and some i16 instructions are slow.
9912 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
9913 if (!isTypeLegal(VT))
9922 case ISD::SIGN_EXTEND:
9923 case ISD::ZERO_EXTEND:
9924 case ISD::ANY_EXTEND:
9937 static bool MayFoldLoad(SDValue Op) {
9938 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
9941 static bool MayFoldIntoStore(SDValue Op) {
9942 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
9945 /// IsDesirableToPromoteOp - This method query the target whether it is
9946 /// beneficial for dag combiner to promote the specified node. If true, it
9947 /// should return the desired promotion type by reference.
9948 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
9949 EVT VT = Op.getValueType();
9953 bool Promote = false;
9954 bool Commute = false;
9955 switch (Op.getOpcode()) {
9958 LoadSDNode *LD = cast<LoadSDNode>(Op);
9959 // If the non-extending load has a single use and it's not live out, then it
9961 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
9963 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
9964 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
9965 // The only case where we'd want to promote LOAD (rather then it being
9966 // promoted as an operand is when it's only use is liveout.
9967 if (UI->getOpcode() != ISD::CopyToReg)
9974 case ISD::SIGN_EXTEND:
9975 case ISD::ZERO_EXTEND:
9976 case ISD::ANY_EXTEND:
9981 SDValue N0 = Op.getOperand(0);
9982 // Look out for (store (shl (load), x)).
9983 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
9996 SDValue N0 = Op.getOperand(0);
9997 SDValue N1 = Op.getOperand(1);
9998 if (!Commute && MayFoldLoad(N1))
10000 // Avoid disabling potential load folding opportunities.
10001 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
10003 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
10013 //===----------------------------------------------------------------------===//
10014 // X86 Inline Assembly Support
10015 //===----------------------------------------------------------------------===//
10017 static bool LowerToBSwap(CallInst *CI) {
10018 // FIXME: this should verify that we are targetting a 486 or better. If not,
10019 // we will turn this bswap into something that will be lowered to logical ops
10020 // instead of emitting the bswap asm. For now, we don't support 486 or lower
10021 // so don't worry about this.
10023 // Verify this is a simple bswap.
10024 if (CI->getNumArgOperands() != 1 ||
10025 CI->getType() != CI->getArgOperand(0)->getType() ||
10026 !CI->getType()->isIntegerTy())
10029 const IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
10030 if (!Ty || Ty->getBitWidth() % 16 != 0)
10033 // Okay, we can do this xform, do so now.
10034 const Type *Tys[] = { Ty };
10035 Module *M = CI->getParent()->getParent()->getParent();
10036 Constant *Int = Intrinsic::getDeclaration(M, Intrinsic::bswap, Tys, 1);
10038 Value *Op = CI->getArgOperand(0);
10039 Op = CallInst::Create(Int, Op, CI->getName(), CI);
10041 CI->replaceAllUsesWith(Op);
10042 CI->eraseFromParent();
10046 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
10047 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
10048 std::vector<InlineAsm::ConstraintInfo> Constraints = IA->ParseConstraints();
10050 std::string AsmStr = IA->getAsmString();
10052 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
10053 SmallVector<StringRef, 4> AsmPieces;
10054 SplitString(AsmStr, AsmPieces, "\n"); // ; as separator?
10056 switch (AsmPieces.size()) {
10057 default: return false;
10059 AsmStr = AsmPieces[0];
10061 SplitString(AsmStr, AsmPieces, " \t"); // Split with whitespace.
10064 if (AsmPieces.size() == 2 &&
10065 (AsmPieces[0] == "bswap" ||
10066 AsmPieces[0] == "bswapq" ||
10067 AsmPieces[0] == "bswapl") &&
10068 (AsmPieces[1] == "$0" ||
10069 AsmPieces[1] == "${0:q}")) {
10070 // No need to check constraints, nothing other than the equivalent of
10071 // "=r,0" would be valid here.
10072 return LowerToBSwap(CI);
10074 // rorw $$8, ${0:w} --> llvm.bswap.i16
10075 if (CI->getType()->isIntegerTy(16) &&
10076 AsmPieces.size() == 3 &&
10077 (AsmPieces[0] == "rorw" || AsmPieces[0] == "rolw") &&
10078 AsmPieces[1] == "$$8," &&
10079 AsmPieces[2] == "${0:w}" &&
10080 IA->getConstraintString().compare(0, 5, "=r,0,") == 0) {
10082 const std::string &Constraints = IA->getConstraintString();
10083 SplitString(StringRef(Constraints).substr(5), AsmPieces, ",");
10084 std::sort(AsmPieces.begin(), AsmPieces.end());
10085 if (AsmPieces.size() == 4 &&
10086 AsmPieces[0] == "~{cc}" &&
10087 AsmPieces[1] == "~{dirflag}" &&
10088 AsmPieces[2] == "~{flags}" &&
10089 AsmPieces[3] == "~{fpsr}") {
10090 return LowerToBSwap(CI);
10095 if (CI->getType()->isIntegerTy(64) &&
10096 Constraints.size() >= 2 &&
10097 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
10098 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
10099 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
10100 SmallVector<StringRef, 4> Words;
10101 SplitString(AsmPieces[0], Words, " \t");
10102 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%eax") {
10104 SplitString(AsmPieces[1], Words, " \t");
10105 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%edx") {
10107 SplitString(AsmPieces[2], Words, " \t,");
10108 if (Words.size() == 3 && Words[0] == "xchgl" && Words[1] == "%eax" &&
10109 Words[2] == "%edx") {
10110 return LowerToBSwap(CI);
10122 /// getConstraintType - Given a constraint letter, return the type of
10123 /// constraint it is for this target.
10124 X86TargetLowering::ConstraintType
10125 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
10126 if (Constraint.size() == 1) {
10127 switch (Constraint[0]) {
10139 return C_RegisterClass;
10147 return TargetLowering::getConstraintType(Constraint);
10150 /// LowerXConstraint - try to replace an X constraint, which matches anything,
10151 /// with another that has more specific requirements based on the type of the
10152 /// corresponding operand.
10153 const char *X86TargetLowering::
10154 LowerXConstraint(EVT ConstraintVT) const {
10155 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
10156 // 'f' like normal targets.
10157 if (ConstraintVT.isFloatingPoint()) {
10158 if (Subtarget->hasSSE2())
10160 if (Subtarget->hasSSE1())
10164 return TargetLowering::LowerXConstraint(ConstraintVT);
10167 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
10168 /// vector. If it is invalid, don't add anything to Ops.
10169 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
10171 std::vector<SDValue>&Ops,
10172 SelectionDAG &DAG) const {
10173 SDValue Result(0, 0);
10175 switch (Constraint) {
10178 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
10179 if (C->getZExtValue() <= 31) {
10180 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
10186 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
10187 if (C->getZExtValue() <= 63) {
10188 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
10194 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
10195 if ((int8_t)C->getSExtValue() == C->getSExtValue()) {
10196 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
10202 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
10203 if (C->getZExtValue() <= 255) {
10204 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
10210 // 32-bit signed value
10211 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
10212 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
10213 C->getSExtValue())) {
10214 // Widen to 64 bits here to get it sign extended.
10215 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
10218 // FIXME gcc accepts some relocatable values here too, but only in certain
10219 // memory models; it's complicated.
10224 // 32-bit unsigned value
10225 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
10226 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
10227 C->getZExtValue())) {
10228 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
10232 // FIXME gcc accepts some relocatable values here too, but only in certain
10233 // memory models; it's complicated.
10237 // Literal immediates are always ok.
10238 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
10239 // Widen to 64 bits here to get it sign extended.
10240 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
10244 // In any sort of PIC mode addresses need to be computed at runtime by
10245 // adding in a register or some sort of table lookup. These can't
10246 // be used as immediates.
10247 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC() ||
10248 Subtarget->isPICStyleRIPRel())
10251 // If we are in non-pic codegen mode, we allow the address of a global (with
10252 // an optional displacement) to be used with 'i'.
10253 GlobalAddressSDNode *GA = 0;
10254 int64_t Offset = 0;
10256 // Match either (GA), (GA+C), (GA+C1+C2), etc.
10258 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
10259 Offset += GA->getOffset();
10261 } else if (Op.getOpcode() == ISD::ADD) {
10262 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
10263 Offset += C->getZExtValue();
10264 Op = Op.getOperand(0);
10267 } else if (Op.getOpcode() == ISD::SUB) {
10268 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
10269 Offset += -C->getZExtValue();
10270 Op = Op.getOperand(0);
10275 // Otherwise, this isn't something we can handle, reject it.
10279 const GlobalValue *GV = GA->getGlobal();
10280 // If we require an extra load to get this address, as in PIC mode, we
10281 // can't accept it.
10282 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
10283 getTargetMachine())))
10286 Result = DAG.getTargetGlobalAddress(GV, GA->getValueType(0), Offset);
10291 if (Result.getNode()) {
10292 Ops.push_back(Result);
10295 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
10298 std::vector<unsigned> X86TargetLowering::
10299 getRegClassForInlineAsmConstraint(const std::string &Constraint,
10301 if (Constraint.size() == 1) {
10302 // FIXME: not handling fp-stack yet!
10303 switch (Constraint[0]) { // GCC X86 Constraint Letters
10304 default: break; // Unknown constraint letter
10305 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
10306 if (Subtarget->is64Bit()) {
10307 if (VT == MVT::i32)
10308 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX,
10309 X86::ESI, X86::EDI, X86::R8D, X86::R9D,
10310 X86::R10D,X86::R11D,X86::R12D,
10311 X86::R13D,X86::R14D,X86::R15D,
10312 X86::EBP, X86::ESP, 0);
10313 else if (VT == MVT::i16)
10314 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX,
10315 X86::SI, X86::DI, X86::R8W,X86::R9W,
10316 X86::R10W,X86::R11W,X86::R12W,
10317 X86::R13W,X86::R14W,X86::R15W,
10318 X86::BP, X86::SP, 0);
10319 else if (VT == MVT::i8)
10320 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL,
10321 X86::SIL, X86::DIL, X86::R8B,X86::R9B,
10322 X86::R10B,X86::R11B,X86::R12B,
10323 X86::R13B,X86::R14B,X86::R15B,
10324 X86::BPL, X86::SPL, 0);
10326 else if (VT == MVT::i64)
10327 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX,
10328 X86::RSI, X86::RDI, X86::R8, X86::R9,
10329 X86::R10, X86::R11, X86::R12,
10330 X86::R13, X86::R14, X86::R15,
10331 X86::RBP, X86::RSP, 0);
10335 // 32-bit fallthrough
10336 case 'Q': // Q_REGS
10337 if (VT == MVT::i32)
10338 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0);
10339 else if (VT == MVT::i16)
10340 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0);
10341 else if (VT == MVT::i8)
10342 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0);
10343 else if (VT == MVT::i64)
10344 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 0);
10349 return std::vector<unsigned>();
10352 std::pair<unsigned, const TargetRegisterClass*>
10353 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
10355 // First, see if this is a constraint that directly corresponds to an LLVM
10357 if (Constraint.size() == 1) {
10358 // GCC Constraint Letters
10359 switch (Constraint[0]) {
10361 case 'r': // GENERAL_REGS
10362 case 'l': // INDEX_REGS
10364 return std::make_pair(0U, X86::GR8RegisterClass);
10365 if (VT == MVT::i16)
10366 return std::make_pair(0U, X86::GR16RegisterClass);
10367 if (VT == MVT::i32 || !Subtarget->is64Bit())
10368 return std::make_pair(0U, X86::GR32RegisterClass);
10369 return std::make_pair(0U, X86::GR64RegisterClass);
10370 case 'R': // LEGACY_REGS
10372 return std::make_pair(0U, X86::GR8_NOREXRegisterClass);
10373 if (VT == MVT::i16)
10374 return std::make_pair(0U, X86::GR16_NOREXRegisterClass);
10375 if (VT == MVT::i32 || !Subtarget->is64Bit())
10376 return std::make_pair(0U, X86::GR32_NOREXRegisterClass);
10377 return std::make_pair(0U, X86::GR64_NOREXRegisterClass);
10378 case 'f': // FP Stack registers.
10379 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
10380 // value to the correct fpstack register class.
10381 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
10382 return std::make_pair(0U, X86::RFP32RegisterClass);
10383 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
10384 return std::make_pair(0U, X86::RFP64RegisterClass);
10385 return std::make_pair(0U, X86::RFP80RegisterClass);
10386 case 'y': // MMX_REGS if MMX allowed.
10387 if (!Subtarget->hasMMX()) break;
10388 return std::make_pair(0U, X86::VR64RegisterClass);
10389 case 'Y': // SSE_REGS if SSE2 allowed
10390 if (!Subtarget->hasSSE2()) break;
10392 case 'x': // SSE_REGS if SSE1 allowed
10393 if (!Subtarget->hasSSE1()) break;
10395 switch (VT.getSimpleVT().SimpleTy) {
10397 // Scalar SSE types.
10400 return std::make_pair(0U, X86::FR32RegisterClass);
10403 return std::make_pair(0U, X86::FR64RegisterClass);
10411 return std::make_pair(0U, X86::VR128RegisterClass);
10417 // Use the default implementation in TargetLowering to convert the register
10418 // constraint into a member of a register class.
10419 std::pair<unsigned, const TargetRegisterClass*> Res;
10420 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
10422 // Not found as a standard register?
10423 if (Res.second == 0) {
10424 // Map st(0) -> st(7) -> ST0
10425 if (Constraint.size() == 7 && Constraint[0] == '{' &&
10426 tolower(Constraint[1]) == 's' &&
10427 tolower(Constraint[2]) == 't' &&
10428 Constraint[3] == '(' &&
10429 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
10430 Constraint[5] == ')' &&
10431 Constraint[6] == '}') {
10433 Res.first = X86::ST0+Constraint[4]-'0';
10434 Res.second = X86::RFP80RegisterClass;
10438 // GCC allows "st(0)" to be called just plain "st".
10439 if (StringRef("{st}").equals_lower(Constraint)) {
10440 Res.first = X86::ST0;
10441 Res.second = X86::RFP80RegisterClass;
10446 if (StringRef("{flags}").equals_lower(Constraint)) {
10447 Res.first = X86::EFLAGS;
10448 Res.second = X86::CCRRegisterClass;
10452 // 'A' means EAX + EDX.
10453 if (Constraint == "A") {
10454 Res.first = X86::EAX;
10455 Res.second = X86::GR32_ADRegisterClass;
10461 // Otherwise, check to see if this is a register class of the wrong value
10462 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
10463 // turn into {ax},{dx}.
10464 if (Res.second->hasType(VT))
10465 return Res; // Correct type already, nothing to do.
10467 // All of the single-register GCC register classes map their values onto
10468 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
10469 // really want an 8-bit or 32-bit register, map to the appropriate register
10470 // class and return the appropriate register.
10471 if (Res.second == X86::GR16RegisterClass) {
10472 if (VT == MVT::i8) {
10473 unsigned DestReg = 0;
10474 switch (Res.first) {
10476 case X86::AX: DestReg = X86::AL; break;
10477 case X86::DX: DestReg = X86::DL; break;
10478 case X86::CX: DestReg = X86::CL; break;
10479 case X86::BX: DestReg = X86::BL; break;
10482 Res.first = DestReg;
10483 Res.second = X86::GR8RegisterClass;
10485 } else if (VT == MVT::i32) {
10486 unsigned DestReg = 0;
10487 switch (Res.first) {
10489 case X86::AX: DestReg = X86::EAX; break;
10490 case X86::DX: DestReg = X86::EDX; break;
10491 case X86::CX: DestReg = X86::ECX; break;
10492 case X86::BX: DestReg = X86::EBX; break;
10493 case X86::SI: DestReg = X86::ESI; break;
10494 case X86::DI: DestReg = X86::EDI; break;
10495 case X86::BP: DestReg = X86::EBP; break;
10496 case X86::SP: DestReg = X86::ESP; break;
10499 Res.first = DestReg;
10500 Res.second = X86::GR32RegisterClass;
10502 } else if (VT == MVT::i64) {
10503 unsigned DestReg = 0;
10504 switch (Res.first) {
10506 case X86::AX: DestReg = X86::RAX; break;
10507 case X86::DX: DestReg = X86::RDX; break;
10508 case X86::CX: DestReg = X86::RCX; break;
10509 case X86::BX: DestReg = X86::RBX; break;
10510 case X86::SI: DestReg = X86::RSI; break;
10511 case X86::DI: DestReg = X86::RDI; break;
10512 case X86::BP: DestReg = X86::RBP; break;
10513 case X86::SP: DestReg = X86::RSP; break;
10516 Res.first = DestReg;
10517 Res.second = X86::GR64RegisterClass;
10520 } else if (Res.second == X86::FR32RegisterClass ||
10521 Res.second == X86::FR64RegisterClass ||
10522 Res.second == X86::VR128RegisterClass) {
10523 // Handle references to XMM physical registers that got mapped into the
10524 // wrong class. This can happen with constraints like {xmm0} where the
10525 // target independent register mapper will just pick the first match it can
10526 // find, ignoring the required type.
10527 if (VT == MVT::f32)
10528 Res.second = X86::FR32RegisterClass;
10529 else if (VT == MVT::f64)
10530 Res.second = X86::FR64RegisterClass;
10531 else if (X86::VR128RegisterClass->hasType(VT))
10532 Res.second = X86::VR128RegisterClass;