1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
16 #include "X86InstrBuilder.h"
17 #include "X86ISelLowering.h"
18 #include "X86MachineFunctionInfo.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/Constants.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/Function.h"
25 #include "llvm/Intrinsics.h"
26 #include "llvm/ADT/BitVector.h"
27 #include "llvm/ADT/VectorExtras.h"
28 #include "llvm/Analysis/ScalarEvolutionExpressions.h"
29 #include "llvm/CodeGen/CallingConvLower.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/CodeGen/SelectionDAG.h"
35 #include "llvm/Support/MathExtras.h"
36 #include "llvm/Support/Debug.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/ADT/SmallSet.h"
39 #include "llvm/ADT/StringExtras.h"
40 #include "llvm/ParameterAttributes.h"
43 X86TargetLowering::X86TargetLowering(TargetMachine &TM)
44 : TargetLowering(TM) {
45 Subtarget = &TM.getSubtarget<X86Subtarget>();
46 X86ScalarSSEf64 = Subtarget->hasSSE2();
47 X86ScalarSSEf32 = Subtarget->hasSSE1();
48 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
52 RegInfo = TM.getRegisterInfo();
54 // Set up the TargetLowering object.
56 // X86 is weird, it always uses i8 for shift amounts and setcc results.
57 setShiftAmountType(MVT::i8);
58 setSetCCResultType(MVT::i8);
59 setSetCCResultContents(ZeroOrOneSetCCResult);
60 setSchedulingPreference(SchedulingForRegPressure);
61 setShiftAmountFlavor(Mask); // shl X, 32 == shl X, 0
62 setStackPointerRegisterToSaveRestore(X86StackPtr);
64 if (Subtarget->isTargetDarwin()) {
65 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
66 setUseUnderscoreSetJmp(false);
67 setUseUnderscoreLongJmp(false);
68 } else if (Subtarget->isTargetMingw()) {
69 // MS runtime is weird: it exports _setjmp, but longjmp!
70 setUseUnderscoreSetJmp(true);
71 setUseUnderscoreLongJmp(false);
73 setUseUnderscoreSetJmp(true);
74 setUseUnderscoreLongJmp(true);
77 // Set up the register classes.
78 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
79 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
80 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
81 if (Subtarget->is64Bit())
82 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
84 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote);
86 // We don't accept any truncstore of integer registers.
87 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
88 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
89 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
90 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
91 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
92 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
94 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
96 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
97 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
98 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
100 if (Subtarget->is64Bit()) {
101 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
102 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
105 // If SSE i64 SINT_TO_FP is not available, expand i32 UINT_TO_FP.
106 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Expand);
108 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
111 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
113 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
114 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
115 // SSE has no i16 to fp conversion, only i32
116 if (X86ScalarSSEf32) {
117 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
118 // f32 and f64 cases are Legal, f80 case is not
119 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
121 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
122 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
125 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
126 // are Legal, f80 is custom lowered.
127 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
128 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
130 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
132 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
133 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
135 if (X86ScalarSSEf32) {
136 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
137 // f32 and f64 cases are Legal, f80 case is not
138 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
140 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
141 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
144 // Handle FP_TO_UINT by promoting the destination to a larger signed
146 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
147 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
148 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
150 if (Subtarget->is64Bit()) {
151 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
152 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
154 if (X86ScalarSSEf32 && !Subtarget->hasSSE3())
155 // Expand FP_TO_UINT into a select.
156 // FIXME: We would like to use a Custom expander here eventually to do
157 // the optimal thing for SSE vs. the default expansion in the legalizer.
158 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
160 // With SSE3 we can use fisttpll to convert to a signed i64.
161 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
164 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
165 if (!X86ScalarSSEf64) {
166 setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand);
167 setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand);
170 // Scalar integer multiply, multiply-high, divide, and remainder are
171 // lowered to use operations that produce two results, to match the
172 // available instructions. This exposes the two-result form to trivial
173 // CSE, which is able to combine x/y and x%y into a single instruction,
174 // for example. The single-result multiply instructions are introduced
175 // in X86ISelDAGToDAG.cpp, after CSE, for uses where the the high part
177 setOperationAction(ISD::MUL , MVT::i8 , Expand);
178 setOperationAction(ISD::MULHS , MVT::i8 , Expand);
179 setOperationAction(ISD::MULHU , MVT::i8 , Expand);
180 setOperationAction(ISD::SDIV , MVT::i8 , Expand);
181 setOperationAction(ISD::UDIV , MVT::i8 , Expand);
182 setOperationAction(ISD::SREM , MVT::i8 , Expand);
183 setOperationAction(ISD::UREM , MVT::i8 , Expand);
184 setOperationAction(ISD::MUL , MVT::i16 , Expand);
185 setOperationAction(ISD::MULHS , MVT::i16 , Expand);
186 setOperationAction(ISD::MULHU , MVT::i16 , Expand);
187 setOperationAction(ISD::SDIV , MVT::i16 , Expand);
188 setOperationAction(ISD::UDIV , MVT::i16 , Expand);
189 setOperationAction(ISD::SREM , MVT::i16 , Expand);
190 setOperationAction(ISD::UREM , MVT::i16 , Expand);
191 setOperationAction(ISD::MUL , MVT::i32 , Expand);
192 setOperationAction(ISD::MULHS , MVT::i32 , Expand);
193 setOperationAction(ISD::MULHU , MVT::i32 , Expand);
194 setOperationAction(ISD::SDIV , MVT::i32 , Expand);
195 setOperationAction(ISD::UDIV , MVT::i32 , Expand);
196 setOperationAction(ISD::SREM , MVT::i32 , Expand);
197 setOperationAction(ISD::UREM , MVT::i32 , Expand);
198 setOperationAction(ISD::MUL , MVT::i64 , Expand);
199 setOperationAction(ISD::MULHS , MVT::i64 , Expand);
200 setOperationAction(ISD::MULHU , MVT::i64 , Expand);
201 setOperationAction(ISD::SDIV , MVT::i64 , Expand);
202 setOperationAction(ISD::UDIV , MVT::i64 , Expand);
203 setOperationAction(ISD::SREM , MVT::i64 , Expand);
204 setOperationAction(ISD::UREM , MVT::i64 , Expand);
206 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
207 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
208 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
209 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
210 setOperationAction(ISD::MEMMOVE , MVT::Other, Expand);
211 if (Subtarget->is64Bit())
212 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
213 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
214 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
215 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
216 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
217 setOperationAction(ISD::FREM , MVT::f64 , Expand);
218 setOperationAction(ISD::FLT_ROUNDS , MVT::i32 , Custom);
220 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
221 setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
222 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
223 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
224 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
225 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
226 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
227 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
228 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
229 if (Subtarget->is64Bit()) {
230 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
231 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
232 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
235 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
236 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
238 // These should be promoted to a larger select which is supported.
239 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
240 setOperationAction(ISD::SELECT , MVT::i8 , Promote);
241 // X86 wants to expand cmov itself.
242 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
243 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
244 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
245 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
246 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
247 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
248 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
249 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
250 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
251 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
252 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
253 if (Subtarget->is64Bit()) {
254 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
255 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
257 // X86 ret instruction may pop stack.
258 setOperationAction(ISD::RET , MVT::Other, Custom);
259 if (!Subtarget->is64Bit())
260 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
263 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
264 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
265 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
266 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
267 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
268 if (Subtarget->is64Bit()) {
269 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
270 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
271 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
272 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
274 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
275 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
276 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
277 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
278 // X86 wants to expand memset / memcpy itself.
279 setOperationAction(ISD::MEMSET , MVT::Other, Custom);
280 setOperationAction(ISD::MEMCPY , MVT::Other, Custom);
282 // Use the default ISD::LOCATION expansion.
283 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
284 // FIXME - use subtarget debug flags
285 if (!Subtarget->isTargetDarwin() &&
286 !Subtarget->isTargetELF() &&
287 !Subtarget->isTargetCygMing())
288 setOperationAction(ISD::LABEL, MVT::Other, Expand);
290 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
291 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
292 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
293 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
294 if (Subtarget->is64Bit()) {
296 setExceptionPointerRegister(X86::RAX);
297 setExceptionSelectorRegister(X86::RDX);
299 setExceptionPointerRegister(X86::EAX);
300 setExceptionSelectorRegister(X86::EDX);
302 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
304 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
306 setOperationAction(ISD::TRAP, MVT::Other, Legal);
308 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
309 setOperationAction(ISD::VASTART , MVT::Other, Custom);
310 setOperationAction(ISD::VAARG , MVT::Other, Expand);
311 setOperationAction(ISD::VAEND , MVT::Other, Expand);
312 if (Subtarget->is64Bit())
313 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
315 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
317 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
318 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
319 if (Subtarget->is64Bit())
320 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
321 if (Subtarget->isTargetCygMing())
322 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
324 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
326 if (X86ScalarSSEf64) {
327 // f32 and f64 use SSE.
328 // Set up the FP register classes.
329 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
330 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
332 // Use ANDPD to simulate FABS.
333 setOperationAction(ISD::FABS , MVT::f64, Custom);
334 setOperationAction(ISD::FABS , MVT::f32, Custom);
336 // Use XORP to simulate FNEG.
337 setOperationAction(ISD::FNEG , MVT::f64, Custom);
338 setOperationAction(ISD::FNEG , MVT::f32, Custom);
340 // Use ANDPD and ORPD to simulate FCOPYSIGN.
341 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
342 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
344 // We don't support sin/cos/fmod
345 setOperationAction(ISD::FSIN , MVT::f64, Expand);
346 setOperationAction(ISD::FCOS , MVT::f64, Expand);
347 setOperationAction(ISD::FREM , MVT::f64, Expand);
348 setOperationAction(ISD::FSIN , MVT::f32, Expand);
349 setOperationAction(ISD::FCOS , MVT::f32, Expand);
350 setOperationAction(ISD::FREM , MVT::f32, Expand);
352 // Expand FP immediates into loads from the stack, except for the special
354 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
355 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
356 addLegalFPImmediate(APFloat(+0.0)); // xorpd
357 addLegalFPImmediate(APFloat(+0.0f)); // xorps
359 // Floating truncations from f80 and extensions to f80 go through memory.
360 // If optimizing, we lie about this though and handle it in
361 // InstructionSelectPreprocess so that dagcombine2 can hack on these.
363 setConvertAction(MVT::f32, MVT::f80, Expand);
364 setConvertAction(MVT::f64, MVT::f80, Expand);
365 setConvertAction(MVT::f80, MVT::f32, Expand);
366 setConvertAction(MVT::f80, MVT::f64, Expand);
368 } else if (X86ScalarSSEf32) {
369 // Use SSE for f32, x87 for f64.
370 // Set up the FP register classes.
371 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
372 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
374 // Use ANDPS to simulate FABS.
375 setOperationAction(ISD::FABS , MVT::f32, Custom);
377 // Use XORP to simulate FNEG.
378 setOperationAction(ISD::FNEG , MVT::f32, Custom);
380 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
382 // Use ANDPS and ORPS to simulate FCOPYSIGN.
383 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
384 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
386 // We don't support sin/cos/fmod
387 setOperationAction(ISD::FSIN , MVT::f32, Expand);
388 setOperationAction(ISD::FCOS , MVT::f32, Expand);
389 setOperationAction(ISD::FREM , MVT::f32, Expand);
391 // Expand FP immediates into loads from the stack, except for the special
393 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
394 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
395 addLegalFPImmediate(APFloat(+0.0f)); // xorps
396 addLegalFPImmediate(APFloat(+0.0)); // FLD0
397 addLegalFPImmediate(APFloat(+1.0)); // FLD1
398 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
399 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
401 // SSE <-> X87 conversions go through memory. If optimizing, we lie about
402 // this though and handle it in InstructionSelectPreprocess so that
403 // dagcombine2 can hack on these.
405 setConvertAction(MVT::f32, MVT::f64, Expand);
406 setConvertAction(MVT::f32, MVT::f80, Expand);
407 setConvertAction(MVT::f80, MVT::f32, Expand);
408 setConvertAction(MVT::f64, MVT::f32, Expand);
409 // And x87->x87 truncations also.
410 setConvertAction(MVT::f80, MVT::f64, Expand);
414 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
415 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
418 // f32 and f64 in x87.
419 // Set up the FP register classes.
420 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
421 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
423 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
424 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
425 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
426 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
428 // Floating truncations go through memory. If optimizing, we lie about
429 // this though and handle it in InstructionSelectPreprocess so that
430 // dagcombine2 can hack on these.
432 setConvertAction(MVT::f80, MVT::f32, Expand);
433 setConvertAction(MVT::f64, MVT::f32, Expand);
434 setConvertAction(MVT::f80, MVT::f64, Expand);
438 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
439 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
442 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
443 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
444 addLegalFPImmediate(APFloat(+0.0)); // FLD0
445 addLegalFPImmediate(APFloat(+1.0)); // FLD1
446 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
447 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
448 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
449 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
450 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
451 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
454 // Long double always uses X87.
455 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
456 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
457 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
459 setOperationAction(ISD::ConstantFP, MVT::f80, Expand);
460 APFloat TmpFlt(+0.0);
461 TmpFlt.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven);
462 addLegalFPImmediate(TmpFlt); // FLD0
464 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
465 APFloat TmpFlt2(+1.0);
466 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven);
467 addLegalFPImmediate(TmpFlt2); // FLD1
468 TmpFlt2.changeSign();
469 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
473 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
474 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
477 // Always use a library call for pow.
478 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
479 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
480 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
482 // First set operation action for all vector types to expand. Then we
483 // will selectively turn on ones that can be effectively codegen'd.
484 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
485 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
486 setOperationAction(ISD::ADD , (MVT::ValueType)VT, Expand);
487 setOperationAction(ISD::SUB , (MVT::ValueType)VT, Expand);
488 setOperationAction(ISD::FADD, (MVT::ValueType)VT, Expand);
489 setOperationAction(ISD::FNEG, (MVT::ValueType)VT, Expand);
490 setOperationAction(ISD::FSUB, (MVT::ValueType)VT, Expand);
491 setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand);
492 setOperationAction(ISD::FMUL, (MVT::ValueType)VT, Expand);
493 setOperationAction(ISD::SDIV, (MVT::ValueType)VT, Expand);
494 setOperationAction(ISD::UDIV, (MVT::ValueType)VT, Expand);
495 setOperationAction(ISD::FDIV, (MVT::ValueType)VT, Expand);
496 setOperationAction(ISD::SREM, (MVT::ValueType)VT, Expand);
497 setOperationAction(ISD::UREM, (MVT::ValueType)VT, Expand);
498 setOperationAction(ISD::LOAD, (MVT::ValueType)VT, Expand);
499 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Expand);
500 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
501 setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
502 setOperationAction(ISD::FABS, (MVT::ValueType)VT, Expand);
503 setOperationAction(ISD::FSIN, (MVT::ValueType)VT, Expand);
504 setOperationAction(ISD::FCOS, (MVT::ValueType)VT, Expand);
505 setOperationAction(ISD::FREM, (MVT::ValueType)VT, Expand);
506 setOperationAction(ISD::FPOWI, (MVT::ValueType)VT, Expand);
507 setOperationAction(ISD::FSQRT, (MVT::ValueType)VT, Expand);
508 setOperationAction(ISD::FCOPYSIGN, (MVT::ValueType)VT, Expand);
509 setOperationAction(ISD::SMUL_LOHI, (MVT::ValueType)VT, Expand);
510 setOperationAction(ISD::UMUL_LOHI, (MVT::ValueType)VT, Expand);
511 setOperationAction(ISD::SDIVREM, (MVT::ValueType)VT, Expand);
512 setOperationAction(ISD::UDIVREM, (MVT::ValueType)VT, Expand);
513 setOperationAction(ISD::FPOW, (MVT::ValueType)VT, Expand);
514 setOperationAction(ISD::CTPOP, (MVT::ValueType)VT, Expand);
515 setOperationAction(ISD::CTTZ, (MVT::ValueType)VT, Expand);
516 setOperationAction(ISD::CTLZ, (MVT::ValueType)VT, Expand);
517 setOperationAction(ISD::SHL, (MVT::ValueType)VT, Expand);
518 setOperationAction(ISD::SRA, (MVT::ValueType)VT, Expand);
519 setOperationAction(ISD::SRL, (MVT::ValueType)VT, Expand);
520 setOperationAction(ISD::ROTL, (MVT::ValueType)VT, Expand);
521 setOperationAction(ISD::ROTR, (MVT::ValueType)VT, Expand);
522 setOperationAction(ISD::BSWAP, (MVT::ValueType)VT, Expand);
525 if (Subtarget->hasMMX()) {
526 addRegisterClass(MVT::v8i8, X86::VR64RegisterClass);
527 addRegisterClass(MVT::v4i16, X86::VR64RegisterClass);
528 addRegisterClass(MVT::v2i32, X86::VR64RegisterClass);
529 addRegisterClass(MVT::v1i64, X86::VR64RegisterClass);
531 // FIXME: add MMX packed arithmetics
533 setOperationAction(ISD::ADD, MVT::v8i8, Legal);
534 setOperationAction(ISD::ADD, MVT::v4i16, Legal);
535 setOperationAction(ISD::ADD, MVT::v2i32, Legal);
536 setOperationAction(ISD::ADD, MVT::v1i64, Legal);
538 setOperationAction(ISD::SUB, MVT::v8i8, Legal);
539 setOperationAction(ISD::SUB, MVT::v4i16, Legal);
540 setOperationAction(ISD::SUB, MVT::v2i32, Legal);
541 setOperationAction(ISD::SUB, MVT::v1i64, Legal);
543 setOperationAction(ISD::MULHS, MVT::v4i16, Legal);
544 setOperationAction(ISD::MUL, MVT::v4i16, Legal);
546 setOperationAction(ISD::AND, MVT::v8i8, Promote);
547 AddPromotedToType (ISD::AND, MVT::v8i8, MVT::v1i64);
548 setOperationAction(ISD::AND, MVT::v4i16, Promote);
549 AddPromotedToType (ISD::AND, MVT::v4i16, MVT::v1i64);
550 setOperationAction(ISD::AND, MVT::v2i32, Promote);
551 AddPromotedToType (ISD::AND, MVT::v2i32, MVT::v1i64);
552 setOperationAction(ISD::AND, MVT::v1i64, Legal);
554 setOperationAction(ISD::OR, MVT::v8i8, Promote);
555 AddPromotedToType (ISD::OR, MVT::v8i8, MVT::v1i64);
556 setOperationAction(ISD::OR, MVT::v4i16, Promote);
557 AddPromotedToType (ISD::OR, MVT::v4i16, MVT::v1i64);
558 setOperationAction(ISD::OR, MVT::v2i32, Promote);
559 AddPromotedToType (ISD::OR, MVT::v2i32, MVT::v1i64);
560 setOperationAction(ISD::OR, MVT::v1i64, Legal);
562 setOperationAction(ISD::XOR, MVT::v8i8, Promote);
563 AddPromotedToType (ISD::XOR, MVT::v8i8, MVT::v1i64);
564 setOperationAction(ISD::XOR, MVT::v4i16, Promote);
565 AddPromotedToType (ISD::XOR, MVT::v4i16, MVT::v1i64);
566 setOperationAction(ISD::XOR, MVT::v2i32, Promote);
567 AddPromotedToType (ISD::XOR, MVT::v2i32, MVT::v1i64);
568 setOperationAction(ISD::XOR, MVT::v1i64, Legal);
570 setOperationAction(ISD::LOAD, MVT::v8i8, Promote);
571 AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v1i64);
572 setOperationAction(ISD::LOAD, MVT::v4i16, Promote);
573 AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v1i64);
574 setOperationAction(ISD::LOAD, MVT::v2i32, Promote);
575 AddPromotedToType (ISD::LOAD, MVT::v2i32, MVT::v1i64);
576 setOperationAction(ISD::LOAD, MVT::v1i64, Legal);
578 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom);
579 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom);
580 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Custom);
581 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom);
583 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
584 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
585 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom);
586 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1i64, Custom);
588 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Custom);
589 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom);
590 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Custom);
591 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom);
594 if (Subtarget->hasSSE1()) {
595 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
597 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
598 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
599 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
600 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
601 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
602 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
603 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
604 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
605 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
606 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
607 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
610 if (Subtarget->hasSSE2()) {
611 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
612 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
613 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
614 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
615 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
617 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
618 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
619 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
620 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
621 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
622 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
623 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
624 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
625 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
626 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
627 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
628 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
629 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
630 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
631 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
633 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
634 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
635 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
636 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
637 // Implement v4f32 insert_vector_elt in terms of SSE2 v8i16 ones.
638 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
640 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
641 for (unsigned VT = (unsigned)MVT::v16i8; VT != (unsigned)MVT::v2i64; VT++) {
642 // Do not attempt to custom lower non-power-of-2 vectors
643 if (!isPowerOf2_32(MVT::getVectorNumElements(VT)))
645 setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Custom);
646 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Custom);
647 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Custom);
649 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
650 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
651 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
652 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
653 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
654 if (Subtarget->is64Bit())
655 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
657 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
658 for (unsigned VT = (unsigned)MVT::v16i8; VT != (unsigned)MVT::v2i64; VT++) {
659 setOperationAction(ISD::AND, (MVT::ValueType)VT, Promote);
660 AddPromotedToType (ISD::AND, (MVT::ValueType)VT, MVT::v2i64);
661 setOperationAction(ISD::OR, (MVT::ValueType)VT, Promote);
662 AddPromotedToType (ISD::OR, (MVT::ValueType)VT, MVT::v2i64);
663 setOperationAction(ISD::XOR, (MVT::ValueType)VT, Promote);
664 AddPromotedToType (ISD::XOR, (MVT::ValueType)VT, MVT::v2i64);
665 setOperationAction(ISD::LOAD, (MVT::ValueType)VT, Promote);
666 AddPromotedToType (ISD::LOAD, (MVT::ValueType)VT, MVT::v2i64);
667 setOperationAction(ISD::SELECT, (MVT::ValueType)VT, Promote);
668 AddPromotedToType (ISD::SELECT, (MVT::ValueType)VT, MVT::v2i64);
671 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
673 // Custom lower v2i64 and v2f64 selects.
674 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
675 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
676 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
677 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
680 // We want to custom lower some of our intrinsics.
681 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
683 // We have target-specific dag combine patterns for the following nodes:
684 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
685 setTargetDAGCombine(ISD::SELECT);
687 computeRegisterProperties();
689 // FIXME: These should be based on subtarget info. Plus, the values should
690 // be smaller when we are in optimizing for size mode.
691 maxStoresPerMemset = 16; // For %llvm.memset -> sequence of stores
692 maxStoresPerMemcpy = 16; // For %llvm.memcpy -> sequence of stores
693 maxStoresPerMemmove = 16; // For %llvm.memmove -> sequence of stores
694 allowUnalignedMemoryAccesses = true; // x86 supports it!
697 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
698 /// the desired ByVal argument alignment.
699 static void getMaxByValAlign(const Type *Ty, unsigned &MaxAlign) {
702 if (const VectorType *VTy = dyn_cast<VectorType>(Ty)) {
703 if (VTy->getBitWidth() == 128)
705 else if (VTy->getBitWidth() == 64)
708 } else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
709 unsigned EltAlign = 0;
710 getMaxByValAlign(ATy->getElementType(), EltAlign);
711 if (EltAlign > MaxAlign)
713 } else if (const StructType *STy = dyn_cast<StructType>(Ty)) {
714 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
715 unsigned EltAlign = 0;
716 getMaxByValAlign(STy->getElementType(i), EltAlign);
717 if (EltAlign > MaxAlign)
726 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
727 /// function arguments in the caller parameter area. For X86, aggregates
728 /// that contains are placed at 16-byte boundaries while the rest are at
729 /// 4-byte boundaries.
730 unsigned X86TargetLowering::getByValTypeAlignment(const Type *Ty) const {
731 if (Subtarget->is64Bit())
732 return getTargetData()->getABITypeAlignment(Ty);
734 getMaxByValAlign(Ty, Align);
738 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
740 SDOperand X86TargetLowering::getPICJumpTableRelocBase(SDOperand Table,
741 SelectionDAG &DAG) const {
742 if (usesGlobalOffsetTable())
743 return DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, getPointerTy());
744 if (!Subtarget->isPICStyleRIPRel())
745 return DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy());
749 //===----------------------------------------------------------------------===//
750 // Return Value Calling Convention Implementation
751 //===----------------------------------------------------------------------===//
753 #include "X86GenCallingConv.inc"
755 /// GetPossiblePreceedingTailCall - Get preceeding X86ISD::TAILCALL node if it
756 /// exists skip possible ISD:TokenFactor.
757 static SDOperand GetPossiblePreceedingTailCall(SDOperand Chain) {
758 if (Chain.getOpcode() == X86ISD::TAILCALL) {
760 } else if (Chain.getOpcode() == ISD::TokenFactor) {
761 if (Chain.getNumOperands() &&
762 Chain.getOperand(0).getOpcode() == X86ISD::TAILCALL)
763 return Chain.getOperand(0);
768 /// LowerRET - Lower an ISD::RET node.
769 SDOperand X86TargetLowering::LowerRET(SDOperand Op, SelectionDAG &DAG) {
770 assert((Op.getNumOperands() & 1) == 1 && "ISD::RET should have odd # args");
772 SmallVector<CCValAssign, 16> RVLocs;
773 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
774 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
775 CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
776 CCInfo.AnalyzeReturn(Op.Val, RetCC_X86);
778 // If this is the first return lowered for this function, add the regs to the
779 // liveout set for the function.
780 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
781 for (unsigned i = 0; i != RVLocs.size(); ++i)
782 if (RVLocs[i].isRegLoc())
783 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
785 SDOperand Chain = Op.getOperand(0);
787 // Handle tail call return.
788 Chain = GetPossiblePreceedingTailCall(Chain);
789 if (Chain.getOpcode() == X86ISD::TAILCALL) {
790 SDOperand TailCall = Chain;
791 SDOperand TargetAddress = TailCall.getOperand(1);
792 SDOperand StackAdjustment = TailCall.getOperand(2);
793 assert(((TargetAddress.getOpcode() == ISD::Register &&
794 (cast<RegisterSDNode>(TargetAddress)->getReg() == X86::ECX ||
795 cast<RegisterSDNode>(TargetAddress)->getReg() == X86::R9)) ||
796 TargetAddress.getOpcode() == ISD::TargetExternalSymbol ||
797 TargetAddress.getOpcode() == ISD::TargetGlobalAddress) &&
798 "Expecting an global address, external symbol, or register");
799 assert(StackAdjustment.getOpcode() == ISD::Constant &&
800 "Expecting a const value");
802 SmallVector<SDOperand,8> Operands;
803 Operands.push_back(Chain.getOperand(0));
804 Operands.push_back(TargetAddress);
805 Operands.push_back(StackAdjustment);
806 // Copy registers used by the call. Last operand is a flag so it is not
808 for (unsigned i=3; i < TailCall.getNumOperands()-1; i++) {
809 Operands.push_back(Chain.getOperand(i));
811 return DAG.getNode(X86ISD::TC_RETURN, MVT::Other, &Operands[0],
818 // Copy the result values into the output registers.
819 if (RVLocs.size() != 1 || !RVLocs[0].isRegLoc() ||
820 RVLocs[0].getLocReg() != X86::ST0) {
821 for (unsigned i = 0; i != RVLocs.size(); ++i) {
822 CCValAssign &VA = RVLocs[i];
823 assert(VA.isRegLoc() && "Can only return in registers!");
824 Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1),
826 Flag = Chain.getValue(1);
829 // We need to handle a destination of ST0 specially, because it isn't really
831 SDOperand Value = Op.getOperand(1);
833 // an XMM register onto the fp-stack. Do this with an FP_EXTEND to f80.
834 // This will get legalized into a load/store if it can't get optimized away.
835 if (isScalarFPTypeInSSEReg(RVLocs[0].getValVT()))
836 Value = DAG.getNode(ISD::FP_EXTEND, MVT::f80, Value);
838 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
839 SDOperand Ops[] = { Chain, Value };
840 Chain = DAG.getNode(X86ISD::FP_SET_RESULT, Tys, Ops, 2);
841 Flag = Chain.getValue(1);
844 SDOperand BytesToPop = DAG.getConstant(getBytesToPopOnReturn(), MVT::i16);
846 return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, Chain, BytesToPop, Flag);
848 return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, Chain, BytesToPop);
852 /// LowerCallResult - Lower the result values of an ISD::CALL into the
853 /// appropriate copies out of appropriate physical registers. This assumes that
854 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
855 /// being lowered. The returns a SDNode with the same number of values as the
857 SDNode *X86TargetLowering::
858 LowerCallResult(SDOperand Chain, SDOperand InFlag, SDNode *TheCall,
859 unsigned CallingConv, SelectionDAG &DAG) {
861 // Assign locations to each value returned by this call.
862 SmallVector<CCValAssign, 16> RVLocs;
863 bool isVarArg = cast<ConstantSDNode>(TheCall->getOperand(2))->getValue() != 0;
864 CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs);
865 CCInfo.AnalyzeCallResult(TheCall, RetCC_X86);
867 SmallVector<SDOperand, 8> ResultVals;
869 // Copy all of the result registers out of their specified physreg.
870 if (RVLocs.size() != 1 || RVLocs[0].getLocReg() != X86::ST0) {
871 for (unsigned i = 0; i != RVLocs.size(); ++i) {
872 Chain = DAG.getCopyFromReg(Chain, RVLocs[i].getLocReg(),
873 RVLocs[i].getValVT(), InFlag).getValue(1);
874 InFlag = Chain.getValue(2);
875 ResultVals.push_back(Chain.getValue(0));
878 // Copies from the FP stack are special, as ST0 isn't a valid register
879 // before the fp stackifier runs.
881 // Copy ST0 into an RFP register with FP_GET_RESULT. If this will end up
882 // in an SSE register, copy it out as F80 and do a truncate, otherwise use
883 // the specified value type.
884 MVT::ValueType GetResultTy = RVLocs[0].getValVT();
885 if (isScalarFPTypeInSSEReg(GetResultTy))
886 GetResultTy = MVT::f80;
887 SDVTList Tys = DAG.getVTList(GetResultTy, MVT::Other, MVT::Flag);
889 SDOperand GROps[] = { Chain, InFlag };
890 SDOperand RetVal = DAG.getNode(X86ISD::FP_GET_RESULT, Tys, GROps, 2);
891 Chain = RetVal.getValue(1);
892 InFlag = RetVal.getValue(2);
894 // If we want the result in an SSE register, use an FP_TRUNCATE to get it
896 if (GetResultTy != RVLocs[0].getValVT())
897 RetVal = DAG.getNode(ISD::FP_ROUND, RVLocs[0].getValVT(), RetVal,
898 // This truncation won't change the value.
899 DAG.getIntPtrConstant(1));
901 ResultVals.push_back(RetVal);
904 // Merge everything together with a MERGE_VALUES node.
905 ResultVals.push_back(Chain);
906 return DAG.getNode(ISD::MERGE_VALUES, TheCall->getVTList(),
907 &ResultVals[0], ResultVals.size()).Val;
911 //===----------------------------------------------------------------------===//
912 // C & StdCall & Fast Calling Convention implementation
913 //===----------------------------------------------------------------------===//
914 // StdCall calling convention seems to be standard for many Windows' API
915 // routines and around. It differs from C calling convention just a little:
916 // callee should clean up the stack, not caller. Symbols should be also
917 // decorated in some fancy way :) It doesn't support any vector arguments.
918 // For info on fast calling convention see Fast Calling Convention (tail call)
919 // implementation LowerX86_32FastCCCallTo.
921 /// AddLiveIn - This helper function adds the specified physical register to the
922 /// MachineFunction as a live in value. It also creates a corresponding virtual
924 static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
925 const TargetRegisterClass *RC) {
926 assert(RC->contains(PReg) && "Not the correct regclass!");
927 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
928 MF.getRegInfo().addLiveIn(PReg, VReg);
932 // Determines whether a CALL node uses struct return semantics.
933 static bool CallIsStructReturn(SDOperand Op) {
934 unsigned NumOps = (Op.getNumOperands() - 5) / 2;
938 ConstantSDNode *Flags = cast<ConstantSDNode>(Op.getOperand(6));
939 return Flags->getValue() & ISD::ParamFlags::StructReturn;
942 // Determines whether a FORMAL_ARGUMENTS node uses struct return semantics.
943 static bool ArgsAreStructReturn(SDOperand Op) {
944 unsigned NumArgs = Op.Val->getNumValues() - 1;
948 ConstantSDNode *Flags = cast<ConstantSDNode>(Op.getOperand(3));
949 return Flags->getValue() & ISD::ParamFlags::StructReturn;
952 // Determines whether a CALL or FORMAL_ARGUMENTS node requires the callee to pop
953 // its own arguments. Callee pop is necessary to support tail calls.
954 bool X86TargetLowering::IsCalleePop(SDOperand Op) {
955 bool IsVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
959 switch (cast<ConstantSDNode>(Op.getOperand(1))->getValue()) {
962 case CallingConv::X86_StdCall:
963 return !Subtarget->is64Bit();
964 case CallingConv::X86_FastCall:
965 return !Subtarget->is64Bit();
966 case CallingConv::Fast:
967 return PerformTailCallOpt;
971 // Selects the correct CCAssignFn for a CALL or FORMAL_ARGUMENTS node.
972 CCAssignFn *X86TargetLowering::CCAssignFnForNode(SDOperand Op) const {
973 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
975 if (Subtarget->is64Bit())
976 if (CC == CallingConv::Fast && PerformTailCallOpt)
977 return CC_X86_64_TailCall;
981 if (CC == CallingConv::X86_FastCall)
982 return CC_X86_32_FastCall;
983 else if (CC == CallingConv::Fast && PerformTailCallOpt)
984 return CC_X86_32_TailCall;
989 // Selects the appropriate decoration to apply to a MachineFunction containing a
990 // given FORMAL_ARGUMENTS node.
992 X86TargetLowering::NameDecorationForFORMAL_ARGUMENTS(SDOperand Op) {
993 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
994 if (CC == CallingConv::X86_FastCall)
996 else if (CC == CallingConv::X86_StdCall)
1002 // IsPossiblyOverwrittenArgumentOfTailCall - Check if the operand could possibly
1003 // be overwritten when lowering the outgoing arguments in a tail call. Currently
1004 // the implementation of this call is very conservative and assumes all
1005 // arguments sourcing from FORMAL_ARGUMENTS or a CopyFromReg with virtual
1006 // registers would be overwritten by direct lowering.
1007 // Possible improvement:
1008 // Check FORMAL_ARGUMENTS corresponding MERGE_VALUES for CopyFromReg nodes
1009 // indicating inreg passed arguments which also need not be lowered to a safe
1011 static bool IsPossiblyOverwrittenArgumentOfTailCall(SDOperand Op) {
1012 RegisterSDNode * OpReg = NULL;
1013 if (Op.getOpcode() == ISD::FORMAL_ARGUMENTS ||
1014 (Op.getOpcode()== ISD::CopyFromReg &&
1015 (OpReg = cast<RegisterSDNode>(Op.getOperand(1))) &&
1016 OpReg->getReg() >= MRegisterInfo::FirstVirtualRegister))
1021 // CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1022 // by "Src" to address "Dst" with size and alignment information specified by
1023 // the specific parameter attribute. The copy will be passed as a byval function
1026 CreateCopyOfByValArgument(SDOperand Src, SDOperand Dst, SDOperand Chain,
1027 unsigned Flags, SelectionDAG &DAG) {
1028 unsigned Align = 1 <<
1029 ((Flags & ISD::ParamFlags::ByValAlign) >> ISD::ParamFlags::ByValAlignOffs);
1030 unsigned Size = (Flags & ISD::ParamFlags::ByValSize) >>
1031 ISD::ParamFlags::ByValSizeOffs;
1032 SDOperand AlignNode = DAG.getConstant(Align, MVT::i32);
1033 SDOperand SizeNode = DAG.getConstant(Size, MVT::i32);
1034 SDOperand AlwaysInline = DAG.getConstant(1, MVT::i32);
1035 return DAG.getMemcpy(Chain, Dst, Src, SizeNode, AlignNode, AlwaysInline);
1038 SDOperand X86TargetLowering::LowerMemArgument(SDOperand Op, SelectionDAG &DAG,
1039 const CCValAssign &VA,
1040 MachineFrameInfo *MFI,
1041 SDOperand Root, unsigned i) {
1042 // Create the nodes corresponding to a load from this parameter slot.
1043 unsigned Flags = cast<ConstantSDNode>(Op.getOperand(3 + i))->getValue();
1044 bool isByVal = Flags & ISD::ParamFlags::ByVal;
1046 // FIXME: For now, all byval parameter objects are marked mutable. This
1047 // can be changed with more analysis.
1048 int FI = MFI->CreateFixedObject(MVT::getSizeInBits(VA.getValVT())/8,
1049 VA.getLocMemOffset(), !isByVal);
1050 SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy());
1053 return DAG.getLoad(VA.getValVT(), Root, FIN, NULL, 0);
1057 X86TargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) {
1058 MachineFunction &MF = DAG.getMachineFunction();
1059 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1061 const Function* Fn = MF.getFunction();
1062 if (Fn->hasExternalLinkage() &&
1063 Subtarget->isTargetCygMing() &&
1064 Fn->getName() == "main")
1065 FuncInfo->setForceFramePointer(true);
1067 // Decorate the function name.
1068 FuncInfo->setDecorationStyle(NameDecorationForFORMAL_ARGUMENTS(Op));
1070 MachineFrameInfo *MFI = MF.getFrameInfo();
1071 SDOperand Root = Op.getOperand(0);
1072 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1073 unsigned CC = MF.getFunction()->getCallingConv();
1074 bool Is64Bit = Subtarget->is64Bit();
1076 assert(!(isVarArg && CC == CallingConv::Fast) &&
1077 "Var args not supported with calling convention fastcc");
1079 // Assign locations to all of the incoming arguments.
1080 SmallVector<CCValAssign, 16> ArgLocs;
1081 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
1082 CCInfo.AnalyzeFormalArguments(Op.Val, CCAssignFnForNode(Op));
1084 SmallVector<SDOperand, 8> ArgValues;
1085 unsigned LastVal = ~0U;
1086 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1087 CCValAssign &VA = ArgLocs[i];
1088 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1090 assert(VA.getValNo() != LastVal &&
1091 "Don't support value assigned to multiple locs yet");
1092 LastVal = VA.getValNo();
1094 if (VA.isRegLoc()) {
1095 MVT::ValueType RegVT = VA.getLocVT();
1096 TargetRegisterClass *RC;
1097 if (RegVT == MVT::i32)
1098 RC = X86::GR32RegisterClass;
1099 else if (Is64Bit && RegVT == MVT::i64)
1100 RC = X86::GR64RegisterClass;
1101 else if (Is64Bit && RegVT == MVT::f32)
1102 RC = X86::FR32RegisterClass;
1103 else if (Is64Bit && RegVT == MVT::f64)
1104 RC = X86::FR64RegisterClass;
1106 assert(MVT::isVector(RegVT));
1107 if (Is64Bit && MVT::getSizeInBits(RegVT) == 64) {
1108 RC = X86::GR64RegisterClass; // MMX values are passed in GPRs.
1111 RC = X86::VR128RegisterClass;
1114 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
1115 SDOperand ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT);
1117 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1118 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1120 if (VA.getLocInfo() == CCValAssign::SExt)
1121 ArgValue = DAG.getNode(ISD::AssertSext, RegVT, ArgValue,
1122 DAG.getValueType(VA.getValVT()));
1123 else if (VA.getLocInfo() == CCValAssign::ZExt)
1124 ArgValue = DAG.getNode(ISD::AssertZext, RegVT, ArgValue,
1125 DAG.getValueType(VA.getValVT()));
1127 if (VA.getLocInfo() != CCValAssign::Full)
1128 ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue);
1130 // Handle MMX values passed in GPRs.
1131 if (Is64Bit && RegVT != VA.getLocVT() && RC == X86::GR64RegisterClass &&
1132 MVT::getSizeInBits(RegVT) == 64)
1133 ArgValue = DAG.getNode(ISD::BIT_CONVERT, VA.getLocVT(), ArgValue);
1135 ArgValues.push_back(ArgValue);
1137 assert(VA.isMemLoc());
1138 ArgValues.push_back(LowerMemArgument(Op, DAG, VA, MFI, Root, i));
1142 unsigned StackSize = CCInfo.getNextStackOffset();
1143 // align stack specially for tail calls
1144 if (CC == CallingConv::Fast)
1145 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1147 // If the function takes variable number of arguments, make a frame index for
1148 // the start of the first vararg value... for expansion of llvm.va_start.
1150 if (Is64Bit || CC != CallingConv::X86_FastCall) {
1151 VarArgsFrameIndex = MFI->CreateFixedObject(1, StackSize);
1154 static const unsigned GPR64ArgRegs[] = {
1155 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1157 static const unsigned XMMArgRegs[] = {
1158 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1159 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1162 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs, 6);
1163 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
1165 // For X86-64, if there are vararg parameters that are passed via
1166 // registers, then we must store them to their spots on the stack so they
1167 // may be loaded by deferencing the result of va_next.
1168 VarArgsGPOffset = NumIntRegs * 8;
1169 VarArgsFPOffset = 6 * 8 + NumXMMRegs * 16;
1170 RegSaveFrameIndex = MFI->CreateStackObject(6 * 8 + 8 * 16, 16);
1172 // Store the integer parameter registers.
1173 SmallVector<SDOperand, 8> MemOps;
1174 SDOperand RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
1175 SDOperand FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN,
1176 DAG.getIntPtrConstant(VarArgsGPOffset));
1177 for (; NumIntRegs != 6; ++NumIntRegs) {
1178 unsigned VReg = AddLiveIn(MF, GPR64ArgRegs[NumIntRegs],
1179 X86::GR64RegisterClass);
1180 SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::i64);
1181 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
1182 MemOps.push_back(Store);
1183 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
1184 DAG.getIntPtrConstant(8));
1187 // Now store the XMM (fp + vector) parameter registers.
1188 FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN,
1189 DAG.getIntPtrConstant(VarArgsFPOffset));
1190 for (; NumXMMRegs != 8; ++NumXMMRegs) {
1191 unsigned VReg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs],
1192 X86::VR128RegisterClass);
1193 SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::v4f32);
1194 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
1195 MemOps.push_back(Store);
1196 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
1197 DAG.getIntPtrConstant(16));
1199 if (!MemOps.empty())
1200 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
1201 &MemOps[0], MemOps.size());
1205 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
1206 // arguments and the arguments after the retaddr has been pushed are
1208 if (!Is64Bit && CC == CallingConv::X86_FastCall &&
1209 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWindows() &&
1210 (StackSize & 7) == 0)
1213 ArgValues.push_back(Root);
1215 // Some CCs need callee pop.
1216 if (IsCalleePop(Op)) {
1217 BytesToPopOnReturn = StackSize; // Callee pops everything.
1218 BytesCallerReserves = 0;
1220 BytesToPopOnReturn = 0; // Callee pops nothing.
1221 // If this is an sret function, the return should pop the hidden pointer.
1222 if (!Is64Bit && ArgsAreStructReturn(Op))
1223 BytesToPopOnReturn = 4;
1224 BytesCallerReserves = StackSize;
1228 RegSaveFrameIndex = 0xAAAAAAA; // RegSaveFrameIndex is X86-64 only.
1229 if (CC == CallingConv::X86_FastCall)
1230 VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs.
1233 FuncInfo->setBytesToPopOnReturn(BytesToPopOnReturn);
1235 // Return the new list of results.
1236 return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(),
1237 &ArgValues[0], ArgValues.size()).getValue(Op.ResNo);
1241 X86TargetLowering::LowerMemOpCallTo(SDOperand Op, SelectionDAG &DAG,
1242 const SDOperand &StackPtr,
1243 const CCValAssign &VA,
1246 SDOperand PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset());
1247 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
1248 SDOperand FlagsOp = Op.getOperand(6+2*VA.getValNo());
1249 unsigned Flags = cast<ConstantSDNode>(FlagsOp)->getValue();
1250 if (Flags & ISD::ParamFlags::ByVal) {
1251 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG);
1253 return DAG.getStore(Chain, Arg, PtrOff, NULL, 0);
1256 SDOperand X86TargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) {
1257 MachineFunction &MF = DAG.getMachineFunction();
1258 SDOperand Chain = Op.getOperand(0);
1259 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
1260 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1261 bool IsTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0
1262 && CC == CallingConv::Fast && PerformTailCallOpt;
1263 SDOperand Callee = Op.getOperand(4);
1264 bool Is64Bit = Subtarget->is64Bit();
1266 assert(!(isVarArg && CC == CallingConv::Fast) &&
1267 "Var args not supported with calling convention fastcc");
1269 // Analyze operands of the call, assigning locations to each operand.
1270 SmallVector<CCValAssign, 16> ArgLocs;
1271 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
1272 CCInfo.AnalyzeCallOperands(Op.Val, CCAssignFnForNode(Op));
1274 // Get a count of how many bytes are to be pushed on the stack.
1275 unsigned NumBytes = CCInfo.getNextStackOffset();
1276 if (CC == CallingConv::Fast)
1277 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
1279 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
1280 // arguments and the arguments after the retaddr has been pushed are aligned.
1281 if (!Is64Bit && CC == CallingConv::X86_FastCall &&
1282 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWindows() &&
1283 (NumBytes & 7) == 0)
1288 // Lower arguments at fp - stackoffset + fpdiff.
1289 unsigned NumBytesCallerPushed =
1290 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
1291 FPDiff = NumBytesCallerPushed - NumBytes;
1293 // Set the delta of movement of the returnaddr stackslot.
1294 // But only set if delta is greater than previous delta.
1295 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
1296 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
1299 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes));
1301 SDOperand RetAddrFrIdx, NewRetAddrFrIdx;
1303 // Adjust the Return address stack slot.
1305 MVT::ValueType VT = Is64Bit ? MVT::i64 : MVT::i32;
1306 RetAddrFrIdx = getReturnAddressFrameIndex(DAG);
1307 // Load the "old" Return address.
1309 DAG.getLoad(VT, Chain,RetAddrFrIdx, NULL, 0);
1310 // Calculate the new stack slot for the return address.
1311 int SlotSize = Is64Bit ? 8 : 4;
1312 int NewReturnAddrFI =
1313 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize);
1314 NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
1315 Chain = SDOperand(RetAddrFrIdx.Val, 1);
1319 SmallVector<std::pair<unsigned, SDOperand>, 8> RegsToPass;
1320 SmallVector<SDOperand, 8> MemOpChains;
1324 // Walk the register/memloc assignments, inserting copies/loads. For tail
1325 // calls, lower arguments which could otherwise be possibly overwritten to the
1326 // stack slot where they would go on normal function calls.
1327 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1328 CCValAssign &VA = ArgLocs[i];
1329 SDOperand Arg = Op.getOperand(5+2*VA.getValNo());
1331 // Promote the value if needed.
1332 switch (VA.getLocInfo()) {
1333 default: assert(0 && "Unknown loc info!");
1334 case CCValAssign::Full: break;
1335 case CCValAssign::SExt:
1336 Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg);
1338 case CCValAssign::ZExt:
1339 Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg);
1341 case CCValAssign::AExt:
1342 Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg);
1346 if (VA.isRegLoc()) {
1347 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1349 if (!IsTailCall || IsPossiblyOverwrittenArgumentOfTailCall(Arg)) {
1350 assert(VA.isMemLoc());
1351 if (StackPtr.Val == 0)
1352 StackPtr = DAG.getCopyFromReg(Chain, X86StackPtr, getPointerTy());
1354 MemOpChains.push_back(LowerMemOpCallTo(Op, DAG, StackPtr, VA, Chain,
1360 if (!MemOpChains.empty())
1361 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
1362 &MemOpChains[0], MemOpChains.size());
1364 // Build a sequence of copy-to-reg nodes chained together with token chain
1365 // and flag operands which copy the outgoing args into registers.
1367 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1368 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
1370 InFlag = Chain.getValue(1);
1374 InFlag = SDOperand(); // ??? Isn't this nuking the preceding loop's output?
1376 // ELF / PIC requires GOT in the EBX register before function calls via PLT
1378 // Does not work with tail call since ebx is not restored correctly by
1379 // tailcaller. TODO: at least for x86 - verify for x86-64
1380 if (!IsTailCall && !Is64Bit &&
1381 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1382 Subtarget->isPICStyleGOT()) {
1383 Chain = DAG.getCopyToReg(Chain, X86::EBX,
1384 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
1386 InFlag = Chain.getValue(1);
1389 if (Is64Bit && isVarArg) {
1390 // From AMD64 ABI document:
1391 // For calls that may call functions that use varargs or stdargs
1392 // (prototype-less calls or calls to functions containing ellipsis (...) in
1393 // the declaration) %al is used as hidden argument to specify the number
1394 // of SSE registers used. The contents of %al do not need to match exactly
1395 // the number of registers, but must be an ubound on the number of SSE
1396 // registers used and is in the range 0 - 8 inclusive.
1398 // Count the number of XMM registers allocated.
1399 static const unsigned XMMArgRegs[] = {
1400 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1401 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1403 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
1405 Chain = DAG.getCopyToReg(Chain, X86::AL,
1406 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
1407 InFlag = Chain.getValue(1);
1410 // For tail calls lower the arguments to the 'real' stack slot.
1412 SmallVector<SDOperand, 8> MemOpChains2;
1415 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1416 CCValAssign &VA = ArgLocs[i];
1417 if (!VA.isRegLoc()) {
1418 assert(VA.isMemLoc());
1419 SDOperand Arg = Op.getOperand(5+2*VA.getValNo());
1420 SDOperand FlagsOp = Op.getOperand(6+2*VA.getValNo());
1421 unsigned Flags = cast<ConstantSDNode>(FlagsOp)->getValue();
1422 // Create frame index.
1423 int32_t Offset = VA.getLocMemOffset()+FPDiff;
1424 uint32_t OpSize = (MVT::getSizeInBits(VA.getLocVT())+7)/8;
1425 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset);
1426 FIN = DAG.getFrameIndex(FI, MVT::i32);
1427 SDOperand Source = Arg;
1428 if (IsPossiblyOverwrittenArgumentOfTailCall(Arg)) {
1429 // Copy from stack slots to stack slot of a tail called function. This
1430 // needs to be done because if we would lower the arguments directly
1431 // to their real stack slot we might end up overwriting each other.
1432 // Get source stack slot.
1433 Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
1434 if (StackPtr.Val == 0)
1435 StackPtr = DAG.getCopyFromReg(Chain, X86StackPtr, getPointerTy());
1436 Source = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, Source);
1437 if ((Flags & ISD::ParamFlags::ByVal)==0)
1438 Source = DAG.getLoad(VA.getValVT(), Chain, Source, NULL, 0);
1441 if (Flags & ISD::ParamFlags::ByVal) {
1442 // Copy relative to framepointer.
1443 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN, Chain,
1446 // Store relative to framepointer.
1447 MemOpChains2.push_back(DAG.getStore(Chain, Source, FIN, NULL, 0));
1452 if (!MemOpChains2.empty())
1453 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
1454 &MemOpChains2[0], MemOpChains2.size());
1456 // Store the return address to the appropriate stack slot.
1458 Chain = DAG.getStore(Chain,RetAddrFrIdx, NewRetAddrFrIdx, NULL, 0);
1461 // If the callee is a GlobalAddress node (quite common, every direct call is)
1462 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
1463 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1464 // We should use extra load for direct calls to dllimported functions in
1466 if ((IsTailCall || !Is64Bit ||
1467 getTargetMachine().getCodeModel() != CodeModel::Large)
1468 && !Subtarget->GVRequiresExtraLoad(G->getGlobal(),
1469 getTargetMachine(), true))
1470 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
1471 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1472 if (IsTailCall || !Is64Bit ||
1473 getTargetMachine().getCodeModel() != CodeModel::Large)
1474 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
1475 } else if (IsTailCall) {
1476 assert(Callee.getOpcode() == ISD::LOAD &&
1477 "Function destination must be loaded into virtual register");
1478 unsigned Opc = Is64Bit ? X86::R9 : X86::ECX;
1480 Chain = DAG.getCopyToReg(Chain,
1481 DAG.getRegister(Opc, getPointerTy()) ,
1483 Callee = DAG.getRegister(Opc, getPointerTy());
1484 // Add register as live out.
1485 DAG.getMachineFunction().getRegInfo().addLiveOut(Opc);
1488 // Returns a chain & a flag for retval copy to use.
1489 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1490 SmallVector<SDOperand, 8> Ops;
1493 Ops.push_back(Chain);
1494 Ops.push_back(DAG.getIntPtrConstant(NumBytes));
1495 Ops.push_back(DAG.getIntPtrConstant(0));
1497 Ops.push_back(InFlag);
1498 Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size());
1499 InFlag = Chain.getValue(1);
1501 // Returns a chain & a flag for retval copy to use.
1502 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1506 Ops.push_back(Chain);
1507 Ops.push_back(Callee);
1510 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
1512 // Add an implicit use GOT pointer in EBX.
1513 if (!IsTailCall && !Is64Bit &&
1514 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1515 Subtarget->isPICStyleGOT())
1516 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
1518 // Add argument registers to the end of the list so that they are known live
1520 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1521 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1522 RegsToPass[i].second.getValueType()));
1525 Ops.push_back(InFlag);
1528 assert(InFlag.Val &&
1529 "Flag must be set. Depend on flag being set in LowerRET");
1530 Chain = DAG.getNode(X86ISD::TAILCALL,
1531 Op.Val->getVTList(), &Ops[0], Ops.size());
1533 return SDOperand(Chain.Val, Op.ResNo);
1536 Chain = DAG.getNode(X86ISD::CALL, NodeTys, &Ops[0], Ops.size());
1537 InFlag = Chain.getValue(1);
1539 // Create the CALLSEQ_END node.
1540 unsigned NumBytesForCalleeToPush;
1541 if (IsCalleePop(Op))
1542 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
1543 else if (!Is64Bit && CallIsStructReturn(Op))
1544 // If this is is a call to a struct-return function, the callee
1545 // pops the hidden struct pointer, so we have to push it back.
1546 // This is common for Darwin/X86, Linux & Mingw32 targets.
1547 NumBytesForCalleeToPush = 4;
1549 NumBytesForCalleeToPush = 0; // Callee pops nothing.
1551 // Returns a flag for retval copy to use.
1552 Chain = DAG.getCALLSEQ_END(Chain,
1553 DAG.getIntPtrConstant(NumBytes),
1554 DAG.getIntPtrConstant(NumBytesForCalleeToPush),
1556 InFlag = Chain.getValue(1);
1558 // Handle result values, copying them out of physregs into vregs that we
1560 return SDOperand(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo);
1564 //===----------------------------------------------------------------------===//
1565 // Fast Calling Convention (tail call) implementation
1566 //===----------------------------------------------------------------------===//
1568 // Like std call, callee cleans arguments, convention except that ECX is
1569 // reserved for storing the tail called function address. Only 2 registers are
1570 // free for argument passing (inreg). Tail call optimization is performed
1572 // * tailcallopt is enabled
1573 // * caller/callee are fastcc
1574 // * elf/pic is disabled OR
1575 // * elf/pic enabled + callee is in module + callee has
1576 // visibility protected or hidden
1577 // To keep the stack aligned according to platform abi the function
1578 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
1579 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
1580 // If a tail called function callee has more arguments than the caller the
1581 // caller needs to make sure that there is room to move the RETADDR to. This is
1582 // achieved by reserving an area the size of the argument delta right after the
1583 // original REtADDR, but before the saved framepointer or the spilled registers
1584 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
1596 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
1597 /// for a 16 byte align requirement.
1598 unsigned X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
1599 SelectionDAG& DAG) {
1600 if (PerformTailCallOpt) {
1601 MachineFunction &MF = DAG.getMachineFunction();
1602 const TargetMachine &TM = MF.getTarget();
1603 const TargetFrameInfo &TFI = *TM.getFrameInfo();
1604 unsigned StackAlignment = TFI.getStackAlignment();
1605 uint64_t AlignMask = StackAlignment - 1;
1606 int64_t Offset = StackSize;
1607 unsigned SlotSize = Subtarget->is64Bit() ? 8 : 4;
1608 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
1609 // Number smaller than 12 so just add the difference.
1610 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
1612 // Mask out lower bits, add stackalignment once plus the 12 bytes.
1613 Offset = ((~AlignMask) & Offset) + StackAlignment +
1614 (StackAlignment-SlotSize);
1621 /// IsEligibleForTailCallElimination - Check to see whether the next instruction
1622 /// following the call is a return. A function is eligible if caller/callee
1623 /// calling conventions match, currently only fastcc supports tail calls, and
1624 /// the function CALL is immediatly followed by a RET.
1625 bool X86TargetLowering::IsEligibleForTailCallOptimization(SDOperand Call,
1627 SelectionDAG& DAG) const {
1628 if (!PerformTailCallOpt)
1631 // Check whether CALL node immediatly preceeds the RET node and whether the
1632 // return uses the result of the node or is a void return.
1633 unsigned NumOps = Ret.getNumOperands();
1635 (Ret.getOperand(0) == SDOperand(Call.Val,1) ||
1636 Ret.getOperand(0) == SDOperand(Call.Val,0))) ||
1638 Ret.getOperand(0) == SDOperand(Call.Val,Call.Val->getNumValues()-1) &&
1639 Ret.getOperand(1) == SDOperand(Call.Val,0))) {
1640 MachineFunction &MF = DAG.getMachineFunction();
1641 unsigned CallerCC = MF.getFunction()->getCallingConv();
1642 unsigned CalleeCC = cast<ConstantSDNode>(Call.getOperand(1))->getValue();
1643 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
1644 SDOperand Callee = Call.getOperand(4);
1645 // On elf/pic %ebx needs to be livein.
1646 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ ||
1647 !Subtarget->isPICStyleGOT())
1650 // Can only do local tail calls with PIC.
1651 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1652 return G->getGlobal()->hasHiddenVisibility()
1653 || G->getGlobal()->hasProtectedVisibility();
1660 //===----------------------------------------------------------------------===//
1661 // Other Lowering Hooks
1662 //===----------------------------------------------------------------------===//
1665 SDOperand X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) {
1666 MachineFunction &MF = DAG.getMachineFunction();
1667 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1668 int ReturnAddrIndex = FuncInfo->getRAIndex();
1670 if (ReturnAddrIndex == 0) {
1671 // Set up a frame object for the return address.
1672 if (Subtarget->is64Bit())
1673 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(8, -8);
1675 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(4, -4);
1677 FuncInfo->setRAIndex(ReturnAddrIndex);
1680 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
1685 /// translateX86CC - do a one to one translation of a ISD::CondCode to the X86
1686 /// specific condition code. It returns a false if it cannot do a direct
1687 /// translation. X86CC is the translated CondCode. LHS/RHS are modified as
1689 static bool translateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
1690 unsigned &X86CC, SDOperand &LHS, SDOperand &RHS,
1691 SelectionDAG &DAG) {
1692 X86CC = X86::COND_INVALID;
1694 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
1695 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
1696 // X > -1 -> X == 0, jump !sign.
1697 RHS = DAG.getConstant(0, RHS.getValueType());
1698 X86CC = X86::COND_NS;
1700 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
1701 // X < 0 -> X == 0, jump on sign.
1702 X86CC = X86::COND_S;
1704 } else if (SetCCOpcode == ISD::SETLT && RHSC->getValue() == 1) {
1706 RHS = DAG.getConstant(0, RHS.getValueType());
1707 X86CC = X86::COND_LE;
1712 switch (SetCCOpcode) {
1714 case ISD::SETEQ: X86CC = X86::COND_E; break;
1715 case ISD::SETGT: X86CC = X86::COND_G; break;
1716 case ISD::SETGE: X86CC = X86::COND_GE; break;
1717 case ISD::SETLT: X86CC = X86::COND_L; break;
1718 case ISD::SETLE: X86CC = X86::COND_LE; break;
1719 case ISD::SETNE: X86CC = X86::COND_NE; break;
1720 case ISD::SETULT: X86CC = X86::COND_B; break;
1721 case ISD::SETUGT: X86CC = X86::COND_A; break;
1722 case ISD::SETULE: X86CC = X86::COND_BE; break;
1723 case ISD::SETUGE: X86CC = X86::COND_AE; break;
1726 // On a floating point condition, the flags are set as follows:
1728 // 0 | 0 | 0 | X > Y
1729 // 0 | 0 | 1 | X < Y
1730 // 1 | 0 | 0 | X == Y
1731 // 1 | 1 | 1 | unordered
1733 switch (SetCCOpcode) {
1736 case ISD::SETEQ: X86CC = X86::COND_E; break;
1737 case ISD::SETOLT: Flip = true; // Fallthrough
1739 case ISD::SETGT: X86CC = X86::COND_A; break;
1740 case ISD::SETOLE: Flip = true; // Fallthrough
1742 case ISD::SETGE: X86CC = X86::COND_AE; break;
1743 case ISD::SETUGT: Flip = true; // Fallthrough
1745 case ISD::SETLT: X86CC = X86::COND_B; break;
1746 case ISD::SETUGE: Flip = true; // Fallthrough
1748 case ISD::SETLE: X86CC = X86::COND_BE; break;
1750 case ISD::SETNE: X86CC = X86::COND_NE; break;
1751 case ISD::SETUO: X86CC = X86::COND_P; break;
1752 case ISD::SETO: X86CC = X86::COND_NP; break;
1755 std::swap(LHS, RHS);
1758 return X86CC != X86::COND_INVALID;
1761 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
1762 /// code. Current x86 isa includes the following FP cmov instructions:
1763 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
1764 static bool hasFPCMov(unsigned X86CC) {
1780 /// isUndefOrInRange - Op is either an undef node or a ConstantSDNode. Return
1781 /// true if Op is undef or if its value falls within the specified range (L, H].
1782 static bool isUndefOrInRange(SDOperand Op, unsigned Low, unsigned Hi) {
1783 if (Op.getOpcode() == ISD::UNDEF)
1786 unsigned Val = cast<ConstantSDNode>(Op)->getValue();
1787 return (Val >= Low && Val < Hi);
1790 /// isUndefOrEqual - Op is either an undef node or a ConstantSDNode. Return
1791 /// true if Op is undef or if its value equal to the specified value.
1792 static bool isUndefOrEqual(SDOperand Op, unsigned Val) {
1793 if (Op.getOpcode() == ISD::UNDEF)
1795 return cast<ConstantSDNode>(Op)->getValue() == Val;
1798 /// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand
1799 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
1800 bool X86::isPSHUFDMask(SDNode *N) {
1801 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1803 if (N->getNumOperands() != 2 && N->getNumOperands() != 4)
1806 // Check if the value doesn't reference the second vector.
1807 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1808 SDOperand Arg = N->getOperand(i);
1809 if (Arg.getOpcode() == ISD::UNDEF) continue;
1810 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1811 if (cast<ConstantSDNode>(Arg)->getValue() >= e)
1818 /// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand
1819 /// specifies a shuffle of elements that is suitable for input to PSHUFHW.
1820 bool X86::isPSHUFHWMask(SDNode *N) {
1821 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1823 if (N->getNumOperands() != 8)
1826 // Lower quadword copied in order.
1827 for (unsigned i = 0; i != 4; ++i) {
1828 SDOperand Arg = N->getOperand(i);
1829 if (Arg.getOpcode() == ISD::UNDEF) continue;
1830 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1831 if (cast<ConstantSDNode>(Arg)->getValue() != i)
1835 // Upper quadword shuffled.
1836 for (unsigned i = 4; i != 8; ++i) {
1837 SDOperand Arg = N->getOperand(i);
1838 if (Arg.getOpcode() == ISD::UNDEF) continue;
1839 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1840 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
1841 if (Val < 4 || Val > 7)
1848 /// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand
1849 /// specifies a shuffle of elements that is suitable for input to PSHUFLW.
1850 bool X86::isPSHUFLWMask(SDNode *N) {
1851 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1853 if (N->getNumOperands() != 8)
1856 // Upper quadword copied in order.
1857 for (unsigned i = 4; i != 8; ++i)
1858 if (!isUndefOrEqual(N->getOperand(i), i))
1861 // Lower quadword shuffled.
1862 for (unsigned i = 0; i != 4; ++i)
1863 if (!isUndefOrInRange(N->getOperand(i), 0, 4))
1869 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
1870 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
1871 static bool isSHUFPMask(const SDOperand *Elems, unsigned NumElems) {
1872 if (NumElems != 2 && NumElems != 4) return false;
1874 unsigned Half = NumElems / 2;
1875 for (unsigned i = 0; i < Half; ++i)
1876 if (!isUndefOrInRange(Elems[i], 0, NumElems))
1878 for (unsigned i = Half; i < NumElems; ++i)
1879 if (!isUndefOrInRange(Elems[i], NumElems, NumElems*2))
1885 bool X86::isSHUFPMask(SDNode *N) {
1886 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1887 return ::isSHUFPMask(N->op_begin(), N->getNumOperands());
1890 /// isCommutedSHUFP - Returns true if the shuffle mask is exactly
1891 /// the reverse of what x86 shuffles want. x86 shuffles requires the lower
1892 /// half elements to come from vector 1 (which would equal the dest.) and
1893 /// the upper half to come from vector 2.
1894 static bool isCommutedSHUFP(const SDOperand *Ops, unsigned NumOps) {
1895 if (NumOps != 2 && NumOps != 4) return false;
1897 unsigned Half = NumOps / 2;
1898 for (unsigned i = 0; i < Half; ++i)
1899 if (!isUndefOrInRange(Ops[i], NumOps, NumOps*2))
1901 for (unsigned i = Half; i < NumOps; ++i)
1902 if (!isUndefOrInRange(Ops[i], 0, NumOps))
1907 static bool isCommutedSHUFP(SDNode *N) {
1908 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1909 return isCommutedSHUFP(N->op_begin(), N->getNumOperands());
1912 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
1913 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
1914 bool X86::isMOVHLPSMask(SDNode *N) {
1915 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1917 if (N->getNumOperands() != 4)
1920 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
1921 return isUndefOrEqual(N->getOperand(0), 6) &&
1922 isUndefOrEqual(N->getOperand(1), 7) &&
1923 isUndefOrEqual(N->getOperand(2), 2) &&
1924 isUndefOrEqual(N->getOperand(3), 3);
1927 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
1928 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
1930 bool X86::isMOVHLPS_v_undef_Mask(SDNode *N) {
1931 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1933 if (N->getNumOperands() != 4)
1936 // Expect bit0 == 2, bit1 == 3, bit2 == 2, bit3 == 3
1937 return isUndefOrEqual(N->getOperand(0), 2) &&
1938 isUndefOrEqual(N->getOperand(1), 3) &&
1939 isUndefOrEqual(N->getOperand(2), 2) &&
1940 isUndefOrEqual(N->getOperand(3), 3);
1943 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
1944 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
1945 bool X86::isMOVLPMask(SDNode *N) {
1946 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1948 unsigned NumElems = N->getNumOperands();
1949 if (NumElems != 2 && NumElems != 4)
1952 for (unsigned i = 0; i < NumElems/2; ++i)
1953 if (!isUndefOrEqual(N->getOperand(i), i + NumElems))
1956 for (unsigned i = NumElems/2; i < NumElems; ++i)
1957 if (!isUndefOrEqual(N->getOperand(i), i))
1963 /// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand
1964 /// specifies a shuffle of elements that is suitable for input to MOVHP{S|D}
1966 bool X86::isMOVHPMask(SDNode *N) {
1967 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1969 unsigned NumElems = N->getNumOperands();
1970 if (NumElems != 2 && NumElems != 4)
1973 for (unsigned i = 0; i < NumElems/2; ++i)
1974 if (!isUndefOrEqual(N->getOperand(i), i))
1977 for (unsigned i = 0; i < NumElems/2; ++i) {
1978 SDOperand Arg = N->getOperand(i + NumElems/2);
1979 if (!isUndefOrEqual(Arg, i + NumElems))
1986 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
1987 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
1988 bool static isUNPCKLMask(const SDOperand *Elts, unsigned NumElts,
1989 bool V2IsSplat = false) {
1990 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
1993 for (unsigned i = 0, j = 0; i != NumElts; i += 2, ++j) {
1994 SDOperand BitI = Elts[i];
1995 SDOperand BitI1 = Elts[i+1];
1996 if (!isUndefOrEqual(BitI, j))
1999 if (isUndefOrEqual(BitI1, NumElts))
2002 if (!isUndefOrEqual(BitI1, j + NumElts))
2010 bool X86::isUNPCKLMask(SDNode *N, bool V2IsSplat) {
2011 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2012 return ::isUNPCKLMask(N->op_begin(), N->getNumOperands(), V2IsSplat);
2015 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
2016 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
2017 bool static isUNPCKHMask(const SDOperand *Elts, unsigned NumElts,
2018 bool V2IsSplat = false) {
2019 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2022 for (unsigned i = 0, j = 0; i != NumElts; i += 2, ++j) {
2023 SDOperand BitI = Elts[i];
2024 SDOperand BitI1 = Elts[i+1];
2025 if (!isUndefOrEqual(BitI, j + NumElts/2))
2028 if (isUndefOrEqual(BitI1, NumElts))
2031 if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts))
2039 bool X86::isUNPCKHMask(SDNode *N, bool V2IsSplat) {
2040 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2041 return ::isUNPCKHMask(N->op_begin(), N->getNumOperands(), V2IsSplat);
2044 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
2045 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
2047 bool X86::isUNPCKL_v_undef_Mask(SDNode *N) {
2048 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2050 unsigned NumElems = N->getNumOperands();
2051 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2054 for (unsigned i = 0, j = 0; i != NumElems; i += 2, ++j) {
2055 SDOperand BitI = N->getOperand(i);
2056 SDOperand BitI1 = N->getOperand(i+1);
2058 if (!isUndefOrEqual(BitI, j))
2060 if (!isUndefOrEqual(BitI1, j))
2067 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
2068 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
2070 bool X86::isUNPCKH_v_undef_Mask(SDNode *N) {
2071 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2073 unsigned NumElems = N->getNumOperands();
2074 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2077 for (unsigned i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) {
2078 SDOperand BitI = N->getOperand(i);
2079 SDOperand BitI1 = N->getOperand(i + 1);
2081 if (!isUndefOrEqual(BitI, j))
2083 if (!isUndefOrEqual(BitI1, j))
2090 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
2091 /// specifies a shuffle of elements that is suitable for input to MOVSS,
2092 /// MOVSD, and MOVD, i.e. setting the lowest element.
2093 static bool isMOVLMask(const SDOperand *Elts, unsigned NumElts) {
2094 if (NumElts != 2 && NumElts != 4)
2097 if (!isUndefOrEqual(Elts[0], NumElts))
2100 for (unsigned i = 1; i < NumElts; ++i) {
2101 if (!isUndefOrEqual(Elts[i], i))
2108 bool X86::isMOVLMask(SDNode *N) {
2109 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2110 return ::isMOVLMask(N->op_begin(), N->getNumOperands());
2113 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
2114 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
2115 /// element of vector 2 and the other elements to come from vector 1 in order.
2116 static bool isCommutedMOVL(const SDOperand *Ops, unsigned NumOps,
2117 bool V2IsSplat = false,
2118 bool V2IsUndef = false) {
2119 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
2122 if (!isUndefOrEqual(Ops[0], 0))
2125 for (unsigned i = 1; i < NumOps; ++i) {
2126 SDOperand Arg = Ops[i];
2127 if (!(isUndefOrEqual(Arg, i+NumOps) ||
2128 (V2IsUndef && isUndefOrInRange(Arg, NumOps, NumOps*2)) ||
2129 (V2IsSplat && isUndefOrEqual(Arg, NumOps))))
2136 static bool isCommutedMOVL(SDNode *N, bool V2IsSplat = false,
2137 bool V2IsUndef = false) {
2138 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2139 return isCommutedMOVL(N->op_begin(), N->getNumOperands(),
2140 V2IsSplat, V2IsUndef);
2143 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2144 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
2145 bool X86::isMOVSHDUPMask(SDNode *N) {
2146 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2148 if (N->getNumOperands() != 4)
2151 // Expect 1, 1, 3, 3
2152 for (unsigned i = 0; i < 2; ++i) {
2153 SDOperand Arg = N->getOperand(i);
2154 if (Arg.getOpcode() == ISD::UNDEF) continue;
2155 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2156 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2157 if (Val != 1) return false;
2161 for (unsigned i = 2; i < 4; ++i) {
2162 SDOperand Arg = N->getOperand(i);
2163 if (Arg.getOpcode() == ISD::UNDEF) continue;
2164 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2165 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2166 if (Val != 3) return false;
2170 // Don't use movshdup if it can be done with a shufps.
2174 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2175 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
2176 bool X86::isMOVSLDUPMask(SDNode *N) {
2177 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2179 if (N->getNumOperands() != 4)
2182 // Expect 0, 0, 2, 2
2183 for (unsigned i = 0; i < 2; ++i) {
2184 SDOperand Arg = N->getOperand(i);
2185 if (Arg.getOpcode() == ISD::UNDEF) continue;
2186 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2187 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2188 if (Val != 0) return false;
2192 for (unsigned i = 2; i < 4; ++i) {
2193 SDOperand Arg = N->getOperand(i);
2194 if (Arg.getOpcode() == ISD::UNDEF) continue;
2195 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2196 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2197 if (Val != 2) return false;
2201 // Don't use movshdup if it can be done with a shufps.
2205 /// isIdentityMask - Return true if the specified VECTOR_SHUFFLE operand
2206 /// specifies a identity operation on the LHS or RHS.
2207 static bool isIdentityMask(SDNode *N, bool RHS = false) {
2208 unsigned NumElems = N->getNumOperands();
2209 for (unsigned i = 0; i < NumElems; ++i)
2210 if (!isUndefOrEqual(N->getOperand(i), i + (RHS ? NumElems : 0)))
2215 /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies
2216 /// a splat of a single element.
2217 static bool isSplatMask(SDNode *N) {
2218 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2220 // This is a splat operation if each element of the permute is the same, and
2221 // if the value doesn't reference the second vector.
2222 unsigned NumElems = N->getNumOperands();
2223 SDOperand ElementBase;
2225 for (; i != NumElems; ++i) {
2226 SDOperand Elt = N->getOperand(i);
2227 if (isa<ConstantSDNode>(Elt)) {
2233 if (!ElementBase.Val)
2236 for (; i != NumElems; ++i) {
2237 SDOperand Arg = N->getOperand(i);
2238 if (Arg.getOpcode() == ISD::UNDEF) continue;
2239 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2240 if (Arg != ElementBase) return false;
2243 // Make sure it is a splat of the first vector operand.
2244 return cast<ConstantSDNode>(ElementBase)->getValue() < NumElems;
2247 /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies
2248 /// a splat of a single element and it's a 2 or 4 element mask.
2249 bool X86::isSplatMask(SDNode *N) {
2250 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2252 // We can only splat 64-bit, and 32-bit quantities with a single instruction.
2253 if (N->getNumOperands() != 4 && N->getNumOperands() != 2)
2255 return ::isSplatMask(N);
2258 /// isSplatLoMask - Return true if the specified VECTOR_SHUFFLE operand
2259 /// specifies a splat of zero element.
2260 bool X86::isSplatLoMask(SDNode *N) {
2261 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2263 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i)
2264 if (!isUndefOrEqual(N->getOperand(i), 0))
2269 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
2270 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP*
2272 unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
2273 unsigned NumOperands = N->getNumOperands();
2274 unsigned Shift = (NumOperands == 4) ? 2 : 1;
2276 for (unsigned i = 0; i < NumOperands; ++i) {
2278 SDOperand Arg = N->getOperand(NumOperands-i-1);
2279 if (Arg.getOpcode() != ISD::UNDEF)
2280 Val = cast<ConstantSDNode>(Arg)->getValue();
2281 if (Val >= NumOperands) Val -= NumOperands;
2283 if (i != NumOperands - 1)
2290 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
2291 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFHW
2293 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
2295 // 8 nodes, but we only care about the last 4.
2296 for (unsigned i = 7; i >= 4; --i) {
2298 SDOperand Arg = N->getOperand(i);
2299 if (Arg.getOpcode() != ISD::UNDEF)
2300 Val = cast<ConstantSDNode>(Arg)->getValue();
2309 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
2310 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFLW
2312 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
2314 // 8 nodes, but we only care about the first 4.
2315 for (int i = 3; i >= 0; --i) {
2317 SDOperand Arg = N->getOperand(i);
2318 if (Arg.getOpcode() != ISD::UNDEF)
2319 Val = cast<ConstantSDNode>(Arg)->getValue();
2328 /// isPSHUFHW_PSHUFLWMask - true if the specified VECTOR_SHUFFLE operand
2329 /// specifies a 8 element shuffle that can be broken into a pair of
2330 /// PSHUFHW and PSHUFLW.
2331 static bool isPSHUFHW_PSHUFLWMask(SDNode *N) {
2332 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2334 if (N->getNumOperands() != 8)
2337 // Lower quadword shuffled.
2338 for (unsigned i = 0; i != 4; ++i) {
2339 SDOperand Arg = N->getOperand(i);
2340 if (Arg.getOpcode() == ISD::UNDEF) continue;
2341 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2342 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2347 // Upper quadword shuffled.
2348 for (unsigned i = 4; i != 8; ++i) {
2349 SDOperand Arg = N->getOperand(i);
2350 if (Arg.getOpcode() == ISD::UNDEF) continue;
2351 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2352 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2353 if (Val < 4 || Val > 7)
2360 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as
2361 /// values in ther permute mask.
2362 static SDOperand CommuteVectorShuffle(SDOperand Op, SDOperand &V1,
2363 SDOperand &V2, SDOperand &Mask,
2364 SelectionDAG &DAG) {
2365 MVT::ValueType VT = Op.getValueType();
2366 MVT::ValueType MaskVT = Mask.getValueType();
2367 MVT::ValueType EltVT = MVT::getVectorElementType(MaskVT);
2368 unsigned NumElems = Mask.getNumOperands();
2369 SmallVector<SDOperand, 8> MaskVec;
2371 for (unsigned i = 0; i != NumElems; ++i) {
2372 SDOperand Arg = Mask.getOperand(i);
2373 if (Arg.getOpcode() == ISD::UNDEF) {
2374 MaskVec.push_back(DAG.getNode(ISD::UNDEF, EltVT));
2377 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2378 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2380 MaskVec.push_back(DAG.getConstant(Val + NumElems, EltVT));
2382 MaskVec.push_back(DAG.getConstant(Val - NumElems, EltVT));
2386 Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], NumElems);
2387 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
2390 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
2391 /// the two vector operands have swapped position.
2393 SDOperand CommuteVectorShuffleMask(SDOperand Mask, SelectionDAG &DAG) {
2394 MVT::ValueType MaskVT = Mask.getValueType();
2395 MVT::ValueType EltVT = MVT::getVectorElementType(MaskVT);
2396 unsigned NumElems = Mask.getNumOperands();
2397 SmallVector<SDOperand, 8> MaskVec;
2398 for (unsigned i = 0; i != NumElems; ++i) {
2399 SDOperand Arg = Mask.getOperand(i);
2400 if (Arg.getOpcode() == ISD::UNDEF) {
2401 MaskVec.push_back(DAG.getNode(ISD::UNDEF, EltVT));
2404 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2405 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2407 MaskVec.push_back(DAG.getConstant(Val + NumElems, EltVT));
2409 MaskVec.push_back(DAG.getConstant(Val - NumElems, EltVT));
2411 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], NumElems);
2415 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
2416 /// match movhlps. The lower half elements should come from upper half of
2417 /// V1 (and in order), and the upper half elements should come from the upper
2418 /// half of V2 (and in order).
2419 static bool ShouldXformToMOVHLPS(SDNode *Mask) {
2420 unsigned NumElems = Mask->getNumOperands();
2423 for (unsigned i = 0, e = 2; i != e; ++i)
2424 if (!isUndefOrEqual(Mask->getOperand(i), i+2))
2426 for (unsigned i = 2; i != 4; ++i)
2427 if (!isUndefOrEqual(Mask->getOperand(i), i+4))
2432 /// isScalarLoadToVector - Returns true if the node is a scalar load that
2433 /// is promoted to a vector.
2434 static inline bool isScalarLoadToVector(SDNode *N) {
2435 if (N->getOpcode() == ISD::SCALAR_TO_VECTOR) {
2436 N = N->getOperand(0).Val;
2437 return ISD::isNON_EXTLoad(N);
2442 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
2443 /// match movlp{s|d}. The lower half elements should come from lower half of
2444 /// V1 (and in order), and the upper half elements should come from the upper
2445 /// half of V2 (and in order). And since V1 will become the source of the
2446 /// MOVLP, it must be either a vector load or a scalar load to vector.
2447 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2, SDNode *Mask) {
2448 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
2450 // Is V2 is a vector load, don't do this transformation. We will try to use
2451 // load folding shufps op.
2452 if (ISD::isNON_EXTLoad(V2))
2455 unsigned NumElems = Mask->getNumOperands();
2456 if (NumElems != 2 && NumElems != 4)
2458 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
2459 if (!isUndefOrEqual(Mask->getOperand(i), i))
2461 for (unsigned i = NumElems/2; i != NumElems; ++i)
2462 if (!isUndefOrEqual(Mask->getOperand(i), i+NumElems))
2467 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
2469 static bool isSplatVector(SDNode *N) {
2470 if (N->getOpcode() != ISD::BUILD_VECTOR)
2473 SDOperand SplatValue = N->getOperand(0);
2474 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
2475 if (N->getOperand(i) != SplatValue)
2480 /// isUndefShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
2482 static bool isUndefShuffle(SDNode *N) {
2483 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
2486 SDOperand V1 = N->getOperand(0);
2487 SDOperand V2 = N->getOperand(1);
2488 SDOperand Mask = N->getOperand(2);
2489 unsigned NumElems = Mask.getNumOperands();
2490 for (unsigned i = 0; i != NumElems; ++i) {
2491 SDOperand Arg = Mask.getOperand(i);
2492 if (Arg.getOpcode() != ISD::UNDEF) {
2493 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2494 if (Val < NumElems && V1.getOpcode() != ISD::UNDEF)
2496 else if (Val >= NumElems && V2.getOpcode() != ISD::UNDEF)
2503 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
2505 static inline bool isZeroNode(SDOperand Elt) {
2506 return ((isa<ConstantSDNode>(Elt) &&
2507 cast<ConstantSDNode>(Elt)->getValue() == 0) ||
2508 (isa<ConstantFPSDNode>(Elt) &&
2509 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
2512 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
2513 /// to an zero vector.
2514 static bool isZeroShuffle(SDNode *N) {
2515 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
2518 SDOperand V1 = N->getOperand(0);
2519 SDOperand V2 = N->getOperand(1);
2520 SDOperand Mask = N->getOperand(2);
2521 unsigned NumElems = Mask.getNumOperands();
2522 for (unsigned i = 0; i != NumElems; ++i) {
2523 SDOperand Arg = Mask.getOperand(i);
2524 if (Arg.getOpcode() == ISD::UNDEF)
2527 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue();
2528 if (Idx < NumElems) {
2529 unsigned Opc = V1.Val->getOpcode();
2530 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.Val))
2532 if (Opc != ISD::BUILD_VECTOR ||
2533 !isZeroNode(V1.Val->getOperand(Idx)))
2535 } else if (Idx >= NumElems) {
2536 unsigned Opc = V2.Val->getOpcode();
2537 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.Val))
2539 if (Opc != ISD::BUILD_VECTOR ||
2540 !isZeroNode(V2.Val->getOperand(Idx - NumElems)))
2547 /// getZeroVector - Returns a vector of specified type with all zero elements.
2549 static SDOperand getZeroVector(MVT::ValueType VT, SelectionDAG &DAG) {
2550 assert(MVT::isVector(VT) && "Expected a vector type");
2552 // Always build zero vectors as <4 x i32> or <2 x i32> bitcasted to their dest
2553 // type. This ensures they get CSE'd.
2554 SDOperand Cst = DAG.getTargetConstant(0, MVT::i32);
2556 if (MVT::getSizeInBits(VT) == 64) // MMX
2557 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, Cst, Cst);
2559 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Cst, Cst, Cst, Cst);
2560 return DAG.getNode(ISD::BIT_CONVERT, VT, Vec);
2563 /// getOnesVector - Returns a vector of specified type with all bits set.
2565 static SDOperand getOnesVector(MVT::ValueType VT, SelectionDAG &DAG) {
2566 assert(MVT::isVector(VT) && "Expected a vector type");
2568 // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest
2569 // type. This ensures they get CSE'd.
2570 SDOperand Cst = DAG.getTargetConstant(~0U, MVT::i32);
2572 if (MVT::getSizeInBits(VT) == 64) // MMX
2573 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, Cst, Cst);
2575 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Cst, Cst, Cst, Cst);
2576 return DAG.getNode(ISD::BIT_CONVERT, VT, Vec);
2580 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
2581 /// that point to V2 points to its first element.
2582 static SDOperand NormalizeMask(SDOperand Mask, SelectionDAG &DAG) {
2583 assert(Mask.getOpcode() == ISD::BUILD_VECTOR);
2585 bool Changed = false;
2586 SmallVector<SDOperand, 8> MaskVec;
2587 unsigned NumElems = Mask.getNumOperands();
2588 for (unsigned i = 0; i != NumElems; ++i) {
2589 SDOperand Arg = Mask.getOperand(i);
2590 if (Arg.getOpcode() != ISD::UNDEF) {
2591 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2592 if (Val > NumElems) {
2593 Arg = DAG.getConstant(NumElems, Arg.getValueType());
2597 MaskVec.push_back(Arg);
2601 Mask = DAG.getNode(ISD::BUILD_VECTOR, Mask.getValueType(),
2602 &MaskVec[0], MaskVec.size());
2606 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
2607 /// operation of specified width.
2608 static SDOperand getMOVLMask(unsigned NumElems, SelectionDAG &DAG) {
2609 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2610 MVT::ValueType BaseVT = MVT::getVectorElementType(MaskVT);
2612 SmallVector<SDOperand, 8> MaskVec;
2613 MaskVec.push_back(DAG.getConstant(NumElems, BaseVT));
2614 for (unsigned i = 1; i != NumElems; ++i)
2615 MaskVec.push_back(DAG.getConstant(i, BaseVT));
2616 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2619 /// getUnpacklMask - Returns a vector_shuffle mask for an unpackl operation
2620 /// of specified width.
2621 static SDOperand getUnpacklMask(unsigned NumElems, SelectionDAG &DAG) {
2622 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2623 MVT::ValueType BaseVT = MVT::getVectorElementType(MaskVT);
2624 SmallVector<SDOperand, 8> MaskVec;
2625 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
2626 MaskVec.push_back(DAG.getConstant(i, BaseVT));
2627 MaskVec.push_back(DAG.getConstant(i + NumElems, BaseVT));
2629 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2632 /// getUnpackhMask - Returns a vector_shuffle mask for an unpackh operation
2633 /// of specified width.
2634 static SDOperand getUnpackhMask(unsigned NumElems, SelectionDAG &DAG) {
2635 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2636 MVT::ValueType BaseVT = MVT::getVectorElementType(MaskVT);
2637 unsigned Half = NumElems/2;
2638 SmallVector<SDOperand, 8> MaskVec;
2639 for (unsigned i = 0; i != Half; ++i) {
2640 MaskVec.push_back(DAG.getConstant(i + Half, BaseVT));
2641 MaskVec.push_back(DAG.getConstant(i + NumElems + Half, BaseVT));
2643 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2646 /// PromoteSplat - Promote a splat of v8i16 or v16i8 to v4i32.
2648 static SDOperand PromoteSplat(SDOperand Op, SelectionDAG &DAG) {
2649 SDOperand V1 = Op.getOperand(0);
2650 SDOperand Mask = Op.getOperand(2);
2651 MVT::ValueType VT = Op.getValueType();
2652 unsigned NumElems = Mask.getNumOperands();
2653 Mask = getUnpacklMask(NumElems, DAG);
2654 while (NumElems != 4) {
2655 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1, Mask);
2658 V1 = DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, V1);
2660 Mask = getZeroVector(MVT::v4i32, DAG);
2661 SDOperand Shuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v4i32, V1,
2662 DAG.getNode(ISD::UNDEF, MVT::v4i32), Mask);
2663 return DAG.getNode(ISD::BIT_CONVERT, VT, Shuffle);
2666 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
2667 /// vector of zero or undef vector. This produces a shuffle where the low
2668 /// element of V2 is swizzled into the zero/undef vector, landing at element
2669 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
2670 static SDOperand getShuffleVectorZeroOrUndef(SDOperand V2, MVT::ValueType VT,
2671 unsigned NumElems, unsigned Idx,
2672 bool isZero, SelectionDAG &DAG) {
2673 SDOperand V1 = isZero ? getZeroVector(VT, DAG) : DAG.getNode(ISD::UNDEF, VT);
2674 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2675 MVT::ValueType EVT = MVT::getVectorElementType(MaskVT);
2676 SmallVector<SDOperand, 16> MaskVec;
2677 for (unsigned i = 0; i != NumElems; ++i)
2678 if (i == Idx) // If this is the insertion idx, put the low elt of V2 here.
2679 MaskVec.push_back(DAG.getConstant(NumElems, EVT));
2681 MaskVec.push_back(DAG.getConstant(i, EVT));
2682 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2683 &MaskVec[0], MaskVec.size());
2684 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
2687 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
2689 static SDOperand LowerBuildVectorv16i8(SDOperand Op, unsigned NonZeros,
2690 unsigned NumNonZero, unsigned NumZero,
2691 SelectionDAG &DAG, TargetLowering &TLI) {
2697 for (unsigned i = 0; i < 16; ++i) {
2698 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
2699 if (ThisIsNonZero && First) {
2701 V = getZeroVector(MVT::v8i16, DAG);
2703 V = DAG.getNode(ISD::UNDEF, MVT::v8i16);
2708 SDOperand ThisElt(0, 0), LastElt(0, 0);
2709 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
2710 if (LastIsNonZero) {
2711 LastElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i-1));
2713 if (ThisIsNonZero) {
2714 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i));
2715 ThisElt = DAG.getNode(ISD::SHL, MVT::i16,
2716 ThisElt, DAG.getConstant(8, MVT::i8));
2718 ThisElt = DAG.getNode(ISD::OR, MVT::i16, ThisElt, LastElt);
2723 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, ThisElt,
2724 DAG.getIntPtrConstant(i/2));
2728 return DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, V);
2731 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
2733 static SDOperand LowerBuildVectorv8i16(SDOperand Op, unsigned NonZeros,
2734 unsigned NumNonZero, unsigned NumZero,
2735 SelectionDAG &DAG, TargetLowering &TLI) {
2741 for (unsigned i = 0; i < 8; ++i) {
2742 bool isNonZero = (NonZeros & (1 << i)) != 0;
2746 V = getZeroVector(MVT::v8i16, DAG);
2748 V = DAG.getNode(ISD::UNDEF, MVT::v8i16);
2751 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, Op.getOperand(i),
2752 DAG.getIntPtrConstant(i));
2760 X86TargetLowering::LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) {
2761 // All zero's are handled with pxor, all one's are handled with pcmpeqd.
2762 if (ISD::isBuildVectorAllZeros(Op.Val) || ISD::isBuildVectorAllOnes(Op.Val)) {
2763 // Canonicalize this to either <4 x i32> or <2 x i32> (SSE vs MMX) to
2764 // 1) ensure the zero vectors are CSE'd, and 2) ensure that i64 scalars are
2765 // eliminated on x86-32 hosts.
2766 if (Op.getValueType() == MVT::v4i32 || Op.getValueType() == MVT::v2i32)
2769 if (ISD::isBuildVectorAllOnes(Op.Val))
2770 return getOnesVector(Op.getValueType(), DAG);
2771 return getZeroVector(Op.getValueType(), DAG);
2774 MVT::ValueType VT = Op.getValueType();
2775 MVT::ValueType EVT = MVT::getVectorElementType(VT);
2776 unsigned EVTBits = MVT::getSizeInBits(EVT);
2778 unsigned NumElems = Op.getNumOperands();
2779 unsigned NumZero = 0;
2780 unsigned NumNonZero = 0;
2781 unsigned NonZeros = 0;
2782 bool HasNonImms = false;
2783 SmallSet<SDOperand, 8> Values;
2784 for (unsigned i = 0; i < NumElems; ++i) {
2785 SDOperand Elt = Op.getOperand(i);
2786 if (Elt.getOpcode() == ISD::UNDEF)
2789 if (Elt.getOpcode() != ISD::Constant &&
2790 Elt.getOpcode() != ISD::ConstantFP)
2792 if (isZeroNode(Elt))
2795 NonZeros |= (1 << i);
2800 if (NumNonZero == 0) {
2801 // All undef vector. Return an UNDEF. All zero vectors were handled above.
2802 return DAG.getNode(ISD::UNDEF, VT);
2805 // Splat is obviously ok. Let legalizer expand it to a shuffle.
2806 if (Values.size() == 1)
2809 // Special case for single non-zero element.
2810 if (NumNonZero == 1 && NumElems <= 4) {
2811 unsigned Idx = CountTrailingZeros_32(NonZeros);
2812 SDOperand Item = Op.getOperand(Idx);
2813 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Item);
2815 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
2816 return getShuffleVectorZeroOrUndef(Item, VT, NumElems, Idx,
2818 else if (!HasNonImms) // Otherwise, it's better to do a constpool load.
2821 if (EVTBits == 32) {
2822 // Turn it into a shuffle of zero and zero-extended scalar to vector.
2823 Item = getShuffleVectorZeroOrUndef(Item, VT, NumElems, 0, NumZero > 0,
2825 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2826 MVT::ValueType MaskEVT = MVT::getVectorElementType(MaskVT);
2827 SmallVector<SDOperand, 8> MaskVec;
2828 for (unsigned i = 0; i < NumElems; i++)
2829 MaskVec.push_back(DAG.getConstant((i == Idx) ? 0 : 1, MaskEVT));
2830 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2831 &MaskVec[0], MaskVec.size());
2832 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Item,
2833 DAG.getNode(ISD::UNDEF, VT), Mask);
2837 // A vector full of immediates; various special cases are already
2838 // handled, so this is best done with a single constant-pool load.
2842 // Let legalizer expand 2-wide build_vectors.
2846 // If element VT is < 32 bits, convert it to inserts into a zero vector.
2847 if (EVTBits == 8 && NumElems == 16) {
2848 SDOperand V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
2850 if (V.Val) return V;
2853 if (EVTBits == 16 && NumElems == 8) {
2854 SDOperand V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
2856 if (V.Val) return V;
2859 // If element VT is == 32 bits, turn it into a number of shuffles.
2860 SmallVector<SDOperand, 8> V;
2862 if (NumElems == 4 && NumZero > 0) {
2863 for (unsigned i = 0; i < 4; ++i) {
2864 bool isZero = !(NonZeros & (1 << i));
2866 V[i] = getZeroVector(VT, DAG);
2868 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(i));
2871 for (unsigned i = 0; i < 2; ++i) {
2872 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
2875 V[i] = V[i*2]; // Must be a zero vector.
2878 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2+1], V[i*2],
2879 getMOVLMask(NumElems, DAG));
2882 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2], V[i*2+1],
2883 getMOVLMask(NumElems, DAG));
2886 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2], V[i*2+1],
2887 getUnpacklMask(NumElems, DAG));
2892 // Take advantage of the fact GR32 to VR128 scalar_to_vector (i.e. movd)
2893 // clears the upper bits.
2894 // FIXME: we can do the same for v4f32 case when we know both parts of
2895 // the lower half come from scalar_to_vector (loadf32). We should do
2896 // that in post legalizer dag combiner with target specific hooks.
2897 if (MVT::isInteger(EVT) && (NonZeros & (0x3 << 2)) == 0)
2899 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2900 MVT::ValueType EVT = MVT::getVectorElementType(MaskVT);
2901 SmallVector<SDOperand, 8> MaskVec;
2902 bool Reverse = (NonZeros & 0x3) == 2;
2903 for (unsigned i = 0; i < 2; ++i)
2905 MaskVec.push_back(DAG.getConstant(1-i, EVT));
2907 MaskVec.push_back(DAG.getConstant(i, EVT));
2908 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
2909 for (unsigned i = 0; i < 2; ++i)
2911 MaskVec.push_back(DAG.getConstant(1-i+NumElems, EVT));
2913 MaskVec.push_back(DAG.getConstant(i+NumElems, EVT));
2914 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2915 &MaskVec[0], MaskVec.size());
2916 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[0], V[1], ShufMask);
2919 if (Values.size() > 2) {
2920 // Expand into a number of unpckl*.
2922 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
2923 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
2924 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
2925 SDOperand UnpckMask = getUnpacklMask(NumElems, DAG);
2926 for (unsigned i = 0; i < NumElems; ++i)
2927 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(i));
2929 while (NumElems != 0) {
2930 for (unsigned i = 0; i < NumElems; ++i)
2931 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i], V[i + NumElems],
2942 SDOperand LowerVECTOR_SHUFFLEv8i16(SDOperand V1, SDOperand V2,
2943 SDOperand PermMask, SelectionDAG &DAG,
2944 TargetLowering &TLI) {
2946 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(8);
2947 MVT::ValueType MaskEVT = MVT::getVectorElementType(MaskVT);
2948 MVT::ValueType PtrVT = TLI.getPointerTy();
2949 SmallVector<SDOperand, 8> MaskElts(PermMask.Val->op_begin(),
2950 PermMask.Val->op_end());
2952 // First record which half of which vector the low elements come from.
2953 SmallVector<unsigned, 4> LowQuad(4);
2954 for (unsigned i = 0; i < 4; ++i) {
2955 SDOperand Elt = MaskElts[i];
2956 if (Elt.getOpcode() == ISD::UNDEF)
2958 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
2959 int QuadIdx = EltIdx / 4;
2962 int BestLowQuad = -1;
2963 unsigned MaxQuad = 1;
2964 for (unsigned i = 0; i < 4; ++i) {
2965 if (LowQuad[i] > MaxQuad) {
2967 MaxQuad = LowQuad[i];
2971 // Record which half of which vector the high elements come from.
2972 SmallVector<unsigned, 4> HighQuad(4);
2973 for (unsigned i = 4; i < 8; ++i) {
2974 SDOperand Elt = MaskElts[i];
2975 if (Elt.getOpcode() == ISD::UNDEF)
2977 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
2978 int QuadIdx = EltIdx / 4;
2979 ++HighQuad[QuadIdx];
2981 int BestHighQuad = -1;
2983 for (unsigned i = 0; i < 4; ++i) {
2984 if (HighQuad[i] > MaxQuad) {
2986 MaxQuad = HighQuad[i];
2990 // If it's possible to sort parts of either half with PSHUF{H|L}W, then do it.
2991 if (BestLowQuad != -1 || BestHighQuad != -1) {
2992 // First sort the 4 chunks in order using shufpd.
2993 SmallVector<SDOperand, 8> MaskVec;
2994 if (BestLowQuad != -1)
2995 MaskVec.push_back(DAG.getConstant(BestLowQuad, MVT::i32));
2997 MaskVec.push_back(DAG.getConstant(0, MVT::i32));
2998 if (BestHighQuad != -1)
2999 MaskVec.push_back(DAG.getConstant(BestHighQuad, MVT::i32));
3001 MaskVec.push_back(DAG.getConstant(1, MVT::i32));
3002 SDOperand Mask= DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, &MaskVec[0],2);
3003 NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v2i64,
3004 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, V1),
3005 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, V2), Mask);
3006 NewV = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, NewV);
3008 // Now sort high and low parts separately.
3009 BitVector InOrder(8);
3010 if (BestLowQuad != -1) {
3011 // Sort lower half in order using PSHUFLW.
3013 bool AnyOutOrder = false;
3014 for (unsigned i = 0; i != 4; ++i) {
3015 SDOperand Elt = MaskElts[i];
3016 if (Elt.getOpcode() == ISD::UNDEF) {
3017 MaskVec.push_back(Elt);
3020 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3023 MaskVec.push_back(DAG.getConstant(EltIdx % 4, MaskEVT));
3024 // If this element is in the right place after this shuffle, then
3026 if ((int)(EltIdx / 4) == BestLowQuad)
3031 for (unsigned i = 4; i != 8; ++i)
3032 MaskVec.push_back(DAG.getConstant(i, MaskEVT));
3033 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8);
3034 NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, NewV, NewV, Mask);
3038 if (BestHighQuad != -1) {
3039 // Sort high half in order using PSHUFHW if possible.
3041 for (unsigned i = 0; i != 4; ++i)
3042 MaskVec.push_back(DAG.getConstant(i, MaskEVT));
3043 bool AnyOutOrder = false;
3044 for (unsigned i = 4; i != 8; ++i) {
3045 SDOperand Elt = MaskElts[i];
3046 if (Elt.getOpcode() == ISD::UNDEF) {
3047 MaskVec.push_back(Elt);
3050 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3053 MaskVec.push_back(DAG.getConstant((EltIdx % 4) + 4, MaskEVT));
3054 // If this element is in the right place after this shuffle, then
3056 if ((int)(EltIdx / 4) == BestHighQuad)
3061 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8);
3062 NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, NewV, NewV, Mask);
3066 // The other elements are put in the right place using pextrw and pinsrw.
3067 for (unsigned i = 0; i != 8; ++i) {
3070 SDOperand Elt = MaskElts[i];
3071 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3074 SDOperand ExtOp = (EltIdx < 8)
3075 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V1,
3076 DAG.getConstant(EltIdx, PtrVT))
3077 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V2,
3078 DAG.getConstant(EltIdx - 8, PtrVT));
3079 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, NewV, ExtOp,
3080 DAG.getConstant(i, PtrVT));
3085 // PSHUF{H|L}W are not used. Lower into extracts and inserts but try to use
3086 ///as few as possible.
3087 // First, let's find out how many elements are already in the right order.
3088 unsigned V1InOrder = 0;
3089 unsigned V1FromV1 = 0;
3090 unsigned V2InOrder = 0;
3091 unsigned V2FromV2 = 0;
3092 SmallVector<SDOperand, 8> V1Elts;
3093 SmallVector<SDOperand, 8> V2Elts;
3094 for (unsigned i = 0; i < 8; ++i) {
3095 SDOperand Elt = MaskElts[i];
3096 if (Elt.getOpcode() == ISD::UNDEF) {
3097 V1Elts.push_back(Elt);
3098 V2Elts.push_back(Elt);
3103 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3105 V1Elts.push_back(Elt);
3106 V2Elts.push_back(DAG.getConstant(i+8, MaskEVT));
3108 } else if (EltIdx == i+8) {
3109 V1Elts.push_back(Elt);
3110 V2Elts.push_back(DAG.getConstant(i, MaskEVT));
3112 } else if (EltIdx < 8) {
3113 V1Elts.push_back(Elt);
3116 V2Elts.push_back(DAG.getConstant(EltIdx-8, MaskEVT));
3121 if (V2InOrder > V1InOrder) {
3122 PermMask = CommuteVectorShuffleMask(PermMask, DAG);
3124 std::swap(V1Elts, V2Elts);
3125 std::swap(V1FromV1, V2FromV2);
3128 if ((V1FromV1 + V1InOrder) != 8) {
3129 // Some elements are from V2.
3131 // If there are elements that are from V1 but out of place,
3132 // then first sort them in place
3133 SmallVector<SDOperand, 8> MaskVec;
3134 for (unsigned i = 0; i < 8; ++i) {
3135 SDOperand Elt = V1Elts[i];
3136 if (Elt.getOpcode() == ISD::UNDEF) {
3137 MaskVec.push_back(DAG.getNode(ISD::UNDEF, MaskEVT));
3140 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3142 MaskVec.push_back(DAG.getNode(ISD::UNDEF, MaskEVT));
3144 MaskVec.push_back(DAG.getConstant(EltIdx, MaskEVT));
3146 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8);
3147 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, V1, V1, Mask);
3151 for (unsigned i = 0; i < 8; ++i) {
3152 SDOperand Elt = V1Elts[i];
3153 if (Elt.getOpcode() == ISD::UNDEF)
3155 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3158 SDOperand ExtOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V2,
3159 DAG.getConstant(EltIdx - 8, PtrVT));
3160 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, NewV, ExtOp,
3161 DAG.getConstant(i, PtrVT));
3165 // All elements are from V1.
3167 for (unsigned i = 0; i < 8; ++i) {
3168 SDOperand Elt = V1Elts[i];
3169 if (Elt.getOpcode() == ISD::UNDEF)
3171 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3172 SDOperand ExtOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V1,
3173 DAG.getConstant(EltIdx, PtrVT));
3174 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, NewV, ExtOp,
3175 DAG.getConstant(i, PtrVT));
3181 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
3182 /// ones, or rewriting v4i32 / v2f32 as 2 wide ones if possible. This can be
3183 /// done when every pair / quad of shuffle mask elements point to elements in
3184 /// the right sequence. e.g.
3185 /// vector_shuffle <>, <>, < 3, 4, | 10, 11, | 0, 1, | 14, 15>
3187 SDOperand RewriteAsNarrowerShuffle(SDOperand V1, SDOperand V2,
3189 SDOperand PermMask, SelectionDAG &DAG,
3190 TargetLowering &TLI) {
3191 unsigned NumElems = PermMask.getNumOperands();
3192 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
3193 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NewWidth);
3194 MVT::ValueType NewVT = MaskVT;
3196 case MVT::v4f32: NewVT = MVT::v2f64; break;
3197 case MVT::v4i32: NewVT = MVT::v2i64; break;
3198 case MVT::v8i16: NewVT = MVT::v4i32; break;
3199 case MVT::v16i8: NewVT = MVT::v4i32; break;
3200 default: assert(false && "Unexpected!");
3204 if (MVT::isInteger(VT))
3208 unsigned Scale = NumElems / NewWidth;
3209 SmallVector<SDOperand, 8> MaskVec;
3210 for (unsigned i = 0; i < NumElems; i += Scale) {
3211 unsigned StartIdx = ~0U;
3212 for (unsigned j = 0; j < Scale; ++j) {
3213 SDOperand Elt = PermMask.getOperand(i+j);
3214 if (Elt.getOpcode() == ISD::UNDEF)
3216 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3217 if (StartIdx == ~0U)
3218 StartIdx = EltIdx - (EltIdx % Scale);
3219 if (EltIdx != StartIdx + j)
3222 if (StartIdx == ~0U)
3223 MaskVec.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
3225 MaskVec.push_back(DAG.getConstant(StartIdx / Scale, MVT::i32));
3228 V1 = DAG.getNode(ISD::BIT_CONVERT, NewVT, V1);
3229 V2 = DAG.getNode(ISD::BIT_CONVERT, NewVT, V2);
3230 return DAG.getNode(ISD::VECTOR_SHUFFLE, NewVT, V1, V2,
3231 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3232 &MaskVec[0], MaskVec.size()));
3236 X86TargetLowering::LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) {
3237 SDOperand V1 = Op.getOperand(0);
3238 SDOperand V2 = Op.getOperand(1);
3239 SDOperand PermMask = Op.getOperand(2);
3240 MVT::ValueType VT = Op.getValueType();
3241 unsigned NumElems = PermMask.getNumOperands();
3242 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
3243 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
3244 bool V1IsSplat = false;
3245 bool V2IsSplat = false;
3247 if (isUndefShuffle(Op.Val))
3248 return DAG.getNode(ISD::UNDEF, VT);
3250 if (isZeroShuffle(Op.Val))
3251 return getZeroVector(VT, DAG);
3253 if (isIdentityMask(PermMask.Val))
3255 else if (isIdentityMask(PermMask.Val, true))
3258 if (isSplatMask(PermMask.Val)) {
3259 if (NumElems <= 4) return Op;
3260 // Promote it to a v4i32 splat.
3261 return PromoteSplat(Op, DAG);
3264 // If the shuffle can be profitably rewritten as a narrower shuffle, then
3266 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
3267 SDOperand NewOp= RewriteAsNarrowerShuffle(V1, V2, VT, PermMask, DAG, *this);
3269 return DAG.getNode(ISD::BIT_CONVERT, VT, LowerVECTOR_SHUFFLE(NewOp, DAG));
3270 } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
3271 // FIXME: Figure out a cleaner way to do this.
3272 // Try to make use of movq to zero out the top part.
3273 if (ISD::isBuildVectorAllZeros(V2.Val)) {
3274 SDOperand NewOp = RewriteAsNarrowerShuffle(V1, V2, VT, PermMask, DAG, *this);
3276 SDOperand NewV1 = NewOp.getOperand(0);
3277 SDOperand NewV2 = NewOp.getOperand(1);
3278 SDOperand NewMask = NewOp.getOperand(2);
3279 if (isCommutedMOVL(NewMask.Val, true, false)) {
3280 NewOp = CommuteVectorShuffle(NewOp, NewV1, NewV2, NewMask, DAG);
3281 NewOp = DAG.getNode(ISD::VECTOR_SHUFFLE, NewOp.getValueType(),
3282 NewV1, NewV2, getMOVLMask(2, DAG));
3283 return DAG.getNode(ISD::BIT_CONVERT, VT, LowerVECTOR_SHUFFLE(NewOp, DAG));
3286 } else if (ISD::isBuildVectorAllZeros(V1.Val)) {
3287 SDOperand NewOp= RewriteAsNarrowerShuffle(V1, V2, VT, PermMask, DAG, *this);
3288 if (NewOp.Val && X86::isMOVLMask(NewOp.getOperand(2).Val))
3289 return DAG.getNode(ISD::BIT_CONVERT, VT, LowerVECTOR_SHUFFLE(NewOp, DAG));
3293 if (X86::isMOVLMask(PermMask.Val))
3294 return (V1IsUndef) ? V2 : Op;
3296 if (X86::isMOVSHDUPMask(PermMask.Val) ||
3297 X86::isMOVSLDUPMask(PermMask.Val) ||
3298 X86::isMOVHLPSMask(PermMask.Val) ||
3299 X86::isMOVHPMask(PermMask.Val) ||
3300 X86::isMOVLPMask(PermMask.Val))
3303 if (ShouldXformToMOVHLPS(PermMask.Val) ||
3304 ShouldXformToMOVLP(V1.Val, V2.Val, PermMask.Val))
3305 return CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
3307 bool Commuted = false;
3308 // FIXME: This should also accept a bitcast of a splat? Be careful, not
3309 // 1,1,1,1 -> v8i16 though.
3310 V1IsSplat = isSplatVector(V1.Val);
3311 V2IsSplat = isSplatVector(V2.Val);
3313 // Canonicalize the splat or undef, if present, to be on the RHS.
3314 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
3315 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
3316 std::swap(V1IsSplat, V2IsSplat);
3317 std::swap(V1IsUndef, V2IsUndef);
3321 // FIXME: Figure out a cleaner way to do this.
3322 if (isCommutedMOVL(PermMask.Val, V2IsSplat, V2IsUndef)) {
3323 if (V2IsUndef) return V1;
3324 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
3326 // V2 is a splat, so the mask may be malformed. That is, it may point
3327 // to any V2 element. The instruction selectior won't like this. Get
3328 // a corrected mask and commute to form a proper MOVS{S|D}.
3329 SDOperand NewMask = getMOVLMask(NumElems, DAG);
3330 if (NewMask.Val != PermMask.Val)
3331 Op = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
3336 if (X86::isUNPCKL_v_undef_Mask(PermMask.Val) ||
3337 X86::isUNPCKH_v_undef_Mask(PermMask.Val) ||
3338 X86::isUNPCKLMask(PermMask.Val) ||
3339 X86::isUNPCKHMask(PermMask.Val))
3343 // Normalize mask so all entries that point to V2 points to its first
3344 // element then try to match unpck{h|l} again. If match, return a
3345 // new vector_shuffle with the corrected mask.
3346 SDOperand NewMask = NormalizeMask(PermMask, DAG);
3347 if (NewMask.Val != PermMask.Val) {
3348 if (X86::isUNPCKLMask(PermMask.Val, true)) {
3349 SDOperand NewMask = getUnpacklMask(NumElems, DAG);
3350 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
3351 } else if (X86::isUNPCKHMask(PermMask.Val, true)) {
3352 SDOperand NewMask = getUnpackhMask(NumElems, DAG);
3353 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
3358 // Normalize the node to match x86 shuffle ops if needed
3359 if (V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(PermMask.Val))
3360 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
3363 // Commute is back and try unpck* again.
3364 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
3365 if (X86::isUNPCKL_v_undef_Mask(PermMask.Val) ||
3366 X86::isUNPCKH_v_undef_Mask(PermMask.Val) ||
3367 X86::isUNPCKLMask(PermMask.Val) ||
3368 X86::isUNPCKHMask(PermMask.Val))
3372 // If VT is integer, try PSHUF* first, then SHUFP*.
3373 if (MVT::isInteger(VT)) {
3374 // MMX doesn't have PSHUFD; it does have PSHUFW. While it's theoretically
3375 // possible to shuffle a v2i32 using PSHUFW, that's not yet implemented.
3376 if (((MVT::getSizeInBits(VT) != 64 || NumElems == 4) &&
3377 X86::isPSHUFDMask(PermMask.Val)) ||
3378 X86::isPSHUFHWMask(PermMask.Val) ||
3379 X86::isPSHUFLWMask(PermMask.Val)) {
3380 if (V2.getOpcode() != ISD::UNDEF)
3381 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1,
3382 DAG.getNode(ISD::UNDEF, V1.getValueType()),PermMask);
3386 if (X86::isSHUFPMask(PermMask.Val) &&
3387 MVT::getSizeInBits(VT) != 64) // Don't do this for MMX.
3390 // Floating point cases in the other order.
3391 if (X86::isSHUFPMask(PermMask.Val))
3393 if (X86::isPSHUFDMask(PermMask.Val) ||
3394 X86::isPSHUFHWMask(PermMask.Val) ||
3395 X86::isPSHUFLWMask(PermMask.Val)) {
3396 if (V2.getOpcode() != ISD::UNDEF)
3397 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1,
3398 DAG.getNode(ISD::UNDEF, V1.getValueType()),PermMask);
3403 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
3404 if (VT == MVT::v8i16) {
3405 SDOperand NewOp = LowerVECTOR_SHUFFLEv8i16(V1, V2, PermMask, DAG, *this);
3410 // Handle all 4 wide cases with a number of shuffles.
3411 if (NumElems == 4 && MVT::getSizeInBits(VT) != 64) {
3412 // Don't do this for MMX.
3413 MVT::ValueType MaskVT = PermMask.getValueType();
3414 MVT::ValueType MaskEVT = MVT::getVectorElementType(MaskVT);
3415 SmallVector<std::pair<int, int>, 8> Locs;
3416 Locs.reserve(NumElems);
3417 SmallVector<SDOperand, 8> Mask1(NumElems,
3418 DAG.getNode(ISD::UNDEF, MaskEVT));
3419 SmallVector<SDOperand, 8> Mask2(NumElems,
3420 DAG.getNode(ISD::UNDEF, MaskEVT));
3423 // If no more than two elements come from either vector. This can be
3424 // implemented with two shuffles. First shuffle gather the elements.
3425 // The second shuffle, which takes the first shuffle as both of its
3426 // vector operands, put the elements into the right order.
3427 for (unsigned i = 0; i != NumElems; ++i) {
3428 SDOperand Elt = PermMask.getOperand(i);
3429 if (Elt.getOpcode() == ISD::UNDEF) {
3430 Locs[i] = std::make_pair(-1, -1);
3432 unsigned Val = cast<ConstantSDNode>(Elt)->getValue();
3433 if (Val < NumElems) {
3434 Locs[i] = std::make_pair(0, NumLo);
3438 Locs[i] = std::make_pair(1, NumHi);
3439 if (2+NumHi < NumElems)
3440 Mask1[2+NumHi] = Elt;
3445 if (NumLo <= 2 && NumHi <= 2) {
3446 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
3447 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3448 &Mask1[0], Mask1.size()));
3449 for (unsigned i = 0; i != NumElems; ++i) {
3450 if (Locs[i].first == -1)
3453 unsigned Idx = (i < NumElems/2) ? 0 : NumElems;
3454 Idx += Locs[i].first * (NumElems/2) + Locs[i].second;
3455 Mask2[i] = DAG.getConstant(Idx, MaskEVT);
3459 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1,
3460 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3461 &Mask2[0], Mask2.size()));
3464 // Break it into (shuffle shuffle_hi, shuffle_lo).
3466 SmallVector<SDOperand,8> LoMask(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT));
3467 SmallVector<SDOperand,8> HiMask(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT));
3468 SmallVector<SDOperand,8> *MaskPtr = &LoMask;
3469 unsigned MaskIdx = 0;
3471 unsigned HiIdx = NumElems/2;
3472 for (unsigned i = 0; i != NumElems; ++i) {
3473 if (i == NumElems/2) {
3479 SDOperand Elt = PermMask.getOperand(i);
3480 if (Elt.getOpcode() == ISD::UNDEF) {
3481 Locs[i] = std::make_pair(-1, -1);
3482 } else if (cast<ConstantSDNode>(Elt)->getValue() < NumElems) {
3483 Locs[i] = std::make_pair(MaskIdx, LoIdx);
3484 (*MaskPtr)[LoIdx] = Elt;
3487 Locs[i] = std::make_pair(MaskIdx, HiIdx);
3488 (*MaskPtr)[HiIdx] = Elt;
3493 SDOperand LoShuffle =
3494 DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
3495 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3496 &LoMask[0], LoMask.size()));
3497 SDOperand HiShuffle =
3498 DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
3499 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3500 &HiMask[0], HiMask.size()));
3501 SmallVector<SDOperand, 8> MaskOps;
3502 for (unsigned i = 0; i != NumElems; ++i) {
3503 if (Locs[i].first == -1) {
3504 MaskOps.push_back(DAG.getNode(ISD::UNDEF, MaskEVT));
3506 unsigned Idx = Locs[i].first * NumElems + Locs[i].second;
3507 MaskOps.push_back(DAG.getConstant(Idx, MaskEVT));
3510 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, LoShuffle, HiShuffle,
3511 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3512 &MaskOps[0], MaskOps.size()));
3519 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) {
3520 if (!isa<ConstantSDNode>(Op.getOperand(1)))
3523 MVT::ValueType VT = Op.getValueType();
3524 // TODO: handle v16i8.
3525 if (MVT::getSizeInBits(VT) == 16) {
3526 SDOperand Vec = Op.getOperand(0);
3527 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
3529 return DAG.getNode(ISD::TRUNCATE, MVT::i16,
3530 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i32,
3531 DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, Vec),
3533 // Transform it so it match pextrw which produces a 32-bit result.
3534 MVT::ValueType EVT = (MVT::ValueType)(VT+1);
3535 SDOperand Extract = DAG.getNode(X86ISD::PEXTRW, EVT,
3536 Op.getOperand(0), Op.getOperand(1));
3537 SDOperand Assert = DAG.getNode(ISD::AssertZext, EVT, Extract,
3538 DAG.getValueType(VT));
3539 return DAG.getNode(ISD::TRUNCATE, VT, Assert);
3540 } else if (MVT::getSizeInBits(VT) == 32) {
3541 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
3544 // SHUFPS the element to the lowest double word, then movss.
3545 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4);
3546 SmallVector<SDOperand, 8> IdxVec;
3548 push_back(DAG.getConstant(Idx, MVT::getVectorElementType(MaskVT)));
3550 push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(MaskVT)));
3552 push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(MaskVT)));
3554 push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(MaskVT)));
3555 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3556 &IdxVec[0], IdxVec.size());
3557 SDOperand Vec = Op.getOperand(0);
3558 Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(),
3559 Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask);
3560 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec,
3561 DAG.getIntPtrConstant(0));
3562 } else if (MVT::getSizeInBits(VT) == 64) {
3563 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
3567 // UNPCKHPD the element to the lowest double word, then movsd.
3568 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
3569 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
3570 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4);
3571 SmallVector<SDOperand, 8> IdxVec;
3572 IdxVec.push_back(DAG.getConstant(1, MVT::getVectorElementType(MaskVT)));
3574 push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(MaskVT)));
3575 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3576 &IdxVec[0], IdxVec.size());
3577 SDOperand Vec = Op.getOperand(0);
3578 Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(),
3579 Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask);
3580 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec,
3581 DAG.getIntPtrConstant(0));
3588 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) {
3589 MVT::ValueType VT = Op.getValueType();
3590 MVT::ValueType EVT = MVT::getVectorElementType(VT);
3594 SDOperand N0 = Op.getOperand(0);
3595 SDOperand N1 = Op.getOperand(1);
3596 SDOperand N2 = Op.getOperand(2);
3598 if (MVT::getSizeInBits(EVT) == 16) {
3599 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
3600 // as its second argument.
3601 if (N1.getValueType() != MVT::i32)
3602 N1 = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, N1);
3603 if (N2.getValueType() != MVT::i32)
3604 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getValue());
3605 return DAG.getNode(X86ISD::PINSRW, VT, N0, N1, N2);
3611 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG) {
3612 SDOperand AnyExt = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, Op.getOperand(0));
3613 return DAG.getNode(X86ISD::S2VEC, Op.getValueType(), AnyExt);
3616 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
3617 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
3618 // one of the above mentioned nodes. It has to be wrapped because otherwise
3619 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
3620 // be used to form addressing mode. These wrapped nodes will be selected
3623 X86TargetLowering::LowerConstantPool(SDOperand Op, SelectionDAG &DAG) {
3624 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
3625 SDOperand Result = DAG.getTargetConstantPool(CP->getConstVal(),
3627 CP->getAlignment());
3628 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
3629 // With PIC, the address is actually $g + Offset.
3630 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
3631 !Subtarget->isPICStyleRIPRel()) {
3632 Result = DAG.getNode(ISD::ADD, getPointerTy(),
3633 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
3641 X86TargetLowering::LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG) {
3642 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3643 SDOperand Result = DAG.getTargetGlobalAddress(GV, getPointerTy());
3644 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
3645 // With PIC, the address is actually $g + Offset.
3646 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
3647 !Subtarget->isPICStyleRIPRel()) {
3648 Result = DAG.getNode(ISD::ADD, getPointerTy(),
3649 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
3653 // For Darwin & Mingw32, external and weak symbols are indirect, so we want to
3654 // load the value at address GV, not the value of GV itself. This means that
3655 // the GlobalAddress must be in the base or index register of the address, not
3656 // the GV offset field. Platform check is inside GVRequiresExtraLoad() call
3657 // The same applies for external symbols during PIC codegen
3658 if (Subtarget->GVRequiresExtraLoad(GV, getTargetMachine(), false))
3659 Result = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), Result, NULL, 0);
3664 // Lower ISD::GlobalTLSAddress using the "general dynamic" model
3666 LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
3667 const MVT::ValueType PtrVT) {
3669 SDOperand Chain = DAG.getCopyToReg(DAG.getEntryNode(), X86::EBX,
3670 DAG.getNode(X86ISD::GlobalBaseReg,
3672 InFlag = Chain.getValue(1);
3674 // emit leal symbol@TLSGD(,%ebx,1), %eax
3675 SDVTList NodeTys = DAG.getVTList(PtrVT, MVT::Other, MVT::Flag);
3676 SDOperand TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
3677 GA->getValueType(0),
3679 SDOperand Ops[] = { Chain, TGA, InFlag };
3680 SDOperand Result = DAG.getNode(X86ISD::TLSADDR, NodeTys, Ops, 3);
3681 InFlag = Result.getValue(2);
3682 Chain = Result.getValue(1);
3684 // call ___tls_get_addr. This function receives its argument in
3685 // the register EAX.
3686 Chain = DAG.getCopyToReg(Chain, X86::EAX, Result, InFlag);
3687 InFlag = Chain.getValue(1);
3689 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
3690 SDOperand Ops1[] = { Chain,
3691 DAG.getTargetExternalSymbol("___tls_get_addr",
3693 DAG.getRegister(X86::EAX, PtrVT),
3694 DAG.getRegister(X86::EBX, PtrVT),
3696 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops1, 5);
3697 InFlag = Chain.getValue(1);
3699 return DAG.getCopyFromReg(Chain, X86::EAX, PtrVT, InFlag);
3702 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
3703 // "local exec" model.
3705 LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
3706 const MVT::ValueType PtrVT) {
3707 // Get the Thread Pointer
3708 SDOperand ThreadPointer = DAG.getNode(X86ISD::THREAD_POINTER, PtrVT);
3709 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
3711 SDOperand TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
3712 GA->getValueType(0),
3714 SDOperand Offset = DAG.getNode(X86ISD::Wrapper, PtrVT, TGA);
3716 if (GA->getGlobal()->isDeclaration()) // initial exec TLS model
3717 Offset = DAG.getLoad(PtrVT, DAG.getEntryNode(), Offset, NULL, 0);
3719 // The address of the thread local variable is the add of the thread
3720 // pointer with the offset of the variable.
3721 return DAG.getNode(ISD::ADD, PtrVT, ThreadPointer, Offset);
3725 X86TargetLowering::LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG) {
3726 // TODO: implement the "local dynamic" model
3727 // TODO: implement the "initial exec"model for pic executables
3728 assert(!Subtarget->is64Bit() && Subtarget->isTargetELF() &&
3729 "TLS not implemented for non-ELF and 64-bit targets");
3730 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
3731 // If the relocation model is PIC, use the "General Dynamic" TLS Model,
3732 // otherwise use the "Local Exec"TLS Model
3733 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
3734 return LowerToTLSGeneralDynamicModel(GA, DAG, getPointerTy());
3736 return LowerToTLSExecModel(GA, DAG, getPointerTy());
3740 X86TargetLowering::LowerExternalSymbol(SDOperand Op, SelectionDAG &DAG) {
3741 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
3742 SDOperand Result = DAG.getTargetExternalSymbol(Sym, getPointerTy());
3743 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
3744 // With PIC, the address is actually $g + Offset.
3745 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
3746 !Subtarget->isPICStyleRIPRel()) {
3747 Result = DAG.getNode(ISD::ADD, getPointerTy(),
3748 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
3755 SDOperand X86TargetLowering::LowerJumpTable(SDOperand Op, SelectionDAG &DAG) {
3756 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
3757 SDOperand Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy());
3758 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
3759 // With PIC, the address is actually $g + Offset.
3760 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
3761 !Subtarget->isPICStyleRIPRel()) {
3762 Result = DAG.getNode(ISD::ADD, getPointerTy(),
3763 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
3770 /// LowerShift - Lower SRA_PARTS and friends, which return two i32 values and
3771 /// take a 2 x i32 value to shift plus a shift amount.
3772 SDOperand X86TargetLowering::LowerShift(SDOperand Op, SelectionDAG &DAG) {
3773 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 &&
3774 "Not an i64 shift!");
3775 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
3776 SDOperand ShOpLo = Op.getOperand(0);
3777 SDOperand ShOpHi = Op.getOperand(1);
3778 SDOperand ShAmt = Op.getOperand(2);
3779 SDOperand Tmp1 = isSRA ?
3780 DAG.getNode(ISD::SRA, MVT::i32, ShOpHi, DAG.getConstant(31, MVT::i8)) :
3781 DAG.getConstant(0, MVT::i32);
3783 SDOperand Tmp2, Tmp3;
3784 if (Op.getOpcode() == ISD::SHL_PARTS) {
3785 Tmp2 = DAG.getNode(X86ISD::SHLD, MVT::i32, ShOpHi, ShOpLo, ShAmt);
3786 Tmp3 = DAG.getNode(ISD::SHL, MVT::i32, ShOpLo, ShAmt);
3788 Tmp2 = DAG.getNode(X86ISD::SHRD, MVT::i32, ShOpLo, ShOpHi, ShAmt);
3789 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, MVT::i32, ShOpHi, ShAmt);
3792 const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag);
3793 SDOperand AndNode = DAG.getNode(ISD::AND, MVT::i8, ShAmt,
3794 DAG.getConstant(32, MVT::i8));
3795 SDOperand Cond = DAG.getNode(X86ISD::CMP, MVT::i32,
3796 AndNode, DAG.getConstant(0, MVT::i8));
3799 SDOperand CC = DAG.getConstant(X86::COND_NE, MVT::i8);
3800 VTs = DAG.getNodeValueTypes(MVT::i32, MVT::Flag);
3801 SmallVector<SDOperand, 4> Ops;
3802 if (Op.getOpcode() == ISD::SHL_PARTS) {
3803 Ops.push_back(Tmp2);
3804 Ops.push_back(Tmp3);
3806 Ops.push_back(Cond);
3807 Hi = DAG.getNode(X86ISD::CMOV, MVT::i32, &Ops[0], Ops.size());
3810 Ops.push_back(Tmp3);
3811 Ops.push_back(Tmp1);
3813 Ops.push_back(Cond);
3814 Lo = DAG.getNode(X86ISD::CMOV, MVT::i32, &Ops[0], Ops.size());
3816 Ops.push_back(Tmp2);
3817 Ops.push_back(Tmp3);
3819 Ops.push_back(Cond);
3820 Lo = DAG.getNode(X86ISD::CMOV, MVT::i32, &Ops[0], Ops.size());
3823 Ops.push_back(Tmp3);
3824 Ops.push_back(Tmp1);
3826 Ops.push_back(Cond);
3827 Hi = DAG.getNode(X86ISD::CMOV, MVT::i32, &Ops[0], Ops.size());
3830 VTs = DAG.getNodeValueTypes(MVT::i32, MVT::i32);
3834 return DAG.getNode(ISD::MERGE_VALUES, VTs, 2, &Ops[0], Ops.size());
3837 SDOperand X86TargetLowering::LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
3838 assert(Op.getOperand(0).getValueType() <= MVT::i64 &&
3839 Op.getOperand(0).getValueType() >= MVT::i16 &&
3840 "Unknown SINT_TO_FP to lower!");
3843 MVT::ValueType SrcVT = Op.getOperand(0).getValueType();
3844 unsigned Size = MVT::getSizeInBits(SrcVT)/8;
3845 MachineFunction &MF = DAG.getMachineFunction();
3846 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
3847 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
3848 SDOperand Chain = DAG.getStore(DAG.getEntryNode(), Op.getOperand(0),
3849 StackSlot, NULL, 0);
3851 // These are really Legal; caller falls through into that case.
3852 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
3854 if (SrcVT == MVT::i64 && Op.getValueType() != MVT::f80 &&
3855 Subtarget->is64Bit())
3860 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
3862 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag);
3864 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
3865 SmallVector<SDOperand, 8> Ops;
3866 Ops.push_back(Chain);
3867 Ops.push_back(StackSlot);
3868 Ops.push_back(DAG.getValueType(SrcVT));
3869 Result = DAG.getNode(useSSE ? X86ISD::FILD_FLAG :X86ISD::FILD,
3870 Tys, &Ops[0], Ops.size());
3873 Chain = Result.getValue(1);
3874 SDOperand InFlag = Result.getValue(2);
3876 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
3877 // shouldn't be necessary except that RFP cannot be live across
3878 // multiple blocks. When stackifier is fixed, they can be uncoupled.
3879 MachineFunction &MF = DAG.getMachineFunction();
3880 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
3881 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
3882 Tys = DAG.getVTList(MVT::Other);
3883 SmallVector<SDOperand, 8> Ops;
3884 Ops.push_back(Chain);
3885 Ops.push_back(Result);
3886 Ops.push_back(StackSlot);
3887 Ops.push_back(DAG.getValueType(Op.getValueType()));
3888 Ops.push_back(InFlag);
3889 Chain = DAG.getNode(X86ISD::FST, Tys, &Ops[0], Ops.size());
3890 Result = DAG.getLoad(Op.getValueType(), Chain, StackSlot, NULL, 0);
3896 std::pair<SDOperand,SDOperand> X86TargetLowering::
3897 FP_TO_SINTHelper(SDOperand Op, SelectionDAG &DAG) {
3898 assert(Op.getValueType() <= MVT::i64 && Op.getValueType() >= MVT::i16 &&
3899 "Unknown FP_TO_SINT to lower!");
3901 // These are really Legal.
3902 if (Op.getValueType() == MVT::i32 &&
3903 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
3904 return std::make_pair(SDOperand(), SDOperand());
3905 if (Subtarget->is64Bit() &&
3906 Op.getValueType() == MVT::i64 &&
3907 Op.getOperand(0).getValueType() != MVT::f80)
3908 return std::make_pair(SDOperand(), SDOperand());
3910 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
3912 MachineFunction &MF = DAG.getMachineFunction();
3913 unsigned MemSize = MVT::getSizeInBits(Op.getValueType())/8;
3914 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
3915 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
3917 switch (Op.getValueType()) {
3918 default: assert(0 && "Invalid FP_TO_SINT to lower!");
3919 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
3920 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
3921 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
3924 SDOperand Chain = DAG.getEntryNode();
3925 SDOperand Value = Op.getOperand(0);
3926 if (isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) {
3927 assert(Op.getValueType() == MVT::i64 && "Invalid FP_TO_SINT to lower!");
3928 Chain = DAG.getStore(Chain, Value, StackSlot, NULL, 0);
3929 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
3931 Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType())
3933 Value = DAG.getNode(X86ISD::FLD, Tys, Ops, 3);
3934 Chain = Value.getValue(1);
3935 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
3936 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
3939 // Build the FP_TO_INT*_IN_MEM
3940 SDOperand Ops[] = { Chain, Value, StackSlot };
3941 SDOperand FIST = DAG.getNode(Opc, MVT::Other, Ops, 3);
3943 return std::make_pair(FIST, StackSlot);
3946 SDOperand X86TargetLowering::LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) {
3947 std::pair<SDOperand,SDOperand> Vals = FP_TO_SINTHelper(Op, DAG);
3948 SDOperand FIST = Vals.first, StackSlot = Vals.second;
3949 if (FIST.Val == 0) return SDOperand();
3952 return DAG.getLoad(Op.getValueType(), FIST, StackSlot, NULL, 0);
3955 SDNode *X86TargetLowering::ExpandFP_TO_SINT(SDNode *N, SelectionDAG &DAG) {
3956 std::pair<SDOperand,SDOperand> Vals = FP_TO_SINTHelper(SDOperand(N, 0), DAG);
3957 SDOperand FIST = Vals.first, StackSlot = Vals.second;
3958 if (FIST.Val == 0) return 0;
3960 // Return an i64 load from the stack slot.
3961 SDOperand Res = DAG.getLoad(MVT::i64, FIST, StackSlot, NULL, 0);
3963 // Use a MERGE_VALUES node to drop the chain result value.
3964 return DAG.getNode(ISD::MERGE_VALUES, MVT::i64, Res).Val;
3967 SDOperand X86TargetLowering::LowerFABS(SDOperand Op, SelectionDAG &DAG) {
3968 MVT::ValueType VT = Op.getValueType();
3969 MVT::ValueType EltVT = VT;
3970 if (MVT::isVector(VT))
3971 EltVT = MVT::getVectorElementType(VT);
3972 const Type *OpNTy = MVT::getTypeForValueType(EltVT);
3973 std::vector<Constant*> CV;
3974 if (EltVT == MVT::f64) {
3975 Constant *C = ConstantFP::get(OpNTy, APFloat(APInt(64, ~(1ULL << 63))));
3979 Constant *C = ConstantFP::get(OpNTy, APFloat(APInt(32, ~(1U << 31))));
3985 Constant *C = ConstantVector::get(CV);
3986 SDOperand CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
3987 SDOperand Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0,
3989 return DAG.getNode(X86ISD::FAND, VT, Op.getOperand(0), Mask);
3992 SDOperand X86TargetLowering::LowerFNEG(SDOperand Op, SelectionDAG &DAG) {
3993 MVT::ValueType VT = Op.getValueType();
3994 MVT::ValueType EltVT = VT;
3995 unsigned EltNum = 1;
3996 if (MVT::isVector(VT)) {
3997 EltVT = MVT::getVectorElementType(VT);
3998 EltNum = MVT::getVectorNumElements(VT);
4000 const Type *OpNTy = MVT::getTypeForValueType(EltVT);
4001 std::vector<Constant*> CV;
4002 if (EltVT == MVT::f64) {
4003 Constant *C = ConstantFP::get(OpNTy, APFloat(APInt(64, 1ULL << 63)));
4007 Constant *C = ConstantFP::get(OpNTy, APFloat(APInt(32, 1U << 31)));
4013 Constant *C = ConstantVector::get(CV);
4014 SDOperand CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
4015 SDOperand Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0,
4017 if (MVT::isVector(VT)) {
4018 return DAG.getNode(ISD::BIT_CONVERT, VT,
4019 DAG.getNode(ISD::XOR, MVT::v2i64,
4020 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, Op.getOperand(0)),
4021 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, Mask)));
4023 return DAG.getNode(X86ISD::FXOR, VT, Op.getOperand(0), Mask);
4027 SDOperand X86TargetLowering::LowerFCOPYSIGN(SDOperand Op, SelectionDAG &DAG) {
4028 SDOperand Op0 = Op.getOperand(0);
4029 SDOperand Op1 = Op.getOperand(1);
4030 MVT::ValueType VT = Op.getValueType();
4031 MVT::ValueType SrcVT = Op1.getValueType();
4032 const Type *SrcTy = MVT::getTypeForValueType(SrcVT);
4034 // If second operand is smaller, extend it first.
4035 if (MVT::getSizeInBits(SrcVT) < MVT::getSizeInBits(VT)) {
4036 Op1 = DAG.getNode(ISD::FP_EXTEND, VT, Op1);
4038 SrcTy = MVT::getTypeForValueType(SrcVT);
4040 // And if it is bigger, shrink it first.
4041 if (MVT::getSizeInBits(SrcVT) > MVT::getSizeInBits(VT)) {
4042 Op1 = DAG.getNode(ISD::FP_ROUND, VT, Op1, DAG.getIntPtrConstant(1));
4044 SrcTy = MVT::getTypeForValueType(SrcVT);
4047 // At this point the operands and the result should have the same
4048 // type, and that won't be f80 since that is not custom lowered.
4050 // First get the sign bit of second operand.
4051 std::vector<Constant*> CV;
4052 if (SrcVT == MVT::f64) {
4053 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(64, 1ULL << 63))));
4054 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(64, 0))));
4056 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(32, 1U << 31))));
4057 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(32, 0))));
4058 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(32, 0))));
4059 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(32, 0))));
4061 Constant *C = ConstantVector::get(CV);
4062 SDOperand CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
4063 SDOperand Mask1 = DAG.getLoad(SrcVT, DAG.getEntryNode(), CPIdx, NULL, 0,
4065 SDOperand SignBit = DAG.getNode(X86ISD::FAND, SrcVT, Op1, Mask1);
4067 // Shift sign bit right or left if the two operands have different types.
4068 if (MVT::getSizeInBits(SrcVT) > MVT::getSizeInBits(VT)) {
4069 // Op0 is MVT::f32, Op1 is MVT::f64.
4070 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v2f64, SignBit);
4071 SignBit = DAG.getNode(X86ISD::FSRL, MVT::v2f64, SignBit,
4072 DAG.getConstant(32, MVT::i32));
4073 SignBit = DAG.getNode(ISD::BIT_CONVERT, MVT::v4f32, SignBit);
4074 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::f32, SignBit,
4075 DAG.getIntPtrConstant(0));
4078 // Clear first operand sign bit.
4080 if (VT == MVT::f64) {
4081 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(64, ~(1ULL << 63)))));
4082 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(64, 0))));
4084 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(32, ~(1U << 31)))));
4085 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(32, 0))));
4086 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(32, 0))));
4087 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(32, 0))));
4089 C = ConstantVector::get(CV);
4090 CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
4091 SDOperand Mask2 = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0,
4093 SDOperand Val = DAG.getNode(X86ISD::FAND, VT, Op0, Mask2);
4095 // Or the value with the sign bit.
4096 return DAG.getNode(X86ISD::FOR, VT, Val, SignBit);
4099 SDOperand X86TargetLowering::LowerSETCC(SDOperand Op, SelectionDAG &DAG) {
4100 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
4102 SDOperand Op0 = Op.getOperand(0);
4103 SDOperand Op1 = Op.getOperand(1);
4104 SDOperand CC = Op.getOperand(2);
4105 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
4106 bool isFP = MVT::isFloatingPoint(Op.getOperand(1).getValueType());
4109 if (translateX86CC(cast<CondCodeSDNode>(CC)->get(), isFP, X86CC,
4111 Cond = DAG.getNode(X86ISD::CMP, MVT::i32, Op0, Op1);
4112 return DAG.getNode(X86ISD::SETCC, MVT::i8,
4113 DAG.getConstant(X86CC, MVT::i8), Cond);
4116 assert(isFP && "Illegal integer SetCC!");
4118 Cond = DAG.getNode(X86ISD::CMP, MVT::i32, Op0, Op1);
4119 switch (SetCCOpcode) {
4120 default: assert(false && "Illegal floating point SetCC!");
4121 case ISD::SETOEQ: { // !PF & ZF
4122 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, MVT::i8,
4123 DAG.getConstant(X86::COND_NP, MVT::i8), Cond);
4124 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8,
4125 DAG.getConstant(X86::COND_E, MVT::i8), Cond);
4126 return DAG.getNode(ISD::AND, MVT::i8, Tmp1, Tmp2);
4128 case ISD::SETUNE: { // PF | !ZF
4129 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, MVT::i8,
4130 DAG.getConstant(X86::COND_P, MVT::i8), Cond);
4131 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8,
4132 DAG.getConstant(X86::COND_NE, MVT::i8), Cond);
4133 return DAG.getNode(ISD::OR, MVT::i8, Tmp1, Tmp2);
4139 SDOperand X86TargetLowering::LowerSELECT(SDOperand Op, SelectionDAG &DAG) {
4140 bool addTest = true;
4141 SDOperand Cond = Op.getOperand(0);
4144 if (Cond.getOpcode() == ISD::SETCC)
4145 Cond = LowerSETCC(Cond, DAG);
4147 // If condition flag is set by a X86ISD::CMP, then use it as the condition
4148 // setting operand in place of the X86ISD::SETCC.
4149 if (Cond.getOpcode() == X86ISD::SETCC) {
4150 CC = Cond.getOperand(0);
4152 SDOperand Cmp = Cond.getOperand(1);
4153 unsigned Opc = Cmp.getOpcode();
4154 MVT::ValueType VT = Op.getValueType();
4156 bool IllegalFPCMov = false;
4157 if (MVT::isFloatingPoint(VT) && !MVT::isVector(VT) &&
4158 !isScalarFPTypeInSSEReg(VT)) // FPStack?
4159 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSignExtended());
4161 if ((Opc == X86ISD::CMP ||
4162 Opc == X86ISD::COMI ||
4163 Opc == X86ISD::UCOMI) && !IllegalFPCMov) {
4170 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
4171 Cond= DAG.getNode(X86ISD::CMP, MVT::i32, Cond, DAG.getConstant(0, MVT::i8));
4174 const MVT::ValueType *VTs = DAG.getNodeValueTypes(Op.getValueType(),
4176 SmallVector<SDOperand, 4> Ops;
4177 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
4178 // condition is true.
4179 Ops.push_back(Op.getOperand(2));
4180 Ops.push_back(Op.getOperand(1));
4182 Ops.push_back(Cond);
4183 return DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size());
4186 SDOperand X86TargetLowering::LowerBRCOND(SDOperand Op, SelectionDAG &DAG) {
4187 bool addTest = true;
4188 SDOperand Chain = Op.getOperand(0);
4189 SDOperand Cond = Op.getOperand(1);
4190 SDOperand Dest = Op.getOperand(2);
4193 if (Cond.getOpcode() == ISD::SETCC)
4194 Cond = LowerSETCC(Cond, DAG);
4196 // If condition flag is set by a X86ISD::CMP, then use it as the condition
4197 // setting operand in place of the X86ISD::SETCC.
4198 if (Cond.getOpcode() == X86ISD::SETCC) {
4199 CC = Cond.getOperand(0);
4201 SDOperand Cmp = Cond.getOperand(1);
4202 unsigned Opc = Cmp.getOpcode();
4203 if (Opc == X86ISD::CMP ||
4204 Opc == X86ISD::COMI ||
4205 Opc == X86ISD::UCOMI) {
4212 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
4213 Cond= DAG.getNode(X86ISD::CMP, MVT::i32, Cond, DAG.getConstant(0, MVT::i8));
4215 return DAG.getNode(X86ISD::BRCOND, Op.getValueType(),
4216 Chain, Op.getOperand(2), CC, Cond);
4220 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
4221 // Calls to _alloca is needed to probe the stack when allocating more than 4k
4222 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
4223 // that the guard pages used by the OS virtual memory manager are allocated in
4224 // correct sequence.
4226 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDOperand Op,
4227 SelectionDAG &DAG) {
4228 assert(Subtarget->isTargetCygMing() &&
4229 "This should be used only on Cygwin/Mingw targets");
4232 SDOperand Chain = Op.getOperand(0);
4233 SDOperand Size = Op.getOperand(1);
4234 // FIXME: Ensure alignment here
4238 MVT::ValueType IntPtr = getPointerTy();
4239 MVT::ValueType SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32;
4241 Chain = DAG.getCopyToReg(Chain, X86::EAX, Size, Flag);
4242 Flag = Chain.getValue(1);
4244 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
4245 SDOperand Ops[] = { Chain,
4246 DAG.getTargetExternalSymbol("_alloca", IntPtr),
4247 DAG.getRegister(X86::EAX, IntPtr),
4249 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops, 4);
4250 Flag = Chain.getValue(1);
4252 Chain = DAG.getCopyFromReg(Chain, X86StackPtr, SPTy).getValue(1);
4254 std::vector<MVT::ValueType> Tys;
4255 Tys.push_back(SPTy);
4256 Tys.push_back(MVT::Other);
4257 SDOperand Ops1[2] = { Chain.getValue(0), Chain };
4258 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops1, 2);
4261 SDOperand X86TargetLowering::LowerMEMSET(SDOperand Op, SelectionDAG &DAG) {
4262 SDOperand InFlag(0, 0);
4263 SDOperand Chain = Op.getOperand(0);
4265 (unsigned)cast<ConstantSDNode>(Op.getOperand(4))->getValue();
4266 if (Align == 0) Align = 1;
4268 ConstantSDNode *I = dyn_cast<ConstantSDNode>(Op.getOperand(3));
4269 // If not DWORD aligned or size is more than the threshold, call memset.
4270 // The libc version is likely to be faster for these cases. It can use the
4271 // address value and run time information about the CPU.
4272 if ((Align & 3) != 0 ||
4273 (I && I->getValue() > Subtarget->getMaxInlineSizeThreshold())) {
4274 MVT::ValueType IntPtr = getPointerTy();
4275 const Type *IntPtrTy = getTargetData()->getIntPtrType();
4276 TargetLowering::ArgListTy Args;
4277 TargetLowering::ArgListEntry Entry;
4278 Entry.Node = Op.getOperand(1);
4279 Entry.Ty = IntPtrTy;
4280 Args.push_back(Entry);
4281 // Extend the unsigned i8 argument to be an int value for the call.
4282 Entry.Node = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Op.getOperand(2));
4283 Entry.Ty = IntPtrTy;
4284 Args.push_back(Entry);
4285 Entry.Node = Op.getOperand(3);
4286 Args.push_back(Entry);
4287 std::pair<SDOperand,SDOperand> CallResult =
4288 LowerCallTo(Chain, Type::VoidTy, false, false, CallingConv::C, false,
4289 DAG.getExternalSymbol("memset", IntPtr), Args, DAG);
4290 return CallResult.second;
4295 ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Op.getOperand(2));
4296 unsigned BytesLeft = 0;
4297 bool TwoRepStos = false;
4300 uint64_t Val = ValC->getValue() & 255;
4302 // If the value is a constant, then we can potentially use larger sets.
4303 switch (Align & 3) {
4304 case 2: // WORD aligned
4307 Val = (Val << 8) | Val;
4309 case 0: // DWORD aligned
4312 Val = (Val << 8) | Val;
4313 Val = (Val << 16) | Val;
4314 if (Subtarget->is64Bit() && ((Align & 0xF) == 0)) { // QWORD aligned
4317 Val = (Val << 32) | Val;
4320 default: // Byte aligned
4323 Count = Op.getOperand(3);
4327 if (AVT > MVT::i8) {
4329 unsigned UBytes = MVT::getSizeInBits(AVT) / 8;
4330 Count = DAG.getIntPtrConstant(I->getValue() / UBytes);
4331 BytesLeft = I->getValue() % UBytes;
4333 assert(AVT >= MVT::i32 &&
4334 "Do not use rep;stos if not at least DWORD aligned");
4335 Count = DAG.getNode(ISD::SRL, Op.getOperand(3).getValueType(),
4336 Op.getOperand(3), DAG.getConstant(2, MVT::i8));
4341 Chain = DAG.getCopyToReg(Chain, ValReg, DAG.getConstant(Val, AVT),
4343 InFlag = Chain.getValue(1);
4346 Count = Op.getOperand(3);
4347 Chain = DAG.getCopyToReg(Chain, X86::AL, Op.getOperand(2), InFlag);
4348 InFlag = Chain.getValue(1);
4351 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RCX : X86::ECX,
4353 InFlag = Chain.getValue(1);
4354 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RDI : X86::EDI,
4355 Op.getOperand(1), InFlag);
4356 InFlag = Chain.getValue(1);
4358 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
4359 SmallVector<SDOperand, 8> Ops;
4360 Ops.push_back(Chain);
4361 Ops.push_back(DAG.getValueType(AVT));
4362 Ops.push_back(InFlag);
4363 Chain = DAG.getNode(X86ISD::REP_STOS, Tys, &Ops[0], Ops.size());
4366 InFlag = Chain.getValue(1);
4367 Count = Op.getOperand(3);
4368 MVT::ValueType CVT = Count.getValueType();
4369 SDOperand Left = DAG.getNode(ISD::AND, CVT, Count,
4370 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT));
4371 Chain = DAG.getCopyToReg(Chain, (CVT == MVT::i64) ? X86::RCX : X86::ECX,
4373 InFlag = Chain.getValue(1);
4374 Tys = DAG.getVTList(MVT::Other, MVT::Flag);
4376 Ops.push_back(Chain);
4377 Ops.push_back(DAG.getValueType(MVT::i8));
4378 Ops.push_back(InFlag);
4379 Chain = DAG.getNode(X86ISD::REP_STOS, Tys, &Ops[0], Ops.size());
4380 } else if (BytesLeft) {
4381 // Issue stores for the last 1 - 7 bytes.
4383 unsigned Val = ValC->getValue() & 255;
4384 unsigned Offset = I->getValue() - BytesLeft;
4385 SDOperand DstAddr = Op.getOperand(1);
4386 MVT::ValueType AddrVT = DstAddr.getValueType();
4387 if (BytesLeft >= 4) {
4388 Val = (Val << 8) | Val;
4389 Val = (Val << 16) | Val;
4390 Value = DAG.getConstant(Val, MVT::i32);
4391 Chain = DAG.getStore(Chain, Value,
4392 DAG.getNode(ISD::ADD, AddrVT, DstAddr,
4393 DAG.getConstant(Offset, AddrVT)),
4398 if (BytesLeft >= 2) {
4399 Value = DAG.getConstant((Val << 8) | Val, MVT::i16);
4400 Chain = DAG.getStore(Chain, Value,
4401 DAG.getNode(ISD::ADD, AddrVT, DstAddr,
4402 DAG.getConstant(Offset, AddrVT)),
4407 if (BytesLeft == 1) {
4408 Value = DAG.getConstant(Val, MVT::i8);
4409 Chain = DAG.getStore(Chain, Value,
4410 DAG.getNode(ISD::ADD, AddrVT, DstAddr,
4411 DAG.getConstant(Offset, AddrVT)),
4419 SDOperand X86TargetLowering::LowerMEMCPYInline(SDOperand Chain,
4424 SelectionDAG &DAG) {
4426 unsigned BytesLeft = 0;
4427 switch (Align & 3) {
4428 case 2: // WORD aligned
4431 case 0: // DWORD aligned
4433 if (Subtarget->is64Bit() && ((Align & 0xF) == 0)) // QWORD aligned
4436 default: // Byte aligned
4441 unsigned UBytes = MVT::getSizeInBits(AVT) / 8;
4442 SDOperand Count = DAG.getIntPtrConstant(Size / UBytes);
4443 BytesLeft = Size % UBytes;
4445 SDOperand InFlag(0, 0);
4446 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RCX : X86::ECX,
4448 InFlag = Chain.getValue(1);
4449 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RDI : X86::EDI,
4451 InFlag = Chain.getValue(1);
4452 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RSI : X86::ESI,
4454 InFlag = Chain.getValue(1);
4456 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
4457 SmallVector<SDOperand, 8> Ops;
4458 Ops.push_back(Chain);
4459 Ops.push_back(DAG.getValueType(AVT));
4460 Ops.push_back(InFlag);
4461 Chain = DAG.getNode(X86ISD::REP_MOVS, Tys, &Ops[0], Ops.size());
4464 // Issue loads and stores for the last 1 - 7 bytes.
4465 unsigned Offset = Size - BytesLeft;
4466 SDOperand DstAddr = Dest;
4467 MVT::ValueType DstVT = DstAddr.getValueType();
4468 SDOperand SrcAddr = Source;
4469 MVT::ValueType SrcVT = SrcAddr.getValueType();
4471 if (BytesLeft >= 4) {
4472 Value = DAG.getLoad(MVT::i32, Chain,
4473 DAG.getNode(ISD::ADD, SrcVT, SrcAddr,
4474 DAG.getConstant(Offset, SrcVT)),
4476 Chain = Value.getValue(1);
4477 Chain = DAG.getStore(Chain, Value,
4478 DAG.getNode(ISD::ADD, DstVT, DstAddr,
4479 DAG.getConstant(Offset, DstVT)),
4484 if (BytesLeft >= 2) {
4485 Value = DAG.getLoad(MVT::i16, Chain,
4486 DAG.getNode(ISD::ADD, SrcVT, SrcAddr,
4487 DAG.getConstant(Offset, SrcVT)),
4489 Chain = Value.getValue(1);
4490 Chain = DAG.getStore(Chain, Value,
4491 DAG.getNode(ISD::ADD, DstVT, DstAddr,
4492 DAG.getConstant(Offset, DstVT)),
4498 if (BytesLeft == 1) {
4499 Value = DAG.getLoad(MVT::i8, Chain,
4500 DAG.getNode(ISD::ADD, SrcVT, SrcAddr,
4501 DAG.getConstant(Offset, SrcVT)),
4503 Chain = Value.getValue(1);
4504 Chain = DAG.getStore(Chain, Value,
4505 DAG.getNode(ISD::ADD, DstVT, DstAddr,
4506 DAG.getConstant(Offset, DstVT)),
4514 /// Expand the result of: i64,outchain = READCYCLECOUNTER inchain
4515 SDNode *X86TargetLowering::ExpandREADCYCLECOUNTER(SDNode *N, SelectionDAG &DAG){
4516 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
4517 SDOperand TheChain = N->getOperand(0);
4518 SDOperand rd = DAG.getNode(X86ISD::RDTSC_DAG, Tys, &TheChain, 1);
4519 if (Subtarget->is64Bit()) {
4520 SDOperand rax = DAG.getCopyFromReg(rd, X86::RAX, MVT::i64, rd.getValue(1));
4521 SDOperand rdx = DAG.getCopyFromReg(rax.getValue(1), X86::RDX,
4522 MVT::i64, rax.getValue(2));
4523 SDOperand Tmp = DAG.getNode(ISD::SHL, MVT::i64, rdx,
4524 DAG.getConstant(32, MVT::i8));
4526 DAG.getNode(ISD::OR, MVT::i64, rax, Tmp), rdx.getValue(1)
4529 Tys = DAG.getVTList(MVT::i64, MVT::Other);
4530 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 2).Val;
4533 SDOperand eax = DAG.getCopyFromReg(rd, X86::EAX, MVT::i32, rd.getValue(1));
4534 SDOperand edx = DAG.getCopyFromReg(eax.getValue(1), X86::EDX,
4535 MVT::i32, eax.getValue(2));
4536 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
4537 SDOperand Ops[] = { eax, edx };
4538 Ops[0] = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Ops, 2);
4540 // Use a MERGE_VALUES to return the value and chain.
4541 Ops[1] = edx.getValue(1);
4542 Tys = DAG.getVTList(MVT::i64, MVT::Other);
4543 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 2).Val;
4546 SDOperand X86TargetLowering::LowerVASTART(SDOperand Op, SelectionDAG &DAG) {
4547 SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2));
4549 if (!Subtarget->is64Bit()) {
4550 // vastart just stores the address of the VarArgsFrameIndex slot into the
4551 // memory location argument.
4552 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
4553 return DAG.getStore(Op.getOperand(0), FR,Op.getOperand(1), SV->getValue(),
4558 // gp_offset (0 - 6 * 8)
4559 // fp_offset (48 - 48 + 8 * 16)
4560 // overflow_arg_area (point to parameters coming in memory).
4562 SmallVector<SDOperand, 8> MemOps;
4563 SDOperand FIN = Op.getOperand(1);
4565 SDOperand Store = DAG.getStore(Op.getOperand(0),
4566 DAG.getConstant(VarArgsGPOffset, MVT::i32),
4567 FIN, SV->getValue(), SV->getOffset());
4568 MemOps.push_back(Store);
4571 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(4));
4572 Store = DAG.getStore(Op.getOperand(0),
4573 DAG.getConstant(VarArgsFPOffset, MVT::i32),
4574 FIN, SV->getValue(), SV->getOffset());
4575 MemOps.push_back(Store);
4577 // Store ptr to overflow_arg_area
4578 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(4));
4579 SDOperand OVFIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
4580 Store = DAG.getStore(Op.getOperand(0), OVFIN, FIN, SV->getValue(),
4582 MemOps.push_back(Store);
4584 // Store ptr to reg_save_area.
4585 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(8));
4586 SDOperand RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
4587 Store = DAG.getStore(Op.getOperand(0), RSFIN, FIN, SV->getValue(),
4589 MemOps.push_back(Store);
4590 return DAG.getNode(ISD::TokenFactor, MVT::Other, &MemOps[0], MemOps.size());
4593 SDOperand X86TargetLowering::LowerVACOPY(SDOperand Op, SelectionDAG &DAG) {
4594 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
4595 SDOperand Chain = Op.getOperand(0);
4596 SDOperand DstPtr = Op.getOperand(1);
4597 SDOperand SrcPtr = Op.getOperand(2);
4598 SrcValueSDNode *DstSV = cast<SrcValueSDNode>(Op.getOperand(3));
4599 SrcValueSDNode *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4));
4601 SrcPtr = DAG.getLoad(getPointerTy(), Chain, SrcPtr,
4602 SrcSV->getValue(), SrcSV->getOffset());
4603 Chain = SrcPtr.getValue(1);
4604 for (unsigned i = 0; i < 3; ++i) {
4605 SDOperand Val = DAG.getLoad(MVT::i64, Chain, SrcPtr,
4606 SrcSV->getValue(), SrcSV->getOffset());
4607 Chain = Val.getValue(1);
4608 Chain = DAG.getStore(Chain, Val, DstPtr,
4609 DstSV->getValue(), DstSV->getOffset());
4612 SrcPtr = DAG.getNode(ISD::ADD, getPointerTy(), SrcPtr,
4613 DAG.getIntPtrConstant(8));
4614 DstPtr = DAG.getNode(ISD::ADD, getPointerTy(), DstPtr,
4615 DAG.getIntPtrConstant(8));
4621 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG) {
4622 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getValue();
4624 default: return SDOperand(); // Don't custom lower most intrinsics.
4625 // Comparison intrinsics.
4626 case Intrinsic::x86_sse_comieq_ss:
4627 case Intrinsic::x86_sse_comilt_ss:
4628 case Intrinsic::x86_sse_comile_ss:
4629 case Intrinsic::x86_sse_comigt_ss:
4630 case Intrinsic::x86_sse_comige_ss:
4631 case Intrinsic::x86_sse_comineq_ss:
4632 case Intrinsic::x86_sse_ucomieq_ss:
4633 case Intrinsic::x86_sse_ucomilt_ss:
4634 case Intrinsic::x86_sse_ucomile_ss:
4635 case Intrinsic::x86_sse_ucomigt_ss:
4636 case Intrinsic::x86_sse_ucomige_ss:
4637 case Intrinsic::x86_sse_ucomineq_ss:
4638 case Intrinsic::x86_sse2_comieq_sd:
4639 case Intrinsic::x86_sse2_comilt_sd:
4640 case Intrinsic::x86_sse2_comile_sd:
4641 case Intrinsic::x86_sse2_comigt_sd:
4642 case Intrinsic::x86_sse2_comige_sd:
4643 case Intrinsic::x86_sse2_comineq_sd:
4644 case Intrinsic::x86_sse2_ucomieq_sd:
4645 case Intrinsic::x86_sse2_ucomilt_sd:
4646 case Intrinsic::x86_sse2_ucomile_sd:
4647 case Intrinsic::x86_sse2_ucomigt_sd:
4648 case Intrinsic::x86_sse2_ucomige_sd:
4649 case Intrinsic::x86_sse2_ucomineq_sd: {
4651 ISD::CondCode CC = ISD::SETCC_INVALID;
4654 case Intrinsic::x86_sse_comieq_ss:
4655 case Intrinsic::x86_sse2_comieq_sd:
4659 case Intrinsic::x86_sse_comilt_ss:
4660 case Intrinsic::x86_sse2_comilt_sd:
4664 case Intrinsic::x86_sse_comile_ss:
4665 case Intrinsic::x86_sse2_comile_sd:
4669 case Intrinsic::x86_sse_comigt_ss:
4670 case Intrinsic::x86_sse2_comigt_sd:
4674 case Intrinsic::x86_sse_comige_ss:
4675 case Intrinsic::x86_sse2_comige_sd:
4679 case Intrinsic::x86_sse_comineq_ss:
4680 case Intrinsic::x86_sse2_comineq_sd:
4684 case Intrinsic::x86_sse_ucomieq_ss:
4685 case Intrinsic::x86_sse2_ucomieq_sd:
4686 Opc = X86ISD::UCOMI;
4689 case Intrinsic::x86_sse_ucomilt_ss:
4690 case Intrinsic::x86_sse2_ucomilt_sd:
4691 Opc = X86ISD::UCOMI;
4694 case Intrinsic::x86_sse_ucomile_ss:
4695 case Intrinsic::x86_sse2_ucomile_sd:
4696 Opc = X86ISD::UCOMI;
4699 case Intrinsic::x86_sse_ucomigt_ss:
4700 case Intrinsic::x86_sse2_ucomigt_sd:
4701 Opc = X86ISD::UCOMI;
4704 case Intrinsic::x86_sse_ucomige_ss:
4705 case Intrinsic::x86_sse2_ucomige_sd:
4706 Opc = X86ISD::UCOMI;
4709 case Intrinsic::x86_sse_ucomineq_ss:
4710 case Intrinsic::x86_sse2_ucomineq_sd:
4711 Opc = X86ISD::UCOMI;
4717 SDOperand LHS = Op.getOperand(1);
4718 SDOperand RHS = Op.getOperand(2);
4719 translateX86CC(CC, true, X86CC, LHS, RHS, DAG);
4721 SDOperand Cond = DAG.getNode(Opc, MVT::i32, LHS, RHS);
4722 SDOperand SetCC = DAG.getNode(X86ISD::SETCC, MVT::i8,
4723 DAG.getConstant(X86CC, MVT::i8), Cond);
4724 return DAG.getNode(ISD::ANY_EXTEND, MVT::i32, SetCC);
4729 SDOperand X86TargetLowering::LowerRETURNADDR(SDOperand Op, SelectionDAG &DAG) {
4730 // Depths > 0 not supported yet!
4731 if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0)
4734 // Just load the return address
4735 SDOperand RetAddrFI = getReturnAddressFrameIndex(DAG);
4736 return DAG.getLoad(getPointerTy(), DAG.getEntryNode(), RetAddrFI, NULL, 0);
4739 SDOperand X86TargetLowering::LowerFRAMEADDR(SDOperand Op, SelectionDAG &DAG) {
4740 // Depths > 0 not supported yet!
4741 if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0)
4744 SDOperand RetAddrFI = getReturnAddressFrameIndex(DAG);
4745 return DAG.getNode(ISD::SUB, getPointerTy(), RetAddrFI,
4746 DAG.getIntPtrConstant(4));
4749 SDOperand X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDOperand Op,
4750 SelectionDAG &DAG) {
4751 // Is not yet supported on x86-64
4752 if (Subtarget->is64Bit())
4755 return DAG.getIntPtrConstant(8);
4758 SDOperand X86TargetLowering::LowerEH_RETURN(SDOperand Op, SelectionDAG &DAG)
4760 assert(!Subtarget->is64Bit() &&
4761 "Lowering of eh_return builtin is not supported yet on x86-64");
4763 MachineFunction &MF = DAG.getMachineFunction();
4764 SDOperand Chain = Op.getOperand(0);
4765 SDOperand Offset = Op.getOperand(1);
4766 SDOperand Handler = Op.getOperand(2);
4768 SDOperand Frame = DAG.getRegister(RegInfo->getFrameRegister(MF),
4771 SDOperand StoreAddr = DAG.getNode(ISD::SUB, getPointerTy(), Frame,
4772 DAG.getIntPtrConstant(-4UL));
4773 StoreAddr = DAG.getNode(ISD::ADD, getPointerTy(), StoreAddr, Offset);
4774 Chain = DAG.getStore(Chain, Handler, StoreAddr, NULL, 0);
4775 Chain = DAG.getCopyToReg(Chain, X86::ECX, StoreAddr);
4776 MF.getRegInfo().addLiveOut(X86::ECX);
4778 return DAG.getNode(X86ISD::EH_RETURN, MVT::Other,
4779 Chain, DAG.getRegister(X86::ECX, getPointerTy()));
4782 SDOperand X86TargetLowering::LowerTRAMPOLINE(SDOperand Op,
4783 SelectionDAG &DAG) {
4784 SDOperand Root = Op.getOperand(0);
4785 SDOperand Trmp = Op.getOperand(1); // trampoline
4786 SDOperand FPtr = Op.getOperand(2); // nested function
4787 SDOperand Nest = Op.getOperand(3); // 'nest' parameter value
4789 SrcValueSDNode *TrmpSV = cast<SrcValueSDNode>(Op.getOperand(4));
4791 const X86InstrInfo *TII =
4792 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
4794 if (Subtarget->is64Bit()) {
4795 SDOperand OutChains[6];
4797 // Large code-model.
4799 const unsigned char JMP64r = TII->getBaseOpcodeFor(X86::JMP64r);
4800 const unsigned char MOV64ri = TII->getBaseOpcodeFor(X86::MOV64ri);
4802 const unsigned char N86R10 =
4803 ((X86RegisterInfo*)RegInfo)->getX86RegNum(X86::R10);
4804 const unsigned char N86R11 =
4805 ((X86RegisterInfo*)RegInfo)->getX86RegNum(X86::R11);
4807 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
4809 // Load the pointer to the nested function into R11.
4810 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
4811 SDOperand Addr = Trmp;
4812 OutChains[0] = DAG.getStore(Root, DAG.getConstant(OpCode, MVT::i16), Addr,
4813 TrmpSV->getValue(), TrmpSV->getOffset());
4815 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(2, MVT::i64));
4816 OutChains[1] = DAG.getStore(Root, FPtr, Addr, TrmpSV->getValue(),
4817 TrmpSV->getOffset() + 2, false, 2);
4819 // Load the 'nest' parameter value into R10.
4820 // R10 is specified in X86CallingConv.td
4821 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
4822 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(10, MVT::i64));
4823 OutChains[2] = DAG.getStore(Root, DAG.getConstant(OpCode, MVT::i16), Addr,
4824 TrmpSV->getValue(), TrmpSV->getOffset() + 10);
4826 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(12, MVT::i64));
4827 OutChains[3] = DAG.getStore(Root, Nest, Addr, TrmpSV->getValue(),
4828 TrmpSV->getOffset() + 12, false, 2);
4830 // Jump to the nested function.
4831 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
4832 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(20, MVT::i64));
4833 OutChains[4] = DAG.getStore(Root, DAG.getConstant(OpCode, MVT::i16), Addr,
4834 TrmpSV->getValue(), TrmpSV->getOffset() + 20);
4836 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
4837 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(22, MVT::i64));
4838 OutChains[5] = DAG.getStore(Root, DAG.getConstant(ModRM, MVT::i8), Addr,
4839 TrmpSV->getValue(), TrmpSV->getOffset() + 22);
4842 { Trmp, DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains, 6) };
4843 return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(), Ops, 2);
4845 Function *Func = (Function *)
4846 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
4847 unsigned CC = Func->getCallingConv();
4852 assert(0 && "Unsupported calling convention");
4853 case CallingConv::C:
4854 case CallingConv::X86_StdCall: {
4855 // Pass 'nest' parameter in ECX.
4856 // Must be kept in sync with X86CallingConv.td
4859 // Check that ECX wasn't needed by an 'inreg' parameter.
4860 const FunctionType *FTy = Func->getFunctionType();
4861 const ParamAttrsList *Attrs = Func->getParamAttrs();
4863 if (Attrs && !Func->isVarArg()) {
4864 unsigned InRegCount = 0;
4867 for (FunctionType::param_iterator I = FTy->param_begin(),
4868 E = FTy->param_end(); I != E; ++I, ++Idx)
4869 if (Attrs->paramHasAttr(Idx, ParamAttr::InReg))
4870 // FIXME: should only count parameters that are lowered to integers.
4871 InRegCount += (getTargetData()->getTypeSizeInBits(*I) + 31) / 32;
4873 if (InRegCount > 2) {
4874 cerr << "Nest register in use - reduce number of inreg parameters!\n";
4880 case CallingConv::X86_FastCall:
4881 // Pass 'nest' parameter in EAX.
4882 // Must be kept in sync with X86CallingConv.td
4887 SDOperand OutChains[4];
4888 SDOperand Addr, Disp;
4890 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(10, MVT::i32));
4891 Disp = DAG.getNode(ISD::SUB, MVT::i32, FPtr, Addr);
4893 const unsigned char MOV32ri = TII->getBaseOpcodeFor(X86::MOV32ri);
4894 const unsigned char N86Reg =
4895 ((X86RegisterInfo*)RegInfo)->getX86RegNum(NestReg);
4896 OutChains[0] = DAG.getStore(Root, DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
4897 Trmp, TrmpSV->getValue(), TrmpSV->getOffset());
4899 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(1, MVT::i32));
4900 OutChains[1] = DAG.getStore(Root, Nest, Addr, TrmpSV->getValue(),
4901 TrmpSV->getOffset() + 1, false, 1);
4903 const unsigned char JMP = TII->getBaseOpcodeFor(X86::JMP);
4904 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(5, MVT::i32));
4905 OutChains[2] = DAG.getStore(Root, DAG.getConstant(JMP, MVT::i8), Addr,
4906 TrmpSV->getValue() + 5, TrmpSV->getOffset());
4908 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(6, MVT::i32));
4909 OutChains[3] = DAG.getStore(Root, Disp, Addr, TrmpSV->getValue(),
4910 TrmpSV->getOffset() + 6, false, 1);
4913 { Trmp, DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains, 4) };
4914 return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(), Ops, 2);
4918 SDOperand X86TargetLowering::LowerFLT_ROUNDS(SDOperand Op, SelectionDAG &DAG) {
4920 The rounding mode is in bits 11:10 of FPSR, and has the following
4927 FLT_ROUNDS, on the other hand, expects the following:
4934 To perform the conversion, we do:
4935 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
4938 MachineFunction &MF = DAG.getMachineFunction();
4939 const TargetMachine &TM = MF.getTarget();
4940 const TargetFrameInfo &TFI = *TM.getFrameInfo();
4941 unsigned StackAlignment = TFI.getStackAlignment();
4942 MVT::ValueType VT = Op.getValueType();
4944 // Save FP Control Word to stack slot
4945 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment);
4946 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
4948 SDOperand Chain = DAG.getNode(X86ISD::FNSTCW16m, MVT::Other,
4949 DAG.getEntryNode(), StackSlot);
4951 // Load FP Control Word from stack slot
4952 SDOperand CWD = DAG.getLoad(MVT::i16, Chain, StackSlot, NULL, 0);
4954 // Transform as necessary
4956 DAG.getNode(ISD::SRL, MVT::i16,
4957 DAG.getNode(ISD::AND, MVT::i16,
4958 CWD, DAG.getConstant(0x800, MVT::i16)),
4959 DAG.getConstant(11, MVT::i8));
4961 DAG.getNode(ISD::SRL, MVT::i16,
4962 DAG.getNode(ISD::AND, MVT::i16,
4963 CWD, DAG.getConstant(0x400, MVT::i16)),
4964 DAG.getConstant(9, MVT::i8));
4967 DAG.getNode(ISD::AND, MVT::i16,
4968 DAG.getNode(ISD::ADD, MVT::i16,
4969 DAG.getNode(ISD::OR, MVT::i16, CWD1, CWD2),
4970 DAG.getConstant(1, MVT::i16)),
4971 DAG.getConstant(3, MVT::i16));
4974 return DAG.getNode((MVT::getSizeInBits(VT) < 16 ?
4975 ISD::TRUNCATE : ISD::ZERO_EXTEND), VT, RetVal);
4978 SDOperand X86TargetLowering::LowerCTLZ(SDOperand Op, SelectionDAG &DAG) {
4979 MVT::ValueType VT = Op.getValueType();
4980 MVT::ValueType OpVT = VT;
4981 unsigned NumBits = MVT::getSizeInBits(VT);
4983 Op = Op.getOperand(0);
4984 if (VT == MVT::i8) {
4985 // Zero extend to i32 since there is not an i8 bsr.
4987 Op = DAG.getNode(ISD::ZERO_EXTEND, OpVT, Op);
4990 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
4991 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
4992 Op = DAG.getNode(X86ISD::BSR, VTs, Op);
4994 // If src is zero (i.e. bsr sets ZF), returns NumBits.
4995 SmallVector<SDOperand, 4> Ops;
4997 Ops.push_back(DAG.getConstant(NumBits+NumBits-1, OpVT));
4998 Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8));
4999 Ops.push_back(Op.getValue(1));
5000 Op = DAG.getNode(X86ISD::CMOV, OpVT, &Ops[0], 4);
5002 // Finally xor with NumBits-1.
5003 Op = DAG.getNode(ISD::XOR, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
5006 Op = DAG.getNode(ISD::TRUNCATE, MVT::i8, Op);
5010 SDOperand X86TargetLowering::LowerCTTZ(SDOperand Op, SelectionDAG &DAG) {
5011 MVT::ValueType VT = Op.getValueType();
5012 MVT::ValueType OpVT = VT;
5013 unsigned NumBits = MVT::getSizeInBits(VT);
5015 Op = Op.getOperand(0);
5016 if (VT == MVT::i8) {
5018 Op = DAG.getNode(ISD::ZERO_EXTEND, OpVT, Op);
5021 // Issue a bsf (scan bits forward) which also sets EFLAGS.
5022 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
5023 Op = DAG.getNode(X86ISD::BSF, VTs, Op);
5025 // If src is zero (i.e. bsf sets ZF), returns NumBits.
5026 SmallVector<SDOperand, 4> Ops;
5028 Ops.push_back(DAG.getConstant(NumBits, OpVT));
5029 Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8));
5030 Ops.push_back(Op.getValue(1));
5031 Op = DAG.getNode(X86ISD::CMOV, OpVT, &Ops[0], 4);
5034 Op = DAG.getNode(ISD::TRUNCATE, MVT::i8, Op);
5038 /// LowerOperation - Provide custom lowering hooks for some operations.
5040 SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
5041 switch (Op.getOpcode()) {
5042 default: assert(0 && "Should not custom lower this!");
5043 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
5044 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
5045 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
5046 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
5047 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
5048 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
5049 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
5050 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
5051 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
5052 case ISD::SHL_PARTS:
5053 case ISD::SRA_PARTS:
5054 case ISD::SRL_PARTS: return LowerShift(Op, DAG);
5055 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
5056 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
5057 case ISD::FABS: return LowerFABS(Op, DAG);
5058 case ISD::FNEG: return LowerFNEG(Op, DAG);
5059 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
5060 case ISD::SETCC: return LowerSETCC(Op, DAG);
5061 case ISD::SELECT: return LowerSELECT(Op, DAG);
5062 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
5063 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
5064 case ISD::CALL: return LowerCALL(Op, DAG);
5065 case ISD::RET: return LowerRET(Op, DAG);
5066 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
5067 case ISD::MEMSET: return LowerMEMSET(Op, DAG);
5068 case ISD::MEMCPY: return LowerMEMCPY(Op, DAG);
5069 case ISD::VASTART: return LowerVASTART(Op, DAG);
5070 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
5071 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
5072 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
5073 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
5074 case ISD::FRAME_TO_ARGS_OFFSET:
5075 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
5076 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
5077 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
5078 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
5079 case ISD::FLT_ROUNDS: return LowerFLT_ROUNDS(Op, DAG);
5080 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
5081 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
5083 // FIXME: REMOVE THIS WHEN LegalizeDAGTypes lands.
5084 case ISD::READCYCLECOUNTER:
5085 return SDOperand(ExpandREADCYCLECOUNTER(Op.Val, DAG), 0);
5089 /// ExpandOperation - Provide custom lowering hooks for expanding operations.
5090 SDNode *X86TargetLowering::ExpandOperationResult(SDNode *N, SelectionDAG &DAG) {
5091 switch (N->getOpcode()) {
5092 default: assert(0 && "Should not custom lower this!");
5093 case ISD::FP_TO_SINT: return ExpandFP_TO_SINT(N, DAG);
5094 case ISD::READCYCLECOUNTER: return ExpandREADCYCLECOUNTER(N, DAG);
5098 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
5100 default: return NULL;
5101 case X86ISD::BSF: return "X86ISD::BSF";
5102 case X86ISD::BSR: return "X86ISD::BSR";
5103 case X86ISD::SHLD: return "X86ISD::SHLD";
5104 case X86ISD::SHRD: return "X86ISD::SHRD";
5105 case X86ISD::FAND: return "X86ISD::FAND";
5106 case X86ISD::FOR: return "X86ISD::FOR";
5107 case X86ISD::FXOR: return "X86ISD::FXOR";
5108 case X86ISD::FSRL: return "X86ISD::FSRL";
5109 case X86ISD::FILD: return "X86ISD::FILD";
5110 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
5111 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
5112 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
5113 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
5114 case X86ISD::FLD: return "X86ISD::FLD";
5115 case X86ISD::FST: return "X86ISD::FST";
5116 case X86ISD::FP_GET_RESULT: return "X86ISD::FP_GET_RESULT";
5117 case X86ISD::FP_SET_RESULT: return "X86ISD::FP_SET_RESULT";
5118 case X86ISD::CALL: return "X86ISD::CALL";
5119 case X86ISD::TAILCALL: return "X86ISD::TAILCALL";
5120 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
5121 case X86ISD::CMP: return "X86ISD::CMP";
5122 case X86ISD::COMI: return "X86ISD::COMI";
5123 case X86ISD::UCOMI: return "X86ISD::UCOMI";
5124 case X86ISD::SETCC: return "X86ISD::SETCC";
5125 case X86ISD::CMOV: return "X86ISD::CMOV";
5126 case X86ISD::BRCOND: return "X86ISD::BRCOND";
5127 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
5128 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
5129 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
5130 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
5131 case X86ISD::Wrapper: return "X86ISD::Wrapper";
5132 case X86ISD::S2VEC: return "X86ISD::S2VEC";
5133 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
5134 case X86ISD::PINSRW: return "X86ISD::PINSRW";
5135 case X86ISD::FMAX: return "X86ISD::FMAX";
5136 case X86ISD::FMIN: return "X86ISD::FMIN";
5137 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
5138 case X86ISD::FRCP: return "X86ISD::FRCP";
5139 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
5140 case X86ISD::THREAD_POINTER: return "X86ISD::THREAD_POINTER";
5141 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
5142 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
5143 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
5147 // isLegalAddressingMode - Return true if the addressing mode represented
5148 // by AM is legal for this target, for a load/store of the specified type.
5149 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
5150 const Type *Ty) const {
5151 // X86 supports extremely general addressing modes.
5153 // X86 allows a sign-extended 32-bit immediate field as a displacement.
5154 if (AM.BaseOffs <= -(1LL << 32) || AM.BaseOffs >= (1LL << 32)-1)
5158 // We can only fold this if we don't need an extra load.
5159 if (Subtarget->GVRequiresExtraLoad(AM.BaseGV, getTargetMachine(), false))
5162 // X86-64 only supports addr of globals in small code model.
5163 if (Subtarget->is64Bit()) {
5164 if (getTargetMachine().getCodeModel() != CodeModel::Small)
5166 // If lower 4G is not available, then we must use rip-relative addressing.
5167 if (AM.BaseOffs || AM.Scale > 1)
5178 // These scales always work.
5183 // These scales are formed with basereg+scalereg. Only accept if there is
5188 default: // Other stuff never works.
5196 bool X86TargetLowering::isTruncateFree(const Type *Ty1, const Type *Ty2) const {
5197 if (!Ty1->isInteger() || !Ty2->isInteger())
5199 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
5200 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
5201 if (NumBits1 <= NumBits2)
5203 return Subtarget->is64Bit() || NumBits1 < 64;
5206 bool X86TargetLowering::isTruncateFree(MVT::ValueType VT1,
5207 MVT::ValueType VT2) const {
5208 if (!MVT::isInteger(VT1) || !MVT::isInteger(VT2))
5210 unsigned NumBits1 = MVT::getSizeInBits(VT1);
5211 unsigned NumBits2 = MVT::getSizeInBits(VT2);
5212 if (NumBits1 <= NumBits2)
5214 return Subtarget->is64Bit() || NumBits1 < 64;
5217 /// isShuffleMaskLegal - Targets can use this to indicate that they only
5218 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
5219 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
5220 /// are assumed to be legal.
5222 X86TargetLowering::isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const {
5223 // Only do shuffles on 128-bit vector types for now.
5224 if (MVT::getSizeInBits(VT) == 64) return false;
5225 return (Mask.Val->getNumOperands() <= 4 ||
5226 isIdentityMask(Mask.Val) ||
5227 isIdentityMask(Mask.Val, true) ||
5228 isSplatMask(Mask.Val) ||
5229 isPSHUFHW_PSHUFLWMask(Mask.Val) ||
5230 X86::isUNPCKLMask(Mask.Val) ||
5231 X86::isUNPCKHMask(Mask.Val) ||
5232 X86::isUNPCKL_v_undef_Mask(Mask.Val) ||
5233 X86::isUNPCKH_v_undef_Mask(Mask.Val));
5236 bool X86TargetLowering::isVectorClearMaskLegal(std::vector<SDOperand> &BVOps,
5238 SelectionDAG &DAG) const {
5239 unsigned NumElts = BVOps.size();
5240 // Only do shuffles on 128-bit vector types for now.
5241 if (MVT::getSizeInBits(EVT) * NumElts == 64) return false;
5242 if (NumElts == 2) return true;
5244 return (isMOVLMask(&BVOps[0], 4) ||
5245 isCommutedMOVL(&BVOps[0], 4, true) ||
5246 isSHUFPMask(&BVOps[0], 4) ||
5247 isCommutedSHUFP(&BVOps[0], 4));
5252 //===----------------------------------------------------------------------===//
5253 // X86 Scheduler Hooks
5254 //===----------------------------------------------------------------------===//
5257 X86TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
5258 MachineBasicBlock *BB) {
5259 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5260 switch (MI->getOpcode()) {
5261 default: assert(false && "Unexpected instr type to insert");
5262 case X86::CMOV_FR32:
5263 case X86::CMOV_FR64:
5264 case X86::CMOV_V4F32:
5265 case X86::CMOV_V2F64:
5266 case X86::CMOV_V2I64: {
5267 // To "insert" a SELECT_CC instruction, we actually have to insert the
5268 // diamond control-flow pattern. The incoming instruction knows the
5269 // destination vreg to set, the condition code register to branch on, the
5270 // true/false values to select between, and a branch opcode to use.
5271 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5272 ilist<MachineBasicBlock>::iterator It = BB;
5278 // cmpTY ccX, r1, r2
5280 // fallthrough --> copy0MBB
5281 MachineBasicBlock *thisMBB = BB;
5282 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
5283 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
5285 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
5286 BuildMI(BB, TII->get(Opc)).addMBB(sinkMBB);
5287 MachineFunction *F = BB->getParent();
5288 F->getBasicBlockList().insert(It, copy0MBB);
5289 F->getBasicBlockList().insert(It, sinkMBB);
5290 // Update machine-CFG edges by first adding all successors of the current
5291 // block to the new block which will contain the Phi node for the select.
5292 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
5293 e = BB->succ_end(); i != e; ++i)
5294 sinkMBB->addSuccessor(*i);
5295 // Next, remove all successors of the current block, and add the true
5296 // and fallthrough blocks as its successors.
5297 while(!BB->succ_empty())
5298 BB->removeSuccessor(BB->succ_begin());
5299 BB->addSuccessor(copy0MBB);
5300 BB->addSuccessor(sinkMBB);
5303 // %FalseValue = ...
5304 // # fallthrough to sinkMBB
5307 // Update machine-CFG edges
5308 BB->addSuccessor(sinkMBB);
5311 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
5314 BuildMI(BB, TII->get(X86::PHI), MI->getOperand(0).getReg())
5315 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
5316 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
5318 delete MI; // The pseudo instruction is gone now.
5322 case X86::FP32_TO_INT16_IN_MEM:
5323 case X86::FP32_TO_INT32_IN_MEM:
5324 case X86::FP32_TO_INT64_IN_MEM:
5325 case X86::FP64_TO_INT16_IN_MEM:
5326 case X86::FP64_TO_INT32_IN_MEM:
5327 case X86::FP64_TO_INT64_IN_MEM:
5328 case X86::FP80_TO_INT16_IN_MEM:
5329 case X86::FP80_TO_INT32_IN_MEM:
5330 case X86::FP80_TO_INT64_IN_MEM: {
5331 // Change the floating point control register to use "round towards zero"
5332 // mode when truncating to an integer value.
5333 MachineFunction *F = BB->getParent();
5334 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2);
5335 addFrameReference(BuildMI(BB, TII->get(X86::FNSTCW16m)), CWFrameIdx);
5337 // Load the old value of the high byte of the control word...
5339 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
5340 addFrameReference(BuildMI(BB, TII->get(X86::MOV16rm), OldCW), CWFrameIdx);
5342 // Set the high part to be round to zero...
5343 addFrameReference(BuildMI(BB, TII->get(X86::MOV16mi)), CWFrameIdx)
5346 // Reload the modified control word now...
5347 addFrameReference(BuildMI(BB, TII->get(X86::FLDCW16m)), CWFrameIdx);
5349 // Restore the memory image of control word to original value
5350 addFrameReference(BuildMI(BB, TII->get(X86::MOV16mr)), CWFrameIdx)
5353 // Get the X86 opcode to use.
5355 switch (MI->getOpcode()) {
5356 default: assert(0 && "illegal opcode!");
5357 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
5358 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
5359 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
5360 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
5361 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
5362 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
5363 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
5364 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
5365 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
5369 MachineOperand &Op = MI->getOperand(0);
5370 if (Op.isRegister()) {
5371 AM.BaseType = X86AddressMode::RegBase;
5372 AM.Base.Reg = Op.getReg();
5374 AM.BaseType = X86AddressMode::FrameIndexBase;
5375 AM.Base.FrameIndex = Op.getIndex();
5377 Op = MI->getOperand(1);
5378 if (Op.isImmediate())
5379 AM.Scale = Op.getImm();
5380 Op = MI->getOperand(2);
5381 if (Op.isImmediate())
5382 AM.IndexReg = Op.getImm();
5383 Op = MI->getOperand(3);
5384 if (Op.isGlobalAddress()) {
5385 AM.GV = Op.getGlobal();
5387 AM.Disp = Op.getImm();
5389 addFullAddress(BuildMI(BB, TII->get(Opc)), AM)
5390 .addReg(MI->getOperand(4).getReg());
5392 // Reload the original control word now.
5393 addFrameReference(BuildMI(BB, TII->get(X86::FLDCW16m)), CWFrameIdx);
5395 delete MI; // The pseudo instruction is gone now.
5401 //===----------------------------------------------------------------------===//
5402 // X86 Optimization Hooks
5403 //===----------------------------------------------------------------------===//
5405 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
5407 uint64_t &KnownZero,
5409 const SelectionDAG &DAG,
5410 unsigned Depth) const {
5411 unsigned Opc = Op.getOpcode();
5412 assert((Opc >= ISD::BUILTIN_OP_END ||
5413 Opc == ISD::INTRINSIC_WO_CHAIN ||
5414 Opc == ISD::INTRINSIC_W_CHAIN ||
5415 Opc == ISD::INTRINSIC_VOID) &&
5416 "Should use MaskedValueIsZero if you don't know whether Op"
5417 " is a target node!");
5419 KnownZero = KnownOne = 0; // Don't know anything.
5423 KnownZero |= (MVT::getIntVTBitMask(Op.getValueType()) ^ 1ULL);
5428 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
5429 /// element of the result of the vector shuffle.
5430 static SDOperand getShuffleScalarElt(SDNode *N, unsigned i, SelectionDAG &DAG) {
5431 MVT::ValueType VT = N->getValueType(0);
5432 SDOperand PermMask = N->getOperand(2);
5433 unsigned NumElems = PermMask.getNumOperands();
5434 SDOperand V = (i < NumElems) ? N->getOperand(0) : N->getOperand(1);
5436 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR) {
5438 ? V.getOperand(0) : DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(VT));
5439 } else if (V.getOpcode() == ISD::VECTOR_SHUFFLE) {
5440 SDOperand Idx = PermMask.getOperand(i);
5441 if (Idx.getOpcode() == ISD::UNDEF)
5442 return DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(VT));
5443 return getShuffleScalarElt(V.Val,cast<ConstantSDNode>(Idx)->getValue(),DAG);
5448 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
5449 /// node is a GlobalAddress + an offset.
5450 static bool isGAPlusOffset(SDNode *N, GlobalValue* &GA, int64_t &Offset) {
5451 unsigned Opc = N->getOpcode();
5452 if (Opc == X86ISD::Wrapper) {
5453 if (dyn_cast<GlobalAddressSDNode>(N->getOperand(0))) {
5454 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
5457 } else if (Opc == ISD::ADD) {
5458 SDOperand N1 = N->getOperand(0);
5459 SDOperand N2 = N->getOperand(1);
5460 if (isGAPlusOffset(N1.Val, GA, Offset)) {
5461 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2);
5463 Offset += V->getSignExtended();
5466 } else if (isGAPlusOffset(N2.Val, GA, Offset)) {
5467 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1);
5469 Offset += V->getSignExtended();
5477 /// isConsecutiveLoad - Returns true if N is loading from an address of Base
5479 static bool isConsecutiveLoad(SDNode *N, SDNode *Base, int Dist, int Size,
5480 MachineFrameInfo *MFI) {
5481 if (N->getOperand(0).Val != Base->getOperand(0).Val)
5484 SDOperand Loc = N->getOperand(1);
5485 SDOperand BaseLoc = Base->getOperand(1);
5486 if (Loc.getOpcode() == ISD::FrameIndex) {
5487 if (BaseLoc.getOpcode() != ISD::FrameIndex)
5489 int FI = cast<FrameIndexSDNode>(Loc)->getIndex();
5490 int BFI = cast<FrameIndexSDNode>(BaseLoc)->getIndex();
5491 int FS = MFI->getObjectSize(FI);
5492 int BFS = MFI->getObjectSize(BFI);
5493 if (FS != BFS || FS != Size) return false;
5494 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Size);
5496 GlobalValue *GV1 = NULL;
5497 GlobalValue *GV2 = NULL;
5498 int64_t Offset1 = 0;
5499 int64_t Offset2 = 0;
5500 bool isGA1 = isGAPlusOffset(Loc.Val, GV1, Offset1);
5501 bool isGA2 = isGAPlusOffset(BaseLoc.Val, GV2, Offset2);
5502 if (isGA1 && isGA2 && GV1 == GV2)
5503 return Offset1 == (Offset2 + Dist*Size);
5509 static bool isBaseAlignment16(SDNode *Base, MachineFrameInfo *MFI,
5510 const X86Subtarget *Subtarget) {
5513 if (isGAPlusOffset(Base, GV, Offset))
5514 return (GV->getAlignment() >= 16 && (Offset % 16) == 0);
5515 // DAG combine handles the stack object case.
5520 /// PerformShuffleCombine - Combine a vector_shuffle that is equal to
5521 /// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load
5522 /// if the load addresses are consecutive, non-overlapping, and in the right
5524 static SDOperand PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
5525 const X86Subtarget *Subtarget) {
5526 MachineFunction &MF = DAG.getMachineFunction();
5527 MachineFrameInfo *MFI = MF.getFrameInfo();
5528 MVT::ValueType VT = N->getValueType(0);
5529 MVT::ValueType EVT = MVT::getVectorElementType(VT);
5530 SDOperand PermMask = N->getOperand(2);
5531 int NumElems = (int)PermMask.getNumOperands();
5532 SDNode *Base = NULL;
5533 for (int i = 0; i < NumElems; ++i) {
5534 SDOperand Idx = PermMask.getOperand(i);
5535 if (Idx.getOpcode() == ISD::UNDEF) {
5536 if (!Base) return SDOperand();
5539 getShuffleScalarElt(N, cast<ConstantSDNode>(Idx)->getValue(), DAG);
5540 if (!Arg.Val || !ISD::isNON_EXTLoad(Arg.Val))
5544 else if (!isConsecutiveLoad(Arg.Val, Base,
5545 i, MVT::getSizeInBits(EVT)/8,MFI))
5550 bool isAlign16 = isBaseAlignment16(Base->getOperand(1).Val, MFI, Subtarget);
5551 LoadSDNode *LD = cast<LoadSDNode>(Base);
5553 return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), LD->getSrcValue(),
5554 LD->getSrcValueOffset(), LD->isVolatile());
5556 return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), LD->getSrcValue(),
5557 LD->getSrcValueOffset(), LD->isVolatile(),
5558 LD->getAlignment());
5562 /// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
5563 static SDOperand PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
5564 const X86Subtarget *Subtarget) {
5565 SDOperand Cond = N->getOperand(0);
5567 // If we have SSE[12] support, try to form min/max nodes.
5568 if (Subtarget->hasSSE2() &&
5569 (N->getValueType(0) == MVT::f32 || N->getValueType(0) == MVT::f64)) {
5570 if (Cond.getOpcode() == ISD::SETCC) {
5571 // Get the LHS/RHS of the select.
5572 SDOperand LHS = N->getOperand(1);
5573 SDOperand RHS = N->getOperand(2);
5574 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
5576 unsigned Opcode = 0;
5577 if (LHS == Cond.getOperand(0) && RHS == Cond.getOperand(1)) {
5580 case ISD::SETOLE: // (X <= Y) ? X : Y -> min
5583 if (!UnsafeFPMath) break;
5585 case ISD::SETOLT: // (X olt/lt Y) ? X : Y -> min
5587 Opcode = X86ISD::FMIN;
5590 case ISD::SETOGT: // (X > Y) ? X : Y -> max
5593 if (!UnsafeFPMath) break;
5595 case ISD::SETUGE: // (X uge/ge Y) ? X : Y -> max
5597 Opcode = X86ISD::FMAX;
5600 } else if (LHS == Cond.getOperand(1) && RHS == Cond.getOperand(0)) {
5603 case ISD::SETOGT: // (X > Y) ? Y : X -> min
5606 if (!UnsafeFPMath) break;
5608 case ISD::SETUGE: // (X uge/ge Y) ? Y : X -> min
5610 Opcode = X86ISD::FMIN;
5613 case ISD::SETOLE: // (X <= Y) ? Y : X -> max
5616 if (!UnsafeFPMath) break;
5618 case ISD::SETOLT: // (X olt/lt Y) ? Y : X -> max
5620 Opcode = X86ISD::FMAX;
5626 return DAG.getNode(Opcode, N->getValueType(0), LHS, RHS);
5634 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
5635 /// X86ISD::FXOR nodes.
5636 static SDOperand PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
5637 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
5638 // F[X]OR(0.0, x) -> x
5639 // F[X]OR(x, 0.0) -> x
5640 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
5641 if (C->getValueAPF().isPosZero())
5642 return N->getOperand(1);
5643 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
5644 if (C->getValueAPF().isPosZero())
5645 return N->getOperand(0);
5649 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
5650 static SDOperand PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
5651 // FAND(0.0, x) -> 0.0
5652 // FAND(x, 0.0) -> 0.0
5653 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
5654 if (C->getValueAPF().isPosZero())
5655 return N->getOperand(0);
5656 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
5657 if (C->getValueAPF().isPosZero())
5658 return N->getOperand(1);
5663 SDOperand X86TargetLowering::PerformDAGCombine(SDNode *N,
5664 DAGCombinerInfo &DCI) const {
5665 SelectionDAG &DAG = DCI.DAG;
5666 switch (N->getOpcode()) {
5668 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, Subtarget);
5669 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget);
5671 case X86ISD::FOR: return PerformFORCombine(N, DAG);
5672 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
5678 //===----------------------------------------------------------------------===//
5679 // X86 Inline Assembly Support
5680 //===----------------------------------------------------------------------===//
5682 /// getConstraintType - Given a constraint letter, return the type of
5683 /// constraint it is for this target.
5684 X86TargetLowering::ConstraintType
5685 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
5686 if (Constraint.size() == 1) {
5687 switch (Constraint[0]) {
5696 return C_RegisterClass;
5701 return TargetLowering::getConstraintType(Constraint);
5704 /// LowerXConstraint - try to replace an X constraint, which matches anything,
5705 /// with another that has more specific requirements based on the type of the
5706 /// corresponding operand.
5707 void X86TargetLowering::lowerXConstraint(MVT::ValueType ConstraintVT,
5708 std::string& s) const {
5709 if (MVT::isFloatingPoint(ConstraintVT)) {
5710 if (Subtarget->hasSSE2())
5712 else if (Subtarget->hasSSE1())
5717 return TargetLowering::lowerXConstraint(ConstraintVT, s);
5720 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
5721 /// vector. If it is invalid, don't add anything to Ops.
5722 void X86TargetLowering::LowerAsmOperandForConstraint(SDOperand Op,
5724 std::vector<SDOperand>&Ops,
5725 SelectionDAG &DAG) {
5726 SDOperand Result(0, 0);
5728 switch (Constraint) {
5731 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
5732 if (C->getValue() <= 31) {
5733 Result = DAG.getTargetConstant(C->getValue(), Op.getValueType());
5739 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
5740 if (C->getValue() <= 255) {
5741 Result = DAG.getTargetConstant(C->getValue(), Op.getValueType());
5747 // Literal immediates are always ok.
5748 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
5749 Result = DAG.getTargetConstant(CST->getValue(), Op.getValueType());
5753 // If we are in non-pic codegen mode, we allow the address of a global (with
5754 // an optional displacement) to be used with 'i'.
5755 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
5758 // Match either (GA) or (GA+C)
5760 Offset = GA->getOffset();
5761 } else if (Op.getOpcode() == ISD::ADD) {
5762 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
5763 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
5765 Offset = GA->getOffset()+C->getValue();
5767 C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
5768 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
5770 Offset = GA->getOffset()+C->getValue();
5777 // If addressing this global requires a load (e.g. in PIC mode), we can't
5779 if (Subtarget->GVRequiresExtraLoad(GA->getGlobal(), getTargetMachine(),
5783 Op = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0),
5789 // Otherwise, not valid for this mode.
5795 Ops.push_back(Result);
5798 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
5801 std::vector<unsigned> X86TargetLowering::
5802 getRegClassForInlineAsmConstraint(const std::string &Constraint,
5803 MVT::ValueType VT) const {
5804 if (Constraint.size() == 1) {
5805 // FIXME: not handling fp-stack yet!
5806 switch (Constraint[0]) { // GCC X86 Constraint Letters
5807 default: break; // Unknown constraint letter
5808 case 'A': // EAX/EDX
5809 if (VT == MVT::i32 || VT == MVT::i64)
5810 return make_vector<unsigned>(X86::EAX, X86::EDX, 0);
5812 case 'q': // Q_REGS (GENERAL_REGS in 64-bit mode)
5815 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0);
5816 else if (VT == MVT::i16)
5817 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0);
5818 else if (VT == MVT::i8)
5819 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0);
5820 else if (VT == MVT::i64)
5821 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 0);
5826 return std::vector<unsigned>();
5829 std::pair<unsigned, const TargetRegisterClass*>
5830 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
5831 MVT::ValueType VT) const {
5832 // First, see if this is a constraint that directly corresponds to an LLVM
5834 if (Constraint.size() == 1) {
5835 // GCC Constraint Letters
5836 switch (Constraint[0]) {
5838 case 'r': // GENERAL_REGS
5839 case 'R': // LEGACY_REGS
5840 case 'l': // INDEX_REGS
5841 if (VT == MVT::i64 && Subtarget->is64Bit())
5842 return std::make_pair(0U, X86::GR64RegisterClass);
5844 return std::make_pair(0U, X86::GR32RegisterClass);
5845 else if (VT == MVT::i16)
5846 return std::make_pair(0U, X86::GR16RegisterClass);
5847 else if (VT == MVT::i8)
5848 return std::make_pair(0U, X86::GR8RegisterClass);
5850 case 'y': // MMX_REGS if MMX allowed.
5851 if (!Subtarget->hasMMX()) break;
5852 return std::make_pair(0U, X86::VR64RegisterClass);
5854 case 'Y': // SSE_REGS if SSE2 allowed
5855 if (!Subtarget->hasSSE2()) break;
5857 case 'x': // SSE_REGS if SSE1 allowed
5858 if (!Subtarget->hasSSE1()) break;
5862 // Scalar SSE types.
5865 return std::make_pair(0U, X86::FR32RegisterClass);
5868 return std::make_pair(0U, X86::FR64RegisterClass);
5876 return std::make_pair(0U, X86::VR128RegisterClass);
5882 // Use the default implementation in TargetLowering to convert the register
5883 // constraint into a member of a register class.
5884 std::pair<unsigned, const TargetRegisterClass*> Res;
5885 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
5887 // Not found as a standard register?
5888 if (Res.second == 0) {
5889 // GCC calls "st(0)" just plain "st".
5890 if (StringsEqualNoCase("{st}", Constraint)) {
5891 Res.first = X86::ST0;
5892 Res.second = X86::RFP80RegisterClass;
5898 // Otherwise, check to see if this is a register class of the wrong value
5899 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
5900 // turn into {ax},{dx}.
5901 if (Res.second->hasType(VT))
5902 return Res; // Correct type already, nothing to do.
5904 // All of the single-register GCC register classes map their values onto
5905 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
5906 // really want an 8-bit or 32-bit register, map to the appropriate register
5907 // class and return the appropriate register.
5908 if (Res.second != X86::GR16RegisterClass)
5911 if (VT == MVT::i8) {
5912 unsigned DestReg = 0;
5913 switch (Res.first) {
5915 case X86::AX: DestReg = X86::AL; break;
5916 case X86::DX: DestReg = X86::DL; break;
5917 case X86::CX: DestReg = X86::CL; break;
5918 case X86::BX: DestReg = X86::BL; break;
5921 Res.first = DestReg;
5922 Res.second = Res.second = X86::GR8RegisterClass;
5924 } else if (VT == MVT::i32) {
5925 unsigned DestReg = 0;
5926 switch (Res.first) {
5928 case X86::AX: DestReg = X86::EAX; break;
5929 case X86::DX: DestReg = X86::EDX; break;
5930 case X86::CX: DestReg = X86::ECX; break;
5931 case X86::BX: DestReg = X86::EBX; break;
5932 case X86::SI: DestReg = X86::ESI; break;
5933 case X86::DI: DestReg = X86::EDI; break;
5934 case X86::BP: DestReg = X86::EBP; break;
5935 case X86::SP: DestReg = X86::ESP; break;
5938 Res.first = DestReg;
5939 Res.second = Res.second = X86::GR32RegisterClass;
5941 } else if (VT == MVT::i64) {
5942 unsigned DestReg = 0;
5943 switch (Res.first) {
5945 case X86::AX: DestReg = X86::RAX; break;
5946 case X86::DX: DestReg = X86::RDX; break;
5947 case X86::CX: DestReg = X86::RCX; break;
5948 case X86::BX: DestReg = X86::RBX; break;
5949 case X86::SI: DestReg = X86::RSI; break;
5950 case X86::DI: DestReg = X86::RDI; break;
5951 case X86::BP: DestReg = X86::RBP; break;
5952 case X86::SP: DestReg = X86::RSP; break;
5955 Res.first = DestReg;
5956 Res.second = Res.second = X86::GR64RegisterClass;