1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86FrameLowering.h"
19 #include "X86InstrBuilder.h"
20 #include "X86MachineFunctionInfo.h"
21 #include "X86TargetMachine.h"
22 #include "X86TargetObjectFile.h"
23 #include "llvm/ADT/SmallBitVector.h"
24 #include "llvm/ADT/SmallSet.h"
25 #include "llvm/ADT/Statistic.h"
26 #include "llvm/ADT/StringExtras.h"
27 #include "llvm/ADT/StringSwitch.h"
28 #include "llvm/Analysis/EHPersonalities.h"
29 #include "llvm/CodeGen/IntrinsicLowering.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/CodeGen/MachineModuleInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/WinEHFuncInfo.h"
37 #include "llvm/IR/CallSite.h"
38 #include "llvm/IR/CallingConv.h"
39 #include "llvm/IR/Constants.h"
40 #include "llvm/IR/DerivedTypes.h"
41 #include "llvm/IR/Function.h"
42 #include "llvm/IR/GlobalAlias.h"
43 #include "llvm/IR/GlobalVariable.h"
44 #include "llvm/IR/Instructions.h"
45 #include "llvm/IR/Intrinsics.h"
46 #include "llvm/MC/MCAsmInfo.h"
47 #include "llvm/MC/MCContext.h"
48 #include "llvm/MC/MCExpr.h"
49 #include "llvm/MC/MCSymbol.h"
50 #include "llvm/Support/CommandLine.h"
51 #include "llvm/Support/Debug.h"
52 #include "llvm/Support/ErrorHandling.h"
53 #include "llvm/Support/MathExtras.h"
54 #include "llvm/Target/TargetOptions.h"
55 #include "X86IntrinsicsInfo.h"
61 #define DEBUG_TYPE "x86-isel"
63 STATISTIC(NumTailCalls, "Number of tail calls");
65 static cl::opt<bool> ExperimentalVectorWideningLegalization(
66 "x86-experimental-vector-widening-legalization", cl::init(false),
67 cl::desc("Enable an experimental vector type legalization through widening "
68 "rather than promotion."),
71 X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
72 const X86Subtarget &STI)
73 : TargetLowering(TM), Subtarget(&STI) {
74 X86ScalarSSEf64 = Subtarget->hasSSE2();
75 X86ScalarSSEf32 = Subtarget->hasSSE1();
76 MVT PtrVT = MVT::getIntegerVT(8 * TM.getPointerSize());
78 // Set up the TargetLowering object.
80 // X86 is weird. It always uses i8 for shift amounts and setcc results.
81 setBooleanContents(ZeroOrOneBooleanContent);
82 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
83 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
85 // For 64-bit, since we have so many registers, use the ILP scheduler.
86 // For 32-bit, use the register pressure specific scheduling.
87 // For Atom, always use ILP scheduling.
88 if (Subtarget->isAtom())
89 setSchedulingPreference(Sched::ILP);
90 else if (Subtarget->is64Bit())
91 setSchedulingPreference(Sched::ILP);
93 setSchedulingPreference(Sched::RegPressure);
94 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
95 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
97 // Bypass expensive divides on Atom when compiling with O2.
98 if (TM.getOptLevel() >= CodeGenOpt::Default) {
99 if (Subtarget->hasSlowDivide32())
100 addBypassSlowDiv(32, 8);
101 if (Subtarget->hasSlowDivide64() && Subtarget->is64Bit())
102 addBypassSlowDiv(64, 16);
105 if (Subtarget->isTargetKnownWindowsMSVC()) {
106 // Setup Windows compiler runtime calls.
107 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
108 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
109 setLibcallName(RTLIB::SREM_I64, "_allrem");
110 setLibcallName(RTLIB::UREM_I64, "_aullrem");
111 setLibcallName(RTLIB::MUL_I64, "_allmul");
112 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
113 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
114 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
115 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
116 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
119 if (Subtarget->isTargetDarwin()) {
120 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
121 setUseUnderscoreSetJmp(false);
122 setUseUnderscoreLongJmp(false);
123 } else if (Subtarget->isTargetWindowsGNU()) {
124 // MS runtime is weird: it exports _setjmp, but longjmp!
125 setUseUnderscoreSetJmp(true);
126 setUseUnderscoreLongJmp(false);
128 setUseUnderscoreSetJmp(true);
129 setUseUnderscoreLongJmp(true);
132 // Set up the register classes.
133 addRegisterClass(MVT::i8, &X86::GR8RegClass);
134 addRegisterClass(MVT::i16, &X86::GR16RegClass);
135 addRegisterClass(MVT::i32, &X86::GR32RegClass);
136 if (Subtarget->is64Bit())
137 addRegisterClass(MVT::i64, &X86::GR64RegClass);
139 for (MVT VT : MVT::integer_valuetypes())
140 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
142 // We don't accept any truncstore of integer registers.
143 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
144 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
145 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
146 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
147 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
148 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
150 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
152 // SETOEQ and SETUNE require checking two conditions.
153 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
154 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
155 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
156 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
157 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
158 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
160 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
162 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
163 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
164 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
166 if (Subtarget->is64Bit()) {
167 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512())
168 // f32/f64 are legal, f80 is custom.
169 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
171 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
172 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
173 } else if (!Subtarget->useSoftFloat()) {
174 // We have an algorithm for SSE2->double, and we turn this into a
175 // 64-bit FILD followed by conditional FADD for other targets.
176 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
177 // We have an algorithm for SSE2, and we turn this into a 64-bit
178 // FILD or VCVTUSI2SS/SD for other targets.
179 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
182 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
184 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
185 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
187 if (!Subtarget->useSoftFloat()) {
188 // SSE has no i16 to fp conversion, only i32
189 if (X86ScalarSSEf32) {
190 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
191 // f32 and f64 cases are Legal, f80 case is not
192 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
194 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
195 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
198 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
199 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
202 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
204 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
205 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
207 if (!Subtarget->useSoftFloat()) {
208 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
209 // are Legal, f80 is custom lowered.
210 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
211 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
213 if (X86ScalarSSEf32) {
214 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
215 // f32 and f64 cases are Legal, f80 case is not
216 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
218 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
219 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
222 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
223 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Expand);
224 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Expand);
227 // Handle FP_TO_UINT by promoting the destination to a larger signed
229 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
230 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
231 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
233 if (Subtarget->is64Bit()) {
234 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512()) {
235 // FP_TO_UINT-i32/i64 is legal for f32/f64, but custom for f80.
236 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
237 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
239 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
240 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
242 } else if (!Subtarget->useSoftFloat()) {
243 // Since AVX is a superset of SSE3, only check for SSE here.
244 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
245 // Expand FP_TO_UINT into a select.
246 // FIXME: We would like to use a Custom expander here eventually to do
247 // the optimal thing for SSE vs. the default expansion in the legalizer.
248 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
250 // With AVX512 we can use vcvts[ds]2usi for f32/f64->i32, f80 is custom.
251 // With SSE3 we can use fisttpll to convert to a signed i64; without
252 // SSE, we're stuck with a fistpll.
253 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
255 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
258 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
259 if (!X86ScalarSSEf64) {
260 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
261 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
262 if (Subtarget->is64Bit()) {
263 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
264 // Without SSE, i64->f64 goes through memory.
265 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
269 // Scalar integer divide and remainder are lowered to use operations that
270 // produce two results, to match the available instructions. This exposes
271 // the two-result form to trivial CSE, which is able to combine x/y and x%y
272 // into a single instruction.
274 // Scalar integer multiply-high is also lowered to use two-result
275 // operations, to match the available instructions. However, plain multiply
276 // (low) operations are left as Legal, as there are single-result
277 // instructions for this in x86. Using the two-result multiply instructions
278 // when both high and low results are needed must be arranged by dagcombine.
279 for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
280 setOperationAction(ISD::MULHS, VT, Expand);
281 setOperationAction(ISD::MULHU, VT, Expand);
282 setOperationAction(ISD::SDIV, VT, Expand);
283 setOperationAction(ISD::UDIV, VT, Expand);
284 setOperationAction(ISD::SREM, VT, Expand);
285 setOperationAction(ISD::UREM, VT, Expand);
287 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
288 setOperationAction(ISD::ADDC, VT, Custom);
289 setOperationAction(ISD::ADDE, VT, Custom);
290 setOperationAction(ISD::SUBC, VT, Custom);
291 setOperationAction(ISD::SUBE, VT, Custom);
294 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
295 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
296 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
297 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
298 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
299 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
300 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
301 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
302 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
303 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
304 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
305 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
306 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
307 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
308 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
309 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
310 if (Subtarget->is64Bit())
311 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
312 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
313 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
314 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
315 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
317 if (Subtarget->is32Bit() && Subtarget->isTargetKnownWindowsMSVC()) {
318 // On 32 bit MSVC, `fmodf(f32)` is not defined - only `fmod(f64)`
319 // is. We should promote the value to 64-bits to solve this.
320 // This is what the CRT headers do - `fmodf` is an inline header
321 // function casting to f64 and calling `fmod`.
322 setOperationAction(ISD::FREM , MVT::f32 , Promote);
324 setOperationAction(ISD::FREM , MVT::f32 , Expand);
327 setOperationAction(ISD::FREM , MVT::f64 , Expand);
328 setOperationAction(ISD::FREM , MVT::f80 , Expand);
329 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
331 // Promote the i8 variants and force them on up to i32 which has a shorter
333 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
334 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
335 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
336 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
337 if (Subtarget->hasBMI()) {
338 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
339 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
340 if (Subtarget->is64Bit())
341 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
343 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
344 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
345 if (Subtarget->is64Bit())
346 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
349 if (Subtarget->hasLZCNT()) {
350 // When promoting the i8 variants, force them to i32 for a shorter
352 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
353 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
354 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
355 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
356 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
357 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
358 if (Subtarget->is64Bit())
359 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
361 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
362 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
363 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
364 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
365 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
366 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
367 if (Subtarget->is64Bit()) {
368 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
369 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
373 // Special handling for half-precision floating point conversions.
374 // If we don't have F16C support, then lower half float conversions
375 // into library calls.
376 if (Subtarget->useSoftFloat() || !Subtarget->hasF16C()) {
377 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
378 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
381 // There's never any support for operations beyond MVT::f32.
382 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
383 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
384 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
385 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
387 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
388 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
389 setLoadExtAction(ISD::EXTLOAD, MVT::f80, MVT::f16, Expand);
390 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
391 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
392 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
394 if (Subtarget->hasPOPCNT()) {
395 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
397 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
398 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
399 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
400 if (Subtarget->is64Bit())
401 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
404 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
406 if (!Subtarget->hasMOVBE())
407 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
409 // These should be promoted to a larger select which is supported.
410 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
411 // X86 wants to expand cmov itself.
412 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
413 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
414 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
415 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
416 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
417 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
418 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
419 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
420 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
421 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
422 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
423 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
424 setOperationAction(ISD::SETCCE , MVT::i8 , Custom);
425 setOperationAction(ISD::SETCCE , MVT::i16 , Custom);
426 setOperationAction(ISD::SETCCE , MVT::i32 , Custom);
427 if (Subtarget->is64Bit()) {
428 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
429 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
430 setOperationAction(ISD::SETCCE , MVT::i64 , Custom);
432 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
433 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
434 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
435 // support continuation, user-level threading, and etc.. As a result, no
436 // other SjLj exception interfaces are implemented and please don't build
437 // your own exception handling based on them.
438 // LLVM/Clang supports zero-cost DWARF exception handling.
439 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
440 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
443 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
444 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
445 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
446 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
447 if (Subtarget->is64Bit())
448 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
449 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
450 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
451 if (Subtarget->is64Bit()) {
452 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
453 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
454 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
455 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
456 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
458 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
459 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
460 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
461 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
462 if (Subtarget->is64Bit()) {
463 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
464 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
465 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
468 if (Subtarget->hasSSE1())
469 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
471 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
473 // Expand certain atomics
474 for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
475 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
476 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
477 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
480 if (Subtarget->hasCmpxchg16b()) {
481 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
484 // FIXME - use subtarget debug flags
485 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
486 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
487 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
490 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
491 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
493 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
494 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
496 setOperationAction(ISD::TRAP, MVT::Other, Legal);
497 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
499 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
500 setOperationAction(ISD::VASTART , MVT::Other, Custom);
501 setOperationAction(ISD::VAEND , MVT::Other, Expand);
502 if (Subtarget->is64Bit()) {
503 setOperationAction(ISD::VAARG , MVT::Other, Custom);
504 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
506 // TargetInfo::CharPtrBuiltinVaList
507 setOperationAction(ISD::VAARG , MVT::Other, Expand);
508 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
511 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
512 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
514 setOperationAction(ISD::DYNAMIC_STACKALLOC, PtrVT, Custom);
516 // GC_TRANSITION_START and GC_TRANSITION_END need custom lowering.
517 setOperationAction(ISD::GC_TRANSITION_START, MVT::Other, Custom);
518 setOperationAction(ISD::GC_TRANSITION_END, MVT::Other, Custom);
520 if (!Subtarget->useSoftFloat() && X86ScalarSSEf64) {
521 // f32 and f64 use SSE.
522 // Set up the FP register classes.
523 addRegisterClass(MVT::f32, &X86::FR32RegClass);
524 addRegisterClass(MVT::f64, &X86::FR64RegClass);
526 // Use ANDPD to simulate FABS.
527 setOperationAction(ISD::FABS , MVT::f64, Custom);
528 setOperationAction(ISD::FABS , MVT::f32, Custom);
530 // Use XORP to simulate FNEG.
531 setOperationAction(ISD::FNEG , MVT::f64, Custom);
532 setOperationAction(ISD::FNEG , MVT::f32, Custom);
534 // Use ANDPD and ORPD to simulate FCOPYSIGN.
535 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
536 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
538 // Lower this to FGETSIGNx86 plus an AND.
539 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
540 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
542 // We don't support sin/cos/fmod
543 setOperationAction(ISD::FSIN , MVT::f64, Expand);
544 setOperationAction(ISD::FCOS , MVT::f64, Expand);
545 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
546 setOperationAction(ISD::FSIN , MVT::f32, Expand);
547 setOperationAction(ISD::FCOS , MVT::f32, Expand);
548 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
550 // Expand FP immediates into loads from the stack, except for the special
552 addLegalFPImmediate(APFloat(+0.0)); // xorpd
553 addLegalFPImmediate(APFloat(+0.0f)); // xorps
554 } else if (!Subtarget->useSoftFloat() && X86ScalarSSEf32) {
555 // Use SSE for f32, x87 for f64.
556 // Set up the FP register classes.
557 addRegisterClass(MVT::f32, &X86::FR32RegClass);
558 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
560 // Use ANDPS to simulate FABS.
561 setOperationAction(ISD::FABS , MVT::f32, Custom);
563 // Use XORP to simulate FNEG.
564 setOperationAction(ISD::FNEG , MVT::f32, Custom);
566 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
568 // Use ANDPS and ORPS to simulate FCOPYSIGN.
569 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
570 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
572 // We don't support sin/cos/fmod
573 setOperationAction(ISD::FSIN , MVT::f32, Expand);
574 setOperationAction(ISD::FCOS , MVT::f32, Expand);
575 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
577 // Special cases we handle for FP constants.
578 addLegalFPImmediate(APFloat(+0.0f)); // xorps
579 addLegalFPImmediate(APFloat(+0.0)); // FLD0
580 addLegalFPImmediate(APFloat(+1.0)); // FLD1
581 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
582 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
584 if (!TM.Options.UnsafeFPMath) {
585 setOperationAction(ISD::FSIN , MVT::f64, Expand);
586 setOperationAction(ISD::FCOS , MVT::f64, Expand);
587 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
589 } else if (!Subtarget->useSoftFloat()) {
590 // f32 and f64 in x87.
591 // Set up the FP register classes.
592 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
593 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
595 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
596 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
597 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
598 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
600 if (!TM.Options.UnsafeFPMath) {
601 setOperationAction(ISD::FSIN , MVT::f64, Expand);
602 setOperationAction(ISD::FSIN , MVT::f32, Expand);
603 setOperationAction(ISD::FCOS , MVT::f64, Expand);
604 setOperationAction(ISD::FCOS , MVT::f32, Expand);
605 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
606 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
608 addLegalFPImmediate(APFloat(+0.0)); // FLD0
609 addLegalFPImmediate(APFloat(+1.0)); // FLD1
610 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
611 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
612 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
613 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
614 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
615 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
618 // We don't support FMA.
619 setOperationAction(ISD::FMA, MVT::f64, Expand);
620 setOperationAction(ISD::FMA, MVT::f32, Expand);
622 // Long double always uses X87.
623 if (!Subtarget->useSoftFloat()) {
624 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
625 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
626 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
628 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
629 addLegalFPImmediate(TmpFlt); // FLD0
631 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
634 APFloat TmpFlt2(+1.0);
635 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
637 addLegalFPImmediate(TmpFlt2); // FLD1
638 TmpFlt2.changeSign();
639 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
642 if (!TM.Options.UnsafeFPMath) {
643 setOperationAction(ISD::FSIN , MVT::f80, Expand);
644 setOperationAction(ISD::FCOS , MVT::f80, Expand);
645 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
648 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
649 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
650 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
651 setOperationAction(ISD::FRINT, MVT::f80, Expand);
652 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
653 setOperationAction(ISD::FMA, MVT::f80, Expand);
656 // Always use a library call for pow.
657 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
658 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
659 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
661 setOperationAction(ISD::FLOG, MVT::f80, Expand);
662 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
663 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
664 setOperationAction(ISD::FEXP, MVT::f80, Expand);
665 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
666 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
667 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
669 // First set operation action for all vector types to either promote
670 // (for widening) or expand (for scalarization). Then we will selectively
671 // turn on ones that can be effectively codegen'd.
672 for (MVT VT : MVT::vector_valuetypes()) {
673 setOperationAction(ISD::ADD , VT, Expand);
674 setOperationAction(ISD::SUB , VT, Expand);
675 setOperationAction(ISD::FADD, VT, Expand);
676 setOperationAction(ISD::FNEG, VT, Expand);
677 setOperationAction(ISD::FSUB, VT, Expand);
678 setOperationAction(ISD::MUL , VT, Expand);
679 setOperationAction(ISD::FMUL, VT, Expand);
680 setOperationAction(ISD::SDIV, VT, Expand);
681 setOperationAction(ISD::UDIV, VT, Expand);
682 setOperationAction(ISD::FDIV, VT, Expand);
683 setOperationAction(ISD::SREM, VT, Expand);
684 setOperationAction(ISD::UREM, VT, Expand);
685 setOperationAction(ISD::LOAD, VT, Expand);
686 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
687 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
688 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
689 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
690 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
691 setOperationAction(ISD::FABS, VT, Expand);
692 setOperationAction(ISD::FSIN, VT, Expand);
693 setOperationAction(ISD::FSINCOS, VT, Expand);
694 setOperationAction(ISD::FCOS, VT, Expand);
695 setOperationAction(ISD::FSINCOS, VT, Expand);
696 setOperationAction(ISD::FREM, VT, Expand);
697 setOperationAction(ISD::FMA, VT, Expand);
698 setOperationAction(ISD::FPOWI, VT, Expand);
699 setOperationAction(ISD::FSQRT, VT, Expand);
700 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
701 setOperationAction(ISD::FFLOOR, VT, Expand);
702 setOperationAction(ISD::FCEIL, VT, Expand);
703 setOperationAction(ISD::FTRUNC, VT, Expand);
704 setOperationAction(ISD::FRINT, VT, Expand);
705 setOperationAction(ISD::FNEARBYINT, VT, Expand);
706 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
707 setOperationAction(ISD::MULHS, VT, Expand);
708 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
709 setOperationAction(ISD::MULHU, VT, Expand);
710 setOperationAction(ISD::SDIVREM, VT, Expand);
711 setOperationAction(ISD::UDIVREM, VT, Expand);
712 setOperationAction(ISD::FPOW, VT, Expand);
713 setOperationAction(ISD::CTPOP, VT, Expand);
714 setOperationAction(ISD::CTTZ, VT, Expand);
715 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
716 setOperationAction(ISD::CTLZ, VT, Expand);
717 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
718 setOperationAction(ISD::SHL, VT, Expand);
719 setOperationAction(ISD::SRA, VT, Expand);
720 setOperationAction(ISD::SRL, VT, Expand);
721 setOperationAction(ISD::ROTL, VT, Expand);
722 setOperationAction(ISD::ROTR, VT, Expand);
723 setOperationAction(ISD::BSWAP, VT, Expand);
724 setOperationAction(ISD::SETCC, VT, Expand);
725 setOperationAction(ISD::FLOG, VT, Expand);
726 setOperationAction(ISD::FLOG2, VT, Expand);
727 setOperationAction(ISD::FLOG10, VT, Expand);
728 setOperationAction(ISD::FEXP, VT, Expand);
729 setOperationAction(ISD::FEXP2, VT, Expand);
730 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
731 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
732 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
733 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
734 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
735 setOperationAction(ISD::TRUNCATE, VT, Expand);
736 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
737 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
738 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
739 setOperationAction(ISD::VSELECT, VT, Expand);
740 setOperationAction(ISD::SELECT_CC, VT, Expand);
741 for (MVT InnerVT : MVT::vector_valuetypes()) {
742 setTruncStoreAction(InnerVT, VT, Expand);
744 setLoadExtAction(ISD::SEXTLOAD, InnerVT, VT, Expand);
745 setLoadExtAction(ISD::ZEXTLOAD, InnerVT, VT, Expand);
747 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like
748 // types, we have to deal with them whether we ask for Expansion or not.
749 // Setting Expand causes its own optimisation problems though, so leave
751 if (VT.getVectorElementType() == MVT::i1)
752 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
754 // EXTLOAD for MVT::f16 vectors is not legal because f16 vectors are
755 // split/scalarized right now.
756 if (VT.getVectorElementType() == MVT::f16)
757 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
761 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
762 // with -msoft-float, disable use of MMX as well.
763 if (!Subtarget->useSoftFloat() && Subtarget->hasMMX()) {
764 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
765 // No operations on x86mmx supported, everything uses intrinsics.
768 // MMX-sized vectors (other than x86mmx) are expected to be expanded
769 // into smaller operations.
770 for (MVT MMXTy : {MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::v1i64}) {
771 setOperationAction(ISD::MULHS, MMXTy, Expand);
772 setOperationAction(ISD::AND, MMXTy, Expand);
773 setOperationAction(ISD::OR, MMXTy, Expand);
774 setOperationAction(ISD::XOR, MMXTy, Expand);
775 setOperationAction(ISD::SCALAR_TO_VECTOR, MMXTy, Expand);
776 setOperationAction(ISD::SELECT, MMXTy, Expand);
777 setOperationAction(ISD::BITCAST, MMXTy, Expand);
779 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
781 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE1()) {
782 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
784 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
785 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
786 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
787 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
788 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
789 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
790 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
791 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
792 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
793 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
794 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
795 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
796 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
797 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
800 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE2()) {
801 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
803 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
804 // registers cannot be used even for integer operations.
805 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
806 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
807 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
808 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
810 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
811 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
812 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
813 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
814 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
815 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
816 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
817 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
818 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
819 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
820 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
821 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
822 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
823 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
824 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
825 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
826 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
827 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
828 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
829 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
830 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
831 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
832 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
834 setOperationAction(ISD::SMAX, MVT::v8i16, Legal);
835 setOperationAction(ISD::UMAX, MVT::v16i8, Legal);
836 setOperationAction(ISD::SMIN, MVT::v8i16, Legal);
837 setOperationAction(ISD::UMIN, MVT::v16i8, Legal);
839 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
840 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
841 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
842 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
844 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
845 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
846 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
847 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
848 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
850 setOperationAction(ISD::CTPOP, MVT::v16i8, Custom);
851 setOperationAction(ISD::CTPOP, MVT::v8i16, Custom);
852 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
853 setOperationAction(ISD::CTPOP, MVT::v2i64, Custom);
855 setOperationAction(ISD::CTTZ, MVT::v16i8, Custom);
856 setOperationAction(ISD::CTTZ, MVT::v8i16, Custom);
857 setOperationAction(ISD::CTTZ, MVT::v4i32, Custom);
858 // ISD::CTTZ v2i64 - scalarization is faster.
859 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i8, Custom);
860 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i16, Custom);
861 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i32, Custom);
862 // ISD::CTTZ_ZERO_UNDEF v2i64 - scalarization is faster.
864 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
865 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32 }) {
866 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
867 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
868 setOperationAction(ISD::VSELECT, VT, Custom);
869 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
872 // We support custom legalizing of sext and anyext loads for specific
873 // memory vector types which we can load as a scalar (or sequence of
874 // scalars) and extend in-register to a legal 128-bit vector type. For sext
875 // loads these must work with a single scalar load.
876 for (MVT VT : MVT::integer_vector_valuetypes()) {
877 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Custom);
878 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Custom);
879 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v8i8, Custom);
880 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Custom);
881 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Custom);
882 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i32, Custom);
883 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Custom);
884 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Custom);
885 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8i8, Custom);
888 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
889 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
890 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
891 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
892 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
893 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
894 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
895 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
897 if (Subtarget->is64Bit()) {
898 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
899 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
902 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
903 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32 }) {
904 setOperationAction(ISD::AND, VT, Promote);
905 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
906 setOperationAction(ISD::OR, VT, Promote);
907 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
908 setOperationAction(ISD::XOR, VT, Promote);
909 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
910 setOperationAction(ISD::LOAD, VT, Promote);
911 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
912 setOperationAction(ISD::SELECT, VT, Promote);
913 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
916 // Custom lower v2i64 and v2f64 selects.
917 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
918 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
919 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
920 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
922 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
923 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
925 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
927 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
928 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
929 // As there is no 64-bit GPR available, we need build a special custom
930 // sequence to convert from v2i32 to v2f32.
931 if (!Subtarget->is64Bit())
932 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
934 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
935 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
937 for (MVT VT : MVT::fp_vector_valuetypes())
938 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2f32, Legal);
940 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
941 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
942 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
945 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE41()) {
946 for (MVT RoundedTy : {MVT::f32, MVT::f64, MVT::v4f32, MVT::v2f64}) {
947 setOperationAction(ISD::FFLOOR, RoundedTy, Legal);
948 setOperationAction(ISD::FCEIL, RoundedTy, Legal);
949 setOperationAction(ISD::FTRUNC, RoundedTy, Legal);
950 setOperationAction(ISD::FRINT, RoundedTy, Legal);
951 setOperationAction(ISD::FNEARBYINT, RoundedTy, Legal);
954 setOperationAction(ISD::SMAX, MVT::v16i8, Legal);
955 setOperationAction(ISD::SMAX, MVT::v4i32, Legal);
956 setOperationAction(ISD::UMAX, MVT::v8i16, Legal);
957 setOperationAction(ISD::UMAX, MVT::v4i32, Legal);
958 setOperationAction(ISD::SMIN, MVT::v16i8, Legal);
959 setOperationAction(ISD::SMIN, MVT::v4i32, Legal);
960 setOperationAction(ISD::UMIN, MVT::v8i16, Legal);
961 setOperationAction(ISD::UMIN, MVT::v4i32, Legal);
963 // FIXME: Do we need to handle scalar-to-vector here?
964 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
966 // We directly match byte blends in the backend as they match the VSELECT
968 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
970 // SSE41 brings specific instructions for doing vector sign extend even in
971 // cases where we don't have SRA.
972 for (MVT VT : MVT::integer_vector_valuetypes()) {
973 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Custom);
974 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Custom);
975 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i32, Custom);
978 // SSE41 also has vector sign/zero extending loads, PMOV[SZ]X
979 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
980 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
981 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
982 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
983 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
984 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
986 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
987 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
988 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
989 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
990 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
991 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
993 // i8 and i16 vectors are custom because the source register and source
994 // source memory operand types are not the same width. f32 vectors are
995 // custom since the immediate controlling the insert encodes additional
997 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
998 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
999 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1000 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1002 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1003 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1004 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1005 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1007 // FIXME: these should be Legal, but that's only for the case where
1008 // the index is constant. For now custom expand to deal with that.
1009 if (Subtarget->is64Bit()) {
1010 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1011 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1015 if (Subtarget->hasSSE2()) {
1016 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v2i64, Custom);
1017 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v4i32, Custom);
1018 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v8i16, Custom);
1020 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1021 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1023 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1024 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1026 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1027 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1029 // In the customized shift lowering, the legal cases in AVX2 will be
1031 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1032 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1034 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1035 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1037 setOperationAction(ISD::SRA, MVT::v2i64, Custom);
1038 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1041 if (Subtarget->hasXOP()) {
1042 setOperationAction(ISD::ROTL, MVT::v16i8, Custom);
1043 setOperationAction(ISD::ROTL, MVT::v8i16, Custom);
1044 setOperationAction(ISD::ROTL, MVT::v4i32, Custom);
1045 setOperationAction(ISD::ROTL, MVT::v2i64, Custom);
1046 setOperationAction(ISD::ROTL, MVT::v32i8, Custom);
1047 setOperationAction(ISD::ROTL, MVT::v16i16, Custom);
1048 setOperationAction(ISD::ROTL, MVT::v8i32, Custom);
1049 setOperationAction(ISD::ROTL, MVT::v4i64, Custom);
1052 if (!Subtarget->useSoftFloat() && Subtarget->hasFp256()) {
1053 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1054 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1055 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1056 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1057 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1058 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1060 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1061 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1062 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1064 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1065 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1066 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1067 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1068 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1069 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1070 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1071 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1072 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1073 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1074 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1075 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1077 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1078 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1079 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1080 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1081 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1082 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1083 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1084 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1085 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1086 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1087 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1088 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1090 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1091 // even though v8i16 is a legal type.
1092 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1093 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1094 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1096 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1097 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1098 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1100 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1101 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1103 for (MVT VT : MVT::fp_vector_valuetypes())
1104 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4f32, Legal);
1106 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1107 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1109 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1110 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1112 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1113 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1115 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1116 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1117 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1118 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1120 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1121 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1122 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1124 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1125 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1126 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1127 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1128 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1129 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1130 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1131 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1132 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1133 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1134 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1135 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1137 setOperationAction(ISD::CTPOP, MVT::v32i8, Custom);
1138 setOperationAction(ISD::CTPOP, MVT::v16i16, Custom);
1139 setOperationAction(ISD::CTPOP, MVT::v8i32, Custom);
1140 setOperationAction(ISD::CTPOP, MVT::v4i64, Custom);
1142 setOperationAction(ISD::CTTZ, MVT::v32i8, Custom);
1143 setOperationAction(ISD::CTTZ, MVT::v16i16, Custom);
1144 setOperationAction(ISD::CTTZ, MVT::v8i32, Custom);
1145 setOperationAction(ISD::CTTZ, MVT::v4i64, Custom);
1146 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v32i8, Custom);
1147 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i16, Custom);
1148 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i32, Custom);
1149 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i64, Custom);
1151 if (Subtarget->hasAnyFMA()) {
1152 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1153 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1154 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1155 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1156 setOperationAction(ISD::FMA, MVT::f32, Legal);
1157 setOperationAction(ISD::FMA, MVT::f64, Legal);
1160 if (Subtarget->hasInt256()) {
1161 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1162 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1163 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1164 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1166 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1167 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1168 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1169 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1171 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1172 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1173 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1174 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1176 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1177 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1178 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1179 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1181 setOperationAction(ISD::SMAX, MVT::v32i8, Legal);
1182 setOperationAction(ISD::SMAX, MVT::v16i16, Legal);
1183 setOperationAction(ISD::SMAX, MVT::v8i32, Legal);
1184 setOperationAction(ISD::UMAX, MVT::v32i8, Legal);
1185 setOperationAction(ISD::UMAX, MVT::v16i16, Legal);
1186 setOperationAction(ISD::UMAX, MVT::v8i32, Legal);
1187 setOperationAction(ISD::SMIN, MVT::v32i8, Legal);
1188 setOperationAction(ISD::SMIN, MVT::v16i16, Legal);
1189 setOperationAction(ISD::SMIN, MVT::v8i32, Legal);
1190 setOperationAction(ISD::UMIN, MVT::v32i8, Legal);
1191 setOperationAction(ISD::UMIN, MVT::v16i16, Legal);
1192 setOperationAction(ISD::UMIN, MVT::v8i32, Legal);
1194 // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1195 // when we have a 256bit-wide blend with immediate.
1196 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom);
1198 // AVX2 also has wider vector sign/zero extending loads, VPMOV[SZ]X
1199 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1200 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1201 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1202 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1203 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1204 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1206 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1207 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1208 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1209 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1210 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1211 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1213 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1214 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1215 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1216 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1218 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1219 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1220 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1221 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1223 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1224 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1225 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1226 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1228 setOperationAction(ISD::SMAX, MVT::v32i8, Custom);
1229 setOperationAction(ISD::SMAX, MVT::v16i16, Custom);
1230 setOperationAction(ISD::SMAX, MVT::v8i32, Custom);
1231 setOperationAction(ISD::UMAX, MVT::v32i8, Custom);
1232 setOperationAction(ISD::UMAX, MVT::v16i16, Custom);
1233 setOperationAction(ISD::UMAX, MVT::v8i32, Custom);
1234 setOperationAction(ISD::SMIN, MVT::v32i8, Custom);
1235 setOperationAction(ISD::SMIN, MVT::v16i16, Custom);
1236 setOperationAction(ISD::SMIN, MVT::v8i32, Custom);
1237 setOperationAction(ISD::UMIN, MVT::v32i8, Custom);
1238 setOperationAction(ISD::UMIN, MVT::v16i16, Custom);
1239 setOperationAction(ISD::UMIN, MVT::v8i32, Custom);
1242 // In the customized shift lowering, the legal cases in AVX2 will be
1244 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1245 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1247 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1248 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1250 setOperationAction(ISD::SRA, MVT::v4i64, Custom);
1251 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1253 // Custom lower several nodes for 256-bit types.
1254 for (MVT VT : MVT::vector_valuetypes()) {
1255 if (VT.getScalarSizeInBits() >= 32) {
1256 setOperationAction(ISD::MLOAD, VT, Legal);
1257 setOperationAction(ISD::MSTORE, VT, Legal);
1259 // Extract subvector is special because the value type
1260 // (result) is 128-bit but the source is 256-bit wide.
1261 if (VT.is128BitVector()) {
1262 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1264 // Do not attempt to custom lower other non-256-bit vectors
1265 if (!VT.is256BitVector())
1268 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1269 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1270 setOperationAction(ISD::VSELECT, VT, Custom);
1271 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1272 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1273 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1274 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1275 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1278 if (Subtarget->hasInt256())
1279 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1281 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1282 for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32 }) {
1283 setOperationAction(ISD::AND, VT, Promote);
1284 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1285 setOperationAction(ISD::OR, VT, Promote);
1286 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1287 setOperationAction(ISD::XOR, VT, Promote);
1288 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1289 setOperationAction(ISD::LOAD, VT, Promote);
1290 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1291 setOperationAction(ISD::SELECT, VT, Promote);
1292 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1296 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512()) {
1297 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1298 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1299 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1300 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1302 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1303 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1304 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1306 for (MVT VT : MVT::fp_vector_valuetypes())
1307 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8f32, Legal);
1309 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i32, MVT::v16i8, Legal);
1310 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i32, MVT::v16i8, Legal);
1311 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i32, MVT::v16i16, Legal);
1312 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i32, MVT::v16i16, Legal);
1313 setLoadExtAction(ISD::ZEXTLOAD, MVT::v32i16, MVT::v32i8, Legal);
1314 setLoadExtAction(ISD::SEXTLOAD, MVT::v32i16, MVT::v32i8, Legal);
1315 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i8, Legal);
1316 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i8, Legal);
1317 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i16, Legal);
1318 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i16, Legal);
1319 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i32, Legal);
1320 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i32, Legal);
1322 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1323 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1324 setOperationAction(ISD::SELECT_CC, MVT::i1, Expand);
1325 setOperationAction(ISD::XOR, MVT::i1, Legal);
1326 setOperationAction(ISD::OR, MVT::i1, Legal);
1327 setOperationAction(ISD::AND, MVT::i1, Legal);
1328 setOperationAction(ISD::SUB, MVT::i1, Custom);
1329 setOperationAction(ISD::ADD, MVT::i1, Custom);
1330 setOperationAction(ISD::MUL, MVT::i1, Custom);
1331 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1332 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1333 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1334 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1335 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1337 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1338 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1339 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1340 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1341 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1342 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1343 setOperationAction(ISD::FABS, MVT::v16f32, Custom);
1345 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1346 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1347 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1348 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1349 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1350 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1351 setOperationAction(ISD::FABS, MVT::v8f64, Custom);
1352 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1353 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1355 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1356 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1357 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1358 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1359 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1360 setOperationAction(ISD::SINT_TO_FP, MVT::v8i1, Custom);
1361 setOperationAction(ISD::SINT_TO_FP, MVT::v16i1, Custom);
1362 setOperationAction(ISD::SINT_TO_FP, MVT::v16i8, Promote);
1363 setOperationAction(ISD::SINT_TO_FP, MVT::v16i16, Promote);
1364 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1365 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1366 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1367 setOperationAction(ISD::UINT_TO_FP, MVT::v16i8, Custom);
1368 setOperationAction(ISD::UINT_TO_FP, MVT::v16i16, Custom);
1369 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1370 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1372 setTruncStoreAction(MVT::v8i64, MVT::v8i8, Legal);
1373 setTruncStoreAction(MVT::v8i64, MVT::v8i16, Legal);
1374 setTruncStoreAction(MVT::v8i64, MVT::v8i32, Legal);
1375 setTruncStoreAction(MVT::v16i32, MVT::v16i8, Legal);
1376 setTruncStoreAction(MVT::v16i32, MVT::v16i16, Legal);
1377 if (Subtarget->hasVLX()){
1378 setTruncStoreAction(MVT::v4i64, MVT::v4i8, Legal);
1379 setTruncStoreAction(MVT::v4i64, MVT::v4i16, Legal);
1380 setTruncStoreAction(MVT::v4i64, MVT::v4i32, Legal);
1381 setTruncStoreAction(MVT::v8i32, MVT::v8i8, Legal);
1382 setTruncStoreAction(MVT::v8i32, MVT::v8i16, Legal);
1384 setTruncStoreAction(MVT::v2i64, MVT::v2i8, Legal);
1385 setTruncStoreAction(MVT::v2i64, MVT::v2i16, Legal);
1386 setTruncStoreAction(MVT::v2i64, MVT::v2i32, Legal);
1387 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Legal);
1388 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Legal);
1390 setOperationAction(ISD::MLOAD, MVT::v8i32, Custom);
1391 setOperationAction(ISD::MLOAD, MVT::v8f32, Custom);
1392 setOperationAction(ISD::MSTORE, MVT::v8i32, Custom);
1393 setOperationAction(ISD::MSTORE, MVT::v8f32, Custom);
1395 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1396 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1397 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1398 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i1, Custom);
1399 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i1, Custom);
1400 if (Subtarget->hasDQI()) {
1401 setOperationAction(ISD::TRUNCATE, MVT::v2i1, Custom);
1402 setOperationAction(ISD::TRUNCATE, MVT::v4i1, Custom);
1404 setOperationAction(ISD::SINT_TO_FP, MVT::v8i64, Legal);
1405 setOperationAction(ISD::UINT_TO_FP, MVT::v8i64, Legal);
1406 setOperationAction(ISD::FP_TO_SINT, MVT::v8i64, Legal);
1407 setOperationAction(ISD::FP_TO_UINT, MVT::v8i64, Legal);
1408 if (Subtarget->hasVLX()) {
1409 setOperationAction(ISD::SINT_TO_FP, MVT::v4i64, Legal);
1410 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
1411 setOperationAction(ISD::UINT_TO_FP, MVT::v4i64, Legal);
1412 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
1413 setOperationAction(ISD::FP_TO_SINT, MVT::v4i64, Legal);
1414 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
1415 setOperationAction(ISD::FP_TO_UINT, MVT::v4i64, Legal);
1416 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
1419 if (Subtarget->hasVLX()) {
1420 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1421 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1422 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1423 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1424 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1425 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1426 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1427 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1429 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1430 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1431 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1432 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1433 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1434 setOperationAction(ISD::ANY_EXTEND, MVT::v16i32, Custom);
1435 setOperationAction(ISD::ANY_EXTEND, MVT::v8i64, Custom);
1436 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1437 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1438 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1439 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1440 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1441 if (Subtarget->hasDQI()) {
1442 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i32, Custom);
1443 setOperationAction(ISD::SIGN_EXTEND, MVT::v2i64, Custom);
1445 setOperationAction(ISD::FFLOOR, MVT::v16f32, Legal);
1446 setOperationAction(ISD::FFLOOR, MVT::v8f64, Legal);
1447 setOperationAction(ISD::FCEIL, MVT::v16f32, Legal);
1448 setOperationAction(ISD::FCEIL, MVT::v8f64, Legal);
1449 setOperationAction(ISD::FTRUNC, MVT::v16f32, Legal);
1450 setOperationAction(ISD::FTRUNC, MVT::v8f64, Legal);
1451 setOperationAction(ISD::FRINT, MVT::v16f32, Legal);
1452 setOperationAction(ISD::FRINT, MVT::v8f64, Legal);
1453 setOperationAction(ISD::FNEARBYINT, MVT::v16f32, Legal);
1454 setOperationAction(ISD::FNEARBYINT, MVT::v8f64, Legal);
1456 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1457 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1458 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1459 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1460 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Custom);
1462 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1463 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1465 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1467 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1468 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1469 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v16i1, Custom);
1470 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1471 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1472 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1473 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1474 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1475 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1476 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1477 setOperationAction(ISD::SELECT, MVT::v16i1, Custom);
1478 setOperationAction(ISD::SELECT, MVT::v8i1, Custom);
1480 setOperationAction(ISD::SMAX, MVT::v16i32, Legal);
1481 setOperationAction(ISD::SMAX, MVT::v8i64, Legal);
1482 setOperationAction(ISD::UMAX, MVT::v16i32, Legal);
1483 setOperationAction(ISD::UMAX, MVT::v8i64, Legal);
1484 setOperationAction(ISD::SMIN, MVT::v16i32, Legal);
1485 setOperationAction(ISD::SMIN, MVT::v8i64, Legal);
1486 setOperationAction(ISD::UMIN, MVT::v16i32, Legal);
1487 setOperationAction(ISD::UMIN, MVT::v8i64, Legal);
1489 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1490 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1492 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1493 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1495 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1497 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1498 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1500 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1501 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1503 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1504 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1506 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1507 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1508 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1509 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1510 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1511 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1513 if (Subtarget->hasCDI()) {
1514 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1515 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1516 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i64, Legal);
1517 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v16i32, Legal);
1519 setOperationAction(ISD::CTLZ, MVT::v8i16, Custom);
1520 setOperationAction(ISD::CTLZ, MVT::v16i8, Custom);
1521 setOperationAction(ISD::CTLZ, MVT::v16i16, Custom);
1522 setOperationAction(ISD::CTLZ, MVT::v32i8, Custom);
1523 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i16, Custom);
1524 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v16i8, Custom);
1525 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v16i16, Custom);
1526 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v32i8, Custom);
1528 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i64, Custom);
1529 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i32, Custom);
1531 if (Subtarget->hasVLX()) {
1532 setOperationAction(ISD::CTLZ, MVT::v4i64, Legal);
1533 setOperationAction(ISD::CTLZ, MVT::v8i32, Legal);
1534 setOperationAction(ISD::CTLZ, MVT::v2i64, Legal);
1535 setOperationAction(ISD::CTLZ, MVT::v4i32, Legal);
1536 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i64, Legal);
1537 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i32, Legal);
1538 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v2i64, Legal);
1539 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i32, Legal);
1541 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i64, Custom);
1542 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i32, Custom);
1543 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i64, Custom);
1544 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i32, Custom);
1546 setOperationAction(ISD::CTLZ, MVT::v4i64, Custom);
1547 setOperationAction(ISD::CTLZ, MVT::v8i32, Custom);
1548 setOperationAction(ISD::CTLZ, MVT::v2i64, Custom);
1549 setOperationAction(ISD::CTLZ, MVT::v4i32, Custom);
1550 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i64, Custom);
1551 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i32, Custom);
1552 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v2i64, Custom);
1553 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i32, Custom);
1555 } // Subtarget->hasCDI()
1557 if (Subtarget->hasDQI()) {
1558 setOperationAction(ISD::MUL, MVT::v2i64, Legal);
1559 setOperationAction(ISD::MUL, MVT::v4i64, Legal);
1560 setOperationAction(ISD::MUL, MVT::v8i64, Legal);
1562 // Custom lower several nodes.
1563 for (MVT VT : MVT::vector_valuetypes()) {
1564 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1566 setOperationAction(ISD::AND, VT, Legal);
1567 setOperationAction(ISD::OR, VT, Legal);
1568 setOperationAction(ISD::XOR, VT, Legal);
1570 if (EltSize >= 32 && VT.getSizeInBits() <= 512) {
1571 setOperationAction(ISD::MGATHER, VT, Custom);
1572 setOperationAction(ISD::MSCATTER, VT, Custom);
1574 // Extract subvector is special because the value type
1575 // (result) is 256/128-bit but the source is 512-bit wide.
1576 if (VT.is128BitVector() || VT.is256BitVector()) {
1577 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1579 if (VT.getVectorElementType() == MVT::i1)
1580 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1582 // Do not attempt to custom lower other non-512-bit vectors
1583 if (!VT.is512BitVector())
1586 if (EltSize >= 32) {
1587 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1588 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1589 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1590 setOperationAction(ISD::VSELECT, VT, Legal);
1591 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1592 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1593 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1594 setOperationAction(ISD::MLOAD, VT, Legal);
1595 setOperationAction(ISD::MSTORE, VT, Legal);
1598 for (auto VT : { MVT::v64i8, MVT::v32i16, MVT::v16i32 }) {
1599 setOperationAction(ISD::SELECT, VT, Promote);
1600 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1604 if (!Subtarget->useSoftFloat() && Subtarget->hasBWI()) {
1605 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1606 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1608 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1609 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1611 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1612 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1613 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1614 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1615 setOperationAction(ISD::ADD, MVT::v32i16, Legal);
1616 setOperationAction(ISD::ADD, MVT::v64i8, Legal);
1617 setOperationAction(ISD::SUB, MVT::v32i16, Legal);
1618 setOperationAction(ISD::SUB, MVT::v64i8, Legal);
1619 setOperationAction(ISD::MUL, MVT::v32i16, Legal);
1620 setOperationAction(ISD::MULHS, MVT::v32i16, Legal);
1621 setOperationAction(ISD::MULHU, MVT::v32i16, Legal);
1622 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i1, Custom);
1623 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i1, Custom);
1624 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i16, Custom);
1625 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i8, Custom);
1626 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i1, Custom);
1627 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i1, Custom);
1628 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i16, Custom);
1629 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i8, Custom);
1630 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v32i16, Custom);
1631 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v64i8, Custom);
1632 setOperationAction(ISD::SELECT, MVT::v32i1, Custom);
1633 setOperationAction(ISD::SELECT, MVT::v64i1, Custom);
1634 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i8, Custom);
1635 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i8, Custom);
1636 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i16, Custom);
1637 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i16, Custom);
1638 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v32i16, Custom);
1639 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v64i8, Custom);
1640 setOperationAction(ISD::SIGN_EXTEND, MVT::v64i8, Custom);
1641 setOperationAction(ISD::ZERO_EXTEND, MVT::v64i8, Custom);
1642 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v32i1, Custom);
1643 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v64i1, Custom);
1644 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v32i16, Custom);
1645 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v64i8, Custom);
1646 setOperationAction(ISD::VSELECT, MVT::v32i16, Legal);
1647 setOperationAction(ISD::VSELECT, MVT::v64i8, Legal);
1648 setOperationAction(ISD::TRUNCATE, MVT::v32i1, Custom);
1649 setOperationAction(ISD::TRUNCATE, MVT::v64i1, Custom);
1650 setOperationAction(ISD::TRUNCATE, MVT::v32i8, Custom);
1651 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v32i1, Custom);
1652 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v64i1, Custom);
1654 setOperationAction(ISD::SMAX, MVT::v64i8, Legal);
1655 setOperationAction(ISD::SMAX, MVT::v32i16, Legal);
1656 setOperationAction(ISD::UMAX, MVT::v64i8, Legal);
1657 setOperationAction(ISD::UMAX, MVT::v32i16, Legal);
1658 setOperationAction(ISD::SMIN, MVT::v64i8, Legal);
1659 setOperationAction(ISD::SMIN, MVT::v32i16, Legal);
1660 setOperationAction(ISD::UMIN, MVT::v64i8, Legal);
1661 setOperationAction(ISD::UMIN, MVT::v32i16, Legal);
1663 setTruncStoreAction(MVT::v32i16, MVT::v32i8, Legal);
1664 setTruncStoreAction(MVT::v16i16, MVT::v16i8, Legal);
1665 if (Subtarget->hasVLX())
1666 setTruncStoreAction(MVT::v8i16, MVT::v8i8, Legal);
1668 if (Subtarget->hasCDI()) {
1669 setOperationAction(ISD::CTLZ, MVT::v32i16, Custom);
1670 setOperationAction(ISD::CTLZ, MVT::v64i8, Custom);
1671 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v32i16, Custom);
1672 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v64i8, Custom);
1675 for (auto VT : { MVT::v64i8, MVT::v32i16 }) {
1676 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1677 setOperationAction(ISD::VSELECT, VT, Legal);
1681 if (!Subtarget->useSoftFloat() && Subtarget->hasVLX()) {
1682 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1683 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1685 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1686 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1687 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i1, Custom);
1688 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1689 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Custom);
1690 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v4i1, Custom);
1691 setOperationAction(ISD::SELECT, MVT::v4i1, Custom);
1692 setOperationAction(ISD::SELECT, MVT::v2i1, Custom);
1693 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i1, Custom);
1694 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i1, Custom);
1695 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i1, Custom);
1696 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i1, Custom);
1698 setOperationAction(ISD::AND, MVT::v8i32, Legal);
1699 setOperationAction(ISD::OR, MVT::v8i32, Legal);
1700 setOperationAction(ISD::XOR, MVT::v8i32, Legal);
1701 setOperationAction(ISD::AND, MVT::v4i32, Legal);
1702 setOperationAction(ISD::OR, MVT::v4i32, Legal);
1703 setOperationAction(ISD::XOR, MVT::v4i32, Legal);
1704 setOperationAction(ISD::SRA, MVT::v2i64, Custom);
1705 setOperationAction(ISD::SRA, MVT::v4i64, Custom);
1707 setOperationAction(ISD::SMAX, MVT::v2i64, Legal);
1708 setOperationAction(ISD::SMAX, MVT::v4i64, Legal);
1709 setOperationAction(ISD::UMAX, MVT::v2i64, Legal);
1710 setOperationAction(ISD::UMAX, MVT::v4i64, Legal);
1711 setOperationAction(ISD::SMIN, MVT::v2i64, Legal);
1712 setOperationAction(ISD::SMIN, MVT::v4i64, Legal);
1713 setOperationAction(ISD::UMIN, MVT::v2i64, Legal);
1714 setOperationAction(ISD::UMIN, MVT::v4i64, Legal);
1717 // We want to custom lower some of our intrinsics.
1718 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1719 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1720 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1721 if (!Subtarget->is64Bit()) {
1722 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1723 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);
1726 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1727 // handle type legalization for these operations here.
1729 // FIXME: We really should do custom legalization for addition and
1730 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1731 // than generic legalization for 64-bit multiplication-with-overflow, though.
1732 for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
1733 if (VT == MVT::i64 && !Subtarget->is64Bit())
1735 // Add/Sub/Mul with overflow operations are custom lowered.
1736 setOperationAction(ISD::SADDO, VT, Custom);
1737 setOperationAction(ISD::UADDO, VT, Custom);
1738 setOperationAction(ISD::SSUBO, VT, Custom);
1739 setOperationAction(ISD::USUBO, VT, Custom);
1740 setOperationAction(ISD::SMULO, VT, Custom);
1741 setOperationAction(ISD::UMULO, VT, Custom);
1744 if (!Subtarget->is64Bit()) {
1745 // These libcalls are not available in 32-bit.
1746 setLibcallName(RTLIB::SHL_I128, nullptr);
1747 setLibcallName(RTLIB::SRL_I128, nullptr);
1748 setLibcallName(RTLIB::SRA_I128, nullptr);
1751 // Combine sin / cos into one node or libcall if possible.
1752 if (Subtarget->hasSinCos()) {
1753 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1754 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1755 if (Subtarget->isTargetDarwin()) {
1756 // For MacOSX, we don't want the normal expansion of a libcall to sincos.
1757 // We want to issue a libcall to __sincos_stret to avoid memory traffic.
1758 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1759 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1763 if (Subtarget->isTargetWin64()) {
1764 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1765 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1766 setOperationAction(ISD::SREM, MVT::i128, Custom);
1767 setOperationAction(ISD::UREM, MVT::i128, Custom);
1768 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1769 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1772 // We have target-specific dag combine patterns for the following nodes:
1773 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1774 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1775 setTargetDAGCombine(ISD::BITCAST);
1776 setTargetDAGCombine(ISD::VSELECT);
1777 setTargetDAGCombine(ISD::SELECT);
1778 setTargetDAGCombine(ISD::SHL);
1779 setTargetDAGCombine(ISD::SRA);
1780 setTargetDAGCombine(ISD::SRL);
1781 setTargetDAGCombine(ISD::OR);
1782 setTargetDAGCombine(ISD::AND);
1783 setTargetDAGCombine(ISD::ADD);
1784 setTargetDAGCombine(ISD::FADD);
1785 setTargetDAGCombine(ISD::FSUB);
1786 setTargetDAGCombine(ISD::FNEG);
1787 setTargetDAGCombine(ISD::FMA);
1788 setTargetDAGCombine(ISD::SUB);
1789 setTargetDAGCombine(ISD::LOAD);
1790 setTargetDAGCombine(ISD::MLOAD);
1791 setTargetDAGCombine(ISD::STORE);
1792 setTargetDAGCombine(ISD::MSTORE);
1793 setTargetDAGCombine(ISD::TRUNCATE);
1794 setTargetDAGCombine(ISD::ZERO_EXTEND);
1795 setTargetDAGCombine(ISD::ANY_EXTEND);
1796 setTargetDAGCombine(ISD::SIGN_EXTEND);
1797 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1798 setTargetDAGCombine(ISD::SINT_TO_FP);
1799 setTargetDAGCombine(ISD::UINT_TO_FP);
1800 setTargetDAGCombine(ISD::SETCC);
1801 setTargetDAGCombine(ISD::BUILD_VECTOR);
1802 setTargetDAGCombine(ISD::MUL);
1803 setTargetDAGCombine(ISD::XOR);
1805 computeRegisterProperties(Subtarget->getRegisterInfo());
1807 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1808 MaxStoresPerMemsetOptSize = 8;
1809 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1810 MaxStoresPerMemcpyOptSize = 4;
1811 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1812 MaxStoresPerMemmoveOptSize = 4;
1813 setPrefLoopAlignment(4); // 2^4 bytes.
1815 // A predictable cmov does not hurt on an in-order CPU.
1816 // FIXME: Use a CPU attribute to trigger this, not a CPU model.
1817 PredictableSelectIsExpensive = !Subtarget->isAtom();
1818 EnableExtLdPromotion = true;
1819 setPrefFunctionAlignment(4); // 2^4 bytes.
1821 verifyIntrinsicTables();
1824 // This has so far only been implemented for 64-bit MachO.
1825 bool X86TargetLowering::useLoadStackGuardNode() const {
1826 return Subtarget->isTargetMachO() && Subtarget->is64Bit();
1829 TargetLoweringBase::LegalizeTypeAction
1830 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1831 if (ExperimentalVectorWideningLegalization &&
1832 VT.getVectorNumElements() != 1 &&
1833 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1834 return TypeWidenVector;
1836 return TargetLoweringBase::getPreferredVectorAction(VT);
1839 EVT X86TargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
1842 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1844 if (VT.isSimple()) {
1845 MVT VVT = VT.getSimpleVT();
1846 const unsigned NumElts = VVT.getVectorNumElements();
1847 const MVT EltVT = VVT.getVectorElementType();
1848 if (VVT.is512BitVector()) {
1849 if (Subtarget->hasAVX512())
1850 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1851 EltVT == MVT::f32 || EltVT == MVT::f64)
1853 case 8: return MVT::v8i1;
1854 case 16: return MVT::v16i1;
1856 if (Subtarget->hasBWI())
1857 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1859 case 32: return MVT::v32i1;
1860 case 64: return MVT::v64i1;
1864 if (VVT.is256BitVector() || VVT.is128BitVector()) {
1865 if (Subtarget->hasVLX())
1866 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1867 EltVT == MVT::f32 || EltVT == MVT::f64)
1869 case 2: return MVT::v2i1;
1870 case 4: return MVT::v4i1;
1871 case 8: return MVT::v8i1;
1873 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1874 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1876 case 8: return MVT::v8i1;
1877 case 16: return MVT::v16i1;
1878 case 32: return MVT::v32i1;
1883 return VT.changeVectorElementTypeToInteger();
1886 /// Helper for getByValTypeAlignment to determine
1887 /// the desired ByVal argument alignment.
1888 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1891 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1892 if (VTy->getBitWidth() == 128)
1894 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1895 unsigned EltAlign = 0;
1896 getMaxByValAlign(ATy->getElementType(), EltAlign);
1897 if (EltAlign > MaxAlign)
1898 MaxAlign = EltAlign;
1899 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1900 for (auto *EltTy : STy->elements()) {
1901 unsigned EltAlign = 0;
1902 getMaxByValAlign(EltTy, EltAlign);
1903 if (EltAlign > MaxAlign)
1904 MaxAlign = EltAlign;
1911 /// Return the desired alignment for ByVal aggregate
1912 /// function arguments in the caller parameter area. For X86, aggregates
1913 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1914 /// are at 4-byte boundaries.
1915 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty,
1916 const DataLayout &DL) const {
1917 if (Subtarget->is64Bit()) {
1918 // Max of 8 and alignment of type.
1919 unsigned TyAlign = DL.getABITypeAlignment(Ty);
1926 if (Subtarget->hasSSE1())
1927 getMaxByValAlign(Ty, Align);
1931 /// Returns the target specific optimal type for load
1932 /// and store operations as a result of memset, memcpy, and memmove
1933 /// lowering. If DstAlign is zero that means it's safe to destination
1934 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1935 /// means there isn't a need to check it against alignment requirement,
1936 /// probably because the source does not need to be loaded. If 'IsMemset' is
1937 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1938 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1939 /// source is constant so it does not need to be loaded.
1940 /// It returns EVT::Other if the type should be determined using generic
1941 /// target-independent logic.
1943 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1944 unsigned DstAlign, unsigned SrcAlign,
1945 bool IsMemset, bool ZeroMemset,
1947 MachineFunction &MF) const {
1948 const Function *F = MF.getFunction();
1949 if ((!IsMemset || ZeroMemset) &&
1950 !F->hasFnAttribute(Attribute::NoImplicitFloat)) {
1952 (!Subtarget->isUnalignedMem16Slow() ||
1953 ((DstAlign == 0 || DstAlign >= 16) &&
1954 (SrcAlign == 0 || SrcAlign >= 16)))) {
1956 // FIXME: Check if unaligned 32-byte accesses are slow.
1957 if (Subtarget->hasInt256())
1959 if (Subtarget->hasFp256())
1962 if (Subtarget->hasSSE2())
1964 if (Subtarget->hasSSE1())
1966 } else if (!MemcpyStrSrc && Size >= 8 &&
1967 !Subtarget->is64Bit() &&
1968 Subtarget->hasSSE2()) {
1969 // Do not use f64 to lower memcpy if source is string constant. It's
1970 // better to use i32 to avoid the loads.
1974 // This is a compromise. If we reach here, unaligned accesses may be slow on
1975 // this target. However, creating smaller, aligned accesses could be even
1976 // slower and would certainly be a lot more code.
1977 if (Subtarget->is64Bit() && Size >= 8)
1982 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1984 return X86ScalarSSEf32;
1985 else if (VT == MVT::f64)
1986 return X86ScalarSSEf64;
1991 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1996 switch (VT.getSizeInBits()) {
1998 // 8-byte and under are always assumed to be fast.
2002 *Fast = !Subtarget->isUnalignedMem16Slow();
2005 *Fast = !Subtarget->isUnalignedMem32Slow();
2007 // TODO: What about AVX-512 (512-bit) accesses?
2010 // Misaligned accesses of any size are always allowed.
2014 /// Return the entry encoding for a jump table in the
2015 /// current function. The returned value is a member of the
2016 /// MachineJumpTableInfo::JTEntryKind enum.
2017 unsigned X86TargetLowering::getJumpTableEncoding() const {
2018 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
2020 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2021 Subtarget->isPICStyleGOT())
2022 return MachineJumpTableInfo::EK_Custom32;
2024 // Otherwise, use the normal jump table encoding heuristics.
2025 return TargetLowering::getJumpTableEncoding();
2028 bool X86TargetLowering::useSoftFloat() const {
2029 return Subtarget->useSoftFloat();
2033 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
2034 const MachineBasicBlock *MBB,
2035 unsigned uid,MCContext &Ctx) const{
2036 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
2037 Subtarget->isPICStyleGOT());
2038 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
2040 return MCSymbolRefExpr::create(MBB->getSymbol(),
2041 MCSymbolRefExpr::VK_GOTOFF, Ctx);
2044 /// Returns relocation base for the given PIC jumptable.
2045 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
2046 SelectionDAG &DAG) const {
2047 if (!Subtarget->is64Bit())
2048 // This doesn't have SDLoc associated with it, but is not really the
2049 // same as a Register.
2050 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(),
2051 getPointerTy(DAG.getDataLayout()));
2055 /// This returns the relocation base for the given PIC jumptable,
2056 /// the same as getPICJumpTableRelocBase, but as an MCExpr.
2057 const MCExpr *X86TargetLowering::
2058 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
2059 MCContext &Ctx) const {
2060 // X86-64 uses RIP relative addressing based on the jump table label.
2061 if (Subtarget->isPICStyleRIPRel())
2062 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
2064 // Otherwise, the reference is relative to the PIC base.
2065 return MCSymbolRefExpr::create(MF->getPICBaseSymbol(), Ctx);
2068 std::pair<const TargetRegisterClass *, uint8_t>
2069 X86TargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
2071 const TargetRegisterClass *RRC = nullptr;
2073 switch (VT.SimpleTy) {
2075 return TargetLowering::findRepresentativeClass(TRI, VT);
2076 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
2077 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
2080 RRC = &X86::VR64RegClass;
2082 case MVT::f32: case MVT::f64:
2083 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
2084 case MVT::v4f32: case MVT::v2f64:
2085 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
2087 RRC = &X86::VR128RegClass;
2090 return std::make_pair(RRC, Cost);
2093 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
2094 unsigned &Offset) const {
2095 if (!Subtarget->isTargetLinux())
2098 if (Subtarget->is64Bit()) {
2099 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
2101 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
2113 Value *X86TargetLowering::getSafeStackPointerLocation(IRBuilder<> &IRB) const {
2114 if (!Subtarget->isTargetAndroid())
2115 return TargetLowering::getSafeStackPointerLocation(IRB);
2117 // Android provides a fixed TLS slot for the SafeStack pointer. See the
2118 // definition of TLS_SLOT_SAFESTACK in
2119 // https://android.googlesource.com/platform/bionic/+/master/libc/private/bionic_tls.h
2120 unsigned AddressSpace, Offset;
2121 if (Subtarget->is64Bit()) {
2122 // %fs:0x48, unless we're using a Kernel code model, in which case it's %gs:
2124 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
2134 return ConstantExpr::getIntToPtr(
2135 ConstantInt::get(Type::getInt32Ty(IRB.getContext()), Offset),
2136 Type::getInt8PtrTy(IRB.getContext())->getPointerTo(AddressSpace));
2139 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
2140 unsigned DestAS) const {
2141 assert(SrcAS != DestAS && "Expected different address spaces!");
2143 return SrcAS < 256 && DestAS < 256;
2146 //===----------------------------------------------------------------------===//
2147 // Return Value Calling Convention Implementation
2148 //===----------------------------------------------------------------------===//
2150 #include "X86GenCallingConv.inc"
2152 bool X86TargetLowering::CanLowerReturn(
2153 CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
2154 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
2155 SmallVector<CCValAssign, 16> RVLocs;
2156 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
2157 return CCInfo.CheckReturn(Outs, RetCC_X86);
2160 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
2161 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
2166 X86TargetLowering::LowerReturn(SDValue Chain,
2167 CallingConv::ID CallConv, bool isVarArg,
2168 const SmallVectorImpl<ISD::OutputArg> &Outs,
2169 const SmallVectorImpl<SDValue> &OutVals,
2170 SDLoc dl, SelectionDAG &DAG) const {
2171 MachineFunction &MF = DAG.getMachineFunction();
2172 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2174 SmallVector<CCValAssign, 16> RVLocs;
2175 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
2176 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
2179 SmallVector<SDValue, 6> RetOps;
2180 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2181 // Operand #1 = Bytes To Pop
2182 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(), dl,
2185 // Copy the result values into the output registers.
2186 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2187 CCValAssign &VA = RVLocs[i];
2188 assert(VA.isRegLoc() && "Can only return in registers!");
2189 SDValue ValToCopy = OutVals[i];
2190 EVT ValVT = ValToCopy.getValueType();
2192 // Promote values to the appropriate types.
2193 if (VA.getLocInfo() == CCValAssign::SExt)
2194 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2195 else if (VA.getLocInfo() == CCValAssign::ZExt)
2196 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2197 else if (VA.getLocInfo() == CCValAssign::AExt) {
2198 if (ValVT.isVector() && ValVT.getVectorElementType() == MVT::i1)
2199 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2201 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2203 else if (VA.getLocInfo() == CCValAssign::BCvt)
2204 ValToCopy = DAG.getBitcast(VA.getLocVT(), ValToCopy);
2206 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2207 "Unexpected FP-extend for return value.");
2209 // If this is x86-64, and we disabled SSE, we can't return FP values,
2210 // or SSE or MMX vectors.
2211 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2212 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2213 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2214 report_fatal_error("SSE register return with SSE disabled");
2216 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2217 // llvm-gcc has never done it right and no one has noticed, so this
2218 // should be OK for now.
2219 if (ValVT == MVT::f64 &&
2220 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2221 report_fatal_error("SSE2 register return with SSE2 disabled");
2223 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2224 // the RET instruction and handled by the FP Stackifier.
2225 if (VA.getLocReg() == X86::FP0 ||
2226 VA.getLocReg() == X86::FP1) {
2227 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2228 // change the value to the FP stack register class.
2229 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2230 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2231 RetOps.push_back(ValToCopy);
2232 // Don't emit a copytoreg.
2236 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2237 // which is returned in RAX / RDX.
2238 if (Subtarget->is64Bit()) {
2239 if (ValVT == MVT::x86mmx) {
2240 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2241 ValToCopy = DAG.getBitcast(MVT::i64, ValToCopy);
2242 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2244 // If we don't have SSE2 available, convert to v4f32 so the generated
2245 // register is legal.
2246 if (!Subtarget->hasSSE2())
2247 ValToCopy = DAG.getBitcast(MVT::v4f32, ValToCopy);
2252 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2253 Flag = Chain.getValue(1);
2254 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2257 // All x86 ABIs require that for returning structs by value we copy
2258 // the sret argument into %rax/%eax (depending on ABI) for the return.
2259 // We saved the argument into a virtual register in the entry block,
2260 // so now we copy the value out and into %rax/%eax.
2262 // Checking Function.hasStructRetAttr() here is insufficient because the IR
2263 // may not have an explicit sret argument. If FuncInfo.CanLowerReturn is
2264 // false, then an sret argument may be implicitly inserted in the SelDAG. In
2265 // either case FuncInfo->setSRetReturnReg() will have been called.
2266 if (unsigned SRetReg = FuncInfo->getSRetReturnReg()) {
2267 SDValue Val = DAG.getCopyFromReg(Chain, dl, SRetReg,
2268 getPointerTy(MF.getDataLayout()));
2271 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2272 X86::RAX : X86::EAX;
2273 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2274 Flag = Chain.getValue(1);
2276 // RAX/EAX now acts like a return value.
2278 DAG.getRegister(RetValReg, getPointerTy(DAG.getDataLayout())));
2281 RetOps[0] = Chain; // Update chain.
2283 // Add the flag if we have it.
2285 RetOps.push_back(Flag);
2287 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2290 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2291 if (N->getNumValues() != 1)
2293 if (!N->hasNUsesOfValue(1, 0))
2296 SDValue TCChain = Chain;
2297 SDNode *Copy = *N->use_begin();
2298 if (Copy->getOpcode() == ISD::CopyToReg) {
2299 // If the copy has a glue operand, we conservatively assume it isn't safe to
2300 // perform a tail call.
2301 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2303 TCChain = Copy->getOperand(0);
2304 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2307 bool HasRet = false;
2308 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2310 if (UI->getOpcode() != X86ISD::RET_FLAG)
2312 // If we are returning more than one value, we can definitely
2313 // not make a tail call see PR19530
2314 if (UI->getNumOperands() > 4)
2316 if (UI->getNumOperands() == 4 &&
2317 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2330 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2331 ISD::NodeType ExtendKind) const {
2333 // TODO: Is this also valid on 32-bit?
2334 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2335 ReturnMVT = MVT::i8;
2337 ReturnMVT = MVT::i32;
2339 EVT MinVT = getRegisterType(Context, ReturnMVT);
2340 return VT.bitsLT(MinVT) ? MinVT : VT;
2343 /// Lower the result values of a call into the
2344 /// appropriate copies out of appropriate physical registers.
2347 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2348 CallingConv::ID CallConv, bool isVarArg,
2349 const SmallVectorImpl<ISD::InputArg> &Ins,
2350 SDLoc dl, SelectionDAG &DAG,
2351 SmallVectorImpl<SDValue> &InVals) const {
2353 // Assign locations to each value returned by this call.
2354 SmallVector<CCValAssign, 16> RVLocs;
2355 bool Is64Bit = Subtarget->is64Bit();
2356 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2358 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2360 // Copy all of the result registers out of their specified physreg.
2361 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2362 CCValAssign &VA = RVLocs[i];
2363 EVT CopyVT = VA.getLocVT();
2365 // If this is x86-64, and we disabled SSE, we can't return FP values
2366 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2367 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2368 report_fatal_error("SSE register return with SSE disabled");
2371 // If we prefer to use the value in xmm registers, copy it out as f80 and
2372 // use a truncate to move it from fp stack reg to xmm reg.
2373 bool RoundAfterCopy = false;
2374 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2375 isScalarFPTypeInSSEReg(VA.getValVT())) {
2377 RoundAfterCopy = (CopyVT != VA.getLocVT());
2380 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2381 CopyVT, InFlag).getValue(1);
2382 SDValue Val = Chain.getValue(0);
2385 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2386 // This truncation won't change the value.
2387 DAG.getIntPtrConstant(1, dl));
2389 if (VA.isExtInLoc() && VA.getValVT().getScalarType() == MVT::i1)
2390 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
2392 InFlag = Chain.getValue(2);
2393 InVals.push_back(Val);
2399 //===----------------------------------------------------------------------===//
2400 // C & StdCall & Fast Calling Convention implementation
2401 //===----------------------------------------------------------------------===//
2402 // StdCall calling convention seems to be standard for many Windows' API
2403 // routines and around. It differs from C calling convention just a little:
2404 // callee should clean up the stack, not caller. Symbols should be also
2405 // decorated in some fancy way :) It doesn't support any vector arguments.
2406 // For info on fast calling convention see Fast Calling Convention (tail call)
2407 // implementation LowerX86_32FastCCCallTo.
2409 /// CallIsStructReturn - Determines whether a call uses struct return
2411 enum StructReturnType {
2416 static StructReturnType
2417 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2419 return NotStructReturn;
2421 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2422 if (!Flags.isSRet())
2423 return NotStructReturn;
2424 if (Flags.isInReg())
2425 return RegStructReturn;
2426 return StackStructReturn;
2429 /// Determines whether a function uses struct return semantics.
2430 static StructReturnType
2431 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2433 return NotStructReturn;
2435 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2436 if (!Flags.isSRet())
2437 return NotStructReturn;
2438 if (Flags.isInReg())
2439 return RegStructReturn;
2440 return StackStructReturn;
2443 /// Make a copy of an aggregate at address specified by "Src" to address
2444 /// "Dst" with size and alignment information specified by the specific
2445 /// parameter attribute. The copy will be passed as a byval function parameter.
2447 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2448 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2450 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
2452 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2453 /*isVolatile*/false, /*AlwaysInline=*/true,
2454 /*isTailCall*/false,
2455 MachinePointerInfo(), MachinePointerInfo());
2458 /// Return true if the calling convention is one that we can guarantee TCO for.
2459 static bool canGuaranteeTCO(CallingConv::ID CC) {
2460 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2461 CC == CallingConv::HiPE || CC == CallingConv::HHVM);
2464 /// Return true if we might ever do TCO for calls with this calling convention.
2465 static bool mayTailCallThisCC(CallingConv::ID CC) {
2467 // C calling conventions:
2468 case CallingConv::C:
2469 case CallingConv::X86_64_Win64:
2470 case CallingConv::X86_64_SysV:
2471 // Callee pop conventions:
2472 case CallingConv::X86_ThisCall:
2473 case CallingConv::X86_StdCall:
2474 case CallingConv::X86_VectorCall:
2475 case CallingConv::X86_FastCall:
2478 return canGuaranteeTCO(CC);
2482 /// Return true if the function is being made into a tailcall target by
2483 /// changing its ABI.
2484 static bool shouldGuaranteeTCO(CallingConv::ID CC, bool GuaranteedTailCallOpt) {
2485 return GuaranteedTailCallOpt && canGuaranteeTCO(CC);
2488 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2490 CI->getParent()->getParent()->getFnAttribute("disable-tail-calls");
2491 if (!CI->isTailCall() || Attr.getValueAsString() == "true")
2495 CallingConv::ID CalleeCC = CS.getCallingConv();
2496 if (!mayTailCallThisCC(CalleeCC))
2503 X86TargetLowering::LowerMemArgument(SDValue Chain,
2504 CallingConv::ID CallConv,
2505 const SmallVectorImpl<ISD::InputArg> &Ins,
2506 SDLoc dl, SelectionDAG &DAG,
2507 const CCValAssign &VA,
2508 MachineFrameInfo *MFI,
2510 // Create the nodes corresponding to a load from this parameter slot.
2511 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2512 bool AlwaysUseMutable = shouldGuaranteeTCO(
2513 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2514 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2517 // If value is passed by pointer we have address passed instead of the value
2519 bool ExtendedInMem = VA.isExtInLoc() &&
2520 VA.getValVT().getScalarType() == MVT::i1;
2522 if (VA.getLocInfo() == CCValAssign::Indirect || ExtendedInMem)
2523 ValVT = VA.getLocVT();
2525 ValVT = VA.getValVT();
2527 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2528 // changed with more analysis.
2529 // In case of tail call optimization mark all arguments mutable. Since they
2530 // could be overwritten by lowering of arguments in case of a tail call.
2531 if (Flags.isByVal()) {
2532 unsigned Bytes = Flags.getByValSize();
2533 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2534 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2535 return DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2537 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2538 VA.getLocMemOffset(), isImmutable);
2539 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2540 SDValue Val = DAG.getLoad(
2541 ValVT, dl, Chain, FIN,
2542 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), false,
2544 return ExtendedInMem ?
2545 DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val) : Val;
2549 // FIXME: Get this from tablegen.
2550 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2551 const X86Subtarget *Subtarget) {
2552 assert(Subtarget->is64Bit());
2554 if (Subtarget->isCallingConvWin64(CallConv)) {
2555 static const MCPhysReg GPR64ArgRegsWin64[] = {
2556 X86::RCX, X86::RDX, X86::R8, X86::R9
2558 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2561 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2562 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2564 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2567 // FIXME: Get this from tablegen.
2568 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2569 CallingConv::ID CallConv,
2570 const X86Subtarget *Subtarget) {
2571 assert(Subtarget->is64Bit());
2572 if (Subtarget->isCallingConvWin64(CallConv)) {
2573 // The XMM registers which might contain var arg parameters are shadowed
2574 // in their paired GPR. So we only need to save the GPR to their home
2576 // TODO: __vectorcall will change this.
2580 const Function *Fn = MF.getFunction();
2581 bool NoImplicitFloatOps = Fn->hasFnAttribute(Attribute::NoImplicitFloat);
2582 bool isSoftFloat = Subtarget->useSoftFloat();
2583 assert(!(isSoftFloat && NoImplicitFloatOps) &&
2584 "SSE register cannot be used when SSE is disabled!");
2585 if (isSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1())
2586 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2590 static const MCPhysReg XMMArgRegs64Bit[] = {
2591 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2592 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2594 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2597 SDValue X86TargetLowering::LowerFormalArguments(
2598 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
2599 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG,
2600 SmallVectorImpl<SDValue> &InVals) const {
2601 MachineFunction &MF = DAG.getMachineFunction();
2602 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2603 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
2605 const Function* Fn = MF.getFunction();
2606 if (Fn->hasExternalLinkage() &&
2607 Subtarget->isTargetCygMing() &&
2608 Fn->getName() == "main")
2609 FuncInfo->setForceFramePointer(true);
2611 MachineFrameInfo *MFI = MF.getFrameInfo();
2612 bool Is64Bit = Subtarget->is64Bit();
2613 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2615 assert(!(isVarArg && canGuaranteeTCO(CallConv)) &&
2616 "Var args not supported with calling convention fastcc, ghc or hipe");
2618 // Assign locations to all of the incoming arguments.
2619 SmallVector<CCValAssign, 16> ArgLocs;
2620 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2622 // Allocate shadow area for Win64
2624 CCInfo.AllocateStack(32, 8);
2626 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2628 unsigned LastVal = ~0U;
2630 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2631 CCValAssign &VA = ArgLocs[i];
2632 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2634 assert(VA.getValNo() != LastVal &&
2635 "Don't support value assigned to multiple locs yet");
2637 LastVal = VA.getValNo();
2639 if (VA.isRegLoc()) {
2640 EVT RegVT = VA.getLocVT();
2641 const TargetRegisterClass *RC;
2642 if (RegVT == MVT::i32)
2643 RC = &X86::GR32RegClass;
2644 else if (Is64Bit && RegVT == MVT::i64)
2645 RC = &X86::GR64RegClass;
2646 else if (RegVT == MVT::f32)
2647 RC = &X86::FR32RegClass;
2648 else if (RegVT == MVT::f64)
2649 RC = &X86::FR64RegClass;
2650 else if (RegVT.is512BitVector())
2651 RC = &X86::VR512RegClass;
2652 else if (RegVT.is256BitVector())
2653 RC = &X86::VR256RegClass;
2654 else if (RegVT.is128BitVector())
2655 RC = &X86::VR128RegClass;
2656 else if (RegVT == MVT::x86mmx)
2657 RC = &X86::VR64RegClass;
2658 else if (RegVT == MVT::i1)
2659 RC = &X86::VK1RegClass;
2660 else if (RegVT == MVT::v8i1)
2661 RC = &X86::VK8RegClass;
2662 else if (RegVT == MVT::v16i1)
2663 RC = &X86::VK16RegClass;
2664 else if (RegVT == MVT::v32i1)
2665 RC = &X86::VK32RegClass;
2666 else if (RegVT == MVT::v64i1)
2667 RC = &X86::VK64RegClass;
2669 llvm_unreachable("Unknown argument type!");
2671 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2672 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2674 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2675 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2677 if (VA.getLocInfo() == CCValAssign::SExt)
2678 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2679 DAG.getValueType(VA.getValVT()));
2680 else if (VA.getLocInfo() == CCValAssign::ZExt)
2681 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2682 DAG.getValueType(VA.getValVT()));
2683 else if (VA.getLocInfo() == CCValAssign::BCvt)
2684 ArgValue = DAG.getBitcast(VA.getValVT(), ArgValue);
2686 if (VA.isExtInLoc()) {
2687 // Handle MMX values passed in XMM regs.
2688 if (RegVT.isVector() && VA.getValVT().getScalarType() != MVT::i1)
2689 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2691 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2694 assert(VA.isMemLoc());
2695 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2698 // If value is passed via pointer - do a load.
2699 if (VA.getLocInfo() == CCValAssign::Indirect)
2700 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2701 MachinePointerInfo(), false, false, false, 0);
2703 InVals.push_back(ArgValue);
2706 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2707 // All x86 ABIs require that for returning structs by value we copy the
2708 // sret argument into %rax/%eax (depending on ABI) for the return. Save
2709 // the argument into a virtual register so that we can access it from the
2711 if (Ins[i].Flags.isSRet()) {
2712 unsigned Reg = FuncInfo->getSRetReturnReg();
2714 MVT PtrTy = getPointerTy(DAG.getDataLayout());
2715 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2716 FuncInfo->setSRetReturnReg(Reg);
2718 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2719 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2724 unsigned StackSize = CCInfo.getNextStackOffset();
2725 // Align stack specially for tail calls.
2726 if (shouldGuaranteeTCO(CallConv,
2727 MF.getTarget().Options.GuaranteedTailCallOpt))
2728 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2730 // If the function takes variable number of arguments, make a frame index for
2731 // the start of the first vararg value... for expansion of llvm.va_start. We
2732 // can skip this if there are no va_start calls.
2733 if (MFI->hasVAStart() &&
2734 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2735 CallConv != CallingConv::X86_ThisCall))) {
2736 FuncInfo->setVarArgsFrameIndex(
2737 MFI->CreateFixedObject(1, StackSize, true));
2740 // Figure out if XMM registers are in use.
2741 assert(!(Subtarget->useSoftFloat() &&
2742 Fn->hasFnAttribute(Attribute::NoImplicitFloat)) &&
2743 "SSE register cannot be used when SSE is disabled!");
2745 // 64-bit calling conventions support varargs and register parameters, so we
2746 // have to do extra work to spill them in the prologue.
2747 if (Is64Bit && isVarArg && MFI->hasVAStart()) {
2748 // Find the first unallocated argument registers.
2749 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2750 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2751 unsigned NumIntRegs = CCInfo.getFirstUnallocated(ArgGPRs);
2752 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(ArgXMMs);
2753 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2754 "SSE register cannot be used when SSE is disabled!");
2756 // Gather all the live in physical registers.
2757 SmallVector<SDValue, 6> LiveGPRs;
2758 SmallVector<SDValue, 8> LiveXMMRegs;
2760 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2761 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2763 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2765 if (!ArgXMMs.empty()) {
2766 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2767 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2768 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2769 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2770 LiveXMMRegs.push_back(
2771 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2776 // Get to the caller-allocated home save location. Add 8 to account
2777 // for the return address.
2778 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2779 FuncInfo->setRegSaveFrameIndex(
2780 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2781 // Fixup to set vararg frame on shadow area (4 x i64).
2783 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2785 // For X86-64, if there are vararg parameters that are passed via
2786 // registers, then we must store them to their spots on the stack so
2787 // they may be loaded by deferencing the result of va_next.
2788 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2789 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2790 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2791 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2794 // Store the integer parameter registers.
2795 SmallVector<SDValue, 8> MemOps;
2796 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2797 getPointerTy(DAG.getDataLayout()));
2798 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2799 for (SDValue Val : LiveGPRs) {
2800 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
2801 RSFIN, DAG.getIntPtrConstant(Offset, dl));
2803 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2804 MachinePointerInfo::getFixedStack(
2805 DAG.getMachineFunction(),
2806 FuncInfo->getRegSaveFrameIndex(), Offset),
2808 MemOps.push_back(Store);
2812 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2813 // Now store the XMM (fp + vector) parameter registers.
2814 SmallVector<SDValue, 12> SaveXMMOps;
2815 SaveXMMOps.push_back(Chain);
2816 SaveXMMOps.push_back(ALVal);
2817 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2818 FuncInfo->getRegSaveFrameIndex(), dl));
2819 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2820 FuncInfo->getVarArgsFPOffset(), dl));
2821 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2823 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2824 MVT::Other, SaveXMMOps));
2827 if (!MemOps.empty())
2828 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2831 if (isVarArg && MFI->hasMustTailInVarArgFunc()) {
2832 // Find the largest legal vector type.
2833 MVT VecVT = MVT::Other;
2834 // FIXME: Only some x86_32 calling conventions support AVX512.
2835 if (Subtarget->hasAVX512() &&
2836 (Is64Bit || (CallConv == CallingConv::X86_VectorCall ||
2837 CallConv == CallingConv::Intel_OCL_BI)))
2838 VecVT = MVT::v16f32;
2839 else if (Subtarget->hasAVX())
2841 else if (Subtarget->hasSSE2())
2844 // We forward some GPRs and some vector types.
2845 SmallVector<MVT, 2> RegParmTypes;
2846 MVT IntVT = Is64Bit ? MVT::i64 : MVT::i32;
2847 RegParmTypes.push_back(IntVT);
2848 if (VecVT != MVT::Other)
2849 RegParmTypes.push_back(VecVT);
2851 // Compute the set of forwarded registers. The rest are scratch.
2852 SmallVectorImpl<ForwardedRegister> &Forwards =
2853 FuncInfo->getForwardedMustTailRegParms();
2854 CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes, CC_X86);
2856 // Conservatively forward AL on x86_64, since it might be used for varargs.
2857 if (Is64Bit && !CCInfo.isAllocated(X86::AL)) {
2858 unsigned ALVReg = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2859 Forwards.push_back(ForwardedRegister(ALVReg, X86::AL, MVT::i8));
2862 // Copy all forwards from physical to virtual registers.
2863 for (ForwardedRegister &F : Forwards) {
2864 // FIXME: Can we use a less constrained schedule?
2865 SDValue RegVal = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2866 F.VReg = MF.getRegInfo().createVirtualRegister(getRegClassFor(F.VT));
2867 Chain = DAG.getCopyToReg(Chain, dl, F.VReg, RegVal);
2871 // Some CCs need callee pop.
2872 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2873 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2874 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2876 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2877 // If this is an sret function, the return should pop the hidden pointer.
2878 if (!Is64Bit && !canGuaranteeTCO(CallConv) &&
2879 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2880 argsAreStructReturn(Ins) == StackStructReturn)
2881 FuncInfo->setBytesToPopOnReturn(4);
2885 // RegSaveFrameIndex is X86-64 only.
2886 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2887 if (CallConv == CallingConv::X86_FastCall ||
2888 CallConv == CallingConv::X86_ThisCall)
2889 // fastcc functions can't have varargs.
2890 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2893 FuncInfo->setArgumentStackSize(StackSize);
2895 if (WinEHFuncInfo *EHInfo = MF.getWinEHFuncInfo()) {
2896 EHPersonality Personality = classifyEHPersonality(Fn->getPersonalityFn());
2897 if (Personality == EHPersonality::CoreCLR) {
2899 // TODO: Add a mechanism to frame lowering that will allow us to indicate
2900 // that we'd prefer this slot be allocated towards the bottom of the frame
2901 // (i.e. near the stack pointer after allocating the frame). Every
2902 // funclet needs a copy of this slot in its (mostly empty) frame, and the
2903 // offset from the bottom of this and each funclet's frame must be the
2904 // same, so the size of funclets' (mostly empty) frames is dictated by
2905 // how far this slot is from the bottom (since they allocate just enough
2906 // space to accomodate holding this slot at the correct offset).
2907 int PSPSymFI = MFI->CreateStackObject(8, 8, /*isSS=*/false);
2908 EHInfo->PSPSymFrameIdx = PSPSymFI;
2916 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2917 SDValue StackPtr, SDValue Arg,
2918 SDLoc dl, SelectionDAG &DAG,
2919 const CCValAssign &VA,
2920 ISD::ArgFlagsTy Flags) const {
2921 unsigned LocMemOffset = VA.getLocMemOffset();
2922 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
2923 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
2925 if (Flags.isByVal())
2926 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2928 return DAG.getStore(
2929 Chain, dl, Arg, PtrOff,
2930 MachinePointerInfo::getStack(DAG.getMachineFunction(), LocMemOffset),
2934 /// Emit a load of return address if tail call
2935 /// optimization is performed and it is required.
2937 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2938 SDValue &OutRetAddr, SDValue Chain,
2939 bool IsTailCall, bool Is64Bit,
2940 int FPDiff, SDLoc dl) const {
2941 // Adjust the Return address stack slot.
2942 EVT VT = getPointerTy(DAG.getDataLayout());
2943 OutRetAddr = getReturnAddressFrameIndex(DAG);
2945 // Load the "old" Return address.
2946 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2947 false, false, false, 0);
2948 return SDValue(OutRetAddr.getNode(), 1);
2951 /// Emit a store of the return address if tail call
2952 /// optimization is performed and it is required (FPDiff!=0).
2953 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2954 SDValue Chain, SDValue RetAddrFrIdx,
2955 EVT PtrVT, unsigned SlotSize,
2956 int FPDiff, SDLoc dl) {
2957 // Store the return address to the appropriate stack slot.
2958 if (!FPDiff) return Chain;
2959 // Calculate the new stack slot for the return address.
2960 int NewReturnAddrFI =
2961 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2963 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2964 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2965 MachinePointerInfo::getFixedStack(
2966 DAG.getMachineFunction(), NewReturnAddrFI),
2971 /// Returns a vector_shuffle mask for an movs{s|d}, movd
2972 /// operation of specified width.
2973 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
2975 unsigned NumElems = VT.getVectorNumElements();
2976 SmallVector<int, 8> Mask;
2977 Mask.push_back(NumElems);
2978 for (unsigned i = 1; i != NumElems; ++i)
2980 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
2984 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2985 SmallVectorImpl<SDValue> &InVals) const {
2986 SelectionDAG &DAG = CLI.DAG;
2988 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2989 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2990 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2991 SDValue Chain = CLI.Chain;
2992 SDValue Callee = CLI.Callee;
2993 CallingConv::ID CallConv = CLI.CallConv;
2994 bool &isTailCall = CLI.IsTailCall;
2995 bool isVarArg = CLI.IsVarArg;
2997 MachineFunction &MF = DAG.getMachineFunction();
2998 bool Is64Bit = Subtarget->is64Bit();
2999 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
3000 StructReturnType SR = callIsStructReturn(Outs);
3001 bool IsSibcall = false;
3002 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
3003 auto Attr = MF.getFunction()->getFnAttribute("disable-tail-calls");
3005 if (Attr.getValueAsString() == "true")
3008 if (Subtarget->isPICStyleGOT() &&
3009 !MF.getTarget().Options.GuaranteedTailCallOpt) {
3010 // If we are using a GOT, disable tail calls to external symbols with
3011 // default visibility. Tail calling such a symbol requires using a GOT
3012 // relocation, which forces early binding of the symbol. This breaks code
3013 // that require lazy function symbol resolution. Using musttail or
3014 // GuaranteedTailCallOpt will override this.
3015 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
3016 if (!G || (!G->getGlobal()->hasLocalLinkage() &&
3017 G->getGlobal()->hasDefaultVisibility()))
3021 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
3023 // Force this to be a tail call. The verifier rules are enough to ensure
3024 // that we can lower this successfully without moving the return address
3027 } else if (isTailCall) {
3028 // Check if it's really possible to do a tail call.
3029 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
3030 isVarArg, SR != NotStructReturn,
3031 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
3032 Outs, OutVals, Ins, DAG);
3034 // Sibcalls are automatically detected tailcalls which do not require
3036 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
3043 assert(!(isVarArg && canGuaranteeTCO(CallConv)) &&
3044 "Var args not supported with calling convention fastcc, ghc or hipe");
3046 // Analyze operands of the call, assigning locations to each operand.
3047 SmallVector<CCValAssign, 16> ArgLocs;
3048 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
3050 // Allocate shadow area for Win64
3052 CCInfo.AllocateStack(32, 8);
3054 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3056 // Get a count of how many bytes are to be pushed on the stack.
3057 unsigned NumBytes = CCInfo.getAlignedCallFrameSize();
3059 // This is a sibcall. The memory operands are available in caller's
3060 // own caller's stack.
3062 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
3063 canGuaranteeTCO(CallConv))
3064 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
3067 if (isTailCall && !IsSibcall && !IsMustTail) {
3068 // Lower arguments at fp - stackoffset + fpdiff.
3069 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
3071 FPDiff = NumBytesCallerPushed - NumBytes;
3073 // Set the delta of movement of the returnaddr stackslot.
3074 // But only set if delta is greater than previous delta.
3075 if (FPDiff < X86Info->getTCReturnAddrDelta())
3076 X86Info->setTCReturnAddrDelta(FPDiff);
3079 unsigned NumBytesToPush = NumBytes;
3080 unsigned NumBytesToPop = NumBytes;
3082 // If we have an inalloca argument, all stack space has already been allocated
3083 // for us and be right at the top of the stack. We don't support multiple
3084 // arguments passed in memory when using inalloca.
3085 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
3087 if (!ArgLocs.back().isMemLoc())
3088 report_fatal_error("cannot use inalloca attribute on a register "
3090 if (ArgLocs.back().getLocMemOffset() != 0)
3091 report_fatal_error("any parameter with the inalloca attribute must be "
3092 "the only memory argument");
3096 Chain = DAG.getCALLSEQ_START(
3097 Chain, DAG.getIntPtrConstant(NumBytesToPush, dl, true), dl);
3099 SDValue RetAddrFrIdx;
3100 // Load return address for tail calls.
3101 if (isTailCall && FPDiff)
3102 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
3103 Is64Bit, FPDiff, dl);
3105 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3106 SmallVector<SDValue, 8> MemOpChains;
3109 // Walk the register/memloc assignments, inserting copies/loads. In the case
3110 // of tail call optimization arguments are handle later.
3111 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3112 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3113 // Skip inalloca arguments, they have already been written.
3114 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3115 if (Flags.isInAlloca())
3118 CCValAssign &VA = ArgLocs[i];
3119 EVT RegVT = VA.getLocVT();
3120 SDValue Arg = OutVals[i];
3121 bool isByVal = Flags.isByVal();
3123 // Promote the value if needed.
3124 switch (VA.getLocInfo()) {
3125 default: llvm_unreachable("Unknown loc info!");
3126 case CCValAssign::Full: break;
3127 case CCValAssign::SExt:
3128 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
3130 case CCValAssign::ZExt:
3131 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
3133 case CCValAssign::AExt:
3134 if (Arg.getValueType().isVector() &&
3135 Arg.getValueType().getVectorElementType() == MVT::i1)
3136 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
3137 else if (RegVT.is128BitVector()) {
3138 // Special case: passing MMX values in XMM registers.
3139 Arg = DAG.getBitcast(MVT::i64, Arg);
3140 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
3141 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
3143 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
3145 case CCValAssign::BCvt:
3146 Arg = DAG.getBitcast(RegVT, Arg);
3148 case CCValAssign::Indirect: {
3149 // Store the argument.
3150 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
3151 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
3152 Chain = DAG.getStore(
3153 Chain, dl, Arg, SpillSlot,
3154 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI),
3161 if (VA.isRegLoc()) {
3162 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
3163 if (isVarArg && IsWin64) {
3164 // Win64 ABI requires argument XMM reg to be copied to the corresponding
3165 // shadow reg if callee is a varargs function.
3166 unsigned ShadowReg = 0;
3167 switch (VA.getLocReg()) {
3168 case X86::XMM0: ShadowReg = X86::RCX; break;
3169 case X86::XMM1: ShadowReg = X86::RDX; break;
3170 case X86::XMM2: ShadowReg = X86::R8; break;
3171 case X86::XMM3: ShadowReg = X86::R9; break;
3174 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
3176 } else if (!IsSibcall && (!isTailCall || isByVal)) {
3177 assert(VA.isMemLoc());
3178 if (!StackPtr.getNode())
3179 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
3180 getPointerTy(DAG.getDataLayout()));
3181 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
3182 dl, DAG, VA, Flags));
3186 if (!MemOpChains.empty())
3187 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
3189 if (Subtarget->isPICStyleGOT()) {
3190 // ELF / PIC requires GOT in the EBX register before function calls via PLT
3193 RegsToPass.push_back(std::make_pair(
3194 unsigned(X86::EBX), DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(),
3195 getPointerTy(DAG.getDataLayout()))));
3197 // If we are tail calling and generating PIC/GOT style code load the
3198 // address of the callee into ECX. The value in ecx is used as target of
3199 // the tail jump. This is done to circumvent the ebx/callee-saved problem
3200 // for tail calls on PIC/GOT architectures. Normally we would just put the
3201 // address of GOT into ebx and then call target@PLT. But for tail calls
3202 // ebx would be restored (since ebx is callee saved) before jumping to the
3205 // Note: The actual moving to ECX is done further down.
3206 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
3207 if (G && !G->getGlobal()->hasLocalLinkage() &&
3208 G->getGlobal()->hasDefaultVisibility())
3209 Callee = LowerGlobalAddress(Callee, DAG);
3210 else if (isa<ExternalSymbolSDNode>(Callee))
3211 Callee = LowerExternalSymbol(Callee, DAG);
3215 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
3216 // From AMD64 ABI document:
3217 // For calls that may call functions that use varargs or stdargs
3218 // (prototype-less calls or calls to functions containing ellipsis (...) in
3219 // the declaration) %al is used as hidden argument to specify the number
3220 // of SSE registers used. The contents of %al do not need to match exactly
3221 // the number of registers, but must be an ubound on the number of SSE
3222 // registers used and is in the range 0 - 8 inclusive.
3224 // Count the number of XMM registers allocated.
3225 static const MCPhysReg XMMArgRegs[] = {
3226 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
3227 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
3229 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs);
3230 assert((Subtarget->hasSSE1() || !NumXMMRegs)
3231 && "SSE registers cannot be used when SSE is disabled");
3233 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
3234 DAG.getConstant(NumXMMRegs, dl,
3238 if (isVarArg && IsMustTail) {
3239 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
3240 for (const auto &F : Forwards) {
3241 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
3242 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
3246 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
3247 // don't need this because the eligibility check rejects calls that require
3248 // shuffling arguments passed in memory.
3249 if (!IsSibcall && isTailCall) {
3250 // Force all the incoming stack arguments to be loaded from the stack
3251 // before any new outgoing arguments are stored to the stack, because the
3252 // outgoing stack slots may alias the incoming argument stack slots, and
3253 // the alias isn't otherwise explicit. This is slightly more conservative
3254 // than necessary, because it means that each store effectively depends
3255 // on every argument instead of just those arguments it would clobber.
3256 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
3258 SmallVector<SDValue, 8> MemOpChains2;
3261 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3262 CCValAssign &VA = ArgLocs[i];
3265 assert(VA.isMemLoc());
3266 SDValue Arg = OutVals[i];
3267 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3268 // Skip inalloca arguments. They don't require any work.
3269 if (Flags.isInAlloca())
3271 // Create frame index.
3272 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3273 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3274 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3275 FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
3277 if (Flags.isByVal()) {
3278 // Copy relative to framepointer.
3279 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset(), dl);
3280 if (!StackPtr.getNode())
3281 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
3282 getPointerTy(DAG.getDataLayout()));
3283 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
3286 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3290 // Store relative to framepointer.
3291 MemOpChains2.push_back(DAG.getStore(
3292 ArgChain, dl, Arg, FIN,
3293 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI),
3298 if (!MemOpChains2.empty())
3299 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3301 // Store the return address to the appropriate stack slot.
3302 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3303 getPointerTy(DAG.getDataLayout()),
3304 RegInfo->getSlotSize(), FPDiff, dl);
3307 // Build a sequence of copy-to-reg nodes chained together with token chain
3308 // and flag operands which copy the outgoing args into registers.
3310 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3311 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3312 RegsToPass[i].second, InFlag);
3313 InFlag = Chain.getValue(1);
3316 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3317 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3318 // In the 64-bit large code model, we have to make all calls
3319 // through a register, since the call instruction's 32-bit
3320 // pc-relative offset may not be large enough to hold the whole
3322 } else if (Callee->getOpcode() == ISD::GlobalAddress) {
3323 // If the callee is a GlobalAddress node (quite common, every direct call
3324 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3326 GlobalAddressSDNode* G = cast<GlobalAddressSDNode>(Callee);
3328 // We should use extra load for direct calls to dllimported functions in
3330 const GlobalValue *GV = G->getGlobal();
3331 if (!GV->hasDLLImportStorageClass()) {
3332 unsigned char OpFlags = 0;
3333 bool ExtraLoad = false;
3334 unsigned WrapperKind = ISD::DELETED_NODE;
3336 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3337 // external symbols most go through the PLT in PIC mode. If the symbol
3338 // has hidden or protected visibility, or if it is static or local, then
3339 // we don't need to use the PLT - we can directly call it.
3340 if (Subtarget->isTargetELF() &&
3341 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3342 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3343 OpFlags = X86II::MO_PLT;
3344 } else if (Subtarget->isPICStyleStubAny() &&
3345 !GV->isStrongDefinitionForLinker() &&
3346 (!Subtarget->getTargetTriple().isMacOSX() ||
3347 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3348 // PC-relative references to external symbols should go through $stub,
3349 // unless we're building with the leopard linker or later, which
3350 // automatically synthesizes these stubs.
3351 OpFlags = X86II::MO_DARWIN_STUB;
3352 } else if (Subtarget->isPICStyleRIPRel() && isa<Function>(GV) &&
3353 cast<Function>(GV)->hasFnAttribute(Attribute::NonLazyBind)) {
3354 // If the function is marked as non-lazy, generate an indirect call
3355 // which loads from the GOT directly. This avoids runtime overhead
3356 // at the cost of eager binding (and one extra byte of encoding).
3357 OpFlags = X86II::MO_GOTPCREL;
3358 WrapperKind = X86ISD::WrapperRIP;
3362 Callee = DAG.getTargetGlobalAddress(
3363 GV, dl, getPointerTy(DAG.getDataLayout()), G->getOffset(), OpFlags);
3365 // Add a wrapper if needed.
3366 if (WrapperKind != ISD::DELETED_NODE)
3367 Callee = DAG.getNode(X86ISD::WrapperRIP, dl,
3368 getPointerTy(DAG.getDataLayout()), Callee);
3369 // Add extra indirection if needed.
3371 Callee = DAG.getLoad(
3372 getPointerTy(DAG.getDataLayout()), dl, DAG.getEntryNode(), Callee,
3373 MachinePointerInfo::getGOT(DAG.getMachineFunction()), false, false,
3376 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3377 unsigned char OpFlags = 0;
3379 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3380 // external symbols should go through the PLT.
3381 if (Subtarget->isTargetELF() &&
3382 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3383 OpFlags = X86II::MO_PLT;
3384 } else if (Subtarget->isPICStyleStubAny() &&
3385 (!Subtarget->getTargetTriple().isMacOSX() ||
3386 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3387 // PC-relative references to external symbols should go through $stub,
3388 // unless we're building with the leopard linker or later, which
3389 // automatically synthesizes these stubs.
3390 OpFlags = X86II::MO_DARWIN_STUB;
3393 Callee = DAG.getTargetExternalSymbol(
3394 S->getSymbol(), getPointerTy(DAG.getDataLayout()), OpFlags);
3395 } else if (Subtarget->isTarget64BitILP32() &&
3396 Callee->getValueType(0) == MVT::i32) {
3397 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3398 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3401 // Returns a chain & a flag for retval copy to use.
3402 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3403 SmallVector<SDValue, 8> Ops;
3405 if (!IsSibcall && isTailCall) {
3406 Chain = DAG.getCALLSEQ_END(Chain,
3407 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3408 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
3409 InFlag = Chain.getValue(1);
3412 Ops.push_back(Chain);
3413 Ops.push_back(Callee);
3416 Ops.push_back(DAG.getConstant(FPDiff, dl, MVT::i32));
3418 // Add argument registers to the end of the list so that they are known live
3420 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3421 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3422 RegsToPass[i].second.getValueType()));
3424 // Add a register mask operand representing the call-preserved registers.
3425 const uint32_t *Mask = RegInfo->getCallPreservedMask(MF, CallConv);
3426 assert(Mask && "Missing call preserved mask for calling convention");
3428 // If this is an invoke in a 32-bit function using a funclet-based
3429 // personality, assume the function clobbers all registers. If an exception
3430 // is thrown, the runtime will not restore CSRs.
3431 // FIXME: Model this more precisely so that we can register allocate across
3432 // the normal edge and spill and fill across the exceptional edge.
3433 if (!Is64Bit && CLI.CS && CLI.CS->isInvoke()) {
3434 const Function *CallerFn = MF.getFunction();
3435 EHPersonality Pers =
3436 CallerFn->hasPersonalityFn()
3437 ? classifyEHPersonality(CallerFn->getPersonalityFn())
3438 : EHPersonality::Unknown;
3439 if (isFuncletEHPersonality(Pers))
3440 Mask = RegInfo->getNoPreservedMask();
3443 Ops.push_back(DAG.getRegisterMask(Mask));
3445 if (InFlag.getNode())
3446 Ops.push_back(InFlag);
3450 //// If this is the first return lowered for this function, add the regs
3451 //// to the liveout set for the function.
3452 // This isn't right, although it's probably harmless on x86; liveouts
3453 // should be computed from returns not tail calls. Consider a void
3454 // function making a tail call to a function returning int.
3455 MF.getFrameInfo()->setHasTailCall();
3456 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3459 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3460 InFlag = Chain.getValue(1);
3462 // Create the CALLSEQ_END node.
3463 unsigned NumBytesForCalleeToPop;
3464 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3465 DAG.getTarget().Options.GuaranteedTailCallOpt))
3466 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3467 else if (!Is64Bit && !canGuaranteeTCO(CallConv) &&
3468 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3469 SR == StackStructReturn)
3470 // If this is a call to a struct-return function, the callee
3471 // pops the hidden struct pointer, so we have to push it back.
3472 // This is common for Darwin/X86, Linux & Mingw32 targets.
3473 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3474 NumBytesForCalleeToPop = 4;
3476 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3478 // Returns a flag for retval copy to use.
3480 Chain = DAG.getCALLSEQ_END(Chain,
3481 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3482 DAG.getIntPtrConstant(NumBytesForCalleeToPop, dl,
3485 InFlag = Chain.getValue(1);
3488 // Handle result values, copying them out of physregs into vregs that we
3490 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3491 Ins, dl, DAG, InVals);
3494 //===----------------------------------------------------------------------===//
3495 // Fast Calling Convention (tail call) implementation
3496 //===----------------------------------------------------------------------===//
3498 // Like std call, callee cleans arguments, convention except that ECX is
3499 // reserved for storing the tail called function address. Only 2 registers are
3500 // free for argument passing (inreg). Tail call optimization is performed
3502 // * tailcallopt is enabled
3503 // * caller/callee are fastcc
3504 // On X86_64 architecture with GOT-style position independent code only local
3505 // (within module) calls are supported at the moment.
3506 // To keep the stack aligned according to platform abi the function
3507 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3508 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3509 // If a tail called function callee has more arguments than the caller the
3510 // caller needs to make sure that there is room to move the RETADDR to. This is
3511 // achieved by reserving an area the size of the argument delta right after the
3512 // original RETADDR, but before the saved framepointer or the spilled registers
3513 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3525 /// Make the stack size align e.g 16n + 12 aligned for a 16-byte align
3528 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3529 SelectionDAG& DAG) const {
3530 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3531 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
3532 unsigned StackAlignment = TFI.getStackAlignment();
3533 uint64_t AlignMask = StackAlignment - 1;
3534 int64_t Offset = StackSize;
3535 unsigned SlotSize = RegInfo->getSlotSize();
3536 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3537 // Number smaller than 12 so just add the difference.
3538 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3540 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3541 Offset = ((~AlignMask) & Offset) + StackAlignment +
3542 (StackAlignment-SlotSize);
3547 /// Return true if the given stack call argument is already available in the
3548 /// same position (relatively) of the caller's incoming argument stack.
3550 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3551 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3552 const X86InstrInfo *TII) {
3553 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3555 if (Arg.getOpcode() == ISD::CopyFromReg) {
3556 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3557 if (!TargetRegisterInfo::isVirtualRegister(VR))
3559 MachineInstr *Def = MRI->getVRegDef(VR);
3562 if (!Flags.isByVal()) {
3563 if (!TII->isLoadFromStackSlot(Def, FI))
3566 unsigned Opcode = Def->getOpcode();
3567 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r ||
3568 Opcode == X86::LEA64_32r) &&
3569 Def->getOperand(1).isFI()) {
3570 FI = Def->getOperand(1).getIndex();
3571 Bytes = Flags.getByValSize();
3575 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3576 if (Flags.isByVal())
3577 // ByVal argument is passed in as a pointer but it's now being
3578 // dereferenced. e.g.
3579 // define @foo(%struct.X* %A) {
3580 // tail call @bar(%struct.X* byval %A)
3583 SDValue Ptr = Ld->getBasePtr();
3584 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3587 FI = FINode->getIndex();
3588 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3589 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3590 FI = FINode->getIndex();
3591 Bytes = Flags.getByValSize();
3595 assert(FI != INT_MAX);
3596 if (!MFI->isFixedObjectIndex(FI))
3598 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3601 /// Check whether the call is eligible for tail call optimization. Targets
3602 /// that want to do tail call optimization should implement this function.
3603 bool X86TargetLowering::IsEligibleForTailCallOptimization(
3604 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
3605 bool isCalleeStructRet, bool isCallerStructRet, Type *RetTy,
3606 const SmallVectorImpl<ISD::OutputArg> &Outs,
3607 const SmallVectorImpl<SDValue> &OutVals,
3608 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const {
3609 if (!mayTailCallThisCC(CalleeCC))
3612 // If -tailcallopt is specified, make fastcc functions tail-callable.
3613 MachineFunction &MF = DAG.getMachineFunction();
3614 const Function *CallerF = MF.getFunction();
3616 // If the function return type is x86_fp80 and the callee return type is not,
3617 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3618 // perform a tailcall optimization here.
3619 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3622 CallingConv::ID CallerCC = CallerF->getCallingConv();
3623 bool CCMatch = CallerCC == CalleeCC;
3624 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3625 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3627 // Win64 functions have extra shadow space for argument homing. Don't do the
3628 // sibcall if the caller and callee have mismatched expectations for this
3630 if (IsCalleeWin64 != IsCallerWin64)
3633 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3634 if (canGuaranteeTCO(CalleeCC) && CCMatch)
3639 // Look for obvious safe cases to perform tail call optimization that do not
3640 // require ABI changes. This is what gcc calls sibcall.
3642 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3643 // emit a special epilogue.
3644 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3645 if (RegInfo->needsStackRealignment(MF))
3648 // Also avoid sibcall optimization if either caller or callee uses struct
3649 // return semantics.
3650 if (isCalleeStructRet || isCallerStructRet)
3653 // Do not sibcall optimize vararg calls unless all arguments are passed via
3655 if (isVarArg && !Outs.empty()) {
3656 // Optimizing for varargs on Win64 is unlikely to be safe without
3657 // additional testing.
3658 if (IsCalleeWin64 || IsCallerWin64)
3661 SmallVector<CCValAssign, 16> ArgLocs;
3662 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3665 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3666 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3667 if (!ArgLocs[i].isRegLoc())
3671 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3672 // stack. Therefore, if it's not used by the call it is not safe to optimize
3673 // this into a sibcall.
3674 bool Unused = false;
3675 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3682 SmallVector<CCValAssign, 16> RVLocs;
3683 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3685 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3686 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3687 CCValAssign &VA = RVLocs[i];
3688 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3693 // If the calling conventions do not match, then we'd better make sure the
3694 // results are returned in the same way as what the caller expects.
3696 SmallVector<CCValAssign, 16> RVLocs1;
3697 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3699 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3701 SmallVector<CCValAssign, 16> RVLocs2;
3702 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3704 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3706 if (RVLocs1.size() != RVLocs2.size())
3708 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3709 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3711 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3713 if (RVLocs1[i].isRegLoc()) {
3714 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3717 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3723 unsigned StackArgsSize = 0;
3725 // If the callee takes no arguments then go on to check the results of the
3727 if (!Outs.empty()) {
3728 // Check if stack adjustment is needed. For now, do not do this if any
3729 // argument is passed on the stack.
3730 SmallVector<CCValAssign, 16> ArgLocs;
3731 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3734 // Allocate shadow area for Win64
3736 CCInfo.AllocateStack(32, 8);
3738 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3739 StackArgsSize = CCInfo.getNextStackOffset();
3741 if (CCInfo.getNextStackOffset()) {
3742 // Check if the arguments are already laid out in the right way as
3743 // the caller's fixed stack objects.
3744 MachineFrameInfo *MFI = MF.getFrameInfo();
3745 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3746 const X86InstrInfo *TII = Subtarget->getInstrInfo();
3747 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3748 CCValAssign &VA = ArgLocs[i];
3749 SDValue Arg = OutVals[i];
3750 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3751 if (VA.getLocInfo() == CCValAssign::Indirect)
3753 if (!VA.isRegLoc()) {
3754 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3761 // If the tailcall address may be in a register, then make sure it's
3762 // possible to register allocate for it. In 32-bit, the call address can
3763 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3764 // callee-saved registers are restored. These happen to be the same
3765 // registers used to pass 'inreg' arguments so watch out for those.
3766 if (!Subtarget->is64Bit() &&
3767 ((!isa<GlobalAddressSDNode>(Callee) &&
3768 !isa<ExternalSymbolSDNode>(Callee)) ||
3769 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3770 unsigned NumInRegs = 0;
3771 // In PIC we need an extra register to formulate the address computation
3773 unsigned MaxInRegs =
3774 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3776 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3777 CCValAssign &VA = ArgLocs[i];
3780 unsigned Reg = VA.getLocReg();
3783 case X86::EAX: case X86::EDX: case X86::ECX:
3784 if (++NumInRegs == MaxInRegs)
3792 bool CalleeWillPop =
3793 X86::isCalleePop(CalleeCC, Subtarget->is64Bit(), isVarArg,
3794 MF.getTarget().Options.GuaranteedTailCallOpt);
3796 if (unsigned BytesToPop =
3797 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn()) {
3798 // If we have bytes to pop, the callee must pop them.
3799 bool CalleePopMatches = CalleeWillPop && BytesToPop == StackArgsSize;
3800 if (!CalleePopMatches)
3802 } else if (CalleeWillPop && StackArgsSize > 0) {
3803 // If we don't have bytes to pop, make sure the callee doesn't pop any.
3811 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3812 const TargetLibraryInfo *libInfo) const {
3813 return X86::createFastISel(funcInfo, libInfo);
3816 //===----------------------------------------------------------------------===//
3817 // Other Lowering Hooks
3818 //===----------------------------------------------------------------------===//
3820 static bool MayFoldLoad(SDValue Op) {
3821 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3824 static bool MayFoldIntoStore(SDValue Op) {
3825 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3828 static bool isTargetShuffle(unsigned Opcode) {
3830 default: return false;
3831 case X86ISD::BLENDI:
3832 case X86ISD::PSHUFB:
3833 case X86ISD::PSHUFD:
3834 case X86ISD::PSHUFHW:
3835 case X86ISD::PSHUFLW:
3837 case X86ISD::PALIGNR:
3838 case X86ISD::MOVLHPS:
3839 case X86ISD::MOVLHPD:
3840 case X86ISD::MOVHLPS:
3841 case X86ISD::MOVLPS:
3842 case X86ISD::MOVLPD:
3843 case X86ISD::MOVSHDUP:
3844 case X86ISD::MOVSLDUP:
3845 case X86ISD::MOVDDUP:
3848 case X86ISD::UNPCKL:
3849 case X86ISD::UNPCKH:
3850 case X86ISD::VPERMILPI:
3851 case X86ISD::VPERM2X128:
3852 case X86ISD::VPERMI:
3853 case X86ISD::VPERMV:
3854 case X86ISD::VPERMV3:
3859 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, MVT VT,
3860 SDValue V1, unsigned TargetMask,
3861 SelectionDAG &DAG) {
3863 default: llvm_unreachable("Unknown x86 shuffle node");
3864 case X86ISD::PSHUFD:
3865 case X86ISD::PSHUFHW:
3866 case X86ISD::PSHUFLW:
3867 case X86ISD::VPERMILPI:
3868 case X86ISD::VPERMI:
3869 return DAG.getNode(Opc, dl, VT, V1,
3870 DAG.getConstant(TargetMask, dl, MVT::i8));
3874 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, MVT VT,
3875 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3877 default: llvm_unreachable("Unknown x86 shuffle node");
3878 case X86ISD::MOVLHPS:
3879 case X86ISD::MOVLHPD:
3880 case X86ISD::MOVHLPS:
3881 case X86ISD::MOVLPS:
3882 case X86ISD::MOVLPD:
3885 case X86ISD::UNPCKL:
3886 case X86ISD::UNPCKH:
3887 return DAG.getNode(Opc, dl, VT, V1, V2);
3891 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3892 MachineFunction &MF = DAG.getMachineFunction();
3893 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3894 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3895 int ReturnAddrIndex = FuncInfo->getRAIndex();
3897 if (ReturnAddrIndex == 0) {
3898 // Set up a frame object for the return address.
3899 unsigned SlotSize = RegInfo->getSlotSize();
3900 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3903 FuncInfo->setRAIndex(ReturnAddrIndex);
3906 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy(DAG.getDataLayout()));
3909 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3910 bool hasSymbolicDisplacement) {
3911 // Offset should fit into 32 bit immediate field.
3912 if (!isInt<32>(Offset))
3915 // If we don't have a symbolic displacement - we don't have any extra
3917 if (!hasSymbolicDisplacement)
3920 // FIXME: Some tweaks might be needed for medium code model.
3921 if (M != CodeModel::Small && M != CodeModel::Kernel)
3924 // For small code model we assume that latest object is 16MB before end of 31
3925 // bits boundary. We may also accept pretty large negative constants knowing
3926 // that all objects are in the positive half of address space.
3927 if (M == CodeModel::Small && Offset < 16*1024*1024)
3930 // For kernel code model we know that all object resist in the negative half
3931 // of 32bits address space. We may not accept negative offsets, since they may
3932 // be just off and we may accept pretty large positive ones.
3933 if (M == CodeModel::Kernel && Offset >= 0)
3939 /// Determines whether the callee is required to pop its own arguments.
3940 /// Callee pop is necessary to support tail calls.
3941 bool X86::isCalleePop(CallingConv::ID CallingConv,
3942 bool is64Bit, bool IsVarArg, bool GuaranteeTCO) {
3943 // If GuaranteeTCO is true, we force some calls to be callee pop so that we
3944 // can guarantee TCO.
3945 if (!IsVarArg && shouldGuaranteeTCO(CallingConv, GuaranteeTCO))
3948 switch (CallingConv) {
3951 case CallingConv::X86_StdCall:
3952 case CallingConv::X86_FastCall:
3953 case CallingConv::X86_ThisCall:
3954 case CallingConv::X86_VectorCall:
3959 /// \brief Return true if the condition is an unsigned comparison operation.
3960 static bool isX86CCUnsigned(unsigned X86CC) {
3962 default: llvm_unreachable("Invalid integer condition!");
3963 case X86::COND_E: return true;
3964 case X86::COND_G: return false;
3965 case X86::COND_GE: return false;
3966 case X86::COND_L: return false;
3967 case X86::COND_LE: return false;
3968 case X86::COND_NE: return true;
3969 case X86::COND_B: return true;
3970 case X86::COND_A: return true;
3971 case X86::COND_BE: return true;
3972 case X86::COND_AE: return true;
3976 static X86::CondCode TranslateIntegerX86CC(ISD::CondCode SetCCOpcode) {
3977 switch (SetCCOpcode) {
3978 default: llvm_unreachable("Invalid integer condition!");
3979 case ISD::SETEQ: return X86::COND_E;
3980 case ISD::SETGT: return X86::COND_G;
3981 case ISD::SETGE: return X86::COND_GE;
3982 case ISD::SETLT: return X86::COND_L;
3983 case ISD::SETLE: return X86::COND_LE;
3984 case ISD::SETNE: return X86::COND_NE;
3985 case ISD::SETULT: return X86::COND_B;
3986 case ISD::SETUGT: return X86::COND_A;
3987 case ISD::SETULE: return X86::COND_BE;
3988 case ISD::SETUGE: return X86::COND_AE;
3992 /// Do a one-to-one translation of a ISD::CondCode to the X86-specific
3993 /// condition code, returning the condition code and the LHS/RHS of the
3994 /// comparison to make.
3995 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, SDLoc DL, bool isFP,
3996 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3998 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3999 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
4000 // X > -1 -> X == 0, jump !sign.
4001 RHS = DAG.getConstant(0, DL, RHS.getValueType());
4002 return X86::COND_NS;
4004 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
4005 // X < 0 -> X == 0, jump on sign.
4008 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
4010 RHS = DAG.getConstant(0, DL, RHS.getValueType());
4011 return X86::COND_LE;
4015 return TranslateIntegerX86CC(SetCCOpcode);
4018 // First determine if it is required or is profitable to flip the operands.
4020 // If LHS is a foldable load, but RHS is not, flip the condition.
4021 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
4022 !ISD::isNON_EXTLoad(RHS.getNode())) {
4023 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
4024 std::swap(LHS, RHS);
4027 switch (SetCCOpcode) {
4033 std::swap(LHS, RHS);
4037 // On a floating point condition, the flags are set as follows:
4039 // 0 | 0 | 0 | X > Y
4040 // 0 | 0 | 1 | X < Y
4041 // 1 | 0 | 0 | X == Y
4042 // 1 | 1 | 1 | unordered
4043 switch (SetCCOpcode) {
4044 default: llvm_unreachable("Condcode should be pre-legalized away");
4046 case ISD::SETEQ: return X86::COND_E;
4047 case ISD::SETOLT: // flipped
4049 case ISD::SETGT: return X86::COND_A;
4050 case ISD::SETOLE: // flipped
4052 case ISD::SETGE: return X86::COND_AE;
4053 case ISD::SETUGT: // flipped
4055 case ISD::SETLT: return X86::COND_B;
4056 case ISD::SETUGE: // flipped
4058 case ISD::SETLE: return X86::COND_BE;
4060 case ISD::SETNE: return X86::COND_NE;
4061 case ISD::SETUO: return X86::COND_P;
4062 case ISD::SETO: return X86::COND_NP;
4064 case ISD::SETUNE: return X86::COND_INVALID;
4068 /// Is there a floating point cmov for the specific X86 condition code?
4069 /// Current x86 isa includes the following FP cmov instructions:
4070 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
4071 static bool hasFPCMov(unsigned X86CC) {
4087 /// Returns true if the target can instruction select the
4088 /// specified FP immediate natively. If false, the legalizer will
4089 /// materialize the FP immediate as a load from a constant pool.
4090 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
4091 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
4092 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
4098 bool X86TargetLowering::shouldReduceLoadWidth(SDNode *Load,
4099 ISD::LoadExtType ExtTy,
4101 // "ELF Handling for Thread-Local Storage" specifies that R_X86_64_GOTTPOFF
4102 // relocation target a movq or addq instruction: don't let the load shrink.
4103 SDValue BasePtr = cast<LoadSDNode>(Load)->getBasePtr();
4104 if (BasePtr.getOpcode() == X86ISD::WrapperRIP)
4105 if (const auto *GA = dyn_cast<GlobalAddressSDNode>(BasePtr.getOperand(0)))
4106 return GA->getTargetFlags() != X86II::MO_GOTTPOFF;
4110 /// \brief Returns true if it is beneficial to convert a load of a constant
4111 /// to just the constant itself.
4112 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
4114 assert(Ty->isIntegerTy());
4116 unsigned BitSize = Ty->getPrimitiveSizeInBits();
4117 if (BitSize == 0 || BitSize > 64)
4122 bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT,
4123 unsigned Index) const {
4124 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
4127 return (Index == 0 || Index == ResVT.getVectorNumElements());
4130 bool X86TargetLowering::isCheapToSpeculateCttz() const {
4131 // Speculate cttz only if we can directly use TZCNT.
4132 return Subtarget->hasBMI();
4135 bool X86TargetLowering::isCheapToSpeculateCtlz() const {
4136 // Speculate ctlz only if we can directly use LZCNT.
4137 return Subtarget->hasLZCNT();
4140 /// Return true if every element in Mask, beginning
4141 /// from position Pos and ending in Pos+Size is undef.
4142 static bool isUndefInRange(ArrayRef<int> Mask, unsigned Pos, unsigned Size) {
4143 for (unsigned i = Pos, e = Pos + Size; i != e; ++i)
4149 /// Return true if Val is undef or if its value falls within the
4150 /// specified range (L, H].
4151 static bool isUndefOrInRange(int Val, int Low, int Hi) {
4152 return (Val < 0) || (Val >= Low && Val < Hi);
4155 /// Val is either less than zero (undef) or equal to the specified value.
4156 static bool isUndefOrEqual(int Val, int CmpVal) {
4157 return (Val < 0 || Val == CmpVal);
4160 /// Return true if every element in Mask, beginning
4161 /// from position Pos and ending in Pos+Size, falls within the specified
4162 /// sequential range (Low, Low+Size]. or is undef.
4163 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
4164 unsigned Pos, unsigned Size, int Low) {
4165 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
4166 if (!isUndefOrEqual(Mask[i], Low))
4171 /// Return true if the specified EXTRACT_SUBVECTOR operand specifies a vector
4172 /// extract that is suitable for instruction that extract 128 or 256 bit vectors
4173 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4174 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4175 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4178 // The index should be aligned on a vecWidth-bit boundary.
4180 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4182 MVT VT = N->getSimpleValueType(0);
4183 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4184 bool Result = (Index * ElSize) % vecWidth == 0;
4189 /// Return true if the specified INSERT_SUBVECTOR
4190 /// operand specifies a subvector insert that is suitable for input to
4191 /// insertion of 128 or 256-bit subvectors
4192 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4193 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4194 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4196 // The index should be aligned on a vecWidth-bit boundary.
4198 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4200 MVT VT = N->getSimpleValueType(0);
4201 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4202 bool Result = (Index * ElSize) % vecWidth == 0;
4207 bool X86::isVINSERT128Index(SDNode *N) {
4208 return isVINSERTIndex(N, 128);
4211 bool X86::isVINSERT256Index(SDNode *N) {
4212 return isVINSERTIndex(N, 256);
4215 bool X86::isVEXTRACT128Index(SDNode *N) {
4216 return isVEXTRACTIndex(N, 128);
4219 bool X86::isVEXTRACT256Index(SDNode *N) {
4220 return isVEXTRACTIndex(N, 256);
4223 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4224 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4225 assert(isa<ConstantSDNode>(N->getOperand(1).getNode()) &&
4226 "Illegal extract subvector for VEXTRACT");
4229 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4231 MVT VecVT = N->getOperand(0).getSimpleValueType();
4232 MVT ElVT = VecVT.getVectorElementType();
4234 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4235 return Index / NumElemsPerChunk;
4238 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4239 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4240 assert(isa<ConstantSDNode>(N->getOperand(2).getNode()) &&
4241 "Illegal insert subvector for VINSERT");
4244 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4246 MVT VecVT = N->getSimpleValueType(0);
4247 MVT ElVT = VecVT.getVectorElementType();
4249 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4250 return Index / NumElemsPerChunk;
4253 /// Return the appropriate immediate to extract the specified
4254 /// EXTRACT_SUBVECTOR index with VEXTRACTF128 and VINSERTI128 instructions.
4255 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4256 return getExtractVEXTRACTImmediate(N, 128);
4259 /// Return the appropriate immediate to extract the specified
4260 /// EXTRACT_SUBVECTOR index with VEXTRACTF64x4 and VINSERTI64x4 instructions.
4261 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4262 return getExtractVEXTRACTImmediate(N, 256);
4265 /// Return the appropriate immediate to insert at the specified
4266 /// INSERT_SUBVECTOR index with VINSERTF128 and VINSERTI128 instructions.
4267 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4268 return getInsertVINSERTImmediate(N, 128);
4271 /// Return the appropriate immediate to insert at the specified
4272 /// INSERT_SUBVECTOR index with VINSERTF46x4 and VINSERTI64x4 instructions.
4273 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4274 return getInsertVINSERTImmediate(N, 256);
4277 /// Returns true if Elt is a constant zero or a floating point constant +0.0.
4278 bool X86::isZeroNode(SDValue Elt) {
4279 return isNullConstant(Elt) || isNullFPConstant(Elt);
4282 // Build a vector of constants
4283 // Use an UNDEF node if MaskElt == -1.
4284 // Spilt 64-bit constants in the 32-bit mode.
4285 static SDValue getConstVector(ArrayRef<int> Values, MVT VT,
4287 SDLoc dl, bool IsMask = false) {
4289 SmallVector<SDValue, 32> Ops;
4292 MVT ConstVecVT = VT;
4293 unsigned NumElts = VT.getVectorNumElements();
4294 bool In64BitMode = DAG.getTargetLoweringInfo().isTypeLegal(MVT::i64);
4295 if (!In64BitMode && VT.getVectorElementType() == MVT::i64) {
4296 ConstVecVT = MVT::getVectorVT(MVT::i32, NumElts * 2);
4300 MVT EltVT = ConstVecVT.getVectorElementType();
4301 for (unsigned i = 0; i < NumElts; ++i) {
4302 bool IsUndef = Values[i] < 0 && IsMask;
4303 SDValue OpNode = IsUndef ? DAG.getUNDEF(EltVT) :
4304 DAG.getConstant(Values[i], dl, EltVT);
4305 Ops.push_back(OpNode);
4307 Ops.push_back(IsUndef ? DAG.getUNDEF(EltVT) :
4308 DAG.getConstant(0, dl, EltVT));
4310 SDValue ConstsNode = DAG.getNode(ISD::BUILD_VECTOR, dl, ConstVecVT, Ops);
4312 ConstsNode = DAG.getBitcast(VT, ConstsNode);
4316 /// Returns a vector of specified type with all zero elements.
4317 static SDValue getZeroVector(MVT VT, const X86Subtarget *Subtarget,
4318 SelectionDAG &DAG, SDLoc dl) {
4319 assert(VT.isVector() && "Expected a vector type");
4321 // Always build SSE zero vectors as <4 x i32> bitcasted
4322 // to their dest type. This ensures they get CSE'd.
4324 if (VT.is128BitVector()) { // SSE
4325 if (Subtarget->hasSSE2()) { // SSE2
4326 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4327 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4329 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
4330 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4332 } else if (VT.is256BitVector()) { // AVX
4333 if (Subtarget->hasInt256()) { // AVX2
4334 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4335 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4336 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4338 // 256-bit logic and arithmetic instructions in AVX are all
4339 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4340 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
4341 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4342 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
4344 } else if (VT.is512BitVector()) { // AVX-512
4345 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4346 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4347 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4348 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
4349 } else if (VT.getVectorElementType() == MVT::i1) {
4351 assert((Subtarget->hasBWI() || VT.getVectorNumElements() <= 16)
4352 && "Unexpected vector type");
4353 assert((Subtarget->hasVLX() || VT.getVectorNumElements() >= 8)
4354 && "Unexpected vector type");
4355 SDValue Cst = DAG.getConstant(0, dl, MVT::i1);
4356 SmallVector<SDValue, 64> Ops(VT.getVectorNumElements(), Cst);
4357 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
4359 llvm_unreachable("Unexpected vector type");
4361 return DAG.getBitcast(VT, Vec);
4364 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
4365 SelectionDAG &DAG, SDLoc dl,
4366 unsigned vectorWidth) {
4367 assert((vectorWidth == 128 || vectorWidth == 256) &&
4368 "Unsupported vector width");
4369 EVT VT = Vec.getValueType();
4370 EVT ElVT = VT.getVectorElementType();
4371 unsigned Factor = VT.getSizeInBits()/vectorWidth;
4372 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
4373 VT.getVectorNumElements()/Factor);
4375 // Extract from UNDEF is UNDEF.
4376 if (Vec.getOpcode() == ISD::UNDEF)
4377 return DAG.getUNDEF(ResultVT);
4379 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
4380 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
4381 assert(isPowerOf2_32(ElemsPerChunk) && "Elements per chunk not power of 2");
4383 // This is the index of the first element of the vectorWidth-bit chunk
4384 // we want. Since ElemsPerChunk is a power of 2 just need to clear bits.
4385 IdxVal &= ~(ElemsPerChunk - 1);
4387 // If the input is a buildvector just emit a smaller one.
4388 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
4389 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
4390 makeArrayRef(Vec->op_begin() + IdxVal, ElemsPerChunk));
4392 SDValue VecIdx = DAG.getIntPtrConstant(IdxVal, dl);
4393 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, VecIdx);
4396 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
4397 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
4398 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
4399 /// instructions or a simple subregister reference. Idx is an index in the
4400 /// 128 bits we want. It need not be aligned to a 128-bit boundary. That makes
4401 /// lowering EXTRACT_VECTOR_ELT operations easier.
4402 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
4403 SelectionDAG &DAG, SDLoc dl) {
4404 assert((Vec.getValueType().is256BitVector() ||
4405 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
4406 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
4409 /// Generate a DAG to grab 256-bits from a 512-bit vector.
4410 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
4411 SelectionDAG &DAG, SDLoc dl) {
4412 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
4413 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
4416 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
4417 unsigned IdxVal, SelectionDAG &DAG,
4418 SDLoc dl, unsigned vectorWidth) {
4419 assert((vectorWidth == 128 || vectorWidth == 256) &&
4420 "Unsupported vector width");
4421 // Inserting UNDEF is Result
4422 if (Vec.getOpcode() == ISD::UNDEF)
4424 EVT VT = Vec.getValueType();
4425 EVT ElVT = VT.getVectorElementType();
4426 EVT ResultVT = Result.getValueType();
4428 // Insert the relevant vectorWidth bits.
4429 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
4430 assert(isPowerOf2_32(ElemsPerChunk) && "Elements per chunk not power of 2");
4432 // This is the index of the first element of the vectorWidth-bit chunk
4433 // we want. Since ElemsPerChunk is a power of 2 just need to clear bits.
4434 IdxVal &= ~(ElemsPerChunk - 1);
4436 SDValue VecIdx = DAG.getIntPtrConstant(IdxVal, dl);
4437 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, VecIdx);
4440 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
4441 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
4442 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
4443 /// simple superregister reference. Idx is an index in the 128 bits
4444 /// we want. It need not be aligned to a 128-bit boundary. That makes
4445 /// lowering INSERT_VECTOR_ELT operations easier.
4446 static SDValue Insert128BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4447 SelectionDAG &DAG, SDLoc dl) {
4448 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
4450 // For insertion into the zero index (low half) of a 256-bit vector, it is
4451 // more efficient to generate a blend with immediate instead of an insert*128.
4452 // We are still creating an INSERT_SUBVECTOR below with an undef node to
4453 // extend the subvector to the size of the result vector. Make sure that
4454 // we are not recursing on that node by checking for undef here.
4455 if (IdxVal == 0 && Result.getValueType().is256BitVector() &&
4456 Result.getOpcode() != ISD::UNDEF) {
4457 EVT ResultVT = Result.getValueType();
4458 SDValue ZeroIndex = DAG.getIntPtrConstant(0, dl);
4459 SDValue Undef = DAG.getUNDEF(ResultVT);
4460 SDValue Vec256 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Undef,
4463 // The blend instruction, and therefore its mask, depend on the data type.
4464 MVT ScalarType = ResultVT.getVectorElementType().getSimpleVT();
4465 if (ScalarType.isFloatingPoint()) {
4466 // Choose either vblendps (float) or vblendpd (double).
4467 unsigned ScalarSize = ScalarType.getSizeInBits();
4468 assert((ScalarSize == 64 || ScalarSize == 32) && "Unknown float type");
4469 unsigned MaskVal = (ScalarSize == 64) ? 0x03 : 0x0f;
4470 SDValue Mask = DAG.getConstant(MaskVal, dl, MVT::i8);
4471 return DAG.getNode(X86ISD::BLENDI, dl, ResultVT, Result, Vec256, Mask);
4474 const X86Subtarget &Subtarget =
4475 static_cast<const X86Subtarget &>(DAG.getSubtarget());
4477 // AVX2 is needed for 256-bit integer blend support.
4478 // Integers must be cast to 32-bit because there is only vpblendd;
4479 // vpblendw can't be used for this because it has a handicapped mask.
4481 // If we don't have AVX2, then cast to float. Using a wrong domain blend
4482 // is still more efficient than using the wrong domain vinsertf128 that
4483 // will be created by InsertSubVector().
4484 MVT CastVT = Subtarget.hasAVX2() ? MVT::v8i32 : MVT::v8f32;
4486 SDValue Mask = DAG.getConstant(0x0f, dl, MVT::i8);
4487 Vec256 = DAG.getBitcast(CastVT, Vec256);
4488 Vec256 = DAG.getNode(X86ISD::BLENDI, dl, CastVT, Result, Vec256, Mask);
4489 return DAG.getBitcast(ResultVT, Vec256);
4492 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
4495 static SDValue Insert256BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4496 SelectionDAG &DAG, SDLoc dl) {
4497 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
4498 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
4501 /// Insert i1-subvector to i1-vector.
4502 static SDValue Insert1BitVector(SDValue Op, SelectionDAG &DAG) {
4505 SDValue Vec = Op.getOperand(0);
4506 SDValue SubVec = Op.getOperand(1);
4507 SDValue Idx = Op.getOperand(2);
4509 if (!isa<ConstantSDNode>(Idx))
4512 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
4513 if (IdxVal == 0 && Vec.isUndef()) // the operation is legal
4516 MVT OpVT = Op.getSimpleValueType();
4517 MVT SubVecVT = SubVec.getSimpleValueType();
4518 unsigned NumElems = OpVT.getVectorNumElements();
4519 unsigned SubVecNumElems = SubVecVT.getVectorNumElements();
4521 assert(IdxVal + SubVecNumElems <= NumElems &&
4522 IdxVal % SubVecVT.getSizeInBits() == 0 &&
4523 "Unexpected index value in INSERT_SUBVECTOR");
4525 // There are 3 possible cases:
4526 // 1. Subvector should be inserted in the lower part (IdxVal == 0)
4527 // 2. Subvector should be inserted in the upper part
4528 // (IdxVal + SubVecNumElems == NumElems)
4529 // 3. Subvector should be inserted in the middle (for example v2i1
4530 // to v16i1, index 2)
4532 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
4533 SDValue Undef = DAG.getUNDEF(OpVT);
4534 SDValue WideSubVec =
4535 DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef, SubVec, ZeroIdx);
4537 return DAG.getNode(X86ISD::VSHLI, dl, OpVT, WideSubVec,
4538 DAG.getConstant(IdxVal, dl, MVT::i8));
4540 if (ISD::isBuildVectorAllZeros(Vec.getNode())) {
4541 unsigned ShiftLeft = NumElems - SubVecNumElems;
4542 unsigned ShiftRight = NumElems - SubVecNumElems - IdxVal;
4543 WideSubVec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, WideSubVec,
4544 DAG.getConstant(ShiftLeft, dl, MVT::i8));
4545 return ShiftRight ? DAG.getNode(X86ISD::VSRLI, dl, OpVT, WideSubVec,
4546 DAG.getConstant(ShiftRight, dl, MVT::i8)) : WideSubVec;
4550 // Zero lower bits of the Vec
4551 SDValue ShiftBits = DAG.getConstant(SubVecNumElems, dl, MVT::i8);
4552 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
4553 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
4554 // Merge them together
4555 return DAG.getNode(ISD::OR, dl, OpVT, Vec, WideSubVec);
4558 // Simple case when we put subvector in the upper part
4559 if (IdxVal + SubVecNumElems == NumElems) {
4560 // Zero upper bits of the Vec
4561 WideSubVec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec,
4562 DAG.getConstant(IdxVal, dl, MVT::i8));
4563 SDValue ShiftBits = DAG.getConstant(SubVecNumElems, dl, MVT::i8);
4564 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
4565 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
4566 return DAG.getNode(ISD::OR, dl, OpVT, Vec, WideSubVec);
4568 // Subvector should be inserted in the middle - use shuffle
4569 SmallVector<int, 64> Mask;
4570 for (unsigned i = 0; i < NumElems; ++i)
4571 Mask.push_back(i >= IdxVal && i < IdxVal + SubVecNumElems ?
4573 return DAG.getVectorShuffle(OpVT, dl, WideSubVec, Vec, Mask);
4576 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
4577 /// instructions. This is used because creating CONCAT_VECTOR nodes of
4578 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
4579 /// large BUILD_VECTORS.
4580 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
4581 unsigned NumElems, SelectionDAG &DAG,
4583 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4584 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
4587 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
4588 unsigned NumElems, SelectionDAG &DAG,
4590 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4591 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
4594 /// Returns a vector of specified type with all bits set.
4595 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4596 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4597 /// Then bitcast to their original type, ensuring they get CSE'd.
4598 static SDValue getOnesVector(EVT VT, const X86Subtarget *Subtarget,
4599 SelectionDAG &DAG, SDLoc dl) {
4600 assert(VT.isVector() && "Expected a vector type");
4602 SDValue Cst = DAG.getConstant(~0U, dl, MVT::i32);
4604 if (VT.is512BitVector()) {
4605 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4606 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4607 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
4608 } else if (VT.is256BitVector()) {
4609 if (Subtarget->hasInt256()) { // AVX2
4610 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4611 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4613 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4614 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4616 } else if (VT.is128BitVector()) {
4617 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4619 llvm_unreachable("Unexpected vector type");
4621 return DAG.getBitcast(VT, Vec);
4624 /// Returns a vector_shuffle node for an unpackl operation.
4625 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4627 unsigned NumElems = VT.getVectorNumElements();
4628 SmallVector<int, 8> Mask;
4629 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4631 Mask.push_back(i + NumElems);
4633 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4636 /// Returns a vector_shuffle node for an unpackh operation.
4637 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4639 unsigned NumElems = VT.getVectorNumElements();
4640 SmallVector<int, 8> Mask;
4641 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4642 Mask.push_back(i + Half);
4643 Mask.push_back(i + NumElems + Half);
4645 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4648 /// Return a vector_shuffle of the specified vector of zero or undef vector.
4649 /// This produces a shuffle where the low element of V2 is swizzled into the
4650 /// zero/undef vector, landing at element Idx.
4651 /// This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4652 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4654 const X86Subtarget *Subtarget,
4655 SelectionDAG &DAG) {
4656 MVT VT = V2.getSimpleValueType();
4658 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
4659 unsigned NumElems = VT.getVectorNumElements();
4660 SmallVector<int, 16> MaskVec;
4661 for (unsigned i = 0; i != NumElems; ++i)
4662 // If this is the insertion idx, put the low elt of V2 here.
4663 MaskVec.push_back(i == Idx ? NumElems : i);
4664 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
4667 /// Calculates the shuffle mask corresponding to the target-specific opcode.
4668 /// Returns true if the Mask could be calculated. Sets IsUnary to true if only
4669 /// uses one source. Note that this will set IsUnary for shuffles which use a
4670 /// single input multiple times, and in those cases it will
4671 /// adjust the mask to only have indices within that single input.
4672 /// FIXME: Add support for Decode*Mask functions that return SM_SentinelZero.
4673 static bool getTargetShuffleMask(SDNode *N, MVT VT,
4674 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4675 unsigned NumElems = VT.getVectorNumElements();
4679 bool IsFakeUnary = false;
4680 switch(N->getOpcode()) {
4681 case X86ISD::BLENDI:
4682 ImmN = N->getOperand(N->getNumOperands()-1);
4683 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4686 ImmN = N->getOperand(N->getNumOperands()-1);
4687 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4688 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4690 case X86ISD::UNPCKH:
4691 DecodeUNPCKHMask(VT, Mask);
4692 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4694 case X86ISD::UNPCKL:
4695 DecodeUNPCKLMask(VT, Mask);
4696 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4698 case X86ISD::MOVHLPS:
4699 DecodeMOVHLPSMask(NumElems, Mask);
4700 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4702 case X86ISD::MOVLHPS:
4703 DecodeMOVLHPSMask(NumElems, Mask);
4704 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4706 case X86ISD::PALIGNR:
4707 ImmN = N->getOperand(N->getNumOperands()-1);
4708 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4710 case X86ISD::PSHUFD:
4711 case X86ISD::VPERMILPI:
4712 ImmN = N->getOperand(N->getNumOperands()-1);
4713 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4716 case X86ISD::PSHUFHW:
4717 ImmN = N->getOperand(N->getNumOperands()-1);
4718 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4721 case X86ISD::PSHUFLW:
4722 ImmN = N->getOperand(N->getNumOperands()-1);
4723 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4726 case X86ISD::PSHUFB: {
4728 SDValue MaskNode = N->getOperand(1);
4729 while (MaskNode->getOpcode() == ISD::BITCAST)
4730 MaskNode = MaskNode->getOperand(0);
4732 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4733 // If we have a build-vector, then things are easy.
4734 MVT VT = MaskNode.getSimpleValueType();
4735 assert(VT.isVector() &&
4736 "Can't produce a non-vector with a build_vector!");
4737 if (!VT.isInteger())
4740 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
4742 SmallVector<uint64_t, 32> RawMask;
4743 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
4744 SDValue Op = MaskNode->getOperand(i);
4745 if (Op->getOpcode() == ISD::UNDEF) {
4746 RawMask.push_back((uint64_t)SM_SentinelUndef);
4749 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
4752 APInt MaskElement = CN->getAPIntValue();
4754 // We now have to decode the element which could be any integer size and
4755 // extract each byte of it.
4756 for (int j = 0; j < NumBytesPerElement; ++j) {
4757 // Note that this is x86 and so always little endian: the low byte is
4758 // the first byte of the mask.
4759 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
4760 MaskElement = MaskElement.lshr(8);
4763 DecodePSHUFBMask(RawMask, Mask);
4767 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4771 SDValue Ptr = MaskLoad->getBasePtr();
4772 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4773 Ptr->getOpcode() == X86ISD::WrapperRIP)
4774 Ptr = Ptr->getOperand(0);
4776 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4777 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4780 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
4781 DecodePSHUFBMask(C, Mask);
4789 case X86ISD::VPERMI:
4790 ImmN = N->getOperand(N->getNumOperands()-1);
4791 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4796 DecodeScalarMoveMask(VT, /* IsLoad */ false, Mask);
4798 case X86ISD::VPERM2X128:
4799 ImmN = N->getOperand(N->getNumOperands()-1);
4800 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4801 if (Mask.empty()) return false;
4802 // Mask only contains negative index if an element is zero.
4803 if (std::any_of(Mask.begin(), Mask.end(),
4804 [](int M){ return M == SM_SentinelZero; }))
4807 case X86ISD::MOVSLDUP:
4808 DecodeMOVSLDUPMask(VT, Mask);
4811 case X86ISD::MOVSHDUP:
4812 DecodeMOVSHDUPMask(VT, Mask);
4815 case X86ISD::MOVDDUP:
4816 DecodeMOVDDUPMask(VT, Mask);
4819 case X86ISD::MOVLHPD:
4820 case X86ISD::MOVLPD:
4821 case X86ISD::MOVLPS:
4822 // Not yet implemented
4824 case X86ISD::VPERMV: {
4826 SDValue MaskNode = N->getOperand(0);
4827 while (MaskNode->getOpcode() == ISD::BITCAST)
4828 MaskNode = MaskNode->getOperand(0);
4830 unsigned MaskLoBits = Log2_64(VT.getVectorNumElements());
4831 SmallVector<uint64_t, 32> RawMask;
4832 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4833 // If we have a build-vector, then things are easy.
4834 assert(MaskNode.getSimpleValueType().isInteger() &&
4835 MaskNode.getSimpleValueType().getVectorNumElements() ==
4836 VT.getVectorNumElements());
4838 for (unsigned i = 0; i < MaskNode->getNumOperands(); ++i) {
4839 SDValue Op = MaskNode->getOperand(i);
4840 if (Op->getOpcode() == ISD::UNDEF)
4841 RawMask.push_back((uint64_t)SM_SentinelUndef);
4842 else if (isa<ConstantSDNode>(Op)) {
4843 APInt MaskElement = cast<ConstantSDNode>(Op)->getAPIntValue();
4844 RawMask.push_back(MaskElement.getLoBits(MaskLoBits).getZExtValue());
4848 DecodeVPERMVMask(RawMask, Mask);
4851 if (MaskNode->getOpcode() == X86ISD::VBROADCAST) {
4852 unsigned NumEltsInMask = MaskNode->getNumOperands();
4853 MaskNode = MaskNode->getOperand(0);
4854 auto *CN = dyn_cast<ConstantSDNode>(MaskNode);
4856 APInt MaskEltValue = CN->getAPIntValue();
4857 for (unsigned i = 0; i < NumEltsInMask; ++i)
4858 RawMask.push_back(MaskEltValue.getLoBits(MaskLoBits).getZExtValue());
4859 DecodeVPERMVMask(RawMask, Mask);
4862 // It may be a scalar load
4865 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4869 SDValue Ptr = MaskLoad->getBasePtr();
4870 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4871 Ptr->getOpcode() == X86ISD::WrapperRIP)
4872 Ptr = Ptr->getOperand(0);
4874 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4875 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4878 auto *C = dyn_cast<Constant>(MaskCP->getConstVal());
4880 DecodeVPERMVMask(C, VT, Mask);
4887 case X86ISD::VPERMV3: {
4889 SDValue MaskNode = N->getOperand(1);
4890 while (MaskNode->getOpcode() == ISD::BITCAST)
4891 MaskNode = MaskNode->getOperand(1);
4893 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4894 // If we have a build-vector, then things are easy.
4895 assert(MaskNode.getSimpleValueType().isInteger() &&
4896 MaskNode.getSimpleValueType().getVectorNumElements() ==
4897 VT.getVectorNumElements());
4899 SmallVector<uint64_t, 32> RawMask;
4900 unsigned MaskLoBits = Log2_64(VT.getVectorNumElements()*2);
4902 for (unsigned i = 0; i < MaskNode->getNumOperands(); ++i) {
4903 SDValue Op = MaskNode->getOperand(i);
4904 if (Op->getOpcode() == ISD::UNDEF)
4905 RawMask.push_back((uint64_t)SM_SentinelUndef);
4907 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
4910 APInt MaskElement = CN->getAPIntValue();
4911 RawMask.push_back(MaskElement.getLoBits(MaskLoBits).getZExtValue());
4914 DecodeVPERMV3Mask(RawMask, Mask);
4918 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4922 SDValue Ptr = MaskLoad->getBasePtr();
4923 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4924 Ptr->getOpcode() == X86ISD::WrapperRIP)
4925 Ptr = Ptr->getOperand(0);
4927 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4928 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4931 auto *C = dyn_cast<Constant>(MaskCP->getConstVal());
4933 DecodeVPERMV3Mask(C, VT, Mask);
4940 default: llvm_unreachable("unknown target shuffle node");
4943 // If we have a fake unary shuffle, the shuffle mask is spread across two
4944 // inputs that are actually the same node. Re-map the mask to always point
4945 // into the first input.
4948 if (M >= (int)Mask.size())
4954 /// Returns the scalar element that will make up the ith
4955 /// element of the result of the vector shuffle.
4956 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
4959 return SDValue(); // Limit search depth.
4961 SDValue V = SDValue(N, 0);
4962 EVT VT = V.getValueType();
4963 unsigned Opcode = V.getOpcode();
4965 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4966 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4967 int Elt = SV->getMaskElt(Index);
4970 return DAG.getUNDEF(VT.getVectorElementType());
4972 unsigned NumElems = VT.getVectorNumElements();
4973 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
4974 : SV->getOperand(1);
4975 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
4978 // Recurse into target specific vector shuffles to find scalars.
4979 if (isTargetShuffle(Opcode)) {
4980 MVT ShufVT = V.getSimpleValueType();
4981 unsigned NumElems = ShufVT.getVectorNumElements();
4982 SmallVector<int, 16> ShuffleMask;
4985 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
4988 int Elt = ShuffleMask[Index];
4990 return DAG.getUNDEF(ShufVT.getVectorElementType());
4992 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
4994 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
4998 // Actual nodes that may contain scalar elements
4999 if (Opcode == ISD::BITCAST) {
5000 V = V.getOperand(0);
5001 EVT SrcVT = V.getValueType();
5002 unsigned NumElems = VT.getVectorNumElements();
5004 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5008 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5009 return (Index == 0) ? V.getOperand(0)
5010 : DAG.getUNDEF(VT.getVectorElementType());
5012 if (V.getOpcode() == ISD::BUILD_VECTOR)
5013 return V.getOperand(Index);
5018 /// Custom lower build_vector of v16i8.
5019 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5020 unsigned NumNonZero, unsigned NumZero,
5022 const X86Subtarget* Subtarget,
5023 const TargetLowering &TLI) {
5031 // SSE4.1 - use PINSRB to insert each byte directly.
5032 if (Subtarget->hasSSE41()) {
5033 for (unsigned i = 0; i < 16; ++i) {
5034 bool isNonZero = (NonZeros & (1 << i)) != 0;
5038 V = getZeroVector(MVT::v16i8, Subtarget, DAG, dl);
5040 V = DAG.getUNDEF(MVT::v16i8);
5043 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5044 MVT::v16i8, V, Op.getOperand(i),
5045 DAG.getIntPtrConstant(i, dl));
5052 // Pre-SSE4.1 - merge byte pairs and insert with PINSRW.
5053 for (unsigned i = 0; i < 16; ++i) {
5054 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5055 if (ThisIsNonZero && First) {
5057 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5059 V = DAG.getUNDEF(MVT::v8i16);
5064 SDValue ThisElt, LastElt;
5065 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5066 if (LastIsNonZero) {
5067 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5068 MVT::i16, Op.getOperand(i-1));
5070 if (ThisIsNonZero) {
5071 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5072 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5073 ThisElt, DAG.getConstant(8, dl, MVT::i8));
5075 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5079 if (ThisElt.getNode())
5080 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5081 DAG.getIntPtrConstant(i/2, dl));
5085 return DAG.getBitcast(MVT::v16i8, V);
5088 /// Custom lower build_vector of v8i16.
5089 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5090 unsigned NumNonZero, unsigned NumZero,
5092 const X86Subtarget* Subtarget,
5093 const TargetLowering &TLI) {
5100 for (unsigned i = 0; i < 8; ++i) {
5101 bool isNonZero = (NonZeros & (1 << i)) != 0;
5105 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5107 V = DAG.getUNDEF(MVT::v8i16);
5110 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5111 MVT::v8i16, V, Op.getOperand(i),
5112 DAG.getIntPtrConstant(i, dl));
5119 /// Custom lower build_vector of v4i32 or v4f32.
5120 static SDValue LowerBuildVectorv4x32(SDValue Op, SelectionDAG &DAG,
5121 const X86Subtarget *Subtarget,
5122 const TargetLowering &TLI) {
5123 // Find all zeroable elements.
5124 std::bitset<4> Zeroable;
5125 for (int i=0; i < 4; ++i) {
5126 SDValue Elt = Op->getOperand(i);
5127 Zeroable[i] = (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt));
5129 assert(Zeroable.size() - Zeroable.count() > 1 &&
5130 "We expect at least two non-zero elements!");
5132 // We only know how to deal with build_vector nodes where elements are either
5133 // zeroable or extract_vector_elt with constant index.
5134 SDValue FirstNonZero;
5135 unsigned FirstNonZeroIdx;
5136 for (unsigned i=0; i < 4; ++i) {
5139 SDValue Elt = Op->getOperand(i);
5140 if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5141 !isa<ConstantSDNode>(Elt.getOperand(1)))
5143 // Make sure that this node is extracting from a 128-bit vector.
5144 MVT VT = Elt.getOperand(0).getSimpleValueType();
5145 if (!VT.is128BitVector())
5147 if (!FirstNonZero.getNode()) {
5149 FirstNonZeroIdx = i;
5153 assert(FirstNonZero.getNode() && "Unexpected build vector of all zeros!");
5154 SDValue V1 = FirstNonZero.getOperand(0);
5155 MVT VT = V1.getSimpleValueType();
5157 // See if this build_vector can be lowered as a blend with zero.
5159 unsigned EltMaskIdx, EltIdx;
5161 for (EltIdx = 0; EltIdx < 4; ++EltIdx) {
5162 if (Zeroable[EltIdx]) {
5163 // The zero vector will be on the right hand side.
5164 Mask[EltIdx] = EltIdx+4;
5168 Elt = Op->getOperand(EltIdx);
5169 // By construction, Elt is a EXTRACT_VECTOR_ELT with constant index.
5170 EltMaskIdx = cast<ConstantSDNode>(Elt.getOperand(1))->getZExtValue();
5171 if (Elt.getOperand(0) != V1 || EltMaskIdx != EltIdx)
5173 Mask[EltIdx] = EltIdx;
5177 // Let the shuffle legalizer deal with blend operations.
5178 SDValue VZero = getZeroVector(VT, Subtarget, DAG, SDLoc(Op));
5179 if (V1.getSimpleValueType() != VT)
5180 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), VT, V1);
5181 return DAG.getVectorShuffle(VT, SDLoc(V1), V1, VZero, &Mask[0]);
5184 // See if we can lower this build_vector to a INSERTPS.
5185 if (!Subtarget->hasSSE41())
5188 SDValue V2 = Elt.getOperand(0);
5189 if (Elt == FirstNonZero && EltIdx == FirstNonZeroIdx)
5192 bool CanFold = true;
5193 for (unsigned i = EltIdx + 1; i < 4 && CanFold; ++i) {
5197 SDValue Current = Op->getOperand(i);
5198 SDValue SrcVector = Current->getOperand(0);
5201 CanFold = SrcVector == V1 &&
5202 cast<ConstantSDNode>(Current.getOperand(1))->getZExtValue() == i;
5208 assert(V1.getNode() && "Expected at least two non-zero elements!");
5209 if (V1.getSimpleValueType() != MVT::v4f32)
5210 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), MVT::v4f32, V1);
5211 if (V2.getSimpleValueType() != MVT::v4f32)
5212 V2 = DAG.getNode(ISD::BITCAST, SDLoc(V2), MVT::v4f32, V2);
5214 // Ok, we can emit an INSERTPS instruction.
5215 unsigned ZMask = Zeroable.to_ulong();
5217 unsigned InsertPSMask = EltMaskIdx << 6 | EltIdx << 4 | ZMask;
5218 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
5220 SDValue Result = DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
5221 DAG.getIntPtrConstant(InsertPSMask, DL));
5222 return DAG.getBitcast(VT, Result);
5225 /// Return a vector logical shift node.
5226 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5227 unsigned NumBits, SelectionDAG &DAG,
5228 const TargetLowering &TLI, SDLoc dl) {
5229 assert(VT.is128BitVector() && "Unknown type for VShift");
5230 MVT ShVT = MVT::v2i64;
5231 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5232 SrcOp = DAG.getBitcast(ShVT, SrcOp);
5233 MVT ScalarShiftTy = TLI.getScalarShiftAmountTy(DAG.getDataLayout(), VT);
5234 assert(NumBits % 8 == 0 && "Only support byte sized shifts");
5235 SDValue ShiftVal = DAG.getConstant(NumBits/8, dl, ScalarShiftTy);
5236 return DAG.getBitcast(VT, DAG.getNode(Opc, dl, ShVT, SrcOp, ShiftVal));
5240 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5242 // Check if the scalar load can be widened into a vector load. And if
5243 // the address is "base + cst" see if the cst can be "absorbed" into
5244 // the shuffle mask.
5245 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5246 SDValue Ptr = LD->getBasePtr();
5247 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5249 EVT PVT = LD->getValueType(0);
5250 if (PVT != MVT::i32 && PVT != MVT::f32)
5255 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5256 FI = FINode->getIndex();
5258 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5259 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5260 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5261 Offset = Ptr.getConstantOperandVal(1);
5262 Ptr = Ptr.getOperand(0);
5267 // FIXME: 256-bit vector instructions don't require a strict alignment,
5268 // improve this code to support it better.
5269 unsigned RequiredAlign = VT.getSizeInBits()/8;
5270 SDValue Chain = LD->getChain();
5271 // Make sure the stack object alignment is at least 16 or 32.
5272 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5273 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5274 if (MFI->isFixedObjectIndex(FI)) {
5275 // Can't change the alignment. FIXME: It's possible to compute
5276 // the exact stack offset and reference FI + adjust offset instead.
5277 // If someone *really* cares about this. That's the way to implement it.
5280 MFI->setObjectAlignment(FI, RequiredAlign);
5284 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5285 // Ptr + (Offset & ~15).
5288 if ((Offset % RequiredAlign) & 3)
5290 int64_t StartOffset = Offset & ~int64_t(RequiredAlign - 1);
5293 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
5294 DAG.getConstant(StartOffset, DL, Ptr.getValueType()));
5297 int EltNo = (Offset - StartOffset) >> 2;
5298 unsigned NumElems = VT.getVectorNumElements();
5300 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5301 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5302 LD->getPointerInfo().getWithOffset(StartOffset),
5303 false, false, false, 0);
5305 SmallVector<int, 8> Mask(NumElems, EltNo);
5307 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5313 /// Given the initializing elements 'Elts' of a vector of type 'VT', see if the
5314 /// elements can be replaced by a single large load which has the same value as
5315 /// a build_vector or insert_subvector whose loaded operands are 'Elts'.
5317 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5319 /// FIXME: we'd also like to handle the case where the last elements are zero
5320 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5321 /// There's even a handy isZeroNode for that purpose.
5322 static SDValue EltsFromConsecutiveLoads(EVT VT, ArrayRef<SDValue> Elts,
5323 SDLoc &DL, SelectionDAG &DAG,
5324 bool isAfterLegalize) {
5325 unsigned NumElems = Elts.size();
5327 LoadSDNode *LDBase = nullptr;
5328 unsigned LastLoadedElt = -1U;
5330 // For each element in the initializer, see if we've found a load or an undef.
5331 // If we don't find an initial load element, or later load elements are
5332 // non-consecutive, bail out.
5333 for (unsigned i = 0; i < NumElems; ++i) {
5334 SDValue Elt = Elts[i];
5335 // Look through a bitcast.
5336 if (Elt.getNode() && Elt.getOpcode() == ISD::BITCAST)
5337 Elt = Elt.getOperand(0);
5338 if (!Elt.getNode() ||
5339 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5342 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5344 LDBase = cast<LoadSDNode>(Elt.getNode());
5348 if (Elt.getOpcode() == ISD::UNDEF)
5351 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5352 EVT LdVT = Elt.getValueType();
5353 // Each loaded element must be the correct fractional portion of the
5354 // requested vector load.
5355 if (LdVT.getSizeInBits() != VT.getSizeInBits() / NumElems)
5357 if (!DAG.isConsecutiveLoad(LD, LDBase, LdVT.getSizeInBits() / 8, i))
5362 // If we have found an entire vector of loads and undefs, then return a large
5363 // load of the entire vector width starting at the base pointer. If we found
5364 // consecutive loads for the low half, generate a vzext_load node.
5365 if (LastLoadedElt == NumElems - 1) {
5366 assert(LDBase && "Did not find base load for merging consecutive loads");
5367 EVT EltVT = LDBase->getValueType(0);
5368 // Ensure that the input vector size for the merged loads matches the
5369 // cumulative size of the input elements.
5370 if (VT.getSizeInBits() != EltVT.getSizeInBits() * NumElems)
5373 if (isAfterLegalize &&
5374 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
5377 SDValue NewLd = SDValue();
5379 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5380 LDBase->getPointerInfo(), LDBase->isVolatile(),
5381 LDBase->isNonTemporal(), LDBase->isInvariant(),
5382 LDBase->getAlignment());
5384 if (LDBase->hasAnyUseOfValue(1)) {
5385 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5387 SDValue(NewLd.getNode(), 1));
5388 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5389 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5390 SDValue(NewLd.getNode(), 1));
5396 //TODO: The code below fires only for for loading the low v2i32 / v2f32
5397 //of a v4i32 / v4f32. It's probably worth generalizing.
5398 EVT EltVT = VT.getVectorElementType();
5399 if (NumElems == 4 && LastLoadedElt == 1 && (EltVT.getSizeInBits() == 32) &&
5400 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5401 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5402 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5404 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
5405 LDBase->getPointerInfo(),
5406 LDBase->getAlignment(),
5407 false/*isVolatile*/, true/*ReadMem*/,
5410 // Make sure the newly-created LOAD is in the same position as LDBase in
5411 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5412 // update uses of LDBase's output chain to use the TokenFactor.
5413 if (LDBase->hasAnyUseOfValue(1)) {
5414 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5415 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5416 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5417 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5418 SDValue(ResNode.getNode(), 1));
5421 return DAG.getBitcast(VT, ResNode);
5426 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
5427 /// to generate a splat value for the following cases:
5428 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
5429 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
5430 /// a scalar load, or a constant.
5431 /// The VBROADCAST node is returned when a pattern is found,
5432 /// or SDValue() otherwise.
5433 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
5434 SelectionDAG &DAG) {
5435 // VBROADCAST requires AVX.
5436 // TODO: Splats could be generated for non-AVX CPUs using SSE
5437 // instructions, but there's less potential gain for only 128-bit vectors.
5438 if (!Subtarget->hasAVX())
5441 MVT VT = Op.getSimpleValueType();
5444 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
5445 "Unsupported vector type for broadcast.");
5450 switch (Op.getOpcode()) {
5452 // Unknown pattern found.
5455 case ISD::BUILD_VECTOR: {
5456 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
5457 BitVector UndefElements;
5458 SDValue Splat = BVOp->getSplatValue(&UndefElements);
5460 // We need a splat of a single value to use broadcast, and it doesn't
5461 // make any sense if the value is only in one element of the vector.
5462 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
5466 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5467 Ld.getOpcode() == ISD::ConstantFP);
5469 // Make sure that all of the users of a non-constant load are from the
5470 // BUILD_VECTOR node.
5471 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
5476 case ISD::VECTOR_SHUFFLE: {
5477 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5479 // Shuffles must have a splat mask where the first element is
5481 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5484 SDValue Sc = Op.getOperand(0);
5485 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5486 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5488 if (!Subtarget->hasInt256())
5491 // Use the register form of the broadcast instruction available on AVX2.
5492 if (VT.getSizeInBits() >= 256)
5493 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5494 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5497 Ld = Sc.getOperand(0);
5498 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5499 Ld.getOpcode() == ISD::ConstantFP);
5501 // The scalar_to_vector node and the suspected
5502 // load node must have exactly one user.
5503 // Constants may have multiple users.
5505 // AVX-512 has register version of the broadcast
5506 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
5507 Ld.getValueType().getSizeInBits() >= 32;
5508 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
5515 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5516 bool IsGE256 = (VT.getSizeInBits() >= 256);
5518 // When optimizing for size, generate up to 5 extra bytes for a broadcast
5519 // instruction to save 8 or more bytes of constant pool data.
5520 // TODO: If multiple splats are generated to load the same constant,
5521 // it may be detrimental to overall size. There needs to be a way to detect
5522 // that condition to know if this is truly a size win.
5523 bool OptForSize = DAG.getMachineFunction().getFunction()->optForSize();
5525 // Handle broadcasting a single constant scalar from the constant pool
5527 // On Sandybridge (no AVX2), it is still better to load a constant vector
5528 // from the constant pool and not to broadcast it from a scalar.
5529 // But override that restriction when optimizing for size.
5530 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
5531 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
5532 EVT CVT = Ld.getValueType();
5533 assert(!CVT.isVector() && "Must not broadcast a vector type");
5535 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
5536 // For size optimization, also splat v2f64 and v2i64, and for size opt
5537 // with AVX2, also splat i8 and i16.
5538 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
5539 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5540 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
5541 const Constant *C = nullptr;
5542 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5543 C = CI->getConstantIntValue();
5544 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5545 C = CF->getConstantFPValue();
5547 assert(C && "Invalid constant type");
5549 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5551 DAG.getConstantPool(C, TLI.getPointerTy(DAG.getDataLayout()));
5552 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5554 CVT, dl, DAG.getEntryNode(), CP,
5555 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), false,
5556 false, false, Alignment);
5558 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5562 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5564 // Handle AVX2 in-register broadcasts.
5565 if (!IsLoad && Subtarget->hasInt256() &&
5566 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
5567 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5569 // The scalar source must be a normal load.
5573 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5574 (Subtarget->hasVLX() && ScalarSize == 64))
5575 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5577 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5578 // double since there is no vbroadcastsd xmm
5579 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
5580 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5581 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5584 // Unsupported broadcast.
5588 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
5589 /// underlying vector and index.
5591 /// Modifies \p ExtractedFromVec to the real vector and returns the real
5593 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
5595 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
5596 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
5599 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
5601 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
5603 // (extract_vector_elt (vector_shuffle<2,u,u,u>
5604 // (extract_subvector (v8f32 %vreg0), Constant<4>),
5607 // In this case the vector is the extract_subvector expression and the index
5608 // is 2, as specified by the shuffle.
5609 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
5610 SDValue ShuffleVec = SVOp->getOperand(0);
5611 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
5612 assert(ShuffleVecVT.getVectorElementType() ==
5613 ExtractedFromVec.getSimpleValueType().getVectorElementType());
5615 int ShuffleIdx = SVOp->getMaskElt(Idx);
5616 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
5617 ExtractedFromVec = ShuffleVec;
5623 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
5624 MVT VT = Op.getSimpleValueType();
5626 // Skip if insert_vec_elt is not supported.
5627 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5628 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
5632 unsigned NumElems = Op.getNumOperands();
5636 SmallVector<unsigned, 4> InsertIndices;
5637 SmallVector<int, 8> Mask(NumElems, -1);
5639 for (unsigned i = 0; i != NumElems; ++i) {
5640 unsigned Opc = Op.getOperand(i).getOpcode();
5642 if (Opc == ISD::UNDEF)
5645 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
5646 // Quit if more than 1 elements need inserting.
5647 if (InsertIndices.size() > 1)
5650 InsertIndices.push_back(i);
5654 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
5655 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
5656 // Quit if non-constant index.
5657 if (!isa<ConstantSDNode>(ExtIdx))
5659 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
5661 // Quit if extracted from vector of different type.
5662 if (ExtractedFromVec.getValueType() != VT)
5665 if (!VecIn1.getNode())
5666 VecIn1 = ExtractedFromVec;
5667 else if (VecIn1 != ExtractedFromVec) {
5668 if (!VecIn2.getNode())
5669 VecIn2 = ExtractedFromVec;
5670 else if (VecIn2 != ExtractedFromVec)
5671 // Quit if more than 2 vectors to shuffle
5675 if (ExtractedFromVec == VecIn1)
5677 else if (ExtractedFromVec == VecIn2)
5678 Mask[i] = Idx + NumElems;
5681 if (!VecIn1.getNode())
5684 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5685 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
5686 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
5687 unsigned Idx = InsertIndices[i];
5688 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
5689 DAG.getIntPtrConstant(Idx, DL));
5695 static SDValue ConvertI1VectorToInteger(SDValue Op, SelectionDAG &DAG) {
5696 assert(ISD::isBuildVectorOfConstantSDNodes(Op.getNode()) &&
5697 Op.getScalarValueSizeInBits() == 1 &&
5698 "Can not convert non-constant vector");
5699 uint64_t Immediate = 0;
5700 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5701 SDValue In = Op.getOperand(idx);
5702 if (In.getOpcode() != ISD::UNDEF)
5703 Immediate |= cast<ConstantSDNode>(In)->getZExtValue() << idx;
5707 MVT::getIntegerVT(std::max((int)Op.getValueType().getSizeInBits(), 8));
5708 return DAG.getConstant(Immediate, dl, VT);
5710 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
5712 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
5714 MVT VT = Op.getSimpleValueType();
5715 assert((VT.getVectorElementType() == MVT::i1) &&
5716 "Unexpected type in LowerBUILD_VECTORvXi1!");
5719 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5720 SDValue Cst = DAG.getTargetConstant(0, dl, MVT::i1);
5721 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5722 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5725 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5726 SDValue Cst = DAG.getTargetConstant(1, dl, MVT::i1);
5727 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5728 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5731 if (ISD::isBuildVectorOfConstantSDNodes(Op.getNode())) {
5732 SDValue Imm = ConvertI1VectorToInteger(Op, DAG);
5733 if (Imm.getValueSizeInBits() == VT.getSizeInBits())
5734 return DAG.getBitcast(VT, Imm);
5735 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, Imm);
5736 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec,
5737 DAG.getIntPtrConstant(0, dl));
5740 // Vector has one or more non-const elements
5741 uint64_t Immediate = 0;
5742 SmallVector<unsigned, 16> NonConstIdx;
5743 bool IsSplat = true;
5744 bool HasConstElts = false;
5746 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5747 SDValue In = Op.getOperand(idx);
5748 if (In.getOpcode() == ISD::UNDEF)
5750 if (!isa<ConstantSDNode>(In))
5751 NonConstIdx.push_back(idx);
5753 Immediate |= cast<ConstantSDNode>(In)->getZExtValue() << idx;
5754 HasConstElts = true;
5758 else if (In != Op.getOperand(SplatIdx))
5762 // for splat use " (select i1 splat_elt, all-ones, all-zeroes)"
5764 return DAG.getNode(ISD::SELECT, dl, VT, Op.getOperand(SplatIdx),
5765 DAG.getConstant(1, dl, VT),
5766 DAG.getConstant(0, dl, VT));
5768 // insert elements one by one
5772 MVT ImmVT = MVT::getIntegerVT(std::max((int)VT.getSizeInBits(), 8));
5773 Imm = DAG.getConstant(Immediate, dl, ImmVT);
5775 else if (HasConstElts)
5776 Imm = DAG.getConstant(0, dl, VT);
5778 Imm = DAG.getUNDEF(VT);
5779 if (Imm.getValueSizeInBits() == VT.getSizeInBits())
5780 DstVec = DAG.getBitcast(VT, Imm);
5782 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, Imm);
5783 DstVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec,
5784 DAG.getIntPtrConstant(0, dl));
5787 for (unsigned i = 0; i < NonConstIdx.size(); ++i) {
5788 unsigned InsertIdx = NonConstIdx[i];
5789 DstVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
5790 Op.getOperand(InsertIdx),
5791 DAG.getIntPtrConstant(InsertIdx, dl));
5796 /// \brief Return true if \p N implements a horizontal binop and return the
5797 /// operands for the horizontal binop into V0 and V1.
5799 /// This is a helper function of LowerToHorizontalOp().
5800 /// This function checks that the build_vector \p N in input implements a
5801 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
5802 /// operation to match.
5803 /// For example, if \p Opcode is equal to ISD::ADD, then this function
5804 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
5805 /// is equal to ISD::SUB, then this function checks if this is a horizontal
5808 /// This function only analyzes elements of \p N whose indices are
5809 /// in range [BaseIdx, LastIdx).
5810 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
5812 unsigned BaseIdx, unsigned LastIdx,
5813 SDValue &V0, SDValue &V1) {
5814 EVT VT = N->getValueType(0);
5816 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
5817 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
5818 "Invalid Vector in input!");
5820 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
5821 bool CanFold = true;
5822 unsigned ExpectedVExtractIdx = BaseIdx;
5823 unsigned NumElts = LastIdx - BaseIdx;
5824 V0 = DAG.getUNDEF(VT);
5825 V1 = DAG.getUNDEF(VT);
5827 // Check if N implements a horizontal binop.
5828 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
5829 SDValue Op = N->getOperand(i + BaseIdx);
5832 if (Op->getOpcode() == ISD::UNDEF) {
5833 // Update the expected vector extract index.
5834 if (i * 2 == NumElts)
5835 ExpectedVExtractIdx = BaseIdx;
5836 ExpectedVExtractIdx += 2;
5840 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
5845 SDValue Op0 = Op.getOperand(0);
5846 SDValue Op1 = Op.getOperand(1);
5848 // Try to match the following pattern:
5849 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
5850 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5851 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5852 Op0.getOperand(0) == Op1.getOperand(0) &&
5853 isa<ConstantSDNode>(Op0.getOperand(1)) &&
5854 isa<ConstantSDNode>(Op1.getOperand(1)));
5858 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
5859 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
5861 if (i * 2 < NumElts) {
5862 if (V0.getOpcode() == ISD::UNDEF) {
5863 V0 = Op0.getOperand(0);
5864 if (V0.getValueType() != VT)
5868 if (V1.getOpcode() == ISD::UNDEF) {
5869 V1 = Op0.getOperand(0);
5870 if (V1.getValueType() != VT)
5873 if (i * 2 == NumElts)
5874 ExpectedVExtractIdx = BaseIdx;
5877 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
5878 if (I0 == ExpectedVExtractIdx)
5879 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
5880 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
5881 // Try to match the following dag sequence:
5882 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
5883 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
5887 ExpectedVExtractIdx += 2;
5893 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
5894 /// a concat_vector.
5896 /// This is a helper function of LowerToHorizontalOp().
5897 /// This function expects two 256-bit vectors called V0 and V1.
5898 /// At first, each vector is split into two separate 128-bit vectors.
5899 /// Then, the resulting 128-bit vectors are used to implement two
5900 /// horizontal binary operations.
5902 /// The kind of horizontal binary operation is defined by \p X86Opcode.
5904 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
5905 /// the two new horizontal binop.
5906 /// When Mode is set, the first horizontal binop dag node would take as input
5907 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
5908 /// horizontal binop dag node would take as input the lower 128-bit of V1
5909 /// and the upper 128-bit of V1.
5911 /// HADD V0_LO, V0_HI
5912 /// HADD V1_LO, V1_HI
5914 /// Otherwise, the first horizontal binop dag node takes as input the lower
5915 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
5916 /// dag node takes the upper 128-bit of V0 and the upper 128-bit of V1.
5918 /// HADD V0_LO, V1_LO
5919 /// HADD V0_HI, V1_HI
5921 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
5922 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
5923 /// the upper 128-bits of the result.
5924 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
5925 SDLoc DL, SelectionDAG &DAG,
5926 unsigned X86Opcode, bool Mode,
5927 bool isUndefLO, bool isUndefHI) {
5928 EVT VT = V0.getValueType();
5929 assert(VT.is256BitVector() && VT == V1.getValueType() &&
5930 "Invalid nodes in input!");
5932 unsigned NumElts = VT.getVectorNumElements();
5933 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
5934 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
5935 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
5936 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
5937 EVT NewVT = V0_LO.getValueType();
5939 SDValue LO = DAG.getUNDEF(NewVT);
5940 SDValue HI = DAG.getUNDEF(NewVT);
5943 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5944 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
5945 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
5946 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
5947 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
5949 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5950 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
5951 V1_LO->getOpcode() != ISD::UNDEF))
5952 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
5954 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
5955 V1_HI->getOpcode() != ISD::UNDEF))
5956 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
5959 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
5962 /// Try to fold a build_vector that performs an 'addsub' to an X86ISD::ADDSUB
5964 static SDValue LowerToAddSub(const BuildVectorSDNode *BV,
5965 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
5966 MVT VT = BV->getSimpleValueType(0);
5967 if ((!Subtarget->hasSSE3() || (VT != MVT::v4f32 && VT != MVT::v2f64)) &&
5968 (!Subtarget->hasAVX() || (VT != MVT::v8f32 && VT != MVT::v4f64)))
5972 unsigned NumElts = VT.getVectorNumElements();
5973 SDValue InVec0 = DAG.getUNDEF(VT);
5974 SDValue InVec1 = DAG.getUNDEF(VT);
5976 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
5977 VT == MVT::v2f64) && "build_vector with an invalid type found!");
5979 // Odd-numbered elements in the input build vector are obtained from
5980 // adding two integer/float elements.
5981 // Even-numbered elements in the input build vector are obtained from
5982 // subtracting two integer/float elements.
5983 unsigned ExpectedOpcode = ISD::FSUB;
5984 unsigned NextExpectedOpcode = ISD::FADD;
5985 bool AddFound = false;
5986 bool SubFound = false;
5988 for (unsigned i = 0, e = NumElts; i != e; ++i) {
5989 SDValue Op = BV->getOperand(i);
5991 // Skip 'undef' values.
5992 unsigned Opcode = Op.getOpcode();
5993 if (Opcode == ISD::UNDEF) {
5994 std::swap(ExpectedOpcode, NextExpectedOpcode);
5998 // Early exit if we found an unexpected opcode.
5999 if (Opcode != ExpectedOpcode)
6002 SDValue Op0 = Op.getOperand(0);
6003 SDValue Op1 = Op.getOperand(1);
6005 // Try to match the following pattern:
6006 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
6007 // Early exit if we cannot match that sequence.
6008 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6009 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6010 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
6011 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
6012 Op0.getOperand(1) != Op1.getOperand(1))
6015 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6019 // We found a valid add/sub node. Update the information accordingly.
6025 // Update InVec0 and InVec1.
6026 if (InVec0.getOpcode() == ISD::UNDEF) {
6027 InVec0 = Op0.getOperand(0);
6028 if (InVec0.getSimpleValueType() != VT)
6031 if (InVec1.getOpcode() == ISD::UNDEF) {
6032 InVec1 = Op1.getOperand(0);
6033 if (InVec1.getSimpleValueType() != VT)
6037 // Make sure that operands in input to each add/sub node always
6038 // come from a same pair of vectors.
6039 if (InVec0 != Op0.getOperand(0)) {
6040 if (ExpectedOpcode == ISD::FSUB)
6043 // FADD is commutable. Try to commute the operands
6044 // and then test again.
6045 std::swap(Op0, Op1);
6046 if (InVec0 != Op0.getOperand(0))
6050 if (InVec1 != Op1.getOperand(0))
6053 // Update the pair of expected opcodes.
6054 std::swap(ExpectedOpcode, NextExpectedOpcode);
6057 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
6058 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
6059 InVec1.getOpcode() != ISD::UNDEF)
6060 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
6065 /// Lower BUILD_VECTOR to a horizontal add/sub operation if possible.
6066 static SDValue LowerToHorizontalOp(const BuildVectorSDNode *BV,
6067 const X86Subtarget *Subtarget,
6068 SelectionDAG &DAG) {
6069 MVT VT = BV->getSimpleValueType(0);
6070 unsigned NumElts = VT.getVectorNumElements();
6071 unsigned NumUndefsLO = 0;
6072 unsigned NumUndefsHI = 0;
6073 unsigned Half = NumElts/2;
6075 // Count the number of UNDEF operands in the build_vector in input.
6076 for (unsigned i = 0, e = Half; i != e; ++i)
6077 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6080 for (unsigned i = Half, e = NumElts; i != e; ++i)
6081 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6084 // Early exit if this is either a build_vector of all UNDEFs or all the
6085 // operands but one are UNDEF.
6086 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
6090 SDValue InVec0, InVec1;
6091 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
6092 // Try to match an SSE3 float HADD/HSUB.
6093 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6094 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6096 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6097 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6098 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
6099 // Try to match an SSSE3 integer HADD/HSUB.
6100 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6101 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
6103 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6104 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
6107 if (!Subtarget->hasAVX())
6110 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
6111 // Try to match an AVX horizontal add/sub of packed single/double
6112 // precision floating point values from 256-bit vectors.
6113 SDValue InVec2, InVec3;
6114 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
6115 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
6116 ((InVec0.getOpcode() == ISD::UNDEF ||
6117 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6118 ((InVec1.getOpcode() == ISD::UNDEF ||
6119 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6120 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6122 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
6123 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
6124 ((InVec0.getOpcode() == ISD::UNDEF ||
6125 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6126 ((InVec1.getOpcode() == ISD::UNDEF ||
6127 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6128 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6129 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6130 // Try to match an AVX2 horizontal add/sub of signed integers.
6131 SDValue InVec2, InVec3;
6133 bool CanFold = true;
6135 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
6136 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6137 ((InVec0.getOpcode() == ISD::UNDEF ||
6138 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6139 ((InVec1.getOpcode() == ISD::UNDEF ||
6140 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6141 X86Opcode = X86ISD::HADD;
6142 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6143 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6144 ((InVec0.getOpcode() == ISD::UNDEF ||
6145 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6146 ((InVec1.getOpcode() == ISD::UNDEF ||
6147 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6148 X86Opcode = X86ISD::HSUB;
6153 // Fold this build_vector into a single horizontal add/sub.
6154 // Do this only if the target has AVX2.
6155 if (Subtarget->hasAVX2())
6156 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6158 // Do not try to expand this build_vector into a pair of horizontal
6159 // add/sub if we can emit a pair of scalar add/sub.
6160 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6163 // Convert this build_vector into a pair of horizontal binop followed by
6165 bool isUndefLO = NumUndefsLO == Half;
6166 bool isUndefHI = NumUndefsHI == Half;
6167 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6168 isUndefLO, isUndefHI);
6172 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6173 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6175 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6176 X86Opcode = X86ISD::HADD;
6177 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6178 X86Opcode = X86ISD::HSUB;
6179 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6180 X86Opcode = X86ISD::FHADD;
6181 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6182 X86Opcode = X86ISD::FHSUB;
6186 // Don't try to expand this build_vector into a pair of horizontal add/sub
6187 // if we can simply emit a pair of scalar add/sub.
6188 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6191 // Convert this build_vector into two horizontal add/sub followed by
6193 bool isUndefLO = NumUndefsLO == Half;
6194 bool isUndefHI = NumUndefsHI == Half;
6195 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6196 isUndefLO, isUndefHI);
6203 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6206 MVT VT = Op.getSimpleValueType();
6207 MVT ExtVT = VT.getVectorElementType();
6208 unsigned NumElems = Op.getNumOperands();
6210 // Generate vectors for predicate vectors.
6211 if (VT.getVectorElementType() == MVT::i1 && Subtarget->hasAVX512())
6212 return LowerBUILD_VECTORvXi1(Op, DAG);
6214 // Vectors containing all zeros can be matched by pxor and xorps later
6215 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6216 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6217 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6218 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6221 return getZeroVector(VT, Subtarget, DAG, dl);
6224 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6225 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6226 // vpcmpeqd on 256-bit vectors.
6227 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6228 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6231 if (!VT.is512BitVector())
6232 return getOnesVector(VT, Subtarget, DAG, dl);
6235 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(Op.getNode());
6236 if (SDValue AddSub = LowerToAddSub(BV, Subtarget, DAG))
6238 if (SDValue HorizontalOp = LowerToHorizontalOp(BV, Subtarget, DAG))
6239 return HorizontalOp;
6240 if (SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG))
6243 unsigned EVTBits = ExtVT.getSizeInBits();
6245 unsigned NumZero = 0;
6246 unsigned NumNonZero = 0;
6247 uint64_t NonZeros = 0;
6248 bool IsAllConstants = true;
6249 SmallSet<SDValue, 8> Values;
6250 for (unsigned i = 0; i < NumElems; ++i) {
6251 SDValue Elt = Op.getOperand(i);
6252 if (Elt.getOpcode() == ISD::UNDEF)
6255 if (Elt.getOpcode() != ISD::Constant &&
6256 Elt.getOpcode() != ISD::ConstantFP)
6257 IsAllConstants = false;
6258 if (X86::isZeroNode(Elt))
6261 assert(i < sizeof(NonZeros) * 8); // Make sure the shift is within range.
6262 NonZeros |= ((uint64_t)1 << i);
6267 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6268 if (NumNonZero == 0)
6269 return DAG.getUNDEF(VT);
6271 // Special case for single non-zero, non-undef, element.
6272 if (NumNonZero == 1) {
6273 unsigned Idx = countTrailingZeros(NonZeros);
6274 SDValue Item = Op.getOperand(Idx);
6276 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6277 // the value are obviously zero, truncate the value to i32 and do the
6278 // insertion that way. Only do this if the value is non-constant or if the
6279 // value is a constant being inserted into element 0. It is cheaper to do
6280 // a constant pool load than it is to do a movd + shuffle.
6281 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6282 (!IsAllConstants || Idx == 0)) {
6283 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6285 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6286 MVT VecVT = MVT::v4i32;
6288 // Truncate the value (which may itself be a constant) to i32, and
6289 // convert it to a vector with movd (S2V+shuffle to zero extend).
6290 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6291 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6292 return DAG.getBitcast(VT, getShuffleVectorZeroOrUndef(
6293 Item, Idx * 2, true, Subtarget, DAG));
6297 // If we have a constant or non-constant insertion into the low element of
6298 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6299 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6300 // depending on what the source datatype is.
6303 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6305 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6306 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6307 if (VT.is512BitVector()) {
6308 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6309 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6310 Item, DAG.getIntPtrConstant(0, dl));
6312 assert((VT.is128BitVector() || VT.is256BitVector()) &&
6313 "Expected an SSE value type!");
6314 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6315 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6316 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6319 // We can't directly insert an i8 or i16 into a vector, so zero extend
6321 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6322 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6323 if (VT.is256BitVector()) {
6324 if (Subtarget->hasAVX()) {
6325 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v8i32, Item);
6326 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6328 // Without AVX, we need to extend to a 128-bit vector and then
6329 // insert into the 256-bit vector.
6330 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6331 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6332 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6335 assert(VT.is128BitVector() && "Expected an SSE value type!");
6336 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6337 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6339 return DAG.getBitcast(VT, Item);
6343 // Is it a vector logical left shift?
6344 if (NumElems == 2 && Idx == 1 &&
6345 X86::isZeroNode(Op.getOperand(0)) &&
6346 !X86::isZeroNode(Op.getOperand(1))) {
6347 unsigned NumBits = VT.getSizeInBits();
6348 return getVShift(true, VT,
6349 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6350 VT, Op.getOperand(1)),
6351 NumBits/2, DAG, *this, dl);
6354 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6357 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6358 // is a non-constant being inserted into an element other than the low one,
6359 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6360 // movd/movss) to move this into the low element, then shuffle it into
6362 if (EVTBits == 32) {
6363 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6364 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
6368 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6369 if (Values.size() == 1) {
6370 if (EVTBits == 32) {
6371 // Instead of a shuffle like this:
6372 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6373 // Check if it's possible to issue this instead.
6374 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6375 unsigned Idx = countTrailingZeros(NonZeros);
6376 SDValue Item = Op.getOperand(Idx);
6377 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6378 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6383 // A vector full of immediates; various special cases are already
6384 // handled, so this is best done with a single constant-pool load.
6388 // For AVX-length vectors, see if we can use a vector load to get all of the
6389 // elements, otherwise build the individual 128-bit pieces and use
6390 // shuffles to put them in place.
6391 if (VT.is256BitVector() || VT.is512BitVector()) {
6392 SmallVector<SDValue, 64> V(Op->op_begin(), Op->op_begin() + NumElems);
6394 // Check for a build vector of consecutive loads.
6395 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
6398 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6400 // Build both the lower and upper subvector.
6401 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6402 makeArrayRef(&V[0], NumElems/2));
6403 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6404 makeArrayRef(&V[NumElems / 2], NumElems/2));
6406 // Recreate the wider vector with the lower and upper part.
6407 if (VT.is256BitVector())
6408 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6409 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6412 // Let legalizer expand 2-wide build_vectors.
6413 if (EVTBits == 64) {
6414 if (NumNonZero == 1) {
6415 // One half is zero or undef.
6416 unsigned Idx = countTrailingZeros(NonZeros);
6417 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6418 Op.getOperand(Idx));
6419 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6424 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6425 if (EVTBits == 8 && NumElems == 16)
6426 if (SDValue V = LowerBuildVectorv16i8(Op, NonZeros, NumNonZero, NumZero,
6427 DAG, Subtarget, *this))
6430 if (EVTBits == 16 && NumElems == 8)
6431 if (SDValue V = LowerBuildVectorv8i16(Op, NonZeros, NumNonZero, NumZero,
6432 DAG, Subtarget, *this))
6435 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
6436 if (EVTBits == 32 && NumElems == 4)
6437 if (SDValue V = LowerBuildVectorv4x32(Op, DAG, Subtarget, *this))
6440 // If element VT is == 32 bits, turn it into a number of shuffles.
6441 SmallVector<SDValue, 8> V(NumElems);
6442 if (NumElems == 4 && NumZero > 0) {
6443 for (unsigned i = 0; i < 4; ++i) {
6444 bool isZero = !(NonZeros & (1ULL << i));
6446 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
6448 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6451 for (unsigned i = 0; i < 2; ++i) {
6452 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
6455 V[i] = V[i*2]; // Must be a zero vector.
6458 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
6461 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
6464 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
6469 bool Reverse1 = (NonZeros & 0x3) == 2;
6470 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
6474 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
6475 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
6477 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
6480 if (Values.size() > 1 && VT.is128BitVector()) {
6481 // Check for a build vector of consecutive loads.
6482 for (unsigned i = 0; i < NumElems; ++i)
6483 V[i] = Op.getOperand(i);
6485 // Check for elements which are consecutive loads.
6486 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
6489 // Check for a build vector from mostly shuffle plus few inserting.
6490 if (SDValue Sh = buildFromShuffleMostly(Op, DAG))
6493 // For SSE 4.1, use insertps to put the high elements into the low element.
6494 if (Subtarget->hasSSE41()) {
6496 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
6497 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
6499 Result = DAG.getUNDEF(VT);
6501 for (unsigned i = 1; i < NumElems; ++i) {
6502 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
6503 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
6504 Op.getOperand(i), DAG.getIntPtrConstant(i, dl));
6509 // Otherwise, expand into a number of unpckl*, start by extending each of
6510 // our (non-undef) elements to the full vector width with the element in the
6511 // bottom slot of the vector (which generates no code for SSE).
6512 for (unsigned i = 0; i < NumElems; ++i) {
6513 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
6514 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6516 V[i] = DAG.getUNDEF(VT);
6519 // Next, we iteratively mix elements, e.g. for v4f32:
6520 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
6521 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
6522 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
6523 unsigned EltStride = NumElems >> 1;
6524 while (EltStride != 0) {
6525 for (unsigned i = 0; i < EltStride; ++i) {
6526 // If V[i+EltStride] is undef and this is the first round of mixing,
6527 // then it is safe to just drop this shuffle: V[i] is already in the
6528 // right place, the one element (since it's the first round) being
6529 // inserted as undef can be dropped. This isn't safe for successive
6530 // rounds because they will permute elements within both vectors.
6531 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
6532 EltStride == NumElems/2)
6535 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
6544 // 256-bit AVX can use the vinsertf128 instruction
6545 // to create 256-bit vectors from two other 128-bit ones.
6546 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6548 MVT ResVT = Op.getSimpleValueType();
6550 assert((ResVT.is256BitVector() ||
6551 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
6553 SDValue V1 = Op.getOperand(0);
6554 SDValue V2 = Op.getOperand(1);
6555 unsigned NumElems = ResVT.getVectorNumElements();
6556 if (ResVT.is256BitVector())
6557 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6559 if (Op.getNumOperands() == 4) {
6560 MVT HalfVT = MVT::getVectorVT(ResVT.getVectorElementType(),
6561 ResVT.getVectorNumElements()/2);
6562 SDValue V3 = Op.getOperand(2);
6563 SDValue V4 = Op.getOperand(3);
6564 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
6565 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
6567 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6570 static SDValue LowerCONCAT_VECTORSvXi1(SDValue Op,
6571 const X86Subtarget *Subtarget,
6572 SelectionDAG & DAG) {
6574 MVT ResVT = Op.getSimpleValueType();
6575 unsigned NumOfOperands = Op.getNumOperands();
6577 assert(isPowerOf2_32(NumOfOperands) &&
6578 "Unexpected number of operands in CONCAT_VECTORS");
6580 SDValue Undef = DAG.getUNDEF(ResVT);
6581 if (NumOfOperands > 2) {
6582 // Specialize the cases when all, or all but one, of the operands are undef.
6583 unsigned NumOfDefinedOps = 0;
6585 for (unsigned i = 0; i < NumOfOperands; i++)
6586 if (!Op.getOperand(i).isUndef()) {
6590 if (NumOfDefinedOps == 0)
6592 if (NumOfDefinedOps == 1) {
6593 unsigned SubVecNumElts =
6594 Op.getOperand(OpIdx).getValueType().getVectorNumElements();
6595 SDValue IdxVal = DAG.getIntPtrConstant(SubVecNumElts * OpIdx, dl);
6596 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef,
6597 Op.getOperand(OpIdx), IdxVal);
6600 MVT HalfVT = MVT::getVectorVT(ResVT.getVectorElementType(),
6601 ResVT.getVectorNumElements()/2);
6602 SmallVector<SDValue, 2> Ops;
6603 for (unsigned i = 0; i < NumOfOperands/2; i++)
6604 Ops.push_back(Op.getOperand(i));
6605 SDValue Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6607 for (unsigned i = NumOfOperands/2; i < NumOfOperands; i++)
6608 Ops.push_back(Op.getOperand(i));
6609 SDValue Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6610 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
6614 SDValue V1 = Op.getOperand(0);
6615 SDValue V2 = Op.getOperand(1);
6616 unsigned NumElems = ResVT.getVectorNumElements();
6617 assert(V1.getValueType() == V2.getValueType() &&
6618 V1.getValueType().getVectorNumElements() == NumElems/2 &&
6619 "Unexpected operands in CONCAT_VECTORS");
6621 if (ResVT.getSizeInBits() >= 16)
6622 return Op; // The operation is legal with KUNPCK
6624 bool IsZeroV1 = ISD::isBuildVectorAllZeros(V1.getNode());
6625 bool IsZeroV2 = ISD::isBuildVectorAllZeros(V2.getNode());
6626 SDValue ZeroVec = getZeroVector(ResVT, Subtarget, DAG, dl);
6627 if (IsZeroV1 && IsZeroV2)
6630 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
6632 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V1, ZeroIdx);
6634 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, ZeroVec, V1, ZeroIdx);
6636 SDValue IdxVal = DAG.getIntPtrConstant(NumElems/2, dl);
6638 V2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V2, IdxVal);
6641 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, ZeroVec, V2, IdxVal);
6643 V1 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V1, ZeroIdx);
6644 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, V1, V2, IdxVal);
6647 static SDValue LowerCONCAT_VECTORS(SDValue Op,
6648 const X86Subtarget *Subtarget,
6649 SelectionDAG &DAG) {
6650 MVT VT = Op.getSimpleValueType();
6651 if (VT.getVectorElementType() == MVT::i1)
6652 return LowerCONCAT_VECTORSvXi1(Op, Subtarget, DAG);
6654 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
6655 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
6656 Op.getNumOperands() == 4)));
6658 // AVX can use the vinsertf128 instruction to create 256-bit vectors
6659 // from two other 128-bit ones.
6661 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
6662 return LowerAVXCONCAT_VECTORS(Op, DAG);
6665 //===----------------------------------------------------------------------===//
6666 // Vector shuffle lowering
6668 // This is an experimental code path for lowering vector shuffles on x86. It is
6669 // designed to handle arbitrary vector shuffles and blends, gracefully
6670 // degrading performance as necessary. It works hard to recognize idiomatic
6671 // shuffles and lower them to optimal instruction patterns without leaving
6672 // a framework that allows reasonably efficient handling of all vector shuffle
6674 //===----------------------------------------------------------------------===//
6676 /// \brief Tiny helper function to identify a no-op mask.
6678 /// This is a somewhat boring predicate function. It checks whether the mask
6679 /// array input, which is assumed to be a single-input shuffle mask of the kind
6680 /// used by the X86 shuffle instructions (not a fully general
6681 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
6682 /// in-place shuffle are 'no-op's.
6683 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
6684 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6685 if (Mask[i] != -1 && Mask[i] != i)
6690 /// \brief Helper function to classify a mask as a single-input mask.
6692 /// This isn't a generic single-input test because in the vector shuffle
6693 /// lowering we canonicalize single inputs to be the first input operand. This
6694 /// means we can more quickly test for a single input by only checking whether
6695 /// an input from the second operand exists. We also assume that the size of
6696 /// mask corresponds to the size of the input vectors which isn't true in the
6697 /// fully general case.
6698 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
6700 if (M >= (int)Mask.size())
6705 /// \brief Test whether there are elements crossing 128-bit lanes in this
6708 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
6709 /// and we routinely test for these.
6710 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
6711 int LaneSize = 128 / VT.getScalarSizeInBits();
6712 int Size = Mask.size();
6713 for (int i = 0; i < Size; ++i)
6714 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
6719 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
6721 /// This checks a shuffle mask to see if it is performing the same
6722 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
6723 /// that it is also not lane-crossing. It may however involve a blend from the
6724 /// same lane of a second vector.
6726 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
6727 /// non-trivial to compute in the face of undef lanes. The representation is
6728 /// *not* suitable for use with existing 128-bit shuffles as it will contain
6729 /// entries from both V1 and V2 inputs to the wider mask.
6731 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
6732 SmallVectorImpl<int> &RepeatedMask) {
6733 int LaneSize = 128 / VT.getScalarSizeInBits();
6734 RepeatedMask.resize(LaneSize, -1);
6735 int Size = Mask.size();
6736 for (int i = 0; i < Size; ++i) {
6739 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
6740 // This entry crosses lanes, so there is no way to model this shuffle.
6743 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
6744 if (RepeatedMask[i % LaneSize] == -1)
6745 // This is the first non-undef entry in this slot of a 128-bit lane.
6746 RepeatedMask[i % LaneSize] =
6747 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
6748 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
6749 // Found a mismatch with the repeated mask.
6755 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
6758 /// This is a fast way to test a shuffle mask against a fixed pattern:
6760 /// if (isShuffleEquivalent(Mask, 3, 2, {1, 0})) { ... }
6762 /// It returns true if the mask is exactly as wide as the argument list, and
6763 /// each element of the mask is either -1 (signifying undef) or the value given
6764 /// in the argument.
6765 static bool isShuffleEquivalent(SDValue V1, SDValue V2, ArrayRef<int> Mask,
6766 ArrayRef<int> ExpectedMask) {
6767 if (Mask.size() != ExpectedMask.size())
6770 int Size = Mask.size();
6772 // If the values are build vectors, we can look through them to find
6773 // equivalent inputs that make the shuffles equivalent.
6774 auto *BV1 = dyn_cast<BuildVectorSDNode>(V1);
6775 auto *BV2 = dyn_cast<BuildVectorSDNode>(V2);
6777 for (int i = 0; i < Size; ++i)
6778 if (Mask[i] != -1 && Mask[i] != ExpectedMask[i]) {
6779 auto *MaskBV = Mask[i] < Size ? BV1 : BV2;
6780 auto *ExpectedBV = ExpectedMask[i] < Size ? BV1 : BV2;
6781 if (!MaskBV || !ExpectedBV ||
6782 MaskBV->getOperand(Mask[i] % Size) !=
6783 ExpectedBV->getOperand(ExpectedMask[i] % Size))
6790 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
6792 /// This helper function produces an 8-bit shuffle immediate corresponding to
6793 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
6794 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
6797 /// NB: We rely heavily on "undef" masks preserving the input lane.
6798 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask, SDLoc DL,
6799 SelectionDAG &DAG) {
6800 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
6801 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
6802 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
6803 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
6804 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
6807 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
6808 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
6809 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
6810 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
6811 return DAG.getConstant(Imm, DL, MVT::i8);
6814 /// \brief Compute whether each element of a shuffle is zeroable.
6816 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
6817 /// Either it is an undef element in the shuffle mask, the element of the input
6818 /// referenced is undef, or the element of the input referenced is known to be
6819 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
6820 /// as many lanes with this technique as possible to simplify the remaining
6822 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
6823 SDValue V1, SDValue V2) {
6824 SmallBitVector Zeroable(Mask.size(), false);
6826 while (V1.getOpcode() == ISD::BITCAST)
6827 V1 = V1->getOperand(0);
6828 while (V2.getOpcode() == ISD::BITCAST)
6829 V2 = V2->getOperand(0);
6831 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
6832 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
6834 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6836 // Handle the easy cases.
6837 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
6842 // If this is an index into a build_vector node (which has the same number
6843 // of elements), dig out the input value and use it.
6844 SDValue V = M < Size ? V1 : V2;
6845 if (V.getOpcode() != ISD::BUILD_VECTOR || Size != (int)V.getNumOperands())
6848 SDValue Input = V.getOperand(M % Size);
6849 // The UNDEF opcode check really should be dead code here, but not quite
6850 // worth asserting on (it isn't invalid, just unexpected).
6851 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
6858 // X86 has dedicated unpack instructions that can handle specific blend
6859 // operations: UNPCKH and UNPCKL.
6860 static SDValue lowerVectorShuffleWithUNPCK(SDLoc DL, MVT VT, ArrayRef<int> Mask,
6861 SDValue V1, SDValue V2,
6862 SelectionDAG &DAG) {
6863 int NumElts = VT.getVectorNumElements();
6864 int NumEltsInLane = 128 / VT.getScalarSizeInBits();
6865 SmallVector<int, 8> Unpckl;
6866 SmallVector<int, 8> Unpckh;
6868 for (int i = 0; i < NumElts; ++i) {
6869 unsigned LaneStart = (i / NumEltsInLane) * NumEltsInLane;
6870 int LoPos = (i % NumEltsInLane) / 2 + LaneStart + NumElts * (i % 2);
6871 int HiPos = LoPos + NumEltsInLane / 2;
6872 Unpckl.push_back(LoPos);
6873 Unpckh.push_back(HiPos);
6876 if (isShuffleEquivalent(V1, V2, Mask, Unpckl))
6877 return DAG.getNode(X86ISD::UNPCKL, DL, VT, V1, V2);
6878 if (isShuffleEquivalent(V1, V2, Mask, Unpckh))
6879 return DAG.getNode(X86ISD::UNPCKH, DL, VT, V1, V2);
6881 // Commute and try again.
6882 ShuffleVectorSDNode::commuteMask(Unpckl);
6883 if (isShuffleEquivalent(V1, V2, Mask, Unpckl))
6884 return DAG.getNode(X86ISD::UNPCKL, DL, VT, V2, V1);
6886 ShuffleVectorSDNode::commuteMask(Unpckh);
6887 if (isShuffleEquivalent(V1, V2, Mask, Unpckh))
6888 return DAG.getNode(X86ISD::UNPCKH, DL, VT, V2, V1);
6893 /// \brief Try to emit a bitmask instruction for a shuffle.
6895 /// This handles cases where we can model a blend exactly as a bitmask due to
6896 /// one of the inputs being zeroable.
6897 static SDValue lowerVectorShuffleAsBitMask(SDLoc DL, MVT VT, SDValue V1,
6898 SDValue V2, ArrayRef<int> Mask,
6899 SelectionDAG &DAG) {
6900 MVT EltVT = VT.getVectorElementType();
6901 int NumEltBits = EltVT.getSizeInBits();
6902 MVT IntEltVT = MVT::getIntegerVT(NumEltBits);
6903 SDValue Zero = DAG.getConstant(0, DL, IntEltVT);
6904 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
6906 if (EltVT.isFloatingPoint()) {
6907 Zero = DAG.getBitcast(EltVT, Zero);
6908 AllOnes = DAG.getBitcast(EltVT, AllOnes);
6910 SmallVector<SDValue, 16> VMaskOps(Mask.size(), Zero);
6911 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6913 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6916 if (Mask[i] % Size != i)
6917 return SDValue(); // Not a blend.
6919 V = Mask[i] < Size ? V1 : V2;
6920 else if (V != (Mask[i] < Size ? V1 : V2))
6921 return SDValue(); // Can only let one input through the mask.
6923 VMaskOps[i] = AllOnes;
6926 return SDValue(); // No non-zeroable elements!
6928 SDValue VMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, VMaskOps);
6929 V = DAG.getNode(VT.isFloatingPoint()
6930 ? (unsigned) X86ISD::FAND : (unsigned) ISD::AND,
6935 /// \brief Try to emit a blend instruction for a shuffle using bit math.
6937 /// This is used as a fallback approach when first class blend instructions are
6938 /// unavailable. Currently it is only suitable for integer vectors, but could
6939 /// be generalized for floating point vectors if desirable.
6940 static SDValue lowerVectorShuffleAsBitBlend(SDLoc DL, MVT VT, SDValue V1,
6941 SDValue V2, ArrayRef<int> Mask,
6942 SelectionDAG &DAG) {
6943 assert(VT.isInteger() && "Only supports integer vector types!");
6944 MVT EltVT = VT.getVectorElementType();
6945 int NumEltBits = EltVT.getSizeInBits();
6946 SDValue Zero = DAG.getConstant(0, DL, EltVT);
6947 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
6949 SmallVector<SDValue, 16> MaskOps;
6950 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6951 if (Mask[i] != -1 && Mask[i] != i && Mask[i] != i + Size)
6952 return SDValue(); // Shuffled input!
6953 MaskOps.push_back(Mask[i] < Size ? AllOnes : Zero);
6956 SDValue V1Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, MaskOps);
6957 V1 = DAG.getNode(ISD::AND, DL, VT, V1, V1Mask);
6958 // We have to cast V2 around.
6959 MVT MaskVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
6960 V2 = DAG.getBitcast(VT, DAG.getNode(X86ISD::ANDNP, DL, MaskVT,
6961 DAG.getBitcast(MaskVT, V1Mask),
6962 DAG.getBitcast(MaskVT, V2)));
6963 return DAG.getNode(ISD::OR, DL, VT, V1, V2);
6966 /// \brief Try to emit a blend instruction for a shuffle.
6968 /// This doesn't do any checks for the availability of instructions for blending
6969 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
6970 /// be matched in the backend with the type given. What it does check for is
6971 /// that the shuffle mask is a blend, or convertible into a blend with zero.
6972 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
6973 SDValue V2, ArrayRef<int> Original,
6974 const X86Subtarget *Subtarget,
6975 SelectionDAG &DAG) {
6976 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
6977 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
6978 SmallVector<int, 8> Mask(Original.begin(), Original.end());
6979 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6980 bool ForceV1Zero = false, ForceV2Zero = false;
6982 // Attempt to generate the binary blend mask. If an input is zero then
6983 // we can use any lane.
6984 // TODO: generalize the zero matching to any scalar like isShuffleEquivalent.
6985 unsigned BlendMask = 0;
6986 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6992 if (M == i + Size) {
6993 BlendMask |= 1u << i;
7004 BlendMask |= 1u << i;
7009 return SDValue(); // Shuffled input!
7012 // Create a REAL zero vector - ISD::isBuildVectorAllZeros allows UNDEFs.
7014 V1 = getZeroVector(VT, Subtarget, DAG, DL);
7016 V2 = getZeroVector(VT, Subtarget, DAG, DL);
7018 auto ScaleBlendMask = [](unsigned BlendMask, int Size, int Scale) {
7019 unsigned ScaledMask = 0;
7020 for (int i = 0; i != Size; ++i)
7021 if (BlendMask & (1u << i))
7022 for (int j = 0; j != Scale; ++j)
7023 ScaledMask |= 1u << (i * Scale + j);
7027 switch (VT.SimpleTy) {
7032 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
7033 DAG.getConstant(BlendMask, DL, MVT::i8));
7037 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7041 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
7042 // that instruction.
7043 if (Subtarget->hasAVX2()) {
7044 // Scale the blend by the number of 32-bit dwords per element.
7045 int Scale = VT.getScalarSizeInBits() / 32;
7046 BlendMask = ScaleBlendMask(BlendMask, Mask.size(), Scale);
7047 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
7048 V1 = DAG.getBitcast(BlendVT, V1);
7049 V2 = DAG.getBitcast(BlendVT, V2);
7050 return DAG.getBitcast(
7051 VT, DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
7052 DAG.getConstant(BlendMask, DL, MVT::i8)));
7056 // For integer shuffles we need to expand the mask and cast the inputs to
7057 // v8i16s prior to blending.
7058 int Scale = 8 / VT.getVectorNumElements();
7059 BlendMask = ScaleBlendMask(BlendMask, Mask.size(), Scale);
7060 V1 = DAG.getBitcast(MVT::v8i16, V1);
7061 V2 = DAG.getBitcast(MVT::v8i16, V2);
7062 return DAG.getBitcast(VT,
7063 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
7064 DAG.getConstant(BlendMask, DL, MVT::i8)));
7068 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7069 SmallVector<int, 8> RepeatedMask;
7070 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
7071 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
7072 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
7074 for (int i = 0; i < 8; ++i)
7075 if (RepeatedMask[i] >= 16)
7076 BlendMask |= 1u << i;
7077 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
7078 DAG.getConstant(BlendMask, DL, MVT::i8));
7084 assert((VT.is128BitVector() || Subtarget->hasAVX2()) &&
7085 "256-bit byte-blends require AVX2 support!");
7087 // Attempt to lower to a bitmask if we can. VPAND is faster than VPBLENDVB.
7088 if (SDValue Masked = lowerVectorShuffleAsBitMask(DL, VT, V1, V2, Mask, DAG))
7091 // Scale the blend by the number of bytes per element.
7092 int Scale = VT.getScalarSizeInBits() / 8;
7094 // This form of blend is always done on bytes. Compute the byte vector
7096 MVT BlendVT = MVT::getVectorVT(MVT::i8, VT.getSizeInBits() / 8);
7098 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
7099 // mix of LLVM's code generator and the x86 backend. We tell the code
7100 // generator that boolean values in the elements of an x86 vector register
7101 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
7102 // mapping a select to operand #1, and 'false' mapping to operand #2. The
7103 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
7104 // of the element (the remaining are ignored) and 0 in that high bit would
7105 // mean operand #1 while 1 in the high bit would mean operand #2. So while
7106 // the LLVM model for boolean values in vector elements gets the relevant
7107 // bit set, it is set backwards and over constrained relative to x86's
7109 SmallVector<SDValue, 32> VSELECTMask;
7110 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7111 for (int j = 0; j < Scale; ++j)
7112 VSELECTMask.push_back(
7113 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
7114 : DAG.getConstant(Mask[i] < Size ? -1 : 0, DL,
7117 V1 = DAG.getBitcast(BlendVT, V1);
7118 V2 = DAG.getBitcast(BlendVT, V2);
7119 return DAG.getBitcast(VT, DAG.getNode(ISD::VSELECT, DL, BlendVT,
7120 DAG.getNode(ISD::BUILD_VECTOR, DL,
7121 BlendVT, VSELECTMask),
7126 llvm_unreachable("Not a supported integer vector type!");
7130 /// \brief Try to lower as a blend of elements from two inputs followed by
7131 /// a single-input permutation.
7133 /// This matches the pattern where we can blend elements from two inputs and
7134 /// then reduce the shuffle to a single-input permutation.
7135 static SDValue lowerVectorShuffleAsBlendAndPermute(SDLoc DL, MVT VT, SDValue V1,
7138 SelectionDAG &DAG) {
7139 // We build up the blend mask while checking whether a blend is a viable way
7140 // to reduce the shuffle.
7141 SmallVector<int, 32> BlendMask(Mask.size(), -1);
7142 SmallVector<int, 32> PermuteMask(Mask.size(), -1);
7144 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7148 assert(Mask[i] < Size * 2 && "Shuffle input is out of bounds.");
7150 if (BlendMask[Mask[i] % Size] == -1)
7151 BlendMask[Mask[i] % Size] = Mask[i];
7152 else if (BlendMask[Mask[i] % Size] != Mask[i])
7153 return SDValue(); // Can't blend in the needed input!
7155 PermuteMask[i] = Mask[i] % Size;
7158 SDValue V = DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7159 return DAG.getVectorShuffle(VT, DL, V, DAG.getUNDEF(VT), PermuteMask);
7162 /// \brief Generic routine to decompose a shuffle and blend into indepndent
7163 /// blends and permutes.
7165 /// This matches the extremely common pattern for handling combined
7166 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
7167 /// operations. It will try to pick the best arrangement of shuffles and
7169 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
7173 SelectionDAG &DAG) {
7174 // Shuffle the input elements into the desired positions in V1 and V2 and
7175 // blend them together.
7176 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7177 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7178 SmallVector<int, 32> BlendMask(Mask.size(), -1);
7179 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7180 if (Mask[i] >= 0 && Mask[i] < Size) {
7181 V1Mask[i] = Mask[i];
7183 } else if (Mask[i] >= Size) {
7184 V2Mask[i] = Mask[i] - Size;
7185 BlendMask[i] = i + Size;
7188 // Try to lower with the simpler initial blend strategy unless one of the
7189 // input shuffles would be a no-op. We prefer to shuffle inputs as the
7190 // shuffle may be able to fold with a load or other benefit. However, when
7191 // we'll have to do 2x as many shuffles in order to achieve this, blending
7192 // first is a better strategy.
7193 if (!isNoopShuffleMask(V1Mask) && !isNoopShuffleMask(V2Mask))
7194 if (SDValue BlendPerm =
7195 lowerVectorShuffleAsBlendAndPermute(DL, VT, V1, V2, Mask, DAG))
7198 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7199 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7200 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7203 /// \brief Try to lower a vector shuffle as a byte rotation.
7205 /// SSSE3 has a generic PALIGNR instruction in x86 that will do an arbitrary
7206 /// byte-rotation of the concatenation of two vectors; pre-SSSE3 can use
7207 /// a PSRLDQ/PSLLDQ/POR pattern to get a similar effect. This routine will
7208 /// try to generically lower a vector shuffle through such an pattern. It
7209 /// does not check for the profitability of lowering either as PALIGNR or
7210 /// PSRLDQ/PSLLDQ/POR, only whether the mask is valid to lower in that form.
7211 /// This matches shuffle vectors that look like:
7213 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
7215 /// Essentially it concatenates V1 and V2, shifts right by some number of
7216 /// elements, and takes the low elements as the result. Note that while this is
7217 /// specified as a *right shift* because x86 is little-endian, it is a *left
7218 /// rotate* of the vector lanes.
7219 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
7222 const X86Subtarget *Subtarget,
7223 SelectionDAG &DAG) {
7224 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7226 int NumElts = Mask.size();
7227 int NumLanes = VT.getSizeInBits() / 128;
7228 int NumLaneElts = NumElts / NumLanes;
7230 // We need to detect various ways of spelling a rotation:
7231 // [11, 12, 13, 14, 15, 0, 1, 2]
7232 // [-1, 12, 13, 14, -1, -1, 1, -1]
7233 // [-1, -1, -1, -1, -1, -1, 1, 2]
7234 // [ 3, 4, 5, 6, 7, 8, 9, 10]
7235 // [-1, 4, 5, 6, -1, -1, 9, -1]
7236 // [-1, 4, 5, 6, -1, -1, -1, -1]
7239 for (int l = 0; l < NumElts; l += NumLaneElts) {
7240 for (int i = 0; i < NumLaneElts; ++i) {
7241 if (Mask[l + i] == -1)
7243 assert(Mask[l + i] >= 0 && "Only -1 is a valid negative mask element!");
7245 // Get the mod-Size index and lane correct it.
7246 int LaneIdx = (Mask[l + i] % NumElts) - l;
7247 // Make sure it was in this lane.
7248 if (LaneIdx < 0 || LaneIdx >= NumLaneElts)
7251 // Determine where a rotated vector would have started.
7252 int StartIdx = i - LaneIdx;
7254 // The identity rotation isn't interesting, stop.
7257 // If we found the tail of a vector the rotation must be the missing
7258 // front. If we found the head of a vector, it must be how much of the
7260 int CandidateRotation = StartIdx < 0 ? -StartIdx : NumLaneElts - StartIdx;
7263 Rotation = CandidateRotation;
7264 else if (Rotation != CandidateRotation)
7265 // The rotations don't match, so we can't match this mask.
7268 // Compute which value this mask is pointing at.
7269 SDValue MaskV = Mask[l + i] < NumElts ? V1 : V2;
7271 // Compute which of the two target values this index should be assigned
7272 // to. This reflects whether the high elements are remaining or the low
7273 // elements are remaining.
7274 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
7276 // Either set up this value if we've not encountered it before, or check
7277 // that it remains consistent.
7280 else if (TargetV != MaskV)
7281 // This may be a rotation, but it pulls from the inputs in some
7282 // unsupported interleaving.
7287 // Check that we successfully analyzed the mask, and normalize the results.
7288 assert(Rotation != 0 && "Failed to locate a viable rotation!");
7289 assert((Lo || Hi) && "Failed to find a rotated input vector!");
7295 // The actual rotate instruction rotates bytes, so we need to scale the
7296 // rotation based on how many bytes are in the vector lane.
7297 int Scale = 16 / NumLaneElts;
7299 // SSSE3 targets can use the palignr instruction.
7300 if (Subtarget->hasSSSE3()) {
7301 // Cast the inputs to i8 vector of correct length to match PALIGNR.
7302 MVT AlignVT = MVT::getVectorVT(MVT::i8, 16 * NumLanes);
7303 Lo = DAG.getBitcast(AlignVT, Lo);
7304 Hi = DAG.getBitcast(AlignVT, Hi);
7306 return DAG.getBitcast(
7307 VT, DAG.getNode(X86ISD::PALIGNR, DL, AlignVT, Lo, Hi,
7308 DAG.getConstant(Rotation * Scale, DL, MVT::i8)));
7311 assert(VT.is128BitVector() &&
7312 "Rotate-based lowering only supports 128-bit lowering!");
7313 assert(Mask.size() <= 16 &&
7314 "Can shuffle at most 16 bytes in a 128-bit vector!");
7316 // Default SSE2 implementation
7317 int LoByteShift = 16 - Rotation * Scale;
7318 int HiByteShift = Rotation * Scale;
7320 // Cast the inputs to v2i64 to match PSLLDQ/PSRLDQ.
7321 Lo = DAG.getBitcast(MVT::v2i64, Lo);
7322 Hi = DAG.getBitcast(MVT::v2i64, Hi);
7324 SDValue LoShift = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, Lo,
7325 DAG.getConstant(LoByteShift, DL, MVT::i8));
7326 SDValue HiShift = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, Hi,
7327 DAG.getConstant(HiByteShift, DL, MVT::i8));
7328 return DAG.getBitcast(VT,
7329 DAG.getNode(ISD::OR, DL, MVT::v2i64, LoShift, HiShift));
7332 /// \brief Try to lower a vector shuffle as a bit shift (shifts in zeros).
7334 /// Attempts to match a shuffle mask against the PSLL(W/D/Q/DQ) and
7335 /// PSRL(W/D/Q/DQ) SSE2 and AVX2 logical bit-shift instructions. The function
7336 /// matches elements from one of the input vectors shuffled to the left or
7337 /// right with zeroable elements 'shifted in'. It handles both the strictly
7338 /// bit-wise element shifts and the byte shift across an entire 128-bit double
7341 /// PSHL : (little-endian) left bit shift.
7342 /// [ zz, 0, zz, 2 ]
7343 /// [ -1, 4, zz, -1 ]
7344 /// PSRL : (little-endian) right bit shift.
7346 /// [ -1, -1, 7, zz]
7347 /// PSLLDQ : (little-endian) left byte shift
7348 /// [ zz, 0, 1, 2, 3, 4, 5, 6]
7349 /// [ zz, zz, -1, -1, 2, 3, 4, -1]
7350 /// [ zz, zz, zz, zz, zz, zz, -1, 1]
7351 /// PSRLDQ : (little-endian) right byte shift
7352 /// [ 5, 6, 7, zz, zz, zz, zz, zz]
7353 /// [ -1, 5, 6, 7, zz, zz, zz, zz]
7354 /// [ 1, 2, -1, -1, -1, -1, zz, zz]
7355 static SDValue lowerVectorShuffleAsShift(SDLoc DL, MVT VT, SDValue V1,
7356 SDValue V2, ArrayRef<int> Mask,
7357 SelectionDAG &DAG) {
7358 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7360 int Size = Mask.size();
7361 assert(Size == (int)VT.getVectorNumElements() && "Unexpected mask size");
7363 auto CheckZeros = [&](int Shift, int Scale, bool Left) {
7364 for (int i = 0; i < Size; i += Scale)
7365 for (int j = 0; j < Shift; ++j)
7366 if (!Zeroable[i + j + (Left ? 0 : (Scale - Shift))])
7372 auto MatchShift = [&](int Shift, int Scale, bool Left, SDValue V) {
7373 for (int i = 0; i != Size; i += Scale) {
7374 unsigned Pos = Left ? i + Shift : i;
7375 unsigned Low = Left ? i : i + Shift;
7376 unsigned Len = Scale - Shift;
7377 if (!isSequentialOrUndefInRange(Mask, Pos, Len,
7378 Low + (V == V1 ? 0 : Size)))
7382 int ShiftEltBits = VT.getScalarSizeInBits() * Scale;
7383 bool ByteShift = ShiftEltBits > 64;
7384 unsigned OpCode = Left ? (ByteShift ? X86ISD::VSHLDQ : X86ISD::VSHLI)
7385 : (ByteShift ? X86ISD::VSRLDQ : X86ISD::VSRLI);
7386 int ShiftAmt = Shift * VT.getScalarSizeInBits() / (ByteShift ? 8 : 1);
7388 // Normalize the scale for byte shifts to still produce an i64 element
7390 Scale = ByteShift ? Scale / 2 : Scale;
7392 // We need to round trip through the appropriate type for the shift.
7393 MVT ShiftSVT = MVT::getIntegerVT(VT.getScalarSizeInBits() * Scale);
7394 MVT ShiftVT = MVT::getVectorVT(ShiftSVT, Size / Scale);
7395 assert(DAG.getTargetLoweringInfo().isTypeLegal(ShiftVT) &&
7396 "Illegal integer vector type");
7397 V = DAG.getBitcast(ShiftVT, V);
7399 V = DAG.getNode(OpCode, DL, ShiftVT, V,
7400 DAG.getConstant(ShiftAmt, DL, MVT::i8));
7401 return DAG.getBitcast(VT, V);
7404 // SSE/AVX supports logical shifts up to 64-bit integers - so we can just
7405 // keep doubling the size of the integer elements up to that. We can
7406 // then shift the elements of the integer vector by whole multiples of
7407 // their width within the elements of the larger integer vector. Test each
7408 // multiple to see if we can find a match with the moved element indices
7409 // and that the shifted in elements are all zeroable.
7410 for (int Scale = 2; Scale * VT.getScalarSizeInBits() <= 128; Scale *= 2)
7411 for (int Shift = 1; Shift != Scale; ++Shift)
7412 for (bool Left : {true, false})
7413 if (CheckZeros(Shift, Scale, Left))
7414 for (SDValue V : {V1, V2})
7415 if (SDValue Match = MatchShift(Shift, Scale, Left, V))
7422 /// \brief Try to lower a vector shuffle using SSE4a EXTRQ/INSERTQ.
7423 static SDValue lowerVectorShuffleWithSSE4A(SDLoc DL, MVT VT, SDValue V1,
7424 SDValue V2, ArrayRef<int> Mask,
7425 SelectionDAG &DAG) {
7426 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7427 assert(!Zeroable.all() && "Fully zeroable shuffle mask");
7429 int Size = Mask.size();
7430 int HalfSize = Size / 2;
7431 assert(Size == (int)VT.getVectorNumElements() && "Unexpected mask size");
7433 // Upper half must be undefined.
7434 if (!isUndefInRange(Mask, HalfSize, HalfSize))
7437 // EXTRQ: Extract Len elements from lower half of source, starting at Idx.
7438 // Remainder of lower half result is zero and upper half is all undef.
7439 auto LowerAsEXTRQ = [&]() {
7440 // Determine the extraction length from the part of the
7441 // lower half that isn't zeroable.
7443 for (; Len > 0; --Len)
7444 if (!Zeroable[Len - 1])
7446 assert(Len > 0 && "Zeroable shuffle mask");
7448 // Attempt to match first Len sequential elements from the lower half.
7451 for (int i = 0; i != Len; ++i) {
7455 SDValue &V = (M < Size ? V1 : V2);
7458 // The extracted elements must start at a valid index and all mask
7459 // elements must be in the lower half.
7460 if (i > M || M >= HalfSize)
7463 if (Idx < 0 || (Src == V && Idx == (M - i))) {
7474 assert((Idx + Len) <= HalfSize && "Illegal extraction mask");
7475 int BitLen = (Len * VT.getScalarSizeInBits()) & 0x3f;
7476 int BitIdx = (Idx * VT.getScalarSizeInBits()) & 0x3f;
7477 return DAG.getNode(X86ISD::EXTRQI, DL, VT, Src,
7478 DAG.getConstant(BitLen, DL, MVT::i8),
7479 DAG.getConstant(BitIdx, DL, MVT::i8));
7482 if (SDValue ExtrQ = LowerAsEXTRQ())
7485 // INSERTQ: Extract lowest Len elements from lower half of second source and
7486 // insert over first source, starting at Idx.
7487 // { A[0], .., A[Idx-1], B[0], .., B[Len-1], A[Idx+Len], .., UNDEF, ... }
7488 auto LowerAsInsertQ = [&]() {
7489 for (int Idx = 0; Idx != HalfSize; ++Idx) {
7492 // Attempt to match first source from mask before insertion point.
7493 if (isUndefInRange(Mask, 0, Idx)) {
7495 } else if (isSequentialOrUndefInRange(Mask, 0, Idx, 0)) {
7497 } else if (isSequentialOrUndefInRange(Mask, 0, Idx, Size)) {
7503 // Extend the extraction length looking to match both the insertion of
7504 // the second source and the remaining elements of the first.
7505 for (int Hi = Idx + 1; Hi <= HalfSize; ++Hi) {
7510 if (isSequentialOrUndefInRange(Mask, Idx, Len, 0)) {
7512 } else if (isSequentialOrUndefInRange(Mask, Idx, Len, Size)) {
7518 // Match the remaining elements of the lower half.
7519 if (isUndefInRange(Mask, Hi, HalfSize - Hi)) {
7521 } else if ((!Base || (Base == V1)) &&
7522 isSequentialOrUndefInRange(Mask, Hi, HalfSize - Hi, Hi)) {
7524 } else if ((!Base || (Base == V2)) &&
7525 isSequentialOrUndefInRange(Mask, Hi, HalfSize - Hi,
7532 // We may not have a base (first source) - this can safely be undefined.
7534 Base = DAG.getUNDEF(VT);
7536 int BitLen = (Len * VT.getScalarSizeInBits()) & 0x3f;
7537 int BitIdx = (Idx * VT.getScalarSizeInBits()) & 0x3f;
7538 return DAG.getNode(X86ISD::INSERTQI, DL, VT, Base, Insert,
7539 DAG.getConstant(BitLen, DL, MVT::i8),
7540 DAG.getConstant(BitIdx, DL, MVT::i8));
7547 if (SDValue InsertQ = LowerAsInsertQ())
7553 /// \brief Lower a vector shuffle as a zero or any extension.
7555 /// Given a specific number of elements, element bit width, and extension
7556 /// stride, produce either a zero or any extension based on the available
7557 /// features of the subtarget. The extended elements are consecutive and
7558 /// begin and can start from an offseted element index in the input; to
7559 /// avoid excess shuffling the offset must either being in the bottom lane
7560 /// or at the start of a higher lane. All extended elements must be from
7562 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7563 SDLoc DL, MVT VT, int Scale, int Offset, bool AnyExt, SDValue InputV,
7564 ArrayRef<int> Mask, const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7565 assert(Scale > 1 && "Need a scale to extend.");
7566 int EltBits = VT.getScalarSizeInBits();
7567 int NumElements = VT.getVectorNumElements();
7568 int NumEltsPerLane = 128 / EltBits;
7569 int OffsetLane = Offset / NumEltsPerLane;
7570 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
7571 "Only 8, 16, and 32 bit elements can be extended.");
7572 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
7573 assert(0 <= Offset && "Extension offset must be positive.");
7574 assert((Offset < NumEltsPerLane || Offset % NumEltsPerLane == 0) &&
7575 "Extension offset must be in the first lane or start an upper lane.");
7577 // Check that an index is in same lane as the base offset.
7578 auto SafeOffset = [&](int Idx) {
7579 return OffsetLane == (Idx / NumEltsPerLane);
7582 // Shift along an input so that the offset base moves to the first element.
7583 auto ShuffleOffset = [&](SDValue V) {
7587 SmallVector<int, 8> ShMask((unsigned)NumElements, -1);
7588 for (int i = 0; i * Scale < NumElements; ++i) {
7589 int SrcIdx = i + Offset;
7590 ShMask[i] = SafeOffset(SrcIdx) ? SrcIdx : -1;
7592 return DAG.getVectorShuffle(VT, DL, V, DAG.getUNDEF(VT), ShMask);
7595 // Found a valid zext mask! Try various lowering strategies based on the
7596 // input type and available ISA extensions.
7597 if (Subtarget->hasSSE41()) {
7598 // Not worth offseting 128-bit vectors if scale == 2, a pattern using
7599 // PUNPCK will catch this in a later shuffle match.
7600 if (Offset && Scale == 2 && VT.is128BitVector())
7602 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
7603 NumElements / Scale);
7604 InputV = DAG.getNode(X86ISD::VZEXT, DL, ExtVT, ShuffleOffset(InputV));
7605 return DAG.getBitcast(VT, InputV);
7608 assert(VT.is128BitVector() && "Only 128-bit vectors can be extended.");
7610 // For any extends we can cheat for larger element sizes and use shuffle
7611 // instructions that can fold with a load and/or copy.
7612 if (AnyExt && EltBits == 32) {
7613 int PSHUFDMask[4] = {Offset, -1, SafeOffset(Offset + 1) ? Offset + 1 : -1,
7615 return DAG.getBitcast(
7616 VT, DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7617 DAG.getBitcast(MVT::v4i32, InputV),
7618 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
7620 if (AnyExt && EltBits == 16 && Scale > 2) {
7621 int PSHUFDMask[4] = {Offset / 2, -1,
7622 SafeOffset(Offset + 1) ? (Offset + 1) / 2 : -1, -1};
7623 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7624 DAG.getBitcast(MVT::v4i32, InputV),
7625 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG));
7626 int PSHUFWMask[4] = {1, -1, -1, -1};
7627 unsigned OddEvenOp = (Offset & 1 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW);
7628 return DAG.getBitcast(
7629 VT, DAG.getNode(OddEvenOp, DL, MVT::v8i16,
7630 DAG.getBitcast(MVT::v8i16, InputV),
7631 getV4X86ShuffleImm8ForMask(PSHUFWMask, DL, DAG)));
7634 // The SSE4A EXTRQ instruction can efficiently extend the first 2 lanes
7636 if ((Scale * EltBits) == 64 && EltBits < 32 && Subtarget->hasSSE4A()) {
7637 assert(NumElements == (int)Mask.size() && "Unexpected shuffle mask size!");
7638 assert(VT.is128BitVector() && "Unexpected vector width!");
7640 int LoIdx = Offset * EltBits;
7641 SDValue Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7642 DAG.getNode(X86ISD::EXTRQI, DL, VT, InputV,
7643 DAG.getConstant(EltBits, DL, MVT::i8),
7644 DAG.getConstant(LoIdx, DL, MVT::i8)));
7646 if (isUndefInRange(Mask, NumElements / 2, NumElements / 2) ||
7647 !SafeOffset(Offset + 1))
7648 return DAG.getNode(ISD::BITCAST, DL, VT, Lo);
7650 int HiIdx = (Offset + 1) * EltBits;
7651 SDValue Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7652 DAG.getNode(X86ISD::EXTRQI, DL, VT, InputV,
7653 DAG.getConstant(EltBits, DL, MVT::i8),
7654 DAG.getConstant(HiIdx, DL, MVT::i8)));
7655 return DAG.getNode(ISD::BITCAST, DL, VT,
7656 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, Lo, Hi));
7659 // If this would require more than 2 unpack instructions to expand, use
7660 // pshufb when available. We can only use more than 2 unpack instructions
7661 // when zero extending i8 elements which also makes it easier to use pshufb.
7662 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
7663 assert(NumElements == 16 && "Unexpected byte vector width!");
7664 SDValue PSHUFBMask[16];
7665 for (int i = 0; i < 16; ++i) {
7666 int Idx = Offset + (i / Scale);
7667 PSHUFBMask[i] = DAG.getConstant(
7668 (i % Scale == 0 && SafeOffset(Idx)) ? Idx : 0x80, DL, MVT::i8);
7670 InputV = DAG.getBitcast(MVT::v16i8, InputV);
7671 return DAG.getBitcast(VT,
7672 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
7673 DAG.getNode(ISD::BUILD_VECTOR, DL,
7674 MVT::v16i8, PSHUFBMask)));
7677 // If we are extending from an offset, ensure we start on a boundary that
7678 // we can unpack from.
7679 int AlignToUnpack = Offset % (NumElements / Scale);
7680 if (AlignToUnpack) {
7681 SmallVector<int, 8> ShMask((unsigned)NumElements, -1);
7682 for (int i = AlignToUnpack; i < NumElements; ++i)
7683 ShMask[i - AlignToUnpack] = i;
7684 InputV = DAG.getVectorShuffle(VT, DL, InputV, DAG.getUNDEF(VT), ShMask);
7685 Offset -= AlignToUnpack;
7688 // Otherwise emit a sequence of unpacks.
7690 unsigned UnpackLoHi = X86ISD::UNPCKL;
7691 if (Offset >= (NumElements / 2)) {
7692 UnpackLoHi = X86ISD::UNPCKH;
7693 Offset -= (NumElements / 2);
7696 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7697 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
7698 : getZeroVector(InputVT, Subtarget, DAG, DL);
7699 InputV = DAG.getBitcast(InputVT, InputV);
7700 InputV = DAG.getNode(UnpackLoHi, DL, InputVT, InputV, Ext);
7704 } while (Scale > 1);
7705 return DAG.getBitcast(VT, InputV);
7708 /// \brief Try to lower a vector shuffle as a zero extension on any microarch.
7710 /// This routine will try to do everything in its power to cleverly lower
7711 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
7712 /// check for the profitability of this lowering, it tries to aggressively
7713 /// match this pattern. It will use all of the micro-architectural details it
7714 /// can to emit an efficient lowering. It handles both blends with all-zero
7715 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
7716 /// masking out later).
7718 /// The reason we have dedicated lowering for zext-style shuffles is that they
7719 /// are both incredibly common and often quite performance sensitive.
7720 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
7721 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7722 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7723 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7725 int Bits = VT.getSizeInBits();
7726 int NumLanes = Bits / 128;
7727 int NumElements = VT.getVectorNumElements();
7728 int NumEltsPerLane = NumElements / NumLanes;
7729 assert(VT.getScalarSizeInBits() <= 32 &&
7730 "Exceeds 32-bit integer zero extension limit");
7731 assert((int)Mask.size() == NumElements && "Unexpected shuffle mask size");
7733 // Define a helper function to check a particular ext-scale and lower to it if
7735 auto Lower = [&](int Scale) -> SDValue {
7740 for (int i = 0; i < NumElements; ++i) {
7743 continue; // Valid anywhere but doesn't tell us anything.
7744 if (i % Scale != 0) {
7745 // Each of the extended elements need to be zeroable.
7749 // We no longer are in the anyext case.
7754 // Each of the base elements needs to be consecutive indices into the
7755 // same input vector.
7756 SDValue V = M < NumElements ? V1 : V2;
7757 M = M % NumElements;
7760 Offset = M - (i / Scale);
7761 } else if (InputV != V)
7762 return SDValue(); // Flip-flopping inputs.
7764 // Offset must start in the lowest 128-bit lane or at the start of an
7766 // FIXME: Is it ever worth allowing a negative base offset?
7767 if (!((0 <= Offset && Offset < NumEltsPerLane) ||
7768 (Offset % NumEltsPerLane) == 0))
7771 // If we are offsetting, all referenced entries must come from the same
7773 if (Offset && (Offset / NumEltsPerLane) != (M / NumEltsPerLane))
7776 if ((M % NumElements) != (Offset + (i / Scale)))
7777 return SDValue(); // Non-consecutive strided elements.
7781 // If we fail to find an input, we have a zero-shuffle which should always
7782 // have already been handled.
7783 // FIXME: Maybe handle this here in case during blending we end up with one?
7787 // If we are offsetting, don't extend if we only match a single input, we
7788 // can always do better by using a basic PSHUF or PUNPCK.
7789 if (Offset != 0 && Matches < 2)
7792 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7793 DL, VT, Scale, Offset, AnyExt, InputV, Mask, Subtarget, DAG);
7796 // The widest scale possible for extending is to a 64-bit integer.
7797 assert(Bits % 64 == 0 &&
7798 "The number of bits in a vector must be divisible by 64 on x86!");
7799 int NumExtElements = Bits / 64;
7801 // Each iteration, try extending the elements half as much, but into twice as
7803 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7804 assert(NumElements % NumExtElements == 0 &&
7805 "The input vector size must be divisible by the extended size.");
7806 if (SDValue V = Lower(NumElements / NumExtElements))
7810 // General extends failed, but 128-bit vectors may be able to use MOVQ.
7814 // Returns one of the source operands if the shuffle can be reduced to a
7815 // MOVQ, copying the lower 64-bits and zero-extending to the upper 64-bits.
7816 auto CanZExtLowHalf = [&]() {
7817 for (int i = NumElements / 2; i != NumElements; ++i)
7820 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, 0))
7822 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, NumElements))
7827 if (SDValue V = CanZExtLowHalf()) {
7828 V = DAG.getBitcast(MVT::v2i64, V);
7829 V = DAG.getNode(X86ISD::VZEXT_MOVL, DL, MVT::v2i64, V);
7830 return DAG.getBitcast(VT, V);
7833 // No viable ext lowering found.
7837 /// \brief Try to get a scalar value for a specific element of a vector.
7839 /// Looks through BUILD_VECTOR and SCALAR_TO_VECTOR nodes to find a scalar.
7840 static SDValue getScalarValueForVectorElement(SDValue V, int Idx,
7841 SelectionDAG &DAG) {
7842 MVT VT = V.getSimpleValueType();
7843 MVT EltVT = VT.getVectorElementType();
7844 while (V.getOpcode() == ISD::BITCAST)
7845 V = V.getOperand(0);
7846 // If the bitcasts shift the element size, we can't extract an equivalent
7848 MVT NewVT = V.getSimpleValueType();
7849 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
7852 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7853 (Idx == 0 && V.getOpcode() == ISD::SCALAR_TO_VECTOR)) {
7854 // Ensure the scalar operand is the same size as the destination.
7855 // FIXME: Add support for scalar truncation where possible.
7856 SDValue S = V.getOperand(Idx);
7857 if (EltVT.getSizeInBits() == S.getSimpleValueType().getSizeInBits())
7858 return DAG.getNode(ISD::BITCAST, SDLoc(V), EltVT, S);
7864 /// \brief Helper to test for a load that can be folded with x86 shuffles.
7866 /// This is particularly important because the set of instructions varies
7867 /// significantly based on whether the operand is a load or not.
7868 static bool isShuffleFoldableLoad(SDValue V) {
7869 while (V.getOpcode() == ISD::BITCAST)
7870 V = V.getOperand(0);
7872 return ISD::isNON_EXTLoad(V.getNode());
7875 /// \brief Try to lower insertion of a single element into a zero vector.
7877 /// This is a common pattern that we have especially efficient patterns to lower
7878 /// across all subtarget feature sets.
7879 static SDValue lowerVectorShuffleAsElementInsertion(
7880 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7881 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7882 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7884 MVT EltVT = VT.getVectorElementType();
7886 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7887 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7889 bool IsV1Zeroable = true;
7890 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7891 if (i != V2Index && !Zeroable[i]) {
7892 IsV1Zeroable = false;
7896 // Check for a single input from a SCALAR_TO_VECTOR node.
7897 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7898 // all the smarts here sunk into that routine. However, the current
7899 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7900 // vector shuffle lowering is dead.
7901 SDValue V2S = getScalarValueForVectorElement(V2, Mask[V2Index] - Mask.size(),
7903 if (V2S && DAG.getTargetLoweringInfo().isTypeLegal(V2S.getValueType())) {
7904 // We need to zext the scalar if it is smaller than an i32.
7905 V2S = DAG.getBitcast(EltVT, V2S);
7906 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7907 // Using zext to expand a narrow element won't work for non-zero
7912 // Zero-extend directly to i32.
7914 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7916 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);
7917 } else if (Mask[V2Index] != (int)Mask.size() || EltVT == MVT::i8 ||
7918 EltVT == MVT::i16) {
7919 // Either not inserting from the low element of the input or the input
7920 // element size is too small to use VZEXT_MOVL to clear the high bits.
7924 if (!IsV1Zeroable) {
7925 // If V1 can't be treated as a zero vector we have fewer options to lower
7926 // this. We can't support integer vectors or non-zero targets cheaply, and
7927 // the V1 elements can't be permuted in any way.
7928 assert(VT == ExtVT && "Cannot change extended type when non-zeroable!");
7929 if (!VT.isFloatingPoint() || V2Index != 0)
7931 SmallVector<int, 8> V1Mask(Mask.begin(), Mask.end());
7932 V1Mask[V2Index] = -1;
7933 if (!isNoopShuffleMask(V1Mask))
7935 // This is essentially a special case blend operation, but if we have
7936 // general purpose blend operations, they are always faster. Bail and let
7937 // the rest of the lowering handle these as blends.
7938 if (Subtarget->hasSSE41())
7941 // Otherwise, use MOVSD or MOVSS.
7942 assert((EltVT == MVT::f32 || EltVT == MVT::f64) &&
7943 "Only two types of floating point element types to handle!");
7944 return DAG.getNode(EltVT == MVT::f32 ? X86ISD::MOVSS : X86ISD::MOVSD, DL,
7948 // This lowering only works for the low element with floating point vectors.
7949 if (VT.isFloatingPoint() && V2Index != 0)
7952 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2);
7954 V2 = DAG.getBitcast(VT, V2);
7957 // If we have 4 or fewer lanes we can cheaply shuffle the element into
7958 // the desired position. Otherwise it is more efficient to do a vector
7959 // shift left. We know that we can do a vector shift left because all
7960 // the inputs are zero.
7961 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
7962 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
7963 V2Shuffle[V2Index] = 0;
7964 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
7966 V2 = DAG.getBitcast(MVT::v2i64, V2);
7968 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
7969 DAG.getConstant(V2Index * EltVT.getSizeInBits() / 8, DL,
7970 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(
7971 DAG.getDataLayout(), VT)));
7972 V2 = DAG.getBitcast(VT, V2);
7978 /// \brief Try to lower broadcast of a single - truncated - integer element,
7979 /// coming from a scalar_to_vector/build_vector node \p V0 with larger elements.
7981 /// This assumes we have AVX2.
7982 static SDValue lowerVectorShuffleAsTruncBroadcast(SDLoc DL, MVT VT, SDValue V0,
7984 const X86Subtarget *Subtarget,
7985 SelectionDAG &DAG) {
7986 assert(Subtarget->hasAVX2() &&
7987 "We can only lower integer broadcasts with AVX2!");
7989 EVT EltVT = VT.getVectorElementType();
7990 EVT V0VT = V0.getValueType();
7992 assert(VT.isInteger() && "Unexpected non-integer trunc broadcast!");
7993 assert(V0VT.isVector() && "Unexpected non-vector vector-sized value!");
7995 EVT V0EltVT = V0VT.getVectorElementType();
7996 if (!V0EltVT.isInteger())
7999 const unsigned EltSize = EltVT.getSizeInBits();
8000 const unsigned V0EltSize = V0EltVT.getSizeInBits();
8002 // This is only a truncation if the original element type is larger.
8003 if (V0EltSize <= EltSize)
8006 assert(((V0EltSize % EltSize) == 0) &&
8007 "Scalar type sizes must all be powers of 2 on x86!");
8009 const unsigned V0Opc = V0.getOpcode();
8010 const unsigned Scale = V0EltSize / EltSize;
8011 const unsigned V0BroadcastIdx = BroadcastIdx / Scale;
8013 if ((V0Opc != ISD::SCALAR_TO_VECTOR || V0BroadcastIdx != 0) &&
8014 V0Opc != ISD::BUILD_VECTOR)
8017 SDValue Scalar = V0.getOperand(V0BroadcastIdx);
8019 // If we're extracting non-least-significant bits, shift so we can truncate.
8020 // Hopefully, we can fold away the trunc/srl/load into the broadcast.
8021 // Even if we can't (and !isShuffleFoldableLoad(Scalar)), prefer
8022 // vpbroadcast+vmovd+shr to vpshufb(m)+vmovd.
8023 if (const int OffsetIdx = BroadcastIdx % Scale)
8024 Scalar = DAG.getNode(ISD::SRL, DL, Scalar.getValueType(), Scalar,
8025 DAG.getConstant(OffsetIdx * EltSize, DL, Scalar.getValueType()));
8027 return DAG.getNode(X86ISD::VBROADCAST, DL, VT,
8028 DAG.getNode(ISD::TRUNCATE, DL, EltVT, Scalar));
8031 /// \brief Try to lower broadcast of a single element.
8033 /// For convenience, this code also bundles all of the subtarget feature set
8034 /// filtering. While a little annoying to re-dispatch on type here, there isn't
8035 /// a convenient way to factor it out.
8036 static SDValue lowerVectorShuffleAsBroadcast(SDLoc DL, MVT VT, SDValue V,
8038 const X86Subtarget *Subtarget,
8039 SelectionDAG &DAG) {
8040 if (!Subtarget->hasAVX())
8042 if (VT.isInteger() && !Subtarget->hasAVX2())
8045 // Check that the mask is a broadcast.
8046 int BroadcastIdx = -1;
8048 if (M >= 0 && BroadcastIdx == -1)
8050 else if (M >= 0 && M != BroadcastIdx)
8053 assert(BroadcastIdx < (int)Mask.size() && "We only expect to be called with "
8054 "a sorted mask where the broadcast "
8057 // Go up the chain of (vector) values to find a scalar load that we can
8058 // combine with the broadcast.
8060 switch (V.getOpcode()) {
8061 case ISD::CONCAT_VECTORS: {
8062 int OperandSize = Mask.size() / V.getNumOperands();
8063 V = V.getOperand(BroadcastIdx / OperandSize);
8064 BroadcastIdx %= OperandSize;
8068 case ISD::INSERT_SUBVECTOR: {
8069 SDValue VOuter = V.getOperand(0), VInner = V.getOperand(1);
8070 auto ConstantIdx = dyn_cast<ConstantSDNode>(V.getOperand(2));
8074 int BeginIdx = (int)ConstantIdx->getZExtValue();
8076 BeginIdx + (int)VInner.getSimpleValueType().getVectorNumElements();
8077 if (BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx) {
8078 BroadcastIdx -= BeginIdx;
8089 // Check if this is a broadcast of a scalar. We special case lowering
8090 // for scalars so that we can more effectively fold with loads.
8091 // First, look through bitcast: if the original value has a larger element
8092 // type than the shuffle, the broadcast element is in essence truncated.
8093 // Make that explicit to ease folding.
8094 if (V.getOpcode() == ISD::BITCAST && VT.isInteger())
8095 if (SDValue TruncBroadcast = lowerVectorShuffleAsTruncBroadcast(
8096 DL, VT, V.getOperand(0), BroadcastIdx, Subtarget, DAG))
8097 return TruncBroadcast;
8099 // Also check the simpler case, where we can directly reuse the scalar.
8100 if (V.getOpcode() == ISD::BUILD_VECTOR ||
8101 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)) {
8102 V = V.getOperand(BroadcastIdx);
8104 // If the scalar isn't a load, we can't broadcast from it in AVX1.
8105 // Only AVX2 has register broadcasts.
8106 if (!Subtarget->hasAVX2() && !isShuffleFoldableLoad(V))
8108 } else if (BroadcastIdx != 0 || !Subtarget->hasAVX2()) {
8109 // We can't broadcast from a vector register without AVX2, and we can only
8110 // broadcast from the zero-element of a vector register.
8114 return DAG.getNode(X86ISD::VBROADCAST, DL, VT, V);
8117 // Check for whether we can use INSERTPS to perform the shuffle. We only use
8118 // INSERTPS when the V1 elements are already in the correct locations
8119 // because otherwise we can just always use two SHUFPS instructions which
8120 // are much smaller to encode than a SHUFPS and an INSERTPS. We can also
8121 // perform INSERTPS if a single V1 element is out of place and all V2
8122 // elements are zeroable.
8123 static SDValue lowerVectorShuffleAsInsertPS(SDValue Op, SDValue V1, SDValue V2,
8125 SelectionDAG &DAG) {
8126 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8127 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8128 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8129 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8131 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
8134 int V1DstIndex = -1;
8135 int V2DstIndex = -1;
8136 bool V1UsedInPlace = false;
8138 for (int i = 0; i < 4; ++i) {
8139 // Synthesize a zero mask from the zeroable elements (includes undefs).
8145 // Flag if we use any V1 inputs in place.
8147 V1UsedInPlace = true;
8151 // We can only insert a single non-zeroable element.
8152 if (V1DstIndex != -1 || V2DstIndex != -1)
8156 // V1 input out of place for insertion.
8159 // V2 input for insertion.
8164 // Don't bother if we have no (non-zeroable) element for insertion.
8165 if (V1DstIndex == -1 && V2DstIndex == -1)
8168 // Determine element insertion src/dst indices. The src index is from the
8169 // start of the inserted vector, not the start of the concatenated vector.
8170 unsigned V2SrcIndex = 0;
8171 if (V1DstIndex != -1) {
8172 // If we have a V1 input out of place, we use V1 as the V2 element insertion
8173 // and don't use the original V2 at all.
8174 V2SrcIndex = Mask[V1DstIndex];
8175 V2DstIndex = V1DstIndex;
8178 V2SrcIndex = Mask[V2DstIndex] - 4;
8181 // If no V1 inputs are used in place, then the result is created only from
8182 // the zero mask and the V2 insertion - so remove V1 dependency.
8184 V1 = DAG.getUNDEF(MVT::v4f32);
8186 unsigned InsertPSMask = V2SrcIndex << 6 | V2DstIndex << 4 | ZMask;
8187 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
8189 // Insert the V2 element into the desired position.
8191 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
8192 DAG.getConstant(InsertPSMask, DL, MVT::i8));
8195 /// \brief Try to lower a shuffle as a permute of the inputs followed by an
8196 /// UNPCK instruction.
8198 /// This specifically targets cases where we end up with alternating between
8199 /// the two inputs, and so can permute them into something that feeds a single
8200 /// UNPCK instruction. Note that this routine only targets integer vectors
8201 /// because for floating point vectors we have a generalized SHUFPS lowering
8202 /// strategy that handles everything that doesn't *exactly* match an unpack,
8203 /// making this clever lowering unnecessary.
8204 static SDValue lowerVectorShuffleAsPermuteAndUnpack(SDLoc DL, MVT VT,
8205 SDValue V1, SDValue V2,
8207 SelectionDAG &DAG) {
8208 assert(!VT.isFloatingPoint() &&
8209 "This routine only supports integer vectors.");
8210 assert(!isSingleInputShuffleMask(Mask) &&
8211 "This routine should only be used when blending two inputs.");
8212 assert(Mask.size() >= 2 && "Single element masks are invalid.");
8214 int Size = Mask.size();
8216 int NumLoInputs = std::count_if(Mask.begin(), Mask.end(), [Size](int M) {
8217 return M >= 0 && M % Size < Size / 2;
8219 int NumHiInputs = std::count_if(
8220 Mask.begin(), Mask.end(), [Size](int M) { return M % Size >= Size / 2; });
8222 bool UnpackLo = NumLoInputs >= NumHiInputs;
8224 auto TryUnpack = [&](MVT UnpackVT, int Scale) {
8225 SmallVector<int, 32> V1Mask(Mask.size(), -1);
8226 SmallVector<int, 32> V2Mask(Mask.size(), -1);
8228 for (int i = 0; i < Size; ++i) {
8232 // Each element of the unpack contains Scale elements from this mask.
8233 int UnpackIdx = i / Scale;
8235 // We only handle the case where V1 feeds the first slots of the unpack.
8236 // We rely on canonicalization to ensure this is the case.
8237 if ((UnpackIdx % 2 == 0) != (Mask[i] < Size))
8240 // Setup the mask for this input. The indexing is tricky as we have to
8241 // handle the unpack stride.
8242 SmallVectorImpl<int> &VMask = (UnpackIdx % 2 == 0) ? V1Mask : V2Mask;
8243 VMask[(UnpackIdx / 2) * Scale + i % Scale + (UnpackLo ? 0 : Size / 2)] =
8247 // If we will have to shuffle both inputs to use the unpack, check whether
8248 // we can just unpack first and shuffle the result. If so, skip this unpack.
8249 if ((NumLoInputs == 0 || NumHiInputs == 0) && !isNoopShuffleMask(V1Mask) &&
8250 !isNoopShuffleMask(V2Mask))
8253 // Shuffle the inputs into place.
8254 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
8255 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
8257 // Cast the inputs to the type we will use to unpack them.
8258 V1 = DAG.getBitcast(UnpackVT, V1);
8259 V2 = DAG.getBitcast(UnpackVT, V2);
8261 // Unpack the inputs and cast the result back to the desired type.
8262 return DAG.getBitcast(
8263 VT, DAG.getNode(UnpackLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
8267 // We try each unpack from the largest to the smallest to try and find one
8268 // that fits this mask.
8269 int OrigNumElements = VT.getVectorNumElements();
8270 int OrigScalarSize = VT.getScalarSizeInBits();
8271 for (int ScalarSize = 64; ScalarSize >= OrigScalarSize; ScalarSize /= 2) {
8272 int Scale = ScalarSize / OrigScalarSize;
8273 int NumElements = OrigNumElements / Scale;
8274 MVT UnpackVT = MVT::getVectorVT(MVT::getIntegerVT(ScalarSize), NumElements);
8275 if (SDValue Unpack = TryUnpack(UnpackVT, Scale))
8279 // If none of the unpack-rooted lowerings worked (or were profitable) try an
8281 if (NumLoInputs == 0 || NumHiInputs == 0) {
8282 assert((NumLoInputs > 0 || NumHiInputs > 0) &&
8283 "We have to have *some* inputs!");
8284 int HalfOffset = NumLoInputs == 0 ? Size / 2 : 0;
8286 // FIXME: We could consider the total complexity of the permute of each
8287 // possible unpacking. Or at the least we should consider how many
8288 // half-crossings are created.
8289 // FIXME: We could consider commuting the unpacks.
8291 SmallVector<int, 32> PermMask;
8292 PermMask.assign(Size, -1);
8293 for (int i = 0; i < Size; ++i) {
8297 assert(Mask[i] % Size >= HalfOffset && "Found input from wrong half!");
8300 2 * ((Mask[i] % Size) - HalfOffset) + (Mask[i] < Size ? 0 : 1);
8302 return DAG.getVectorShuffle(
8303 VT, DL, DAG.getNode(NumLoInputs == 0 ? X86ISD::UNPCKH : X86ISD::UNPCKL,
8305 DAG.getUNDEF(VT), PermMask);
8311 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
8313 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
8314 /// support for floating point shuffles but not integer shuffles. These
8315 /// instructions will incur a domain crossing penalty on some chips though so
8316 /// it is better to avoid lowering through this for integer vectors where
8318 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8319 const X86Subtarget *Subtarget,
8320 SelectionDAG &DAG) {
8322 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
8323 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8324 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8325 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8326 ArrayRef<int> Mask = SVOp->getMask();
8327 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8329 if (isSingleInputShuffleMask(Mask)) {
8330 // Use low duplicate instructions for masks that match their pattern.
8331 if (Subtarget->hasSSE3())
8332 if (isShuffleEquivalent(V1, V2, Mask, {0, 0}))
8333 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v2f64, V1);
8335 // Straight shuffle of a single input vector. Simulate this by using the
8336 // single input as both of the "inputs" to this instruction..
8337 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
8339 if (Subtarget->hasAVX()) {
8340 // If we have AVX, we can use VPERMILPS which will allow folding a load
8341 // into the shuffle.
8342 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
8343 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
8346 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V1,
8347 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
8349 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
8350 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
8352 // If we have a single input, insert that into V1 if we can do so cheaply.
8353 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8354 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8355 DL, MVT::v2f64, V1, V2, Mask, Subtarget, DAG))
8357 // Try inverting the insertion since for v2 masks it is easy to do and we
8358 // can't reliably sort the mask one way or the other.
8359 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8360 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8361 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8362 DL, MVT::v2f64, V2, V1, InverseMask, Subtarget, DAG))
8366 // Try to use one of the special instruction patterns to handle two common
8367 // blend patterns if a zero-blend above didn't work.
8368 if (isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
8369 isShuffleEquivalent(V1, V2, Mask, {1, 3}))
8370 if (SDValue V1S = getScalarValueForVectorElement(V1, Mask[0], DAG))
8371 // We can either use a special instruction to load over the low double or
8372 // to move just the low double.
8374 isShuffleFoldableLoad(V1S) ? X86ISD::MOVLPD : X86ISD::MOVSD,
8376 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64, V1S));
8378 if (Subtarget->hasSSE41())
8379 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
8383 // Use dedicated unpack instructions for masks that match their pattern.
8385 lowerVectorShuffleWithUNPCK(DL, MVT::v2f64, Mask, V1, V2, DAG))
8388 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
8389 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V2,
8390 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
8393 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
8395 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
8396 /// the integer unit to minimize domain crossing penalties. However, for blends
8397 /// it falls back to the floating point shuffle operation with appropriate bit
8399 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8400 const X86Subtarget *Subtarget,
8401 SelectionDAG &DAG) {
8403 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
8404 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8405 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8406 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8407 ArrayRef<int> Mask = SVOp->getMask();
8408 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8410 if (isSingleInputShuffleMask(Mask)) {
8411 // Check for being able to broadcast a single element.
8412 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v2i64, V1,
8413 Mask, Subtarget, DAG))
8416 // Straight shuffle of a single input vector. For everything from SSE2
8417 // onward this has a single fast instruction with no scary immediates.
8418 // We have to map the mask as it is actually a v4i32 shuffle instruction.
8419 V1 = DAG.getBitcast(MVT::v4i32, V1);
8420 int WidenedMask[4] = {
8421 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
8422 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
8423 return DAG.getBitcast(
8425 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8426 getV4X86ShuffleImm8ForMask(WidenedMask, DL, DAG)));
8428 assert(Mask[0] != -1 && "No undef lanes in multi-input v2 shuffles!");
8429 assert(Mask[1] != -1 && "No undef lanes in multi-input v2 shuffles!");
8430 assert(Mask[0] < 2 && "We sort V1 to be the first input.");
8431 assert(Mask[1] >= 2 && "We sort V2 to be the second input.");
8433 // If we have a blend of two PACKUS operations an the blend aligns with the
8434 // low and half halves, we can just merge the PACKUS operations. This is
8435 // particularly important as it lets us merge shuffles that this routine itself
8437 auto GetPackNode = [](SDValue V) {
8438 while (V.getOpcode() == ISD::BITCAST)
8439 V = V.getOperand(0);
8441 return V.getOpcode() == X86ISD::PACKUS ? V : SDValue();
8443 if (SDValue V1Pack = GetPackNode(V1))
8444 if (SDValue V2Pack = GetPackNode(V2))
8445 return DAG.getBitcast(MVT::v2i64,
8446 DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8,
8447 Mask[0] == 0 ? V1Pack.getOperand(0)
8448 : V1Pack.getOperand(1),
8449 Mask[1] == 2 ? V2Pack.getOperand(0)
8450 : V2Pack.getOperand(1)));
8452 // Try to use shift instructions.
8454 lowerVectorShuffleAsShift(DL, MVT::v2i64, V1, V2, Mask, DAG))
8457 // When loading a scalar and then shuffling it into a vector we can often do
8458 // the insertion cheaply.
8459 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8460 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
8462 // Try inverting the insertion since for v2 masks it is easy to do and we
8463 // can't reliably sort the mask one way or the other.
8464 int InverseMask[2] = {Mask[0] ^ 2, Mask[1] ^ 2};
8465 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8466 DL, MVT::v2i64, V2, V1, InverseMask, Subtarget, DAG))
8469 // We have different paths for blend lowering, but they all must use the
8470 // *exact* same predicate.
8471 bool IsBlendSupported = Subtarget->hasSSE41();
8472 if (IsBlendSupported)
8473 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
8477 // Use dedicated unpack instructions for masks that match their pattern.
8479 lowerVectorShuffleWithUNPCK(DL, MVT::v2i64, Mask, V1, V2, DAG))
8482 // Try to use byte rotation instructions.
8483 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8484 if (Subtarget->hasSSSE3())
8485 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8486 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
8489 // If we have direct support for blends, we should lower by decomposing into
8490 // a permute. That will be faster than the domain cross.
8491 if (IsBlendSupported)
8492 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v2i64, V1, V2,
8495 // We implement this with SHUFPD which is pretty lame because it will likely
8496 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
8497 // However, all the alternatives are still more cycles and newer chips don't
8498 // have this problem. It would be really nice if x86 had better shuffles here.
8499 V1 = DAG.getBitcast(MVT::v2f64, V1);
8500 V2 = DAG.getBitcast(MVT::v2f64, V2);
8501 return DAG.getBitcast(MVT::v2i64,
8502 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
8505 /// \brief Test whether this can be lowered with a single SHUFPS instruction.
8507 /// This is used to disable more specialized lowerings when the shufps lowering
8508 /// will happen to be efficient.
8509 static bool isSingleSHUFPSMask(ArrayRef<int> Mask) {
8510 // This routine only handles 128-bit shufps.
8511 assert(Mask.size() == 4 && "Unsupported mask size!");
8513 // To lower with a single SHUFPS we need to have the low half and high half
8514 // each requiring a single input.
8515 if (Mask[0] != -1 && Mask[1] != -1 && (Mask[0] < 4) != (Mask[1] < 4))
8517 if (Mask[2] != -1 && Mask[3] != -1 && (Mask[2] < 4) != (Mask[3] < 4))
8523 /// \brief Lower a vector shuffle using the SHUFPS instruction.
8525 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
8526 /// It makes no assumptions about whether this is the *best* lowering, it simply
8528 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
8529 ArrayRef<int> Mask, SDValue V1,
8530 SDValue V2, SelectionDAG &DAG) {
8531 SDValue LowV = V1, HighV = V2;
8532 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
8535 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8537 if (NumV2Elements == 1) {
8539 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8542 // Compute the index adjacent to V2Index and in the same half by toggling
8544 int V2AdjIndex = V2Index ^ 1;
8546 if (Mask[V2AdjIndex] == -1) {
8547 // Handles all the cases where we have a single V2 element and an undef.
8548 // This will only ever happen in the high lanes because we commute the
8549 // vector otherwise.
8551 std::swap(LowV, HighV);
8552 NewMask[V2Index] -= 4;
8554 // Handle the case where the V2 element ends up adjacent to a V1 element.
8555 // To make this work, blend them together as the first step.
8556 int V1Index = V2AdjIndex;
8557 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
8558 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
8559 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
8561 // Now proceed to reconstruct the final blend as we have the necessary
8562 // high or low half formed.
8569 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
8570 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
8572 } else if (NumV2Elements == 2) {
8573 if (Mask[0] < 4 && Mask[1] < 4) {
8574 // Handle the easy case where we have V1 in the low lanes and V2 in the
8578 } else if (Mask[2] < 4 && Mask[3] < 4) {
8579 // We also handle the reversed case because this utility may get called
8580 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
8581 // arrange things in the right direction.
8587 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
8588 // trying to place elements directly, just blend them and set up the final
8589 // shuffle to place them.
8591 // The first two blend mask elements are for V1, the second two are for
8593 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
8594 Mask[2] < 4 ? Mask[2] : Mask[3],
8595 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
8596 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
8597 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
8598 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
8600 // Now we do a normal shuffle of V1 by giving V1 as both operands to
8603 NewMask[0] = Mask[0] < 4 ? 0 : 2;
8604 NewMask[1] = Mask[0] < 4 ? 2 : 0;
8605 NewMask[2] = Mask[2] < 4 ? 1 : 3;
8606 NewMask[3] = Mask[2] < 4 ? 3 : 1;
8609 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
8610 getV4X86ShuffleImm8ForMask(NewMask, DL, DAG));
8613 /// \brief Lower 4-lane 32-bit floating point shuffles.
8615 /// Uses instructions exclusively from the floating point unit to minimize
8616 /// domain crossing penalties, as these are sufficient to implement all v4f32
8618 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8619 const X86Subtarget *Subtarget,
8620 SelectionDAG &DAG) {
8622 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8623 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8624 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8625 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8626 ArrayRef<int> Mask = SVOp->getMask();
8627 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8630 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8632 if (NumV2Elements == 0) {
8633 // Check for being able to broadcast a single element.
8634 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f32, V1,
8635 Mask, Subtarget, DAG))
8638 // Use even/odd duplicate instructions for masks that match their pattern.
8639 if (Subtarget->hasSSE3()) {
8640 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
8641 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v4f32, V1);
8642 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3}))
8643 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v4f32, V1);
8646 if (Subtarget->hasAVX()) {
8647 // If we have AVX, we can use VPERMILPS which will allow folding a load
8648 // into the shuffle.
8649 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
8650 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8653 // Otherwise, use a straight shuffle of a single input vector. We pass the
8654 // input vector to both operands to simulate this with a SHUFPS.
8655 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
8656 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8659 // There are special ways we can lower some single-element blends. However, we
8660 // have custom ways we can lower more complex single-element blends below that
8661 // we defer to if both this and BLENDPS fail to match, so restrict this to
8662 // when the V2 input is targeting element 0 of the mask -- that is the fast
8664 if (NumV2Elements == 1 && Mask[0] >= 4)
8665 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4f32, V1, V2,
8666 Mask, Subtarget, DAG))
8669 if (Subtarget->hasSSE41()) {
8670 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
8674 // Use INSERTPS if we can complete the shuffle efficiently.
8675 if (SDValue V = lowerVectorShuffleAsInsertPS(Op, V1, V2, Mask, DAG))
8678 if (!isSingleSHUFPSMask(Mask))
8679 if (SDValue BlendPerm = lowerVectorShuffleAsBlendAndPermute(
8680 DL, MVT::v4f32, V1, V2, Mask, DAG))
8684 // Use dedicated unpack instructions for masks that match their pattern.
8686 lowerVectorShuffleWithUNPCK(DL, MVT::v4f32, Mask, V1, V2, DAG))
8689 // Otherwise fall back to a SHUFPS lowering strategy.
8690 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
8693 /// \brief Lower 4-lane i32 vector shuffles.
8695 /// We try to handle these with integer-domain shuffles where we can, but for
8696 /// blends we use the floating point domain blend instructions.
8697 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8698 const X86Subtarget *Subtarget,
8699 SelectionDAG &DAG) {
8701 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
8702 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8703 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8704 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8705 ArrayRef<int> Mask = SVOp->getMask();
8706 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8708 // Whenever we can lower this as a zext, that instruction is strictly faster
8709 // than any alternative. It also allows us to fold memory operands into the
8710 // shuffle in many cases.
8711 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
8712 Mask, Subtarget, DAG))
8716 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8718 if (NumV2Elements == 0) {
8719 // Check for being able to broadcast a single element.
8720 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i32, V1,
8721 Mask, Subtarget, DAG))
8724 // Straight shuffle of a single input vector. For everything from SSE2
8725 // onward this has a single fast instruction with no scary immediates.
8726 // We coerce the shuffle pattern to be compatible with UNPCK instructions
8727 // but we aren't actually going to use the UNPCK instruction because doing
8728 // so prevents folding a load into this instruction or making a copy.
8729 const int UnpackLoMask[] = {0, 0, 1, 1};
8730 const int UnpackHiMask[] = {2, 2, 3, 3};
8731 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 1, 1}))
8732 Mask = UnpackLoMask;
8733 else if (isShuffleEquivalent(V1, V2, Mask, {2, 2, 3, 3}))
8734 Mask = UnpackHiMask;
8736 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8737 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8740 // Try to use shift instructions.
8742 lowerVectorShuffleAsShift(DL, MVT::v4i32, V1, V2, Mask, DAG))
8745 // There are special ways we can lower some single-element blends.
8746 if (NumV2Elements == 1)
8747 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4i32, V1, V2,
8748 Mask, Subtarget, DAG))
8751 // We have different paths for blend lowering, but they all must use the
8752 // *exact* same predicate.
8753 bool IsBlendSupported = Subtarget->hasSSE41();
8754 if (IsBlendSupported)
8755 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
8759 if (SDValue Masked =
8760 lowerVectorShuffleAsBitMask(DL, MVT::v4i32, V1, V2, Mask, DAG))
8763 // Use dedicated unpack instructions for masks that match their pattern.
8765 lowerVectorShuffleWithUNPCK(DL, MVT::v4i32, Mask, V1, V2, DAG))
8768 // Try to use byte rotation instructions.
8769 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8770 if (Subtarget->hasSSSE3())
8771 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8772 DL, MVT::v4i32, V1, V2, Mask, Subtarget, DAG))
8775 // If we have direct support for blends, we should lower by decomposing into
8776 // a permute. That will be faster than the domain cross.
8777 if (IsBlendSupported)
8778 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i32, V1, V2,
8781 // Try to lower by permuting the inputs into an unpack instruction.
8782 if (SDValue Unpack = lowerVectorShuffleAsPermuteAndUnpack(DL, MVT::v4i32, V1,
8786 // We implement this with SHUFPS because it can blend from two vectors.
8787 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
8788 // up the inputs, bypassing domain shift penalties that we would encur if we
8789 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
8791 return DAG.getBitcast(
8793 DAG.getVectorShuffle(MVT::v4f32, DL, DAG.getBitcast(MVT::v4f32, V1),
8794 DAG.getBitcast(MVT::v4f32, V2), Mask));
8797 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
8798 /// shuffle lowering, and the most complex part.
8800 /// The lowering strategy is to try to form pairs of input lanes which are
8801 /// targeted at the same half of the final vector, and then use a dword shuffle
8802 /// to place them onto the right half, and finally unpack the paired lanes into
8803 /// their final position.
8805 /// The exact breakdown of how to form these dword pairs and align them on the
8806 /// correct sides is really tricky. See the comments within the function for
8807 /// more of the details.
8809 /// This code also handles repeated 128-bit lanes of v8i16 shuffles, but each
8810 /// lane must shuffle the *exact* same way. In fact, you must pass a v8 Mask to
8811 /// this routine for it to work correctly. To shuffle a 256-bit or 512-bit i16
8812 /// vector, form the analogous 128-bit 8-element Mask.
8813 static SDValue lowerV8I16GeneralSingleInputVectorShuffle(
8814 SDLoc DL, MVT VT, SDValue V, MutableArrayRef<int> Mask,
8815 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8816 assert(VT.getVectorElementType() == MVT::i16 && "Bad input type!");
8817 MVT PSHUFDVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
8819 assert(Mask.size() == 8 && "Shuffle mask length doen't match!");
8820 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8821 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8823 SmallVector<int, 4> LoInputs;
8824 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8825 [](int M) { return M >= 0; });
8826 std::sort(LoInputs.begin(), LoInputs.end());
8827 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8828 SmallVector<int, 4> HiInputs;
8829 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8830 [](int M) { return M >= 0; });
8831 std::sort(HiInputs.begin(), HiInputs.end());
8832 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8834 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8835 int NumHToL = LoInputs.size() - NumLToL;
8837 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8838 int NumHToH = HiInputs.size() - NumLToH;
8839 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8840 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8841 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8842 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8844 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8845 // such inputs we can swap two of the dwords across the half mark and end up
8846 // with <=2 inputs to each half in each half. Once there, we can fall through
8847 // to the generic code below. For example:
8849 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8850 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8852 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8853 // and an existing 2-into-2 on the other half. In this case we may have to
8854 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8855 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8856 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8857 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8858 // half than the one we target for fixing) will be fixed when we re-enter this
8859 // path. We will also combine away any sequence of PSHUFD instructions that
8860 // result into a single instruction. Here is an example of the tricky case:
8862 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8863 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8865 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8867 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8868 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8870 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8871 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8873 // The result is fine to be handled by the generic logic.
8874 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8875 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8876 int AOffset, int BOffset) {
8877 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8878 "Must call this with A having 3 or 1 inputs from the A half.");
8879 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8880 "Must call this with B having 1 or 3 inputs from the B half.");
8881 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8882 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8884 bool ThreeAInputs = AToAInputs.size() == 3;
8886 // Compute the index of dword with only one word among the three inputs in
8887 // a half by taking the sum of the half with three inputs and subtracting
8888 // the sum of the actual three inputs. The difference is the remaining
8891 int &TripleDWord = ThreeAInputs ? ADWord : BDWord;
8892 int &OneInputDWord = ThreeAInputs ? BDWord : ADWord;
8893 int TripleInputOffset = ThreeAInputs ? AOffset : BOffset;
8894 ArrayRef<int> TripleInputs = ThreeAInputs ? AToAInputs : BToAInputs;
8895 int OneInput = ThreeAInputs ? BToAInputs[0] : AToAInputs[0];
8896 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8897 int TripleNonInputIdx =
8898 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8899 TripleDWord = TripleNonInputIdx / 2;
8901 // We use xor with one to compute the adjacent DWord to whichever one the
8903 OneInputDWord = (OneInput / 2) ^ 1;
8905 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8906 // and BToA inputs. If there is also such a problem with the BToB and AToB
8907 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8908 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8909 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8910 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8911 // Compute how many inputs will be flipped by swapping these DWords. We
8913 // to balance this to ensure we don't form a 3-1 shuffle in the other
8915 int NumFlippedAToBInputs =
8916 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8917 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8918 int NumFlippedBToBInputs =
8919 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8920 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8921 if ((NumFlippedAToBInputs == 1 &&
8922 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8923 (NumFlippedBToBInputs == 1 &&
8924 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8925 // We choose whether to fix the A half or B half based on whether that
8926 // half has zero flipped inputs. At zero, we may not be able to fix it
8927 // with that half. We also bias towards fixing the B half because that
8928 // will more commonly be the high half, and we have to bias one way.
8929 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8930 ArrayRef<int> Inputs) {
8931 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8932 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8933 PinnedIdx ^ 1) != Inputs.end();
8934 // Determine whether the free index is in the flipped dword or the
8935 // unflipped dword based on where the pinned index is. We use this bit
8936 // in an xor to conditionally select the adjacent dword.
8937 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8938 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8939 FixFreeIdx) != Inputs.end();
8940 if (IsFixIdxInput == IsFixFreeIdxInput)
8942 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8943 FixFreeIdx) != Inputs.end();
8944 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8945 "We need to be changing the number of flipped inputs!");
8946 int PSHUFHalfMask[] = {0, 1, 2, 3};
8947 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8948 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8950 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DL, DAG));
8953 if (M != -1 && M == FixIdx)
8955 else if (M != -1 && M == FixFreeIdx)
8958 if (NumFlippedBToBInputs != 0) {
8960 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8961 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8963 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8964 int APinnedIdx = ThreeAInputs ? TripleNonInputIdx : OneInput;
8965 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8970 int PSHUFDMask[] = {0, 1, 2, 3};
8971 PSHUFDMask[ADWord] = BDWord;
8972 PSHUFDMask[BDWord] = ADWord;
8975 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT, DAG.getBitcast(PSHUFDVT, V),
8976 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
8978 // Adjust the mask to match the new locations of A and B.
8980 if (M != -1 && M/2 == ADWord)
8981 M = 2 * BDWord + M % 2;
8982 else if (M != -1 && M/2 == BDWord)
8983 M = 2 * ADWord + M % 2;
8985 // Recurse back into this routine to re-compute state now that this isn't
8986 // a 3 and 1 problem.
8987 return lowerV8I16GeneralSingleInputVectorShuffle(DL, VT, V, Mask, Subtarget,
8990 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8991 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8992 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8993 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8995 // At this point there are at most two inputs to the low and high halves from
8996 // each half. That means the inputs can always be grouped into dwords and
8997 // those dwords can then be moved to the correct half with a dword shuffle.
8998 // We use at most one low and one high word shuffle to collect these paired
8999 // inputs into dwords, and finally a dword shuffle to place them.
9000 int PSHUFLMask[4] = {-1, -1, -1, -1};
9001 int PSHUFHMask[4] = {-1, -1, -1, -1};
9002 int PSHUFDMask[4] = {-1, -1, -1, -1};
9004 // First fix the masks for all the inputs that are staying in their
9005 // original halves. This will then dictate the targets of the cross-half
9007 auto fixInPlaceInputs =
9008 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
9009 MutableArrayRef<int> SourceHalfMask,
9010 MutableArrayRef<int> HalfMask, int HalfOffset) {
9011 if (InPlaceInputs.empty())
9013 if (InPlaceInputs.size() == 1) {
9014 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
9015 InPlaceInputs[0] - HalfOffset;
9016 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
9019 if (IncomingInputs.empty()) {
9020 // Just fix all of the in place inputs.
9021 for (int Input : InPlaceInputs) {
9022 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
9023 PSHUFDMask[Input / 2] = Input / 2;
9028 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
9029 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
9030 InPlaceInputs[0] - HalfOffset;
9031 // Put the second input next to the first so that they are packed into
9032 // a dword. We find the adjacent index by toggling the low bit.
9033 int AdjIndex = InPlaceInputs[0] ^ 1;
9034 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
9035 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
9036 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
9038 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
9039 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
9041 // Now gather the cross-half inputs and place them into a free dword of
9042 // their target half.
9043 // FIXME: This operation could almost certainly be simplified dramatically to
9044 // look more like the 3-1 fixing operation.
9045 auto moveInputsToRightHalf = [&PSHUFDMask](
9046 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
9047 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
9048 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
9050 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
9051 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
9053 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
9055 int LowWord = Word & ~1;
9056 int HighWord = Word | 1;
9057 return isWordClobbered(SourceHalfMask, LowWord) ||
9058 isWordClobbered(SourceHalfMask, HighWord);
9061 if (IncomingInputs.empty())
9064 if (ExistingInputs.empty()) {
9065 // Map any dwords with inputs from them into the right half.
9066 for (int Input : IncomingInputs) {
9067 // If the source half mask maps over the inputs, turn those into
9068 // swaps and use the swapped lane.
9069 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
9070 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
9071 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
9072 Input - SourceOffset;
9073 // We have to swap the uses in our half mask in one sweep.
9074 for (int &M : HalfMask)
9075 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
9077 else if (M == Input)
9078 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
9080 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
9081 Input - SourceOffset &&
9082 "Previous placement doesn't match!");
9084 // Note that this correctly re-maps both when we do a swap and when
9085 // we observe the other side of the swap above. We rely on that to
9086 // avoid swapping the members of the input list directly.
9087 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
9090 // Map the input's dword into the correct half.
9091 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
9092 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
9094 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
9096 "Previous placement doesn't match!");
9099 // And just directly shift any other-half mask elements to be same-half
9100 // as we will have mirrored the dword containing the element into the
9101 // same position within that half.
9102 for (int &M : HalfMask)
9103 if (M >= SourceOffset && M < SourceOffset + 4) {
9104 M = M - SourceOffset + DestOffset;
9105 assert(M >= 0 && "This should never wrap below zero!");
9110 // Ensure we have the input in a viable dword of its current half. This
9111 // is particularly tricky because the original position may be clobbered
9112 // by inputs being moved and *staying* in that half.
9113 if (IncomingInputs.size() == 1) {
9114 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
9115 int InputFixed = std::find(std::begin(SourceHalfMask),
9116 std::end(SourceHalfMask), -1) -
9117 std::begin(SourceHalfMask) + SourceOffset;
9118 SourceHalfMask[InputFixed - SourceOffset] =
9119 IncomingInputs[0] - SourceOffset;
9120 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
9122 IncomingInputs[0] = InputFixed;
9124 } else if (IncomingInputs.size() == 2) {
9125 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
9126 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
9127 // We have two non-adjacent or clobbered inputs we need to extract from
9128 // the source half. To do this, we need to map them into some adjacent
9129 // dword slot in the source mask.
9130 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
9131 IncomingInputs[1] - SourceOffset};
9133 // If there is a free slot in the source half mask adjacent to one of
9134 // the inputs, place the other input in it. We use (Index XOR 1) to
9135 // compute an adjacent index.
9136 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
9137 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
9138 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
9139 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
9140 InputsFixed[1] = InputsFixed[0] ^ 1;
9141 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
9142 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
9143 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
9144 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
9145 InputsFixed[0] = InputsFixed[1] ^ 1;
9146 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
9147 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
9148 // The two inputs are in the same DWord but it is clobbered and the
9149 // adjacent DWord isn't used at all. Move both inputs to the free
9151 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
9152 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
9153 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
9154 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
9156 // The only way we hit this point is if there is no clobbering
9157 // (because there are no off-half inputs to this half) and there is no
9158 // free slot adjacent to one of the inputs. In this case, we have to
9159 // swap an input with a non-input.
9160 for (int i = 0; i < 4; ++i)
9161 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
9162 "We can't handle any clobbers here!");
9163 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
9164 "Cannot have adjacent inputs here!");
9166 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
9167 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
9169 // We also have to update the final source mask in this case because
9170 // it may need to undo the above swap.
9171 for (int &M : FinalSourceHalfMask)
9172 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
9173 M = InputsFixed[1] + SourceOffset;
9174 else if (M == InputsFixed[1] + SourceOffset)
9175 M = (InputsFixed[0] ^ 1) + SourceOffset;
9177 InputsFixed[1] = InputsFixed[0] ^ 1;
9180 // Point everything at the fixed inputs.
9181 for (int &M : HalfMask)
9182 if (M == IncomingInputs[0])
9183 M = InputsFixed[0] + SourceOffset;
9184 else if (M == IncomingInputs[1])
9185 M = InputsFixed[1] + SourceOffset;
9187 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
9188 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
9191 llvm_unreachable("Unhandled input size!");
9194 // Now hoist the DWord down to the right half.
9195 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
9196 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
9197 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
9198 for (int &M : HalfMask)
9199 for (int Input : IncomingInputs)
9201 M = FreeDWord * 2 + Input % 2;
9203 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
9204 /*SourceOffset*/ 4, /*DestOffset*/ 0);
9205 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
9206 /*SourceOffset*/ 0, /*DestOffset*/ 4);
9208 // Now enact all the shuffles we've computed to move the inputs into their
9210 if (!isNoopShuffleMask(PSHUFLMask))
9211 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
9212 getV4X86ShuffleImm8ForMask(PSHUFLMask, DL, DAG));
9213 if (!isNoopShuffleMask(PSHUFHMask))
9214 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
9215 getV4X86ShuffleImm8ForMask(PSHUFHMask, DL, DAG));
9216 if (!isNoopShuffleMask(PSHUFDMask))
9219 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT, DAG.getBitcast(PSHUFDVT, V),
9220 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
9222 // At this point, each half should contain all its inputs, and we can then
9223 // just shuffle them into their final position.
9224 assert(std::count_if(LoMask.begin(), LoMask.end(),
9225 [](int M) { return M >= 4; }) == 0 &&
9226 "Failed to lift all the high half inputs to the low mask!");
9227 assert(std::count_if(HiMask.begin(), HiMask.end(),
9228 [](int M) { return M >= 0 && M < 4; }) == 0 &&
9229 "Failed to lift all the low half inputs to the high mask!");
9231 // Do a half shuffle for the low mask.
9232 if (!isNoopShuffleMask(LoMask))
9233 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
9234 getV4X86ShuffleImm8ForMask(LoMask, DL, DAG));
9236 // Do a half shuffle with the high mask after shifting its values down.
9237 for (int &M : HiMask)
9240 if (!isNoopShuffleMask(HiMask))
9241 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
9242 getV4X86ShuffleImm8ForMask(HiMask, DL, DAG));
9247 /// \brief Helper to form a PSHUFB-based shuffle+blend.
9248 static SDValue lowerVectorShuffleAsPSHUFB(SDLoc DL, MVT VT, SDValue V1,
9249 SDValue V2, ArrayRef<int> Mask,
9250 SelectionDAG &DAG, bool &V1InUse,
9252 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
9258 int Size = Mask.size();
9259 int Scale = 16 / Size;
9260 for (int i = 0; i < 16; ++i) {
9261 if (Mask[i / Scale] == -1) {
9262 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
9264 const int ZeroMask = 0x80;
9265 int V1Idx = Mask[i / Scale] < Size ? Mask[i / Scale] * Scale + i % Scale
9267 int V2Idx = Mask[i / Scale] < Size
9269 : (Mask[i / Scale] - Size) * Scale + i % Scale;
9270 if (Zeroable[i / Scale])
9271 V1Idx = V2Idx = ZeroMask;
9272 V1Mask[i] = DAG.getConstant(V1Idx, DL, MVT::i8);
9273 V2Mask[i] = DAG.getConstant(V2Idx, DL, MVT::i8);
9274 V1InUse |= (ZeroMask != V1Idx);
9275 V2InUse |= (ZeroMask != V2Idx);
9280 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
9281 DAG.getBitcast(MVT::v16i8, V1),
9282 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
9284 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
9285 DAG.getBitcast(MVT::v16i8, V2),
9286 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
9288 // If we need shuffled inputs from both, blend the two.
9290 if (V1InUse && V2InUse)
9291 V = DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
9293 V = V1InUse ? V1 : V2;
9295 // Cast the result back to the correct type.
9296 return DAG.getBitcast(VT, V);
9299 /// \brief Generic lowering of 8-lane i16 shuffles.
9301 /// This handles both single-input shuffles and combined shuffle/blends with
9302 /// two inputs. The single input shuffles are immediately delegated to
9303 /// a dedicated lowering routine.
9305 /// The blends are lowered in one of three fundamental ways. If there are few
9306 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
9307 /// of the input is significantly cheaper when lowered as an interleaving of
9308 /// the two inputs, try to interleave them. Otherwise, blend the low and high
9309 /// halves of the inputs separately (making them have relatively few inputs)
9310 /// and then concatenate them.
9311 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9312 const X86Subtarget *Subtarget,
9313 SelectionDAG &DAG) {
9315 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
9316 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9317 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9318 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9319 ArrayRef<int> OrigMask = SVOp->getMask();
9320 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9321 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
9322 MutableArrayRef<int> Mask(MaskStorage);
9324 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9326 // Whenever we can lower this as a zext, that instruction is strictly faster
9327 // than any alternative.
9328 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9329 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
9332 auto isV1 = [](int M) { return M >= 0 && M < 8; };
9334 auto isV2 = [](int M) { return M >= 8; };
9336 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
9338 if (NumV2Inputs == 0) {
9339 // Check for being able to broadcast a single element.
9340 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i16, V1,
9341 Mask, Subtarget, DAG))
9344 // Try to use shift instructions.
9346 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V1, Mask, DAG))
9349 // Use dedicated unpack instructions for masks that match their pattern.
9351 lowerVectorShuffleWithUNPCK(DL, MVT::v8i16, Mask, V1, V2, DAG))
9354 // Try to use byte rotation instructions.
9355 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v8i16, V1, V1,
9356 Mask, Subtarget, DAG))
9359 return lowerV8I16GeneralSingleInputVectorShuffle(DL, MVT::v8i16, V1, Mask,
9363 assert(std::any_of(Mask.begin(), Mask.end(), isV1) &&
9364 "All single-input shuffles should be canonicalized to be V1-input "
9367 // Try to use shift instructions.
9369 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V2, Mask, DAG))
9372 // See if we can use SSE4A Extraction / Insertion.
9373 if (Subtarget->hasSSE4A())
9374 if (SDValue V = lowerVectorShuffleWithSSE4A(DL, MVT::v8i16, V1, V2, Mask, DAG))
9377 // There are special ways we can lower some single-element blends.
9378 if (NumV2Inputs == 1)
9379 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v8i16, V1, V2,
9380 Mask, Subtarget, DAG))
9383 // We have different paths for blend lowering, but they all must use the
9384 // *exact* same predicate.
9385 bool IsBlendSupported = Subtarget->hasSSE41();
9386 if (IsBlendSupported)
9387 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
9391 if (SDValue Masked =
9392 lowerVectorShuffleAsBitMask(DL, MVT::v8i16, V1, V2, Mask, DAG))
9395 // Use dedicated unpack instructions for masks that match their pattern.
9397 lowerVectorShuffleWithUNPCK(DL, MVT::v8i16, Mask, V1, V2, DAG))
9400 // Try to use byte rotation instructions.
9401 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9402 DL, MVT::v8i16, V1, V2, Mask, Subtarget, DAG))
9405 if (SDValue BitBlend =
9406 lowerVectorShuffleAsBitBlend(DL, MVT::v8i16, V1, V2, Mask, DAG))
9409 if (SDValue Unpack = lowerVectorShuffleAsPermuteAndUnpack(DL, MVT::v8i16, V1,
9413 // If we can't directly blend but can use PSHUFB, that will be better as it
9414 // can both shuffle and set up the inefficient blend.
9415 if (!IsBlendSupported && Subtarget->hasSSSE3()) {
9416 bool V1InUse, V2InUse;
9417 return lowerVectorShuffleAsPSHUFB(DL, MVT::v8i16, V1, V2, Mask, DAG,
9421 // We can always bit-blend if we have to so the fallback strategy is to
9422 // decompose into single-input permutes and blends.
9423 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i16, V1, V2,
9427 /// \brief Check whether a compaction lowering can be done by dropping even
9428 /// elements and compute how many times even elements must be dropped.
9430 /// This handles shuffles which take every Nth element where N is a power of
9431 /// two. Example shuffle masks:
9433 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
9434 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
9435 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
9436 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
9437 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
9438 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
9440 /// Any of these lanes can of course be undef.
9442 /// This routine only supports N <= 3.
9443 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
9446 /// \returns N above, or the number of times even elements must be dropped if
9447 /// there is such a number. Otherwise returns zero.
9448 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
9449 // Figure out whether we're looping over two inputs or just one.
9450 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9452 // The modulus for the shuffle vector entries is based on whether this is
9453 // a single input or not.
9454 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
9455 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
9456 "We should only be called with masks with a power-of-2 size!");
9458 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
9460 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
9461 // and 2^3 simultaneously. This is because we may have ambiguity with
9462 // partially undef inputs.
9463 bool ViableForN[3] = {true, true, true};
9465 for (int i = 0, e = Mask.size(); i < e; ++i) {
9466 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
9471 bool IsAnyViable = false;
9472 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9473 if (ViableForN[j]) {
9476 // The shuffle mask must be equal to (i * 2^N) % M.
9477 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
9480 ViableForN[j] = false;
9482 // Early exit if we exhaust the possible powers of two.
9487 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9491 // Return 0 as there is no viable power of two.
9495 /// \brief Generic lowering of v16i8 shuffles.
9497 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
9498 /// detect any complexity reducing interleaving. If that doesn't help, it uses
9499 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
9500 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
9502 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9503 const X86Subtarget *Subtarget,
9504 SelectionDAG &DAG) {
9506 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
9507 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9508 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9509 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9510 ArrayRef<int> Mask = SVOp->getMask();
9511 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9513 // Try to use shift instructions.
9515 lowerVectorShuffleAsShift(DL, MVT::v16i8, V1, V2, Mask, DAG))
9518 // Try to use byte rotation instructions.
9519 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9520 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
9523 // Try to use a zext lowering.
9524 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9525 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
9528 // See if we can use SSE4A Extraction / Insertion.
9529 if (Subtarget->hasSSE4A())
9530 if (SDValue V = lowerVectorShuffleWithSSE4A(DL, MVT::v16i8, V1, V2, Mask, DAG))
9534 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
9536 // For single-input shuffles, there are some nicer lowering tricks we can use.
9537 if (NumV2Elements == 0) {
9538 // Check for being able to broadcast a single element.
9539 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i8, V1,
9540 Mask, Subtarget, DAG))
9543 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
9544 // Notably, this handles splat and partial-splat shuffles more efficiently.
9545 // However, it only makes sense if the pre-duplication shuffle simplifies
9546 // things significantly. Currently, this means we need to be able to
9547 // express the pre-duplication shuffle as an i16 shuffle.
9549 // FIXME: We should check for other patterns which can be widened into an
9550 // i16 shuffle as well.
9551 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
9552 for (int i = 0; i < 16; i += 2)
9553 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
9558 auto tryToWidenViaDuplication = [&]() -> SDValue {
9559 if (!canWidenViaDuplication(Mask))
9561 SmallVector<int, 4> LoInputs;
9562 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
9563 [](int M) { return M >= 0 && M < 8; });
9564 std::sort(LoInputs.begin(), LoInputs.end());
9565 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
9567 SmallVector<int, 4> HiInputs;
9568 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
9569 [](int M) { return M >= 8; });
9570 std::sort(HiInputs.begin(), HiInputs.end());
9571 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
9574 bool TargetLo = LoInputs.size() >= HiInputs.size();
9575 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
9576 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
9578 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9579 SmallDenseMap<int, int, 8> LaneMap;
9580 for (int I : InPlaceInputs) {
9581 PreDupI16Shuffle[I/2] = I/2;
9584 int j = TargetLo ? 0 : 4, je = j + 4;
9585 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
9586 // Check if j is already a shuffle of this input. This happens when
9587 // there are two adjacent bytes after we move the low one.
9588 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
9589 // If we haven't yet mapped the input, search for a slot into which
9591 while (j < je && PreDupI16Shuffle[j] != -1)
9595 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
9598 // Map this input with the i16 shuffle.
9599 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
9602 // Update the lane map based on the mapping we ended up with.
9603 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
9605 V1 = DAG.getBitcast(
9607 DAG.getVectorShuffle(MVT::v8i16, DL, DAG.getBitcast(MVT::v8i16, V1),
9608 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
9610 // Unpack the bytes to form the i16s that will be shuffled into place.
9611 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9612 MVT::v16i8, V1, V1);
9614 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9615 for (int i = 0; i < 16; ++i)
9616 if (Mask[i] != -1) {
9617 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
9618 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
9619 if (PostDupI16Shuffle[i / 2] == -1)
9620 PostDupI16Shuffle[i / 2] = MappedMask;
9622 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
9623 "Conflicting entrties in the original shuffle!");
9625 return DAG.getBitcast(
9627 DAG.getVectorShuffle(MVT::v8i16, DL, DAG.getBitcast(MVT::v8i16, V1),
9628 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
9630 if (SDValue V = tryToWidenViaDuplication())
9634 if (SDValue Masked =
9635 lowerVectorShuffleAsBitMask(DL, MVT::v16i8, V1, V2, Mask, DAG))
9638 // Use dedicated unpack instructions for masks that match their pattern.
9640 lowerVectorShuffleWithUNPCK(DL, MVT::v16i8, Mask, V1, V2, DAG))
9643 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
9644 // with PSHUFB. It is important to do this before we attempt to generate any
9645 // blends but after all of the single-input lowerings. If the single input
9646 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
9647 // want to preserve that and we can DAG combine any longer sequences into
9648 // a PSHUFB in the end. But once we start blending from multiple inputs,
9649 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
9650 // and there are *very* few patterns that would actually be faster than the
9651 // PSHUFB approach because of its ability to zero lanes.
9653 // FIXME: The only exceptions to the above are blends which are exact
9654 // interleavings with direct instructions supporting them. We currently don't
9655 // handle those well here.
9656 if (Subtarget->hasSSSE3()) {
9657 bool V1InUse = false;
9658 bool V2InUse = false;
9660 SDValue PSHUFB = lowerVectorShuffleAsPSHUFB(DL, MVT::v16i8, V1, V2, Mask,
9661 DAG, V1InUse, V2InUse);
9663 // If both V1 and V2 are in use and we can use a direct blend or an unpack,
9664 // do so. This avoids using them to handle blends-with-zero which is
9665 // important as a single pshufb is significantly faster for that.
9666 if (V1InUse && V2InUse) {
9667 if (Subtarget->hasSSE41())
9668 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i8, V1, V2,
9669 Mask, Subtarget, DAG))
9672 // We can use an unpack to do the blending rather than an or in some
9673 // cases. Even though the or may be (very minorly) more efficient, we
9674 // preference this lowering because there are common cases where part of
9675 // the complexity of the shuffles goes away when we do the final blend as
9677 // FIXME: It might be worth trying to detect if the unpack-feeding
9678 // shuffles will both be pshufb, in which case we shouldn't bother with
9680 if (SDValue Unpack = lowerVectorShuffleAsPermuteAndUnpack(
9681 DL, MVT::v16i8, V1, V2, Mask, DAG))
9688 // There are special ways we can lower some single-element blends.
9689 if (NumV2Elements == 1)
9690 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v16i8, V1, V2,
9691 Mask, Subtarget, DAG))
9694 if (SDValue BitBlend =
9695 lowerVectorShuffleAsBitBlend(DL, MVT::v16i8, V1, V2, Mask, DAG))
9698 // Check whether a compaction lowering can be done. This handles shuffles
9699 // which take every Nth element for some even N. See the helper function for
9702 // We special case these as they can be particularly efficiently handled with
9703 // the PACKUSB instruction on x86 and they show up in common patterns of
9704 // rearranging bytes to truncate wide elements.
9705 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
9706 // NumEvenDrops is the power of two stride of the elements. Another way of
9707 // thinking about it is that we need to drop the even elements this many
9708 // times to get the original input.
9709 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9711 // First we need to zero all the dropped bytes.
9712 assert(NumEvenDrops <= 3 &&
9713 "No support for dropping even elements more than 3 times.");
9714 // We use the mask type to pick which bytes are preserved based on how many
9715 // elements are dropped.
9716 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
9717 SDValue ByteClearMask = DAG.getBitcast(
9718 MVT::v16i8, DAG.getConstant(0xFF, DL, MaskVTs[NumEvenDrops - 1]));
9719 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
9721 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
9723 // Now pack things back together.
9724 V1 = DAG.getBitcast(MVT::v8i16, V1);
9725 V2 = IsSingleInput ? V1 : DAG.getBitcast(MVT::v8i16, V2);
9726 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
9727 for (int i = 1; i < NumEvenDrops; ++i) {
9728 Result = DAG.getBitcast(MVT::v8i16, Result);
9729 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
9735 // Handle multi-input cases by blending single-input shuffles.
9736 if (NumV2Elements > 0)
9737 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v16i8, V1, V2,
9740 // The fallback path for single-input shuffles widens this into two v8i16
9741 // vectors with unpacks, shuffles those, and then pulls them back together
9745 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9746 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9747 for (int i = 0; i < 16; ++i)
9749 (i < 8 ? LoBlendMask[i] : HiBlendMask[i % 8]) = Mask[i];
9751 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
9753 SDValue VLoHalf, VHiHalf;
9754 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
9755 // them out and avoid using UNPCK{L,H} to extract the elements of V as
9757 if (std::none_of(std::begin(LoBlendMask), std::end(LoBlendMask),
9758 [](int M) { return M >= 0 && M % 2 == 1; }) &&
9759 std::none_of(std::begin(HiBlendMask), std::end(HiBlendMask),
9760 [](int M) { return M >= 0 && M % 2 == 1; })) {
9761 // Use a mask to drop the high bytes.
9762 VLoHalf = DAG.getBitcast(MVT::v8i16, V);
9763 VLoHalf = DAG.getNode(ISD::AND, DL, MVT::v8i16, VLoHalf,
9764 DAG.getConstant(0x00FF, DL, MVT::v8i16));
9766 // This will be a single vector shuffle instead of a blend so nuke VHiHalf.
9767 VHiHalf = DAG.getUNDEF(MVT::v8i16);
9769 // Squash the masks to point directly into VLoHalf.
9770 for (int &M : LoBlendMask)
9773 for (int &M : HiBlendMask)
9777 // Otherwise just unpack the low half of V into VLoHalf and the high half into
9778 // VHiHalf so that we can blend them as i16s.
9779 VLoHalf = DAG.getBitcast(
9780 MVT::v8i16, DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
9781 VHiHalf = DAG.getBitcast(
9782 MVT::v8i16, DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
9785 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, LoBlendMask);
9786 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, HiBlendMask);
9788 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
9791 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
9793 /// This routine breaks down the specific type of 128-bit shuffle and
9794 /// dispatches to the lowering routines accordingly.
9795 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9796 MVT VT, const X86Subtarget *Subtarget,
9797 SelectionDAG &DAG) {
9798 switch (VT.SimpleTy) {
9800 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9802 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9804 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9806 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9808 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9810 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9813 llvm_unreachable("Unimplemented!");
9817 /// \brief Helper function to test whether a shuffle mask could be
9818 /// simplified by widening the elements being shuffled.
9820 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
9821 /// leaves it in an unspecified state.
9823 /// NOTE: This must handle normal vector shuffle masks and *target* vector
9824 /// shuffle masks. The latter have the special property of a '-2' representing
9825 /// a zero-ed lane of a vector.
9826 static bool canWidenShuffleElements(ArrayRef<int> Mask,
9827 SmallVectorImpl<int> &WidenedMask) {
9828 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
9829 // If both elements are undef, its trivial.
9830 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
9831 WidenedMask.push_back(SM_SentinelUndef);
9835 // Check for an undef mask and a mask value properly aligned to fit with
9836 // a pair of values. If we find such a case, use the non-undef mask's value.
9837 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
9838 WidenedMask.push_back(Mask[i + 1] / 2);
9841 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
9842 WidenedMask.push_back(Mask[i] / 2);
9846 // When zeroing, we need to spread the zeroing across both lanes to widen.
9847 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
9848 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
9849 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
9850 WidenedMask.push_back(SM_SentinelZero);
9856 // Finally check if the two mask values are adjacent and aligned with
9858 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
9859 WidenedMask.push_back(Mask[i] / 2);
9863 // Otherwise we can't safely widen the elements used in this shuffle.
9866 assert(WidenedMask.size() == Mask.size() / 2 &&
9867 "Incorrect size of mask after widening the elements!");
9872 /// \brief Generic routine to split vector shuffle into half-sized shuffles.
9874 /// This routine just extracts two subvectors, shuffles them independently, and
9875 /// then concatenates them back together. This should work effectively with all
9876 /// AVX vector shuffle types.
9877 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9878 SDValue V2, ArrayRef<int> Mask,
9879 SelectionDAG &DAG) {
9880 assert(VT.getSizeInBits() >= 256 &&
9881 "Only for 256-bit or wider vector shuffles!");
9882 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9883 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9885 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
9886 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
9888 int NumElements = VT.getVectorNumElements();
9889 int SplitNumElements = NumElements / 2;
9890 MVT ScalarVT = VT.getVectorElementType();
9891 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9893 // Rather than splitting build-vectors, just build two narrower build
9894 // vectors. This helps shuffling with splats and zeros.
9895 auto SplitVector = [&](SDValue V) {
9896 while (V.getOpcode() == ISD::BITCAST)
9897 V = V->getOperand(0);
9899 MVT OrigVT = V.getSimpleValueType();
9900 int OrigNumElements = OrigVT.getVectorNumElements();
9901 int OrigSplitNumElements = OrigNumElements / 2;
9902 MVT OrigScalarVT = OrigVT.getVectorElementType();
9903 MVT OrigSplitVT = MVT::getVectorVT(OrigScalarVT, OrigNumElements / 2);
9907 auto *BV = dyn_cast<BuildVectorSDNode>(V);
9909 LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
9910 DAG.getIntPtrConstant(0, DL));
9911 HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
9912 DAG.getIntPtrConstant(OrigSplitNumElements, DL));
9915 SmallVector<SDValue, 16> LoOps, HiOps;
9916 for (int i = 0; i < OrigSplitNumElements; ++i) {
9917 LoOps.push_back(BV->getOperand(i));
9918 HiOps.push_back(BV->getOperand(i + OrigSplitNumElements));
9920 LoV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, LoOps);
9921 HiV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, HiOps);
9923 return std::make_pair(DAG.getBitcast(SplitVT, LoV),
9924 DAG.getBitcast(SplitVT, HiV));
9927 SDValue LoV1, HiV1, LoV2, HiV2;
9928 std::tie(LoV1, HiV1) = SplitVector(V1);
9929 std::tie(LoV2, HiV2) = SplitVector(V2);
9931 // Now create two 4-way blends of these half-width vectors.
9932 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9933 bool UseLoV1 = false, UseHiV1 = false, UseLoV2 = false, UseHiV2 = false;
9934 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
9935 for (int i = 0; i < SplitNumElements; ++i) {
9936 int M = HalfMask[i];
9937 if (M >= NumElements) {
9938 if (M >= NumElements + SplitNumElements)
9942 V2BlendMask.push_back(M - NumElements);
9943 V1BlendMask.push_back(-1);
9944 BlendMask.push_back(SplitNumElements + i);
9945 } else if (M >= 0) {
9946 if (M >= SplitNumElements)
9950 V2BlendMask.push_back(-1);
9951 V1BlendMask.push_back(M);
9952 BlendMask.push_back(i);
9954 V2BlendMask.push_back(-1);
9955 V1BlendMask.push_back(-1);
9956 BlendMask.push_back(-1);
9960 // Because the lowering happens after all combining takes place, we need to
9961 // manually combine these blend masks as much as possible so that we create
9962 // a minimal number of high-level vector shuffle nodes.
9964 // First try just blending the halves of V1 or V2.
9965 if (!UseLoV1 && !UseHiV1 && !UseLoV2 && !UseHiV2)
9966 return DAG.getUNDEF(SplitVT);
9967 if (!UseLoV2 && !UseHiV2)
9968 return DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9969 if (!UseLoV1 && !UseHiV1)
9970 return DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9972 SDValue V1Blend, V2Blend;
9973 if (UseLoV1 && UseHiV1) {
9975 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9977 // We only use half of V1 so map the usage down into the final blend mask.
9978 V1Blend = UseLoV1 ? LoV1 : HiV1;
9979 for (int i = 0; i < SplitNumElements; ++i)
9980 if (BlendMask[i] >= 0 && BlendMask[i] < SplitNumElements)
9981 BlendMask[i] = V1BlendMask[i] - (UseLoV1 ? 0 : SplitNumElements);
9983 if (UseLoV2 && UseHiV2) {
9985 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9987 // We only use half of V2 so map the usage down into the final blend mask.
9988 V2Blend = UseLoV2 ? LoV2 : HiV2;
9989 for (int i = 0; i < SplitNumElements; ++i)
9990 if (BlendMask[i] >= SplitNumElements)
9991 BlendMask[i] = V2BlendMask[i] + (UseLoV2 ? SplitNumElements : 0);
9993 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9995 SDValue Lo = HalfBlend(LoMask);
9996 SDValue Hi = HalfBlend(HiMask);
9997 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
10000 /// \brief Either split a vector in halves or decompose the shuffles and the
10003 /// This is provided as a good fallback for many lowerings of non-single-input
10004 /// shuffles with more than one 128-bit lane. In those cases, we want to select
10005 /// between splitting the shuffle into 128-bit components and stitching those
10006 /// back together vs. extracting the single-input shuffles and blending those
10008 static SDValue lowerVectorShuffleAsSplitOrBlend(SDLoc DL, MVT VT, SDValue V1,
10009 SDValue V2, ArrayRef<int> Mask,
10010 SelectionDAG &DAG) {
10011 assert(!isSingleInputShuffleMask(Mask) && "This routine must not be used to "
10012 "lower single-input shuffles as it "
10013 "could then recurse on itself.");
10014 int Size = Mask.size();
10016 // If this can be modeled as a broadcast of two elements followed by a blend,
10017 // prefer that lowering. This is especially important because broadcasts can
10018 // often fold with memory operands.
10019 auto DoBothBroadcast = [&] {
10020 int V1BroadcastIdx = -1, V2BroadcastIdx = -1;
10023 if (V2BroadcastIdx == -1)
10024 V2BroadcastIdx = M - Size;
10025 else if (M - Size != V2BroadcastIdx)
10027 } else if (M >= 0) {
10028 if (V1BroadcastIdx == -1)
10029 V1BroadcastIdx = M;
10030 else if (M != V1BroadcastIdx)
10035 if (DoBothBroadcast())
10036 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask,
10039 // If the inputs all stem from a single 128-bit lane of each input, then we
10040 // split them rather than blending because the split will decompose to
10041 // unusually few instructions.
10042 int LaneCount = VT.getSizeInBits() / 128;
10043 int LaneSize = Size / LaneCount;
10044 SmallBitVector LaneInputs[2];
10045 LaneInputs[0].resize(LaneCount, false);
10046 LaneInputs[1].resize(LaneCount, false);
10047 for (int i = 0; i < Size; ++i)
10049 LaneInputs[Mask[i] / Size][(Mask[i] % Size) / LaneSize] = true;
10050 if (LaneInputs[0].count() <= 1 && LaneInputs[1].count() <= 1)
10051 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10053 // Otherwise, just fall back to decomposed shuffles and a blend. This requires
10054 // that the decomposed single-input shuffles don't end up here.
10055 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
10058 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
10059 /// a permutation and blend of those lanes.
10061 /// This essentially blends the out-of-lane inputs to each lane into the lane
10062 /// from a permuted copy of the vector. This lowering strategy results in four
10063 /// instructions in the worst case for a single-input cross lane shuffle which
10064 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
10065 /// of. Special cases for each particular shuffle pattern should be handled
10066 /// prior to trying this lowering.
10067 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
10068 SDValue V1, SDValue V2,
10069 ArrayRef<int> Mask,
10070 SelectionDAG &DAG) {
10071 // FIXME: This should probably be generalized for 512-bit vectors as well.
10072 assert(VT.is256BitVector() && "Only for 256-bit vector shuffles!");
10073 int LaneSize = Mask.size() / 2;
10075 // If there are only inputs from one 128-bit lane, splitting will in fact be
10076 // less expensive. The flags track whether the given lane contains an element
10077 // that crosses to another lane.
10078 bool LaneCrossing[2] = {false, false};
10079 for (int i = 0, Size = Mask.size(); i < Size; ++i)
10080 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
10081 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
10082 if (!LaneCrossing[0] || !LaneCrossing[1])
10083 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10085 if (isSingleInputShuffleMask(Mask)) {
10086 SmallVector<int, 32> FlippedBlendMask;
10087 for (int i = 0, Size = Mask.size(); i < Size; ++i)
10088 FlippedBlendMask.push_back(
10089 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
10091 : Mask[i] % LaneSize +
10092 (i / LaneSize) * LaneSize + Size));
10094 // Flip the vector, and blend the results which should now be in-lane. The
10095 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
10096 // 5 for the high source. The value 3 selects the high half of source 2 and
10097 // the value 2 selects the low half of source 2. We only use source 2 to
10098 // allow folding it into a memory operand.
10099 unsigned PERMMask = 3 | 2 << 4;
10100 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
10101 V1, DAG.getConstant(PERMMask, DL, MVT::i8));
10102 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
10105 // This now reduces to two single-input shuffles of V1 and V2 which at worst
10106 // will be handled by the above logic and a blend of the results, much like
10107 // other patterns in AVX.
10108 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
10111 /// \brief Handle lowering 2-lane 128-bit shuffles.
10112 static SDValue lowerV2X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1,
10113 SDValue V2, ArrayRef<int> Mask,
10114 const X86Subtarget *Subtarget,
10115 SelectionDAG &DAG) {
10116 // TODO: If minimizing size and one of the inputs is a zero vector and the
10117 // the zero vector has only one use, we could use a VPERM2X128 to save the
10118 // instruction bytes needed to explicitly generate the zero vector.
10120 // Blends are faster and handle all the non-lane-crossing cases.
10121 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, VT, V1, V2, Mask,
10125 bool IsV1Zero = ISD::isBuildVectorAllZeros(V1.getNode());
10126 bool IsV2Zero = ISD::isBuildVectorAllZeros(V2.getNode());
10128 // If either input operand is a zero vector, use VPERM2X128 because its mask
10129 // allows us to replace the zero input with an implicit zero.
10130 if (!IsV1Zero && !IsV2Zero) {
10131 // Check for patterns which can be matched with a single insert of a 128-bit
10133 bool OnlyUsesV1 = isShuffleEquivalent(V1, V2, Mask, {0, 1, 0, 1});
10134 if (OnlyUsesV1 || isShuffleEquivalent(V1, V2, Mask, {0, 1, 4, 5})) {
10135 MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(),
10136 VT.getVectorNumElements() / 2);
10137 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
10138 DAG.getIntPtrConstant(0, DL));
10139 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
10140 OnlyUsesV1 ? V1 : V2,
10141 DAG.getIntPtrConstant(0, DL));
10142 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
10146 // Otherwise form a 128-bit permutation. After accounting for undefs,
10147 // convert the 64-bit shuffle mask selection values into 128-bit
10148 // selection bits by dividing the indexes by 2 and shifting into positions
10149 // defined by a vperm2*128 instruction's immediate control byte.
10151 // The immediate permute control byte looks like this:
10152 // [1:0] - select 128 bits from sources for low half of destination
10154 // [3] - zero low half of destination
10155 // [5:4] - select 128 bits from sources for high half of destination
10157 // [7] - zero high half of destination
10159 int MaskLO = Mask[0];
10160 if (MaskLO == SM_SentinelUndef)
10161 MaskLO = Mask[1] == SM_SentinelUndef ? 0 : Mask[1];
10163 int MaskHI = Mask[2];
10164 if (MaskHI == SM_SentinelUndef)
10165 MaskHI = Mask[3] == SM_SentinelUndef ? 0 : Mask[3];
10167 unsigned PermMask = MaskLO / 2 | (MaskHI / 2) << 4;
10169 // If either input is a zero vector, replace it with an undef input.
10170 // Shuffle mask values < 4 are selecting elements of V1.
10171 // Shuffle mask values >= 4 are selecting elements of V2.
10172 // Adjust each half of the permute mask by clearing the half that was
10173 // selecting the zero vector and setting the zero mask bit.
10175 V1 = DAG.getUNDEF(VT);
10177 PermMask = (PermMask & 0xf0) | 0x08;
10179 PermMask = (PermMask & 0x0f) | 0x80;
10182 V2 = DAG.getUNDEF(VT);
10184 PermMask = (PermMask & 0xf0) | 0x08;
10186 PermMask = (PermMask & 0x0f) | 0x80;
10189 return DAG.getNode(X86ISD::VPERM2X128, DL, VT, V1, V2,
10190 DAG.getConstant(PermMask, DL, MVT::i8));
10193 /// \brief Lower a vector shuffle by first fixing the 128-bit lanes and then
10194 /// shuffling each lane.
10196 /// This will only succeed when the result of fixing the 128-bit lanes results
10197 /// in a single-input non-lane-crossing shuffle with a repeating shuffle mask in
10198 /// each 128-bit lanes. This handles many cases where we can quickly blend away
10199 /// the lane crosses early and then use simpler shuffles within each lane.
10201 /// FIXME: It might be worthwhile at some point to support this without
10202 /// requiring the 128-bit lane-relative shuffles to be repeating, but currently
10203 /// in x86 only floating point has interesting non-repeating shuffles, and even
10204 /// those are still *marginally* more expensive.
10205 static SDValue lowerVectorShuffleByMerging128BitLanes(
10206 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
10207 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
10208 assert(!isSingleInputShuffleMask(Mask) &&
10209 "This is only useful with multiple inputs.");
10211 int Size = Mask.size();
10212 int LaneSize = 128 / VT.getScalarSizeInBits();
10213 int NumLanes = Size / LaneSize;
10214 assert(NumLanes > 1 && "Only handles 256-bit and wider shuffles.");
10216 // See if we can build a hypothetical 128-bit lane-fixing shuffle mask. Also
10217 // check whether the in-128-bit lane shuffles share a repeating pattern.
10218 SmallVector<int, 4> Lanes;
10219 Lanes.resize(NumLanes, -1);
10220 SmallVector<int, 4> InLaneMask;
10221 InLaneMask.resize(LaneSize, -1);
10222 for (int i = 0; i < Size; ++i) {
10226 int j = i / LaneSize;
10228 if (Lanes[j] < 0) {
10229 // First entry we've seen for this lane.
10230 Lanes[j] = Mask[i] / LaneSize;
10231 } else if (Lanes[j] != Mask[i] / LaneSize) {
10232 // This doesn't match the lane selected previously!
10236 // Check that within each lane we have a consistent shuffle mask.
10237 int k = i % LaneSize;
10238 if (InLaneMask[k] < 0) {
10239 InLaneMask[k] = Mask[i] % LaneSize;
10240 } else if (InLaneMask[k] != Mask[i] % LaneSize) {
10241 // This doesn't fit a repeating in-lane mask.
10246 // First shuffle the lanes into place.
10247 MVT LaneVT = MVT::getVectorVT(VT.isFloatingPoint() ? MVT::f64 : MVT::i64,
10248 VT.getSizeInBits() / 64);
10249 SmallVector<int, 8> LaneMask;
10250 LaneMask.resize(NumLanes * 2, -1);
10251 for (int i = 0; i < NumLanes; ++i)
10252 if (Lanes[i] >= 0) {
10253 LaneMask[2 * i + 0] = 2*Lanes[i] + 0;
10254 LaneMask[2 * i + 1] = 2*Lanes[i] + 1;
10257 V1 = DAG.getBitcast(LaneVT, V1);
10258 V2 = DAG.getBitcast(LaneVT, V2);
10259 SDValue LaneShuffle = DAG.getVectorShuffle(LaneVT, DL, V1, V2, LaneMask);
10261 // Cast it back to the type we actually want.
10262 LaneShuffle = DAG.getBitcast(VT, LaneShuffle);
10264 // Now do a simple shuffle that isn't lane crossing.
10265 SmallVector<int, 8> NewMask;
10266 NewMask.resize(Size, -1);
10267 for (int i = 0; i < Size; ++i)
10269 NewMask[i] = (i / LaneSize) * LaneSize + Mask[i] % LaneSize;
10270 assert(!is128BitLaneCrossingShuffleMask(VT, NewMask) &&
10271 "Must not introduce lane crosses at this point!");
10273 return DAG.getVectorShuffle(VT, DL, LaneShuffle, DAG.getUNDEF(VT), NewMask);
10276 /// \brief Test whether the specified input (0 or 1) is in-place blended by the
10279 /// This returns true if the elements from a particular input are already in the
10280 /// slot required by the given mask and require no permutation.
10281 static bool isShuffleMaskInputInPlace(int Input, ArrayRef<int> Mask) {
10282 assert((Input == 0 || Input == 1) && "Only two inputs to shuffles.");
10283 int Size = Mask.size();
10284 for (int i = 0; i < Size; ++i)
10285 if (Mask[i] >= 0 && Mask[i] / Size == Input && Mask[i] % Size != i)
10291 static SDValue lowerVectorShuffleWithSHUFPD(SDLoc DL, MVT VT,
10292 ArrayRef<int> Mask, SDValue V1,
10293 SDValue V2, SelectionDAG &DAG) {
10295 // Mask for V8F64: 0/1, 8/9, 2/3, 10/11, 4/5, ..
10296 // Mask for V4F64; 0/1, 4/5, 2/3, 6/7..
10297 assert(VT.getScalarSizeInBits() == 64 && "Unexpected data type for VSHUFPD");
10298 int NumElts = VT.getVectorNumElements();
10299 bool ShufpdMask = true;
10300 bool CommutableMask = true;
10301 unsigned Immediate = 0;
10302 for (int i = 0; i < NumElts; ++i) {
10305 int Val = (i & 6) + NumElts * (i & 1);
10306 int CommutVal = (i & 0xe) + NumElts * ((i & 1)^1);
10307 if (Mask[i] < Val || Mask[i] > Val + 1)
10308 ShufpdMask = false;
10309 if (Mask[i] < CommutVal || Mask[i] > CommutVal + 1)
10310 CommutableMask = false;
10311 Immediate |= (Mask[i] % 2) << i;
10314 return DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
10315 DAG.getConstant(Immediate, DL, MVT::i8));
10316 if (CommutableMask)
10317 return DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
10318 DAG.getConstant(Immediate, DL, MVT::i8));
10322 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
10324 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
10325 /// isn't available.
10326 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10327 const X86Subtarget *Subtarget,
10328 SelectionDAG &DAG) {
10330 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10331 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10332 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10333 ArrayRef<int> Mask = SVOp->getMask();
10334 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10336 SmallVector<int, 4> WidenedMask;
10337 if (canWidenShuffleElements(Mask, WidenedMask))
10338 return lowerV2X128VectorShuffle(DL, MVT::v4f64, V1, V2, Mask, Subtarget,
10341 if (isSingleInputShuffleMask(Mask)) {
10342 // Check for being able to broadcast a single element.
10343 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f64, V1,
10344 Mask, Subtarget, DAG))
10347 // Use low duplicate instructions for masks that match their pattern.
10348 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
10349 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v4f64, V1);
10351 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
10352 // Non-half-crossing single input shuffles can be lowerid with an
10353 // interleaved permutation.
10354 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
10355 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
10356 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
10357 DAG.getConstant(VPERMILPMask, DL, MVT::i8));
10360 // With AVX2 we have direct support for this permutation.
10361 if (Subtarget->hasAVX2())
10362 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
10363 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
10365 // Otherwise, fall back.
10366 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
10370 // Use dedicated unpack instructions for masks that match their pattern.
10372 lowerVectorShuffleWithUNPCK(DL, MVT::v4f64, Mask, V1, V2, DAG))
10375 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
10379 // Check if the blend happens to exactly fit that of SHUFPD.
10381 lowerVectorShuffleWithSHUFPD(DL, MVT::v4f64, Mask, V1, V2, DAG))
10384 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10385 // shuffle. However, if we have AVX2 and either inputs are already in place,
10386 // we will be able to shuffle even across lanes the other input in a single
10387 // instruction so skip this pattern.
10388 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10389 isShuffleMaskInputInPlace(1, Mask))))
10390 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10391 DL, MVT::v4f64, V1, V2, Mask, Subtarget, DAG))
10394 // If we have AVX2 then we always want to lower with a blend because an v4 we
10395 // can fully permute the elements.
10396 if (Subtarget->hasAVX2())
10397 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
10400 // Otherwise fall back on generic lowering.
10401 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v4f64, V1, V2, Mask, DAG);
10404 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
10406 /// This routine is only called when we have AVX2 and thus a reasonable
10407 /// instruction set for v4i64 shuffling..
10408 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10409 const X86Subtarget *Subtarget,
10410 SelectionDAG &DAG) {
10412 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10413 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10414 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10415 ArrayRef<int> Mask = SVOp->getMask();
10416 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10417 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
10419 SmallVector<int, 4> WidenedMask;
10420 if (canWidenShuffleElements(Mask, WidenedMask))
10421 return lowerV2X128VectorShuffle(DL, MVT::v4i64, V1, V2, Mask, Subtarget,
10424 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
10428 // Check for being able to broadcast a single element.
10429 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i64, V1,
10430 Mask, Subtarget, DAG))
10433 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
10434 // use lower latency instructions that will operate on both 128-bit lanes.
10435 SmallVector<int, 2> RepeatedMask;
10436 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
10437 if (isSingleInputShuffleMask(Mask)) {
10438 int PSHUFDMask[] = {-1, -1, -1, -1};
10439 for (int i = 0; i < 2; ++i)
10440 if (RepeatedMask[i] >= 0) {
10441 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
10442 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
10444 return DAG.getBitcast(
10446 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
10447 DAG.getBitcast(MVT::v8i32, V1),
10448 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
10452 // AVX2 provides a direct instruction for permuting a single input across
10454 if (isSingleInputShuffleMask(Mask))
10455 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
10456 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
10458 // Try to use shift instructions.
10459 if (SDValue Shift =
10460 lowerVectorShuffleAsShift(DL, MVT::v4i64, V1, V2, Mask, DAG))
10463 // Use dedicated unpack instructions for masks that match their pattern.
10465 lowerVectorShuffleWithUNPCK(DL, MVT::v4i64, Mask, V1, V2, DAG))
10468 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10469 // shuffle. However, if we have AVX2 and either inputs are already in place,
10470 // we will be able to shuffle even across lanes the other input in a single
10471 // instruction so skip this pattern.
10472 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10473 isShuffleMaskInputInPlace(1, Mask))))
10474 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10475 DL, MVT::v4i64, V1, V2, Mask, Subtarget, DAG))
10478 // Otherwise fall back on generic blend lowering.
10479 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
10483 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
10485 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
10486 /// isn't available.
10487 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10488 const X86Subtarget *Subtarget,
10489 SelectionDAG &DAG) {
10491 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10492 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10493 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10494 ArrayRef<int> Mask = SVOp->getMask();
10495 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10497 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
10501 // Check for being able to broadcast a single element.
10502 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8f32, V1,
10503 Mask, Subtarget, DAG))
10506 // If the shuffle mask is repeated in each 128-bit lane, we have many more
10507 // options to efficiently lower the shuffle.
10508 SmallVector<int, 4> RepeatedMask;
10509 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
10510 assert(RepeatedMask.size() == 4 &&
10511 "Repeated masks must be half the mask width!");
10513 // Use even/odd duplicate instructions for masks that match their pattern.
10514 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2, 4, 4, 6, 6}))
10515 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v8f32, V1);
10516 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3, 5, 5, 7, 7}))
10517 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v8f32, V1);
10519 if (isSingleInputShuffleMask(Mask))
10520 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
10521 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
10523 // Use dedicated unpack instructions for masks that match their pattern.
10525 lowerVectorShuffleWithUNPCK(DL, MVT::v8f32, Mask, V1, V2, DAG))
10528 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
10529 // have already handled any direct blends. We also need to squash the
10530 // repeated mask into a simulated v4f32 mask.
10531 for (int i = 0; i < 4; ++i)
10532 if (RepeatedMask[i] >= 8)
10533 RepeatedMask[i] -= 4;
10534 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
10537 // If we have a single input shuffle with different shuffle patterns in the
10538 // two 128-bit lanes use the variable mask to VPERMILPS.
10539 if (isSingleInputShuffleMask(Mask)) {
10540 SDValue VPermMask[8];
10541 for (int i = 0; i < 8; ++i)
10542 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10543 : DAG.getConstant(Mask[i], DL, MVT::i32);
10544 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
10545 return DAG.getNode(
10546 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
10547 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
10549 if (Subtarget->hasAVX2())
10550 return DAG.getNode(
10551 X86ISD::VPERMV, DL, MVT::v8f32,
10552 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
10554 // Otherwise, fall back.
10555 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
10559 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10561 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10562 DL, MVT::v8f32, V1, V2, Mask, Subtarget, DAG))
10565 // If we have AVX2 then we always want to lower with a blend because at v8 we
10566 // can fully permute the elements.
10567 if (Subtarget->hasAVX2())
10568 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
10571 // Otherwise fall back on generic lowering.
10572 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v8f32, V1, V2, Mask, DAG);
10575 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
10577 /// This routine is only called when we have AVX2 and thus a reasonable
10578 /// instruction set for v8i32 shuffling..
10579 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10580 const X86Subtarget *Subtarget,
10581 SelectionDAG &DAG) {
10583 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10584 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10585 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10586 ArrayRef<int> Mask = SVOp->getMask();
10587 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10588 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
10590 // Whenever we can lower this as a zext, that instruction is strictly faster
10591 // than any alternative. It also allows us to fold memory operands into the
10592 // shuffle in many cases.
10593 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v8i32, V1, V2,
10594 Mask, Subtarget, DAG))
10597 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
10601 // Check for being able to broadcast a single element.
10602 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i32, V1,
10603 Mask, Subtarget, DAG))
10606 // If the shuffle mask is repeated in each 128-bit lane we can use more
10607 // efficient instructions that mirror the shuffles across the two 128-bit
10609 SmallVector<int, 4> RepeatedMask;
10610 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
10611 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
10612 if (isSingleInputShuffleMask(Mask))
10613 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
10614 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
10616 // Use dedicated unpack instructions for masks that match their pattern.
10618 lowerVectorShuffleWithUNPCK(DL, MVT::v8i32, Mask, V1, V2, DAG))
10622 // Try to use shift instructions.
10623 if (SDValue Shift =
10624 lowerVectorShuffleAsShift(DL, MVT::v8i32, V1, V2, Mask, DAG))
10627 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10628 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10631 // If the shuffle patterns aren't repeated but it is a single input, directly
10632 // generate a cross-lane VPERMD instruction.
10633 if (isSingleInputShuffleMask(Mask)) {
10634 SDValue VPermMask[8];
10635 for (int i = 0; i < 8; ++i)
10636 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10637 : DAG.getConstant(Mask[i], DL, MVT::i32);
10638 return DAG.getNode(
10639 X86ISD::VPERMV, DL, MVT::v8i32,
10640 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
10643 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10645 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10646 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10649 // Otherwise fall back on generic blend lowering.
10650 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
10654 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
10656 /// This routine is only called when we have AVX2 and thus a reasonable
10657 /// instruction set for v16i16 shuffling..
10658 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10659 const X86Subtarget *Subtarget,
10660 SelectionDAG &DAG) {
10662 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10663 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10664 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10665 ArrayRef<int> Mask = SVOp->getMask();
10666 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10667 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
10669 // Whenever we can lower this as a zext, that instruction is strictly faster
10670 // than any alternative. It also allows us to fold memory operands into the
10671 // shuffle in many cases.
10672 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v16i16, V1, V2,
10673 Mask, Subtarget, DAG))
10676 // Check for being able to broadcast a single element.
10677 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i16, V1,
10678 Mask, Subtarget, DAG))
10681 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
10685 // Use dedicated unpack instructions for masks that match their pattern.
10687 lowerVectorShuffleWithUNPCK(DL, MVT::v16i16, Mask, V1, V2, DAG))
10690 // Try to use shift instructions.
10691 if (SDValue Shift =
10692 lowerVectorShuffleAsShift(DL, MVT::v16i16, V1, V2, Mask, DAG))
10695 // Try to use byte rotation instructions.
10696 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10697 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10700 if (isSingleInputShuffleMask(Mask)) {
10701 // There are no generalized cross-lane shuffle operations available on i16
10703 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
10704 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
10707 SmallVector<int, 8> RepeatedMask;
10708 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
10709 // As this is a single-input shuffle, the repeated mask should be
10710 // a strictly valid v8i16 mask that we can pass through to the v8i16
10711 // lowering to handle even the v16 case.
10712 return lowerV8I16GeneralSingleInputVectorShuffle(
10713 DL, MVT::v16i16, V1, RepeatedMask, Subtarget, DAG);
10716 SDValue PSHUFBMask[32];
10717 for (int i = 0; i < 16; ++i) {
10718 if (Mask[i] == -1) {
10719 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
10723 int M = i < 8 ? Mask[i] : Mask[i] - 8;
10724 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
10725 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, DL, MVT::i8);
10726 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, DL, MVT::i8);
10728 return DAG.getBitcast(MVT::v16i16,
10729 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8,
10730 DAG.getBitcast(MVT::v32i8, V1),
10731 DAG.getNode(ISD::BUILD_VECTOR, DL,
10732 MVT::v32i8, PSHUFBMask)));
10735 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10737 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10738 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10741 // Otherwise fall back on generic lowering.
10742 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v16i16, V1, V2, Mask, DAG);
10745 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
10747 /// This routine is only called when we have AVX2 and thus a reasonable
10748 /// instruction set for v32i8 shuffling..
10749 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10750 const X86Subtarget *Subtarget,
10751 SelectionDAG &DAG) {
10753 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10754 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10755 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10756 ArrayRef<int> Mask = SVOp->getMask();
10757 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10758 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
10760 // Whenever we can lower this as a zext, that instruction is strictly faster
10761 // than any alternative. It also allows us to fold memory operands into the
10762 // shuffle in many cases.
10763 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v32i8, V1, V2,
10764 Mask, Subtarget, DAG))
10767 // Check for being able to broadcast a single element.
10768 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v32i8, V1,
10769 Mask, Subtarget, DAG))
10772 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
10776 // Use dedicated unpack instructions for masks that match their pattern.
10778 lowerVectorShuffleWithUNPCK(DL, MVT::v32i8, Mask, V1, V2, DAG))
10781 // Try to use shift instructions.
10782 if (SDValue Shift =
10783 lowerVectorShuffleAsShift(DL, MVT::v32i8, V1, V2, Mask, DAG))
10786 // Try to use byte rotation instructions.
10787 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10788 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10791 if (isSingleInputShuffleMask(Mask)) {
10792 // There are no generalized cross-lane shuffle operations available on i8
10794 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
10795 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
10798 SDValue PSHUFBMask[32];
10799 for (int i = 0; i < 32; ++i)
10802 ? DAG.getUNDEF(MVT::i8)
10803 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, DL,
10806 return DAG.getNode(
10807 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
10808 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
10811 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10813 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10814 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10817 // Otherwise fall back on generic lowering.
10818 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v32i8, V1, V2, Mask, DAG);
10821 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
10823 /// This routine either breaks down the specific type of a 256-bit x86 vector
10824 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
10825 /// together based on the available instructions.
10826 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10827 MVT VT, const X86Subtarget *Subtarget,
10828 SelectionDAG &DAG) {
10830 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10831 ArrayRef<int> Mask = SVOp->getMask();
10833 // If we have a single input to the zero element, insert that into V1 if we
10834 // can do so cheaply.
10835 int NumElts = VT.getVectorNumElements();
10836 int NumV2Elements = std::count_if(Mask.begin(), Mask.end(), [NumElts](int M) {
10837 return M >= NumElts;
10840 if (NumV2Elements == 1 && Mask[0] >= NumElts)
10841 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
10842 DL, VT, V1, V2, Mask, Subtarget, DAG))
10845 // There is a really nice hard cut-over between AVX1 and AVX2 that means we
10846 // can check for those subtargets here and avoid much of the subtarget
10847 // querying in the per-vector-type lowering routines. With AVX1 we have
10848 // essentially *zero* ability to manipulate a 256-bit vector with integer
10849 // types. Since we'll use floating point types there eventually, just
10850 // immediately cast everything to a float and operate entirely in that domain.
10851 if (VT.isInteger() && !Subtarget->hasAVX2()) {
10852 int ElementBits = VT.getScalarSizeInBits();
10853 if (ElementBits < 32)
10854 // No floating point type available, decompose into 128-bit vectors.
10855 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10857 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
10858 VT.getVectorNumElements());
10859 V1 = DAG.getBitcast(FpVT, V1);
10860 V2 = DAG.getBitcast(FpVT, V2);
10861 return DAG.getBitcast(VT, DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
10864 switch (VT.SimpleTy) {
10866 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10868 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10870 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10872 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10874 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10876 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10879 llvm_unreachable("Not a valid 256-bit x86 vector type!");
10883 /// \brief Try to lower a vector shuffle as a 128-bit shuffles.
10884 static SDValue lowerV4X128VectorShuffle(SDLoc DL, MVT VT,
10885 ArrayRef<int> Mask,
10886 SDValue V1, SDValue V2,
10887 SelectionDAG &DAG) {
10888 assert(VT.getScalarSizeInBits() == 64 &&
10889 "Unexpected element type size for 128bit shuffle.");
10891 // To handle 256 bit vector requires VLX and most probably
10892 // function lowerV2X128VectorShuffle() is better solution.
10893 assert(VT.is512BitVector() && "Unexpected vector size for 128bit shuffle.");
10895 SmallVector<int, 4> WidenedMask;
10896 if (!canWidenShuffleElements(Mask, WidenedMask))
10899 // Form a 128-bit permutation.
10900 // Convert the 64-bit shuffle mask selection values into 128-bit selection
10901 // bits defined by a vshuf64x2 instruction's immediate control byte.
10902 unsigned PermMask = 0, Imm = 0;
10903 unsigned ControlBitsNum = WidenedMask.size() / 2;
10905 for (int i = 0, Size = WidenedMask.size(); i < Size; ++i) {
10906 if (WidenedMask[i] == SM_SentinelZero)
10909 // Use first element in place of undef mask.
10910 Imm = (WidenedMask[i] == SM_SentinelUndef) ? 0 : WidenedMask[i];
10911 PermMask |= (Imm % WidenedMask.size()) << (i * ControlBitsNum);
10914 return DAG.getNode(X86ISD::SHUF128, DL, VT, V1, V2,
10915 DAG.getConstant(PermMask, DL, MVT::i8));
10918 static SDValue lowerVectorShuffleWithPERMV(SDLoc DL, MVT VT,
10919 ArrayRef<int> Mask, SDValue V1,
10920 SDValue V2, SelectionDAG &DAG) {
10922 assert(VT.getScalarSizeInBits() >= 16 && "Unexpected data type for PERMV");
10924 MVT MaskEltVT = MVT::getIntegerVT(VT.getScalarSizeInBits());
10925 MVT MaskVecVT = MVT::getVectorVT(MaskEltVT, VT.getVectorNumElements());
10927 SDValue MaskNode = getConstVector(Mask, MaskVecVT, DAG, DL, true);
10928 if (isSingleInputShuffleMask(Mask))
10929 return DAG.getNode(X86ISD::VPERMV, DL, VT, MaskNode, V1);
10931 return DAG.getNode(X86ISD::VPERMV3, DL, VT, V1, MaskNode, V2);
10934 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
10935 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10936 const X86Subtarget *Subtarget,
10937 SelectionDAG &DAG) {
10939 assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10940 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10941 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10942 ArrayRef<int> Mask = SVOp->getMask();
10943 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10945 if (SDValue Shuf128 =
10946 lowerV4X128VectorShuffle(DL, MVT::v8f64, Mask, V1, V2, DAG))
10949 if (SDValue Unpck =
10950 lowerVectorShuffleWithUNPCK(DL, MVT::v8f64, Mask, V1, V2, DAG))
10953 return lowerVectorShuffleWithPERMV(DL, MVT::v8f64, Mask, V1, V2, DAG);
10956 /// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
10957 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10958 const X86Subtarget *Subtarget,
10959 SelectionDAG &DAG) {
10961 assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10962 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10963 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10964 ArrayRef<int> Mask = SVOp->getMask();
10965 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10967 if (SDValue Unpck =
10968 lowerVectorShuffleWithUNPCK(DL, MVT::v16f32, Mask, V1, V2, DAG))
10971 return lowerVectorShuffleWithPERMV(DL, MVT::v16f32, Mask, V1, V2, DAG);
10974 /// \brief Handle lowering of 8-lane 64-bit integer shuffles.
10975 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10976 const X86Subtarget *Subtarget,
10977 SelectionDAG &DAG) {
10979 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10980 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10981 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10982 ArrayRef<int> Mask = SVOp->getMask();
10983 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10985 if (SDValue Shuf128 =
10986 lowerV4X128VectorShuffle(DL, MVT::v8i64, Mask, V1, V2, DAG))
10989 if (SDValue Unpck =
10990 lowerVectorShuffleWithUNPCK(DL, MVT::v8i64, Mask, V1, V2, DAG))
10993 return lowerVectorShuffleWithPERMV(DL, MVT::v8i64, Mask, V1, V2, DAG);
10996 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
10997 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10998 const X86Subtarget *Subtarget,
10999 SelectionDAG &DAG) {
11001 assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
11002 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
11003 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11004 ArrayRef<int> Mask = SVOp->getMask();
11005 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
11007 if (SDValue Unpck =
11008 lowerVectorShuffleWithUNPCK(DL, MVT::v16i32, Mask, V1, V2, DAG))
11011 return lowerVectorShuffleWithPERMV(DL, MVT::v16i32, Mask, V1, V2, DAG);
11014 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
11015 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
11016 const X86Subtarget *Subtarget,
11017 SelectionDAG &DAG) {
11019 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
11020 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
11021 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11022 ArrayRef<int> Mask = SVOp->getMask();
11023 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
11024 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
11026 return lowerVectorShuffleWithPERMV(DL, MVT::v32i16, Mask, V1, V2, DAG);
11029 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
11030 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
11031 const X86Subtarget *Subtarget,
11032 SelectionDAG &DAG) {
11034 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
11035 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
11036 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11037 ArrayRef<int> Mask = SVOp->getMask();
11038 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
11039 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
11041 // FIXME: Implement direct support for this type!
11042 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
11045 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
11047 /// This routine either breaks down the specific type of a 512-bit x86 vector
11048 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
11049 /// together based on the available instructions.
11050 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
11051 MVT VT, const X86Subtarget *Subtarget,
11052 SelectionDAG &DAG) {
11054 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11055 ArrayRef<int> Mask = SVOp->getMask();
11056 assert(Subtarget->hasAVX512() &&
11057 "Cannot lower 512-bit vectors w/ basic ISA!");
11059 // Check for being able to broadcast a single element.
11060 if (SDValue Broadcast =
11061 lowerVectorShuffleAsBroadcast(DL, VT, V1, Mask, Subtarget, DAG))
11064 // Dispatch to each element type for lowering. If we don't have supprot for
11065 // specific element type shuffles at 512 bits, immediately split them and
11066 // lower them. Each lowering routine of a given type is allowed to assume that
11067 // the requisite ISA extensions for that element type are available.
11068 switch (VT.SimpleTy) {
11070 return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
11072 return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
11074 return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
11076 return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
11078 if (Subtarget->hasBWI())
11079 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
11082 if (Subtarget->hasBWI())
11083 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
11087 llvm_unreachable("Not a valid 512-bit x86 vector type!");
11090 // Otherwise fall back on splitting.
11091 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
11094 // Lower vXi1 vector shuffles.
11095 // There is no a dedicated instruction on AVX-512 that shuffles the masks.
11096 // The only way to shuffle bits is to sign-extend the mask vector to SIMD
11097 // vector, shuffle and then truncate it back.
11098 static SDValue lower1BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
11099 MVT VT, const X86Subtarget *Subtarget,
11100 SelectionDAG &DAG) {
11102 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11103 ArrayRef<int> Mask = SVOp->getMask();
11104 assert(Subtarget->hasAVX512() &&
11105 "Cannot lower 512-bit vectors w/o basic ISA!");
11107 switch (VT.SimpleTy) {
11109 llvm_unreachable("Expected a vector of i1 elements");
11111 ExtVT = MVT::v2i64;
11114 ExtVT = MVT::v4i32;
11117 ExtVT = MVT::v8i64; // Take 512-bit type, more shuffles on KNL
11120 ExtVT = MVT::v16i32;
11123 ExtVT = MVT::v32i16;
11126 ExtVT = MVT::v64i8;
11130 if (ISD::isBuildVectorAllZeros(V1.getNode()))
11131 V1 = getZeroVector(ExtVT, Subtarget, DAG, DL);
11132 else if (ISD::isBuildVectorAllOnes(V1.getNode()))
11133 V1 = getOnesVector(ExtVT, Subtarget, DAG, DL);
11135 V1 = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, V1);
11138 V2 = DAG.getUNDEF(ExtVT);
11139 else if (ISD::isBuildVectorAllZeros(V2.getNode()))
11140 V2 = getZeroVector(ExtVT, Subtarget, DAG, DL);
11141 else if (ISD::isBuildVectorAllOnes(V2.getNode()))
11142 V2 = getOnesVector(ExtVT, Subtarget, DAG, DL);
11144 V2 = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, V2);
11145 return DAG.getNode(ISD::TRUNCATE, DL, VT,
11146 DAG.getVectorShuffle(ExtVT, DL, V1, V2, Mask));
11148 /// \brief Top-level lowering for x86 vector shuffles.
11150 /// This handles decomposition, canonicalization, and lowering of all x86
11151 /// vector shuffles. Most of the specific lowering strategies are encapsulated
11152 /// above in helper routines. The canonicalization attempts to widen shuffles
11153 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
11154 /// s.t. only one of the two inputs needs to be tested, etc.
11155 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
11156 SelectionDAG &DAG) {
11157 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11158 ArrayRef<int> Mask = SVOp->getMask();
11159 SDValue V1 = Op.getOperand(0);
11160 SDValue V2 = Op.getOperand(1);
11161 MVT VT = Op.getSimpleValueType();
11162 int NumElements = VT.getVectorNumElements();
11164 bool Is1BitVector = (VT.getVectorElementType() == MVT::i1);
11166 assert((VT.getSizeInBits() != 64 || Is1BitVector) &&
11167 "Can't lower MMX shuffles");
11169 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
11170 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
11171 if (V1IsUndef && V2IsUndef)
11172 return DAG.getUNDEF(VT);
11174 // When we create a shuffle node we put the UNDEF node to second operand,
11175 // but in some cases the first operand may be transformed to UNDEF.
11176 // In this case we should just commute the node.
11178 return DAG.getCommutedVectorShuffle(*SVOp);
11180 // Check for non-undef masks pointing at an undef vector and make the masks
11181 // undef as well. This makes it easier to match the shuffle based solely on
11185 if (M >= NumElements) {
11186 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
11187 for (int &M : NewMask)
11188 if (M >= NumElements)
11190 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
11193 // We actually see shuffles that are entirely re-arrangements of a set of
11194 // zero inputs. This mostly happens while decomposing complex shuffles into
11195 // simple ones. Directly lower these as a buildvector of zeros.
11196 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
11197 if (Zeroable.all())
11198 return getZeroVector(VT, Subtarget, DAG, dl);
11200 // Try to collapse shuffles into using a vector type with fewer elements but
11201 // wider element types. We cap this to not form integers or floating point
11202 // elements wider than 64 bits, but it might be interesting to form i128
11203 // integers to handle flipping the low and high halves of AVX 256-bit vectors.
11204 SmallVector<int, 16> WidenedMask;
11205 if (VT.getScalarSizeInBits() < 64 && !Is1BitVector &&
11206 canWidenShuffleElements(Mask, WidenedMask)) {
11207 MVT NewEltVT = VT.isFloatingPoint()
11208 ? MVT::getFloatingPointVT(VT.getScalarSizeInBits() * 2)
11209 : MVT::getIntegerVT(VT.getScalarSizeInBits() * 2);
11210 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2);
11211 // Make sure that the new vector type is legal. For example, v2f64 isn't
11213 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) {
11214 V1 = DAG.getBitcast(NewVT, V1);
11215 V2 = DAG.getBitcast(NewVT, V2);
11216 return DAG.getBitcast(
11217 VT, DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
11221 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
11222 for (int M : SVOp->getMask())
11224 ++NumUndefElements;
11225 else if (M < NumElements)
11230 // Commute the shuffle as needed such that more elements come from V1 than
11231 // V2. This allows us to match the shuffle pattern strictly on how many
11232 // elements come from V1 without handling the symmetric cases.
11233 if (NumV2Elements > NumV1Elements)
11234 return DAG.getCommutedVectorShuffle(*SVOp);
11236 // When the number of V1 and V2 elements are the same, try to minimize the
11237 // number of uses of V2 in the low half of the vector. When that is tied,
11238 // ensure that the sum of indices for V1 is equal to or lower than the sum
11239 // indices for V2. When those are equal, try to ensure that the number of odd
11240 // indices for V1 is lower than the number of odd indices for V2.
11241 if (NumV1Elements == NumV2Elements) {
11242 int LowV1Elements = 0, LowV2Elements = 0;
11243 for (int M : SVOp->getMask().slice(0, NumElements / 2))
11244 if (M >= NumElements)
11248 if (LowV2Elements > LowV1Elements) {
11249 return DAG.getCommutedVectorShuffle(*SVOp);
11250 } else if (LowV2Elements == LowV1Elements) {
11251 int SumV1Indices = 0, SumV2Indices = 0;
11252 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
11253 if (SVOp->getMask()[i] >= NumElements)
11255 else if (SVOp->getMask()[i] >= 0)
11257 if (SumV2Indices < SumV1Indices) {
11258 return DAG.getCommutedVectorShuffle(*SVOp);
11259 } else if (SumV2Indices == SumV1Indices) {
11260 int NumV1OddIndices = 0, NumV2OddIndices = 0;
11261 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
11262 if (SVOp->getMask()[i] >= NumElements)
11263 NumV2OddIndices += i % 2;
11264 else if (SVOp->getMask()[i] >= 0)
11265 NumV1OddIndices += i % 2;
11266 if (NumV2OddIndices < NumV1OddIndices)
11267 return DAG.getCommutedVectorShuffle(*SVOp);
11272 // For each vector width, delegate to a specialized lowering routine.
11273 if (VT.is128BitVector())
11274 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11276 if (VT.is256BitVector())
11277 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11279 if (VT.is512BitVector())
11280 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11283 return lower1BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11284 llvm_unreachable("Unimplemented!");
11287 // This function assumes its argument is a BUILD_VECTOR of constants or
11288 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
11290 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
11291 unsigned &MaskValue) {
11293 unsigned NumElems = BuildVector->getNumOperands();
11295 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
11296 // We don't handle the >2 lanes case right now.
11297 unsigned NumLanes = (NumElems - 1) / 8 + 1;
11301 unsigned NumElemsInLane = NumElems / NumLanes;
11303 // Blend for v16i16 should be symmetric for the both lanes.
11304 for (unsigned i = 0; i < NumElemsInLane; ++i) {
11305 SDValue EltCond = BuildVector->getOperand(i);
11306 SDValue SndLaneEltCond =
11307 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
11309 int Lane1Cond = -1, Lane2Cond = -1;
11310 if (isa<ConstantSDNode>(EltCond))
11311 Lane1Cond = !isNullConstant(EltCond);
11312 if (isa<ConstantSDNode>(SndLaneEltCond))
11313 Lane2Cond = !isNullConstant(SndLaneEltCond);
11315 unsigned LaneMask = 0;
11316 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
11317 // Lane1Cond != 0, means we want the first argument.
11318 // Lane1Cond == 0, means we want the second argument.
11319 // The encoding of this argument is 0 for the first argument, 1
11320 // for the second. Therefore, invert the condition.
11321 LaneMask = !Lane1Cond << i;
11322 else if (Lane1Cond < 0)
11323 LaneMask = !Lane2Cond << i;
11327 MaskValue |= LaneMask;
11329 MaskValue |= LaneMask << NumElemsInLane;
11334 /// \brief Try to lower a VSELECT instruction to a vector shuffle.
11335 static SDValue lowerVSELECTtoVectorShuffle(SDValue Op,
11336 const X86Subtarget *Subtarget,
11337 SelectionDAG &DAG) {
11338 SDValue Cond = Op.getOperand(0);
11339 SDValue LHS = Op.getOperand(1);
11340 SDValue RHS = Op.getOperand(2);
11342 MVT VT = Op.getSimpleValueType();
11344 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
11346 auto *CondBV = cast<BuildVectorSDNode>(Cond);
11348 // Only non-legal VSELECTs reach this lowering, convert those into generic
11349 // shuffles and re-use the shuffle lowering path for blends.
11350 SmallVector<int, 32> Mask;
11351 for (int i = 0, Size = VT.getVectorNumElements(); i < Size; ++i) {
11352 SDValue CondElt = CondBV->getOperand(i);
11354 isa<ConstantSDNode>(CondElt) ? i + (isNullConstant(CondElt) ? Size : 0)
11357 return DAG.getVectorShuffle(VT, dl, LHS, RHS, Mask);
11360 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
11361 // A vselect where all conditions and data are constants can be optimized into
11362 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
11363 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
11364 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
11365 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
11368 // Try to lower this to a blend-style vector shuffle. This can handle all
11369 // constant condition cases.
11370 if (SDValue BlendOp = lowerVSELECTtoVectorShuffle(Op, Subtarget, DAG))
11373 // Variable blends are only legal from SSE4.1 onward.
11374 if (!Subtarget->hasSSE41())
11377 // Only some types will be legal on some subtargets. If we can emit a legal
11378 // VSELECT-matching blend, return Op, and but if we need to expand, return
11380 switch (Op.getSimpleValueType().SimpleTy) {
11382 // Most of the vector types have blends past SSE4.1.
11386 // The byte blends for AVX vectors were introduced only in AVX2.
11387 if (Subtarget->hasAVX2())
11394 // AVX-512 BWI and VLX features support VSELECT with i16 elements.
11395 if (Subtarget->hasBWI() && Subtarget->hasVLX())
11398 // FIXME: We should custom lower this by fixing the condition and using i8
11404 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
11405 MVT VT = Op.getSimpleValueType();
11408 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
11411 if (VT.getSizeInBits() == 8) {
11412 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
11413 Op.getOperand(0), Op.getOperand(1));
11414 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11415 DAG.getValueType(VT));
11416 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11419 if (VT.getSizeInBits() == 16) {
11420 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
11421 if (isNullConstant(Op.getOperand(1)))
11422 return DAG.getNode(
11423 ISD::TRUNCATE, dl, MVT::i16,
11424 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11425 DAG.getBitcast(MVT::v4i32, Op.getOperand(0)),
11426 Op.getOperand(1)));
11427 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
11428 Op.getOperand(0), Op.getOperand(1));
11429 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11430 DAG.getValueType(VT));
11431 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11434 if (VT == MVT::f32) {
11435 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
11436 // the result back to FR32 register. It's only worth matching if the
11437 // result has a single use which is a store or a bitcast to i32. And in
11438 // the case of a store, it's not worth it if the index is a constant 0,
11439 // because a MOVSSmr can be used instead, which is smaller and faster.
11440 if (!Op.hasOneUse())
11442 SDNode *User = *Op.getNode()->use_begin();
11443 if ((User->getOpcode() != ISD::STORE ||
11444 isNullConstant(Op.getOperand(1))) &&
11445 (User->getOpcode() != ISD::BITCAST ||
11446 User->getValueType(0) != MVT::i32))
11448 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11449 DAG.getBitcast(MVT::v4i32, Op.getOperand(0)),
11451 return DAG.getBitcast(MVT::f32, Extract);
11454 if (VT == MVT::i32 || VT == MVT::i64) {
11455 // ExtractPS/pextrq works with constant index.
11456 if (isa<ConstantSDNode>(Op.getOperand(1)))
11462 /// Extract one bit from mask vector, like v16i1 or v8i1.
11463 /// AVX-512 feature.
11465 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
11466 SDValue Vec = Op.getOperand(0);
11468 MVT VecVT = Vec.getSimpleValueType();
11469 SDValue Idx = Op.getOperand(1);
11470 MVT EltVT = Op.getSimpleValueType();
11472 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
11473 assert((VecVT.getVectorNumElements() <= 16 || Subtarget->hasBWI()) &&
11474 "Unexpected vector type in ExtractBitFromMaskVector");
11476 // variable index can't be handled in mask registers,
11477 // extend vector to VR512
11478 if (!isa<ConstantSDNode>(Idx)) {
11479 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11480 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
11481 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
11482 ExtVT.getVectorElementType(), Ext, Idx);
11483 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
11486 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11487 const TargetRegisterClass* rc = getRegClassFor(VecVT);
11488 if (!Subtarget->hasDQI() && (VecVT.getVectorNumElements() <= 8))
11489 rc = getRegClassFor(MVT::v16i1);
11490 unsigned MaxSift = rc->getSize()*8 - 1;
11491 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
11492 DAG.getConstant(MaxSift - IdxVal, dl, MVT::i8));
11493 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
11494 DAG.getConstant(MaxSift, dl, MVT::i8));
11495 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
11496 DAG.getIntPtrConstant(0, dl));
11500 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
11501 SelectionDAG &DAG) const {
11503 SDValue Vec = Op.getOperand(0);
11504 MVT VecVT = Vec.getSimpleValueType();
11505 SDValue Idx = Op.getOperand(1);
11507 if (Op.getSimpleValueType() == MVT::i1)
11508 return ExtractBitFromMaskVector(Op, DAG);
11510 if (!isa<ConstantSDNode>(Idx)) {
11511 if (VecVT.is512BitVector() ||
11512 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
11513 VecVT.getVectorElementType().getSizeInBits() == 32)) {
11516 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
11517 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
11518 MaskEltVT.getSizeInBits());
11520 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
11521 auto PtrVT = getPointerTy(DAG.getDataLayout());
11522 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
11523 getZeroVector(MaskVT, Subtarget, DAG, dl), Idx,
11524 DAG.getConstant(0, dl, PtrVT));
11525 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
11526 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Perm,
11527 DAG.getConstant(0, dl, PtrVT));
11532 // If this is a 256-bit vector result, first extract the 128-bit vector and
11533 // then extract the element from the 128-bit vector.
11534 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
11536 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11537 // Get the 128-bit vector.
11538 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
11539 MVT EltVT = VecVT.getVectorElementType();
11541 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
11542 assert(isPowerOf2_32(ElemsPerChunk) && "Elements per chunk not power of 2");
11544 // Find IdxVal modulo ElemsPerChunk. Since ElemsPerChunk is a power of 2
11545 // this can be done with a mask.
11546 IdxVal &= ElemsPerChunk - 1;
11547 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
11548 DAG.getConstant(IdxVal, dl, MVT::i32));
11551 assert(VecVT.is128BitVector() && "Unexpected vector length");
11553 if (Subtarget->hasSSE41())
11554 if (SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG))
11557 MVT VT = Op.getSimpleValueType();
11558 // TODO: handle v16i8.
11559 if (VT.getSizeInBits() == 16) {
11560 SDValue Vec = Op.getOperand(0);
11561 if (isNullConstant(Op.getOperand(1)))
11562 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
11563 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11564 DAG.getBitcast(MVT::v4i32, Vec),
11565 Op.getOperand(1)));
11566 // Transform it so it match pextrw which produces a 32-bit result.
11567 MVT EltVT = MVT::i32;
11568 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
11569 Op.getOperand(0), Op.getOperand(1));
11570 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
11571 DAG.getValueType(VT));
11572 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11575 if (VT.getSizeInBits() == 32) {
11576 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11580 // SHUFPS the element to the lowest double word, then movss.
11581 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
11582 MVT VVT = Op.getOperand(0).getSimpleValueType();
11583 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
11584 DAG.getUNDEF(VVT), Mask);
11585 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
11586 DAG.getIntPtrConstant(0, dl));
11589 if (VT.getSizeInBits() == 64) {
11590 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
11591 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
11592 // to match extract_elt for f64.
11593 if (isNullConstant(Op.getOperand(1)))
11596 // UNPCKHPD the element to the lowest double word, then movsd.
11597 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
11598 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
11599 int Mask[2] = { 1, -1 };
11600 MVT VVT = Op.getOperand(0).getSimpleValueType();
11601 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
11602 DAG.getUNDEF(VVT), Mask);
11603 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
11604 DAG.getIntPtrConstant(0, dl));
11610 /// Insert one bit to mask vector, like v16i1 or v8i1.
11611 /// AVX-512 feature.
11613 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
11615 SDValue Vec = Op.getOperand(0);
11616 SDValue Elt = Op.getOperand(1);
11617 SDValue Idx = Op.getOperand(2);
11618 MVT VecVT = Vec.getSimpleValueType();
11620 if (!isa<ConstantSDNode>(Idx)) {
11621 // Non constant index. Extend source and destination,
11622 // insert element and then truncate the result.
11623 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11624 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
11625 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
11626 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
11627 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
11628 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
11631 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11632 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
11634 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
11635 DAG.getConstant(IdxVal, dl, MVT::i8));
11636 if (Vec.getOpcode() == ISD::UNDEF)
11638 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
11641 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
11642 SelectionDAG &DAG) const {
11643 MVT VT = Op.getSimpleValueType();
11644 MVT EltVT = VT.getVectorElementType();
11646 if (EltVT == MVT::i1)
11647 return InsertBitToMaskVector(Op, DAG);
11650 SDValue N0 = Op.getOperand(0);
11651 SDValue N1 = Op.getOperand(1);
11652 SDValue N2 = Op.getOperand(2);
11653 if (!isa<ConstantSDNode>(N2))
11655 auto *N2C = cast<ConstantSDNode>(N2);
11656 unsigned IdxVal = N2C->getZExtValue();
11658 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
11659 // into that, and then insert the subvector back into the result.
11660 if (VT.is256BitVector() || VT.is512BitVector()) {
11661 // With a 256-bit vector, we can insert into the zero element efficiently
11662 // using a blend if we have AVX or AVX2 and the right data type.
11663 if (VT.is256BitVector() && IdxVal == 0) {
11664 // TODO: It is worthwhile to cast integer to floating point and back
11665 // and incur a domain crossing penalty if that's what we'll end up
11666 // doing anyway after extracting to a 128-bit vector.
11667 if ((Subtarget->hasAVX() && (EltVT == MVT::f64 || EltVT == MVT::f32)) ||
11668 (Subtarget->hasAVX2() && EltVT == MVT::i32)) {
11669 SDValue N1Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, N1);
11670 N2 = DAG.getIntPtrConstant(1, dl);
11671 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1Vec, N2);
11675 // Get the desired 128-bit vector chunk.
11676 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
11678 // Insert the element into the desired chunk.
11679 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
11680 assert(isPowerOf2_32(NumEltsIn128));
11681 // Since NumEltsIn128 is a power of 2 we can use mask instead of modulo.
11682 unsigned IdxIn128 = IdxVal & (NumEltsIn128 - 1);
11684 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
11685 DAG.getConstant(IdxIn128, dl, MVT::i32));
11687 // Insert the changed part back into the bigger vector
11688 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
11690 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
11692 if (Subtarget->hasSSE41()) {
11693 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
11695 if (VT == MVT::v8i16) {
11696 Opc = X86ISD::PINSRW;
11698 assert(VT == MVT::v16i8);
11699 Opc = X86ISD::PINSRB;
11702 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
11704 if (N1.getValueType() != MVT::i32)
11705 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11706 if (N2.getValueType() != MVT::i32)
11707 N2 = DAG.getIntPtrConstant(IdxVal, dl);
11708 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
11711 if (EltVT == MVT::f32) {
11712 // Bits [7:6] of the constant are the source select. This will always be
11713 // zero here. The DAG Combiner may combine an extract_elt index into
11714 // these bits. For example (insert (extract, 3), 2) could be matched by
11715 // putting the '3' into bits [7:6] of X86ISD::INSERTPS.
11716 // Bits [5:4] of the constant are the destination select. This is the
11717 // value of the incoming immediate.
11718 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
11719 // combine either bitwise AND or insert of float 0.0 to set these bits.
11721 bool MinSize = DAG.getMachineFunction().getFunction()->optForMinSize();
11722 if (IdxVal == 0 && (!MinSize || !MayFoldLoad(N1))) {
11723 // If this is an insertion of 32-bits into the low 32-bits of
11724 // a vector, we prefer to generate a blend with immediate rather
11725 // than an insertps. Blends are simpler operations in hardware and so
11726 // will always have equal or better performance than insertps.
11727 // But if optimizing for size and there's a load folding opportunity,
11728 // generate insertps because blendps does not have a 32-bit memory
11730 N2 = DAG.getIntPtrConstant(1, dl);
11731 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
11732 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1, N2);
11734 N2 = DAG.getIntPtrConstant(IdxVal << 4, dl);
11735 // Create this as a scalar to vector..
11736 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
11737 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
11740 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
11741 // PINSR* works with constant index.
11746 if (EltVT == MVT::i8)
11749 if (EltVT.getSizeInBits() == 16) {
11750 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
11751 // as its second argument.
11752 if (N1.getValueType() != MVT::i32)
11753 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11754 if (N2.getValueType() != MVT::i32)
11755 N2 = DAG.getIntPtrConstant(IdxVal, dl);
11756 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
11761 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
11763 MVT OpVT = Op.getSimpleValueType();
11765 // If this is a 256-bit vector result, first insert into a 128-bit
11766 // vector and then insert into the 256-bit vector.
11767 if (!OpVT.is128BitVector()) {
11768 // Insert into a 128-bit vector.
11769 unsigned SizeFactor = OpVT.getSizeInBits()/128;
11770 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
11771 OpVT.getVectorNumElements() / SizeFactor);
11773 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
11775 // Insert the 128-bit vector.
11776 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
11779 if (OpVT == MVT::v1i64 &&
11780 Op.getOperand(0).getValueType() == MVT::i64)
11781 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
11783 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
11784 assert(OpVT.is128BitVector() && "Expected an SSE type!");
11785 return DAG.getBitcast(
11786 OpVT, DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, AnyExt));
11789 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
11790 // a simple subregister reference or explicit instructions to grab
11791 // upper bits of a vector.
11792 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11793 SelectionDAG &DAG) {
11795 SDValue In = Op.getOperand(0);
11796 SDValue Idx = Op.getOperand(1);
11797 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11798 MVT ResVT = Op.getSimpleValueType();
11799 MVT InVT = In.getSimpleValueType();
11801 if (Subtarget->hasFp256()) {
11802 if (ResVT.is128BitVector() &&
11803 (InVT.is256BitVector() || InVT.is512BitVector()) &&
11804 isa<ConstantSDNode>(Idx)) {
11805 return Extract128BitVector(In, IdxVal, DAG, dl);
11807 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
11808 isa<ConstantSDNode>(Idx)) {
11809 return Extract256BitVector(In, IdxVal, DAG, dl);
11815 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
11816 // simple superregister reference or explicit instructions to insert
11817 // the upper bits of a vector.
11818 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11819 SelectionDAG &DAG) {
11820 if (!Subtarget->hasAVX())
11824 SDValue Vec = Op.getOperand(0);
11825 SDValue SubVec = Op.getOperand(1);
11826 SDValue Idx = Op.getOperand(2);
11828 if (!isa<ConstantSDNode>(Idx))
11831 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11832 MVT OpVT = Op.getSimpleValueType();
11833 MVT SubVecVT = SubVec.getSimpleValueType();
11835 // Fold two 16-byte subvector loads into one 32-byte load:
11836 // (insert_subvector (insert_subvector undef, (load addr), 0),
11837 // (load addr + 16), Elts/2)
11839 if ((IdxVal == OpVT.getVectorNumElements() / 2) &&
11840 Vec.getOpcode() == ISD::INSERT_SUBVECTOR &&
11841 OpVT.is256BitVector() && SubVecVT.is128BitVector()) {
11842 auto *Idx2 = dyn_cast<ConstantSDNode>(Vec.getOperand(2));
11843 if (Idx2 && Idx2->getZExtValue() == 0) {
11844 SDValue SubVec2 = Vec.getOperand(1);
11845 // If needed, look through a bitcast to get to the load.
11846 if (SubVec2.getNode() && SubVec2.getOpcode() == ISD::BITCAST)
11847 SubVec2 = SubVec2.getOperand(0);
11849 if (auto *FirstLd = dyn_cast<LoadSDNode>(SubVec2)) {
11851 unsigned Alignment = FirstLd->getAlignment();
11852 unsigned AS = FirstLd->getAddressSpace();
11853 const X86TargetLowering *TLI = Subtarget->getTargetLowering();
11854 if (TLI->allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(),
11855 OpVT, AS, Alignment, &Fast) && Fast) {
11856 SDValue Ops[] = { SubVec2, SubVec };
11857 if (SDValue Ld = EltsFromConsecutiveLoads(OpVT, Ops, dl, DAG, false))
11864 if ((OpVT.is256BitVector() || OpVT.is512BitVector()) &&
11865 SubVecVT.is128BitVector())
11866 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
11868 if (OpVT.is512BitVector() && SubVecVT.is256BitVector())
11869 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
11871 if (OpVT.getVectorElementType() == MVT::i1)
11872 return Insert1BitVector(Op, DAG);
11877 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
11878 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
11879 // one of the above mentioned nodes. It has to be wrapped because otherwise
11880 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
11881 // be used to form addressing mode. These wrapped nodes will be selected
11884 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
11885 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
11887 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11888 // global base reg.
11889 unsigned char OpFlag = 0;
11890 unsigned WrapperKind = X86ISD::Wrapper;
11891 CodeModel::Model M = DAG.getTarget().getCodeModel();
11893 if (Subtarget->isPICStyleRIPRel() &&
11894 (M == CodeModel::Small || M == CodeModel::Kernel))
11895 WrapperKind = X86ISD::WrapperRIP;
11896 else if (Subtarget->isPICStyleGOT())
11897 OpFlag = X86II::MO_GOTOFF;
11898 else if (Subtarget->isPICStyleStubPIC())
11899 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11901 auto PtrVT = getPointerTy(DAG.getDataLayout());
11902 SDValue Result = DAG.getTargetConstantPool(
11903 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(), OpFlag);
11905 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11906 // With PIC, the address is actually $g + Offset.
11909 DAG.getNode(ISD::ADD, DL, PtrVT,
11910 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
11916 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
11917 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
11919 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11920 // global base reg.
11921 unsigned char OpFlag = 0;
11922 unsigned WrapperKind = X86ISD::Wrapper;
11923 CodeModel::Model M = DAG.getTarget().getCodeModel();
11925 if (Subtarget->isPICStyleRIPRel() &&
11926 (M == CodeModel::Small || M == CodeModel::Kernel))
11927 WrapperKind = X86ISD::WrapperRIP;
11928 else if (Subtarget->isPICStyleGOT())
11929 OpFlag = X86II::MO_GOTOFF;
11930 else if (Subtarget->isPICStyleStubPIC())
11931 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11933 auto PtrVT = getPointerTy(DAG.getDataLayout());
11934 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OpFlag);
11936 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11938 // With PIC, the address is actually $g + Offset.
11941 DAG.getNode(ISD::ADD, DL, PtrVT,
11942 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
11948 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
11949 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
11951 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11952 // global base reg.
11953 unsigned char OpFlag = 0;
11954 unsigned WrapperKind = X86ISD::Wrapper;
11955 CodeModel::Model M = DAG.getTarget().getCodeModel();
11957 if (Subtarget->isPICStyleRIPRel() &&
11958 (M == CodeModel::Small || M == CodeModel::Kernel)) {
11959 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
11960 OpFlag = X86II::MO_GOTPCREL;
11961 WrapperKind = X86ISD::WrapperRIP;
11962 } else if (Subtarget->isPICStyleGOT()) {
11963 OpFlag = X86II::MO_GOT;
11964 } else if (Subtarget->isPICStyleStubPIC()) {
11965 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
11966 } else if (Subtarget->isPICStyleStubNoDynamic()) {
11967 OpFlag = X86II::MO_DARWIN_NONLAZY;
11970 auto PtrVT = getPointerTy(DAG.getDataLayout());
11971 SDValue Result = DAG.getTargetExternalSymbol(Sym, PtrVT, OpFlag);
11974 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11976 // With PIC, the address is actually $g + Offset.
11977 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
11978 !Subtarget->is64Bit()) {
11980 DAG.getNode(ISD::ADD, DL, PtrVT,
11981 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
11984 // For symbols that require a load from a stub to get the address, emit the
11986 if (isGlobalStubReference(OpFlag))
11987 Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
11988 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
11989 false, false, false, 0);
11995 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
11996 // Create the TargetBlockAddressAddress node.
11997 unsigned char OpFlags =
11998 Subtarget->ClassifyBlockAddressReference();
11999 CodeModel::Model M = DAG.getTarget().getCodeModel();
12000 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
12001 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
12003 auto PtrVT = getPointerTy(DAG.getDataLayout());
12004 SDValue Result = DAG.getTargetBlockAddress(BA, PtrVT, Offset, OpFlags);
12006 if (Subtarget->isPICStyleRIPRel() &&
12007 (M == CodeModel::Small || M == CodeModel::Kernel))
12008 Result = DAG.getNode(X86ISD::WrapperRIP, dl, PtrVT, Result);
12010 Result = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, Result);
12012 // With PIC, the address is actually $g + Offset.
12013 if (isGlobalRelativeToPICBase(OpFlags)) {
12014 Result = DAG.getNode(ISD::ADD, dl, PtrVT,
12015 DAG.getNode(X86ISD::GlobalBaseReg, dl, PtrVT), Result);
12022 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
12023 int64_t Offset, SelectionDAG &DAG) const {
12024 // Create the TargetGlobalAddress node, folding in the constant
12025 // offset if it is legal.
12026 unsigned char OpFlags =
12027 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
12028 CodeModel::Model M = DAG.getTarget().getCodeModel();
12029 auto PtrVT = getPointerTy(DAG.getDataLayout());
12031 if (OpFlags == X86II::MO_NO_FLAG &&
12032 X86::isOffsetSuitableForCodeModel(Offset, M)) {
12033 // A direct static reference to a global.
12034 Result = DAG.getTargetGlobalAddress(GV, dl, PtrVT, Offset);
12037 Result = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, OpFlags);
12040 if (Subtarget->isPICStyleRIPRel() &&
12041 (M == CodeModel::Small || M == CodeModel::Kernel))
12042 Result = DAG.getNode(X86ISD::WrapperRIP, dl, PtrVT, Result);
12044 Result = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, Result);
12046 // With PIC, the address is actually $g + Offset.
12047 if (isGlobalRelativeToPICBase(OpFlags)) {
12048 Result = DAG.getNode(ISD::ADD, dl, PtrVT,
12049 DAG.getNode(X86ISD::GlobalBaseReg, dl, PtrVT), Result);
12052 // For globals that require a load from a stub to get the address, emit the
12054 if (isGlobalStubReference(OpFlags))
12055 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
12056 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
12057 false, false, false, 0);
12059 // If there was a non-zero offset that we didn't fold, create an explicit
12060 // addition for it.
12062 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result,
12063 DAG.getConstant(Offset, dl, PtrVT));
12069 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
12070 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
12071 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
12072 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
12076 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
12077 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
12078 unsigned char OperandFlags, bool LocalDynamic = false) {
12079 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12080 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12082 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12083 GA->getValueType(0),
12087 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
12091 SDValue Ops[] = { Chain, TGA, *InFlag };
12092 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
12094 SDValue Ops[] = { Chain, TGA };
12095 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
12098 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
12099 MFI->setAdjustsStack(true);
12100 MFI->setHasCalls(true);
12102 SDValue Flag = Chain.getValue(1);
12103 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
12106 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
12108 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12111 SDLoc dl(GA); // ? function entry point might be better
12112 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
12113 DAG.getNode(X86ISD::GlobalBaseReg,
12114 SDLoc(), PtrVT), InFlag);
12115 InFlag = Chain.getValue(1);
12117 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
12120 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
12122 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12124 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
12125 X86::RAX, X86II::MO_TLSGD);
12128 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
12134 // Get the start address of the TLS block for this module.
12135 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
12136 .getInfo<X86MachineFunctionInfo>();
12137 MFI->incNumLocalDynamicTLSAccesses();
12141 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
12142 X86II::MO_TLSLD, /*LocalDynamic=*/true);
12145 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
12146 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
12147 InFlag = Chain.getValue(1);
12148 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
12149 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
12152 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
12156 unsigned char OperandFlags = X86II::MO_DTPOFF;
12157 unsigned WrapperKind = X86ISD::Wrapper;
12158 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12159 GA->getValueType(0),
12160 GA->getOffset(), OperandFlags);
12161 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12163 // Add x@dtpoff with the base.
12164 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
12167 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
12168 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12169 const EVT PtrVT, TLSModel::Model model,
12170 bool is64Bit, bool isPIC) {
12173 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
12174 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
12175 is64Bit ? 257 : 256));
12177 SDValue ThreadPointer =
12178 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0, dl),
12179 MachinePointerInfo(Ptr), false, false, false, 0);
12181 unsigned char OperandFlags = 0;
12182 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
12184 unsigned WrapperKind = X86ISD::Wrapper;
12185 if (model == TLSModel::LocalExec) {
12186 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
12187 } else if (model == TLSModel::InitialExec) {
12189 OperandFlags = X86II::MO_GOTTPOFF;
12190 WrapperKind = X86ISD::WrapperRIP;
12192 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
12195 llvm_unreachable("Unexpected model");
12198 // emit "addl x@ntpoff,%eax" (local exec)
12199 // or "addl x@indntpoff,%eax" (initial exec)
12200 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
12202 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
12203 GA->getOffset(), OperandFlags);
12204 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12206 if (model == TLSModel::InitialExec) {
12207 if (isPIC && !is64Bit) {
12208 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
12209 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
12213 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
12214 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
12215 false, false, false, 0);
12218 // The address of the thread local variable is the add of the thread
12219 // pointer with the offset of the variable.
12220 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
12224 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
12226 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
12227 const GlobalValue *GV = GA->getGlobal();
12228 auto PtrVT = getPointerTy(DAG.getDataLayout());
12230 if (Subtarget->isTargetELF()) {
12231 if (DAG.getTarget().Options.EmulatedTLS)
12232 return LowerToTLSEmulatedModel(GA, DAG);
12233 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
12235 case TLSModel::GeneralDynamic:
12236 if (Subtarget->is64Bit())
12237 return LowerToTLSGeneralDynamicModel64(GA, DAG, PtrVT);
12238 return LowerToTLSGeneralDynamicModel32(GA, DAG, PtrVT);
12239 case TLSModel::LocalDynamic:
12240 return LowerToTLSLocalDynamicModel(GA, DAG, PtrVT,
12241 Subtarget->is64Bit());
12242 case TLSModel::InitialExec:
12243 case TLSModel::LocalExec:
12244 return LowerToTLSExecModel(GA, DAG, PtrVT, model, Subtarget->is64Bit(),
12245 DAG.getTarget().getRelocationModel() ==
12248 llvm_unreachable("Unknown TLS model.");
12251 if (Subtarget->isTargetDarwin()) {
12252 // Darwin only has one model of TLS. Lower to that.
12253 unsigned char OpFlag = 0;
12254 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
12255 X86ISD::WrapperRIP : X86ISD::Wrapper;
12257 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12258 // global base reg.
12259 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
12260 !Subtarget->is64Bit();
12262 OpFlag = X86II::MO_TLVP_PIC_BASE;
12264 OpFlag = X86II::MO_TLVP;
12266 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
12267 GA->getValueType(0),
12268 GA->getOffset(), OpFlag);
12269 SDValue Offset = DAG.getNode(WrapperKind, DL, PtrVT, Result);
12271 // With PIC32, the address is actually $g + Offset.
12273 Offset = DAG.getNode(ISD::ADD, DL, PtrVT,
12274 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
12277 // Lowering the machine isd will make sure everything is in the right
12279 SDValue Chain = DAG.getEntryNode();
12280 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12281 SDValue Args[] = { Chain, Offset };
12282 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
12284 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
12285 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12286 MFI->setAdjustsStack(true);
12288 // And our return value (tls address) is in the standard call return value
12290 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
12291 return DAG.getCopyFromReg(Chain, DL, Reg, PtrVT, Chain.getValue(1));
12294 if (Subtarget->isTargetKnownWindowsMSVC() ||
12295 Subtarget->isTargetWindowsGNU()) {
12296 // Just use the implicit TLS architecture
12297 // Need to generate someting similar to:
12298 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
12300 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
12301 // mov rcx, qword [rdx+rcx*8]
12302 // mov eax, .tls$:tlsvar
12303 // [rax+rcx] contains the address
12304 // Windows 64bit: gs:0x58
12305 // Windows 32bit: fs:__tls_array
12308 SDValue Chain = DAG.getEntryNode();
12310 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
12311 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
12312 // use its literal value of 0x2C.
12313 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
12314 ? Type::getInt8PtrTy(*DAG.getContext(),
12316 : Type::getInt32PtrTy(*DAG.getContext(),
12319 SDValue TlsArray = Subtarget->is64Bit()
12320 ? DAG.getIntPtrConstant(0x58, dl)
12321 : (Subtarget->isTargetWindowsGNU()
12322 ? DAG.getIntPtrConstant(0x2C, dl)
12323 : DAG.getExternalSymbol("_tls_array", PtrVT));
12325 SDValue ThreadPointer =
12326 DAG.getLoad(PtrVT, dl, Chain, TlsArray, MachinePointerInfo(Ptr), false,
12330 if (GV->getThreadLocalMode() == GlobalVariable::LocalExecTLSModel) {
12331 res = ThreadPointer;
12333 // Load the _tls_index variable
12334 SDValue IDX = DAG.getExternalSymbol("_tls_index", PtrVT);
12335 if (Subtarget->is64Bit())
12336 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, PtrVT, Chain, IDX,
12337 MachinePointerInfo(), MVT::i32, false, false,
12340 IDX = DAG.getLoad(PtrVT, dl, Chain, IDX, MachinePointerInfo(), false,
12343 auto &DL = DAG.getDataLayout();
12345 DAG.getConstant(Log2_64_Ceil(DL.getPointerSize()), dl, PtrVT);
12346 IDX = DAG.getNode(ISD::SHL, dl, PtrVT, IDX, Scale);
12348 res = DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, IDX);
12351 res = DAG.getLoad(PtrVT, dl, Chain, res, MachinePointerInfo(), false, false,
12354 // Get the offset of start of .tls section
12355 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12356 GA->getValueType(0),
12357 GA->getOffset(), X86II::MO_SECREL);
12358 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, TGA);
12360 // The address of the thread local variable is the add of the thread
12361 // pointer with the offset of the variable.
12362 return DAG.getNode(ISD::ADD, dl, PtrVT, res, Offset);
12365 llvm_unreachable("TLS not implemented for this target.");
12368 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
12369 /// and take a 2 x i32 value to shift plus a shift amount.
12370 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
12371 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
12372 MVT VT = Op.getSimpleValueType();
12373 unsigned VTBits = VT.getSizeInBits();
12375 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
12376 SDValue ShOpLo = Op.getOperand(0);
12377 SDValue ShOpHi = Op.getOperand(1);
12378 SDValue ShAmt = Op.getOperand(2);
12379 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
12380 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
12382 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12383 DAG.getConstant(VTBits - 1, dl, MVT::i8));
12384 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
12385 DAG.getConstant(VTBits - 1, dl, MVT::i8))
12386 : DAG.getConstant(0, dl, VT);
12388 SDValue Tmp2, Tmp3;
12389 if (Op.getOpcode() == ISD::SHL_PARTS) {
12390 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
12391 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
12393 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
12394 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
12397 // If the shift amount is larger or equal than the width of a part we can't
12398 // rely on the results of shld/shrd. Insert a test and select the appropriate
12399 // values for large shift amounts.
12400 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12401 DAG.getConstant(VTBits, dl, MVT::i8));
12402 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
12403 AndNode, DAG.getConstant(0, dl, MVT::i8));
12406 SDValue CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
12407 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
12408 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
12410 if (Op.getOpcode() == ISD::SHL_PARTS) {
12411 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12412 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12414 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12415 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12418 SDValue Ops[2] = { Lo, Hi };
12419 return DAG.getMergeValues(Ops, dl);
12422 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
12423 SelectionDAG &DAG) const {
12424 SDValue Src = Op.getOperand(0);
12425 MVT SrcVT = Src.getSimpleValueType();
12426 MVT VT = Op.getSimpleValueType();
12429 if (SrcVT.isVector()) {
12430 if (SrcVT == MVT::v2i32 && VT == MVT::v2f64) {
12431 return DAG.getNode(X86ISD::CVTDQ2PD, dl, VT,
12432 DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4i32, Src,
12433 DAG.getUNDEF(SrcVT)));
12435 if (SrcVT.getVectorElementType() == MVT::i1) {
12436 MVT IntegerVT = MVT::getVectorVT(MVT::i32, SrcVT.getVectorNumElements());
12437 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
12438 DAG.getNode(ISD::SIGN_EXTEND, dl, IntegerVT, Src));
12443 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
12444 "Unknown SINT_TO_FP to lower!");
12446 // These are really Legal; return the operand so the caller accepts it as
12448 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
12450 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
12451 Subtarget->is64Bit()) {
12455 unsigned Size = SrcVT.getSizeInBits()/8;
12456 MachineFunction &MF = DAG.getMachineFunction();
12457 auto PtrVT = getPointerTy(MF.getDataLayout());
12458 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
12459 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12460 SDValue Chain = DAG.getStore(
12461 DAG.getEntryNode(), dl, Op.getOperand(0), StackSlot,
12462 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI), false,
12464 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
12467 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
12469 SelectionDAG &DAG) const {
12473 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
12475 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
12477 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
12479 unsigned ByteSize = SrcVT.getSizeInBits()/8;
12481 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
12482 MachineMemOperand *MMO;
12484 int SSFI = FI->getIndex();
12485 MMO = DAG.getMachineFunction().getMachineMemOperand(
12486 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12487 MachineMemOperand::MOLoad, ByteSize, ByteSize);
12489 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
12490 StackSlot = StackSlot.getOperand(1);
12492 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
12493 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
12495 Tys, Ops, SrcVT, MMO);
12498 Chain = Result.getValue(1);
12499 SDValue InFlag = Result.getValue(2);
12501 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
12502 // shouldn't be necessary except that RFP cannot be live across
12503 // multiple blocks. When stackifier is fixed, they can be uncoupled.
12504 MachineFunction &MF = DAG.getMachineFunction();
12505 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
12506 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
12507 auto PtrVT = getPointerTy(MF.getDataLayout());
12508 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12509 Tys = DAG.getVTList(MVT::Other);
12511 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
12513 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
12514 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12515 MachineMemOperand::MOStore, SSFISize, SSFISize);
12517 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
12518 Ops, Op.getValueType(), MMO);
12519 Result = DAG.getLoad(
12520 Op.getValueType(), DL, Chain, StackSlot,
12521 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12522 false, false, false, 0);
12528 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
12529 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
12530 SelectionDAG &DAG) const {
12531 // This algorithm is not obvious. Here it is what we're trying to output:
12534 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
12535 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
12537 haddpd %xmm0, %xmm0
12539 pshufd $0x4e, %xmm0, %xmm1
12545 LLVMContext *Context = DAG.getContext();
12547 // Build some magic constants.
12548 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
12549 Constant *C0 = ConstantDataVector::get(*Context, CV0);
12550 auto PtrVT = getPointerTy(DAG.getDataLayout());
12551 SDValue CPIdx0 = DAG.getConstantPool(C0, PtrVT, 16);
12553 SmallVector<Constant*,2> CV1;
12555 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12556 APInt(64, 0x4330000000000000ULL))));
12558 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12559 APInt(64, 0x4530000000000000ULL))));
12560 Constant *C1 = ConstantVector::get(CV1);
12561 SDValue CPIdx1 = DAG.getConstantPool(C1, PtrVT, 16);
12563 // Load the 64-bit value into an XMM register.
12564 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
12567 DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
12568 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
12569 false, false, false, 16);
12571 getUnpackl(DAG, dl, MVT::v4i32, DAG.getBitcast(MVT::v4i32, XR1), CLod0);
12574 DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
12575 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
12576 false, false, false, 16);
12577 SDValue XR2F = DAG.getBitcast(MVT::v2f64, Unpck1);
12578 // TODO: Are there any fast-math-flags to propagate here?
12579 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
12582 if (Subtarget->hasSSE3()) {
12583 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
12584 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
12586 SDValue S2F = DAG.getBitcast(MVT::v4i32, Sub);
12587 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
12589 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
12590 DAG.getBitcast(MVT::v2f64, Shuffle), Sub);
12593 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
12594 DAG.getIntPtrConstant(0, dl));
12597 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
12598 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
12599 SelectionDAG &DAG) const {
12601 // FP constant to bias correct the final result.
12602 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
12605 // Load the 32-bit value into an XMM register.
12606 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
12609 // Zero out the upper parts of the register.
12610 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
12612 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
12613 DAG.getBitcast(MVT::v2f64, Load),
12614 DAG.getIntPtrConstant(0, dl));
12616 // Or the load with the bias.
12617 SDValue Or = DAG.getNode(
12618 ISD::OR, dl, MVT::v2i64,
12619 DAG.getBitcast(MVT::v2i64,
12620 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, Load)),
12621 DAG.getBitcast(MVT::v2i64,
12622 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, Bias)));
12624 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
12625 DAG.getBitcast(MVT::v2f64, Or), DAG.getIntPtrConstant(0, dl));
12627 // Subtract the bias.
12628 // TODO: Are there any fast-math-flags to propagate here?
12629 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
12631 // Handle final rounding.
12632 MVT DestVT = Op.getSimpleValueType();
12634 if (DestVT.bitsLT(MVT::f64))
12635 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
12636 DAG.getIntPtrConstant(0, dl));
12637 if (DestVT.bitsGT(MVT::f64))
12638 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
12640 // Handle final rounding.
12644 static SDValue lowerUINT_TO_FP_vXi32(SDValue Op, SelectionDAG &DAG,
12645 const X86Subtarget &Subtarget) {
12646 // The algorithm is the following:
12647 // #ifdef __SSE4_1__
12648 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
12649 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
12650 // (uint4) 0x53000000, 0xaa);
12652 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
12653 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
12655 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
12656 // return (float4) lo + fhi;
12658 // We shouldn't use it when unsafe-fp-math is enabled though: we might later
12659 // reassociate the two FADDs, and if we do that, the algorithm fails
12660 // spectacularly (PR24512).
12661 // FIXME: If we ever have some kind of Machine FMF, this should be marked
12662 // as non-fast and always be enabled. Why isn't SDAG FMF enough? Because
12663 // there's also the MachineCombiner reassociations happening on Machine IR.
12664 if (DAG.getTarget().Options.UnsafeFPMath)
12668 SDValue V = Op->getOperand(0);
12669 MVT VecIntVT = V.getSimpleValueType();
12670 bool Is128 = VecIntVT == MVT::v4i32;
12671 MVT VecFloatVT = Is128 ? MVT::v4f32 : MVT::v8f32;
12672 // If we convert to something else than the supported type, e.g., to v4f64,
12674 if (VecFloatVT != Op->getSimpleValueType(0))
12677 unsigned NumElts = VecIntVT.getVectorNumElements();
12678 assert((VecIntVT == MVT::v4i32 || VecIntVT == MVT::v8i32) &&
12679 "Unsupported custom type");
12680 assert(NumElts <= 8 && "The size of the constant array must be fixed");
12682 // In the #idef/#else code, we have in common:
12683 // - The vector of constants:
12689 // Create the splat vector for 0x4b000000.
12690 SDValue CstLow = DAG.getConstant(0x4b000000, DL, MVT::i32);
12691 SDValue CstLowArray[] = {CstLow, CstLow, CstLow, CstLow,
12692 CstLow, CstLow, CstLow, CstLow};
12693 SDValue VecCstLow = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12694 makeArrayRef(&CstLowArray[0], NumElts));
12695 // Create the splat vector for 0x53000000.
12696 SDValue CstHigh = DAG.getConstant(0x53000000, DL, MVT::i32);
12697 SDValue CstHighArray[] = {CstHigh, CstHigh, CstHigh, CstHigh,
12698 CstHigh, CstHigh, CstHigh, CstHigh};
12699 SDValue VecCstHigh = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12700 makeArrayRef(&CstHighArray[0], NumElts));
12702 // Create the right shift.
12703 SDValue CstShift = DAG.getConstant(16, DL, MVT::i32);
12704 SDValue CstShiftArray[] = {CstShift, CstShift, CstShift, CstShift,
12705 CstShift, CstShift, CstShift, CstShift};
12706 SDValue VecCstShift = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12707 makeArrayRef(&CstShiftArray[0], NumElts));
12708 SDValue HighShift = DAG.getNode(ISD::SRL, DL, VecIntVT, V, VecCstShift);
12711 if (Subtarget.hasSSE41()) {
12712 MVT VecI16VT = Is128 ? MVT::v8i16 : MVT::v16i16;
12713 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
12714 SDValue VecCstLowBitcast = DAG.getBitcast(VecI16VT, VecCstLow);
12715 SDValue VecBitcast = DAG.getBitcast(VecI16VT, V);
12716 // Low will be bitcasted right away, so do not bother bitcasting back to its
12718 Low = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecBitcast,
12719 VecCstLowBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
12720 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
12721 // (uint4) 0x53000000, 0xaa);
12722 SDValue VecCstHighBitcast = DAG.getBitcast(VecI16VT, VecCstHigh);
12723 SDValue VecShiftBitcast = DAG.getBitcast(VecI16VT, HighShift);
12724 // High will be bitcasted right away, so do not bother bitcasting back to
12725 // its original type.
12726 High = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecShiftBitcast,
12727 VecCstHighBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
12729 SDValue CstMask = DAG.getConstant(0xffff, DL, MVT::i32);
12730 SDValue VecCstMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, CstMask,
12731 CstMask, CstMask, CstMask);
12732 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
12733 SDValue LowAnd = DAG.getNode(ISD::AND, DL, VecIntVT, V, VecCstMask);
12734 Low = DAG.getNode(ISD::OR, DL, VecIntVT, LowAnd, VecCstLow);
12736 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
12737 High = DAG.getNode(ISD::OR, DL, VecIntVT, HighShift, VecCstHigh);
12740 // Create the vector constant for -(0x1.0p39f + 0x1.0p23f).
12741 SDValue CstFAdd = DAG.getConstantFP(
12742 APFloat(APFloat::IEEEsingle, APInt(32, 0xD3000080)), DL, MVT::f32);
12743 SDValue CstFAddArray[] = {CstFAdd, CstFAdd, CstFAdd, CstFAdd,
12744 CstFAdd, CstFAdd, CstFAdd, CstFAdd};
12745 SDValue VecCstFAdd = DAG.getNode(ISD::BUILD_VECTOR, DL, VecFloatVT,
12746 makeArrayRef(&CstFAddArray[0], NumElts));
12748 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
12749 SDValue HighBitcast = DAG.getBitcast(VecFloatVT, High);
12750 // TODO: Are there any fast-math-flags to propagate here?
12752 DAG.getNode(ISD::FADD, DL, VecFloatVT, HighBitcast, VecCstFAdd);
12753 // return (float4) lo + fhi;
12754 SDValue LowBitcast = DAG.getBitcast(VecFloatVT, Low);
12755 return DAG.getNode(ISD::FADD, DL, VecFloatVT, LowBitcast, FHigh);
12758 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
12759 SelectionDAG &DAG) const {
12760 SDValue N0 = Op.getOperand(0);
12761 MVT SVT = N0.getSimpleValueType();
12764 switch (SVT.SimpleTy) {
12766 llvm_unreachable("Custom UINT_TO_FP is not supported!");
12771 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
12772 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
12773 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
12777 return lowerUINT_TO_FP_vXi32(Op, DAG, *Subtarget);
12780 assert(Subtarget->hasAVX512());
12781 return DAG.getNode(ISD::UINT_TO_FP, dl, Op.getValueType(),
12782 DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v16i32, N0));
12786 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
12787 SelectionDAG &DAG) const {
12788 SDValue N0 = Op.getOperand(0);
12790 auto PtrVT = getPointerTy(DAG.getDataLayout());
12792 if (Op.getSimpleValueType().isVector())
12793 return lowerUINT_TO_FP_vec(Op, DAG);
12795 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
12796 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
12797 // the optimization here.
12798 if (DAG.SignBitIsZero(N0))
12799 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
12801 MVT SrcVT = N0.getSimpleValueType();
12802 MVT DstVT = Op.getSimpleValueType();
12804 if (Subtarget->hasAVX512() && isScalarFPTypeInSSEReg(DstVT) &&
12805 (SrcVT == MVT::i32 || (SrcVT == MVT::i64 && Subtarget->is64Bit()))) {
12806 // Conversions from unsigned i32 to f32/f64 are legal,
12807 // using VCVTUSI2SS/SD. Same for i64 in 64-bit mode.
12811 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
12812 return LowerUINT_TO_FP_i64(Op, DAG);
12813 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
12814 return LowerUINT_TO_FP_i32(Op, DAG);
12815 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
12818 // Make a 64-bit buffer, and use it to build an FILD.
12819 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
12820 if (SrcVT == MVT::i32) {
12821 SDValue WordOff = DAG.getConstant(4, dl, PtrVT);
12822 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, WordOff);
12823 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12824 StackSlot, MachinePointerInfo(),
12826 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, dl, MVT::i32),
12827 OffsetSlot, MachinePointerInfo(),
12829 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
12833 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
12834 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12835 StackSlot, MachinePointerInfo(),
12837 // For i64 source, we need to add the appropriate power of 2 if the input
12838 // was negative. This is the same as the optimization in
12839 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
12840 // we must be careful to do the computation in x87 extended precision, not
12841 // in SSE. (The generic code can't know it's OK to do this, or how to.)
12842 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
12843 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
12844 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12845 MachineMemOperand::MOLoad, 8, 8);
12847 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
12848 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
12849 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
12852 APInt FF(32, 0x5F800000ULL);
12854 // Check whether the sign bit is set.
12855 SDValue SignSet = DAG.getSetCC(
12856 dl, getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::i64),
12857 Op.getOperand(0), DAG.getConstant(0, dl, MVT::i64), ISD::SETLT);
12859 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
12860 SDValue FudgePtr = DAG.getConstantPool(
12861 ConstantInt::get(*DAG.getContext(), FF.zext(64)), PtrVT);
12863 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
12864 SDValue Zero = DAG.getIntPtrConstant(0, dl);
12865 SDValue Four = DAG.getIntPtrConstant(4, dl);
12866 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
12868 FudgePtr = DAG.getNode(ISD::ADD, dl, PtrVT, FudgePtr, Offset);
12870 // Load the value out, extending it from f32 to f80.
12871 // FIXME: Avoid the extend by constructing the right constant pool?
12872 SDValue Fudge = DAG.getExtLoad(
12873 ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(), FudgePtr,
12874 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), MVT::f32,
12875 false, false, false, 4);
12876 // Extend everything to 80 bits to force it to be done on x87.
12877 // TODO: Are there any fast-math-flags to propagate here?
12878 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
12879 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add,
12880 DAG.getIntPtrConstant(0, dl));
12883 // If the given FP_TO_SINT (IsSigned) or FP_TO_UINT (!IsSigned) operation
12884 // is legal, or has an fp128 or f16 source (which needs to be promoted to f32),
12885 // just return an <SDValue(), SDValue()> pair.
12886 // Otherwise it is assumed to be a conversion from one of f32, f64 or f80
12887 // to i16, i32 or i64, and we lower it to a legal sequence.
12888 // If lowered to the final integer result we return a <result, SDValue()> pair.
12889 // Otherwise we lower it to a sequence ending with a FIST, return a
12890 // <FIST, StackSlot> pair, and the caller is responsible for loading
12891 // the final integer result from StackSlot.
12892 std::pair<SDValue,SDValue>
12893 X86TargetLowering::FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
12894 bool IsSigned, bool IsReplace) const {
12897 EVT DstTy = Op.getValueType();
12898 EVT TheVT = Op.getOperand(0).getValueType();
12899 auto PtrVT = getPointerTy(DAG.getDataLayout());
12901 if (TheVT != MVT::f32 && TheVT != MVT::f64 && TheVT != MVT::f80) {
12902 // f16 must be promoted before using the lowering in this routine.
12903 // fp128 does not use this lowering.
12904 return std::make_pair(SDValue(), SDValue());
12907 // If using FIST to compute an unsigned i64, we'll need some fixup
12908 // to handle values above the maximum signed i64. A FIST is always
12909 // used for the 32-bit subtarget, but also for f80 on a 64-bit target.
12910 bool UnsignedFixup = !IsSigned &&
12911 DstTy == MVT::i64 &&
12912 (!Subtarget->is64Bit() ||
12913 !isScalarFPTypeInSSEReg(TheVT));
12915 if (!IsSigned && DstTy != MVT::i64 && !Subtarget->hasAVX512()) {
12916 // Replace the fp-to-uint32 operation with an fp-to-sint64 FIST.
12917 // The low 32 bits of the fist result will have the correct uint32 result.
12918 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
12922 assert(DstTy.getSimpleVT() <= MVT::i64 &&
12923 DstTy.getSimpleVT() >= MVT::i16 &&
12924 "Unknown FP_TO_INT to lower!");
12926 // These are really Legal.
12927 if (DstTy == MVT::i32 &&
12928 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12929 return std::make_pair(SDValue(), SDValue());
12930 if (Subtarget->is64Bit() &&
12931 DstTy == MVT::i64 &&
12932 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12933 return std::make_pair(SDValue(), SDValue());
12935 // We lower FP->int64 into FISTP64 followed by a load from a temporary
12937 MachineFunction &MF = DAG.getMachineFunction();
12938 unsigned MemSize = DstTy.getSizeInBits()/8;
12939 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12940 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12943 switch (DstTy.getSimpleVT().SimpleTy) {
12944 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
12945 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
12946 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
12947 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
12950 SDValue Chain = DAG.getEntryNode();
12951 SDValue Value = Op.getOperand(0);
12952 SDValue Adjust; // 0x0 or 0x80000000, for result sign bit adjustment.
12954 if (UnsignedFixup) {
12956 // Conversion to unsigned i64 is implemented with a select,
12957 // depending on whether the source value fits in the range
12958 // of a signed i64. Let Thresh be the FP equivalent of
12959 // 0x8000000000000000ULL.
12961 // Adjust i32 = (Value < Thresh) ? 0 : 0x80000000;
12962 // FistSrc = (Value < Thresh) ? Value : (Value - Thresh);
12963 // Fist-to-mem64 FistSrc
12964 // Add 0 or 0x800...0ULL to the 64-bit result, which is equivalent
12965 // to XOR'ing the high 32 bits with Adjust.
12967 // Being a power of 2, Thresh is exactly representable in all FP formats.
12968 // For X87 we'd like to use the smallest FP type for this constant, but
12969 // for DAG type consistency we have to match the FP operand type.
12971 APFloat Thresh(APFloat::IEEEsingle, APInt(32, 0x5f000000));
12972 LLVM_ATTRIBUTE_UNUSED APFloat::opStatus Status = APFloat::opOK;
12973 bool LosesInfo = false;
12974 if (TheVT == MVT::f64)
12975 // The rounding mode is irrelevant as the conversion should be exact.
12976 Status = Thresh.convert(APFloat::IEEEdouble, APFloat::rmNearestTiesToEven,
12978 else if (TheVT == MVT::f80)
12979 Status = Thresh.convert(APFloat::x87DoubleExtended,
12980 APFloat::rmNearestTiesToEven, &LosesInfo);
12982 assert(Status == APFloat::opOK && !LosesInfo &&
12983 "FP conversion should have been exact");
12985 SDValue ThreshVal = DAG.getConstantFP(Thresh, DL, TheVT);
12987 SDValue Cmp = DAG.getSetCC(DL,
12988 getSetCCResultType(DAG.getDataLayout(),
12989 *DAG.getContext(), TheVT),
12990 Value, ThreshVal, ISD::SETLT);
12991 Adjust = DAG.getSelect(DL, MVT::i32, Cmp,
12992 DAG.getConstant(0, DL, MVT::i32),
12993 DAG.getConstant(0x80000000, DL, MVT::i32));
12994 SDValue Sub = DAG.getNode(ISD::FSUB, DL, TheVT, Value, ThreshVal);
12995 Cmp = DAG.getSetCC(DL, getSetCCResultType(DAG.getDataLayout(),
12996 *DAG.getContext(), TheVT),
12997 Value, ThreshVal, ISD::SETLT);
12998 Value = DAG.getSelect(DL, TheVT, Cmp, Value, Sub);
13001 // FIXME This causes a redundant load/store if the SSE-class value is already
13002 // in memory, such as if it is on the callstack.
13003 if (isScalarFPTypeInSSEReg(TheVT)) {
13004 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
13005 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
13006 MachinePointerInfo::getFixedStack(MF, SSFI), false,
13008 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
13010 Chain, StackSlot, DAG.getValueType(TheVT)
13013 MachineMemOperand *MMO =
13014 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
13015 MachineMemOperand::MOLoad, MemSize, MemSize);
13016 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
13017 Chain = Value.getValue(1);
13018 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
13019 StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
13022 MachineMemOperand *MMO =
13023 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
13024 MachineMemOperand::MOStore, MemSize, MemSize);
13026 if (UnsignedFixup) {
13028 // Insert the FIST, load its result as two i32's,
13029 // and XOR the high i32 with Adjust.
13031 SDValue FistOps[] = { Chain, Value, StackSlot };
13032 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
13033 FistOps, DstTy, MMO);
13035 SDValue Low32 = DAG.getLoad(MVT::i32, DL, FIST, StackSlot,
13036 MachinePointerInfo(),
13037 false, false, false, 0);
13038 SDValue HighAddr = DAG.getNode(ISD::ADD, DL, PtrVT, StackSlot,
13039 DAG.getConstant(4, DL, PtrVT));
13041 SDValue High32 = DAG.getLoad(MVT::i32, DL, FIST, HighAddr,
13042 MachinePointerInfo(),
13043 false, false, false, 0);
13044 High32 = DAG.getNode(ISD::XOR, DL, MVT::i32, High32, Adjust);
13046 if (Subtarget->is64Bit()) {
13047 // Join High32 and Low32 into a 64-bit result.
13048 // (High32 << 32) | Low32
13049 Low32 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Low32);
13050 High32 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, High32);
13051 High32 = DAG.getNode(ISD::SHL, DL, MVT::i64, High32,
13052 DAG.getConstant(32, DL, MVT::i8));
13053 SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i64, High32, Low32);
13054 return std::make_pair(Result, SDValue());
13057 SDValue ResultOps[] = { Low32, High32 };
13059 SDValue pair = IsReplace
13060 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, ResultOps)
13061 : DAG.getMergeValues(ResultOps, DL);
13062 return std::make_pair(pair, SDValue());
13064 // Build the FP_TO_INT*_IN_MEM
13065 SDValue Ops[] = { Chain, Value, StackSlot };
13066 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
13068 return std::make_pair(FIST, StackSlot);
13072 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
13073 const X86Subtarget *Subtarget) {
13074 MVT VT = Op->getSimpleValueType(0);
13075 SDValue In = Op->getOperand(0);
13076 MVT InVT = In.getSimpleValueType();
13079 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
13080 return DAG.getNode(ISD::ZERO_EXTEND, dl, VT, In);
13082 // Optimize vectors in AVX mode:
13085 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
13086 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
13087 // Concat upper and lower parts.
13090 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
13091 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
13092 // Concat upper and lower parts.
13095 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
13096 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
13097 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
13100 if (Subtarget->hasInt256())
13101 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
13103 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
13104 SDValue Undef = DAG.getUNDEF(InVT);
13105 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
13106 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
13107 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
13109 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
13110 VT.getVectorNumElements()/2);
13112 OpLo = DAG.getBitcast(HVT, OpLo);
13113 OpHi = DAG.getBitcast(HVT, OpHi);
13115 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
13118 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
13119 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
13120 MVT VT = Op->getSimpleValueType(0);
13121 SDValue In = Op->getOperand(0);
13122 MVT InVT = In.getSimpleValueType();
13124 unsigned int NumElts = VT.getVectorNumElements();
13125 if (NumElts != 8 && NumElts != 16 && !Subtarget->hasBWI())
13128 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
13129 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
13131 assert(InVT.getVectorElementType() == MVT::i1);
13132 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
13134 DAG.getConstant(APInt(ExtVT.getScalarSizeInBits(), 1), DL, ExtVT);
13136 DAG.getConstant(APInt::getNullValue(ExtVT.getScalarSizeInBits()), DL, ExtVT);
13138 SDValue V = DAG.getNode(ISD::VSELECT, DL, ExtVT, In, One, Zero);
13139 if (VT.is512BitVector())
13141 return DAG.getNode(X86ISD::VTRUNC, DL, VT, V);
13144 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13145 SelectionDAG &DAG) {
13146 if (Subtarget->hasFp256())
13147 if (SDValue Res = LowerAVXExtend(Op, DAG, Subtarget))
13153 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13154 SelectionDAG &DAG) {
13156 MVT VT = Op.getSimpleValueType();
13157 SDValue In = Op.getOperand(0);
13158 MVT SVT = In.getSimpleValueType();
13160 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
13161 return LowerZERO_EXTEND_AVX512(Op, Subtarget, DAG);
13163 if (Subtarget->hasFp256())
13164 if (SDValue Res = LowerAVXExtend(Op, DAG, Subtarget))
13167 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
13168 VT.getVectorNumElements() != SVT.getVectorNumElements());
13172 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
13174 MVT VT = Op.getSimpleValueType();
13175 SDValue In = Op.getOperand(0);
13176 MVT InVT = In.getSimpleValueType();
13178 if (VT == MVT::i1) {
13179 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
13180 "Invalid scalar TRUNCATE operation");
13181 if (InVT.getSizeInBits() >= 32)
13183 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
13184 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
13186 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
13187 "Invalid TRUNCATE operation");
13189 // move vector to mask - truncate solution for SKX
13190 if (VT.getVectorElementType() == MVT::i1) {
13191 if (InVT.is512BitVector() && InVT.getScalarSizeInBits() <= 16 &&
13192 Subtarget->hasBWI())
13193 return Op; // legal, will go to VPMOVB2M, VPMOVW2M
13194 if ((InVT.is256BitVector() || InVT.is128BitVector())
13195 && InVT.getScalarSizeInBits() <= 16 &&
13196 Subtarget->hasBWI() && Subtarget->hasVLX())
13197 return Op; // legal, will go to VPMOVB2M, VPMOVW2M
13198 if (InVT.is512BitVector() && InVT.getScalarSizeInBits() >= 32 &&
13199 Subtarget->hasDQI())
13200 return Op; // legal, will go to VPMOVD2M, VPMOVQ2M
13201 if ((InVT.is256BitVector() || InVT.is128BitVector())
13202 && InVT.getScalarSizeInBits() >= 32 &&
13203 Subtarget->hasDQI() && Subtarget->hasVLX())
13204 return Op; // legal, will go to VPMOVB2M, VPMOVQ2M
13207 if (VT.getVectorElementType() == MVT::i1) {
13208 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
13209 unsigned NumElts = InVT.getVectorNumElements();
13210 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
13211 if (InVT.getSizeInBits() < 512) {
13212 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
13213 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
13218 DAG.getConstant(APInt::getSignBit(InVT.getScalarSizeInBits()), DL, InVT);
13219 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
13220 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
13223 // vpmovqb/w/d, vpmovdb/w, vpmovwb
13224 if (Subtarget->hasAVX512()) {
13225 // word to byte only under BWI
13226 if (InVT == MVT::v16i16 && !Subtarget->hasBWI()) // v16i16 -> v16i8
13227 return DAG.getNode(X86ISD::VTRUNC, DL, VT,
13228 DAG.getNode(X86ISD::VSEXT, DL, MVT::v16i32, In));
13229 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
13231 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
13232 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
13233 if (Subtarget->hasInt256()) {
13234 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
13235 In = DAG.getBitcast(MVT::v8i32, In);
13236 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
13238 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
13239 DAG.getIntPtrConstant(0, DL));
13242 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13243 DAG.getIntPtrConstant(0, DL));
13244 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13245 DAG.getIntPtrConstant(2, DL));
13246 OpLo = DAG.getBitcast(MVT::v4i32, OpLo);
13247 OpHi = DAG.getBitcast(MVT::v4i32, OpHi);
13248 static const int ShufMask[] = {0, 2, 4, 6};
13249 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
13252 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
13253 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
13254 if (Subtarget->hasInt256()) {
13255 In = DAG.getBitcast(MVT::v32i8, In);
13257 SmallVector<SDValue,32> pshufbMask;
13258 for (unsigned i = 0; i < 2; ++i) {
13259 pshufbMask.push_back(DAG.getConstant(0x0, DL, MVT::i8));
13260 pshufbMask.push_back(DAG.getConstant(0x1, DL, MVT::i8));
13261 pshufbMask.push_back(DAG.getConstant(0x4, DL, MVT::i8));
13262 pshufbMask.push_back(DAG.getConstant(0x5, DL, MVT::i8));
13263 pshufbMask.push_back(DAG.getConstant(0x8, DL, MVT::i8));
13264 pshufbMask.push_back(DAG.getConstant(0x9, DL, MVT::i8));
13265 pshufbMask.push_back(DAG.getConstant(0xc, DL, MVT::i8));
13266 pshufbMask.push_back(DAG.getConstant(0xd, DL, MVT::i8));
13267 for (unsigned j = 0; j < 8; ++j)
13268 pshufbMask.push_back(DAG.getConstant(0x80, DL, MVT::i8));
13270 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
13271 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
13272 In = DAG.getBitcast(MVT::v4i64, In);
13274 static const int ShufMask[] = {0, 2, -1, -1};
13275 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
13277 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13278 DAG.getIntPtrConstant(0, DL));
13279 return DAG.getBitcast(VT, In);
13282 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13283 DAG.getIntPtrConstant(0, DL));
13285 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13286 DAG.getIntPtrConstant(4, DL));
13288 OpLo = DAG.getBitcast(MVT::v16i8, OpLo);
13289 OpHi = DAG.getBitcast(MVT::v16i8, OpHi);
13291 // The PSHUFB mask:
13292 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
13293 -1, -1, -1, -1, -1, -1, -1, -1};
13295 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
13296 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
13297 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
13299 OpLo = DAG.getBitcast(MVT::v4i32, OpLo);
13300 OpHi = DAG.getBitcast(MVT::v4i32, OpHi);
13302 // The MOVLHPS Mask:
13303 static const int ShufMask2[] = {0, 1, 4, 5};
13304 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
13305 return DAG.getBitcast(MVT::v8i16, res);
13308 // Handle truncation of V256 to V128 using shuffles.
13309 if (!VT.is128BitVector() || !InVT.is256BitVector())
13312 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
13314 unsigned NumElems = VT.getVectorNumElements();
13315 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
13317 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
13318 // Prepare truncation shuffle mask
13319 for (unsigned i = 0; i != NumElems; ++i)
13320 MaskVec[i] = i * 2;
13321 SDValue V = DAG.getVectorShuffle(NVT, DL, DAG.getBitcast(NVT, In),
13322 DAG.getUNDEF(NVT), &MaskVec[0]);
13323 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
13324 DAG.getIntPtrConstant(0, DL));
13327 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
13328 SelectionDAG &DAG) const {
13329 assert(!Op.getSimpleValueType().isVector());
13331 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13332 /*IsSigned=*/ true, /*IsReplace=*/ false);
13333 SDValue FIST = Vals.first, StackSlot = Vals.second;
13334 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
13335 if (!FIST.getNode())
13338 if (StackSlot.getNode())
13339 // Load the result.
13340 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13341 FIST, StackSlot, MachinePointerInfo(),
13342 false, false, false, 0);
13344 // The node is the result.
13348 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
13349 SelectionDAG &DAG) const {
13350 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13351 /*IsSigned=*/ false, /*IsReplace=*/ false);
13352 SDValue FIST = Vals.first, StackSlot = Vals.second;
13353 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
13354 if (!FIST.getNode())
13357 if (StackSlot.getNode())
13358 // Load the result.
13359 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13360 FIST, StackSlot, MachinePointerInfo(),
13361 false, false, false, 0);
13363 // The node is the result.
13367 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
13369 MVT VT = Op.getSimpleValueType();
13370 SDValue In = Op.getOperand(0);
13371 MVT SVT = In.getSimpleValueType();
13373 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
13375 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
13376 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
13377 In, DAG.getUNDEF(SVT)));
13380 /// The only differences between FABS and FNEG are the mask and the logic op.
13381 /// FNEG also has a folding opportunity for FNEG(FABS(x)).
13382 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
13383 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
13384 "Wrong opcode for lowering FABS or FNEG.");
13386 bool IsFABS = (Op.getOpcode() == ISD::FABS);
13388 // If this is a FABS and it has an FNEG user, bail out to fold the combination
13389 // into an FNABS. We'll lower the FABS after that if it is still in use.
13391 for (SDNode *User : Op->uses())
13392 if (User->getOpcode() == ISD::FNEG)
13396 MVT VT = Op.getSimpleValueType();
13398 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
13399 // decide if we should generate a 16-byte constant mask when we only need 4 or
13400 // 8 bytes for the scalar case.
13406 if (VT.isVector()) {
13408 EltVT = VT.getVectorElementType();
13409 NumElts = VT.getVectorNumElements();
13411 // There are no scalar bitwise logical SSE/AVX instructions, so we
13412 // generate a 16-byte vector constant and logic op even for the scalar case.
13413 // Using a 16-byte mask allows folding the load of the mask with
13414 // the logic op, so it can save (~4 bytes) on code size.
13415 LogicVT = (VT == MVT::f64) ? MVT::v2f64 : MVT::v4f32;
13417 NumElts = (VT == MVT::f64) ? 2 : 4;
13420 unsigned EltBits = EltVT.getSizeInBits();
13421 LLVMContext *Context = DAG.getContext();
13422 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
13424 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
13425 Constant *C = ConstantInt::get(*Context, MaskElt);
13426 C = ConstantVector::getSplat(NumElts, C);
13427 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13428 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(DAG.getDataLayout()));
13429 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
13431 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
13432 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
13433 false, false, false, Alignment);
13435 SDValue Op0 = Op.getOperand(0);
13436 bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);
13438 IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR;
13439 SDValue Operand = IsFNABS ? Op0.getOperand(0) : Op0;
13442 return DAG.getNode(LogicOp, dl, LogicVT, Operand, Mask);
13444 // For the scalar case extend to a 128-bit vector, perform the logic op,
13445 // and extract the scalar result back out.
13446 Operand = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Operand);
13447 SDValue LogicNode = DAG.getNode(LogicOp, dl, LogicVT, Operand, Mask);
13448 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, LogicNode,
13449 DAG.getIntPtrConstant(0, dl));
13452 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
13453 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13454 LLVMContext *Context = DAG.getContext();
13455 SDValue Op0 = Op.getOperand(0);
13456 SDValue Op1 = Op.getOperand(1);
13458 MVT VT = Op.getSimpleValueType();
13459 MVT SrcVT = Op1.getSimpleValueType();
13461 // If second operand is smaller, extend it first.
13462 if (SrcVT.bitsLT(VT)) {
13463 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
13466 // And if it is bigger, shrink it first.
13467 if (SrcVT.bitsGT(VT)) {
13468 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1, dl));
13472 // At this point the operands and the result should have the same
13473 // type, and that won't be f80 since that is not custom lowered.
13475 const fltSemantics &Sem =
13476 VT == MVT::f64 ? APFloat::IEEEdouble : APFloat::IEEEsingle;
13477 const unsigned SizeInBits = VT.getSizeInBits();
13479 SmallVector<Constant *, 4> CV(
13480 VT == MVT::f64 ? 2 : 4,
13481 ConstantFP::get(*Context, APFloat(Sem, APInt(SizeInBits, 0))));
13483 // First, clear all bits but the sign bit from the second operand (sign).
13484 CV[0] = ConstantFP::get(*Context,
13485 APFloat(Sem, APInt::getHighBitsSet(SizeInBits, 1)));
13486 Constant *C = ConstantVector::get(CV);
13487 auto PtrVT = TLI.getPointerTy(DAG.getDataLayout());
13488 SDValue CPIdx = DAG.getConstantPool(C, PtrVT, 16);
13490 // Perform all logic operations as 16-byte vectors because there are no
13491 // scalar FP logic instructions in SSE. This allows load folding of the
13492 // constants into the logic instructions.
13493 MVT LogicVT = (VT == MVT::f64) ? MVT::v2f64 : MVT::v4f32;
13495 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
13496 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
13497 false, false, false, 16);
13498 Op1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Op1);
13499 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, LogicVT, Op1, Mask1);
13501 // Next, clear the sign bit from the first operand (magnitude).
13502 // If it's a constant, we can clear it here.
13503 if (ConstantFPSDNode *Op0CN = dyn_cast<ConstantFPSDNode>(Op0)) {
13504 APFloat APF = Op0CN->getValueAPF();
13505 // If the magnitude is a positive zero, the sign bit alone is enough.
13506 if (APF.isPosZero())
13507 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SrcVT, SignBit,
13508 DAG.getIntPtrConstant(0, dl));
13510 CV[0] = ConstantFP::get(*Context, APF);
13512 CV[0] = ConstantFP::get(
13514 APFloat(Sem, APInt::getLowBitsSet(SizeInBits, SizeInBits - 1)));
13516 C = ConstantVector::get(CV);
13517 CPIdx = DAG.getConstantPool(C, PtrVT, 16);
13519 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
13520 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
13521 false, false, false, 16);
13522 // If the magnitude operand wasn't a constant, we need to AND out the sign.
13523 if (!isa<ConstantFPSDNode>(Op0)) {
13524 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Op0);
13525 Val = DAG.getNode(X86ISD::FAND, dl, LogicVT, Op0, Val);
13527 // OR the magnitude value with the sign bit.
13528 Val = DAG.getNode(X86ISD::FOR, dl, LogicVT, Val, SignBit);
13529 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SrcVT, Val,
13530 DAG.getIntPtrConstant(0, dl));
13533 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
13534 SDValue N0 = Op.getOperand(0);
13536 MVT VT = Op.getSimpleValueType();
13538 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
13539 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
13540 DAG.getConstant(1, dl, VT));
13541 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, dl, VT));
13544 // Check whether an OR'd tree is PTEST-able.
13545 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
13546 SelectionDAG &DAG) {
13547 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
13549 if (!Subtarget->hasSSE41())
13552 if (!Op->hasOneUse())
13555 SDNode *N = Op.getNode();
13558 SmallVector<SDValue, 8> Opnds;
13559 DenseMap<SDValue, unsigned> VecInMap;
13560 SmallVector<SDValue, 8> VecIns;
13561 EVT VT = MVT::Other;
13563 // Recognize a special case where a vector is casted into wide integer to
13565 Opnds.push_back(N->getOperand(0));
13566 Opnds.push_back(N->getOperand(1));
13568 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
13569 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
13570 // BFS traverse all OR'd operands.
13571 if (I->getOpcode() == ISD::OR) {
13572 Opnds.push_back(I->getOperand(0));
13573 Opnds.push_back(I->getOperand(1));
13574 // Re-evaluate the number of nodes to be traversed.
13575 e += 2; // 2 more nodes (LHS and RHS) are pushed.
13579 // Quit if a non-EXTRACT_VECTOR_ELT
13580 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
13583 // Quit if without a constant index.
13584 SDValue Idx = I->getOperand(1);
13585 if (!isa<ConstantSDNode>(Idx))
13588 SDValue ExtractedFromVec = I->getOperand(0);
13589 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
13590 if (M == VecInMap.end()) {
13591 VT = ExtractedFromVec.getValueType();
13592 // Quit if not 128/256-bit vector.
13593 if (!VT.is128BitVector() && !VT.is256BitVector())
13595 // Quit if not the same type.
13596 if (VecInMap.begin() != VecInMap.end() &&
13597 VT != VecInMap.begin()->first.getValueType())
13599 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
13600 VecIns.push_back(ExtractedFromVec);
13602 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
13605 assert((VT.is128BitVector() || VT.is256BitVector()) &&
13606 "Not extracted from 128-/256-bit vector.");
13608 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
13610 for (DenseMap<SDValue, unsigned>::const_iterator
13611 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
13612 // Quit if not all elements are used.
13613 if (I->second != FullMask)
13617 MVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
13619 // Cast all vectors into TestVT for PTEST.
13620 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
13621 VecIns[i] = DAG.getBitcast(TestVT, VecIns[i]);
13623 // If more than one full vectors are evaluated, OR them first before PTEST.
13624 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
13625 // Each iteration will OR 2 nodes and append the result until there is only
13626 // 1 node left, i.e. the final OR'd value of all vectors.
13627 SDValue LHS = VecIns[Slot];
13628 SDValue RHS = VecIns[Slot + 1];
13629 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
13632 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
13633 VecIns.back(), VecIns.back());
13636 /// \brief return true if \c Op has a use that doesn't just read flags.
13637 static bool hasNonFlagsUse(SDValue Op) {
13638 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
13640 SDNode *User = *UI;
13641 unsigned UOpNo = UI.getOperandNo();
13642 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
13643 // Look pass truncate.
13644 UOpNo = User->use_begin().getOperandNo();
13645 User = *User->use_begin();
13648 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
13649 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
13655 /// Emit nodes that will be selected as "test Op0,Op0", or something
13657 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
13658 SelectionDAG &DAG) const {
13659 if (Op.getValueType() == MVT::i1) {
13660 SDValue ExtOp = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i8, Op);
13661 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, ExtOp,
13662 DAG.getConstant(0, dl, MVT::i8));
13664 // CF and OF aren't always set the way we want. Determine which
13665 // of these we need.
13666 bool NeedCF = false;
13667 bool NeedOF = false;
13670 case X86::COND_A: case X86::COND_AE:
13671 case X86::COND_B: case X86::COND_BE:
13674 case X86::COND_G: case X86::COND_GE:
13675 case X86::COND_L: case X86::COND_LE:
13676 case X86::COND_O: case X86::COND_NO: {
13677 // Check if we really need to set the
13678 // Overflow flag. If NoSignedWrap is present
13679 // that is not actually needed.
13680 switch (Op->getOpcode()) {
13685 const auto *BinNode = cast<BinaryWithFlagsSDNode>(Op.getNode());
13686 if (BinNode->Flags.hasNoSignedWrap())
13696 // See if we can use the EFLAGS value from the operand instead of
13697 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
13698 // we prove that the arithmetic won't overflow, we can't use OF or CF.
13699 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
13700 // Emit a CMP with 0, which is the TEST pattern.
13701 //if (Op.getValueType() == MVT::i1)
13702 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
13703 // DAG.getConstant(0, MVT::i1));
13704 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13705 DAG.getConstant(0, dl, Op.getValueType()));
13707 unsigned Opcode = 0;
13708 unsigned NumOperands = 0;
13710 // Truncate operations may prevent the merge of the SETCC instruction
13711 // and the arithmetic instruction before it. Attempt to truncate the operands
13712 // of the arithmetic instruction and use a reduced bit-width instruction.
13713 bool NeedTruncation = false;
13714 SDValue ArithOp = Op;
13715 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
13716 SDValue Arith = Op->getOperand(0);
13717 // Both the trunc and the arithmetic op need to have one user each.
13718 if (Arith->hasOneUse())
13719 switch (Arith.getOpcode()) {
13726 NeedTruncation = true;
13732 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
13733 // which may be the result of a CAST. We use the variable 'Op', which is the
13734 // non-casted variable when we check for possible users.
13735 switch (ArithOp.getOpcode()) {
13737 // Due to an isel shortcoming, be conservative if this add is likely to be
13738 // selected as part of a load-modify-store instruction. When the root node
13739 // in a match is a store, isel doesn't know how to remap non-chain non-flag
13740 // uses of other nodes in the match, such as the ADD in this case. This
13741 // leads to the ADD being left around and reselected, with the result being
13742 // two adds in the output. Alas, even if none our users are stores, that
13743 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
13744 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
13745 // climbing the DAG back to the root, and it doesn't seem to be worth the
13747 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13748 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13749 if (UI->getOpcode() != ISD::CopyToReg &&
13750 UI->getOpcode() != ISD::SETCC &&
13751 UI->getOpcode() != ISD::STORE)
13754 if (ConstantSDNode *C =
13755 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
13756 // An add of one will be selected as an INC.
13757 if (C->isOne() && !Subtarget->slowIncDec()) {
13758 Opcode = X86ISD::INC;
13763 // An add of negative one (subtract of one) will be selected as a DEC.
13764 if (C->isAllOnesValue() && !Subtarget->slowIncDec()) {
13765 Opcode = X86ISD::DEC;
13771 // Otherwise use a regular EFLAGS-setting add.
13772 Opcode = X86ISD::ADD;
13777 // If we have a constant logical shift that's only used in a comparison
13778 // against zero turn it into an equivalent AND. This allows turning it into
13779 // a TEST instruction later.
13780 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
13781 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
13782 EVT VT = Op.getValueType();
13783 unsigned BitWidth = VT.getSizeInBits();
13784 unsigned ShAmt = Op->getConstantOperandVal(1);
13785 if (ShAmt >= BitWidth) // Avoid undefined shifts.
13787 APInt Mask = ArithOp.getOpcode() == ISD::SRL
13788 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
13789 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
13790 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
13792 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
13793 DAG.getConstant(Mask, dl, VT));
13794 DAG.ReplaceAllUsesWith(Op, New);
13800 // If the primary and result isn't used, don't bother using X86ISD::AND,
13801 // because a TEST instruction will be better.
13802 if (!hasNonFlagsUse(Op))
13808 // Due to the ISEL shortcoming noted above, be conservative if this op is
13809 // likely to be selected as part of a load-modify-store instruction.
13810 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13811 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13812 if (UI->getOpcode() == ISD::STORE)
13815 // Otherwise use a regular EFLAGS-setting instruction.
13816 switch (ArithOp.getOpcode()) {
13817 default: llvm_unreachable("unexpected operator!");
13818 case ISD::SUB: Opcode = X86ISD::SUB; break;
13819 case ISD::XOR: Opcode = X86ISD::XOR; break;
13820 case ISD::AND: Opcode = X86ISD::AND; break;
13822 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
13823 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
13824 if (EFLAGS.getNode())
13827 Opcode = X86ISD::OR;
13841 return SDValue(Op.getNode(), 1);
13847 // If we found that truncation is beneficial, perform the truncation and
13849 if (NeedTruncation) {
13850 EVT VT = Op.getValueType();
13851 SDValue WideVal = Op->getOperand(0);
13852 EVT WideVT = WideVal.getValueType();
13853 unsigned ConvertedOp = 0;
13854 // Use a target machine opcode to prevent further DAGCombine
13855 // optimizations that may separate the arithmetic operations
13856 // from the setcc node.
13857 switch (WideVal.getOpcode()) {
13859 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
13860 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
13861 case ISD::AND: ConvertedOp = X86ISD::AND; break;
13862 case ISD::OR: ConvertedOp = X86ISD::OR; break;
13863 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
13867 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13868 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
13869 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
13870 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
13871 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
13877 // Emit a CMP with 0, which is the TEST pattern.
13878 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13879 DAG.getConstant(0, dl, Op.getValueType()));
13881 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
13882 SmallVector<SDValue, 4> Ops(Op->op_begin(), Op->op_begin() + NumOperands);
13884 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
13885 DAG.ReplaceAllUsesWith(Op, New);
13886 return SDValue(New.getNode(), 1);
13889 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
13891 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
13892 SDLoc dl, SelectionDAG &DAG) const {
13893 if (isNullConstant(Op1))
13894 return EmitTest(Op0, X86CC, dl, DAG);
13896 assert(!(isa<ConstantSDNode>(Op1) && Op0.getValueType() == MVT::i1) &&
13897 "Unexpected comparison operation for MVT::i1 operands");
13899 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
13900 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
13901 // Do the comparison at i32 if it's smaller, besides the Atom case.
13902 // This avoids subregister aliasing issues. Keep the smaller reference
13903 // if we're optimizing for size, however, as that'll allow better folding
13904 // of memory operations.
13905 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
13906 !DAG.getMachineFunction().getFunction()->optForMinSize() &&
13907 !Subtarget->isAtom()) {
13908 unsigned ExtendOp =
13909 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
13910 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
13911 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
13913 // Use SUB instead of CMP to enable CSE between SUB and CMP.
13914 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
13915 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
13917 return SDValue(Sub.getNode(), 1);
13919 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
13922 /// Convert a comparison if required by the subtarget.
13923 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
13924 SelectionDAG &DAG) const {
13925 // If the subtarget does not support the FUCOMI instruction, floating-point
13926 // comparisons have to be converted.
13927 if (Subtarget->hasCMov() ||
13928 Cmp.getOpcode() != X86ISD::CMP ||
13929 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
13930 !Cmp.getOperand(1).getValueType().isFloatingPoint())
13933 // The instruction selector will select an FUCOM instruction instead of
13934 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
13935 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
13936 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
13938 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
13939 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
13940 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
13941 DAG.getConstant(8, dl, MVT::i8));
13942 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
13944 // Some 64-bit targets lack SAHF support, but they do support FCOMI.
13945 assert(Subtarget->hasLAHFSAHF() && "Target doesn't support SAHF or FCOMI?");
13946 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
13949 /// The minimum architected relative accuracy is 2^-12. We need one
13950 /// Newton-Raphson step to have a good float result (24 bits of precision).
13951 SDValue X86TargetLowering::getRsqrtEstimate(SDValue Op,
13952 DAGCombinerInfo &DCI,
13953 unsigned &RefinementSteps,
13954 bool &UseOneConstNR) const {
13955 EVT VT = Op.getValueType();
13956 const char *RecipOp;
13958 // SSE1 has rsqrtss and rsqrtps. AVX adds a 256-bit variant for rsqrtps.
13959 // TODO: Add support for AVX512 (v16f32).
13960 // It is likely not profitable to do this for f64 because a double-precision
13961 // rsqrt estimate with refinement on x86 prior to FMA requires at least 16
13962 // instructions: convert to single, rsqrtss, convert back to double, refine
13963 // (3 steps = at least 13 insts). If an 'rsqrtsd' variant was added to the ISA
13964 // along with FMA, this could be a throughput win.
13965 if (VT == MVT::f32 && Subtarget->hasSSE1())
13967 else if ((VT == MVT::v4f32 && Subtarget->hasSSE1()) ||
13968 (VT == MVT::v8f32 && Subtarget->hasAVX()))
13969 RecipOp = "vec-sqrtf";
13973 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
13974 if (!Recips.isEnabled(RecipOp))
13977 RefinementSteps = Recips.getRefinementSteps(RecipOp);
13978 UseOneConstNR = false;
13979 return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op);
13982 /// The minimum architected relative accuracy is 2^-12. We need one
13983 /// Newton-Raphson step to have a good float result (24 bits of precision).
13984 SDValue X86TargetLowering::getRecipEstimate(SDValue Op,
13985 DAGCombinerInfo &DCI,
13986 unsigned &RefinementSteps) const {
13987 EVT VT = Op.getValueType();
13988 const char *RecipOp;
13990 // SSE1 has rcpss and rcpps. AVX adds a 256-bit variant for rcpps.
13991 // TODO: Add support for AVX512 (v16f32).
13992 // It is likely not profitable to do this for f64 because a double-precision
13993 // reciprocal estimate with refinement on x86 prior to FMA requires
13994 // 15 instructions: convert to single, rcpss, convert back to double, refine
13995 // (3 steps = 12 insts). If an 'rcpsd' variant was added to the ISA
13996 // along with FMA, this could be a throughput win.
13997 if (VT == MVT::f32 && Subtarget->hasSSE1())
13999 else if ((VT == MVT::v4f32 && Subtarget->hasSSE1()) ||
14000 (VT == MVT::v8f32 && Subtarget->hasAVX()))
14001 RecipOp = "vec-divf";
14005 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
14006 if (!Recips.isEnabled(RecipOp))
14009 RefinementSteps = Recips.getRefinementSteps(RecipOp);
14010 return DCI.DAG.getNode(X86ISD::FRCP, SDLoc(Op), VT, Op);
14013 /// If we have at least two divisions that use the same divisor, convert to
14014 /// multplication by a reciprocal. This may need to be adjusted for a given
14015 /// CPU if a division's cost is not at least twice the cost of a multiplication.
14016 /// This is because we still need one division to calculate the reciprocal and
14017 /// then we need two multiplies by that reciprocal as replacements for the
14018 /// original divisions.
14019 unsigned X86TargetLowering::combineRepeatedFPDivisors() const {
14023 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
14024 /// if it's possible.
14025 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
14026 SDLoc dl, SelectionDAG &DAG) const {
14027 SDValue Op0 = And.getOperand(0);
14028 SDValue Op1 = And.getOperand(1);
14029 if (Op0.getOpcode() == ISD::TRUNCATE)
14030 Op0 = Op0.getOperand(0);
14031 if (Op1.getOpcode() == ISD::TRUNCATE)
14032 Op1 = Op1.getOperand(0);
14035 if (Op1.getOpcode() == ISD::SHL)
14036 std::swap(Op0, Op1);
14037 if (Op0.getOpcode() == ISD::SHL) {
14038 if (isOneConstant(Op0.getOperand(0))) {
14039 // If we looked past a truncate, check that it's only truncating away
14041 unsigned BitWidth = Op0.getValueSizeInBits();
14042 unsigned AndBitWidth = And.getValueSizeInBits();
14043 if (BitWidth > AndBitWidth) {
14045 DAG.computeKnownBits(Op0, Zeros, Ones);
14046 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
14050 RHS = Op0.getOperand(1);
14052 } else if (Op1.getOpcode() == ISD::Constant) {
14053 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
14054 uint64_t AndRHSVal = AndRHS->getZExtValue();
14055 SDValue AndLHS = Op0;
14057 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
14058 LHS = AndLHS.getOperand(0);
14059 RHS = AndLHS.getOperand(1);
14062 // Use BT if the immediate can't be encoded in a TEST instruction.
14063 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
14065 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), dl, LHS.getValueType());
14069 if (LHS.getNode()) {
14070 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
14071 // instruction. Since the shift amount is in-range-or-undefined, we know
14072 // that doing a bittest on the i32 value is ok. We extend to i32 because
14073 // the encoding for the i16 version is larger than the i32 version.
14074 // Also promote i16 to i32 for performance / code size reason.
14075 if (LHS.getValueType() == MVT::i8 ||
14076 LHS.getValueType() == MVT::i16)
14077 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
14079 // If the operand types disagree, extend the shift amount to match. Since
14080 // BT ignores high bits (like shifts) we can use anyextend.
14081 if (LHS.getValueType() != RHS.getValueType())
14082 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
14084 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
14085 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
14086 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14087 DAG.getConstant(Cond, dl, MVT::i8), BT);
14093 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
14095 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
14100 // SSE Condition code mapping:
14109 switch (SetCCOpcode) {
14110 default: llvm_unreachable("Unexpected SETCC condition");
14112 case ISD::SETEQ: SSECC = 0; break;
14114 case ISD::SETGT: Swap = true; // Fallthrough
14116 case ISD::SETOLT: SSECC = 1; break;
14118 case ISD::SETGE: Swap = true; // Fallthrough
14120 case ISD::SETOLE: SSECC = 2; break;
14121 case ISD::SETUO: SSECC = 3; break;
14123 case ISD::SETNE: SSECC = 4; break;
14124 case ISD::SETULE: Swap = true; // Fallthrough
14125 case ISD::SETUGE: SSECC = 5; break;
14126 case ISD::SETULT: Swap = true; // Fallthrough
14127 case ISD::SETUGT: SSECC = 6; break;
14128 case ISD::SETO: SSECC = 7; break;
14130 case ISD::SETONE: SSECC = 8; break;
14133 std::swap(Op0, Op1);
14138 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
14139 // ones, and then concatenate the result back.
14140 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
14141 MVT VT = Op.getSimpleValueType();
14143 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
14144 "Unsupported value type for operation");
14146 unsigned NumElems = VT.getVectorNumElements();
14148 SDValue CC = Op.getOperand(2);
14150 // Extract the LHS vectors
14151 SDValue LHS = Op.getOperand(0);
14152 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
14153 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
14155 // Extract the RHS vectors
14156 SDValue RHS = Op.getOperand(1);
14157 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
14158 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
14160 // Issue the operation on the smaller types and concatenate the result back
14161 MVT EltVT = VT.getVectorElementType();
14162 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
14163 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
14164 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
14165 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
14168 static SDValue LowerBoolVSETCC_AVX512(SDValue Op, SelectionDAG &DAG) {
14169 SDValue Op0 = Op.getOperand(0);
14170 SDValue Op1 = Op.getOperand(1);
14171 SDValue CC = Op.getOperand(2);
14172 MVT VT = Op.getSimpleValueType();
14175 assert(Op0.getSimpleValueType().getVectorElementType() == MVT::i1 &&
14176 "Unexpected type for boolean compare operation");
14177 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14178 SDValue NotOp0 = DAG.getNode(ISD::XOR, dl, VT, Op0,
14179 DAG.getConstant(-1, dl, VT));
14180 SDValue NotOp1 = DAG.getNode(ISD::XOR, dl, VT, Op1,
14181 DAG.getConstant(-1, dl, VT));
14182 switch (SetCCOpcode) {
14183 default: llvm_unreachable("Unexpected SETCC condition");
14185 // (x == y) -> ~(x ^ y)
14186 return DAG.getNode(ISD::XOR, dl, VT,
14187 DAG.getNode(ISD::XOR, dl, VT, Op0, Op1),
14188 DAG.getConstant(-1, dl, VT));
14190 // (x != y) -> (x ^ y)
14191 return DAG.getNode(ISD::XOR, dl, VT, Op0, Op1);
14194 // (x > y) -> (x & ~y)
14195 return DAG.getNode(ISD::AND, dl, VT, Op0, NotOp1);
14198 // (x < y) -> (~x & y)
14199 return DAG.getNode(ISD::AND, dl, VT, NotOp0, Op1);
14202 // (x <= y) -> (~x | y)
14203 return DAG.getNode(ISD::OR, dl, VT, NotOp0, Op1);
14206 // (x >=y) -> (x | ~y)
14207 return DAG.getNode(ISD::OR, dl, VT, Op0, NotOp1);
14211 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
14212 const X86Subtarget *Subtarget) {
14213 SDValue Op0 = Op.getOperand(0);
14214 SDValue Op1 = Op.getOperand(1);
14215 SDValue CC = Op.getOperand(2);
14216 MVT VT = Op.getSimpleValueType();
14219 assert(Op0.getSimpleValueType().getVectorElementType().getSizeInBits() >= 8 &&
14220 Op.getSimpleValueType().getVectorElementType() == MVT::i1 &&
14221 "Cannot set masked compare for this operation");
14223 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14225 bool Unsigned = false;
14228 switch (SetCCOpcode) {
14229 default: llvm_unreachable("Unexpected SETCC condition");
14230 case ISD::SETNE: SSECC = 4; break;
14231 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
14232 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
14233 case ISD::SETLT: Swap = true; //fall-through
14234 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
14235 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
14236 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
14237 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
14238 case ISD::SETULE: Unsigned = true; //fall-through
14239 case ISD::SETLE: SSECC = 2; break;
14243 std::swap(Op0, Op1);
14245 return DAG.getNode(Opc, dl, VT, Op0, Op1);
14246 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
14247 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14248 DAG.getConstant(SSECC, dl, MVT::i8));
14251 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
14252 /// operand \p Op1. If non-trivial (for example because it's not constant)
14253 /// return an empty value.
14254 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
14256 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
14260 MVT VT = Op1.getSimpleValueType();
14261 MVT EVT = VT.getVectorElementType();
14262 unsigned n = VT.getVectorNumElements();
14263 SmallVector<SDValue, 8> ULTOp1;
14265 for (unsigned i = 0; i < n; ++i) {
14266 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
14267 if (!Elt || Elt->isOpaque() || Elt->getSimpleValueType(0) != EVT)
14270 // Avoid underflow.
14271 APInt Val = Elt->getAPIntValue();
14275 ULTOp1.push_back(DAG.getConstant(Val - 1, dl, EVT));
14278 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
14281 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
14282 SelectionDAG &DAG) {
14283 SDValue Op0 = Op.getOperand(0);
14284 SDValue Op1 = Op.getOperand(1);
14285 SDValue CC = Op.getOperand(2);
14286 MVT VT = Op.getSimpleValueType();
14287 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14288 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
14293 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
14294 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
14297 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
14298 unsigned Opc = X86ISD::CMPP;
14299 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
14300 assert(VT.getVectorNumElements() <= 16);
14301 Opc = X86ISD::CMPM;
14303 // In the two special cases we can't handle, emit two comparisons.
14306 unsigned CombineOpc;
14307 if (SetCCOpcode == ISD::SETUEQ) {
14308 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
14310 assert(SetCCOpcode == ISD::SETONE);
14311 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
14314 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14315 DAG.getConstant(CC0, dl, MVT::i8));
14316 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14317 DAG.getConstant(CC1, dl, MVT::i8));
14318 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
14320 // Handle all other FP comparisons here.
14321 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14322 DAG.getConstant(SSECC, dl, MVT::i8));
14325 MVT VTOp0 = Op0.getSimpleValueType();
14326 assert(VTOp0 == Op1.getSimpleValueType() &&
14327 "Expected operands with same type!");
14328 assert(VT.getVectorNumElements() == VTOp0.getVectorNumElements() &&
14329 "Invalid number of packed elements for source and destination!");
14331 if (VT.is128BitVector() && VTOp0.is256BitVector()) {
14332 // On non-AVX512 targets, a vector of MVT::i1 is promoted by the type
14333 // legalizer to a wider vector type. In the case of 'vsetcc' nodes, the
14334 // legalizer firstly checks if the first operand in input to the setcc has
14335 // a legal type. If so, then it promotes the return type to that same type.
14336 // Otherwise, the return type is promoted to the 'next legal type' which,
14337 // for a vector of MVT::i1 is always a 128-bit integer vector type.
14339 // We reach this code only if the following two conditions are met:
14340 // 1. Both return type and operand type have been promoted to wider types
14341 // by the type legalizer.
14342 // 2. The original operand type has been promoted to a 256-bit vector.
14344 // Note that condition 2. only applies for AVX targets.
14345 SDValue NewOp = DAG.getSetCC(dl, VTOp0, Op0, Op1, SetCCOpcode);
14346 return DAG.getZExtOrTrunc(NewOp, dl, VT);
14349 // The non-AVX512 code below works under the assumption that source and
14350 // destination types are the same.
14351 assert((Subtarget->hasAVX512() || (VT == VTOp0)) &&
14352 "Value types for source and destination must be the same!");
14354 // Break 256-bit integer vector compare into smaller ones.
14355 if (VT.is256BitVector() && !Subtarget->hasInt256())
14356 return Lower256IntVSETCC(Op, DAG);
14358 MVT OpVT = Op1.getSimpleValueType();
14359 if (OpVT.getVectorElementType() == MVT::i1)
14360 return LowerBoolVSETCC_AVX512(Op, DAG);
14362 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
14363 if (Subtarget->hasAVX512()) {
14364 if (Op1.getSimpleValueType().is512BitVector() ||
14365 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
14366 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
14367 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
14369 // In AVX-512 architecture setcc returns mask with i1 elements,
14370 // But there is no compare instruction for i8 and i16 elements in KNL.
14371 // We are not talking about 512-bit operands in this case, these
14372 // types are illegal.
14374 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
14375 OpVT.getVectorElementType().getSizeInBits() >= 8))
14376 return DAG.getNode(ISD::TRUNCATE, dl, VT,
14377 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
14380 // Lower using XOP integer comparisons.
14381 if ((VT == MVT::v16i8 || VT == MVT::v8i16 ||
14382 VT == MVT::v4i32 || VT == MVT::v2i64) && Subtarget->hasXOP()) {
14383 // Translate compare code to XOP PCOM compare mode.
14384 unsigned CmpMode = 0;
14385 switch (SetCCOpcode) {
14386 default: llvm_unreachable("Unexpected SETCC condition");
14388 case ISD::SETLT: CmpMode = 0x00; break;
14390 case ISD::SETLE: CmpMode = 0x01; break;
14392 case ISD::SETGT: CmpMode = 0x02; break;
14394 case ISD::SETGE: CmpMode = 0x03; break;
14395 case ISD::SETEQ: CmpMode = 0x04; break;
14396 case ISD::SETNE: CmpMode = 0x05; break;
14399 // Are we comparing unsigned or signed integers?
14400 unsigned Opc = ISD::isUnsignedIntSetCC(SetCCOpcode)
14401 ? X86ISD::VPCOMU : X86ISD::VPCOM;
14403 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14404 DAG.getConstant(CmpMode, dl, MVT::i8));
14407 // We are handling one of the integer comparisons here. Since SSE only has
14408 // GT and EQ comparisons for integer, swapping operands and multiple
14409 // operations may be required for some comparisons.
14411 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
14412 bool Subus = false;
14414 switch (SetCCOpcode) {
14415 default: llvm_unreachable("Unexpected SETCC condition");
14416 case ISD::SETNE: Invert = true;
14417 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
14418 case ISD::SETLT: Swap = true;
14419 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
14420 case ISD::SETGE: Swap = true;
14421 case ISD::SETLE: Opc = X86ISD::PCMPGT;
14422 Invert = true; break;
14423 case ISD::SETULT: Swap = true;
14424 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
14425 FlipSigns = true; break;
14426 case ISD::SETUGE: Swap = true;
14427 case ISD::SETULE: Opc = X86ISD::PCMPGT;
14428 FlipSigns = true; Invert = true; break;
14431 // Special case: Use min/max operations for SETULE/SETUGE
14432 MVT VET = VT.getVectorElementType();
14434 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
14435 || (Subtarget->hasSSE2() && (VET == MVT::i8));
14438 switch (SetCCOpcode) {
14440 case ISD::SETULE: Opc = ISD::UMIN; MinMax = true; break;
14441 case ISD::SETUGE: Opc = ISD::UMAX; MinMax = true; break;
14444 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
14447 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
14448 if (!MinMax && hasSubus) {
14449 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
14451 // t = psubus Op0, Op1
14452 // pcmpeq t, <0..0>
14453 switch (SetCCOpcode) {
14455 case ISD::SETULT: {
14456 // If the comparison is against a constant we can turn this into a
14457 // setule. With psubus, setule does not require a swap. This is
14458 // beneficial because the constant in the register is no longer
14459 // destructed as the destination so it can be hoisted out of a loop.
14460 // Only do this pre-AVX since vpcmp* is no longer destructive.
14461 if (Subtarget->hasAVX())
14463 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
14464 if (ULEOp1.getNode()) {
14466 Subus = true; Invert = false; Swap = false;
14470 // Psubus is better than flip-sign because it requires no inversion.
14471 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
14472 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
14476 Opc = X86ISD::SUBUS;
14482 std::swap(Op0, Op1);
14484 // Check that the operation in question is available (most are plain SSE2,
14485 // but PCMPGTQ and PCMPEQQ have different requirements).
14486 if (VT == MVT::v2i64) {
14487 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
14488 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
14490 // First cast everything to the right type.
14491 Op0 = DAG.getBitcast(MVT::v4i32, Op0);
14492 Op1 = DAG.getBitcast(MVT::v4i32, Op1);
14494 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14495 // bits of the inputs before performing those operations. The lower
14496 // compare is always unsigned.
14499 SB = DAG.getConstant(0x80000000U, dl, MVT::v4i32);
14501 SDValue Sign = DAG.getConstant(0x80000000U, dl, MVT::i32);
14502 SDValue Zero = DAG.getConstant(0x00000000U, dl, MVT::i32);
14503 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
14504 Sign, Zero, Sign, Zero);
14506 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
14507 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
14509 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
14510 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
14511 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
14513 // Create masks for only the low parts/high parts of the 64 bit integers.
14514 static const int MaskHi[] = { 1, 1, 3, 3 };
14515 static const int MaskLo[] = { 0, 0, 2, 2 };
14516 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
14517 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
14518 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
14520 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
14521 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
14524 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14526 return DAG.getBitcast(VT, Result);
14529 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
14530 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
14531 // pcmpeqd + pshufd + pand.
14532 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
14534 // First cast everything to the right type.
14535 Op0 = DAG.getBitcast(MVT::v4i32, Op0);
14536 Op1 = DAG.getBitcast(MVT::v4i32, Op1);
14539 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
14541 // Make sure the lower and upper halves are both all-ones.
14542 static const int Mask[] = { 1, 0, 3, 2 };
14543 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
14544 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
14547 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14549 return DAG.getBitcast(VT, Result);
14553 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14554 // bits of the inputs before performing those operations.
14556 MVT EltVT = VT.getVectorElementType();
14557 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), dl,
14559 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
14560 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
14563 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
14565 // If the logical-not of the result is required, perform that now.
14567 Result = DAG.getNOT(dl, Result, VT);
14570 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
14573 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
14574 getZeroVector(VT, Subtarget, DAG, dl));
14579 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
14581 MVT VT = Op.getSimpleValueType();
14583 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
14585 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
14586 && "SetCC type must be 8-bit or 1-bit integer");
14587 SDValue Op0 = Op.getOperand(0);
14588 SDValue Op1 = Op.getOperand(1);
14590 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
14592 // Optimize to BT if possible.
14593 // Lower (X & (1 << N)) == 0 to BT(X, N).
14594 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
14595 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
14596 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
14597 isNullConstant(Op1) &&
14598 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14599 if (SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG)) {
14601 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewSetCC);
14606 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
14608 if ((isOneConstant(Op1) || isNullConstant(Op1)) &&
14609 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14611 // If the input is a setcc, then reuse the input setcc or use a new one with
14612 // the inverted condition.
14613 if (Op0.getOpcode() == X86ISD::SETCC) {
14614 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
14615 bool Invert = (CC == ISD::SETNE) ^ isNullConstant(Op1);
14619 CCode = X86::GetOppositeBranchCondition(CCode);
14620 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14621 DAG.getConstant(CCode, dl, MVT::i8),
14622 Op0.getOperand(1));
14624 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14628 if ((Op0.getValueType() == MVT::i1) && isOneConstant(Op1) &&
14629 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14631 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
14632 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, dl, MVT::i1), NewCC);
14635 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
14636 unsigned X86CC = TranslateX86CC(CC, dl, isFP, Op0, Op1, DAG);
14637 if (X86CC == X86::COND_INVALID)
14640 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
14641 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
14642 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14643 DAG.getConstant(X86CC, dl, MVT::i8), EFLAGS);
14645 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14649 SDValue X86TargetLowering::LowerSETCCE(SDValue Op, SelectionDAG &DAG) const {
14650 SDValue LHS = Op.getOperand(0);
14651 SDValue RHS = Op.getOperand(1);
14652 SDValue Carry = Op.getOperand(2);
14653 SDValue Cond = Op.getOperand(3);
14656 assert(LHS.getSimpleValueType().isInteger() && "SETCCE is integer only.");
14657 X86::CondCode CC = TranslateIntegerX86CC(cast<CondCodeSDNode>(Cond)->get());
14659 assert(Carry.getOpcode() != ISD::CARRY_FALSE);
14660 SDVTList VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14661 SDValue Cmp = DAG.getNode(X86ISD::SBB, DL, VTs, LHS, RHS, Carry);
14662 return DAG.getNode(X86ISD::SETCC, DL, Op.getValueType(),
14663 DAG.getConstant(CC, DL, MVT::i8), Cmp.getValue(1));
14666 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
14667 static bool isX86LogicalCmp(SDValue Op) {
14668 unsigned Opc = Op.getNode()->getOpcode();
14669 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
14670 Opc == X86ISD::SAHF)
14672 if (Op.getResNo() == 1 &&
14673 (Opc == X86ISD::ADD ||
14674 Opc == X86ISD::SUB ||
14675 Opc == X86ISD::ADC ||
14676 Opc == X86ISD::SBB ||
14677 Opc == X86ISD::SMUL ||
14678 Opc == X86ISD::UMUL ||
14679 Opc == X86ISD::INC ||
14680 Opc == X86ISD::DEC ||
14681 Opc == X86ISD::OR ||
14682 Opc == X86ISD::XOR ||
14683 Opc == X86ISD::AND))
14686 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
14692 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
14693 if (V.getOpcode() != ISD::TRUNCATE)
14696 SDValue VOp0 = V.getOperand(0);
14697 unsigned InBits = VOp0.getValueSizeInBits();
14698 unsigned Bits = V.getValueSizeInBits();
14699 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
14702 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
14703 bool addTest = true;
14704 SDValue Cond = Op.getOperand(0);
14705 SDValue Op1 = Op.getOperand(1);
14706 SDValue Op2 = Op.getOperand(2);
14708 MVT VT = Op1.getSimpleValueType();
14711 // Lower FP selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
14712 // are available or VBLENDV if AVX is available.
14713 // Otherwise FP cmovs get lowered into a less efficient branch sequence later.
14714 if (Cond.getOpcode() == ISD::SETCC &&
14715 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
14716 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
14717 VT == Cond.getOperand(0).getSimpleValueType() && Cond->hasOneUse()) {
14718 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
14719 int SSECC = translateX86FSETCC(
14720 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
14723 if (Subtarget->hasAVX512()) {
14724 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
14725 DAG.getConstant(SSECC, DL, MVT::i8));
14726 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
14729 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
14730 DAG.getConstant(SSECC, DL, MVT::i8));
14732 // If we have AVX, we can use a variable vector select (VBLENDV) instead
14733 // of 3 logic instructions for size savings and potentially speed.
14734 // Unfortunately, there is no scalar form of VBLENDV.
14736 // If either operand is a constant, don't try this. We can expect to
14737 // optimize away at least one of the logic instructions later in that
14738 // case, so that sequence would be faster than a variable blend.
14740 // BLENDV was introduced with SSE 4.1, but the 2 register form implicitly
14741 // uses XMM0 as the selection register. That may need just as many
14742 // instructions as the AND/ANDN/OR sequence due to register moves, so
14745 if (Subtarget->hasAVX() &&
14746 !isa<ConstantFPSDNode>(Op1) && !isa<ConstantFPSDNode>(Op2)) {
14748 // Convert to vectors, do a VSELECT, and convert back to scalar.
14749 // All of the conversions should be optimized away.
14751 MVT VecVT = VT == MVT::f32 ? MVT::v4f32 : MVT::v2f64;
14752 SDValue VOp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op1);
14753 SDValue VOp2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op2);
14754 SDValue VCmp = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Cmp);
14756 MVT VCmpVT = VT == MVT::f32 ? MVT::v4i32 : MVT::v2i64;
14757 VCmp = DAG.getBitcast(VCmpVT, VCmp);
14759 SDValue VSel = DAG.getNode(ISD::VSELECT, DL, VecVT, VCmp, VOp1, VOp2);
14761 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT,
14762 VSel, DAG.getIntPtrConstant(0, DL));
14764 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
14765 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
14766 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
14770 if (VT.isVector() && VT.getVectorElementType() == MVT::i1) {
14772 if (ISD::isBuildVectorOfConstantSDNodes(Op1.getNode()))
14773 Op1Scalar = ConvertI1VectorToInteger(Op1, DAG);
14774 else if (Op1.getOpcode() == ISD::BITCAST && Op1.getOperand(0))
14775 Op1Scalar = Op1.getOperand(0);
14777 if (ISD::isBuildVectorOfConstantSDNodes(Op2.getNode()))
14778 Op2Scalar = ConvertI1VectorToInteger(Op2, DAG);
14779 else if (Op2.getOpcode() == ISD::BITCAST && Op2.getOperand(0))
14780 Op2Scalar = Op2.getOperand(0);
14781 if (Op1Scalar.getNode() && Op2Scalar.getNode()) {
14782 SDValue newSelect = DAG.getNode(ISD::SELECT, DL,
14783 Op1Scalar.getValueType(),
14784 Cond, Op1Scalar, Op2Scalar);
14785 if (newSelect.getValueSizeInBits() == VT.getSizeInBits())
14786 return DAG.getBitcast(VT, newSelect);
14787 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, newSelect);
14788 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, ExtVec,
14789 DAG.getIntPtrConstant(0, DL));
14793 if (VT == MVT::v4i1 || VT == MVT::v2i1) {
14794 SDValue zeroConst = DAG.getIntPtrConstant(0, DL);
14795 Op1 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
14796 DAG.getUNDEF(MVT::v8i1), Op1, zeroConst);
14797 Op2 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
14798 DAG.getUNDEF(MVT::v8i1), Op2, zeroConst);
14799 SDValue newSelect = DAG.getNode(ISD::SELECT, DL, MVT::v8i1,
14801 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, newSelect, zeroConst);
14804 if (Cond.getOpcode() == ISD::SETCC) {
14805 SDValue NewCond = LowerSETCC(Cond, DAG);
14806 if (NewCond.getNode())
14810 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
14811 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
14812 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
14813 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
14814 if (Cond.getOpcode() == X86ISD::SETCC &&
14815 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
14816 isNullConstant(Cond.getOperand(1).getOperand(1))) {
14817 SDValue Cmp = Cond.getOperand(1);
14819 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
14821 if ((isAllOnesConstant(Op1) || isAllOnesConstant(Op2)) &&
14822 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
14823 SDValue Y = isAllOnesConstant(Op2) ? Op1 : Op2;
14825 SDValue CmpOp0 = Cmp.getOperand(0);
14826 // Apply further optimizations for special cases
14827 // (select (x != 0), -1, 0) -> neg & sbb
14828 // (select (x == 0), 0, -1) -> neg & sbb
14829 if (isNullConstant(Y) &&
14830 (isAllOnesConstant(Op1) == (CondCode == X86::COND_NE))) {
14831 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
14832 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
14833 DAG.getConstant(0, DL,
14834 CmpOp0.getValueType()),
14836 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14837 DAG.getConstant(X86::COND_B, DL, MVT::i8),
14838 SDValue(Neg.getNode(), 1));
14842 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
14843 CmpOp0, DAG.getConstant(1, DL, CmpOp0.getValueType()));
14844 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14846 SDValue Res = // Res = 0 or -1.
14847 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14848 DAG.getConstant(X86::COND_B, DL, MVT::i8), Cmp);
14850 if (isAllOnesConstant(Op1) != (CondCode == X86::COND_E))
14851 Res = DAG.getNOT(DL, Res, Res.getValueType());
14853 if (!isNullConstant(Op2))
14854 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
14859 // Look past (and (setcc_carry (cmp ...)), 1).
14860 if (Cond.getOpcode() == ISD::AND &&
14861 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY &&
14862 isOneConstant(Cond.getOperand(1)))
14863 Cond = Cond.getOperand(0);
14865 // If condition flag is set by a X86ISD::CMP, then use it as the condition
14866 // setting operand in place of the X86ISD::SETCC.
14867 unsigned CondOpcode = Cond.getOpcode();
14868 if (CondOpcode == X86ISD::SETCC ||
14869 CondOpcode == X86ISD::SETCC_CARRY) {
14870 CC = Cond.getOperand(0);
14872 SDValue Cmp = Cond.getOperand(1);
14873 unsigned Opc = Cmp.getOpcode();
14874 MVT VT = Op.getSimpleValueType();
14876 bool IllegalFPCMov = false;
14877 if (VT.isFloatingPoint() && !VT.isVector() &&
14878 !isScalarFPTypeInSSEReg(VT)) // FPStack?
14879 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
14881 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
14882 Opc == X86ISD::BT) { // FIXME
14886 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
14887 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
14888 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
14889 Cond.getOperand(0).getValueType() != MVT::i8)) {
14890 SDValue LHS = Cond.getOperand(0);
14891 SDValue RHS = Cond.getOperand(1);
14892 unsigned X86Opcode;
14895 switch (CondOpcode) {
14896 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
14897 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
14898 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
14899 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
14900 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
14901 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
14902 default: llvm_unreachable("unexpected overflowing operator");
14904 if (CondOpcode == ISD::UMULO)
14905 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
14908 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14910 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
14912 if (CondOpcode == ISD::UMULO)
14913 Cond = X86Op.getValue(2);
14915 Cond = X86Op.getValue(1);
14917 CC = DAG.getConstant(X86Cond, DL, MVT::i8);
14922 // Look past the truncate if the high bits are known zero.
14923 if (isTruncWithZeroHighBitsInput(Cond, DAG))
14924 Cond = Cond.getOperand(0);
14926 // We know the result of AND is compared against zero. Try to match
14928 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
14929 if (SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG)) {
14930 CC = NewSetCC.getOperand(0);
14931 Cond = NewSetCC.getOperand(1);
14938 CC = DAG.getConstant(X86::COND_NE, DL, MVT::i8);
14939 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
14942 // a < b ? -1 : 0 -> RES = ~setcc_carry
14943 // a < b ? 0 : -1 -> RES = setcc_carry
14944 // a >= b ? -1 : 0 -> RES = setcc_carry
14945 // a >= b ? 0 : -1 -> RES = ~setcc_carry
14946 if (Cond.getOpcode() == X86ISD::SUB) {
14947 Cond = ConvertCmpIfNecessary(Cond, DAG);
14948 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
14950 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
14951 (isAllOnesConstant(Op1) || isAllOnesConstant(Op2)) &&
14952 (isNullConstant(Op1) || isNullConstant(Op2))) {
14953 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14954 DAG.getConstant(X86::COND_B, DL, MVT::i8),
14956 if (isAllOnesConstant(Op1) != (CondCode == X86::COND_B))
14957 return DAG.getNOT(DL, Res, Res.getValueType());
14962 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
14963 // widen the cmov and push the truncate through. This avoids introducing a new
14964 // branch during isel and doesn't add any extensions.
14965 if (Op.getValueType() == MVT::i8 &&
14966 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
14967 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
14968 if (T1.getValueType() == T2.getValueType() &&
14969 // Blacklist CopyFromReg to avoid partial register stalls.
14970 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
14971 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
14972 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
14973 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
14977 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
14978 // condition is true.
14979 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
14980 SDValue Ops[] = { Op2, Op1, CC, Cond };
14981 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
14984 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op,
14985 const X86Subtarget *Subtarget,
14986 SelectionDAG &DAG) {
14987 MVT VT = Op->getSimpleValueType(0);
14988 SDValue In = Op->getOperand(0);
14989 MVT InVT = In.getSimpleValueType();
14990 MVT VTElt = VT.getVectorElementType();
14991 MVT InVTElt = InVT.getVectorElementType();
14995 if ((InVTElt == MVT::i1) &&
14996 (((Subtarget->hasBWI() && Subtarget->hasVLX() &&
14997 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() <= 16)) ||
14999 ((Subtarget->hasBWI() && VT.is512BitVector() &&
15000 VTElt.getSizeInBits() <= 16)) ||
15002 ((Subtarget->hasDQI() && Subtarget->hasVLX() &&
15003 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() >= 32)) ||
15005 ((Subtarget->hasDQI() && VT.is512BitVector() &&
15006 VTElt.getSizeInBits() >= 32))))
15007 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15009 unsigned int NumElts = VT.getVectorNumElements();
15011 if (NumElts != 8 && NumElts != 16 && !Subtarget->hasBWI())
15014 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1) {
15015 if (In.getOpcode() == X86ISD::VSEXT || In.getOpcode() == X86ISD::VZEXT)
15016 return DAG.getNode(In.getOpcode(), dl, VT, In.getOperand(0));
15017 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15020 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
15021 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
15023 DAG.getConstant(APInt::getAllOnesValue(ExtVT.getScalarSizeInBits()), dl,
15026 DAG.getConstant(APInt::getNullValue(ExtVT.getScalarSizeInBits()), dl, ExtVT);
15028 SDValue V = DAG.getNode(ISD::VSELECT, dl, ExtVT, In, NegOne, Zero);
15029 if (VT.is512BitVector())
15031 return DAG.getNode(X86ISD::VTRUNC, dl, VT, V);
15034 static SDValue LowerSIGN_EXTEND_VECTOR_INREG(SDValue Op,
15035 const X86Subtarget *Subtarget,
15036 SelectionDAG &DAG) {
15037 SDValue In = Op->getOperand(0);
15038 MVT VT = Op->getSimpleValueType(0);
15039 MVT InVT = In.getSimpleValueType();
15040 assert(VT.getSizeInBits() == InVT.getSizeInBits());
15042 MVT InSVT = InVT.getVectorElementType();
15043 assert(VT.getVectorElementType().getSizeInBits() > InSVT.getSizeInBits());
15045 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
15047 if (InSVT != MVT::i32 && InSVT != MVT::i16 && InSVT != MVT::i8)
15052 // SSE41 targets can use the pmovsx* instructions directly.
15053 if (Subtarget->hasSSE41())
15054 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15056 // pre-SSE41 targets unpack lower lanes and then sign-extend using SRAI.
15060 // As SRAI is only available on i16/i32 types, we expand only up to i32
15061 // and handle i64 separately.
15062 while (CurrVT != VT && CurrVT.getVectorElementType() != MVT::i32) {
15063 Curr = DAG.getNode(X86ISD::UNPCKL, dl, CurrVT, DAG.getUNDEF(CurrVT), Curr);
15064 MVT CurrSVT = MVT::getIntegerVT(CurrVT.getScalarSizeInBits() * 2);
15065 CurrVT = MVT::getVectorVT(CurrSVT, CurrVT.getVectorNumElements() / 2);
15066 Curr = DAG.getBitcast(CurrVT, Curr);
15069 SDValue SignExt = Curr;
15070 if (CurrVT != InVT) {
15071 unsigned SignExtShift =
15072 CurrVT.getVectorElementType().getSizeInBits() - InSVT.getSizeInBits();
15073 SignExt = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr,
15074 DAG.getConstant(SignExtShift, dl, MVT::i8));
15080 if (VT == MVT::v2i64 && CurrVT == MVT::v4i32) {
15081 SDValue Sign = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr,
15082 DAG.getConstant(31, dl, MVT::i8));
15083 SDValue Ext = DAG.getVectorShuffle(CurrVT, dl, SignExt, Sign, {0, 4, 1, 5});
15084 return DAG.getBitcast(VT, Ext);
15090 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
15091 SelectionDAG &DAG) {
15092 MVT VT = Op->getSimpleValueType(0);
15093 SDValue In = Op->getOperand(0);
15094 MVT InVT = In.getSimpleValueType();
15097 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
15098 return LowerSIGN_EXTEND_AVX512(Op, Subtarget, DAG);
15100 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
15101 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
15102 (VT != MVT::v16i16 || InVT != MVT::v16i8))
15105 if (Subtarget->hasInt256())
15106 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15108 // Optimize vectors in AVX mode
15109 // Sign extend v8i16 to v8i32 and
15112 // Divide input vector into two parts
15113 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
15114 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
15115 // concat the vectors to original VT
15117 unsigned NumElems = InVT.getVectorNumElements();
15118 SDValue Undef = DAG.getUNDEF(InVT);
15120 SmallVector<int,8> ShufMask1(NumElems, -1);
15121 for (unsigned i = 0; i != NumElems/2; ++i)
15124 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
15126 SmallVector<int,8> ShufMask2(NumElems, -1);
15127 for (unsigned i = 0; i != NumElems/2; ++i)
15128 ShufMask2[i] = i + NumElems/2;
15130 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
15132 MVT HalfVT = MVT::getVectorVT(VT.getVectorElementType(),
15133 VT.getVectorNumElements()/2);
15135 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
15136 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
15138 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
15141 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
15142 // may emit an illegal shuffle but the expansion is still better than scalar
15143 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
15144 // we'll emit a shuffle and a arithmetic shift.
15145 // FIXME: Is the expansion actually better than scalar code? It doesn't seem so.
15146 // TODO: It is possible to support ZExt by zeroing the undef values during
15147 // the shuffle phase or after the shuffle.
15148 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
15149 SelectionDAG &DAG) {
15150 MVT RegVT = Op.getSimpleValueType();
15151 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
15152 assert(RegVT.isInteger() &&
15153 "We only custom lower integer vector sext loads.");
15155 // Nothing useful we can do without SSE2 shuffles.
15156 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
15158 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
15160 EVT MemVT = Ld->getMemoryVT();
15161 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15162 unsigned RegSz = RegVT.getSizeInBits();
15164 ISD::LoadExtType Ext = Ld->getExtensionType();
15166 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
15167 && "Only anyext and sext are currently implemented.");
15168 assert(MemVT != RegVT && "Cannot extend to the same type");
15169 assert(MemVT.isVector() && "Must load a vector from memory");
15171 unsigned NumElems = RegVT.getVectorNumElements();
15172 unsigned MemSz = MemVT.getSizeInBits();
15173 assert(RegSz > MemSz && "Register size must be greater than the mem size");
15175 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
15176 // The only way in which we have a legal 256-bit vector result but not the
15177 // integer 256-bit operations needed to directly lower a sextload is if we
15178 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
15179 // a 128-bit vector and a normal sign_extend to 256-bits that should get
15180 // correctly legalized. We do this late to allow the canonical form of
15181 // sextload to persist throughout the rest of the DAG combiner -- it wants
15182 // to fold together any extensions it can, and so will fuse a sign_extend
15183 // of an sextload into a sextload targeting a wider value.
15185 if (MemSz == 128) {
15186 // Just switch this to a normal load.
15187 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
15188 "it must be a legal 128-bit vector "
15190 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
15191 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
15192 Ld->isInvariant(), Ld->getAlignment());
15194 assert(MemSz < 128 &&
15195 "Can't extend a type wider than 128 bits to a 256 bit vector!");
15196 // Do an sext load to a 128-bit vector type. We want to use the same
15197 // number of elements, but elements half as wide. This will end up being
15198 // recursively lowered by this routine, but will succeed as we definitely
15199 // have all the necessary features if we're using AVX1.
15201 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
15202 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
15204 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
15205 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
15206 Ld->isNonTemporal(), Ld->isInvariant(),
15207 Ld->getAlignment());
15210 // Replace chain users with the new chain.
15211 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
15212 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
15214 // Finally, do a normal sign-extend to the desired register.
15215 return DAG.getSExtOrTrunc(Load, dl, RegVT);
15218 // All sizes must be a power of two.
15219 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
15220 "Non-power-of-two elements are not custom lowered!");
15222 // Attempt to load the original value using scalar loads.
15223 // Find the largest scalar type that divides the total loaded size.
15224 MVT SclrLoadTy = MVT::i8;
15225 for (MVT Tp : MVT::integer_valuetypes()) {
15226 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
15231 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
15232 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
15234 SclrLoadTy = MVT::f64;
15236 // Calculate the number of scalar loads that we need to perform
15237 // in order to load our vector from memory.
15238 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
15240 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
15241 "Can only lower sext loads with a single scalar load!");
15243 unsigned loadRegZize = RegSz;
15244 if (Ext == ISD::SEXTLOAD && RegSz >= 256)
15247 // Represent our vector as a sequence of elements which are the
15248 // largest scalar that we can load.
15249 EVT LoadUnitVecVT = EVT::getVectorVT(
15250 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
15252 // Represent the data using the same element type that is stored in
15253 // memory. In practice, we ''widen'' MemVT.
15255 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
15256 loadRegZize / MemVT.getScalarSizeInBits());
15258 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
15259 "Invalid vector type");
15261 // We can't shuffle using an illegal type.
15262 assert(TLI.isTypeLegal(WideVecVT) &&
15263 "We only lower types that form legal widened vector types");
15265 SmallVector<SDValue, 8> Chains;
15266 SDValue Ptr = Ld->getBasePtr();
15267 SDValue Increment = DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, dl,
15268 TLI.getPointerTy(DAG.getDataLayout()));
15269 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
15271 for (unsigned i = 0; i < NumLoads; ++i) {
15272 // Perform a single load.
15273 SDValue ScalarLoad =
15274 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
15275 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
15276 Ld->getAlignment());
15277 Chains.push_back(ScalarLoad.getValue(1));
15278 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
15279 // another round of DAGCombining.
15281 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
15283 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
15284 ScalarLoad, DAG.getIntPtrConstant(i, dl));
15286 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
15289 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
15291 // Bitcast the loaded value to a vector of the original element type, in
15292 // the size of the target vector type.
15293 SDValue SlicedVec = DAG.getBitcast(WideVecVT, Res);
15294 unsigned SizeRatio = RegSz / MemSz;
15296 if (Ext == ISD::SEXTLOAD) {
15297 // If we have SSE4.1, we can directly emit a VSEXT node.
15298 if (Subtarget->hasSSE41()) {
15299 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
15300 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15304 // Otherwise we'll use SIGN_EXTEND_VECTOR_INREG to sign extend the lowest
15306 assert(TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND_VECTOR_INREG, RegVT) &&
15307 "We can't implement a sext load without SIGN_EXTEND_VECTOR_INREG!");
15309 SDValue Shuff = DAG.getSignExtendVectorInReg(SlicedVec, dl, RegVT);
15310 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15314 // Redistribute the loaded elements into the different locations.
15315 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
15316 for (unsigned i = 0; i != NumElems; ++i)
15317 ShuffleVec[i * SizeRatio] = i;
15319 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
15320 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
15322 // Bitcast to the requested type.
15323 Shuff = DAG.getBitcast(RegVT, Shuff);
15324 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15328 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
15329 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
15330 // from the AND / OR.
15331 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
15332 Opc = Op.getOpcode();
15333 if (Opc != ISD::OR && Opc != ISD::AND)
15335 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15336 Op.getOperand(0).hasOneUse() &&
15337 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
15338 Op.getOperand(1).hasOneUse());
15341 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
15342 // 1 and that the SETCC node has a single use.
15343 static bool isXor1OfSetCC(SDValue Op) {
15344 if (Op.getOpcode() != ISD::XOR)
15346 if (isOneConstant(Op.getOperand(1)))
15347 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15348 Op.getOperand(0).hasOneUse();
15352 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
15353 bool addTest = true;
15354 SDValue Chain = Op.getOperand(0);
15355 SDValue Cond = Op.getOperand(1);
15356 SDValue Dest = Op.getOperand(2);
15359 bool Inverted = false;
15361 if (Cond.getOpcode() == ISD::SETCC) {
15362 // Check for setcc([su]{add,sub,mul}o == 0).
15363 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
15364 isNullConstant(Cond.getOperand(1)) &&
15365 Cond.getOperand(0).getResNo() == 1 &&
15366 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
15367 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
15368 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
15369 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
15370 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
15371 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
15373 Cond = Cond.getOperand(0);
15375 SDValue NewCond = LowerSETCC(Cond, DAG);
15376 if (NewCond.getNode())
15381 // FIXME: LowerXALUO doesn't handle these!!
15382 else if (Cond.getOpcode() == X86ISD::ADD ||
15383 Cond.getOpcode() == X86ISD::SUB ||
15384 Cond.getOpcode() == X86ISD::SMUL ||
15385 Cond.getOpcode() == X86ISD::UMUL)
15386 Cond = LowerXALUO(Cond, DAG);
15389 // Look pass (and (setcc_carry (cmp ...)), 1).
15390 if (Cond.getOpcode() == ISD::AND &&
15391 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY &&
15392 isOneConstant(Cond.getOperand(1)))
15393 Cond = Cond.getOperand(0);
15395 // If condition flag is set by a X86ISD::CMP, then use it as the condition
15396 // setting operand in place of the X86ISD::SETCC.
15397 unsigned CondOpcode = Cond.getOpcode();
15398 if (CondOpcode == X86ISD::SETCC ||
15399 CondOpcode == X86ISD::SETCC_CARRY) {
15400 CC = Cond.getOperand(0);
15402 SDValue Cmp = Cond.getOperand(1);
15403 unsigned Opc = Cmp.getOpcode();
15404 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
15405 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
15409 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
15413 // These can only come from an arithmetic instruction with overflow,
15414 // e.g. SADDO, UADDO.
15415 Cond = Cond.getNode()->getOperand(1);
15421 CondOpcode = Cond.getOpcode();
15422 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
15423 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
15424 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
15425 Cond.getOperand(0).getValueType() != MVT::i8)) {
15426 SDValue LHS = Cond.getOperand(0);
15427 SDValue RHS = Cond.getOperand(1);
15428 unsigned X86Opcode;
15431 // Keep this in sync with LowerXALUO, otherwise we might create redundant
15432 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
15434 switch (CondOpcode) {
15435 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
15437 if (isOneConstant(RHS)) {
15438 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
15441 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
15442 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
15444 if (isOneConstant(RHS)) {
15445 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
15448 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
15449 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
15450 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
15451 default: llvm_unreachable("unexpected overflowing operator");
15454 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
15455 if (CondOpcode == ISD::UMULO)
15456 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
15459 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
15461 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
15463 if (CondOpcode == ISD::UMULO)
15464 Cond = X86Op.getValue(2);
15466 Cond = X86Op.getValue(1);
15468 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
15472 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
15473 SDValue Cmp = Cond.getOperand(0).getOperand(1);
15474 if (CondOpc == ISD::OR) {
15475 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
15476 // two branches instead of an explicit OR instruction with a
15478 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15479 isX86LogicalCmp(Cmp)) {
15480 CC = Cond.getOperand(0).getOperand(0);
15481 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15482 Chain, Dest, CC, Cmp);
15483 CC = Cond.getOperand(1).getOperand(0);
15487 } else { // ISD::AND
15488 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
15489 // two branches instead of an explicit AND instruction with a
15490 // separate test. However, we only do this if this block doesn't
15491 // have a fall-through edge, because this requires an explicit
15492 // jmp when the condition is false.
15493 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15494 isX86LogicalCmp(Cmp) &&
15495 Op.getNode()->hasOneUse()) {
15496 X86::CondCode CCode =
15497 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15498 CCode = X86::GetOppositeBranchCondition(CCode);
15499 CC = DAG.getConstant(CCode, dl, MVT::i8);
15500 SDNode *User = *Op.getNode()->use_begin();
15501 // Look for an unconditional branch following this conditional branch.
15502 // We need this because we need to reverse the successors in order
15503 // to implement FCMP_OEQ.
15504 if (User->getOpcode() == ISD::BR) {
15505 SDValue FalseBB = User->getOperand(1);
15507 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15508 assert(NewBR == User);
15512 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15513 Chain, Dest, CC, Cmp);
15514 X86::CondCode CCode =
15515 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
15516 CCode = X86::GetOppositeBranchCondition(CCode);
15517 CC = DAG.getConstant(CCode, dl, MVT::i8);
15523 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
15524 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
15525 // It should be transformed during dag combiner except when the condition
15526 // is set by a arithmetics with overflow node.
15527 X86::CondCode CCode =
15528 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15529 CCode = X86::GetOppositeBranchCondition(CCode);
15530 CC = DAG.getConstant(CCode, dl, MVT::i8);
15531 Cond = Cond.getOperand(0).getOperand(1);
15533 } else if (Cond.getOpcode() == ISD::SETCC &&
15534 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
15535 // For FCMP_OEQ, we can emit
15536 // two branches instead of an explicit AND instruction with a
15537 // separate test. However, we only do this if this block doesn't
15538 // have a fall-through edge, because this requires an explicit
15539 // jmp when the condition is false.
15540 if (Op.getNode()->hasOneUse()) {
15541 SDNode *User = *Op.getNode()->use_begin();
15542 // Look for an unconditional branch following this conditional branch.
15543 // We need this because we need to reverse the successors in order
15544 // to implement FCMP_OEQ.
15545 if (User->getOpcode() == ISD::BR) {
15546 SDValue FalseBB = User->getOperand(1);
15548 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15549 assert(NewBR == User);
15553 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15554 Cond.getOperand(0), Cond.getOperand(1));
15555 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15556 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
15557 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15558 Chain, Dest, CC, Cmp);
15559 CC = DAG.getConstant(X86::COND_P, dl, MVT::i8);
15564 } else if (Cond.getOpcode() == ISD::SETCC &&
15565 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
15566 // For FCMP_UNE, we can emit
15567 // two branches instead of an explicit AND instruction with a
15568 // separate test. However, we only do this if this block doesn't
15569 // have a fall-through edge, because this requires an explicit
15570 // jmp when the condition is false.
15571 if (Op.getNode()->hasOneUse()) {
15572 SDNode *User = *Op.getNode()->use_begin();
15573 // Look for an unconditional branch following this conditional branch.
15574 // We need this because we need to reverse the successors in order
15575 // to implement FCMP_UNE.
15576 if (User->getOpcode() == ISD::BR) {
15577 SDValue FalseBB = User->getOperand(1);
15579 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15580 assert(NewBR == User);
15583 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15584 Cond.getOperand(0), Cond.getOperand(1));
15585 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15586 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
15587 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15588 Chain, Dest, CC, Cmp);
15589 CC = DAG.getConstant(X86::COND_NP, dl, MVT::i8);
15599 // Look pass the truncate if the high bits are known zero.
15600 if (isTruncWithZeroHighBitsInput(Cond, DAG))
15601 Cond = Cond.getOperand(0);
15603 // We know the result of AND is compared against zero. Try to match
15605 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
15606 if (SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG)) {
15607 CC = NewSetCC.getOperand(0);
15608 Cond = NewSetCC.getOperand(1);
15615 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
15616 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
15617 Cond = EmitTest(Cond, X86Cond, dl, DAG);
15619 Cond = ConvertCmpIfNecessary(Cond, DAG);
15620 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15621 Chain, Dest, CC, Cond);
15624 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
15625 // Calls to _alloca are needed to probe the stack when allocating more than 4k
15626 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
15627 // that the guard pages used by the OS virtual memory manager are allocated in
15628 // correct sequence.
15630 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
15631 SelectionDAG &DAG) const {
15632 MachineFunction &MF = DAG.getMachineFunction();
15633 bool SplitStack = MF.shouldSplitStack();
15634 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMachO()) ||
15639 SDNode *Node = Op.getNode();
15640 SDValue Chain = Op.getOperand(0);
15641 SDValue Size = Op.getOperand(1);
15642 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
15643 EVT VT = Node->getValueType(0);
15645 // Chain the dynamic stack allocation so that it doesn't modify the stack
15646 // pointer when other instructions are using the stack.
15647 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, dl, true), dl);
15649 bool Is64Bit = Subtarget->is64Bit();
15650 MVT SPTy = getPointerTy(DAG.getDataLayout());
15654 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15655 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
15656 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
15657 " not tell us which reg is the stack pointer!");
15658 EVT VT = Node->getValueType(0);
15659 SDValue Tmp3 = Node->getOperand(2);
15661 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
15662 Chain = SP.getValue(1);
15663 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
15664 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
15665 unsigned StackAlign = TFI.getStackAlignment();
15666 Result = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
15667 if (Align > StackAlign)
15668 Result = DAG.getNode(ISD::AND, dl, VT, Result,
15669 DAG.getConstant(-(uint64_t)Align, dl, VT));
15670 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Result); // Output chain
15671 } else if (SplitStack) {
15672 MachineRegisterInfo &MRI = MF.getRegInfo();
15675 // The 64 bit implementation of segmented stacks needs to clobber both r10
15676 // r11. This makes it impossible to use it along with nested parameters.
15677 const Function *F = MF.getFunction();
15679 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
15681 if (I->hasNestAttr())
15682 report_fatal_error("Cannot use segmented stacks with functions that "
15683 "have nested arguments.");
15686 const TargetRegisterClass *AddrRegClass = getRegClassFor(SPTy);
15687 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
15688 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
15689 Result = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
15690 DAG.getRegister(Vreg, SPTy));
15693 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
15695 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
15696 Flag = Chain.getValue(1);
15697 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
15699 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
15701 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15702 unsigned SPReg = RegInfo->getStackRegister();
15703 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
15704 Chain = SP.getValue(1);
15707 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
15708 DAG.getConstant(-(uint64_t)Align, dl, VT));
15709 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
15715 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, dl, true),
15716 DAG.getIntPtrConstant(0, dl, true), SDValue(), dl);
15718 SDValue Ops[2] = {Result, Chain};
15719 return DAG.getMergeValues(Ops, dl);
15722 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
15723 MachineFunction &MF = DAG.getMachineFunction();
15724 auto PtrVT = getPointerTy(MF.getDataLayout());
15725 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
15727 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15730 if (!Subtarget->is64Bit() ||
15731 Subtarget->isCallingConvWin64(MF.getFunction()->getCallingConv())) {
15732 // vastart just stores the address of the VarArgsFrameIndex slot into the
15733 // memory location argument.
15734 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
15735 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
15736 MachinePointerInfo(SV), false, false, 0);
15740 // gp_offset (0 - 6 * 8)
15741 // fp_offset (48 - 48 + 8 * 16)
15742 // overflow_arg_area (point to parameters coming in memory).
15744 SmallVector<SDValue, 8> MemOps;
15745 SDValue FIN = Op.getOperand(1);
15747 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
15748 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
15750 FIN, MachinePointerInfo(SV), false, false, 0);
15751 MemOps.push_back(Store);
15754 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(4, DL));
15755 Store = DAG.getStore(Op.getOperand(0), DL,
15756 DAG.getConstant(FuncInfo->getVarArgsFPOffset(), DL,
15758 FIN, MachinePointerInfo(SV, 4), false, false, 0);
15759 MemOps.push_back(Store);
15761 // Store ptr to overflow_arg_area
15762 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(4, DL));
15763 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
15764 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
15765 MachinePointerInfo(SV, 8),
15767 MemOps.push_back(Store);
15769 // Store ptr to reg_save_area.
15770 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(
15771 Subtarget->isTarget64BitLP64() ? 8 : 4, DL));
15772 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), PtrVT);
15773 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN, MachinePointerInfo(
15774 SV, Subtarget->isTarget64BitLP64() ? 16 : 12), false, false, 0);
15775 MemOps.push_back(Store);
15776 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
15779 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
15780 assert(Subtarget->is64Bit() &&
15781 "LowerVAARG only handles 64-bit va_arg!");
15782 assert(Op.getNode()->getNumOperands() == 4);
15784 MachineFunction &MF = DAG.getMachineFunction();
15785 if (Subtarget->isCallingConvWin64(MF.getFunction()->getCallingConv()))
15786 // The Win64 ABI uses char* instead of a structure.
15787 return DAG.expandVAArg(Op.getNode());
15789 SDValue Chain = Op.getOperand(0);
15790 SDValue SrcPtr = Op.getOperand(1);
15791 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15792 unsigned Align = Op.getConstantOperandVal(3);
15795 EVT ArgVT = Op.getNode()->getValueType(0);
15796 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
15797 uint32_t ArgSize = DAG.getDataLayout().getTypeAllocSize(ArgTy);
15800 // Decide which area this value should be read from.
15801 // TODO: Implement the AMD64 ABI in its entirety. This simple
15802 // selection mechanism works only for the basic types.
15803 if (ArgVT == MVT::f80) {
15804 llvm_unreachable("va_arg for f80 not yet implemented");
15805 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
15806 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
15807 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
15808 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
15810 llvm_unreachable("Unhandled argument type in LowerVAARG");
15813 if (ArgMode == 2) {
15814 // Sanity Check: Make sure using fp_offset makes sense.
15815 assert(!Subtarget->useSoftFloat() &&
15816 !(MF.getFunction()->hasFnAttribute(Attribute::NoImplicitFloat)) &&
15817 Subtarget->hasSSE1());
15820 // Insert VAARG_64 node into the DAG
15821 // VAARG_64 returns two values: Variable Argument Address, Chain
15822 SDValue InstOps[] = {Chain, SrcPtr, DAG.getConstant(ArgSize, dl, MVT::i32),
15823 DAG.getConstant(ArgMode, dl, MVT::i8),
15824 DAG.getConstant(Align, dl, MVT::i32)};
15825 SDVTList VTs = DAG.getVTList(getPointerTy(DAG.getDataLayout()), MVT::Other);
15826 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
15827 VTs, InstOps, MVT::i64,
15828 MachinePointerInfo(SV),
15830 /*Volatile=*/false,
15832 /*WriteMem=*/true);
15833 Chain = VAARG.getValue(1);
15835 // Load the next argument and return it
15836 return DAG.getLoad(ArgVT, dl,
15839 MachinePointerInfo(),
15840 false, false, false, 0);
15843 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
15844 SelectionDAG &DAG) {
15845 // X86-64 va_list is a struct { i32, i32, i8*, i8* }, except on Windows,
15846 // where a va_list is still an i8*.
15847 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
15848 if (Subtarget->isCallingConvWin64(
15849 DAG.getMachineFunction().getFunction()->getCallingConv()))
15850 // Probably a Win64 va_copy.
15851 return DAG.expandVACopy(Op.getNode());
15853 SDValue Chain = Op.getOperand(0);
15854 SDValue DstPtr = Op.getOperand(1);
15855 SDValue SrcPtr = Op.getOperand(2);
15856 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
15857 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
15860 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
15861 DAG.getIntPtrConstant(24, DL), 8, /*isVolatile*/false,
15863 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
15866 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
15867 // amount is a constant. Takes immediate version of shift as input.
15868 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
15869 SDValue SrcOp, uint64_t ShiftAmt,
15870 SelectionDAG &DAG) {
15871 MVT ElementType = VT.getVectorElementType();
15873 // Fold this packed shift into its first operand if ShiftAmt is 0.
15877 // Check for ShiftAmt >= element width
15878 if (ShiftAmt >= ElementType.getSizeInBits()) {
15879 if (Opc == X86ISD::VSRAI)
15880 ShiftAmt = ElementType.getSizeInBits() - 1;
15882 return DAG.getConstant(0, dl, VT);
15885 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
15886 && "Unknown target vector shift-by-constant node");
15888 // Fold this packed vector shift into a build vector if SrcOp is a
15889 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
15890 if (VT == SrcOp.getSimpleValueType() &&
15891 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
15892 SmallVector<SDValue, 8> Elts;
15893 unsigned NumElts = SrcOp->getNumOperands();
15894 ConstantSDNode *ND;
15897 default: llvm_unreachable(nullptr);
15898 case X86ISD::VSHLI:
15899 for (unsigned i=0; i!=NumElts; ++i) {
15900 SDValue CurrentOp = SrcOp->getOperand(i);
15901 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15902 Elts.push_back(CurrentOp);
15905 ND = cast<ConstantSDNode>(CurrentOp);
15906 const APInt &C = ND->getAPIntValue();
15907 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), dl, ElementType));
15910 case X86ISD::VSRLI:
15911 for (unsigned i=0; i!=NumElts; ++i) {
15912 SDValue CurrentOp = SrcOp->getOperand(i);
15913 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15914 Elts.push_back(CurrentOp);
15917 ND = cast<ConstantSDNode>(CurrentOp);
15918 const APInt &C = ND->getAPIntValue();
15919 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), dl, ElementType));
15922 case X86ISD::VSRAI:
15923 for (unsigned i=0; i!=NumElts; ++i) {
15924 SDValue CurrentOp = SrcOp->getOperand(i);
15925 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15926 Elts.push_back(CurrentOp);
15929 ND = cast<ConstantSDNode>(CurrentOp);
15930 const APInt &C = ND->getAPIntValue();
15931 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), dl, ElementType));
15936 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
15939 return DAG.getNode(Opc, dl, VT, SrcOp,
15940 DAG.getConstant(ShiftAmt, dl, MVT::i8));
15943 // getTargetVShiftNode - Handle vector element shifts where the shift amount
15944 // may or may not be a constant. Takes immediate version of shift as input.
15945 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
15946 SDValue SrcOp, SDValue ShAmt,
15947 SelectionDAG &DAG) {
15948 MVT SVT = ShAmt.getSimpleValueType();
15949 assert((SVT == MVT::i32 || SVT == MVT::i64) && "Unexpected value type!");
15951 // Catch shift-by-constant.
15952 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
15953 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
15954 CShAmt->getZExtValue(), DAG);
15956 // Change opcode to non-immediate version
15958 default: llvm_unreachable("Unknown target vector shift node");
15959 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
15960 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
15961 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
15964 const X86Subtarget &Subtarget =
15965 static_cast<const X86Subtarget &>(DAG.getSubtarget());
15966 if (Subtarget.hasSSE41() && ShAmt.getOpcode() == ISD::ZERO_EXTEND &&
15967 ShAmt.getOperand(0).getSimpleValueType() == MVT::i16) {
15968 // Let the shuffle legalizer expand this shift amount node.
15969 SDValue Op0 = ShAmt.getOperand(0);
15970 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(Op0), MVT::v8i16, Op0);
15971 ShAmt = getShuffleVectorZeroOrUndef(Op0, 0, true, &Subtarget, DAG);
15973 // Need to build a vector containing shift amount.
15974 // SSE/AVX packed shifts only use the lower 64-bit of the shift count.
15975 SmallVector<SDValue, 4> ShOps;
15976 ShOps.push_back(ShAmt);
15977 if (SVT == MVT::i32) {
15978 ShOps.push_back(DAG.getConstant(0, dl, SVT));
15979 ShOps.push_back(DAG.getUNDEF(SVT));
15981 ShOps.push_back(DAG.getUNDEF(SVT));
15983 MVT BVT = SVT == MVT::i32 ? MVT::v4i32 : MVT::v2i64;
15984 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, BVT, ShOps);
15987 // The return type has to be a 128-bit type with the same element
15988 // type as the input type.
15989 MVT EltVT = VT.getVectorElementType();
15990 MVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
15992 ShAmt = DAG.getBitcast(ShVT, ShAmt);
15993 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
15996 /// \brief Return Mask with the necessary casting or extending
15997 /// for \p Mask according to \p MaskVT when lowering masking intrinsics
15998 static SDValue getMaskNode(SDValue Mask, MVT MaskVT,
15999 const X86Subtarget *Subtarget,
16000 SelectionDAG &DAG, SDLoc dl) {
16002 if (MaskVT.bitsGT(Mask.getSimpleValueType())) {
16003 // Mask should be extended
16004 Mask = DAG.getNode(ISD::ANY_EXTEND, dl,
16005 MVT::getIntegerVT(MaskVT.getSizeInBits()), Mask);
16008 if (Mask.getSimpleValueType() == MVT::i64 && Subtarget->is32Bit()) {
16009 if (MaskVT == MVT::v64i1) {
16010 assert(Subtarget->hasBWI() && "Expected AVX512BW target!");
16011 // In case 32bit mode, bitcast i64 is illegal, extend/split it.
16013 Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Mask,
16014 DAG.getConstant(0, dl, MVT::i32));
16015 Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Mask,
16016 DAG.getConstant(1, dl, MVT::i32));
16018 Lo = DAG.getBitcast(MVT::v32i1, Lo);
16019 Hi = DAG.getBitcast(MVT::v32i1, Hi);
16021 return DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v64i1, Lo, Hi);
16023 // MaskVT require < 64bit. Truncate mask (should succeed in any case),
16025 MVT TruncVT = MVT::getIntegerVT(MaskVT.getSizeInBits());
16026 return DAG.getBitcast(MaskVT,
16027 DAG.getNode(ISD::TRUNCATE, dl, TruncVT, Mask));
16031 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
16032 Mask.getSimpleValueType().getSizeInBits());
16033 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16034 // are extracted by EXTRACT_SUBVECTOR.
16035 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16036 DAG.getBitcast(BitcastVT, Mask),
16037 DAG.getIntPtrConstant(0, dl));
16041 /// \brief Return (and \p Op, \p Mask) for compare instructions or
16042 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
16043 /// necessary casting or extending for \p Mask when lowering masking intrinsics
16044 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
16045 SDValue PreservedSrc,
16046 const X86Subtarget *Subtarget,
16047 SelectionDAG &DAG) {
16048 MVT VT = Op.getSimpleValueType();
16049 MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
16050 unsigned OpcodeSelect = ISD::VSELECT;
16053 if (isAllOnesConstant(Mask))
16056 SDValue VMask = getMaskNode(Mask, MaskVT, Subtarget, DAG, dl);
16058 switch (Op.getOpcode()) {
16060 case X86ISD::PCMPEQM:
16061 case X86ISD::PCMPGTM:
16063 case X86ISD::CMPMU:
16064 return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
16065 case X86ISD::VFPCLASS:
16066 case X86ISD::VFPCLASSS:
16067 return DAG.getNode(ISD::OR, dl, VT, Op, VMask);
16068 case X86ISD::VTRUNC:
16069 case X86ISD::VTRUNCS:
16070 case X86ISD::VTRUNCUS:
16071 // We can't use ISD::VSELECT here because it is not always "Legal"
16072 // for the destination type. For example vpmovqb require only AVX512
16073 // and vselect that can operate on byte element type require BWI
16074 OpcodeSelect = X86ISD::SELECT;
16077 if (PreservedSrc.getOpcode() == ISD::UNDEF)
16078 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
16079 return DAG.getNode(OpcodeSelect, dl, VT, VMask, Op, PreservedSrc);
16082 /// \brief Creates an SDNode for a predicated scalar operation.
16083 /// \returns (X86vselect \p Mask, \p Op, \p PreservedSrc).
16084 /// The mask is coming as MVT::i8 and it should be truncated
16085 /// to MVT::i1 while lowering masking intrinsics.
16086 /// The main difference between ScalarMaskingNode and VectorMaskingNode is using
16087 /// "X86select" instead of "vselect". We just can't create the "vselect" node
16088 /// for a scalar instruction.
16089 static SDValue getScalarMaskingNode(SDValue Op, SDValue Mask,
16090 SDValue PreservedSrc,
16091 const X86Subtarget *Subtarget,
16092 SelectionDAG &DAG) {
16093 if (isAllOnesConstant(Mask))
16096 MVT VT = Op.getSimpleValueType();
16098 // The mask should be of type MVT::i1
16099 SDValue IMask = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Mask);
16101 if (Op.getOpcode() == X86ISD::FSETCC)
16102 return DAG.getNode(ISD::AND, dl, VT, Op, IMask);
16103 if (Op.getOpcode() == X86ISD::VFPCLASS ||
16104 Op.getOpcode() == X86ISD::VFPCLASSS)
16105 return DAG.getNode(ISD::OR, dl, VT, Op, IMask);
16107 if (PreservedSrc.getOpcode() == ISD::UNDEF)
16108 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
16109 return DAG.getNode(X86ISD::SELECT, dl, VT, IMask, Op, PreservedSrc);
16112 static int getSEHRegistrationNodeSize(const Function *Fn) {
16113 if (!Fn->hasPersonalityFn())
16114 report_fatal_error(
16115 "querying registration node size for function without personality");
16116 // The RegNodeSize is 6 32-bit words for SEH and 4 for C++ EH. See
16117 // WinEHStatePass for the full struct definition.
16118 switch (classifyEHPersonality(Fn->getPersonalityFn())) {
16119 case EHPersonality::MSVC_X86SEH: return 24;
16120 case EHPersonality::MSVC_CXX: return 16;
16123 report_fatal_error("can only recover FP for MSVC EH personality functions");
16126 /// When the 32-bit MSVC runtime transfers control to us, either to an outlined
16127 /// function or when returning to a parent frame after catching an exception, we
16128 /// recover the parent frame pointer by doing arithmetic on the incoming EBP.
16129 /// Here's the math:
16130 /// RegNodeBase = EntryEBP - RegNodeSize
16131 /// ParentFP = RegNodeBase - RegNodeFrameOffset
16132 /// Subtracting RegNodeSize takes us to the offset of the registration node, and
16133 /// subtracting the offset (negative on x86) takes us back to the parent FP.
16134 static SDValue recoverFramePointer(SelectionDAG &DAG, const Function *Fn,
16135 SDValue EntryEBP) {
16136 MachineFunction &MF = DAG.getMachineFunction();
16139 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16140 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());
16142 // It's possible that the parent function no longer has a personality function
16143 // if the exceptional code was optimized away, in which case we just return
16144 // the incoming EBP.
16145 if (!Fn->hasPersonalityFn())
16148 int RegNodeSize = getSEHRegistrationNodeSize(Fn);
16150 // Get an MCSymbol that will ultimately resolve to the frame offset of the EH
16152 MCSymbol *OffsetSym =
16153 MF.getMMI().getContext().getOrCreateParentFrameOffsetSymbol(
16154 GlobalValue::getRealLinkageName(Fn->getName()));
16155 SDValue OffsetSymVal = DAG.getMCSymbol(OffsetSym, PtrVT);
16156 SDValue RegNodeFrameOffset =
16157 DAG.getNode(ISD::LOCAL_RECOVER, dl, PtrVT, OffsetSymVal);
16159 // RegNodeBase = EntryEBP - RegNodeSize
16160 // ParentFP = RegNodeBase - RegNodeFrameOffset
16161 SDValue RegNodeBase = DAG.getNode(ISD::SUB, dl, PtrVT, EntryEBP,
16162 DAG.getConstant(RegNodeSize, dl, PtrVT));
16163 return DAG.getNode(ISD::SUB, dl, PtrVT, RegNodeBase, RegNodeFrameOffset);
16166 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
16167 SelectionDAG &DAG) {
16169 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16170 MVT VT = Op.getSimpleValueType();
16171 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
16173 switch(IntrData->Type) {
16174 case INTR_TYPE_1OP:
16175 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
16176 case INTR_TYPE_2OP:
16177 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16179 case INTR_TYPE_2OP_IMM8:
16180 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16181 DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op.getOperand(2)));
16182 case INTR_TYPE_3OP:
16183 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16184 Op.getOperand(2), Op.getOperand(3));
16185 case INTR_TYPE_4OP:
16186 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16187 Op.getOperand(2), Op.getOperand(3), Op.getOperand(4));
16188 case INTR_TYPE_1OP_MASK_RM: {
16189 SDValue Src = Op.getOperand(1);
16190 SDValue PassThru = Op.getOperand(2);
16191 SDValue Mask = Op.getOperand(3);
16192 SDValue RoundingMode;
16193 // We allways add rounding mode to the Node.
16194 // If the rounding mode is not specified, we add the
16195 // "current direction" mode.
16196 if (Op.getNumOperands() == 4)
16198 DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
16200 RoundingMode = Op.getOperand(4);
16201 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16202 if (IntrWithRoundingModeOpcode != 0)
16203 if (cast<ConstantSDNode>(RoundingMode)->getZExtValue() !=
16204 X86::STATIC_ROUNDING::CUR_DIRECTION)
16205 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16206 dl, Op.getValueType(), Src, RoundingMode),
16207 Mask, PassThru, Subtarget, DAG);
16208 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src,
16210 Mask, PassThru, Subtarget, DAG);
16212 case INTR_TYPE_1OP_MASK: {
16213 SDValue Src = Op.getOperand(1);
16214 SDValue PassThru = Op.getOperand(2);
16215 SDValue Mask = Op.getOperand(3);
16216 // We add rounding mode to the Node when
16217 // - RM Opcode is specified and
16218 // - RM is not "current direction".
16219 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16220 if (IntrWithRoundingModeOpcode != 0) {
16221 SDValue Rnd = Op.getOperand(4);
16222 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
16223 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
16224 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16225 dl, Op.getValueType(),
16227 Mask, PassThru, Subtarget, DAG);
16230 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src),
16231 Mask, PassThru, Subtarget, DAG);
16233 case INTR_TYPE_SCALAR_MASK: {
16234 SDValue Src1 = Op.getOperand(1);
16235 SDValue Src2 = Op.getOperand(2);
16236 SDValue passThru = Op.getOperand(3);
16237 SDValue Mask = Op.getOperand(4);
16238 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2),
16239 Mask, passThru, Subtarget, DAG);
16241 case INTR_TYPE_SCALAR_MASK_RM: {
16242 SDValue Src1 = Op.getOperand(1);
16243 SDValue Src2 = Op.getOperand(2);
16244 SDValue Src0 = Op.getOperand(3);
16245 SDValue Mask = Op.getOperand(4);
16246 // There are 2 kinds of intrinsics in this group:
16247 // (1) With suppress-all-exceptions (sae) or rounding mode- 6 operands
16248 // (2) With rounding mode and sae - 7 operands.
16249 if (Op.getNumOperands() == 6) {
16250 SDValue Sae = Op.getOperand(5);
16251 unsigned Opc = IntrData->Opc1 ? IntrData->Opc1 : IntrData->Opc0;
16252 return getScalarMaskingNode(DAG.getNode(Opc, dl, VT, Src1, Src2,
16254 Mask, Src0, Subtarget, DAG);
16256 assert(Op.getNumOperands() == 7 && "Unexpected intrinsic form");
16257 SDValue RoundingMode = Op.getOperand(5);
16258 SDValue Sae = Op.getOperand(6);
16259 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2,
16260 RoundingMode, Sae),
16261 Mask, Src0, Subtarget, DAG);
16263 case INTR_TYPE_2OP_MASK:
16264 case INTR_TYPE_2OP_IMM8_MASK: {
16265 SDValue Src1 = Op.getOperand(1);
16266 SDValue Src2 = Op.getOperand(2);
16267 SDValue PassThru = Op.getOperand(3);
16268 SDValue Mask = Op.getOperand(4);
16270 if (IntrData->Type == INTR_TYPE_2OP_IMM8_MASK)
16271 Src2 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Src2);
16273 // We specify 2 possible opcodes for intrinsics with rounding modes.
16274 // First, we check if the intrinsic may have non-default rounding mode,
16275 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16276 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16277 if (IntrWithRoundingModeOpcode != 0) {
16278 SDValue Rnd = Op.getOperand(5);
16279 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
16280 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
16281 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16282 dl, Op.getValueType(),
16284 Mask, PassThru, Subtarget, DAG);
16287 // TODO: Intrinsics should have fast-math-flags to propagate.
16288 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,Src1,Src2),
16289 Mask, PassThru, Subtarget, DAG);
16291 case INTR_TYPE_2OP_MASK_RM: {
16292 SDValue Src1 = Op.getOperand(1);
16293 SDValue Src2 = Op.getOperand(2);
16294 SDValue PassThru = Op.getOperand(3);
16295 SDValue Mask = Op.getOperand(4);
16296 // We specify 2 possible modes for intrinsics, with/without rounding
16298 // First, we check if the intrinsic have rounding mode (6 operands),
16299 // if not, we set rounding mode to "current".
16301 if (Op.getNumOperands() == 6)
16302 Rnd = Op.getOperand(5);
16304 Rnd = DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
16305 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16307 Mask, PassThru, Subtarget, DAG);
16309 case INTR_TYPE_3OP_SCALAR_MASK_RM: {
16310 SDValue Src1 = Op.getOperand(1);
16311 SDValue Src2 = Op.getOperand(2);
16312 SDValue Src3 = Op.getOperand(3);
16313 SDValue PassThru = Op.getOperand(4);
16314 SDValue Mask = Op.getOperand(5);
16315 SDValue Sae = Op.getOperand(6);
16317 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1,
16319 Mask, PassThru, Subtarget, DAG);
16321 case INTR_TYPE_3OP_MASK_RM: {
16322 SDValue Src1 = Op.getOperand(1);
16323 SDValue Src2 = Op.getOperand(2);
16324 SDValue Imm = Op.getOperand(3);
16325 SDValue PassThru = Op.getOperand(4);
16326 SDValue Mask = Op.getOperand(5);
16327 // We specify 2 possible modes for intrinsics, with/without rounding
16329 // First, we check if the intrinsic have rounding mode (7 operands),
16330 // if not, we set rounding mode to "current".
16332 if (Op.getNumOperands() == 7)
16333 Rnd = Op.getOperand(6);
16335 Rnd = DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
16336 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16337 Src1, Src2, Imm, Rnd),
16338 Mask, PassThru, Subtarget, DAG);
16340 case INTR_TYPE_3OP_IMM8_MASK:
16341 case INTR_TYPE_3OP_MASK:
16342 case INSERT_SUBVEC: {
16343 SDValue Src1 = Op.getOperand(1);
16344 SDValue Src2 = Op.getOperand(2);
16345 SDValue Src3 = Op.getOperand(3);
16346 SDValue PassThru = Op.getOperand(4);
16347 SDValue Mask = Op.getOperand(5);
16349 if (IntrData->Type == INTR_TYPE_3OP_IMM8_MASK)
16350 Src3 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Src3);
16351 else if (IntrData->Type == INSERT_SUBVEC) {
16352 // imm should be adapted to ISD::INSERT_SUBVECTOR behavior
16353 assert(isa<ConstantSDNode>(Src3) && "Expected a ConstantSDNode here!");
16354 unsigned Imm = cast<ConstantSDNode>(Src3)->getZExtValue();
16355 Imm *= Src2.getSimpleValueType().getVectorNumElements();
16356 Src3 = DAG.getTargetConstant(Imm, dl, MVT::i32);
16359 // We specify 2 possible opcodes for intrinsics with rounding modes.
16360 // First, we check if the intrinsic may have non-default rounding mode,
16361 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16362 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16363 if (IntrWithRoundingModeOpcode != 0) {
16364 SDValue Rnd = Op.getOperand(6);
16365 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
16366 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
16367 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16368 dl, Op.getValueType(),
16369 Src1, Src2, Src3, Rnd),
16370 Mask, PassThru, Subtarget, DAG);
16373 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16375 Mask, PassThru, Subtarget, DAG);
16377 case VPERM_3OP_MASKZ:
16378 case VPERM_3OP_MASK:{
16379 // Src2 is the PassThru
16380 SDValue Src1 = Op.getOperand(1);
16381 SDValue Src2 = Op.getOperand(2);
16382 SDValue Src3 = Op.getOperand(3);
16383 SDValue Mask = Op.getOperand(4);
16384 MVT VT = Op.getSimpleValueType();
16385 SDValue PassThru = SDValue();
16387 // set PassThru element
16388 if (IntrData->Type == VPERM_3OP_MASKZ)
16389 PassThru = getZeroVector(VT, Subtarget, DAG, dl);
16391 PassThru = DAG.getBitcast(VT, Src2);
16393 // Swap Src1 and Src2 in the node creation
16394 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0,
16395 dl, Op.getValueType(),
16397 Mask, PassThru, Subtarget, DAG);
16401 case FMA_OP_MASK: {
16402 SDValue Src1 = Op.getOperand(1);
16403 SDValue Src2 = Op.getOperand(2);
16404 SDValue Src3 = Op.getOperand(3);
16405 SDValue Mask = Op.getOperand(4);
16406 MVT VT = Op.getSimpleValueType();
16407 SDValue PassThru = SDValue();
16409 // set PassThru element
16410 if (IntrData->Type == FMA_OP_MASKZ)
16411 PassThru = getZeroVector(VT, Subtarget, DAG, dl);
16412 else if (IntrData->Type == FMA_OP_MASK3)
16417 // We specify 2 possible opcodes for intrinsics with rounding modes.
16418 // First, we check if the intrinsic may have non-default rounding mode,
16419 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16420 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16421 if (IntrWithRoundingModeOpcode != 0) {
16422 SDValue Rnd = Op.getOperand(5);
16423 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
16424 X86::STATIC_ROUNDING::CUR_DIRECTION)
16425 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16426 dl, Op.getValueType(),
16427 Src1, Src2, Src3, Rnd),
16428 Mask, PassThru, Subtarget, DAG);
16430 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0,
16431 dl, Op.getValueType(),
16433 Mask, PassThru, Subtarget, DAG);
16435 case TERLOG_OP_MASK:
16436 case TERLOG_OP_MASKZ: {
16437 SDValue Src1 = Op.getOperand(1);
16438 SDValue Src2 = Op.getOperand(2);
16439 SDValue Src3 = Op.getOperand(3);
16440 SDValue Src4 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op.getOperand(4));
16441 SDValue Mask = Op.getOperand(5);
16442 MVT VT = Op.getSimpleValueType();
16443 SDValue PassThru = Src1;
16444 // Set PassThru element.
16445 if (IntrData->Type == TERLOG_OP_MASKZ)
16446 PassThru = getZeroVector(VT, Subtarget, DAG, dl);
16448 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16449 Src1, Src2, Src3, Src4),
16450 Mask, PassThru, Subtarget, DAG);
16453 // FPclass intrinsics with mask
16454 SDValue Src1 = Op.getOperand(1);
16455 MVT VT = Src1.getSimpleValueType();
16456 MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
16457 SDValue Imm = Op.getOperand(2);
16458 SDValue Mask = Op.getOperand(3);
16459 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
16460 Mask.getSimpleValueType().getSizeInBits());
16461 SDValue FPclass = DAG.getNode(IntrData->Opc0, dl, MaskVT, Src1, Imm);
16462 SDValue FPclassMask = getVectorMaskingNode(FPclass, Mask,
16463 DAG.getTargetConstant(0, dl, MaskVT),
16465 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16466 DAG.getUNDEF(BitcastVT), FPclassMask,
16467 DAG.getIntPtrConstant(0, dl));
16468 return DAG.getBitcast(Op.getValueType(), Res);
16471 SDValue Src1 = Op.getOperand(1);
16472 SDValue Imm = Op.getOperand(2);
16473 SDValue Mask = Op.getOperand(3);
16474 SDValue FPclass = DAG.getNode(IntrData->Opc0, dl, MVT::i1, Src1, Imm);
16475 SDValue FPclassMask = getScalarMaskingNode(FPclass, Mask,
16476 DAG.getTargetConstant(0, dl, MVT::i1), Subtarget, DAG);
16477 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i8, FPclassMask);
16480 case CMP_MASK_CC: {
16481 // Comparison intrinsics with masks.
16482 // Example of transformation:
16483 // (i8 (int_x86_avx512_mask_pcmpeq_q_128
16484 // (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
16486 // (v8i1 (insert_subvector undef,
16487 // (v2i1 (and (PCMPEQM %a, %b),
16488 // (extract_subvector
16489 // (v8i1 (bitcast %mask)), 0))), 0))))
16490 MVT VT = Op.getOperand(1).getSimpleValueType();
16491 MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
16492 SDValue Mask = Op.getOperand((IntrData->Type == CMP_MASK_CC) ? 4 : 3);
16493 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
16494 Mask.getSimpleValueType().getSizeInBits());
16496 if (IntrData->Type == CMP_MASK_CC) {
16497 SDValue CC = Op.getOperand(3);
16498 CC = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, CC);
16499 // We specify 2 possible opcodes for intrinsics with rounding modes.
16500 // First, we check if the intrinsic may have non-default rounding mode,
16501 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16502 if (IntrData->Opc1 != 0) {
16503 SDValue Rnd = Op.getOperand(5);
16504 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
16505 X86::STATIC_ROUNDING::CUR_DIRECTION)
16506 Cmp = DAG.getNode(IntrData->Opc1, dl, MaskVT, Op.getOperand(1),
16507 Op.getOperand(2), CC, Rnd);
16509 //default rounding mode
16511 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16512 Op.getOperand(2), CC);
16515 assert(IntrData->Type == CMP_MASK && "Unexpected intrinsic type!");
16516 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16519 SDValue CmpMask = getVectorMaskingNode(Cmp, Mask,
16520 DAG.getTargetConstant(0, dl,
16523 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16524 DAG.getUNDEF(BitcastVT), CmpMask,
16525 DAG.getIntPtrConstant(0, dl));
16526 return DAG.getBitcast(Op.getValueType(), Res);
16528 case CMP_MASK_SCALAR_CC: {
16529 SDValue Src1 = Op.getOperand(1);
16530 SDValue Src2 = Op.getOperand(2);
16531 SDValue CC = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op.getOperand(3));
16532 SDValue Mask = Op.getOperand(4);
16535 if (IntrData->Opc1 != 0) {
16536 SDValue Rnd = Op.getOperand(5);
16537 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
16538 X86::STATIC_ROUNDING::CUR_DIRECTION)
16539 Cmp = DAG.getNode(IntrData->Opc1, dl, MVT::i1, Src1, Src2, CC, Rnd);
16541 //default rounding mode
16543 Cmp = DAG.getNode(IntrData->Opc0, dl, MVT::i1, Src1, Src2, CC);
16545 SDValue CmpMask = getScalarMaskingNode(Cmp, Mask,
16546 DAG.getTargetConstant(0, dl,
16550 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::i8,
16551 DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i8, CmpMask),
16552 DAG.getValueType(MVT::i1));
16554 case COMI: { // Comparison intrinsics
16555 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
16556 SDValue LHS = Op.getOperand(1);
16557 SDValue RHS = Op.getOperand(2);
16558 unsigned X86CC = TranslateX86CC(CC, dl, true, LHS, RHS, DAG);
16559 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
16560 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
16561 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16562 DAG.getConstant(X86CC, dl, MVT::i8), Cond);
16563 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16565 case COMI_RM: { // Comparison intrinsics with Sae
16566 SDValue LHS = Op.getOperand(1);
16567 SDValue RHS = Op.getOperand(2);
16568 SDValue CC = Op.getOperand(3);
16569 SDValue Sae = Op.getOperand(4);
16570 auto ComiType = TranslateX86ConstCondToX86CC(CC);
16571 // choose between ordered and unordered (comi/ucomi)
16572 unsigned comiOp = std::get<0>(ComiType) ? IntrData->Opc0 : IntrData->Opc1;
16574 if (cast<ConstantSDNode>(Sae)->getZExtValue() !=
16575 X86::STATIC_ROUNDING::CUR_DIRECTION)
16576 Cond = DAG.getNode(comiOp, dl, MVT::i32, LHS, RHS, Sae);
16578 Cond = DAG.getNode(comiOp, dl, MVT::i32, LHS, RHS);
16579 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16580 DAG.getConstant(std::get<1>(ComiType), dl, MVT::i8), Cond);
16581 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16584 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
16585 Op.getOperand(1), Op.getOperand(2), DAG);
16587 return getVectorMaskingNode(getTargetVShiftNode(IntrData->Opc0, dl,
16588 Op.getSimpleValueType(),
16590 Op.getOperand(2), DAG),
16591 Op.getOperand(4), Op.getOperand(3), Subtarget,
16593 case COMPRESS_EXPAND_IN_REG: {
16594 SDValue Mask = Op.getOperand(3);
16595 SDValue DataToCompress = Op.getOperand(1);
16596 SDValue PassThru = Op.getOperand(2);
16597 if (isAllOnesConstant(Mask)) // return data as is
16598 return Op.getOperand(1);
16600 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16602 Mask, PassThru, Subtarget, DAG);
16605 SDValue Mask = Op.getOperand(1);
16606 MVT MaskVT = MVT::getVectorVT(MVT::i1, Mask.getSimpleValueType().getSizeInBits());
16607 Mask = DAG.getBitcast(MaskVT, Mask);
16608 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Mask);
16611 SDValue Mask = Op.getOperand(3);
16612 MVT VT = Op.getSimpleValueType();
16613 MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
16614 SDValue VMask = getMaskNode(Mask, MaskVT, Subtarget, DAG, dl);
16615 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, Op.getOperand(1),
16619 MVT VT = Op.getSimpleValueType();
16620 MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getSizeInBits()/2);
16622 SDValue Src1 = getMaskNode(Op.getOperand(1), MaskVT, Subtarget, DAG, dl);
16623 SDValue Src2 = getMaskNode(Op.getOperand(2), MaskVT, Subtarget, DAG, dl);
16624 // Arguments should be swapped.
16625 SDValue Res = DAG.getNode(IntrData->Opc0, dl,
16626 MVT::getVectorVT(MVT::i1, VT.getSizeInBits()),
16628 return DAG.getBitcast(VT, Res);
16636 default: return SDValue(); // Don't custom lower most intrinsics.
16638 case Intrinsic::x86_avx2_permd:
16639 case Intrinsic::x86_avx2_permps:
16640 // Operands intentionally swapped. Mask is last operand to intrinsic,
16641 // but second operand for node/instruction.
16642 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
16643 Op.getOperand(2), Op.getOperand(1));
16645 // ptest and testp intrinsics. The intrinsic these come from are designed to
16646 // return an integer value, not just an instruction so lower it to the ptest
16647 // or testp pattern and a setcc for the result.
16648 case Intrinsic::x86_sse41_ptestz:
16649 case Intrinsic::x86_sse41_ptestc:
16650 case Intrinsic::x86_sse41_ptestnzc:
16651 case Intrinsic::x86_avx_ptestz_256:
16652 case Intrinsic::x86_avx_ptestc_256:
16653 case Intrinsic::x86_avx_ptestnzc_256:
16654 case Intrinsic::x86_avx_vtestz_ps:
16655 case Intrinsic::x86_avx_vtestc_ps:
16656 case Intrinsic::x86_avx_vtestnzc_ps:
16657 case Intrinsic::x86_avx_vtestz_pd:
16658 case Intrinsic::x86_avx_vtestc_pd:
16659 case Intrinsic::x86_avx_vtestnzc_pd:
16660 case Intrinsic::x86_avx_vtestz_ps_256:
16661 case Intrinsic::x86_avx_vtestc_ps_256:
16662 case Intrinsic::x86_avx_vtestnzc_ps_256:
16663 case Intrinsic::x86_avx_vtestz_pd_256:
16664 case Intrinsic::x86_avx_vtestc_pd_256:
16665 case Intrinsic::x86_avx_vtestnzc_pd_256: {
16666 bool IsTestPacked = false;
16669 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
16670 case Intrinsic::x86_avx_vtestz_ps:
16671 case Intrinsic::x86_avx_vtestz_pd:
16672 case Intrinsic::x86_avx_vtestz_ps_256:
16673 case Intrinsic::x86_avx_vtestz_pd_256:
16674 IsTestPacked = true; // Fallthrough
16675 case Intrinsic::x86_sse41_ptestz:
16676 case Intrinsic::x86_avx_ptestz_256:
16678 X86CC = X86::COND_E;
16680 case Intrinsic::x86_avx_vtestc_ps:
16681 case Intrinsic::x86_avx_vtestc_pd:
16682 case Intrinsic::x86_avx_vtestc_ps_256:
16683 case Intrinsic::x86_avx_vtestc_pd_256:
16684 IsTestPacked = true; // Fallthrough
16685 case Intrinsic::x86_sse41_ptestc:
16686 case Intrinsic::x86_avx_ptestc_256:
16688 X86CC = X86::COND_B;
16690 case Intrinsic::x86_avx_vtestnzc_ps:
16691 case Intrinsic::x86_avx_vtestnzc_pd:
16692 case Intrinsic::x86_avx_vtestnzc_ps_256:
16693 case Intrinsic::x86_avx_vtestnzc_pd_256:
16694 IsTestPacked = true; // Fallthrough
16695 case Intrinsic::x86_sse41_ptestnzc:
16696 case Intrinsic::x86_avx_ptestnzc_256:
16698 X86CC = X86::COND_A;
16702 SDValue LHS = Op.getOperand(1);
16703 SDValue RHS = Op.getOperand(2);
16704 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
16705 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
16706 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
16707 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
16708 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16710 case Intrinsic::x86_avx512_kortestz_w:
16711 case Intrinsic::x86_avx512_kortestc_w: {
16712 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
16713 SDValue LHS = DAG.getBitcast(MVT::v16i1, Op.getOperand(1));
16714 SDValue RHS = DAG.getBitcast(MVT::v16i1, Op.getOperand(2));
16715 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
16716 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
16717 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
16718 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16721 case Intrinsic::x86_sse42_pcmpistria128:
16722 case Intrinsic::x86_sse42_pcmpestria128:
16723 case Intrinsic::x86_sse42_pcmpistric128:
16724 case Intrinsic::x86_sse42_pcmpestric128:
16725 case Intrinsic::x86_sse42_pcmpistrio128:
16726 case Intrinsic::x86_sse42_pcmpestrio128:
16727 case Intrinsic::x86_sse42_pcmpistris128:
16728 case Intrinsic::x86_sse42_pcmpestris128:
16729 case Intrinsic::x86_sse42_pcmpistriz128:
16730 case Intrinsic::x86_sse42_pcmpestriz128: {
16734 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16735 case Intrinsic::x86_sse42_pcmpistria128:
16736 Opcode = X86ISD::PCMPISTRI;
16737 X86CC = X86::COND_A;
16739 case Intrinsic::x86_sse42_pcmpestria128:
16740 Opcode = X86ISD::PCMPESTRI;
16741 X86CC = X86::COND_A;
16743 case Intrinsic::x86_sse42_pcmpistric128:
16744 Opcode = X86ISD::PCMPISTRI;
16745 X86CC = X86::COND_B;
16747 case Intrinsic::x86_sse42_pcmpestric128:
16748 Opcode = X86ISD::PCMPESTRI;
16749 X86CC = X86::COND_B;
16751 case Intrinsic::x86_sse42_pcmpistrio128:
16752 Opcode = X86ISD::PCMPISTRI;
16753 X86CC = X86::COND_O;
16755 case Intrinsic::x86_sse42_pcmpestrio128:
16756 Opcode = X86ISD::PCMPESTRI;
16757 X86CC = X86::COND_O;
16759 case Intrinsic::x86_sse42_pcmpistris128:
16760 Opcode = X86ISD::PCMPISTRI;
16761 X86CC = X86::COND_S;
16763 case Intrinsic::x86_sse42_pcmpestris128:
16764 Opcode = X86ISD::PCMPESTRI;
16765 X86CC = X86::COND_S;
16767 case Intrinsic::x86_sse42_pcmpistriz128:
16768 Opcode = X86ISD::PCMPISTRI;
16769 X86CC = X86::COND_E;
16771 case Intrinsic::x86_sse42_pcmpestriz128:
16772 Opcode = X86ISD::PCMPESTRI;
16773 X86CC = X86::COND_E;
16776 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
16777 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
16778 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
16779 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16780 DAG.getConstant(X86CC, dl, MVT::i8),
16781 SDValue(PCMP.getNode(), 1));
16782 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16785 case Intrinsic::x86_sse42_pcmpistri128:
16786 case Intrinsic::x86_sse42_pcmpestri128: {
16788 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
16789 Opcode = X86ISD::PCMPISTRI;
16791 Opcode = X86ISD::PCMPESTRI;
16793 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
16794 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
16795 return DAG.getNode(Opcode, dl, VTs, NewOps);
16798 case Intrinsic::x86_seh_lsda: {
16799 // Compute the symbol for the LSDA. We know it'll get emitted later.
16800 MachineFunction &MF = DAG.getMachineFunction();
16801 SDValue Op1 = Op.getOperand(1);
16802 auto *Fn = cast<Function>(cast<GlobalAddressSDNode>(Op1)->getGlobal());
16803 MCSymbol *LSDASym = MF.getMMI().getContext().getOrCreateLSDASymbol(
16804 GlobalValue::getRealLinkageName(Fn->getName()));
16806 // Generate a simple absolute symbol reference. This intrinsic is only
16807 // supported on 32-bit Windows, which isn't PIC.
16808 SDValue Result = DAG.getMCSymbol(LSDASym, VT);
16809 return DAG.getNode(X86ISD::Wrapper, dl, VT, Result);
16812 case Intrinsic::x86_seh_recoverfp: {
16813 SDValue FnOp = Op.getOperand(1);
16814 SDValue IncomingFPOp = Op.getOperand(2);
16815 GlobalAddressSDNode *GSD = dyn_cast<GlobalAddressSDNode>(FnOp);
16816 auto *Fn = dyn_cast_or_null<Function>(GSD ? GSD->getGlobal() : nullptr);
16818 report_fatal_error(
16819 "llvm.x86.seh.recoverfp must take a function as the first argument");
16820 return recoverFramePointer(DAG, Fn, IncomingFPOp);
16823 case Intrinsic::localaddress: {
16824 // Returns one of the stack, base, or frame pointer registers, depending on
16825 // which is used to reference local variables.
16826 MachineFunction &MF = DAG.getMachineFunction();
16827 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
16829 if (RegInfo->hasBasePointer(MF))
16830 Reg = RegInfo->getBaseRegister();
16831 else // This function handles the SP or FP case.
16832 Reg = RegInfo->getPtrSizedFrameRegister(MF);
16833 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
16838 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16839 SDValue Src, SDValue Mask, SDValue Base,
16840 SDValue Index, SDValue ScaleOp, SDValue Chain,
16841 const X86Subtarget * Subtarget) {
16843 auto *C = cast<ConstantSDNode>(ScaleOp);
16844 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
16845 MVT MaskVT = MVT::getVectorVT(MVT::i1,
16846 Index.getSimpleValueType().getVectorNumElements());
16848 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16850 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
16852 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
16853 Mask.getSimpleValueType().getSizeInBits());
16855 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16856 // are extracted by EXTRACT_SUBVECTOR.
16857 MaskInReg = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16858 DAG.getBitcast(BitcastVT, Mask),
16859 DAG.getIntPtrConstant(0, dl));
16861 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
16862 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
16863 SDValue Segment = DAG.getRegister(0, MVT::i32);
16864 if (Src.getOpcode() == ISD::UNDEF)
16865 Src = getZeroVector(Op.getSimpleValueType(), Subtarget, DAG, dl);
16866 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16867 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16868 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
16869 return DAG.getMergeValues(RetOps, dl);
16872 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16873 SDValue Src, SDValue Mask, SDValue Base,
16874 SDValue Index, SDValue ScaleOp, SDValue Chain) {
16876 auto *C = cast<ConstantSDNode>(ScaleOp);
16877 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
16878 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
16879 SDValue Segment = DAG.getRegister(0, MVT::i32);
16880 MVT MaskVT = MVT::getVectorVT(MVT::i1,
16881 Index.getSimpleValueType().getVectorNumElements());
16883 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16885 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
16887 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
16888 Mask.getSimpleValueType().getSizeInBits());
16890 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16891 // are extracted by EXTRACT_SUBVECTOR.
16892 MaskInReg = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16893 DAG.getBitcast(BitcastVT, Mask),
16894 DAG.getIntPtrConstant(0, dl));
16896 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
16897 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
16898 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16899 return SDValue(Res, 1);
16902 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16903 SDValue Mask, SDValue Base, SDValue Index,
16904 SDValue ScaleOp, SDValue Chain) {
16906 auto *C = cast<ConstantSDNode>(ScaleOp);
16907 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
16908 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
16909 SDValue Segment = DAG.getRegister(0, MVT::i32);
16911 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
16913 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16915 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
16917 MaskInReg = DAG.getBitcast(MaskVT, Mask);
16918 //SDVTList VTs = DAG.getVTList(MVT::Other);
16919 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16920 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
16921 return SDValue(Res, 0);
16924 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
16925 // read performance monitor counters (x86_rdpmc).
16926 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
16927 SelectionDAG &DAG, const X86Subtarget *Subtarget,
16928 SmallVectorImpl<SDValue> &Results) {
16929 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
16930 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16933 // The ECX register is used to select the index of the performance counter
16935 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
16937 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
16939 // Reads the content of a 64-bit performance counter and returns it in the
16940 // registers EDX:EAX.
16941 if (Subtarget->is64Bit()) {
16942 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
16943 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
16946 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
16947 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
16950 Chain = HI.getValue(1);
16952 if (Subtarget->is64Bit()) {
16953 // The EAX register is loaded with the low-order 32 bits. The EDX register
16954 // is loaded with the supported high-order bits of the counter.
16955 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
16956 DAG.getConstant(32, DL, MVT::i8));
16957 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
16958 Results.push_back(Chain);
16962 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
16963 SDValue Ops[] = { LO, HI };
16964 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
16965 Results.push_back(Pair);
16966 Results.push_back(Chain);
16969 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
16970 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
16971 // also used to custom lower READCYCLECOUNTER nodes.
16972 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
16973 SelectionDAG &DAG, const X86Subtarget *Subtarget,
16974 SmallVectorImpl<SDValue> &Results) {
16975 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16976 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
16979 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
16980 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
16981 // and the EAX register is loaded with the low-order 32 bits.
16982 if (Subtarget->is64Bit()) {
16983 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
16984 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
16987 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
16988 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
16991 SDValue Chain = HI.getValue(1);
16993 if (Opcode == X86ISD::RDTSCP_DAG) {
16994 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
16996 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
16997 // the ECX register. Add 'ecx' explicitly to the chain.
16998 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
17000 // Explicitly store the content of ECX at the location passed in input
17001 // to the 'rdtscp' intrinsic.
17002 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
17003 MachinePointerInfo(), false, false, 0);
17006 if (Subtarget->is64Bit()) {
17007 // The EDX register is loaded with the high-order 32 bits of the MSR, and
17008 // the EAX register is loaded with the low-order 32 bits.
17009 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
17010 DAG.getConstant(32, DL, MVT::i8));
17011 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
17012 Results.push_back(Chain);
17016 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
17017 SDValue Ops[] = { LO, HI };
17018 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
17019 Results.push_back(Pair);
17020 Results.push_back(Chain);
17023 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
17024 SelectionDAG &DAG) {
17025 SmallVector<SDValue, 2> Results;
17027 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
17029 return DAG.getMergeValues(Results, DL);
17032 static SDValue LowerSEHRESTOREFRAME(SDValue Op, const X86Subtarget *Subtarget,
17033 SelectionDAG &DAG) {
17034 MachineFunction &MF = DAG.getMachineFunction();
17035 const Function *Fn = MF.getFunction();
17037 SDValue Chain = Op.getOperand(0);
17039 assert(Subtarget->getFrameLowering()->hasFP(MF) &&
17040 "using llvm.x86.seh.restoreframe requires a frame pointer");
17042 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17043 MVT VT = TLI.getPointerTy(DAG.getDataLayout());
17045 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17046 unsigned FrameReg =
17047 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
17048 unsigned SPReg = RegInfo->getStackRegister();
17049 unsigned SlotSize = RegInfo->getSlotSize();
17051 // Get incoming EBP.
17052 SDValue IncomingEBP =
17053 DAG.getCopyFromReg(Chain, dl, FrameReg, VT);
17055 // SP is saved in the first field of every registration node, so load
17056 // [EBP-RegNodeSize] into SP.
17057 int RegNodeSize = getSEHRegistrationNodeSize(Fn);
17058 SDValue SPAddr = DAG.getNode(ISD::ADD, dl, VT, IncomingEBP,
17059 DAG.getConstant(-RegNodeSize, dl, VT));
17061 DAG.getLoad(VT, dl, Chain, SPAddr, MachinePointerInfo(), false, false,
17062 false, VT.getScalarSizeInBits() / 8);
17063 Chain = DAG.getCopyToReg(Chain, dl, SPReg, NewSP);
17065 if (!RegInfo->needsStackRealignment(MF)) {
17066 // Adjust EBP to point back to the original frame position.
17067 SDValue NewFP = recoverFramePointer(DAG, Fn, IncomingEBP);
17068 Chain = DAG.getCopyToReg(Chain, dl, FrameReg, NewFP);
17070 assert(RegInfo->hasBasePointer(MF) &&
17071 "functions with Win32 EH must use frame or base pointer register");
17073 // Reload the base pointer (ESI) with the adjusted incoming EBP.
17074 SDValue NewBP = recoverFramePointer(DAG, Fn, IncomingEBP);
17075 Chain = DAG.getCopyToReg(Chain, dl, RegInfo->getBaseRegister(), NewBP);
17077 // Reload the spilled EBP value, now that the stack and base pointers are
17079 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
17080 X86FI->setHasSEHFramePtrSave(true);
17081 int FI = MF.getFrameInfo()->CreateSpillStackObject(SlotSize, SlotSize);
17082 X86FI->setSEHFramePtrSaveIndex(FI);
17083 SDValue NewFP = DAG.getLoad(VT, dl, Chain, DAG.getFrameIndex(FI, VT),
17084 MachinePointerInfo(), false, false, false,
17085 VT.getScalarSizeInBits() / 8);
17086 Chain = DAG.getCopyToReg(NewFP, dl, FrameReg, NewFP);
17092 static SDValue MarkEHRegistrationNode(SDValue Op, SelectionDAG &DAG) {
17093 MachineFunction &MF = DAG.getMachineFunction();
17094 SDValue Chain = Op.getOperand(0);
17095 SDValue RegNode = Op.getOperand(2);
17096 WinEHFuncInfo *EHInfo = MF.getWinEHFuncInfo();
17098 report_fatal_error("EH registrations only live in functions using WinEH");
17100 // Cast the operand to an alloca, and remember the frame index.
17101 auto *FINode = dyn_cast<FrameIndexSDNode>(RegNode);
17103 report_fatal_error("llvm.x86.seh.ehregnode expects a static alloca");
17104 EHInfo->EHRegNodeFrameIndex = FINode->getIndex();
17106 // Return the chain operand without making any DAG nodes.
17110 /// \brief Lower intrinsics for TRUNCATE_TO_MEM case
17111 /// return truncate Store/MaskedStore Node
17112 static SDValue LowerINTRINSIC_TRUNCATE_TO_MEM(const SDValue & Op,
17116 SDValue Mask = Op.getOperand(4);
17117 SDValue DataToTruncate = Op.getOperand(3);
17118 SDValue Addr = Op.getOperand(2);
17119 SDValue Chain = Op.getOperand(0);
17121 MVT VT = DataToTruncate.getSimpleValueType();
17122 MVT SVT = MVT::getVectorVT(ElementType, VT.getVectorNumElements());
17124 if (isAllOnesConstant(Mask)) // return just a truncate store
17125 return DAG.getTruncStore(Chain, dl, DataToTruncate, Addr,
17126 MachinePointerInfo(), SVT, false, false,
17127 SVT.getScalarSizeInBits()/8);
17129 MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
17130 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
17131 Mask.getSimpleValueType().getSizeInBits());
17132 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
17133 // are extracted by EXTRACT_SUBVECTOR.
17134 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
17135 DAG.getBitcast(BitcastVT, Mask),
17136 DAG.getIntPtrConstant(0, dl));
17138 MachineMemOperand *MMO = DAG.getMachineFunction().
17139 getMachineMemOperand(MachinePointerInfo(),
17140 MachineMemOperand::MOStore, SVT.getStoreSize(),
17141 SVT.getScalarSizeInBits()/8);
17143 return DAG.getMaskedStore(Chain, dl, DataToTruncate, Addr,
17144 VMask, SVT, MMO, true);
17147 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
17148 SelectionDAG &DAG) {
17149 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
17151 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
17153 if (IntNo == llvm::Intrinsic::x86_seh_restoreframe)
17154 return LowerSEHRESTOREFRAME(Op, Subtarget, DAG);
17155 else if (IntNo == llvm::Intrinsic::x86_seh_ehregnode)
17156 return MarkEHRegistrationNode(Op, DAG);
17161 switch(IntrData->Type) {
17162 default: llvm_unreachable("Unknown Intrinsic Type");
17165 // Emit the node with the right value type.
17166 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
17167 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17169 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
17170 // Otherwise return the value from Rand, which is always 0, casted to i32.
17171 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
17172 DAG.getConstant(1, dl, Op->getValueType(1)),
17173 DAG.getConstant(X86::COND_B, dl, MVT::i32),
17174 SDValue(Result.getNode(), 1) };
17175 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
17176 DAG.getVTList(Op->getValueType(1), MVT::Glue),
17179 // Return { result, isValid, chain }.
17180 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
17181 SDValue(Result.getNode(), 2));
17184 //gather(v1, mask, index, base, scale);
17185 SDValue Chain = Op.getOperand(0);
17186 SDValue Src = Op.getOperand(2);
17187 SDValue Base = Op.getOperand(3);
17188 SDValue Index = Op.getOperand(4);
17189 SDValue Mask = Op.getOperand(5);
17190 SDValue Scale = Op.getOperand(6);
17191 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale,
17195 //scatter(base, mask, index, v1, scale);
17196 SDValue Chain = Op.getOperand(0);
17197 SDValue Base = Op.getOperand(2);
17198 SDValue Mask = Op.getOperand(3);
17199 SDValue Index = Op.getOperand(4);
17200 SDValue Src = Op.getOperand(5);
17201 SDValue Scale = Op.getOperand(6);
17202 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index,
17206 SDValue Hint = Op.getOperand(6);
17207 unsigned HintVal = cast<ConstantSDNode>(Hint)->getZExtValue();
17208 assert(HintVal < 2 && "Wrong prefetch hint in intrinsic: should be 0 or 1");
17209 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
17210 SDValue Chain = Op.getOperand(0);
17211 SDValue Mask = Op.getOperand(2);
17212 SDValue Index = Op.getOperand(3);
17213 SDValue Base = Op.getOperand(4);
17214 SDValue Scale = Op.getOperand(5);
17215 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
17217 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
17219 SmallVector<SDValue, 2> Results;
17220 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget,
17222 return DAG.getMergeValues(Results, dl);
17224 // Read Performance Monitoring Counters.
17226 SmallVector<SDValue, 2> Results;
17227 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
17228 return DAG.getMergeValues(Results, dl);
17230 // XTEST intrinsics.
17232 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17233 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17234 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17235 DAG.getConstant(X86::COND_NE, dl, MVT::i8),
17237 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
17238 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
17239 Ret, SDValue(InTrans.getNode(), 1));
17243 SmallVector<SDValue, 2> Results;
17244 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17245 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
17246 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
17247 DAG.getConstant(-1, dl, MVT::i8));
17248 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
17249 Op.getOperand(4), GenCF.getValue(1));
17250 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
17251 Op.getOperand(5), MachinePointerInfo(),
17253 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17254 DAG.getConstant(X86::COND_B, dl, MVT::i8),
17256 Results.push_back(SetCC);
17257 Results.push_back(Store);
17258 return DAG.getMergeValues(Results, dl);
17260 case COMPRESS_TO_MEM: {
17262 SDValue Mask = Op.getOperand(4);
17263 SDValue DataToCompress = Op.getOperand(3);
17264 SDValue Addr = Op.getOperand(2);
17265 SDValue Chain = Op.getOperand(0);
17267 MVT VT = DataToCompress.getSimpleValueType();
17268 if (isAllOnesConstant(Mask)) // return just a store
17269 return DAG.getStore(Chain, dl, DataToCompress, Addr,
17270 MachinePointerInfo(), false, false,
17271 VT.getScalarSizeInBits()/8);
17273 SDValue Compressed =
17274 getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, DataToCompress),
17275 Mask, DAG.getUNDEF(VT), Subtarget, DAG);
17276 return DAG.getStore(Chain, dl, Compressed, Addr,
17277 MachinePointerInfo(), false, false,
17278 VT.getScalarSizeInBits()/8);
17280 case TRUNCATE_TO_MEM_VI8:
17281 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i8);
17282 case TRUNCATE_TO_MEM_VI16:
17283 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i16);
17284 case TRUNCATE_TO_MEM_VI32:
17285 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i32);
17286 case EXPAND_FROM_MEM: {
17288 SDValue Mask = Op.getOperand(4);
17289 SDValue PassThru = Op.getOperand(3);
17290 SDValue Addr = Op.getOperand(2);
17291 SDValue Chain = Op.getOperand(0);
17292 MVT VT = Op.getSimpleValueType();
17294 if (isAllOnesConstant(Mask)) // return just a load
17295 return DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(), false, false,
17296 false, VT.getScalarSizeInBits()/8);
17298 SDValue DataToExpand = DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(),
17299 false, false, false,
17300 VT.getScalarSizeInBits()/8);
17302 SDValue Results[] = {
17303 getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, DataToExpand),
17304 Mask, PassThru, Subtarget, DAG), Chain};
17305 return DAG.getMergeValues(Results, dl);
17310 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
17311 SelectionDAG &DAG) const {
17312 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
17313 MFI->setReturnAddressIsTaken(true);
17315 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
17318 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17320 EVT PtrVT = getPointerTy(DAG.getDataLayout());
17323 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
17324 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17325 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), dl, PtrVT);
17326 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17327 DAG.getNode(ISD::ADD, dl, PtrVT,
17328 FrameAddr, Offset),
17329 MachinePointerInfo(), false, false, false, 0);
17332 // Just load the return address.
17333 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
17334 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17335 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
17338 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
17339 MachineFunction &MF = DAG.getMachineFunction();
17340 MachineFrameInfo *MFI = MF.getFrameInfo();
17341 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
17342 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17343 EVT VT = Op.getValueType();
17345 MFI->setFrameAddressIsTaken(true);
17347 if (MF.getTarget().getMCAsmInfo()->usesWindowsCFI()) {
17348 // Depth > 0 makes no sense on targets which use Windows unwind codes. It
17349 // is not possible to crawl up the stack without looking at the unwind codes
17351 int FrameAddrIndex = FuncInfo->getFAIndex();
17352 if (!FrameAddrIndex) {
17353 // Set up a frame object for the return address.
17354 unsigned SlotSize = RegInfo->getSlotSize();
17355 FrameAddrIndex = MF.getFrameInfo()->CreateFixedObject(
17356 SlotSize, /*Offset=*/0, /*IsImmutable=*/false);
17357 FuncInfo->setFAIndex(FrameAddrIndex);
17359 return DAG.getFrameIndex(FrameAddrIndex, VT);
17362 unsigned FrameReg =
17363 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
17364 SDLoc dl(Op); // FIXME probably not meaningful
17365 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17366 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
17367 (FrameReg == X86::EBP && VT == MVT::i32)) &&
17368 "Invalid Frame Register!");
17369 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
17371 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
17372 MachinePointerInfo(),
17373 false, false, false, 0);
17377 // FIXME? Maybe this could be a TableGen attribute on some registers and
17378 // this table could be generated automatically from RegInfo.
17379 unsigned X86TargetLowering::getRegisterByName(const char* RegName, EVT VT,
17380 SelectionDAG &DAG) const {
17381 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
17382 const MachineFunction &MF = DAG.getMachineFunction();
17384 unsigned Reg = StringSwitch<unsigned>(RegName)
17385 .Case("esp", X86::ESP)
17386 .Case("rsp", X86::RSP)
17387 .Case("ebp", X86::EBP)
17388 .Case("rbp", X86::RBP)
17391 if (Reg == X86::EBP || Reg == X86::RBP) {
17392 if (!TFI.hasFP(MF))
17393 report_fatal_error("register " + StringRef(RegName) +
17394 " is allocatable: function has no frame pointer");
17397 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17398 unsigned FrameReg =
17399 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
17400 assert((FrameReg == X86::EBP || FrameReg == X86::RBP) &&
17401 "Invalid Frame Register!");
17409 report_fatal_error("Invalid register name global variable");
17412 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
17413 SelectionDAG &DAG) const {
17414 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17415 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize(), SDLoc(Op));
17418 unsigned X86TargetLowering::getExceptionPointerRegister(
17419 const Constant *PersonalityFn) const {
17420 if (classifyEHPersonality(PersonalityFn) == EHPersonality::CoreCLR)
17421 return Subtarget->isTarget64BitLP64() ? X86::RDX : X86::EDX;
17423 return Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX;
17426 unsigned X86TargetLowering::getExceptionSelectorRegister(
17427 const Constant *PersonalityFn) const {
17428 // Funclet personalities don't use selectors (the runtime does the selection).
17429 assert(!isFuncletEHPersonality(classifyEHPersonality(PersonalityFn)));
17430 return Subtarget->isTarget64BitLP64() ? X86::RDX : X86::EDX;
17433 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
17434 SDValue Chain = Op.getOperand(0);
17435 SDValue Offset = Op.getOperand(1);
17436 SDValue Handler = Op.getOperand(2);
17439 EVT PtrVT = getPointerTy(DAG.getDataLayout());
17440 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17441 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
17442 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
17443 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
17444 "Invalid Frame Register!");
17445 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
17446 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
17448 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
17449 DAG.getIntPtrConstant(RegInfo->getSlotSize(),
17451 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
17452 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
17454 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
17456 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
17457 DAG.getRegister(StoreAddrReg, PtrVT));
17460 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
17461 SelectionDAG &DAG) const {
17463 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
17464 DAG.getVTList(MVT::i32, MVT::Other),
17465 Op.getOperand(0), Op.getOperand(1));
17468 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
17469 SelectionDAG &DAG) const {
17471 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
17472 Op.getOperand(0), Op.getOperand(1));
17475 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
17476 return Op.getOperand(0);
17479 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
17480 SelectionDAG &DAG) const {
17481 SDValue Root = Op.getOperand(0);
17482 SDValue Trmp = Op.getOperand(1); // trampoline
17483 SDValue FPtr = Op.getOperand(2); // nested function
17484 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
17487 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
17488 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
17490 if (Subtarget->is64Bit()) {
17491 SDValue OutChains[6];
17493 // Large code-model.
17494 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
17495 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
17497 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
17498 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
17500 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
17502 // Load the pointer to the nested function into R11.
17503 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
17504 SDValue Addr = Trmp;
17505 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
17506 Addr, MachinePointerInfo(TrmpAddr),
17509 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17510 DAG.getConstant(2, dl, MVT::i64));
17511 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
17512 MachinePointerInfo(TrmpAddr, 2),
17515 // Load the 'nest' parameter value into R10.
17516 // R10 is specified in X86CallingConv.td
17517 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
17518 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17519 DAG.getConstant(10, dl, MVT::i64));
17520 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
17521 Addr, MachinePointerInfo(TrmpAddr, 10),
17524 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17525 DAG.getConstant(12, dl, MVT::i64));
17526 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
17527 MachinePointerInfo(TrmpAddr, 12),
17530 // Jump to the nested function.
17531 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
17532 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17533 DAG.getConstant(20, dl, MVT::i64));
17534 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
17535 Addr, MachinePointerInfo(TrmpAddr, 20),
17538 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
17539 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17540 DAG.getConstant(22, dl, MVT::i64));
17541 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, dl, MVT::i8),
17542 Addr, MachinePointerInfo(TrmpAddr, 22),
17545 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17547 const Function *Func =
17548 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
17549 CallingConv::ID CC = Func->getCallingConv();
17554 llvm_unreachable("Unsupported calling convention");
17555 case CallingConv::C:
17556 case CallingConv::X86_StdCall: {
17557 // Pass 'nest' parameter in ECX.
17558 // Must be kept in sync with X86CallingConv.td
17559 NestReg = X86::ECX;
17561 // Check that ECX wasn't needed by an 'inreg' parameter.
17562 FunctionType *FTy = Func->getFunctionType();
17563 const AttributeSet &Attrs = Func->getAttributes();
17565 if (!Attrs.isEmpty() && !Func->isVarArg()) {
17566 unsigned InRegCount = 0;
17569 for (FunctionType::param_iterator I = FTy->param_begin(),
17570 E = FTy->param_end(); I != E; ++I, ++Idx)
17571 if (Attrs.hasAttribute(Idx, Attribute::InReg)) {
17572 auto &DL = DAG.getDataLayout();
17573 // FIXME: should only count parameters that are lowered to integers.
17574 InRegCount += (DL.getTypeSizeInBits(*I) + 31) / 32;
17577 if (InRegCount > 2) {
17578 report_fatal_error("Nest register in use - reduce number of inreg"
17584 case CallingConv::X86_FastCall:
17585 case CallingConv::X86_ThisCall:
17586 case CallingConv::Fast:
17587 // Pass 'nest' parameter in EAX.
17588 // Must be kept in sync with X86CallingConv.td
17589 NestReg = X86::EAX;
17593 SDValue OutChains[4];
17594 SDValue Addr, Disp;
17596 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17597 DAG.getConstant(10, dl, MVT::i32));
17598 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
17600 // This is storing the opcode for MOV32ri.
17601 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
17602 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
17603 OutChains[0] = DAG.getStore(Root, dl,
17604 DAG.getConstant(MOV32ri|N86Reg, dl, MVT::i8),
17605 Trmp, MachinePointerInfo(TrmpAddr),
17608 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17609 DAG.getConstant(1, dl, MVT::i32));
17610 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
17611 MachinePointerInfo(TrmpAddr, 1),
17614 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
17615 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17616 DAG.getConstant(5, dl, MVT::i32));
17617 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, dl, MVT::i8),
17618 Addr, MachinePointerInfo(TrmpAddr, 5),
17621 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17622 DAG.getConstant(6, dl, MVT::i32));
17623 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
17624 MachinePointerInfo(TrmpAddr, 6),
17627 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17631 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
17632 SelectionDAG &DAG) const {
17634 The rounding mode is in bits 11:10 of FPSR, and has the following
17636 00 Round to nearest
17641 FLT_ROUNDS, on the other hand, expects the following:
17648 To perform the conversion, we do:
17649 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
17652 MachineFunction &MF = DAG.getMachineFunction();
17653 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
17654 unsigned StackAlignment = TFI.getStackAlignment();
17655 MVT VT = Op.getSimpleValueType();
17658 // Save FP Control Word to stack slot
17659 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
17660 SDValue StackSlot =
17661 DAG.getFrameIndex(SSFI, getPointerTy(DAG.getDataLayout()));
17663 MachineMemOperand *MMO =
17664 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
17665 MachineMemOperand::MOStore, 2, 2);
17667 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
17668 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
17669 DAG.getVTList(MVT::Other),
17670 Ops, MVT::i16, MMO);
17672 // Load FP Control Word from stack slot
17673 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
17674 MachinePointerInfo(), false, false, false, 0);
17676 // Transform as necessary
17678 DAG.getNode(ISD::SRL, DL, MVT::i16,
17679 DAG.getNode(ISD::AND, DL, MVT::i16,
17680 CWD, DAG.getConstant(0x800, DL, MVT::i16)),
17681 DAG.getConstant(11, DL, MVT::i8));
17683 DAG.getNode(ISD::SRL, DL, MVT::i16,
17684 DAG.getNode(ISD::AND, DL, MVT::i16,
17685 CWD, DAG.getConstant(0x400, DL, MVT::i16)),
17686 DAG.getConstant(9, DL, MVT::i8));
17689 DAG.getNode(ISD::AND, DL, MVT::i16,
17690 DAG.getNode(ISD::ADD, DL, MVT::i16,
17691 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
17692 DAG.getConstant(1, DL, MVT::i16)),
17693 DAG.getConstant(3, DL, MVT::i16));
17695 return DAG.getNode((VT.getSizeInBits() < 16 ?
17696 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
17699 /// \brief Lower a vector CTLZ using native supported vector CTLZ instruction.
17701 // 1. i32/i64 128/256-bit vector (native support require VLX) are expended
17702 // to 512-bit vector.
17703 // 2. i8/i16 vector implemented using dword LZCNT vector instruction
17704 // ( sub(trunc(lzcnt(zext32(x)))) ). In case zext32(x) is illegal,
17705 // split the vector, perform operation on it's Lo a Hi part and
17706 // concatenate the results.
17707 static SDValue LowerVectorCTLZ_AVX512(SDValue Op, SelectionDAG &DAG) {
17709 MVT VT = Op.getSimpleValueType();
17710 MVT EltVT = VT.getVectorElementType();
17711 unsigned NumElems = VT.getVectorNumElements();
17713 if (EltVT == MVT::i64 || EltVT == MVT::i32) {
17714 // Extend to 512 bit vector.
17715 assert((VT.is256BitVector() || VT.is128BitVector()) &&
17716 "Unsupported value type for operation");
17718 MVT NewVT = MVT::getVectorVT(EltVT, 512 / VT.getScalarSizeInBits());
17719 SDValue Vec512 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, NewVT,
17720 DAG.getUNDEF(NewVT),
17722 DAG.getIntPtrConstant(0, dl));
17723 SDValue CtlzNode = DAG.getNode(ISD::CTLZ, dl, NewVT, Vec512);
17725 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, CtlzNode,
17726 DAG.getIntPtrConstant(0, dl));
17729 assert((EltVT == MVT::i8 || EltVT == MVT::i16) &&
17730 "Unsupported element type");
17732 if (16 < NumElems) {
17733 // Split vector, it's Lo and Hi parts will be handled in next iteration.
17735 std::tie(Lo, Hi) = DAG.SplitVector(Op.getOperand(0), dl);
17736 MVT OutVT = MVT::getVectorVT(EltVT, NumElems/2);
17738 Lo = DAG.getNode(Op.getOpcode(), dl, OutVT, Lo);
17739 Hi = DAG.getNode(Op.getOpcode(), dl, OutVT, Hi);
17741 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Lo, Hi);
17744 MVT NewVT = MVT::getVectorVT(MVT::i32, NumElems);
17746 assert((NewVT.is256BitVector() || NewVT.is512BitVector()) &&
17747 "Unsupported value type for operation");
17749 // Use native supported vector instruction vplzcntd.
17750 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, NewVT, Op.getOperand(0));
17751 SDValue CtlzNode = DAG.getNode(ISD::CTLZ, dl, NewVT, Op);
17752 SDValue TruncNode = DAG.getNode(ISD::TRUNCATE, dl, VT, CtlzNode);
17753 SDValue Delta = DAG.getConstant(32 - EltVT.getSizeInBits(), dl, VT);
17755 return DAG.getNode(ISD::SUB, dl, VT, TruncNode, Delta);
17758 static SDValue LowerCTLZ(SDValue Op, const X86Subtarget *Subtarget,
17759 SelectionDAG &DAG) {
17760 MVT VT = Op.getSimpleValueType();
17762 unsigned NumBits = VT.getSizeInBits();
17765 if (VT.isVector() && Subtarget->hasAVX512())
17766 return LowerVectorCTLZ_AVX512(Op, DAG);
17768 Op = Op.getOperand(0);
17769 if (VT == MVT::i8) {
17770 // Zero extend to i32 since there is not an i8 bsr.
17772 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17775 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
17776 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17777 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17779 // If src is zero (i.e. bsr sets ZF), returns NumBits.
17782 DAG.getConstant(NumBits + NumBits - 1, dl, OpVT),
17783 DAG.getConstant(X86::COND_E, dl, MVT::i8),
17786 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
17788 // Finally xor with NumBits-1.
17789 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
17790 DAG.getConstant(NumBits - 1, dl, OpVT));
17793 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17797 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, const X86Subtarget *Subtarget,
17798 SelectionDAG &DAG) {
17799 MVT VT = Op.getSimpleValueType();
17801 unsigned NumBits = VT.getSizeInBits();
17804 if (VT.isVector() && Subtarget->hasAVX512())
17805 return LowerVectorCTLZ_AVX512(Op, DAG);
17807 Op = Op.getOperand(0);
17808 if (VT == MVT::i8) {
17809 // Zero extend to i32 since there is not an i8 bsr.
17811 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17814 // Issue a bsr (scan bits in reverse).
17815 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17816 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17818 // And xor with NumBits-1.
17819 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
17820 DAG.getConstant(NumBits - 1, dl, OpVT));
17823 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17827 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
17828 MVT VT = Op.getSimpleValueType();
17829 unsigned NumBits = VT.getScalarSizeInBits();
17832 if (VT.isVector()) {
17833 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17835 SDValue N0 = Op.getOperand(0);
17836 SDValue Zero = DAG.getConstant(0, dl, VT);
17838 // lsb(x) = (x & -x)
17839 SDValue LSB = DAG.getNode(ISD::AND, dl, VT, N0,
17840 DAG.getNode(ISD::SUB, dl, VT, Zero, N0));
17842 // cttz_undef(x) = (width - 1) - ctlz(lsb)
17843 if (Op.getOpcode() == ISD::CTTZ_ZERO_UNDEF &&
17844 TLI.isOperationLegal(ISD::CTLZ, VT)) {
17845 SDValue WidthMinusOne = DAG.getConstant(NumBits - 1, dl, VT);
17846 return DAG.getNode(ISD::SUB, dl, VT, WidthMinusOne,
17847 DAG.getNode(ISD::CTLZ, dl, VT, LSB));
17850 // cttz(x) = ctpop(lsb - 1)
17851 SDValue One = DAG.getConstant(1, dl, VT);
17852 return DAG.getNode(ISD::CTPOP, dl, VT,
17853 DAG.getNode(ISD::SUB, dl, VT, LSB, One));
17856 assert(Op.getOpcode() == ISD::CTTZ &&
17857 "Only scalar CTTZ requires custom lowering");
17859 // Issue a bsf (scan bits forward) which also sets EFLAGS.
17860 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
17861 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op.getOperand(0));
17863 // If src is zero (i.e. bsf sets ZF), returns NumBits.
17866 DAG.getConstant(NumBits, dl, VT),
17867 DAG.getConstant(X86::COND_E, dl, MVT::i8),
17870 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
17873 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
17874 // ones, and then concatenate the result back.
17875 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
17876 MVT VT = Op.getSimpleValueType();
17878 assert(VT.is256BitVector() && VT.isInteger() &&
17879 "Unsupported value type for operation");
17881 unsigned NumElems = VT.getVectorNumElements();
17884 // Extract the LHS vectors
17885 SDValue LHS = Op.getOperand(0);
17886 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
17887 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
17889 // Extract the RHS vectors
17890 SDValue RHS = Op.getOperand(1);
17891 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
17892 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
17894 MVT EltVT = VT.getVectorElementType();
17895 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17897 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
17898 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
17899 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
17902 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
17903 if (Op.getValueType() == MVT::i1)
17904 return DAG.getNode(ISD::XOR, SDLoc(Op), Op.getValueType(),
17905 Op.getOperand(0), Op.getOperand(1));
17906 assert(Op.getSimpleValueType().is256BitVector() &&
17907 Op.getSimpleValueType().isInteger() &&
17908 "Only handle AVX 256-bit vector integer operation");
17909 return Lower256IntArith(Op, DAG);
17912 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
17913 if (Op.getValueType() == MVT::i1)
17914 return DAG.getNode(ISD::XOR, SDLoc(Op), Op.getValueType(),
17915 Op.getOperand(0), Op.getOperand(1));
17916 assert(Op.getSimpleValueType().is256BitVector() &&
17917 Op.getSimpleValueType().isInteger() &&
17918 "Only handle AVX 256-bit vector integer operation");
17919 return Lower256IntArith(Op, DAG);
17922 static SDValue LowerMINMAX(SDValue Op, SelectionDAG &DAG) {
17923 assert(Op.getSimpleValueType().is256BitVector() &&
17924 Op.getSimpleValueType().isInteger() &&
17925 "Only handle AVX 256-bit vector integer operation");
17926 return Lower256IntArith(Op, DAG);
17929 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
17930 SelectionDAG &DAG) {
17932 MVT VT = Op.getSimpleValueType();
17935 return DAG.getNode(ISD::AND, dl, VT, Op.getOperand(0), Op.getOperand(1));
17937 // Decompose 256-bit ops into smaller 128-bit ops.
17938 if (VT.is256BitVector() && !Subtarget->hasInt256())
17939 return Lower256IntArith(Op, DAG);
17941 SDValue A = Op.getOperand(0);
17942 SDValue B = Op.getOperand(1);
17944 // Lower v16i8/v32i8 mul as promotion to v8i16/v16i16 vector
17945 // pairs, multiply and truncate.
17946 if (VT == MVT::v16i8 || VT == MVT::v32i8) {
17947 if (Subtarget->hasInt256()) {
17948 if (VT == MVT::v32i8) {
17949 MVT SubVT = MVT::getVectorVT(MVT::i8, VT.getVectorNumElements() / 2);
17950 SDValue Lo = DAG.getIntPtrConstant(0, dl);
17951 SDValue Hi = DAG.getIntPtrConstant(VT.getVectorNumElements() / 2, dl);
17952 SDValue ALo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Lo);
17953 SDValue BLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Lo);
17954 SDValue AHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Hi);
17955 SDValue BHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Hi);
17956 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
17957 DAG.getNode(ISD::MUL, dl, SubVT, ALo, BLo),
17958 DAG.getNode(ISD::MUL, dl, SubVT, AHi, BHi));
17961 MVT ExVT = MVT::getVectorVT(MVT::i16, VT.getVectorNumElements());
17962 return DAG.getNode(
17963 ISD::TRUNCATE, dl, VT,
17964 DAG.getNode(ISD::MUL, dl, ExVT,
17965 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, A),
17966 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, B)));
17969 assert(VT == MVT::v16i8 &&
17970 "Pre-AVX2 support only supports v16i8 multiplication");
17971 MVT ExVT = MVT::v8i16;
17973 // Extract the lo parts and sign extend to i16
17975 if (Subtarget->hasSSE41()) {
17976 ALo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, A);
17977 BLo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, B);
17979 const int ShufMask[] = {-1, 0, -1, 1, -1, 2, -1, 3,
17980 -1, 4, -1, 5, -1, 6, -1, 7};
17981 ALo = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
17982 BLo = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
17983 ALo = DAG.getBitcast(ExVT, ALo);
17984 BLo = DAG.getBitcast(ExVT, BLo);
17985 ALo = DAG.getNode(ISD::SRA, dl, ExVT, ALo, DAG.getConstant(8, dl, ExVT));
17986 BLo = DAG.getNode(ISD::SRA, dl, ExVT, BLo, DAG.getConstant(8, dl, ExVT));
17989 // Extract the hi parts and sign extend to i16
17991 if (Subtarget->hasSSE41()) {
17992 const int ShufMask[] = {8, 9, 10, 11, 12, 13, 14, 15,
17993 -1, -1, -1, -1, -1, -1, -1, -1};
17994 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
17995 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
17996 AHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, AHi);
17997 BHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, BHi);
17999 const int ShufMask[] = {-1, 8, -1, 9, -1, 10, -1, 11,
18000 -1, 12, -1, 13, -1, 14, -1, 15};
18001 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
18002 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
18003 AHi = DAG.getBitcast(ExVT, AHi);
18004 BHi = DAG.getBitcast(ExVT, BHi);
18005 AHi = DAG.getNode(ISD::SRA, dl, ExVT, AHi, DAG.getConstant(8, dl, ExVT));
18006 BHi = DAG.getNode(ISD::SRA, dl, ExVT, BHi, DAG.getConstant(8, dl, ExVT));
18009 // Multiply, mask the lower 8bits of the lo/hi results and pack
18010 SDValue RLo = DAG.getNode(ISD::MUL, dl, ExVT, ALo, BLo);
18011 SDValue RHi = DAG.getNode(ISD::MUL, dl, ExVT, AHi, BHi);
18012 RLo = DAG.getNode(ISD::AND, dl, ExVT, RLo, DAG.getConstant(255, dl, ExVT));
18013 RHi = DAG.getNode(ISD::AND, dl, ExVT, RHi, DAG.getConstant(255, dl, ExVT));
18014 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);
18017 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
18018 if (VT == MVT::v4i32) {
18019 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
18020 "Should not custom lower when pmuldq is available!");
18022 // Extract the odd parts.
18023 static const int UnpackMask[] = { 1, -1, 3, -1 };
18024 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
18025 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
18027 // Multiply the even parts.
18028 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
18029 // Now multiply odd parts.
18030 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
18032 Evens = DAG.getBitcast(VT, Evens);
18033 Odds = DAG.getBitcast(VT, Odds);
18035 // Merge the two vectors back together with a shuffle. This expands into 2
18037 static const int ShufMask[] = { 0, 4, 2, 6 };
18038 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
18041 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
18042 "Only know how to lower V2I64/V4I64/V8I64 multiply");
18044 // Ahi = psrlqi(a, 32);
18045 // Bhi = psrlqi(b, 32);
18047 // AloBlo = pmuludq(a, b);
18048 // AloBhi = pmuludq(a, Bhi);
18049 // AhiBlo = pmuludq(Ahi, b);
18051 // AloBhi = psllqi(AloBhi, 32);
18052 // AhiBlo = psllqi(AhiBlo, 32);
18053 // return AloBlo + AloBhi + AhiBlo;
18055 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
18056 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
18058 SDValue AhiBlo = Ahi;
18059 SDValue AloBhi = Bhi;
18060 // Bit cast to 32-bit vectors for MULUDQ
18061 MVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
18062 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
18063 A = DAG.getBitcast(MulVT, A);
18064 B = DAG.getBitcast(MulVT, B);
18065 Ahi = DAG.getBitcast(MulVT, Ahi);
18066 Bhi = DAG.getBitcast(MulVT, Bhi);
18068 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
18069 // After shifting right const values the result may be all-zero.
18070 if (!ISD::isBuildVectorAllZeros(Ahi.getNode())) {
18071 AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
18072 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
18074 if (!ISD::isBuildVectorAllZeros(Bhi.getNode())) {
18075 AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
18076 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
18079 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
18080 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
18083 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
18084 assert(Subtarget->isTargetWin64() && "Unexpected target");
18085 EVT VT = Op.getValueType();
18086 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
18087 "Unexpected return type for lowering");
18091 switch (Op->getOpcode()) {
18092 default: llvm_unreachable("Unexpected request for libcall!");
18093 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
18094 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
18095 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
18096 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
18097 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
18098 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
18102 SDValue InChain = DAG.getEntryNode();
18104 TargetLowering::ArgListTy Args;
18105 TargetLowering::ArgListEntry Entry;
18106 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
18107 EVT ArgVT = Op->getOperand(i).getValueType();
18108 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
18109 "Unexpected argument type for lowering");
18110 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
18111 Entry.Node = StackPtr;
18112 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
18114 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
18115 Entry.Ty = PointerType::get(ArgTy,0);
18116 Entry.isSExt = false;
18117 Entry.isZExt = false;
18118 Args.push_back(Entry);
18121 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
18122 getPointerTy(DAG.getDataLayout()));
18124 TargetLowering::CallLoweringInfo CLI(DAG);
18125 CLI.setDebugLoc(dl).setChain(InChain)
18126 .setCallee(getLibcallCallingConv(LC),
18127 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
18128 Callee, std::move(Args), 0)
18129 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
18131 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
18132 return DAG.getBitcast(VT, CallInfo.first);
18135 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
18136 SelectionDAG &DAG) {
18137 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
18138 MVT VT = Op0.getSimpleValueType();
18141 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
18142 (VT == MVT::v8i32 && Subtarget->hasInt256()));
18144 // PMULxD operations multiply each even value (starting at 0) of LHS with
18145 // the related value of RHS and produce a widen result.
18146 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
18147 // => <2 x i64> <ae|cg>
18149 // In other word, to have all the results, we need to perform two PMULxD:
18150 // 1. one with the even values.
18151 // 2. one with the odd values.
18152 // To achieve #2, with need to place the odd values at an even position.
18154 // Place the odd value at an even position (basically, shift all values 1
18155 // step to the left):
18156 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
18157 // <a|b|c|d> => <b|undef|d|undef>
18158 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
18159 // <e|f|g|h> => <f|undef|h|undef>
18160 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
18162 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
18164 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
18165 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
18167 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
18168 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
18169 // => <2 x i64> <ae|cg>
18170 SDValue Mul1 = DAG.getBitcast(VT, DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
18171 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
18172 // => <2 x i64> <bf|dh>
18173 SDValue Mul2 = DAG.getBitcast(VT, DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
18175 // Shuffle it back into the right order.
18176 SDValue Highs, Lows;
18177 if (VT == MVT::v8i32) {
18178 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
18179 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
18180 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
18181 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
18183 const int HighMask[] = {1, 5, 3, 7};
18184 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
18185 const int LowMask[] = {0, 4, 2, 6};
18186 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
18189 // If we have a signed multiply but no PMULDQ fix up the high parts of a
18190 // unsigned multiply.
18191 if (IsSigned && !Subtarget->hasSSE41()) {
18192 SDValue ShAmt = DAG.getConstant(
18194 DAG.getTargetLoweringInfo().getShiftAmountTy(VT, DAG.getDataLayout()));
18195 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
18196 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
18197 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
18198 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
18200 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
18201 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
18204 // The first result of MUL_LOHI is actually the low value, followed by the
18206 SDValue Ops[] = {Lows, Highs};
18207 return DAG.getMergeValues(Ops, dl);
18210 // Return true if the required (according to Opcode) shift-imm form is natively
18211 // supported by the Subtarget
18212 static bool SupportedVectorShiftWithImm(MVT VT, const X86Subtarget *Subtarget,
18214 if (VT.getScalarSizeInBits() < 16)
18217 if (VT.is512BitVector() &&
18218 (VT.getScalarSizeInBits() > 16 || Subtarget->hasBWI()))
18221 bool LShift = VT.is128BitVector() ||
18222 (VT.is256BitVector() && Subtarget->hasInt256());
18224 bool AShift = LShift && (Subtarget->hasVLX() ||
18225 (VT != MVT::v2i64 && VT != MVT::v4i64));
18226 return (Opcode == ISD::SRA) ? AShift : LShift;
18229 // The shift amount is a variable, but it is the same for all vector lanes.
18230 // These instructions are defined together with shift-immediate.
18232 bool SupportedVectorShiftWithBaseAmnt(MVT VT, const X86Subtarget *Subtarget,
18234 return SupportedVectorShiftWithImm(VT, Subtarget, Opcode);
18237 // Return true if the required (according to Opcode) variable-shift form is
18238 // natively supported by the Subtarget
18239 static bool SupportedVectorVarShift(MVT VT, const X86Subtarget *Subtarget,
18242 if (!Subtarget->hasInt256() || VT.getScalarSizeInBits() < 16)
18245 // vXi16 supported only on AVX-512, BWI
18246 if (VT.getScalarSizeInBits() == 16 && !Subtarget->hasBWI())
18249 if (VT.is512BitVector() || Subtarget->hasVLX())
18252 bool LShift = VT.is128BitVector() || VT.is256BitVector();
18253 bool AShift = LShift && VT != MVT::v2i64 && VT != MVT::v4i64;
18254 return (Opcode == ISD::SRA) ? AShift : LShift;
18257 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
18258 const X86Subtarget *Subtarget) {
18259 MVT VT = Op.getSimpleValueType();
18261 SDValue R = Op.getOperand(0);
18262 SDValue Amt = Op.getOperand(1);
18264 unsigned X86Opc = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
18265 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
18267 auto ArithmeticShiftRight64 = [&](uint64_t ShiftAmt) {
18268 assert((VT == MVT::v2i64 || VT == MVT::v4i64) && "Unexpected SRA type");
18269 MVT ExVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() * 2);
18270 SDValue Ex = DAG.getBitcast(ExVT, R);
18272 if (ShiftAmt >= 32) {
18273 // Splat sign to upper i32 dst, and SRA upper i32 src to lower i32.
18275 getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex, 31, DAG);
18276 SDValue Lower = getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex,
18277 ShiftAmt - 32, DAG);
18278 if (VT == MVT::v2i64)
18279 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower, {5, 1, 7, 3});
18280 if (VT == MVT::v4i64)
18281 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower,
18282 {9, 1, 11, 3, 13, 5, 15, 7});
18284 // SRA upper i32, SHL whole i64 and select lower i32.
18285 SDValue Upper = getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex,
18288 getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt, DAG);
18289 Lower = DAG.getBitcast(ExVT, Lower);
18290 if (VT == MVT::v2i64)
18291 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower, {4, 1, 6, 3});
18292 if (VT == MVT::v4i64)
18293 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower,
18294 {8, 1, 10, 3, 12, 5, 14, 7});
18296 return DAG.getBitcast(VT, Ex);
18299 // Optimize shl/srl/sra with constant shift amount.
18300 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
18301 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
18302 uint64_t ShiftAmt = ShiftConst->getZExtValue();
18304 if (SupportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode()))
18305 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
18307 // i64 SRA needs to be performed as partial shifts.
18308 if ((VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
18309 Op.getOpcode() == ISD::SRA && !Subtarget->hasXOP())
18310 return ArithmeticShiftRight64(ShiftAmt);
18312 if (VT == MVT::v16i8 || (Subtarget->hasInt256() && VT == MVT::v32i8)) {
18313 unsigned NumElts = VT.getVectorNumElements();
18314 MVT ShiftVT = MVT::getVectorVT(MVT::i16, NumElts / 2);
18316 // Simple i8 add case
18317 if (Op.getOpcode() == ISD::SHL && ShiftAmt == 1)
18318 return DAG.getNode(ISD::ADD, dl, VT, R, R);
18320 // ashr(R, 7) === cmp_slt(R, 0)
18321 if (Op.getOpcode() == ISD::SRA && ShiftAmt == 7) {
18322 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
18323 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
18326 // XOP can shift v16i8 directly instead of as shift v8i16 + mask.
18327 if (VT == MVT::v16i8 && Subtarget->hasXOP())
18330 if (Op.getOpcode() == ISD::SHL) {
18331 // Make a large shift.
18332 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, ShiftVT,
18334 SHL = DAG.getBitcast(VT, SHL);
18335 // Zero out the rightmost bits.
18336 SmallVector<SDValue, 32> V(
18337 NumElts, DAG.getConstant(uint8_t(-1U << ShiftAmt), dl, MVT::i8));
18338 return DAG.getNode(ISD::AND, dl, VT, SHL,
18339 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18341 if (Op.getOpcode() == ISD::SRL) {
18342 // Make a large shift.
18343 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, ShiftVT,
18345 SRL = DAG.getBitcast(VT, SRL);
18346 // Zero out the leftmost bits.
18347 SmallVector<SDValue, 32> V(
18348 NumElts, DAG.getConstant(uint8_t(-1U) >> ShiftAmt, dl, MVT::i8));
18349 return DAG.getNode(ISD::AND, dl, VT, SRL,
18350 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18352 if (Op.getOpcode() == ISD::SRA) {
18353 // ashr(R, Amt) === sub(xor(lshr(R, Amt), Mask), Mask)
18354 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18355 SmallVector<SDValue, 32> V(NumElts,
18356 DAG.getConstant(128 >> ShiftAmt, dl,
18358 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
18359 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
18360 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
18363 llvm_unreachable("Unknown shift opcode.");
18368 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18369 if (!Subtarget->is64Bit() && !Subtarget->hasXOP() &&
18370 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64))) {
18372 // Peek through any splat that was introduced for i64 shift vectorization.
18373 int SplatIndex = -1;
18374 if (ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt.getNode()))
18375 if (SVN->isSplat()) {
18376 SplatIndex = SVN->getSplatIndex();
18377 Amt = Amt.getOperand(0);
18378 assert(SplatIndex < (int)VT.getVectorNumElements() &&
18379 "Splat shuffle referencing second operand");
18382 if (Amt.getOpcode() != ISD::BITCAST ||
18383 Amt.getOperand(0).getOpcode() != ISD::BUILD_VECTOR)
18386 Amt = Amt.getOperand(0);
18387 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18388 VT.getVectorNumElements();
18389 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
18390 uint64_t ShiftAmt = 0;
18391 unsigned BaseOp = (SplatIndex < 0 ? 0 : SplatIndex * Ratio);
18392 for (unsigned i = 0; i != Ratio; ++i) {
18393 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i + BaseOp));
18397 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
18400 // Check remaining shift amounts (if not a splat).
18401 if (SplatIndex < 0) {
18402 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18403 uint64_t ShAmt = 0;
18404 for (unsigned j = 0; j != Ratio; ++j) {
18405 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
18409 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
18411 if (ShAmt != ShiftAmt)
18416 if (SupportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode()))
18417 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
18419 if (Op.getOpcode() == ISD::SRA)
18420 return ArithmeticShiftRight64(ShiftAmt);
18426 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
18427 const X86Subtarget* Subtarget) {
18428 MVT VT = Op.getSimpleValueType();
18430 SDValue R = Op.getOperand(0);
18431 SDValue Amt = Op.getOperand(1);
18433 unsigned X86OpcI = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
18434 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
18436 unsigned X86OpcV = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHL :
18437 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRL : X86ISD::VSRA;
18439 if (SupportedVectorShiftWithBaseAmnt(VT, Subtarget, Op.getOpcode())) {
18441 MVT EltVT = VT.getVectorElementType();
18443 if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Amt)) {
18444 // Check if this build_vector node is doing a splat.
18445 // If so, then set BaseShAmt equal to the splat value.
18446 BaseShAmt = BV->getSplatValue();
18447 if (BaseShAmt && BaseShAmt.getOpcode() == ISD::UNDEF)
18448 BaseShAmt = SDValue();
18450 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
18451 Amt = Amt.getOperand(0);
18453 ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt);
18454 if (SVN && SVN->isSplat()) {
18455 unsigned SplatIdx = (unsigned)SVN->getSplatIndex();
18456 SDValue InVec = Amt.getOperand(0);
18457 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
18458 assert((SplatIdx < InVec.getSimpleValueType().getVectorNumElements()) &&
18459 "Unexpected shuffle index found!");
18460 BaseShAmt = InVec.getOperand(SplatIdx);
18461 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
18462 if (ConstantSDNode *C =
18463 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
18464 if (C->getZExtValue() == SplatIdx)
18465 BaseShAmt = InVec.getOperand(1);
18470 // Avoid introducing an extract element from a shuffle.
18471 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InVec,
18472 DAG.getIntPtrConstant(SplatIdx, dl));
18476 if (BaseShAmt.getNode()) {
18477 assert(EltVT.bitsLE(MVT::i64) && "Unexpected element type!");
18478 if (EltVT != MVT::i64 && EltVT.bitsGT(MVT::i32))
18479 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, BaseShAmt);
18480 else if (EltVT.bitsLT(MVT::i32))
18481 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
18483 return getTargetVShiftNode(X86OpcI, dl, VT, R, BaseShAmt, DAG);
18487 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18488 if (!Subtarget->is64Bit() && VT == MVT::v2i64 &&
18489 Amt.getOpcode() == ISD::BITCAST &&
18490 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
18491 Amt = Amt.getOperand(0);
18492 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18493 VT.getVectorNumElements();
18494 std::vector<SDValue> Vals(Ratio);
18495 for (unsigned i = 0; i != Ratio; ++i)
18496 Vals[i] = Amt.getOperand(i);
18497 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18498 for (unsigned j = 0; j != Ratio; ++j)
18499 if (Vals[j] != Amt.getOperand(i + j))
18503 if (SupportedVectorShiftWithBaseAmnt(VT, Subtarget, Op.getOpcode()))
18504 return DAG.getNode(X86OpcV, dl, VT, R, Op.getOperand(1));
18509 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
18510 SelectionDAG &DAG) {
18511 MVT VT = Op.getSimpleValueType();
18513 SDValue R = Op.getOperand(0);
18514 SDValue Amt = Op.getOperand(1);
18516 assert(VT.isVector() && "Custom lowering only for vector shifts!");
18517 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
18519 if (SDValue V = LowerScalarImmediateShift(Op, DAG, Subtarget))
18522 if (SDValue V = LowerScalarVariableShift(Op, DAG, Subtarget))
18525 if (SupportedVectorVarShift(VT, Subtarget, Op.getOpcode()))
18528 // XOP has 128-bit variable logical/arithmetic shifts.
18529 // +ve/-ve Amt = shift left/right.
18530 if (Subtarget->hasXOP() &&
18531 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
18532 VT == MVT::v8i16 || VT == MVT::v16i8)) {
18533 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SRA) {
18534 SDValue Zero = getZeroVector(VT, Subtarget, DAG, dl);
18535 Amt = DAG.getNode(ISD::SUB, dl, VT, Zero, Amt);
18537 if (Op.getOpcode() == ISD::SHL || Op.getOpcode() == ISD::SRL)
18538 return DAG.getNode(X86ISD::VPSHL, dl, VT, R, Amt);
18539 if (Op.getOpcode() == ISD::SRA)
18540 return DAG.getNode(X86ISD::VPSHA, dl, VT, R, Amt);
18543 // 2i64 vector logical shifts can efficiently avoid scalarization - do the
18544 // shifts per-lane and then shuffle the partial results back together.
18545 if (VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) {
18546 // Splat the shift amounts so the scalar shifts above will catch it.
18547 SDValue Amt0 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {0, 0});
18548 SDValue Amt1 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {1, 1});
18549 SDValue R0 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt0);
18550 SDValue R1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt1);
18551 return DAG.getVectorShuffle(VT, dl, R0, R1, {0, 3});
18554 // i64 vector arithmetic shift can be emulated with the transform:
18555 // M = lshr(SIGN_BIT, Amt)
18556 // ashr(R, Amt) === sub(xor(lshr(R, Amt), M), M)
18557 if ((VT == MVT::v2i64 || (VT == MVT::v4i64 && Subtarget->hasInt256())) &&
18558 Op.getOpcode() == ISD::SRA) {
18559 SDValue S = DAG.getConstant(APInt::getSignBit(64), dl, VT);
18560 SDValue M = DAG.getNode(ISD::SRL, dl, VT, S, Amt);
18561 R = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18562 R = DAG.getNode(ISD::XOR, dl, VT, R, M);
18563 R = DAG.getNode(ISD::SUB, dl, VT, R, M);
18567 // If possible, lower this packed shift into a vector multiply instead of
18568 // expanding it into a sequence of scalar shifts.
18569 // Do this only if the vector shift count is a constant build_vector.
18570 if (Op.getOpcode() == ISD::SHL &&
18571 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
18572 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
18573 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18574 SmallVector<SDValue, 8> Elts;
18575 MVT SVT = VT.getVectorElementType();
18576 unsigned SVTBits = SVT.getSizeInBits();
18577 APInt One(SVTBits, 1);
18578 unsigned NumElems = VT.getVectorNumElements();
18580 for (unsigned i=0; i !=NumElems; ++i) {
18581 SDValue Op = Amt->getOperand(i);
18582 if (Op->getOpcode() == ISD::UNDEF) {
18583 Elts.push_back(Op);
18587 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
18588 APInt C(SVTBits, ND->getAPIntValue().getZExtValue());
18589 uint64_t ShAmt = C.getZExtValue();
18590 if (ShAmt >= SVTBits) {
18591 Elts.push_back(DAG.getUNDEF(SVT));
18594 Elts.push_back(DAG.getConstant(One.shl(ShAmt), dl, SVT));
18596 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
18597 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
18600 // Lower SHL with variable shift amount.
18601 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
18602 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, dl, VT));
18604 Op = DAG.getNode(ISD::ADD, dl, VT, Op,
18605 DAG.getConstant(0x3f800000U, dl, VT));
18606 Op = DAG.getBitcast(MVT::v4f32, Op);
18607 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
18608 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
18611 // If possible, lower this shift as a sequence of two shifts by
18612 // constant plus a MOVSS/MOVSD instead of scalarizing it.
18614 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
18616 // Could be rewritten as:
18617 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
18619 // The advantage is that the two shifts from the example would be
18620 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
18621 // the vector shift into four scalar shifts plus four pairs of vector
18623 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
18624 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18625 unsigned TargetOpcode = X86ISD::MOVSS;
18626 bool CanBeSimplified;
18627 // The splat value for the first packed shift (the 'X' from the example).
18628 SDValue Amt1 = Amt->getOperand(0);
18629 // The splat value for the second packed shift (the 'Y' from the example).
18630 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
18631 Amt->getOperand(2);
18633 // See if it is possible to replace this node with a sequence of
18634 // two shifts followed by a MOVSS/MOVSD
18635 if (VT == MVT::v4i32) {
18636 // Check if it is legal to use a MOVSS.
18637 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
18638 Amt2 == Amt->getOperand(3);
18639 if (!CanBeSimplified) {
18640 // Otherwise, check if we can still simplify this node using a MOVSD.
18641 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
18642 Amt->getOperand(2) == Amt->getOperand(3);
18643 TargetOpcode = X86ISD::MOVSD;
18644 Amt2 = Amt->getOperand(2);
18647 // Do similar checks for the case where the machine value type
18649 CanBeSimplified = Amt1 == Amt->getOperand(1);
18650 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
18651 CanBeSimplified = Amt2 == Amt->getOperand(i);
18653 if (!CanBeSimplified) {
18654 TargetOpcode = X86ISD::MOVSD;
18655 CanBeSimplified = true;
18656 Amt2 = Amt->getOperand(4);
18657 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
18658 CanBeSimplified = Amt1 == Amt->getOperand(i);
18659 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
18660 CanBeSimplified = Amt2 == Amt->getOperand(j);
18664 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
18665 isa<ConstantSDNode>(Amt2)) {
18666 // Replace this node with two shifts followed by a MOVSS/MOVSD.
18667 MVT CastVT = MVT::v4i32;
18669 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), dl, VT);
18670 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
18672 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), dl, VT);
18673 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
18674 if (TargetOpcode == X86ISD::MOVSD)
18675 CastVT = MVT::v2i64;
18676 SDValue BitCast1 = DAG.getBitcast(CastVT, Shift1);
18677 SDValue BitCast2 = DAG.getBitcast(CastVT, Shift2);
18678 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
18680 return DAG.getBitcast(VT, Result);
18684 // v4i32 Non Uniform Shifts.
18685 // If the shift amount is constant we can shift each lane using the SSE2
18686 // immediate shifts, else we need to zero-extend each lane to the lower i64
18687 // and shift using the SSE2 variable shifts.
18688 // The separate results can then be blended together.
18689 if (VT == MVT::v4i32) {
18690 unsigned Opc = Op.getOpcode();
18691 SDValue Amt0, Amt1, Amt2, Amt3;
18692 if (ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18693 Amt0 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {0, 0, 0, 0});
18694 Amt1 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {1, 1, 1, 1});
18695 Amt2 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {2, 2, 2, 2});
18696 Amt3 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {3, 3, 3, 3});
18698 // ISD::SHL is handled above but we include it here for completeness.
18701 llvm_unreachable("Unknown target vector shift node");
18703 Opc = X86ISD::VSHL;
18706 Opc = X86ISD::VSRL;
18709 Opc = X86ISD::VSRA;
18712 // The SSE2 shifts use the lower i64 as the same shift amount for
18713 // all lanes and the upper i64 is ignored. These shuffle masks
18714 // optimally zero-extend each lanes on SSE2/SSE41/AVX targets.
18715 SDValue Z = getZeroVector(VT, Subtarget, DAG, dl);
18716 Amt0 = DAG.getVectorShuffle(VT, dl, Amt, Z, {0, 4, -1, -1});
18717 Amt1 = DAG.getVectorShuffle(VT, dl, Amt, Z, {1, 5, -1, -1});
18718 Amt2 = DAG.getVectorShuffle(VT, dl, Amt, Z, {2, 6, -1, -1});
18719 Amt3 = DAG.getVectorShuffle(VT, dl, Amt, Z, {3, 7, -1, -1});
18722 SDValue R0 = DAG.getNode(Opc, dl, VT, R, Amt0);
18723 SDValue R1 = DAG.getNode(Opc, dl, VT, R, Amt1);
18724 SDValue R2 = DAG.getNode(Opc, dl, VT, R, Amt2);
18725 SDValue R3 = DAG.getNode(Opc, dl, VT, R, Amt3);
18726 SDValue R02 = DAG.getVectorShuffle(VT, dl, R0, R2, {0, -1, 6, -1});
18727 SDValue R13 = DAG.getVectorShuffle(VT, dl, R1, R3, {-1, 1, -1, 7});
18728 return DAG.getVectorShuffle(VT, dl, R02, R13, {0, 5, 2, 7});
18731 if (VT == MVT::v16i8 ||
18732 (VT == MVT::v32i8 && Subtarget->hasInt256() && !Subtarget->hasXOP())) {
18733 MVT ExtVT = MVT::getVectorVT(MVT::i16, VT.getVectorNumElements() / 2);
18734 unsigned ShiftOpcode = Op->getOpcode();
18736 auto SignBitSelect = [&](MVT SelVT, SDValue Sel, SDValue V0, SDValue V1) {
18737 // On SSE41 targets we make use of the fact that VSELECT lowers
18738 // to PBLENDVB which selects bytes based just on the sign bit.
18739 if (Subtarget->hasSSE41()) {
18740 V0 = DAG.getBitcast(VT, V0);
18741 V1 = DAG.getBitcast(VT, V1);
18742 Sel = DAG.getBitcast(VT, Sel);
18743 return DAG.getBitcast(SelVT,
18744 DAG.getNode(ISD::VSELECT, dl, VT, Sel, V0, V1));
18746 // On pre-SSE41 targets we test for the sign bit by comparing to
18747 // zero - a negative value will set all bits of the lanes to true
18748 // and VSELECT uses that in its OR(AND(V0,C),AND(V1,~C)) lowering.
18749 SDValue Z = getZeroVector(SelVT, Subtarget, DAG, dl);
18750 SDValue C = DAG.getNode(X86ISD::PCMPGT, dl, SelVT, Z, Sel);
18751 return DAG.getNode(ISD::VSELECT, dl, SelVT, C, V0, V1);
18754 // Turn 'a' into a mask suitable for VSELECT: a = a << 5;
18755 // We can safely do this using i16 shifts as we're only interested in
18756 // the 3 lower bits of each byte.
18757 Amt = DAG.getBitcast(ExtVT, Amt);
18758 Amt = DAG.getNode(ISD::SHL, dl, ExtVT, Amt, DAG.getConstant(5, dl, ExtVT));
18759 Amt = DAG.getBitcast(VT, Amt);
18761 if (Op->getOpcode() == ISD::SHL || Op->getOpcode() == ISD::SRL) {
18762 // r = VSELECT(r, shift(r, 4), a);
18764 DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(4, dl, VT));
18765 R = SignBitSelect(VT, Amt, M, R);
18768 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18770 // r = VSELECT(r, shift(r, 2), a);
18771 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(2, dl, VT));
18772 R = SignBitSelect(VT, Amt, M, R);
18775 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18777 // return VSELECT(r, shift(r, 1), a);
18778 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(1, dl, VT));
18779 R = SignBitSelect(VT, Amt, M, R);
18783 if (Op->getOpcode() == ISD::SRA) {
18784 // For SRA we need to unpack each byte to the higher byte of a i16 vector
18785 // so we can correctly sign extend. We don't care what happens to the
18787 SDValue ALo = DAG.getNode(X86ISD::UNPCKL, dl, VT, DAG.getUNDEF(VT), Amt);
18788 SDValue AHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, DAG.getUNDEF(VT), Amt);
18789 SDValue RLo = DAG.getNode(X86ISD::UNPCKL, dl, VT, DAG.getUNDEF(VT), R);
18790 SDValue RHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, DAG.getUNDEF(VT), R);
18791 ALo = DAG.getBitcast(ExtVT, ALo);
18792 AHi = DAG.getBitcast(ExtVT, AHi);
18793 RLo = DAG.getBitcast(ExtVT, RLo);
18794 RHi = DAG.getBitcast(ExtVT, RHi);
18796 // r = VSELECT(r, shift(r, 4), a);
18797 SDValue MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
18798 DAG.getConstant(4, dl, ExtVT));
18799 SDValue MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
18800 DAG.getConstant(4, dl, ExtVT));
18801 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
18802 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
18805 ALo = DAG.getNode(ISD::ADD, dl, ExtVT, ALo, ALo);
18806 AHi = DAG.getNode(ISD::ADD, dl, ExtVT, AHi, AHi);
18808 // r = VSELECT(r, shift(r, 2), a);
18809 MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
18810 DAG.getConstant(2, dl, ExtVT));
18811 MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
18812 DAG.getConstant(2, dl, ExtVT));
18813 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
18814 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
18817 ALo = DAG.getNode(ISD::ADD, dl, ExtVT, ALo, ALo);
18818 AHi = DAG.getNode(ISD::ADD, dl, ExtVT, AHi, AHi);
18820 // r = VSELECT(r, shift(r, 1), a);
18821 MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
18822 DAG.getConstant(1, dl, ExtVT));
18823 MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
18824 DAG.getConstant(1, dl, ExtVT));
18825 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
18826 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
18828 // Logical shift the result back to the lower byte, leaving a zero upper
18830 // meaning that we can safely pack with PACKUSWB.
18832 DAG.getNode(ISD::SRL, dl, ExtVT, RLo, DAG.getConstant(8, dl, ExtVT));
18834 DAG.getNode(ISD::SRL, dl, ExtVT, RHi, DAG.getConstant(8, dl, ExtVT));
18835 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);
18839 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
18840 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
18841 // solution better.
18842 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
18843 MVT ExtVT = MVT::v8i32;
18845 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
18846 R = DAG.getNode(ExtOpc, dl, ExtVT, R);
18847 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, ExtVT, Amt);
18848 return DAG.getNode(ISD::TRUNCATE, dl, VT,
18849 DAG.getNode(Op.getOpcode(), dl, ExtVT, R, Amt));
18852 if (Subtarget->hasInt256() && !Subtarget->hasXOP() && VT == MVT::v16i16) {
18853 MVT ExtVT = MVT::v8i32;
18854 SDValue Z = getZeroVector(VT, Subtarget, DAG, dl);
18855 SDValue ALo = DAG.getNode(X86ISD::UNPCKL, dl, VT, Amt, Z);
18856 SDValue AHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, Amt, Z);
18857 SDValue RLo = DAG.getNode(X86ISD::UNPCKL, dl, VT, R, R);
18858 SDValue RHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, R, R);
18859 ALo = DAG.getBitcast(ExtVT, ALo);
18860 AHi = DAG.getBitcast(ExtVT, AHi);
18861 RLo = DAG.getBitcast(ExtVT, RLo);
18862 RHi = DAG.getBitcast(ExtVT, RHi);
18863 SDValue Lo = DAG.getNode(Op.getOpcode(), dl, ExtVT, RLo, ALo);
18864 SDValue Hi = DAG.getNode(Op.getOpcode(), dl, ExtVT, RHi, AHi);
18865 Lo = DAG.getNode(ISD::SRL, dl, ExtVT, Lo, DAG.getConstant(16, dl, ExtVT));
18866 Hi = DAG.getNode(ISD::SRL, dl, ExtVT, Hi, DAG.getConstant(16, dl, ExtVT));
18867 return DAG.getNode(X86ISD::PACKUS, dl, VT, Lo, Hi);
18870 if (VT == MVT::v8i16) {
18871 unsigned ShiftOpcode = Op->getOpcode();
18873 auto SignBitSelect = [&](SDValue Sel, SDValue V0, SDValue V1) {
18874 // On SSE41 targets we make use of the fact that VSELECT lowers
18875 // to PBLENDVB which selects bytes based just on the sign bit.
18876 if (Subtarget->hasSSE41()) {
18877 MVT ExtVT = MVT::getVectorVT(MVT::i8, VT.getVectorNumElements() * 2);
18878 V0 = DAG.getBitcast(ExtVT, V0);
18879 V1 = DAG.getBitcast(ExtVT, V1);
18880 Sel = DAG.getBitcast(ExtVT, Sel);
18881 return DAG.getBitcast(
18882 VT, DAG.getNode(ISD::VSELECT, dl, ExtVT, Sel, V0, V1));
18884 // On pre-SSE41 targets we splat the sign bit - a negative value will
18885 // set all bits of the lanes to true and VSELECT uses that in
18886 // its OR(AND(V0,C),AND(V1,~C)) lowering.
18888 DAG.getNode(ISD::SRA, dl, VT, Sel, DAG.getConstant(15, dl, VT));
18889 return DAG.getNode(ISD::VSELECT, dl, VT, C, V0, V1);
18892 // Turn 'a' into a mask suitable for VSELECT: a = a << 12;
18893 if (Subtarget->hasSSE41()) {
18894 // On SSE41 targets we need to replicate the shift mask in both
18895 // bytes for PBLENDVB.
18898 DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(4, dl, VT)),
18899 DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(12, dl, VT)));
18901 Amt = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(12, dl, VT));
18904 // r = VSELECT(r, shift(r, 8), a);
18905 SDValue M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(8, dl, VT));
18906 R = SignBitSelect(Amt, M, R);
18909 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18911 // r = VSELECT(r, shift(r, 4), a);
18912 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(4, dl, VT));
18913 R = SignBitSelect(Amt, M, R);
18916 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18918 // r = VSELECT(r, shift(r, 2), a);
18919 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(2, dl, VT));
18920 R = SignBitSelect(Amt, M, R);
18923 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18925 // return VSELECT(r, shift(r, 1), a);
18926 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(1, dl, VT));
18927 R = SignBitSelect(Amt, M, R);
18931 // Decompose 256-bit shifts into smaller 128-bit shifts.
18932 if (VT.is256BitVector()) {
18933 unsigned NumElems = VT.getVectorNumElements();
18934 MVT EltVT = VT.getVectorElementType();
18935 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18937 // Extract the two vectors
18938 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
18939 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
18941 // Recreate the shift amount vectors
18942 SDValue Amt1, Amt2;
18943 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
18944 // Constant shift amount
18945 SmallVector<SDValue, 8> Ops(Amt->op_begin(), Amt->op_begin() + NumElems);
18946 ArrayRef<SDValue> Amt1Csts = makeArrayRef(Ops).slice(0, NumElems / 2);
18947 ArrayRef<SDValue> Amt2Csts = makeArrayRef(Ops).slice(NumElems / 2);
18949 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
18950 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
18952 // Variable shift amount
18953 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
18954 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
18957 // Issue new vector shifts for the smaller types
18958 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
18959 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
18961 // Concatenate the result back
18962 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
18968 static SDValue LowerRotate(SDValue Op, const X86Subtarget *Subtarget,
18969 SelectionDAG &DAG) {
18970 MVT VT = Op.getSimpleValueType();
18972 SDValue R = Op.getOperand(0);
18973 SDValue Amt = Op.getOperand(1);
18975 assert(VT.isVector() && "Custom lowering only for vector rotates!");
18976 assert(Subtarget->hasXOP() && "XOP support required for vector rotates!");
18977 assert((Op.getOpcode() == ISD::ROTL) && "Only ROTL supported");
18979 // XOP has 128-bit vector variable + immediate rotates.
18980 // +ve/-ve Amt = rotate left/right.
18982 // Split 256-bit integers.
18983 if (VT.is256BitVector())
18984 return Lower256IntArith(Op, DAG);
18986 assert(VT.is128BitVector() && "Only rotate 128-bit vectors!");
18988 // Attempt to rotate by immediate.
18989 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
18990 if (auto *RotateConst = BVAmt->getConstantSplatNode()) {
18991 uint64_t RotateAmt = RotateConst->getAPIntValue().getZExtValue();
18992 assert(RotateAmt < VT.getScalarSizeInBits() && "Rotation out of range");
18993 return DAG.getNode(X86ISD::VPROTI, DL, VT, R,
18994 DAG.getConstant(RotateAmt, DL, MVT::i8));
18998 // Use general rotate by variable (per-element).
18999 return DAG.getNode(X86ISD::VPROT, DL, VT, R, Amt);
19002 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
19003 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
19004 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
19005 // looks for this combo and may remove the "setcc" instruction if the "setcc"
19006 // has only one use.
19007 SDNode *N = Op.getNode();
19008 SDValue LHS = N->getOperand(0);
19009 SDValue RHS = N->getOperand(1);
19010 unsigned BaseOp = 0;
19013 switch (Op.getOpcode()) {
19014 default: llvm_unreachable("Unknown ovf instruction!");
19016 // A subtract of one will be selected as a INC. Note that INC doesn't
19017 // set CF, so we can't do this for UADDO.
19018 if (isOneConstant(RHS)) {
19019 BaseOp = X86ISD::INC;
19020 Cond = X86::COND_O;
19023 BaseOp = X86ISD::ADD;
19024 Cond = X86::COND_O;
19027 BaseOp = X86ISD::ADD;
19028 Cond = X86::COND_B;
19031 // A subtract of one will be selected as a DEC. Note that DEC doesn't
19032 // set CF, so we can't do this for USUBO.
19033 if (isOneConstant(RHS)) {
19034 BaseOp = X86ISD::DEC;
19035 Cond = X86::COND_O;
19038 BaseOp = X86ISD::SUB;
19039 Cond = X86::COND_O;
19042 BaseOp = X86ISD::SUB;
19043 Cond = X86::COND_B;
19046 BaseOp = N->getValueType(0) == MVT::i8 ? X86ISD::SMUL8 : X86ISD::SMUL;
19047 Cond = X86::COND_O;
19049 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
19050 if (N->getValueType(0) == MVT::i8) {
19051 BaseOp = X86ISD::UMUL8;
19052 Cond = X86::COND_O;
19055 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
19057 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
19060 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
19061 DAG.getConstant(X86::COND_O, DL, MVT::i32),
19062 SDValue(Sum.getNode(), 2));
19064 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
19068 // Also sets EFLAGS.
19069 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
19070 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
19073 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
19074 DAG.getConstant(Cond, DL, MVT::i32),
19075 SDValue(Sum.getNode(), 1));
19077 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
19080 /// Returns true if the operand type is exactly twice the native width, and
19081 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
19082 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
19083 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
19084 bool X86TargetLowering::needsCmpXchgNb(Type *MemType) const {
19085 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
19088 return !Subtarget->is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
19089 else if (OpWidth == 128)
19090 return Subtarget->hasCmpxchg16b();
19095 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
19096 return needsCmpXchgNb(SI->getValueOperand()->getType());
19099 // Note: this turns large loads into lock cmpxchg8b/16b.
19100 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
19101 TargetLowering::AtomicExpansionKind
19102 X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
19103 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
19104 return needsCmpXchgNb(PTy->getElementType()) ? AtomicExpansionKind::CmpXChg
19105 : AtomicExpansionKind::None;
19108 TargetLowering::AtomicExpansionKind
19109 X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
19110 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
19111 Type *MemType = AI->getType();
19113 // If the operand is too big, we must see if cmpxchg8/16b is available
19114 // and default to library calls otherwise.
19115 if (MemType->getPrimitiveSizeInBits() > NativeWidth) {
19116 return needsCmpXchgNb(MemType) ? AtomicExpansionKind::CmpXChg
19117 : AtomicExpansionKind::None;
19120 AtomicRMWInst::BinOp Op = AI->getOperation();
19123 llvm_unreachable("Unknown atomic operation");
19124 case AtomicRMWInst::Xchg:
19125 case AtomicRMWInst::Add:
19126 case AtomicRMWInst::Sub:
19127 // It's better to use xadd, xsub or xchg for these in all cases.
19128 return AtomicExpansionKind::None;
19129 case AtomicRMWInst::Or:
19130 case AtomicRMWInst::And:
19131 case AtomicRMWInst::Xor:
19132 // If the atomicrmw's result isn't actually used, we can just add a "lock"
19133 // prefix to a normal instruction for these operations.
19134 return !AI->use_empty() ? AtomicExpansionKind::CmpXChg
19135 : AtomicExpansionKind::None;
19136 case AtomicRMWInst::Nand:
19137 case AtomicRMWInst::Max:
19138 case AtomicRMWInst::Min:
19139 case AtomicRMWInst::UMax:
19140 case AtomicRMWInst::UMin:
19141 // These always require a non-trivial set of data operations on x86. We must
19142 // use a cmpxchg loop.
19143 return AtomicExpansionKind::CmpXChg;
19147 static bool hasMFENCE(const X86Subtarget& Subtarget) {
19148 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
19149 // no-sse2). There isn't any reason to disable it if the target processor
19151 return Subtarget.hasSSE2() || Subtarget.is64Bit();
19155 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
19156 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
19157 Type *MemType = AI->getType();
19158 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
19159 // there is no benefit in turning such RMWs into loads, and it is actually
19160 // harmful as it introduces a mfence.
19161 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
19164 auto Builder = IRBuilder<>(AI);
19165 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
19166 auto SynchScope = AI->getSynchScope();
19167 // We must restrict the ordering to avoid generating loads with Release or
19168 // ReleaseAcquire orderings.
19169 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
19170 auto Ptr = AI->getPointerOperand();
19172 // Before the load we need a fence. Here is an example lifted from
19173 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
19176 // x.store(1, relaxed);
19177 // r1 = y.fetch_add(0, release);
19179 // y.fetch_add(42, acquire);
19180 // r2 = x.load(relaxed);
19181 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
19182 // lowered to just a load without a fence. A mfence flushes the store buffer,
19183 // making the optimization clearly correct.
19184 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
19185 // otherwise, we might be able to be more aggressive on relaxed idempotent
19186 // rmw. In practice, they do not look useful, so we don't try to be
19187 // especially clever.
19188 if (SynchScope == SingleThread)
19189 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
19190 // the IR level, so we must wrap it in an intrinsic.
19193 if (!hasMFENCE(*Subtarget))
19194 // FIXME: it might make sense to use a locked operation here but on a
19195 // different cache-line to prevent cache-line bouncing. In practice it
19196 // is probably a small win, and x86 processors without mfence are rare
19197 // enough that we do not bother.
19201 llvm::Intrinsic::getDeclaration(M, Intrinsic::x86_sse2_mfence);
19202 Builder.CreateCall(MFence, {});
19204 // Finally we can emit the atomic load.
19205 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
19206 AI->getType()->getPrimitiveSizeInBits());
19207 Loaded->setAtomic(Order, SynchScope);
19208 AI->replaceAllUsesWith(Loaded);
19209 AI->eraseFromParent();
19213 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
19214 SelectionDAG &DAG) {
19216 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
19217 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
19218 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
19219 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
19221 // The only fence that needs an instruction is a sequentially-consistent
19222 // cross-thread fence.
19223 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
19224 if (hasMFENCE(*Subtarget))
19225 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
19227 SDValue Chain = Op.getOperand(0);
19228 SDValue Zero = DAG.getConstant(0, dl, MVT::i32);
19230 DAG.getRegister(X86::ESP, MVT::i32), // Base
19231 DAG.getTargetConstant(1, dl, MVT::i8), // Scale
19232 DAG.getRegister(0, MVT::i32), // Index
19233 DAG.getTargetConstant(0, dl, MVT::i32), // Disp
19234 DAG.getRegister(0, MVT::i32), // Segment.
19238 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
19239 return SDValue(Res, 0);
19242 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
19243 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
19246 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
19247 SelectionDAG &DAG) {
19248 MVT T = Op.getSimpleValueType();
19252 switch(T.SimpleTy) {
19253 default: llvm_unreachable("Invalid value type!");
19254 case MVT::i8: Reg = X86::AL; size = 1; break;
19255 case MVT::i16: Reg = X86::AX; size = 2; break;
19256 case MVT::i32: Reg = X86::EAX; size = 4; break;
19258 assert(Subtarget->is64Bit() && "Node not type legal!");
19259 Reg = X86::RAX; size = 8;
19262 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
19263 Op.getOperand(2), SDValue());
19264 SDValue Ops[] = { cpIn.getValue(0),
19267 DAG.getTargetConstant(size, DL, MVT::i8),
19268 cpIn.getValue(1) };
19269 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
19270 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
19271 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
19275 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
19276 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
19277 MVT::i32, cpOut.getValue(2));
19278 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
19279 DAG.getConstant(X86::COND_E, DL, MVT::i8),
19282 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
19283 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
19284 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
19288 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
19289 SelectionDAG &DAG) {
19290 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
19291 MVT DstVT = Op.getSimpleValueType();
19293 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
19294 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19295 if (DstVT != MVT::f64)
19296 // This conversion needs to be expanded.
19299 SDValue InVec = Op->getOperand(0);
19301 unsigned NumElts = SrcVT.getVectorNumElements();
19302 MVT SVT = SrcVT.getVectorElementType();
19304 // Widen the vector in input in the case of MVT::v2i32.
19305 // Example: from MVT::v2i32 to MVT::v4i32.
19306 SmallVector<SDValue, 16> Elts;
19307 for (unsigned i = 0, e = NumElts; i != e; ++i)
19308 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
19309 DAG.getIntPtrConstant(i, dl)));
19311 // Explicitly mark the extra elements as Undef.
19312 Elts.append(NumElts, DAG.getUNDEF(SVT));
19314 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19315 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
19316 SDValue ToV2F64 = DAG.getBitcast(MVT::v2f64, BV);
19317 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
19318 DAG.getIntPtrConstant(0, dl));
19321 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
19322 Subtarget->hasMMX() && "Unexpected custom BITCAST");
19323 assert((DstVT == MVT::i64 ||
19324 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
19325 "Unexpected custom BITCAST");
19326 // i64 <=> MMX conversions are Legal.
19327 if (SrcVT==MVT::i64 && DstVT.isVector())
19329 if (DstVT==MVT::i64 && SrcVT.isVector())
19331 // MMX <=> MMX conversions are Legal.
19332 if (SrcVT.isVector() && DstVT.isVector())
19334 // All other conversions need to be expanded.
19338 /// Compute the horizontal sum of bytes in V for the elements of VT.
19340 /// Requires V to be a byte vector and VT to be an integer vector type with
19341 /// wider elements than V's type. The width of the elements of VT determines
19342 /// how many bytes of V are summed horizontally to produce each element of the
19344 static SDValue LowerHorizontalByteSum(SDValue V, MVT VT,
19345 const X86Subtarget *Subtarget,
19346 SelectionDAG &DAG) {
19348 MVT ByteVecVT = V.getSimpleValueType();
19349 MVT EltVT = VT.getVectorElementType();
19350 int NumElts = VT.getVectorNumElements();
19351 assert(ByteVecVT.getVectorElementType() == MVT::i8 &&
19352 "Expected value to have byte element type.");
19353 assert(EltVT != MVT::i8 &&
19354 "Horizontal byte sum only makes sense for wider elements!");
19355 unsigned VecSize = VT.getSizeInBits();
19356 assert(ByteVecVT.getSizeInBits() == VecSize && "Cannot change vector size!");
19358 // PSADBW instruction horizontally add all bytes and leave the result in i64
19359 // chunks, thus directly computes the pop count for v2i64 and v4i64.
19360 if (EltVT == MVT::i64) {
19361 SDValue Zeros = getZeroVector(ByteVecVT, Subtarget, DAG, DL);
19362 MVT SadVecVT = MVT::getVectorVT(MVT::i64, VecSize / 64);
19363 V = DAG.getNode(X86ISD::PSADBW, DL, SadVecVT, V, Zeros);
19364 return DAG.getBitcast(VT, V);
19367 if (EltVT == MVT::i32) {
19368 // We unpack the low half and high half into i32s interleaved with zeros so
19369 // that we can use PSADBW to horizontally sum them. The most useful part of
19370 // this is that it lines up the results of two PSADBW instructions to be
19371 // two v2i64 vectors which concatenated are the 4 population counts. We can
19372 // then use PACKUSWB to shrink and concatenate them into a v4i32 again.
19373 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, DL);
19374 SDValue Low = DAG.getNode(X86ISD::UNPCKL, DL, VT, V, Zeros);
19375 SDValue High = DAG.getNode(X86ISD::UNPCKH, DL, VT, V, Zeros);
19377 // Do the horizontal sums into two v2i64s.
19378 Zeros = getZeroVector(ByteVecVT, Subtarget, DAG, DL);
19379 MVT SadVecVT = MVT::getVectorVT(MVT::i64, VecSize / 64);
19380 Low = DAG.getNode(X86ISD::PSADBW, DL, SadVecVT,
19381 DAG.getBitcast(ByteVecVT, Low), Zeros);
19382 High = DAG.getNode(X86ISD::PSADBW, DL, SadVecVT,
19383 DAG.getBitcast(ByteVecVT, High), Zeros);
19385 // Merge them together.
19386 MVT ShortVecVT = MVT::getVectorVT(MVT::i16, VecSize / 16);
19387 V = DAG.getNode(X86ISD::PACKUS, DL, ByteVecVT,
19388 DAG.getBitcast(ShortVecVT, Low),
19389 DAG.getBitcast(ShortVecVT, High));
19391 return DAG.getBitcast(VT, V);
19394 // The only element type left is i16.
19395 assert(EltVT == MVT::i16 && "Unknown how to handle type");
19397 // To obtain pop count for each i16 element starting from the pop count for
19398 // i8 elements, shift the i16s left by 8, sum as i8s, and then shift as i16s
19399 // right by 8. It is important to shift as i16s as i8 vector shift isn't
19400 // directly supported.
19401 SmallVector<SDValue, 16> Shifters(NumElts, DAG.getConstant(8, DL, EltVT));
19402 SDValue Shifter = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Shifters);
19403 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, DAG.getBitcast(VT, V), Shifter);
19404 V = DAG.getNode(ISD::ADD, DL, ByteVecVT, DAG.getBitcast(ByteVecVT, Shl),
19405 DAG.getBitcast(ByteVecVT, V));
19406 return DAG.getNode(ISD::SRL, DL, VT, DAG.getBitcast(VT, V), Shifter);
19409 static SDValue LowerVectorCTPOPInRegLUT(SDValue Op, SDLoc DL,
19410 const X86Subtarget *Subtarget,
19411 SelectionDAG &DAG) {
19412 MVT VT = Op.getSimpleValueType();
19413 MVT EltVT = VT.getVectorElementType();
19414 unsigned VecSize = VT.getSizeInBits();
19416 // Implement a lookup table in register by using an algorithm based on:
19417 // http://wm.ite.pl/articles/sse-popcount.html
19419 // The general idea is that every lower byte nibble in the input vector is an
19420 // index into a in-register pre-computed pop count table. We then split up the
19421 // input vector in two new ones: (1) a vector with only the shifted-right
19422 // higher nibbles for each byte and (2) a vector with the lower nibbles (and
19423 // masked out higher ones) for each byte. PSHUB is used separately with both
19424 // to index the in-register table. Next, both are added and the result is a
19425 // i8 vector where each element contains the pop count for input byte.
19427 // To obtain the pop count for elements != i8, we follow up with the same
19428 // approach and use additional tricks as described below.
19430 const int LUT[16] = {/* 0 */ 0, /* 1 */ 1, /* 2 */ 1, /* 3 */ 2,
19431 /* 4 */ 1, /* 5 */ 2, /* 6 */ 2, /* 7 */ 3,
19432 /* 8 */ 1, /* 9 */ 2, /* a */ 2, /* b */ 3,
19433 /* c */ 2, /* d */ 3, /* e */ 3, /* f */ 4};
19435 int NumByteElts = VecSize / 8;
19436 MVT ByteVecVT = MVT::getVectorVT(MVT::i8, NumByteElts);
19437 SDValue In = DAG.getBitcast(ByteVecVT, Op);
19438 SmallVector<SDValue, 16> LUTVec;
19439 for (int i = 0; i < NumByteElts; ++i)
19440 LUTVec.push_back(DAG.getConstant(LUT[i % 16], DL, MVT::i8));
19441 SDValue InRegLUT = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, LUTVec);
19442 SmallVector<SDValue, 16> Mask0F(NumByteElts,
19443 DAG.getConstant(0x0F, DL, MVT::i8));
19444 SDValue M0F = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, Mask0F);
19447 SmallVector<SDValue, 16> Four(NumByteElts, DAG.getConstant(4, DL, MVT::i8));
19448 SDValue FourV = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, Four);
19449 SDValue HighNibbles = DAG.getNode(ISD::SRL, DL, ByteVecVT, In, FourV);
19452 SDValue LowNibbles = DAG.getNode(ISD::AND, DL, ByteVecVT, In, M0F);
19454 // The input vector is used as the shuffle mask that index elements into the
19455 // LUT. After counting low and high nibbles, add the vector to obtain the
19456 // final pop count per i8 element.
19457 SDValue HighPopCnt =
19458 DAG.getNode(X86ISD::PSHUFB, DL, ByteVecVT, InRegLUT, HighNibbles);
19459 SDValue LowPopCnt =
19460 DAG.getNode(X86ISD::PSHUFB, DL, ByteVecVT, InRegLUT, LowNibbles);
19461 SDValue PopCnt = DAG.getNode(ISD::ADD, DL, ByteVecVT, HighPopCnt, LowPopCnt);
19463 if (EltVT == MVT::i8)
19466 return LowerHorizontalByteSum(PopCnt, VT, Subtarget, DAG);
19469 static SDValue LowerVectorCTPOPBitmath(SDValue Op, SDLoc DL,
19470 const X86Subtarget *Subtarget,
19471 SelectionDAG &DAG) {
19472 MVT VT = Op.getSimpleValueType();
19473 assert(VT.is128BitVector() &&
19474 "Only 128-bit vector bitmath lowering supported.");
19476 int VecSize = VT.getSizeInBits();
19477 MVT EltVT = VT.getVectorElementType();
19478 int Len = EltVT.getSizeInBits();
19480 // This is the vectorized version of the "best" algorithm from
19481 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
19482 // with a minor tweak to use a series of adds + shifts instead of vector
19483 // multiplications. Implemented for all integer vector types. We only use
19484 // this when we don't have SSSE3 which allows a LUT-based lowering that is
19485 // much faster, even faster than using native popcnt instructions.
19487 auto GetShift = [&](unsigned OpCode, SDValue V, int Shifter) {
19488 MVT VT = V.getSimpleValueType();
19489 SmallVector<SDValue, 32> Shifters(
19490 VT.getVectorNumElements(),
19491 DAG.getConstant(Shifter, DL, VT.getVectorElementType()));
19492 return DAG.getNode(OpCode, DL, VT, V,
19493 DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Shifters));
19495 auto GetMask = [&](SDValue V, APInt Mask) {
19496 MVT VT = V.getSimpleValueType();
19497 SmallVector<SDValue, 32> Masks(
19498 VT.getVectorNumElements(),
19499 DAG.getConstant(Mask, DL, VT.getVectorElementType()));
19500 return DAG.getNode(ISD::AND, DL, VT, V,
19501 DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Masks));
19504 // We don't want to incur the implicit masks required to SRL vNi8 vectors on
19505 // x86, so set the SRL type to have elements at least i16 wide. This is
19506 // correct because all of our SRLs are followed immediately by a mask anyways
19507 // that handles any bits that sneak into the high bits of the byte elements.
19508 MVT SrlVT = Len > 8 ? VT : MVT::getVectorVT(MVT::i16, VecSize / 16);
19512 // v = v - ((v >> 1) & 0x55555555...)
19514 DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 1));
19515 SDValue And = GetMask(Srl, APInt::getSplat(Len, APInt(8, 0x55)));
19516 V = DAG.getNode(ISD::SUB, DL, VT, V, And);
19518 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
19519 SDValue AndLHS = GetMask(V, APInt::getSplat(Len, APInt(8, 0x33)));
19520 Srl = DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 2));
19521 SDValue AndRHS = GetMask(Srl, APInt::getSplat(Len, APInt(8, 0x33)));
19522 V = DAG.getNode(ISD::ADD, DL, VT, AndLHS, AndRHS);
19524 // v = (v + (v >> 4)) & 0x0F0F0F0F...
19525 Srl = DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 4));
19526 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, V, Srl);
19527 V = GetMask(Add, APInt::getSplat(Len, APInt(8, 0x0F)));
19529 // At this point, V contains the byte-wise population count, and we are
19530 // merely doing a horizontal sum if necessary to get the wider element
19532 if (EltVT == MVT::i8)
19535 return LowerHorizontalByteSum(
19536 DAG.getBitcast(MVT::getVectorVT(MVT::i8, VecSize / 8), V), VT, Subtarget,
19540 static SDValue LowerVectorCTPOP(SDValue Op, const X86Subtarget *Subtarget,
19541 SelectionDAG &DAG) {
19542 MVT VT = Op.getSimpleValueType();
19543 // FIXME: Need to add AVX-512 support here!
19544 assert((VT.is256BitVector() || VT.is128BitVector()) &&
19545 "Unknown CTPOP type to handle");
19546 SDLoc DL(Op.getNode());
19547 SDValue Op0 = Op.getOperand(0);
19549 if (!Subtarget->hasSSSE3()) {
19550 // We can't use the fast LUT approach, so fall back on vectorized bitmath.
19551 assert(VT.is128BitVector() && "Only 128-bit vectors supported in SSE!");
19552 return LowerVectorCTPOPBitmath(Op0, DL, Subtarget, DAG);
19555 if (VT.is256BitVector() && !Subtarget->hasInt256()) {
19556 unsigned NumElems = VT.getVectorNumElements();
19558 // Extract each 128-bit vector, compute pop count and concat the result.
19559 SDValue LHS = Extract128BitVector(Op0, 0, DAG, DL);
19560 SDValue RHS = Extract128BitVector(Op0, NumElems/2, DAG, DL);
19562 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT,
19563 LowerVectorCTPOPInRegLUT(LHS, DL, Subtarget, DAG),
19564 LowerVectorCTPOPInRegLUT(RHS, DL, Subtarget, DAG));
19567 return LowerVectorCTPOPInRegLUT(Op0, DL, Subtarget, DAG);
19570 static SDValue LowerCTPOP(SDValue Op, const X86Subtarget *Subtarget,
19571 SelectionDAG &DAG) {
19572 assert(Op.getSimpleValueType().isVector() &&
19573 "We only do custom lowering for vector population count.");
19574 return LowerVectorCTPOP(Op, Subtarget, DAG);
19577 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
19578 SDNode *Node = Op.getNode();
19580 EVT T = Node->getValueType(0);
19581 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
19582 DAG.getConstant(0, dl, T), Node->getOperand(2));
19583 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
19584 cast<AtomicSDNode>(Node)->getMemoryVT(),
19585 Node->getOperand(0),
19586 Node->getOperand(1), negOp,
19587 cast<AtomicSDNode>(Node)->getMemOperand(),
19588 cast<AtomicSDNode>(Node)->getOrdering(),
19589 cast<AtomicSDNode>(Node)->getSynchScope());
19592 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
19593 SDNode *Node = Op.getNode();
19595 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
19597 // Convert seq_cst store -> xchg
19598 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
19599 // FIXME: On 32-bit, store -> fist or movq would be more efficient
19600 // (The only way to get a 16-byte store is cmpxchg16b)
19601 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
19602 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
19603 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
19604 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
19605 cast<AtomicSDNode>(Node)->getMemoryVT(),
19606 Node->getOperand(0),
19607 Node->getOperand(1), Node->getOperand(2),
19608 cast<AtomicSDNode>(Node)->getMemOperand(),
19609 cast<AtomicSDNode>(Node)->getOrdering(),
19610 cast<AtomicSDNode>(Node)->getSynchScope());
19611 return Swap.getValue(1);
19613 // Other atomic stores have a simple pattern.
19617 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
19618 MVT VT = Op.getNode()->getSimpleValueType(0);
19620 // Let legalize expand this if it isn't a legal type yet.
19621 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
19624 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
19627 bool ExtraOp = false;
19628 switch (Op.getOpcode()) {
19629 default: llvm_unreachable("Invalid code");
19630 case ISD::ADDC: Opc = X86ISD::ADD; break;
19631 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
19632 case ISD::SUBC: Opc = X86ISD::SUB; break;
19633 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
19637 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19639 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19640 Op.getOperand(1), Op.getOperand(2));
19643 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
19644 SelectionDAG &DAG) {
19645 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
19647 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
19648 // which returns the values as { float, float } (in XMM0) or
19649 // { double, double } (which is returned in XMM0, XMM1).
19651 SDValue Arg = Op.getOperand(0);
19652 EVT ArgVT = Arg.getValueType();
19653 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
19655 TargetLowering::ArgListTy Args;
19656 TargetLowering::ArgListEntry Entry;
19660 Entry.isSExt = false;
19661 Entry.isZExt = false;
19662 Args.push_back(Entry);
19664 bool isF64 = ArgVT == MVT::f64;
19665 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
19666 // the small struct {f32, f32} is returned in (eax, edx). For f64,
19667 // the results are returned via SRet in memory.
19668 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
19669 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19671 DAG.getExternalSymbol(LibcallName, TLI.getPointerTy(DAG.getDataLayout()));
19673 Type *RetTy = isF64
19674 ? (Type*)StructType::get(ArgTy, ArgTy, nullptr)
19675 : (Type*)VectorType::get(ArgTy, 4);
19677 TargetLowering::CallLoweringInfo CLI(DAG);
19678 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
19679 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
19681 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
19684 // Returned in xmm0 and xmm1.
19685 return CallResult.first;
19687 // Returned in bits 0:31 and 32:64 xmm0.
19688 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19689 CallResult.first, DAG.getIntPtrConstant(0, dl));
19690 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19691 CallResult.first, DAG.getIntPtrConstant(1, dl));
19692 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
19693 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
19696 /// Widen a vector input to a vector of NVT. The
19697 /// input vector must have the same element type as NVT.
19698 static SDValue ExtendToType(SDValue InOp, MVT NVT, SelectionDAG &DAG,
19699 bool FillWithZeroes = false) {
19700 // Check if InOp already has the right width.
19701 MVT InVT = InOp.getSimpleValueType();
19705 if (InOp.isUndef())
19706 return DAG.getUNDEF(NVT);
19708 assert(InVT.getVectorElementType() == NVT.getVectorElementType() &&
19709 "input and widen element type must match");
19711 unsigned InNumElts = InVT.getVectorNumElements();
19712 unsigned WidenNumElts = NVT.getVectorNumElements();
19713 assert(WidenNumElts > InNumElts && WidenNumElts % InNumElts == 0 &&
19714 "Unexpected request for vector widening");
19716 EVT EltVT = NVT.getVectorElementType();
19719 if (ISD::isBuildVectorOfConstantSDNodes(InOp.getNode()) ||
19720 ISD::isBuildVectorOfConstantFPSDNodes(InOp.getNode())) {
19721 SmallVector<SDValue, 16> Ops;
19722 for (unsigned i = 0; i < InNumElts; ++i)
19723 Ops.push_back(InOp.getOperand(i));
19725 SDValue FillVal = FillWithZeroes ? DAG.getConstant(0, dl, EltVT) :
19726 DAG.getUNDEF(EltVT);
19727 for (unsigned i = 0; i < WidenNumElts - InNumElts; ++i)
19728 Ops.push_back(FillVal);
19729 return DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, Ops);
19731 SDValue FillVal = FillWithZeroes ? DAG.getConstant(0, dl, NVT) :
19733 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, NVT, FillVal,
19734 InOp, DAG.getIntPtrConstant(0, dl));
19737 static SDValue LowerMSCATTER(SDValue Op, const X86Subtarget *Subtarget,
19738 SelectionDAG &DAG) {
19739 assert(Subtarget->hasAVX512() &&
19740 "MGATHER/MSCATTER are supported on AVX-512 arch only");
19742 MaskedScatterSDNode *N = cast<MaskedScatterSDNode>(Op.getNode());
19743 MVT VT = N->getValue().getSimpleValueType();
19744 assert(VT.getScalarSizeInBits() >= 32 && "Unsupported scatter op");
19747 // X86 scatter kills mask register, so its type should be added to
19748 // the list of return values
19749 if (N->getNumValues() == 1) {
19750 SDValue Index = N->getIndex();
19751 if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
19752 !Index.getSimpleValueType().is512BitVector())
19753 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
19755 SDVTList VTs = DAG.getVTList(N->getMask().getValueType(), MVT::Other);
19756 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
19757 N->getOperand(3), Index };
19759 SDValue NewScatter = DAG.getMaskedScatter(VTs, VT, dl, Ops, N->getMemOperand());
19760 DAG.ReplaceAllUsesWith(Op, SDValue(NewScatter.getNode(), 1));
19761 return SDValue(NewScatter.getNode(), 0);
19766 static SDValue LowerMLOAD(SDValue Op, const X86Subtarget *Subtarget,
19767 SelectionDAG &DAG) {
19769 MaskedLoadSDNode *N = cast<MaskedLoadSDNode>(Op.getNode());
19770 MVT VT = Op.getSimpleValueType();
19771 SDValue Mask = N->getMask();
19774 if (Subtarget->hasAVX512() && !Subtarget->hasVLX() &&
19775 !VT.is512BitVector() && Mask.getValueType() == MVT::v8i1) {
19776 // This operation is legal for targets with VLX, but without
19777 // VLX the vector should be widened to 512 bit
19778 unsigned NumEltsInWideVec = 512/VT.getScalarSizeInBits();
19779 MVT WideDataVT = MVT::getVectorVT(VT.getScalarType(), NumEltsInWideVec);
19780 MVT WideMaskVT = MVT::getVectorVT(MVT::i1, NumEltsInWideVec);
19781 SDValue Src0 = N->getSrc0();
19782 Src0 = ExtendToType(Src0, WideDataVT, DAG);
19783 Mask = ExtendToType(Mask, WideMaskVT, DAG, true);
19784 SDValue NewLoad = DAG.getMaskedLoad(WideDataVT, dl, N->getChain(),
19785 N->getBasePtr(), Mask, Src0,
19786 N->getMemoryVT(), N->getMemOperand(),
19787 N->getExtensionType());
19789 SDValue Exract = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
19790 NewLoad.getValue(0),
19791 DAG.getIntPtrConstant(0, dl));
19792 SDValue RetOps[] = {Exract, NewLoad.getValue(1)};
19793 return DAG.getMergeValues(RetOps, dl);
19798 static SDValue LowerMSTORE(SDValue Op, const X86Subtarget *Subtarget,
19799 SelectionDAG &DAG) {
19800 MaskedStoreSDNode *N = cast<MaskedStoreSDNode>(Op.getNode());
19801 SDValue DataToStore = N->getValue();
19802 MVT VT = DataToStore.getSimpleValueType();
19803 SDValue Mask = N->getMask();
19806 if (Subtarget->hasAVX512() && !Subtarget->hasVLX() &&
19807 !VT.is512BitVector() && Mask.getValueType() == MVT::v8i1) {
19808 // This operation is legal for targets with VLX, but without
19809 // VLX the vector should be widened to 512 bit
19810 unsigned NumEltsInWideVec = 512/VT.getScalarSizeInBits();
19811 MVT WideDataVT = MVT::getVectorVT(VT.getScalarType(), NumEltsInWideVec);
19812 MVT WideMaskVT = MVT::getVectorVT(MVT::i1, NumEltsInWideVec);
19813 DataToStore = ExtendToType(DataToStore, WideDataVT, DAG);
19814 Mask = ExtendToType(Mask, WideMaskVT, DAG, true);
19815 return DAG.getMaskedStore(N->getChain(), dl, DataToStore, N->getBasePtr(),
19816 Mask, N->getMemoryVT(), N->getMemOperand(),
19817 N->isTruncatingStore());
19822 static SDValue LowerMGATHER(SDValue Op, const X86Subtarget *Subtarget,
19823 SelectionDAG &DAG) {
19824 assert(Subtarget->hasAVX512() &&
19825 "MGATHER/MSCATTER are supported on AVX-512 arch only");
19827 MaskedGatherSDNode *N = cast<MaskedGatherSDNode>(Op.getNode());
19828 MVT VT = Op.getSimpleValueType();
19829 assert(VT.getScalarSizeInBits() >= 32 && "Unsupported gather op");
19832 SDValue Index = N->getIndex();
19833 if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
19834 !Index.getSimpleValueType().is512BitVector()) {
19835 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
19836 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
19837 N->getOperand(3), Index };
19838 DAG.UpdateNodeOperands(N, Ops);
19843 SDValue X86TargetLowering::LowerGC_TRANSITION_START(SDValue Op,
19844 SelectionDAG &DAG) const {
19845 // TODO: Eventually, the lowering of these nodes should be informed by or
19846 // deferred to the GC strategy for the function in which they appear. For
19847 // now, however, they must be lowered to something. Since they are logically
19848 // no-ops in the case of a null GC strategy (or a GC strategy which does not
19849 // require special handling for these nodes), lower them as literal NOOPs for
19851 SmallVector<SDValue, 2> Ops;
19853 Ops.push_back(Op.getOperand(0));
19854 if (Op->getGluedNode())
19855 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
19858 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
19859 SDValue NOOP(DAG.getMachineNode(X86::NOOP, SDLoc(Op), VTs, Ops), 0);
19864 SDValue X86TargetLowering::LowerGC_TRANSITION_END(SDValue Op,
19865 SelectionDAG &DAG) const {
19866 // TODO: Eventually, the lowering of these nodes should be informed by or
19867 // deferred to the GC strategy for the function in which they appear. For
19868 // now, however, they must be lowered to something. Since they are logically
19869 // no-ops in the case of a null GC strategy (or a GC strategy which does not
19870 // require special handling for these nodes), lower them as literal NOOPs for
19872 SmallVector<SDValue, 2> Ops;
19874 Ops.push_back(Op.getOperand(0));
19875 if (Op->getGluedNode())
19876 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
19879 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
19880 SDValue NOOP(DAG.getMachineNode(X86::NOOP, SDLoc(Op), VTs, Ops), 0);
19885 /// LowerOperation - Provide custom lowering hooks for some operations.
19887 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
19888 switch (Op.getOpcode()) {
19889 default: llvm_unreachable("Should not custom lower this!");
19890 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
19891 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
19892 return LowerCMP_SWAP(Op, Subtarget, DAG);
19893 case ISD::CTPOP: return LowerCTPOP(Op, Subtarget, DAG);
19894 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
19895 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
19896 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
19897 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, Subtarget, DAG);
19898 case ISD::VECTOR_SHUFFLE: return lowerVectorShuffle(Op, Subtarget, DAG);
19899 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
19900 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
19901 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
19902 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
19903 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
19904 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
19905 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
19906 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
19907 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
19908 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
19909 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
19910 case ISD::SHL_PARTS:
19911 case ISD::SRA_PARTS:
19912 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
19913 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
19914 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
19915 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
19916 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
19917 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
19918 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
19919 case ISD::SIGN_EXTEND_VECTOR_INREG:
19920 return LowerSIGN_EXTEND_VECTOR_INREG(Op, Subtarget, DAG);
19921 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
19922 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
19923 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
19924 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
19926 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
19927 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
19928 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
19929 case ISD::SETCC: return LowerSETCC(Op, DAG);
19930 case ISD::SETCCE: return LowerSETCCE(Op, DAG);
19931 case ISD::SELECT: return LowerSELECT(Op, DAG);
19932 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
19933 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
19934 case ISD::VASTART: return LowerVASTART(Op, DAG);
19935 case ISD::VAARG: return LowerVAARG(Op, DAG);
19936 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
19937 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, Subtarget, DAG);
19938 case ISD::INTRINSIC_VOID:
19939 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
19940 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
19941 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
19942 case ISD::FRAME_TO_ARGS_OFFSET:
19943 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
19944 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
19945 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
19946 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
19947 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
19948 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
19949 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
19950 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
19951 case ISD::CTLZ: return LowerCTLZ(Op, Subtarget, DAG);
19952 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, Subtarget, DAG);
19954 case ISD::CTTZ_ZERO_UNDEF: return LowerCTTZ(Op, DAG);
19955 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
19956 case ISD::UMUL_LOHI:
19957 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
19958 case ISD::ROTL: return LowerRotate(Op, Subtarget, DAG);
19961 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
19967 case ISD::UMULO: return LowerXALUO(Op, DAG);
19968 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
19969 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
19973 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
19974 case ISD::ADD: return LowerADD(Op, DAG);
19975 case ISD::SUB: return LowerSUB(Op, DAG);
19979 case ISD::UMIN: return LowerMINMAX(Op, DAG);
19980 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
19981 case ISD::MLOAD: return LowerMLOAD(Op, Subtarget, DAG);
19982 case ISD::MSTORE: return LowerMSTORE(Op, Subtarget, DAG);
19983 case ISD::MGATHER: return LowerMGATHER(Op, Subtarget, DAG);
19984 case ISD::MSCATTER: return LowerMSCATTER(Op, Subtarget, DAG);
19985 case ISD::GC_TRANSITION_START:
19986 return LowerGC_TRANSITION_START(Op, DAG);
19987 case ISD::GC_TRANSITION_END: return LowerGC_TRANSITION_END(Op, DAG);
19991 /// ReplaceNodeResults - Replace a node with an illegal result type
19992 /// with a new node built out of custom code.
19993 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
19994 SmallVectorImpl<SDValue>&Results,
19995 SelectionDAG &DAG) const {
19997 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19998 switch (N->getOpcode()) {
20000 llvm_unreachable("Do not know how to custom type legalize this operation!");
20001 case X86ISD::AVG: {
20002 // Legalize types for X86ISD::AVG by expanding vectors.
20003 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
20005 auto InVT = N->getValueType(0);
20006 auto InVTSize = InVT.getSizeInBits();
20007 const unsigned RegSize =
20008 (InVTSize > 128) ? ((InVTSize > 256) ? 512 : 256) : 128;
20009 assert((!Subtarget->hasAVX512() || RegSize < 512) &&
20010 "512-bit vector requires AVX512");
20011 assert((!Subtarget->hasAVX2() || RegSize < 256) &&
20012 "256-bit vector requires AVX2");
20014 auto ElemVT = InVT.getVectorElementType();
20015 auto RegVT = EVT::getVectorVT(*DAG.getContext(), ElemVT,
20016 RegSize / ElemVT.getSizeInBits());
20017 assert(RegSize % InVT.getSizeInBits() == 0);
20018 unsigned NumConcat = RegSize / InVT.getSizeInBits();
20020 SmallVector<SDValue, 16> Ops(NumConcat, DAG.getUNDEF(InVT));
20021 Ops[0] = N->getOperand(0);
20022 SDValue InVec0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, RegVT, Ops);
20023 Ops[0] = N->getOperand(1);
20024 SDValue InVec1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, RegVT, Ops);
20026 SDValue Res = DAG.getNode(X86ISD::AVG, dl, RegVT, InVec0, InVec1);
20027 Results.push_back(DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InVT, Res,
20028 DAG.getIntPtrConstant(0, dl)));
20031 // We might have generated v2f32 FMIN/FMAX operations. Widen them to v4f32.
20032 case X86ISD::FMINC:
20034 case X86ISD::FMAXC:
20035 case X86ISD::FMAX: {
20036 EVT VT = N->getValueType(0);
20037 assert(VT == MVT::v2f32 && "Unexpected type (!= v2f32) on FMIN/FMAX.");
20038 SDValue UNDEF = DAG.getUNDEF(VT);
20039 SDValue LHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
20040 N->getOperand(0), UNDEF);
20041 SDValue RHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
20042 N->getOperand(1), UNDEF);
20043 Results.push_back(DAG.getNode(N->getOpcode(), dl, MVT::v4f32, LHS, RHS));
20046 case ISD::SIGN_EXTEND_INREG:
20051 // We don't want to expand or promote these.
20058 case ISD::UDIVREM: {
20059 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
20060 Results.push_back(V);
20063 case ISD::FP_TO_SINT:
20064 case ISD::FP_TO_UINT: {
20065 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
20067 std::pair<SDValue,SDValue> Vals =
20068 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
20069 SDValue FIST = Vals.first, StackSlot = Vals.second;
20070 if (FIST.getNode()) {
20071 EVT VT = N->getValueType(0);
20072 // Return a load from the stack slot.
20073 if (StackSlot.getNode())
20074 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
20075 MachinePointerInfo(),
20076 false, false, false, 0));
20078 Results.push_back(FIST);
20082 case ISD::UINT_TO_FP: {
20083 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
20084 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
20085 N->getValueType(0) != MVT::v2f32)
20087 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
20089 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
20091 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
20092 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
20093 DAG.getBitcast(MVT::v2i64, VBias));
20094 Or = DAG.getBitcast(MVT::v2f64, Or);
20095 // TODO: Are there any fast-math-flags to propagate here?
20096 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
20097 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
20100 case ISD::FP_ROUND: {
20101 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
20103 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
20104 Results.push_back(V);
20107 case ISD::FP_EXTEND: {
20108 // Right now, only MVT::v2f32 has OperationAction for FP_EXTEND.
20109 // No other ValueType for FP_EXTEND should reach this point.
20110 assert(N->getValueType(0) == MVT::v2f32 &&
20111 "Do not know how to legalize this Node");
20114 case ISD::INTRINSIC_W_CHAIN: {
20115 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
20117 default : llvm_unreachable("Do not know how to custom type "
20118 "legalize this intrinsic operation!");
20119 case Intrinsic::x86_rdtsc:
20120 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
20122 case Intrinsic::x86_rdtscp:
20123 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
20125 case Intrinsic::x86_rdpmc:
20126 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
20129 case ISD::INTRINSIC_WO_CHAIN: {
20130 if (SDValue V = LowerINTRINSIC_WO_CHAIN(SDValue(N, 0), Subtarget, DAG))
20131 Results.push_back(V);
20134 case ISD::READCYCLECOUNTER: {
20135 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
20138 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
20139 EVT T = N->getValueType(0);
20140 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
20141 bool Regs64bit = T == MVT::i128;
20142 MVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
20143 SDValue cpInL, cpInH;
20144 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
20145 DAG.getConstant(0, dl, HalfT));
20146 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
20147 DAG.getConstant(1, dl, HalfT));
20148 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
20149 Regs64bit ? X86::RAX : X86::EAX,
20151 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
20152 Regs64bit ? X86::RDX : X86::EDX,
20153 cpInH, cpInL.getValue(1));
20154 SDValue swapInL, swapInH;
20155 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
20156 DAG.getConstant(0, dl, HalfT));
20157 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
20158 DAG.getConstant(1, dl, HalfT));
20159 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
20160 Regs64bit ? X86::RBX : X86::EBX,
20161 swapInL, cpInH.getValue(1));
20162 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
20163 Regs64bit ? X86::RCX : X86::ECX,
20164 swapInH, swapInL.getValue(1));
20165 SDValue Ops[] = { swapInH.getValue(0),
20167 swapInH.getValue(1) };
20168 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
20169 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
20170 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
20171 X86ISD::LCMPXCHG8_DAG;
20172 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
20173 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
20174 Regs64bit ? X86::RAX : X86::EAX,
20175 HalfT, Result.getValue(1));
20176 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
20177 Regs64bit ? X86::RDX : X86::EDX,
20178 HalfT, cpOutL.getValue(2));
20179 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
20181 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
20182 MVT::i32, cpOutH.getValue(2));
20184 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
20185 DAG.getConstant(X86::COND_E, dl, MVT::i8), EFLAGS);
20186 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
20188 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
20189 Results.push_back(Success);
20190 Results.push_back(EFLAGS.getValue(1));
20193 case ISD::ATOMIC_SWAP:
20194 case ISD::ATOMIC_LOAD_ADD:
20195 case ISD::ATOMIC_LOAD_SUB:
20196 case ISD::ATOMIC_LOAD_AND:
20197 case ISD::ATOMIC_LOAD_OR:
20198 case ISD::ATOMIC_LOAD_XOR:
20199 case ISD::ATOMIC_LOAD_NAND:
20200 case ISD::ATOMIC_LOAD_MIN:
20201 case ISD::ATOMIC_LOAD_MAX:
20202 case ISD::ATOMIC_LOAD_UMIN:
20203 case ISD::ATOMIC_LOAD_UMAX:
20204 case ISD::ATOMIC_LOAD: {
20205 // Delegate to generic TypeLegalization. Situations we can really handle
20206 // should have already been dealt with by AtomicExpandPass.cpp.
20209 case ISD::BITCAST: {
20210 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
20211 EVT DstVT = N->getValueType(0);
20212 EVT SrcVT = N->getOperand(0)->getValueType(0);
20214 if (SrcVT != MVT::f64 ||
20215 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
20218 unsigned NumElts = DstVT.getVectorNumElements();
20219 EVT SVT = DstVT.getVectorElementType();
20220 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
20221 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
20222 MVT::v2f64, N->getOperand(0));
20223 SDValue ToVecInt = DAG.getBitcast(WiderVT, Expanded);
20225 if (ExperimentalVectorWideningLegalization) {
20226 // If we are legalizing vectors by widening, we already have the desired
20227 // legal vector type, just return it.
20228 Results.push_back(ToVecInt);
20232 SmallVector<SDValue, 8> Elts;
20233 for (unsigned i = 0, e = NumElts; i != e; ++i)
20234 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
20235 ToVecInt, DAG.getIntPtrConstant(i, dl)));
20237 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
20242 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
20243 switch ((X86ISD::NodeType)Opcode) {
20244 case X86ISD::FIRST_NUMBER: break;
20245 case X86ISD::BSF: return "X86ISD::BSF";
20246 case X86ISD::BSR: return "X86ISD::BSR";
20247 case X86ISD::SHLD: return "X86ISD::SHLD";
20248 case X86ISD::SHRD: return "X86ISD::SHRD";
20249 case X86ISD::FAND: return "X86ISD::FAND";
20250 case X86ISD::FANDN: return "X86ISD::FANDN";
20251 case X86ISD::FOR: return "X86ISD::FOR";
20252 case X86ISD::FXOR: return "X86ISD::FXOR";
20253 case X86ISD::FILD: return "X86ISD::FILD";
20254 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
20255 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
20256 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
20257 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
20258 case X86ISD::FLD: return "X86ISD::FLD";
20259 case X86ISD::FST: return "X86ISD::FST";
20260 case X86ISD::CALL: return "X86ISD::CALL";
20261 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
20262 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
20263 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
20264 case X86ISD::BT: return "X86ISD::BT";
20265 case X86ISD::CMP: return "X86ISD::CMP";
20266 case X86ISD::COMI: return "X86ISD::COMI";
20267 case X86ISD::UCOMI: return "X86ISD::UCOMI";
20268 case X86ISD::CMPM: return "X86ISD::CMPM";
20269 case X86ISD::CMPMU: return "X86ISD::CMPMU";
20270 case X86ISD::CMPM_RND: return "X86ISD::CMPM_RND";
20271 case X86ISD::SETCC: return "X86ISD::SETCC";
20272 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
20273 case X86ISD::FSETCC: return "X86ISD::FSETCC";
20274 case X86ISD::FGETSIGNx86: return "X86ISD::FGETSIGNx86";
20275 case X86ISD::CMOV: return "X86ISD::CMOV";
20276 case X86ISD::BRCOND: return "X86ISD::BRCOND";
20277 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
20278 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
20279 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
20280 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
20281 case X86ISD::Wrapper: return "X86ISD::Wrapper";
20282 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
20283 case X86ISD::MOVDQ2Q: return "X86ISD::MOVDQ2Q";
20284 case X86ISD::MMX_MOVD2W: return "X86ISD::MMX_MOVD2W";
20285 case X86ISD::MMX_MOVW2D: return "X86ISD::MMX_MOVW2D";
20286 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
20287 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
20288 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
20289 case X86ISD::PINSRB: return "X86ISD::PINSRB";
20290 case X86ISD::PINSRW: return "X86ISD::PINSRW";
20291 case X86ISD::MMX_PINSRW: return "X86ISD::MMX_PINSRW";
20292 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
20293 case X86ISD::ANDNP: return "X86ISD::ANDNP";
20294 case X86ISD::PSIGN: return "X86ISD::PSIGN";
20295 case X86ISD::BLENDI: return "X86ISD::BLENDI";
20296 case X86ISD::SHRUNKBLEND: return "X86ISD::SHRUNKBLEND";
20297 case X86ISD::ADDUS: return "X86ISD::ADDUS";
20298 case X86ISD::SUBUS: return "X86ISD::SUBUS";
20299 case X86ISD::HADD: return "X86ISD::HADD";
20300 case X86ISD::HSUB: return "X86ISD::HSUB";
20301 case X86ISD::FHADD: return "X86ISD::FHADD";
20302 case X86ISD::FHSUB: return "X86ISD::FHSUB";
20303 case X86ISD::ABS: return "X86ISD::ABS";
20304 case X86ISD::CONFLICT: return "X86ISD::CONFLICT";
20305 case X86ISD::FMAX: return "X86ISD::FMAX";
20306 case X86ISD::FMAX_RND: return "X86ISD::FMAX_RND";
20307 case X86ISD::FMIN: return "X86ISD::FMIN";
20308 case X86ISD::FMIN_RND: return "X86ISD::FMIN_RND";
20309 case X86ISD::FMAXC: return "X86ISD::FMAXC";
20310 case X86ISD::FMINC: return "X86ISD::FMINC";
20311 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
20312 case X86ISD::FRCP: return "X86ISD::FRCP";
20313 case X86ISD::EXTRQI: return "X86ISD::EXTRQI";
20314 case X86ISD::INSERTQI: return "X86ISD::INSERTQI";
20315 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
20316 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
20317 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
20318 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
20319 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
20320 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
20321 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
20322 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
20323 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
20324 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
20325 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
20326 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
20327 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
20328 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
20329 case X86ISD::VZEXT: return "X86ISD::VZEXT";
20330 case X86ISD::VSEXT: return "X86ISD::VSEXT";
20331 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
20332 case X86ISD::VTRUNCS: return "X86ISD::VTRUNCS";
20333 case X86ISD::VTRUNCUS: return "X86ISD::VTRUNCUS";
20334 case X86ISD::VINSERT: return "X86ISD::VINSERT";
20335 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
20336 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
20337 case X86ISD::CVTDQ2PD: return "X86ISD::CVTDQ2PD";
20338 case X86ISD::CVTUDQ2PD: return "X86ISD::CVTUDQ2PD";
20339 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
20340 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
20341 case X86ISD::VSHL: return "X86ISD::VSHL";
20342 case X86ISD::VSRL: return "X86ISD::VSRL";
20343 case X86ISD::VSRA: return "X86ISD::VSRA";
20344 case X86ISD::VSHLI: return "X86ISD::VSHLI";
20345 case X86ISD::VSRLI: return "X86ISD::VSRLI";
20346 case X86ISD::VSRAI: return "X86ISD::VSRAI";
20347 case X86ISD::CMPP: return "X86ISD::CMPP";
20348 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
20349 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
20350 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
20351 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
20352 case X86ISD::ADD: return "X86ISD::ADD";
20353 case X86ISD::SUB: return "X86ISD::SUB";
20354 case X86ISD::ADC: return "X86ISD::ADC";
20355 case X86ISD::SBB: return "X86ISD::SBB";
20356 case X86ISD::SMUL: return "X86ISD::SMUL";
20357 case X86ISD::UMUL: return "X86ISD::UMUL";
20358 case X86ISD::SMUL8: return "X86ISD::SMUL8";
20359 case X86ISD::UMUL8: return "X86ISD::UMUL8";
20360 case X86ISD::SDIVREM8_SEXT_HREG: return "X86ISD::SDIVREM8_SEXT_HREG";
20361 case X86ISD::UDIVREM8_ZEXT_HREG: return "X86ISD::UDIVREM8_ZEXT_HREG";
20362 case X86ISD::INC: return "X86ISD::INC";
20363 case X86ISD::DEC: return "X86ISD::DEC";
20364 case X86ISD::OR: return "X86ISD::OR";
20365 case X86ISD::XOR: return "X86ISD::XOR";
20366 case X86ISD::AND: return "X86ISD::AND";
20367 case X86ISD::BEXTR: return "X86ISD::BEXTR";
20368 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
20369 case X86ISD::PTEST: return "X86ISD::PTEST";
20370 case X86ISD::TESTP: return "X86ISD::TESTP";
20371 case X86ISD::TESTM: return "X86ISD::TESTM";
20372 case X86ISD::TESTNM: return "X86ISD::TESTNM";
20373 case X86ISD::KORTEST: return "X86ISD::KORTEST";
20374 case X86ISD::KTEST: return "X86ISD::KTEST";
20375 case X86ISD::PACKSS: return "X86ISD::PACKSS";
20376 case X86ISD::PACKUS: return "X86ISD::PACKUS";
20377 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
20378 case X86ISD::VALIGN: return "X86ISD::VALIGN";
20379 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
20380 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
20381 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
20382 case X86ISD::SHUFP: return "X86ISD::SHUFP";
20383 case X86ISD::SHUF128: return "X86ISD::SHUF128";
20384 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
20385 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
20386 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
20387 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
20388 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
20389 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
20390 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
20391 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
20392 case X86ISD::MOVSD: return "X86ISD::MOVSD";
20393 case X86ISD::MOVSS: return "X86ISD::MOVSS";
20394 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
20395 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
20396 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
20397 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
20398 case X86ISD::SUBV_BROADCAST: return "X86ISD::SUBV_BROADCAST";
20399 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
20400 case X86ISD::VPERMILPV: return "X86ISD::VPERMILPV";
20401 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
20402 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
20403 case X86ISD::VPERMV: return "X86ISD::VPERMV";
20404 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
20405 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
20406 case X86ISD::VPERMI: return "X86ISD::VPERMI";
20407 case X86ISD::VPTERNLOG: return "X86ISD::VPTERNLOG";
20408 case X86ISD::VFIXUPIMM: return "X86ISD::VFIXUPIMM";
20409 case X86ISD::VRANGE: return "X86ISD::VRANGE";
20410 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
20411 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
20412 case X86ISD::PSADBW: return "X86ISD::PSADBW";
20413 case X86ISD::DBPSADBW: return "X86ISD::DBPSADBW";
20414 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
20415 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
20416 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
20417 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
20418 case X86ISD::MFENCE: return "X86ISD::MFENCE";
20419 case X86ISD::SFENCE: return "X86ISD::SFENCE";
20420 case X86ISD::LFENCE: return "X86ISD::LFENCE";
20421 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
20422 case X86ISD::SAHF: return "X86ISD::SAHF";
20423 case X86ISD::RDRAND: return "X86ISD::RDRAND";
20424 case X86ISD::RDSEED: return "X86ISD::RDSEED";
20425 case X86ISD::VPMADDUBSW: return "X86ISD::VPMADDUBSW";
20426 case X86ISD::VPMADDWD: return "X86ISD::VPMADDWD";
20427 case X86ISD::VPROT: return "X86ISD::VPROT";
20428 case X86ISD::VPROTI: return "X86ISD::VPROTI";
20429 case X86ISD::VPSHA: return "X86ISD::VPSHA";
20430 case X86ISD::VPSHL: return "X86ISD::VPSHL";
20431 case X86ISD::VPCOM: return "X86ISD::VPCOM";
20432 case X86ISD::VPCOMU: return "X86ISD::VPCOMU";
20433 case X86ISD::FMADD: return "X86ISD::FMADD";
20434 case X86ISD::FMSUB: return "X86ISD::FMSUB";
20435 case X86ISD::FNMADD: return "X86ISD::FNMADD";
20436 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
20437 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
20438 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
20439 case X86ISD::FMADD_RND: return "X86ISD::FMADD_RND";
20440 case X86ISD::FNMADD_RND: return "X86ISD::FNMADD_RND";
20441 case X86ISD::FMSUB_RND: return "X86ISD::FMSUB_RND";
20442 case X86ISD::FNMSUB_RND: return "X86ISD::FNMSUB_RND";
20443 case X86ISD::FMADDSUB_RND: return "X86ISD::FMADDSUB_RND";
20444 case X86ISD::FMSUBADD_RND: return "X86ISD::FMSUBADD_RND";
20445 case X86ISD::VRNDSCALE: return "X86ISD::VRNDSCALE";
20446 case X86ISD::VREDUCE: return "X86ISD::VREDUCE";
20447 case X86ISD::VGETMANT: return "X86ISD::VGETMANT";
20448 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
20449 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
20450 case X86ISD::XTEST: return "X86ISD::XTEST";
20451 case X86ISD::COMPRESS: return "X86ISD::COMPRESS";
20452 case X86ISD::EXPAND: return "X86ISD::EXPAND";
20453 case X86ISD::SELECT: return "X86ISD::SELECT";
20454 case X86ISD::ADDSUB: return "X86ISD::ADDSUB";
20455 case X86ISD::RCP28: return "X86ISD::RCP28";
20456 case X86ISD::EXP2: return "X86ISD::EXP2";
20457 case X86ISD::RSQRT28: return "X86ISD::RSQRT28";
20458 case X86ISD::FADD_RND: return "X86ISD::FADD_RND";
20459 case X86ISD::FSUB_RND: return "X86ISD::FSUB_RND";
20460 case X86ISD::FMUL_RND: return "X86ISD::FMUL_RND";
20461 case X86ISD::FDIV_RND: return "X86ISD::FDIV_RND";
20462 case X86ISD::FSQRT_RND: return "X86ISD::FSQRT_RND";
20463 case X86ISD::FGETEXP_RND: return "X86ISD::FGETEXP_RND";
20464 case X86ISD::SCALEF: return "X86ISD::SCALEF";
20465 case X86ISD::ADDS: return "X86ISD::ADDS";
20466 case X86ISD::SUBS: return "X86ISD::SUBS";
20467 case X86ISD::AVG: return "X86ISD::AVG";
20468 case X86ISD::MULHRS: return "X86ISD::MULHRS";
20469 case X86ISD::SINT_TO_FP_RND: return "X86ISD::SINT_TO_FP_RND";
20470 case X86ISD::UINT_TO_FP_RND: return "X86ISD::UINT_TO_FP_RND";
20471 case X86ISD::FP_TO_SINT_RND: return "X86ISD::FP_TO_SINT_RND";
20472 case X86ISD::FP_TO_UINT_RND: return "X86ISD::FP_TO_UINT_RND";
20473 case X86ISD::VFPCLASS: return "X86ISD::VFPCLASS";
20474 case X86ISD::VFPCLASSS: return "X86ISD::VFPCLASSS";
20479 // isLegalAddressingMode - Return true if the addressing mode represented
20480 // by AM is legal for this target, for a load/store of the specified type.
20481 bool X86TargetLowering::isLegalAddressingMode(const DataLayout &DL,
20482 const AddrMode &AM, Type *Ty,
20483 unsigned AS) const {
20484 // X86 supports extremely general addressing modes.
20485 CodeModel::Model M = getTargetMachine().getCodeModel();
20486 Reloc::Model R = getTargetMachine().getRelocationModel();
20488 // X86 allows a sign-extended 32-bit immediate field as a displacement.
20489 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
20494 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
20496 // If a reference to this global requires an extra load, we can't fold it.
20497 if (isGlobalStubReference(GVFlags))
20500 // If BaseGV requires a register for the PIC base, we cannot also have a
20501 // BaseReg specified.
20502 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
20505 // If lower 4G is not available, then we must use rip-relative addressing.
20506 if ((M != CodeModel::Small || R != Reloc::Static) &&
20507 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
20511 switch (AM.Scale) {
20517 // These scales always work.
20522 // These scales are formed with basereg+scalereg. Only accept if there is
20527 default: // Other stuff never works.
20534 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
20535 unsigned Bits = Ty->getScalarSizeInBits();
20537 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
20538 // particularly cheaper than those without.
20542 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
20543 // variable shifts just as cheap as scalar ones.
20544 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
20547 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
20548 // fully general vector.
20552 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
20553 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
20555 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
20556 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
20557 return NumBits1 > NumBits2;
20560 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
20561 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
20564 if (!isTypeLegal(EVT::getEVT(Ty1)))
20567 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
20569 // Assuming the caller doesn't have a zeroext or signext return parameter,
20570 // truncation all the way down to i1 is valid.
20574 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
20575 return isInt<32>(Imm);
20578 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
20579 // Can also use sub to handle negated immediates.
20580 return isInt<32>(Imm);
20583 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
20584 if (!VT1.isInteger() || !VT2.isInteger())
20586 unsigned NumBits1 = VT1.getSizeInBits();
20587 unsigned NumBits2 = VT2.getSizeInBits();
20588 return NumBits1 > NumBits2;
20591 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
20592 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
20593 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
20596 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
20597 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
20598 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
20601 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
20602 EVT VT1 = Val.getValueType();
20603 if (isZExtFree(VT1, VT2))
20606 if (Val.getOpcode() != ISD::LOAD)
20609 if (!VT1.isSimple() || !VT1.isInteger() ||
20610 !VT2.isSimple() || !VT2.isInteger())
20613 switch (VT1.getSimpleVT().SimpleTy) {
20618 // X86 has 8, 16, and 32-bit zero-extending loads.
20625 bool X86TargetLowering::isVectorLoadExtDesirable(SDValue) const { return true; }
20628 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
20629 if (!Subtarget->hasAnyFMA())
20632 VT = VT.getScalarType();
20634 if (!VT.isSimple())
20637 switch (VT.getSimpleVT().SimpleTy) {
20648 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
20649 // i16 instructions are longer (0x66 prefix) and potentially slower.
20650 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
20653 /// isShuffleMaskLegal - Targets can use this to indicate that they only
20654 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
20655 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
20656 /// are assumed to be legal.
20658 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
20660 if (!VT.isSimple())
20663 // Not for i1 vectors
20664 if (VT.getSimpleVT().getScalarType() == MVT::i1)
20667 // Very little shuffling can be done for 64-bit vectors right now.
20668 if (VT.getSimpleVT().getSizeInBits() == 64)
20671 // We only care that the types being shuffled are legal. The lowering can
20672 // handle any possible shuffle mask that results.
20673 return isTypeLegal(VT.getSimpleVT());
20677 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
20679 // Just delegate to the generic legality, clear masks aren't special.
20680 return isShuffleMaskLegal(Mask, VT);
20683 //===----------------------------------------------------------------------===//
20684 // X86 Scheduler Hooks
20685 //===----------------------------------------------------------------------===//
20687 /// Utility function to emit xbegin specifying the start of an RTM region.
20688 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
20689 const TargetInstrInfo *TII) {
20690 DebugLoc DL = MI->getDebugLoc();
20692 const BasicBlock *BB = MBB->getBasicBlock();
20693 MachineFunction::iterator I = ++MBB->getIterator();
20695 // For the v = xbegin(), we generate
20706 MachineBasicBlock *thisMBB = MBB;
20707 MachineFunction *MF = MBB->getParent();
20708 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
20709 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
20710 MF->insert(I, mainMBB);
20711 MF->insert(I, sinkMBB);
20713 // Transfer the remainder of BB and its successor edges to sinkMBB.
20714 sinkMBB->splice(sinkMBB->begin(), MBB,
20715 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20716 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
20720 // # fallthrough to mainMBB
20721 // # abortion to sinkMBB
20722 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
20723 thisMBB->addSuccessor(mainMBB);
20724 thisMBB->addSuccessor(sinkMBB);
20728 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
20729 mainMBB->addSuccessor(sinkMBB);
20732 // EAX is live into the sinkMBB
20733 sinkMBB->addLiveIn(X86::EAX);
20734 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20735 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20738 MI->eraseFromParent();
20742 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
20743 // or XMM0_V32I8 in AVX all of this code can be replaced with that
20744 // in the .td file.
20745 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
20746 const TargetInstrInfo *TII) {
20748 switch (MI->getOpcode()) {
20749 default: llvm_unreachable("illegal opcode!");
20750 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
20751 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
20752 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
20753 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
20754 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
20755 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
20756 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
20757 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
20760 DebugLoc dl = MI->getDebugLoc();
20761 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20763 unsigned NumArgs = MI->getNumOperands();
20764 for (unsigned i = 1; i < NumArgs; ++i) {
20765 MachineOperand &Op = MI->getOperand(i);
20766 if (!(Op.isReg() && Op.isImplicit()))
20767 MIB.addOperand(Op);
20769 if (MI->hasOneMemOperand())
20770 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20772 BuildMI(*BB, MI, dl,
20773 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20774 .addReg(X86::XMM0);
20776 MI->eraseFromParent();
20780 // FIXME: Custom handling because TableGen doesn't support multiple implicit
20781 // defs in an instruction pattern
20782 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
20783 const TargetInstrInfo *TII) {
20785 switch (MI->getOpcode()) {
20786 default: llvm_unreachable("illegal opcode!");
20787 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
20788 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
20789 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
20790 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
20791 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
20792 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
20793 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
20794 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
20797 DebugLoc dl = MI->getDebugLoc();
20798 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20800 unsigned NumArgs = MI->getNumOperands(); // remove the results
20801 for (unsigned i = 1; i < NumArgs; ++i) {
20802 MachineOperand &Op = MI->getOperand(i);
20803 if (!(Op.isReg() && Op.isImplicit()))
20804 MIB.addOperand(Op);
20806 if (MI->hasOneMemOperand())
20807 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20809 BuildMI(*BB, MI, dl,
20810 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20813 MI->eraseFromParent();
20817 static MachineBasicBlock *EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
20818 const X86Subtarget *Subtarget) {
20819 DebugLoc dl = MI->getDebugLoc();
20820 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20821 // Address into RAX/EAX, other two args into ECX, EDX.
20822 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
20823 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
20824 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
20825 for (int i = 0; i < X86::AddrNumOperands; ++i)
20826 MIB.addOperand(MI->getOperand(i));
20828 unsigned ValOps = X86::AddrNumOperands;
20829 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
20830 .addReg(MI->getOperand(ValOps).getReg());
20831 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
20832 .addReg(MI->getOperand(ValOps+1).getReg());
20834 // The instruction doesn't actually take any operands though.
20835 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
20837 MI->eraseFromParent(); // The pseudo is gone now.
20841 MachineBasicBlock *
20842 X86TargetLowering::EmitVAARG64WithCustomInserter(MachineInstr *MI,
20843 MachineBasicBlock *MBB) const {
20844 // Emit va_arg instruction on X86-64.
20846 // Operands to this pseudo-instruction:
20847 // 0 ) Output : destination address (reg)
20848 // 1-5) Input : va_list address (addr, i64mem)
20849 // 6 ) ArgSize : Size (in bytes) of vararg type
20850 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
20851 // 8 ) Align : Alignment of type
20852 // 9 ) EFLAGS (implicit-def)
20854 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
20855 static_assert(X86::AddrNumOperands == 5,
20856 "VAARG_64 assumes 5 address operands");
20858 unsigned DestReg = MI->getOperand(0).getReg();
20859 MachineOperand &Base = MI->getOperand(1);
20860 MachineOperand &Scale = MI->getOperand(2);
20861 MachineOperand &Index = MI->getOperand(3);
20862 MachineOperand &Disp = MI->getOperand(4);
20863 MachineOperand &Segment = MI->getOperand(5);
20864 unsigned ArgSize = MI->getOperand(6).getImm();
20865 unsigned ArgMode = MI->getOperand(7).getImm();
20866 unsigned Align = MI->getOperand(8).getImm();
20868 // Memory Reference
20869 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
20870 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20871 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20873 // Machine Information
20874 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20875 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
20876 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
20877 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
20878 DebugLoc DL = MI->getDebugLoc();
20880 // struct va_list {
20883 // i64 overflow_area (address)
20884 // i64 reg_save_area (address)
20886 // sizeof(va_list) = 24
20887 // alignment(va_list) = 8
20889 unsigned TotalNumIntRegs = 6;
20890 unsigned TotalNumXMMRegs = 8;
20891 bool UseGPOffset = (ArgMode == 1);
20892 bool UseFPOffset = (ArgMode == 2);
20893 unsigned MaxOffset = TotalNumIntRegs * 8 +
20894 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
20896 /* Align ArgSize to a multiple of 8 */
20897 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
20898 bool NeedsAlign = (Align > 8);
20900 MachineBasicBlock *thisMBB = MBB;
20901 MachineBasicBlock *overflowMBB;
20902 MachineBasicBlock *offsetMBB;
20903 MachineBasicBlock *endMBB;
20905 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
20906 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
20907 unsigned OffsetReg = 0;
20909 if (!UseGPOffset && !UseFPOffset) {
20910 // If we only pull from the overflow region, we don't create a branch.
20911 // We don't need to alter control flow.
20912 OffsetDestReg = 0; // unused
20913 OverflowDestReg = DestReg;
20915 offsetMBB = nullptr;
20916 overflowMBB = thisMBB;
20919 // First emit code to check if gp_offset (or fp_offset) is below the bound.
20920 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
20921 // If not, pull from overflow_area. (branch to overflowMBB)
20926 // offsetMBB overflowMBB
20931 // Registers for the PHI in endMBB
20932 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
20933 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
20935 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20936 MachineFunction *MF = MBB->getParent();
20937 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20938 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20939 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20941 MachineFunction::iterator MBBIter = ++MBB->getIterator();
20943 // Insert the new basic blocks
20944 MF->insert(MBBIter, offsetMBB);
20945 MF->insert(MBBIter, overflowMBB);
20946 MF->insert(MBBIter, endMBB);
20948 // Transfer the remainder of MBB and its successor edges to endMBB.
20949 endMBB->splice(endMBB->begin(), thisMBB,
20950 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
20951 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
20953 // Make offsetMBB and overflowMBB successors of thisMBB
20954 thisMBB->addSuccessor(offsetMBB);
20955 thisMBB->addSuccessor(overflowMBB);
20957 // endMBB is a successor of both offsetMBB and overflowMBB
20958 offsetMBB->addSuccessor(endMBB);
20959 overflowMBB->addSuccessor(endMBB);
20961 // Load the offset value into a register
20962 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20963 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
20967 .addDisp(Disp, UseFPOffset ? 4 : 0)
20968 .addOperand(Segment)
20969 .setMemRefs(MMOBegin, MMOEnd);
20971 // Check if there is enough room left to pull this argument.
20972 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
20974 .addImm(MaxOffset + 8 - ArgSizeA8);
20976 // Branch to "overflowMBB" if offset >= max
20977 // Fall through to "offsetMBB" otherwise
20978 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
20979 .addMBB(overflowMBB);
20982 // In offsetMBB, emit code to use the reg_save_area.
20984 assert(OffsetReg != 0);
20986 // Read the reg_save_area address.
20987 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
20988 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
20993 .addOperand(Segment)
20994 .setMemRefs(MMOBegin, MMOEnd);
20996 // Zero-extend the offset
20997 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
20998 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
21001 .addImm(X86::sub_32bit);
21003 // Add the offset to the reg_save_area to get the final address.
21004 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
21005 .addReg(OffsetReg64)
21006 .addReg(RegSaveReg);
21008 // Compute the offset for the next argument
21009 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
21010 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
21012 .addImm(UseFPOffset ? 16 : 8);
21014 // Store it back into the va_list.
21015 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
21019 .addDisp(Disp, UseFPOffset ? 4 : 0)
21020 .addOperand(Segment)
21021 .addReg(NextOffsetReg)
21022 .setMemRefs(MMOBegin, MMOEnd);
21025 BuildMI(offsetMBB, DL, TII->get(X86::JMP_1))
21030 // Emit code to use overflow area
21033 // Load the overflow_area address into a register.
21034 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
21035 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
21040 .addOperand(Segment)
21041 .setMemRefs(MMOBegin, MMOEnd);
21043 // If we need to align it, do so. Otherwise, just copy the address
21044 // to OverflowDestReg.
21046 // Align the overflow address
21047 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
21048 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
21050 // aligned_addr = (addr + (align-1)) & ~(align-1)
21051 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
21052 .addReg(OverflowAddrReg)
21055 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
21057 .addImm(~(uint64_t)(Align-1));
21059 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
21060 .addReg(OverflowAddrReg);
21063 // Compute the next overflow address after this argument.
21064 // (the overflow address should be kept 8-byte aligned)
21065 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
21066 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
21067 .addReg(OverflowDestReg)
21068 .addImm(ArgSizeA8);
21070 // Store the new overflow address.
21071 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
21076 .addOperand(Segment)
21077 .addReg(NextAddrReg)
21078 .setMemRefs(MMOBegin, MMOEnd);
21080 // If we branched, emit the PHI to the front of endMBB.
21082 BuildMI(*endMBB, endMBB->begin(), DL,
21083 TII->get(X86::PHI), DestReg)
21084 .addReg(OffsetDestReg).addMBB(offsetMBB)
21085 .addReg(OverflowDestReg).addMBB(overflowMBB);
21088 // Erase the pseudo instruction
21089 MI->eraseFromParent();
21094 MachineBasicBlock *
21095 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
21097 MachineBasicBlock *MBB) const {
21098 // Emit code to save XMM registers to the stack. The ABI says that the
21099 // number of registers to save is given in %al, so it's theoretically
21100 // possible to do an indirect jump trick to avoid saving all of them,
21101 // however this code takes a simpler approach and just executes all
21102 // of the stores if %al is non-zero. It's less code, and it's probably
21103 // easier on the hardware branch predictor, and stores aren't all that
21104 // expensive anyway.
21106 // Create the new basic blocks. One block contains all the XMM stores,
21107 // and one block is the final destination regardless of whether any
21108 // stores were performed.
21109 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
21110 MachineFunction *F = MBB->getParent();
21111 MachineFunction::iterator MBBIter = ++MBB->getIterator();
21112 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
21113 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
21114 F->insert(MBBIter, XMMSaveMBB);
21115 F->insert(MBBIter, EndMBB);
21117 // Transfer the remainder of MBB and its successor edges to EndMBB.
21118 EndMBB->splice(EndMBB->begin(), MBB,
21119 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
21120 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
21122 // The original block will now fall through to the XMM save block.
21123 MBB->addSuccessor(XMMSaveMBB);
21124 // The XMMSaveMBB will fall through to the end block.
21125 XMMSaveMBB->addSuccessor(EndMBB);
21127 // Now add the instructions.
21128 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21129 DebugLoc DL = MI->getDebugLoc();
21131 unsigned CountReg = MI->getOperand(0).getReg();
21132 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
21133 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
21135 if (!Subtarget->isCallingConvWin64(F->getFunction()->getCallingConv())) {
21136 // If %al is 0, branch around the XMM save block.
21137 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
21138 BuildMI(MBB, DL, TII->get(X86::JE_1)).addMBB(EndMBB);
21139 MBB->addSuccessor(EndMBB);
21142 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
21143 // that was just emitted, but clearly shouldn't be "saved".
21144 assert((MI->getNumOperands() <= 3 ||
21145 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
21146 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
21147 && "Expected last argument to be EFLAGS");
21148 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
21149 // In the XMM save block, save all the XMM argument registers.
21150 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
21151 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
21152 MachineMemOperand *MMO = F->getMachineMemOperand(
21153 MachinePointerInfo::getFixedStack(*F, RegSaveFrameIndex, Offset),
21154 MachineMemOperand::MOStore,
21155 /*Size=*/16, /*Align=*/16);
21156 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
21157 .addFrameIndex(RegSaveFrameIndex)
21158 .addImm(/*Scale=*/1)
21159 .addReg(/*IndexReg=*/0)
21160 .addImm(/*Disp=*/Offset)
21161 .addReg(/*Segment=*/0)
21162 .addReg(MI->getOperand(i).getReg())
21163 .addMemOperand(MMO);
21166 MI->eraseFromParent(); // The pseudo instruction is gone now.
21171 // The EFLAGS operand of SelectItr might be missing a kill marker
21172 // because there were multiple uses of EFLAGS, and ISel didn't know
21173 // which to mark. Figure out whether SelectItr should have had a
21174 // kill marker, and set it if it should. Returns the correct kill
21176 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
21177 MachineBasicBlock* BB,
21178 const TargetRegisterInfo* TRI) {
21179 // Scan forward through BB for a use/def of EFLAGS.
21180 MachineBasicBlock::iterator miI(std::next(SelectItr));
21181 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
21182 const MachineInstr& mi = *miI;
21183 if (mi.readsRegister(X86::EFLAGS))
21185 if (mi.definesRegister(X86::EFLAGS))
21186 break; // Should have kill-flag - update below.
21189 // If we hit the end of the block, check whether EFLAGS is live into a
21191 if (miI == BB->end()) {
21192 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
21193 sEnd = BB->succ_end();
21194 sItr != sEnd; ++sItr) {
21195 MachineBasicBlock* succ = *sItr;
21196 if (succ->isLiveIn(X86::EFLAGS))
21201 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
21202 // out. SelectMI should have a kill flag on EFLAGS.
21203 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
21207 // Return true if it is OK for this CMOV pseudo-opcode to be cascaded
21208 // together with other CMOV pseudo-opcodes into a single basic-block with
21209 // conditional jump around it.
21210 static bool isCMOVPseudo(MachineInstr *MI) {
21211 switch (MI->getOpcode()) {
21212 case X86::CMOV_FR32:
21213 case X86::CMOV_FR64:
21214 case X86::CMOV_GR8:
21215 case X86::CMOV_GR16:
21216 case X86::CMOV_GR32:
21217 case X86::CMOV_RFP32:
21218 case X86::CMOV_RFP64:
21219 case X86::CMOV_RFP80:
21220 case X86::CMOV_V2F64:
21221 case X86::CMOV_V2I64:
21222 case X86::CMOV_V4F32:
21223 case X86::CMOV_V4F64:
21224 case X86::CMOV_V4I64:
21225 case X86::CMOV_V16F32:
21226 case X86::CMOV_V8F32:
21227 case X86::CMOV_V8F64:
21228 case X86::CMOV_V8I64:
21229 case X86::CMOV_V8I1:
21230 case X86::CMOV_V16I1:
21231 case X86::CMOV_V32I1:
21232 case X86::CMOV_V64I1:
21240 MachineBasicBlock *
21241 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
21242 MachineBasicBlock *BB) const {
21243 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21244 DebugLoc DL = MI->getDebugLoc();
21246 // To "insert" a SELECT_CC instruction, we actually have to insert the
21247 // diamond control-flow pattern. The incoming instruction knows the
21248 // destination vreg to set, the condition code register to branch on, the
21249 // true/false values to select between, and a branch opcode to use.
21250 const BasicBlock *LLVM_BB = BB->getBasicBlock();
21251 MachineFunction::iterator It = ++BB->getIterator();
21256 // cmpTY ccX, r1, r2
21258 // fallthrough --> copy0MBB
21259 MachineBasicBlock *thisMBB = BB;
21260 MachineFunction *F = BB->getParent();
21262 // This code lowers all pseudo-CMOV instructions. Generally it lowers these
21263 // as described above, by inserting a BB, and then making a PHI at the join
21264 // point to select the true and false operands of the CMOV in the PHI.
21266 // The code also handles two different cases of multiple CMOV opcodes
21270 // In this case, there are multiple CMOVs in a row, all which are based on
21271 // the same condition setting (or the exact opposite condition setting).
21272 // In this case we can lower all the CMOVs using a single inserted BB, and
21273 // then make a number of PHIs at the join point to model the CMOVs. The only
21274 // trickiness here, is that in a case like:
21276 // t2 = CMOV cond1 t1, f1
21277 // t3 = CMOV cond1 t2, f2
21279 // when rewriting this into PHIs, we have to perform some renaming on the
21280 // temps since you cannot have a PHI operand refer to a PHI result earlier
21281 // in the same block. The "simple" but wrong lowering would be:
21283 // t2 = PHI t1(BB1), f1(BB2)
21284 // t3 = PHI t2(BB1), f2(BB2)
21286 // but clearly t2 is not defined in BB1, so that is incorrect. The proper
21287 // renaming is to note that on the path through BB1, t2 is really just a
21288 // copy of t1, and do that renaming, properly generating:
21290 // t2 = PHI t1(BB1), f1(BB2)
21291 // t3 = PHI t1(BB1), f2(BB2)
21293 // Case 2, we lower cascaded CMOVs such as
21295 // (CMOV (CMOV F, T, cc1), T, cc2)
21297 // to two successives branches. For that, we look for another CMOV as the
21298 // following instruction.
21300 // Without this, we would add a PHI between the two jumps, which ends up
21301 // creating a few copies all around. For instance, for
21303 // (sitofp (zext (fcmp une)))
21305 // we would generate:
21307 // ucomiss %xmm1, %xmm0
21308 // movss <1.0f>, %xmm0
21309 // movaps %xmm0, %xmm1
21311 // xorps %xmm1, %xmm1
21314 // movaps %xmm1, %xmm0
21318 // because this custom-inserter would have generated:
21330 // A: X = ...; Y = ...
21332 // C: Z = PHI [X, A], [Y, B]
21334 // E: PHI [X, C], [Z, D]
21336 // If we lower both CMOVs in a single step, we can instead generate:
21348 // A: X = ...; Y = ...
21350 // E: PHI [X, A], [X, C], [Y, D]
21352 // Which, in our sitofp/fcmp example, gives us something like:
21354 // ucomiss %xmm1, %xmm0
21355 // movss <1.0f>, %xmm0
21358 // xorps %xmm0, %xmm0
21362 MachineInstr *CascadedCMOV = nullptr;
21363 MachineInstr *LastCMOV = MI;
21364 X86::CondCode CC = X86::CondCode(MI->getOperand(3).getImm());
21365 X86::CondCode OppCC = X86::GetOppositeBranchCondition(CC);
21366 MachineBasicBlock::iterator NextMIIt =
21367 std::next(MachineBasicBlock::iterator(MI));
21369 // Check for case 1, where there are multiple CMOVs with the same condition
21370 // first. Of the two cases of multiple CMOV lowerings, case 1 reduces the
21371 // number of jumps the most.
21373 if (isCMOVPseudo(MI)) {
21374 // See if we have a string of CMOVS with the same condition.
21375 while (NextMIIt != BB->end() &&
21376 isCMOVPseudo(NextMIIt) &&
21377 (NextMIIt->getOperand(3).getImm() == CC ||
21378 NextMIIt->getOperand(3).getImm() == OppCC)) {
21379 LastCMOV = &*NextMIIt;
21384 // This checks for case 2, but only do this if we didn't already find
21385 // case 1, as indicated by LastCMOV == MI.
21386 if (LastCMOV == MI &&
21387 NextMIIt != BB->end() && NextMIIt->getOpcode() == MI->getOpcode() &&
21388 NextMIIt->getOperand(2).getReg() == MI->getOperand(2).getReg() &&
21389 NextMIIt->getOperand(1).getReg() == MI->getOperand(0).getReg()) {
21390 CascadedCMOV = &*NextMIIt;
21393 MachineBasicBlock *jcc1MBB = nullptr;
21395 // If we have a cascaded CMOV, we lower it to two successive branches to
21396 // the same block. EFLAGS is used by both, so mark it as live in the second.
21397 if (CascadedCMOV) {
21398 jcc1MBB = F->CreateMachineBasicBlock(LLVM_BB);
21399 F->insert(It, jcc1MBB);
21400 jcc1MBB->addLiveIn(X86::EFLAGS);
21403 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
21404 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
21405 F->insert(It, copy0MBB);
21406 F->insert(It, sinkMBB);
21408 // If the EFLAGS register isn't dead in the terminator, then claim that it's
21409 // live into the sink and copy blocks.
21410 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
21412 MachineInstr *LastEFLAGSUser = CascadedCMOV ? CascadedCMOV : LastCMOV;
21413 if (!LastEFLAGSUser->killsRegister(X86::EFLAGS) &&
21414 !checkAndUpdateEFLAGSKill(LastEFLAGSUser, BB, TRI)) {
21415 copy0MBB->addLiveIn(X86::EFLAGS);
21416 sinkMBB->addLiveIn(X86::EFLAGS);
21419 // Transfer the remainder of BB and its successor edges to sinkMBB.
21420 sinkMBB->splice(sinkMBB->begin(), BB,
21421 std::next(MachineBasicBlock::iterator(LastCMOV)), BB->end());
21422 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
21424 // Add the true and fallthrough blocks as its successors.
21425 if (CascadedCMOV) {
21426 // The fallthrough block may be jcc1MBB, if we have a cascaded CMOV.
21427 BB->addSuccessor(jcc1MBB);
21429 // In that case, jcc1MBB will itself fallthrough the copy0MBB, and
21430 // jump to the sinkMBB.
21431 jcc1MBB->addSuccessor(copy0MBB);
21432 jcc1MBB->addSuccessor(sinkMBB);
21434 BB->addSuccessor(copy0MBB);
21437 // The true block target of the first (or only) branch is always sinkMBB.
21438 BB->addSuccessor(sinkMBB);
21440 // Create the conditional branch instruction.
21441 unsigned Opc = X86::GetCondBranchFromCond(CC);
21442 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
21444 if (CascadedCMOV) {
21445 unsigned Opc2 = X86::GetCondBranchFromCond(
21446 (X86::CondCode)CascadedCMOV->getOperand(3).getImm());
21447 BuildMI(jcc1MBB, DL, TII->get(Opc2)).addMBB(sinkMBB);
21451 // %FalseValue = ...
21452 // # fallthrough to sinkMBB
21453 copy0MBB->addSuccessor(sinkMBB);
21456 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
21458 MachineBasicBlock::iterator MIItBegin = MachineBasicBlock::iterator(MI);
21459 MachineBasicBlock::iterator MIItEnd =
21460 std::next(MachineBasicBlock::iterator(LastCMOV));
21461 MachineBasicBlock::iterator SinkInsertionPoint = sinkMBB->begin();
21462 DenseMap<unsigned, std::pair<unsigned, unsigned>> RegRewriteTable;
21463 MachineInstrBuilder MIB;
21465 // As we are creating the PHIs, we have to be careful if there is more than
21466 // one. Later CMOVs may reference the results of earlier CMOVs, but later
21467 // PHIs have to reference the individual true/false inputs from earlier PHIs.
21468 // That also means that PHI construction must work forward from earlier to
21469 // later, and that the code must maintain a mapping from earlier PHI's
21470 // destination registers, and the registers that went into the PHI.
21472 for (MachineBasicBlock::iterator MIIt = MIItBegin; MIIt != MIItEnd; ++MIIt) {
21473 unsigned DestReg = MIIt->getOperand(0).getReg();
21474 unsigned Op1Reg = MIIt->getOperand(1).getReg();
21475 unsigned Op2Reg = MIIt->getOperand(2).getReg();
21477 // If this CMOV we are generating is the opposite condition from
21478 // the jump we generated, then we have to swap the operands for the
21479 // PHI that is going to be generated.
21480 if (MIIt->getOperand(3).getImm() == OppCC)
21481 std::swap(Op1Reg, Op2Reg);
21483 if (RegRewriteTable.find(Op1Reg) != RegRewriteTable.end())
21484 Op1Reg = RegRewriteTable[Op1Reg].first;
21486 if (RegRewriteTable.find(Op2Reg) != RegRewriteTable.end())
21487 Op2Reg = RegRewriteTable[Op2Reg].second;
21489 MIB = BuildMI(*sinkMBB, SinkInsertionPoint, DL,
21490 TII->get(X86::PHI), DestReg)
21491 .addReg(Op1Reg).addMBB(copy0MBB)
21492 .addReg(Op2Reg).addMBB(thisMBB);
21494 // Add this PHI to the rewrite table.
21495 RegRewriteTable[DestReg] = std::make_pair(Op1Reg, Op2Reg);
21498 // If we have a cascaded CMOV, the second Jcc provides the same incoming
21499 // value as the first Jcc (the True operand of the SELECT_CC/CMOV nodes).
21500 if (CascadedCMOV) {
21501 MIB.addReg(MI->getOperand(2).getReg()).addMBB(jcc1MBB);
21502 // Copy the PHI result to the register defined by the second CMOV.
21503 BuildMI(*sinkMBB, std::next(MachineBasicBlock::iterator(MIB.getInstr())),
21504 DL, TII->get(TargetOpcode::COPY),
21505 CascadedCMOV->getOperand(0).getReg())
21506 .addReg(MI->getOperand(0).getReg());
21507 CascadedCMOV->eraseFromParent();
21510 // Now remove the CMOV(s).
21511 for (MachineBasicBlock::iterator MIIt = MIItBegin; MIIt != MIItEnd; )
21512 (MIIt++)->eraseFromParent();
21517 MachineBasicBlock *
21518 X86TargetLowering::EmitLoweredAtomicFP(MachineInstr *MI,
21519 MachineBasicBlock *BB) const {
21520 // Combine the following atomic floating-point modification pattern:
21521 // a.store(reg OP a.load(acquire), release)
21522 // Transform them into:
21523 // OPss (%gpr), %xmm
21524 // movss %xmm, (%gpr)
21525 // Or sd equivalent for 64-bit operations.
21527 switch (MI->getOpcode()) {
21528 default: llvm_unreachable("unexpected instr type for EmitLoweredAtomicFP");
21529 case X86::RELEASE_FADD32mr: MOp = X86::MOVSSmr; FOp = X86::ADDSSrm; break;
21530 case X86::RELEASE_FADD64mr: MOp = X86::MOVSDmr; FOp = X86::ADDSDrm; break;
21532 const X86InstrInfo *TII = Subtarget->getInstrInfo();
21533 DebugLoc DL = MI->getDebugLoc();
21534 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
21535 MachineOperand MSrc = MI->getOperand(0);
21536 unsigned VSrc = MI->getOperand(5).getReg();
21537 const MachineOperand &Disp = MI->getOperand(3);
21538 MachineOperand ZeroDisp = MachineOperand::CreateImm(0);
21539 bool hasDisp = Disp.isGlobal() || Disp.isImm();
21540 if (hasDisp && MSrc.isReg())
21541 MSrc.setIsKill(false);
21542 MachineInstrBuilder MIM = BuildMI(*BB, MI, DL, TII->get(MOp))
21543 .addOperand(/*Base=*/MSrc)
21544 .addImm(/*Scale=*/1)
21545 .addReg(/*Index=*/0)
21546 .addDisp(hasDisp ? Disp : ZeroDisp, /*off=*/0)
21548 MachineInstr *MIO = BuildMI(*BB, (MachineInstr *)MIM, DL, TII->get(FOp),
21549 MRI.createVirtualRegister(MRI.getRegClass(VSrc)))
21551 .addOperand(/*Base=*/MSrc)
21552 .addImm(/*Scale=*/1)
21553 .addReg(/*Index=*/0)
21554 .addDisp(hasDisp ? Disp : ZeroDisp, /*off=*/0)
21555 .addReg(/*Segment=*/0);
21556 MIM.addReg(MIO->getOperand(0).getReg(), RegState::Kill);
21557 MI->eraseFromParent(); // The pseudo instruction is gone now.
21561 MachineBasicBlock *
21562 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
21563 MachineBasicBlock *BB) const {
21564 MachineFunction *MF = BB->getParent();
21565 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21566 DebugLoc DL = MI->getDebugLoc();
21567 const BasicBlock *LLVM_BB = BB->getBasicBlock();
21569 assert(MF->shouldSplitStack());
21571 const bool Is64Bit = Subtarget->is64Bit();
21572 const bool IsLP64 = Subtarget->isTarget64BitLP64();
21574 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
21575 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
21578 // ... [Till the alloca]
21579 // If stacklet is not large enough, jump to mallocMBB
21582 // Allocate by subtracting from RSP
21583 // Jump to continueMBB
21586 // Allocate by call to runtime
21590 // [rest of original BB]
21593 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
21594 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
21595 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
21597 MachineRegisterInfo &MRI = MF->getRegInfo();
21598 const TargetRegisterClass *AddrRegClass =
21599 getRegClassFor(getPointerTy(MF->getDataLayout()));
21601 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
21602 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
21603 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
21604 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
21605 sizeVReg = MI->getOperand(1).getReg(),
21606 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
21608 MachineFunction::iterator MBBIter = ++BB->getIterator();
21610 MF->insert(MBBIter, bumpMBB);
21611 MF->insert(MBBIter, mallocMBB);
21612 MF->insert(MBBIter, continueMBB);
21614 continueMBB->splice(continueMBB->begin(), BB,
21615 std::next(MachineBasicBlock::iterator(MI)), BB->end());
21616 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
21618 // Add code to the main basic block to check if the stack limit has been hit,
21619 // and if so, jump to mallocMBB otherwise to bumpMBB.
21620 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
21621 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
21622 .addReg(tmpSPVReg).addReg(sizeVReg);
21623 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
21624 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
21625 .addReg(SPLimitVReg);
21626 BuildMI(BB, DL, TII->get(X86::JG_1)).addMBB(mallocMBB);
21628 // bumpMBB simply decreases the stack pointer, since we know the current
21629 // stacklet has enough space.
21630 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
21631 .addReg(SPLimitVReg);
21632 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
21633 .addReg(SPLimitVReg);
21634 BuildMI(bumpMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
21636 // Calls into a routine in libgcc to allocate more space from the heap.
21637 const uint32_t *RegMask =
21638 Subtarget->getRegisterInfo()->getCallPreservedMask(*MF, CallingConv::C);
21640 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
21642 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
21643 .addExternalSymbol("__morestack_allocate_stack_space")
21644 .addRegMask(RegMask)
21645 .addReg(X86::RDI, RegState::Implicit)
21646 .addReg(X86::RAX, RegState::ImplicitDefine);
21647 } else if (Is64Bit) {
21648 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
21650 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
21651 .addExternalSymbol("__morestack_allocate_stack_space")
21652 .addRegMask(RegMask)
21653 .addReg(X86::EDI, RegState::Implicit)
21654 .addReg(X86::EAX, RegState::ImplicitDefine);
21656 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
21658 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
21659 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
21660 .addExternalSymbol("__morestack_allocate_stack_space")
21661 .addRegMask(RegMask)
21662 .addReg(X86::EAX, RegState::ImplicitDefine);
21666 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
21669 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
21670 .addReg(IsLP64 ? X86::RAX : X86::EAX);
21671 BuildMI(mallocMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
21673 // Set up the CFG correctly.
21674 BB->addSuccessor(bumpMBB);
21675 BB->addSuccessor(mallocMBB);
21676 mallocMBB->addSuccessor(continueMBB);
21677 bumpMBB->addSuccessor(continueMBB);
21679 // Take care of the PHI nodes.
21680 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
21681 MI->getOperand(0).getReg())
21682 .addReg(mallocPtrVReg).addMBB(mallocMBB)
21683 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
21685 // Delete the original pseudo instruction.
21686 MI->eraseFromParent();
21689 return continueMBB;
21692 MachineBasicBlock *
21693 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
21694 MachineBasicBlock *BB) const {
21695 assert(!Subtarget->isTargetMachO());
21696 DebugLoc DL = MI->getDebugLoc();
21697 MachineInstr *ResumeMI = Subtarget->getFrameLowering()->emitStackProbe(
21698 *BB->getParent(), *BB, MI, DL, false);
21699 MachineBasicBlock *ResumeBB = ResumeMI->getParent();
21700 MI->eraseFromParent(); // The pseudo instruction is gone now.
21704 MachineBasicBlock *
21705 X86TargetLowering::EmitLoweredCatchRet(MachineInstr *MI,
21706 MachineBasicBlock *BB) const {
21707 MachineFunction *MF = BB->getParent();
21708 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
21709 MachineBasicBlock *TargetMBB = MI->getOperand(0).getMBB();
21710 DebugLoc DL = MI->getDebugLoc();
21712 assert(!isAsynchronousEHPersonality(
21713 classifyEHPersonality(MF->getFunction()->getPersonalityFn())) &&
21714 "SEH does not use catchret!");
21716 // Only 32-bit EH needs to worry about manually restoring stack pointers.
21717 if (!Subtarget->is32Bit())
21720 // C++ EH creates a new target block to hold the restore code, and wires up
21721 // the new block to the return destination with a normal JMP_4.
21722 MachineBasicBlock *RestoreMBB =
21723 MF->CreateMachineBasicBlock(BB->getBasicBlock());
21724 assert(BB->succ_size() == 1);
21725 MF->insert(std::next(BB->getIterator()), RestoreMBB);
21726 RestoreMBB->transferSuccessorsAndUpdatePHIs(BB);
21727 BB->addSuccessor(RestoreMBB);
21728 MI->getOperand(0).setMBB(RestoreMBB);
21730 auto RestoreMBBI = RestoreMBB->begin();
21731 BuildMI(*RestoreMBB, RestoreMBBI, DL, TII.get(X86::EH_RESTORE));
21732 BuildMI(*RestoreMBB, RestoreMBBI, DL, TII.get(X86::JMP_4)).addMBB(TargetMBB);
21736 MachineBasicBlock *
21737 X86TargetLowering::EmitLoweredCatchPad(MachineInstr *MI,
21738 MachineBasicBlock *BB) const {
21739 MachineFunction *MF = BB->getParent();
21740 const Constant *PerFn = MF->getFunction()->getPersonalityFn();
21741 bool IsSEH = isAsynchronousEHPersonality(classifyEHPersonality(PerFn));
21742 // Only 32-bit SEH requires special handling for catchpad.
21743 if (IsSEH && Subtarget->is32Bit()) {
21744 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
21745 DebugLoc DL = MI->getDebugLoc();
21746 BuildMI(*BB, MI, DL, TII.get(X86::EH_RESTORE));
21748 MI->eraseFromParent();
21752 MachineBasicBlock *
21753 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
21754 MachineBasicBlock *BB) const {
21755 // This is pretty easy. We're taking the value that we received from
21756 // our load from the relocation, sticking it in either RDI (x86-64)
21757 // or EAX and doing an indirect call. The return value will then
21758 // be in the normal return register.
21759 MachineFunction *F = BB->getParent();
21760 const X86InstrInfo *TII = Subtarget->getInstrInfo();
21761 DebugLoc DL = MI->getDebugLoc();
21763 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
21764 assert(MI->getOperand(3).isGlobal() && "This should be a global");
21766 // Get a register mask for the lowered call.
21767 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
21768 // proper register mask.
21769 const uint32_t *RegMask =
21770 Subtarget->is64Bit() ?
21771 Subtarget->getRegisterInfo()->getDarwinTLSCallPreservedMask() :
21772 Subtarget->getRegisterInfo()->getCallPreservedMask(*F, CallingConv::C);
21773 if (Subtarget->is64Bit()) {
21774 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21775 TII->get(X86::MOV64rm), X86::RDI)
21777 .addImm(0).addReg(0)
21778 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21779 MI->getOperand(3).getTargetFlags())
21781 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
21782 addDirectMem(MIB, X86::RDI);
21783 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
21784 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
21785 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21786 TII->get(X86::MOV32rm), X86::EAX)
21788 .addImm(0).addReg(0)
21789 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21790 MI->getOperand(3).getTargetFlags())
21792 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
21793 addDirectMem(MIB, X86::EAX);
21794 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
21796 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21797 TII->get(X86::MOV32rm), X86::EAX)
21798 .addReg(TII->getGlobalBaseReg(F))
21799 .addImm(0).addReg(0)
21800 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21801 MI->getOperand(3).getTargetFlags())
21803 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
21804 addDirectMem(MIB, X86::EAX);
21805 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
21808 MI->eraseFromParent(); // The pseudo instruction is gone now.
21812 MachineBasicBlock *
21813 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
21814 MachineBasicBlock *MBB) const {
21815 DebugLoc DL = MI->getDebugLoc();
21816 MachineFunction *MF = MBB->getParent();
21817 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21818 MachineRegisterInfo &MRI = MF->getRegInfo();
21820 const BasicBlock *BB = MBB->getBasicBlock();
21821 MachineFunction::iterator I = ++MBB->getIterator();
21823 // Memory Reference
21824 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
21825 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
21828 unsigned MemOpndSlot = 0;
21830 unsigned CurOp = 0;
21832 DstReg = MI->getOperand(CurOp++).getReg();
21833 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
21834 assert(RC->hasType(MVT::i32) && "Invalid destination!");
21835 unsigned mainDstReg = MRI.createVirtualRegister(RC);
21836 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
21838 MemOpndSlot = CurOp;
21840 MVT PVT = getPointerTy(MF->getDataLayout());
21841 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
21842 "Invalid Pointer Size!");
21844 // For v = setjmp(buf), we generate
21847 // buf[LabelOffset] = restoreMBB <-- takes address of restoreMBB
21848 // SjLjSetup restoreMBB
21854 // v = phi(main, restore)
21857 // if base pointer being used, load it from frame
21860 MachineBasicBlock *thisMBB = MBB;
21861 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
21862 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
21863 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
21864 MF->insert(I, mainMBB);
21865 MF->insert(I, sinkMBB);
21866 MF->push_back(restoreMBB);
21867 restoreMBB->setHasAddressTaken();
21869 MachineInstrBuilder MIB;
21871 // Transfer the remainder of BB and its successor edges to sinkMBB.
21872 sinkMBB->splice(sinkMBB->begin(), MBB,
21873 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
21874 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
21877 unsigned PtrStoreOpc = 0;
21878 unsigned LabelReg = 0;
21879 const int64_t LabelOffset = 1 * PVT.getStoreSize();
21880 Reloc::Model RM = MF->getTarget().getRelocationModel();
21881 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
21882 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
21884 // Prepare IP either in reg or imm.
21885 if (!UseImmLabel) {
21886 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
21887 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
21888 LabelReg = MRI.createVirtualRegister(PtrRC);
21889 if (Subtarget->is64Bit()) {
21890 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
21894 .addMBB(restoreMBB)
21897 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
21898 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
21899 .addReg(XII->getGlobalBaseReg(MF))
21902 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
21906 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
21908 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
21909 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21910 if (i == X86::AddrDisp)
21911 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
21913 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
21916 MIB.addReg(LabelReg);
21918 MIB.addMBB(restoreMBB);
21919 MIB.setMemRefs(MMOBegin, MMOEnd);
21921 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
21922 .addMBB(restoreMBB);
21924 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
21925 MIB.addRegMask(RegInfo->getNoPreservedMask());
21926 thisMBB->addSuccessor(mainMBB);
21927 thisMBB->addSuccessor(restoreMBB);
21931 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
21932 mainMBB->addSuccessor(sinkMBB);
21935 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
21936 TII->get(X86::PHI), DstReg)
21937 .addReg(mainDstReg).addMBB(mainMBB)
21938 .addReg(restoreDstReg).addMBB(restoreMBB);
21941 if (RegInfo->hasBasePointer(*MF)) {
21942 const bool Uses64BitFramePtr =
21943 Subtarget->isTarget64BitLP64() || Subtarget->isTargetNaCl64();
21944 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
21945 X86FI->setRestoreBasePointer(MF);
21946 unsigned FramePtr = RegInfo->getFrameRegister(*MF);
21947 unsigned BasePtr = RegInfo->getBaseRegister();
21948 unsigned Opm = Uses64BitFramePtr ? X86::MOV64rm : X86::MOV32rm;
21949 addRegOffset(BuildMI(restoreMBB, DL, TII->get(Opm), BasePtr),
21950 FramePtr, true, X86FI->getRestoreBasePointerOffset())
21951 .setMIFlag(MachineInstr::FrameSetup);
21953 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
21954 BuildMI(restoreMBB, DL, TII->get(X86::JMP_1)).addMBB(sinkMBB);
21955 restoreMBB->addSuccessor(sinkMBB);
21957 MI->eraseFromParent();
21961 MachineBasicBlock *
21962 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
21963 MachineBasicBlock *MBB) const {
21964 DebugLoc DL = MI->getDebugLoc();
21965 MachineFunction *MF = MBB->getParent();
21966 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21967 MachineRegisterInfo &MRI = MF->getRegInfo();
21969 // Memory Reference
21970 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
21971 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
21973 MVT PVT = getPointerTy(MF->getDataLayout());
21974 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
21975 "Invalid Pointer Size!");
21977 const TargetRegisterClass *RC =
21978 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
21979 unsigned Tmp = MRI.createVirtualRegister(RC);
21980 // Since FP is only updated here but NOT referenced, it's treated as GPR.
21981 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
21982 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
21983 unsigned SP = RegInfo->getStackRegister();
21985 MachineInstrBuilder MIB;
21987 const int64_t LabelOffset = 1 * PVT.getStoreSize();
21988 const int64_t SPOffset = 2 * PVT.getStoreSize();
21990 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
21991 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
21994 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
21995 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
21996 MIB.addOperand(MI->getOperand(i));
21997 MIB.setMemRefs(MMOBegin, MMOEnd);
21999 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
22000 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
22001 if (i == X86::AddrDisp)
22002 MIB.addDisp(MI->getOperand(i), LabelOffset);
22004 MIB.addOperand(MI->getOperand(i));
22006 MIB.setMemRefs(MMOBegin, MMOEnd);
22008 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
22009 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
22010 if (i == X86::AddrDisp)
22011 MIB.addDisp(MI->getOperand(i), SPOffset);
22013 MIB.addOperand(MI->getOperand(i));
22015 MIB.setMemRefs(MMOBegin, MMOEnd);
22017 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
22019 MI->eraseFromParent();
22023 // Replace 213-type (isel default) FMA3 instructions with 231-type for
22024 // accumulator loops. Writing back to the accumulator allows the coalescer
22025 // to remove extra copies in the loop.
22026 // FIXME: Do this on AVX512. We don't support 231 variants yet (PR23937).
22027 MachineBasicBlock *
22028 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
22029 MachineBasicBlock *MBB) const {
22030 MachineOperand &AddendOp = MI->getOperand(3);
22032 // Bail out early if the addend isn't a register - we can't switch these.
22033 if (!AddendOp.isReg())
22036 MachineFunction &MF = *MBB->getParent();
22037 MachineRegisterInfo &MRI = MF.getRegInfo();
22039 // Check whether the addend is defined by a PHI:
22040 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
22041 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
22042 if (!AddendDef.isPHI())
22045 // Look for the following pattern:
22047 // %addend = phi [%entry, 0], [%loop, %result]
22049 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
22053 // %addend = phi [%entry, 0], [%loop, %result]
22055 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
22057 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
22058 assert(AddendDef.getOperand(i).isReg());
22059 MachineOperand PHISrcOp = AddendDef.getOperand(i);
22060 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
22061 if (&PHISrcInst == MI) {
22062 // Found a matching instruction.
22063 unsigned NewFMAOpc = 0;
22064 switch (MI->getOpcode()) {
22065 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
22066 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
22067 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
22068 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
22069 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
22070 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
22071 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
22072 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
22073 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
22074 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
22075 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
22076 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
22077 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
22078 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
22079 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
22080 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
22081 case X86::VFMADDSUBPDr213r: NewFMAOpc = X86::VFMADDSUBPDr231r; break;
22082 case X86::VFMADDSUBPSr213r: NewFMAOpc = X86::VFMADDSUBPSr231r; break;
22083 case X86::VFMSUBADDPDr213r: NewFMAOpc = X86::VFMSUBADDPDr231r; break;
22084 case X86::VFMSUBADDPSr213r: NewFMAOpc = X86::VFMSUBADDPSr231r; break;
22086 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
22087 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
22088 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
22089 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
22090 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
22091 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
22092 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
22093 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
22094 case X86::VFMADDSUBPDr213rY: NewFMAOpc = X86::VFMADDSUBPDr231rY; break;
22095 case X86::VFMADDSUBPSr213rY: NewFMAOpc = X86::VFMADDSUBPSr231rY; break;
22096 case X86::VFMSUBADDPDr213rY: NewFMAOpc = X86::VFMSUBADDPDr231rY; break;
22097 case X86::VFMSUBADDPSr213rY: NewFMAOpc = X86::VFMSUBADDPSr231rY; break;
22098 default: llvm_unreachable("Unrecognized FMA variant.");
22101 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
22102 MachineInstrBuilder MIB =
22103 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
22104 .addOperand(MI->getOperand(0))
22105 .addOperand(MI->getOperand(3))
22106 .addOperand(MI->getOperand(2))
22107 .addOperand(MI->getOperand(1));
22108 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
22109 MI->eraseFromParent();
22116 MachineBasicBlock *
22117 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
22118 MachineBasicBlock *BB) const {
22119 switch (MI->getOpcode()) {
22120 default: llvm_unreachable("Unexpected instr type to insert");
22121 case X86::TAILJMPd64:
22122 case X86::TAILJMPr64:
22123 case X86::TAILJMPm64:
22124 case X86::TAILJMPd64_REX:
22125 case X86::TAILJMPr64_REX:
22126 case X86::TAILJMPm64_REX:
22127 llvm_unreachable("TAILJMP64 would not be touched here.");
22128 case X86::TCRETURNdi64:
22129 case X86::TCRETURNri64:
22130 case X86::TCRETURNmi64:
22132 case X86::WIN_ALLOCA:
22133 return EmitLoweredWinAlloca(MI, BB);
22134 case X86::CATCHRET:
22135 return EmitLoweredCatchRet(MI, BB);
22136 case X86::CATCHPAD:
22137 return EmitLoweredCatchPad(MI, BB);
22138 case X86::SEG_ALLOCA_32:
22139 case X86::SEG_ALLOCA_64:
22140 return EmitLoweredSegAlloca(MI, BB);
22141 case X86::TLSCall_32:
22142 case X86::TLSCall_64:
22143 return EmitLoweredTLSCall(MI, BB);
22144 case X86::CMOV_FR32:
22145 case X86::CMOV_FR64:
22146 case X86::CMOV_GR8:
22147 case X86::CMOV_GR16:
22148 case X86::CMOV_GR32:
22149 case X86::CMOV_RFP32:
22150 case X86::CMOV_RFP64:
22151 case X86::CMOV_RFP80:
22152 case X86::CMOV_V2F64:
22153 case X86::CMOV_V2I64:
22154 case X86::CMOV_V4F32:
22155 case X86::CMOV_V4F64:
22156 case X86::CMOV_V4I64:
22157 case X86::CMOV_V16F32:
22158 case X86::CMOV_V8F32:
22159 case X86::CMOV_V8F64:
22160 case X86::CMOV_V8I64:
22161 case X86::CMOV_V8I1:
22162 case X86::CMOV_V16I1:
22163 case X86::CMOV_V32I1:
22164 case X86::CMOV_V64I1:
22165 return EmitLoweredSelect(MI, BB);
22167 case X86::RELEASE_FADD32mr:
22168 case X86::RELEASE_FADD64mr:
22169 return EmitLoweredAtomicFP(MI, BB);
22171 case X86::FP32_TO_INT16_IN_MEM:
22172 case X86::FP32_TO_INT32_IN_MEM:
22173 case X86::FP32_TO_INT64_IN_MEM:
22174 case X86::FP64_TO_INT16_IN_MEM:
22175 case X86::FP64_TO_INT32_IN_MEM:
22176 case X86::FP64_TO_INT64_IN_MEM:
22177 case X86::FP80_TO_INT16_IN_MEM:
22178 case X86::FP80_TO_INT32_IN_MEM:
22179 case X86::FP80_TO_INT64_IN_MEM: {
22180 MachineFunction *F = BB->getParent();
22181 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
22182 DebugLoc DL = MI->getDebugLoc();
22184 // Change the floating point control register to use "round towards zero"
22185 // mode when truncating to an integer value.
22186 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
22187 addFrameReference(BuildMI(*BB, MI, DL,
22188 TII->get(X86::FNSTCW16m)), CWFrameIdx);
22190 // Load the old value of the high byte of the control word...
22192 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
22193 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
22196 // Set the high part to be round to zero...
22197 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
22200 // Reload the modified control word now...
22201 addFrameReference(BuildMI(*BB, MI, DL,
22202 TII->get(X86::FLDCW16m)), CWFrameIdx);
22204 // Restore the memory image of control word to original value
22205 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
22208 // Get the X86 opcode to use.
22210 switch (MI->getOpcode()) {
22211 default: llvm_unreachable("illegal opcode!");
22212 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
22213 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
22214 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
22215 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
22216 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
22217 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
22218 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
22219 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
22220 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
22224 MachineOperand &Op = MI->getOperand(0);
22226 AM.BaseType = X86AddressMode::RegBase;
22227 AM.Base.Reg = Op.getReg();
22229 AM.BaseType = X86AddressMode::FrameIndexBase;
22230 AM.Base.FrameIndex = Op.getIndex();
22232 Op = MI->getOperand(1);
22234 AM.Scale = Op.getImm();
22235 Op = MI->getOperand(2);
22237 AM.IndexReg = Op.getImm();
22238 Op = MI->getOperand(3);
22239 if (Op.isGlobal()) {
22240 AM.GV = Op.getGlobal();
22242 AM.Disp = Op.getImm();
22244 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
22245 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
22247 // Reload the original control word now.
22248 addFrameReference(BuildMI(*BB, MI, DL,
22249 TII->get(X86::FLDCW16m)), CWFrameIdx);
22251 MI->eraseFromParent(); // The pseudo instruction is gone now.
22254 // String/text processing lowering.
22255 case X86::PCMPISTRM128REG:
22256 case X86::VPCMPISTRM128REG:
22257 case X86::PCMPISTRM128MEM:
22258 case X86::VPCMPISTRM128MEM:
22259 case X86::PCMPESTRM128REG:
22260 case X86::VPCMPESTRM128REG:
22261 case X86::PCMPESTRM128MEM:
22262 case X86::VPCMPESTRM128MEM:
22263 assert(Subtarget->hasSSE42() &&
22264 "Target must have SSE4.2 or AVX features enabled");
22265 return EmitPCMPSTRM(MI, BB, Subtarget->getInstrInfo());
22267 // String/text processing lowering.
22268 case X86::PCMPISTRIREG:
22269 case X86::VPCMPISTRIREG:
22270 case X86::PCMPISTRIMEM:
22271 case X86::VPCMPISTRIMEM:
22272 case X86::PCMPESTRIREG:
22273 case X86::VPCMPESTRIREG:
22274 case X86::PCMPESTRIMEM:
22275 case X86::VPCMPESTRIMEM:
22276 assert(Subtarget->hasSSE42() &&
22277 "Target must have SSE4.2 or AVX features enabled");
22278 return EmitPCMPSTRI(MI, BB, Subtarget->getInstrInfo());
22280 // Thread synchronization.
22282 return EmitMonitor(MI, BB, Subtarget);
22286 return EmitXBegin(MI, BB, Subtarget->getInstrInfo());
22288 case X86::VASTART_SAVE_XMM_REGS:
22289 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
22291 case X86::VAARG_64:
22292 return EmitVAARG64WithCustomInserter(MI, BB);
22294 case X86::EH_SjLj_SetJmp32:
22295 case X86::EH_SjLj_SetJmp64:
22296 return emitEHSjLjSetJmp(MI, BB);
22298 case X86::EH_SjLj_LongJmp32:
22299 case X86::EH_SjLj_LongJmp64:
22300 return emitEHSjLjLongJmp(MI, BB);
22302 case TargetOpcode::STATEPOINT:
22303 // As an implementation detail, STATEPOINT shares the STACKMAP format at
22304 // this point in the process. We diverge later.
22305 return emitPatchPoint(MI, BB);
22307 case TargetOpcode::STACKMAP:
22308 case TargetOpcode::PATCHPOINT:
22309 return emitPatchPoint(MI, BB);
22311 case X86::VFMADDPDr213r:
22312 case X86::VFMADDPSr213r:
22313 case X86::VFMADDSDr213r:
22314 case X86::VFMADDSSr213r:
22315 case X86::VFMSUBPDr213r:
22316 case X86::VFMSUBPSr213r:
22317 case X86::VFMSUBSDr213r:
22318 case X86::VFMSUBSSr213r:
22319 case X86::VFNMADDPDr213r:
22320 case X86::VFNMADDPSr213r:
22321 case X86::VFNMADDSDr213r:
22322 case X86::VFNMADDSSr213r:
22323 case X86::VFNMSUBPDr213r:
22324 case X86::VFNMSUBPSr213r:
22325 case X86::VFNMSUBSDr213r:
22326 case X86::VFNMSUBSSr213r:
22327 case X86::VFMADDSUBPDr213r:
22328 case X86::VFMADDSUBPSr213r:
22329 case X86::VFMSUBADDPDr213r:
22330 case X86::VFMSUBADDPSr213r:
22331 case X86::VFMADDPDr213rY:
22332 case X86::VFMADDPSr213rY:
22333 case X86::VFMSUBPDr213rY:
22334 case X86::VFMSUBPSr213rY:
22335 case X86::VFNMADDPDr213rY:
22336 case X86::VFNMADDPSr213rY:
22337 case X86::VFNMSUBPDr213rY:
22338 case X86::VFNMSUBPSr213rY:
22339 case X86::VFMADDSUBPDr213rY:
22340 case X86::VFMADDSUBPSr213rY:
22341 case X86::VFMSUBADDPDr213rY:
22342 case X86::VFMSUBADDPSr213rY:
22343 return emitFMA3Instr(MI, BB);
22347 //===----------------------------------------------------------------------===//
22348 // X86 Optimization Hooks
22349 //===----------------------------------------------------------------------===//
22351 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
22354 const SelectionDAG &DAG,
22355 unsigned Depth) const {
22356 unsigned BitWidth = KnownZero.getBitWidth();
22357 unsigned Opc = Op.getOpcode();
22358 assert((Opc >= ISD::BUILTIN_OP_END ||
22359 Opc == ISD::INTRINSIC_WO_CHAIN ||
22360 Opc == ISD::INTRINSIC_W_CHAIN ||
22361 Opc == ISD::INTRINSIC_VOID) &&
22362 "Should use MaskedValueIsZero if you don't know whether Op"
22363 " is a target node!");
22365 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
22379 // These nodes' second result is a boolean.
22380 if (Op.getResNo() == 0)
22383 case X86ISD::SETCC:
22384 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
22386 case ISD::INTRINSIC_WO_CHAIN: {
22387 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
22388 unsigned NumLoBits = 0;
22391 case Intrinsic::x86_sse_movmsk_ps:
22392 case Intrinsic::x86_avx_movmsk_ps_256:
22393 case Intrinsic::x86_sse2_movmsk_pd:
22394 case Intrinsic::x86_avx_movmsk_pd_256:
22395 case Intrinsic::x86_mmx_pmovmskb:
22396 case Intrinsic::x86_sse2_pmovmskb_128:
22397 case Intrinsic::x86_avx2_pmovmskb: {
22398 // High bits of movmskp{s|d}, pmovmskb are known zero.
22400 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
22401 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
22402 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
22403 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
22404 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
22405 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
22406 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
22407 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
22409 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
22418 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
22420 const SelectionDAG &,
22421 unsigned Depth) const {
22422 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
22423 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
22424 return Op.getValueType().getScalarSizeInBits();
22430 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
22431 /// node is a GlobalAddress + offset.
22432 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
22433 const GlobalValue* &GA,
22434 int64_t &Offset) const {
22435 if (N->getOpcode() == X86ISD::Wrapper) {
22436 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
22437 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
22438 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
22442 return TargetLowering::isGAPlusOffset(N, GA, Offset);
22445 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
22446 /// same as extracting the high 128-bit part of 256-bit vector and then
22447 /// inserting the result into the low part of a new 256-bit vector
22448 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
22449 EVT VT = SVOp->getValueType(0);
22450 unsigned NumElems = VT.getVectorNumElements();
22452 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
22453 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
22454 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
22455 SVOp->getMaskElt(j) >= 0)
22461 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
22462 /// same as extracting the low 128-bit part of 256-bit vector and then
22463 /// inserting the result into the high part of a new 256-bit vector
22464 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
22465 EVT VT = SVOp->getValueType(0);
22466 unsigned NumElems = VT.getVectorNumElements();
22468 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
22469 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
22470 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
22471 SVOp->getMaskElt(j) >= 0)
22477 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
22478 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
22479 TargetLowering::DAGCombinerInfo &DCI,
22480 const X86Subtarget* Subtarget) {
22482 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
22483 SDValue V1 = SVOp->getOperand(0);
22484 SDValue V2 = SVOp->getOperand(1);
22485 MVT VT = SVOp->getSimpleValueType(0);
22486 unsigned NumElems = VT.getVectorNumElements();
22488 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
22489 V2.getOpcode() == ISD::CONCAT_VECTORS) {
22493 // V UNDEF BUILD_VECTOR UNDEF
22495 // CONCAT_VECTOR CONCAT_VECTOR
22498 // RESULT: V + zero extended
22500 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
22501 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
22502 V1.getOperand(1).getOpcode() != ISD::UNDEF)
22505 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
22508 // To match the shuffle mask, the first half of the mask should
22509 // be exactly the first vector, and all the rest a splat with the
22510 // first element of the second one.
22511 for (unsigned i = 0; i != NumElems/2; ++i)
22512 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
22513 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
22516 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
22517 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
22518 if (Ld->hasNUsesOfValue(1, 0)) {
22519 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
22520 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
22522 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
22524 Ld->getPointerInfo(),
22525 Ld->getAlignment(),
22526 false/*isVolatile*/, true/*ReadMem*/,
22527 false/*WriteMem*/);
22529 // Make sure the newly-created LOAD is in the same position as Ld in
22530 // terms of dependency. We create a TokenFactor for Ld and ResNode,
22531 // and update uses of Ld's output chain to use the TokenFactor.
22532 if (Ld->hasAnyUseOfValue(1)) {
22533 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
22534 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
22535 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
22536 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
22537 SDValue(ResNode.getNode(), 1));
22540 return DAG.getBitcast(VT, ResNode);
22544 // Emit a zeroed vector and insert the desired subvector on its
22546 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
22547 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
22548 return DCI.CombineTo(N, InsV);
22551 //===--------------------------------------------------------------------===//
22552 // Combine some shuffles into subvector extracts and inserts:
22555 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
22556 if (isShuffleHigh128VectorInsertLow(SVOp)) {
22557 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
22558 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
22559 return DCI.CombineTo(N, InsV);
22562 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
22563 if (isShuffleLow128VectorInsertHigh(SVOp)) {
22564 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
22565 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
22566 return DCI.CombineTo(N, InsV);
22572 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
22575 /// This is the leaf of the recursive combinine below. When we have found some
22576 /// chain of single-use x86 shuffle instructions and accumulated the combined
22577 /// shuffle mask represented by them, this will try to pattern match that mask
22578 /// into either a single instruction if there is a special purpose instruction
22579 /// for this operation, or into a PSHUFB instruction which is a fully general
22580 /// instruction but should only be used to replace chains over a certain depth.
22581 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
22582 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
22583 TargetLowering::DAGCombinerInfo &DCI,
22584 const X86Subtarget *Subtarget) {
22585 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
22587 // Find the operand that enters the chain. Note that multiple uses are OK
22588 // here, we're not going to remove the operand we find.
22589 SDValue Input = Op.getOperand(0);
22590 while (Input.getOpcode() == ISD::BITCAST)
22591 Input = Input.getOperand(0);
22593 MVT VT = Input.getSimpleValueType();
22594 MVT RootVT = Root.getSimpleValueType();
22597 if (Mask.size() == 1) {
22598 int Index = Mask[0];
22599 assert((Index >= 0 || Index == SM_SentinelUndef ||
22600 Index == SM_SentinelZero) &&
22601 "Invalid shuffle index found!");
22603 // We may end up with an accumulated mask of size 1 as a result of
22604 // widening of shuffle operands (see function canWidenShuffleElements).
22605 // If the only shuffle index is equal to SM_SentinelZero then propagate
22606 // a zero vector. Otherwise, the combine shuffle mask is a no-op shuffle
22607 // mask, and therefore the entire chain of shuffles can be folded away.
22608 if (Index == SM_SentinelZero)
22609 DCI.CombineTo(Root.getNode(), getZeroVector(RootVT, Subtarget, DAG, DL));
22611 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Input),
22616 // Use the float domain if the operand type is a floating point type.
22617 bool FloatDomain = VT.isFloatingPoint();
22619 // For floating point shuffles, we don't have free copies in the shuffle
22620 // instructions or the ability to load as part of the instruction, so
22621 // canonicalize their shuffles to UNPCK or MOV variants.
22623 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
22624 // vectors because it can have a load folded into it that UNPCK cannot. This
22625 // doesn't preclude something switching to the shorter encoding post-RA.
22627 // FIXME: Should teach these routines about AVX vector widths.
22628 if (FloatDomain && VT.is128BitVector()) {
22629 if (Mask.equals({0, 0}) || Mask.equals({1, 1})) {
22630 bool Lo = Mask.equals({0, 0});
22633 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
22634 // is no slower than UNPCKLPD but has the option to fold the input operand
22635 // into even an unaligned memory load.
22636 if (Lo && Subtarget->hasSSE3()) {
22637 Shuffle = X86ISD::MOVDDUP;
22638 ShuffleVT = MVT::v2f64;
22640 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
22641 // than the UNPCK variants.
22642 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
22643 ShuffleVT = MVT::v4f32;
22645 if (Depth == 1 && Root->getOpcode() == Shuffle)
22646 return false; // Nothing to do!
22647 Op = DAG.getBitcast(ShuffleVT, Input);
22648 DCI.AddToWorklist(Op.getNode());
22649 if (Shuffle == X86ISD::MOVDDUP)
22650 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
22652 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
22653 DCI.AddToWorklist(Op.getNode());
22654 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22658 if (Subtarget->hasSSE3() &&
22659 (Mask.equals({0, 0, 2, 2}) || Mask.equals({1, 1, 3, 3}))) {
22660 bool Lo = Mask.equals({0, 0, 2, 2});
22661 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
22662 MVT ShuffleVT = MVT::v4f32;
22663 if (Depth == 1 && Root->getOpcode() == Shuffle)
22664 return false; // Nothing to do!
22665 Op = DAG.getBitcast(ShuffleVT, Input);
22666 DCI.AddToWorklist(Op.getNode());
22667 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
22668 DCI.AddToWorklist(Op.getNode());
22669 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22673 if (Mask.equals({0, 0, 1, 1}) || Mask.equals({2, 2, 3, 3})) {
22674 bool Lo = Mask.equals({0, 0, 1, 1});
22675 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
22676 MVT ShuffleVT = MVT::v4f32;
22677 if (Depth == 1 && Root->getOpcode() == Shuffle)
22678 return false; // Nothing to do!
22679 Op = DAG.getBitcast(ShuffleVT, Input);
22680 DCI.AddToWorklist(Op.getNode());
22681 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
22682 DCI.AddToWorklist(Op.getNode());
22683 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22689 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
22690 // variants as none of these have single-instruction variants that are
22691 // superior to the UNPCK formulation.
22692 if (!FloatDomain && VT.is128BitVector() &&
22693 (Mask.equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
22694 Mask.equals({4, 4, 5, 5, 6, 6, 7, 7}) ||
22695 Mask.equals({0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7}) ||
22697 {8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}))) {
22698 bool Lo = Mask[0] == 0;
22699 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
22700 if (Depth == 1 && Root->getOpcode() == Shuffle)
22701 return false; // Nothing to do!
22703 switch (Mask.size()) {
22705 ShuffleVT = MVT::v8i16;
22708 ShuffleVT = MVT::v16i8;
22711 llvm_unreachable("Impossible mask size!");
22713 Op = DAG.getBitcast(ShuffleVT, Input);
22714 DCI.AddToWorklist(Op.getNode());
22715 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
22716 DCI.AddToWorklist(Op.getNode());
22717 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22722 // Don't try to re-form single instruction chains under any circumstances now
22723 // that we've done encoding canonicalization for them.
22727 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
22728 // can replace them with a single PSHUFB instruction profitably. Intel's
22729 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
22730 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
22731 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
22732 SmallVector<SDValue, 16> PSHUFBMask;
22733 int NumBytes = VT.getSizeInBits() / 8;
22734 int Ratio = NumBytes / Mask.size();
22735 for (int i = 0; i < NumBytes; ++i) {
22736 if (Mask[i / Ratio] == SM_SentinelUndef) {
22737 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
22740 int M = Mask[i / Ratio] != SM_SentinelZero
22741 ? Ratio * Mask[i / Ratio] + i % Ratio
22743 PSHUFBMask.push_back(DAG.getConstant(M, DL, MVT::i8));
22745 MVT ByteVT = MVT::getVectorVT(MVT::i8, NumBytes);
22746 Op = DAG.getBitcast(ByteVT, Input);
22747 DCI.AddToWorklist(Op.getNode());
22748 SDValue PSHUFBMaskOp =
22749 DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVT, PSHUFBMask);
22750 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
22751 Op = DAG.getNode(X86ISD::PSHUFB, DL, ByteVT, Op, PSHUFBMaskOp);
22752 DCI.AddToWorklist(Op.getNode());
22753 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22758 // Failed to find any combines.
22762 /// \brief Fully generic combining of x86 shuffle instructions.
22764 /// This should be the last combine run over the x86 shuffle instructions. Once
22765 /// they have been fully optimized, this will recursively consider all chains
22766 /// of single-use shuffle instructions, build a generic model of the cumulative
22767 /// shuffle operation, and check for simpler instructions which implement this
22768 /// operation. We use this primarily for two purposes:
22770 /// 1) Collapse generic shuffles to specialized single instructions when
22771 /// equivalent. In most cases, this is just an encoding size win, but
22772 /// sometimes we will collapse multiple generic shuffles into a single
22773 /// special-purpose shuffle.
22774 /// 2) Look for sequences of shuffle instructions with 3 or more total
22775 /// instructions, and replace them with the slightly more expensive SSSE3
22776 /// PSHUFB instruction if available. We do this as the last combining step
22777 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
22778 /// a suitable short sequence of other instructions. The PHUFB will either
22779 /// use a register or have to read from memory and so is slightly (but only
22780 /// slightly) more expensive than the other shuffle instructions.
22782 /// Because this is inherently a quadratic operation (for each shuffle in
22783 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
22784 /// This should never be an issue in practice as the shuffle lowering doesn't
22785 /// produce sequences of more than 8 instructions.
22787 /// FIXME: We will currently miss some cases where the redundant shuffling
22788 /// would simplify under the threshold for PSHUFB formation because of
22789 /// combine-ordering. To fix this, we should do the redundant instruction
22790 /// combining in this recursive walk.
22791 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
22792 ArrayRef<int> RootMask,
22793 int Depth, bool HasPSHUFB,
22795 TargetLowering::DAGCombinerInfo &DCI,
22796 const X86Subtarget *Subtarget) {
22797 // Bound the depth of our recursive combine because this is ultimately
22798 // quadratic in nature.
22802 // Directly rip through bitcasts to find the underlying operand.
22803 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
22804 Op = Op.getOperand(0);
22806 MVT VT = Op.getSimpleValueType();
22807 if (!VT.isVector())
22808 return false; // Bail if we hit a non-vector.
22810 assert(Root.getSimpleValueType().isVector() &&
22811 "Shuffles operate on vector types!");
22812 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
22813 "Can only combine shuffles of the same vector register size.");
22815 if (!isTargetShuffle(Op.getOpcode()))
22817 SmallVector<int, 16> OpMask;
22819 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
22820 // We only can combine unary shuffles which we can decode the mask for.
22821 if (!HaveMask || !IsUnary)
22824 assert(VT.getVectorNumElements() == OpMask.size() &&
22825 "Different mask size from vector size!");
22826 assert(((RootMask.size() > OpMask.size() &&
22827 RootMask.size() % OpMask.size() == 0) ||
22828 (OpMask.size() > RootMask.size() &&
22829 OpMask.size() % RootMask.size() == 0) ||
22830 OpMask.size() == RootMask.size()) &&
22831 "The smaller number of elements must divide the larger.");
22832 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
22833 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
22834 assert(((RootRatio == 1 && OpRatio == 1) ||
22835 (RootRatio == 1) != (OpRatio == 1)) &&
22836 "Must not have a ratio for both incoming and op masks!");
22838 SmallVector<int, 16> Mask;
22839 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
22841 // Merge this shuffle operation's mask into our accumulated mask. Note that
22842 // this shuffle's mask will be the first applied to the input, followed by the
22843 // root mask to get us all the way to the root value arrangement. The reason
22844 // for this order is that we are recursing up the operation chain.
22845 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
22846 int RootIdx = i / RootRatio;
22847 if (RootMask[RootIdx] < 0) {
22848 // This is a zero or undef lane, we're done.
22849 Mask.push_back(RootMask[RootIdx]);
22853 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
22854 int OpIdx = RootMaskedIdx / OpRatio;
22855 if (OpMask[OpIdx] < 0) {
22856 // The incoming lanes are zero or undef, it doesn't matter which ones we
22858 Mask.push_back(OpMask[OpIdx]);
22862 // Ok, we have non-zero lanes, map them through.
22863 Mask.push_back(OpMask[OpIdx] * OpRatio +
22864 RootMaskedIdx % OpRatio);
22867 // See if we can recurse into the operand to combine more things.
22868 switch (Op.getOpcode()) {
22869 case X86ISD::PSHUFB:
22871 case X86ISD::PSHUFD:
22872 case X86ISD::PSHUFHW:
22873 case X86ISD::PSHUFLW:
22874 if (Op.getOperand(0).hasOneUse() &&
22875 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
22876 HasPSHUFB, DAG, DCI, Subtarget))
22880 case X86ISD::UNPCKL:
22881 case X86ISD::UNPCKH:
22882 assert(Op.getOperand(0) == Op.getOperand(1) &&
22883 "We only combine unary shuffles!");
22884 // We can't check for single use, we have to check that this shuffle is the
22886 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
22887 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
22888 HasPSHUFB, DAG, DCI, Subtarget))
22893 // Minor canonicalization of the accumulated shuffle mask to make it easier
22894 // to match below. All this does is detect masks with squential pairs of
22895 // elements, and shrink them to the half-width mask. It does this in a loop
22896 // so it will reduce the size of the mask to the minimal width mask which
22897 // performs an equivalent shuffle.
22898 SmallVector<int, 16> WidenedMask;
22899 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
22900 Mask = std::move(WidenedMask);
22901 WidenedMask.clear();
22904 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
22908 /// \brief Get the PSHUF-style mask from PSHUF node.
22910 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
22911 /// PSHUF-style masks that can be reused with such instructions.
22912 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
22913 MVT VT = N.getSimpleValueType();
22914 SmallVector<int, 4> Mask;
22916 bool HaveMask = getTargetShuffleMask(N.getNode(), VT, Mask, IsUnary);
22920 // If we have more than 128-bits, only the low 128-bits of shuffle mask
22921 // matter. Check that the upper masks are repeats and remove them.
22922 if (VT.getSizeInBits() > 128) {
22923 int LaneElts = 128 / VT.getScalarSizeInBits();
22925 for (int i = 1, NumLanes = VT.getSizeInBits() / 128; i < NumLanes; ++i)
22926 for (int j = 0; j < LaneElts; ++j)
22927 assert(Mask[j] == Mask[i * LaneElts + j] - (LaneElts * i) &&
22928 "Mask doesn't repeat in high 128-bit lanes!");
22930 Mask.resize(LaneElts);
22933 switch (N.getOpcode()) {
22934 case X86ISD::PSHUFD:
22936 case X86ISD::PSHUFLW:
22939 case X86ISD::PSHUFHW:
22940 Mask.erase(Mask.begin(), Mask.begin() + 4);
22941 for (int &M : Mask)
22945 llvm_unreachable("No valid shuffle instruction found!");
22949 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
22951 /// We walk up the chain and look for a combinable shuffle, skipping over
22952 /// shuffles that we could hoist this shuffle's transformation past without
22953 /// altering anything.
22955 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
22957 TargetLowering::DAGCombinerInfo &DCI) {
22958 assert(N.getOpcode() == X86ISD::PSHUFD &&
22959 "Called with something other than an x86 128-bit half shuffle!");
22962 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
22963 // of the shuffles in the chain so that we can form a fresh chain to replace
22965 SmallVector<SDValue, 8> Chain;
22966 SDValue V = N.getOperand(0);
22967 for (; V.hasOneUse(); V = V.getOperand(0)) {
22968 switch (V.getOpcode()) {
22970 return SDValue(); // Nothing combined!
22973 // Skip bitcasts as we always know the type for the target specific
22977 case X86ISD::PSHUFD:
22978 // Found another dword shuffle.
22981 case X86ISD::PSHUFLW:
22982 // Check that the low words (being shuffled) are the identity in the
22983 // dword shuffle, and the high words are self-contained.
22984 if (Mask[0] != 0 || Mask[1] != 1 ||
22985 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
22988 Chain.push_back(V);
22991 case X86ISD::PSHUFHW:
22992 // Check that the high words (being shuffled) are the identity in the
22993 // dword shuffle, and the low words are self-contained.
22994 if (Mask[2] != 2 || Mask[3] != 3 ||
22995 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
22998 Chain.push_back(V);
23001 case X86ISD::UNPCKL:
23002 case X86ISD::UNPCKH:
23003 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
23004 // shuffle into a preceding word shuffle.
23005 if (V.getSimpleValueType().getVectorElementType() != MVT::i8 &&
23006 V.getSimpleValueType().getVectorElementType() != MVT::i16)
23009 // Search for a half-shuffle which we can combine with.
23010 unsigned CombineOp =
23011 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
23012 if (V.getOperand(0) != V.getOperand(1) ||
23013 !V->isOnlyUserOf(V.getOperand(0).getNode()))
23015 Chain.push_back(V);
23016 V = V.getOperand(0);
23018 switch (V.getOpcode()) {
23020 return SDValue(); // Nothing to combine.
23022 case X86ISD::PSHUFLW:
23023 case X86ISD::PSHUFHW:
23024 if (V.getOpcode() == CombineOp)
23027 Chain.push_back(V);
23031 V = V.getOperand(0);
23035 } while (V.hasOneUse());
23038 // Break out of the loop if we break out of the switch.
23042 if (!V.hasOneUse())
23043 // We fell out of the loop without finding a viable combining instruction.
23046 // Merge this node's mask and our incoming mask.
23047 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
23048 for (int &M : Mask)
23050 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
23051 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
23053 // Rebuild the chain around this new shuffle.
23054 while (!Chain.empty()) {
23055 SDValue W = Chain.pop_back_val();
23057 if (V.getValueType() != W.getOperand(0).getValueType())
23058 V = DAG.getBitcast(W.getOperand(0).getValueType(), V);
23060 switch (W.getOpcode()) {
23062 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
23064 case X86ISD::UNPCKL:
23065 case X86ISD::UNPCKH:
23066 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
23069 case X86ISD::PSHUFD:
23070 case X86ISD::PSHUFLW:
23071 case X86ISD::PSHUFHW:
23072 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
23076 if (V.getValueType() != N.getValueType())
23077 V = DAG.getBitcast(N.getValueType(), V);
23079 // Return the new chain to replace N.
23083 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or
23086 /// We walk up the chain, skipping shuffles of the other half and looking
23087 /// through shuffles which switch halves trying to find a shuffle of the same
23088 /// pair of dwords.
23089 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
23091 TargetLowering::DAGCombinerInfo &DCI) {
23093 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
23094 "Called with something other than an x86 128-bit half shuffle!");
23096 unsigned CombineOpcode = N.getOpcode();
23098 // Walk up a single-use chain looking for a combinable shuffle.
23099 SDValue V = N.getOperand(0);
23100 for (; V.hasOneUse(); V = V.getOperand(0)) {
23101 switch (V.getOpcode()) {
23103 return false; // Nothing combined!
23106 // Skip bitcasts as we always know the type for the target specific
23110 case X86ISD::PSHUFLW:
23111 case X86ISD::PSHUFHW:
23112 if (V.getOpcode() == CombineOpcode)
23115 // Other-half shuffles are no-ops.
23118 // Break out of the loop if we break out of the switch.
23122 if (!V.hasOneUse())
23123 // We fell out of the loop without finding a viable combining instruction.
23126 // Combine away the bottom node as its shuffle will be accumulated into
23127 // a preceding shuffle.
23128 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
23130 // Record the old value.
23133 // Merge this node's mask and our incoming mask (adjusted to account for all
23134 // the pshufd instructions encountered).
23135 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
23136 for (int &M : Mask)
23138 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
23139 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
23141 // Check that the shuffles didn't cancel each other out. If not, we need to
23142 // combine to the new one.
23144 // Replace the combinable shuffle with the combined one, updating all users
23145 // so that we re-evaluate the chain here.
23146 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
23151 /// \brief Try to combine x86 target specific shuffles.
23152 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
23153 TargetLowering::DAGCombinerInfo &DCI,
23154 const X86Subtarget *Subtarget) {
23156 MVT VT = N.getSimpleValueType();
23157 SmallVector<int, 4> Mask;
23159 switch (N.getOpcode()) {
23160 case X86ISD::PSHUFD:
23161 case X86ISD::PSHUFLW:
23162 case X86ISD::PSHUFHW:
23163 Mask = getPSHUFShuffleMask(N);
23164 assert(Mask.size() == 4);
23166 case X86ISD::UNPCKL: {
23167 // Combine X86ISD::UNPCKL and ISD::VECTOR_SHUFFLE into X86ISD::UNPCKH, in
23168 // which X86ISD::UNPCKL has a ISD::UNDEF operand, and ISD::VECTOR_SHUFFLE
23169 // moves upper half elements into the lower half part. For example:
23171 // t2: v16i8 = vector_shuffle<8,9,10,11,12,13,14,15,u,u,u,u,u,u,u,u> t1,
23173 // t3: v16i8 = X86ISD::UNPCKL undef:v16i8, t2
23175 // will be combined to:
23177 // t3: v16i8 = X86ISD::UNPCKH undef:v16i8, t1
23179 // This is only for 128-bit vectors. From SSE4.1 onward this combine may not
23180 // happen due to advanced instructions.
23181 if (!VT.is128BitVector())
23184 auto Op0 = N.getOperand(0);
23185 auto Op1 = N.getOperand(1);
23186 if (Op0.getOpcode() == ISD::UNDEF &&
23187 Op1.getNode()->getOpcode() == ISD::VECTOR_SHUFFLE) {
23188 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Op1.getNode())->getMask();
23190 unsigned NumElts = VT.getVectorNumElements();
23191 SmallVector<int, 8> ExpectedMask(NumElts, -1);
23192 std::iota(ExpectedMask.begin(), ExpectedMask.begin() + NumElts / 2,
23195 auto ShufOp = Op1.getOperand(0);
23196 if (isShuffleEquivalent(Op1, ShufOp, Mask, ExpectedMask))
23197 return DAG.getNode(X86ISD::UNPCKH, DL, VT, N.getOperand(0), ShufOp);
23205 // Nuke no-op shuffles that show up after combining.
23206 if (isNoopShuffleMask(Mask))
23207 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
23209 // Look for simplifications involving one or two shuffle instructions.
23210 SDValue V = N.getOperand(0);
23211 switch (N.getOpcode()) {
23214 case X86ISD::PSHUFLW:
23215 case X86ISD::PSHUFHW:
23216 assert(VT.getVectorElementType() == MVT::i16 && "Bad word shuffle type!");
23218 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
23219 return SDValue(); // We combined away this shuffle, so we're done.
23221 // See if this reduces to a PSHUFD which is no more expensive and can
23222 // combine with more operations. Note that it has to at least flip the
23223 // dwords as otherwise it would have been removed as a no-op.
23224 if (makeArrayRef(Mask).equals({2, 3, 0, 1})) {
23225 int DMask[] = {0, 1, 2, 3};
23226 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
23227 DMask[DOffset + 0] = DOffset + 1;
23228 DMask[DOffset + 1] = DOffset + 0;
23229 MVT DVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
23230 V = DAG.getBitcast(DVT, V);
23231 DCI.AddToWorklist(V.getNode());
23232 V = DAG.getNode(X86ISD::PSHUFD, DL, DVT, V,
23233 getV4X86ShuffleImm8ForMask(DMask, DL, DAG));
23234 DCI.AddToWorklist(V.getNode());
23235 return DAG.getBitcast(VT, V);
23238 // Look for shuffle patterns which can be implemented as a single unpack.
23239 // FIXME: This doesn't handle the location of the PSHUFD generically, and
23240 // only works when we have a PSHUFD followed by two half-shuffles.
23241 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
23242 (V.getOpcode() == X86ISD::PSHUFLW ||
23243 V.getOpcode() == X86ISD::PSHUFHW) &&
23244 V.getOpcode() != N.getOpcode() &&
23246 SDValue D = V.getOperand(0);
23247 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
23248 D = D.getOperand(0);
23249 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
23250 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
23251 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
23252 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
23253 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
23255 for (int i = 0; i < 4; ++i) {
23256 WordMask[i + NOffset] = Mask[i] + NOffset;
23257 WordMask[i + VOffset] = VMask[i] + VOffset;
23259 // Map the word mask through the DWord mask.
23261 for (int i = 0; i < 8; ++i)
23262 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
23263 if (makeArrayRef(MappedMask).equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
23264 makeArrayRef(MappedMask).equals({4, 4, 5, 5, 6, 6, 7, 7})) {
23265 // We can replace all three shuffles with an unpack.
23266 V = DAG.getBitcast(VT, D.getOperand(0));
23267 DCI.AddToWorklist(V.getNode());
23268 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
23277 case X86ISD::PSHUFD:
23278 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
23287 /// \brief Try to combine a shuffle into a target-specific add-sub node.
23289 /// We combine this directly on the abstract vector shuffle nodes so it is
23290 /// easier to generically match. We also insert dummy vector shuffle nodes for
23291 /// the operands which explicitly discard the lanes which are unused by this
23292 /// operation to try to flow through the rest of the combiner the fact that
23293 /// they're unused.
23294 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
23296 EVT VT = N->getValueType(0);
23298 // We only handle target-independent shuffles.
23299 // FIXME: It would be easy and harmless to use the target shuffle mask
23300 // extraction tool to support more.
23301 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
23304 auto *SVN = cast<ShuffleVectorSDNode>(N);
23305 SmallVector<int, 8> Mask;
23306 for (int M : SVN->getMask())
23309 SDValue V1 = N->getOperand(0);
23310 SDValue V2 = N->getOperand(1);
23312 // We require the first shuffle operand to be the FSUB node, and the second to
23313 // be the FADD node.
23314 if (V1.getOpcode() == ISD::FADD && V2.getOpcode() == ISD::FSUB) {
23315 ShuffleVectorSDNode::commuteMask(Mask);
23317 } else if (V1.getOpcode() != ISD::FSUB || V2.getOpcode() != ISD::FADD)
23320 // If there are other uses of these operations we can't fold them.
23321 if (!V1->hasOneUse() || !V2->hasOneUse())
23324 // Ensure that both operations have the same operands. Note that we can
23325 // commute the FADD operands.
23326 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
23327 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
23328 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
23331 // We're looking for blends between FADD and FSUB nodes. We insist on these
23332 // nodes being lined up in a specific expected pattern.
23333 if (!(isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
23334 isShuffleEquivalent(V1, V2, Mask, {0, 5, 2, 7}) ||
23335 isShuffleEquivalent(V1, V2, Mask, {0, 9, 2, 11, 4, 13, 6, 15})))
23338 // Only specific types are legal at this point, assert so we notice if and
23339 // when these change.
23340 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
23341 VT == MVT::v4f64) &&
23342 "Unknown vector type encountered!");
23344 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
23347 /// PerformShuffleCombine - Performs several different shuffle combines.
23348 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
23349 TargetLowering::DAGCombinerInfo &DCI,
23350 const X86Subtarget *Subtarget) {
23352 SDValue N0 = N->getOperand(0);
23353 SDValue N1 = N->getOperand(1);
23354 EVT VT = N->getValueType(0);
23356 // Don't create instructions with illegal types after legalize types has run.
23357 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23358 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
23361 // If we have legalized the vector types, look for blends of FADD and FSUB
23362 // nodes that we can fuse into an ADDSUB node.
23363 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
23364 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
23367 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
23368 if (TLI.isTypeLegal(VT) && Subtarget->hasFp256() && VT.is256BitVector() &&
23369 N->getOpcode() == ISD::VECTOR_SHUFFLE)
23370 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
23372 // During Type Legalization, when promoting illegal vector types,
23373 // the backend might introduce new shuffle dag nodes and bitcasts.
23375 // This code performs the following transformation:
23376 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
23377 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
23379 // We do this only if both the bitcast and the BINOP dag nodes have
23380 // one use. Also, perform this transformation only if the new binary
23381 // operation is legal. This is to avoid introducing dag nodes that
23382 // potentially need to be further expanded (or custom lowered) into a
23383 // less optimal sequence of dag nodes.
23384 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
23385 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
23386 N0.getOpcode() == ISD::BITCAST) {
23387 SDValue BC0 = N0.getOperand(0);
23388 EVT SVT = BC0.getValueType();
23389 unsigned Opcode = BC0.getOpcode();
23390 unsigned NumElts = VT.getVectorNumElements();
23392 if (BC0.hasOneUse() && SVT.isVector() &&
23393 SVT.getVectorNumElements() * 2 == NumElts &&
23394 TLI.isOperationLegal(Opcode, VT)) {
23395 bool CanFold = false;
23407 unsigned SVTNumElts = SVT.getVectorNumElements();
23408 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
23409 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
23410 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
23411 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
23412 CanFold = SVOp->getMaskElt(i) < 0;
23415 SDValue BC00 = DAG.getBitcast(VT, BC0.getOperand(0));
23416 SDValue BC01 = DAG.getBitcast(VT, BC0.getOperand(1));
23417 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
23418 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
23423 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
23424 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
23425 // consecutive, non-overlapping, and in the right order.
23426 SmallVector<SDValue, 16> Elts;
23427 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
23428 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
23430 if (SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true))
23433 if (isTargetShuffle(N->getOpcode())) {
23435 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
23436 if (Shuffle.getNode())
23439 // Try recursively combining arbitrary sequences of x86 shuffle
23440 // instructions into higher-order shuffles. We do this after combining
23441 // specific PSHUF instruction sequences into their minimal form so that we
23442 // can evaluate how many specialized shuffle instructions are involved in
23443 // a particular chain.
23444 SmallVector<int, 1> NonceMask; // Just a placeholder.
23445 NonceMask.push_back(0);
23446 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
23447 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
23449 return SDValue(); // This routine will use CombineTo to replace N.
23455 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
23456 /// specific shuffle of a load can be folded into a single element load.
23457 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
23458 /// shuffles have been custom lowered so we need to handle those here.
23459 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
23460 TargetLowering::DAGCombinerInfo &DCI) {
23461 if (DCI.isBeforeLegalizeOps())
23464 SDValue InVec = N->getOperand(0);
23465 SDValue EltNo = N->getOperand(1);
23467 if (!isa<ConstantSDNode>(EltNo))
23470 EVT OriginalVT = InVec.getValueType();
23472 if (InVec.getOpcode() == ISD::BITCAST) {
23473 // Don't duplicate a load with other uses.
23474 if (!InVec.hasOneUse())
23476 EVT BCVT = InVec.getOperand(0).getValueType();
23477 if (!BCVT.isVector() ||
23478 BCVT.getVectorNumElements() != OriginalVT.getVectorNumElements())
23480 InVec = InVec.getOperand(0);
23483 EVT CurrentVT = InVec.getValueType();
23485 if (!isTargetShuffle(InVec.getOpcode()))
23488 // Don't duplicate a load with other uses.
23489 if (!InVec.hasOneUse())
23492 SmallVector<int, 16> ShuffleMask;
23494 if (!getTargetShuffleMask(InVec.getNode(), CurrentVT.getSimpleVT(),
23495 ShuffleMask, UnaryShuffle))
23498 // Select the input vector, guarding against out of range extract vector.
23499 unsigned NumElems = CurrentVT.getVectorNumElements();
23500 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
23501 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
23502 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
23503 : InVec.getOperand(1);
23505 // If inputs to shuffle are the same for both ops, then allow 2 uses
23506 unsigned AllowedUses = InVec.getNumOperands() > 1 &&
23507 InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
23509 if (LdNode.getOpcode() == ISD::BITCAST) {
23510 // Don't duplicate a load with other uses.
23511 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
23514 AllowedUses = 1; // only allow 1 load use if we have a bitcast
23515 LdNode = LdNode.getOperand(0);
23518 if (!ISD::isNormalLoad(LdNode.getNode()))
23521 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
23523 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
23526 EVT EltVT = N->getValueType(0);
23527 // If there's a bitcast before the shuffle, check if the load type and
23528 // alignment is valid.
23529 unsigned Align = LN0->getAlignment();
23530 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23531 unsigned NewAlign = DAG.getDataLayout().getABITypeAlignment(
23532 EltVT.getTypeForEVT(*DAG.getContext()));
23534 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
23537 // All checks match so transform back to vector_shuffle so that DAG combiner
23538 // can finish the job
23541 // Create shuffle node taking into account the case that its a unary shuffle
23542 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(CurrentVT)
23543 : InVec.getOperand(1);
23544 Shuffle = DAG.getVectorShuffle(CurrentVT, dl,
23545 InVec.getOperand(0), Shuffle,
23547 Shuffle = DAG.getBitcast(OriginalVT, Shuffle);
23548 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
23552 static SDValue PerformBITCASTCombine(SDNode *N, SelectionDAG &DAG,
23553 const X86Subtarget *Subtarget) {
23554 SDValue N0 = N->getOperand(0);
23555 EVT VT = N->getValueType(0);
23557 // Detect bitcasts between i32 to x86mmx low word. Since MMX types are
23558 // special and don't usually play with other vector types, it's better to
23559 // handle them early to be sure we emit efficient code by avoiding
23560 // store-load conversions.
23561 if (VT == MVT::x86mmx && N0.getOpcode() == ISD::BUILD_VECTOR &&
23562 N0.getValueType() == MVT::v2i32 &&
23563 isNullConstant(N0.getOperand(1))) {
23564 SDValue N00 = N0->getOperand(0);
23565 if (N00.getValueType() == MVT::i32)
23566 return DAG.getNode(X86ISD::MMX_MOVW2D, SDLoc(N00), VT, N00);
23569 // Convert a bitcasted integer logic operation that has one bitcasted
23570 // floating-point operand and one constant operand into a floating-point
23571 // logic operation. This may create a load of the constant, but that is
23572 // cheaper than materializing the constant in an integer register and
23573 // transferring it to an SSE register or transferring the SSE operand to
23574 // integer register and back.
23576 switch (N0.getOpcode()) {
23577 case ISD::AND: FPOpcode = X86ISD::FAND; break;
23578 case ISD::OR: FPOpcode = X86ISD::FOR; break;
23579 case ISD::XOR: FPOpcode = X86ISD::FXOR; break;
23580 default: return SDValue();
23582 if (((Subtarget->hasSSE1() && VT == MVT::f32) ||
23583 (Subtarget->hasSSE2() && VT == MVT::f64)) &&
23584 isa<ConstantSDNode>(N0.getOperand(1)) &&
23585 N0.getOperand(0).getOpcode() == ISD::BITCAST &&
23586 N0.getOperand(0).getOperand(0).getValueType() == VT) {
23587 SDValue N000 = N0.getOperand(0).getOperand(0);
23588 SDValue FPConst = DAG.getBitcast(VT, N0.getOperand(1));
23589 return DAG.getNode(FPOpcode, SDLoc(N0), VT, N000, FPConst);
23595 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
23596 /// generation and convert it from being a bunch of shuffles and extracts
23597 /// into a somewhat faster sequence. For i686, the best sequence is apparently
23598 /// storing the value and loading scalars back, while for x64 we should
23599 /// use 64-bit extracts and shifts.
23600 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
23601 TargetLowering::DAGCombinerInfo &DCI) {
23602 if (SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI))
23605 SDValue InputVector = N->getOperand(0);
23606 SDLoc dl(InputVector);
23607 // Detect mmx to i32 conversion through a v2i32 elt extract.
23608 if (InputVector.getOpcode() == ISD::BITCAST && InputVector.hasOneUse() &&
23609 N->getValueType(0) == MVT::i32 &&
23610 InputVector.getValueType() == MVT::v2i32) {
23612 // The bitcast source is a direct mmx result.
23613 SDValue MMXSrc = InputVector.getNode()->getOperand(0);
23614 if (MMXSrc.getValueType() == MVT::x86mmx)
23615 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
23616 N->getValueType(0),
23617 InputVector.getNode()->getOperand(0));
23619 // The mmx is indirect: (i64 extract_elt (v1i64 bitcast (x86mmx ...))).
23620 if (MMXSrc.getOpcode() == ISD::EXTRACT_VECTOR_ELT && MMXSrc.hasOneUse() &&
23621 MMXSrc.getValueType() == MVT::i64) {
23622 SDValue MMXSrcOp = MMXSrc.getOperand(0);
23623 if (MMXSrcOp.hasOneUse() && MMXSrcOp.getOpcode() == ISD::BITCAST &&
23624 MMXSrcOp.getValueType() == MVT::v1i64 &&
23625 MMXSrcOp.getOperand(0).getValueType() == MVT::x86mmx)
23626 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
23627 N->getValueType(0), MMXSrcOp.getOperand(0));
23631 EVT VT = N->getValueType(0);
23633 if (VT == MVT::i1 && isa<ConstantSDNode>(N->getOperand(1)) &&
23634 InputVector.getOpcode() == ISD::BITCAST &&
23635 isa<ConstantSDNode>(InputVector.getOperand(0))) {
23636 uint64_t ExtractedElt =
23637 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
23638 uint64_t InputValue =
23639 cast<ConstantSDNode>(InputVector.getOperand(0))->getZExtValue();
23640 uint64_t Res = (InputValue >> ExtractedElt) & 1;
23641 return DAG.getConstant(Res, dl, MVT::i1);
23643 // Only operate on vectors of 4 elements, where the alternative shuffling
23644 // gets to be more expensive.
23645 if (InputVector.getValueType() != MVT::v4i32)
23648 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
23649 // single use which is a sign-extend or zero-extend, and all elements are
23651 SmallVector<SDNode *, 4> Uses;
23652 unsigned ExtractedElements = 0;
23653 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
23654 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
23655 if (UI.getUse().getResNo() != InputVector.getResNo())
23658 SDNode *Extract = *UI;
23659 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
23662 if (Extract->getValueType(0) != MVT::i32)
23664 if (!Extract->hasOneUse())
23666 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
23667 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
23669 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
23672 // Record which element was extracted.
23673 ExtractedElements |=
23674 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
23676 Uses.push_back(Extract);
23679 // If not all the elements were used, this may not be worthwhile.
23680 if (ExtractedElements != 15)
23683 // Ok, we've now decided to do the transformation.
23684 // If 64-bit shifts are legal, use the extract-shift sequence,
23685 // otherwise bounce the vector off the cache.
23686 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23689 if (TLI.isOperationLegal(ISD::SRA, MVT::i64)) {
23690 SDValue Cst = DAG.getBitcast(MVT::v2i64, InputVector);
23691 auto &DL = DAG.getDataLayout();
23692 EVT VecIdxTy = DAG.getTargetLoweringInfo().getVectorIdxTy(DL);
23693 SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
23694 DAG.getConstant(0, dl, VecIdxTy));
23695 SDValue TopHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
23696 DAG.getConstant(1, dl, VecIdxTy));
23698 SDValue ShAmt = DAG.getConstant(
23699 32, dl, DAG.getTargetLoweringInfo().getShiftAmountTy(MVT::i64, DL));
23700 Vals[0] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BottomHalf);
23701 Vals[1] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
23702 DAG.getNode(ISD::SRA, dl, MVT::i64, BottomHalf, ShAmt));
23703 Vals[2] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, TopHalf);
23704 Vals[3] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
23705 DAG.getNode(ISD::SRA, dl, MVT::i64, TopHalf, ShAmt));
23707 // Store the value to a temporary stack slot.
23708 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
23709 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
23710 MachinePointerInfo(), false, false, 0);
23712 EVT ElementType = InputVector.getValueType().getVectorElementType();
23713 unsigned EltSize = ElementType.getSizeInBits() / 8;
23715 // Replace each use (extract) with a load of the appropriate element.
23716 for (unsigned i = 0; i < 4; ++i) {
23717 uint64_t Offset = EltSize * i;
23718 auto PtrVT = TLI.getPointerTy(DAG.getDataLayout());
23719 SDValue OffsetVal = DAG.getConstant(Offset, dl, PtrVT);
23721 SDValue ScalarAddr =
23722 DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, OffsetVal);
23724 // Load the scalar.
23725 Vals[i] = DAG.getLoad(ElementType, dl, Ch,
23726 ScalarAddr, MachinePointerInfo(),
23727 false, false, false, 0);
23732 // Replace the extracts
23733 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
23734 UE = Uses.end(); UI != UE; ++UI) {
23735 SDNode *Extract = *UI;
23737 SDValue Idx = Extract->getOperand(1);
23738 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
23739 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), Vals[IdxVal]);
23742 // The replacement was made in place; don't return anything.
23747 transformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
23748 const X86Subtarget *Subtarget) {
23750 SDValue Cond = N->getOperand(0);
23751 SDValue LHS = N->getOperand(1);
23752 SDValue RHS = N->getOperand(2);
23754 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
23755 SDValue CondSrc = Cond->getOperand(0);
23756 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
23757 Cond = CondSrc->getOperand(0);
23760 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
23763 // A vselect where all conditions and data are constants can be optimized into
23764 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
23765 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
23766 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
23769 unsigned MaskValue = 0;
23770 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
23773 MVT VT = N->getSimpleValueType(0);
23774 unsigned NumElems = VT.getVectorNumElements();
23775 SmallVector<int, 8> ShuffleMask(NumElems, -1);
23776 for (unsigned i = 0; i < NumElems; ++i) {
23777 // Be sure we emit undef where we can.
23778 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
23779 ShuffleMask[i] = -1;
23781 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
23784 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23785 if (!TLI.isShuffleMaskLegal(ShuffleMask, VT))
23787 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
23790 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
23792 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
23793 TargetLowering::DAGCombinerInfo &DCI,
23794 const X86Subtarget *Subtarget) {
23796 SDValue Cond = N->getOperand(0);
23797 // Get the LHS/RHS of the select.
23798 SDValue LHS = N->getOperand(1);
23799 SDValue RHS = N->getOperand(2);
23800 EVT VT = LHS.getValueType();
23801 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23803 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
23804 // instructions match the semantics of the common C idiom x<y?x:y but not
23805 // x<=y?x:y, because of how they handle negative zero (which can be
23806 // ignored in unsafe-math mode).
23807 // We also try to create v2f32 min/max nodes, which we later widen to v4f32.
23808 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
23809 VT != MVT::f80 && (TLI.isTypeLegal(VT) || VT == MVT::v2f32) &&
23810 (Subtarget->hasSSE2() ||
23811 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
23812 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23814 unsigned Opcode = 0;
23815 // Check for x CC y ? x : y.
23816 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
23817 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
23821 // Converting this to a min would handle NaNs incorrectly, and swapping
23822 // the operands would cause it to handle comparisons between positive
23823 // and negative zero incorrectly.
23824 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
23825 if (!DAG.getTarget().Options.UnsafeFPMath &&
23826 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
23828 std::swap(LHS, RHS);
23830 Opcode = X86ISD::FMIN;
23833 // Converting this to a min would handle comparisons between positive
23834 // and negative zero incorrectly.
23835 if (!DAG.getTarget().Options.UnsafeFPMath &&
23836 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
23838 Opcode = X86ISD::FMIN;
23841 // Converting this to a min would handle both negative zeros and NaNs
23842 // incorrectly, but we can swap the operands to fix both.
23843 std::swap(LHS, RHS);
23847 Opcode = X86ISD::FMIN;
23851 // Converting this to a max would handle comparisons between positive
23852 // and negative zero incorrectly.
23853 if (!DAG.getTarget().Options.UnsafeFPMath &&
23854 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
23856 Opcode = X86ISD::FMAX;
23859 // Converting this to a max would handle NaNs incorrectly, and swapping
23860 // the operands would cause it to handle comparisons between positive
23861 // and negative zero incorrectly.
23862 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
23863 if (!DAG.getTarget().Options.UnsafeFPMath &&
23864 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
23866 std::swap(LHS, RHS);
23868 Opcode = X86ISD::FMAX;
23871 // Converting this to a max would handle both negative zeros and NaNs
23872 // incorrectly, but we can swap the operands to fix both.
23873 std::swap(LHS, RHS);
23877 Opcode = X86ISD::FMAX;
23880 // Check for x CC y ? y : x -- a min/max with reversed arms.
23881 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
23882 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
23886 // Converting this to a min would handle comparisons between positive
23887 // and negative zero incorrectly, and swapping the operands would
23888 // cause it to handle NaNs incorrectly.
23889 if (!DAG.getTarget().Options.UnsafeFPMath &&
23890 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
23891 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23893 std::swap(LHS, RHS);
23895 Opcode = X86ISD::FMIN;
23898 // Converting this to a min would handle NaNs incorrectly.
23899 if (!DAG.getTarget().Options.UnsafeFPMath &&
23900 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
23902 Opcode = X86ISD::FMIN;
23905 // Converting this to a min would handle both negative zeros and NaNs
23906 // incorrectly, but we can swap the operands to fix both.
23907 std::swap(LHS, RHS);
23911 Opcode = X86ISD::FMIN;
23915 // Converting this to a max would handle NaNs incorrectly.
23916 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23918 Opcode = X86ISD::FMAX;
23921 // Converting this to a max would handle comparisons between positive
23922 // and negative zero incorrectly, and swapping the operands would
23923 // cause it to handle NaNs incorrectly.
23924 if (!DAG.getTarget().Options.UnsafeFPMath &&
23925 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
23926 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23928 std::swap(LHS, RHS);
23930 Opcode = X86ISD::FMAX;
23933 // Converting this to a max would handle both negative zeros and NaNs
23934 // incorrectly, but we can swap the operands to fix both.
23935 std::swap(LHS, RHS);
23939 Opcode = X86ISD::FMAX;
23945 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
23948 EVT CondVT = Cond.getValueType();
23949 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
23950 CondVT.getVectorElementType() == MVT::i1) {
23951 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
23952 // lowering on KNL. In this case we convert it to
23953 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
23954 // The same situation for all 128 and 256-bit vectors of i8 and i16.
23955 // Since SKX these selects have a proper lowering.
23956 EVT OpVT = LHS.getValueType();
23957 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
23958 (OpVT.getVectorElementType() == MVT::i8 ||
23959 OpVT.getVectorElementType() == MVT::i16) &&
23960 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
23961 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
23962 DCI.AddToWorklist(Cond.getNode());
23963 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
23966 // If this is a select between two integer constants, try to do some
23968 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
23969 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
23970 // Don't do this for crazy integer types.
23971 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
23972 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
23973 // so that TrueC (the true value) is larger than FalseC.
23974 bool NeedsCondInvert = false;
23976 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
23977 // Efficiently invertible.
23978 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
23979 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
23980 isa<ConstantSDNode>(Cond.getOperand(1))))) {
23981 NeedsCondInvert = true;
23982 std::swap(TrueC, FalseC);
23985 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
23986 if (FalseC->getAPIntValue() == 0 &&
23987 TrueC->getAPIntValue().isPowerOf2()) {
23988 if (NeedsCondInvert) // Invert the condition if needed.
23989 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23990 DAG.getConstant(1, DL, Cond.getValueType()));
23992 // Zero extend the condition if needed.
23993 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
23995 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
23996 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
23997 DAG.getConstant(ShAmt, DL, MVT::i8));
24000 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
24001 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
24002 if (NeedsCondInvert) // Invert the condition if needed.
24003 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
24004 DAG.getConstant(1, DL, Cond.getValueType()));
24006 // Zero extend the condition if needed.
24007 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
24008 FalseC->getValueType(0), Cond);
24009 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
24010 SDValue(FalseC, 0));
24013 // Optimize cases that will turn into an LEA instruction. This requires
24014 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
24015 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
24016 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
24017 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
24019 bool isFastMultiplier = false;
24021 switch ((unsigned char)Diff) {
24023 case 1: // result = add base, cond
24024 case 2: // result = lea base( , cond*2)
24025 case 3: // result = lea base(cond, cond*2)
24026 case 4: // result = lea base( , cond*4)
24027 case 5: // result = lea base(cond, cond*4)
24028 case 8: // result = lea base( , cond*8)
24029 case 9: // result = lea base(cond, cond*8)
24030 isFastMultiplier = true;
24035 if (isFastMultiplier) {
24036 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
24037 if (NeedsCondInvert) // Invert the condition if needed.
24038 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
24039 DAG.getConstant(1, DL, Cond.getValueType()));
24041 // Zero extend the condition if needed.
24042 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
24044 // Scale the condition by the difference.
24046 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
24047 DAG.getConstant(Diff, DL,
24048 Cond.getValueType()));
24050 // Add the base if non-zero.
24051 if (FalseC->getAPIntValue() != 0)
24052 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
24053 SDValue(FalseC, 0));
24060 // Canonicalize max and min:
24061 // (x > y) ? x : y -> (x >= y) ? x : y
24062 // (x < y) ? x : y -> (x <= y) ? x : y
24063 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
24064 // the need for an extra compare
24065 // against zero. e.g.
24066 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
24068 // testl %edi, %edi
24070 // cmovgl %edi, %eax
24074 // cmovsl %eax, %edi
24075 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
24076 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
24077 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
24078 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
24083 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
24084 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
24085 Cond.getOperand(0), Cond.getOperand(1), NewCC);
24086 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
24091 // Early exit check
24092 if (!TLI.isTypeLegal(VT))
24095 // Match VSELECTs into subs with unsigned saturation.
24096 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
24097 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
24098 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
24099 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
24100 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
24102 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
24103 // left side invert the predicate to simplify logic below.
24105 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
24107 CC = ISD::getSetCCInverse(CC, true);
24108 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
24112 if (Other.getNode() && Other->getNumOperands() == 2 &&
24113 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
24114 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
24115 SDValue CondRHS = Cond->getOperand(1);
24117 // Look for a general sub with unsigned saturation first.
24118 // x >= y ? x-y : 0 --> subus x, y
24119 // x > y ? x-y : 0 --> subus x, y
24120 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
24121 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
24122 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
24124 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
24125 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
24126 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
24127 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
24128 // If the RHS is a constant we have to reverse the const
24129 // canonicalization.
24130 // x > C-1 ? x+-C : 0 --> subus x, C
24131 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
24132 CondRHSConst->getAPIntValue() ==
24133 (-OpRHSConst->getAPIntValue() - 1))
24134 return DAG.getNode(
24135 X86ISD::SUBUS, DL, VT, OpLHS,
24136 DAG.getConstant(-OpRHSConst->getAPIntValue(), DL, VT));
24138 // Another special case: If C was a sign bit, the sub has been
24139 // canonicalized into a xor.
24140 // FIXME: Would it be better to use computeKnownBits to determine
24141 // whether it's safe to decanonicalize the xor?
24142 // x s< 0 ? x^C : 0 --> subus x, C
24143 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
24144 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
24145 OpRHSConst->getAPIntValue().isSignBit())
24146 // Note that we have to rebuild the RHS constant here to ensure we
24147 // don't rely on particular values of undef lanes.
24148 return DAG.getNode(
24149 X86ISD::SUBUS, DL, VT, OpLHS,
24150 DAG.getConstant(OpRHSConst->getAPIntValue(), DL, VT));
24155 // Simplify vector selection if condition value type matches vselect
24157 if (N->getOpcode() == ISD::VSELECT && CondVT == VT) {
24158 assert(Cond.getValueType().isVector() &&
24159 "vector select expects a vector selector!");
24161 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
24162 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
24164 // Try invert the condition if true value is not all 1s and false value
24166 if (!TValIsAllOnes && !FValIsAllZeros &&
24167 // Check if the selector will be produced by CMPP*/PCMP*
24168 Cond.getOpcode() == ISD::SETCC &&
24169 // Check if SETCC has already been promoted
24170 TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT) ==
24172 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
24173 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
24175 if (TValIsAllZeros || FValIsAllOnes) {
24176 SDValue CC = Cond.getOperand(2);
24177 ISD::CondCode NewCC =
24178 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
24179 Cond.getOperand(0).getValueType().isInteger());
24180 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
24181 std::swap(LHS, RHS);
24182 TValIsAllOnes = FValIsAllOnes;
24183 FValIsAllZeros = TValIsAllZeros;
24187 if (TValIsAllOnes || FValIsAllZeros) {
24190 if (TValIsAllOnes && FValIsAllZeros)
24192 else if (TValIsAllOnes)
24194 DAG.getNode(ISD::OR, DL, CondVT, Cond, DAG.getBitcast(CondVT, RHS));
24195 else if (FValIsAllZeros)
24196 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
24197 DAG.getBitcast(CondVT, LHS));
24199 return DAG.getBitcast(VT, Ret);
24203 // We should generate an X86ISD::BLENDI from a vselect if its argument
24204 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
24205 // constants. This specific pattern gets generated when we split a
24206 // selector for a 512 bit vector in a machine without AVX512 (but with
24207 // 256-bit vectors), during legalization:
24209 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
24211 // Iff we find this pattern and the build_vectors are built from
24212 // constants, we translate the vselect into a shuffle_vector that we
24213 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
24214 if ((N->getOpcode() == ISD::VSELECT ||
24215 N->getOpcode() == X86ISD::SHRUNKBLEND) &&
24216 !DCI.isBeforeLegalize() && !VT.is512BitVector()) {
24217 SDValue Shuffle = transformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
24218 if (Shuffle.getNode())
24222 // If this is a *dynamic* select (non-constant condition) and we can match
24223 // this node with one of the variable blend instructions, restructure the
24224 // condition so that the blends can use the high bit of each element and use
24225 // SimplifyDemandedBits to simplify the condition operand.
24226 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
24227 !DCI.isBeforeLegalize() &&
24228 !ISD::isBuildVectorOfConstantSDNodes(Cond.getNode())) {
24229 unsigned BitWidth = Cond.getValueType().getScalarSizeInBits();
24231 // Don't optimize vector selects that map to mask-registers.
24235 // We can only handle the cases where VSELECT is directly legal on the
24236 // subtarget. We custom lower VSELECT nodes with constant conditions and
24237 // this makes it hard to see whether a dynamic VSELECT will correctly
24238 // lower, so we both check the operation's status and explicitly handle the
24239 // cases where a *dynamic* blend will fail even though a constant-condition
24240 // blend could be custom lowered.
24241 // FIXME: We should find a better way to handle this class of problems.
24242 // Potentially, we should combine constant-condition vselect nodes
24243 // pre-legalization into shuffles and not mark as many types as custom
24245 if (!TLI.isOperationLegalOrCustom(ISD::VSELECT, VT))
24247 // FIXME: We don't support i16-element blends currently. We could and
24248 // should support them by making *all* the bits in the condition be set
24249 // rather than just the high bit and using an i8-element blend.
24250 if (VT.getVectorElementType() == MVT::i16)
24252 // Dynamic blending was only available from SSE4.1 onward.
24253 if (VT.is128BitVector() && !Subtarget->hasSSE41())
24255 // Byte blends are only available in AVX2
24256 if (VT == MVT::v32i8 && !Subtarget->hasAVX2())
24259 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
24260 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
24262 APInt KnownZero, KnownOne;
24263 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
24264 DCI.isBeforeLegalizeOps());
24265 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
24266 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne,
24268 // If we changed the computation somewhere in the DAG, this change
24269 // will affect all users of Cond.
24270 // Make sure it is fine and update all the nodes so that we do not
24271 // use the generic VSELECT anymore. Otherwise, we may perform
24272 // wrong optimizations as we messed up with the actual expectation
24273 // for the vector boolean values.
24274 if (Cond != TLO.Old) {
24275 // Check all uses of that condition operand to check whether it will be
24276 // consumed by non-BLEND instructions, which may depend on all bits are
24278 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
24280 if (I->getOpcode() != ISD::VSELECT)
24281 // TODO: Add other opcodes eventually lowered into BLEND.
24284 // Update all the users of the condition, before committing the change,
24285 // so that the VSELECT optimizations that expect the correct vector
24286 // boolean value will not be triggered.
24287 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
24289 DAG.ReplaceAllUsesOfValueWith(
24291 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(*I), I->getValueType(0),
24292 Cond, I->getOperand(1), I->getOperand(2)));
24293 DCI.CommitTargetLoweringOpt(TLO);
24296 // At this point, only Cond is changed. Change the condition
24297 // just for N to keep the opportunity to optimize all other
24298 // users their own way.
24299 DAG.ReplaceAllUsesOfValueWith(
24301 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(N), N->getValueType(0),
24302 TLO.New, N->getOperand(1), N->getOperand(2)));
24310 // Check whether a boolean test is testing a boolean value generated by
24311 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
24314 // Simplify the following patterns:
24315 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
24316 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
24317 // to (Op EFLAGS Cond)
24319 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
24320 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
24321 // to (Op EFLAGS !Cond)
24323 // where Op could be BRCOND or CMOV.
24325 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
24326 // Quit if not CMP and SUB with its value result used.
24327 if (Cmp.getOpcode() != X86ISD::CMP &&
24328 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
24331 // Quit if not used as a boolean value.
24332 if (CC != X86::COND_E && CC != X86::COND_NE)
24335 // Check CMP operands. One of them should be 0 or 1 and the other should be
24336 // an SetCC or extended from it.
24337 SDValue Op1 = Cmp.getOperand(0);
24338 SDValue Op2 = Cmp.getOperand(1);
24341 const ConstantSDNode* C = nullptr;
24342 bool needOppositeCond = (CC == X86::COND_E);
24343 bool checkAgainstTrue = false; // Is it a comparison against 1?
24345 if ((C = dyn_cast<ConstantSDNode>(Op1)))
24347 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
24349 else // Quit if all operands are not constants.
24352 if (C->getZExtValue() == 1) {
24353 needOppositeCond = !needOppositeCond;
24354 checkAgainstTrue = true;
24355 } else if (C->getZExtValue() != 0)
24356 // Quit if the constant is neither 0 or 1.
24359 bool truncatedToBoolWithAnd = false;
24360 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
24361 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
24362 SetCC.getOpcode() == ISD::TRUNCATE ||
24363 SetCC.getOpcode() == ISD::AND) {
24364 if (SetCC.getOpcode() == ISD::AND) {
24366 if (isOneConstant(SetCC.getOperand(0)))
24368 if (isOneConstant(SetCC.getOperand(1)))
24372 SetCC = SetCC.getOperand(OpIdx);
24373 truncatedToBoolWithAnd = true;
24375 SetCC = SetCC.getOperand(0);
24378 switch (SetCC.getOpcode()) {
24379 case X86ISD::SETCC_CARRY:
24380 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
24381 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
24382 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
24383 // truncated to i1 using 'and'.
24384 if (checkAgainstTrue && !truncatedToBoolWithAnd)
24386 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
24387 "Invalid use of SETCC_CARRY!");
24389 case X86ISD::SETCC:
24390 // Set the condition code or opposite one if necessary.
24391 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
24392 if (needOppositeCond)
24393 CC = X86::GetOppositeBranchCondition(CC);
24394 return SetCC.getOperand(1);
24395 case X86ISD::CMOV: {
24396 // Check whether false/true value has canonical one, i.e. 0 or 1.
24397 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
24398 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
24399 // Quit if true value is not a constant.
24402 // Quit if false value is not a constant.
24404 SDValue Op = SetCC.getOperand(0);
24405 // Skip 'zext' or 'trunc' node.
24406 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
24407 Op.getOpcode() == ISD::TRUNCATE)
24408 Op = Op.getOperand(0);
24409 // A special case for rdrand/rdseed, where 0 is set if false cond is
24411 if ((Op.getOpcode() != X86ISD::RDRAND &&
24412 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
24415 // Quit if false value is not the constant 0 or 1.
24416 bool FValIsFalse = true;
24417 if (FVal && FVal->getZExtValue() != 0) {
24418 if (FVal->getZExtValue() != 1)
24420 // If FVal is 1, opposite cond is needed.
24421 needOppositeCond = !needOppositeCond;
24422 FValIsFalse = false;
24424 // Quit if TVal is not the constant opposite of FVal.
24425 if (FValIsFalse && TVal->getZExtValue() != 1)
24427 if (!FValIsFalse && TVal->getZExtValue() != 0)
24429 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
24430 if (needOppositeCond)
24431 CC = X86::GetOppositeBranchCondition(CC);
24432 return SetCC.getOperand(3);
24439 /// Check whether Cond is an AND/OR of SETCCs off of the same EFLAGS.
24441 /// (X86or (X86setcc) (X86setcc))
24442 /// (X86cmp (and (X86setcc) (X86setcc)), 0)
24443 static bool checkBoolTestAndOrSetCCCombine(SDValue Cond, X86::CondCode &CC0,
24444 X86::CondCode &CC1, SDValue &Flags,
24446 if (Cond->getOpcode() == X86ISD::CMP) {
24447 if (!isNullConstant(Cond->getOperand(1)))
24450 Cond = Cond->getOperand(0);
24455 SDValue SetCC0, SetCC1;
24456 switch (Cond->getOpcode()) {
24457 default: return false;
24464 SetCC0 = Cond->getOperand(0);
24465 SetCC1 = Cond->getOperand(1);
24469 // Make sure we have SETCC nodes, using the same flags value.
24470 if (SetCC0.getOpcode() != X86ISD::SETCC ||
24471 SetCC1.getOpcode() != X86ISD::SETCC ||
24472 SetCC0->getOperand(1) != SetCC1->getOperand(1))
24475 CC0 = (X86::CondCode)SetCC0->getConstantOperandVal(0);
24476 CC1 = (X86::CondCode)SetCC1->getConstantOperandVal(0);
24477 Flags = SetCC0->getOperand(1);
24481 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
24482 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
24483 TargetLowering::DAGCombinerInfo &DCI,
24484 const X86Subtarget *Subtarget) {
24487 // If the flag operand isn't dead, don't touch this CMOV.
24488 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
24491 SDValue FalseOp = N->getOperand(0);
24492 SDValue TrueOp = N->getOperand(1);
24493 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
24494 SDValue Cond = N->getOperand(3);
24496 if (CC == X86::COND_E || CC == X86::COND_NE) {
24497 switch (Cond.getOpcode()) {
24501 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
24502 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
24503 return (CC == X86::COND_E) ? FalseOp : TrueOp;
24509 Flags = checkBoolTestSetCCCombine(Cond, CC);
24510 if (Flags.getNode() &&
24511 // Extra check as FCMOV only supports a subset of X86 cond.
24512 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
24513 SDValue Ops[] = { FalseOp, TrueOp,
24514 DAG.getConstant(CC, DL, MVT::i8), Flags };
24515 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
24518 // If this is a select between two integer constants, try to do some
24519 // optimizations. Note that the operands are ordered the opposite of SELECT
24521 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
24522 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
24523 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
24524 // larger than FalseC (the false value).
24525 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
24526 CC = X86::GetOppositeBranchCondition(CC);
24527 std::swap(TrueC, FalseC);
24528 std::swap(TrueOp, FalseOp);
24531 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
24532 // This is efficient for any integer data type (including i8/i16) and
24534 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
24535 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
24536 DAG.getConstant(CC, DL, MVT::i8), Cond);
24538 // Zero extend the condition if needed.
24539 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
24541 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
24542 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
24543 DAG.getConstant(ShAmt, DL, MVT::i8));
24544 if (N->getNumValues() == 2) // Dead flag value?
24545 return DCI.CombineTo(N, Cond, SDValue());
24549 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
24550 // for any integer data type, including i8/i16.
24551 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
24552 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
24553 DAG.getConstant(CC, DL, MVT::i8), Cond);
24555 // Zero extend the condition if needed.
24556 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
24557 FalseC->getValueType(0), Cond);
24558 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
24559 SDValue(FalseC, 0));
24561 if (N->getNumValues() == 2) // Dead flag value?
24562 return DCI.CombineTo(N, Cond, SDValue());
24566 // Optimize cases that will turn into an LEA instruction. This requires
24567 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
24568 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
24569 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
24570 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
24572 bool isFastMultiplier = false;
24574 switch ((unsigned char)Diff) {
24576 case 1: // result = add base, cond
24577 case 2: // result = lea base( , cond*2)
24578 case 3: // result = lea base(cond, cond*2)
24579 case 4: // result = lea base( , cond*4)
24580 case 5: // result = lea base(cond, cond*4)
24581 case 8: // result = lea base( , cond*8)
24582 case 9: // result = lea base(cond, cond*8)
24583 isFastMultiplier = true;
24588 if (isFastMultiplier) {
24589 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
24590 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
24591 DAG.getConstant(CC, DL, MVT::i8), Cond);
24592 // Zero extend the condition if needed.
24593 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
24595 // Scale the condition by the difference.
24597 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
24598 DAG.getConstant(Diff, DL, Cond.getValueType()));
24600 // Add the base if non-zero.
24601 if (FalseC->getAPIntValue() != 0)
24602 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
24603 SDValue(FalseC, 0));
24604 if (N->getNumValues() == 2) // Dead flag value?
24605 return DCI.CombineTo(N, Cond, SDValue());
24612 // Handle these cases:
24613 // (select (x != c), e, c) -> select (x != c), e, x),
24614 // (select (x == c), c, e) -> select (x == c), x, e)
24615 // where the c is an integer constant, and the "select" is the combination
24616 // of CMOV and CMP.
24618 // The rationale for this change is that the conditional-move from a constant
24619 // needs two instructions, however, conditional-move from a register needs
24620 // only one instruction.
24622 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
24623 // some instruction-combining opportunities. This opt needs to be
24624 // postponed as late as possible.
24626 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
24627 // the DCI.xxxx conditions are provided to postpone the optimization as
24628 // late as possible.
24630 ConstantSDNode *CmpAgainst = nullptr;
24631 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
24632 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
24633 !isa<ConstantSDNode>(Cond.getOperand(0))) {
24635 if (CC == X86::COND_NE &&
24636 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
24637 CC = X86::GetOppositeBranchCondition(CC);
24638 std::swap(TrueOp, FalseOp);
24641 if (CC == X86::COND_E &&
24642 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
24643 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
24644 DAG.getConstant(CC, DL, MVT::i8), Cond };
24645 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
24650 // Fold and/or of setcc's to double CMOV:
24651 // (CMOV F, T, ((cc1 | cc2) != 0)) -> (CMOV (CMOV F, T, cc1), T, cc2)
24652 // (CMOV F, T, ((cc1 & cc2) != 0)) -> (CMOV (CMOV T, F, !cc1), F, !cc2)
24654 // This combine lets us generate:
24655 // cmovcc1 (jcc1 if we don't have CMOV)
24661 // cmovne (jne if we don't have CMOV)
24662 // When we can't use the CMOV instruction, it might increase branch
24664 // When we can use CMOV, or when there is no mispredict, this improves
24665 // throughput and reduces register pressure.
24667 if (CC == X86::COND_NE) {
24669 X86::CondCode CC0, CC1;
24671 if (checkBoolTestAndOrSetCCCombine(Cond, CC0, CC1, Flags, isAndSetCC)) {
24673 std::swap(FalseOp, TrueOp);
24674 CC0 = X86::GetOppositeBranchCondition(CC0);
24675 CC1 = X86::GetOppositeBranchCondition(CC1);
24678 SDValue LOps[] = {FalseOp, TrueOp, DAG.getConstant(CC0, DL, MVT::i8),
24680 SDValue LCMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), LOps);
24681 SDValue Ops[] = {LCMOV, TrueOp, DAG.getConstant(CC1, DL, MVT::i8), Flags};
24682 SDValue CMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
24683 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SDValue(CMOV.getNode(), 1));
24691 /// PerformMulCombine - Optimize a single multiply with constant into two
24692 /// in order to implement it with two cheaper instructions, e.g.
24693 /// LEA + SHL, LEA + LEA.
24694 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
24695 TargetLowering::DAGCombinerInfo &DCI) {
24696 // An imul is usually smaller than the alternative sequence.
24697 if (DAG.getMachineFunction().getFunction()->optForMinSize())
24700 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
24703 EVT VT = N->getValueType(0);
24704 if (VT != MVT::i64 && VT != MVT::i32)
24707 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
24710 uint64_t MulAmt = C->getZExtValue();
24711 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
24714 uint64_t MulAmt1 = 0;
24715 uint64_t MulAmt2 = 0;
24716 if ((MulAmt % 9) == 0) {
24718 MulAmt2 = MulAmt / 9;
24719 } else if ((MulAmt % 5) == 0) {
24721 MulAmt2 = MulAmt / 5;
24722 } else if ((MulAmt % 3) == 0) {
24724 MulAmt2 = MulAmt / 3;
24727 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
24730 if (isPowerOf2_64(MulAmt2) &&
24731 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
24732 // If second multiplifer is pow2, issue it first. We want the multiply by
24733 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
24735 std::swap(MulAmt1, MulAmt2);
24738 if (isPowerOf2_64(MulAmt1))
24739 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
24740 DAG.getConstant(Log2_64(MulAmt1), DL, MVT::i8));
24742 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
24743 DAG.getConstant(MulAmt1, DL, VT));
24745 if (isPowerOf2_64(MulAmt2))
24746 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
24747 DAG.getConstant(Log2_64(MulAmt2), DL, MVT::i8));
24749 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
24750 DAG.getConstant(MulAmt2, DL, VT));
24752 // Do not add new nodes to DAG combiner worklist.
24753 DCI.CombineTo(N, NewMul, false);
24758 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
24759 SDValue N0 = N->getOperand(0);
24760 SDValue N1 = N->getOperand(1);
24761 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
24762 EVT VT = N0.getValueType();
24764 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
24765 // since the result of setcc_c is all zero's or all ones.
24766 if (VT.isInteger() && !VT.isVector() &&
24767 N1C && N0.getOpcode() == ISD::AND &&
24768 N0.getOperand(1).getOpcode() == ISD::Constant) {
24769 SDValue N00 = N0.getOperand(0);
24770 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
24771 APInt ShAmt = N1C->getAPIntValue();
24772 Mask = Mask.shl(ShAmt);
24773 bool MaskOK = false;
24774 // We can handle cases concerning bit-widening nodes containing setcc_c if
24775 // we carefully interrogate the mask to make sure we are semantics
24777 // The transform is not safe if the result of C1 << C2 exceeds the bitwidth
24778 // of the underlying setcc_c operation if the setcc_c was zero extended.
24779 // Consider the following example:
24780 // zext(setcc_c) -> i32 0x0000FFFF
24781 // c1 -> i32 0x0000FFFF
24782 // c2 -> i32 0x00000001
24783 // (shl (and (setcc_c), c1), c2) -> i32 0x0001FFFE
24784 // (and setcc_c, (c1 << c2)) -> i32 0x0000FFFE
24785 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
24787 } else if (N00.getOpcode() == ISD::SIGN_EXTEND &&
24788 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
24790 } else if ((N00.getOpcode() == ISD::ZERO_EXTEND ||
24791 N00.getOpcode() == ISD::ANY_EXTEND) &&
24792 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
24793 MaskOK = Mask.isIntN(N00.getOperand(0).getValueSizeInBits());
24795 if (MaskOK && Mask != 0) {
24797 return DAG.getNode(ISD::AND, DL, VT, N00, DAG.getConstant(Mask, DL, VT));
24801 // Hardware support for vector shifts is sparse which makes us scalarize the
24802 // vector operations in many cases. Also, on sandybridge ADD is faster than
24804 // (shl V, 1) -> add V,V
24805 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
24806 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
24807 assert(N0.getValueType().isVector() && "Invalid vector shift type");
24808 // We shift all of the values by one. In many cases we do not have
24809 // hardware support for this operation. This is better expressed as an ADD
24811 if (N1SplatC->getAPIntValue() == 1)
24812 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
24818 /// \brief Returns a vector of 0s if the node in input is a vector logical
24819 /// shift by a constant amount which is known to be bigger than or equal
24820 /// to the vector element size in bits.
24821 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
24822 const X86Subtarget *Subtarget) {
24823 EVT VT = N->getValueType(0);
24825 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
24826 (!Subtarget->hasInt256() ||
24827 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
24830 SDValue Amt = N->getOperand(1);
24832 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
24833 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
24834 APInt ShiftAmt = AmtSplat->getAPIntValue();
24835 unsigned MaxAmount =
24836 VT.getSimpleVT().getVectorElementType().getSizeInBits();
24838 // SSE2/AVX2 logical shifts always return a vector of 0s
24839 // if the shift amount is bigger than or equal to
24840 // the element size. The constant shift amount will be
24841 // encoded as a 8-bit immediate.
24842 if (ShiftAmt.trunc(8).uge(MaxAmount))
24843 return getZeroVector(VT.getSimpleVT(), Subtarget, DAG, DL);
24849 /// PerformShiftCombine - Combine shifts.
24850 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
24851 TargetLowering::DAGCombinerInfo &DCI,
24852 const X86Subtarget *Subtarget) {
24853 if (N->getOpcode() == ISD::SHL)
24854 if (SDValue V = PerformSHLCombine(N, DAG))
24857 // Try to fold this logical shift into a zero vector.
24858 if (N->getOpcode() != ISD::SRA)
24859 if (SDValue V = performShiftToAllZeros(N, DAG, Subtarget))
24865 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
24866 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
24867 // and friends. Likewise for OR -> CMPNEQSS.
24868 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
24869 TargetLowering::DAGCombinerInfo &DCI,
24870 const X86Subtarget *Subtarget) {
24873 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
24874 // we're requiring SSE2 for both.
24875 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
24876 SDValue N0 = N->getOperand(0);
24877 SDValue N1 = N->getOperand(1);
24878 SDValue CMP0 = N0->getOperand(1);
24879 SDValue CMP1 = N1->getOperand(1);
24882 // The SETCCs should both refer to the same CMP.
24883 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
24886 SDValue CMP00 = CMP0->getOperand(0);
24887 SDValue CMP01 = CMP0->getOperand(1);
24888 EVT VT = CMP00.getValueType();
24890 if (VT == MVT::f32 || VT == MVT::f64) {
24891 bool ExpectingFlags = false;
24892 // Check for any users that want flags:
24893 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
24894 !ExpectingFlags && UI != UE; ++UI)
24895 switch (UI->getOpcode()) {
24900 ExpectingFlags = true;
24902 case ISD::CopyToReg:
24903 case ISD::SIGN_EXTEND:
24904 case ISD::ZERO_EXTEND:
24905 case ISD::ANY_EXTEND:
24909 if (!ExpectingFlags) {
24910 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
24911 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
24913 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
24914 X86::CondCode tmp = cc0;
24919 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
24920 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
24921 // FIXME: need symbolic constants for these magic numbers.
24922 // See X86ATTInstPrinter.cpp:printSSECC().
24923 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
24924 if (Subtarget->hasAVX512()) {
24925 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
24927 DAG.getConstant(x86cc, DL, MVT::i8));
24928 if (N->getValueType(0) != MVT::i1)
24929 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
24933 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
24934 CMP00.getValueType(), CMP00, CMP01,
24935 DAG.getConstant(x86cc, DL,
24938 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
24939 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
24941 if (is64BitFP && !Subtarget->is64Bit()) {
24942 // On a 32-bit target, we cannot bitcast the 64-bit float to a
24943 // 64-bit integer, since that's not a legal type. Since
24944 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
24945 // bits, but can do this little dance to extract the lowest 32 bits
24946 // and work with those going forward.
24947 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
24949 SDValue Vector32 = DAG.getBitcast(MVT::v4f32, Vector64);
24950 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
24951 Vector32, DAG.getIntPtrConstant(0, DL));
24955 SDValue OnesOrZeroesI = DAG.getBitcast(IntVT, OnesOrZeroesF);
24956 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
24957 DAG.getConstant(1, DL, IntVT));
24958 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8,
24960 return OneBitOfTruth;
24968 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
24969 /// so it can be folded inside ANDNP.
24970 static bool CanFoldXORWithAllOnes(const SDNode *N) {
24971 EVT VT = N->getValueType(0);
24973 // Match direct AllOnes for 128 and 256-bit vectors
24974 if (ISD::isBuildVectorAllOnes(N))
24977 // Look through a bit convert.
24978 if (N->getOpcode() == ISD::BITCAST)
24979 N = N->getOperand(0).getNode();
24981 // Sometimes the operand may come from a insert_subvector building a 256-bit
24983 if (VT.is256BitVector() &&
24984 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
24985 SDValue V1 = N->getOperand(0);
24986 SDValue V2 = N->getOperand(1);
24988 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
24989 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
24990 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
24991 ISD::isBuildVectorAllOnes(V2.getNode()))
24998 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
24999 // register. In most cases we actually compare or select YMM-sized registers
25000 // and mixing the two types creates horrible code. This method optimizes
25001 // some of the transition sequences.
25002 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
25003 TargetLowering::DAGCombinerInfo &DCI,
25004 const X86Subtarget *Subtarget) {
25005 EVT VT = N->getValueType(0);
25006 if (!VT.is256BitVector())
25009 assert((N->getOpcode() == ISD::ANY_EXTEND ||
25010 N->getOpcode() == ISD::ZERO_EXTEND ||
25011 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
25013 SDValue Narrow = N->getOperand(0);
25014 EVT NarrowVT = Narrow->getValueType(0);
25015 if (!NarrowVT.is128BitVector())
25018 if (Narrow->getOpcode() != ISD::XOR &&
25019 Narrow->getOpcode() != ISD::AND &&
25020 Narrow->getOpcode() != ISD::OR)
25023 SDValue N0 = Narrow->getOperand(0);
25024 SDValue N1 = Narrow->getOperand(1);
25027 // The Left side has to be a trunc.
25028 if (N0.getOpcode() != ISD::TRUNCATE)
25031 // The type of the truncated inputs.
25032 EVT WideVT = N0->getOperand(0)->getValueType(0);
25036 // The right side has to be a 'trunc' or a constant vector.
25037 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
25038 ConstantSDNode *RHSConstSplat = nullptr;
25039 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
25040 RHSConstSplat = RHSBV->getConstantSplatNode();
25041 if (!RHSTrunc && !RHSConstSplat)
25044 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25046 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
25049 // Set N0 and N1 to hold the inputs to the new wide operation.
25050 N0 = N0->getOperand(0);
25051 if (RHSConstSplat) {
25052 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getVectorElementType(),
25053 SDValue(RHSConstSplat, 0));
25054 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
25055 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
25056 } else if (RHSTrunc) {
25057 N1 = N1->getOperand(0);
25060 // Generate the wide operation.
25061 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
25062 unsigned Opcode = N->getOpcode();
25064 case ISD::ANY_EXTEND:
25066 case ISD::ZERO_EXTEND: {
25067 unsigned InBits = NarrowVT.getScalarSizeInBits();
25068 APInt Mask = APInt::getAllOnesValue(InBits);
25069 Mask = Mask.zext(VT.getScalarSizeInBits());
25070 return DAG.getNode(ISD::AND, DL, VT,
25071 Op, DAG.getConstant(Mask, DL, VT));
25073 case ISD::SIGN_EXTEND:
25074 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
25075 Op, DAG.getValueType(NarrowVT));
25077 llvm_unreachable("Unexpected opcode");
25081 static SDValue VectorZextCombine(SDNode *N, SelectionDAG &DAG,
25082 TargetLowering::DAGCombinerInfo &DCI,
25083 const X86Subtarget *Subtarget) {
25084 SDValue N0 = N->getOperand(0);
25085 SDValue N1 = N->getOperand(1);
25088 // A vector zext_in_reg may be represented as a shuffle,
25089 // feeding into a bitcast (this represents anyext) feeding into
25090 // an and with a mask.
25091 // We'd like to try to combine that into a shuffle with zero
25092 // plus a bitcast, removing the and.
25093 if (N0.getOpcode() != ISD::BITCAST ||
25094 N0.getOperand(0).getOpcode() != ISD::VECTOR_SHUFFLE)
25097 // The other side of the AND should be a splat of 2^C, where C
25098 // is the number of bits in the source type.
25099 if (N1.getOpcode() == ISD::BITCAST)
25100 N1 = N1.getOperand(0);
25101 if (N1.getOpcode() != ISD::BUILD_VECTOR)
25103 BuildVectorSDNode *Vector = cast<BuildVectorSDNode>(N1);
25105 ShuffleVectorSDNode *Shuffle = cast<ShuffleVectorSDNode>(N0.getOperand(0));
25106 EVT SrcType = Shuffle->getValueType(0);
25108 // We expect a single-source shuffle
25109 if (Shuffle->getOperand(1)->getOpcode() != ISD::UNDEF)
25112 unsigned SrcSize = SrcType.getScalarSizeInBits();
25114 APInt SplatValue, SplatUndef;
25115 unsigned SplatBitSize;
25117 if (!Vector->isConstantSplat(SplatValue, SplatUndef,
25118 SplatBitSize, HasAnyUndefs))
25121 unsigned ResSize = N1.getValueType().getScalarSizeInBits();
25122 // Make sure the splat matches the mask we expect
25123 if (SplatBitSize > ResSize ||
25124 (SplatValue + 1).exactLogBase2() != (int)SrcSize)
25127 // Make sure the input and output size make sense
25128 if (SrcSize >= ResSize || ResSize % SrcSize)
25131 // We expect a shuffle of the form <0, u, u, u, 1, u, u, u...>
25132 // The number of u's between each two values depends on the ratio between
25133 // the source and dest type.
25134 unsigned ZextRatio = ResSize / SrcSize;
25135 bool IsZext = true;
25136 for (unsigned i = 0; i < SrcType.getVectorNumElements(); ++i) {
25137 if (i % ZextRatio) {
25138 if (Shuffle->getMaskElt(i) > 0) {
25144 if (Shuffle->getMaskElt(i) != (int)(i / ZextRatio)) {
25145 // Expected element number
25155 // Ok, perform the transformation - replace the shuffle with
25156 // a shuffle of the form <0, k, k, k, 1, k, k, k> with zero
25157 // (instead of undef) where the k elements come from the zero vector.
25158 SmallVector<int, 8> Mask;
25159 unsigned NumElems = SrcType.getVectorNumElements();
25160 for (unsigned i = 0; i < NumElems; ++i)
25162 Mask.push_back(NumElems);
25164 Mask.push_back(i / ZextRatio);
25166 SDValue NewShuffle = DAG.getVectorShuffle(Shuffle->getValueType(0), DL,
25167 Shuffle->getOperand(0), DAG.getConstant(0, DL, SrcType), Mask);
25168 return DAG.getBitcast(N0.getValueType(), NewShuffle);
25171 /// If both input operands of a logic op are being cast from floating point
25172 /// types, try to convert this into a floating point logic node to avoid
25173 /// unnecessary moves from SSE to integer registers.
25174 static SDValue convertIntLogicToFPLogic(SDNode *N, SelectionDAG &DAG,
25175 const X86Subtarget *Subtarget) {
25176 unsigned FPOpcode = ISD::DELETED_NODE;
25177 if (N->getOpcode() == ISD::AND)
25178 FPOpcode = X86ISD::FAND;
25179 else if (N->getOpcode() == ISD::OR)
25180 FPOpcode = X86ISD::FOR;
25181 else if (N->getOpcode() == ISD::XOR)
25182 FPOpcode = X86ISD::FXOR;
25184 assert(FPOpcode != ISD::DELETED_NODE &&
25185 "Unexpected input node for FP logic conversion");
25187 EVT VT = N->getValueType(0);
25188 SDValue N0 = N->getOperand(0);
25189 SDValue N1 = N->getOperand(1);
25191 if (N0.getOpcode() == ISD::BITCAST && N1.getOpcode() == ISD::BITCAST &&
25192 ((Subtarget->hasSSE1() && VT == MVT::i32) ||
25193 (Subtarget->hasSSE2() && VT == MVT::i64))) {
25194 SDValue N00 = N0.getOperand(0);
25195 SDValue N10 = N1.getOperand(0);
25196 EVT N00Type = N00.getValueType();
25197 EVT N10Type = N10.getValueType();
25198 if (N00Type.isFloatingPoint() && N10Type.isFloatingPoint()) {
25199 SDValue FPLogic = DAG.getNode(FPOpcode, DL, N00Type, N00, N10);
25200 return DAG.getBitcast(VT, FPLogic);
25206 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
25207 TargetLowering::DAGCombinerInfo &DCI,
25208 const X86Subtarget *Subtarget) {
25209 if (DCI.isBeforeLegalizeOps())
25212 if (SDValue Zext = VectorZextCombine(N, DAG, DCI, Subtarget))
25215 if (SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget))
25218 if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, Subtarget))
25221 EVT VT = N->getValueType(0);
25222 SDValue N0 = N->getOperand(0);
25223 SDValue N1 = N->getOperand(1);
25226 // Create BEXTR instructions
25227 // BEXTR is ((X >> imm) & (2**size-1))
25228 if (VT == MVT::i32 || VT == MVT::i64) {
25229 // Check for BEXTR.
25230 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
25231 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
25232 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
25233 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
25234 if (MaskNode && ShiftNode) {
25235 uint64_t Mask = MaskNode->getZExtValue();
25236 uint64_t Shift = ShiftNode->getZExtValue();
25237 if (isMask_64(Mask)) {
25238 uint64_t MaskSize = countPopulation(Mask);
25239 if (Shift + MaskSize <= VT.getSizeInBits())
25240 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
25241 DAG.getConstant(Shift | (MaskSize << 8), DL,
25250 // Want to form ANDNP nodes:
25251 // 1) In the hopes of then easily combining them with OR and AND nodes
25252 // to form PBLEND/PSIGN.
25253 // 2) To match ANDN packed intrinsics
25254 if (VT != MVT::v2i64 && VT != MVT::v4i64)
25257 // Check LHS for vnot
25258 if (N0.getOpcode() == ISD::XOR &&
25259 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
25260 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
25261 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
25263 // Check RHS for vnot
25264 if (N1.getOpcode() == ISD::XOR &&
25265 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
25266 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
25267 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
25272 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
25273 TargetLowering::DAGCombinerInfo &DCI,
25274 const X86Subtarget *Subtarget) {
25275 if (DCI.isBeforeLegalizeOps())
25278 if (SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget))
25281 if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, Subtarget))
25284 SDValue N0 = N->getOperand(0);
25285 SDValue N1 = N->getOperand(1);
25286 EVT VT = N->getValueType(0);
25288 // look for psign/blend
25289 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
25290 if (!Subtarget->hasSSSE3() ||
25291 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
25294 // Canonicalize pandn to RHS
25295 if (N0.getOpcode() == X86ISD::ANDNP)
25297 // or (and (m, y), (pandn m, x))
25298 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
25299 SDValue Mask = N1.getOperand(0);
25300 SDValue X = N1.getOperand(1);
25302 if (N0.getOperand(0) == Mask)
25303 Y = N0.getOperand(1);
25304 if (N0.getOperand(1) == Mask)
25305 Y = N0.getOperand(0);
25307 // Check to see if the mask appeared in both the AND and ANDNP and
25311 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
25312 // Look through mask bitcast.
25313 if (Mask.getOpcode() == ISD::BITCAST)
25314 Mask = Mask.getOperand(0);
25315 if (X.getOpcode() == ISD::BITCAST)
25316 X = X.getOperand(0);
25317 if (Y.getOpcode() == ISD::BITCAST)
25318 Y = Y.getOperand(0);
25320 EVT MaskVT = Mask.getValueType();
25322 // Validate that the Mask operand is a vector sra node.
25323 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
25324 // there is no psrai.b
25325 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
25326 unsigned SraAmt = ~0;
25327 if (Mask.getOpcode() == ISD::SRA) {
25328 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
25329 if (auto *AmtConst = AmtBV->getConstantSplatNode())
25330 SraAmt = AmtConst->getZExtValue();
25331 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
25332 SDValue SraC = Mask.getOperand(1);
25333 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
25335 if ((SraAmt + 1) != EltBits)
25340 // Now we know we at least have a plendvb with the mask val. See if
25341 // we can form a psignb/w/d.
25342 // psign = x.type == y.type == mask.type && y = sub(0, x);
25343 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
25344 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
25345 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
25346 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
25347 "Unsupported VT for PSIGN");
25348 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
25349 return DAG.getBitcast(VT, Mask);
25351 // PBLENDVB only available on SSE 4.1
25352 if (!Subtarget->hasSSE41())
25355 MVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
25357 X = DAG.getBitcast(BlendVT, X);
25358 Y = DAG.getBitcast(BlendVT, Y);
25359 Mask = DAG.getBitcast(BlendVT, Mask);
25360 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
25361 return DAG.getBitcast(VT, Mask);
25365 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
25368 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
25369 bool OptForSize = DAG.getMachineFunction().getFunction()->optForSize();
25371 // SHLD/SHRD instructions have lower register pressure, but on some
25372 // platforms they have higher latency than the equivalent
25373 // series of shifts/or that would otherwise be generated.
25374 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
25375 // have higher latencies and we are not optimizing for size.
25376 if (!OptForSize && Subtarget->isSHLDSlow())
25379 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
25381 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
25383 if (!N0.hasOneUse() || !N1.hasOneUse())
25386 SDValue ShAmt0 = N0.getOperand(1);
25387 if (ShAmt0.getValueType() != MVT::i8)
25389 SDValue ShAmt1 = N1.getOperand(1);
25390 if (ShAmt1.getValueType() != MVT::i8)
25392 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
25393 ShAmt0 = ShAmt0.getOperand(0);
25394 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
25395 ShAmt1 = ShAmt1.getOperand(0);
25398 unsigned Opc = X86ISD::SHLD;
25399 SDValue Op0 = N0.getOperand(0);
25400 SDValue Op1 = N1.getOperand(0);
25401 if (ShAmt0.getOpcode() == ISD::SUB) {
25402 Opc = X86ISD::SHRD;
25403 std::swap(Op0, Op1);
25404 std::swap(ShAmt0, ShAmt1);
25407 unsigned Bits = VT.getSizeInBits();
25408 if (ShAmt1.getOpcode() == ISD::SUB) {
25409 SDValue Sum = ShAmt1.getOperand(0);
25410 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
25411 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
25412 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
25413 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
25414 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
25415 return DAG.getNode(Opc, DL, VT,
25417 DAG.getNode(ISD::TRUNCATE, DL,
25420 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
25421 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
25423 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
25424 return DAG.getNode(Opc, DL, VT,
25425 N0.getOperand(0), N1.getOperand(0),
25426 DAG.getNode(ISD::TRUNCATE, DL,
25433 // Generate NEG and CMOV for integer abs.
25434 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
25435 EVT VT = N->getValueType(0);
25437 // Since X86 does not have CMOV for 8-bit integer, we don't convert
25438 // 8-bit integer abs to NEG and CMOV.
25439 if (VT.isInteger() && VT.getSizeInBits() == 8)
25442 SDValue N0 = N->getOperand(0);
25443 SDValue N1 = N->getOperand(1);
25446 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
25447 // and change it to SUB and CMOV.
25448 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
25449 N0.getOpcode() == ISD::ADD &&
25450 N0.getOperand(1) == N1 &&
25451 N1.getOpcode() == ISD::SRA &&
25452 N1.getOperand(0) == N0.getOperand(0))
25453 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
25454 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
25455 // Generate SUB & CMOV.
25456 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
25457 DAG.getConstant(0, DL, VT), N0.getOperand(0));
25459 SDValue Ops[] = { N0.getOperand(0), Neg,
25460 DAG.getConstant(X86::COND_GE, DL, MVT::i8),
25461 SDValue(Neg.getNode(), 1) };
25462 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
25467 // Try to turn tests against the signbit in the form of:
25468 // XOR(TRUNCATE(SRL(X, size(X)-1)), 1)
25471 static SDValue foldXorTruncShiftIntoCmp(SDNode *N, SelectionDAG &DAG) {
25472 // This is only worth doing if the output type is i8.
25473 if (N->getValueType(0) != MVT::i8)
25476 SDValue N0 = N->getOperand(0);
25477 SDValue N1 = N->getOperand(1);
25479 // We should be performing an xor against a truncated shift.
25480 if (N0.getOpcode() != ISD::TRUNCATE || !N0.hasOneUse())
25483 // Make sure we are performing an xor against one.
25484 if (!isOneConstant(N1))
25487 // SetCC on x86 zero extends so only act on this if it's a logical shift.
25488 SDValue Shift = N0.getOperand(0);
25489 if (Shift.getOpcode() != ISD::SRL || !Shift.hasOneUse())
25492 // Make sure we are truncating from one of i16, i32 or i64.
25493 EVT ShiftTy = Shift.getValueType();
25494 if (ShiftTy != MVT::i16 && ShiftTy != MVT::i32 && ShiftTy != MVT::i64)
25497 // Make sure the shift amount extracts the sign bit.
25498 if (!isa<ConstantSDNode>(Shift.getOperand(1)) ||
25499 Shift.getConstantOperandVal(1) != ShiftTy.getSizeInBits() - 1)
25502 // Create a greater-than comparison against -1.
25503 // N.B. Using SETGE against 0 works but we want a canonical looking
25504 // comparison, using SETGT matches up with what TranslateX86CC.
25506 SDValue ShiftOp = Shift.getOperand(0);
25507 EVT ShiftOpTy = ShiftOp.getValueType();
25508 SDValue Cond = DAG.getSetCC(DL, MVT::i8, ShiftOp,
25509 DAG.getConstant(-1, DL, ShiftOpTy), ISD::SETGT);
25513 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
25514 TargetLowering::DAGCombinerInfo &DCI,
25515 const X86Subtarget *Subtarget) {
25516 if (DCI.isBeforeLegalizeOps())
25519 if (SDValue RV = foldXorTruncShiftIntoCmp(N, DAG))
25522 if (Subtarget->hasCMov())
25523 if (SDValue RV = performIntegerAbsCombine(N, DAG))
25526 if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, Subtarget))
25532 /// This function detects the AVG pattern between vectors of unsigned i8/i16,
25533 /// which is c = (a + b + 1) / 2, and replace this operation with the efficient
25534 /// X86ISD::AVG instruction.
25535 static SDValue detectAVGPattern(SDValue In, EVT VT, SelectionDAG &DAG,
25536 const X86Subtarget *Subtarget, SDLoc DL) {
25537 if (!VT.isVector() || !VT.isSimple())
25539 EVT InVT = In.getValueType();
25540 unsigned NumElems = VT.getVectorNumElements();
25542 EVT ScalarVT = VT.getVectorElementType();
25543 if (!((ScalarVT == MVT::i8 || ScalarVT == MVT::i16) &&
25544 isPowerOf2_32(NumElems)))
25547 // InScalarVT is the intermediate type in AVG pattern and it should be greater
25548 // than the original input type (i8/i16).
25549 EVT InScalarVT = InVT.getVectorElementType();
25550 if (InScalarVT.getSizeInBits() <= ScalarVT.getSizeInBits())
25553 if (Subtarget->hasAVX512()) {
25554 if (VT.getSizeInBits() > 512)
25556 } else if (Subtarget->hasAVX2()) {
25557 if (VT.getSizeInBits() > 256)
25560 if (VT.getSizeInBits() > 128)
25564 // Detect the following pattern:
25566 // %1 = zext <N x i8> %a to <N x i32>
25567 // %2 = zext <N x i8> %b to <N x i32>
25568 // %3 = add nuw nsw <N x i32> %1, <i32 1 x N>
25569 // %4 = add nuw nsw <N x i32> %3, %2
25570 // %5 = lshr <N x i32> %N, <i32 1 x N>
25571 // %6 = trunc <N x i32> %5 to <N x i8>
25573 // In AVX512, the last instruction can also be a trunc store.
25575 if (In.getOpcode() != ISD::SRL)
25578 // A lambda checking the given SDValue is a constant vector and each element
25579 // is in the range [Min, Max].
25580 auto IsConstVectorInRange = [](SDValue V, unsigned Min, unsigned Max) {
25581 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(V);
25582 if (!BV || !BV->isConstant())
25584 for (unsigned i = 0, e = V.getNumOperands(); i < e; i++) {
25585 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V.getOperand(i));
25588 uint64_t Val = C->getZExtValue();
25589 if (Val < Min || Val > Max)
25595 // Check if each element of the vector is left-shifted by one.
25596 auto LHS = In.getOperand(0);
25597 auto RHS = In.getOperand(1);
25598 if (!IsConstVectorInRange(RHS, 1, 1))
25600 if (LHS.getOpcode() != ISD::ADD)
25603 // Detect a pattern of a + b + 1 where the order doesn't matter.
25604 SDValue Operands[3];
25605 Operands[0] = LHS.getOperand(0);
25606 Operands[1] = LHS.getOperand(1);
25608 // Take care of the case when one of the operands is a constant vector whose
25609 // element is in the range [1, 256].
25610 if (IsConstVectorInRange(Operands[1], 1, ScalarVT == MVT::i8 ? 256 : 65536) &&
25611 Operands[0].getOpcode() == ISD::ZERO_EXTEND &&
25612 Operands[0].getOperand(0).getValueType() == VT) {
25613 // The pattern is detected. Subtract one from the constant vector, then
25614 // demote it and emit X86ISD::AVG instruction.
25615 SDValue One = DAG.getConstant(1, DL, InScalarVT);
25616 SDValue Ones = DAG.getNode(ISD::BUILD_VECTOR, DL, InVT,
25617 SmallVector<SDValue, 8>(NumElems, One));
25618 Operands[1] = DAG.getNode(ISD::SUB, DL, InVT, Operands[1], Ones);
25619 Operands[1] = DAG.getNode(ISD::TRUNCATE, DL, VT, Operands[1]);
25620 return DAG.getNode(X86ISD::AVG, DL, VT, Operands[0].getOperand(0),
25624 if (Operands[0].getOpcode() == ISD::ADD)
25625 std::swap(Operands[0], Operands[1]);
25626 else if (Operands[1].getOpcode() != ISD::ADD)
25628 Operands[2] = Operands[1].getOperand(0);
25629 Operands[1] = Operands[1].getOperand(1);
25631 // Now we have three operands of two additions. Check that one of them is a
25632 // constant vector with ones, and the other two are promoted from i8/i16.
25633 for (int i = 0; i < 3; ++i) {
25634 if (!IsConstVectorInRange(Operands[i], 1, 1))
25636 std::swap(Operands[i], Operands[2]);
25638 // Check if Operands[0] and Operands[1] are results of type promotion.
25639 for (int j = 0; j < 2; ++j)
25640 if (Operands[j].getOpcode() != ISD::ZERO_EXTEND ||
25641 Operands[j].getOperand(0).getValueType() != VT)
25644 // The pattern is detected, emit X86ISD::AVG instruction.
25645 return DAG.getNode(X86ISD::AVG, DL, VT, Operands[0].getOperand(0),
25646 Operands[1].getOperand(0));
25652 static SDValue PerformTRUNCATECombine(SDNode *N, SelectionDAG &DAG,
25653 const X86Subtarget *Subtarget) {
25654 return detectAVGPattern(N->getOperand(0), N->getValueType(0), DAG, Subtarget,
25658 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
25659 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
25660 TargetLowering::DAGCombinerInfo &DCI,
25661 const X86Subtarget *Subtarget) {
25662 LoadSDNode *Ld = cast<LoadSDNode>(N);
25663 EVT RegVT = Ld->getValueType(0);
25664 EVT MemVT = Ld->getMemoryVT();
25666 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25668 // For chips with slow 32-byte unaligned loads, break the 32-byte operation
25669 // into two 16-byte operations.
25670 ISD::LoadExtType Ext = Ld->getExtensionType();
25672 unsigned AddressSpace = Ld->getAddressSpace();
25673 unsigned Alignment = Ld->getAlignment();
25674 if (RegVT.is256BitVector() && !DCI.isBeforeLegalizeOps() &&
25675 Ext == ISD::NON_EXTLOAD &&
25676 TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), RegVT,
25677 AddressSpace, Alignment, &Fast) && !Fast) {
25678 unsigned NumElems = RegVT.getVectorNumElements();
25682 SDValue Ptr = Ld->getBasePtr();
25683 SDValue Increment =
25684 DAG.getConstant(16, dl, TLI.getPointerTy(DAG.getDataLayout()));
25686 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
25688 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
25689 Ld->getPointerInfo(), Ld->isVolatile(),
25690 Ld->isNonTemporal(), Ld->isInvariant(),
25692 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
25693 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
25694 Ld->getPointerInfo(), Ld->isVolatile(),
25695 Ld->isNonTemporal(), Ld->isInvariant(),
25696 std::min(16U, Alignment));
25697 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
25699 Load2.getValue(1));
25701 SDValue NewVec = DAG.getUNDEF(RegVT);
25702 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
25703 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
25704 return DCI.CombineTo(N, NewVec, TF, true);
25710 /// PerformMLOADCombine - Resolve extending loads
25711 static SDValue PerformMLOADCombine(SDNode *N, SelectionDAG &DAG,
25712 TargetLowering::DAGCombinerInfo &DCI,
25713 const X86Subtarget *Subtarget) {
25714 MaskedLoadSDNode *Mld = cast<MaskedLoadSDNode>(N);
25715 if (Mld->getExtensionType() != ISD::SEXTLOAD)
25718 EVT VT = Mld->getValueType(0);
25719 unsigned NumElems = VT.getVectorNumElements();
25720 EVT LdVT = Mld->getMemoryVT();
25723 assert(LdVT != VT && "Cannot extend to the same type");
25724 unsigned ToSz = VT.getVectorElementType().getSizeInBits();
25725 unsigned FromSz = LdVT.getVectorElementType().getSizeInBits();
25726 // From, To sizes and ElemCount must be pow of two
25727 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
25728 "Unexpected size for extending masked load");
25730 unsigned SizeRatio = ToSz / FromSz;
25731 assert(SizeRatio * NumElems * FromSz == VT.getSizeInBits());
25733 // Create a type on which we perform the shuffle
25734 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
25735 LdVT.getScalarType(), NumElems*SizeRatio);
25736 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
25738 // Convert Src0 value
25739 SDValue WideSrc0 = DAG.getBitcast(WideVecVT, Mld->getSrc0());
25740 if (Mld->getSrc0().getOpcode() != ISD::UNDEF) {
25741 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
25742 for (unsigned i = 0; i != NumElems; ++i)
25743 ShuffleVec[i] = i * SizeRatio;
25745 // Can't shuffle using an illegal type.
25746 assert(DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT) &&
25747 "WideVecVT should be legal");
25748 WideSrc0 = DAG.getVectorShuffle(WideVecVT, dl, WideSrc0,
25749 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
25751 // Prepare the new mask
25753 SDValue Mask = Mld->getMask();
25754 if (Mask.getValueType() == VT) {
25755 // Mask and original value have the same type
25756 NewMask = DAG.getBitcast(WideVecVT, Mask);
25757 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
25758 for (unsigned i = 0; i != NumElems; ++i)
25759 ShuffleVec[i] = i * SizeRatio;
25760 for (unsigned i = NumElems; i != NumElems * SizeRatio; ++i)
25761 ShuffleVec[i] = NumElems * SizeRatio;
25762 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
25763 DAG.getConstant(0, dl, WideVecVT),
25767 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
25768 unsigned WidenNumElts = NumElems*SizeRatio;
25769 unsigned MaskNumElts = VT.getVectorNumElements();
25770 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
25773 unsigned NumConcat = WidenNumElts / MaskNumElts;
25774 SmallVector<SDValue, 16> Ops(NumConcat);
25775 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
25777 for (unsigned i = 1; i != NumConcat; ++i)
25780 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
25783 SDValue WideLd = DAG.getMaskedLoad(WideVecVT, dl, Mld->getChain(),
25784 Mld->getBasePtr(), NewMask, WideSrc0,
25785 Mld->getMemoryVT(), Mld->getMemOperand(),
25787 SDValue NewVec = DAG.getNode(X86ISD::VSEXT, dl, VT, WideLd);
25788 return DCI.CombineTo(N, NewVec, WideLd.getValue(1), true);
25790 /// PerformMSTORECombine - Resolve truncating stores
25791 static SDValue PerformMSTORECombine(SDNode *N, SelectionDAG &DAG,
25792 const X86Subtarget *Subtarget) {
25793 MaskedStoreSDNode *Mst = cast<MaskedStoreSDNode>(N);
25794 if (!Mst->isTruncatingStore())
25797 EVT VT = Mst->getValue().getValueType();
25798 unsigned NumElems = VT.getVectorNumElements();
25799 EVT StVT = Mst->getMemoryVT();
25802 assert(StVT != VT && "Cannot truncate to the same type");
25803 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
25804 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
25806 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25808 // The truncating store is legal in some cases. For example
25809 // vpmovqb, vpmovqw, vpmovqd, vpmovdb, vpmovdw
25810 // are designated for truncate store.
25811 // In this case we don't need any further transformations.
25812 if (TLI.isTruncStoreLegal(VT, StVT))
25815 // From, To sizes and ElemCount must be pow of two
25816 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
25817 "Unexpected size for truncating masked store");
25818 // We are going to use the original vector elt for storing.
25819 // Accumulated smaller vector elements must be a multiple of the store size.
25820 assert (((NumElems * FromSz) % ToSz) == 0 &&
25821 "Unexpected ratio for truncating masked store");
25823 unsigned SizeRatio = FromSz / ToSz;
25824 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
25826 // Create a type on which we perform the shuffle
25827 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
25828 StVT.getScalarType(), NumElems*SizeRatio);
25830 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
25832 SDValue WideVec = DAG.getBitcast(WideVecVT, Mst->getValue());
25833 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
25834 for (unsigned i = 0; i != NumElems; ++i)
25835 ShuffleVec[i] = i * SizeRatio;
25837 // Can't shuffle using an illegal type.
25838 assert(DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT) &&
25839 "WideVecVT should be legal");
25841 SDValue TruncatedVal = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
25842 DAG.getUNDEF(WideVecVT),
25846 SDValue Mask = Mst->getMask();
25847 if (Mask.getValueType() == VT) {
25848 // Mask and original value have the same type
25849 NewMask = DAG.getBitcast(WideVecVT, Mask);
25850 for (unsigned i = 0; i != NumElems; ++i)
25851 ShuffleVec[i] = i * SizeRatio;
25852 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
25853 ShuffleVec[i] = NumElems*SizeRatio;
25854 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
25855 DAG.getConstant(0, dl, WideVecVT),
25859 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
25860 unsigned WidenNumElts = NumElems*SizeRatio;
25861 unsigned MaskNumElts = VT.getVectorNumElements();
25862 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
25865 unsigned NumConcat = WidenNumElts / MaskNumElts;
25866 SmallVector<SDValue, 16> Ops(NumConcat);
25867 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
25869 for (unsigned i = 1; i != NumConcat; ++i)
25872 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
25875 return DAG.getMaskedStore(Mst->getChain(), dl, TruncatedVal,
25876 Mst->getBasePtr(), NewMask, StVT,
25877 Mst->getMemOperand(), false);
25879 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
25880 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
25881 const X86Subtarget *Subtarget) {
25882 StoreSDNode *St = cast<StoreSDNode>(N);
25883 EVT VT = St->getValue().getValueType();
25884 EVT StVT = St->getMemoryVT();
25886 SDValue StoredVal = St->getOperand(1);
25887 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25889 // If we are saving a concatenation of two XMM registers and 32-byte stores
25890 // are slow, such as on Sandy Bridge, perform two 16-byte stores.
25892 unsigned AddressSpace = St->getAddressSpace();
25893 unsigned Alignment = St->getAlignment();
25894 if (VT.is256BitVector() && StVT == VT &&
25895 TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), VT,
25896 AddressSpace, Alignment, &Fast) && !Fast) {
25897 unsigned NumElems = VT.getVectorNumElements();
25901 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
25902 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
25905 DAG.getConstant(16, dl, TLI.getPointerTy(DAG.getDataLayout()));
25906 SDValue Ptr0 = St->getBasePtr();
25907 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
25909 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
25910 St->getPointerInfo(), St->isVolatile(),
25911 St->isNonTemporal(), Alignment);
25912 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
25913 St->getPointerInfo(), St->isVolatile(),
25914 St->isNonTemporal(),
25915 std::min(16U, Alignment));
25916 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
25919 // Optimize trunc store (of multiple scalars) to shuffle and store.
25920 // First, pack all of the elements in one place. Next, store to memory
25921 // in fewer chunks.
25922 if (St->isTruncatingStore() && VT.isVector()) {
25923 // Check if we can detect an AVG pattern from the truncation. If yes,
25924 // replace the trunc store by a normal store with the result of X86ISD::AVG
25927 detectAVGPattern(St->getValue(), St->getMemoryVT(), DAG, Subtarget, dl);
25929 return DAG.getStore(St->getChain(), dl, Avg, St->getBasePtr(),
25930 St->getPointerInfo(), St->isVolatile(),
25931 St->isNonTemporal(), St->getAlignment());
25933 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25934 unsigned NumElems = VT.getVectorNumElements();
25935 assert(StVT != VT && "Cannot truncate to the same type");
25936 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
25937 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
25939 // The truncating store is legal in some cases. For example
25940 // vpmovqb, vpmovqw, vpmovqd, vpmovdb, vpmovdw
25941 // are designated for truncate store.
25942 // In this case we don't need any further transformations.
25943 if (TLI.isTruncStoreLegal(VT, StVT))
25946 // From, To sizes and ElemCount must be pow of two
25947 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
25948 // We are going to use the original vector elt for storing.
25949 // Accumulated smaller vector elements must be a multiple of the store size.
25950 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
25952 unsigned SizeRatio = FromSz / ToSz;
25954 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
25956 // Create a type on which we perform the shuffle
25957 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
25958 StVT.getScalarType(), NumElems*SizeRatio);
25960 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
25962 SDValue WideVec = DAG.getBitcast(WideVecVT, St->getValue());
25963 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
25964 for (unsigned i = 0; i != NumElems; ++i)
25965 ShuffleVec[i] = i * SizeRatio;
25967 // Can't shuffle using an illegal type.
25968 if (!TLI.isTypeLegal(WideVecVT))
25971 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
25972 DAG.getUNDEF(WideVecVT),
25974 // At this point all of the data is stored at the bottom of the
25975 // register. We now need to save it to mem.
25977 // Find the largest store unit
25978 MVT StoreType = MVT::i8;
25979 for (MVT Tp : MVT::integer_valuetypes()) {
25980 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
25984 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
25985 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
25986 (64 <= NumElems * ToSz))
25987 StoreType = MVT::f64;
25989 // Bitcast the original vector into a vector of store-size units
25990 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
25991 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
25992 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
25993 SDValue ShuffWide = DAG.getBitcast(StoreVecVT, Shuff);
25994 SmallVector<SDValue, 8> Chains;
25995 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits() / 8, dl,
25996 TLI.getPointerTy(DAG.getDataLayout()));
25997 SDValue Ptr = St->getBasePtr();
25999 // Perform one or more big stores into memory.
26000 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
26001 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
26002 StoreType, ShuffWide,
26003 DAG.getIntPtrConstant(i, dl));
26004 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
26005 St->getPointerInfo(), St->isVolatile(),
26006 St->isNonTemporal(), St->getAlignment());
26007 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
26008 Chains.push_back(Ch);
26011 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
26014 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
26015 // the FP state in cases where an emms may be missing.
26016 // A preferable solution to the general problem is to figure out the right
26017 // places to insert EMMS. This qualifies as a quick hack.
26019 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
26020 if (VT.getSizeInBits() != 64)
26023 const Function *F = DAG.getMachineFunction().getFunction();
26024 bool NoImplicitFloatOps = F->hasFnAttribute(Attribute::NoImplicitFloat);
26026 !Subtarget->useSoftFloat() && !NoImplicitFloatOps && Subtarget->hasSSE2();
26027 if ((VT.isVector() ||
26028 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
26029 isa<LoadSDNode>(St->getValue()) &&
26030 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
26031 St->getChain().hasOneUse() && !St->isVolatile()) {
26032 SDNode* LdVal = St->getValue().getNode();
26033 LoadSDNode *Ld = nullptr;
26034 int TokenFactorIndex = -1;
26035 SmallVector<SDValue, 8> Ops;
26036 SDNode* ChainVal = St->getChain().getNode();
26037 // Must be a store of a load. We currently handle two cases: the load
26038 // is a direct child, and it's under an intervening TokenFactor. It is
26039 // possible to dig deeper under nested TokenFactors.
26040 if (ChainVal == LdVal)
26041 Ld = cast<LoadSDNode>(St->getChain());
26042 else if (St->getValue().hasOneUse() &&
26043 ChainVal->getOpcode() == ISD::TokenFactor) {
26044 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
26045 if (ChainVal->getOperand(i).getNode() == LdVal) {
26046 TokenFactorIndex = i;
26047 Ld = cast<LoadSDNode>(St->getValue());
26049 Ops.push_back(ChainVal->getOperand(i));
26053 if (!Ld || !ISD::isNormalLoad(Ld))
26056 // If this is not the MMX case, i.e. we are just turning i64 load/store
26057 // into f64 load/store, avoid the transformation if there are multiple
26058 // uses of the loaded value.
26059 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
26064 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
26065 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
26067 if (Subtarget->is64Bit() || F64IsLegal) {
26068 MVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
26069 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
26070 Ld->getPointerInfo(), Ld->isVolatile(),
26071 Ld->isNonTemporal(), Ld->isInvariant(),
26072 Ld->getAlignment());
26073 SDValue NewChain = NewLd.getValue(1);
26074 if (TokenFactorIndex != -1) {
26075 Ops.push_back(NewChain);
26076 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
26078 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
26079 St->getPointerInfo(),
26080 St->isVolatile(), St->isNonTemporal(),
26081 St->getAlignment());
26084 // Otherwise, lower to two pairs of 32-bit loads / stores.
26085 SDValue LoAddr = Ld->getBasePtr();
26086 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
26087 DAG.getConstant(4, LdDL, MVT::i32));
26089 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
26090 Ld->getPointerInfo(),
26091 Ld->isVolatile(), Ld->isNonTemporal(),
26092 Ld->isInvariant(), Ld->getAlignment());
26093 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
26094 Ld->getPointerInfo().getWithOffset(4),
26095 Ld->isVolatile(), Ld->isNonTemporal(),
26097 MinAlign(Ld->getAlignment(), 4));
26099 SDValue NewChain = LoLd.getValue(1);
26100 if (TokenFactorIndex != -1) {
26101 Ops.push_back(LoLd);
26102 Ops.push_back(HiLd);
26103 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
26106 LoAddr = St->getBasePtr();
26107 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
26108 DAG.getConstant(4, StDL, MVT::i32));
26110 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
26111 St->getPointerInfo(),
26112 St->isVolatile(), St->isNonTemporal(),
26113 St->getAlignment());
26114 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
26115 St->getPointerInfo().getWithOffset(4),
26117 St->isNonTemporal(),
26118 MinAlign(St->getAlignment(), 4));
26119 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
26122 // This is similar to the above case, but here we handle a scalar 64-bit
26123 // integer store that is extracted from a vector on a 32-bit target.
26124 // If we have SSE2, then we can treat it like a floating-point double
26125 // to get past legalization. The execution dependencies fixup pass will
26126 // choose the optimal machine instruction for the store if this really is
26127 // an integer or v2f32 rather than an f64.
26128 if (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit() &&
26129 St->getOperand(1).getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
26130 SDValue OldExtract = St->getOperand(1);
26131 SDValue ExtOp0 = OldExtract.getOperand(0);
26132 unsigned VecSize = ExtOp0.getValueSizeInBits();
26133 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, VecSize / 64);
26134 SDValue BitCast = DAG.getBitcast(VecVT, ExtOp0);
26135 SDValue NewExtract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
26136 BitCast, OldExtract.getOperand(1));
26137 return DAG.getStore(St->getChain(), dl, NewExtract, St->getBasePtr(),
26138 St->getPointerInfo(), St->isVolatile(),
26139 St->isNonTemporal(), St->getAlignment());
26145 /// Return 'true' if this vector operation is "horizontal"
26146 /// and return the operands for the horizontal operation in LHS and RHS. A
26147 /// horizontal operation performs the binary operation on successive elements
26148 /// of its first operand, then on successive elements of its second operand,
26149 /// returning the resulting values in a vector. For example, if
26150 /// A = < float a0, float a1, float a2, float a3 >
26152 /// B = < float b0, float b1, float b2, float b3 >
26153 /// then the result of doing a horizontal operation on A and B is
26154 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
26155 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
26156 /// A horizontal-op B, for some already available A and B, and if so then LHS is
26157 /// set to A, RHS to B, and the routine returns 'true'.
26158 /// Note that the binary operation should have the property that if one of the
26159 /// operands is UNDEF then the result is UNDEF.
26160 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
26161 // Look for the following pattern: if
26162 // A = < float a0, float a1, float a2, float a3 >
26163 // B = < float b0, float b1, float b2, float b3 >
26165 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
26166 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
26167 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
26168 // which is A horizontal-op B.
26170 // At least one of the operands should be a vector shuffle.
26171 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
26172 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
26175 MVT VT = LHS.getSimpleValueType();
26177 assert((VT.is128BitVector() || VT.is256BitVector()) &&
26178 "Unsupported vector type for horizontal add/sub");
26180 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
26181 // operate independently on 128-bit lanes.
26182 unsigned NumElts = VT.getVectorNumElements();
26183 unsigned NumLanes = VT.getSizeInBits()/128;
26184 unsigned NumLaneElts = NumElts / NumLanes;
26185 assert((NumLaneElts % 2 == 0) &&
26186 "Vector type should have an even number of elements in each lane");
26187 unsigned HalfLaneElts = NumLaneElts/2;
26189 // View LHS in the form
26190 // LHS = VECTOR_SHUFFLE A, B, LMask
26191 // If LHS is not a shuffle then pretend it is the shuffle
26192 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
26193 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
26196 SmallVector<int, 16> LMask(NumElts);
26197 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
26198 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
26199 A = LHS.getOperand(0);
26200 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
26201 B = LHS.getOperand(1);
26202 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
26203 std::copy(Mask.begin(), Mask.end(), LMask.begin());
26205 if (LHS.getOpcode() != ISD::UNDEF)
26207 for (unsigned i = 0; i != NumElts; ++i)
26211 // Likewise, view RHS in the form
26212 // RHS = VECTOR_SHUFFLE C, D, RMask
26214 SmallVector<int, 16> RMask(NumElts);
26215 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
26216 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
26217 C = RHS.getOperand(0);
26218 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
26219 D = RHS.getOperand(1);
26220 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
26221 std::copy(Mask.begin(), Mask.end(), RMask.begin());
26223 if (RHS.getOpcode() != ISD::UNDEF)
26225 for (unsigned i = 0; i != NumElts; ++i)
26229 // Check that the shuffles are both shuffling the same vectors.
26230 if (!(A == C && B == D) && !(A == D && B == C))
26233 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
26234 if (!A.getNode() && !B.getNode())
26237 // If A and B occur in reverse order in RHS, then "swap" them (which means
26238 // rewriting the mask).
26240 ShuffleVectorSDNode::commuteMask(RMask);
26242 // At this point LHS and RHS are equivalent to
26243 // LHS = VECTOR_SHUFFLE A, B, LMask
26244 // RHS = VECTOR_SHUFFLE A, B, RMask
26245 // Check that the masks correspond to performing a horizontal operation.
26246 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
26247 for (unsigned i = 0; i != NumLaneElts; ++i) {
26248 int LIdx = LMask[i+l], RIdx = RMask[i+l];
26250 // Ignore any UNDEF components.
26251 if (LIdx < 0 || RIdx < 0 ||
26252 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
26253 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
26256 // Check that successive elements are being operated on. If not, this is
26257 // not a horizontal operation.
26258 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
26259 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
26260 if (!(LIdx == Index && RIdx == Index + 1) &&
26261 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
26266 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
26267 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
26271 /// Do target-specific dag combines on floating point adds.
26272 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
26273 const X86Subtarget *Subtarget) {
26274 EVT VT = N->getValueType(0);
26275 SDValue LHS = N->getOperand(0);
26276 SDValue RHS = N->getOperand(1);
26278 // Try to synthesize horizontal adds from adds of shuffles.
26279 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
26280 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
26281 isHorizontalBinOp(LHS, RHS, true))
26282 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
26286 /// Do target-specific dag combines on floating point subs.
26287 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
26288 const X86Subtarget *Subtarget) {
26289 EVT VT = N->getValueType(0);
26290 SDValue LHS = N->getOperand(0);
26291 SDValue RHS = N->getOperand(1);
26293 // Try to synthesize horizontal subs from subs of shuffles.
26294 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
26295 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
26296 isHorizontalBinOp(LHS, RHS, false))
26297 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
26301 /// Do target-specific dag combines on floating point negations.
26302 static SDValue PerformFNEGCombine(SDNode *N, SelectionDAG &DAG,
26303 const X86Subtarget *Subtarget) {
26304 EVT VT = N->getValueType(0);
26305 EVT SVT = VT.getScalarType();
26306 SDValue Arg = N->getOperand(0);
26309 // Let legalize expand this if it isn't a legal type yet.
26310 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
26313 // If we're negating a FMUL node on a target with FMA, then we can avoid the
26314 // use of a constant by performing (-0 - A*B) instead.
26315 // FIXME: Check rounding control flags as well once it becomes available.
26316 if (Arg.getOpcode() == ISD::FMUL && (SVT == MVT::f32 || SVT == MVT::f64) &&
26317 Arg->getFlags()->hasNoSignedZeros() && Subtarget->hasAnyFMA()) {
26318 SDValue Zero = DAG.getConstantFP(0.0, DL, VT);
26319 return DAG.getNode(X86ISD::FNMSUB, DL, VT, Arg.getOperand(0),
26320 Arg.getOperand(1), Zero);
26323 // If we're negating a FMA node, then we can adjust the
26324 // instruction to include the extra negation.
26325 if (Arg.hasOneUse()) {
26326 switch (Arg.getOpcode()) {
26327 case X86ISD::FMADD:
26328 return DAG.getNode(X86ISD::FNMSUB, DL, VT, Arg.getOperand(0),
26329 Arg.getOperand(1), Arg.getOperand(2));
26330 case X86ISD::FMSUB:
26331 return DAG.getNode(X86ISD::FNMADD, DL, VT, Arg.getOperand(0),
26332 Arg.getOperand(1), Arg.getOperand(2));
26333 case X86ISD::FNMADD:
26334 return DAG.getNode(X86ISD::FMSUB, DL, VT, Arg.getOperand(0),
26335 Arg.getOperand(1), Arg.getOperand(2));
26336 case X86ISD::FNMSUB:
26337 return DAG.getNode(X86ISD::FMADD, DL, VT, Arg.getOperand(0),
26338 Arg.getOperand(1), Arg.getOperand(2));
26344 static SDValue lowerX86FPLogicOp(SDNode *N, SelectionDAG &DAG,
26345 const X86Subtarget *Subtarget) {
26346 EVT VT = N->getValueType(0);
26347 if (VT.is512BitVector() && !Subtarget->hasDQI()) {
26348 // VXORPS, VORPS, VANDPS, VANDNPS are supported only under DQ extention.
26349 // These logic operations may be executed in the integer domain.
26351 MVT IntScalar = MVT::getIntegerVT(VT.getScalarSizeInBits());
26352 MVT IntVT = MVT::getVectorVT(IntScalar, VT.getVectorNumElements());
26354 SDValue Op0 = DAG.getNode(ISD::BITCAST, dl, IntVT, N->getOperand(0));
26355 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, IntVT, N->getOperand(1));
26356 unsigned IntOpcode = 0;
26357 switch (N->getOpcode()) {
26358 default: llvm_unreachable("Unexpected FP logic op");
26359 case X86ISD::FOR: IntOpcode = ISD::OR; break;
26360 case X86ISD::FXOR: IntOpcode = ISD::XOR; break;
26361 case X86ISD::FAND: IntOpcode = ISD::AND; break;
26362 case X86ISD::FANDN: IntOpcode = X86ISD::ANDNP; break;
26364 SDValue IntOp = DAG.getNode(IntOpcode, dl, IntVT, Op0, Op1);
26365 return DAG.getNode(ISD::BITCAST, dl, VT, IntOp);
26369 /// Do target-specific dag combines on X86ISD::FOR and X86ISD::FXOR nodes.
26370 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG,
26371 const X86Subtarget *Subtarget) {
26372 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
26374 // F[X]OR(0.0, x) -> x
26375 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
26376 if (C->getValueAPF().isPosZero())
26377 return N->getOperand(1);
26379 // F[X]OR(x, 0.0) -> x
26380 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
26381 if (C->getValueAPF().isPosZero())
26382 return N->getOperand(0);
26384 return lowerX86FPLogicOp(N, DAG, Subtarget);
26387 /// Do target-specific dag combines on X86ISD::FMIN and X86ISD::FMAX nodes.
26388 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
26389 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
26391 // Only perform optimizations if UnsafeMath is used.
26392 if (!DAG.getTarget().Options.UnsafeFPMath)
26395 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
26396 // into FMINC and FMAXC, which are Commutative operations.
26397 unsigned NewOp = 0;
26398 switch (N->getOpcode()) {
26399 default: llvm_unreachable("unknown opcode");
26400 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
26401 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
26404 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
26405 N->getOperand(0), N->getOperand(1));
26408 /// Do target-specific dag combines on X86ISD::FAND nodes.
26409 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG,
26410 const X86Subtarget *Subtarget) {
26411 // FAND(0.0, x) -> 0.0
26412 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
26413 if (C->getValueAPF().isPosZero())
26414 return N->getOperand(0);
26416 // FAND(x, 0.0) -> 0.0
26417 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
26418 if (C->getValueAPF().isPosZero())
26419 return N->getOperand(1);
26421 return lowerX86FPLogicOp(N, DAG, Subtarget);
26424 /// Do target-specific dag combines on X86ISD::FANDN nodes
26425 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG,
26426 const X86Subtarget *Subtarget) {
26427 // FANDN(0.0, x) -> x
26428 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
26429 if (C->getValueAPF().isPosZero())
26430 return N->getOperand(1);
26432 // FANDN(x, 0.0) -> 0.0
26433 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
26434 if (C->getValueAPF().isPosZero())
26435 return N->getOperand(1);
26437 return lowerX86FPLogicOp(N, DAG, Subtarget);
26440 static SDValue PerformBTCombine(SDNode *N,
26442 TargetLowering::DAGCombinerInfo &DCI) {
26443 // BT ignores high bits in the bit index operand.
26444 SDValue Op1 = N->getOperand(1);
26445 if (Op1.hasOneUse()) {
26446 unsigned BitWidth = Op1.getValueSizeInBits();
26447 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
26448 APInt KnownZero, KnownOne;
26449 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
26450 !DCI.isBeforeLegalizeOps());
26451 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
26452 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
26453 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
26454 DCI.CommitTargetLoweringOpt(TLO);
26459 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
26460 SDValue Op = N->getOperand(0);
26461 if (Op.getOpcode() == ISD::BITCAST)
26462 Op = Op.getOperand(0);
26463 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
26464 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
26465 VT.getVectorElementType().getSizeInBits() ==
26466 OpVT.getVectorElementType().getSizeInBits()) {
26467 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
26472 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
26473 const X86Subtarget *Subtarget) {
26474 EVT VT = N->getValueType(0);
26475 if (!VT.isVector())
26478 SDValue N0 = N->getOperand(0);
26479 SDValue N1 = N->getOperand(1);
26480 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
26483 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
26484 // both SSE and AVX2 since there is no sign-extended shift right
26485 // operation on a vector with 64-bit elements.
26486 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
26487 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
26488 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
26489 N0.getOpcode() == ISD::SIGN_EXTEND)) {
26490 SDValue N00 = N0.getOperand(0);
26492 // EXTLOAD has a better solution on AVX2,
26493 // it may be replaced with X86ISD::VSEXT node.
26494 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
26495 if (!ISD::isNormalLoad(N00.getNode()))
26498 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
26499 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
26501 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
26507 /// sext(add_nsw(x, C)) --> add(sext(x), C_sext)
26508 /// Promoting a sign extension ahead of an 'add nsw' exposes opportunities
26509 /// to combine math ops, use an LEA, or use a complex addressing mode. This can
26510 /// eliminate extend, add, and shift instructions.
26511 static SDValue promoteSextBeforeAddNSW(SDNode *Sext, SelectionDAG &DAG,
26512 const X86Subtarget *Subtarget) {
26513 // TODO: This should be valid for other integer types.
26514 EVT VT = Sext->getValueType(0);
26515 if (VT != MVT::i64)
26518 // We need an 'add nsw' feeding into the 'sext'.
26519 SDValue Add = Sext->getOperand(0);
26520 if (Add.getOpcode() != ISD::ADD || !Add->getFlags()->hasNoSignedWrap())
26523 // Having a constant operand to the 'add' ensures that we are not increasing
26524 // the instruction count because the constant is extended for free below.
26525 // A constant operand can also become the displacement field of an LEA.
26526 auto *AddOp1 = dyn_cast<ConstantSDNode>(Add.getOperand(1));
26530 // Don't make the 'add' bigger if there's no hope of combining it with some
26531 // other 'add' or 'shl' instruction.
26532 // TODO: It may be profitable to generate simpler LEA instructions in place
26533 // of single 'add' instructions, but the cost model for selecting an LEA
26534 // currently has a high threshold.
26535 bool HasLEAPotential = false;
26536 for (auto *User : Sext->uses()) {
26537 if (User->getOpcode() == ISD::ADD || User->getOpcode() == ISD::SHL) {
26538 HasLEAPotential = true;
26542 if (!HasLEAPotential)
26545 // Everything looks good, so pull the 'sext' ahead of the 'add'.
26546 int64_t AddConstant = AddOp1->getSExtValue();
26547 SDValue AddOp0 = Add.getOperand(0);
26548 SDValue NewSext = DAG.getNode(ISD::SIGN_EXTEND, SDLoc(Sext), VT, AddOp0);
26549 SDValue NewConstant = DAG.getConstant(AddConstant, SDLoc(Add), VT);
26551 // The wider add is guaranteed to not wrap because both operands are
26554 Flags.setNoSignedWrap(true);
26555 return DAG.getNode(ISD::ADD, SDLoc(Add), VT, NewSext, NewConstant, &Flags);
26558 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
26559 TargetLowering::DAGCombinerInfo &DCI,
26560 const X86Subtarget *Subtarget) {
26561 SDValue N0 = N->getOperand(0);
26562 EVT VT = N->getValueType(0);
26563 EVT SVT = VT.getScalarType();
26564 EVT InVT = N0.getValueType();
26565 EVT InSVT = InVT.getScalarType();
26568 // (i8,i32 sext (sdivrem (i8 x, i8 y)) ->
26569 // (i8,i32 (sdivrem_sext_hreg (i8 x, i8 y)
26570 // This exposes the sext to the sdivrem lowering, so that it directly extends
26571 // from AH (which we otherwise need to do contortions to access).
26572 if (N0.getOpcode() == ISD::SDIVREM && N0.getResNo() == 1 &&
26573 InVT == MVT::i8 && VT == MVT::i32) {
26574 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
26575 SDValue R = DAG.getNode(X86ISD::SDIVREM8_SEXT_HREG, DL, NodeTys,
26576 N0.getOperand(0), N0.getOperand(1));
26577 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
26578 return R.getValue(1);
26581 if (!DCI.isBeforeLegalizeOps()) {
26582 if (InVT == MVT::i1) {
26583 SDValue Zero = DAG.getConstant(0, DL, VT);
26585 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), DL, VT);
26586 return DAG.getNode(ISD::SELECT, DL, VT, N0, AllOnes, Zero);
26591 if (VT.isVector() && Subtarget->hasSSE2()) {
26592 auto ExtendVecSize = [&DAG](SDLoc DL, SDValue N, unsigned Size) {
26593 EVT InVT = N.getValueType();
26594 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), InVT.getScalarType(),
26595 Size / InVT.getScalarSizeInBits());
26596 SmallVector<SDValue, 8> Opnds(Size / InVT.getSizeInBits(),
26597 DAG.getUNDEF(InVT));
26599 return DAG.getNode(ISD::CONCAT_VECTORS, DL, OutVT, Opnds);
26602 // If target-size is less than 128-bits, extend to a type that would extend
26603 // to 128 bits, extend that and extract the original target vector.
26604 if (VT.getSizeInBits() < 128 && !(128 % VT.getSizeInBits()) &&
26605 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
26606 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
26607 unsigned Scale = 128 / VT.getSizeInBits();
26609 EVT::getVectorVT(*DAG.getContext(), SVT, 128 / SVT.getSizeInBits());
26610 SDValue Ex = ExtendVecSize(DL, N0, Scale * InVT.getSizeInBits());
26611 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND, DL, ExVT, Ex);
26612 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, SExt,
26613 DAG.getIntPtrConstant(0, DL));
26616 // If target-size is 128-bits, then convert to ISD::SIGN_EXTEND_VECTOR_INREG
26617 // which ensures lowering to X86ISD::VSEXT (pmovsx*).
26618 if (VT.getSizeInBits() == 128 &&
26619 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
26620 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
26621 SDValue ExOp = ExtendVecSize(DL, N0, 128);
26622 return DAG.getSignExtendVectorInReg(ExOp, DL, VT);
26625 // On pre-AVX2 targets, split into 128-bit nodes of
26626 // ISD::SIGN_EXTEND_VECTOR_INREG.
26627 if (!Subtarget->hasInt256() && !(VT.getSizeInBits() % 128) &&
26628 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
26629 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
26630 unsigned NumVecs = VT.getSizeInBits() / 128;
26631 unsigned NumSubElts = 128 / SVT.getSizeInBits();
26632 EVT SubVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumSubElts);
26633 EVT InSubVT = EVT::getVectorVT(*DAG.getContext(), InSVT, NumSubElts);
26635 SmallVector<SDValue, 8> Opnds;
26636 for (unsigned i = 0, Offset = 0; i != NumVecs;
26637 ++i, Offset += NumSubElts) {
26638 SDValue SrcVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InSubVT, N0,
26639 DAG.getIntPtrConstant(Offset, DL));
26640 SrcVec = ExtendVecSize(DL, SrcVec, 128);
26641 SrcVec = DAG.getSignExtendVectorInReg(SrcVec, DL, SubVT);
26642 Opnds.push_back(SrcVec);
26644 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Opnds);
26648 if (Subtarget->hasAVX() && VT.is256BitVector())
26649 if (SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget))
26652 if (SDValue NewAdd = promoteSextBeforeAddNSW(N, DAG, Subtarget))
26658 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
26659 const X86Subtarget* Subtarget) {
26661 EVT VT = N->getValueType(0);
26663 // Let legalize expand this if it isn't a legal type yet.
26664 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
26667 EVT ScalarVT = VT.getScalarType();
26668 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) || !Subtarget->hasAnyFMA())
26671 SDValue A = N->getOperand(0);
26672 SDValue B = N->getOperand(1);
26673 SDValue C = N->getOperand(2);
26675 bool NegA = (A.getOpcode() == ISD::FNEG);
26676 bool NegB = (B.getOpcode() == ISD::FNEG);
26677 bool NegC = (C.getOpcode() == ISD::FNEG);
26679 // Negative multiplication when NegA xor NegB
26680 bool NegMul = (NegA != NegB);
26682 A = A.getOperand(0);
26684 B = B.getOperand(0);
26686 C = C.getOperand(0);
26690 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
26692 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
26694 return DAG.getNode(Opcode, dl, VT, A, B, C);
26697 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
26698 TargetLowering::DAGCombinerInfo &DCI,
26699 const X86Subtarget *Subtarget) {
26700 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
26701 // (and (i32 x86isd::setcc_carry), 1)
26702 // This eliminates the zext. This transformation is necessary because
26703 // ISD::SETCC is always legalized to i8.
26705 SDValue N0 = N->getOperand(0);
26706 EVT VT = N->getValueType(0);
26708 if (N0.getOpcode() == ISD::AND &&
26710 N0.getOperand(0).hasOneUse()) {
26711 SDValue N00 = N0.getOperand(0);
26712 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
26713 if (!isOneConstant(N0.getOperand(1)))
26715 return DAG.getNode(ISD::AND, dl, VT,
26716 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
26717 N00.getOperand(0), N00.getOperand(1)),
26718 DAG.getConstant(1, dl, VT));
26722 if (N0.getOpcode() == ISD::TRUNCATE &&
26724 N0.getOperand(0).hasOneUse()) {
26725 SDValue N00 = N0.getOperand(0);
26726 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
26727 return DAG.getNode(ISD::AND, dl, VT,
26728 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
26729 N00.getOperand(0), N00.getOperand(1)),
26730 DAG.getConstant(1, dl, VT));
26734 if (VT.is256BitVector())
26735 if (SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget))
26738 // (i8,i32 zext (udivrem (i8 x, i8 y)) ->
26739 // (i8,i32 (udivrem_zext_hreg (i8 x, i8 y)
26740 // This exposes the zext to the udivrem lowering, so that it directly extends
26741 // from AH (which we otherwise need to do contortions to access).
26742 if (N0.getOpcode() == ISD::UDIVREM &&
26743 N0.getResNo() == 1 && N0.getValueType() == MVT::i8 &&
26744 (VT == MVT::i32 || VT == MVT::i64)) {
26745 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
26746 SDValue R = DAG.getNode(X86ISD::UDIVREM8_ZEXT_HREG, dl, NodeTys,
26747 N0.getOperand(0), N0.getOperand(1));
26748 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
26749 return R.getValue(1);
26755 // Optimize x == -y --> x+y == 0
26756 // x != -y --> x+y != 0
26757 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
26758 const X86Subtarget* Subtarget) {
26759 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
26760 SDValue LHS = N->getOperand(0);
26761 SDValue RHS = N->getOperand(1);
26762 EVT VT = N->getValueType(0);
26765 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
26766 if (isNullConstant(LHS.getOperand(0)) && LHS.hasOneUse()) {
26767 SDValue addV = DAG.getNode(ISD::ADD, DL, LHS.getValueType(), RHS,
26768 LHS.getOperand(1));
26769 return DAG.getSetCC(DL, N->getValueType(0), addV,
26770 DAG.getConstant(0, DL, addV.getValueType()), CC);
26772 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
26773 if (isNullConstant(RHS.getOperand(0)) && RHS.hasOneUse()) {
26774 SDValue addV = DAG.getNode(ISD::ADD, DL, RHS.getValueType(), LHS,
26775 RHS.getOperand(1));
26776 return DAG.getSetCC(DL, N->getValueType(0), addV,
26777 DAG.getConstant(0, DL, addV.getValueType()), CC);
26780 if (VT.getScalarType() == MVT::i1 &&
26781 (CC == ISD::SETNE || CC == ISD::SETEQ || ISD::isSignedIntSetCC(CC))) {
26783 (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
26784 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
26785 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
26787 if (!IsSEXT0 || !IsVZero1) {
26788 // Swap the operands and update the condition code.
26789 std::swap(LHS, RHS);
26790 CC = ISD::getSetCCSwappedOperands(CC);
26792 IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
26793 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
26794 IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
26797 if (IsSEXT0 && IsVZero1) {
26798 assert(VT == LHS.getOperand(0).getValueType() &&
26799 "Uexpected operand type");
26800 if (CC == ISD::SETGT)
26801 return DAG.getConstant(0, DL, VT);
26802 if (CC == ISD::SETLE)
26803 return DAG.getConstant(1, DL, VT);
26804 if (CC == ISD::SETEQ || CC == ISD::SETGE)
26805 return DAG.getNOT(DL, LHS.getOperand(0), VT);
26807 assert((CC == ISD::SETNE || CC == ISD::SETLT) &&
26808 "Unexpected condition code!");
26809 return LHS.getOperand(0);
26816 static SDValue PerformBLENDICombine(SDNode *N, SelectionDAG &DAG) {
26817 SDValue V0 = N->getOperand(0);
26818 SDValue V1 = N->getOperand(1);
26820 EVT VT = N->getValueType(0);
26822 // Canonicalize a v2f64 blend with a mask of 2 by swapping the vector
26823 // operands and changing the mask to 1. This saves us a bunch of
26824 // pattern-matching possibilities related to scalar math ops in SSE/AVX.
26825 // x86InstrInfo knows how to commute this back after instruction selection
26826 // if it would help register allocation.
26828 // TODO: If optimizing for size or a processor that doesn't suffer from
26829 // partial register update stalls, this should be transformed into a MOVSD
26830 // instruction because a MOVSD is 1-2 bytes smaller than a BLENDPD.
26832 if (VT == MVT::v2f64)
26833 if (auto *Mask = dyn_cast<ConstantSDNode>(N->getOperand(2)))
26834 if (Mask->getZExtValue() == 2 && !isShuffleFoldableLoad(V0)) {
26835 SDValue NewMask = DAG.getConstant(1, DL, MVT::i8);
26836 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V0, NewMask);
26842 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
26843 // as "sbb reg,reg", since it can be extended without zext and produces
26844 // an all-ones bit which is more useful than 0/1 in some cases.
26845 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
26848 return DAG.getNode(ISD::AND, DL, VT,
26849 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
26850 DAG.getConstant(X86::COND_B, DL, MVT::i8),
26852 DAG.getConstant(1, DL, VT));
26853 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
26854 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
26855 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
26856 DAG.getConstant(X86::COND_B, DL, MVT::i8),
26860 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
26861 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
26862 TargetLowering::DAGCombinerInfo &DCI,
26863 const X86Subtarget *Subtarget) {
26865 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
26866 SDValue EFLAGS = N->getOperand(1);
26868 if (CC == X86::COND_A) {
26869 // Try to convert COND_A into COND_B in an attempt to facilitate
26870 // materializing "setb reg".
26872 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
26873 // cannot take an immediate as its first operand.
26875 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
26876 EFLAGS.getValueType().isInteger() &&
26877 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
26878 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
26879 EFLAGS.getNode()->getVTList(),
26880 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
26881 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
26882 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
26886 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
26887 // a zext and produces an all-ones bit which is more useful than 0/1 in some
26889 if (CC == X86::COND_B)
26890 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
26892 if (SDValue Flags = checkBoolTestSetCCCombine(EFLAGS, CC)) {
26893 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
26894 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
26900 // Optimize branch condition evaluation.
26902 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
26903 TargetLowering::DAGCombinerInfo &DCI,
26904 const X86Subtarget *Subtarget) {
26906 SDValue Chain = N->getOperand(0);
26907 SDValue Dest = N->getOperand(1);
26908 SDValue EFLAGS = N->getOperand(3);
26909 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
26911 if (SDValue Flags = checkBoolTestSetCCCombine(EFLAGS, CC)) {
26912 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
26913 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
26920 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
26921 SelectionDAG &DAG) {
26922 // Take advantage of vector comparisons producing 0 or -1 in each lane to
26923 // optimize away operation when it's from a constant.
26925 // The general transformation is:
26926 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
26927 // AND(VECTOR_CMP(x,y), constant2)
26928 // constant2 = UNARYOP(constant)
26930 // Early exit if this isn't a vector operation, the operand of the
26931 // unary operation isn't a bitwise AND, or if the sizes of the operations
26932 // aren't the same.
26933 EVT VT = N->getValueType(0);
26934 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
26935 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
26936 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
26939 // Now check that the other operand of the AND is a constant. We could
26940 // make the transformation for non-constant splats as well, but it's unclear
26941 // that would be a benefit as it would not eliminate any operations, just
26942 // perform one more step in scalar code before moving to the vector unit.
26943 if (BuildVectorSDNode *BV =
26944 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
26945 // Bail out if the vector isn't a constant.
26946 if (!BV->isConstant())
26949 // Everything checks out. Build up the new and improved node.
26951 EVT IntVT = BV->getValueType(0);
26952 // Create a new constant of the appropriate type for the transformed
26954 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
26955 // The AND node needs bitcasts to/from an integer vector type around it.
26956 SDValue MaskConst = DAG.getBitcast(IntVT, SourceConst);
26957 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
26958 N->getOperand(0)->getOperand(0), MaskConst);
26959 SDValue Res = DAG.getBitcast(VT, NewAnd);
26966 static SDValue PerformUINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
26967 const X86Subtarget *Subtarget) {
26968 SDValue Op0 = N->getOperand(0);
26969 EVT VT = N->getValueType(0);
26970 EVT InVT = Op0.getValueType();
26971 EVT InSVT = InVT.getScalarType();
26972 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
26974 // UINT_TO_FP(vXi8) -> SINT_TO_FP(ZEXT(vXi8 to vXi32))
26975 // UINT_TO_FP(vXi16) -> SINT_TO_FP(ZEXT(vXi16 to vXi32))
26976 if (InVT.isVector() && (InSVT == MVT::i8 || InSVT == MVT::i16)) {
26978 EVT DstVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
26979 InVT.getVectorNumElements());
26980 SDValue P = DAG.getNode(ISD::ZERO_EXTEND, dl, DstVT, Op0);
26982 if (TLI.isOperationLegal(ISD::UINT_TO_FP, DstVT))
26983 return DAG.getNode(ISD::UINT_TO_FP, dl, VT, P);
26985 return DAG.getNode(ISD::SINT_TO_FP, dl, VT, P);
26991 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
26992 const X86Subtarget *Subtarget) {
26993 // First try to optimize away the conversion entirely when it's
26994 // conditionally from a constant. Vectors only.
26995 if (SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG))
26998 // Now move on to more general possibilities.
26999 SDValue Op0 = N->getOperand(0);
27000 EVT VT = N->getValueType(0);
27001 EVT InVT = Op0.getValueType();
27002 EVT InSVT = InVT.getScalarType();
27004 // SINT_TO_FP(vXi8) -> SINT_TO_FP(SEXT(vXi8 to vXi32))
27005 // SINT_TO_FP(vXi16) -> SINT_TO_FP(SEXT(vXi16 to vXi32))
27006 if (InVT.isVector() && (InSVT == MVT::i8 || InSVT == MVT::i16)) {
27008 EVT DstVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
27009 InVT.getVectorNumElements());
27010 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
27011 return DAG.getNode(ISD::SINT_TO_FP, dl, VT, P);
27014 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
27015 // a 32-bit target where SSE doesn't support i64->FP operations.
27016 if (!Subtarget->useSoftFloat() && Op0.getOpcode() == ISD::LOAD) {
27017 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
27018 EVT LdVT = Ld->getValueType(0);
27020 // This transformation is not supported if the result type is f16
27021 if (VT == MVT::f16)
27024 if (!Ld->isVolatile() && !VT.isVector() &&
27025 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
27026 !Subtarget->is64Bit() && LdVT == MVT::i64) {
27027 SDValue FILDChain = Subtarget->getTargetLowering()->BuildFILD(
27028 SDValue(N, 0), LdVT, Ld->getChain(), Op0, DAG);
27029 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
27036 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
27037 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
27038 X86TargetLowering::DAGCombinerInfo &DCI) {
27039 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
27040 // the result is either zero or one (depending on the input carry bit).
27041 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
27042 if (X86::isZeroNode(N->getOperand(0)) &&
27043 X86::isZeroNode(N->getOperand(1)) &&
27044 // We don't have a good way to replace an EFLAGS use, so only do this when
27046 SDValue(N, 1).use_empty()) {
27048 EVT VT = N->getValueType(0);
27049 SDValue CarryOut = DAG.getConstant(0, DL, N->getValueType(1));
27050 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
27051 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
27052 DAG.getConstant(X86::COND_B, DL,
27055 DAG.getConstant(1, DL, VT));
27056 return DCI.CombineTo(N, Res1, CarryOut);
27062 // fold (add Y, (sete X, 0)) -> adc 0, Y
27063 // (add Y, (setne X, 0)) -> sbb -1, Y
27064 // (sub (sete X, 0), Y) -> sbb 0, Y
27065 // (sub (setne X, 0), Y) -> adc -1, Y
27066 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
27069 // Look through ZExts.
27070 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
27071 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
27074 SDValue SetCC = Ext.getOperand(0);
27075 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
27078 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
27079 if (CC != X86::COND_E && CC != X86::COND_NE)
27082 SDValue Cmp = SetCC.getOperand(1);
27083 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
27084 !X86::isZeroNode(Cmp.getOperand(1)) ||
27085 !Cmp.getOperand(0).getValueType().isInteger())
27088 SDValue CmpOp0 = Cmp.getOperand(0);
27089 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
27090 DAG.getConstant(1, DL, CmpOp0.getValueType()));
27092 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
27093 if (CC == X86::COND_NE)
27094 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
27095 DL, OtherVal.getValueType(), OtherVal,
27096 DAG.getConstant(-1ULL, DL, OtherVal.getValueType()),
27098 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
27099 DL, OtherVal.getValueType(), OtherVal,
27100 DAG.getConstant(0, DL, OtherVal.getValueType()), NewCmp);
27103 /// PerformADDCombine - Do target-specific dag combines on integer adds.
27104 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
27105 const X86Subtarget *Subtarget) {
27106 EVT VT = N->getValueType(0);
27107 SDValue Op0 = N->getOperand(0);
27108 SDValue Op1 = N->getOperand(1);
27110 // Try to synthesize horizontal adds from adds of shuffles.
27111 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
27112 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
27113 isHorizontalBinOp(Op0, Op1, true))
27114 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
27116 return OptimizeConditionalInDecrement(N, DAG);
27119 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
27120 const X86Subtarget *Subtarget) {
27121 SDValue Op0 = N->getOperand(0);
27122 SDValue Op1 = N->getOperand(1);
27124 // X86 can't encode an immediate LHS of a sub. See if we can push the
27125 // negation into a preceding instruction.
27126 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
27127 // If the RHS of the sub is a XOR with one use and a constant, invert the
27128 // immediate. Then add one to the LHS of the sub so we can turn
27129 // X-Y -> X+~Y+1, saving one register.
27130 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
27131 isa<ConstantSDNode>(Op1.getOperand(1))) {
27132 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
27133 EVT VT = Op0.getValueType();
27134 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
27136 DAG.getConstant(~XorC, SDLoc(Op1), VT));
27137 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
27138 DAG.getConstant(C->getAPIntValue() + 1, SDLoc(N), VT));
27142 // Try to synthesize horizontal adds from adds of shuffles.
27143 EVT VT = N->getValueType(0);
27144 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
27145 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
27146 isHorizontalBinOp(Op0, Op1, true))
27147 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
27149 return OptimizeConditionalInDecrement(N, DAG);
27152 /// performVZEXTCombine - Performs build vector combines
27153 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
27154 TargetLowering::DAGCombinerInfo &DCI,
27155 const X86Subtarget *Subtarget) {
27157 MVT VT = N->getSimpleValueType(0);
27158 SDValue Op = N->getOperand(0);
27159 MVT OpVT = Op.getSimpleValueType();
27160 MVT OpEltVT = OpVT.getVectorElementType();
27161 unsigned InputBits = OpEltVT.getSizeInBits() * VT.getVectorNumElements();
27163 // (vzext (bitcast (vzext (x)) -> (vzext x)
27165 while (V.getOpcode() == ISD::BITCAST)
27166 V = V.getOperand(0);
27168 if (V != Op && V.getOpcode() == X86ISD::VZEXT) {
27169 MVT InnerVT = V.getSimpleValueType();
27170 MVT InnerEltVT = InnerVT.getVectorElementType();
27172 // If the element sizes match exactly, we can just do one larger vzext. This
27173 // is always an exact type match as vzext operates on integer types.
27174 if (OpEltVT == InnerEltVT) {
27175 assert(OpVT == InnerVT && "Types must match for vzext!");
27176 return DAG.getNode(X86ISD::VZEXT, DL, VT, V.getOperand(0));
27179 // The only other way we can combine them is if only a single element of the
27180 // inner vzext is used in the input to the outer vzext.
27181 if (InnerEltVT.getSizeInBits() < InputBits)
27184 // In this case, the inner vzext is completely dead because we're going to
27185 // only look at bits inside of the low element. Just do the outer vzext on
27186 // a bitcast of the input to the inner.
27187 return DAG.getNode(X86ISD::VZEXT, DL, VT, DAG.getBitcast(OpVT, V));
27190 // Check if we can bypass extracting and re-inserting an element of an input
27191 // vector. Essentially:
27192 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
27193 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
27194 V.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
27195 V.getOperand(0).getSimpleValueType().getSizeInBits() == InputBits) {
27196 SDValue ExtractedV = V.getOperand(0);
27197 SDValue OrigV = ExtractedV.getOperand(0);
27198 if (isNullConstant(ExtractedV.getOperand(1))) {
27199 MVT OrigVT = OrigV.getSimpleValueType();
27200 // Extract a subvector if necessary...
27201 if (OrigVT.getSizeInBits() > OpVT.getSizeInBits()) {
27202 int Ratio = OrigVT.getSizeInBits() / OpVT.getSizeInBits();
27203 OrigVT = MVT::getVectorVT(OrigVT.getVectorElementType(),
27204 OrigVT.getVectorNumElements() / Ratio);
27205 OrigV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigVT, OrigV,
27206 DAG.getIntPtrConstant(0, DL));
27208 Op = DAG.getBitcast(OpVT, OrigV);
27209 return DAG.getNode(X86ISD::VZEXT, DL, VT, Op);
27216 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
27217 DAGCombinerInfo &DCI) const {
27218 SelectionDAG &DAG = DCI.DAG;
27219 switch (N->getOpcode()) {
27221 case ISD::EXTRACT_VECTOR_ELT:
27222 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
27225 case X86ISD::SHRUNKBLEND:
27226 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
27227 case ISD::BITCAST: return PerformBITCASTCombine(N, DAG, Subtarget);
27228 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
27229 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
27230 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
27231 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
27232 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
27235 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
27236 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
27237 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
27238 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
27239 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
27240 case ISD::MLOAD: return PerformMLOADCombine(N, DAG, DCI, Subtarget);
27241 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
27242 case ISD::MSTORE: return PerformMSTORECombine(N, DAG, Subtarget);
27243 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, Subtarget);
27244 case ISD::UINT_TO_FP: return PerformUINT_TO_FPCombine(N, DAG, Subtarget);
27245 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
27246 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
27247 case ISD::FNEG: return PerformFNEGCombine(N, DAG, Subtarget);
27248 case ISD::TRUNCATE: return PerformTRUNCATECombine(N, DAG, Subtarget);
27250 case X86ISD::FOR: return PerformFORCombine(N, DAG, Subtarget);
27252 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
27253 case X86ISD::FAND: return PerformFANDCombine(N, DAG, Subtarget);
27254 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG, Subtarget);
27255 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
27256 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
27257 case ISD::ANY_EXTEND:
27258 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
27259 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
27260 case ISD::SIGN_EXTEND_INREG:
27261 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
27262 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
27263 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
27264 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
27265 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
27266 case X86ISD::SHUFP: // Handle all target specific shuffles
27267 case X86ISD::PALIGNR:
27268 case X86ISD::UNPCKH:
27269 case X86ISD::UNPCKL:
27270 case X86ISD::MOVHLPS:
27271 case X86ISD::MOVLHPS:
27272 case X86ISD::PSHUFB:
27273 case X86ISD::PSHUFD:
27274 case X86ISD::PSHUFHW:
27275 case X86ISD::PSHUFLW:
27276 case X86ISD::MOVSS:
27277 case X86ISD::MOVSD:
27278 case X86ISD::VPERMILPI:
27279 case X86ISD::VPERM2X128:
27280 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
27281 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
27282 case X86ISD::BLENDI: return PerformBLENDICombine(N, DAG);
27288 /// isTypeDesirableForOp - Return true if the target has native support for
27289 /// the specified value type and it is 'desirable' to use the type for the
27290 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
27291 /// instruction encodings are longer and some i16 instructions are slow.
27292 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
27293 if (!isTypeLegal(VT))
27295 if (VT != MVT::i16)
27302 case ISD::SIGN_EXTEND:
27303 case ISD::ZERO_EXTEND:
27304 case ISD::ANY_EXTEND:
27317 /// IsDesirableToPromoteOp - This method query the target whether it is
27318 /// beneficial for dag combiner to promote the specified node. If true, it
27319 /// should return the desired promotion type by reference.
27320 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
27321 EVT VT = Op.getValueType();
27322 if (VT != MVT::i16)
27325 bool Promote = false;
27326 bool Commute = false;
27327 switch (Op.getOpcode()) {
27330 LoadSDNode *LD = cast<LoadSDNode>(Op);
27331 // If the non-extending load has a single use and it's not live out, then it
27332 // might be folded.
27333 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
27334 Op.hasOneUse()*/) {
27335 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
27336 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
27337 // The only case where we'd want to promote LOAD (rather then it being
27338 // promoted as an operand is when it's only use is liveout.
27339 if (UI->getOpcode() != ISD::CopyToReg)
27346 case ISD::SIGN_EXTEND:
27347 case ISD::ZERO_EXTEND:
27348 case ISD::ANY_EXTEND:
27353 SDValue N0 = Op.getOperand(0);
27354 // Look out for (store (shl (load), x)).
27355 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
27368 SDValue N0 = Op.getOperand(0);
27369 SDValue N1 = Op.getOperand(1);
27370 if (!Commute && MayFoldLoad(N1))
27372 // Avoid disabling potential load folding opportunities.
27373 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
27375 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
27385 //===----------------------------------------------------------------------===//
27386 // X86 Inline Assembly Support
27387 //===----------------------------------------------------------------------===//
27389 // Helper to match a string separated by whitespace.
27390 static bool matchAsm(StringRef S, ArrayRef<const char *> Pieces) {
27391 S = S.substr(S.find_first_not_of(" \t")); // Skip leading whitespace.
27393 for (StringRef Piece : Pieces) {
27394 if (!S.startswith(Piece)) // Check if the piece matches.
27397 S = S.substr(Piece.size());
27398 StringRef::size_type Pos = S.find_first_not_of(" \t");
27399 if (Pos == 0) // We matched a prefix.
27408 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
27410 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
27411 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
27412 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
27413 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
27415 if (AsmPieces.size() == 3)
27417 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
27424 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
27425 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
27427 std::string AsmStr = IA->getAsmString();
27429 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
27430 if (!Ty || Ty->getBitWidth() % 16 != 0)
27433 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
27434 SmallVector<StringRef, 4> AsmPieces;
27435 SplitString(AsmStr, AsmPieces, ";\n");
27437 switch (AsmPieces.size()) {
27438 default: return false;
27440 // FIXME: this should verify that we are targeting a 486 or better. If not,
27441 // we will turn this bswap into something that will be lowered to logical
27442 // ops instead of emitting the bswap asm. For now, we don't support 486 or
27443 // lower so don't worry about this.
27445 if (matchAsm(AsmPieces[0], {"bswap", "$0"}) ||
27446 matchAsm(AsmPieces[0], {"bswapl", "$0"}) ||
27447 matchAsm(AsmPieces[0], {"bswapq", "$0"}) ||
27448 matchAsm(AsmPieces[0], {"bswap", "${0:q}"}) ||
27449 matchAsm(AsmPieces[0], {"bswapl", "${0:q}"}) ||
27450 matchAsm(AsmPieces[0], {"bswapq", "${0:q}"})) {
27451 // No need to check constraints, nothing other than the equivalent of
27452 // "=r,0" would be valid here.
27453 return IntrinsicLowering::LowerToByteSwap(CI);
27456 // rorw $$8, ${0:w} --> llvm.bswap.i16
27457 if (CI->getType()->isIntegerTy(16) &&
27458 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
27459 (matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) ||
27460 matchAsm(AsmPieces[0], {"rolw", "$$8,", "${0:w}"}))) {
27462 StringRef ConstraintsStr = IA->getConstraintString();
27463 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
27464 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
27465 if (clobbersFlagRegisters(AsmPieces))
27466 return IntrinsicLowering::LowerToByteSwap(CI);
27470 if (CI->getType()->isIntegerTy(32) &&
27471 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
27472 matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) &&
27473 matchAsm(AsmPieces[1], {"rorl", "$$16,", "$0"}) &&
27474 matchAsm(AsmPieces[2], {"rorw", "$$8,", "${0:w}"})) {
27476 StringRef ConstraintsStr = IA->getConstraintString();
27477 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
27478 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
27479 if (clobbersFlagRegisters(AsmPieces))
27480 return IntrinsicLowering::LowerToByteSwap(CI);
27483 if (CI->getType()->isIntegerTy(64)) {
27484 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
27485 if (Constraints.size() >= 2 &&
27486 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
27487 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
27488 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
27489 if (matchAsm(AsmPieces[0], {"bswap", "%eax"}) &&
27490 matchAsm(AsmPieces[1], {"bswap", "%edx"}) &&
27491 matchAsm(AsmPieces[2], {"xchgl", "%eax,", "%edx"}))
27492 return IntrinsicLowering::LowerToByteSwap(CI);
27500 /// getConstraintType - Given a constraint letter, return the type of
27501 /// constraint it is for this target.
27502 X86TargetLowering::ConstraintType
27503 X86TargetLowering::getConstraintType(StringRef Constraint) const {
27504 if (Constraint.size() == 1) {
27505 switch (Constraint[0]) {
27516 return C_RegisterClass;
27540 return TargetLowering::getConstraintType(Constraint);
27543 /// Examine constraint type and operand type and determine a weight value.
27544 /// This object must already have been set up with the operand type
27545 /// and the current alternative constraint selected.
27546 TargetLowering::ConstraintWeight
27547 X86TargetLowering::getSingleConstraintMatchWeight(
27548 AsmOperandInfo &info, const char *constraint) const {
27549 ConstraintWeight weight = CW_Invalid;
27550 Value *CallOperandVal = info.CallOperandVal;
27551 // If we don't have a value, we can't do a match,
27552 // but allow it at the lowest weight.
27553 if (!CallOperandVal)
27555 Type *type = CallOperandVal->getType();
27556 // Look at the constraint type.
27557 switch (*constraint) {
27559 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
27570 if (CallOperandVal->getType()->isIntegerTy())
27571 weight = CW_SpecificReg;
27576 if (type->isFloatingPointTy())
27577 weight = CW_SpecificReg;
27580 if (type->isX86_MMXTy() && Subtarget->hasMMX())
27581 weight = CW_SpecificReg;
27585 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
27586 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
27587 weight = CW_Register;
27590 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
27591 if (C->getZExtValue() <= 31)
27592 weight = CW_Constant;
27596 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27597 if (C->getZExtValue() <= 63)
27598 weight = CW_Constant;
27602 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27603 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
27604 weight = CW_Constant;
27608 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27609 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
27610 weight = CW_Constant;
27614 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27615 if (C->getZExtValue() <= 3)
27616 weight = CW_Constant;
27620 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27621 if (C->getZExtValue() <= 0xff)
27622 weight = CW_Constant;
27627 if (isa<ConstantFP>(CallOperandVal)) {
27628 weight = CW_Constant;
27632 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27633 if ((C->getSExtValue() >= -0x80000000LL) &&
27634 (C->getSExtValue() <= 0x7fffffffLL))
27635 weight = CW_Constant;
27639 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27640 if (C->getZExtValue() <= 0xffffffff)
27641 weight = CW_Constant;
27648 /// LowerXConstraint - try to replace an X constraint, which matches anything,
27649 /// with another that has more specific requirements based on the type of the
27650 /// corresponding operand.
27651 const char *X86TargetLowering::
27652 LowerXConstraint(EVT ConstraintVT) const {
27653 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
27654 // 'f' like normal targets.
27655 if (ConstraintVT.isFloatingPoint()) {
27656 if (Subtarget->hasSSE2())
27658 if (Subtarget->hasSSE1())
27662 return TargetLowering::LowerXConstraint(ConstraintVT);
27665 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
27666 /// vector. If it is invalid, don't add anything to Ops.
27667 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
27668 std::string &Constraint,
27669 std::vector<SDValue>&Ops,
27670 SelectionDAG &DAG) const {
27673 // Only support length 1 constraints for now.
27674 if (Constraint.length() > 1) return;
27676 char ConstraintLetter = Constraint[0];
27677 switch (ConstraintLetter) {
27680 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27681 if (C->getZExtValue() <= 31) {
27682 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27683 Op.getValueType());
27689 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27690 if (C->getZExtValue() <= 63) {
27691 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27692 Op.getValueType());
27698 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27699 if (isInt<8>(C->getSExtValue())) {
27700 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27701 Op.getValueType());
27707 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27708 if (C->getZExtValue() == 0xff || C->getZExtValue() == 0xffff ||
27709 (Subtarget->is64Bit() && C->getZExtValue() == 0xffffffff)) {
27710 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
27711 Op.getValueType());
27717 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27718 if (C->getZExtValue() <= 3) {
27719 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27720 Op.getValueType());
27726 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27727 if (C->getZExtValue() <= 255) {
27728 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27729 Op.getValueType());
27735 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27736 if (C->getZExtValue() <= 127) {
27737 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27738 Op.getValueType());
27744 // 32-bit signed value
27745 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27746 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
27747 C->getSExtValue())) {
27748 // Widen to 64 bits here to get it sign extended.
27749 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op), MVT::i64);
27752 // FIXME gcc accepts some relocatable values here too, but only in certain
27753 // memory models; it's complicated.
27758 // 32-bit unsigned value
27759 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27760 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
27761 C->getZExtValue())) {
27762 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27763 Op.getValueType());
27767 // FIXME gcc accepts some relocatable values here too, but only in certain
27768 // memory models; it's complicated.
27772 // Literal immediates are always ok.
27773 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
27774 // Widen to 64 bits here to get it sign extended.
27775 Result = DAG.getTargetConstant(CST->getSExtValue(), SDLoc(Op), MVT::i64);
27779 // In any sort of PIC mode addresses need to be computed at runtime by
27780 // adding in a register or some sort of table lookup. These can't
27781 // be used as immediates.
27782 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
27785 // If we are in non-pic codegen mode, we allow the address of a global (with
27786 // an optional displacement) to be used with 'i'.
27787 GlobalAddressSDNode *GA = nullptr;
27788 int64_t Offset = 0;
27790 // Match either (GA), (GA+C), (GA+C1+C2), etc.
27792 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
27793 Offset += GA->getOffset();
27795 } else if (Op.getOpcode() == ISD::ADD) {
27796 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
27797 Offset += C->getZExtValue();
27798 Op = Op.getOperand(0);
27801 } else if (Op.getOpcode() == ISD::SUB) {
27802 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
27803 Offset += -C->getZExtValue();
27804 Op = Op.getOperand(0);
27809 // Otherwise, this isn't something we can handle, reject it.
27813 const GlobalValue *GV = GA->getGlobal();
27814 // If we require an extra load to get this address, as in PIC mode, we
27815 // can't accept it.
27816 if (isGlobalStubReference(
27817 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
27820 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
27821 GA->getValueType(0), Offset);
27826 if (Result.getNode()) {
27827 Ops.push_back(Result);
27830 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
27833 std::pair<unsigned, const TargetRegisterClass *>
27834 X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
27835 StringRef Constraint,
27837 // First, see if this is a constraint that directly corresponds to an LLVM
27839 if (Constraint.size() == 1) {
27840 // GCC Constraint Letters
27841 switch (Constraint[0]) {
27843 // TODO: Slight differences here in allocation order and leaving
27844 // RIP in the class. Do they matter any more here than they do
27845 // in the normal allocation?
27846 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
27847 if (Subtarget->is64Bit()) {
27848 if (VT == MVT::i32 || VT == MVT::f32)
27849 return std::make_pair(0U, &X86::GR32RegClass);
27850 if (VT == MVT::i16)
27851 return std::make_pair(0U, &X86::GR16RegClass);
27852 if (VT == MVT::i8 || VT == MVT::i1)
27853 return std::make_pair(0U, &X86::GR8RegClass);
27854 if (VT == MVT::i64 || VT == MVT::f64)
27855 return std::make_pair(0U, &X86::GR64RegClass);
27858 // 32-bit fallthrough
27859 case 'Q': // Q_REGS
27860 if (VT == MVT::i32 || VT == MVT::f32)
27861 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
27862 if (VT == MVT::i16)
27863 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
27864 if (VT == MVT::i8 || VT == MVT::i1)
27865 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
27866 if (VT == MVT::i64)
27867 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
27869 case 'r': // GENERAL_REGS
27870 case 'l': // INDEX_REGS
27871 if (VT == MVT::i8 || VT == MVT::i1)
27872 return std::make_pair(0U, &X86::GR8RegClass);
27873 if (VT == MVT::i16)
27874 return std::make_pair(0U, &X86::GR16RegClass);
27875 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
27876 return std::make_pair(0U, &X86::GR32RegClass);
27877 return std::make_pair(0U, &X86::GR64RegClass);
27878 case 'R': // LEGACY_REGS
27879 if (VT == MVT::i8 || VT == MVT::i1)
27880 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
27881 if (VT == MVT::i16)
27882 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
27883 if (VT == MVT::i32 || !Subtarget->is64Bit())
27884 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
27885 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
27886 case 'f': // FP Stack registers.
27887 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
27888 // value to the correct fpstack register class.
27889 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
27890 return std::make_pair(0U, &X86::RFP32RegClass);
27891 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
27892 return std::make_pair(0U, &X86::RFP64RegClass);
27893 return std::make_pair(0U, &X86::RFP80RegClass);
27894 case 'y': // MMX_REGS if MMX allowed.
27895 if (!Subtarget->hasMMX()) break;
27896 return std::make_pair(0U, &X86::VR64RegClass);
27897 case 'Y': // SSE_REGS if SSE2 allowed
27898 if (!Subtarget->hasSSE2()) break;
27900 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
27901 if (!Subtarget->hasSSE1()) break;
27903 switch (VT.SimpleTy) {
27905 // Scalar SSE types.
27908 return std::make_pair(0U, &X86::FR32RegClass);
27911 return std::make_pair(0U, &X86::FR64RegClass);
27919 return std::make_pair(0U, &X86::VR128RegClass);
27927 return std::make_pair(0U, &X86::VR256RegClass);
27932 return std::make_pair(0U, &X86::VR512RegClass);
27938 // Use the default implementation in TargetLowering to convert the register
27939 // constraint into a member of a register class.
27940 std::pair<unsigned, const TargetRegisterClass*> Res;
27941 Res = TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
27943 // Not found as a standard register?
27945 // Map st(0) -> st(7) -> ST0
27946 if (Constraint.size() == 7 && Constraint[0] == '{' &&
27947 tolower(Constraint[1]) == 's' &&
27948 tolower(Constraint[2]) == 't' &&
27949 Constraint[3] == '(' &&
27950 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
27951 Constraint[5] == ')' &&
27952 Constraint[6] == '}') {
27954 Res.first = X86::FP0+Constraint[4]-'0';
27955 Res.second = &X86::RFP80RegClass;
27959 // GCC allows "st(0)" to be called just plain "st".
27960 if (StringRef("{st}").equals_lower(Constraint)) {
27961 Res.first = X86::FP0;
27962 Res.second = &X86::RFP80RegClass;
27967 if (StringRef("{flags}").equals_lower(Constraint)) {
27968 Res.first = X86::EFLAGS;
27969 Res.second = &X86::CCRRegClass;
27973 // 'A' means EAX + EDX.
27974 if (Constraint == "A") {
27975 Res.first = X86::EAX;
27976 Res.second = &X86::GR32_ADRegClass;
27982 // Otherwise, check to see if this is a register class of the wrong value
27983 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
27984 // turn into {ax},{dx}.
27985 // MVT::Other is used to specify clobber names.
27986 if (Res.second->hasType(VT) || VT == MVT::Other)
27987 return Res; // Correct type already, nothing to do.
27989 // Get a matching integer of the correct size. i.e. "ax" with MVT::32 should
27990 // return "eax". This should even work for things like getting 64bit integer
27991 // registers when given an f64 type.
27992 const TargetRegisterClass *Class = Res.second;
27993 if (Class == &X86::GR8RegClass || Class == &X86::GR16RegClass ||
27994 Class == &X86::GR32RegClass || Class == &X86::GR64RegClass) {
27995 unsigned Size = VT.getSizeInBits();
27996 MVT::SimpleValueType SimpleTy = Size == 1 || Size == 8 ? MVT::i8
27997 : Size == 16 ? MVT::i16
27998 : Size == 32 ? MVT::i32
27999 : Size == 64 ? MVT::i64
28001 unsigned DestReg = getX86SubSuperRegisterOrZero(Res.first, SimpleTy);
28003 Res.first = DestReg;
28004 Res.second = SimpleTy == MVT::i8 ? &X86::GR8RegClass
28005 : SimpleTy == MVT::i16 ? &X86::GR16RegClass
28006 : SimpleTy == MVT::i32 ? &X86::GR32RegClass
28007 : &X86::GR64RegClass;
28008 assert(Res.second->contains(Res.first) && "Register in register class");
28010 // No register found/type mismatch.
28012 Res.second = nullptr;
28014 } else if (Class == &X86::FR32RegClass || Class == &X86::FR64RegClass ||
28015 Class == &X86::VR128RegClass || Class == &X86::VR256RegClass ||
28016 Class == &X86::FR32XRegClass || Class == &X86::FR64XRegClass ||
28017 Class == &X86::VR128XRegClass || Class == &X86::VR256XRegClass ||
28018 Class == &X86::VR512RegClass) {
28019 // Handle references to XMM physical registers that got mapped into the
28020 // wrong class. This can happen with constraints like {xmm0} where the
28021 // target independent register mapper will just pick the first match it can
28022 // find, ignoring the required type.
28024 if (VT == MVT::f32 || VT == MVT::i32)
28025 Res.second = &X86::FR32RegClass;
28026 else if (VT == MVT::f64 || VT == MVT::i64)
28027 Res.second = &X86::FR64RegClass;
28028 else if (X86::VR128RegClass.hasType(VT))
28029 Res.second = &X86::VR128RegClass;
28030 else if (X86::VR256RegClass.hasType(VT))
28031 Res.second = &X86::VR256RegClass;
28032 else if (X86::VR512RegClass.hasType(VT))
28033 Res.second = &X86::VR512RegClass;
28035 // Type mismatch and not a clobber: Return an error;
28037 Res.second = nullptr;
28044 int X86TargetLowering::getScalingFactorCost(const DataLayout &DL,
28045 const AddrMode &AM, Type *Ty,
28046 unsigned AS) const {
28047 // Scaling factors are not free at all.
28048 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
28049 // will take 2 allocations in the out of order engine instead of 1
28050 // for plain addressing mode, i.e. inst (reg1).
28052 // vaddps (%rsi,%drx), %ymm0, %ymm1
28053 // Requires two allocations (one for the load, one for the computation)
28055 // vaddps (%rsi), %ymm0, %ymm1
28056 // Requires just 1 allocation, i.e., freeing allocations for other operations
28057 // and having less micro operations to execute.
28059 // For some X86 architectures, this is even worse because for instance for
28060 // stores, the complex addressing mode forces the instruction to use the
28061 // "load" ports instead of the dedicated "store" port.
28062 // E.g., on Haswell:
28063 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
28064 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
28065 if (isLegalAddressingMode(DL, AM, Ty, AS))
28066 // Scale represents reg2 * scale, thus account for 1
28067 // as soon as we use a second register.
28068 return AM.Scale != 0;
28072 bool X86TargetLowering::isIntDivCheap(EVT VT, AttributeSet Attr) const {
28073 // Integer division on x86 is expensive. However, when aggressively optimizing
28074 // for code size, we prefer to use a div instruction, as it is usually smaller
28075 // than the alternative sequence.
28076 // The exception to this is vector division. Since x86 doesn't have vector
28077 // integer division, leaving the division as-is is a loss even in terms of
28078 // size, because it will have to be scalarized, while the alternative code
28079 // sequence can be performed in vector form.
28080 bool OptSize = Attr.hasAttribute(AttributeSet::FunctionIndex,
28081 Attribute::MinSize);
28082 return OptSize && !VT.isVector();
28085 void X86TargetLowering::markInRegArguments(SelectionDAG &DAG,
28086 TargetLowering::ArgListTy& Args) const {
28087 // The MCU psABI requires some arguments to be passed in-register.
28088 // For regular calls, the inreg arguments are marked by the front-end.
28089 // However, for compiler generated library calls, we have to patch this
28091 if (!Subtarget->isTargetMCU() || !Args.size())
28094 unsigned FreeRegs = 3;
28095 for (auto &Arg : Args) {
28096 // For library functions, we do not expect any fancy types.
28097 unsigned Size = DAG.getDataLayout().getTypeSizeInBits(Arg.Ty);
28098 unsigned SizeInRegs = (Size + 31) / 32;
28099 if (SizeInRegs > 2 || SizeInRegs > FreeRegs)
28102 Arg.isInReg = true;
28103 FreeRegs -= SizeInRegs;