1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
16 #include "X86ISelLowering.h"
18 #include "X86InstrBuilder.h"
19 #include "X86TargetMachine.h"
20 #include "X86TargetObjectFile.h"
21 #include "Utils/X86ShuffleDecode.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/GlobalAlias.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/Function.h"
28 #include "llvm/Instructions.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/LLVMContext.h"
31 #include "llvm/CodeGen/IntrinsicLowering.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineFunction.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineJumpTableInfo.h"
36 #include "llvm/CodeGen/MachineModuleInfo.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/MC/MCAsmInfo.h"
39 #include "llvm/MC/MCContext.h"
40 #include "llvm/MC/MCExpr.h"
41 #include "llvm/MC/MCSymbol.h"
42 #include "llvm/ADT/SmallSet.h"
43 #include "llvm/ADT/Statistic.h"
44 #include "llvm/ADT/StringExtras.h"
45 #include "llvm/ADT/VariadicFunction.h"
46 #include "llvm/Support/CallSite.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/MathExtras.h"
50 #include "llvm/Target/TargetOptions.h"
54 STATISTIC(NumTailCalls, "Number of tail calls");
56 // Forward declarations.
57 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
60 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
61 /// sets things up to match to an AVX VEXTRACTF128 instruction or a
62 /// simple subregister reference. Idx is an index in the 128 bits we
63 /// want. It need not be aligned to a 128-bit bounday. That makes
64 /// lowering EXTRACT_VECTOR_ELT operations easier.
65 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
66 SelectionDAG &DAG, DebugLoc dl) {
67 EVT VT = Vec.getValueType();
68 assert(VT.getSizeInBits() == 256 && "Unexpected vector size!");
69 EVT ElVT = VT.getVectorElementType();
70 unsigned Factor = VT.getSizeInBits()/128;
71 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
72 VT.getVectorNumElements()/Factor);
74 // Extract from UNDEF is UNDEF.
75 if (Vec.getOpcode() == ISD::UNDEF)
76 return DAG.getUNDEF(ResultVT);
78 // Extract the relevant 128 bits. Generate an EXTRACT_SUBVECTOR
79 // we can match to VEXTRACTF128.
80 unsigned ElemsPerChunk = 128 / ElVT.getSizeInBits();
82 // This is the index of the first element of the 128-bit chunk
84 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / 128)
87 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
88 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
94 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
95 /// sets things up to match to an AVX VINSERTF128 instruction or a
96 /// simple superregister reference. Idx is an index in the 128 bits
97 /// we want. It need not be aligned to a 128-bit bounday. That makes
98 /// lowering INSERT_VECTOR_ELT operations easier.
99 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
100 unsigned IdxVal, SelectionDAG &DAG,
102 // Inserting UNDEF is Result
103 if (Vec.getOpcode() == ISD::UNDEF)
106 EVT VT = Vec.getValueType();
107 assert(VT.getSizeInBits() == 128 && "Unexpected vector size!");
109 EVT ElVT = VT.getVectorElementType();
110 EVT ResultVT = Result.getValueType();
112 // Insert the relevant 128 bits.
113 unsigned ElemsPerChunk = 128/ElVT.getSizeInBits();
115 // This is the index of the first element of the 128-bit chunk
117 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/128)
120 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
121 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
125 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
126 /// instructions. This is used because creating CONCAT_VECTOR nodes of
127 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
128 /// large BUILD_VECTORS.
129 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
130 unsigned NumElems, SelectionDAG &DAG,
132 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
133 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
136 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
137 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
138 bool is64Bit = Subtarget->is64Bit();
140 if (Subtarget->isTargetEnvMacho()) {
142 return new X86_64MachoTargetObjectFile();
143 return new TargetLoweringObjectFileMachO();
146 if (Subtarget->isTargetLinux())
147 return new X86LinuxTargetObjectFile();
148 if (Subtarget->isTargetELF())
149 return new TargetLoweringObjectFileELF();
150 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
151 return new TargetLoweringObjectFileCOFF();
152 llvm_unreachable("unknown subtarget type");
155 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
156 : TargetLowering(TM, createTLOF(TM)) {
157 Subtarget = &TM.getSubtarget<X86Subtarget>();
158 X86ScalarSSEf64 = Subtarget->hasSSE2();
159 X86ScalarSSEf32 = Subtarget->hasSSE1();
160 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
162 RegInfo = TM.getRegisterInfo();
163 TD = getTargetData();
165 // Set up the TargetLowering object.
166 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
168 // X86 is weird, it always uses i8 for shift amounts and setcc results.
169 setBooleanContents(ZeroOrOneBooleanContent);
170 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
171 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
173 // For 64-bit since we have so many registers use the ILP scheduler, for
174 // 32-bit code use the register pressure specific scheduling.
175 // For Atom, always use ILP scheduling.
176 if (Subtarget->isAtom())
177 setSchedulingPreference(Sched::ILP);
178 else if (Subtarget->is64Bit())
179 setSchedulingPreference(Sched::ILP);
181 setSchedulingPreference(Sched::RegPressure);
182 setStackPointerRegisterToSaveRestore(X86StackPtr);
184 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) {
185 // Setup Windows compiler runtime calls.
186 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
187 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
188 setLibcallName(RTLIB::SREM_I64, "_allrem");
189 setLibcallName(RTLIB::UREM_I64, "_aullrem");
190 setLibcallName(RTLIB::MUL_I64, "_allmul");
191 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
192 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
193 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
194 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
195 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
197 // The _ftol2 runtime function has an unusual calling conv, which
198 // is modeled by a special pseudo-instruction.
199 setLibcallName(RTLIB::FPTOUINT_F64_I64, 0);
200 setLibcallName(RTLIB::FPTOUINT_F32_I64, 0);
201 setLibcallName(RTLIB::FPTOUINT_F64_I32, 0);
202 setLibcallName(RTLIB::FPTOUINT_F32_I32, 0);
205 if (Subtarget->isTargetDarwin()) {
206 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
207 setUseUnderscoreSetJmp(false);
208 setUseUnderscoreLongJmp(false);
209 } else if (Subtarget->isTargetMingw()) {
210 // MS runtime is weird: it exports _setjmp, but longjmp!
211 setUseUnderscoreSetJmp(true);
212 setUseUnderscoreLongJmp(false);
214 setUseUnderscoreSetJmp(true);
215 setUseUnderscoreLongJmp(true);
218 // Set up the register classes.
219 addRegisterClass(MVT::i8, &X86::GR8RegClass);
220 addRegisterClass(MVT::i16, &X86::GR16RegClass);
221 addRegisterClass(MVT::i32, &X86::GR32RegClass);
222 if (Subtarget->is64Bit())
223 addRegisterClass(MVT::i64, &X86::GR64RegClass);
225 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
227 // We don't accept any truncstore of integer registers.
228 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
229 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
230 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
231 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
232 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
233 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
235 // SETOEQ and SETUNE require checking two conditions.
236 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
237 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
238 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
239 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
240 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
241 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
243 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
245 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
246 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
247 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
249 if (Subtarget->is64Bit()) {
250 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
251 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
252 } else if (!TM.Options.UseSoftFloat) {
253 // We have an algorithm for SSE2->double, and we turn this into a
254 // 64-bit FILD followed by conditional FADD for other targets.
255 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
256 // We have an algorithm for SSE2, and we turn this into a 64-bit
257 // FILD for other targets.
258 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
261 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
263 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
264 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
266 if (!TM.Options.UseSoftFloat) {
267 // SSE has no i16 to fp conversion, only i32
268 if (X86ScalarSSEf32) {
269 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
270 // f32 and f64 cases are Legal, f80 case is not
271 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
273 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
274 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
277 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
278 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
281 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
282 // are Legal, f80 is custom lowered.
283 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
284 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
286 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
288 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
289 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
291 if (X86ScalarSSEf32) {
292 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
293 // f32 and f64 cases are Legal, f80 case is not
294 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
296 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
297 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
300 // Handle FP_TO_UINT by promoting the destination to a larger signed
302 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
303 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
304 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
306 if (Subtarget->is64Bit()) {
307 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
308 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
309 } else if (!TM.Options.UseSoftFloat) {
310 // Since AVX is a superset of SSE3, only check for SSE here.
311 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
312 // Expand FP_TO_UINT into a select.
313 // FIXME: We would like to use a Custom expander here eventually to do
314 // the optimal thing for SSE vs. the default expansion in the legalizer.
315 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
317 // With SSE3 we can use fisttpll to convert to a signed i64; without
318 // SSE, we're stuck with a fistpll.
319 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
322 if (isTargetFTOL()) {
323 // Use the _ftol2 runtime function, which has a pseudo-instruction
324 // to handle its weird calling convention.
325 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
328 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
329 if (!X86ScalarSSEf64) {
330 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
331 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
332 if (Subtarget->is64Bit()) {
333 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
334 // Without SSE, i64->f64 goes through memory.
335 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
339 // Scalar integer divide and remainder are lowered to use operations that
340 // produce two results, to match the available instructions. This exposes
341 // the two-result form to trivial CSE, which is able to combine x/y and x%y
342 // into a single instruction.
344 // Scalar integer multiply-high is also lowered to use two-result
345 // operations, to match the available instructions. However, plain multiply
346 // (low) operations are left as Legal, as there are single-result
347 // instructions for this in x86. Using the two-result multiply instructions
348 // when both high and low results are needed must be arranged by dagcombine.
349 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
351 setOperationAction(ISD::MULHS, VT, Expand);
352 setOperationAction(ISD::MULHU, VT, Expand);
353 setOperationAction(ISD::SDIV, VT, Expand);
354 setOperationAction(ISD::UDIV, VT, Expand);
355 setOperationAction(ISD::SREM, VT, Expand);
356 setOperationAction(ISD::UREM, VT, Expand);
358 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
359 setOperationAction(ISD::ADDC, VT, Custom);
360 setOperationAction(ISD::ADDE, VT, Custom);
361 setOperationAction(ISD::SUBC, VT, Custom);
362 setOperationAction(ISD::SUBE, VT, Custom);
365 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
366 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
367 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
368 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
369 if (Subtarget->is64Bit())
370 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
371 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
372 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
373 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
374 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
375 setOperationAction(ISD::FREM , MVT::f32 , Expand);
376 setOperationAction(ISD::FREM , MVT::f64 , Expand);
377 setOperationAction(ISD::FREM , MVT::f80 , Expand);
378 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
380 // Promote the i8 variants and force them on up to i32 which has a shorter
382 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
383 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
384 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
385 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
386 if (Subtarget->hasBMI()) {
387 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
388 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
389 if (Subtarget->is64Bit())
390 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
392 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
393 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
394 if (Subtarget->is64Bit())
395 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
398 if (Subtarget->hasLZCNT()) {
399 // When promoting the i8 variants, force them to i32 for a shorter
401 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
402 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
403 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
404 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
405 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
406 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
407 if (Subtarget->is64Bit())
408 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
410 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
411 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
412 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
413 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
414 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
415 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
416 if (Subtarget->is64Bit()) {
417 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
418 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
422 if (Subtarget->hasPOPCNT()) {
423 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
425 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
426 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
427 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
428 if (Subtarget->is64Bit())
429 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
432 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
433 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
435 // These should be promoted to a larger select which is supported.
436 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
437 // X86 wants to expand cmov itself.
438 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
439 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
440 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
441 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
442 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
443 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
444 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
445 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
446 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
447 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
448 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
449 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
450 if (Subtarget->is64Bit()) {
451 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
452 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
454 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
457 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
458 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
459 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
460 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
461 if (Subtarget->is64Bit())
462 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
463 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
464 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
465 if (Subtarget->is64Bit()) {
466 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
467 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
468 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
469 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
470 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
472 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
473 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
474 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
475 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
476 if (Subtarget->is64Bit()) {
477 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
478 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
479 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
482 if (Subtarget->hasSSE1())
483 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
485 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom);
486 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
488 // On X86 and X86-64, atomic operations are lowered to locked instructions.
489 // Locked instructions, in turn, have implicit fence semantics (all memory
490 // operations are flushed before issuing the locked instruction, and they
491 // are not buffered), so we can fold away the common pattern of
492 // fence-atomic-fence.
493 setShouldFoldAtomicFences(true);
495 // Expand certain atomics
496 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
498 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom);
499 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
500 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
503 if (!Subtarget->is64Bit()) {
504 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
505 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
506 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
507 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
508 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
509 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
510 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
511 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
514 if (Subtarget->hasCmpxchg16b()) {
515 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom);
518 // FIXME - use subtarget debug flags
519 if (!Subtarget->isTargetDarwin() &&
520 !Subtarget->isTargetELF() &&
521 !Subtarget->isTargetCygMing()) {
522 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
525 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
526 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
527 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
528 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
529 if (Subtarget->is64Bit()) {
530 setExceptionPointerRegister(X86::RAX);
531 setExceptionSelectorRegister(X86::RDX);
533 setExceptionPointerRegister(X86::EAX);
534 setExceptionSelectorRegister(X86::EDX);
536 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
537 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
539 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
540 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
542 setOperationAction(ISD::TRAP, MVT::Other, Legal);
544 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
545 setOperationAction(ISD::VASTART , MVT::Other, Custom);
546 setOperationAction(ISD::VAEND , MVT::Other, Expand);
547 if (Subtarget->is64Bit()) {
548 setOperationAction(ISD::VAARG , MVT::Other, Custom);
549 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
551 setOperationAction(ISD::VAARG , MVT::Other, Expand);
552 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
555 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
556 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
558 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
559 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
560 MVT::i64 : MVT::i32, Custom);
561 else if (TM.Options.EnableSegmentedStacks)
562 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
563 MVT::i64 : MVT::i32, Custom);
565 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
566 MVT::i64 : MVT::i32, Expand);
568 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
569 // f32 and f64 use SSE.
570 // Set up the FP register classes.
571 addRegisterClass(MVT::f32, &X86::FR32RegClass);
572 addRegisterClass(MVT::f64, &X86::FR64RegClass);
574 // Use ANDPD to simulate FABS.
575 setOperationAction(ISD::FABS , MVT::f64, Custom);
576 setOperationAction(ISD::FABS , MVT::f32, Custom);
578 // Use XORP to simulate FNEG.
579 setOperationAction(ISD::FNEG , MVT::f64, Custom);
580 setOperationAction(ISD::FNEG , MVT::f32, Custom);
582 // Use ANDPD and ORPD to simulate FCOPYSIGN.
583 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
584 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
586 // Lower this to FGETSIGNx86 plus an AND.
587 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
588 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
590 // We don't support sin/cos/fmod
591 setOperationAction(ISD::FSIN , MVT::f64, Expand);
592 setOperationAction(ISD::FCOS , MVT::f64, Expand);
593 setOperationAction(ISD::FSIN , MVT::f32, Expand);
594 setOperationAction(ISD::FCOS , MVT::f32, Expand);
596 // Expand FP immediates into loads from the stack, except for the special
598 addLegalFPImmediate(APFloat(+0.0)); // xorpd
599 addLegalFPImmediate(APFloat(+0.0f)); // xorps
600 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
601 // Use SSE for f32, x87 for f64.
602 // Set up the FP register classes.
603 addRegisterClass(MVT::f32, &X86::FR32RegClass);
604 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
606 // Use ANDPS to simulate FABS.
607 setOperationAction(ISD::FABS , MVT::f32, Custom);
609 // Use XORP to simulate FNEG.
610 setOperationAction(ISD::FNEG , MVT::f32, Custom);
612 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
614 // Use ANDPS and ORPS to simulate FCOPYSIGN.
615 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
616 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
618 // We don't support sin/cos/fmod
619 setOperationAction(ISD::FSIN , MVT::f32, Expand);
620 setOperationAction(ISD::FCOS , MVT::f32, Expand);
622 // Special cases we handle for FP constants.
623 addLegalFPImmediate(APFloat(+0.0f)); // xorps
624 addLegalFPImmediate(APFloat(+0.0)); // FLD0
625 addLegalFPImmediate(APFloat(+1.0)); // FLD1
626 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
627 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
629 if (!TM.Options.UnsafeFPMath) {
630 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
631 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
633 } else if (!TM.Options.UseSoftFloat) {
634 // f32 and f64 in x87.
635 // Set up the FP register classes.
636 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
637 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
639 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
640 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
641 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
642 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
644 if (!TM.Options.UnsafeFPMath) {
645 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
646 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
648 addLegalFPImmediate(APFloat(+0.0)); // FLD0
649 addLegalFPImmediate(APFloat(+1.0)); // FLD1
650 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
651 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
652 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
653 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
654 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
655 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
658 // We don't support FMA.
659 setOperationAction(ISD::FMA, MVT::f64, Expand);
660 setOperationAction(ISD::FMA, MVT::f32, Expand);
662 // Long double always uses X87.
663 if (!TM.Options.UseSoftFloat) {
664 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
665 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
666 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
668 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
669 addLegalFPImmediate(TmpFlt); // FLD0
671 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
674 APFloat TmpFlt2(+1.0);
675 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
677 addLegalFPImmediate(TmpFlt2); // FLD1
678 TmpFlt2.changeSign();
679 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
682 if (!TM.Options.UnsafeFPMath) {
683 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
684 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
687 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
688 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
689 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
690 setOperationAction(ISD::FRINT, MVT::f80, Expand);
691 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
692 setOperationAction(ISD::FMA, MVT::f80, Expand);
695 // Always use a library call for pow.
696 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
697 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
698 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
700 setOperationAction(ISD::FLOG, MVT::f80, Expand);
701 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
702 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
703 setOperationAction(ISD::FEXP, MVT::f80, Expand);
704 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
706 // First set operation action for all vector types to either promote
707 // (for widening) or expand (for scalarization). Then we will selectively
708 // turn on ones that can be effectively codegen'd.
709 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
710 VT <= MVT::LAST_VECTOR_VALUETYPE; ++VT) {
711 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
712 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
713 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
714 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
715 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
716 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
717 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
718 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
719 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
720 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
721 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
722 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
723 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
724 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
725 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
726 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
727 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
728 setOperationAction(ISD::INSERT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
729 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
730 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
731 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
732 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
733 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
734 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
735 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
736 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
737 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
738 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
739 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
740 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
741 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
742 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
743 setOperationAction(ISD::CTTZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand);
744 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
745 setOperationAction(ISD::CTLZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand);
746 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
747 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
748 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
749 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
750 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
751 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
752 setOperationAction(ISD::SETCC, (MVT::SimpleValueType)VT, Expand);
753 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
754 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
755 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
756 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
757 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
758 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand);
759 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand);
760 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
761 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
762 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand);
763 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand);
764 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand);
765 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand);
766 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand);
767 setOperationAction(ISD::VSELECT, (MVT::SimpleValueType)VT, Expand);
768 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
769 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
770 setTruncStoreAction((MVT::SimpleValueType)VT,
771 (MVT::SimpleValueType)InnerVT, Expand);
772 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
773 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
774 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
777 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
778 // with -msoft-float, disable use of MMX as well.
779 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
780 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
781 // No operations on x86mmx supported, everything uses intrinsics.
784 // MMX-sized vectors (other than x86mmx) are expected to be expanded
785 // into smaller operations.
786 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
787 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
788 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
789 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
790 setOperationAction(ISD::AND, MVT::v8i8, Expand);
791 setOperationAction(ISD::AND, MVT::v4i16, Expand);
792 setOperationAction(ISD::AND, MVT::v2i32, Expand);
793 setOperationAction(ISD::AND, MVT::v1i64, Expand);
794 setOperationAction(ISD::OR, MVT::v8i8, Expand);
795 setOperationAction(ISD::OR, MVT::v4i16, Expand);
796 setOperationAction(ISD::OR, MVT::v2i32, Expand);
797 setOperationAction(ISD::OR, MVT::v1i64, Expand);
798 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
799 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
800 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
801 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
802 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
803 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
804 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
805 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
806 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
807 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
808 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
809 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
810 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
811 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
812 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
813 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
814 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
816 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
817 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
819 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
820 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
821 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
822 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
823 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
824 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
825 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
826 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
827 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
828 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
829 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
830 setOperationAction(ISD::SETCC, MVT::v4f32, Custom);
833 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
834 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
836 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
837 // registers cannot be used even for integer operations.
838 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
839 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
840 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
841 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
843 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
844 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
845 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
846 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
847 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
848 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
849 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
850 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
851 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
852 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
853 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
854 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
855 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
856 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
857 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
858 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
860 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
861 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
862 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
863 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
865 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
866 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
867 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
868 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
869 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
871 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom);
872 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom);
873 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom);
874 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom);
875 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
877 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
878 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
879 EVT VT = (MVT::SimpleValueType)i;
880 // Do not attempt to custom lower non-power-of-2 vectors
881 if (!isPowerOf2_32(VT.getVectorNumElements()))
883 // Do not attempt to custom lower non-128-bit vectors
884 if (!VT.is128BitVector())
886 setOperationAction(ISD::BUILD_VECTOR,
887 VT.getSimpleVT().SimpleTy, Custom);
888 setOperationAction(ISD::VECTOR_SHUFFLE,
889 VT.getSimpleVT().SimpleTy, Custom);
890 setOperationAction(ISD::EXTRACT_VECTOR_ELT,
891 VT.getSimpleVT().SimpleTy, Custom);
894 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
895 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
896 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
897 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
898 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
899 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
901 if (Subtarget->is64Bit()) {
902 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
903 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
906 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
907 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
908 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
911 // Do not attempt to promote non-128-bit vectors
912 if (!VT.is128BitVector())
915 setOperationAction(ISD::AND, SVT, Promote);
916 AddPromotedToType (ISD::AND, SVT, MVT::v2i64);
917 setOperationAction(ISD::OR, SVT, Promote);
918 AddPromotedToType (ISD::OR, SVT, MVT::v2i64);
919 setOperationAction(ISD::XOR, SVT, Promote);
920 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64);
921 setOperationAction(ISD::LOAD, SVT, Promote);
922 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64);
923 setOperationAction(ISD::SELECT, SVT, Promote);
924 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64);
927 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
929 // Custom lower v2i64 and v2f64 selects.
930 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
931 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
932 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
933 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
935 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
936 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
939 if (Subtarget->hasSSE41()) {
940 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
941 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
942 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
943 setOperationAction(ISD::FRINT, MVT::f32, Legal);
944 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
945 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
946 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
947 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
948 setOperationAction(ISD::FRINT, MVT::f64, Legal);
949 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
951 // FIXME: Do we need to handle scalar-to-vector here?
952 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
954 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
955 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal);
956 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
957 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
958 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
960 // i8 and i16 vectors are custom , because the source register and source
961 // source memory operand types are not the same width. f32 vectors are
962 // custom since the immediate controlling the insert encodes additional
964 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
965 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
966 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
967 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
969 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
970 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
971 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
972 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
974 // FIXME: these should be Legal but thats only for the case where
975 // the index is constant. For now custom expand to deal with that.
976 if (Subtarget->is64Bit()) {
977 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
978 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
982 if (Subtarget->hasSSE2()) {
983 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
984 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
986 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
987 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
989 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
990 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
992 if (Subtarget->hasAVX2()) {
993 setOperationAction(ISD::SRL, MVT::v2i64, Legal);
994 setOperationAction(ISD::SRL, MVT::v4i32, Legal);
996 setOperationAction(ISD::SHL, MVT::v2i64, Legal);
997 setOperationAction(ISD::SHL, MVT::v4i32, Legal);
999 setOperationAction(ISD::SRA, MVT::v4i32, Legal);
1001 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1002 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1004 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1005 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1007 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1011 if (Subtarget->hasSSE42())
1012 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
1014 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX()) {
1015 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1016 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1017 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1018 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1019 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1020 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1022 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1023 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1024 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1026 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1027 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1028 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1029 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1030 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1031 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1033 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1034 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1035 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1036 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1037 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1038 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1040 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1041 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1042 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1044 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f64, Custom);
1045 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i64, Custom);
1046 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom);
1047 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom);
1048 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i8, Custom);
1049 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i16, Custom);
1051 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1052 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1054 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1055 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1057 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1058 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1060 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1061 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1062 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1063 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1065 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1066 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1067 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1069 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal);
1070 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal);
1071 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal);
1072 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal);
1074 if (Subtarget->hasAVX2()) {
1075 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1076 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1077 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1078 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1080 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1081 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1082 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1083 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1085 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1086 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1087 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1088 // Don't lower v32i8 because there is no 128-bit byte mul
1090 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1092 setOperationAction(ISD::SRL, MVT::v4i64, Legal);
1093 setOperationAction(ISD::SRL, MVT::v8i32, Legal);
1095 setOperationAction(ISD::SHL, MVT::v4i64, Legal);
1096 setOperationAction(ISD::SHL, MVT::v8i32, Legal);
1098 setOperationAction(ISD::SRA, MVT::v8i32, Legal);
1100 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1101 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1102 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1103 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1105 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1106 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1107 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1108 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1110 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1111 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1112 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1113 // Don't lower v32i8 because there is no 128-bit byte mul
1115 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1116 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1118 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1119 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1121 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1124 // Custom lower several nodes for 256-bit types.
1125 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1126 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1127 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
1130 // Extract subvector is special because the value type
1131 // (result) is 128-bit but the source is 256-bit wide.
1132 if (VT.is128BitVector())
1133 setOperationAction(ISD::EXTRACT_SUBVECTOR, SVT, Custom);
1135 // Do not attempt to custom lower other non-256-bit vectors
1136 if (!VT.is256BitVector())
1139 setOperationAction(ISD::BUILD_VECTOR, SVT, Custom);
1140 setOperationAction(ISD::VECTOR_SHUFFLE, SVT, Custom);
1141 setOperationAction(ISD::INSERT_VECTOR_ELT, SVT, Custom);
1142 setOperationAction(ISD::EXTRACT_VECTOR_ELT, SVT, Custom);
1143 setOperationAction(ISD::SCALAR_TO_VECTOR, SVT, Custom);
1144 setOperationAction(ISD::INSERT_SUBVECTOR, SVT, Custom);
1147 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1148 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1149 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
1152 // Do not attempt to promote non-256-bit vectors
1153 if (!VT.is256BitVector())
1156 setOperationAction(ISD::AND, SVT, Promote);
1157 AddPromotedToType (ISD::AND, SVT, MVT::v4i64);
1158 setOperationAction(ISD::OR, SVT, Promote);
1159 AddPromotedToType (ISD::OR, SVT, MVT::v4i64);
1160 setOperationAction(ISD::XOR, SVT, Promote);
1161 AddPromotedToType (ISD::XOR, SVT, MVT::v4i64);
1162 setOperationAction(ISD::LOAD, SVT, Promote);
1163 AddPromotedToType (ISD::LOAD, SVT, MVT::v4i64);
1164 setOperationAction(ISD::SELECT, SVT, Promote);
1165 AddPromotedToType (ISD::SELECT, SVT, MVT::v4i64);
1169 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1170 // of this type with custom code.
1171 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1172 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1173 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1177 // We want to custom lower some of our intrinsics.
1178 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1181 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1182 // handle type legalization for these operations here.
1184 // FIXME: We really should do custom legalization for addition and
1185 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1186 // than generic legalization for 64-bit multiplication-with-overflow, though.
1187 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1188 // Add/Sub/Mul with overflow operations are custom lowered.
1190 setOperationAction(ISD::SADDO, VT, Custom);
1191 setOperationAction(ISD::UADDO, VT, Custom);
1192 setOperationAction(ISD::SSUBO, VT, Custom);
1193 setOperationAction(ISD::USUBO, VT, Custom);
1194 setOperationAction(ISD::SMULO, VT, Custom);
1195 setOperationAction(ISD::UMULO, VT, Custom);
1198 // There are no 8-bit 3-address imul/mul instructions
1199 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1200 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1202 if (!Subtarget->is64Bit()) {
1203 // These libcalls are not available in 32-bit.
1204 setLibcallName(RTLIB::SHL_I128, 0);
1205 setLibcallName(RTLIB::SRL_I128, 0);
1206 setLibcallName(RTLIB::SRA_I128, 0);
1209 // We have target-specific dag combine patterns for the following nodes:
1210 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1211 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1212 setTargetDAGCombine(ISD::VSELECT);
1213 setTargetDAGCombine(ISD::SELECT);
1214 setTargetDAGCombine(ISD::SHL);
1215 setTargetDAGCombine(ISD::SRA);
1216 setTargetDAGCombine(ISD::SRL);
1217 setTargetDAGCombine(ISD::OR);
1218 setTargetDAGCombine(ISD::AND);
1219 setTargetDAGCombine(ISD::ADD);
1220 setTargetDAGCombine(ISD::FADD);
1221 setTargetDAGCombine(ISD::FSUB);
1222 setTargetDAGCombine(ISD::SUB);
1223 setTargetDAGCombine(ISD::LOAD);
1224 setTargetDAGCombine(ISD::STORE);
1225 setTargetDAGCombine(ISD::ZERO_EXTEND);
1226 setTargetDAGCombine(ISD::ANY_EXTEND);
1227 setTargetDAGCombine(ISD::SIGN_EXTEND);
1228 setTargetDAGCombine(ISD::TRUNCATE);
1229 setTargetDAGCombine(ISD::UINT_TO_FP);
1230 setTargetDAGCombine(ISD::SINT_TO_FP);
1231 setTargetDAGCombine(ISD::SETCC);
1232 setTargetDAGCombine(ISD::FP_TO_SINT);
1233 if (Subtarget->is64Bit())
1234 setTargetDAGCombine(ISD::MUL);
1235 setTargetDAGCombine(ISD::XOR);
1237 computeRegisterProperties();
1239 // On Darwin, -Os means optimize for size without hurting performance,
1240 // do not reduce the limit.
1241 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1242 maxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1243 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1244 maxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1245 maxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1246 maxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1247 setPrefLoopAlignment(4); // 2^4 bytes.
1248 benefitFromCodePlacementOpt = true;
1250 // Predictable cmov don't hurt on atom because it's in-order.
1251 predictableSelectIsExpensive = !Subtarget->isAtom();
1253 setPrefFunctionAlignment(4); // 2^4 bytes.
1257 EVT X86TargetLowering::getSetCCResultType(EVT VT) const {
1258 if (!VT.isVector()) return MVT::i8;
1259 return VT.changeVectorElementTypeToInteger();
1263 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1264 /// the desired ByVal argument alignment.
1265 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1268 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1269 if (VTy->getBitWidth() == 128)
1271 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1272 unsigned EltAlign = 0;
1273 getMaxByValAlign(ATy->getElementType(), EltAlign);
1274 if (EltAlign > MaxAlign)
1275 MaxAlign = EltAlign;
1276 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1277 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1278 unsigned EltAlign = 0;
1279 getMaxByValAlign(STy->getElementType(i), EltAlign);
1280 if (EltAlign > MaxAlign)
1281 MaxAlign = EltAlign;
1288 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1289 /// function arguments in the caller parameter area. For X86, aggregates
1290 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1291 /// are at 4-byte boundaries.
1292 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1293 if (Subtarget->is64Bit()) {
1294 // Max of 8 and alignment of type.
1295 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1302 if (Subtarget->hasSSE1())
1303 getMaxByValAlign(Ty, Align);
1307 /// getOptimalMemOpType - Returns the target specific optimal type for load
1308 /// and store operations as a result of memset, memcpy, and memmove
1309 /// lowering. If DstAlign is zero that means it's safe to destination
1310 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1311 /// means there isn't a need to check it against alignment requirement,
1312 /// probably because the source does not need to be loaded. If
1313 /// 'IsZeroVal' is true, that means it's safe to return a
1314 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
1315 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
1316 /// constant so it does not need to be loaded.
1317 /// It returns EVT::Other if the type should be determined using generic
1318 /// target-independent logic.
1320 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1321 unsigned DstAlign, unsigned SrcAlign,
1324 MachineFunction &MF) const {
1325 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
1326 // linux. This is because the stack realignment code can't handle certain
1327 // cases like PR2962. This should be removed when PR2962 is fixed.
1328 const Function *F = MF.getFunction();
1330 !F->hasFnAttr(Attribute::NoImplicitFloat)) {
1332 (Subtarget->isUnalignedMemAccessFast() ||
1333 ((DstAlign == 0 || DstAlign >= 16) &&
1334 (SrcAlign == 0 || SrcAlign >= 16))) &&
1335 Subtarget->getStackAlignment() >= 16) {
1336 if (Subtarget->getStackAlignment() >= 32) {
1337 if (Subtarget->hasAVX2())
1339 if (Subtarget->hasAVX())
1342 if (Subtarget->hasSSE2())
1344 if (Subtarget->hasSSE1())
1346 } else if (!MemcpyStrSrc && Size >= 8 &&
1347 !Subtarget->is64Bit() &&
1348 Subtarget->getStackAlignment() >= 8 &&
1349 Subtarget->hasSSE2()) {
1350 // Do not use f64 to lower memcpy if source is string constant. It's
1351 // better to use i32 to avoid the loads.
1355 if (Subtarget->is64Bit() && Size >= 8)
1360 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1361 /// current function. The returned value is a member of the
1362 /// MachineJumpTableInfo::JTEntryKind enum.
1363 unsigned X86TargetLowering::getJumpTableEncoding() const {
1364 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1366 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1367 Subtarget->isPICStyleGOT())
1368 return MachineJumpTableInfo::EK_Custom32;
1370 // Otherwise, use the normal jump table encoding heuristics.
1371 return TargetLowering::getJumpTableEncoding();
1375 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1376 const MachineBasicBlock *MBB,
1377 unsigned uid,MCContext &Ctx) const{
1378 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1379 Subtarget->isPICStyleGOT());
1380 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1382 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1383 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1386 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1388 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1389 SelectionDAG &DAG) const {
1390 if (!Subtarget->is64Bit())
1391 // This doesn't have DebugLoc associated with it, but is not really the
1392 // same as a Register.
1393 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy());
1397 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1398 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1400 const MCExpr *X86TargetLowering::
1401 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1402 MCContext &Ctx) const {
1403 // X86-64 uses RIP relative addressing based on the jump table label.
1404 if (Subtarget->isPICStyleRIPRel())
1405 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1407 // Otherwise, the reference is relative to the PIC base.
1408 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1411 // FIXME: Why this routine is here? Move to RegInfo!
1412 std::pair<const TargetRegisterClass*, uint8_t>
1413 X86TargetLowering::findRepresentativeClass(EVT VT) const{
1414 const TargetRegisterClass *RRC = 0;
1416 switch (VT.getSimpleVT().SimpleTy) {
1418 return TargetLowering::findRepresentativeClass(VT);
1419 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1420 RRC = Subtarget->is64Bit() ?
1421 (const TargetRegisterClass*)&X86::GR64RegClass :
1422 (const TargetRegisterClass*)&X86::GR32RegClass;
1425 RRC = &X86::VR64RegClass;
1427 case MVT::f32: case MVT::f64:
1428 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1429 case MVT::v4f32: case MVT::v2f64:
1430 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1432 RRC = &X86::VR128RegClass;
1435 return std::make_pair(RRC, Cost);
1438 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1439 unsigned &Offset) const {
1440 if (!Subtarget->isTargetLinux())
1443 if (Subtarget->is64Bit()) {
1444 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1446 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1459 //===----------------------------------------------------------------------===//
1460 // Return Value Calling Convention Implementation
1461 //===----------------------------------------------------------------------===//
1463 #include "X86GenCallingConv.inc"
1466 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1467 MachineFunction &MF, bool isVarArg,
1468 const SmallVectorImpl<ISD::OutputArg> &Outs,
1469 LLVMContext &Context) const {
1470 SmallVector<CCValAssign, 16> RVLocs;
1471 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1473 return CCInfo.CheckReturn(Outs, RetCC_X86);
1477 X86TargetLowering::LowerReturn(SDValue Chain,
1478 CallingConv::ID CallConv, bool isVarArg,
1479 const SmallVectorImpl<ISD::OutputArg> &Outs,
1480 const SmallVectorImpl<SDValue> &OutVals,
1481 DebugLoc dl, SelectionDAG &DAG) const {
1482 MachineFunction &MF = DAG.getMachineFunction();
1483 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1485 SmallVector<CCValAssign, 16> RVLocs;
1486 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1487 RVLocs, *DAG.getContext());
1488 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1490 // Add the regs to the liveout set for the function.
1491 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1492 for (unsigned i = 0; i != RVLocs.size(); ++i)
1493 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg()))
1494 MRI.addLiveOut(RVLocs[i].getLocReg());
1498 SmallVector<SDValue, 6> RetOps;
1499 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1500 // Operand #1 = Bytes To Pop
1501 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1504 // Copy the result values into the output registers.
1505 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1506 CCValAssign &VA = RVLocs[i];
1507 assert(VA.isRegLoc() && "Can only return in registers!");
1508 SDValue ValToCopy = OutVals[i];
1509 EVT ValVT = ValToCopy.getValueType();
1511 // Promote values to the appropriate types
1512 if (VA.getLocInfo() == CCValAssign::SExt)
1513 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
1514 else if (VA.getLocInfo() == CCValAssign::ZExt)
1515 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
1516 else if (VA.getLocInfo() == CCValAssign::AExt)
1517 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
1518 else if (VA.getLocInfo() == CCValAssign::BCvt)
1519 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
1521 // If this is x86-64, and we disabled SSE, we can't return FP values,
1522 // or SSE or MMX vectors.
1523 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1524 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1525 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1526 report_fatal_error("SSE register return with SSE disabled");
1528 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1529 // llvm-gcc has never done it right and no one has noticed, so this
1530 // should be OK for now.
1531 if (ValVT == MVT::f64 &&
1532 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1533 report_fatal_error("SSE2 register return with SSE2 disabled");
1535 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1536 // the RET instruction and handled by the FP Stackifier.
1537 if (VA.getLocReg() == X86::ST0 ||
1538 VA.getLocReg() == X86::ST1) {
1539 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1540 // change the value to the FP stack register class.
1541 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1542 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1543 RetOps.push_back(ValToCopy);
1544 // Don't emit a copytoreg.
1548 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1549 // which is returned in RAX / RDX.
1550 if (Subtarget->is64Bit()) {
1551 if (ValVT == MVT::x86mmx) {
1552 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1553 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1554 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1556 // If we don't have SSE2 available, convert to v4f32 so the generated
1557 // register is legal.
1558 if (!Subtarget->hasSSE2())
1559 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1564 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1565 Flag = Chain.getValue(1);
1568 // The x86-64 ABI for returning structs by value requires that we copy
1569 // the sret argument into %rax for the return. We saved the argument into
1570 // a virtual register in the entry block, so now we copy the value out
1572 if (Subtarget->is64Bit() &&
1573 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1574 MachineFunction &MF = DAG.getMachineFunction();
1575 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1576 unsigned Reg = FuncInfo->getSRetReturnReg();
1578 "SRetReturnReg should have been set in LowerFormalArguments().");
1579 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1581 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
1582 Flag = Chain.getValue(1);
1584 // RAX now acts like a return value.
1585 MRI.addLiveOut(X86::RAX);
1588 RetOps[0] = Chain; // Update chain.
1590 // Add the flag if we have it.
1592 RetOps.push_back(Flag);
1594 return DAG.getNode(X86ISD::RET_FLAG, dl,
1595 MVT::Other, &RetOps[0], RetOps.size());
1598 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
1599 if (N->getNumValues() != 1)
1601 if (!N->hasNUsesOfValue(1, 0))
1604 SDValue TCChain = Chain;
1605 SDNode *Copy = *N->use_begin();
1606 if (Copy->getOpcode() == ISD::CopyToReg) {
1607 // If the copy has a glue operand, we conservatively assume it isn't safe to
1608 // perform a tail call.
1609 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
1611 TCChain = Copy->getOperand(0);
1612 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
1615 bool HasRet = false;
1616 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1618 if (UI->getOpcode() != X86ISD::RET_FLAG)
1631 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
1632 ISD::NodeType ExtendKind) const {
1634 // TODO: Is this also valid on 32-bit?
1635 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
1636 ReturnMVT = MVT::i8;
1638 ReturnMVT = MVT::i32;
1640 EVT MinVT = getRegisterType(Context, ReturnMVT);
1641 return VT.bitsLT(MinVT) ? MinVT : VT;
1644 /// LowerCallResult - Lower the result values of a call into the
1645 /// appropriate copies out of appropriate physical registers.
1648 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1649 CallingConv::ID CallConv, bool isVarArg,
1650 const SmallVectorImpl<ISD::InputArg> &Ins,
1651 DebugLoc dl, SelectionDAG &DAG,
1652 SmallVectorImpl<SDValue> &InVals) const {
1654 // Assign locations to each value returned by this call.
1655 SmallVector<CCValAssign, 16> RVLocs;
1656 bool Is64Bit = Subtarget->is64Bit();
1657 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1658 getTargetMachine(), RVLocs, *DAG.getContext());
1659 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1661 // Copy all of the result registers out of their specified physreg.
1662 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1663 CCValAssign &VA = RVLocs[i];
1664 EVT CopyVT = VA.getValVT();
1666 // If this is x86-64, and we disabled SSE, we can't return FP values
1667 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1668 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
1669 report_fatal_error("SSE register return with SSE disabled");
1674 // If this is a call to a function that returns an fp value on the floating
1675 // point stack, we must guarantee the the value is popped from the stack, so
1676 // a CopyFromReg is not good enough - the copy instruction may be eliminated
1677 // if the return value is not used. We use the FpPOP_RETVAL instruction
1679 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
1680 // If we prefer to use the value in xmm registers, copy it out as f80 and
1681 // use a truncate to move it from fp stack reg to xmm reg.
1682 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
1683 SDValue Ops[] = { Chain, InFlag };
1684 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT,
1685 MVT::Other, MVT::Glue, Ops, 2), 1);
1686 Val = Chain.getValue(0);
1688 // Round the f80 to the right size, which also moves it to the appropriate
1690 if (CopyVT != VA.getValVT())
1691 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1692 // This truncation won't change the value.
1693 DAG.getIntPtrConstant(1));
1695 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1696 CopyVT, InFlag).getValue(1);
1697 Val = Chain.getValue(0);
1699 InFlag = Chain.getValue(2);
1700 InVals.push_back(Val);
1707 //===----------------------------------------------------------------------===//
1708 // C & StdCall & Fast Calling Convention implementation
1709 //===----------------------------------------------------------------------===//
1710 // StdCall calling convention seems to be standard for many Windows' API
1711 // routines and around. It differs from C calling convention just a little:
1712 // callee should clean up the stack, not caller. Symbols should be also
1713 // decorated in some fancy way :) It doesn't support any vector arguments.
1714 // For info on fast calling convention see Fast Calling Convention (tail call)
1715 // implementation LowerX86_32FastCCCallTo.
1717 /// CallIsStructReturn - Determines whether a call uses struct return
1719 static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1723 return Outs[0].Flags.isSRet();
1726 /// ArgsAreStructReturn - Determines whether a function uses struct
1727 /// return semantics.
1729 ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
1733 return Ins[0].Flags.isSRet();
1736 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1737 /// by "Src" to address "Dst" with size and alignment information specified by
1738 /// the specific parameter attribute. The copy will be passed as a byval
1739 /// function parameter.
1741 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1742 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1744 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1746 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1747 /*isVolatile*/false, /*AlwaysInline=*/true,
1748 MachinePointerInfo(), MachinePointerInfo());
1751 /// IsTailCallConvention - Return true if the calling convention is one that
1752 /// supports tail call optimization.
1753 static bool IsTailCallConvention(CallingConv::ID CC) {
1754 return (CC == CallingConv::Fast || CC == CallingConv::GHC);
1757 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
1758 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
1762 CallingConv::ID CalleeCC = CS.getCallingConv();
1763 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C)
1769 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
1770 /// a tailcall target by changing its ABI.
1771 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
1772 bool GuaranteedTailCallOpt) {
1773 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
1777 X86TargetLowering::LowerMemArgument(SDValue Chain,
1778 CallingConv::ID CallConv,
1779 const SmallVectorImpl<ISD::InputArg> &Ins,
1780 DebugLoc dl, SelectionDAG &DAG,
1781 const CCValAssign &VA,
1782 MachineFrameInfo *MFI,
1784 // Create the nodes corresponding to a load from this parameter slot.
1785 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1786 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv,
1787 getTargetMachine().Options.GuaranteedTailCallOpt);
1788 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1791 // If value is passed by pointer we have address passed instead of the value
1793 if (VA.getLocInfo() == CCValAssign::Indirect)
1794 ValVT = VA.getLocVT();
1796 ValVT = VA.getValVT();
1798 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1799 // changed with more analysis.
1800 // In case of tail call optimization mark all arguments mutable. Since they
1801 // could be overwritten by lowering of arguments in case of a tail call.
1802 if (Flags.isByVal()) {
1803 unsigned Bytes = Flags.getByValSize();
1804 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
1805 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
1806 return DAG.getFrameIndex(FI, getPointerTy());
1808 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
1809 VA.getLocMemOffset(), isImmutable);
1810 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1811 return DAG.getLoad(ValVT, dl, Chain, FIN,
1812 MachinePointerInfo::getFixedStack(FI),
1813 false, false, false, 0);
1818 X86TargetLowering::LowerFormalArguments(SDValue Chain,
1819 CallingConv::ID CallConv,
1821 const SmallVectorImpl<ISD::InputArg> &Ins,
1824 SmallVectorImpl<SDValue> &InVals)
1826 MachineFunction &MF = DAG.getMachineFunction();
1827 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1829 const Function* Fn = MF.getFunction();
1830 if (Fn->hasExternalLinkage() &&
1831 Subtarget->isTargetCygMing() &&
1832 Fn->getName() == "main")
1833 FuncInfo->setForceFramePointer(true);
1835 MachineFrameInfo *MFI = MF.getFrameInfo();
1836 bool Is64Bit = Subtarget->is64Bit();
1837 bool IsWindows = Subtarget->isTargetWindows();
1838 bool IsWin64 = Subtarget->isTargetWin64();
1840 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1841 "Var args not supported with calling convention fastcc or ghc");
1843 // Assign locations to all of the incoming arguments.
1844 SmallVector<CCValAssign, 16> ArgLocs;
1845 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1846 ArgLocs, *DAG.getContext());
1848 // Allocate shadow area for Win64
1850 CCInfo.AllocateStack(32, 8);
1853 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
1855 unsigned LastVal = ~0U;
1857 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1858 CCValAssign &VA = ArgLocs[i];
1859 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1861 assert(VA.getValNo() != LastVal &&
1862 "Don't support value assigned to multiple locs yet");
1864 LastVal = VA.getValNo();
1866 if (VA.isRegLoc()) {
1867 EVT RegVT = VA.getLocVT();
1868 const TargetRegisterClass *RC;
1869 if (RegVT == MVT::i32)
1870 RC = &X86::GR32RegClass;
1871 else if (Is64Bit && RegVT == MVT::i64)
1872 RC = &X86::GR64RegClass;
1873 else if (RegVT == MVT::f32)
1874 RC = &X86::FR32RegClass;
1875 else if (RegVT == MVT::f64)
1876 RC = &X86::FR64RegClass;
1877 else if (RegVT.isVector() && RegVT.getSizeInBits() == 256)
1878 RC = &X86::VR256RegClass;
1879 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1880 RC = &X86::VR128RegClass;
1881 else if (RegVT == MVT::x86mmx)
1882 RC = &X86::VR64RegClass;
1884 llvm_unreachable("Unknown argument type!");
1886 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1887 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1889 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1890 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1892 if (VA.getLocInfo() == CCValAssign::SExt)
1893 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1894 DAG.getValueType(VA.getValVT()));
1895 else if (VA.getLocInfo() == CCValAssign::ZExt)
1896 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1897 DAG.getValueType(VA.getValVT()));
1898 else if (VA.getLocInfo() == CCValAssign::BCvt)
1899 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
1901 if (VA.isExtInLoc()) {
1902 // Handle MMX values passed in XMM regs.
1903 if (RegVT.isVector()) {
1904 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(),
1907 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1910 assert(VA.isMemLoc());
1911 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
1914 // If value is passed via pointer - do a load.
1915 if (VA.getLocInfo() == CCValAssign::Indirect)
1916 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
1917 MachinePointerInfo(), false, false, false, 0);
1919 InVals.push_back(ArgValue);
1922 // The x86-64 ABI for returning structs by value requires that we copy
1923 // the sret argument into %rax for the return. Save the argument into
1924 // a virtual register so that we can access it from the return points.
1925 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) {
1926 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1927 unsigned Reg = FuncInfo->getSRetReturnReg();
1929 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1930 FuncInfo->setSRetReturnReg(Reg);
1932 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1933 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1936 unsigned StackSize = CCInfo.getNextStackOffset();
1937 // Align stack specially for tail calls.
1938 if (FuncIsMadeTailCallSafe(CallConv,
1939 MF.getTarget().Options.GuaranteedTailCallOpt))
1940 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1942 // If the function takes variable number of arguments, make a frame index for
1943 // the start of the first vararg value... for expansion of llvm.va_start.
1945 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
1946 CallConv != CallingConv::X86_ThisCall)) {
1947 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
1950 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1952 // FIXME: We should really autogenerate these arrays
1953 static const uint16_t GPR64ArgRegsWin64[] = {
1954 X86::RCX, X86::RDX, X86::R8, X86::R9
1956 static const uint16_t GPR64ArgRegs64Bit[] = {
1957 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1959 static const uint16_t XMMArgRegs64Bit[] = {
1960 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1961 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1963 const uint16_t *GPR64ArgRegs;
1964 unsigned NumXMMRegs = 0;
1967 // The XMM registers which might contain var arg parameters are shadowed
1968 // in their paired GPR. So we only need to save the GPR to their home
1970 TotalNumIntRegs = 4;
1971 GPR64ArgRegs = GPR64ArgRegsWin64;
1973 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1974 GPR64ArgRegs = GPR64ArgRegs64Bit;
1976 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit,
1979 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1982 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat);
1983 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
1984 "SSE register cannot be used when SSE is disabled!");
1985 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat &&
1986 NoImplicitFloatOps) &&
1987 "SSE register cannot be used when SSE is disabled!");
1988 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
1989 !Subtarget->hasSSE1())
1990 // Kernel mode asks for SSE to be disabled, so don't push them
1992 TotalNumXMMRegs = 0;
1995 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering();
1996 // Get to the caller-allocated home save location. Add 8 to account
1997 // for the return address.
1998 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
1999 FuncInfo->setRegSaveFrameIndex(
2000 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2001 // Fixup to set vararg frame on shadow area (4 x i64).
2003 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2005 // For X86-64, if there are vararg parameters that are passed via
2006 // registers, then we must store them to their spots on the stack so
2007 // they may be loaded by deferencing the result of va_next.
2008 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2009 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
2010 FuncInfo->setRegSaveFrameIndex(
2011 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
2015 // Store the integer parameter registers.
2016 SmallVector<SDValue, 8> MemOps;
2017 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2019 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2020 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
2021 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2022 DAG.getIntPtrConstant(Offset));
2023 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
2024 &X86::GR64RegClass);
2025 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2027 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2028 MachinePointerInfo::getFixedStack(
2029 FuncInfo->getRegSaveFrameIndex(), Offset),
2031 MemOps.push_back(Store);
2035 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
2036 // Now store the XMM (fp + vector) parameter registers.
2037 SmallVector<SDValue, 11> SaveXMMOps;
2038 SaveXMMOps.push_back(Chain);
2040 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2041 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
2042 SaveXMMOps.push_back(ALVal);
2044 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2045 FuncInfo->getRegSaveFrameIndex()));
2046 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2047 FuncInfo->getVarArgsFPOffset()));
2049 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
2050 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
2051 &X86::VR128RegClass);
2052 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
2053 SaveXMMOps.push_back(Val);
2055 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2057 &SaveXMMOps[0], SaveXMMOps.size()));
2060 if (!MemOps.empty())
2061 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2062 &MemOps[0], MemOps.size());
2066 // Some CCs need callee pop.
2067 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2068 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2069 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2071 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2072 // If this is an sret function, the return should pop the hidden pointer.
2073 if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2074 ArgsAreStructReturn(Ins))
2075 FuncInfo->setBytesToPopOnReturn(4);
2079 // RegSaveFrameIndex is X86-64 only.
2080 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2081 if (CallConv == CallingConv::X86_FastCall ||
2082 CallConv == CallingConv::X86_ThisCall)
2083 // fastcc functions can't have varargs.
2084 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2087 FuncInfo->setArgumentStackSize(StackSize);
2093 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2094 SDValue StackPtr, SDValue Arg,
2095 DebugLoc dl, SelectionDAG &DAG,
2096 const CCValAssign &VA,
2097 ISD::ArgFlagsTy Flags) const {
2098 unsigned LocMemOffset = VA.getLocMemOffset();
2099 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2100 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2101 if (Flags.isByVal())
2102 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2104 return DAG.getStore(Chain, dl, Arg, PtrOff,
2105 MachinePointerInfo::getStack(LocMemOffset),
2109 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2110 /// optimization is performed and it is required.
2112 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2113 SDValue &OutRetAddr, SDValue Chain,
2114 bool IsTailCall, bool Is64Bit,
2115 int FPDiff, DebugLoc dl) const {
2116 // Adjust the Return address stack slot.
2117 EVT VT = getPointerTy();
2118 OutRetAddr = getReturnAddressFrameIndex(DAG);
2120 // Load the "old" Return address.
2121 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2122 false, false, false, 0);
2123 return SDValue(OutRetAddr.getNode(), 1);
2126 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2127 /// optimization is performed and it is required (FPDiff!=0).
2129 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
2130 SDValue Chain, SDValue RetAddrFrIdx,
2131 bool Is64Bit, int FPDiff, DebugLoc dl) {
2132 // Store the return address to the appropriate stack slot.
2133 if (!FPDiff) return Chain;
2134 // Calculate the new stack slot for the return address.
2135 int SlotSize = Is64Bit ? 8 : 4;
2136 int NewReturnAddrFI =
2137 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false);
2138 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
2139 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
2140 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2141 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2147 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2148 SmallVectorImpl<SDValue> &InVals) const {
2149 SelectionDAG &DAG = CLI.DAG;
2150 DebugLoc &dl = CLI.DL;
2151 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
2152 SmallVector<SDValue, 32> &OutVals = CLI.OutVals;
2153 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
2154 SDValue Chain = CLI.Chain;
2155 SDValue Callee = CLI.Callee;
2156 CallingConv::ID CallConv = CLI.CallConv;
2157 bool &isTailCall = CLI.IsTailCall;
2158 bool isVarArg = CLI.IsVarArg;
2160 MachineFunction &MF = DAG.getMachineFunction();
2161 bool Is64Bit = Subtarget->is64Bit();
2162 bool IsWin64 = Subtarget->isTargetWin64();
2163 bool IsWindows = Subtarget->isTargetWindows();
2164 bool IsStructRet = CallIsStructReturn(Outs);
2165 bool IsSibcall = false;
2167 if (MF.getTarget().Options.DisableTailCalls)
2171 // Check if it's really possible to do a tail call.
2172 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2173 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
2174 Outs, OutVals, Ins, DAG);
2176 // Sibcalls are automatically detected tailcalls which do not require
2178 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2185 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2186 "Var args not supported with calling convention fastcc or ghc");
2188 // Analyze operands of the call, assigning locations to each operand.
2189 SmallVector<CCValAssign, 16> ArgLocs;
2190 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2191 ArgLocs, *DAG.getContext());
2193 // Allocate shadow area for Win64
2195 CCInfo.AllocateStack(32, 8);
2198 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2200 // Get a count of how many bytes are to be pushed on the stack.
2201 unsigned NumBytes = CCInfo.getNextStackOffset();
2203 // This is a sibcall. The memory operands are available in caller's
2204 // own caller's stack.
2206 else if (getTargetMachine().Options.GuaranteedTailCallOpt &&
2207 IsTailCallConvention(CallConv))
2208 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2211 if (isTailCall && !IsSibcall) {
2212 // Lower arguments at fp - stackoffset + fpdiff.
2213 unsigned NumBytesCallerPushed =
2214 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
2215 FPDiff = NumBytesCallerPushed - NumBytes;
2217 // Set the delta of movement of the returnaddr stackslot.
2218 // But only set if delta is greater than previous delta.
2219 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
2220 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
2224 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
2226 SDValue RetAddrFrIdx;
2227 // Load return address for tail calls.
2228 if (isTailCall && FPDiff)
2229 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2230 Is64Bit, FPDiff, dl);
2232 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2233 SmallVector<SDValue, 8> MemOpChains;
2236 // Walk the register/memloc assignments, inserting copies/loads. In the case
2237 // of tail call optimization arguments are handle later.
2238 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2239 CCValAssign &VA = ArgLocs[i];
2240 EVT RegVT = VA.getLocVT();
2241 SDValue Arg = OutVals[i];
2242 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2243 bool isByVal = Flags.isByVal();
2245 // Promote the value if needed.
2246 switch (VA.getLocInfo()) {
2247 default: llvm_unreachable("Unknown loc info!");
2248 case CCValAssign::Full: break;
2249 case CCValAssign::SExt:
2250 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2252 case CCValAssign::ZExt:
2253 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2255 case CCValAssign::AExt:
2256 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) {
2257 // Special case: passing MMX values in XMM registers.
2258 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2259 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2260 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2262 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2264 case CCValAssign::BCvt:
2265 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2267 case CCValAssign::Indirect: {
2268 // Store the argument.
2269 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2270 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2271 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2272 MachinePointerInfo::getFixedStack(FI),
2279 if (VA.isRegLoc()) {
2280 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2281 if (isVarArg && IsWin64) {
2282 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2283 // shadow reg if callee is a varargs function.
2284 unsigned ShadowReg = 0;
2285 switch (VA.getLocReg()) {
2286 case X86::XMM0: ShadowReg = X86::RCX; break;
2287 case X86::XMM1: ShadowReg = X86::RDX; break;
2288 case X86::XMM2: ShadowReg = X86::R8; break;
2289 case X86::XMM3: ShadowReg = X86::R9; break;
2292 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2294 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2295 assert(VA.isMemLoc());
2296 if (StackPtr.getNode() == 0)
2297 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
2298 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2299 dl, DAG, VA, Flags));
2303 if (!MemOpChains.empty())
2304 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2305 &MemOpChains[0], MemOpChains.size());
2307 // Build a sequence of copy-to-reg nodes chained together with token chain
2308 // and flag operands which copy the outgoing args into registers.
2310 // Tail call byval lowering might overwrite argument registers so in case of
2311 // tail call optimization the copies to registers are lowered later.
2313 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2314 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2315 RegsToPass[i].second, InFlag);
2316 InFlag = Chain.getValue(1);
2319 if (Subtarget->isPICStyleGOT()) {
2320 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2323 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX,
2324 DAG.getNode(X86ISD::GlobalBaseReg,
2325 DebugLoc(), getPointerTy()),
2327 InFlag = Chain.getValue(1);
2329 // If we are tail calling and generating PIC/GOT style code load the
2330 // address of the callee into ECX. The value in ecx is used as target of
2331 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2332 // for tail calls on PIC/GOT architectures. Normally we would just put the
2333 // address of GOT into ebx and then call target@PLT. But for tail calls
2334 // ebx would be restored (since ebx is callee saved) before jumping to the
2337 // Note: The actual moving to ECX is done further down.
2338 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2339 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2340 !G->getGlobal()->hasProtectedVisibility())
2341 Callee = LowerGlobalAddress(Callee, DAG);
2342 else if (isa<ExternalSymbolSDNode>(Callee))
2343 Callee = LowerExternalSymbol(Callee, DAG);
2347 if (Is64Bit && isVarArg && !IsWin64) {
2348 // From AMD64 ABI document:
2349 // For calls that may call functions that use varargs or stdargs
2350 // (prototype-less calls or calls to functions containing ellipsis (...) in
2351 // the declaration) %al is used as hidden argument to specify the number
2352 // of SSE registers used. The contents of %al do not need to match exactly
2353 // the number of registers, but must be an ubound on the number of SSE
2354 // registers used and is in the range 0 - 8 inclusive.
2356 // Count the number of XMM registers allocated.
2357 static const uint16_t XMMArgRegs[] = {
2358 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2359 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2361 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2362 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2363 && "SSE registers cannot be used when SSE is disabled");
2365 Chain = DAG.getCopyToReg(Chain, dl, X86::AL,
2366 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
2367 InFlag = Chain.getValue(1);
2371 // For tail calls lower the arguments to the 'real' stack slot.
2373 // Force all the incoming stack arguments to be loaded from the stack
2374 // before any new outgoing arguments are stored to the stack, because the
2375 // outgoing stack slots may alias the incoming argument stack slots, and
2376 // the alias isn't otherwise explicit. This is slightly more conservative
2377 // than necessary, because it means that each store effectively depends
2378 // on every argument instead of just those arguments it would clobber.
2379 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2381 SmallVector<SDValue, 8> MemOpChains2;
2384 // Do not flag preceding copytoreg stuff together with the following stuff.
2386 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2387 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2388 CCValAssign &VA = ArgLocs[i];
2391 assert(VA.isMemLoc());
2392 SDValue Arg = OutVals[i];
2393 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2394 // Create frame index.
2395 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2396 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2397 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2398 FIN = DAG.getFrameIndex(FI, getPointerTy());
2400 if (Flags.isByVal()) {
2401 // Copy relative to framepointer.
2402 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2403 if (StackPtr.getNode() == 0)
2404 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
2406 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2408 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2412 // Store relative to framepointer.
2413 MemOpChains2.push_back(
2414 DAG.getStore(ArgChain, dl, Arg, FIN,
2415 MachinePointerInfo::getFixedStack(FI),
2421 if (!MemOpChains2.empty())
2422 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2423 &MemOpChains2[0], MemOpChains2.size());
2425 // Copy arguments to their registers.
2426 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2427 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2428 RegsToPass[i].second, InFlag);
2429 InFlag = Chain.getValue(1);
2433 // Store the return address to the appropriate stack slot.
2434 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
2438 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2439 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2440 // In the 64-bit large code model, we have to make all calls
2441 // through a register, since the call instruction's 32-bit
2442 // pc-relative offset may not be large enough to hold the whole
2444 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2445 // If the callee is a GlobalAddress node (quite common, every direct call
2446 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2449 // We should use extra load for direct calls to dllimported functions in
2451 const GlobalValue *GV = G->getGlobal();
2452 if (!GV->hasDLLImportLinkage()) {
2453 unsigned char OpFlags = 0;
2454 bool ExtraLoad = false;
2455 unsigned WrapperKind = ISD::DELETED_NODE;
2457 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2458 // external symbols most go through the PLT in PIC mode. If the symbol
2459 // has hidden or protected visibility, or if it is static or local, then
2460 // we don't need to use the PLT - we can directly call it.
2461 if (Subtarget->isTargetELF() &&
2462 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2463 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2464 OpFlags = X86II::MO_PLT;
2465 } else if (Subtarget->isPICStyleStubAny() &&
2466 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2467 (!Subtarget->getTargetTriple().isMacOSX() ||
2468 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2469 // PC-relative references to external symbols should go through $stub,
2470 // unless we're building with the leopard linker or later, which
2471 // automatically synthesizes these stubs.
2472 OpFlags = X86II::MO_DARWIN_STUB;
2473 } else if (Subtarget->isPICStyleRIPRel() &&
2474 isa<Function>(GV) &&
2475 cast<Function>(GV)->hasFnAttr(Attribute::NonLazyBind)) {
2476 // If the function is marked as non-lazy, generate an indirect call
2477 // which loads from the GOT directly. This avoids runtime overhead
2478 // at the cost of eager binding (and one extra byte of encoding).
2479 OpFlags = X86II::MO_GOTPCREL;
2480 WrapperKind = X86ISD::WrapperRIP;
2484 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2485 G->getOffset(), OpFlags);
2487 // Add a wrapper if needed.
2488 if (WrapperKind != ISD::DELETED_NODE)
2489 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
2490 // Add extra indirection if needed.
2492 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
2493 MachinePointerInfo::getGOT(),
2494 false, false, false, 0);
2496 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2497 unsigned char OpFlags = 0;
2499 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2500 // external symbols should go through the PLT.
2501 if (Subtarget->isTargetELF() &&
2502 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2503 OpFlags = X86II::MO_PLT;
2504 } else if (Subtarget->isPICStyleStubAny() &&
2505 (!Subtarget->getTargetTriple().isMacOSX() ||
2506 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2507 // PC-relative references to external symbols should go through $stub,
2508 // unless we're building with the leopard linker or later, which
2509 // automatically synthesizes these stubs.
2510 OpFlags = X86II::MO_DARWIN_STUB;
2513 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2517 // Returns a chain & a flag for retval copy to use.
2518 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2519 SmallVector<SDValue, 8> Ops;
2521 if (!IsSibcall && isTailCall) {
2522 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2523 DAG.getIntPtrConstant(0, true), InFlag);
2524 InFlag = Chain.getValue(1);
2527 Ops.push_back(Chain);
2528 Ops.push_back(Callee);
2531 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2533 // Add argument registers to the end of the list so that they are known live
2535 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2536 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2537 RegsToPass[i].second.getValueType()));
2539 // Add an implicit use GOT pointer in EBX.
2540 if (!isTailCall && Subtarget->isPICStyleGOT())
2541 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
2543 // Add an implicit use of AL for non-Windows x86 64-bit vararg functions.
2544 if (Is64Bit && isVarArg && !IsWin64)
2545 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
2547 // Add a register mask operand representing the call-preserved registers.
2548 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2549 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
2550 assert(Mask && "Missing call preserved mask for calling convention");
2551 Ops.push_back(DAG.getRegisterMask(Mask));
2553 if (InFlag.getNode())
2554 Ops.push_back(InFlag);
2558 //// If this is the first return lowered for this function, add the regs
2559 //// to the liveout set for the function.
2560 // This isn't right, although it's probably harmless on x86; liveouts
2561 // should be computed from returns not tail calls. Consider a void
2562 // function making a tail call to a function returning int.
2563 return DAG.getNode(X86ISD::TC_RETURN, dl,
2564 NodeTys, &Ops[0], Ops.size());
2567 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2568 InFlag = Chain.getValue(1);
2570 // Create the CALLSEQ_END node.
2571 unsigned NumBytesForCalleeToPush;
2572 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2573 getTargetMachine().Options.GuaranteedTailCallOpt))
2574 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2575 else if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2577 // If this is a call to a struct-return function, the callee
2578 // pops the hidden struct pointer, so we have to push it back.
2579 // This is common for Darwin/X86, Linux & Mingw32 targets.
2580 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
2581 NumBytesForCalleeToPush = 4;
2583 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2585 // Returns a flag for retval copy to use.
2587 Chain = DAG.getCALLSEQ_END(Chain,
2588 DAG.getIntPtrConstant(NumBytes, true),
2589 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2592 InFlag = Chain.getValue(1);
2595 // Handle result values, copying them out of physregs into vregs that we
2597 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2598 Ins, dl, DAG, InVals);
2602 //===----------------------------------------------------------------------===//
2603 // Fast Calling Convention (tail call) implementation
2604 //===----------------------------------------------------------------------===//
2606 // Like std call, callee cleans arguments, convention except that ECX is
2607 // reserved for storing the tail called function address. Only 2 registers are
2608 // free for argument passing (inreg). Tail call optimization is performed
2610 // * tailcallopt is enabled
2611 // * caller/callee are fastcc
2612 // On X86_64 architecture with GOT-style position independent code only local
2613 // (within module) calls are supported at the moment.
2614 // To keep the stack aligned according to platform abi the function
2615 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2616 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2617 // If a tail called function callee has more arguments than the caller the
2618 // caller needs to make sure that there is room to move the RETADDR to. This is
2619 // achieved by reserving an area the size of the argument delta right after the
2620 // original REtADDR, but before the saved framepointer or the spilled registers
2621 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2633 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2634 /// for a 16 byte align requirement.
2636 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2637 SelectionDAG& DAG) const {
2638 MachineFunction &MF = DAG.getMachineFunction();
2639 const TargetMachine &TM = MF.getTarget();
2640 const TargetFrameLowering &TFI = *TM.getFrameLowering();
2641 unsigned StackAlignment = TFI.getStackAlignment();
2642 uint64_t AlignMask = StackAlignment - 1;
2643 int64_t Offset = StackSize;
2644 uint64_t SlotSize = TD->getPointerSize();
2645 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2646 // Number smaller than 12 so just add the difference.
2647 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2649 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2650 Offset = ((~AlignMask) & Offset) + StackAlignment +
2651 (StackAlignment-SlotSize);
2656 /// MatchingStackOffset - Return true if the given stack call argument is
2657 /// already available in the same position (relatively) of the caller's
2658 /// incoming argument stack.
2660 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2661 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2662 const X86InstrInfo *TII) {
2663 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
2665 if (Arg.getOpcode() == ISD::CopyFromReg) {
2666 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2667 if (!TargetRegisterInfo::isVirtualRegister(VR))
2669 MachineInstr *Def = MRI->getVRegDef(VR);
2672 if (!Flags.isByVal()) {
2673 if (!TII->isLoadFromStackSlot(Def, FI))
2676 unsigned Opcode = Def->getOpcode();
2677 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
2678 Def->getOperand(1).isFI()) {
2679 FI = Def->getOperand(1).getIndex();
2680 Bytes = Flags.getByValSize();
2684 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2685 if (Flags.isByVal())
2686 // ByVal argument is passed in as a pointer but it's now being
2687 // dereferenced. e.g.
2688 // define @foo(%struct.X* %A) {
2689 // tail call @bar(%struct.X* byval %A)
2692 SDValue Ptr = Ld->getBasePtr();
2693 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2696 FI = FINode->getIndex();
2697 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
2698 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
2699 FI = FINode->getIndex();
2700 Bytes = Flags.getByValSize();
2704 assert(FI != INT_MAX);
2705 if (!MFI->isFixedObjectIndex(FI))
2707 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
2710 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2711 /// for tail call optimization. Targets which want to do tail call
2712 /// optimization should implement this function.
2714 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2715 CallingConv::ID CalleeCC,
2717 bool isCalleeStructRet,
2718 bool isCallerStructRet,
2719 const SmallVectorImpl<ISD::OutputArg> &Outs,
2720 const SmallVectorImpl<SDValue> &OutVals,
2721 const SmallVectorImpl<ISD::InputArg> &Ins,
2722 SelectionDAG& DAG) const {
2723 if (!IsTailCallConvention(CalleeCC) &&
2724 CalleeCC != CallingConv::C)
2727 // If -tailcallopt is specified, make fastcc functions tail-callable.
2728 const MachineFunction &MF = DAG.getMachineFunction();
2729 const Function *CallerF = DAG.getMachineFunction().getFunction();
2730 CallingConv::ID CallerCC = CallerF->getCallingConv();
2731 bool CCMatch = CallerCC == CalleeCC;
2733 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2734 if (IsTailCallConvention(CalleeCC) && CCMatch)
2739 // Look for obvious safe cases to perform tail call optimization that do not
2740 // require ABI changes. This is what gcc calls sibcall.
2742 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
2743 // emit a special epilogue.
2744 if (RegInfo->needsStackRealignment(MF))
2747 // Also avoid sibcall optimization if either caller or callee uses struct
2748 // return semantics.
2749 if (isCalleeStructRet || isCallerStructRet)
2752 // An stdcall caller is expected to clean up its arguments; the callee
2753 // isn't going to do that.
2754 if (!CCMatch && CallerCC==CallingConv::X86_StdCall)
2757 // Do not sibcall optimize vararg calls unless all arguments are passed via
2759 if (isVarArg && !Outs.empty()) {
2761 // Optimizing for varargs on Win64 is unlikely to be safe without
2762 // additional testing.
2763 if (Subtarget->isTargetWin64())
2766 SmallVector<CCValAssign, 16> ArgLocs;
2767 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2768 getTargetMachine(), ArgLocs, *DAG.getContext());
2770 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2771 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
2772 if (!ArgLocs[i].isRegLoc())
2776 // If the call result is in ST0 / ST1, it needs to be popped off the x87
2777 // stack. Therefore, if it's not used by the call it is not safe to optimize
2778 // this into a sibcall.
2779 bool Unused = false;
2780 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
2787 SmallVector<CCValAssign, 16> RVLocs;
2788 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(),
2789 getTargetMachine(), RVLocs, *DAG.getContext());
2790 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2791 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2792 CCValAssign &VA = RVLocs[i];
2793 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
2798 // If the calling conventions do not match, then we'd better make sure the
2799 // results are returned in the same way as what the caller expects.
2801 SmallVector<CCValAssign, 16> RVLocs1;
2802 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
2803 getTargetMachine(), RVLocs1, *DAG.getContext());
2804 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
2806 SmallVector<CCValAssign, 16> RVLocs2;
2807 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
2808 getTargetMachine(), RVLocs2, *DAG.getContext());
2809 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
2811 if (RVLocs1.size() != RVLocs2.size())
2813 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2814 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2816 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2818 if (RVLocs1[i].isRegLoc()) {
2819 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2822 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2828 // If the callee takes no arguments then go on to check the results of the
2830 if (!Outs.empty()) {
2831 // Check if stack adjustment is needed. For now, do not do this if any
2832 // argument is passed on the stack.
2833 SmallVector<CCValAssign, 16> ArgLocs;
2834 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2835 getTargetMachine(), ArgLocs, *DAG.getContext());
2837 // Allocate shadow area for Win64
2838 if (Subtarget->isTargetWin64()) {
2839 CCInfo.AllocateStack(32, 8);
2842 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2843 if (CCInfo.getNextStackOffset()) {
2844 MachineFunction &MF = DAG.getMachineFunction();
2845 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
2848 // Check if the arguments are already laid out in the right way as
2849 // the caller's fixed stack objects.
2850 MachineFrameInfo *MFI = MF.getFrameInfo();
2851 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2852 const X86InstrInfo *TII =
2853 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
2854 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2855 CCValAssign &VA = ArgLocs[i];
2856 SDValue Arg = OutVals[i];
2857 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2858 if (VA.getLocInfo() == CCValAssign::Indirect)
2860 if (!VA.isRegLoc()) {
2861 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2868 // If the tailcall address may be in a register, then make sure it's
2869 // possible to register allocate for it. In 32-bit, the call address can
2870 // only target EAX, EDX, or ECX since the tail call must be scheduled after
2871 // callee-saved registers are restored. These happen to be the same
2872 // registers used to pass 'inreg' arguments so watch out for those.
2873 if (!Subtarget->is64Bit() &&
2874 !isa<GlobalAddressSDNode>(Callee) &&
2875 !isa<ExternalSymbolSDNode>(Callee)) {
2876 unsigned NumInRegs = 0;
2877 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2878 CCValAssign &VA = ArgLocs[i];
2881 unsigned Reg = VA.getLocReg();
2884 case X86::EAX: case X86::EDX: case X86::ECX:
2885 if (++NumInRegs == 3)
2897 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const {
2898 return X86::createFastISel(funcInfo);
2902 //===----------------------------------------------------------------------===//
2903 // Other Lowering Hooks
2904 //===----------------------------------------------------------------------===//
2906 static bool MayFoldLoad(SDValue Op) {
2907 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
2910 static bool MayFoldIntoStore(SDValue Op) {
2911 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
2914 static bool isTargetShuffle(unsigned Opcode) {
2916 default: return false;
2917 case X86ISD::PSHUFD:
2918 case X86ISD::PSHUFHW:
2919 case X86ISD::PSHUFLW:
2921 case X86ISD::PALIGN:
2922 case X86ISD::MOVLHPS:
2923 case X86ISD::MOVLHPD:
2924 case X86ISD::MOVHLPS:
2925 case X86ISD::MOVLPS:
2926 case X86ISD::MOVLPD:
2927 case X86ISD::MOVSHDUP:
2928 case X86ISD::MOVSLDUP:
2929 case X86ISD::MOVDDUP:
2932 case X86ISD::UNPCKL:
2933 case X86ISD::UNPCKH:
2934 case X86ISD::VPERMILP:
2935 case X86ISD::VPERM2X128:
2936 case X86ISD::VPERMI:
2941 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2942 SDValue V1, SelectionDAG &DAG) {
2944 default: llvm_unreachable("Unknown x86 shuffle node");
2945 case X86ISD::MOVSHDUP:
2946 case X86ISD::MOVSLDUP:
2947 case X86ISD::MOVDDUP:
2948 return DAG.getNode(Opc, dl, VT, V1);
2952 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2953 SDValue V1, unsigned TargetMask,
2954 SelectionDAG &DAG) {
2956 default: llvm_unreachable("Unknown x86 shuffle node");
2957 case X86ISD::PSHUFD:
2958 case X86ISD::PSHUFHW:
2959 case X86ISD::PSHUFLW:
2960 case X86ISD::VPERMILP:
2961 case X86ISD::VPERMI:
2962 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
2966 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2967 SDValue V1, SDValue V2, unsigned TargetMask,
2968 SelectionDAG &DAG) {
2970 default: llvm_unreachable("Unknown x86 shuffle node");
2971 case X86ISD::PALIGN:
2973 case X86ISD::VPERM2X128:
2974 return DAG.getNode(Opc, dl, VT, V1, V2,
2975 DAG.getConstant(TargetMask, MVT::i8));
2979 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2980 SDValue V1, SDValue V2, SelectionDAG &DAG) {
2982 default: llvm_unreachable("Unknown x86 shuffle node");
2983 case X86ISD::MOVLHPS:
2984 case X86ISD::MOVLHPD:
2985 case X86ISD::MOVHLPS:
2986 case X86ISD::MOVLPS:
2987 case X86ISD::MOVLPD:
2990 case X86ISD::UNPCKL:
2991 case X86ISD::UNPCKH:
2992 return DAG.getNode(Opc, dl, VT, V1, V2);
2996 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
2997 MachineFunction &MF = DAG.getMachineFunction();
2998 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2999 int ReturnAddrIndex = FuncInfo->getRAIndex();
3001 if (ReturnAddrIndex == 0) {
3002 // Set up a frame object for the return address.
3003 uint64_t SlotSize = TD->getPointerSize();
3004 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
3006 FuncInfo->setRAIndex(ReturnAddrIndex);
3009 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3013 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3014 bool hasSymbolicDisplacement) {
3015 // Offset should fit into 32 bit immediate field.
3016 if (!isInt<32>(Offset))
3019 // If we don't have a symbolic displacement - we don't have any extra
3021 if (!hasSymbolicDisplacement)
3024 // FIXME: Some tweaks might be needed for medium code model.
3025 if (M != CodeModel::Small && M != CodeModel::Kernel)
3028 // For small code model we assume that latest object is 16MB before end of 31
3029 // bits boundary. We may also accept pretty large negative constants knowing
3030 // that all objects are in the positive half of address space.
3031 if (M == CodeModel::Small && Offset < 16*1024*1024)
3034 // For kernel code model we know that all object resist in the negative half
3035 // of 32bits address space. We may not accept negative offsets, since they may
3036 // be just off and we may accept pretty large positive ones.
3037 if (M == CodeModel::Kernel && Offset > 0)
3043 /// isCalleePop - Determines whether the callee is required to pop its
3044 /// own arguments. Callee pop is necessary to support tail calls.
3045 bool X86::isCalleePop(CallingConv::ID CallingConv,
3046 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3050 switch (CallingConv) {
3053 case CallingConv::X86_StdCall:
3055 case CallingConv::X86_FastCall:
3057 case CallingConv::X86_ThisCall:
3059 case CallingConv::Fast:
3061 case CallingConv::GHC:
3066 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3067 /// specific condition code, returning the condition code and the LHS/RHS of the
3068 /// comparison to make.
3069 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3070 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3072 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3073 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3074 // X > -1 -> X == 0, jump !sign.
3075 RHS = DAG.getConstant(0, RHS.getValueType());
3076 return X86::COND_NS;
3078 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3079 // X < 0 -> X == 0, jump on sign.
3082 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3084 RHS = DAG.getConstant(0, RHS.getValueType());
3085 return X86::COND_LE;
3089 switch (SetCCOpcode) {
3090 default: llvm_unreachable("Invalid integer condition!");
3091 case ISD::SETEQ: return X86::COND_E;
3092 case ISD::SETGT: return X86::COND_G;
3093 case ISD::SETGE: return X86::COND_GE;
3094 case ISD::SETLT: return X86::COND_L;
3095 case ISD::SETLE: return X86::COND_LE;
3096 case ISD::SETNE: return X86::COND_NE;
3097 case ISD::SETULT: return X86::COND_B;
3098 case ISD::SETUGT: return X86::COND_A;
3099 case ISD::SETULE: return X86::COND_BE;
3100 case ISD::SETUGE: return X86::COND_AE;
3104 // First determine if it is required or is profitable to flip the operands.
3106 // If LHS is a foldable load, but RHS is not, flip the condition.
3107 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3108 !ISD::isNON_EXTLoad(RHS.getNode())) {
3109 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3110 std::swap(LHS, RHS);
3113 switch (SetCCOpcode) {
3119 std::swap(LHS, RHS);
3123 // On a floating point condition, the flags are set as follows:
3125 // 0 | 0 | 0 | X > Y
3126 // 0 | 0 | 1 | X < Y
3127 // 1 | 0 | 0 | X == Y
3128 // 1 | 1 | 1 | unordered
3129 switch (SetCCOpcode) {
3130 default: llvm_unreachable("Condcode should be pre-legalized away");
3132 case ISD::SETEQ: return X86::COND_E;
3133 case ISD::SETOLT: // flipped
3135 case ISD::SETGT: return X86::COND_A;
3136 case ISD::SETOLE: // flipped
3138 case ISD::SETGE: return X86::COND_AE;
3139 case ISD::SETUGT: // flipped
3141 case ISD::SETLT: return X86::COND_B;
3142 case ISD::SETUGE: // flipped
3144 case ISD::SETLE: return X86::COND_BE;
3146 case ISD::SETNE: return X86::COND_NE;
3147 case ISD::SETUO: return X86::COND_P;
3148 case ISD::SETO: return X86::COND_NP;
3150 case ISD::SETUNE: return X86::COND_INVALID;
3154 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3155 /// code. Current x86 isa includes the following FP cmov instructions:
3156 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3157 static bool hasFPCMov(unsigned X86CC) {
3173 /// isFPImmLegal - Returns true if the target can instruction select the
3174 /// specified FP immediate natively. If false, the legalizer will
3175 /// materialize the FP immediate as a load from a constant pool.
3176 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3177 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3178 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3184 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3185 /// the specified range (L, H].
3186 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3187 return (Val < 0) || (Val >= Low && Val < Hi);
3190 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3191 /// specified value.
3192 static bool isUndefOrEqual(int Val, int CmpVal) {
3193 if (Val < 0 || Val == CmpVal)
3198 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3199 /// from position Pos and ending in Pos+Size, falls within the specified
3200 /// sequential range (L, L+Pos]. or is undef.
3201 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3202 unsigned Pos, unsigned Size, int Low) {
3203 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3204 if (!isUndefOrEqual(Mask[i], Low))
3209 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3210 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3211 /// the second operand.
3212 static bool isPSHUFDMask(ArrayRef<int> Mask, EVT VT) {
3213 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3214 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3215 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3216 return (Mask[0] < 2 && Mask[1] < 2);
3220 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3221 /// is suitable for input to PSHUFHW.
3222 static bool isPSHUFHWMask(ArrayRef<int> Mask, EVT VT, bool HasAVX2) {
3223 if (VT != MVT::v8i16 && (!HasAVX2 || VT != MVT::v16i16))
3226 // Lower quadword copied in order or undef.
3227 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3230 // Upper quadword shuffled.
3231 for (unsigned i = 4; i != 8; ++i)
3232 if (!isUndefOrInRange(Mask[i], 4, 8))
3235 if (VT == MVT::v16i16) {
3236 // Lower quadword copied in order or undef.
3237 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3240 // Upper quadword shuffled.
3241 for (unsigned i = 12; i != 16; ++i)
3242 if (!isUndefOrInRange(Mask[i], 12, 16))
3249 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3250 /// is suitable for input to PSHUFLW.
3251 static bool isPSHUFLWMask(ArrayRef<int> Mask, EVT VT, bool HasAVX2) {
3252 if (VT != MVT::v8i16 && (!HasAVX2 || VT != MVT::v16i16))
3255 // Upper quadword copied in order.
3256 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3259 // Lower quadword shuffled.
3260 for (unsigned i = 0; i != 4; ++i)
3261 if (!isUndefOrInRange(Mask[i], 0, 4))
3264 if (VT == MVT::v16i16) {
3265 // Upper quadword copied in order.
3266 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3269 // Lower quadword shuffled.
3270 for (unsigned i = 8; i != 12; ++i)
3271 if (!isUndefOrInRange(Mask[i], 8, 12))
3278 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
3279 /// is suitable for input to PALIGNR.
3280 static bool isPALIGNRMask(ArrayRef<int> Mask, EVT VT,
3281 const X86Subtarget *Subtarget) {
3282 if ((VT.getSizeInBits() == 128 && !Subtarget->hasSSSE3()) ||
3283 (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2()))
3286 unsigned NumElts = VT.getVectorNumElements();
3287 unsigned NumLanes = VT.getSizeInBits()/128;
3288 unsigned NumLaneElts = NumElts/NumLanes;
3290 // Do not handle 64-bit element shuffles with palignr.
3291 if (NumLaneElts == 2)
3294 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3296 for (i = 0; i != NumLaneElts; ++i) {
3301 // Lane is all undef, go to next lane
3302 if (i == NumLaneElts)
3305 int Start = Mask[i+l];
3307 // Make sure its in this lane in one of the sources
3308 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3309 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3312 // If not lane 0, then we must match lane 0
3313 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3316 // Correct second source to be contiguous with first source
3317 if (Start >= (int)NumElts)
3318 Start -= NumElts - NumLaneElts;
3320 // Make sure we're shifting in the right direction.
3321 if (Start <= (int)(i+l))
3326 // Check the rest of the elements to see if they are consecutive.
3327 for (++i; i != NumLaneElts; ++i) {
3328 int Idx = Mask[i+l];
3330 // Make sure its in this lane
3331 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3332 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3335 // If not lane 0, then we must match lane 0
3336 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3339 if (Idx >= (int)NumElts)
3340 Idx -= NumElts - NumLaneElts;
3342 if (!isUndefOrEqual(Idx, Start+i))
3351 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3352 /// the two vector operands have swapped position.
3353 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
3354 unsigned NumElems) {
3355 for (unsigned i = 0; i != NumElems; ++i) {
3359 else if (idx < (int)NumElems)
3360 Mask[i] = idx + NumElems;
3362 Mask[i] = idx - NumElems;
3366 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
3367 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
3368 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
3369 /// reverse of what x86 shuffles want.
3370 static bool isSHUFPMask(ArrayRef<int> Mask, EVT VT, bool HasAVX,
3371 bool Commuted = false) {
3372 if (!HasAVX && VT.getSizeInBits() == 256)
3375 unsigned NumElems = VT.getVectorNumElements();
3376 unsigned NumLanes = VT.getSizeInBits()/128;
3377 unsigned NumLaneElems = NumElems/NumLanes;
3379 if (NumLaneElems != 2 && NumLaneElems != 4)
3382 // VSHUFPSY divides the resulting vector into 4 chunks.
3383 // The sources are also splitted into 4 chunks, and each destination
3384 // chunk must come from a different source chunk.
3386 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
3387 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
3389 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
3390 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
3392 // VSHUFPDY divides the resulting vector into 4 chunks.
3393 // The sources are also splitted into 4 chunks, and each destination
3394 // chunk must come from a different source chunk.
3396 // SRC1 => X3 X2 X1 X0
3397 // SRC2 => Y3 Y2 Y1 Y0
3399 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
3401 unsigned HalfLaneElems = NumLaneElems/2;
3402 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
3403 for (unsigned i = 0; i != NumLaneElems; ++i) {
3404 int Idx = Mask[i+l];
3405 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
3406 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
3408 // For VSHUFPSY, the mask of the second half must be the same as the
3409 // first but with the appropriate offsets. This works in the same way as
3410 // VPERMILPS works with masks.
3411 if (NumElems != 8 || l == 0 || Mask[i] < 0)
3413 if (!isUndefOrEqual(Idx, Mask[i]+l))
3421 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3422 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3423 static bool isMOVHLPSMask(ArrayRef<int> Mask, EVT VT) {
3424 unsigned NumElems = VT.getVectorNumElements();
3426 if (VT.getSizeInBits() != 128)
3432 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3433 return isUndefOrEqual(Mask[0], 6) &&
3434 isUndefOrEqual(Mask[1], 7) &&
3435 isUndefOrEqual(Mask[2], 2) &&
3436 isUndefOrEqual(Mask[3], 3);
3439 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3440 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3442 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, EVT VT) {
3443 unsigned NumElems = VT.getVectorNumElements();
3445 if (VT.getSizeInBits() != 128)
3451 return isUndefOrEqual(Mask[0], 2) &&
3452 isUndefOrEqual(Mask[1], 3) &&
3453 isUndefOrEqual(Mask[2], 2) &&
3454 isUndefOrEqual(Mask[3], 3);
3457 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3458 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3459 static bool isMOVLPMask(ArrayRef<int> Mask, EVT VT) {
3460 if (VT.getSizeInBits() != 128)
3463 unsigned NumElems = VT.getVectorNumElements();
3465 if (NumElems != 2 && NumElems != 4)
3468 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3469 if (!isUndefOrEqual(Mask[i], i + NumElems))
3472 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
3473 if (!isUndefOrEqual(Mask[i], i))
3479 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3480 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3481 static bool isMOVLHPSMask(ArrayRef<int> Mask, EVT VT) {
3482 unsigned NumElems = VT.getVectorNumElements();
3484 if ((NumElems != 2 && NumElems != 4)
3485 || VT.getSizeInBits() > 128)
3488 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3489 if (!isUndefOrEqual(Mask[i], i))
3492 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3493 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
3500 // Some special combinations that can be optimized.
3503 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
3504 SelectionDAG &DAG) {
3505 EVT VT = SVOp->getValueType(0);
3506 DebugLoc dl = SVOp->getDebugLoc();
3508 if (VT != MVT::v8i32 && VT != MVT::v8f32)
3511 ArrayRef<int> Mask = SVOp->getMask();
3513 // These are the special masks that may be optimized.
3514 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
3515 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
3516 bool MatchEvenMask = true;
3517 bool MatchOddMask = true;
3518 for (int i=0; i<8; ++i) {
3519 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
3520 MatchEvenMask = false;
3521 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
3522 MatchOddMask = false;
3524 static const int CompactionMaskEven[] = {0, 2, -1, -1, 4, 6, -1, -1};
3525 static const int CompactionMaskOdd [] = {1, 3, -1, -1, 5, 7, -1, -1};
3527 const int *CompactionMask;
3529 CompactionMask = CompactionMaskEven;
3530 else if (MatchOddMask)
3531 CompactionMask = CompactionMaskOdd;
3535 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
3537 SDValue Op0 = DAG.getVectorShuffle(VT, dl, SVOp->getOperand(0),
3538 UndefNode, CompactionMask);
3539 SDValue Op1 = DAG.getVectorShuffle(VT, dl, SVOp->getOperand(1),
3540 UndefNode, CompactionMask);
3541 static const int UnpackMask[] = {0, 8, 1, 9, 4, 12, 5, 13};
3542 return DAG.getVectorShuffle(VT, dl, Op0, Op1, UnpackMask);
3545 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
3546 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
3547 static bool isUNPCKLMask(ArrayRef<int> Mask, EVT VT,
3548 bool HasAVX2, bool V2IsSplat = false) {
3549 unsigned NumElts = VT.getVectorNumElements();
3551 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3552 "Unsupported vector type for unpckh");
3554 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3555 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3558 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3559 // independently on 128-bit lanes.
3560 unsigned NumLanes = VT.getSizeInBits()/128;
3561 unsigned NumLaneElts = NumElts/NumLanes;
3563 for (unsigned l = 0; l != NumLanes; ++l) {
3564 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts;
3565 i != (l+1)*NumLaneElts;
3568 int BitI1 = Mask[i+1];
3569 if (!isUndefOrEqual(BitI, j))
3572 if (!isUndefOrEqual(BitI1, NumElts))
3575 if (!isUndefOrEqual(BitI1, j + NumElts))
3584 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
3585 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
3586 static bool isUNPCKHMask(ArrayRef<int> Mask, EVT VT,
3587 bool HasAVX2, bool V2IsSplat = false) {
3588 unsigned NumElts = VT.getVectorNumElements();
3590 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3591 "Unsupported vector type for unpckh");
3593 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3594 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3597 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3598 // independently on 128-bit lanes.
3599 unsigned NumLanes = VT.getSizeInBits()/128;
3600 unsigned NumLaneElts = NumElts/NumLanes;
3602 for (unsigned l = 0; l != NumLanes; ++l) {
3603 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2;
3604 i != (l+1)*NumLaneElts; i += 2, ++j) {
3606 int BitI1 = Mask[i+1];
3607 if (!isUndefOrEqual(BitI, j))
3610 if (isUndefOrEqual(BitI1, NumElts))
3613 if (!isUndefOrEqual(BitI1, j+NumElts))
3621 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
3622 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
3624 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, EVT VT,
3626 unsigned NumElts = VT.getVectorNumElements();
3628 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3629 "Unsupported vector type for unpckh");
3631 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3632 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3635 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
3636 // FIXME: Need a better way to get rid of this, there's no latency difference
3637 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
3638 // the former later. We should also remove the "_undef" special mask.
3639 if (NumElts == 4 && VT.getSizeInBits() == 256)
3642 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3643 // independently on 128-bit lanes.
3644 unsigned NumLanes = VT.getSizeInBits()/128;
3645 unsigned NumLaneElts = NumElts/NumLanes;
3647 for (unsigned l = 0; l != NumLanes; ++l) {
3648 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts;
3649 i != (l+1)*NumLaneElts;
3652 int BitI1 = Mask[i+1];
3654 if (!isUndefOrEqual(BitI, j))
3656 if (!isUndefOrEqual(BitI1, j))
3664 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
3665 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
3667 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, EVT VT, bool HasAVX2) {
3668 unsigned NumElts = VT.getVectorNumElements();
3670 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3671 "Unsupported vector type for unpckh");
3673 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3674 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3677 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3678 // independently on 128-bit lanes.
3679 unsigned NumLanes = VT.getSizeInBits()/128;
3680 unsigned NumLaneElts = NumElts/NumLanes;
3682 for (unsigned l = 0; l != NumLanes; ++l) {
3683 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2;
3684 i != (l+1)*NumLaneElts; i += 2, ++j) {
3686 int BitI1 = Mask[i+1];
3687 if (!isUndefOrEqual(BitI, j))
3689 if (!isUndefOrEqual(BitI1, j))
3696 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
3697 /// specifies a shuffle of elements that is suitable for input to MOVSS,
3698 /// MOVSD, and MOVD, i.e. setting the lowest element.
3699 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
3700 if (VT.getVectorElementType().getSizeInBits() < 32)
3702 if (VT.getSizeInBits() == 256)
3705 unsigned NumElts = VT.getVectorNumElements();
3707 if (!isUndefOrEqual(Mask[0], NumElts))
3710 for (unsigned i = 1; i != NumElts; ++i)
3711 if (!isUndefOrEqual(Mask[i], i))
3717 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
3718 /// as permutations between 128-bit chunks or halves. As an example: this
3720 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
3721 /// The first half comes from the second half of V1 and the second half from the
3722 /// the second half of V2.
3723 static bool isVPERM2X128Mask(ArrayRef<int> Mask, EVT VT, bool HasAVX) {
3724 if (!HasAVX || VT.getSizeInBits() != 256)
3727 // The shuffle result is divided into half A and half B. In total the two
3728 // sources have 4 halves, namely: C, D, E, F. The final values of A and
3729 // B must come from C, D, E or F.
3730 unsigned HalfSize = VT.getVectorNumElements()/2;
3731 bool MatchA = false, MatchB = false;
3733 // Check if A comes from one of C, D, E, F.
3734 for (unsigned Half = 0; Half != 4; ++Half) {
3735 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
3741 // Check if B comes from one of C, D, E, F.
3742 for (unsigned Half = 0; Half != 4; ++Half) {
3743 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
3749 return MatchA && MatchB;
3752 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
3753 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
3754 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
3755 EVT VT = SVOp->getValueType(0);
3757 unsigned HalfSize = VT.getVectorNumElements()/2;
3759 unsigned FstHalf = 0, SndHalf = 0;
3760 for (unsigned i = 0; i < HalfSize; ++i) {
3761 if (SVOp->getMaskElt(i) > 0) {
3762 FstHalf = SVOp->getMaskElt(i)/HalfSize;
3766 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
3767 if (SVOp->getMaskElt(i) > 0) {
3768 SndHalf = SVOp->getMaskElt(i)/HalfSize;
3773 return (FstHalf | (SndHalf << 4));
3776 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
3777 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
3778 /// Note that VPERMIL mask matching is different depending whether theunderlying
3779 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
3780 /// to the same elements of the low, but to the higher half of the source.
3781 /// In VPERMILPD the two lanes could be shuffled independently of each other
3782 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
3783 static bool isVPERMILPMask(ArrayRef<int> Mask, EVT VT, bool HasAVX) {
3787 unsigned NumElts = VT.getVectorNumElements();
3788 // Only match 256-bit with 32/64-bit types
3789 if (VT.getSizeInBits() != 256 || (NumElts != 4 && NumElts != 8))
3792 unsigned NumLanes = VT.getSizeInBits()/128;
3793 unsigned LaneSize = NumElts/NumLanes;
3794 for (unsigned l = 0; l != NumElts; l += LaneSize) {
3795 for (unsigned i = 0; i != LaneSize; ++i) {
3796 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
3798 if (NumElts != 8 || l == 0)
3800 // VPERMILPS handling
3803 if (!isUndefOrEqual(Mask[i+l], Mask[i]+l))
3811 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
3812 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
3813 /// element of vector 2 and the other elements to come from vector 1 in order.
3814 static bool isCommutedMOVLMask(ArrayRef<int> Mask, EVT VT,
3815 bool V2IsSplat = false, bool V2IsUndef = false) {
3816 unsigned NumOps = VT.getVectorNumElements();
3817 if (VT.getSizeInBits() == 256)
3819 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
3822 if (!isUndefOrEqual(Mask[0], 0))
3825 for (unsigned i = 1; i != NumOps; ++i)
3826 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
3827 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
3828 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
3834 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3835 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
3836 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
3837 static bool isMOVSHDUPMask(ArrayRef<int> Mask, EVT VT,
3838 const X86Subtarget *Subtarget) {
3839 if (!Subtarget->hasSSE3())
3842 unsigned NumElems = VT.getVectorNumElements();
3844 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3845 (VT.getSizeInBits() == 256 && NumElems != 8))
3848 // "i+1" is the value the indexed mask element must have
3849 for (unsigned i = 0; i != NumElems; i += 2)
3850 if (!isUndefOrEqual(Mask[i], i+1) ||
3851 !isUndefOrEqual(Mask[i+1], i+1))
3857 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3858 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
3859 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
3860 static bool isMOVSLDUPMask(ArrayRef<int> Mask, EVT VT,
3861 const X86Subtarget *Subtarget) {
3862 if (!Subtarget->hasSSE3())
3865 unsigned NumElems = VT.getVectorNumElements();
3867 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3868 (VT.getSizeInBits() == 256 && NumElems != 8))
3871 // "i" is the value the indexed mask element must have
3872 for (unsigned i = 0; i != NumElems; i += 2)
3873 if (!isUndefOrEqual(Mask[i], i) ||
3874 !isUndefOrEqual(Mask[i+1], i))
3880 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
3881 /// specifies a shuffle of elements that is suitable for input to 256-bit
3882 /// version of MOVDDUP.
3883 static bool isMOVDDUPYMask(ArrayRef<int> Mask, EVT VT, bool HasAVX) {
3884 unsigned NumElts = VT.getVectorNumElements();
3886 if (!HasAVX || VT.getSizeInBits() != 256 || NumElts != 4)
3889 for (unsigned i = 0; i != NumElts/2; ++i)
3890 if (!isUndefOrEqual(Mask[i], 0))
3892 for (unsigned i = NumElts/2; i != NumElts; ++i)
3893 if (!isUndefOrEqual(Mask[i], NumElts/2))
3898 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3899 /// specifies a shuffle of elements that is suitable for input to 128-bit
3900 /// version of MOVDDUP.
3901 static bool isMOVDDUPMask(ArrayRef<int> Mask, EVT VT) {
3902 if (VT.getSizeInBits() != 128)
3905 unsigned e = VT.getVectorNumElements() / 2;
3906 for (unsigned i = 0; i != e; ++i)
3907 if (!isUndefOrEqual(Mask[i], i))
3909 for (unsigned i = 0; i != e; ++i)
3910 if (!isUndefOrEqual(Mask[e+i], i))
3915 /// isVEXTRACTF128Index - Return true if the specified
3916 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
3917 /// suitable for input to VEXTRACTF128.
3918 bool X86::isVEXTRACTF128Index(SDNode *N) {
3919 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3922 // The index should be aligned on a 128-bit boundary.
3924 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3926 unsigned VL = N->getValueType(0).getVectorNumElements();
3927 unsigned VBits = N->getValueType(0).getSizeInBits();
3928 unsigned ElSize = VBits / VL;
3929 bool Result = (Index * ElSize) % 128 == 0;
3934 /// isVINSERTF128Index - Return true if the specified INSERT_SUBVECTOR
3935 /// operand specifies a subvector insert that is suitable for input to
3937 bool X86::isVINSERTF128Index(SDNode *N) {
3938 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3941 // The index should be aligned on a 128-bit boundary.
3943 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3945 unsigned VL = N->getValueType(0).getVectorNumElements();
3946 unsigned VBits = N->getValueType(0).getSizeInBits();
3947 unsigned ElSize = VBits / VL;
3948 bool Result = (Index * ElSize) % 128 == 0;
3953 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
3954 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
3955 /// Handles 128-bit and 256-bit.
3956 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
3957 EVT VT = N->getValueType(0);
3959 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3960 "Unsupported vector type for PSHUF/SHUFP");
3962 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
3963 // independently on 128-bit lanes.
3964 unsigned NumElts = VT.getVectorNumElements();
3965 unsigned NumLanes = VT.getSizeInBits()/128;
3966 unsigned NumLaneElts = NumElts/NumLanes;
3968 assert((NumLaneElts == 2 || NumLaneElts == 4) &&
3969 "Only supports 2 or 4 elements per lane");
3971 unsigned Shift = (NumLaneElts == 4) ? 1 : 0;
3973 for (unsigned i = 0; i != NumElts; ++i) {
3974 int Elt = N->getMaskElt(i);
3975 if (Elt < 0) continue;
3976 Elt &= NumLaneElts - 1;
3977 unsigned ShAmt = (i << Shift) % 8;
3978 Mask |= Elt << ShAmt;
3984 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
3985 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
3986 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
3987 EVT VT = N->getValueType(0);
3989 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
3990 "Unsupported vector type for PSHUFHW");
3992 unsigned NumElts = VT.getVectorNumElements();
3995 for (unsigned l = 0; l != NumElts; l += 8) {
3996 // 8 nodes per lane, but we only care about the last 4.
3997 for (unsigned i = 0; i < 4; ++i) {
3998 int Elt = N->getMaskElt(l+i+4);
3999 if (Elt < 0) continue;
4000 Elt &= 0x3; // only 2-bits.
4001 Mask |= Elt << (i * 2);
4008 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4009 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4010 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4011 EVT VT = N->getValueType(0);
4013 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4014 "Unsupported vector type for PSHUFHW");
4016 unsigned NumElts = VT.getVectorNumElements();
4019 for (unsigned l = 0; l != NumElts; l += 8) {
4020 // 8 nodes per lane, but we only care about the first 4.
4021 for (unsigned i = 0; i < 4; ++i) {
4022 int Elt = N->getMaskElt(l+i);
4023 if (Elt < 0) continue;
4024 Elt &= 0x3; // only 2-bits
4025 Mask |= Elt << (i * 2);
4032 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
4033 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
4034 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4035 EVT VT = SVOp->getValueType(0);
4036 unsigned EltSize = VT.getVectorElementType().getSizeInBits() >> 3;
4038 unsigned NumElts = VT.getVectorNumElements();
4039 unsigned NumLanes = VT.getSizeInBits()/128;
4040 unsigned NumLaneElts = NumElts/NumLanes;
4044 for (i = 0; i != NumElts; ++i) {
4045 Val = SVOp->getMaskElt(i);
4049 if (Val >= (int)NumElts)
4050 Val -= NumElts - NumLaneElts;
4052 assert(Val - i > 0 && "PALIGNR imm should be positive");
4053 return (Val - i) * EltSize;
4056 /// getExtractVEXTRACTF128Immediate - Return the appropriate immediate
4057 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4059 unsigned X86::getExtractVEXTRACTF128Immediate(SDNode *N) {
4060 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4061 llvm_unreachable("Illegal extract subvector for VEXTRACTF128");
4064 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4066 EVT VecVT = N->getOperand(0).getValueType();
4067 EVT ElVT = VecVT.getVectorElementType();
4069 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
4070 return Index / NumElemsPerChunk;
4073 /// getInsertVINSERTF128Immediate - Return the appropriate immediate
4074 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4076 unsigned X86::getInsertVINSERTF128Immediate(SDNode *N) {
4077 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4078 llvm_unreachable("Illegal insert subvector for VINSERTF128");
4081 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4083 EVT VecVT = N->getValueType(0);
4084 EVT ElVT = VecVT.getVectorElementType();
4086 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
4087 return Index / NumElemsPerChunk;
4090 /// getShuffleCLImmediate - Return the appropriate immediate to shuffle
4091 /// the specified VECTOR_SHUFFLE mask with VPERMQ and VPERMPD instructions.
4092 /// Handles 256-bit.
4093 static unsigned getShuffleCLImmediate(ShuffleVectorSDNode *N) {
4094 EVT VT = N->getValueType(0);
4096 unsigned NumElts = VT.getVectorNumElements();
4098 assert((VT.is256BitVector() && NumElts == 4) &&
4099 "Unsupported vector type for VPERMQ/VPERMPD");
4102 for (unsigned i = 0; i != NumElts; ++i) {
4103 int Elt = N->getMaskElt(i);
4106 Mask |= Elt << (i*2);
4111 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4113 bool X86::isZeroNode(SDValue Elt) {
4114 return ((isa<ConstantSDNode>(Elt) &&
4115 cast<ConstantSDNode>(Elt)->isNullValue()) ||
4116 (isa<ConstantFPSDNode>(Elt) &&
4117 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
4120 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
4121 /// their permute mask.
4122 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
4123 SelectionDAG &DAG) {
4124 EVT VT = SVOp->getValueType(0);
4125 unsigned NumElems = VT.getVectorNumElements();
4126 SmallVector<int, 8> MaskVec;
4128 for (unsigned i = 0; i != NumElems; ++i) {
4129 int Idx = SVOp->getMaskElt(i);
4131 if (Idx < (int)NumElems)
4136 MaskVec.push_back(Idx);
4138 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
4139 SVOp->getOperand(0), &MaskVec[0]);
4142 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4143 /// match movhlps. The lower half elements should come from upper half of
4144 /// V1 (and in order), and the upper half elements should come from the upper
4145 /// half of V2 (and in order).
4146 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, EVT VT) {
4147 if (VT.getSizeInBits() != 128)
4149 if (VT.getVectorNumElements() != 4)
4151 for (unsigned i = 0, e = 2; i != e; ++i)
4152 if (!isUndefOrEqual(Mask[i], i+2))
4154 for (unsigned i = 2; i != 4; ++i)
4155 if (!isUndefOrEqual(Mask[i], i+4))
4160 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4161 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4163 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
4164 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4166 N = N->getOperand(0).getNode();
4167 if (!ISD::isNON_EXTLoad(N))
4170 *LD = cast<LoadSDNode>(N);
4174 // Test whether the given value is a vector value which will be legalized
4176 static bool WillBeConstantPoolLoad(SDNode *N) {
4177 if (N->getOpcode() != ISD::BUILD_VECTOR)
4180 // Check for any non-constant elements.
4181 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4182 switch (N->getOperand(i).getNode()->getOpcode()) {
4184 case ISD::ConstantFP:
4191 // Vectors of all-zeros and all-ones are materialized with special
4192 // instructions rather than being loaded.
4193 return !ISD::isBuildVectorAllZeros(N) &&
4194 !ISD::isBuildVectorAllOnes(N);
4197 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4198 /// match movlp{s|d}. The lower half elements should come from lower half of
4199 /// V1 (and in order), and the upper half elements should come from the upper
4200 /// half of V2 (and in order). And since V1 will become the source of the
4201 /// MOVLP, it must be either a vector load or a scalar load to vector.
4202 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
4203 ArrayRef<int> Mask, EVT VT) {
4204 if (VT.getSizeInBits() != 128)
4207 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
4209 // Is V2 is a vector load, don't do this transformation. We will try to use
4210 // load folding shufps op.
4211 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
4214 unsigned NumElems = VT.getVectorNumElements();
4216 if (NumElems != 2 && NumElems != 4)
4218 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4219 if (!isUndefOrEqual(Mask[i], i))
4221 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4222 if (!isUndefOrEqual(Mask[i], i+NumElems))
4227 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
4229 static bool isSplatVector(SDNode *N) {
4230 if (N->getOpcode() != ISD::BUILD_VECTOR)
4233 SDValue SplatValue = N->getOperand(0);
4234 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
4235 if (N->getOperand(i) != SplatValue)
4240 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
4241 /// to an zero vector.
4242 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
4243 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
4244 SDValue V1 = N->getOperand(0);
4245 SDValue V2 = N->getOperand(1);
4246 unsigned NumElems = N->getValueType(0).getVectorNumElements();
4247 for (unsigned i = 0; i != NumElems; ++i) {
4248 int Idx = N->getMaskElt(i);
4249 if (Idx >= (int)NumElems) {
4250 unsigned Opc = V2.getOpcode();
4251 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4253 if (Opc != ISD::BUILD_VECTOR ||
4254 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
4256 } else if (Idx >= 0) {
4257 unsigned Opc = V1.getOpcode();
4258 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
4260 if (Opc != ISD::BUILD_VECTOR ||
4261 !X86::isZeroNode(V1.getOperand(Idx)))
4268 /// getZeroVector - Returns a vector of specified type with all zero elements.
4270 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4271 SelectionDAG &DAG, DebugLoc dl) {
4272 assert(VT.isVector() && "Expected a vector type");
4273 unsigned Size = VT.getSizeInBits();
4275 // Always build SSE zero vectors as <4 x i32> bitcasted
4276 // to their dest type. This ensures they get CSE'd.
4278 if (Size == 128) { // SSE
4279 if (Subtarget->hasSSE2()) { // SSE2
4280 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4281 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4283 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4284 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4286 } else if (Size == 256) { // AVX
4287 if (Subtarget->hasAVX2()) { // AVX2
4288 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4289 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4290 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8);
4292 // 256-bit logic and arithmetic instructions in AVX are all
4293 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4294 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4295 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4296 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8);
4299 llvm_unreachable("Unexpected vector type");
4301 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4304 /// getOnesVector - Returns a vector of specified type with all bits set.
4305 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4306 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4307 /// Then bitcast to their original type, ensuring they get CSE'd.
4308 static SDValue getOnesVector(EVT VT, bool HasAVX2, SelectionDAG &DAG,
4310 assert(VT.isVector() && "Expected a vector type");
4311 unsigned Size = VT.getSizeInBits();
4313 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
4316 if (HasAVX2) { // AVX2
4317 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4318 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8);
4320 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4321 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4323 } else if (Size == 128) {
4324 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4326 llvm_unreachable("Unexpected vector type");
4328 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4331 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
4332 /// that point to V2 points to its first element.
4333 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
4334 for (unsigned i = 0; i != NumElems; ++i) {
4335 if (Mask[i] > (int)NumElems) {
4341 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4342 /// operation of specified width.
4343 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4345 unsigned NumElems = VT.getVectorNumElements();
4346 SmallVector<int, 8> Mask;
4347 Mask.push_back(NumElems);
4348 for (unsigned i = 1; i != NumElems; ++i)
4350 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4353 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4354 static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4356 unsigned NumElems = VT.getVectorNumElements();
4357 SmallVector<int, 8> Mask;
4358 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4360 Mask.push_back(i + NumElems);
4362 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4365 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4366 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4368 unsigned NumElems = VT.getVectorNumElements();
4369 SmallVector<int, 8> Mask;
4370 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4371 Mask.push_back(i + Half);
4372 Mask.push_back(i + NumElems + Half);
4374 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4377 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
4378 // a generic shuffle instruction because the target has no such instructions.
4379 // Generate shuffles which repeat i16 and i8 several times until they can be
4380 // represented by v4f32 and then be manipulated by target suported shuffles.
4381 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
4382 EVT VT = V.getValueType();
4383 int NumElems = VT.getVectorNumElements();
4384 DebugLoc dl = V.getDebugLoc();
4386 while (NumElems > 4) {
4387 if (EltNo < NumElems/2) {
4388 V = getUnpackl(DAG, dl, VT, V, V);
4390 V = getUnpackh(DAG, dl, VT, V, V);
4391 EltNo -= NumElems/2;
4398 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
4399 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
4400 EVT VT = V.getValueType();
4401 DebugLoc dl = V.getDebugLoc();
4402 unsigned Size = VT.getSizeInBits();
4405 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
4406 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
4407 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
4409 } else if (Size == 256) {
4410 // To use VPERMILPS to splat scalars, the second half of indicies must
4411 // refer to the higher part, which is a duplication of the lower one,
4412 // because VPERMILPS can only handle in-lane permutations.
4413 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
4414 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
4416 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
4417 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
4420 llvm_unreachable("Vector size not supported");
4422 return DAG.getNode(ISD::BITCAST, dl, VT, V);
4425 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
4426 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
4427 EVT SrcVT = SV->getValueType(0);
4428 SDValue V1 = SV->getOperand(0);
4429 DebugLoc dl = SV->getDebugLoc();
4431 int EltNo = SV->getSplatIndex();
4432 int NumElems = SrcVT.getVectorNumElements();
4433 unsigned Size = SrcVT.getSizeInBits();
4435 assert(((Size == 128 && NumElems > 4) || Size == 256) &&
4436 "Unknown how to promote splat for type");
4438 // Extract the 128-bit part containing the splat element and update
4439 // the splat element index when it refers to the higher register.
4441 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
4442 if (EltNo >= NumElems/2)
4443 EltNo -= NumElems/2;
4446 // All i16 and i8 vector types can't be used directly by a generic shuffle
4447 // instruction because the target has no such instruction. Generate shuffles
4448 // which repeat i16 and i8 several times until they fit in i32, and then can
4449 // be manipulated by target suported shuffles.
4450 EVT EltVT = SrcVT.getVectorElementType();
4451 if (EltVT == MVT::i8 || EltVT == MVT::i16)
4452 V1 = PromoteSplati8i16(V1, DAG, EltNo);
4454 // Recreate the 256-bit vector and place the same 128-bit vector
4455 // into the low and high part. This is necessary because we want
4456 // to use VPERM* to shuffle the vectors
4458 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
4461 return getLegalSplat(DAG, V1, EltNo);
4464 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4465 /// vector of zero or undef vector. This produces a shuffle where the low
4466 /// element of V2 is swizzled into the zero/undef vector, landing at element
4467 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4468 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4470 const X86Subtarget *Subtarget,
4471 SelectionDAG &DAG) {
4472 EVT VT = V2.getValueType();
4474 ? getZeroVector(VT, Subtarget, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT);
4475 unsigned NumElems = VT.getVectorNumElements();
4476 SmallVector<int, 16> MaskVec;
4477 for (unsigned i = 0; i != NumElems; ++i)
4478 // If this is the insertion idx, put the low elt of V2 here.
4479 MaskVec.push_back(i == Idx ? NumElems : i);
4480 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
4483 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
4484 /// target specific opcode. Returns true if the Mask could be calculated.
4485 /// Sets IsUnary to true if only uses one source.
4486 static bool getTargetShuffleMask(SDNode *N, MVT VT,
4487 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4488 unsigned NumElems = VT.getVectorNumElements();
4492 switch(N->getOpcode()) {
4494 ImmN = N->getOperand(N->getNumOperands()-1);
4495 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4497 case X86ISD::UNPCKH:
4498 DecodeUNPCKHMask(VT, Mask);
4500 case X86ISD::UNPCKL:
4501 DecodeUNPCKLMask(VT, Mask);
4503 case X86ISD::MOVHLPS:
4504 DecodeMOVHLPSMask(NumElems, Mask);
4506 case X86ISD::MOVLHPS:
4507 DecodeMOVLHPSMask(NumElems, Mask);
4509 case X86ISD::PSHUFD:
4510 case X86ISD::VPERMILP:
4511 ImmN = N->getOperand(N->getNumOperands()-1);
4512 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4515 case X86ISD::PSHUFHW:
4516 ImmN = N->getOperand(N->getNumOperands()-1);
4517 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4520 case X86ISD::PSHUFLW:
4521 ImmN = N->getOperand(N->getNumOperands()-1);
4522 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4525 case X86ISD::VPERMI:
4526 ImmN = N->getOperand(N->getNumOperands()-1);
4527 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4531 case X86ISD::MOVSD: {
4532 // The index 0 always comes from the first element of the second source,
4533 // this is why MOVSS and MOVSD are used in the first place. The other
4534 // elements come from the other positions of the first source vector
4535 Mask.push_back(NumElems);
4536 for (unsigned i = 1; i != NumElems; ++i) {
4541 case X86ISD::VPERM2X128:
4542 ImmN = N->getOperand(N->getNumOperands()-1);
4543 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4544 if (Mask.empty()) return false;
4546 case X86ISD::MOVDDUP:
4547 case X86ISD::MOVLHPD:
4548 case X86ISD::MOVLPD:
4549 case X86ISD::MOVLPS:
4550 case X86ISD::MOVSHDUP:
4551 case X86ISD::MOVSLDUP:
4552 case X86ISD::PALIGN:
4553 // Not yet implemented
4555 default: llvm_unreachable("unknown target shuffle node");
4561 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4562 /// element of the result of the vector shuffle.
4563 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
4566 return SDValue(); // Limit search depth.
4568 SDValue V = SDValue(N, 0);
4569 EVT VT = V.getValueType();
4570 unsigned Opcode = V.getOpcode();
4572 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4573 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4574 int Elt = SV->getMaskElt(Index);
4577 return DAG.getUNDEF(VT.getVectorElementType());
4579 unsigned NumElems = VT.getVectorNumElements();
4580 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
4581 : SV->getOperand(1);
4582 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
4585 // Recurse into target specific vector shuffles to find scalars.
4586 if (isTargetShuffle(Opcode)) {
4587 MVT ShufVT = V.getValueType().getSimpleVT();
4588 unsigned NumElems = ShufVT.getVectorNumElements();
4589 SmallVector<int, 16> ShuffleMask;
4593 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
4596 int Elt = ShuffleMask[Index];
4598 return DAG.getUNDEF(ShufVT.getVectorElementType());
4600 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
4602 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
4606 // Actual nodes that may contain scalar elements
4607 if (Opcode == ISD::BITCAST) {
4608 V = V.getOperand(0);
4609 EVT SrcVT = V.getValueType();
4610 unsigned NumElems = VT.getVectorNumElements();
4612 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4616 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4617 return (Index == 0) ? V.getOperand(0)
4618 : DAG.getUNDEF(VT.getVectorElementType());
4620 if (V.getOpcode() == ISD::BUILD_VECTOR)
4621 return V.getOperand(Index);
4626 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
4627 /// shuffle operation which come from a consecutively from a zero. The
4628 /// search can start in two different directions, from left or right.
4630 unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp, unsigned NumElems,
4631 bool ZerosFromLeft, SelectionDAG &DAG) {
4633 for (i = 0; i != NumElems; ++i) {
4634 unsigned Index = ZerosFromLeft ? i : NumElems-i-1;
4635 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
4636 if (!(Elt.getNode() &&
4637 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt))))
4644 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
4645 /// correspond consecutively to elements from one of the vector operands,
4646 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
4648 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
4649 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
4650 unsigned NumElems, unsigned &OpNum) {
4651 bool SeenV1 = false;
4652 bool SeenV2 = false;
4654 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
4655 int Idx = SVOp->getMaskElt(i);
4656 // Ignore undef indicies
4660 if (Idx < (int)NumElems)
4665 // Only accept consecutive elements from the same vector
4666 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
4670 OpNum = SeenV1 ? 0 : 1;
4674 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
4675 /// logical left shift of a vector.
4676 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4677 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4678 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4679 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4680 false /* check zeros from right */, DAG);
4686 // Considering the elements in the mask that are not consecutive zeros,
4687 // check if they consecutively come from only one of the source vectors.
4689 // V1 = {X, A, B, C} 0
4691 // vector_shuffle V1, V2 <1, 2, 3, X>
4693 if (!isShuffleMaskConsecutive(SVOp,
4694 0, // Mask Start Index
4695 NumElems-NumZeros, // Mask End Index(exclusive)
4696 NumZeros, // Where to start looking in the src vector
4697 NumElems, // Number of elements in vector
4698 OpSrc)) // Which source operand ?
4703 ShVal = SVOp->getOperand(OpSrc);
4707 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
4708 /// logical left shift of a vector.
4709 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4710 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4711 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4712 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4713 true /* check zeros from left */, DAG);
4719 // Considering the elements in the mask that are not consecutive zeros,
4720 // check if they consecutively come from only one of the source vectors.
4722 // 0 { A, B, X, X } = V2
4724 // vector_shuffle V1, V2 <X, X, 4, 5>
4726 if (!isShuffleMaskConsecutive(SVOp,
4727 NumZeros, // Mask Start Index
4728 NumElems, // Mask End Index(exclusive)
4729 0, // Where to start looking in the src vector
4730 NumElems, // Number of elements in vector
4731 OpSrc)) // Which source operand ?
4736 ShVal = SVOp->getOperand(OpSrc);
4740 /// isVectorShift - Returns true if the shuffle can be implemented as a
4741 /// logical left or right shift of a vector.
4742 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4743 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4744 // Although the logic below support any bitwidth size, there are no
4745 // shift instructions which handle more than 128-bit vectors.
4746 if (SVOp->getValueType(0).getSizeInBits() > 128)
4749 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
4750 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
4756 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
4758 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4759 unsigned NumNonZero, unsigned NumZero,
4761 const X86Subtarget* Subtarget,
4762 const TargetLowering &TLI) {
4766 DebugLoc dl = Op.getDebugLoc();
4769 for (unsigned i = 0; i < 16; ++i) {
4770 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4771 if (ThisIsNonZero && First) {
4773 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4775 V = DAG.getUNDEF(MVT::v8i16);
4780 SDValue ThisElt(0, 0), LastElt(0, 0);
4781 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4782 if (LastIsNonZero) {
4783 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4784 MVT::i16, Op.getOperand(i-1));
4786 if (ThisIsNonZero) {
4787 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4788 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4789 ThisElt, DAG.getConstant(8, MVT::i8));
4791 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4795 if (ThisElt.getNode())
4796 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
4797 DAG.getIntPtrConstant(i/2));
4801 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
4804 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
4806 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
4807 unsigned NumNonZero, unsigned NumZero,
4809 const X86Subtarget* Subtarget,
4810 const TargetLowering &TLI) {
4814 DebugLoc dl = Op.getDebugLoc();
4817 for (unsigned i = 0; i < 8; ++i) {
4818 bool isNonZero = (NonZeros & (1 << i)) != 0;
4822 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4824 V = DAG.getUNDEF(MVT::v8i16);
4827 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4828 MVT::v8i16, V, Op.getOperand(i),
4829 DAG.getIntPtrConstant(i));
4836 /// getVShift - Return a vector logical shift node.
4838 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
4839 unsigned NumBits, SelectionDAG &DAG,
4840 const TargetLowering &TLI, DebugLoc dl) {
4841 assert(VT.getSizeInBits() == 128 && "Unknown type for VShift");
4842 EVT ShVT = MVT::v2i64;
4843 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
4844 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
4845 return DAG.getNode(ISD::BITCAST, dl, VT,
4846 DAG.getNode(Opc, dl, ShVT, SrcOp,
4847 DAG.getConstant(NumBits,
4848 TLI.getShiftAmountTy(SrcOp.getValueType()))));
4852 X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
4853 SelectionDAG &DAG) const {
4855 // Check if the scalar load can be widened into a vector load. And if
4856 // the address is "base + cst" see if the cst can be "absorbed" into
4857 // the shuffle mask.
4858 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
4859 SDValue Ptr = LD->getBasePtr();
4860 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
4862 EVT PVT = LD->getValueType(0);
4863 if (PVT != MVT::i32 && PVT != MVT::f32)
4868 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
4869 FI = FINode->getIndex();
4871 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
4872 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4873 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4874 Offset = Ptr.getConstantOperandVal(1);
4875 Ptr = Ptr.getOperand(0);
4880 // FIXME: 256-bit vector instructions don't require a strict alignment,
4881 // improve this code to support it better.
4882 unsigned RequiredAlign = VT.getSizeInBits()/8;
4883 SDValue Chain = LD->getChain();
4884 // Make sure the stack object alignment is at least 16 or 32.
4885 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4886 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
4887 if (MFI->isFixedObjectIndex(FI)) {
4888 // Can't change the alignment. FIXME: It's possible to compute
4889 // the exact stack offset and reference FI + adjust offset instead.
4890 // If someone *really* cares about this. That's the way to implement it.
4893 MFI->setObjectAlignment(FI, RequiredAlign);
4897 // (Offset % 16 or 32) must be multiple of 4. Then address is then
4898 // Ptr + (Offset & ~15).
4901 if ((Offset % RequiredAlign) & 3)
4903 int64_t StartOffset = Offset & ~(RequiredAlign-1);
4905 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(),
4906 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
4908 int EltNo = (Offset - StartOffset) >> 2;
4909 unsigned NumElems = VT.getVectorNumElements();
4911 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
4912 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
4913 LD->getPointerInfo().getWithOffset(StartOffset),
4914 false, false, false, 0);
4916 SmallVector<int, 8> Mask;
4917 for (unsigned i = 0; i != NumElems; ++i)
4918 Mask.push_back(EltNo);
4920 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
4926 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
4927 /// vector of type 'VT', see if the elements can be replaced by a single large
4928 /// load which has the same value as a build_vector whose operands are 'elts'.
4930 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
4932 /// FIXME: we'd also like to handle the case where the last elements are zero
4933 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
4934 /// There's even a handy isZeroNode for that purpose.
4935 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
4936 DebugLoc &DL, SelectionDAG &DAG) {
4937 EVT EltVT = VT.getVectorElementType();
4938 unsigned NumElems = Elts.size();
4940 LoadSDNode *LDBase = NULL;
4941 unsigned LastLoadedElt = -1U;
4943 // For each element in the initializer, see if we've found a load or an undef.
4944 // If we don't find an initial load element, or later load elements are
4945 // non-consecutive, bail out.
4946 for (unsigned i = 0; i < NumElems; ++i) {
4947 SDValue Elt = Elts[i];
4949 if (!Elt.getNode() ||
4950 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
4953 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
4955 LDBase = cast<LoadSDNode>(Elt.getNode());
4959 if (Elt.getOpcode() == ISD::UNDEF)
4962 LoadSDNode *LD = cast<LoadSDNode>(Elt);
4963 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
4968 // If we have found an entire vector of loads and undefs, then return a large
4969 // load of the entire vector width starting at the base pointer. If we found
4970 // consecutive loads for the low half, generate a vzext_load node.
4971 if (LastLoadedElt == NumElems - 1) {
4972 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
4973 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4974 LDBase->getPointerInfo(),
4975 LDBase->isVolatile(), LDBase->isNonTemporal(),
4976 LDBase->isInvariant(), 0);
4977 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4978 LDBase->getPointerInfo(),
4979 LDBase->isVolatile(), LDBase->isNonTemporal(),
4980 LDBase->isInvariant(), LDBase->getAlignment());
4982 if (NumElems == 4 && LastLoadedElt == 1 &&
4983 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
4984 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
4985 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
4987 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, 2, MVT::i64,
4988 LDBase->getPointerInfo(),
4989 LDBase->getAlignment(),
4990 false/*isVolatile*/, true/*ReadMem*/,
4992 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
4997 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
4998 /// to generate a splat value for the following cases:
4999 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
5000 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
5001 /// a scalar load, or a constant.
5002 /// The VBROADCAST node is returned when a pattern is found,
5003 /// or SDValue() otherwise.
5005 X86TargetLowering::LowerVectorBroadcast(SDValue &Op, SelectionDAG &DAG) const {
5006 if (!Subtarget->hasAVX())
5009 EVT VT = Op.getValueType();
5010 DebugLoc dl = Op.getDebugLoc();
5012 assert((VT.is128BitVector() || VT.is256BitVector()) &&
5013 "Unsupported vector type for broadcast.");
5018 switch (Op.getOpcode()) {
5020 // Unknown pattern found.
5023 case ISD::BUILD_VECTOR: {
5024 // The BUILD_VECTOR node must be a splat.
5025 if (!isSplatVector(Op.getNode()))
5028 Ld = Op.getOperand(0);
5029 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5030 Ld.getOpcode() == ISD::ConstantFP);
5032 // The suspected load node has several users. Make sure that all
5033 // of its users are from the BUILD_VECTOR node.
5034 // Constants may have multiple users.
5035 if (!ConstSplatVal && !Ld->hasNUsesOfValue(VT.getVectorNumElements(), 0))
5040 case ISD::VECTOR_SHUFFLE: {
5041 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5043 // Shuffles must have a splat mask where the first element is
5045 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5048 SDValue Sc = Op.getOperand(0);
5049 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5050 Sc.getOpcode() != ISD::BUILD_VECTOR)
5053 Ld = Sc.getOperand(0);
5054 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5055 Ld.getOpcode() == ISD::ConstantFP);
5057 // The scalar_to_vector node and the suspected
5058 // load node must have exactly one user.
5059 // Constants may have multiple users.
5060 if (!ConstSplatVal && (!Sc.hasOneUse() || !Ld.hasOneUse()))
5066 bool Is256 = VT.getSizeInBits() == 256;
5068 // Handle the broadcasting a single constant scalar from the constant pool
5069 // into a vector. On Sandybridge it is still better to load a constant vector
5070 // from the constant pool and not to broadcast it from a scalar.
5071 if (ConstSplatVal && Subtarget->hasAVX2()) {
5072 EVT CVT = Ld.getValueType();
5073 assert(!CVT.isVector() && "Must not broadcast a vector type");
5074 unsigned ScalarSize = CVT.getSizeInBits();
5076 if (ScalarSize == 32 || (Is256 && ScalarSize == 64)) {
5077 const Constant *C = 0;
5078 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5079 C = CI->getConstantIntValue();
5080 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5081 C = CF->getConstantFPValue();
5083 assert(C && "Invalid constant type");
5085 SDValue CP = DAG.getConstantPool(C, getPointerTy());
5086 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5087 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
5088 MachinePointerInfo::getConstantPool(),
5089 false, false, false, Alignment);
5091 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5095 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5096 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5098 // Handle AVX2 in-register broadcasts.
5099 if (!IsLoad && Subtarget->hasAVX2() &&
5100 (ScalarSize == 32 || (Is256 && ScalarSize == 64)))
5101 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5103 // The scalar source must be a normal load.
5107 if (ScalarSize == 32 || (Is256 && ScalarSize == 64))
5108 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5110 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5111 // double since there is no vbroadcastsd xmm
5112 if (Subtarget->hasAVX2() && Ld.getValueType().isInteger()) {
5113 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5114 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5117 // Unsupported broadcast.
5122 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5123 DebugLoc dl = Op.getDebugLoc();
5125 EVT VT = Op.getValueType();
5126 EVT ExtVT = VT.getVectorElementType();
5127 unsigned NumElems = Op.getNumOperands();
5129 // Vectors containing all zeros can be matched by pxor and xorps later
5130 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5131 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
5132 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
5133 if (VT == MVT::v4i32 || VT == MVT::v8i32)
5136 return getZeroVector(VT, Subtarget, DAG, dl);
5139 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
5140 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
5141 // vpcmpeqd on 256-bit vectors.
5142 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5143 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasAVX2()))
5146 return getOnesVector(VT, Subtarget->hasAVX2(), DAG, dl);
5149 SDValue Broadcast = LowerVectorBroadcast(Op, DAG);
5150 if (Broadcast.getNode())
5153 unsigned EVTBits = ExtVT.getSizeInBits();
5155 unsigned NumZero = 0;
5156 unsigned NumNonZero = 0;
5157 unsigned NonZeros = 0;
5158 bool IsAllConstants = true;
5159 SmallSet<SDValue, 8> Values;
5160 for (unsigned i = 0; i < NumElems; ++i) {
5161 SDValue Elt = Op.getOperand(i);
5162 if (Elt.getOpcode() == ISD::UNDEF)
5165 if (Elt.getOpcode() != ISD::Constant &&
5166 Elt.getOpcode() != ISD::ConstantFP)
5167 IsAllConstants = false;
5168 if (X86::isZeroNode(Elt))
5171 NonZeros |= (1 << i);
5176 // All undef vector. Return an UNDEF. All zero vectors were handled above.
5177 if (NumNonZero == 0)
5178 return DAG.getUNDEF(VT);
5180 // Special case for single non-zero, non-undef, element.
5181 if (NumNonZero == 1) {
5182 unsigned Idx = CountTrailingZeros_32(NonZeros);
5183 SDValue Item = Op.getOperand(Idx);
5185 // If this is an insertion of an i64 value on x86-32, and if the top bits of
5186 // the value are obviously zero, truncate the value to i32 and do the
5187 // insertion that way. Only do this if the value is non-constant or if the
5188 // value is a constant being inserted into element 0. It is cheaper to do
5189 // a constant pool load than it is to do a movd + shuffle.
5190 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5191 (!IsAllConstants || Idx == 0)) {
5192 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
5194 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5195 EVT VecVT = MVT::v4i32;
5196 unsigned VecElts = 4;
5198 // Truncate the value (which may itself be a constant) to i32, and
5199 // convert it to a vector with movd (S2V+shuffle to zero extend).
5200 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5201 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5202 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5204 // Now we have our 32-bit value zero extended in the low element of
5205 // a vector. If Idx != 0, swizzle it into place.
5207 SmallVector<int, 4> Mask;
5208 Mask.push_back(Idx);
5209 for (unsigned i = 1; i != VecElts; ++i)
5211 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
5214 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5218 // If we have a constant or non-constant insertion into the low element of
5219 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5220 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5221 // depending on what the source datatype is.
5224 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5226 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5227 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5228 if (VT.getSizeInBits() == 256) {
5229 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
5230 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
5231 Item, DAG.getIntPtrConstant(0));
5233 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!");
5234 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5235 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
5236 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5239 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
5240 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5241 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5242 if (VT.getSizeInBits() == 256) {
5243 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
5244 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
5246 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!");
5247 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5249 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5253 // Is it a vector logical left shift?
5254 if (NumElems == 2 && Idx == 1 &&
5255 X86::isZeroNode(Op.getOperand(0)) &&
5256 !X86::isZeroNode(Op.getOperand(1))) {
5257 unsigned NumBits = VT.getSizeInBits();
5258 return getVShift(true, VT,
5259 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5260 VT, Op.getOperand(1)),
5261 NumBits/2, DAG, *this, dl);
5264 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
5267 // Otherwise, if this is a vector with i32 or f32 elements, and the element
5268 // is a non-constant being inserted into an element other than the low one,
5269 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
5270 // movd/movss) to move this into the low element, then shuffle it into
5272 if (EVTBits == 32) {
5273 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5275 // Turn it into a shuffle of zero and zero-extended scalar to vector.
5276 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
5277 SmallVector<int, 8> MaskVec;
5278 for (unsigned i = 0; i != NumElems; ++i)
5279 MaskVec.push_back(i == Idx ? 0 : 1);
5280 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
5284 // Splat is obviously ok. Let legalizer expand it to a shuffle.
5285 if (Values.size() == 1) {
5286 if (EVTBits == 32) {
5287 // Instead of a shuffle like this:
5288 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
5289 // Check if it's possible to issue this instead.
5290 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
5291 unsigned Idx = CountTrailingZeros_32(NonZeros);
5292 SDValue Item = Op.getOperand(Idx);
5293 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
5294 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
5299 // A vector full of immediates; various special cases are already
5300 // handled, so this is best done with a single constant-pool load.
5304 // For AVX-length vectors, build the individual 128-bit pieces and use
5305 // shuffles to put them in place.
5306 if (VT.getSizeInBits() == 256) {
5307 SmallVector<SDValue, 32> V;
5308 for (unsigned i = 0; i != NumElems; ++i)
5309 V.push_back(Op.getOperand(i));
5311 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
5313 // Build both the lower and upper subvector.
5314 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2);
5315 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2],
5318 // Recreate the wider vector with the lower and upper part.
5319 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
5322 // Let legalizer expand 2-wide build_vectors.
5323 if (EVTBits == 64) {
5324 if (NumNonZero == 1) {
5325 // One half is zero or undef.
5326 unsigned Idx = CountTrailingZeros_32(NonZeros);
5327 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
5328 Op.getOperand(Idx));
5329 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
5334 // If element VT is < 32 bits, convert it to inserts into a zero vector.
5335 if (EVTBits == 8 && NumElems == 16) {
5336 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
5338 if (V.getNode()) return V;
5341 if (EVTBits == 16 && NumElems == 8) {
5342 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
5344 if (V.getNode()) return V;
5347 // If element VT is == 32 bits, turn it into a number of shuffles.
5348 SmallVector<SDValue, 8> V(NumElems);
5349 if (NumElems == 4 && NumZero > 0) {
5350 for (unsigned i = 0; i < 4; ++i) {
5351 bool isZero = !(NonZeros & (1 << i));
5353 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
5355 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5358 for (unsigned i = 0; i < 2; ++i) {
5359 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
5362 V[i] = V[i*2]; // Must be a zero vector.
5365 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
5368 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
5371 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
5376 bool Reverse1 = (NonZeros & 0x3) == 2;
5377 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
5381 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
5382 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
5384 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
5387 if (Values.size() > 1 && VT.getSizeInBits() == 128) {
5388 // Check for a build vector of consecutive loads.
5389 for (unsigned i = 0; i < NumElems; ++i)
5390 V[i] = Op.getOperand(i);
5392 // Check for elements which are consecutive loads.
5393 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG);
5397 // For SSE 4.1, use insertps to put the high elements into the low element.
5398 if (getSubtarget()->hasSSE41()) {
5400 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
5401 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
5403 Result = DAG.getUNDEF(VT);
5405 for (unsigned i = 1; i < NumElems; ++i) {
5406 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
5407 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
5408 Op.getOperand(i), DAG.getIntPtrConstant(i));
5413 // Otherwise, expand into a number of unpckl*, start by extending each of
5414 // our (non-undef) elements to the full vector width with the element in the
5415 // bottom slot of the vector (which generates no code for SSE).
5416 for (unsigned i = 0; i < NumElems; ++i) {
5417 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
5418 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5420 V[i] = DAG.getUNDEF(VT);
5423 // Next, we iteratively mix elements, e.g. for v4f32:
5424 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
5425 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
5426 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
5427 unsigned EltStride = NumElems >> 1;
5428 while (EltStride != 0) {
5429 for (unsigned i = 0; i < EltStride; ++i) {
5430 // If V[i+EltStride] is undef and this is the first round of mixing,
5431 // then it is safe to just drop this shuffle: V[i] is already in the
5432 // right place, the one element (since it's the first round) being
5433 // inserted as undef can be dropped. This isn't safe for successive
5434 // rounds because they will permute elements within both vectors.
5435 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
5436 EltStride == NumElems/2)
5439 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
5448 // LowerMMXCONCAT_VECTORS - We support concatenate two MMX registers and place
5449 // them in a MMX register. This is better than doing a stack convert.
5450 static SDValue LowerMMXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5451 DebugLoc dl = Op.getDebugLoc();
5452 EVT ResVT = Op.getValueType();
5454 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 ||
5455 ResVT == MVT::v8i16 || ResVT == MVT::v16i8);
5457 SDValue InVec = DAG.getNode(ISD::BITCAST,dl, MVT::v1i64, Op.getOperand(0));
5458 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
5459 InVec = Op.getOperand(1);
5460 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
5461 unsigned NumElts = ResVT.getVectorNumElements();
5462 VecOp = DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
5463 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp,
5464 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1));
5466 InVec = DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, InVec);
5467 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
5468 Mask[0] = 0; Mask[1] = 2;
5469 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask);
5471 return DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
5474 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
5475 // to create 256-bit vectors from two other 128-bit ones.
5476 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5477 DebugLoc dl = Op.getDebugLoc();
5478 EVT ResVT = Op.getValueType();
5480 assert(ResVT.getSizeInBits() == 256 && "Value type must be 256-bit wide");
5482 SDValue V1 = Op.getOperand(0);
5483 SDValue V2 = Op.getOperand(1);
5484 unsigned NumElems = ResVT.getVectorNumElements();
5486 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
5490 X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
5491 EVT ResVT = Op.getValueType();
5493 assert(Op.getNumOperands() == 2);
5494 assert((ResVT.getSizeInBits() == 128 || ResVT.getSizeInBits() == 256) &&
5495 "Unsupported CONCAT_VECTORS for value type");
5497 // We support concatenate two MMX registers and place them in a MMX register.
5498 // This is better than doing a stack convert.
5499 if (ResVT.is128BitVector())
5500 return LowerMMXCONCAT_VECTORS(Op, DAG);
5502 // 256-bit AVX can use the vinsertf128 instruction to create 256-bit vectors
5503 // from two other 128-bit ones.
5504 return LowerAVXCONCAT_VECTORS(Op, DAG);
5507 // Try to lower a shuffle node into a simple blend instruction.
5508 static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
5509 const X86Subtarget *Subtarget,
5510 SelectionDAG &DAG) {
5511 SDValue V1 = SVOp->getOperand(0);
5512 SDValue V2 = SVOp->getOperand(1);
5513 DebugLoc dl = SVOp->getDebugLoc();
5514 MVT VT = SVOp->getValueType(0).getSimpleVT();
5515 unsigned NumElems = VT.getVectorNumElements();
5517 if (!Subtarget->hasSSE41())
5523 switch (VT.SimpleTy) {
5524 default: return SDValue();
5526 ISDNo = X86ISD::BLENDPW;
5531 ISDNo = X86ISD::BLENDPS;
5536 ISDNo = X86ISD::BLENDPD;
5541 if (!Subtarget->hasAVX())
5543 ISDNo = X86ISD::BLENDPS;
5548 if (!Subtarget->hasAVX())
5550 ISDNo = X86ISD::BLENDPD;
5554 assert(ISDNo && "Invalid Op Number");
5556 unsigned MaskVals = 0;
5558 for (unsigned i = 0; i != NumElems; ++i) {
5559 int EltIdx = SVOp->getMaskElt(i);
5560 if (EltIdx == (int)i || EltIdx < 0)
5562 else if (EltIdx == (int)(i + NumElems))
5563 continue; // Bit is set to zero;
5568 V1 = DAG.getNode(ISD::BITCAST, dl, OpTy, V1);
5569 V2 = DAG.getNode(ISD::BITCAST, dl, OpTy, V2);
5570 SDValue Ret = DAG.getNode(ISDNo, dl, OpTy, V1, V2,
5571 DAG.getConstant(MaskVals, MVT::i32));
5572 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
5575 // v8i16 shuffles - Prefer shuffles in the following order:
5576 // 1. [all] pshuflw, pshufhw, optional move
5577 // 2. [ssse3] 1 x pshufb
5578 // 3. [ssse3] 2 x pshufb + 1 x por
5579 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
5581 X86TargetLowering::LowerVECTOR_SHUFFLEv8i16(SDValue Op,
5582 SelectionDAG &DAG) const {
5583 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5584 SDValue V1 = SVOp->getOperand(0);
5585 SDValue V2 = SVOp->getOperand(1);
5586 DebugLoc dl = SVOp->getDebugLoc();
5587 SmallVector<int, 8> MaskVals;
5589 // Determine if more than 1 of the words in each of the low and high quadwords
5590 // of the result come from the same quadword of one of the two inputs. Undef
5591 // mask values count as coming from any quadword, for better codegen.
5592 unsigned LoQuad[] = { 0, 0, 0, 0 };
5593 unsigned HiQuad[] = { 0, 0, 0, 0 };
5594 std::bitset<4> InputQuads;
5595 for (unsigned i = 0; i < 8; ++i) {
5596 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
5597 int EltIdx = SVOp->getMaskElt(i);
5598 MaskVals.push_back(EltIdx);
5607 InputQuads.set(EltIdx / 4);
5610 int BestLoQuad = -1;
5611 unsigned MaxQuad = 1;
5612 for (unsigned i = 0; i < 4; ++i) {
5613 if (LoQuad[i] > MaxQuad) {
5615 MaxQuad = LoQuad[i];
5619 int BestHiQuad = -1;
5621 for (unsigned i = 0; i < 4; ++i) {
5622 if (HiQuad[i] > MaxQuad) {
5624 MaxQuad = HiQuad[i];
5628 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
5629 // of the two input vectors, shuffle them into one input vector so only a
5630 // single pshufb instruction is necessary. If There are more than 2 input
5631 // quads, disable the next transformation since it does not help SSSE3.
5632 bool V1Used = InputQuads[0] || InputQuads[1];
5633 bool V2Used = InputQuads[2] || InputQuads[3];
5634 if (Subtarget->hasSSSE3()) {
5635 if (InputQuads.count() == 2 && V1Used && V2Used) {
5636 BestLoQuad = InputQuads[0] ? 0 : 1;
5637 BestHiQuad = InputQuads[2] ? 2 : 3;
5639 if (InputQuads.count() > 2) {
5645 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
5646 // the shuffle mask. If a quad is scored as -1, that means that it contains
5647 // words from all 4 input quadwords.
5649 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
5651 BestLoQuad < 0 ? 0 : BestLoQuad,
5652 BestHiQuad < 0 ? 1 : BestHiQuad
5654 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
5655 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
5656 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
5657 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
5659 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
5660 // source words for the shuffle, to aid later transformations.
5661 bool AllWordsInNewV = true;
5662 bool InOrder[2] = { true, true };
5663 for (unsigned i = 0; i != 8; ++i) {
5664 int idx = MaskVals[i];
5666 InOrder[i/4] = false;
5667 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
5669 AllWordsInNewV = false;
5673 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
5674 if (AllWordsInNewV) {
5675 for (int i = 0; i != 8; ++i) {
5676 int idx = MaskVals[i];
5679 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
5680 if ((idx != i) && idx < 4)
5682 if ((idx != i) && idx > 3)
5691 // If we've eliminated the use of V2, and the new mask is a pshuflw or
5692 // pshufhw, that's as cheap as it gets. Return the new shuffle.
5693 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
5694 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
5695 unsigned TargetMask = 0;
5696 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
5697 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
5698 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
5699 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
5700 getShufflePSHUFLWImmediate(SVOp);
5701 V1 = NewV.getOperand(0);
5702 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
5706 // If we have SSSE3, and all words of the result are from 1 input vector,
5707 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
5708 // is present, fall back to case 4.
5709 if (Subtarget->hasSSSE3()) {
5710 SmallVector<SDValue,16> pshufbMask;
5712 // If we have elements from both input vectors, set the high bit of the
5713 // shuffle mask element to zero out elements that come from V2 in the V1
5714 // mask, and elements that come from V1 in the V2 mask, so that the two
5715 // results can be OR'd together.
5716 bool TwoInputs = V1Used && V2Used;
5717 for (unsigned i = 0; i != 8; ++i) {
5718 int EltIdx = MaskVals[i] * 2;
5719 int Idx0 = (TwoInputs && (EltIdx >= 16)) ? 0x80 : EltIdx;
5720 int Idx1 = (TwoInputs && (EltIdx >= 16)) ? 0x80 : EltIdx+1;
5721 pshufbMask.push_back(DAG.getConstant(Idx0, MVT::i8));
5722 pshufbMask.push_back(DAG.getConstant(Idx1, MVT::i8));
5724 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1);
5725 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5726 DAG.getNode(ISD::BUILD_VECTOR, dl,
5727 MVT::v16i8, &pshufbMask[0], 16));
5729 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5731 // Calculate the shuffle mask for the second input, shuffle it, and
5732 // OR it with the first shuffled input.
5734 for (unsigned i = 0; i != 8; ++i) {
5735 int EltIdx = MaskVals[i] * 2;
5736 int Idx0 = (EltIdx < 16) ? 0x80 : EltIdx - 16;
5737 int Idx1 = (EltIdx < 16) ? 0x80 : EltIdx - 15;
5738 pshufbMask.push_back(DAG.getConstant(Idx0, MVT::i8));
5739 pshufbMask.push_back(DAG.getConstant(Idx1, MVT::i8));
5741 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2);
5742 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5743 DAG.getNode(ISD::BUILD_VECTOR, dl,
5744 MVT::v16i8, &pshufbMask[0], 16));
5745 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5746 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5749 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
5750 // and update MaskVals with new element order.
5751 std::bitset<8> InOrder;
5752 if (BestLoQuad >= 0) {
5753 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
5754 for (int i = 0; i != 4; ++i) {
5755 int idx = MaskVals[i];
5758 } else if ((idx / 4) == BestLoQuad) {
5763 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5766 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
5767 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
5768 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
5770 getShufflePSHUFLWImmediate(SVOp), DAG);
5774 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
5775 // and update MaskVals with the new element order.
5776 if (BestHiQuad >= 0) {
5777 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
5778 for (unsigned i = 4; i != 8; ++i) {
5779 int idx = MaskVals[i];
5782 } else if ((idx / 4) == BestHiQuad) {
5783 MaskV[i] = (idx & 3) + 4;
5787 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5790 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
5791 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
5792 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
5794 getShufflePSHUFHWImmediate(SVOp), DAG);
5798 // In case BestHi & BestLo were both -1, which means each quadword has a word
5799 // from each of the four input quadwords, calculate the InOrder bitvector now
5800 // before falling through to the insert/extract cleanup.
5801 if (BestLoQuad == -1 && BestHiQuad == -1) {
5803 for (int i = 0; i != 8; ++i)
5804 if (MaskVals[i] < 0 || MaskVals[i] == i)
5808 // The other elements are put in the right place using pextrw and pinsrw.
5809 for (unsigned i = 0; i != 8; ++i) {
5812 int EltIdx = MaskVals[i];
5815 SDValue ExtOp = (EltIdx < 8) ?
5816 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
5817 DAG.getIntPtrConstant(EltIdx)) :
5818 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
5819 DAG.getIntPtrConstant(EltIdx - 8));
5820 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
5821 DAG.getIntPtrConstant(i));
5826 // v16i8 shuffles - Prefer shuffles in the following order:
5827 // 1. [ssse3] 1 x pshufb
5828 // 2. [ssse3] 2 x pshufb + 1 x por
5829 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
5831 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
5833 const X86TargetLowering &TLI) {
5834 SDValue V1 = SVOp->getOperand(0);
5835 SDValue V2 = SVOp->getOperand(1);
5836 DebugLoc dl = SVOp->getDebugLoc();
5837 ArrayRef<int> MaskVals = SVOp->getMask();
5839 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
5841 // If we have SSSE3, case 1 is generated when all result bytes come from
5842 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
5843 // present, fall back to case 3.
5845 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
5846 if (TLI.getSubtarget()->hasSSSE3()) {
5847 SmallVector<SDValue,16> pshufbMask;
5849 // If all result elements are from one input vector, then only translate
5850 // undef mask values to 0x80 (zero out result) in the pshufb mask.
5852 // Otherwise, we have elements from both input vectors, and must zero out
5853 // elements that come from V2 in the first mask, and V1 in the second mask
5854 // so that we can OR them together.
5855 for (unsigned i = 0; i != 16; ++i) {
5856 int EltIdx = MaskVals[i];
5857 if (EltIdx < 0 || EltIdx >= 16)
5859 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5861 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5862 DAG.getNode(ISD::BUILD_VECTOR, dl,
5863 MVT::v16i8, &pshufbMask[0], 16));
5867 // Calculate the shuffle mask for the second input, shuffle it, and
5868 // OR it with the first shuffled input.
5870 for (unsigned i = 0; i != 16; ++i) {
5871 int EltIdx = MaskVals[i];
5872 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
5873 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5875 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5876 DAG.getNode(ISD::BUILD_VECTOR, dl,
5877 MVT::v16i8, &pshufbMask[0], 16));
5878 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5881 // No SSSE3 - Calculate in place words and then fix all out of place words
5882 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
5883 // the 16 different words that comprise the two doublequadword input vectors.
5884 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5885 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
5887 for (int i = 0; i != 8; ++i) {
5888 int Elt0 = MaskVals[i*2];
5889 int Elt1 = MaskVals[i*2+1];
5891 // This word of the result is all undef, skip it.
5892 if (Elt0 < 0 && Elt1 < 0)
5895 // This word of the result is already in the correct place, skip it.
5896 if ((Elt0 == i*2) && (Elt1 == i*2+1))
5899 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
5900 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
5903 // If Elt0 and Elt1 are defined, are consecutive, and can be load
5904 // using a single extract together, load it and store it.
5905 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
5906 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5907 DAG.getIntPtrConstant(Elt1 / 2));
5908 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5909 DAG.getIntPtrConstant(i));
5913 // If Elt1 is defined, extract it from the appropriate source. If the
5914 // source byte is not also odd, shift the extracted word left 8 bits
5915 // otherwise clear the bottom 8 bits if we need to do an or.
5917 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5918 DAG.getIntPtrConstant(Elt1 / 2));
5919 if ((Elt1 & 1) == 0)
5920 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
5922 TLI.getShiftAmountTy(InsElt.getValueType())));
5924 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
5925 DAG.getConstant(0xFF00, MVT::i16));
5927 // If Elt0 is defined, extract it from the appropriate source. If the
5928 // source byte is not also even, shift the extracted word right 8 bits. If
5929 // Elt1 was also defined, OR the extracted values together before
5930 // inserting them in the result.
5932 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
5933 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
5934 if ((Elt0 & 1) != 0)
5935 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
5937 TLI.getShiftAmountTy(InsElt0.getValueType())));
5939 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
5940 DAG.getConstant(0x00FF, MVT::i16));
5941 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
5944 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5945 DAG.getIntPtrConstant(i));
5947 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
5950 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
5951 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
5952 /// done when every pair / quad of shuffle mask elements point to elements in
5953 /// the right sequence. e.g.
5954 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
5956 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
5957 SelectionDAG &DAG, DebugLoc dl) {
5958 MVT VT = SVOp->getValueType(0).getSimpleVT();
5959 unsigned NumElems = VT.getVectorNumElements();
5962 switch (VT.SimpleTy) {
5963 default: llvm_unreachable("Unexpected!");
5964 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
5965 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
5966 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
5967 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
5968 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
5969 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
5972 SmallVector<int, 8> MaskVec;
5973 for (unsigned i = 0; i != NumElems; i += Scale) {
5975 for (unsigned j = 0; j != Scale; ++j) {
5976 int EltIdx = SVOp->getMaskElt(i+j);
5980 StartIdx = (EltIdx / Scale);
5981 if (EltIdx != (int)(StartIdx*Scale + j))
5984 MaskVec.push_back(StartIdx);
5987 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
5988 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
5989 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
5992 /// getVZextMovL - Return a zero-extending vector move low node.
5994 static SDValue getVZextMovL(EVT VT, EVT OpVT,
5995 SDValue SrcOp, SelectionDAG &DAG,
5996 const X86Subtarget *Subtarget, DebugLoc dl) {
5997 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
5998 LoadSDNode *LD = NULL;
5999 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
6000 LD = dyn_cast<LoadSDNode>(SrcOp);
6002 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
6004 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
6005 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
6006 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
6007 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
6008 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
6010 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
6011 return DAG.getNode(ISD::BITCAST, dl, VT,
6012 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
6013 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6021 return DAG.getNode(ISD::BITCAST, dl, VT,
6022 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
6023 DAG.getNode(ISD::BITCAST, dl,
6027 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
6028 /// which could not be matched by any known target speficic shuffle
6030 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6032 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
6033 if (NewOp.getNode())
6036 EVT VT = SVOp->getValueType(0);
6038 unsigned NumElems = VT.getVectorNumElements();
6039 unsigned NumLaneElems = NumElems / 2;
6041 DebugLoc dl = SVOp->getDebugLoc();
6042 MVT EltVT = VT.getVectorElementType().getSimpleVT();
6043 EVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
6046 SmallVector<int, 16> Mask;
6047 for (unsigned l = 0; l < 2; ++l) {
6048 // Build a shuffle mask for the output, discovering on the fly which
6049 // input vectors to use as shuffle operands (recorded in InputUsed).
6050 // If building a suitable shuffle vector proves too hard, then bail
6051 // out with UseBuildVector set.
6052 bool UseBuildVector = false;
6053 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
6054 unsigned LaneStart = l * NumLaneElems;
6055 for (unsigned i = 0; i != NumLaneElems; ++i) {
6056 // The mask element. This indexes into the input.
6057 int Idx = SVOp->getMaskElt(i+LaneStart);
6059 // the mask element does not index into any input vector.
6064 // The input vector this mask element indexes into.
6065 int Input = Idx / NumLaneElems;
6067 // Turn the index into an offset from the start of the input vector.
6068 Idx -= Input * NumLaneElems;
6070 // Find or create a shuffle vector operand to hold this input.
6072 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
6073 if (InputUsed[OpNo] == Input)
6074 // This input vector is already an operand.
6076 if (InputUsed[OpNo] < 0) {
6077 // Create a new operand for this input vector.
6078 InputUsed[OpNo] = Input;
6083 if (OpNo >= array_lengthof(InputUsed)) {
6084 // More than two input vectors used! Give up on trying to create a
6085 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
6086 UseBuildVector = true;
6090 // Add the mask index for the new shuffle vector.
6091 Mask.push_back(Idx + OpNo * NumLaneElems);
6094 if (UseBuildVector) {
6095 SmallVector<SDValue, 16> SVOps;
6096 for (unsigned i = 0; i != NumLaneElems; ++i) {
6097 // The mask element. This indexes into the input.
6098 int Idx = SVOp->getMaskElt(i+LaneStart);
6100 SVOps.push_back(DAG.getUNDEF(EltVT));
6104 // The input vector this mask element indexes into.
6105 int Input = Idx / NumElems;
6107 // Turn the index into an offset from the start of the input vector.
6108 Idx -= Input * NumElems;
6110 // Extract the vector element by hand.
6111 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
6112 SVOp->getOperand(Input),
6113 DAG.getIntPtrConstant(Idx)));
6116 // Construct the output using a BUILD_VECTOR.
6117 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, &SVOps[0],
6119 } else if (InputUsed[0] < 0) {
6120 // No input vectors were used! The result is undefined.
6121 Output[l] = DAG.getUNDEF(NVT);
6123 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
6124 (InputUsed[0] % 2) * NumLaneElems,
6126 // If only one input was used, use an undefined vector for the other.
6127 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
6128 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
6129 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
6130 // At least one input vector was used. Create a new shuffle vector.
6131 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
6137 // Concatenate the result back
6138 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
6141 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
6142 /// 4 elements, and match them with several different shuffle types.
6144 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6145 SDValue V1 = SVOp->getOperand(0);
6146 SDValue V2 = SVOp->getOperand(1);
6147 DebugLoc dl = SVOp->getDebugLoc();
6148 EVT VT = SVOp->getValueType(0);
6150 assert(VT.getSizeInBits() == 128 && "Unsupported vector size");
6152 std::pair<int, int> Locs[4];
6153 int Mask1[] = { -1, -1, -1, -1 };
6154 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
6158 for (unsigned i = 0; i != 4; ++i) {
6159 int Idx = PermMask[i];
6161 Locs[i] = std::make_pair(-1, -1);
6163 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
6165 Locs[i] = std::make_pair(0, NumLo);
6169 Locs[i] = std::make_pair(1, NumHi);
6171 Mask1[2+NumHi] = Idx;
6177 if (NumLo <= 2 && NumHi <= 2) {
6178 // If no more than two elements come from either vector. This can be
6179 // implemented with two shuffles. First shuffle gather the elements.
6180 // The second shuffle, which takes the first shuffle as both of its
6181 // vector operands, put the elements into the right order.
6182 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6184 int Mask2[] = { -1, -1, -1, -1 };
6186 for (unsigned i = 0; i != 4; ++i)
6187 if (Locs[i].first != -1) {
6188 unsigned Idx = (i < 2) ? 0 : 4;
6189 Idx += Locs[i].first * 2 + Locs[i].second;
6193 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
6196 if (NumLo == 3 || NumHi == 3) {
6197 // Otherwise, we must have three elements from one vector, call it X, and
6198 // one element from the other, call it Y. First, use a shufps to build an
6199 // intermediate vector with the one element from Y and the element from X
6200 // that will be in the same half in the final destination (the indexes don't
6201 // matter). Then, use a shufps to build the final vector, taking the half
6202 // containing the element from Y from the intermediate, and the other half
6205 // Normalize it so the 3 elements come from V1.
6206 CommuteVectorShuffleMask(PermMask, 4);
6210 // Find the element from V2.
6212 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
6213 int Val = PermMask[HiIndex];
6220 Mask1[0] = PermMask[HiIndex];
6222 Mask1[2] = PermMask[HiIndex^1];
6224 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6227 Mask1[0] = PermMask[0];
6228 Mask1[1] = PermMask[1];
6229 Mask1[2] = HiIndex & 1 ? 6 : 4;
6230 Mask1[3] = HiIndex & 1 ? 4 : 6;
6231 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6234 Mask1[0] = HiIndex & 1 ? 2 : 0;
6235 Mask1[1] = HiIndex & 1 ? 0 : 2;
6236 Mask1[2] = PermMask[2];
6237 Mask1[3] = PermMask[3];
6242 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
6245 // Break it into (shuffle shuffle_hi, shuffle_lo).
6246 int LoMask[] = { -1, -1, -1, -1 };
6247 int HiMask[] = { -1, -1, -1, -1 };
6249 int *MaskPtr = LoMask;
6250 unsigned MaskIdx = 0;
6253 for (unsigned i = 0; i != 4; ++i) {
6260 int Idx = PermMask[i];
6262 Locs[i] = std::make_pair(-1, -1);
6263 } else if (Idx < 4) {
6264 Locs[i] = std::make_pair(MaskIdx, LoIdx);
6265 MaskPtr[LoIdx] = Idx;
6268 Locs[i] = std::make_pair(MaskIdx, HiIdx);
6269 MaskPtr[HiIdx] = Idx;
6274 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
6275 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
6276 int MaskOps[] = { -1, -1, -1, -1 };
6277 for (unsigned i = 0; i != 4; ++i)
6278 if (Locs[i].first != -1)
6279 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
6280 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
6283 static bool MayFoldVectorLoad(SDValue V) {
6284 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6285 V = V.getOperand(0);
6286 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6287 V = V.getOperand(0);
6288 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
6289 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
6290 // BUILD_VECTOR (load), undef
6291 V = V.getOperand(0);
6297 // FIXME: the version above should always be used. Since there's
6298 // a bug where several vector shuffles can't be folded because the
6299 // DAG is not updated during lowering and a node claims to have two
6300 // uses while it only has one, use this version, and let isel match
6301 // another instruction if the load really happens to have more than
6302 // one use. Remove this version after this bug get fixed.
6303 // rdar://8434668, PR8156
6304 static bool RelaxedMayFoldVectorLoad(SDValue V) {
6305 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6306 V = V.getOperand(0);
6307 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6308 V = V.getOperand(0);
6309 if (ISD::isNormalLoad(V.getNode()))
6315 SDValue getMOVDDup(SDValue &Op, DebugLoc &dl, SDValue V1, SelectionDAG &DAG) {
6316 EVT VT = Op.getValueType();
6318 // Canonizalize to v2f64.
6319 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
6320 return DAG.getNode(ISD::BITCAST, dl, VT,
6321 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
6326 SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG,
6328 SDValue V1 = Op.getOperand(0);
6329 SDValue V2 = Op.getOperand(1);
6330 EVT VT = Op.getValueType();
6332 assert(VT != MVT::v2i64 && "unsupported shuffle type");
6334 if (HasSSE2 && VT == MVT::v2f64)
6335 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
6337 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
6338 return DAG.getNode(ISD::BITCAST, dl, VT,
6339 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
6340 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
6341 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
6345 SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) {
6346 SDValue V1 = Op.getOperand(0);
6347 SDValue V2 = Op.getOperand(1);
6348 EVT VT = Op.getValueType();
6350 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
6351 "unsupported shuffle type");
6353 if (V2.getOpcode() == ISD::UNDEF)
6357 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
6361 SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
6362 SDValue V1 = Op.getOperand(0);
6363 SDValue V2 = Op.getOperand(1);
6364 EVT VT = Op.getValueType();
6365 unsigned NumElems = VT.getVectorNumElements();
6367 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
6368 // operand of these instructions is only memory, so check if there's a
6369 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
6371 bool CanFoldLoad = false;
6373 // Trivial case, when V2 comes from a load.
6374 if (MayFoldVectorLoad(V2))
6377 // When V1 is a load, it can be folded later into a store in isel, example:
6378 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
6380 // (MOVLPSmr addr:$src1, VR128:$src2)
6381 // So, recognize this potential and also use MOVLPS or MOVLPD
6382 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
6385 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6387 if (HasSSE2 && NumElems == 2)
6388 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
6391 // If we don't care about the second element, proceed to use movss.
6392 if (SVOp->getMaskElt(1) != -1)
6393 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
6396 // movl and movlp will both match v2i64, but v2i64 is never matched by
6397 // movl earlier because we make it strict to avoid messing with the movlp load
6398 // folding logic (see the code above getMOVLP call). Match it here then,
6399 // this is horrible, but will stay like this until we move all shuffle
6400 // matching to x86 specific nodes. Note that for the 1st condition all
6401 // types are matched with movsd.
6403 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
6404 // as to remove this logic from here, as much as possible
6405 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
6406 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6407 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6410 assert(VT != MVT::v4i32 && "unsupported shuffle type");
6412 // Invert the operand order and use SHUFPS to match it.
6413 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
6414 getShuffleSHUFImmediate(SVOp), DAG);
6418 X86TargetLowering::NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG) const {
6419 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6420 EVT VT = Op.getValueType();
6421 DebugLoc dl = Op.getDebugLoc();
6422 SDValue V1 = Op.getOperand(0);
6423 SDValue V2 = Op.getOperand(1);
6425 if (isZeroShuffle(SVOp))
6426 return getZeroVector(VT, Subtarget, DAG, dl);
6428 // Handle splat operations
6429 if (SVOp->isSplat()) {
6430 unsigned NumElem = VT.getVectorNumElements();
6431 int Size = VT.getSizeInBits();
6433 // Use vbroadcast whenever the splat comes from a foldable load
6434 SDValue Broadcast = LowerVectorBroadcast(Op, DAG);
6435 if (Broadcast.getNode())
6438 // Handle splats by matching through known shuffle masks
6439 if ((Size == 128 && NumElem <= 4) ||
6440 (Size == 256 && NumElem < 8))
6443 // All remaning splats are promoted to target supported vector shuffles.
6444 return PromoteSplat(SVOp, DAG);
6447 // If the shuffle can be profitably rewritten as a narrower shuffle, then
6449 if (VT == MVT::v8i16 || VT == MVT::v16i8 ||
6450 VT == MVT::v16i16 || VT == MVT::v32i8) {
6451 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6452 if (NewOp.getNode())
6453 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
6454 } else if ((VT == MVT::v4i32 ||
6455 (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
6456 // FIXME: Figure out a cleaner way to do this.
6457 // Try to make use of movq to zero out the top part.
6458 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
6459 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6460 if (NewOp.getNode()) {
6461 EVT NewVT = NewOp.getValueType();
6462 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
6463 NewVT, true, false))
6464 return getVZextMovL(VT, NewVT, NewOp.getOperand(0),
6465 DAG, Subtarget, dl);
6467 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
6468 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6469 if (NewOp.getNode()) {
6470 EVT NewVT = NewOp.getValueType();
6471 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
6472 return getVZextMovL(VT, NewVT, NewOp.getOperand(1),
6473 DAG, Subtarget, dl);
6481 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
6482 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6483 SDValue V1 = Op.getOperand(0);
6484 SDValue V2 = Op.getOperand(1);
6485 EVT VT = Op.getValueType();
6486 DebugLoc dl = Op.getDebugLoc();
6487 unsigned NumElems = VT.getVectorNumElements();
6488 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
6489 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
6490 bool V1IsSplat = false;
6491 bool V2IsSplat = false;
6492 bool HasSSE2 = Subtarget->hasSSE2();
6493 bool HasAVX = Subtarget->hasAVX();
6494 bool HasAVX2 = Subtarget->hasAVX2();
6495 MachineFunction &MF = DAG.getMachineFunction();
6496 bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize);
6498 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
6500 if (V1IsUndef && V2IsUndef)
6501 return DAG.getUNDEF(VT);
6503 assert(!V1IsUndef && "Op 1 of shuffle should not be undef");
6505 // Vector shuffle lowering takes 3 steps:
6507 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
6508 // narrowing and commutation of operands should be handled.
6509 // 2) Matching of shuffles with known shuffle masks to x86 target specific
6511 // 3) Rewriting of unmatched masks into new generic shuffle operations,
6512 // so the shuffle can be broken into other shuffles and the legalizer can
6513 // try the lowering again.
6515 // The general idea is that no vector_shuffle operation should be left to
6516 // be matched during isel, all of them must be converted to a target specific
6519 // Normalize the input vectors. Here splats, zeroed vectors, profitable
6520 // narrowing and commutation of operands should be handled. The actual code
6521 // doesn't include all of those, work in progress...
6522 SDValue NewOp = NormalizeVectorShuffle(Op, DAG);
6523 if (NewOp.getNode())
6526 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
6528 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
6529 // unpckh_undef). Only use pshufd if speed is more important than size.
6530 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasAVX2))
6531 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6532 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasAVX2))
6533 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6535 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
6536 V2IsUndef && RelaxedMayFoldVectorLoad(V1))
6537 return getMOVDDup(Op, dl, V1, DAG);
6539 if (isMOVHLPS_v_undef_Mask(M, VT))
6540 return getMOVHighToLow(Op, dl, DAG);
6542 // Use to match splats
6543 if (HasSSE2 && isUNPCKHMask(M, VT, HasAVX2) && V2IsUndef &&
6544 (VT == MVT::v2f64 || VT == MVT::v2i64))
6545 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6547 if (isPSHUFDMask(M, VT)) {
6548 // The actual implementation will match the mask in the if above and then
6549 // during isel it can match several different instructions, not only pshufd
6550 // as its name says, sad but true, emulate the behavior for now...
6551 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
6552 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
6554 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
6556 if (HasAVX && (VT == MVT::v4f32 || VT == MVT::v2f64))
6557 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, TargetMask, DAG);
6559 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
6560 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
6562 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
6566 // Check if this can be converted into a logical shift.
6567 bool isLeft = false;
6570 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
6571 if (isShift && ShVal.hasOneUse()) {
6572 // If the shifted value has multiple uses, it may be cheaper to use
6573 // v_set0 + movlhps or movhlps, etc.
6574 EVT EltVT = VT.getVectorElementType();
6575 ShAmt *= EltVT.getSizeInBits();
6576 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6579 if (isMOVLMask(M, VT)) {
6580 if (ISD::isBuildVectorAllZeros(V1.getNode()))
6581 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
6582 if (!isMOVLPMask(M, VT)) {
6583 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
6584 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6586 if (VT == MVT::v4i32 || VT == MVT::v4f32)
6587 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6591 // FIXME: fold these into legal mask.
6592 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasAVX2))
6593 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
6595 if (isMOVHLPSMask(M, VT))
6596 return getMOVHighToLow(Op, dl, DAG);
6598 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
6599 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
6601 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
6602 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
6604 if (isMOVLPMask(M, VT))
6605 return getMOVLP(Op, dl, DAG, HasSSE2);
6607 if (ShouldXformToMOVHLPS(M, VT) ||
6608 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
6609 return CommuteVectorShuffle(SVOp, DAG);
6612 // No better options. Use a vshldq / vsrldq.
6613 EVT EltVT = VT.getVectorElementType();
6614 ShAmt *= EltVT.getSizeInBits();
6615 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6618 bool Commuted = false;
6619 // FIXME: This should also accept a bitcast of a splat? Be careful, not
6620 // 1,1,1,1 -> v8i16 though.
6621 V1IsSplat = isSplatVector(V1.getNode());
6622 V2IsSplat = isSplatVector(V2.getNode());
6624 // Canonicalize the splat or undef, if present, to be on the RHS.
6625 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
6626 CommuteVectorShuffleMask(M, NumElems);
6628 std::swap(V1IsSplat, V2IsSplat);
6632 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
6633 // Shuffling low element of v1 into undef, just return v1.
6636 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
6637 // the instruction selector will not match, so get a canonical MOVL with
6638 // swapped operands to undo the commute.
6639 return getMOVL(DAG, dl, VT, V2, V1);
6642 if (isUNPCKLMask(M, VT, HasAVX2))
6643 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6645 if (isUNPCKHMask(M, VT, HasAVX2))
6646 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6649 // Normalize mask so all entries that point to V2 points to its first
6650 // element then try to match unpck{h|l} again. If match, return a
6651 // new vector_shuffle with the corrected mask.p
6652 SmallVector<int, 8> NewMask(M.begin(), M.end());
6653 NormalizeMask(NewMask, NumElems);
6654 if (isUNPCKLMask(NewMask, VT, HasAVX2, true))
6655 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6656 if (isUNPCKHMask(NewMask, VT, HasAVX2, true))
6657 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6661 // Commute is back and try unpck* again.
6662 // FIXME: this seems wrong.
6663 CommuteVectorShuffleMask(M, NumElems);
6665 std::swap(V1IsSplat, V2IsSplat);
6668 if (isUNPCKLMask(M, VT, HasAVX2))
6669 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6671 if (isUNPCKHMask(M, VT, HasAVX2))
6672 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6675 // Normalize the node to match x86 shuffle ops if needed
6676 if (!V2IsUndef && (isSHUFPMask(M, VT, HasAVX, /* Commuted */ true)))
6677 return CommuteVectorShuffle(SVOp, DAG);
6679 // The checks below are all present in isShuffleMaskLegal, but they are
6680 // inlined here right now to enable us to directly emit target specific
6681 // nodes, and remove one by one until they don't return Op anymore.
6683 if (isPALIGNRMask(M, VT, Subtarget))
6684 return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2,
6685 getShufflePALIGNRImmediate(SVOp),
6688 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
6689 SVOp->getSplatIndex() == 0 && V2IsUndef) {
6690 if (VT == MVT::v2f64 || VT == MVT::v2i64)
6691 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6694 if (isPSHUFHWMask(M, VT, HasAVX2))
6695 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
6696 getShufflePSHUFHWImmediate(SVOp),
6699 if (isPSHUFLWMask(M, VT, HasAVX2))
6700 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
6701 getShufflePSHUFLWImmediate(SVOp),
6704 if (isSHUFPMask(M, VT, HasAVX))
6705 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
6706 getShuffleSHUFImmediate(SVOp), DAG);
6708 if (isUNPCKL_v_undef_Mask(M, VT, HasAVX2))
6709 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6710 if (isUNPCKH_v_undef_Mask(M, VT, HasAVX2))
6711 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6713 //===--------------------------------------------------------------------===//
6714 // Generate target specific nodes for 128 or 256-bit shuffles only
6715 // supported in the AVX instruction set.
6718 // Handle VMOVDDUPY permutations
6719 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasAVX))
6720 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
6722 // Handle VPERMILPS/D* permutations
6723 if (isVPERMILPMask(M, VT, HasAVX)) {
6724 if (HasAVX2 && VT == MVT::v8i32)
6725 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
6726 getShuffleSHUFImmediate(SVOp), DAG);
6727 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1,
6728 getShuffleSHUFImmediate(SVOp), DAG);
6731 // Handle VPERM2F128/VPERM2I128 permutations
6732 if (isVPERM2X128Mask(M, VT, HasAVX))
6733 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
6734 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
6736 SDValue BlendOp = LowerVECTOR_SHUFFLEtoBlend(SVOp, Subtarget, DAG);
6737 if (BlendOp.getNode())
6740 if (V2IsUndef && HasAVX2 && (VT == MVT::v8i32 || VT == MVT::v8f32)) {
6741 SmallVector<SDValue, 8> permclMask;
6742 for (unsigned i = 0; i != 8; ++i) {
6743 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MVT::i32));
6745 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32,
6747 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
6748 return DAG.getNode(X86ISD::VPERMV, dl, VT,
6749 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
6752 if (V2IsUndef && HasAVX2 && (VT == MVT::v4i64 || VT == MVT::v4f64))
6753 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1,
6754 getShuffleCLImmediate(SVOp), DAG);
6757 //===--------------------------------------------------------------------===//
6758 // Since no target specific shuffle was selected for this generic one,
6759 // lower it into other known shuffles. FIXME: this isn't true yet, but
6760 // this is the plan.
6763 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
6764 if (VT == MVT::v8i16) {
6765 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, DAG);
6766 if (NewOp.getNode())
6770 if (VT == MVT::v16i8) {
6771 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
6772 if (NewOp.getNode())
6776 // Handle all 128-bit wide vectors with 4 elements, and match them with
6777 // several different shuffle types.
6778 if (NumElems == 4 && VT.getSizeInBits() == 128)
6779 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
6781 // Handle general 256-bit shuffles
6782 if (VT.is256BitVector())
6783 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
6789 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
6790 SelectionDAG &DAG) const {
6791 EVT VT = Op.getValueType();
6792 DebugLoc dl = Op.getDebugLoc();
6794 if (Op.getOperand(0).getValueType().getSizeInBits() != 128)
6797 if (VT.getSizeInBits() == 8) {
6798 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
6799 Op.getOperand(0), Op.getOperand(1));
6800 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6801 DAG.getValueType(VT));
6802 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6805 if (VT.getSizeInBits() == 16) {
6806 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6807 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
6809 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6810 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6811 DAG.getNode(ISD::BITCAST, dl,
6815 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
6816 Op.getOperand(0), Op.getOperand(1));
6817 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6818 DAG.getValueType(VT));
6819 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6822 if (VT == MVT::f32) {
6823 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
6824 // the result back to FR32 register. It's only worth matching if the
6825 // result has a single use which is a store or a bitcast to i32. And in
6826 // the case of a store, it's not worth it if the index is a constant 0,
6827 // because a MOVSSmr can be used instead, which is smaller and faster.
6828 if (!Op.hasOneUse())
6830 SDNode *User = *Op.getNode()->use_begin();
6831 if ((User->getOpcode() != ISD::STORE ||
6832 (isa<ConstantSDNode>(Op.getOperand(1)) &&
6833 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
6834 (User->getOpcode() != ISD::BITCAST ||
6835 User->getValueType(0) != MVT::i32))
6837 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6838 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
6841 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
6844 if (VT == MVT::i32 || VT == MVT::i64) {
6845 // ExtractPS/pextrq works with constant index.
6846 if (isa<ConstantSDNode>(Op.getOperand(1)))
6854 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
6855 SelectionDAG &DAG) const {
6856 if (!isa<ConstantSDNode>(Op.getOperand(1)))
6859 SDValue Vec = Op.getOperand(0);
6860 EVT VecVT = Vec.getValueType();
6862 // If this is a 256-bit vector result, first extract the 128-bit vector and
6863 // then extract the element from the 128-bit vector.
6864 if (VecVT.getSizeInBits() == 256) {
6865 DebugLoc dl = Op.getNode()->getDebugLoc();
6866 unsigned NumElems = VecVT.getVectorNumElements();
6867 SDValue Idx = Op.getOperand(1);
6868 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
6870 // Get the 128-bit vector.
6871 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
6873 if (IdxVal >= NumElems/2)
6874 IdxVal -= NumElems/2;
6875 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
6876 DAG.getConstant(IdxVal, MVT::i32));
6879 assert(Vec.getValueSizeInBits() <= 128 && "Unexpected vector length");
6881 if (Subtarget->hasSSE41()) {
6882 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
6887 EVT VT = Op.getValueType();
6888 DebugLoc dl = Op.getDebugLoc();
6889 // TODO: handle v16i8.
6890 if (VT.getSizeInBits() == 16) {
6891 SDValue Vec = Op.getOperand(0);
6892 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6894 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6895 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6896 DAG.getNode(ISD::BITCAST, dl,
6899 // Transform it so it match pextrw which produces a 32-bit result.
6900 EVT EltVT = MVT::i32;
6901 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
6902 Op.getOperand(0), Op.getOperand(1));
6903 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
6904 DAG.getValueType(VT));
6905 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6908 if (VT.getSizeInBits() == 32) {
6909 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6913 // SHUFPS the element to the lowest double word, then movss.
6914 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
6915 EVT VVT = Op.getOperand(0).getValueType();
6916 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6917 DAG.getUNDEF(VVT), Mask);
6918 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6919 DAG.getIntPtrConstant(0));
6922 if (VT.getSizeInBits() == 64) {
6923 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
6924 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
6925 // to match extract_elt for f64.
6926 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6930 // UNPCKHPD the element to the lowest double word, then movsd.
6931 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
6932 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
6933 int Mask[2] = { 1, -1 };
6934 EVT VVT = Op.getOperand(0).getValueType();
6935 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6936 DAG.getUNDEF(VVT), Mask);
6937 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6938 DAG.getIntPtrConstant(0));
6945 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op,
6946 SelectionDAG &DAG) const {
6947 EVT VT = Op.getValueType();
6948 EVT EltVT = VT.getVectorElementType();
6949 DebugLoc dl = Op.getDebugLoc();
6951 SDValue N0 = Op.getOperand(0);
6952 SDValue N1 = Op.getOperand(1);
6953 SDValue N2 = Op.getOperand(2);
6955 if (VT.getSizeInBits() == 256)
6958 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
6959 isa<ConstantSDNode>(N2)) {
6961 if (VT == MVT::v8i16)
6962 Opc = X86ISD::PINSRW;
6963 else if (VT == MVT::v16i8)
6964 Opc = X86ISD::PINSRB;
6966 Opc = X86ISD::PINSRB;
6968 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
6970 if (N1.getValueType() != MVT::i32)
6971 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
6972 if (N2.getValueType() != MVT::i32)
6973 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
6974 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
6977 if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
6978 // Bits [7:6] of the constant are the source select. This will always be
6979 // zero here. The DAG Combiner may combine an extract_elt index into these
6980 // bits. For example (insert (extract, 3), 2) could be matched by putting
6981 // the '3' into bits [7:6] of X86ISD::INSERTPS.
6982 // Bits [5:4] of the constant are the destination select. This is the
6983 // value of the incoming immediate.
6984 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
6985 // combine either bitwise AND or insert of float 0.0 to set these bits.
6986 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
6987 // Create this as a scalar to vector..
6988 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
6989 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
6992 if ((EltVT == MVT::i32 || EltVT == MVT::i64) && isa<ConstantSDNode>(N2)) {
6993 // PINSR* works with constant index.
7000 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
7001 EVT VT = Op.getValueType();
7002 EVT EltVT = VT.getVectorElementType();
7004 DebugLoc dl = Op.getDebugLoc();
7005 SDValue N0 = Op.getOperand(0);
7006 SDValue N1 = Op.getOperand(1);
7007 SDValue N2 = Op.getOperand(2);
7009 // If this is a 256-bit vector result, first extract the 128-bit vector,
7010 // insert the element into the extracted half and then place it back.
7011 if (VT.getSizeInBits() == 256) {
7012 if (!isa<ConstantSDNode>(N2))
7015 // Get the desired 128-bit vector half.
7016 unsigned NumElems = VT.getVectorNumElements();
7017 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue();
7018 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
7020 // Insert the element into the desired half.
7021 bool Upper = IdxVal >= NumElems/2;
7022 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
7023 DAG.getConstant(Upper ? IdxVal-NumElems/2 : IdxVal, MVT::i32));
7025 // Insert the changed part back to the 256-bit vector
7026 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
7029 if (Subtarget->hasSSE41())
7030 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
7032 if (EltVT == MVT::i8)
7035 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
7036 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
7037 // as its second argument.
7038 if (N1.getValueType() != MVT::i32)
7039 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
7040 if (N2.getValueType() != MVT::i32)
7041 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
7042 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
7048 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const {
7049 LLVMContext *Context = DAG.getContext();
7050 DebugLoc dl = Op.getDebugLoc();
7051 EVT OpVT = Op.getValueType();
7053 // If this is a 256-bit vector result, first insert into a 128-bit
7054 // vector and then insert into the 256-bit vector.
7055 if (OpVT.getSizeInBits() > 128) {
7056 // Insert into a 128-bit vector.
7057 EVT VT128 = EVT::getVectorVT(*Context,
7058 OpVT.getVectorElementType(),
7059 OpVT.getVectorNumElements() / 2);
7061 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
7063 // Insert the 128-bit vector.
7064 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
7067 if (OpVT == MVT::v1i64 &&
7068 Op.getOperand(0).getValueType() == MVT::i64)
7069 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
7071 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
7072 assert(OpVT.getSizeInBits() == 128 && "Expected an SSE type!");
7073 return DAG.getNode(ISD::BITCAST, dl, OpVT,
7074 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
7077 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
7078 // a simple subregister reference or explicit instructions to grab
7079 // upper bits of a vector.
7081 X86TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
7082 if (Subtarget->hasAVX()) {
7083 DebugLoc dl = Op.getNode()->getDebugLoc();
7084 SDValue Vec = Op.getNode()->getOperand(0);
7085 SDValue Idx = Op.getNode()->getOperand(1);
7087 if (Op.getNode()->getValueType(0).getSizeInBits() == 128 &&
7088 Vec.getNode()->getValueType(0).getSizeInBits() == 256 &&
7089 isa<ConstantSDNode>(Idx)) {
7090 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7091 return Extract128BitVector(Vec, IdxVal, DAG, dl);
7097 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
7098 // simple superregister reference or explicit instructions to insert
7099 // the upper bits of a vector.
7101 X86TargetLowering::LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
7102 if (Subtarget->hasAVX()) {
7103 DebugLoc dl = Op.getNode()->getDebugLoc();
7104 SDValue Vec = Op.getNode()->getOperand(0);
7105 SDValue SubVec = Op.getNode()->getOperand(1);
7106 SDValue Idx = Op.getNode()->getOperand(2);
7108 if (Op.getNode()->getValueType(0).getSizeInBits() == 256 &&
7109 SubVec.getNode()->getValueType(0).getSizeInBits() == 128 &&
7110 isa<ConstantSDNode>(Idx)) {
7111 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7112 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
7118 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
7119 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
7120 // one of the above mentioned nodes. It has to be wrapped because otherwise
7121 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
7122 // be used to form addressing mode. These wrapped nodes will be selected
7125 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
7126 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
7128 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7130 unsigned char OpFlag = 0;
7131 unsigned WrapperKind = X86ISD::Wrapper;
7132 CodeModel::Model M = getTargetMachine().getCodeModel();
7134 if (Subtarget->isPICStyleRIPRel() &&
7135 (M == CodeModel::Small || M == CodeModel::Kernel))
7136 WrapperKind = X86ISD::WrapperRIP;
7137 else if (Subtarget->isPICStyleGOT())
7138 OpFlag = X86II::MO_GOTOFF;
7139 else if (Subtarget->isPICStyleStubPIC())
7140 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7142 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
7144 CP->getOffset(), OpFlag);
7145 DebugLoc DL = CP->getDebugLoc();
7146 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7147 // With PIC, the address is actually $g + Offset.
7149 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7150 DAG.getNode(X86ISD::GlobalBaseReg,
7151 DebugLoc(), getPointerTy()),
7158 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
7159 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
7161 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7163 unsigned char OpFlag = 0;
7164 unsigned WrapperKind = X86ISD::Wrapper;
7165 CodeModel::Model M = getTargetMachine().getCodeModel();
7167 if (Subtarget->isPICStyleRIPRel() &&
7168 (M == CodeModel::Small || M == CodeModel::Kernel))
7169 WrapperKind = X86ISD::WrapperRIP;
7170 else if (Subtarget->isPICStyleGOT())
7171 OpFlag = X86II::MO_GOTOFF;
7172 else if (Subtarget->isPICStyleStubPIC())
7173 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7175 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
7177 DebugLoc DL = JT->getDebugLoc();
7178 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7180 // With PIC, the address is actually $g + Offset.
7182 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7183 DAG.getNode(X86ISD::GlobalBaseReg,
7184 DebugLoc(), getPointerTy()),
7191 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
7192 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
7194 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7196 unsigned char OpFlag = 0;
7197 unsigned WrapperKind = X86ISD::Wrapper;
7198 CodeModel::Model M = getTargetMachine().getCodeModel();
7200 if (Subtarget->isPICStyleRIPRel() &&
7201 (M == CodeModel::Small || M == CodeModel::Kernel)) {
7202 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
7203 OpFlag = X86II::MO_GOTPCREL;
7204 WrapperKind = X86ISD::WrapperRIP;
7205 } else if (Subtarget->isPICStyleGOT()) {
7206 OpFlag = X86II::MO_GOT;
7207 } else if (Subtarget->isPICStyleStubPIC()) {
7208 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
7209 } else if (Subtarget->isPICStyleStubNoDynamic()) {
7210 OpFlag = X86II::MO_DARWIN_NONLAZY;
7213 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
7215 DebugLoc DL = Op.getDebugLoc();
7216 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7219 // With PIC, the address is actually $g + Offset.
7220 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
7221 !Subtarget->is64Bit()) {
7222 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7223 DAG.getNode(X86ISD::GlobalBaseReg,
7224 DebugLoc(), getPointerTy()),
7228 // For symbols that require a load from a stub to get the address, emit the
7230 if (isGlobalStubReference(OpFlag))
7231 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
7232 MachinePointerInfo::getGOT(), false, false, false, 0);
7238 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
7239 // Create the TargetBlockAddressAddress node.
7240 unsigned char OpFlags =
7241 Subtarget->ClassifyBlockAddressReference();
7242 CodeModel::Model M = getTargetMachine().getCodeModel();
7243 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
7244 DebugLoc dl = Op.getDebugLoc();
7245 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(),
7246 /*isTarget=*/true, OpFlags);
7248 if (Subtarget->isPICStyleRIPRel() &&
7249 (M == CodeModel::Small || M == CodeModel::Kernel))
7250 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7252 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7254 // With PIC, the address is actually $g + Offset.
7255 if (isGlobalRelativeToPICBase(OpFlags)) {
7256 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7257 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7265 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
7267 SelectionDAG &DAG) const {
7268 // Create the TargetGlobalAddress node, folding in the constant
7269 // offset if it is legal.
7270 unsigned char OpFlags =
7271 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
7272 CodeModel::Model M = getTargetMachine().getCodeModel();
7274 if (OpFlags == X86II::MO_NO_FLAG &&
7275 X86::isOffsetSuitableForCodeModel(Offset, M)) {
7276 // A direct static reference to a global.
7277 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
7280 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
7283 if (Subtarget->isPICStyleRIPRel() &&
7284 (M == CodeModel::Small || M == CodeModel::Kernel))
7285 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7287 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7289 // With PIC, the address is actually $g + Offset.
7290 if (isGlobalRelativeToPICBase(OpFlags)) {
7291 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7292 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7296 // For globals that require a load from a stub to get the address, emit the
7298 if (isGlobalStubReference(OpFlags))
7299 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
7300 MachinePointerInfo::getGOT(), false, false, false, 0);
7302 // If there was a non-zero offset that we didn't fold, create an explicit
7305 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
7306 DAG.getConstant(Offset, getPointerTy()));
7312 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
7313 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
7314 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
7315 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
7319 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
7320 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
7321 unsigned char OperandFlags, bool LocalDynamic = false) {
7322 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7323 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7324 DebugLoc dl = GA->getDebugLoc();
7325 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7326 GA->getValueType(0),
7330 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
7334 SDValue Ops[] = { Chain, TGA, *InFlag };
7335 Chain = DAG.getNode(CallType, dl, NodeTys, Ops, 3);
7337 SDValue Ops[] = { Chain, TGA };
7338 Chain = DAG.getNode(CallType, dl, NodeTys, Ops, 2);
7341 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
7342 MFI->setAdjustsStack(true);
7344 SDValue Flag = Chain.getValue(1);
7345 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
7348 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
7350 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7353 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
7354 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
7355 DAG.getNode(X86ISD::GlobalBaseReg,
7356 DebugLoc(), PtrVT), InFlag);
7357 InFlag = Chain.getValue(1);
7359 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
7362 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
7364 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7366 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
7367 X86::RAX, X86II::MO_TLSGD);
7370 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
7374 DebugLoc dl = GA->getDebugLoc();
7376 // Get the start address of the TLS block for this module.
7377 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
7378 .getInfo<X86MachineFunctionInfo>();
7379 MFI->incNumLocalDynamicTLSAccesses();
7383 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT, X86::RAX,
7384 X86II::MO_TLSLD, /*LocalDynamic=*/true);
7387 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
7388 DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), PtrVT), InFlag);
7389 InFlag = Chain.getValue(1);
7390 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
7391 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
7394 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
7398 unsigned char OperandFlags = X86II::MO_DTPOFF;
7399 unsigned WrapperKind = X86ISD::Wrapper;
7400 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7401 GA->getValueType(0),
7402 GA->getOffset(), OperandFlags);
7403 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
7405 // Add x@dtpoff with the base.
7406 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
7409 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
7410 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7411 const EVT PtrVT, TLSModel::Model model,
7412 bool is64Bit, bool isPIC) {
7413 DebugLoc dl = GA->getDebugLoc();
7415 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
7416 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
7417 is64Bit ? 257 : 256));
7419 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
7420 DAG.getIntPtrConstant(0),
7421 MachinePointerInfo(Ptr),
7422 false, false, false, 0);
7424 unsigned char OperandFlags = 0;
7425 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
7427 unsigned WrapperKind = X86ISD::Wrapper;
7428 if (model == TLSModel::LocalExec) {
7429 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
7430 } else if (model == TLSModel::InitialExec) {
7432 OperandFlags = X86II::MO_GOTTPOFF;
7433 WrapperKind = X86ISD::WrapperRIP;
7435 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
7438 llvm_unreachable("Unexpected model");
7441 // emit "addl x@ntpoff,%eax" (local exec)
7442 // or "addl x@indntpoff,%eax" (initial exec)
7443 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
7444 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7445 GA->getValueType(0),
7446 GA->getOffset(), OperandFlags);
7447 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
7449 if (model == TLSModel::InitialExec) {
7450 if (isPIC && !is64Bit) {
7451 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
7452 DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), PtrVT),
7455 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
7456 MachinePointerInfo::getGOT(), false, false, false,
7461 // The address of the thread local variable is the add of the thread
7462 // pointer with the offset of the variable.
7463 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
7467 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
7469 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
7470 const GlobalValue *GV = GA->getGlobal();
7472 if (Subtarget->isTargetELF()) {
7473 TLSModel::Model model = getTargetMachine().getTLSModel(GV);
7476 case TLSModel::GeneralDynamic:
7477 if (Subtarget->is64Bit())
7478 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
7479 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
7480 case TLSModel::LocalDynamic:
7481 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
7482 Subtarget->is64Bit());
7483 case TLSModel::InitialExec:
7484 case TLSModel::LocalExec:
7485 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
7486 Subtarget->is64Bit(),
7487 getTargetMachine().getRelocationModel() == Reloc::PIC_);
7489 llvm_unreachable("Unknown TLS model.");
7492 if (Subtarget->isTargetDarwin()) {
7493 // Darwin only has one model of TLS. Lower to that.
7494 unsigned char OpFlag = 0;
7495 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
7496 X86ISD::WrapperRIP : X86ISD::Wrapper;
7498 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7500 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
7501 !Subtarget->is64Bit();
7503 OpFlag = X86II::MO_TLVP_PIC_BASE;
7505 OpFlag = X86II::MO_TLVP;
7506 DebugLoc DL = Op.getDebugLoc();
7507 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
7508 GA->getValueType(0),
7509 GA->getOffset(), OpFlag);
7510 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7512 // With PIC32, the address is actually $g + Offset.
7514 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7515 DAG.getNode(X86ISD::GlobalBaseReg,
7516 DebugLoc(), getPointerTy()),
7519 // Lowering the machine isd will make sure everything is in the right
7521 SDValue Chain = DAG.getEntryNode();
7522 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7523 SDValue Args[] = { Chain, Offset };
7524 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2);
7526 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
7527 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7528 MFI->setAdjustsStack(true);
7530 // And our return value (tls address) is in the standard call return value
7532 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
7533 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
7537 if (Subtarget->isTargetWindows()) {
7538 // Just use the implicit TLS architecture
7539 // Need to generate someting similar to:
7540 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
7542 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
7543 // mov rcx, qword [rdx+rcx*8]
7544 // mov eax, .tls$:tlsvar
7545 // [rax+rcx] contains the address
7546 // Windows 64bit: gs:0x58
7547 // Windows 32bit: fs:__tls_array
7549 // If GV is an alias then use the aliasee for determining
7550 // thread-localness.
7551 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
7552 GV = GA->resolveAliasedGlobal(false);
7553 DebugLoc dl = GA->getDebugLoc();
7554 SDValue Chain = DAG.getEntryNode();
7556 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
7557 // %gs:0x58 (64-bit).
7558 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
7559 ? Type::getInt8PtrTy(*DAG.getContext(),
7561 : Type::getInt32PtrTy(*DAG.getContext(),
7564 SDValue ThreadPointer = DAG.getLoad(getPointerTy(), dl, Chain,
7565 Subtarget->is64Bit()
7566 ? DAG.getIntPtrConstant(0x58)
7567 : DAG.getExternalSymbol("_tls_array",
7569 MachinePointerInfo(Ptr),
7570 false, false, false, 0);
7572 // Load the _tls_index variable
7573 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
7574 if (Subtarget->is64Bit())
7575 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
7576 IDX, MachinePointerInfo(), MVT::i32,
7579 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
7580 false, false, false, 0);
7582 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
7584 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
7586 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
7587 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
7588 false, false, false, 0);
7590 // Get the offset of start of .tls section
7591 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7592 GA->getValueType(0),
7593 GA->getOffset(), X86II::MO_SECREL);
7594 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
7596 // The address of the thread local variable is the add of the thread
7597 // pointer with the offset of the variable.
7598 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
7601 llvm_unreachable("TLS not implemented for this target.");
7605 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
7606 /// and take a 2 x i32 value to shift plus a shift amount.
7607 SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const{
7608 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
7609 EVT VT = Op.getValueType();
7610 unsigned VTBits = VT.getSizeInBits();
7611 DebugLoc dl = Op.getDebugLoc();
7612 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
7613 SDValue ShOpLo = Op.getOperand(0);
7614 SDValue ShOpHi = Op.getOperand(1);
7615 SDValue ShAmt = Op.getOperand(2);
7616 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
7617 DAG.getConstant(VTBits - 1, MVT::i8))
7618 : DAG.getConstant(0, VT);
7621 if (Op.getOpcode() == ISD::SHL_PARTS) {
7622 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
7623 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
7625 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
7626 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
7629 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
7630 DAG.getConstant(VTBits, MVT::i8));
7631 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
7632 AndNode, DAG.getConstant(0, MVT::i8));
7635 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
7636 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
7637 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
7639 if (Op.getOpcode() == ISD::SHL_PARTS) {
7640 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7641 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7643 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7644 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7647 SDValue Ops[2] = { Lo, Hi };
7648 return DAG.getMergeValues(Ops, 2, dl);
7651 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
7652 SelectionDAG &DAG) const {
7653 EVT SrcVT = Op.getOperand(0).getValueType();
7655 if (SrcVT.isVector())
7658 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
7659 "Unknown SINT_TO_FP to lower!");
7661 // These are really Legal; return the operand so the caller accepts it as
7663 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
7665 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
7666 Subtarget->is64Bit()) {
7670 DebugLoc dl = Op.getDebugLoc();
7671 unsigned Size = SrcVT.getSizeInBits()/8;
7672 MachineFunction &MF = DAG.getMachineFunction();
7673 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
7674 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7675 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7677 MachinePointerInfo::getFixedStack(SSFI),
7679 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
7682 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
7684 SelectionDAG &DAG) const {
7686 DebugLoc DL = Op.getDebugLoc();
7688 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
7690 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
7692 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
7694 unsigned ByteSize = SrcVT.getSizeInBits()/8;
7696 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
7697 MachineMemOperand *MMO;
7699 int SSFI = FI->getIndex();
7701 DAG.getMachineFunction()
7702 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7703 MachineMemOperand::MOLoad, ByteSize, ByteSize);
7705 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
7706 StackSlot = StackSlot.getOperand(1);
7708 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
7709 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
7711 Tys, Ops, array_lengthof(Ops),
7715 Chain = Result.getValue(1);
7716 SDValue InFlag = Result.getValue(2);
7718 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
7719 // shouldn't be necessary except that RFP cannot be live across
7720 // multiple blocks. When stackifier is fixed, they can be uncoupled.
7721 MachineFunction &MF = DAG.getMachineFunction();
7722 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
7723 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
7724 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7725 Tys = DAG.getVTList(MVT::Other);
7727 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
7729 MachineMemOperand *MMO =
7730 DAG.getMachineFunction()
7731 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7732 MachineMemOperand::MOStore, SSFISize, SSFISize);
7734 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
7735 Ops, array_lengthof(Ops),
7736 Op.getValueType(), MMO);
7737 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
7738 MachinePointerInfo::getFixedStack(SSFI),
7739 false, false, false, 0);
7745 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
7746 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
7747 SelectionDAG &DAG) const {
7748 // This algorithm is not obvious. Here it is what we're trying to output:
7751 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
7752 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
7756 pshufd $0x4e, %xmm0, %xmm1
7761 DebugLoc dl = Op.getDebugLoc();
7762 LLVMContext *Context = DAG.getContext();
7764 // Build some magic constants.
7765 const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
7766 Constant *C0 = ConstantDataVector::get(*Context, CV0);
7767 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
7769 SmallVector<Constant*,2> CV1;
7771 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL))));
7773 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL))));
7774 Constant *C1 = ConstantVector::get(CV1);
7775 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
7777 // Load the 64-bit value into an XMM register.
7778 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
7780 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
7781 MachinePointerInfo::getConstantPool(),
7782 false, false, false, 16);
7783 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
7784 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
7787 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
7788 MachinePointerInfo::getConstantPool(),
7789 false, false, false, 16);
7790 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
7791 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
7794 if (Subtarget->hasSSE3()) {
7795 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
7796 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
7798 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
7799 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
7801 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
7802 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
7806 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
7807 DAG.getIntPtrConstant(0));
7810 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
7811 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
7812 SelectionDAG &DAG) const {
7813 DebugLoc dl = Op.getDebugLoc();
7814 // FP constant to bias correct the final result.
7815 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
7818 // Load the 32-bit value into an XMM register.
7819 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
7822 // Zero out the upper parts of the register.
7823 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
7825 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7826 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
7827 DAG.getIntPtrConstant(0));
7829 // Or the load with the bias.
7830 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
7831 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7832 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7834 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7835 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7836 MVT::v2f64, Bias)));
7837 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7838 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
7839 DAG.getIntPtrConstant(0));
7841 // Subtract the bias.
7842 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
7844 // Handle final rounding.
7845 EVT DestVT = Op.getValueType();
7847 if (DestVT.bitsLT(MVT::f64))
7848 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
7849 DAG.getIntPtrConstant(0));
7850 if (DestVT.bitsGT(MVT::f64))
7851 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
7853 // Handle final rounding.
7857 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
7858 SelectionDAG &DAG) const {
7859 SDValue N0 = Op.getOperand(0);
7860 DebugLoc dl = Op.getDebugLoc();
7862 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
7863 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
7864 // the optimization here.
7865 if (DAG.SignBitIsZero(N0))
7866 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
7868 EVT SrcVT = N0.getValueType();
7869 EVT DstVT = Op.getValueType();
7870 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
7871 return LowerUINT_TO_FP_i64(Op, DAG);
7872 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
7873 return LowerUINT_TO_FP_i32(Op, DAG);
7874 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
7877 // Make a 64-bit buffer, and use it to build an FILD.
7878 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
7879 if (SrcVT == MVT::i32) {
7880 SDValue WordOff = DAG.getConstant(4, getPointerTy());
7881 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
7882 getPointerTy(), StackSlot, WordOff);
7883 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7884 StackSlot, MachinePointerInfo(),
7886 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
7887 OffsetSlot, MachinePointerInfo(),
7889 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
7893 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
7894 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7895 StackSlot, MachinePointerInfo(),
7897 // For i64 source, we need to add the appropriate power of 2 if the input
7898 // was negative. This is the same as the optimization in
7899 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
7900 // we must be careful to do the computation in x87 extended precision, not
7901 // in SSE. (The generic code can't know it's OK to do this, or how to.)
7902 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
7903 MachineMemOperand *MMO =
7904 DAG.getMachineFunction()
7905 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7906 MachineMemOperand::MOLoad, 8, 8);
7908 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
7909 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
7910 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, 3,
7913 APInt FF(32, 0x5F800000ULL);
7915 // Check whether the sign bit is set.
7916 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
7917 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
7920 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
7921 SDValue FudgePtr = DAG.getConstantPool(
7922 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
7925 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
7926 SDValue Zero = DAG.getIntPtrConstant(0);
7927 SDValue Four = DAG.getIntPtrConstant(4);
7928 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
7930 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
7932 // Load the value out, extending it from f32 to f80.
7933 // FIXME: Avoid the extend by constructing the right constant pool?
7934 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
7935 FudgePtr, MachinePointerInfo::getConstantPool(),
7936 MVT::f32, false, false, 4);
7937 // Extend everything to 80 bits to force it to be done on x87.
7938 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
7939 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
7942 std::pair<SDValue,SDValue> X86TargetLowering::
7943 FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned, bool IsReplace) const {
7944 DebugLoc DL = Op.getDebugLoc();
7946 EVT DstTy = Op.getValueType();
7948 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
7949 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
7953 assert(DstTy.getSimpleVT() <= MVT::i64 &&
7954 DstTy.getSimpleVT() >= MVT::i16 &&
7955 "Unknown FP_TO_INT to lower!");
7957 // These are really Legal.
7958 if (DstTy == MVT::i32 &&
7959 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
7960 return std::make_pair(SDValue(), SDValue());
7961 if (Subtarget->is64Bit() &&
7962 DstTy == MVT::i64 &&
7963 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
7964 return std::make_pair(SDValue(), SDValue());
7966 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
7967 // stack slot, or into the FTOL runtime function.
7968 MachineFunction &MF = DAG.getMachineFunction();
7969 unsigned MemSize = DstTy.getSizeInBits()/8;
7970 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
7971 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7974 if (!IsSigned && isIntegerTypeFTOL(DstTy))
7975 Opc = X86ISD::WIN_FTOL;
7977 switch (DstTy.getSimpleVT().SimpleTy) {
7978 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
7979 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
7980 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
7981 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
7984 SDValue Chain = DAG.getEntryNode();
7985 SDValue Value = Op.getOperand(0);
7986 EVT TheVT = Op.getOperand(0).getValueType();
7987 // FIXME This causes a redundant load/store if the SSE-class value is already
7988 // in memory, such as if it is on the callstack.
7989 if (isScalarFPTypeInSSEReg(TheVT)) {
7990 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
7991 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
7992 MachinePointerInfo::getFixedStack(SSFI),
7994 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
7996 Chain, StackSlot, DAG.getValueType(TheVT)
7999 MachineMemOperand *MMO =
8000 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8001 MachineMemOperand::MOLoad, MemSize, MemSize);
8002 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, 3,
8004 Chain = Value.getValue(1);
8005 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
8006 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8009 MachineMemOperand *MMO =
8010 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8011 MachineMemOperand::MOStore, MemSize, MemSize);
8013 if (Opc != X86ISD::WIN_FTOL) {
8014 // Build the FP_TO_INT*_IN_MEM
8015 SDValue Ops[] = { Chain, Value, StackSlot };
8016 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
8017 Ops, 3, DstTy, MMO);
8018 return std::make_pair(FIST, StackSlot);
8020 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
8021 DAG.getVTList(MVT::Other, MVT::Glue),
8023 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
8024 MVT::i32, ftol.getValue(1));
8025 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
8026 MVT::i32, eax.getValue(2));
8027 SDValue Ops[] = { eax, edx };
8028 SDValue pair = IsReplace
8029 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops, 2)
8030 : DAG.getMergeValues(Ops, 2, DL);
8031 return std::make_pair(pair, SDValue());
8035 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
8036 SelectionDAG &DAG) const {
8037 if (Op.getValueType().isVector())
8040 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
8041 /*IsSigned=*/ true, /*IsReplace=*/ false);
8042 SDValue FIST = Vals.first, StackSlot = Vals.second;
8043 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
8044 if (FIST.getNode() == 0) return Op;
8046 if (StackSlot.getNode())
8048 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
8049 FIST, StackSlot, MachinePointerInfo(),
8050 false, false, false, 0);
8052 // The node is the result.
8056 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
8057 SelectionDAG &DAG) const {
8058 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
8059 /*IsSigned=*/ false, /*IsReplace=*/ false);
8060 SDValue FIST = Vals.first, StackSlot = Vals.second;
8061 assert(FIST.getNode() && "Unexpected failure");
8063 if (StackSlot.getNode())
8065 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
8066 FIST, StackSlot, MachinePointerInfo(),
8067 false, false, false, 0);
8069 // The node is the result.
8073 SDValue X86TargetLowering::LowerFABS(SDValue Op,
8074 SelectionDAG &DAG) const {
8075 LLVMContext *Context = DAG.getContext();
8076 DebugLoc dl = Op.getDebugLoc();
8077 EVT VT = Op.getValueType();
8080 EltVT = VT.getVectorElementType();
8082 if (EltVT == MVT::f64) {
8083 C = ConstantVector::getSplat(2,
8084 ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
8086 C = ConstantVector::getSplat(4,
8087 ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
8089 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8090 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8091 MachinePointerInfo::getConstantPool(),
8092 false, false, false, 16);
8093 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
8096 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
8097 LLVMContext *Context = DAG.getContext();
8098 DebugLoc dl = Op.getDebugLoc();
8099 EVT VT = Op.getValueType();
8101 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
8102 if (VT.isVector()) {
8103 EltVT = VT.getVectorElementType();
8104 NumElts = VT.getVectorNumElements();
8107 if (EltVT == MVT::f64)
8108 C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)));
8110 C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)));
8111 C = ConstantVector::getSplat(NumElts, C);
8112 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8113 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8114 MachinePointerInfo::getConstantPool(),
8115 false, false, false, 16);
8116 if (VT.isVector()) {
8117 MVT XORVT = VT.getSizeInBits() == 128 ? MVT::v2i64 : MVT::v4i64;
8118 return DAG.getNode(ISD::BITCAST, dl, VT,
8119 DAG.getNode(ISD::XOR, dl, XORVT,
8120 DAG.getNode(ISD::BITCAST, dl, XORVT,
8122 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask)));
8125 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
8128 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
8129 LLVMContext *Context = DAG.getContext();
8130 SDValue Op0 = Op.getOperand(0);
8131 SDValue Op1 = Op.getOperand(1);
8132 DebugLoc dl = Op.getDebugLoc();
8133 EVT VT = Op.getValueType();
8134 EVT SrcVT = Op1.getValueType();
8136 // If second operand is smaller, extend it first.
8137 if (SrcVT.bitsLT(VT)) {
8138 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
8141 // And if it is bigger, shrink it first.
8142 if (SrcVT.bitsGT(VT)) {
8143 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
8147 // At this point the operands and the result should have the same
8148 // type, and that won't be f80 since that is not custom lowered.
8150 // First get the sign bit of second operand.
8151 SmallVector<Constant*,4> CV;
8152 if (SrcVT == MVT::f64) {
8153 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))));
8154 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
8156 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))));
8157 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8158 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8159 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8161 Constant *C = ConstantVector::get(CV);
8162 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8163 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
8164 MachinePointerInfo::getConstantPool(),
8165 false, false, false, 16);
8166 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
8168 // Shift sign bit right or left if the two operands have different types.
8169 if (SrcVT.bitsGT(VT)) {
8170 // Op0 is MVT::f32, Op1 is MVT::f64.
8171 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
8172 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
8173 DAG.getConstant(32, MVT::i32));
8174 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
8175 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
8176 DAG.getIntPtrConstant(0));
8179 // Clear first operand sign bit.
8181 if (VT == MVT::f64) {
8182 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
8183 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
8185 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
8186 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8187 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8188 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8190 C = ConstantVector::get(CV);
8191 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8192 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8193 MachinePointerInfo::getConstantPool(),
8194 false, false, false, 16);
8195 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
8197 // Or the value with the sign bit.
8198 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
8201 SDValue X86TargetLowering::LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) const {
8202 SDValue N0 = Op.getOperand(0);
8203 DebugLoc dl = Op.getDebugLoc();
8204 EVT VT = Op.getValueType();
8206 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
8207 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
8208 DAG.getConstant(1, VT));
8209 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
8212 /// Emit nodes that will be selected as "test Op0,Op0", or something
8214 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
8215 SelectionDAG &DAG) const {
8216 DebugLoc dl = Op.getDebugLoc();
8218 // CF and OF aren't always set the way we want. Determine which
8219 // of these we need.
8220 bool NeedCF = false;
8221 bool NeedOF = false;
8224 case X86::COND_A: case X86::COND_AE:
8225 case X86::COND_B: case X86::COND_BE:
8228 case X86::COND_G: case X86::COND_GE:
8229 case X86::COND_L: case X86::COND_LE:
8230 case X86::COND_O: case X86::COND_NO:
8235 // See if we can use the EFLAGS value from the operand instead of
8236 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
8237 // we prove that the arithmetic won't overflow, we can't use OF or CF.
8238 if (Op.getResNo() != 0 || NeedOF || NeedCF)
8239 // Emit a CMP with 0, which is the TEST pattern.
8240 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8241 DAG.getConstant(0, Op.getValueType()));
8243 unsigned Opcode = 0;
8244 unsigned NumOperands = 0;
8245 switch (Op.getNode()->getOpcode()) {
8247 // Due to an isel shortcoming, be conservative if this add is likely to be
8248 // selected as part of a load-modify-store instruction. When the root node
8249 // in a match is a store, isel doesn't know how to remap non-chain non-flag
8250 // uses of other nodes in the match, such as the ADD in this case. This
8251 // leads to the ADD being left around and reselected, with the result being
8252 // two adds in the output. Alas, even if none our users are stores, that
8253 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
8254 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
8255 // climbing the DAG back to the root, and it doesn't seem to be worth the
8257 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8258 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8259 if (UI->getOpcode() != ISD::CopyToReg &&
8260 UI->getOpcode() != ISD::SETCC &&
8261 UI->getOpcode() != ISD::STORE)
8264 if (ConstantSDNode *C =
8265 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
8266 // An add of one will be selected as an INC.
8267 if (C->getAPIntValue() == 1) {
8268 Opcode = X86ISD::INC;
8273 // An add of negative one (subtract of one) will be selected as a DEC.
8274 if (C->getAPIntValue().isAllOnesValue()) {
8275 Opcode = X86ISD::DEC;
8281 // Otherwise use a regular EFLAGS-setting add.
8282 Opcode = X86ISD::ADD;
8286 // If the primary and result isn't used, don't bother using X86ISD::AND,
8287 // because a TEST instruction will be better.
8288 bool NonFlagUse = false;
8289 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8290 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
8292 unsigned UOpNo = UI.getOperandNo();
8293 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
8294 // Look pass truncate.
8295 UOpNo = User->use_begin().getOperandNo();
8296 User = *User->use_begin();
8299 if (User->getOpcode() != ISD::BRCOND &&
8300 User->getOpcode() != ISD::SETCC &&
8301 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) {
8314 // Due to the ISEL shortcoming noted above, be conservative if this op is
8315 // likely to be selected as part of a load-modify-store instruction.
8316 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8317 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8318 if (UI->getOpcode() == ISD::STORE)
8321 // Otherwise use a regular EFLAGS-setting instruction.
8322 switch (Op.getNode()->getOpcode()) {
8323 default: llvm_unreachable("unexpected operator!");
8325 // If the only use of SUB is EFLAGS, use CMP instead.
8327 Opcode = X86ISD::CMP;
8329 Opcode = X86ISD::SUB;
8331 case ISD::OR: Opcode = X86ISD::OR; break;
8332 case ISD::XOR: Opcode = X86ISD::XOR; break;
8333 case ISD::AND: Opcode = X86ISD::AND; break;
8345 return SDValue(Op.getNode(), 1);
8352 // Emit a CMP with 0, which is the TEST pattern.
8353 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8354 DAG.getConstant(0, Op.getValueType()));
8356 if (Opcode == X86ISD::CMP) {
8357 SDValue New = DAG.getNode(Opcode, dl, MVT::i32, Op.getOperand(0),
8359 // We can't replace usage of SUB with CMP.
8360 // The SUB node will be removed later because there is no use of it.
8361 return SDValue(New.getNode(), 0);
8364 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
8365 SmallVector<SDValue, 4> Ops;
8366 for (unsigned i = 0; i != NumOperands; ++i)
8367 Ops.push_back(Op.getOperand(i));
8369 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
8370 DAG.ReplaceAllUsesWith(Op, New);
8371 return SDValue(New.getNode(), 1);
8374 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
8376 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
8377 SelectionDAG &DAG) const {
8378 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
8379 if (C->getAPIntValue() == 0)
8380 return EmitTest(Op0, X86CC, DAG);
8382 DebugLoc dl = Op0.getDebugLoc();
8383 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
8386 /// Convert a comparison if required by the subtarget.
8387 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
8388 SelectionDAG &DAG) const {
8389 // If the subtarget does not support the FUCOMI instruction, floating-point
8390 // comparisons have to be converted.
8391 if (Subtarget->hasCMov() ||
8392 Cmp.getOpcode() != X86ISD::CMP ||
8393 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
8394 !Cmp.getOperand(1).getValueType().isFloatingPoint())
8397 // The instruction selector will select an FUCOM instruction instead of
8398 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
8399 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
8400 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
8401 DebugLoc dl = Cmp.getDebugLoc();
8402 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
8403 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
8404 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
8405 DAG.getConstant(8, MVT::i8));
8406 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
8407 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
8410 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
8411 /// if it's possible.
8412 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
8413 DebugLoc dl, SelectionDAG &DAG) const {
8414 SDValue Op0 = And.getOperand(0);
8415 SDValue Op1 = And.getOperand(1);
8416 if (Op0.getOpcode() == ISD::TRUNCATE)
8417 Op0 = Op0.getOperand(0);
8418 if (Op1.getOpcode() == ISD::TRUNCATE)
8419 Op1 = Op1.getOperand(0);
8422 if (Op1.getOpcode() == ISD::SHL)
8423 std::swap(Op0, Op1);
8424 if (Op0.getOpcode() == ISD::SHL) {
8425 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
8426 if (And00C->getZExtValue() == 1) {
8427 // If we looked past a truncate, check that it's only truncating away
8429 unsigned BitWidth = Op0.getValueSizeInBits();
8430 unsigned AndBitWidth = And.getValueSizeInBits();
8431 if (BitWidth > AndBitWidth) {
8433 DAG.ComputeMaskedBits(Op0, Zeros, Ones);
8434 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
8438 RHS = Op0.getOperand(1);
8440 } else if (Op1.getOpcode() == ISD::Constant) {
8441 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
8442 uint64_t AndRHSVal = AndRHS->getZExtValue();
8443 SDValue AndLHS = Op0;
8445 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
8446 LHS = AndLHS.getOperand(0);
8447 RHS = AndLHS.getOperand(1);
8450 // Use BT if the immediate can't be encoded in a TEST instruction.
8451 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
8453 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
8457 if (LHS.getNode()) {
8458 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
8459 // instruction. Since the shift amount is in-range-or-undefined, we know
8460 // that doing a bittest on the i32 value is ok. We extend to i32 because
8461 // the encoding for the i16 version is larger than the i32 version.
8462 // Also promote i16 to i32 for performance / code size reason.
8463 if (LHS.getValueType() == MVT::i8 ||
8464 LHS.getValueType() == MVT::i16)
8465 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
8467 // If the operand types disagree, extend the shift amount to match. Since
8468 // BT ignores high bits (like shifts) we can use anyextend.
8469 if (LHS.getValueType() != RHS.getValueType())
8470 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
8472 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
8473 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
8474 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8475 DAG.getConstant(Cond, MVT::i8), BT);
8481 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
8483 if (Op.getValueType().isVector()) return LowerVSETCC(Op, DAG);
8485 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
8486 SDValue Op0 = Op.getOperand(0);
8487 SDValue Op1 = Op.getOperand(1);
8488 DebugLoc dl = Op.getDebugLoc();
8489 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
8491 // Optimize to BT if possible.
8492 // Lower (X & (1 << N)) == 0 to BT(X, N).
8493 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
8494 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
8495 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
8496 Op1.getOpcode() == ISD::Constant &&
8497 cast<ConstantSDNode>(Op1)->isNullValue() &&
8498 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8499 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
8500 if (NewSetCC.getNode())
8504 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
8506 if (Op1.getOpcode() == ISD::Constant &&
8507 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
8508 cast<ConstantSDNode>(Op1)->isNullValue()) &&
8509 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8511 // If the input is a setcc, then reuse the input setcc or use a new one with
8512 // the inverted condition.
8513 if (Op0.getOpcode() == X86ISD::SETCC) {
8514 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
8515 bool Invert = (CC == ISD::SETNE) ^
8516 cast<ConstantSDNode>(Op1)->isNullValue();
8517 if (!Invert) return Op0;
8519 CCode = X86::GetOppositeBranchCondition(CCode);
8520 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8521 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
8525 bool isFP = Op1.getValueType().isFloatingPoint();
8526 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
8527 if (X86CC == X86::COND_INVALID)
8530 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG);
8531 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
8532 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8533 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
8536 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
8537 // ones, and then concatenate the result back.
8538 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
8539 EVT VT = Op.getValueType();
8541 assert(VT.getSizeInBits() == 256 && Op.getOpcode() == ISD::SETCC &&
8542 "Unsupported value type for operation");
8544 unsigned NumElems = VT.getVectorNumElements();
8545 DebugLoc dl = Op.getDebugLoc();
8546 SDValue CC = Op.getOperand(2);
8548 // Extract the LHS vectors
8549 SDValue LHS = Op.getOperand(0);
8550 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
8551 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
8553 // Extract the RHS vectors
8554 SDValue RHS = Op.getOperand(1);
8555 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
8556 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
8558 // Issue the operation on the smaller types and concatenate the result back
8559 MVT EltVT = VT.getVectorElementType().getSimpleVT();
8560 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
8561 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
8562 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
8563 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
8567 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const {
8569 SDValue Op0 = Op.getOperand(0);
8570 SDValue Op1 = Op.getOperand(1);
8571 SDValue CC = Op.getOperand(2);
8572 EVT VT = Op.getValueType();
8573 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
8574 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
8575 DebugLoc dl = Op.getDebugLoc();
8579 EVT EltVT = Op0.getValueType().getVectorElementType();
8580 assert(EltVT == MVT::f32 || EltVT == MVT::f64); (void)EltVT;
8584 // SSE Condition code mapping:
8593 switch (SetCCOpcode) {
8596 case ISD::SETEQ: SSECC = 0; break;
8598 case ISD::SETGT: Swap = true; // Fallthrough
8600 case ISD::SETOLT: SSECC = 1; break;
8602 case ISD::SETGE: Swap = true; // Fallthrough
8604 case ISD::SETOLE: SSECC = 2; break;
8605 case ISD::SETUO: SSECC = 3; break;
8607 case ISD::SETNE: SSECC = 4; break;
8608 case ISD::SETULE: Swap = true;
8609 case ISD::SETUGE: SSECC = 5; break;
8610 case ISD::SETULT: Swap = true;
8611 case ISD::SETUGT: SSECC = 6; break;
8612 case ISD::SETO: SSECC = 7; break;
8615 std::swap(Op0, Op1);
8617 // In the two special cases we can't handle, emit two comparisons.
8619 if (SetCCOpcode == ISD::SETUEQ) {
8621 UNORD = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8622 DAG.getConstant(3, MVT::i8));
8623 EQ = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8624 DAG.getConstant(0, MVT::i8));
8625 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
8627 if (SetCCOpcode == ISD::SETONE) {
8629 ORD = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8630 DAG.getConstant(7, MVT::i8));
8631 NEQ = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8632 DAG.getConstant(4, MVT::i8));
8633 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
8635 llvm_unreachable("Illegal FP comparison");
8637 // Handle all other FP comparisons here.
8638 return DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8639 DAG.getConstant(SSECC, MVT::i8));
8642 // Break 256-bit integer vector compare into smaller ones.
8643 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2())
8644 return Lower256IntVSETCC(Op, DAG);
8646 // We are handling one of the integer comparisons here. Since SSE only has
8647 // GT and EQ comparisons for integer, swapping operands and multiple
8648 // operations may be required for some comparisons.
8650 bool Swap = false, Invert = false, FlipSigns = false;
8652 switch (SetCCOpcode) {
8654 case ISD::SETNE: Invert = true;
8655 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
8656 case ISD::SETLT: Swap = true;
8657 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
8658 case ISD::SETGE: Swap = true;
8659 case ISD::SETLE: Opc = X86ISD::PCMPGT; Invert = true; break;
8660 case ISD::SETULT: Swap = true;
8661 case ISD::SETUGT: Opc = X86ISD::PCMPGT; FlipSigns = true; break;
8662 case ISD::SETUGE: Swap = true;
8663 case ISD::SETULE: Opc = X86ISD::PCMPGT; FlipSigns = true; Invert = true; break;
8666 std::swap(Op0, Op1);
8668 // Check that the operation in question is available (most are plain SSE2,
8669 // but PCMPGTQ and PCMPEQQ have different requirements).
8670 if (Opc == X86ISD::PCMPGT && VT == MVT::v2i64 && !Subtarget->hasSSE42())
8672 if (Opc == X86ISD::PCMPEQ && VT == MVT::v2i64 && !Subtarget->hasSSE41())
8675 // Since SSE has no unsigned integer comparisons, we need to flip the sign
8676 // bits of the inputs before performing those operations.
8678 EVT EltVT = VT.getVectorElementType();
8679 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
8681 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
8682 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
8684 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
8685 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
8688 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
8690 // If the logical-not of the result is required, perform that now.
8692 Result = DAG.getNOT(dl, Result, VT);
8697 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
8698 static bool isX86LogicalCmp(SDValue Op) {
8699 unsigned Opc = Op.getNode()->getOpcode();
8700 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
8701 Opc == X86ISD::SAHF)
8703 if (Op.getResNo() == 1 &&
8704 (Opc == X86ISD::ADD ||
8705 Opc == X86ISD::SUB ||
8706 Opc == X86ISD::ADC ||
8707 Opc == X86ISD::SBB ||
8708 Opc == X86ISD::SMUL ||
8709 Opc == X86ISD::UMUL ||
8710 Opc == X86ISD::INC ||
8711 Opc == X86ISD::DEC ||
8712 Opc == X86ISD::OR ||
8713 Opc == X86ISD::XOR ||
8714 Opc == X86ISD::AND))
8717 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
8723 static bool isZero(SDValue V) {
8724 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
8725 return C && C->isNullValue();
8728 static bool isAllOnes(SDValue V) {
8729 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
8730 return C && C->isAllOnesValue();
8733 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
8734 bool addTest = true;
8735 SDValue Cond = Op.getOperand(0);
8736 SDValue Op1 = Op.getOperand(1);
8737 SDValue Op2 = Op.getOperand(2);
8738 DebugLoc DL = Op.getDebugLoc();
8741 if (Cond.getOpcode() == ISD::SETCC) {
8742 SDValue NewCond = LowerSETCC(Cond, DAG);
8743 if (NewCond.getNode())
8747 // Handle the following cases related to max and min:
8748 // (a > b) ? (a-b) : 0
8749 // (a >= b) ? (a-b) : 0
8750 // (b < a) ? (a-b) : 0
8751 // (b <= a) ? (a-b) : 0
8752 // Comparison is removed to use EFLAGS from SUB.
8753 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op2))
8754 if (Cond.getOpcode() == X86ISD::SETCC &&
8755 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
8756 (Op1.getOpcode() == ISD::SUB || Op1.getOpcode() == X86ISD::SUB) &&
8757 C->getAPIntValue() == 0) {
8758 SDValue Cmp = Cond.getOperand(1);
8759 unsigned CC = cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
8760 if ((DAG.isEqualTo(Op1.getOperand(0), Cmp.getOperand(0)) &&
8761 DAG.isEqualTo(Op1.getOperand(1), Cmp.getOperand(1)) &&
8762 (CC == X86::COND_G || CC == X86::COND_GE ||
8763 CC == X86::COND_A || CC == X86::COND_AE)) ||
8764 (DAG.isEqualTo(Op1.getOperand(0), Cmp.getOperand(1)) &&
8765 DAG.isEqualTo(Op1.getOperand(1), Cmp.getOperand(0)) &&
8766 (CC == X86::COND_L || CC == X86::COND_LE ||
8767 CC == X86::COND_B || CC == X86::COND_BE))) {
8769 if (Op1.getOpcode() == ISD::SUB) {
8770 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i32);
8771 SDValue New = DAG.getNode(X86ISD::SUB, DL, VTs,
8772 Op1.getOperand(0), Op1.getOperand(1));
8773 DAG.ReplaceAllUsesWith(Op1, New);
8777 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
8778 unsigned NewCC = (CC == X86::COND_G || CC == X86::COND_GE ||
8779 CC == X86::COND_L ||
8780 CC == X86::COND_LE) ? X86::COND_GE : X86::COND_AE;
8781 SDValue Ops[] = { Op2, Op1, DAG.getConstant(NewCC, MVT::i8),
8782 SDValue(Op1.getNode(), 1) };
8783 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
8787 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
8788 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
8789 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
8790 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
8791 if (Cond.getOpcode() == X86ISD::SETCC &&
8792 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
8793 isZero(Cond.getOperand(1).getOperand(1))) {
8794 SDValue Cmp = Cond.getOperand(1);
8796 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
8798 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
8799 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
8800 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
8802 SDValue CmpOp0 = Cmp.getOperand(0);
8803 // Apply further optimizations for special cases
8804 // (select (x != 0), -1, 0) -> neg & sbb
8805 // (select (x == 0), 0, -1) -> neg & sbb
8806 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
8807 if (YC->isNullValue() &&
8808 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
8809 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
8810 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
8811 DAG.getConstant(0, CmpOp0.getValueType()),
8813 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8814 DAG.getConstant(X86::COND_B, MVT::i8),
8815 SDValue(Neg.getNode(), 1));
8819 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
8820 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
8821 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
8823 SDValue Res = // Res = 0 or -1.
8824 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8825 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
8827 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
8828 Res = DAG.getNOT(DL, Res, Res.getValueType());
8830 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
8831 if (N2C == 0 || !N2C->isNullValue())
8832 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
8837 // Look past (and (setcc_carry (cmp ...)), 1).
8838 if (Cond.getOpcode() == ISD::AND &&
8839 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
8840 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
8841 if (C && C->getAPIntValue() == 1)
8842 Cond = Cond.getOperand(0);
8845 // If condition flag is set by a X86ISD::CMP, then use it as the condition
8846 // setting operand in place of the X86ISD::SETCC.
8847 unsigned CondOpcode = Cond.getOpcode();
8848 if (CondOpcode == X86ISD::SETCC ||
8849 CondOpcode == X86ISD::SETCC_CARRY) {
8850 CC = Cond.getOperand(0);
8852 SDValue Cmp = Cond.getOperand(1);
8853 unsigned Opc = Cmp.getOpcode();
8854 EVT VT = Op.getValueType();
8856 bool IllegalFPCMov = false;
8857 if (VT.isFloatingPoint() && !VT.isVector() &&
8858 !isScalarFPTypeInSSEReg(VT)) // FPStack?
8859 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
8861 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
8862 Opc == X86ISD::BT) { // FIXME
8866 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
8867 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
8868 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
8869 Cond.getOperand(0).getValueType() != MVT::i8)) {
8870 SDValue LHS = Cond.getOperand(0);
8871 SDValue RHS = Cond.getOperand(1);
8875 switch (CondOpcode) {
8876 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
8877 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
8878 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
8879 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
8880 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
8881 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
8882 default: llvm_unreachable("unexpected overflowing operator");
8884 if (CondOpcode == ISD::UMULO)
8885 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
8888 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
8890 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
8892 if (CondOpcode == ISD::UMULO)
8893 Cond = X86Op.getValue(2);
8895 Cond = X86Op.getValue(1);
8897 CC = DAG.getConstant(X86Cond, MVT::i8);
8902 // Look pass the truncate.
8903 if (Cond.getOpcode() == ISD::TRUNCATE)
8904 Cond = Cond.getOperand(0);
8906 // We know the result of AND is compared against zero. Try to match
8908 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
8909 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
8910 if (NewSetCC.getNode()) {
8911 CC = NewSetCC.getOperand(0);
8912 Cond = NewSetCC.getOperand(1);
8919 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8920 Cond = EmitTest(Cond, X86::COND_NE, DAG);
8923 // a < b ? -1 : 0 -> RES = ~setcc_carry
8924 // a < b ? 0 : -1 -> RES = setcc_carry
8925 // a >= b ? -1 : 0 -> RES = setcc_carry
8926 // a >= b ? 0 : -1 -> RES = ~setcc_carry
8927 if (Cond.getOpcode() == X86ISD::CMP) {
8928 Cond = ConvertCmpIfNecessary(Cond, DAG);
8929 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
8931 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
8932 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
8933 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8934 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
8935 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
8936 return DAG.getNOT(DL, Res, Res.getValueType());
8941 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
8942 // condition is true.
8943 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
8944 SDValue Ops[] = { Op2, Op1, CC, Cond };
8945 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
8948 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
8949 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
8950 // from the AND / OR.
8951 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
8952 Opc = Op.getOpcode();
8953 if (Opc != ISD::OR && Opc != ISD::AND)
8955 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
8956 Op.getOperand(0).hasOneUse() &&
8957 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
8958 Op.getOperand(1).hasOneUse());
8961 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
8962 // 1 and that the SETCC node has a single use.
8963 static bool isXor1OfSetCC(SDValue Op) {
8964 if (Op.getOpcode() != ISD::XOR)
8966 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
8967 if (N1C && N1C->getAPIntValue() == 1) {
8968 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
8969 Op.getOperand(0).hasOneUse();
8974 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
8975 bool addTest = true;
8976 SDValue Chain = Op.getOperand(0);
8977 SDValue Cond = Op.getOperand(1);
8978 SDValue Dest = Op.getOperand(2);
8979 DebugLoc dl = Op.getDebugLoc();
8981 bool Inverted = false;
8983 if (Cond.getOpcode() == ISD::SETCC) {
8984 // Check for setcc([su]{add,sub,mul}o == 0).
8985 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
8986 isa<ConstantSDNode>(Cond.getOperand(1)) &&
8987 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
8988 Cond.getOperand(0).getResNo() == 1 &&
8989 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
8990 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
8991 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
8992 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
8993 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
8994 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
8996 Cond = Cond.getOperand(0);
8998 SDValue NewCond = LowerSETCC(Cond, DAG);
8999 if (NewCond.getNode())
9004 // FIXME: LowerXALUO doesn't handle these!!
9005 else if (Cond.getOpcode() == X86ISD::ADD ||
9006 Cond.getOpcode() == X86ISD::SUB ||
9007 Cond.getOpcode() == X86ISD::SMUL ||
9008 Cond.getOpcode() == X86ISD::UMUL)
9009 Cond = LowerXALUO(Cond, DAG);
9012 // Look pass (and (setcc_carry (cmp ...)), 1).
9013 if (Cond.getOpcode() == ISD::AND &&
9014 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
9015 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
9016 if (C && C->getAPIntValue() == 1)
9017 Cond = Cond.getOperand(0);
9020 // If condition flag is set by a X86ISD::CMP, then use it as the condition
9021 // setting operand in place of the X86ISD::SETCC.
9022 unsigned CondOpcode = Cond.getOpcode();
9023 if (CondOpcode == X86ISD::SETCC ||
9024 CondOpcode == X86ISD::SETCC_CARRY) {
9025 CC = Cond.getOperand(0);
9027 SDValue Cmp = Cond.getOperand(1);
9028 unsigned Opc = Cmp.getOpcode();
9029 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
9030 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
9034 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
9038 // These can only come from an arithmetic instruction with overflow,
9039 // e.g. SADDO, UADDO.
9040 Cond = Cond.getNode()->getOperand(1);
9046 CondOpcode = Cond.getOpcode();
9047 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
9048 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
9049 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
9050 Cond.getOperand(0).getValueType() != MVT::i8)) {
9051 SDValue LHS = Cond.getOperand(0);
9052 SDValue RHS = Cond.getOperand(1);
9056 switch (CondOpcode) {
9057 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
9058 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
9059 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
9060 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
9061 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
9062 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
9063 default: llvm_unreachable("unexpected overflowing operator");
9066 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
9067 if (CondOpcode == ISD::UMULO)
9068 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
9071 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
9073 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
9075 if (CondOpcode == ISD::UMULO)
9076 Cond = X86Op.getValue(2);
9078 Cond = X86Op.getValue(1);
9080 CC = DAG.getConstant(X86Cond, MVT::i8);
9084 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
9085 SDValue Cmp = Cond.getOperand(0).getOperand(1);
9086 if (CondOpc == ISD::OR) {
9087 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
9088 // two branches instead of an explicit OR instruction with a
9090 if (Cmp == Cond.getOperand(1).getOperand(1) &&
9091 isX86LogicalCmp(Cmp)) {
9092 CC = Cond.getOperand(0).getOperand(0);
9093 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
9094 Chain, Dest, CC, Cmp);
9095 CC = Cond.getOperand(1).getOperand(0);
9099 } else { // ISD::AND
9100 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
9101 // two branches instead of an explicit AND instruction with a
9102 // separate test. However, we only do this if this block doesn't
9103 // have a fall-through edge, because this requires an explicit
9104 // jmp when the condition is false.
9105 if (Cmp == Cond.getOperand(1).getOperand(1) &&
9106 isX86LogicalCmp(Cmp) &&
9107 Op.getNode()->hasOneUse()) {
9108 X86::CondCode CCode =
9109 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
9110 CCode = X86::GetOppositeBranchCondition(CCode);
9111 CC = DAG.getConstant(CCode, MVT::i8);
9112 SDNode *User = *Op.getNode()->use_begin();
9113 // Look for an unconditional branch following this conditional branch.
9114 // We need this because we need to reverse the successors in order
9115 // to implement FCMP_OEQ.
9116 if (User->getOpcode() == ISD::BR) {
9117 SDValue FalseBB = User->getOperand(1);
9119 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
9120 assert(NewBR == User);
9124 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
9125 Chain, Dest, CC, Cmp);
9126 X86::CondCode CCode =
9127 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
9128 CCode = X86::GetOppositeBranchCondition(CCode);
9129 CC = DAG.getConstant(CCode, MVT::i8);
9135 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
9136 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
9137 // It should be transformed during dag combiner except when the condition
9138 // is set by a arithmetics with overflow node.
9139 X86::CondCode CCode =
9140 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
9141 CCode = X86::GetOppositeBranchCondition(CCode);
9142 CC = DAG.getConstant(CCode, MVT::i8);
9143 Cond = Cond.getOperand(0).getOperand(1);
9145 } else if (Cond.getOpcode() == ISD::SETCC &&
9146 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
9147 // For FCMP_OEQ, we can emit
9148 // two branches instead of an explicit AND instruction with a
9149 // separate test. However, we only do this if this block doesn't
9150 // have a fall-through edge, because this requires an explicit
9151 // jmp when the condition is false.
9152 if (Op.getNode()->hasOneUse()) {
9153 SDNode *User = *Op.getNode()->use_begin();
9154 // Look for an unconditional branch following this conditional branch.
9155 // We need this because we need to reverse the successors in order
9156 // to implement FCMP_OEQ.
9157 if (User->getOpcode() == ISD::BR) {
9158 SDValue FalseBB = User->getOperand(1);
9160 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
9161 assert(NewBR == User);
9165 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
9166 Cond.getOperand(0), Cond.getOperand(1));
9167 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
9168 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
9169 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
9170 Chain, Dest, CC, Cmp);
9171 CC = DAG.getConstant(X86::COND_P, MVT::i8);
9176 } else if (Cond.getOpcode() == ISD::SETCC &&
9177 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
9178 // For FCMP_UNE, we can emit
9179 // two branches instead of an explicit AND instruction with a
9180 // separate test. However, we only do this if this block doesn't
9181 // have a fall-through edge, because this requires an explicit
9182 // jmp when the condition is false.
9183 if (Op.getNode()->hasOneUse()) {
9184 SDNode *User = *Op.getNode()->use_begin();
9185 // Look for an unconditional branch following this conditional branch.
9186 // We need this because we need to reverse the successors in order
9187 // to implement FCMP_UNE.
9188 if (User->getOpcode() == ISD::BR) {
9189 SDValue FalseBB = User->getOperand(1);
9191 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
9192 assert(NewBR == User);
9195 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
9196 Cond.getOperand(0), Cond.getOperand(1));
9197 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
9198 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
9199 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
9200 Chain, Dest, CC, Cmp);
9201 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
9211 // Look pass the truncate.
9212 if (Cond.getOpcode() == ISD::TRUNCATE)
9213 Cond = Cond.getOperand(0);
9215 // We know the result of AND is compared against zero. Try to match
9217 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
9218 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
9219 if (NewSetCC.getNode()) {
9220 CC = NewSetCC.getOperand(0);
9221 Cond = NewSetCC.getOperand(1);
9228 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
9229 Cond = EmitTest(Cond, X86::COND_NE, DAG);
9231 Cond = ConvertCmpIfNecessary(Cond, DAG);
9232 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
9233 Chain, Dest, CC, Cond);
9237 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
9238 // Calls to _alloca is needed to probe the stack when allocating more than 4k
9239 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
9240 // that the guard pages used by the OS virtual memory manager are allocated in
9241 // correct sequence.
9243 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
9244 SelectionDAG &DAG) const {
9245 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() ||
9246 getTargetMachine().Options.EnableSegmentedStacks) &&
9247 "This should be used only on Windows targets or when segmented stacks "
9249 assert(!Subtarget->isTargetEnvMacho() && "Not implemented");
9250 DebugLoc dl = Op.getDebugLoc();
9253 SDValue Chain = Op.getOperand(0);
9254 SDValue Size = Op.getOperand(1);
9255 // FIXME: Ensure alignment here
9257 bool Is64Bit = Subtarget->is64Bit();
9258 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32;
9260 if (getTargetMachine().Options.EnableSegmentedStacks) {
9261 MachineFunction &MF = DAG.getMachineFunction();
9262 MachineRegisterInfo &MRI = MF.getRegInfo();
9265 // The 64 bit implementation of segmented stacks needs to clobber both r10
9266 // r11. This makes it impossible to use it along with nested parameters.
9267 const Function *F = MF.getFunction();
9269 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
9271 if (I->hasNestAttr())
9272 report_fatal_error("Cannot use segmented stacks with functions that "
9273 "have nested arguments.");
9276 const TargetRegisterClass *AddrRegClass =
9277 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
9278 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
9279 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
9280 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
9281 DAG.getRegister(Vreg, SPTy));
9282 SDValue Ops1[2] = { Value, Chain };
9283 return DAG.getMergeValues(Ops1, 2, dl);
9286 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
9288 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
9289 Flag = Chain.getValue(1);
9290 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
9292 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
9293 Flag = Chain.getValue(1);
9295 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
9297 SDValue Ops1[2] = { Chain.getValue(0), Chain };
9298 return DAG.getMergeValues(Ops1, 2, dl);
9302 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
9303 MachineFunction &MF = DAG.getMachineFunction();
9304 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
9306 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
9307 DebugLoc DL = Op.getDebugLoc();
9309 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
9310 // vastart just stores the address of the VarArgsFrameIndex slot into the
9311 // memory location argument.
9312 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
9314 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
9315 MachinePointerInfo(SV), false, false, 0);
9319 // gp_offset (0 - 6 * 8)
9320 // fp_offset (48 - 48 + 8 * 16)
9321 // overflow_arg_area (point to parameters coming in memory).
9323 SmallVector<SDValue, 8> MemOps;
9324 SDValue FIN = Op.getOperand(1);
9326 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
9327 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
9329 FIN, MachinePointerInfo(SV), false, false, 0);
9330 MemOps.push_back(Store);
9333 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9334 FIN, DAG.getIntPtrConstant(4));
9335 Store = DAG.getStore(Op.getOperand(0), DL,
9336 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
9338 FIN, MachinePointerInfo(SV, 4), false, false, 0);
9339 MemOps.push_back(Store);
9341 // Store ptr to overflow_arg_area
9342 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9343 FIN, DAG.getIntPtrConstant(4));
9344 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
9346 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
9347 MachinePointerInfo(SV, 8),
9349 MemOps.push_back(Store);
9351 // Store ptr to reg_save_area.
9352 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9353 FIN, DAG.getIntPtrConstant(8));
9354 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
9356 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
9357 MachinePointerInfo(SV, 16), false, false, 0);
9358 MemOps.push_back(Store);
9359 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
9360 &MemOps[0], MemOps.size());
9363 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
9364 assert(Subtarget->is64Bit() &&
9365 "LowerVAARG only handles 64-bit va_arg!");
9366 assert((Subtarget->isTargetLinux() ||
9367 Subtarget->isTargetDarwin()) &&
9368 "Unhandled target in LowerVAARG");
9369 assert(Op.getNode()->getNumOperands() == 4);
9370 SDValue Chain = Op.getOperand(0);
9371 SDValue SrcPtr = Op.getOperand(1);
9372 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
9373 unsigned Align = Op.getConstantOperandVal(3);
9374 DebugLoc dl = Op.getDebugLoc();
9376 EVT ArgVT = Op.getNode()->getValueType(0);
9377 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
9378 uint32_t ArgSize = getTargetData()->getTypeAllocSize(ArgTy);
9381 // Decide which area this value should be read from.
9382 // TODO: Implement the AMD64 ABI in its entirety. This simple
9383 // selection mechanism works only for the basic types.
9384 if (ArgVT == MVT::f80) {
9385 llvm_unreachable("va_arg for f80 not yet implemented");
9386 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
9387 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
9388 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
9389 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
9391 llvm_unreachable("Unhandled argument type in LowerVAARG");
9395 // Sanity Check: Make sure using fp_offset makes sense.
9396 assert(!getTargetMachine().Options.UseSoftFloat &&
9397 !(DAG.getMachineFunction()
9398 .getFunction()->hasFnAttr(Attribute::NoImplicitFloat)) &&
9399 Subtarget->hasSSE1());
9402 // Insert VAARG_64 node into the DAG
9403 // VAARG_64 returns two values: Variable Argument Address, Chain
9404 SmallVector<SDValue, 11> InstOps;
9405 InstOps.push_back(Chain);
9406 InstOps.push_back(SrcPtr);
9407 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
9408 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
9409 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
9410 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
9411 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
9412 VTs, &InstOps[0], InstOps.size(),
9414 MachinePointerInfo(SV),
9419 Chain = VAARG.getValue(1);
9421 // Load the next argument and return it
9422 return DAG.getLoad(ArgVT, dl,
9425 MachinePointerInfo(),
9426 false, false, false, 0);
9429 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
9430 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
9431 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
9432 SDValue Chain = Op.getOperand(0);
9433 SDValue DstPtr = Op.getOperand(1);
9434 SDValue SrcPtr = Op.getOperand(2);
9435 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
9436 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
9437 DebugLoc DL = Op.getDebugLoc();
9439 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
9440 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
9442 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
9445 // getTargetVShiftNOde - Handle vector element shifts where the shift amount
9446 // may or may not be a constant. Takes immediate version of shift as input.
9447 static SDValue getTargetVShiftNode(unsigned Opc, DebugLoc dl, EVT VT,
9448 SDValue SrcOp, SDValue ShAmt,
9449 SelectionDAG &DAG) {
9450 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
9452 if (isa<ConstantSDNode>(ShAmt)) {
9454 default: llvm_unreachable("Unknown target vector shift node");
9458 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
9462 // Change opcode to non-immediate version
9464 default: llvm_unreachable("Unknown target vector shift node");
9465 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
9466 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
9467 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
9470 // Need to build a vector containing shift amount
9471 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
9474 ShOps[1] = DAG.getConstant(0, MVT::i32);
9475 ShOps[2] = DAG.getUNDEF(MVT::i32);
9476 ShOps[3] = DAG.getUNDEF(MVT::i32);
9477 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &ShOps[0], 4);
9478 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt);
9479 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
9483 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const {
9484 DebugLoc dl = Op.getDebugLoc();
9485 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9487 default: return SDValue(); // Don't custom lower most intrinsics.
9488 // Comparison intrinsics.
9489 case Intrinsic::x86_sse_comieq_ss:
9490 case Intrinsic::x86_sse_comilt_ss:
9491 case Intrinsic::x86_sse_comile_ss:
9492 case Intrinsic::x86_sse_comigt_ss:
9493 case Intrinsic::x86_sse_comige_ss:
9494 case Intrinsic::x86_sse_comineq_ss:
9495 case Intrinsic::x86_sse_ucomieq_ss:
9496 case Intrinsic::x86_sse_ucomilt_ss:
9497 case Intrinsic::x86_sse_ucomile_ss:
9498 case Intrinsic::x86_sse_ucomigt_ss:
9499 case Intrinsic::x86_sse_ucomige_ss:
9500 case Intrinsic::x86_sse_ucomineq_ss:
9501 case Intrinsic::x86_sse2_comieq_sd:
9502 case Intrinsic::x86_sse2_comilt_sd:
9503 case Intrinsic::x86_sse2_comile_sd:
9504 case Intrinsic::x86_sse2_comigt_sd:
9505 case Intrinsic::x86_sse2_comige_sd:
9506 case Intrinsic::x86_sse2_comineq_sd:
9507 case Intrinsic::x86_sse2_ucomieq_sd:
9508 case Intrinsic::x86_sse2_ucomilt_sd:
9509 case Intrinsic::x86_sse2_ucomile_sd:
9510 case Intrinsic::x86_sse2_ucomigt_sd:
9511 case Intrinsic::x86_sse2_ucomige_sd:
9512 case Intrinsic::x86_sse2_ucomineq_sd: {
9514 ISD::CondCode CC = ISD::SETCC_INVALID;
9516 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9517 case Intrinsic::x86_sse_comieq_ss:
9518 case Intrinsic::x86_sse2_comieq_sd:
9522 case Intrinsic::x86_sse_comilt_ss:
9523 case Intrinsic::x86_sse2_comilt_sd:
9527 case Intrinsic::x86_sse_comile_ss:
9528 case Intrinsic::x86_sse2_comile_sd:
9532 case Intrinsic::x86_sse_comigt_ss:
9533 case Intrinsic::x86_sse2_comigt_sd:
9537 case Intrinsic::x86_sse_comige_ss:
9538 case Intrinsic::x86_sse2_comige_sd:
9542 case Intrinsic::x86_sse_comineq_ss:
9543 case Intrinsic::x86_sse2_comineq_sd:
9547 case Intrinsic::x86_sse_ucomieq_ss:
9548 case Intrinsic::x86_sse2_ucomieq_sd:
9549 Opc = X86ISD::UCOMI;
9552 case Intrinsic::x86_sse_ucomilt_ss:
9553 case Intrinsic::x86_sse2_ucomilt_sd:
9554 Opc = X86ISD::UCOMI;
9557 case Intrinsic::x86_sse_ucomile_ss:
9558 case Intrinsic::x86_sse2_ucomile_sd:
9559 Opc = X86ISD::UCOMI;
9562 case Intrinsic::x86_sse_ucomigt_ss:
9563 case Intrinsic::x86_sse2_ucomigt_sd:
9564 Opc = X86ISD::UCOMI;
9567 case Intrinsic::x86_sse_ucomige_ss:
9568 case Intrinsic::x86_sse2_ucomige_sd:
9569 Opc = X86ISD::UCOMI;
9572 case Intrinsic::x86_sse_ucomineq_ss:
9573 case Intrinsic::x86_sse2_ucomineq_sd:
9574 Opc = X86ISD::UCOMI;
9579 SDValue LHS = Op.getOperand(1);
9580 SDValue RHS = Op.getOperand(2);
9581 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
9582 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
9583 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
9584 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9585 DAG.getConstant(X86CC, MVT::i8), Cond);
9586 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
9588 // Arithmetic intrinsics.
9589 case Intrinsic::x86_sse2_pmulu_dq:
9590 case Intrinsic::x86_avx2_pmulu_dq:
9591 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
9592 Op.getOperand(1), Op.getOperand(2));
9593 case Intrinsic::x86_sse3_hadd_ps:
9594 case Intrinsic::x86_sse3_hadd_pd:
9595 case Intrinsic::x86_avx_hadd_ps_256:
9596 case Intrinsic::x86_avx_hadd_pd_256:
9597 return DAG.getNode(X86ISD::FHADD, dl, Op.getValueType(),
9598 Op.getOperand(1), Op.getOperand(2));
9599 case Intrinsic::x86_sse3_hsub_ps:
9600 case Intrinsic::x86_sse3_hsub_pd:
9601 case Intrinsic::x86_avx_hsub_ps_256:
9602 case Intrinsic::x86_avx_hsub_pd_256:
9603 return DAG.getNode(X86ISD::FHSUB, dl, Op.getValueType(),
9604 Op.getOperand(1), Op.getOperand(2));
9605 case Intrinsic::x86_ssse3_phadd_w_128:
9606 case Intrinsic::x86_ssse3_phadd_d_128:
9607 case Intrinsic::x86_avx2_phadd_w:
9608 case Intrinsic::x86_avx2_phadd_d:
9609 return DAG.getNode(X86ISD::HADD, dl, Op.getValueType(),
9610 Op.getOperand(1), Op.getOperand(2));
9611 case Intrinsic::x86_ssse3_phsub_w_128:
9612 case Intrinsic::x86_ssse3_phsub_d_128:
9613 case Intrinsic::x86_avx2_phsub_w:
9614 case Intrinsic::x86_avx2_phsub_d:
9615 return DAG.getNode(X86ISD::HSUB, dl, Op.getValueType(),
9616 Op.getOperand(1), Op.getOperand(2));
9617 case Intrinsic::x86_avx2_psllv_d:
9618 case Intrinsic::x86_avx2_psllv_q:
9619 case Intrinsic::x86_avx2_psllv_d_256:
9620 case Intrinsic::x86_avx2_psllv_q_256:
9621 return DAG.getNode(ISD::SHL, dl, Op.getValueType(),
9622 Op.getOperand(1), Op.getOperand(2));
9623 case Intrinsic::x86_avx2_psrlv_d:
9624 case Intrinsic::x86_avx2_psrlv_q:
9625 case Intrinsic::x86_avx2_psrlv_d_256:
9626 case Intrinsic::x86_avx2_psrlv_q_256:
9627 return DAG.getNode(ISD::SRL, dl, Op.getValueType(),
9628 Op.getOperand(1), Op.getOperand(2));
9629 case Intrinsic::x86_avx2_psrav_d:
9630 case Intrinsic::x86_avx2_psrav_d_256:
9631 return DAG.getNode(ISD::SRA, dl, Op.getValueType(),
9632 Op.getOperand(1), Op.getOperand(2));
9633 case Intrinsic::x86_ssse3_pshuf_b_128:
9634 case Intrinsic::x86_avx2_pshuf_b:
9635 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
9636 Op.getOperand(1), Op.getOperand(2));
9637 case Intrinsic::x86_ssse3_psign_b_128:
9638 case Intrinsic::x86_ssse3_psign_w_128:
9639 case Intrinsic::x86_ssse3_psign_d_128:
9640 case Intrinsic::x86_avx2_psign_b:
9641 case Intrinsic::x86_avx2_psign_w:
9642 case Intrinsic::x86_avx2_psign_d:
9643 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
9644 Op.getOperand(1), Op.getOperand(2));
9645 case Intrinsic::x86_sse41_insertps:
9646 return DAG.getNode(X86ISD::INSERTPS, dl, Op.getValueType(),
9647 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
9648 case Intrinsic::x86_avx_vperm2f128_ps_256:
9649 case Intrinsic::x86_avx_vperm2f128_pd_256:
9650 case Intrinsic::x86_avx_vperm2f128_si_256:
9651 case Intrinsic::x86_avx2_vperm2i128:
9652 return DAG.getNode(X86ISD::VPERM2X128, dl, Op.getValueType(),
9653 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
9654 case Intrinsic::x86_avx2_permd:
9655 case Intrinsic::x86_avx2_permps:
9656 // Operands intentionally swapped. Mask is last operand to intrinsic,
9657 // but second operand for node/intruction.
9658 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
9659 Op.getOperand(2), Op.getOperand(1));
9661 // ptest and testp intrinsics. The intrinsic these come from are designed to
9662 // return an integer value, not just an instruction so lower it to the ptest
9663 // or testp pattern and a setcc for the result.
9664 case Intrinsic::x86_sse41_ptestz:
9665 case Intrinsic::x86_sse41_ptestc:
9666 case Intrinsic::x86_sse41_ptestnzc:
9667 case Intrinsic::x86_avx_ptestz_256:
9668 case Intrinsic::x86_avx_ptestc_256:
9669 case Intrinsic::x86_avx_ptestnzc_256:
9670 case Intrinsic::x86_avx_vtestz_ps:
9671 case Intrinsic::x86_avx_vtestc_ps:
9672 case Intrinsic::x86_avx_vtestnzc_ps:
9673 case Intrinsic::x86_avx_vtestz_pd:
9674 case Intrinsic::x86_avx_vtestc_pd:
9675 case Intrinsic::x86_avx_vtestnzc_pd:
9676 case Intrinsic::x86_avx_vtestz_ps_256:
9677 case Intrinsic::x86_avx_vtestc_ps_256:
9678 case Intrinsic::x86_avx_vtestnzc_ps_256:
9679 case Intrinsic::x86_avx_vtestz_pd_256:
9680 case Intrinsic::x86_avx_vtestc_pd_256:
9681 case Intrinsic::x86_avx_vtestnzc_pd_256: {
9682 bool IsTestPacked = false;
9685 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
9686 case Intrinsic::x86_avx_vtestz_ps:
9687 case Intrinsic::x86_avx_vtestz_pd:
9688 case Intrinsic::x86_avx_vtestz_ps_256:
9689 case Intrinsic::x86_avx_vtestz_pd_256:
9690 IsTestPacked = true; // Fallthrough
9691 case Intrinsic::x86_sse41_ptestz:
9692 case Intrinsic::x86_avx_ptestz_256:
9694 X86CC = X86::COND_E;
9696 case Intrinsic::x86_avx_vtestc_ps:
9697 case Intrinsic::x86_avx_vtestc_pd:
9698 case Intrinsic::x86_avx_vtestc_ps_256:
9699 case Intrinsic::x86_avx_vtestc_pd_256:
9700 IsTestPacked = true; // Fallthrough
9701 case Intrinsic::x86_sse41_ptestc:
9702 case Intrinsic::x86_avx_ptestc_256:
9704 X86CC = X86::COND_B;
9706 case Intrinsic::x86_avx_vtestnzc_ps:
9707 case Intrinsic::x86_avx_vtestnzc_pd:
9708 case Intrinsic::x86_avx_vtestnzc_ps_256:
9709 case Intrinsic::x86_avx_vtestnzc_pd_256:
9710 IsTestPacked = true; // Fallthrough
9711 case Intrinsic::x86_sse41_ptestnzc:
9712 case Intrinsic::x86_avx_ptestnzc_256:
9714 X86CC = X86::COND_A;
9718 SDValue LHS = Op.getOperand(1);
9719 SDValue RHS = Op.getOperand(2);
9720 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
9721 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
9722 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
9723 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
9724 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
9727 // SSE/AVX shift intrinsics
9728 case Intrinsic::x86_sse2_psll_w:
9729 case Intrinsic::x86_sse2_psll_d:
9730 case Intrinsic::x86_sse2_psll_q:
9731 case Intrinsic::x86_avx2_psll_w:
9732 case Intrinsic::x86_avx2_psll_d:
9733 case Intrinsic::x86_avx2_psll_q:
9734 return DAG.getNode(X86ISD::VSHL, dl, Op.getValueType(),
9735 Op.getOperand(1), Op.getOperand(2));
9736 case Intrinsic::x86_sse2_psrl_w:
9737 case Intrinsic::x86_sse2_psrl_d:
9738 case Intrinsic::x86_sse2_psrl_q:
9739 case Intrinsic::x86_avx2_psrl_w:
9740 case Intrinsic::x86_avx2_psrl_d:
9741 case Intrinsic::x86_avx2_psrl_q:
9742 return DAG.getNode(X86ISD::VSRL, dl, Op.getValueType(),
9743 Op.getOperand(1), Op.getOperand(2));
9744 case Intrinsic::x86_sse2_psra_w:
9745 case Intrinsic::x86_sse2_psra_d:
9746 case Intrinsic::x86_avx2_psra_w:
9747 case Intrinsic::x86_avx2_psra_d:
9748 return DAG.getNode(X86ISD::VSRA, dl, Op.getValueType(),
9749 Op.getOperand(1), Op.getOperand(2));
9750 case Intrinsic::x86_sse2_pslli_w:
9751 case Intrinsic::x86_sse2_pslli_d:
9752 case Intrinsic::x86_sse2_pslli_q:
9753 case Intrinsic::x86_avx2_pslli_w:
9754 case Intrinsic::x86_avx2_pslli_d:
9755 case Intrinsic::x86_avx2_pslli_q:
9756 return getTargetVShiftNode(X86ISD::VSHLI, dl, Op.getValueType(),
9757 Op.getOperand(1), Op.getOperand(2), DAG);
9758 case Intrinsic::x86_sse2_psrli_w:
9759 case Intrinsic::x86_sse2_psrli_d:
9760 case Intrinsic::x86_sse2_psrli_q:
9761 case Intrinsic::x86_avx2_psrli_w:
9762 case Intrinsic::x86_avx2_psrli_d:
9763 case Intrinsic::x86_avx2_psrli_q:
9764 return getTargetVShiftNode(X86ISD::VSRLI, dl, Op.getValueType(),
9765 Op.getOperand(1), Op.getOperand(2), DAG);
9766 case Intrinsic::x86_sse2_psrai_w:
9767 case Intrinsic::x86_sse2_psrai_d:
9768 case Intrinsic::x86_avx2_psrai_w:
9769 case Intrinsic::x86_avx2_psrai_d:
9770 return getTargetVShiftNode(X86ISD::VSRAI, dl, Op.getValueType(),
9771 Op.getOperand(1), Op.getOperand(2), DAG);
9772 // Fix vector shift instructions where the last operand is a non-immediate
9774 case Intrinsic::x86_mmx_pslli_w:
9775 case Intrinsic::x86_mmx_pslli_d:
9776 case Intrinsic::x86_mmx_pslli_q:
9777 case Intrinsic::x86_mmx_psrli_w:
9778 case Intrinsic::x86_mmx_psrli_d:
9779 case Intrinsic::x86_mmx_psrli_q:
9780 case Intrinsic::x86_mmx_psrai_w:
9781 case Intrinsic::x86_mmx_psrai_d: {
9782 SDValue ShAmt = Op.getOperand(2);
9783 if (isa<ConstantSDNode>(ShAmt))
9786 unsigned NewIntNo = 0;
9788 case Intrinsic::x86_mmx_pslli_w:
9789 NewIntNo = Intrinsic::x86_mmx_psll_w;
9791 case Intrinsic::x86_mmx_pslli_d:
9792 NewIntNo = Intrinsic::x86_mmx_psll_d;
9794 case Intrinsic::x86_mmx_pslli_q:
9795 NewIntNo = Intrinsic::x86_mmx_psll_q;
9797 case Intrinsic::x86_mmx_psrli_w:
9798 NewIntNo = Intrinsic::x86_mmx_psrl_w;
9800 case Intrinsic::x86_mmx_psrli_d:
9801 NewIntNo = Intrinsic::x86_mmx_psrl_d;
9803 case Intrinsic::x86_mmx_psrli_q:
9804 NewIntNo = Intrinsic::x86_mmx_psrl_q;
9806 case Intrinsic::x86_mmx_psrai_w:
9807 NewIntNo = Intrinsic::x86_mmx_psra_w;
9809 case Intrinsic::x86_mmx_psrai_d:
9810 NewIntNo = Intrinsic::x86_mmx_psra_d;
9812 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9815 // The vector shift intrinsics with scalars uses 32b shift amounts but
9816 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
9818 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, ShAmt,
9819 DAG.getConstant(0, MVT::i32));
9820 // FIXME this must be lowered to get rid of the invalid type.
9822 EVT VT = Op.getValueType();
9823 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt);
9824 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9825 DAG.getConstant(NewIntNo, MVT::i32),
9826 Op.getOperand(1), ShAmt);
9831 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
9832 SelectionDAG &DAG) const {
9833 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9834 MFI->setReturnAddressIsTaken(true);
9836 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9837 DebugLoc dl = Op.getDebugLoc();
9840 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
9842 DAG.getConstant(TD->getPointerSize(),
9843 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
9844 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9845 DAG.getNode(ISD::ADD, dl, getPointerTy(),
9847 MachinePointerInfo(), false, false, false, 0);
9850 // Just load the return address.
9851 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
9852 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9853 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
9856 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
9857 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9858 MFI->setFrameAddressIsTaken(true);
9860 EVT VT = Op.getValueType();
9861 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
9862 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9863 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
9864 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
9866 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
9867 MachinePointerInfo(),
9868 false, false, false, 0);
9872 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
9873 SelectionDAG &DAG) const {
9874 return DAG.getIntPtrConstant(2*TD->getPointerSize());
9877 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
9878 SDValue Chain = Op.getOperand(0);
9879 SDValue Offset = Op.getOperand(1);
9880 SDValue Handler = Op.getOperand(2);
9881 DebugLoc dl = Op.getDebugLoc();
9883 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
9884 Subtarget->is64Bit() ? X86::RBP : X86::EBP,
9886 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
9888 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame,
9889 DAG.getIntPtrConstant(TD->getPointerSize()));
9890 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
9891 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
9893 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
9895 return DAG.getNode(X86ISD::EH_RETURN, dl,
9897 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
9900 SDValue X86TargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
9901 SelectionDAG &DAG) const {
9902 return Op.getOperand(0);
9905 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
9906 SelectionDAG &DAG) const {
9907 SDValue Root = Op.getOperand(0);
9908 SDValue Trmp = Op.getOperand(1); // trampoline
9909 SDValue FPtr = Op.getOperand(2); // nested function
9910 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
9911 DebugLoc dl = Op.getDebugLoc();
9913 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
9915 if (Subtarget->is64Bit()) {
9916 SDValue OutChains[6];
9918 // Large code-model.
9919 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
9920 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
9922 const unsigned char N86R10 = X86_MC::getX86RegNum(X86::R10);
9923 const unsigned char N86R11 = X86_MC::getX86RegNum(X86::R11);
9925 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
9927 // Load the pointer to the nested function into R11.
9928 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
9929 SDValue Addr = Trmp;
9930 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9931 Addr, MachinePointerInfo(TrmpAddr),
9934 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9935 DAG.getConstant(2, MVT::i64));
9936 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
9937 MachinePointerInfo(TrmpAddr, 2),
9940 // Load the 'nest' parameter value into R10.
9941 // R10 is specified in X86CallingConv.td
9942 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
9943 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9944 DAG.getConstant(10, MVT::i64));
9945 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9946 Addr, MachinePointerInfo(TrmpAddr, 10),
9949 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9950 DAG.getConstant(12, MVT::i64));
9951 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
9952 MachinePointerInfo(TrmpAddr, 12),
9955 // Jump to the nested function.
9956 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
9957 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9958 DAG.getConstant(20, MVT::i64));
9959 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9960 Addr, MachinePointerInfo(TrmpAddr, 20),
9963 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
9964 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9965 DAG.getConstant(22, MVT::i64));
9966 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
9967 MachinePointerInfo(TrmpAddr, 22),
9970 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6);
9972 const Function *Func =
9973 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
9974 CallingConv::ID CC = Func->getCallingConv();
9979 llvm_unreachable("Unsupported calling convention");
9980 case CallingConv::C:
9981 case CallingConv::X86_StdCall: {
9982 // Pass 'nest' parameter in ECX.
9983 // Must be kept in sync with X86CallingConv.td
9986 // Check that ECX wasn't needed by an 'inreg' parameter.
9987 FunctionType *FTy = Func->getFunctionType();
9988 const AttrListPtr &Attrs = Func->getAttributes();
9990 if (!Attrs.isEmpty() && !Func->isVarArg()) {
9991 unsigned InRegCount = 0;
9994 for (FunctionType::param_iterator I = FTy->param_begin(),
9995 E = FTy->param_end(); I != E; ++I, ++Idx)
9996 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
9997 // FIXME: should only count parameters that are lowered to integers.
9998 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
10000 if (InRegCount > 2) {
10001 report_fatal_error("Nest register in use - reduce number of inreg"
10007 case CallingConv::X86_FastCall:
10008 case CallingConv::X86_ThisCall:
10009 case CallingConv::Fast:
10010 // Pass 'nest' parameter in EAX.
10011 // Must be kept in sync with X86CallingConv.td
10012 NestReg = X86::EAX;
10016 SDValue OutChains[4];
10017 SDValue Addr, Disp;
10019 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
10020 DAG.getConstant(10, MVT::i32));
10021 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
10023 // This is storing the opcode for MOV32ri.
10024 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
10025 const unsigned char N86Reg = X86_MC::getX86RegNum(NestReg);
10026 OutChains[0] = DAG.getStore(Root, dl,
10027 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
10028 Trmp, MachinePointerInfo(TrmpAddr),
10031 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
10032 DAG.getConstant(1, MVT::i32));
10033 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
10034 MachinePointerInfo(TrmpAddr, 1),
10037 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
10038 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
10039 DAG.getConstant(5, MVT::i32));
10040 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
10041 MachinePointerInfo(TrmpAddr, 5),
10044 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
10045 DAG.getConstant(6, MVT::i32));
10046 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
10047 MachinePointerInfo(TrmpAddr, 6),
10050 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4);
10054 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
10055 SelectionDAG &DAG) const {
10057 The rounding mode is in bits 11:10 of FPSR, and has the following
10059 00 Round to nearest
10064 FLT_ROUNDS, on the other hand, expects the following:
10071 To perform the conversion, we do:
10072 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
10075 MachineFunction &MF = DAG.getMachineFunction();
10076 const TargetMachine &TM = MF.getTarget();
10077 const TargetFrameLowering &TFI = *TM.getFrameLowering();
10078 unsigned StackAlignment = TFI.getStackAlignment();
10079 EVT VT = Op.getValueType();
10080 DebugLoc DL = Op.getDebugLoc();
10082 // Save FP Control Word to stack slot
10083 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
10084 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
10087 MachineMemOperand *MMO =
10088 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
10089 MachineMemOperand::MOStore, 2, 2);
10091 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
10092 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
10093 DAG.getVTList(MVT::Other),
10094 Ops, 2, MVT::i16, MMO);
10096 // Load FP Control Word from stack slot
10097 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
10098 MachinePointerInfo(), false, false, false, 0);
10100 // Transform as necessary
10102 DAG.getNode(ISD::SRL, DL, MVT::i16,
10103 DAG.getNode(ISD::AND, DL, MVT::i16,
10104 CWD, DAG.getConstant(0x800, MVT::i16)),
10105 DAG.getConstant(11, MVT::i8));
10107 DAG.getNode(ISD::SRL, DL, MVT::i16,
10108 DAG.getNode(ISD::AND, DL, MVT::i16,
10109 CWD, DAG.getConstant(0x400, MVT::i16)),
10110 DAG.getConstant(9, MVT::i8));
10113 DAG.getNode(ISD::AND, DL, MVT::i16,
10114 DAG.getNode(ISD::ADD, DL, MVT::i16,
10115 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
10116 DAG.getConstant(1, MVT::i16)),
10117 DAG.getConstant(3, MVT::i16));
10120 return DAG.getNode((VT.getSizeInBits() < 16 ?
10121 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
10124 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const {
10125 EVT VT = Op.getValueType();
10127 unsigned NumBits = VT.getSizeInBits();
10128 DebugLoc dl = Op.getDebugLoc();
10130 Op = Op.getOperand(0);
10131 if (VT == MVT::i8) {
10132 // Zero extend to i32 since there is not an i8 bsr.
10134 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
10137 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
10138 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
10139 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
10141 // If src is zero (i.e. bsr sets ZF), returns NumBits.
10144 DAG.getConstant(NumBits+NumBits-1, OpVT),
10145 DAG.getConstant(X86::COND_E, MVT::i8),
10148 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
10150 // Finally xor with NumBits-1.
10151 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
10154 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
10158 SDValue X86TargetLowering::LowerCTLZ_ZERO_UNDEF(SDValue Op,
10159 SelectionDAG &DAG) const {
10160 EVT VT = Op.getValueType();
10162 unsigned NumBits = VT.getSizeInBits();
10163 DebugLoc dl = Op.getDebugLoc();
10165 Op = Op.getOperand(0);
10166 if (VT == MVT::i8) {
10167 // Zero extend to i32 since there is not an i8 bsr.
10169 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
10172 // Issue a bsr (scan bits in reverse).
10173 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
10174 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
10176 // And xor with NumBits-1.
10177 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
10180 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
10184 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const {
10185 EVT VT = Op.getValueType();
10186 unsigned NumBits = VT.getSizeInBits();
10187 DebugLoc dl = Op.getDebugLoc();
10188 Op = Op.getOperand(0);
10190 // Issue a bsf (scan bits forward) which also sets EFLAGS.
10191 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
10192 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
10194 // If src is zero (i.e. bsf sets ZF), returns NumBits.
10197 DAG.getConstant(NumBits, VT),
10198 DAG.getConstant(X86::COND_E, MVT::i8),
10201 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops, array_lengthof(Ops));
10204 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
10205 // ones, and then concatenate the result back.
10206 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
10207 EVT VT = Op.getValueType();
10209 assert(VT.getSizeInBits() == 256 && VT.isInteger() &&
10210 "Unsupported value type for operation");
10212 unsigned NumElems = VT.getVectorNumElements();
10213 DebugLoc dl = Op.getDebugLoc();
10215 // Extract the LHS vectors
10216 SDValue LHS = Op.getOperand(0);
10217 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
10218 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
10220 // Extract the RHS vectors
10221 SDValue RHS = Op.getOperand(1);
10222 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
10223 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
10225 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10226 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10228 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
10229 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
10230 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
10233 SDValue X86TargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) const {
10234 assert(Op.getValueType().getSizeInBits() == 256 &&
10235 Op.getValueType().isInteger() &&
10236 "Only handle AVX 256-bit vector integer operation");
10237 return Lower256IntArith(Op, DAG);
10240 SDValue X86TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) const {
10241 assert(Op.getValueType().getSizeInBits() == 256 &&
10242 Op.getValueType().isInteger() &&
10243 "Only handle AVX 256-bit vector integer operation");
10244 return Lower256IntArith(Op, DAG);
10247 SDValue X86TargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
10248 EVT VT = Op.getValueType();
10250 // Decompose 256-bit ops into smaller 128-bit ops.
10251 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2())
10252 return Lower256IntArith(Op, DAG);
10254 assert((VT == MVT::v2i64 || VT == MVT::v4i64) &&
10255 "Only know how to lower V2I64/V4I64 multiply");
10257 DebugLoc dl = Op.getDebugLoc();
10259 // Ahi = psrlqi(a, 32);
10260 // Bhi = psrlqi(b, 32);
10262 // AloBlo = pmuludq(a, b);
10263 // AloBhi = pmuludq(a, Bhi);
10264 // AhiBlo = pmuludq(Ahi, b);
10266 // AloBhi = psllqi(AloBhi, 32);
10267 // AhiBlo = psllqi(AhiBlo, 32);
10268 // return AloBlo + AloBhi + AhiBlo;
10270 SDValue A = Op.getOperand(0);
10271 SDValue B = Op.getOperand(1);
10273 SDValue ShAmt = DAG.getConstant(32, MVT::i32);
10275 SDValue Ahi = DAG.getNode(X86ISD::VSRLI, dl, VT, A, ShAmt);
10276 SDValue Bhi = DAG.getNode(X86ISD::VSRLI, dl, VT, B, ShAmt);
10278 // Bit cast to 32-bit vectors for MULUDQ
10279 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 : MVT::v8i32;
10280 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
10281 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
10282 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
10283 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
10285 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
10286 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
10287 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
10289 AloBhi = DAG.getNode(X86ISD::VSHLI, dl, VT, AloBhi, ShAmt);
10290 AhiBlo = DAG.getNode(X86ISD::VSHLI, dl, VT, AhiBlo, ShAmt);
10292 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
10293 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
10296 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
10298 EVT VT = Op.getValueType();
10299 DebugLoc dl = Op.getDebugLoc();
10300 SDValue R = Op.getOperand(0);
10301 SDValue Amt = Op.getOperand(1);
10302 LLVMContext *Context = DAG.getContext();
10304 if (!Subtarget->hasSSE2())
10307 // Optimize shl/srl/sra with constant shift amount.
10308 if (isSplatVector(Amt.getNode())) {
10309 SDValue SclrAmt = Amt->getOperand(0);
10310 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
10311 uint64_t ShiftAmt = C->getZExtValue();
10313 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
10314 (Subtarget->hasAVX2() &&
10315 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16))) {
10316 if (Op.getOpcode() == ISD::SHL)
10317 return DAG.getNode(X86ISD::VSHLI, dl, VT, R,
10318 DAG.getConstant(ShiftAmt, MVT::i32));
10319 if (Op.getOpcode() == ISD::SRL)
10320 return DAG.getNode(X86ISD::VSRLI, dl, VT, R,
10321 DAG.getConstant(ShiftAmt, MVT::i32));
10322 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
10323 return DAG.getNode(X86ISD::VSRAI, dl, VT, R,
10324 DAG.getConstant(ShiftAmt, MVT::i32));
10327 if (VT == MVT::v16i8) {
10328 if (Op.getOpcode() == ISD::SHL) {
10329 // Make a large shift.
10330 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, R,
10331 DAG.getConstant(ShiftAmt, MVT::i32));
10332 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
10333 // Zero out the rightmost bits.
10334 SmallVector<SDValue, 16> V(16,
10335 DAG.getConstant(uint8_t(-1U << ShiftAmt),
10337 return DAG.getNode(ISD::AND, dl, VT, SHL,
10338 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
10340 if (Op.getOpcode() == ISD::SRL) {
10341 // Make a large shift.
10342 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v8i16, R,
10343 DAG.getConstant(ShiftAmt, MVT::i32));
10344 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
10345 // Zero out the leftmost bits.
10346 SmallVector<SDValue, 16> V(16,
10347 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
10349 return DAG.getNode(ISD::AND, dl, VT, SRL,
10350 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
10352 if (Op.getOpcode() == ISD::SRA) {
10353 if (ShiftAmt == 7) {
10354 // R s>> 7 === R s< 0
10355 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
10356 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
10359 // R s>> a === ((R u>> a) ^ m) - m
10360 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
10361 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
10363 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16);
10364 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
10365 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
10368 llvm_unreachable("Unknown shift opcode.");
10371 if (Subtarget->hasAVX2() && VT == MVT::v32i8) {
10372 if (Op.getOpcode() == ISD::SHL) {
10373 // Make a large shift.
10374 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v16i16, R,
10375 DAG.getConstant(ShiftAmt, MVT::i32));
10376 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
10377 // Zero out the rightmost bits.
10378 SmallVector<SDValue, 32> V(32,
10379 DAG.getConstant(uint8_t(-1U << ShiftAmt),
10381 return DAG.getNode(ISD::AND, dl, VT, SHL,
10382 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
10384 if (Op.getOpcode() == ISD::SRL) {
10385 // Make a large shift.
10386 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v16i16, R,
10387 DAG.getConstant(ShiftAmt, MVT::i32));
10388 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
10389 // Zero out the leftmost bits.
10390 SmallVector<SDValue, 32> V(32,
10391 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
10393 return DAG.getNode(ISD::AND, dl, VT, SRL,
10394 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
10396 if (Op.getOpcode() == ISD::SRA) {
10397 if (ShiftAmt == 7) {
10398 // R s>> 7 === R s< 0
10399 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
10400 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
10403 // R s>> a === ((R u>> a) ^ m) - m
10404 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
10405 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
10407 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32);
10408 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
10409 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
10412 llvm_unreachable("Unknown shift opcode.");
10417 // Lower SHL with variable shift amount.
10418 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
10419 Op = DAG.getNode(X86ISD::VSHLI, dl, VT, Op.getOperand(1),
10420 DAG.getConstant(23, MVT::i32));
10422 const uint32_t CV[] = { 0x3f800000U, 0x3f800000U, 0x3f800000U, 0x3f800000U};
10423 Constant *C = ConstantDataVector::get(*Context, CV);
10424 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
10425 SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
10426 MachinePointerInfo::getConstantPool(),
10427 false, false, false, 16);
10429 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend);
10430 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
10431 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
10432 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
10434 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
10435 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
10438 Op = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, Op.getOperand(1),
10439 DAG.getConstant(5, MVT::i32));
10440 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
10442 // Turn 'a' into a mask suitable for VSELECT
10443 SDValue VSelM = DAG.getConstant(0x80, VT);
10444 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10445 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
10447 SDValue CM1 = DAG.getConstant(0x0f, VT);
10448 SDValue CM2 = DAG.getConstant(0x3f, VT);
10450 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
10451 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
10452 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M,
10453 DAG.getConstant(4, MVT::i32), DAG);
10454 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
10455 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
10458 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
10459 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10460 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
10462 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
10463 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
10464 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M,
10465 DAG.getConstant(2, MVT::i32), DAG);
10466 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
10467 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
10470 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
10471 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10472 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
10474 // return VSELECT(r, r+r, a);
10475 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
10476 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
10480 // Decompose 256-bit shifts into smaller 128-bit shifts.
10481 if (VT.getSizeInBits() == 256) {
10482 unsigned NumElems = VT.getVectorNumElements();
10483 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10484 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10486 // Extract the two vectors
10487 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
10488 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
10490 // Recreate the shift amount vectors
10491 SDValue Amt1, Amt2;
10492 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
10493 // Constant shift amount
10494 SmallVector<SDValue, 4> Amt1Csts;
10495 SmallVector<SDValue, 4> Amt2Csts;
10496 for (unsigned i = 0; i != NumElems/2; ++i)
10497 Amt1Csts.push_back(Amt->getOperand(i));
10498 for (unsigned i = NumElems/2; i != NumElems; ++i)
10499 Amt2Csts.push_back(Amt->getOperand(i));
10501 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
10502 &Amt1Csts[0], NumElems/2);
10503 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
10504 &Amt2Csts[0], NumElems/2);
10506 // Variable shift amount
10507 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
10508 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
10511 // Issue new vector shifts for the smaller types
10512 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
10513 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
10515 // Concatenate the result back
10516 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
10522 SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {
10523 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
10524 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
10525 // looks for this combo and may remove the "setcc" instruction if the "setcc"
10526 // has only one use.
10527 SDNode *N = Op.getNode();
10528 SDValue LHS = N->getOperand(0);
10529 SDValue RHS = N->getOperand(1);
10530 unsigned BaseOp = 0;
10532 DebugLoc DL = Op.getDebugLoc();
10533 switch (Op.getOpcode()) {
10534 default: llvm_unreachable("Unknown ovf instruction!");
10536 // A subtract of one will be selected as a INC. Note that INC doesn't
10537 // set CF, so we can't do this for UADDO.
10538 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
10540 BaseOp = X86ISD::INC;
10541 Cond = X86::COND_O;
10544 BaseOp = X86ISD::ADD;
10545 Cond = X86::COND_O;
10548 BaseOp = X86ISD::ADD;
10549 Cond = X86::COND_B;
10552 // A subtract of one will be selected as a DEC. Note that DEC doesn't
10553 // set CF, so we can't do this for USUBO.
10554 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
10556 BaseOp = X86ISD::DEC;
10557 Cond = X86::COND_O;
10560 BaseOp = X86ISD::SUB;
10561 Cond = X86::COND_O;
10564 BaseOp = X86ISD::SUB;
10565 Cond = X86::COND_B;
10568 BaseOp = X86ISD::SMUL;
10569 Cond = X86::COND_O;
10571 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
10572 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
10574 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
10577 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
10578 DAG.getConstant(X86::COND_O, MVT::i32),
10579 SDValue(Sum.getNode(), 2));
10581 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
10585 // Also sets EFLAGS.
10586 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
10587 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
10590 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
10591 DAG.getConstant(Cond, MVT::i32),
10592 SDValue(Sum.getNode(), 1));
10594 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
10597 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
10598 SelectionDAG &DAG) const {
10599 DebugLoc dl = Op.getDebugLoc();
10600 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
10601 EVT VT = Op.getValueType();
10603 if (!Subtarget->hasSSE2() || !VT.isVector())
10606 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
10607 ExtraVT.getScalarType().getSizeInBits();
10608 SDValue ShAmt = DAG.getConstant(BitsDiff, MVT::i32);
10610 switch (VT.getSimpleVT().SimpleTy) {
10611 default: return SDValue();
10614 if (!Subtarget->hasAVX())
10616 if (!Subtarget->hasAVX2()) {
10617 // needs to be split
10618 unsigned NumElems = VT.getVectorNumElements();
10620 // Extract the LHS vectors
10621 SDValue LHS = Op.getOperand(0);
10622 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
10623 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
10625 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10626 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10628 EVT ExtraEltVT = ExtraVT.getVectorElementType();
10629 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
10630 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
10632 SDValue Extra = DAG.getValueType(ExtraVT);
10634 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
10635 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
10637 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);;
10642 SDValue Tmp1 = getTargetVShiftNode(X86ISD::VSHLI, dl, VT,
10643 Op.getOperand(0), ShAmt, DAG);
10644 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, Tmp1, ShAmt, DAG);
10650 SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{
10651 DebugLoc dl = Op.getDebugLoc();
10653 // Go ahead and emit the fence on x86-64 even if we asked for no-sse2.
10654 // There isn't any reason to disable it if the target processor supports it.
10655 if (!Subtarget->hasSSE2() && !Subtarget->is64Bit()) {
10656 SDValue Chain = Op.getOperand(0);
10657 SDValue Zero = DAG.getConstant(0, MVT::i32);
10659 DAG.getRegister(X86::ESP, MVT::i32), // Base
10660 DAG.getTargetConstant(1, MVT::i8), // Scale
10661 DAG.getRegister(0, MVT::i32), // Index
10662 DAG.getTargetConstant(0, MVT::i32), // Disp
10663 DAG.getRegister(0, MVT::i32), // Segment.
10668 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
10669 array_lengthof(Ops));
10670 return SDValue(Res, 0);
10673 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue();
10675 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
10677 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10678 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
10679 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
10680 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
10682 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
10683 if (!Op1 && !Op2 && !Op3 && Op4)
10684 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0));
10686 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
10687 if (Op1 && !Op2 && !Op3 && !Op4)
10688 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0));
10690 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)),
10692 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
10695 SDValue X86TargetLowering::LowerATOMIC_FENCE(SDValue Op,
10696 SelectionDAG &DAG) const {
10697 DebugLoc dl = Op.getDebugLoc();
10698 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
10699 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
10700 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
10701 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
10703 // The only fence that needs an instruction is a sequentially-consistent
10704 // cross-thread fence.
10705 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
10706 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
10707 // no-sse2). There isn't any reason to disable it if the target processor
10709 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
10710 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
10712 SDValue Chain = Op.getOperand(0);
10713 SDValue Zero = DAG.getConstant(0, MVT::i32);
10715 DAG.getRegister(X86::ESP, MVT::i32), // Base
10716 DAG.getTargetConstant(1, MVT::i8), // Scale
10717 DAG.getRegister(0, MVT::i32), // Index
10718 DAG.getTargetConstant(0, MVT::i32), // Disp
10719 DAG.getRegister(0, MVT::i32), // Segment.
10724 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
10725 array_lengthof(Ops));
10726 return SDValue(Res, 0);
10729 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
10730 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
10734 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const {
10735 EVT T = Op.getValueType();
10736 DebugLoc DL = Op.getDebugLoc();
10739 switch(T.getSimpleVT().SimpleTy) {
10740 default: llvm_unreachable("Invalid value type!");
10741 case MVT::i8: Reg = X86::AL; size = 1; break;
10742 case MVT::i16: Reg = X86::AX; size = 2; break;
10743 case MVT::i32: Reg = X86::EAX; size = 4; break;
10745 assert(Subtarget->is64Bit() && "Node not type legal!");
10746 Reg = X86::RAX; size = 8;
10749 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
10750 Op.getOperand(2), SDValue());
10751 SDValue Ops[] = { cpIn.getValue(0),
10754 DAG.getTargetConstant(size, MVT::i8),
10755 cpIn.getValue(1) };
10756 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10757 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
10758 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
10761 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
10765 SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
10766 SelectionDAG &DAG) const {
10767 assert(Subtarget->is64Bit() && "Result not type legalized?");
10768 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10769 SDValue TheChain = Op.getOperand(0);
10770 DebugLoc dl = Op.getDebugLoc();
10771 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
10772 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
10773 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
10775 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
10776 DAG.getConstant(32, MVT::i8));
10778 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
10781 return DAG.getMergeValues(Ops, 2, dl);
10784 SDValue X86TargetLowering::LowerBITCAST(SDValue Op,
10785 SelectionDAG &DAG) const {
10786 EVT SrcVT = Op.getOperand(0).getValueType();
10787 EVT DstVT = Op.getValueType();
10788 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
10789 Subtarget->hasMMX() && "Unexpected custom BITCAST");
10790 assert((DstVT == MVT::i64 ||
10791 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
10792 "Unexpected custom BITCAST");
10793 // i64 <=> MMX conversions are Legal.
10794 if (SrcVT==MVT::i64 && DstVT.isVector())
10796 if (DstVT==MVT::i64 && SrcVT.isVector())
10798 // MMX <=> MMX conversions are Legal.
10799 if (SrcVT.isVector() && DstVT.isVector())
10801 // All other conversions need to be expanded.
10805 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const {
10806 SDNode *Node = Op.getNode();
10807 DebugLoc dl = Node->getDebugLoc();
10808 EVT T = Node->getValueType(0);
10809 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
10810 DAG.getConstant(0, T), Node->getOperand(2));
10811 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
10812 cast<AtomicSDNode>(Node)->getMemoryVT(),
10813 Node->getOperand(0),
10814 Node->getOperand(1), negOp,
10815 cast<AtomicSDNode>(Node)->getSrcValue(),
10816 cast<AtomicSDNode>(Node)->getAlignment(),
10817 cast<AtomicSDNode>(Node)->getOrdering(),
10818 cast<AtomicSDNode>(Node)->getSynchScope());
10821 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
10822 SDNode *Node = Op.getNode();
10823 DebugLoc dl = Node->getDebugLoc();
10824 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
10826 // Convert seq_cst store -> xchg
10827 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
10828 // FIXME: On 32-bit, store -> fist or movq would be more efficient
10829 // (The only way to get a 16-byte store is cmpxchg16b)
10830 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
10831 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
10832 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
10833 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
10834 cast<AtomicSDNode>(Node)->getMemoryVT(),
10835 Node->getOperand(0),
10836 Node->getOperand(1), Node->getOperand(2),
10837 cast<AtomicSDNode>(Node)->getMemOperand(),
10838 cast<AtomicSDNode>(Node)->getOrdering(),
10839 cast<AtomicSDNode>(Node)->getSynchScope());
10840 return Swap.getValue(1);
10842 // Other atomic stores have a simple pattern.
10846 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
10847 EVT VT = Op.getNode()->getValueType(0);
10849 // Let legalize expand this if it isn't a legal type yet.
10850 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
10853 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
10856 bool ExtraOp = false;
10857 switch (Op.getOpcode()) {
10858 default: llvm_unreachable("Invalid code");
10859 case ISD::ADDC: Opc = X86ISD::ADD; break;
10860 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
10861 case ISD::SUBC: Opc = X86ISD::SUB; break;
10862 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
10866 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
10868 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
10869 Op.getOperand(1), Op.getOperand(2));
10872 /// LowerOperation - Provide custom lowering hooks for some operations.
10874 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
10875 switch (Op.getOpcode()) {
10876 default: llvm_unreachable("Should not custom lower this!");
10877 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
10878 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op,DAG);
10879 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op,DAG);
10880 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
10881 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
10882 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
10883 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
10884 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
10885 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
10886 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
10887 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
10888 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
10889 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG);
10890 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
10891 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
10892 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
10893 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
10894 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
10895 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
10896 case ISD::SHL_PARTS:
10897 case ISD::SRA_PARTS:
10898 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
10899 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
10900 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
10901 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
10902 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
10903 case ISD::FABS: return LowerFABS(Op, DAG);
10904 case ISD::FNEG: return LowerFNEG(Op, DAG);
10905 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
10906 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
10907 case ISD::SETCC: return LowerSETCC(Op, DAG);
10908 case ISD::SELECT: return LowerSELECT(Op, DAG);
10909 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
10910 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
10911 case ISD::VASTART: return LowerVASTART(Op, DAG);
10912 case ISD::VAARG: return LowerVAARG(Op, DAG);
10913 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
10914 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
10915 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
10916 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
10917 case ISD::FRAME_TO_ARGS_OFFSET:
10918 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
10919 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
10920 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
10921 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
10922 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
10923 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
10924 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
10925 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
10926 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
10927 case ISD::MUL: return LowerMUL(Op, DAG);
10930 case ISD::SHL: return LowerShift(Op, DAG);
10936 case ISD::UMULO: return LowerXALUO(Op, DAG);
10937 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
10938 case ISD::BITCAST: return LowerBITCAST(Op, DAG);
10942 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
10943 case ISD::ADD: return LowerADD(Op, DAG);
10944 case ISD::SUB: return LowerSUB(Op, DAG);
10948 static void ReplaceATOMIC_LOAD(SDNode *Node,
10949 SmallVectorImpl<SDValue> &Results,
10950 SelectionDAG &DAG) {
10951 DebugLoc dl = Node->getDebugLoc();
10952 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
10954 // Convert wide load -> cmpxchg8b/cmpxchg16b
10955 // FIXME: On 32-bit, load -> fild or movq would be more efficient
10956 // (The only way to get a 16-byte load is cmpxchg16b)
10957 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
10958 SDValue Zero = DAG.getConstant(0, VT);
10959 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT,
10960 Node->getOperand(0),
10961 Node->getOperand(1), Zero, Zero,
10962 cast<AtomicSDNode>(Node)->getMemOperand(),
10963 cast<AtomicSDNode>(Node)->getOrdering(),
10964 cast<AtomicSDNode>(Node)->getSynchScope());
10965 Results.push_back(Swap.getValue(0));
10966 Results.push_back(Swap.getValue(1));
10969 void X86TargetLowering::
10970 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
10971 SelectionDAG &DAG, unsigned NewOp) const {
10972 DebugLoc dl = Node->getDebugLoc();
10973 assert (Node->getValueType(0) == MVT::i64 &&
10974 "Only know how to expand i64 atomics");
10976 SDValue Chain = Node->getOperand(0);
10977 SDValue In1 = Node->getOperand(1);
10978 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
10979 Node->getOperand(2), DAG.getIntPtrConstant(0));
10980 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
10981 Node->getOperand(2), DAG.getIntPtrConstant(1));
10982 SDValue Ops[] = { Chain, In1, In2L, In2H };
10983 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
10985 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64,
10986 cast<MemSDNode>(Node)->getMemOperand());
10987 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
10988 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
10989 Results.push_back(Result.getValue(2));
10992 /// ReplaceNodeResults - Replace a node with an illegal result type
10993 /// with a new node built out of custom code.
10994 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
10995 SmallVectorImpl<SDValue>&Results,
10996 SelectionDAG &DAG) const {
10997 DebugLoc dl = N->getDebugLoc();
10998 switch (N->getOpcode()) {
11000 llvm_unreachable("Do not know how to custom type legalize this operation!");
11001 case ISD::SIGN_EXTEND_INREG:
11006 // We don't want to expand or promote these.
11008 case ISD::FP_TO_SINT:
11009 case ISD::FP_TO_UINT: {
11010 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
11012 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
11015 std::pair<SDValue,SDValue> Vals =
11016 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
11017 SDValue FIST = Vals.first, StackSlot = Vals.second;
11018 if (FIST.getNode() != 0) {
11019 EVT VT = N->getValueType(0);
11020 // Return a load from the stack slot.
11021 if (StackSlot.getNode() != 0)
11022 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
11023 MachinePointerInfo(),
11024 false, false, false, 0));
11026 Results.push_back(FIST);
11030 case ISD::READCYCLECOUNTER: {
11031 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
11032 SDValue TheChain = N->getOperand(0);
11033 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
11034 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
11036 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
11038 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
11039 SDValue Ops[] = { eax, edx };
11040 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
11041 Results.push_back(edx.getValue(1));
11044 case ISD::ATOMIC_CMP_SWAP: {
11045 EVT T = N->getValueType(0);
11046 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
11047 bool Regs64bit = T == MVT::i128;
11048 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
11049 SDValue cpInL, cpInH;
11050 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
11051 DAG.getConstant(0, HalfT));
11052 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
11053 DAG.getConstant(1, HalfT));
11054 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
11055 Regs64bit ? X86::RAX : X86::EAX,
11057 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
11058 Regs64bit ? X86::RDX : X86::EDX,
11059 cpInH, cpInL.getValue(1));
11060 SDValue swapInL, swapInH;
11061 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
11062 DAG.getConstant(0, HalfT));
11063 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
11064 DAG.getConstant(1, HalfT));
11065 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
11066 Regs64bit ? X86::RBX : X86::EBX,
11067 swapInL, cpInH.getValue(1));
11068 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
11069 Regs64bit ? X86::RCX : X86::ECX,
11070 swapInH, swapInL.getValue(1));
11071 SDValue Ops[] = { swapInH.getValue(0),
11073 swapInH.getValue(1) };
11074 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
11075 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
11076 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
11077 X86ISD::LCMPXCHG8_DAG;
11078 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys,
11080 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
11081 Regs64bit ? X86::RAX : X86::EAX,
11082 HalfT, Result.getValue(1));
11083 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
11084 Regs64bit ? X86::RDX : X86::EDX,
11085 HalfT, cpOutL.getValue(2));
11086 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
11087 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2));
11088 Results.push_back(cpOutH.getValue(1));
11091 case ISD::ATOMIC_LOAD_ADD:
11092 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
11094 case ISD::ATOMIC_LOAD_AND:
11095 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
11097 case ISD::ATOMIC_LOAD_NAND:
11098 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
11100 case ISD::ATOMIC_LOAD_OR:
11101 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
11103 case ISD::ATOMIC_LOAD_SUB:
11104 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
11106 case ISD::ATOMIC_LOAD_XOR:
11107 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
11109 case ISD::ATOMIC_SWAP:
11110 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
11112 case ISD::ATOMIC_LOAD:
11113 ReplaceATOMIC_LOAD(N, Results, DAG);
11117 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
11119 default: return NULL;
11120 case X86ISD::BSF: return "X86ISD::BSF";
11121 case X86ISD::BSR: return "X86ISD::BSR";
11122 case X86ISD::SHLD: return "X86ISD::SHLD";
11123 case X86ISD::SHRD: return "X86ISD::SHRD";
11124 case X86ISD::FAND: return "X86ISD::FAND";
11125 case X86ISD::FOR: return "X86ISD::FOR";
11126 case X86ISD::FXOR: return "X86ISD::FXOR";
11127 case X86ISD::FSRL: return "X86ISD::FSRL";
11128 case X86ISD::FILD: return "X86ISD::FILD";
11129 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
11130 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
11131 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
11132 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
11133 case X86ISD::FLD: return "X86ISD::FLD";
11134 case X86ISD::FST: return "X86ISD::FST";
11135 case X86ISD::CALL: return "X86ISD::CALL";
11136 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
11137 case X86ISD::BT: return "X86ISD::BT";
11138 case X86ISD::CMP: return "X86ISD::CMP";
11139 case X86ISD::COMI: return "X86ISD::COMI";
11140 case X86ISD::UCOMI: return "X86ISD::UCOMI";
11141 case X86ISD::SETCC: return "X86ISD::SETCC";
11142 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
11143 case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd";
11144 case X86ISD::FSETCCss: return "X86ISD::FSETCCss";
11145 case X86ISD::CMOV: return "X86ISD::CMOV";
11146 case X86ISD::BRCOND: return "X86ISD::BRCOND";
11147 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
11148 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
11149 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
11150 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
11151 case X86ISD::Wrapper: return "X86ISD::Wrapper";
11152 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
11153 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
11154 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
11155 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
11156 case X86ISD::PINSRB: return "X86ISD::PINSRB";
11157 case X86ISD::PINSRW: return "X86ISD::PINSRW";
11158 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
11159 case X86ISD::ANDNP: return "X86ISD::ANDNP";
11160 case X86ISD::PSIGN: return "X86ISD::PSIGN";
11161 case X86ISD::BLENDV: return "X86ISD::BLENDV";
11162 case X86ISD::BLENDPW: return "X86ISD::BLENDPW";
11163 case X86ISD::BLENDPS: return "X86ISD::BLENDPS";
11164 case X86ISD::BLENDPD: return "X86ISD::BLENDPD";
11165 case X86ISD::HADD: return "X86ISD::HADD";
11166 case X86ISD::HSUB: return "X86ISD::HSUB";
11167 case X86ISD::FHADD: return "X86ISD::FHADD";
11168 case X86ISD::FHSUB: return "X86ISD::FHSUB";
11169 case X86ISD::FMAX: return "X86ISD::FMAX";
11170 case X86ISD::FMIN: return "X86ISD::FMIN";
11171 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
11172 case X86ISD::FRCP: return "X86ISD::FRCP";
11173 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
11174 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
11175 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
11176 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
11177 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
11178 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
11179 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
11180 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
11181 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
11182 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
11183 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
11184 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
11185 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
11186 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
11187 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
11188 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
11189 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
11190 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
11191 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
11192 case X86ISD::VSHL: return "X86ISD::VSHL";
11193 case X86ISD::VSRL: return "X86ISD::VSRL";
11194 case X86ISD::VSRA: return "X86ISD::VSRA";
11195 case X86ISD::VSHLI: return "X86ISD::VSHLI";
11196 case X86ISD::VSRLI: return "X86ISD::VSRLI";
11197 case X86ISD::VSRAI: return "X86ISD::VSRAI";
11198 case X86ISD::CMPP: return "X86ISD::CMPP";
11199 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
11200 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
11201 case X86ISD::ADD: return "X86ISD::ADD";
11202 case X86ISD::SUB: return "X86ISD::SUB";
11203 case X86ISD::ADC: return "X86ISD::ADC";
11204 case X86ISD::SBB: return "X86ISD::SBB";
11205 case X86ISD::SMUL: return "X86ISD::SMUL";
11206 case X86ISD::UMUL: return "X86ISD::UMUL";
11207 case X86ISD::INC: return "X86ISD::INC";
11208 case X86ISD::DEC: return "X86ISD::DEC";
11209 case X86ISD::OR: return "X86ISD::OR";
11210 case X86ISD::XOR: return "X86ISD::XOR";
11211 case X86ISD::AND: return "X86ISD::AND";
11212 case X86ISD::ANDN: return "X86ISD::ANDN";
11213 case X86ISD::BLSI: return "X86ISD::BLSI";
11214 case X86ISD::BLSMSK: return "X86ISD::BLSMSK";
11215 case X86ISD::BLSR: return "X86ISD::BLSR";
11216 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
11217 case X86ISD::PTEST: return "X86ISD::PTEST";
11218 case X86ISD::TESTP: return "X86ISD::TESTP";
11219 case X86ISD::PALIGN: return "X86ISD::PALIGN";
11220 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
11221 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
11222 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
11223 case X86ISD::SHUFP: return "X86ISD::SHUFP";
11224 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
11225 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
11226 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
11227 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
11228 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
11229 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
11230 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
11231 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
11232 case X86ISD::MOVSD: return "X86ISD::MOVSD";
11233 case X86ISD::MOVSS: return "X86ISD::MOVSS";
11234 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
11235 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
11236 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
11237 case X86ISD::VPERMILP: return "X86ISD::VPERMILP";
11238 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
11239 case X86ISD::VPERMV: return "X86ISD::VPERMV";
11240 case X86ISD::VPERMI: return "X86ISD::VPERMI";
11241 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
11242 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
11243 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
11244 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
11245 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
11246 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
11247 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
11248 case X86ISD::SAHF: return "X86ISD::SAHF";
11252 // isLegalAddressingMode - Return true if the addressing mode represented
11253 // by AM is legal for this target, for a load/store of the specified type.
11254 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
11256 // X86 supports extremely general addressing modes.
11257 CodeModel::Model M = getTargetMachine().getCodeModel();
11258 Reloc::Model R = getTargetMachine().getRelocationModel();
11260 // X86 allows a sign-extended 32-bit immediate field as a displacement.
11261 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
11266 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
11268 // If a reference to this global requires an extra load, we can't fold it.
11269 if (isGlobalStubReference(GVFlags))
11272 // If BaseGV requires a register for the PIC base, we cannot also have a
11273 // BaseReg specified.
11274 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
11277 // If lower 4G is not available, then we must use rip-relative addressing.
11278 if ((M != CodeModel::Small || R != Reloc::Static) &&
11279 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
11283 switch (AM.Scale) {
11289 // These scales always work.
11294 // These scales are formed with basereg+scalereg. Only accept if there is
11299 default: // Other stuff never works.
11307 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
11308 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
11310 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
11311 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
11312 if (NumBits1 <= NumBits2)
11317 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
11318 if (!VT1.isInteger() || !VT2.isInteger())
11320 unsigned NumBits1 = VT1.getSizeInBits();
11321 unsigned NumBits2 = VT2.getSizeInBits();
11322 if (NumBits1 <= NumBits2)
11327 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
11328 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
11329 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
11332 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
11333 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
11334 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
11337 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
11338 // i16 instructions are longer (0x66 prefix) and potentially slower.
11339 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
11342 /// isShuffleMaskLegal - Targets can use this to indicate that they only
11343 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
11344 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
11345 /// are assumed to be legal.
11347 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
11349 // Very little shuffling can be done for 64-bit vectors right now.
11350 if (VT.getSizeInBits() == 64)
11353 // FIXME: pshufb, blends, shifts.
11354 return (VT.getVectorNumElements() == 2 ||
11355 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
11356 isMOVLMask(M, VT) ||
11357 isSHUFPMask(M, VT, Subtarget->hasAVX()) ||
11358 isPSHUFDMask(M, VT) ||
11359 isPSHUFHWMask(M, VT, Subtarget->hasAVX2()) ||
11360 isPSHUFLWMask(M, VT, Subtarget->hasAVX2()) ||
11361 isPALIGNRMask(M, VT, Subtarget) ||
11362 isUNPCKLMask(M, VT, Subtarget->hasAVX2()) ||
11363 isUNPCKHMask(M, VT, Subtarget->hasAVX2()) ||
11364 isUNPCKL_v_undef_Mask(M, VT, Subtarget->hasAVX2()) ||
11365 isUNPCKH_v_undef_Mask(M, VT, Subtarget->hasAVX2()));
11369 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
11371 unsigned NumElts = VT.getVectorNumElements();
11372 // FIXME: This collection of masks seems suspect.
11375 if (NumElts == 4 && VT.getSizeInBits() == 128) {
11376 return (isMOVLMask(Mask, VT) ||
11377 isCommutedMOVLMask(Mask, VT, true) ||
11378 isSHUFPMask(Mask, VT, Subtarget->hasAVX()) ||
11379 isSHUFPMask(Mask, VT, Subtarget->hasAVX(), /* Commuted */ true));
11384 //===----------------------------------------------------------------------===//
11385 // X86 Scheduler Hooks
11386 //===----------------------------------------------------------------------===//
11388 // private utility function
11389 MachineBasicBlock *
11390 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
11391 MachineBasicBlock *MBB,
11398 const TargetRegisterClass *RC,
11399 bool Invert) const {
11400 // For the atomic bitwise operator, we generate
11403 // ld t1 = [bitinstr.addr]
11404 // op t2 = t1, [bitinstr.val]
11405 // not t3 = t2 (if Invert)
11407 // lcs dest = [bitinstr.addr], t3 [EAX is implicit]
11409 // fallthrough -->nextMBB
11410 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11411 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11412 MachineFunction::iterator MBBIter = MBB;
11415 /// First build the CFG
11416 MachineFunction *F = MBB->getParent();
11417 MachineBasicBlock *thisMBB = MBB;
11418 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11419 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11420 F->insert(MBBIter, newMBB);
11421 F->insert(MBBIter, nextMBB);
11423 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11424 nextMBB->splice(nextMBB->begin(), thisMBB,
11425 llvm::next(MachineBasicBlock::iterator(bInstr)),
11427 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11429 // Update thisMBB to fall through to newMBB
11430 thisMBB->addSuccessor(newMBB);
11432 // newMBB jumps to itself and fall through to nextMBB
11433 newMBB->addSuccessor(nextMBB);
11434 newMBB->addSuccessor(newMBB);
11436 // Insert instructions into newMBB based on incoming instruction
11437 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
11438 "unexpected number of operands");
11439 DebugLoc dl = bInstr->getDebugLoc();
11440 MachineOperand& destOper = bInstr->getOperand(0);
11441 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11442 int numArgs = bInstr->getNumOperands() - 1;
11443 for (int i=0; i < numArgs; ++i)
11444 argOpers[i] = &bInstr->getOperand(i+1);
11446 // x86 address has 4 operands: base, index, scale, and displacement
11447 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11448 int valArgIndx = lastAddrIndx + 1;
11450 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
11451 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1);
11452 for (int i=0; i <= lastAddrIndx; ++i)
11453 (*MIB).addOperand(*argOpers[i]);
11455 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
11456 assert((argOpers[valArgIndx]->isReg() ||
11457 argOpers[valArgIndx]->isImm()) &&
11458 "invalid operand");
11459 if (argOpers[valArgIndx]->isReg())
11460 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2);
11462 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2);
11464 (*MIB).addOperand(*argOpers[valArgIndx]);
11466 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
11468 MIB = BuildMI(newMBB, dl, TII->get(notOpc), t3).addReg(t2);
11473 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg);
11476 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
11477 for (int i=0; i <= lastAddrIndx; ++i)
11478 (*MIB).addOperand(*argOpers[i]);
11480 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11481 (*MIB).setMemRefs(bInstr->memoperands_begin(),
11482 bInstr->memoperands_end());
11484 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
11485 MIB.addReg(EAXreg);
11488 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11490 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
11494 // private utility function: 64 bit atomics on 32 bit host.
11495 MachineBasicBlock *
11496 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
11497 MachineBasicBlock *MBB,
11502 bool Invert) const {
11503 // For the atomic bitwise operator, we generate
11504 // thisMBB (instructions are in pairs, except cmpxchg8b)
11505 // ld t1,t2 = [bitinstr.addr]
11507 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
11508 // op t5, t6 <- out1, out2, [bitinstr.val]
11509 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
11510 // neg t7, t8 < t5, t6 (if Invert)
11511 // mov ECX, EBX <- t5, t6
11512 // mov EAX, EDX <- t1, t2
11513 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
11514 // mov t3, t4 <- EAX, EDX
11516 // result in out1, out2
11517 // fallthrough -->nextMBB
11519 const TargetRegisterClass *RC = &X86::GR32RegClass;
11520 const unsigned LoadOpc = X86::MOV32rm;
11521 const unsigned NotOpc = X86::NOT32r;
11522 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11523 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11524 MachineFunction::iterator MBBIter = MBB;
11527 /// First build the CFG
11528 MachineFunction *F = MBB->getParent();
11529 MachineBasicBlock *thisMBB = MBB;
11530 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11531 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11532 F->insert(MBBIter, newMBB);
11533 F->insert(MBBIter, nextMBB);
11535 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11536 nextMBB->splice(nextMBB->begin(), thisMBB,
11537 llvm::next(MachineBasicBlock::iterator(bInstr)),
11539 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11541 // Update thisMBB to fall through to newMBB
11542 thisMBB->addSuccessor(newMBB);
11544 // newMBB jumps to itself and fall through to nextMBB
11545 newMBB->addSuccessor(nextMBB);
11546 newMBB->addSuccessor(newMBB);
11548 DebugLoc dl = bInstr->getDebugLoc();
11549 // Insert instructions into newMBB based on incoming instruction
11550 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
11551 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 14 &&
11552 "unexpected number of operands");
11553 MachineOperand& dest1Oper = bInstr->getOperand(0);
11554 MachineOperand& dest2Oper = bInstr->getOperand(1);
11555 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11556 for (int i=0; i < 2 + X86::AddrNumOperands; ++i) {
11557 argOpers[i] = &bInstr->getOperand(i+2);
11559 // We use some of the operands multiple times, so conservatively just
11560 // clear any kill flags that might be present.
11561 if (argOpers[i]->isReg() && argOpers[i]->isUse())
11562 argOpers[i]->setIsKill(false);
11565 // x86 address has 5 operands: base, index, scale, displacement, and segment.
11566 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11568 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
11569 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1);
11570 for (int i=0; i <= lastAddrIndx; ++i)
11571 (*MIB).addOperand(*argOpers[i]);
11572 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
11573 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
11574 // add 4 to displacement.
11575 for (int i=0; i <= lastAddrIndx-2; ++i)
11576 (*MIB).addOperand(*argOpers[i]);
11577 MachineOperand newOp3 = *(argOpers[3]);
11578 if (newOp3.isImm())
11579 newOp3.setImm(newOp3.getImm()+4);
11581 newOp3.setOffset(newOp3.getOffset()+4);
11582 (*MIB).addOperand(newOp3);
11583 (*MIB).addOperand(*argOpers[lastAddrIndx]);
11585 // t3/4 are defined later, at the bottom of the loop
11586 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
11587 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
11588 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg())
11589 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
11590 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
11591 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
11593 // The subsequent operations should be using the destination registers of
11594 // the PHI instructions.
11595 t1 = dest1Oper.getReg();
11596 t2 = dest2Oper.getReg();
11598 int valArgIndx = lastAddrIndx + 1;
11599 assert((argOpers[valArgIndx]->isReg() ||
11600 argOpers[valArgIndx]->isImm()) &&
11601 "invalid operand");
11602 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
11603 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
11604 if (argOpers[valArgIndx]->isReg())
11605 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5);
11607 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
11608 if (regOpcL != X86::MOV32rr)
11610 (*MIB).addOperand(*argOpers[valArgIndx]);
11611 assert(argOpers[valArgIndx + 1]->isReg() ==
11612 argOpers[valArgIndx]->isReg());
11613 assert(argOpers[valArgIndx + 1]->isImm() ==
11614 argOpers[valArgIndx]->isImm());
11615 if (argOpers[valArgIndx + 1]->isReg())
11616 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
11618 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
11619 if (regOpcH != X86::MOV32rr)
11621 (*MIB).addOperand(*argOpers[valArgIndx + 1]);
11625 t7 = F->getRegInfo().createVirtualRegister(RC);
11626 t8 = F->getRegInfo().createVirtualRegister(RC);
11627 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t7).addReg(t5);
11628 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t8).addReg(t6);
11634 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
11636 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EDX);
11639 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EBX);
11641 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::ECX);
11644 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
11645 for (int i=0; i <= lastAddrIndx; ++i)
11646 (*MIB).addOperand(*argOpers[i]);
11648 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11649 (*MIB).setMemRefs(bInstr->memoperands_begin(),
11650 bInstr->memoperands_end());
11652 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t3);
11653 MIB.addReg(X86::EAX);
11654 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t4);
11655 MIB.addReg(X86::EDX);
11658 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11660 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
11664 // private utility function
11665 MachineBasicBlock *
11666 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
11667 MachineBasicBlock *MBB,
11668 unsigned cmovOpc) const {
11669 // For the atomic min/max operator, we generate
11672 // ld t1 = [min/max.addr]
11673 // mov t2 = [min/max.val]
11675 // cmov[cond] t2 = t1
11677 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
11679 // fallthrough -->nextMBB
11681 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11682 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11683 MachineFunction::iterator MBBIter = MBB;
11686 /// First build the CFG
11687 MachineFunction *F = MBB->getParent();
11688 MachineBasicBlock *thisMBB = MBB;
11689 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11690 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11691 F->insert(MBBIter, newMBB);
11692 F->insert(MBBIter, nextMBB);
11694 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11695 nextMBB->splice(nextMBB->begin(), thisMBB,
11696 llvm::next(MachineBasicBlock::iterator(mInstr)),
11698 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11700 // Update thisMBB to fall through to newMBB
11701 thisMBB->addSuccessor(newMBB);
11703 // newMBB jumps to newMBB and fall through to nextMBB
11704 newMBB->addSuccessor(nextMBB);
11705 newMBB->addSuccessor(newMBB);
11707 DebugLoc dl = mInstr->getDebugLoc();
11708 // Insert instructions into newMBB based on incoming instruction
11709 assert(mInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
11710 "unexpected number of operands");
11711 MachineOperand& destOper = mInstr->getOperand(0);
11712 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11713 int numArgs = mInstr->getNumOperands() - 1;
11714 for (int i=0; i < numArgs; ++i)
11715 argOpers[i] = &mInstr->getOperand(i+1);
11717 // x86 address has 4 operands: base, index, scale, and displacement
11718 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11719 int valArgIndx = lastAddrIndx + 1;
11721 unsigned t1 = F->getRegInfo().createVirtualRegister(&X86::GR32RegClass);
11722 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1);
11723 for (int i=0; i <= lastAddrIndx; ++i)
11724 (*MIB).addOperand(*argOpers[i]);
11726 // We only support register and immediate values
11727 assert((argOpers[valArgIndx]->isReg() ||
11728 argOpers[valArgIndx]->isImm()) &&
11729 "invalid operand");
11731 unsigned t2 = F->getRegInfo().createVirtualRegister(&X86::GR32RegClass);
11732 if (argOpers[valArgIndx]->isReg())
11733 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t2);
11735 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
11736 (*MIB).addOperand(*argOpers[valArgIndx]);
11738 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
11741 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr));
11746 unsigned t3 = F->getRegInfo().createVirtualRegister(&X86::GR32RegClass);
11747 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3);
11751 // Cmp and exchange if none has modified the memory location
11752 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32));
11753 for (int i=0; i <= lastAddrIndx; ++i)
11754 (*MIB).addOperand(*argOpers[i]);
11756 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11757 (*MIB).setMemRefs(mInstr->memoperands_begin(),
11758 mInstr->memoperands_end());
11760 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
11761 MIB.addReg(X86::EAX);
11764 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11766 mInstr->eraseFromParent(); // The pseudo instruction is gone now.
11770 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
11771 // or XMM0_V32I8 in AVX all of this code can be replaced with that
11772 // in the .td file.
11773 MachineBasicBlock *
11774 X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB,
11775 unsigned numArgs, bool memArg) const {
11776 assert(Subtarget->hasSSE42() &&
11777 "Target must have SSE4.2 or AVX features enabled");
11779 DebugLoc dl = MI->getDebugLoc();
11780 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11782 if (!Subtarget->hasAVX()) {
11784 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm;
11786 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr;
11789 Opc = numArgs == 3 ? X86::VPCMPISTRM128rm : X86::VPCMPESTRM128rm;
11791 Opc = numArgs == 3 ? X86::VPCMPISTRM128rr : X86::VPCMPESTRM128rr;
11794 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
11795 for (unsigned i = 0; i < numArgs; ++i) {
11796 MachineOperand &Op = MI->getOperand(i+1);
11797 if (!(Op.isReg() && Op.isImplicit()))
11798 MIB.addOperand(Op);
11800 BuildMI(*BB, MI, dl,
11801 TII->get(Subtarget->hasAVX() ? X86::VMOVAPSrr : X86::MOVAPSrr),
11802 MI->getOperand(0).getReg())
11803 .addReg(X86::XMM0);
11805 MI->eraseFromParent();
11809 MachineBasicBlock *
11810 X86TargetLowering::EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB) const {
11811 DebugLoc dl = MI->getDebugLoc();
11812 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11814 // Address into RAX/EAX, other two args into ECX, EDX.
11815 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
11816 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
11817 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
11818 for (int i = 0; i < X86::AddrNumOperands; ++i)
11819 MIB.addOperand(MI->getOperand(i));
11821 unsigned ValOps = X86::AddrNumOperands;
11822 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
11823 .addReg(MI->getOperand(ValOps).getReg());
11824 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
11825 .addReg(MI->getOperand(ValOps+1).getReg());
11827 // The instruction doesn't actually take any operands though.
11828 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
11830 MI->eraseFromParent(); // The pseudo is gone now.
11834 MachineBasicBlock *
11835 X86TargetLowering::EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const {
11836 DebugLoc dl = MI->getDebugLoc();
11837 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11839 // First arg in ECX, the second in EAX.
11840 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
11841 .addReg(MI->getOperand(0).getReg());
11842 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EAX)
11843 .addReg(MI->getOperand(1).getReg());
11845 // The instruction doesn't actually take any operands though.
11846 BuildMI(*BB, MI, dl, TII->get(X86::MWAITrr));
11848 MI->eraseFromParent(); // The pseudo is gone now.
11852 MachineBasicBlock *
11853 X86TargetLowering::EmitVAARG64WithCustomInserter(
11855 MachineBasicBlock *MBB) const {
11856 // Emit va_arg instruction on X86-64.
11858 // Operands to this pseudo-instruction:
11859 // 0 ) Output : destination address (reg)
11860 // 1-5) Input : va_list address (addr, i64mem)
11861 // 6 ) ArgSize : Size (in bytes) of vararg type
11862 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
11863 // 8 ) Align : Alignment of type
11864 // 9 ) EFLAGS (implicit-def)
11866 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
11867 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
11869 unsigned DestReg = MI->getOperand(0).getReg();
11870 MachineOperand &Base = MI->getOperand(1);
11871 MachineOperand &Scale = MI->getOperand(2);
11872 MachineOperand &Index = MI->getOperand(3);
11873 MachineOperand &Disp = MI->getOperand(4);
11874 MachineOperand &Segment = MI->getOperand(5);
11875 unsigned ArgSize = MI->getOperand(6).getImm();
11876 unsigned ArgMode = MI->getOperand(7).getImm();
11877 unsigned Align = MI->getOperand(8).getImm();
11879 // Memory Reference
11880 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
11881 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
11882 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
11884 // Machine Information
11885 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11886 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
11887 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
11888 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
11889 DebugLoc DL = MI->getDebugLoc();
11891 // struct va_list {
11894 // i64 overflow_area (address)
11895 // i64 reg_save_area (address)
11897 // sizeof(va_list) = 24
11898 // alignment(va_list) = 8
11900 unsigned TotalNumIntRegs = 6;
11901 unsigned TotalNumXMMRegs = 8;
11902 bool UseGPOffset = (ArgMode == 1);
11903 bool UseFPOffset = (ArgMode == 2);
11904 unsigned MaxOffset = TotalNumIntRegs * 8 +
11905 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
11907 /* Align ArgSize to a multiple of 8 */
11908 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
11909 bool NeedsAlign = (Align > 8);
11911 MachineBasicBlock *thisMBB = MBB;
11912 MachineBasicBlock *overflowMBB;
11913 MachineBasicBlock *offsetMBB;
11914 MachineBasicBlock *endMBB;
11916 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
11917 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
11918 unsigned OffsetReg = 0;
11920 if (!UseGPOffset && !UseFPOffset) {
11921 // If we only pull from the overflow region, we don't create a branch.
11922 // We don't need to alter control flow.
11923 OffsetDestReg = 0; // unused
11924 OverflowDestReg = DestReg;
11927 overflowMBB = thisMBB;
11930 // First emit code to check if gp_offset (or fp_offset) is below the bound.
11931 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
11932 // If not, pull from overflow_area. (branch to overflowMBB)
11937 // offsetMBB overflowMBB
11942 // Registers for the PHI in endMBB
11943 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
11944 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
11946 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11947 MachineFunction *MF = MBB->getParent();
11948 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11949 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11950 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11952 MachineFunction::iterator MBBIter = MBB;
11955 // Insert the new basic blocks
11956 MF->insert(MBBIter, offsetMBB);
11957 MF->insert(MBBIter, overflowMBB);
11958 MF->insert(MBBIter, endMBB);
11960 // Transfer the remainder of MBB and its successor edges to endMBB.
11961 endMBB->splice(endMBB->begin(), thisMBB,
11962 llvm::next(MachineBasicBlock::iterator(MI)),
11964 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11966 // Make offsetMBB and overflowMBB successors of thisMBB
11967 thisMBB->addSuccessor(offsetMBB);
11968 thisMBB->addSuccessor(overflowMBB);
11970 // endMBB is a successor of both offsetMBB and overflowMBB
11971 offsetMBB->addSuccessor(endMBB);
11972 overflowMBB->addSuccessor(endMBB);
11974 // Load the offset value into a register
11975 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
11976 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
11980 .addDisp(Disp, UseFPOffset ? 4 : 0)
11981 .addOperand(Segment)
11982 .setMemRefs(MMOBegin, MMOEnd);
11984 // Check if there is enough room left to pull this argument.
11985 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
11987 .addImm(MaxOffset + 8 - ArgSizeA8);
11989 // Branch to "overflowMBB" if offset >= max
11990 // Fall through to "offsetMBB" otherwise
11991 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
11992 .addMBB(overflowMBB);
11995 // In offsetMBB, emit code to use the reg_save_area.
11997 assert(OffsetReg != 0);
11999 // Read the reg_save_area address.
12000 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
12001 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
12006 .addOperand(Segment)
12007 .setMemRefs(MMOBegin, MMOEnd);
12009 // Zero-extend the offset
12010 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
12011 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
12014 .addImm(X86::sub_32bit);
12016 // Add the offset to the reg_save_area to get the final address.
12017 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
12018 .addReg(OffsetReg64)
12019 .addReg(RegSaveReg);
12021 // Compute the offset for the next argument
12022 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
12023 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
12025 .addImm(UseFPOffset ? 16 : 8);
12027 // Store it back into the va_list.
12028 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
12032 .addDisp(Disp, UseFPOffset ? 4 : 0)
12033 .addOperand(Segment)
12034 .addReg(NextOffsetReg)
12035 .setMemRefs(MMOBegin, MMOEnd);
12038 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
12043 // Emit code to use overflow area
12046 // Load the overflow_area address into a register.
12047 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
12048 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
12053 .addOperand(Segment)
12054 .setMemRefs(MMOBegin, MMOEnd);
12056 // If we need to align it, do so. Otherwise, just copy the address
12057 // to OverflowDestReg.
12059 // Align the overflow address
12060 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
12061 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
12063 // aligned_addr = (addr + (align-1)) & ~(align-1)
12064 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
12065 .addReg(OverflowAddrReg)
12068 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
12070 .addImm(~(uint64_t)(Align-1));
12072 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
12073 .addReg(OverflowAddrReg);
12076 // Compute the next overflow address after this argument.
12077 // (the overflow address should be kept 8-byte aligned)
12078 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
12079 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
12080 .addReg(OverflowDestReg)
12081 .addImm(ArgSizeA8);
12083 // Store the new overflow address.
12084 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
12089 .addOperand(Segment)
12090 .addReg(NextAddrReg)
12091 .setMemRefs(MMOBegin, MMOEnd);
12093 // If we branched, emit the PHI to the front of endMBB.
12095 BuildMI(*endMBB, endMBB->begin(), DL,
12096 TII->get(X86::PHI), DestReg)
12097 .addReg(OffsetDestReg).addMBB(offsetMBB)
12098 .addReg(OverflowDestReg).addMBB(overflowMBB);
12101 // Erase the pseudo instruction
12102 MI->eraseFromParent();
12107 MachineBasicBlock *
12108 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
12110 MachineBasicBlock *MBB) const {
12111 // Emit code to save XMM registers to the stack. The ABI says that the
12112 // number of registers to save is given in %al, so it's theoretically
12113 // possible to do an indirect jump trick to avoid saving all of them,
12114 // however this code takes a simpler approach and just executes all
12115 // of the stores if %al is non-zero. It's less code, and it's probably
12116 // easier on the hardware branch predictor, and stores aren't all that
12117 // expensive anyway.
12119 // Create the new basic blocks. One block contains all the XMM stores,
12120 // and one block is the final destination regardless of whether any
12121 // stores were performed.
12122 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
12123 MachineFunction *F = MBB->getParent();
12124 MachineFunction::iterator MBBIter = MBB;
12126 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
12127 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
12128 F->insert(MBBIter, XMMSaveMBB);
12129 F->insert(MBBIter, EndMBB);
12131 // Transfer the remainder of MBB and its successor edges to EndMBB.
12132 EndMBB->splice(EndMBB->begin(), MBB,
12133 llvm::next(MachineBasicBlock::iterator(MI)),
12135 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
12137 // The original block will now fall through to the XMM save block.
12138 MBB->addSuccessor(XMMSaveMBB);
12139 // The XMMSaveMBB will fall through to the end block.
12140 XMMSaveMBB->addSuccessor(EndMBB);
12142 // Now add the instructions.
12143 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12144 DebugLoc DL = MI->getDebugLoc();
12146 unsigned CountReg = MI->getOperand(0).getReg();
12147 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
12148 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
12150 if (!Subtarget->isTargetWin64()) {
12151 // If %al is 0, branch around the XMM save block.
12152 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
12153 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
12154 MBB->addSuccessor(EndMBB);
12157 unsigned MOVOpc = Subtarget->hasAVX() ? X86::VMOVAPSmr : X86::MOVAPSmr;
12158 // In the XMM save block, save all the XMM argument registers.
12159 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
12160 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
12161 MachineMemOperand *MMO =
12162 F->getMachineMemOperand(
12163 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
12164 MachineMemOperand::MOStore,
12165 /*Size=*/16, /*Align=*/16);
12166 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
12167 .addFrameIndex(RegSaveFrameIndex)
12168 .addImm(/*Scale=*/1)
12169 .addReg(/*IndexReg=*/0)
12170 .addImm(/*Disp=*/Offset)
12171 .addReg(/*Segment=*/0)
12172 .addReg(MI->getOperand(i).getReg())
12173 .addMemOperand(MMO);
12176 MI->eraseFromParent(); // The pseudo instruction is gone now.
12181 // The EFLAGS operand of SelectItr might be missing a kill marker
12182 // because there were multiple uses of EFLAGS, and ISel didn't know
12183 // which to mark. Figure out whether SelectItr should have had a
12184 // kill marker, and set it if it should. Returns the correct kill
12186 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
12187 MachineBasicBlock* BB,
12188 const TargetRegisterInfo* TRI) {
12189 // Scan forward through BB for a use/def of EFLAGS.
12190 MachineBasicBlock::iterator miI(llvm::next(SelectItr));
12191 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
12192 const MachineInstr& mi = *miI;
12193 if (mi.readsRegister(X86::EFLAGS))
12195 if (mi.definesRegister(X86::EFLAGS))
12196 break; // Should have kill-flag - update below.
12199 // If we hit the end of the block, check whether EFLAGS is live into a
12201 if (miI == BB->end()) {
12202 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
12203 sEnd = BB->succ_end();
12204 sItr != sEnd; ++sItr) {
12205 MachineBasicBlock* succ = *sItr;
12206 if (succ->isLiveIn(X86::EFLAGS))
12211 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
12212 // out. SelectMI should have a kill flag on EFLAGS.
12213 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
12217 MachineBasicBlock *
12218 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
12219 MachineBasicBlock *BB) const {
12220 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12221 DebugLoc DL = MI->getDebugLoc();
12223 // To "insert" a SELECT_CC instruction, we actually have to insert the
12224 // diamond control-flow pattern. The incoming instruction knows the
12225 // destination vreg to set, the condition code register to branch on, the
12226 // true/false values to select between, and a branch opcode to use.
12227 const BasicBlock *LLVM_BB = BB->getBasicBlock();
12228 MachineFunction::iterator It = BB;
12234 // cmpTY ccX, r1, r2
12236 // fallthrough --> copy0MBB
12237 MachineBasicBlock *thisMBB = BB;
12238 MachineFunction *F = BB->getParent();
12239 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
12240 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
12241 F->insert(It, copy0MBB);
12242 F->insert(It, sinkMBB);
12244 // If the EFLAGS register isn't dead in the terminator, then claim that it's
12245 // live into the sink and copy blocks.
12246 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
12247 if (!MI->killsRegister(X86::EFLAGS) &&
12248 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
12249 copy0MBB->addLiveIn(X86::EFLAGS);
12250 sinkMBB->addLiveIn(X86::EFLAGS);
12253 // Transfer the remainder of BB and its successor edges to sinkMBB.
12254 sinkMBB->splice(sinkMBB->begin(), BB,
12255 llvm::next(MachineBasicBlock::iterator(MI)),
12257 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
12259 // Add the true and fallthrough blocks as its successors.
12260 BB->addSuccessor(copy0MBB);
12261 BB->addSuccessor(sinkMBB);
12263 // Create the conditional branch instruction.
12265 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
12266 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
12269 // %FalseValue = ...
12270 // # fallthrough to sinkMBB
12271 copy0MBB->addSuccessor(sinkMBB);
12274 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
12276 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
12277 TII->get(X86::PHI), MI->getOperand(0).getReg())
12278 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
12279 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
12281 MI->eraseFromParent(); // The pseudo instruction is gone now.
12285 MachineBasicBlock *
12286 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
12287 bool Is64Bit) const {
12288 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12289 DebugLoc DL = MI->getDebugLoc();
12290 MachineFunction *MF = BB->getParent();
12291 const BasicBlock *LLVM_BB = BB->getBasicBlock();
12293 assert(getTargetMachine().Options.EnableSegmentedStacks);
12295 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
12296 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30;
12299 // ... [Till the alloca]
12300 // If stacklet is not large enough, jump to mallocMBB
12303 // Allocate by subtracting from RSP
12304 // Jump to continueMBB
12307 // Allocate by call to runtime
12311 // [rest of original BB]
12314 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12315 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12316 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12318 MachineRegisterInfo &MRI = MF->getRegInfo();
12319 const TargetRegisterClass *AddrRegClass =
12320 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32);
12322 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
12323 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
12324 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
12325 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
12326 sizeVReg = MI->getOperand(1).getReg(),
12327 physSPReg = Is64Bit ? X86::RSP : X86::ESP;
12329 MachineFunction::iterator MBBIter = BB;
12332 MF->insert(MBBIter, bumpMBB);
12333 MF->insert(MBBIter, mallocMBB);
12334 MF->insert(MBBIter, continueMBB);
12336 continueMBB->splice(continueMBB->begin(), BB, llvm::next
12337 (MachineBasicBlock::iterator(MI)), BB->end());
12338 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
12340 // Add code to the main basic block to check if the stack limit has been hit,
12341 // and if so, jump to mallocMBB otherwise to bumpMBB.
12342 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
12343 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
12344 .addReg(tmpSPVReg).addReg(sizeVReg);
12345 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr))
12346 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
12347 .addReg(SPLimitVReg);
12348 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
12350 // bumpMBB simply decreases the stack pointer, since we know the current
12351 // stacklet has enough space.
12352 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
12353 .addReg(SPLimitVReg);
12354 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
12355 .addReg(SPLimitVReg);
12356 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
12358 // Calls into a routine in libgcc to allocate more space from the heap.
12359 const uint32_t *RegMask =
12360 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
12362 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
12364 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
12365 .addExternalSymbol("__morestack_allocate_stack_space").addReg(X86::RDI)
12366 .addRegMask(RegMask)
12367 .addReg(X86::RAX, RegState::ImplicitDefine);
12369 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
12371 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
12372 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
12373 .addExternalSymbol("__morestack_allocate_stack_space")
12374 .addRegMask(RegMask)
12375 .addReg(X86::EAX, RegState::ImplicitDefine);
12379 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
12382 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
12383 .addReg(Is64Bit ? X86::RAX : X86::EAX);
12384 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
12386 // Set up the CFG correctly.
12387 BB->addSuccessor(bumpMBB);
12388 BB->addSuccessor(mallocMBB);
12389 mallocMBB->addSuccessor(continueMBB);
12390 bumpMBB->addSuccessor(continueMBB);
12392 // Take care of the PHI nodes.
12393 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
12394 MI->getOperand(0).getReg())
12395 .addReg(mallocPtrVReg).addMBB(mallocMBB)
12396 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
12398 // Delete the original pseudo instruction.
12399 MI->eraseFromParent();
12402 return continueMBB;
12405 MachineBasicBlock *
12406 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
12407 MachineBasicBlock *BB) const {
12408 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12409 DebugLoc DL = MI->getDebugLoc();
12411 assert(!Subtarget->isTargetEnvMacho());
12413 // The lowering is pretty easy: we're just emitting the call to _alloca. The
12414 // non-trivial part is impdef of ESP.
12416 if (Subtarget->isTargetWin64()) {
12417 if (Subtarget->isTargetCygMing()) {
12418 // ___chkstk(Mingw64):
12419 // Clobbers R10, R11, RAX and EFLAGS.
12421 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
12422 .addExternalSymbol("___chkstk")
12423 .addReg(X86::RAX, RegState::Implicit)
12424 .addReg(X86::RSP, RegState::Implicit)
12425 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
12426 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
12427 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12429 // __chkstk(MSVCRT): does not update stack pointer.
12430 // Clobbers R10, R11 and EFLAGS.
12431 // FIXME: RAX(allocated size) might be reused and not killed.
12432 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
12433 .addExternalSymbol("__chkstk")
12434 .addReg(X86::RAX, RegState::Implicit)
12435 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12436 // RAX has the offset to subtracted from RSP.
12437 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
12442 const char *StackProbeSymbol =
12443 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca";
12445 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
12446 .addExternalSymbol(StackProbeSymbol)
12447 .addReg(X86::EAX, RegState::Implicit)
12448 .addReg(X86::ESP, RegState::Implicit)
12449 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
12450 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
12451 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12454 MI->eraseFromParent(); // The pseudo instruction is gone now.
12458 MachineBasicBlock *
12459 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
12460 MachineBasicBlock *BB) const {
12461 // This is pretty easy. We're taking the value that we received from
12462 // our load from the relocation, sticking it in either RDI (x86-64)
12463 // or EAX and doing an indirect call. The return value will then
12464 // be in the normal return register.
12465 const X86InstrInfo *TII
12466 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
12467 DebugLoc DL = MI->getDebugLoc();
12468 MachineFunction *F = BB->getParent();
12470 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
12471 assert(MI->getOperand(3).isGlobal() && "This should be a global");
12473 // Get a register mask for the lowered call.
12474 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
12475 // proper register mask.
12476 const uint32_t *RegMask =
12477 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
12478 if (Subtarget->is64Bit()) {
12479 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12480 TII->get(X86::MOV64rm), X86::RDI)
12482 .addImm(0).addReg(0)
12483 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12484 MI->getOperand(3).getTargetFlags())
12486 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
12487 addDirectMem(MIB, X86::RDI);
12488 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
12489 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
12490 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12491 TII->get(X86::MOV32rm), X86::EAX)
12493 .addImm(0).addReg(0)
12494 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12495 MI->getOperand(3).getTargetFlags())
12497 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
12498 addDirectMem(MIB, X86::EAX);
12499 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
12501 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12502 TII->get(X86::MOV32rm), X86::EAX)
12503 .addReg(TII->getGlobalBaseReg(F))
12504 .addImm(0).addReg(0)
12505 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12506 MI->getOperand(3).getTargetFlags())
12508 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
12509 addDirectMem(MIB, X86::EAX);
12510 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
12513 MI->eraseFromParent(); // The pseudo instruction is gone now.
12517 MachineBasicBlock *
12518 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
12519 MachineBasicBlock *BB) const {
12520 switch (MI->getOpcode()) {
12521 default: llvm_unreachable("Unexpected instr type to insert");
12522 case X86::TAILJMPd64:
12523 case X86::TAILJMPr64:
12524 case X86::TAILJMPm64:
12525 llvm_unreachable("TAILJMP64 would not be touched here.");
12526 case X86::TCRETURNdi64:
12527 case X86::TCRETURNri64:
12528 case X86::TCRETURNmi64:
12530 case X86::WIN_ALLOCA:
12531 return EmitLoweredWinAlloca(MI, BB);
12532 case X86::SEG_ALLOCA_32:
12533 return EmitLoweredSegAlloca(MI, BB, false);
12534 case X86::SEG_ALLOCA_64:
12535 return EmitLoweredSegAlloca(MI, BB, true);
12536 case X86::TLSCall_32:
12537 case X86::TLSCall_64:
12538 return EmitLoweredTLSCall(MI, BB);
12539 case X86::CMOV_GR8:
12540 case X86::CMOV_FR32:
12541 case X86::CMOV_FR64:
12542 case X86::CMOV_V4F32:
12543 case X86::CMOV_V2F64:
12544 case X86::CMOV_V2I64:
12545 case X86::CMOV_V8F32:
12546 case X86::CMOV_V4F64:
12547 case X86::CMOV_V4I64:
12548 case X86::CMOV_GR16:
12549 case X86::CMOV_GR32:
12550 case X86::CMOV_RFP32:
12551 case X86::CMOV_RFP64:
12552 case X86::CMOV_RFP80:
12553 return EmitLoweredSelect(MI, BB);
12555 case X86::FP32_TO_INT16_IN_MEM:
12556 case X86::FP32_TO_INT32_IN_MEM:
12557 case X86::FP32_TO_INT64_IN_MEM:
12558 case X86::FP64_TO_INT16_IN_MEM:
12559 case X86::FP64_TO_INT32_IN_MEM:
12560 case X86::FP64_TO_INT64_IN_MEM:
12561 case X86::FP80_TO_INT16_IN_MEM:
12562 case X86::FP80_TO_INT32_IN_MEM:
12563 case X86::FP80_TO_INT64_IN_MEM: {
12564 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12565 DebugLoc DL = MI->getDebugLoc();
12567 // Change the floating point control register to use "round towards zero"
12568 // mode when truncating to an integer value.
12569 MachineFunction *F = BB->getParent();
12570 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
12571 addFrameReference(BuildMI(*BB, MI, DL,
12572 TII->get(X86::FNSTCW16m)), CWFrameIdx);
12574 // Load the old value of the high byte of the control word...
12576 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
12577 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
12580 // Set the high part to be round to zero...
12581 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
12584 // Reload the modified control word now...
12585 addFrameReference(BuildMI(*BB, MI, DL,
12586 TII->get(X86::FLDCW16m)), CWFrameIdx);
12588 // Restore the memory image of control word to original value
12589 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
12592 // Get the X86 opcode to use.
12594 switch (MI->getOpcode()) {
12595 default: llvm_unreachable("illegal opcode!");
12596 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
12597 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
12598 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
12599 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
12600 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
12601 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
12602 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
12603 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
12604 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
12608 MachineOperand &Op = MI->getOperand(0);
12610 AM.BaseType = X86AddressMode::RegBase;
12611 AM.Base.Reg = Op.getReg();
12613 AM.BaseType = X86AddressMode::FrameIndexBase;
12614 AM.Base.FrameIndex = Op.getIndex();
12616 Op = MI->getOperand(1);
12618 AM.Scale = Op.getImm();
12619 Op = MI->getOperand(2);
12621 AM.IndexReg = Op.getImm();
12622 Op = MI->getOperand(3);
12623 if (Op.isGlobal()) {
12624 AM.GV = Op.getGlobal();
12626 AM.Disp = Op.getImm();
12628 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
12629 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
12631 // Reload the original control word now.
12632 addFrameReference(BuildMI(*BB, MI, DL,
12633 TII->get(X86::FLDCW16m)), CWFrameIdx);
12635 MI->eraseFromParent(); // The pseudo instruction is gone now.
12638 // String/text processing lowering.
12639 case X86::PCMPISTRM128REG:
12640 case X86::VPCMPISTRM128REG:
12641 return EmitPCMP(MI, BB, 3, false /* in-mem */);
12642 case X86::PCMPISTRM128MEM:
12643 case X86::VPCMPISTRM128MEM:
12644 return EmitPCMP(MI, BB, 3, true /* in-mem */);
12645 case X86::PCMPESTRM128REG:
12646 case X86::VPCMPESTRM128REG:
12647 return EmitPCMP(MI, BB, 5, false /* in mem */);
12648 case X86::PCMPESTRM128MEM:
12649 case X86::VPCMPESTRM128MEM:
12650 return EmitPCMP(MI, BB, 5, true /* in mem */);
12652 // Thread synchronization.
12654 return EmitMonitor(MI, BB);
12656 return EmitMwait(MI, BB);
12658 // Atomic Lowering.
12659 case X86::ATOMAND32:
12660 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
12661 X86::AND32ri, X86::MOV32rm,
12663 X86::NOT32r, X86::EAX,
12664 &X86::GR32RegClass);
12665 case X86::ATOMOR32:
12666 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
12667 X86::OR32ri, X86::MOV32rm,
12669 X86::NOT32r, X86::EAX,
12670 &X86::GR32RegClass);
12671 case X86::ATOMXOR32:
12672 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
12673 X86::XOR32ri, X86::MOV32rm,
12675 X86::NOT32r, X86::EAX,
12676 &X86::GR32RegClass);
12677 case X86::ATOMNAND32:
12678 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
12679 X86::AND32ri, X86::MOV32rm,
12681 X86::NOT32r, X86::EAX,
12682 &X86::GR32RegClass, true);
12683 case X86::ATOMMIN32:
12684 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
12685 case X86::ATOMMAX32:
12686 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
12687 case X86::ATOMUMIN32:
12688 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
12689 case X86::ATOMUMAX32:
12690 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
12692 case X86::ATOMAND16:
12693 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
12694 X86::AND16ri, X86::MOV16rm,
12696 X86::NOT16r, X86::AX,
12697 &X86::GR16RegClass);
12698 case X86::ATOMOR16:
12699 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
12700 X86::OR16ri, X86::MOV16rm,
12702 X86::NOT16r, X86::AX,
12703 &X86::GR16RegClass);
12704 case X86::ATOMXOR16:
12705 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
12706 X86::XOR16ri, X86::MOV16rm,
12708 X86::NOT16r, X86::AX,
12709 &X86::GR16RegClass);
12710 case X86::ATOMNAND16:
12711 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
12712 X86::AND16ri, X86::MOV16rm,
12714 X86::NOT16r, X86::AX,
12715 &X86::GR16RegClass, true);
12716 case X86::ATOMMIN16:
12717 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
12718 case X86::ATOMMAX16:
12719 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
12720 case X86::ATOMUMIN16:
12721 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
12722 case X86::ATOMUMAX16:
12723 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
12725 case X86::ATOMAND8:
12726 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
12727 X86::AND8ri, X86::MOV8rm,
12729 X86::NOT8r, X86::AL,
12730 &X86::GR8RegClass);
12732 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
12733 X86::OR8ri, X86::MOV8rm,
12735 X86::NOT8r, X86::AL,
12736 &X86::GR8RegClass);
12737 case X86::ATOMXOR8:
12738 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
12739 X86::XOR8ri, X86::MOV8rm,
12741 X86::NOT8r, X86::AL,
12742 &X86::GR8RegClass);
12743 case X86::ATOMNAND8:
12744 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
12745 X86::AND8ri, X86::MOV8rm,
12747 X86::NOT8r, X86::AL,
12748 &X86::GR8RegClass, true);
12749 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
12750 // This group is for 64-bit host.
12751 case X86::ATOMAND64:
12752 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
12753 X86::AND64ri32, X86::MOV64rm,
12755 X86::NOT64r, X86::RAX,
12756 &X86::GR64RegClass);
12757 case X86::ATOMOR64:
12758 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
12759 X86::OR64ri32, X86::MOV64rm,
12761 X86::NOT64r, X86::RAX,
12762 &X86::GR64RegClass);
12763 case X86::ATOMXOR64:
12764 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
12765 X86::XOR64ri32, X86::MOV64rm,
12767 X86::NOT64r, X86::RAX,
12768 &X86::GR64RegClass);
12769 case X86::ATOMNAND64:
12770 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
12771 X86::AND64ri32, X86::MOV64rm,
12773 X86::NOT64r, X86::RAX,
12774 &X86::GR64RegClass, true);
12775 case X86::ATOMMIN64:
12776 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
12777 case X86::ATOMMAX64:
12778 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
12779 case X86::ATOMUMIN64:
12780 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
12781 case X86::ATOMUMAX64:
12782 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
12784 // This group does 64-bit operations on a 32-bit host.
12785 case X86::ATOMAND6432:
12786 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12787 X86::AND32rr, X86::AND32rr,
12788 X86::AND32ri, X86::AND32ri,
12790 case X86::ATOMOR6432:
12791 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12792 X86::OR32rr, X86::OR32rr,
12793 X86::OR32ri, X86::OR32ri,
12795 case X86::ATOMXOR6432:
12796 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12797 X86::XOR32rr, X86::XOR32rr,
12798 X86::XOR32ri, X86::XOR32ri,
12800 case X86::ATOMNAND6432:
12801 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12802 X86::AND32rr, X86::AND32rr,
12803 X86::AND32ri, X86::AND32ri,
12805 case X86::ATOMADD6432:
12806 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12807 X86::ADD32rr, X86::ADC32rr,
12808 X86::ADD32ri, X86::ADC32ri,
12810 case X86::ATOMSUB6432:
12811 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12812 X86::SUB32rr, X86::SBB32rr,
12813 X86::SUB32ri, X86::SBB32ri,
12815 case X86::ATOMSWAP6432:
12816 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12817 X86::MOV32rr, X86::MOV32rr,
12818 X86::MOV32ri, X86::MOV32ri,
12820 case X86::VASTART_SAVE_XMM_REGS:
12821 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
12823 case X86::VAARG_64:
12824 return EmitVAARG64WithCustomInserter(MI, BB);
12828 //===----------------------------------------------------------------------===//
12829 // X86 Optimization Hooks
12830 //===----------------------------------------------------------------------===//
12832 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
12835 const SelectionDAG &DAG,
12836 unsigned Depth) const {
12837 unsigned BitWidth = KnownZero.getBitWidth();
12838 unsigned Opc = Op.getOpcode();
12839 assert((Opc >= ISD::BUILTIN_OP_END ||
12840 Opc == ISD::INTRINSIC_WO_CHAIN ||
12841 Opc == ISD::INTRINSIC_W_CHAIN ||
12842 Opc == ISD::INTRINSIC_VOID) &&
12843 "Should use MaskedValueIsZero if you don't know whether Op"
12844 " is a target node!");
12846 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
12860 // These nodes' second result is a boolean.
12861 if (Op.getResNo() == 0)
12864 case X86ISD::SETCC:
12865 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
12867 case ISD::INTRINSIC_WO_CHAIN: {
12868 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
12869 unsigned NumLoBits = 0;
12872 case Intrinsic::x86_sse_movmsk_ps:
12873 case Intrinsic::x86_avx_movmsk_ps_256:
12874 case Intrinsic::x86_sse2_movmsk_pd:
12875 case Intrinsic::x86_avx_movmsk_pd_256:
12876 case Intrinsic::x86_mmx_pmovmskb:
12877 case Intrinsic::x86_sse2_pmovmskb_128:
12878 case Intrinsic::x86_avx2_pmovmskb: {
12879 // High bits of movmskp{s|d}, pmovmskb are known zero.
12881 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
12882 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
12883 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
12884 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
12885 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
12886 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
12887 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
12888 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
12890 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
12899 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
12900 unsigned Depth) const {
12901 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
12902 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
12903 return Op.getValueType().getScalarType().getSizeInBits();
12909 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
12910 /// node is a GlobalAddress + offset.
12911 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
12912 const GlobalValue* &GA,
12913 int64_t &Offset) const {
12914 if (N->getOpcode() == X86ISD::Wrapper) {
12915 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
12916 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
12917 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
12921 return TargetLowering::isGAPlusOffset(N, GA, Offset);
12924 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
12925 /// same as extracting the high 128-bit part of 256-bit vector and then
12926 /// inserting the result into the low part of a new 256-bit vector
12927 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
12928 EVT VT = SVOp->getValueType(0);
12929 unsigned NumElems = VT.getVectorNumElements();
12931 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
12932 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
12933 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
12934 SVOp->getMaskElt(j) >= 0)
12940 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
12941 /// same as extracting the low 128-bit part of 256-bit vector and then
12942 /// inserting the result into the high part of a new 256-bit vector
12943 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
12944 EVT VT = SVOp->getValueType(0);
12945 unsigned NumElems = VT.getVectorNumElements();
12947 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
12948 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
12949 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
12950 SVOp->getMaskElt(j) >= 0)
12956 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
12957 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
12958 TargetLowering::DAGCombinerInfo &DCI,
12959 const X86Subtarget* Subtarget) {
12960 DebugLoc dl = N->getDebugLoc();
12961 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
12962 SDValue V1 = SVOp->getOperand(0);
12963 SDValue V2 = SVOp->getOperand(1);
12964 EVT VT = SVOp->getValueType(0);
12965 unsigned NumElems = VT.getVectorNumElements();
12967 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
12968 V2.getOpcode() == ISD::CONCAT_VECTORS) {
12972 // V UNDEF BUILD_VECTOR UNDEF
12974 // CONCAT_VECTOR CONCAT_VECTOR
12977 // RESULT: V + zero extended
12979 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
12980 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
12981 V1.getOperand(1).getOpcode() != ISD::UNDEF)
12984 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
12987 // To match the shuffle mask, the first half of the mask should
12988 // be exactly the first vector, and all the rest a splat with the
12989 // first element of the second one.
12990 for (unsigned i = 0; i != NumElems/2; ++i)
12991 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
12992 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
12995 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
12996 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
12997 if (Ld->hasNUsesOfValue(1, 0)) {
12998 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
12999 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
13001 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2,
13003 Ld->getPointerInfo(),
13004 Ld->getAlignment(),
13005 false/*isVolatile*/, true/*ReadMem*/,
13006 false/*WriteMem*/);
13007 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
13011 // Emit a zeroed vector and insert the desired subvector on its
13013 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
13014 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
13015 return DCI.CombineTo(N, InsV);
13018 //===--------------------------------------------------------------------===//
13019 // Combine some shuffles into subvector extracts and inserts:
13022 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
13023 if (isShuffleHigh128VectorInsertLow(SVOp)) {
13024 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
13025 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
13026 return DCI.CombineTo(N, InsV);
13029 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
13030 if (isShuffleLow128VectorInsertHigh(SVOp)) {
13031 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
13032 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
13033 return DCI.CombineTo(N, InsV);
13039 /// PerformShuffleCombine - Performs several different shuffle combines.
13040 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
13041 TargetLowering::DAGCombinerInfo &DCI,
13042 const X86Subtarget *Subtarget) {
13043 DebugLoc dl = N->getDebugLoc();
13044 EVT VT = N->getValueType(0);
13046 // Don't create instructions with illegal types after legalize types has run.
13047 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13048 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
13051 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
13052 if (Subtarget->hasAVX() && VT.getSizeInBits() == 256 &&
13053 N->getOpcode() == ISD::VECTOR_SHUFFLE)
13054 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
13056 // Only handle 128 wide vector from here on.
13057 if (VT.getSizeInBits() != 128)
13060 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
13061 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
13062 // consecutive, non-overlapping, and in the right order.
13063 SmallVector<SDValue, 16> Elts;
13064 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
13065 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
13067 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG);
13071 /// DCI, PerformTruncateCombine - Converts truncate operation to
13072 /// a sequence of vector shuffle operations.
13073 /// It is possible when we truncate 256-bit vector to 128-bit vector
13075 SDValue X86TargetLowering::PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
13076 DAGCombinerInfo &DCI) const {
13077 if (!DCI.isBeforeLegalizeOps())
13080 if (!Subtarget->hasAVX())
13083 EVT VT = N->getValueType(0);
13084 SDValue Op = N->getOperand(0);
13085 EVT OpVT = Op.getValueType();
13086 DebugLoc dl = N->getDebugLoc();
13088 if ((VT == MVT::v4i32) && (OpVT == MVT::v4i64)) {
13090 if (Subtarget->hasAVX2()) {
13091 // AVX2: v4i64 -> v4i32
13094 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
13096 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v8i32, Op);
13097 Op = DAG.getVectorShuffle(MVT::v8i32, dl, Op, DAG.getUNDEF(MVT::v8i32),
13100 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, Op,
13101 DAG.getIntPtrConstant(0));
13104 // AVX: v4i64 -> v4i32
13105 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op,
13106 DAG.getIntPtrConstant(0));
13108 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op,
13109 DAG.getIntPtrConstant(2));
13111 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpLo);
13112 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpHi);
13115 static const int ShufMask1[] = {0, 2, 0, 0};
13117 OpLo = DAG.getVectorShuffle(VT, dl, OpLo, DAG.getUNDEF(VT), ShufMask1);
13118 OpHi = DAG.getVectorShuffle(VT, dl, OpHi, DAG.getUNDEF(VT), ShufMask1);
13121 static const int ShufMask2[] = {0, 1, 4, 5};
13123 return DAG.getVectorShuffle(VT, dl, OpLo, OpHi, ShufMask2);
13126 if ((VT == MVT::v8i16) && (OpVT == MVT::v8i32)) {
13128 if (Subtarget->hasAVX2()) {
13129 // AVX2: v8i32 -> v8i16
13131 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v32i8, Op);
13134 SmallVector<SDValue,32> pshufbMask;
13135 for (unsigned i = 0; i < 2; ++i) {
13136 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
13137 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
13138 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
13139 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
13140 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
13141 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
13142 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
13143 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
13144 for (unsigned j = 0; j < 8; ++j)
13145 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
13147 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v32i8,
13148 &pshufbMask[0], 32);
13149 Op = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v32i8, Op, BV);
13151 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4i64, Op);
13153 static const int ShufMask[] = {0, 2, -1, -1};
13154 Op = DAG.getVectorShuffle(MVT::v4i64, dl, Op, DAG.getUNDEF(MVT::v4i64),
13157 Op = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op,
13158 DAG.getIntPtrConstant(0));
13160 return DAG.getNode(ISD::BITCAST, dl, VT, Op);
13163 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i32, Op,
13164 DAG.getIntPtrConstant(0));
13166 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i32, Op,
13167 DAG.getIntPtrConstant(4));
13169 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLo);
13170 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpHi);
13173 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
13174 -1, -1, -1, -1, -1, -1, -1, -1};
13176 OpLo = DAG.getVectorShuffle(MVT::v16i8, dl, OpLo, DAG.getUNDEF(MVT::v16i8),
13178 OpHi = DAG.getVectorShuffle(MVT::v16i8, dl, OpHi, DAG.getUNDEF(MVT::v16i8),
13181 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpLo);
13182 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpHi);
13185 static const int ShufMask2[] = {0, 1, 4, 5};
13187 SDValue res = DAG.getVectorShuffle(MVT::v4i32, dl, OpLo, OpHi, ShufMask2);
13188 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, res);
13194 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
13195 /// specific shuffle of a load can be folded into a single element load.
13196 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
13197 /// shuffles have been customed lowered so we need to handle those here.
13198 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
13199 TargetLowering::DAGCombinerInfo &DCI) {
13200 if (DCI.isBeforeLegalizeOps())
13203 SDValue InVec = N->getOperand(0);
13204 SDValue EltNo = N->getOperand(1);
13206 if (!isa<ConstantSDNode>(EltNo))
13209 EVT VT = InVec.getValueType();
13211 bool HasShuffleIntoBitcast = false;
13212 if (InVec.getOpcode() == ISD::BITCAST) {
13213 // Don't duplicate a load with other uses.
13214 if (!InVec.hasOneUse())
13216 EVT BCVT = InVec.getOperand(0).getValueType();
13217 if (BCVT.getVectorNumElements() != VT.getVectorNumElements())
13219 InVec = InVec.getOperand(0);
13220 HasShuffleIntoBitcast = true;
13223 if (!isTargetShuffle(InVec.getOpcode()))
13226 // Don't duplicate a load with other uses.
13227 if (!InVec.hasOneUse())
13230 SmallVector<int, 16> ShuffleMask;
13232 if (!getTargetShuffleMask(InVec.getNode(), VT.getSimpleVT(), ShuffleMask,
13236 // Select the input vector, guarding against out of range extract vector.
13237 unsigned NumElems = VT.getVectorNumElements();
13238 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
13239 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
13240 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
13241 : InVec.getOperand(1);
13243 // If inputs to shuffle are the same for both ops, then allow 2 uses
13244 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
13246 if (LdNode.getOpcode() == ISD::BITCAST) {
13247 // Don't duplicate a load with other uses.
13248 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
13251 AllowedUses = 1; // only allow 1 load use if we have a bitcast
13252 LdNode = LdNode.getOperand(0);
13255 if (!ISD::isNormalLoad(LdNode.getNode()))
13258 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
13260 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
13263 if (HasShuffleIntoBitcast) {
13264 // If there's a bitcast before the shuffle, check if the load type and
13265 // alignment is valid.
13266 unsigned Align = LN0->getAlignment();
13267 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13268 unsigned NewAlign = TLI.getTargetData()->
13269 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
13271 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
13275 // All checks match so transform back to vector_shuffle so that DAG combiner
13276 // can finish the job
13277 DebugLoc dl = N->getDebugLoc();
13279 // Create shuffle node taking into account the case that its a unary shuffle
13280 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1);
13281 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl,
13282 InVec.getOperand(0), Shuffle,
13284 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
13285 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
13289 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
13290 /// generation and convert it from being a bunch of shuffles and extracts
13291 /// to a simple store and scalar loads to extract the elements.
13292 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
13293 TargetLowering::DAGCombinerInfo &DCI) {
13294 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
13295 if (NewOp.getNode())
13298 SDValue InputVector = N->getOperand(0);
13300 // Only operate on vectors of 4 elements, where the alternative shuffling
13301 // gets to be more expensive.
13302 if (InputVector.getValueType() != MVT::v4i32)
13305 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
13306 // single use which is a sign-extend or zero-extend, and all elements are
13308 SmallVector<SDNode *, 4> Uses;
13309 unsigned ExtractedElements = 0;
13310 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
13311 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
13312 if (UI.getUse().getResNo() != InputVector.getResNo())
13315 SDNode *Extract = *UI;
13316 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
13319 if (Extract->getValueType(0) != MVT::i32)
13321 if (!Extract->hasOneUse())
13323 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
13324 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
13326 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
13329 // Record which element was extracted.
13330 ExtractedElements |=
13331 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
13333 Uses.push_back(Extract);
13336 // If not all the elements were used, this may not be worthwhile.
13337 if (ExtractedElements != 15)
13340 // Ok, we've now decided to do the transformation.
13341 DebugLoc dl = InputVector.getDebugLoc();
13343 // Store the value to a temporary stack slot.
13344 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
13345 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
13346 MachinePointerInfo(), false, false, 0);
13348 // Replace each use (extract) with a load of the appropriate element.
13349 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
13350 UE = Uses.end(); UI != UE; ++UI) {
13351 SDNode *Extract = *UI;
13353 // cOMpute the element's address.
13354 SDValue Idx = Extract->getOperand(1);
13356 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
13357 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
13358 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13359 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
13361 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
13362 StackPtr, OffsetVal);
13364 // Load the scalar.
13365 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
13366 ScalarAddr, MachinePointerInfo(),
13367 false, false, false, 0);
13369 // Replace the exact with the load.
13370 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
13373 // The replacement was made in place; don't return anything.
13377 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
13379 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
13380 TargetLowering::DAGCombinerInfo &DCI,
13381 const X86Subtarget *Subtarget) {
13382 DebugLoc DL = N->getDebugLoc();
13383 SDValue Cond = N->getOperand(0);
13384 // Get the LHS/RHS of the select.
13385 SDValue LHS = N->getOperand(1);
13386 SDValue RHS = N->getOperand(2);
13387 EVT VT = LHS.getValueType();
13389 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
13390 // instructions match the semantics of the common C idiom x<y?x:y but not
13391 // x<=y?x:y, because of how they handle negative zero (which can be
13392 // ignored in unsafe-math mode).
13393 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
13394 VT != MVT::f80 && DAG.getTargetLoweringInfo().isTypeLegal(VT) &&
13395 (Subtarget->hasSSE2() ||
13396 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
13397 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
13399 unsigned Opcode = 0;
13400 // Check for x CC y ? x : y.
13401 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
13402 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
13406 // Converting this to a min would handle NaNs incorrectly, and swapping
13407 // the operands would cause it to handle comparisons between positive
13408 // and negative zero incorrectly.
13409 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
13410 if (!DAG.getTarget().Options.UnsafeFPMath &&
13411 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
13413 std::swap(LHS, RHS);
13415 Opcode = X86ISD::FMIN;
13418 // Converting this to a min would handle comparisons between positive
13419 // and negative zero incorrectly.
13420 if (!DAG.getTarget().Options.UnsafeFPMath &&
13421 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
13423 Opcode = X86ISD::FMIN;
13426 // Converting this to a min would handle both negative zeros and NaNs
13427 // incorrectly, but we can swap the operands to fix both.
13428 std::swap(LHS, RHS);
13432 Opcode = X86ISD::FMIN;
13436 // Converting this to a max would handle comparisons between positive
13437 // and negative zero incorrectly.
13438 if (!DAG.getTarget().Options.UnsafeFPMath &&
13439 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
13441 Opcode = X86ISD::FMAX;
13444 // Converting this to a max would handle NaNs incorrectly, and swapping
13445 // the operands would cause it to handle comparisons between positive
13446 // and negative zero incorrectly.
13447 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
13448 if (!DAG.getTarget().Options.UnsafeFPMath &&
13449 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
13451 std::swap(LHS, RHS);
13453 Opcode = X86ISD::FMAX;
13456 // Converting this to a max would handle both negative zeros and NaNs
13457 // incorrectly, but we can swap the operands to fix both.
13458 std::swap(LHS, RHS);
13462 Opcode = X86ISD::FMAX;
13465 // Check for x CC y ? y : x -- a min/max with reversed arms.
13466 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
13467 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
13471 // Converting this to a min would handle comparisons between positive
13472 // and negative zero incorrectly, and swapping the operands would
13473 // cause it to handle NaNs incorrectly.
13474 if (!DAG.getTarget().Options.UnsafeFPMath &&
13475 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
13476 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
13478 std::swap(LHS, RHS);
13480 Opcode = X86ISD::FMIN;
13483 // Converting this to a min would handle NaNs incorrectly.
13484 if (!DAG.getTarget().Options.UnsafeFPMath &&
13485 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
13487 Opcode = X86ISD::FMIN;
13490 // Converting this to a min would handle both negative zeros and NaNs
13491 // incorrectly, but we can swap the operands to fix both.
13492 std::swap(LHS, RHS);
13496 Opcode = X86ISD::FMIN;
13500 // Converting this to a max would handle NaNs incorrectly.
13501 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
13503 Opcode = X86ISD::FMAX;
13506 // Converting this to a max would handle comparisons between positive
13507 // and negative zero incorrectly, and swapping the operands would
13508 // cause it to handle NaNs incorrectly.
13509 if (!DAG.getTarget().Options.UnsafeFPMath &&
13510 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
13511 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
13513 std::swap(LHS, RHS);
13515 Opcode = X86ISD::FMAX;
13518 // Converting this to a max would handle both negative zeros and NaNs
13519 // incorrectly, but we can swap the operands to fix both.
13520 std::swap(LHS, RHS);
13524 Opcode = X86ISD::FMAX;
13530 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
13533 // If this is a select between two integer constants, try to do some
13535 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
13536 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
13537 // Don't do this for crazy integer types.
13538 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
13539 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
13540 // so that TrueC (the true value) is larger than FalseC.
13541 bool NeedsCondInvert = false;
13543 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
13544 // Efficiently invertible.
13545 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
13546 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
13547 isa<ConstantSDNode>(Cond.getOperand(1))))) {
13548 NeedsCondInvert = true;
13549 std::swap(TrueC, FalseC);
13552 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
13553 if (FalseC->getAPIntValue() == 0 &&
13554 TrueC->getAPIntValue().isPowerOf2()) {
13555 if (NeedsCondInvert) // Invert the condition if needed.
13556 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13557 DAG.getConstant(1, Cond.getValueType()));
13559 // Zero extend the condition if needed.
13560 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
13562 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
13563 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
13564 DAG.getConstant(ShAmt, MVT::i8));
13567 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
13568 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
13569 if (NeedsCondInvert) // Invert the condition if needed.
13570 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13571 DAG.getConstant(1, Cond.getValueType()));
13573 // Zero extend the condition if needed.
13574 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
13575 FalseC->getValueType(0), Cond);
13576 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13577 SDValue(FalseC, 0));
13580 // Optimize cases that will turn into an LEA instruction. This requires
13581 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
13582 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
13583 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
13584 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
13586 bool isFastMultiplier = false;
13588 switch ((unsigned char)Diff) {
13590 case 1: // result = add base, cond
13591 case 2: // result = lea base( , cond*2)
13592 case 3: // result = lea base(cond, cond*2)
13593 case 4: // result = lea base( , cond*4)
13594 case 5: // result = lea base(cond, cond*4)
13595 case 8: // result = lea base( , cond*8)
13596 case 9: // result = lea base(cond, cond*8)
13597 isFastMultiplier = true;
13602 if (isFastMultiplier) {
13603 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
13604 if (NeedsCondInvert) // Invert the condition if needed.
13605 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13606 DAG.getConstant(1, Cond.getValueType()));
13608 // Zero extend the condition if needed.
13609 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
13611 // Scale the condition by the difference.
13613 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
13614 DAG.getConstant(Diff, Cond.getValueType()));
13616 // Add the base if non-zero.
13617 if (FalseC->getAPIntValue() != 0)
13618 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13619 SDValue(FalseC, 0));
13626 // Canonicalize max and min:
13627 // (x > y) ? x : y -> (x >= y) ? x : y
13628 // (x < y) ? x : y -> (x <= y) ? x : y
13629 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
13630 // the need for an extra compare
13631 // against zero. e.g.
13632 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
13634 // testl %edi, %edi
13636 // cmovgl %edi, %eax
13640 // cmovsl %eax, %edi
13641 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
13642 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
13643 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
13644 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
13649 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
13650 Cond = DAG.getSetCC(Cond.getDebugLoc(), Cond.getValueType(),
13651 Cond.getOperand(0), Cond.getOperand(1), NewCC);
13652 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
13657 // If we know that this node is legal then we know that it is going to be
13658 // matched by one of the SSE/AVX BLEND instructions. These instructions only
13659 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
13660 // to simplify previous instructions.
13661 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13662 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
13663 !DCI.isBeforeLegalize() && TLI.isOperationLegal(ISD::VSELECT, VT)) {
13664 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
13666 // Don't optimize vector selects that map to mask-registers.
13670 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
13671 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
13673 APInt KnownZero, KnownOne;
13674 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
13675 DCI.isBeforeLegalizeOps());
13676 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
13677 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
13678 DCI.CommitTargetLoweringOpt(TLO);
13684 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
13685 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
13686 TargetLowering::DAGCombinerInfo &DCI) {
13687 DebugLoc DL = N->getDebugLoc();
13689 // If the flag operand isn't dead, don't touch this CMOV.
13690 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
13693 SDValue FalseOp = N->getOperand(0);
13694 SDValue TrueOp = N->getOperand(1);
13695 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
13696 SDValue Cond = N->getOperand(3);
13697 if (CC == X86::COND_E || CC == X86::COND_NE) {
13698 switch (Cond.getOpcode()) {
13702 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
13703 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
13704 return (CC == X86::COND_E) ? FalseOp : TrueOp;
13708 // If this is a select between two integer constants, try to do some
13709 // optimizations. Note that the operands are ordered the opposite of SELECT
13711 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
13712 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
13713 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
13714 // larger than FalseC (the false value).
13715 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
13716 CC = X86::GetOppositeBranchCondition(CC);
13717 std::swap(TrueC, FalseC);
13720 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
13721 // This is efficient for any integer data type (including i8/i16) and
13723 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
13724 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13725 DAG.getConstant(CC, MVT::i8), Cond);
13727 // Zero extend the condition if needed.
13728 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
13730 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
13731 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
13732 DAG.getConstant(ShAmt, MVT::i8));
13733 if (N->getNumValues() == 2) // Dead flag value?
13734 return DCI.CombineTo(N, Cond, SDValue());
13738 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
13739 // for any integer data type, including i8/i16.
13740 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
13741 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13742 DAG.getConstant(CC, MVT::i8), Cond);
13744 // Zero extend the condition if needed.
13745 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
13746 FalseC->getValueType(0), Cond);
13747 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13748 SDValue(FalseC, 0));
13750 if (N->getNumValues() == 2) // Dead flag value?
13751 return DCI.CombineTo(N, Cond, SDValue());
13755 // Optimize cases that will turn into an LEA instruction. This requires
13756 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
13757 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
13758 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
13759 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
13761 bool isFastMultiplier = false;
13763 switch ((unsigned char)Diff) {
13765 case 1: // result = add base, cond
13766 case 2: // result = lea base( , cond*2)
13767 case 3: // result = lea base(cond, cond*2)
13768 case 4: // result = lea base( , cond*4)
13769 case 5: // result = lea base(cond, cond*4)
13770 case 8: // result = lea base( , cond*8)
13771 case 9: // result = lea base(cond, cond*8)
13772 isFastMultiplier = true;
13777 if (isFastMultiplier) {
13778 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
13779 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13780 DAG.getConstant(CC, MVT::i8), Cond);
13781 // Zero extend the condition if needed.
13782 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
13784 // Scale the condition by the difference.
13786 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
13787 DAG.getConstant(Diff, Cond.getValueType()));
13789 // Add the base if non-zero.
13790 if (FalseC->getAPIntValue() != 0)
13791 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13792 SDValue(FalseC, 0));
13793 if (N->getNumValues() == 2) // Dead flag value?
13794 return DCI.CombineTo(N, Cond, SDValue());
13804 /// PerformMulCombine - Optimize a single multiply with constant into two
13805 /// in order to implement it with two cheaper instructions, e.g.
13806 /// LEA + SHL, LEA + LEA.
13807 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
13808 TargetLowering::DAGCombinerInfo &DCI) {
13809 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
13812 EVT VT = N->getValueType(0);
13813 if (VT != MVT::i64)
13816 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
13819 uint64_t MulAmt = C->getZExtValue();
13820 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
13823 uint64_t MulAmt1 = 0;
13824 uint64_t MulAmt2 = 0;
13825 if ((MulAmt % 9) == 0) {
13827 MulAmt2 = MulAmt / 9;
13828 } else if ((MulAmt % 5) == 0) {
13830 MulAmt2 = MulAmt / 5;
13831 } else if ((MulAmt % 3) == 0) {
13833 MulAmt2 = MulAmt / 3;
13836 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
13837 DebugLoc DL = N->getDebugLoc();
13839 if (isPowerOf2_64(MulAmt2) &&
13840 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
13841 // If second multiplifer is pow2, issue it first. We want the multiply by
13842 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
13844 std::swap(MulAmt1, MulAmt2);
13847 if (isPowerOf2_64(MulAmt1))
13848 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
13849 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
13851 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
13852 DAG.getConstant(MulAmt1, VT));
13854 if (isPowerOf2_64(MulAmt2))
13855 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
13856 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
13858 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
13859 DAG.getConstant(MulAmt2, VT));
13861 // Do not add new nodes to DAG combiner worklist.
13862 DCI.CombineTo(N, NewMul, false);
13867 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
13868 SDValue N0 = N->getOperand(0);
13869 SDValue N1 = N->getOperand(1);
13870 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
13871 EVT VT = N0.getValueType();
13873 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
13874 // since the result of setcc_c is all zero's or all ones.
13875 if (VT.isInteger() && !VT.isVector() &&
13876 N1C && N0.getOpcode() == ISD::AND &&
13877 N0.getOperand(1).getOpcode() == ISD::Constant) {
13878 SDValue N00 = N0.getOperand(0);
13879 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
13880 ((N00.getOpcode() == ISD::ANY_EXTEND ||
13881 N00.getOpcode() == ISD::ZERO_EXTEND) &&
13882 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
13883 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
13884 APInt ShAmt = N1C->getAPIntValue();
13885 Mask = Mask.shl(ShAmt);
13887 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
13888 N00, DAG.getConstant(Mask, VT));
13893 // Hardware support for vector shifts is sparse which makes us scalarize the
13894 // vector operations in many cases. Also, on sandybridge ADD is faster than
13896 // (shl V, 1) -> add V,V
13897 if (isSplatVector(N1.getNode())) {
13898 assert(N0.getValueType().isVector() && "Invalid vector shift type");
13899 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1->getOperand(0));
13900 // We shift all of the values by one. In many cases we do not have
13901 // hardware support for this operation. This is better expressed as an ADD
13903 if (N1C && (1 == N1C->getZExtValue())) {
13904 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N0);
13911 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
13913 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
13914 TargetLowering::DAGCombinerInfo &DCI,
13915 const X86Subtarget *Subtarget) {
13916 EVT VT = N->getValueType(0);
13917 if (N->getOpcode() == ISD::SHL) {
13918 SDValue V = PerformSHLCombine(N, DAG);
13919 if (V.getNode()) return V;
13922 // On X86 with SSE2 support, we can transform this to a vector shift if
13923 // all elements are shifted by the same amount. We can't do this in legalize
13924 // because the a constant vector is typically transformed to a constant pool
13925 // so we have no knowledge of the shift amount.
13926 if (!Subtarget->hasSSE2())
13929 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
13930 (!Subtarget->hasAVX2() ||
13931 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
13934 SDValue ShAmtOp = N->getOperand(1);
13935 EVT EltVT = VT.getVectorElementType();
13936 DebugLoc DL = N->getDebugLoc();
13937 SDValue BaseShAmt = SDValue();
13938 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
13939 unsigned NumElts = VT.getVectorNumElements();
13941 for (; i != NumElts; ++i) {
13942 SDValue Arg = ShAmtOp.getOperand(i);
13943 if (Arg.getOpcode() == ISD::UNDEF) continue;
13947 // Handle the case where the build_vector is all undef
13948 // FIXME: Should DAG allow this?
13952 for (; i != NumElts; ++i) {
13953 SDValue Arg = ShAmtOp.getOperand(i);
13954 if (Arg.getOpcode() == ISD::UNDEF) continue;
13955 if (Arg != BaseShAmt) {
13959 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
13960 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
13961 SDValue InVec = ShAmtOp.getOperand(0);
13962 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
13963 unsigned NumElts = InVec.getValueType().getVectorNumElements();
13965 for (; i != NumElts; ++i) {
13966 SDValue Arg = InVec.getOperand(i);
13967 if (Arg.getOpcode() == ISD::UNDEF) continue;
13971 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
13972 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
13973 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex();
13974 if (C->getZExtValue() == SplatIdx)
13975 BaseShAmt = InVec.getOperand(1);
13978 if (BaseShAmt.getNode() == 0) {
13979 // Don't create instructions with illegal types after legalize
13981 if (!DAG.getTargetLoweringInfo().isTypeLegal(EltVT) &&
13982 !DCI.isBeforeLegalize())
13985 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
13986 DAG.getIntPtrConstant(0));
13991 // The shift amount is an i32.
13992 if (EltVT.bitsGT(MVT::i32))
13993 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
13994 else if (EltVT.bitsLT(MVT::i32))
13995 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt);
13997 // The shift amount is identical so we can do a vector shift.
13998 SDValue ValOp = N->getOperand(0);
13999 switch (N->getOpcode()) {
14001 llvm_unreachable("Unknown shift opcode!");
14003 switch (VT.getSimpleVT().SimpleTy) {
14004 default: return SDValue();
14011 return getTargetVShiftNode(X86ISD::VSHLI, DL, VT, ValOp, BaseShAmt, DAG);
14014 switch (VT.getSimpleVT().SimpleTy) {
14015 default: return SDValue();
14020 return getTargetVShiftNode(X86ISD::VSRAI, DL, VT, ValOp, BaseShAmt, DAG);
14023 switch (VT.getSimpleVT().SimpleTy) {
14024 default: return SDValue();
14031 return getTargetVShiftNode(X86ISD::VSRLI, DL, VT, ValOp, BaseShAmt, DAG);
14037 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
14038 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
14039 // and friends. Likewise for OR -> CMPNEQSS.
14040 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
14041 TargetLowering::DAGCombinerInfo &DCI,
14042 const X86Subtarget *Subtarget) {
14045 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
14046 // we're requiring SSE2 for both.
14047 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
14048 SDValue N0 = N->getOperand(0);
14049 SDValue N1 = N->getOperand(1);
14050 SDValue CMP0 = N0->getOperand(1);
14051 SDValue CMP1 = N1->getOperand(1);
14052 DebugLoc DL = N->getDebugLoc();
14054 // The SETCCs should both refer to the same CMP.
14055 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
14058 SDValue CMP00 = CMP0->getOperand(0);
14059 SDValue CMP01 = CMP0->getOperand(1);
14060 EVT VT = CMP00.getValueType();
14062 if (VT == MVT::f32 || VT == MVT::f64) {
14063 bool ExpectingFlags = false;
14064 // Check for any users that want flags:
14065 for (SDNode::use_iterator UI = N->use_begin(),
14067 !ExpectingFlags && UI != UE; ++UI)
14068 switch (UI->getOpcode()) {
14073 ExpectingFlags = true;
14075 case ISD::CopyToReg:
14076 case ISD::SIGN_EXTEND:
14077 case ISD::ZERO_EXTEND:
14078 case ISD::ANY_EXTEND:
14082 if (!ExpectingFlags) {
14083 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
14084 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
14086 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
14087 X86::CondCode tmp = cc0;
14092 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
14093 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
14094 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
14095 X86ISD::NodeType NTOperator = is64BitFP ?
14096 X86ISD::FSETCCsd : X86ISD::FSETCCss;
14097 // FIXME: need symbolic constants for these magic numbers.
14098 // See X86ATTInstPrinter.cpp:printSSECC().
14099 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
14100 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01,
14101 DAG.getConstant(x86cc, MVT::i8));
14102 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32,
14104 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI,
14105 DAG.getConstant(1, MVT::i32));
14106 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
14107 return OneBitOfTruth;
14115 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
14116 /// so it can be folded inside ANDNP.
14117 static bool CanFoldXORWithAllOnes(const SDNode *N) {
14118 EVT VT = N->getValueType(0);
14120 // Match direct AllOnes for 128 and 256-bit vectors
14121 if (ISD::isBuildVectorAllOnes(N))
14124 // Look through a bit convert.
14125 if (N->getOpcode() == ISD::BITCAST)
14126 N = N->getOperand(0).getNode();
14128 // Sometimes the operand may come from a insert_subvector building a 256-bit
14130 if (VT.getSizeInBits() == 256 &&
14131 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
14132 SDValue V1 = N->getOperand(0);
14133 SDValue V2 = N->getOperand(1);
14135 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
14136 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
14137 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
14138 ISD::isBuildVectorAllOnes(V2.getNode()))
14145 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
14146 TargetLowering::DAGCombinerInfo &DCI,
14147 const X86Subtarget *Subtarget) {
14148 if (DCI.isBeforeLegalizeOps())
14151 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
14155 EVT VT = N->getValueType(0);
14157 // Create ANDN, BLSI, and BLSR instructions
14158 // BLSI is X & (-X)
14159 // BLSR is X & (X-1)
14160 if (Subtarget->hasBMI() && (VT == MVT::i32 || VT == MVT::i64)) {
14161 SDValue N0 = N->getOperand(0);
14162 SDValue N1 = N->getOperand(1);
14163 DebugLoc DL = N->getDebugLoc();
14165 // Check LHS for not
14166 if (N0.getOpcode() == ISD::XOR && isAllOnes(N0.getOperand(1)))
14167 return DAG.getNode(X86ISD::ANDN, DL, VT, N0.getOperand(0), N1);
14168 // Check RHS for not
14169 if (N1.getOpcode() == ISD::XOR && isAllOnes(N1.getOperand(1)))
14170 return DAG.getNode(X86ISD::ANDN, DL, VT, N1.getOperand(0), N0);
14172 // Check LHS for neg
14173 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1) == N1 &&
14174 isZero(N0.getOperand(0)))
14175 return DAG.getNode(X86ISD::BLSI, DL, VT, N1);
14177 // Check RHS for neg
14178 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1) == N0 &&
14179 isZero(N1.getOperand(0)))
14180 return DAG.getNode(X86ISD::BLSI, DL, VT, N0);
14182 // Check LHS for X-1
14183 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
14184 isAllOnes(N0.getOperand(1)))
14185 return DAG.getNode(X86ISD::BLSR, DL, VT, N1);
14187 // Check RHS for X-1
14188 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
14189 isAllOnes(N1.getOperand(1)))
14190 return DAG.getNode(X86ISD::BLSR, DL, VT, N0);
14195 // Want to form ANDNP nodes:
14196 // 1) In the hopes of then easily combining them with OR and AND nodes
14197 // to form PBLEND/PSIGN.
14198 // 2) To match ANDN packed intrinsics
14199 if (VT != MVT::v2i64 && VT != MVT::v4i64)
14202 SDValue N0 = N->getOperand(0);
14203 SDValue N1 = N->getOperand(1);
14204 DebugLoc DL = N->getDebugLoc();
14206 // Check LHS for vnot
14207 if (N0.getOpcode() == ISD::XOR &&
14208 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
14209 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
14210 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
14212 // Check RHS for vnot
14213 if (N1.getOpcode() == ISD::XOR &&
14214 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
14215 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
14216 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
14221 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
14222 TargetLowering::DAGCombinerInfo &DCI,
14223 const X86Subtarget *Subtarget) {
14224 if (DCI.isBeforeLegalizeOps())
14227 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
14231 EVT VT = N->getValueType(0);
14233 SDValue N0 = N->getOperand(0);
14234 SDValue N1 = N->getOperand(1);
14236 // look for psign/blend
14237 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
14238 if (!Subtarget->hasSSSE3() ||
14239 (VT == MVT::v4i64 && !Subtarget->hasAVX2()))
14242 // Canonicalize pandn to RHS
14243 if (N0.getOpcode() == X86ISD::ANDNP)
14245 // or (and (m, y), (pandn m, x))
14246 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
14247 SDValue Mask = N1.getOperand(0);
14248 SDValue X = N1.getOperand(1);
14250 if (N0.getOperand(0) == Mask)
14251 Y = N0.getOperand(1);
14252 if (N0.getOperand(1) == Mask)
14253 Y = N0.getOperand(0);
14255 // Check to see if the mask appeared in both the AND and ANDNP and
14259 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
14260 // Look through mask bitcast.
14261 if (Mask.getOpcode() == ISD::BITCAST)
14262 Mask = Mask.getOperand(0);
14263 if (X.getOpcode() == ISD::BITCAST)
14264 X = X.getOperand(0);
14265 if (Y.getOpcode() == ISD::BITCAST)
14266 Y = Y.getOperand(0);
14268 EVT MaskVT = Mask.getValueType();
14270 // Validate that the Mask operand is a vector sra node.
14271 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
14272 // there is no psrai.b
14273 if (Mask.getOpcode() != X86ISD::VSRAI)
14276 // Check that the SRA is all signbits.
14277 SDValue SraC = Mask.getOperand(1);
14278 unsigned SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
14279 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
14280 if ((SraAmt + 1) != EltBits)
14283 DebugLoc DL = N->getDebugLoc();
14285 // Now we know we at least have a plendvb with the mask val. See if
14286 // we can form a psignb/w/d.
14287 // psign = x.type == y.type == mask.type && y = sub(0, x);
14288 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
14289 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
14290 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
14291 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
14292 "Unsupported VT for PSIGN");
14293 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
14294 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
14296 // PBLENDVB only available on SSE 4.1
14297 if (!Subtarget->hasSSE41())
14300 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
14302 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
14303 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
14304 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
14305 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
14306 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
14310 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
14313 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
14314 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
14316 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
14318 if (!N0.hasOneUse() || !N1.hasOneUse())
14321 SDValue ShAmt0 = N0.getOperand(1);
14322 if (ShAmt0.getValueType() != MVT::i8)
14324 SDValue ShAmt1 = N1.getOperand(1);
14325 if (ShAmt1.getValueType() != MVT::i8)
14327 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
14328 ShAmt0 = ShAmt0.getOperand(0);
14329 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
14330 ShAmt1 = ShAmt1.getOperand(0);
14332 DebugLoc DL = N->getDebugLoc();
14333 unsigned Opc = X86ISD::SHLD;
14334 SDValue Op0 = N0.getOperand(0);
14335 SDValue Op1 = N1.getOperand(0);
14336 if (ShAmt0.getOpcode() == ISD::SUB) {
14337 Opc = X86ISD::SHRD;
14338 std::swap(Op0, Op1);
14339 std::swap(ShAmt0, ShAmt1);
14342 unsigned Bits = VT.getSizeInBits();
14343 if (ShAmt1.getOpcode() == ISD::SUB) {
14344 SDValue Sum = ShAmt1.getOperand(0);
14345 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
14346 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
14347 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
14348 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
14349 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
14350 return DAG.getNode(Opc, DL, VT,
14352 DAG.getNode(ISD::TRUNCATE, DL,
14355 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
14356 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
14358 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
14359 return DAG.getNode(Opc, DL, VT,
14360 N0.getOperand(0), N1.getOperand(0),
14361 DAG.getNode(ISD::TRUNCATE, DL,
14368 // Generate NEG and CMOV for integer abs.
14369 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
14370 EVT VT = N->getValueType(0);
14372 // Since X86 does not have CMOV for 8-bit integer, we don't convert
14373 // 8-bit integer abs to NEG and CMOV.
14374 if (VT.isInteger() && VT.getSizeInBits() == 8)
14377 SDValue N0 = N->getOperand(0);
14378 SDValue N1 = N->getOperand(1);
14379 DebugLoc DL = N->getDebugLoc();
14381 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
14382 // and change it to SUB and CMOV.
14383 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
14384 N0.getOpcode() == ISD::ADD &&
14385 N0.getOperand(1) == N1 &&
14386 N1.getOpcode() == ISD::SRA &&
14387 N1.getOperand(0) == N0.getOperand(0))
14388 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
14389 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
14390 // Generate SUB & CMOV.
14391 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
14392 DAG.getConstant(0, VT), N0.getOperand(0));
14394 SDValue Ops[] = { N0.getOperand(0), Neg,
14395 DAG.getConstant(X86::COND_GE, MVT::i8),
14396 SDValue(Neg.getNode(), 1) };
14397 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue),
14398 Ops, array_lengthof(Ops));
14403 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
14404 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
14405 TargetLowering::DAGCombinerInfo &DCI,
14406 const X86Subtarget *Subtarget) {
14407 if (DCI.isBeforeLegalizeOps())
14410 if (Subtarget->hasCMov()) {
14411 SDValue RV = performIntegerAbsCombine(N, DAG);
14416 // Try forming BMI if it is available.
14417 if (!Subtarget->hasBMI())
14420 EVT VT = N->getValueType(0);
14422 if (VT != MVT::i32 && VT != MVT::i64)
14425 assert(Subtarget->hasBMI() && "Creating BLSMSK requires BMI instructions");
14427 // Create BLSMSK instructions by finding X ^ (X-1)
14428 SDValue N0 = N->getOperand(0);
14429 SDValue N1 = N->getOperand(1);
14430 DebugLoc DL = N->getDebugLoc();
14432 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
14433 isAllOnes(N0.getOperand(1)))
14434 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N1);
14436 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
14437 isAllOnes(N1.getOperand(1)))
14438 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N0);
14443 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
14444 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
14445 const X86Subtarget *Subtarget) {
14446 LoadSDNode *Ld = cast<LoadSDNode>(N);
14447 EVT RegVT = Ld->getValueType(0);
14448 EVT MemVT = Ld->getMemoryVT();
14449 DebugLoc dl = Ld->getDebugLoc();
14450 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14452 ISD::LoadExtType Ext = Ld->getExtensionType();
14454 // If this is a vector EXT Load then attempt to optimize it using a
14455 // shuffle. We need SSE4 for the shuffles.
14456 // TODO: It is possible to support ZExt by zeroing the undef values
14457 // during the shuffle phase or after the shuffle.
14458 if (RegVT.isVector() && RegVT.isInteger() &&
14459 Ext == ISD::EXTLOAD && Subtarget->hasSSE41()) {
14460 assert(MemVT != RegVT && "Cannot extend to the same type");
14461 assert(MemVT.isVector() && "Must load a vector from memory");
14463 unsigned NumElems = RegVT.getVectorNumElements();
14464 unsigned RegSz = RegVT.getSizeInBits();
14465 unsigned MemSz = MemVT.getSizeInBits();
14466 assert(RegSz > MemSz && "Register size must be greater than the mem size");
14467 // All sizes must be a power of two
14468 if (!isPowerOf2_32(RegSz * MemSz * NumElems)) return SDValue();
14470 // Attempt to load the original value using a single load op.
14471 // Find a scalar type which is equal to the loaded word size.
14472 MVT SclrLoadTy = MVT::i8;
14473 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
14474 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
14475 MVT Tp = (MVT::SimpleValueType)tp;
14476 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() == MemSz) {
14482 // Proceed if a load word is found.
14483 if (SclrLoadTy.getSizeInBits() != MemSz) return SDValue();
14485 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy,
14486 RegSz/SclrLoadTy.getSizeInBits());
14488 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
14489 RegSz/MemVT.getScalarType().getSizeInBits());
14490 // Can't shuffle using an illegal type.
14491 if (!TLI.isTypeLegal(WideVecVT)) return SDValue();
14493 // Perform a single load.
14494 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(),
14496 Ld->getPointerInfo(), Ld->isVolatile(),
14497 Ld->isNonTemporal(), Ld->isInvariant(),
14498 Ld->getAlignment());
14500 // Insert the word loaded into a vector.
14501 SDValue ScalarInVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
14502 LoadUnitVecVT, ScalarLoad);
14504 // Bitcast the loaded value to a vector of the original element type, in
14505 // the size of the target vector type.
14506 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT,
14508 unsigned SizeRatio = RegSz/MemSz;
14510 // Redistribute the loaded elements into the different locations.
14511 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
14512 for (unsigned i = 0; i != NumElems; ++i)
14513 ShuffleVec[i*SizeRatio] = i;
14515 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
14516 DAG.getUNDEF(WideVecVT),
14519 // Bitcast to the requested type.
14520 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
14521 // Replace the original load with the new sequence
14522 // and return the new chain.
14523 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Shuff);
14524 return SDValue(ScalarLoad.getNode(), 1);
14530 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
14531 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
14532 const X86Subtarget *Subtarget) {
14533 StoreSDNode *St = cast<StoreSDNode>(N);
14534 EVT VT = St->getValue().getValueType();
14535 EVT StVT = St->getMemoryVT();
14536 DebugLoc dl = St->getDebugLoc();
14537 SDValue StoredVal = St->getOperand(1);
14538 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14540 // If we are saving a concatenation of two XMM registers, perform two stores.
14541 // On Sandy Bridge, 256-bit memory operations are executed by two
14542 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit
14543 // memory operation.
14544 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2() &&
14545 StoredVal.getNode()->getOpcode() == ISD::CONCAT_VECTORS &&
14546 StoredVal.getNumOperands() == 2) {
14547 SDValue Value0 = StoredVal.getOperand(0);
14548 SDValue Value1 = StoredVal.getOperand(1);
14550 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
14551 SDValue Ptr0 = St->getBasePtr();
14552 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
14554 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
14555 St->getPointerInfo(), St->isVolatile(),
14556 St->isNonTemporal(), St->getAlignment());
14557 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
14558 St->getPointerInfo(), St->isVolatile(),
14559 St->isNonTemporal(), St->getAlignment());
14560 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
14563 // Optimize trunc store (of multiple scalars) to shuffle and store.
14564 // First, pack all of the elements in one place. Next, store to memory
14565 // in fewer chunks.
14566 if (St->isTruncatingStore() && VT.isVector()) {
14567 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14568 unsigned NumElems = VT.getVectorNumElements();
14569 assert(StVT != VT && "Cannot truncate to the same type");
14570 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
14571 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
14573 // From, To sizes and ElemCount must be pow of two
14574 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
14575 // We are going to use the original vector elt for storing.
14576 // Accumulated smaller vector elements must be a multiple of the store size.
14577 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
14579 unsigned SizeRatio = FromSz / ToSz;
14581 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
14583 // Create a type on which we perform the shuffle
14584 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
14585 StVT.getScalarType(), NumElems*SizeRatio);
14587 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
14589 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
14590 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
14591 for (unsigned i = 0; i != NumElems; ++i)
14592 ShuffleVec[i] = i * SizeRatio;
14594 // Can't shuffle using an illegal type
14595 if (!TLI.isTypeLegal(WideVecVT)) return SDValue();
14597 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
14598 DAG.getUNDEF(WideVecVT),
14600 // At this point all of the data is stored at the bottom of the
14601 // register. We now need to save it to mem.
14603 // Find the largest store unit
14604 MVT StoreType = MVT::i8;
14605 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
14606 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
14607 MVT Tp = (MVT::SimpleValueType)tp;
14608 if (TLI.isTypeLegal(Tp) && StoreType.getSizeInBits() < NumElems * ToSz)
14612 // Bitcast the original vector into a vector of store-size units
14613 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
14614 StoreType, VT.getSizeInBits()/EVT(StoreType).getSizeInBits());
14615 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
14616 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
14617 SmallVector<SDValue, 8> Chains;
14618 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
14619 TLI.getPointerTy());
14620 SDValue Ptr = St->getBasePtr();
14622 // Perform one or more big stores into memory.
14623 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
14624 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
14625 StoreType, ShuffWide,
14626 DAG.getIntPtrConstant(i));
14627 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
14628 St->getPointerInfo(), St->isVolatile(),
14629 St->isNonTemporal(), St->getAlignment());
14630 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
14631 Chains.push_back(Ch);
14634 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
14639 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
14640 // the FP state in cases where an emms may be missing.
14641 // A preferable solution to the general problem is to figure out the right
14642 // places to insert EMMS. This qualifies as a quick hack.
14644 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
14645 if (VT.getSizeInBits() != 64)
14648 const Function *F = DAG.getMachineFunction().getFunction();
14649 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
14650 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
14651 && Subtarget->hasSSE2();
14652 if ((VT.isVector() ||
14653 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
14654 isa<LoadSDNode>(St->getValue()) &&
14655 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
14656 St->getChain().hasOneUse() && !St->isVolatile()) {
14657 SDNode* LdVal = St->getValue().getNode();
14658 LoadSDNode *Ld = 0;
14659 int TokenFactorIndex = -1;
14660 SmallVector<SDValue, 8> Ops;
14661 SDNode* ChainVal = St->getChain().getNode();
14662 // Must be a store of a load. We currently handle two cases: the load
14663 // is a direct child, and it's under an intervening TokenFactor. It is
14664 // possible to dig deeper under nested TokenFactors.
14665 if (ChainVal == LdVal)
14666 Ld = cast<LoadSDNode>(St->getChain());
14667 else if (St->getValue().hasOneUse() &&
14668 ChainVal->getOpcode() == ISD::TokenFactor) {
14669 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
14670 if (ChainVal->getOperand(i).getNode() == LdVal) {
14671 TokenFactorIndex = i;
14672 Ld = cast<LoadSDNode>(St->getValue());
14674 Ops.push_back(ChainVal->getOperand(i));
14678 if (!Ld || !ISD::isNormalLoad(Ld))
14681 // If this is not the MMX case, i.e. we are just turning i64 load/store
14682 // into f64 load/store, avoid the transformation if there are multiple
14683 // uses of the loaded value.
14684 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
14687 DebugLoc LdDL = Ld->getDebugLoc();
14688 DebugLoc StDL = N->getDebugLoc();
14689 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
14690 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
14692 if (Subtarget->is64Bit() || F64IsLegal) {
14693 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
14694 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
14695 Ld->getPointerInfo(), Ld->isVolatile(),
14696 Ld->isNonTemporal(), Ld->isInvariant(),
14697 Ld->getAlignment());
14698 SDValue NewChain = NewLd.getValue(1);
14699 if (TokenFactorIndex != -1) {
14700 Ops.push_back(NewChain);
14701 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
14704 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
14705 St->getPointerInfo(),
14706 St->isVolatile(), St->isNonTemporal(),
14707 St->getAlignment());
14710 // Otherwise, lower to two pairs of 32-bit loads / stores.
14711 SDValue LoAddr = Ld->getBasePtr();
14712 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
14713 DAG.getConstant(4, MVT::i32));
14715 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
14716 Ld->getPointerInfo(),
14717 Ld->isVolatile(), Ld->isNonTemporal(),
14718 Ld->isInvariant(), Ld->getAlignment());
14719 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
14720 Ld->getPointerInfo().getWithOffset(4),
14721 Ld->isVolatile(), Ld->isNonTemporal(),
14723 MinAlign(Ld->getAlignment(), 4));
14725 SDValue NewChain = LoLd.getValue(1);
14726 if (TokenFactorIndex != -1) {
14727 Ops.push_back(LoLd);
14728 Ops.push_back(HiLd);
14729 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
14733 LoAddr = St->getBasePtr();
14734 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
14735 DAG.getConstant(4, MVT::i32));
14737 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
14738 St->getPointerInfo(),
14739 St->isVolatile(), St->isNonTemporal(),
14740 St->getAlignment());
14741 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
14742 St->getPointerInfo().getWithOffset(4),
14744 St->isNonTemporal(),
14745 MinAlign(St->getAlignment(), 4));
14746 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
14751 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
14752 /// and return the operands for the horizontal operation in LHS and RHS. A
14753 /// horizontal operation performs the binary operation on successive elements
14754 /// of its first operand, then on successive elements of its second operand,
14755 /// returning the resulting values in a vector. For example, if
14756 /// A = < float a0, float a1, float a2, float a3 >
14758 /// B = < float b0, float b1, float b2, float b3 >
14759 /// then the result of doing a horizontal operation on A and B is
14760 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
14761 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
14762 /// A horizontal-op B, for some already available A and B, and if so then LHS is
14763 /// set to A, RHS to B, and the routine returns 'true'.
14764 /// Note that the binary operation should have the property that if one of the
14765 /// operands is UNDEF then the result is UNDEF.
14766 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
14767 // Look for the following pattern: if
14768 // A = < float a0, float a1, float a2, float a3 >
14769 // B = < float b0, float b1, float b2, float b3 >
14771 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
14772 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
14773 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
14774 // which is A horizontal-op B.
14776 // At least one of the operands should be a vector shuffle.
14777 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
14778 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
14781 EVT VT = LHS.getValueType();
14783 assert((VT.is128BitVector() || VT.is256BitVector()) &&
14784 "Unsupported vector type for horizontal add/sub");
14786 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
14787 // operate independently on 128-bit lanes.
14788 unsigned NumElts = VT.getVectorNumElements();
14789 unsigned NumLanes = VT.getSizeInBits()/128;
14790 unsigned NumLaneElts = NumElts / NumLanes;
14791 assert((NumLaneElts % 2 == 0) &&
14792 "Vector type should have an even number of elements in each lane");
14793 unsigned HalfLaneElts = NumLaneElts/2;
14795 // View LHS in the form
14796 // LHS = VECTOR_SHUFFLE A, B, LMask
14797 // If LHS is not a shuffle then pretend it is the shuffle
14798 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
14799 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
14802 SmallVector<int, 16> LMask(NumElts);
14803 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
14804 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
14805 A = LHS.getOperand(0);
14806 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
14807 B = LHS.getOperand(1);
14808 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
14809 std::copy(Mask.begin(), Mask.end(), LMask.begin());
14811 if (LHS.getOpcode() != ISD::UNDEF)
14813 for (unsigned i = 0; i != NumElts; ++i)
14817 // Likewise, view RHS in the form
14818 // RHS = VECTOR_SHUFFLE C, D, RMask
14820 SmallVector<int, 16> RMask(NumElts);
14821 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
14822 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
14823 C = RHS.getOperand(0);
14824 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
14825 D = RHS.getOperand(1);
14826 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
14827 std::copy(Mask.begin(), Mask.end(), RMask.begin());
14829 if (RHS.getOpcode() != ISD::UNDEF)
14831 for (unsigned i = 0; i != NumElts; ++i)
14835 // Check that the shuffles are both shuffling the same vectors.
14836 if (!(A == C && B == D) && !(A == D && B == C))
14839 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
14840 if (!A.getNode() && !B.getNode())
14843 // If A and B occur in reverse order in RHS, then "swap" them (which means
14844 // rewriting the mask).
14846 CommuteVectorShuffleMask(RMask, NumElts);
14848 // At this point LHS and RHS are equivalent to
14849 // LHS = VECTOR_SHUFFLE A, B, LMask
14850 // RHS = VECTOR_SHUFFLE A, B, RMask
14851 // Check that the masks correspond to performing a horizontal operation.
14852 for (unsigned i = 0; i != NumElts; ++i) {
14853 int LIdx = LMask[i], RIdx = RMask[i];
14855 // Ignore any UNDEF components.
14856 if (LIdx < 0 || RIdx < 0 ||
14857 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
14858 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
14861 // Check that successive elements are being operated on. If not, this is
14862 // not a horizontal operation.
14863 unsigned Src = (i/HalfLaneElts) % 2; // each lane is split between srcs
14864 unsigned LaneStart = (i/NumLaneElts) * NumLaneElts;
14865 int Index = 2*(i%HalfLaneElts) + NumElts*Src + LaneStart;
14866 if (!(LIdx == Index && RIdx == Index + 1) &&
14867 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
14871 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
14872 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
14876 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
14877 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
14878 const X86Subtarget *Subtarget) {
14879 EVT VT = N->getValueType(0);
14880 SDValue LHS = N->getOperand(0);
14881 SDValue RHS = N->getOperand(1);
14883 // Try to synthesize horizontal adds from adds of shuffles.
14884 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
14885 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
14886 isHorizontalBinOp(LHS, RHS, true))
14887 return DAG.getNode(X86ISD::FHADD, N->getDebugLoc(), VT, LHS, RHS);
14891 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
14892 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
14893 const X86Subtarget *Subtarget) {
14894 EVT VT = N->getValueType(0);
14895 SDValue LHS = N->getOperand(0);
14896 SDValue RHS = N->getOperand(1);
14898 // Try to synthesize horizontal subs from subs of shuffles.
14899 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
14900 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
14901 isHorizontalBinOp(LHS, RHS, false))
14902 return DAG.getNode(X86ISD::FHSUB, N->getDebugLoc(), VT, LHS, RHS);
14906 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
14907 /// X86ISD::FXOR nodes.
14908 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
14909 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
14910 // F[X]OR(0.0, x) -> x
14911 // F[X]OR(x, 0.0) -> x
14912 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
14913 if (C->getValueAPF().isPosZero())
14914 return N->getOperand(1);
14915 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
14916 if (C->getValueAPF().isPosZero())
14917 return N->getOperand(0);
14921 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
14922 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
14923 // FAND(0.0, x) -> 0.0
14924 // FAND(x, 0.0) -> 0.0
14925 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
14926 if (C->getValueAPF().isPosZero())
14927 return N->getOperand(0);
14928 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
14929 if (C->getValueAPF().isPosZero())
14930 return N->getOperand(1);
14934 static SDValue PerformBTCombine(SDNode *N,
14936 TargetLowering::DAGCombinerInfo &DCI) {
14937 // BT ignores high bits in the bit index operand.
14938 SDValue Op1 = N->getOperand(1);
14939 if (Op1.hasOneUse()) {
14940 unsigned BitWidth = Op1.getValueSizeInBits();
14941 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
14942 APInt KnownZero, KnownOne;
14943 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
14944 !DCI.isBeforeLegalizeOps());
14945 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14946 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
14947 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
14948 DCI.CommitTargetLoweringOpt(TLO);
14953 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
14954 SDValue Op = N->getOperand(0);
14955 if (Op.getOpcode() == ISD::BITCAST)
14956 Op = Op.getOperand(0);
14957 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
14958 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
14959 VT.getVectorElementType().getSizeInBits() ==
14960 OpVT.getVectorElementType().getSizeInBits()) {
14961 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op);
14966 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
14967 TargetLowering::DAGCombinerInfo &DCI,
14968 const X86Subtarget *Subtarget) {
14969 if (!DCI.isBeforeLegalizeOps())
14972 if (!Subtarget->hasAVX())
14975 EVT VT = N->getValueType(0);
14976 SDValue Op = N->getOperand(0);
14977 EVT OpVT = Op.getValueType();
14978 DebugLoc dl = N->getDebugLoc();
14980 if ((VT == MVT::v4i64 && OpVT == MVT::v4i32) ||
14981 (VT == MVT::v8i32 && OpVT == MVT::v8i16)) {
14983 if (Subtarget->hasAVX2())
14984 return DAG.getNode(X86ISD::VSEXT_MOVL, dl, VT, Op);
14986 // Optimize vectors in AVX mode
14987 // Sign extend v8i16 to v8i32 and
14990 // Divide input vector into two parts
14991 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
14992 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
14993 // concat the vectors to original VT
14995 unsigned NumElems = OpVT.getVectorNumElements();
14996 SmallVector<int,8> ShufMask1(NumElems, -1);
14997 for (unsigned i = 0; i != NumElems/2; ++i)
15000 SDValue OpLo = DAG.getVectorShuffle(OpVT, dl, Op, DAG.getUNDEF(OpVT),
15003 SmallVector<int,8> ShufMask2(NumElems, -1);
15004 for (unsigned i = 0; i != NumElems/2; ++i)
15005 ShufMask2[i] = i + NumElems/2;
15007 SDValue OpHi = DAG.getVectorShuffle(OpVT, dl, Op, DAG.getUNDEF(OpVT),
15010 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), VT.getScalarType(),
15011 VT.getVectorNumElements()/2);
15013 OpLo = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpLo);
15014 OpHi = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpHi);
15016 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
15021 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
15022 TargetLowering::DAGCombinerInfo &DCI,
15023 const X86Subtarget *Subtarget) {
15024 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
15025 // (and (i32 x86isd::setcc_carry), 1)
15026 // This eliminates the zext. This transformation is necessary because
15027 // ISD::SETCC is always legalized to i8.
15028 DebugLoc dl = N->getDebugLoc();
15029 SDValue N0 = N->getOperand(0);
15030 EVT VT = N->getValueType(0);
15031 EVT OpVT = N0.getValueType();
15033 if (N0.getOpcode() == ISD::AND &&
15035 N0.getOperand(0).hasOneUse()) {
15036 SDValue N00 = N0.getOperand(0);
15037 if (N00.getOpcode() != X86ISD::SETCC_CARRY)
15039 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
15040 if (!C || C->getZExtValue() != 1)
15042 return DAG.getNode(ISD::AND, dl, VT,
15043 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
15044 N00.getOperand(0), N00.getOperand(1)),
15045 DAG.getConstant(1, VT));
15048 // Optimize vectors in AVX mode:
15051 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
15052 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
15053 // Concat upper and lower parts.
15056 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
15057 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
15058 // Concat upper and lower parts.
15060 if (!DCI.isBeforeLegalizeOps())
15063 if (!Subtarget->hasAVX())
15066 if (((VT == MVT::v8i32) && (OpVT == MVT::v8i16)) ||
15067 ((VT == MVT::v4i64) && (OpVT == MVT::v4i32))) {
15069 if (Subtarget->hasAVX2())
15070 return DAG.getNode(X86ISD::VZEXT_MOVL, dl, VT, N0);
15072 SDValue ZeroVec = getZeroVector(OpVT, Subtarget, DAG, dl);
15073 SDValue OpLo = getUnpackl(DAG, dl, OpVT, N0, ZeroVec);
15074 SDValue OpHi = getUnpackh(DAG, dl, OpVT, N0, ZeroVec);
15076 EVT HVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
15077 VT.getVectorNumElements()/2);
15079 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
15080 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
15082 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
15088 // Optimize x == -y --> x+y == 0
15089 // x != -y --> x+y != 0
15090 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG) {
15091 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
15092 SDValue LHS = N->getOperand(0);
15093 SDValue RHS = N->getOperand(1);
15095 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
15096 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
15097 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
15098 SDValue addV = DAG.getNode(ISD::ADD, N->getDebugLoc(),
15099 LHS.getValueType(), RHS, LHS.getOperand(1));
15100 return DAG.getSetCC(N->getDebugLoc(), N->getValueType(0),
15101 addV, DAG.getConstant(0, addV.getValueType()), CC);
15103 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
15104 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
15105 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
15106 SDValue addV = DAG.getNode(ISD::ADD, N->getDebugLoc(),
15107 RHS.getValueType(), LHS, RHS.getOperand(1));
15108 return DAG.getSetCC(N->getDebugLoc(), N->getValueType(0),
15109 addV, DAG.getConstant(0, addV.getValueType()), CC);
15114 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
15115 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG) {
15116 unsigned X86CC = N->getConstantOperandVal(0);
15117 SDValue EFLAG = N->getOperand(1);
15118 DebugLoc DL = N->getDebugLoc();
15120 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
15121 // a zext and produces an all-ones bit which is more useful than 0/1 in some
15123 if (X86CC == X86::COND_B)
15124 return DAG.getNode(ISD::AND, DL, MVT::i8,
15125 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
15126 DAG.getConstant(X86CC, MVT::i8), EFLAG),
15127 DAG.getConstant(1, MVT::i8));
15132 static SDValue PerformUINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG) {
15133 SDValue Op0 = N->getOperand(0);
15134 EVT InVT = Op0->getValueType(0);
15136 // UINT_TO_FP(v4i8) -> SINT_TO_FP(ZEXT(v4i8 to v4i32))
15137 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
15138 DebugLoc dl = N->getDebugLoc();
15139 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
15140 SDValue P = DAG.getNode(ISD::ZERO_EXTEND, dl, DstVT, Op0);
15141 // Notice that we use SINT_TO_FP because we know that the high bits
15142 // are zero and SINT_TO_FP is better supported by the hardware.
15143 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
15149 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
15150 const X86TargetLowering *XTLI) {
15151 SDValue Op0 = N->getOperand(0);
15152 EVT InVT = Op0->getValueType(0);
15154 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
15155 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
15156 DebugLoc dl = N->getDebugLoc();
15157 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
15158 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
15159 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
15162 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
15163 // a 32-bit target where SSE doesn't support i64->FP operations.
15164 if (Op0.getOpcode() == ISD::LOAD) {
15165 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
15166 EVT VT = Ld->getValueType(0);
15167 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
15168 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
15169 !XTLI->getSubtarget()->is64Bit() &&
15170 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
15171 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
15172 Ld->getChain(), Op0, DAG);
15173 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
15180 static SDValue PerformFP_TO_SINTCombine(SDNode *N, SelectionDAG &DAG) {
15181 EVT VT = N->getValueType(0);
15183 // v4i8 = FP_TO_SINT() -> v4i8 = TRUNCATE (V4i32 = FP_TO_SINT()
15184 if (VT == MVT::v8i8 || VT == MVT::v4i8) {
15185 DebugLoc dl = N->getDebugLoc();
15186 MVT DstVT = VT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
15187 SDValue I = DAG.getNode(ISD::FP_TO_SINT, dl, DstVT, N->getOperand(0));
15188 return DAG.getNode(ISD::TRUNCATE, dl, VT, I);
15194 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
15195 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
15196 X86TargetLowering::DAGCombinerInfo &DCI) {
15197 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
15198 // the result is either zero or one (depending on the input carry bit).
15199 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
15200 if (X86::isZeroNode(N->getOperand(0)) &&
15201 X86::isZeroNode(N->getOperand(1)) &&
15202 // We don't have a good way to replace an EFLAGS use, so only do this when
15204 SDValue(N, 1).use_empty()) {
15205 DebugLoc DL = N->getDebugLoc();
15206 EVT VT = N->getValueType(0);
15207 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
15208 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
15209 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
15210 DAG.getConstant(X86::COND_B,MVT::i8),
15212 DAG.getConstant(1, VT));
15213 return DCI.CombineTo(N, Res1, CarryOut);
15219 // fold (add Y, (sete X, 0)) -> adc 0, Y
15220 // (add Y, (setne X, 0)) -> sbb -1, Y
15221 // (sub (sete X, 0), Y) -> sbb 0, Y
15222 // (sub (setne X, 0), Y) -> adc -1, Y
15223 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
15224 DebugLoc DL = N->getDebugLoc();
15226 // Look through ZExts.
15227 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
15228 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
15231 SDValue SetCC = Ext.getOperand(0);
15232 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
15235 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
15236 if (CC != X86::COND_E && CC != X86::COND_NE)
15239 SDValue Cmp = SetCC.getOperand(1);
15240 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
15241 !X86::isZeroNode(Cmp.getOperand(1)) ||
15242 !Cmp.getOperand(0).getValueType().isInteger())
15245 SDValue CmpOp0 = Cmp.getOperand(0);
15246 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
15247 DAG.getConstant(1, CmpOp0.getValueType()));
15249 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
15250 if (CC == X86::COND_NE)
15251 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
15252 DL, OtherVal.getValueType(), OtherVal,
15253 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
15254 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
15255 DL, OtherVal.getValueType(), OtherVal,
15256 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
15259 /// PerformADDCombine - Do target-specific dag combines on integer adds.
15260 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
15261 const X86Subtarget *Subtarget) {
15262 EVT VT = N->getValueType(0);
15263 SDValue Op0 = N->getOperand(0);
15264 SDValue Op1 = N->getOperand(1);
15266 // Try to synthesize horizontal adds from adds of shuffles.
15267 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
15268 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
15269 isHorizontalBinOp(Op0, Op1, true))
15270 return DAG.getNode(X86ISD::HADD, N->getDebugLoc(), VT, Op0, Op1);
15272 return OptimizeConditionalInDecrement(N, DAG);
15275 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
15276 const X86Subtarget *Subtarget) {
15277 SDValue Op0 = N->getOperand(0);
15278 SDValue Op1 = N->getOperand(1);
15280 // X86 can't encode an immediate LHS of a sub. See if we can push the
15281 // negation into a preceding instruction.
15282 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
15283 // If the RHS of the sub is a XOR with one use and a constant, invert the
15284 // immediate. Then add one to the LHS of the sub so we can turn
15285 // X-Y -> X+~Y+1, saving one register.
15286 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
15287 isa<ConstantSDNode>(Op1.getOperand(1))) {
15288 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
15289 EVT VT = Op0.getValueType();
15290 SDValue NewXor = DAG.getNode(ISD::XOR, Op1.getDebugLoc(), VT,
15292 DAG.getConstant(~XorC, VT));
15293 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, NewXor,
15294 DAG.getConstant(C->getAPIntValue()+1, VT));
15298 // Try to synthesize horizontal adds from adds of shuffles.
15299 EVT VT = N->getValueType(0);
15300 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
15301 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
15302 isHorizontalBinOp(Op0, Op1, true))
15303 return DAG.getNode(X86ISD::HSUB, N->getDebugLoc(), VT, Op0, Op1);
15305 return OptimizeConditionalInDecrement(N, DAG);
15308 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
15309 DAGCombinerInfo &DCI) const {
15310 SelectionDAG &DAG = DCI.DAG;
15311 switch (N->getOpcode()) {
15313 case ISD::EXTRACT_VECTOR_ELT:
15314 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
15316 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
15317 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);
15318 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
15319 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
15320 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
15321 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
15324 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
15325 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
15326 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
15327 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
15328 case ISD::LOAD: return PerformLOADCombine(N, DAG, Subtarget);
15329 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
15330 case ISD::UINT_TO_FP: return PerformUINT_TO_FPCombine(N, DAG);
15331 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
15332 case ISD::FP_TO_SINT: return PerformFP_TO_SINTCombine(N, DAG);
15333 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
15334 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
15336 case X86ISD::FOR: return PerformFORCombine(N, DAG);
15337 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
15338 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
15339 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
15340 case ISD::ANY_EXTEND:
15341 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
15342 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
15343 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG, DCI);
15344 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG);
15345 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG);
15346 case X86ISD::SHUFP: // Handle all target specific shuffles
15347 case X86ISD::PALIGN:
15348 case X86ISD::UNPCKH:
15349 case X86ISD::UNPCKL:
15350 case X86ISD::MOVHLPS:
15351 case X86ISD::MOVLHPS:
15352 case X86ISD::PSHUFD:
15353 case X86ISD::PSHUFHW:
15354 case X86ISD::PSHUFLW:
15355 case X86ISD::MOVSS:
15356 case X86ISD::MOVSD:
15357 case X86ISD::VPERMILP:
15358 case X86ISD::VPERM2X128:
15359 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
15365 /// isTypeDesirableForOp - Return true if the target has native support for
15366 /// the specified value type and it is 'desirable' to use the type for the
15367 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
15368 /// instruction encodings are longer and some i16 instructions are slow.
15369 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
15370 if (!isTypeLegal(VT))
15372 if (VT != MVT::i16)
15379 case ISD::SIGN_EXTEND:
15380 case ISD::ZERO_EXTEND:
15381 case ISD::ANY_EXTEND:
15394 /// IsDesirableToPromoteOp - This method query the target whether it is
15395 /// beneficial for dag combiner to promote the specified node. If true, it
15396 /// should return the desired promotion type by reference.
15397 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
15398 EVT VT = Op.getValueType();
15399 if (VT != MVT::i16)
15402 bool Promote = false;
15403 bool Commute = false;
15404 switch (Op.getOpcode()) {
15407 LoadSDNode *LD = cast<LoadSDNode>(Op);
15408 // If the non-extending load has a single use and it's not live out, then it
15409 // might be folded.
15410 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
15411 Op.hasOneUse()*/) {
15412 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
15413 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
15414 // The only case where we'd want to promote LOAD (rather then it being
15415 // promoted as an operand is when it's only use is liveout.
15416 if (UI->getOpcode() != ISD::CopyToReg)
15423 case ISD::SIGN_EXTEND:
15424 case ISD::ZERO_EXTEND:
15425 case ISD::ANY_EXTEND:
15430 SDValue N0 = Op.getOperand(0);
15431 // Look out for (store (shl (load), x)).
15432 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
15445 SDValue N0 = Op.getOperand(0);
15446 SDValue N1 = Op.getOperand(1);
15447 if (!Commute && MayFoldLoad(N1))
15449 // Avoid disabling potential load folding opportunities.
15450 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
15452 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
15462 //===----------------------------------------------------------------------===//
15463 // X86 Inline Assembly Support
15464 //===----------------------------------------------------------------------===//
15467 // Helper to match a string separated by whitespace.
15468 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
15469 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
15471 for (unsigned i = 0, e = args.size(); i != e; ++i) {
15472 StringRef piece(*args[i]);
15473 if (!s.startswith(piece)) // Check if the piece matches.
15476 s = s.substr(piece.size());
15477 StringRef::size_type pos = s.find_first_not_of(" \t");
15478 if (pos == 0) // We matched a prefix.
15486 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
15489 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
15490 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
15492 std::string AsmStr = IA->getAsmString();
15494 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
15495 if (!Ty || Ty->getBitWidth() % 16 != 0)
15498 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
15499 SmallVector<StringRef, 4> AsmPieces;
15500 SplitString(AsmStr, AsmPieces, ";\n");
15502 switch (AsmPieces.size()) {
15503 default: return false;
15505 // FIXME: this should verify that we are targeting a 486 or better. If not,
15506 // we will turn this bswap into something that will be lowered to logical
15507 // ops instead of emitting the bswap asm. For now, we don't support 486 or
15508 // lower so don't worry about this.
15510 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
15511 matchAsm(AsmPieces[0], "bswapl", "$0") ||
15512 matchAsm(AsmPieces[0], "bswapq", "$0") ||
15513 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
15514 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
15515 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
15516 // No need to check constraints, nothing other than the equivalent of
15517 // "=r,0" would be valid here.
15518 return IntrinsicLowering::LowerToByteSwap(CI);
15521 // rorw $$8, ${0:w} --> llvm.bswap.i16
15522 if (CI->getType()->isIntegerTy(16) &&
15523 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
15524 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
15525 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
15527 const std::string &ConstraintsStr = IA->getConstraintString();
15528 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
15529 std::sort(AsmPieces.begin(), AsmPieces.end());
15530 if (AsmPieces.size() == 4 &&
15531 AsmPieces[0] == "~{cc}" &&
15532 AsmPieces[1] == "~{dirflag}" &&
15533 AsmPieces[2] == "~{flags}" &&
15534 AsmPieces[3] == "~{fpsr}")
15535 return IntrinsicLowering::LowerToByteSwap(CI);
15539 if (CI->getType()->isIntegerTy(32) &&
15540 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
15541 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
15542 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
15543 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
15545 const std::string &ConstraintsStr = IA->getConstraintString();
15546 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
15547 std::sort(AsmPieces.begin(), AsmPieces.end());
15548 if (AsmPieces.size() == 4 &&
15549 AsmPieces[0] == "~{cc}" &&
15550 AsmPieces[1] == "~{dirflag}" &&
15551 AsmPieces[2] == "~{flags}" &&
15552 AsmPieces[3] == "~{fpsr}")
15553 return IntrinsicLowering::LowerToByteSwap(CI);
15556 if (CI->getType()->isIntegerTy(64)) {
15557 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
15558 if (Constraints.size() >= 2 &&
15559 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
15560 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
15561 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
15562 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
15563 matchAsm(AsmPieces[1], "bswap", "%edx") &&
15564 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
15565 return IntrinsicLowering::LowerToByteSwap(CI);
15575 /// getConstraintType - Given a constraint letter, return the type of
15576 /// constraint it is for this target.
15577 X86TargetLowering::ConstraintType
15578 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
15579 if (Constraint.size() == 1) {
15580 switch (Constraint[0]) {
15591 return C_RegisterClass;
15615 return TargetLowering::getConstraintType(Constraint);
15618 /// Examine constraint type and operand type and determine a weight value.
15619 /// This object must already have been set up with the operand type
15620 /// and the current alternative constraint selected.
15621 TargetLowering::ConstraintWeight
15622 X86TargetLowering::getSingleConstraintMatchWeight(
15623 AsmOperandInfo &info, const char *constraint) const {
15624 ConstraintWeight weight = CW_Invalid;
15625 Value *CallOperandVal = info.CallOperandVal;
15626 // If we don't have a value, we can't do a match,
15627 // but allow it at the lowest weight.
15628 if (CallOperandVal == NULL)
15630 Type *type = CallOperandVal->getType();
15631 // Look at the constraint type.
15632 switch (*constraint) {
15634 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
15645 if (CallOperandVal->getType()->isIntegerTy())
15646 weight = CW_SpecificReg;
15651 if (type->isFloatingPointTy())
15652 weight = CW_SpecificReg;
15655 if (type->isX86_MMXTy() && Subtarget->hasMMX())
15656 weight = CW_SpecificReg;
15660 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
15661 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasAVX()))
15662 weight = CW_Register;
15665 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
15666 if (C->getZExtValue() <= 31)
15667 weight = CW_Constant;
15671 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15672 if (C->getZExtValue() <= 63)
15673 weight = CW_Constant;
15677 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15678 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
15679 weight = CW_Constant;
15683 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15684 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
15685 weight = CW_Constant;
15689 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15690 if (C->getZExtValue() <= 3)
15691 weight = CW_Constant;
15695 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15696 if (C->getZExtValue() <= 0xff)
15697 weight = CW_Constant;
15702 if (dyn_cast<ConstantFP>(CallOperandVal)) {
15703 weight = CW_Constant;
15707 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15708 if ((C->getSExtValue() >= -0x80000000LL) &&
15709 (C->getSExtValue() <= 0x7fffffffLL))
15710 weight = CW_Constant;
15714 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15715 if (C->getZExtValue() <= 0xffffffff)
15716 weight = CW_Constant;
15723 /// LowerXConstraint - try to replace an X constraint, which matches anything,
15724 /// with another that has more specific requirements based on the type of the
15725 /// corresponding operand.
15726 const char *X86TargetLowering::
15727 LowerXConstraint(EVT ConstraintVT) const {
15728 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
15729 // 'f' like normal targets.
15730 if (ConstraintVT.isFloatingPoint()) {
15731 if (Subtarget->hasSSE2())
15733 if (Subtarget->hasSSE1())
15737 return TargetLowering::LowerXConstraint(ConstraintVT);
15740 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
15741 /// vector. If it is invalid, don't add anything to Ops.
15742 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
15743 std::string &Constraint,
15744 std::vector<SDValue>&Ops,
15745 SelectionDAG &DAG) const {
15746 SDValue Result(0, 0);
15748 // Only support length 1 constraints for now.
15749 if (Constraint.length() > 1) return;
15751 char ConstraintLetter = Constraint[0];
15752 switch (ConstraintLetter) {
15755 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15756 if (C->getZExtValue() <= 31) {
15757 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15763 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15764 if (C->getZExtValue() <= 63) {
15765 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15771 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15772 if ((int8_t)C->getSExtValue() == C->getSExtValue()) {
15773 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15779 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15780 if (C->getZExtValue() <= 255) {
15781 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15787 // 32-bit signed value
15788 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15789 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
15790 C->getSExtValue())) {
15791 // Widen to 64 bits here to get it sign extended.
15792 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
15795 // FIXME gcc accepts some relocatable values here too, but only in certain
15796 // memory models; it's complicated.
15801 // 32-bit unsigned value
15802 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15803 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
15804 C->getZExtValue())) {
15805 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15809 // FIXME gcc accepts some relocatable values here too, but only in certain
15810 // memory models; it's complicated.
15814 // Literal immediates are always ok.
15815 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
15816 // Widen to 64 bits here to get it sign extended.
15817 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
15821 // In any sort of PIC mode addresses need to be computed at runtime by
15822 // adding in a register or some sort of table lookup. These can't
15823 // be used as immediates.
15824 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
15827 // If we are in non-pic codegen mode, we allow the address of a global (with
15828 // an optional displacement) to be used with 'i'.
15829 GlobalAddressSDNode *GA = 0;
15830 int64_t Offset = 0;
15832 // Match either (GA), (GA+C), (GA+C1+C2), etc.
15834 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
15835 Offset += GA->getOffset();
15837 } else if (Op.getOpcode() == ISD::ADD) {
15838 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
15839 Offset += C->getZExtValue();
15840 Op = Op.getOperand(0);
15843 } else if (Op.getOpcode() == ISD::SUB) {
15844 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
15845 Offset += -C->getZExtValue();
15846 Op = Op.getOperand(0);
15851 // Otherwise, this isn't something we can handle, reject it.
15855 const GlobalValue *GV = GA->getGlobal();
15856 // If we require an extra load to get this address, as in PIC mode, we
15857 // can't accept it.
15858 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
15859 getTargetMachine())))
15862 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(),
15863 GA->getValueType(0), Offset);
15868 if (Result.getNode()) {
15869 Ops.push_back(Result);
15872 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
15875 std::pair<unsigned, const TargetRegisterClass*>
15876 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
15878 // First, see if this is a constraint that directly corresponds to an LLVM
15880 if (Constraint.size() == 1) {
15881 // GCC Constraint Letters
15882 switch (Constraint[0]) {
15884 // TODO: Slight differences here in allocation order and leaving
15885 // RIP in the class. Do they matter any more here than they do
15886 // in the normal allocation?
15887 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
15888 if (Subtarget->is64Bit()) {
15889 if (VT == MVT::i32 || VT == MVT::f32)
15890 return std::make_pair(0U, &X86::GR32RegClass);
15891 if (VT == MVT::i16)
15892 return std::make_pair(0U, &X86::GR16RegClass);
15893 if (VT == MVT::i8 || VT == MVT::i1)
15894 return std::make_pair(0U, &X86::GR8RegClass);
15895 if (VT == MVT::i64 || VT == MVT::f64)
15896 return std::make_pair(0U, &X86::GR64RegClass);
15899 // 32-bit fallthrough
15900 case 'Q': // Q_REGS
15901 if (VT == MVT::i32 || VT == MVT::f32)
15902 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
15903 if (VT == MVT::i16)
15904 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
15905 if (VT == MVT::i8 || VT == MVT::i1)
15906 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
15907 if (VT == MVT::i64)
15908 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
15910 case 'r': // GENERAL_REGS
15911 case 'l': // INDEX_REGS
15912 if (VT == MVT::i8 || VT == MVT::i1)
15913 return std::make_pair(0U, &X86::GR8RegClass);
15914 if (VT == MVT::i16)
15915 return std::make_pair(0U, &X86::GR16RegClass);
15916 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
15917 return std::make_pair(0U, &X86::GR32RegClass);
15918 return std::make_pair(0U, &X86::GR64RegClass);
15919 case 'R': // LEGACY_REGS
15920 if (VT == MVT::i8 || VT == MVT::i1)
15921 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
15922 if (VT == MVT::i16)
15923 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
15924 if (VT == MVT::i32 || !Subtarget->is64Bit())
15925 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
15926 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
15927 case 'f': // FP Stack registers.
15928 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
15929 // value to the correct fpstack register class.
15930 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
15931 return std::make_pair(0U, &X86::RFP32RegClass);
15932 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
15933 return std::make_pair(0U, &X86::RFP64RegClass);
15934 return std::make_pair(0U, &X86::RFP80RegClass);
15935 case 'y': // MMX_REGS if MMX allowed.
15936 if (!Subtarget->hasMMX()) break;
15937 return std::make_pair(0U, &X86::VR64RegClass);
15938 case 'Y': // SSE_REGS if SSE2 allowed
15939 if (!Subtarget->hasSSE2()) break;
15941 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
15942 if (!Subtarget->hasSSE1()) break;
15944 switch (VT.getSimpleVT().SimpleTy) {
15946 // Scalar SSE types.
15949 return std::make_pair(0U, &X86::FR32RegClass);
15952 return std::make_pair(0U, &X86::FR64RegClass);
15960 return std::make_pair(0U, &X86::VR128RegClass);
15968 return std::make_pair(0U, &X86::VR256RegClass);
15974 // Use the default implementation in TargetLowering to convert the register
15975 // constraint into a member of a register class.
15976 std::pair<unsigned, const TargetRegisterClass*> Res;
15977 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
15979 // Not found as a standard register?
15980 if (Res.second == 0) {
15981 // Map st(0) -> st(7) -> ST0
15982 if (Constraint.size() == 7 && Constraint[0] == '{' &&
15983 tolower(Constraint[1]) == 's' &&
15984 tolower(Constraint[2]) == 't' &&
15985 Constraint[3] == '(' &&
15986 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
15987 Constraint[5] == ')' &&
15988 Constraint[6] == '}') {
15990 Res.first = X86::ST0+Constraint[4]-'0';
15991 Res.second = &X86::RFP80RegClass;
15995 // GCC allows "st(0)" to be called just plain "st".
15996 if (StringRef("{st}").equals_lower(Constraint)) {
15997 Res.first = X86::ST0;
15998 Res.second = &X86::RFP80RegClass;
16003 if (StringRef("{flags}").equals_lower(Constraint)) {
16004 Res.first = X86::EFLAGS;
16005 Res.second = &X86::CCRRegClass;
16009 // 'A' means EAX + EDX.
16010 if (Constraint == "A") {
16011 Res.first = X86::EAX;
16012 Res.second = &X86::GR32_ADRegClass;
16018 // Otherwise, check to see if this is a register class of the wrong value
16019 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
16020 // turn into {ax},{dx}.
16021 if (Res.second->hasType(VT))
16022 return Res; // Correct type already, nothing to do.
16024 // All of the single-register GCC register classes map their values onto
16025 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
16026 // really want an 8-bit or 32-bit register, map to the appropriate register
16027 // class and return the appropriate register.
16028 if (Res.second == &X86::GR16RegClass) {
16029 if (VT == MVT::i8) {
16030 unsigned DestReg = 0;
16031 switch (Res.first) {
16033 case X86::AX: DestReg = X86::AL; break;
16034 case X86::DX: DestReg = X86::DL; break;
16035 case X86::CX: DestReg = X86::CL; break;
16036 case X86::BX: DestReg = X86::BL; break;
16039 Res.first = DestReg;
16040 Res.second = &X86::GR8RegClass;
16042 } else if (VT == MVT::i32) {
16043 unsigned DestReg = 0;
16044 switch (Res.first) {
16046 case X86::AX: DestReg = X86::EAX; break;
16047 case X86::DX: DestReg = X86::EDX; break;
16048 case X86::CX: DestReg = X86::ECX; break;
16049 case X86::BX: DestReg = X86::EBX; break;
16050 case X86::SI: DestReg = X86::ESI; break;
16051 case X86::DI: DestReg = X86::EDI; break;
16052 case X86::BP: DestReg = X86::EBP; break;
16053 case X86::SP: DestReg = X86::ESP; break;
16056 Res.first = DestReg;
16057 Res.second = &X86::GR32RegClass;
16059 } else if (VT == MVT::i64) {
16060 unsigned DestReg = 0;
16061 switch (Res.first) {
16063 case X86::AX: DestReg = X86::RAX; break;
16064 case X86::DX: DestReg = X86::RDX; break;
16065 case X86::CX: DestReg = X86::RCX; break;
16066 case X86::BX: DestReg = X86::RBX; break;
16067 case X86::SI: DestReg = X86::RSI; break;
16068 case X86::DI: DestReg = X86::RDI; break;
16069 case X86::BP: DestReg = X86::RBP; break;
16070 case X86::SP: DestReg = X86::RSP; break;
16073 Res.first = DestReg;
16074 Res.second = &X86::GR64RegClass;
16077 } else if (Res.second == &X86::FR32RegClass ||
16078 Res.second == &X86::FR64RegClass ||
16079 Res.second == &X86::VR128RegClass) {
16080 // Handle references to XMM physical registers that got mapped into the
16081 // wrong class. This can happen with constraints like {xmm0} where the
16082 // target independent register mapper will just pick the first match it can
16083 // find, ignoring the required type.
16085 if (VT == MVT::f32 || VT == MVT::i32)
16086 Res.second = &X86::FR32RegClass;
16087 else if (VT == MVT::f64 || VT == MVT::i64)
16088 Res.second = &X86::FR64RegClass;
16089 else if (X86::VR128RegClass.hasType(VT))
16090 Res.second = &X86::VR128RegClass;
16091 else if (X86::VR256RegClass.hasType(VT))
16092 Res.second = &X86::VR256RegClass;