1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/ADT/SmallBitVector.h"
23 #include "llvm/ADT/SmallSet.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/ADT/VariadicFunction.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/IR/CallSite.h"
36 #include "llvm/IR/CallingConv.h"
37 #include "llvm/IR/Constants.h"
38 #include "llvm/IR/DerivedTypes.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/GlobalAlias.h"
41 #include "llvm/IR/GlobalVariable.h"
42 #include "llvm/IR/Instructions.h"
43 #include "llvm/IR/Intrinsics.h"
44 #include "llvm/MC/MCAsmInfo.h"
45 #include "llvm/MC/MCContext.h"
46 #include "llvm/MC/MCExpr.h"
47 #include "llvm/MC/MCSymbol.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/MathExtras.h"
52 #include "llvm/Target/TargetOptions.h"
53 #include "X86IntrinsicsInfo.h"
59 #define DEBUG_TYPE "x86-isel"
61 STATISTIC(NumTailCalls, "Number of tail calls");
63 static cl::opt<bool> ExperimentalVectorWideningLegalization(
64 "x86-experimental-vector-widening-legalization", cl::init(false),
65 cl::desc("Enable an experimental vector type legalization through widening "
66 "rather than promotion."),
69 static cl::opt<bool> ExperimentalVectorShuffleLowering(
70 "x86-experimental-vector-shuffle-lowering", cl::init(true),
71 cl::desc("Enable an experimental vector shuffle lowering code path."),
74 static cl::opt<int> ReciprocalEstimateRefinementSteps(
75 "x86-recip-refinement-steps", cl::init(1),
76 cl::desc("Specify the number of Newton-Raphson iterations applied to the "
77 "result of the hardware reciprocal estimate instruction."),
80 // Forward declarations.
81 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
84 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
85 SelectionDAG &DAG, SDLoc dl,
86 unsigned vectorWidth) {
87 assert((vectorWidth == 128 || vectorWidth == 256) &&
88 "Unsupported vector width");
89 EVT VT = Vec.getValueType();
90 EVT ElVT = VT.getVectorElementType();
91 unsigned Factor = VT.getSizeInBits()/vectorWidth;
92 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
93 VT.getVectorNumElements()/Factor);
95 // Extract from UNDEF is UNDEF.
96 if (Vec.getOpcode() == ISD::UNDEF)
97 return DAG.getUNDEF(ResultVT);
99 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
100 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
102 // This is the index of the first element of the vectorWidth-bit chunk
104 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
107 // If the input is a buildvector just emit a smaller one.
108 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
109 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
110 makeArrayRef(Vec->op_begin() + NormalizedIdxVal,
113 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
114 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, VecIdx);
117 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
118 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
119 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
120 /// instructions or a simple subregister reference. Idx is an index in the
121 /// 128 bits we want. It need not be aligned to a 128-bit boundary. That makes
122 /// lowering EXTRACT_VECTOR_ELT operations easier.
123 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
124 SelectionDAG &DAG, SDLoc dl) {
125 assert((Vec.getValueType().is256BitVector() ||
126 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
127 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
130 /// Generate a DAG to grab 256-bits from a 512-bit vector.
131 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
132 SelectionDAG &DAG, SDLoc dl) {
133 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
134 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
137 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
138 unsigned IdxVal, SelectionDAG &DAG,
139 SDLoc dl, unsigned vectorWidth) {
140 assert((vectorWidth == 128 || vectorWidth == 256) &&
141 "Unsupported vector width");
142 // Inserting UNDEF is Result
143 if (Vec.getOpcode() == ISD::UNDEF)
145 EVT VT = Vec.getValueType();
146 EVT ElVT = VT.getVectorElementType();
147 EVT ResultVT = Result.getValueType();
149 // Insert the relevant vectorWidth bits.
150 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
152 // This is the index of the first element of the vectorWidth-bit chunk
154 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
157 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
158 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, VecIdx);
161 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
162 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
163 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
164 /// simple superregister reference. Idx is an index in the 128 bits
165 /// we want. It need not be aligned to a 128-bit boundary. That makes
166 /// lowering INSERT_VECTOR_ELT operations easier.
167 static SDValue Insert128BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
168 SelectionDAG &DAG,SDLoc dl) {
169 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
170 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
173 static SDValue Insert256BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
174 SelectionDAG &DAG, SDLoc dl) {
175 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
176 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
179 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
180 /// instructions. This is used because creating CONCAT_VECTOR nodes of
181 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
182 /// large BUILD_VECTORS.
183 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
184 unsigned NumElems, SelectionDAG &DAG,
186 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
187 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
190 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
191 unsigned NumElems, SelectionDAG &DAG,
193 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
194 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
197 // FIXME: This should stop caching the target machine as soon as
198 // we can remove resetOperationActions et al.
199 X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM)
200 : TargetLowering(TM) {
201 Subtarget = &TM.getSubtarget<X86Subtarget>();
202 X86ScalarSSEf64 = Subtarget->hasSSE2();
203 X86ScalarSSEf32 = Subtarget->hasSSE1();
204 TD = getDataLayout();
206 resetOperationActions();
209 void X86TargetLowering::resetOperationActions() {
210 const TargetMachine &TM = getTargetMachine();
211 static bool FirstTimeThrough = true;
213 // If none of the target options have changed, then we don't need to reset the
214 // operation actions.
215 if (!FirstTimeThrough && TO == TM.Options) return;
217 if (!FirstTimeThrough) {
218 // Reinitialize the actions.
220 FirstTimeThrough = false;
225 // Set up the TargetLowering object.
226 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
228 // X86 is weird. It always uses i8 for shift amounts and setcc results.
229 setBooleanContents(ZeroOrOneBooleanContent);
230 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
231 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
233 // For 64-bit, since we have so many registers, use the ILP scheduler.
234 // For 32-bit, use the register pressure specific scheduling.
235 // For Atom, always use ILP scheduling.
236 if (Subtarget->isAtom())
237 setSchedulingPreference(Sched::ILP);
238 else if (Subtarget->is64Bit())
239 setSchedulingPreference(Sched::ILP);
241 setSchedulingPreference(Sched::RegPressure);
242 const X86RegisterInfo *RegInfo =
243 TM.getSubtarget<X86Subtarget>().getRegisterInfo();
244 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
246 // Bypass expensive divides on Atom when compiling with O2.
247 if (TM.getOptLevel() >= CodeGenOpt::Default) {
248 if (Subtarget->hasSlowDivide32())
249 addBypassSlowDiv(32, 8);
250 if (Subtarget->hasSlowDivide64() && Subtarget->is64Bit())
251 addBypassSlowDiv(64, 16);
254 if (Subtarget->isTargetKnownWindowsMSVC()) {
255 // Setup Windows compiler runtime calls.
256 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
257 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
258 setLibcallName(RTLIB::SREM_I64, "_allrem");
259 setLibcallName(RTLIB::UREM_I64, "_aullrem");
260 setLibcallName(RTLIB::MUL_I64, "_allmul");
261 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
262 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
263 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
264 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
265 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
267 // The _ftol2 runtime function has an unusual calling conv, which
268 // is modeled by a special pseudo-instruction.
269 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
270 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
271 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
272 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
275 if (Subtarget->isTargetDarwin()) {
276 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
277 setUseUnderscoreSetJmp(false);
278 setUseUnderscoreLongJmp(false);
279 } else if (Subtarget->isTargetWindowsGNU()) {
280 // MS runtime is weird: it exports _setjmp, but longjmp!
281 setUseUnderscoreSetJmp(true);
282 setUseUnderscoreLongJmp(false);
284 setUseUnderscoreSetJmp(true);
285 setUseUnderscoreLongJmp(true);
288 // Set up the register classes.
289 addRegisterClass(MVT::i8, &X86::GR8RegClass);
290 addRegisterClass(MVT::i16, &X86::GR16RegClass);
291 addRegisterClass(MVT::i32, &X86::GR32RegClass);
292 if (Subtarget->is64Bit())
293 addRegisterClass(MVT::i64, &X86::GR64RegClass);
295 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
297 // We don't accept any truncstore of integer registers.
298 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
299 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
300 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
301 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
302 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
303 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
305 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
307 // SETOEQ and SETUNE require checking two conditions.
308 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
309 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
310 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
311 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
312 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
313 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
315 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
317 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
318 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
319 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
321 if (Subtarget->is64Bit()) {
322 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
323 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
324 } else if (!TM.Options.UseSoftFloat) {
325 // We have an algorithm for SSE2->double, and we turn this into a
326 // 64-bit FILD followed by conditional FADD for other targets.
327 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
328 // We have an algorithm for SSE2, and we turn this into a 64-bit
329 // FILD for other targets.
330 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
333 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
335 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
336 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
338 if (!TM.Options.UseSoftFloat) {
339 // SSE has no i16 to fp conversion, only i32
340 if (X86ScalarSSEf32) {
341 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
342 // f32 and f64 cases are Legal, f80 case is not
343 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
345 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
346 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
349 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
350 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
353 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
354 // are Legal, f80 is custom lowered.
355 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
356 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
358 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
360 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
361 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
363 if (X86ScalarSSEf32) {
364 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
365 // f32 and f64 cases are Legal, f80 case is not
366 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
368 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
369 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
372 // Handle FP_TO_UINT by promoting the destination to a larger signed
374 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
375 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
376 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
378 if (Subtarget->is64Bit()) {
379 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
380 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
381 } else if (!TM.Options.UseSoftFloat) {
382 // Since AVX is a superset of SSE3, only check for SSE here.
383 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
384 // Expand FP_TO_UINT into a select.
385 // FIXME: We would like to use a Custom expander here eventually to do
386 // the optimal thing for SSE vs. the default expansion in the legalizer.
387 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
389 // With SSE3 we can use fisttpll to convert to a signed i64; without
390 // SSE, we're stuck with a fistpll.
391 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
394 if (isTargetFTOL()) {
395 // Use the _ftol2 runtime function, which has a pseudo-instruction
396 // to handle its weird calling convention.
397 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
400 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
401 if (!X86ScalarSSEf64) {
402 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
403 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
404 if (Subtarget->is64Bit()) {
405 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
406 // Without SSE, i64->f64 goes through memory.
407 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
411 // Scalar integer divide and remainder are lowered to use operations that
412 // produce two results, to match the available instructions. This exposes
413 // the two-result form to trivial CSE, which is able to combine x/y and x%y
414 // into a single instruction.
416 // Scalar integer multiply-high is also lowered to use two-result
417 // operations, to match the available instructions. However, plain multiply
418 // (low) operations are left as Legal, as there are single-result
419 // instructions for this in x86. Using the two-result multiply instructions
420 // when both high and low results are needed must be arranged by dagcombine.
421 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
423 setOperationAction(ISD::MULHS, VT, Expand);
424 setOperationAction(ISD::MULHU, VT, Expand);
425 setOperationAction(ISD::SDIV, VT, Expand);
426 setOperationAction(ISD::UDIV, VT, Expand);
427 setOperationAction(ISD::SREM, VT, Expand);
428 setOperationAction(ISD::UREM, VT, Expand);
430 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
431 setOperationAction(ISD::ADDC, VT, Custom);
432 setOperationAction(ISD::ADDE, VT, Custom);
433 setOperationAction(ISD::SUBC, VT, Custom);
434 setOperationAction(ISD::SUBE, VT, Custom);
437 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
438 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
439 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
440 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
441 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
442 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
443 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
444 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
445 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
446 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
447 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
448 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
449 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
450 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
451 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
452 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
453 if (Subtarget->is64Bit())
454 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
455 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
456 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
457 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
458 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
459 setOperationAction(ISD::FREM , MVT::f32 , Expand);
460 setOperationAction(ISD::FREM , MVT::f64 , Expand);
461 setOperationAction(ISD::FREM , MVT::f80 , Expand);
462 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
464 // Promote the i8 variants and force them on up to i32 which has a shorter
466 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
467 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
468 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
469 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
470 if (Subtarget->hasBMI()) {
471 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
472 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
473 if (Subtarget->is64Bit())
474 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
476 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
477 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
478 if (Subtarget->is64Bit())
479 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
482 if (Subtarget->hasLZCNT()) {
483 // When promoting the i8 variants, force them to i32 for a shorter
485 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
486 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
487 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
488 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
489 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
490 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
491 if (Subtarget->is64Bit())
492 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
494 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
495 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
496 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
497 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
498 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
499 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
500 if (Subtarget->is64Bit()) {
501 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
502 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
506 // Special handling for half-precision floating point conversions.
507 // If we don't have F16C support, then lower half float conversions
508 // into library calls.
509 if (TM.Options.UseSoftFloat || !Subtarget->hasF16C()) {
510 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
511 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
514 // There's never any support for operations beyond MVT::f32.
515 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
516 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
517 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
518 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
520 setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
521 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
522 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
523 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
525 if (Subtarget->hasPOPCNT()) {
526 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
528 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
529 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
530 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
531 if (Subtarget->is64Bit())
532 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
535 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
537 if (!Subtarget->hasMOVBE())
538 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
540 // These should be promoted to a larger select which is supported.
541 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
542 // X86 wants to expand cmov itself.
543 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
544 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
545 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
546 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
547 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
548 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
549 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
550 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
551 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
552 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
553 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
554 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
555 if (Subtarget->is64Bit()) {
556 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
557 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
559 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
560 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
561 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
562 // support continuation, user-level threading, and etc.. As a result, no
563 // other SjLj exception interfaces are implemented and please don't build
564 // your own exception handling based on them.
565 // LLVM/Clang supports zero-cost DWARF exception handling.
566 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
567 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
570 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
571 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
572 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
573 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
574 if (Subtarget->is64Bit())
575 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
576 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
577 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
578 if (Subtarget->is64Bit()) {
579 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
580 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
581 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
582 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
583 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
585 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
586 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
587 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
588 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
589 if (Subtarget->is64Bit()) {
590 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
591 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
592 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
595 if (Subtarget->hasSSE1())
596 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
598 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
600 // Expand certain atomics
601 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
603 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
604 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
605 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
608 if (Subtarget->hasCmpxchg16b()) {
609 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
612 // FIXME - use subtarget debug flags
613 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
614 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
615 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
618 if (Subtarget->is64Bit()) {
619 setExceptionPointerRegister(X86::RAX);
620 setExceptionSelectorRegister(X86::RDX);
622 setExceptionPointerRegister(X86::EAX);
623 setExceptionSelectorRegister(X86::EDX);
625 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
626 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
628 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
629 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
631 setOperationAction(ISD::TRAP, MVT::Other, Legal);
632 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
634 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
635 setOperationAction(ISD::VASTART , MVT::Other, Custom);
636 setOperationAction(ISD::VAEND , MVT::Other, Expand);
637 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
638 // TargetInfo::X86_64ABIBuiltinVaList
639 setOperationAction(ISD::VAARG , MVT::Other, Custom);
640 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
642 // TargetInfo::CharPtrBuiltinVaList
643 setOperationAction(ISD::VAARG , MVT::Other, Expand);
644 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
647 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
648 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
650 setOperationAction(ISD::DYNAMIC_STACKALLOC, getPointerTy(), Custom);
652 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
653 // f32 and f64 use SSE.
654 // Set up the FP register classes.
655 addRegisterClass(MVT::f32, &X86::FR32RegClass);
656 addRegisterClass(MVT::f64, &X86::FR64RegClass);
658 // Use ANDPD to simulate FABS.
659 setOperationAction(ISD::FABS , MVT::f64, Custom);
660 setOperationAction(ISD::FABS , MVT::f32, Custom);
662 // Use XORP to simulate FNEG.
663 setOperationAction(ISD::FNEG , MVT::f64, Custom);
664 setOperationAction(ISD::FNEG , MVT::f32, Custom);
666 // Use ANDPD and ORPD to simulate FCOPYSIGN.
667 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
668 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
670 // Lower this to FGETSIGNx86 plus an AND.
671 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
672 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
674 // We don't support sin/cos/fmod
675 setOperationAction(ISD::FSIN , MVT::f64, Expand);
676 setOperationAction(ISD::FCOS , MVT::f64, Expand);
677 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
678 setOperationAction(ISD::FSIN , MVT::f32, Expand);
679 setOperationAction(ISD::FCOS , MVT::f32, Expand);
680 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
682 // Expand FP immediates into loads from the stack, except for the special
684 addLegalFPImmediate(APFloat(+0.0)); // xorpd
685 addLegalFPImmediate(APFloat(+0.0f)); // xorps
686 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
687 // Use SSE for f32, x87 for f64.
688 // Set up the FP register classes.
689 addRegisterClass(MVT::f32, &X86::FR32RegClass);
690 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
692 // Use ANDPS to simulate FABS.
693 setOperationAction(ISD::FABS , MVT::f32, Custom);
695 // Use XORP to simulate FNEG.
696 setOperationAction(ISD::FNEG , MVT::f32, Custom);
698 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
700 // Use ANDPS and ORPS to simulate FCOPYSIGN.
701 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
702 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
704 // We don't support sin/cos/fmod
705 setOperationAction(ISD::FSIN , MVT::f32, Expand);
706 setOperationAction(ISD::FCOS , MVT::f32, Expand);
707 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
709 // Special cases we handle for FP constants.
710 addLegalFPImmediate(APFloat(+0.0f)); // xorps
711 addLegalFPImmediate(APFloat(+0.0)); // FLD0
712 addLegalFPImmediate(APFloat(+1.0)); // FLD1
713 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
714 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
716 if (!TM.Options.UnsafeFPMath) {
717 setOperationAction(ISD::FSIN , MVT::f64, Expand);
718 setOperationAction(ISD::FCOS , MVT::f64, Expand);
719 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
721 } else if (!TM.Options.UseSoftFloat) {
722 // f32 and f64 in x87.
723 // Set up the FP register classes.
724 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
725 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
727 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
728 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
729 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
730 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
732 if (!TM.Options.UnsafeFPMath) {
733 setOperationAction(ISD::FSIN , MVT::f64, Expand);
734 setOperationAction(ISD::FSIN , MVT::f32, Expand);
735 setOperationAction(ISD::FCOS , MVT::f64, Expand);
736 setOperationAction(ISD::FCOS , MVT::f32, Expand);
737 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
738 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
740 addLegalFPImmediate(APFloat(+0.0)); // FLD0
741 addLegalFPImmediate(APFloat(+1.0)); // FLD1
742 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
743 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
744 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
745 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
746 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
747 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
750 // We don't support FMA.
751 setOperationAction(ISD::FMA, MVT::f64, Expand);
752 setOperationAction(ISD::FMA, MVT::f32, Expand);
754 // Long double always uses X87.
755 if (!TM.Options.UseSoftFloat) {
756 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
757 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
758 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
760 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
761 addLegalFPImmediate(TmpFlt); // FLD0
763 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
766 APFloat TmpFlt2(+1.0);
767 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
769 addLegalFPImmediate(TmpFlt2); // FLD1
770 TmpFlt2.changeSign();
771 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
774 if (!TM.Options.UnsafeFPMath) {
775 setOperationAction(ISD::FSIN , MVT::f80, Expand);
776 setOperationAction(ISD::FCOS , MVT::f80, Expand);
777 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
780 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
781 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
782 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
783 setOperationAction(ISD::FRINT, MVT::f80, Expand);
784 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
785 setOperationAction(ISD::FMA, MVT::f80, Expand);
788 // Always use a library call for pow.
789 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
790 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
791 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
793 setOperationAction(ISD::FLOG, MVT::f80, Expand);
794 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
795 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
796 setOperationAction(ISD::FEXP, MVT::f80, Expand);
797 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
798 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
799 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
801 // First set operation action for all vector types to either promote
802 // (for widening) or expand (for scalarization). Then we will selectively
803 // turn on ones that can be effectively codegen'd.
804 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
805 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
806 MVT VT = (MVT::SimpleValueType)i;
807 setOperationAction(ISD::ADD , VT, Expand);
808 setOperationAction(ISD::SUB , VT, Expand);
809 setOperationAction(ISD::FADD, VT, Expand);
810 setOperationAction(ISD::FNEG, VT, Expand);
811 setOperationAction(ISD::FSUB, VT, Expand);
812 setOperationAction(ISD::MUL , VT, Expand);
813 setOperationAction(ISD::FMUL, VT, Expand);
814 setOperationAction(ISD::SDIV, VT, Expand);
815 setOperationAction(ISD::UDIV, VT, Expand);
816 setOperationAction(ISD::FDIV, VT, Expand);
817 setOperationAction(ISD::SREM, VT, Expand);
818 setOperationAction(ISD::UREM, VT, Expand);
819 setOperationAction(ISD::LOAD, VT, Expand);
820 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
821 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
822 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
823 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
824 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
825 setOperationAction(ISD::FABS, VT, Expand);
826 setOperationAction(ISD::FSIN, VT, Expand);
827 setOperationAction(ISD::FSINCOS, VT, Expand);
828 setOperationAction(ISD::FCOS, VT, Expand);
829 setOperationAction(ISD::FSINCOS, VT, Expand);
830 setOperationAction(ISD::FREM, VT, Expand);
831 setOperationAction(ISD::FMA, VT, Expand);
832 setOperationAction(ISD::FPOWI, VT, Expand);
833 setOperationAction(ISD::FSQRT, VT, Expand);
834 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
835 setOperationAction(ISD::FFLOOR, VT, Expand);
836 setOperationAction(ISD::FCEIL, VT, Expand);
837 setOperationAction(ISD::FTRUNC, VT, Expand);
838 setOperationAction(ISD::FRINT, VT, Expand);
839 setOperationAction(ISD::FNEARBYINT, VT, Expand);
840 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
841 setOperationAction(ISD::MULHS, VT, Expand);
842 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
843 setOperationAction(ISD::MULHU, VT, Expand);
844 setOperationAction(ISD::SDIVREM, VT, Expand);
845 setOperationAction(ISD::UDIVREM, VT, Expand);
846 setOperationAction(ISD::FPOW, VT, Expand);
847 setOperationAction(ISD::CTPOP, VT, Expand);
848 setOperationAction(ISD::CTTZ, VT, Expand);
849 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
850 setOperationAction(ISD::CTLZ, VT, Expand);
851 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
852 setOperationAction(ISD::SHL, VT, Expand);
853 setOperationAction(ISD::SRA, VT, Expand);
854 setOperationAction(ISD::SRL, VT, Expand);
855 setOperationAction(ISD::ROTL, VT, Expand);
856 setOperationAction(ISD::ROTR, VT, Expand);
857 setOperationAction(ISD::BSWAP, VT, Expand);
858 setOperationAction(ISD::SETCC, VT, Expand);
859 setOperationAction(ISD::FLOG, VT, Expand);
860 setOperationAction(ISD::FLOG2, VT, Expand);
861 setOperationAction(ISD::FLOG10, VT, Expand);
862 setOperationAction(ISD::FEXP, VT, Expand);
863 setOperationAction(ISD::FEXP2, VT, Expand);
864 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
865 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
866 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
867 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
868 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
869 setOperationAction(ISD::TRUNCATE, VT, Expand);
870 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
871 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
872 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
873 setOperationAction(ISD::VSELECT, VT, Expand);
874 setOperationAction(ISD::SELECT_CC, VT, Expand);
875 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
876 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
877 setTruncStoreAction(VT,
878 (MVT::SimpleValueType)InnerVT, Expand);
879 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
880 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
882 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like types,
883 // we have to deal with them whether we ask for Expansion or not. Setting
884 // Expand causes its own optimisation problems though, so leave them legal.
885 if (VT.getVectorElementType() == MVT::i1)
886 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
889 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
890 // with -msoft-float, disable use of MMX as well.
891 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
892 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
893 // No operations on x86mmx supported, everything uses intrinsics.
896 // MMX-sized vectors (other than x86mmx) are expected to be expanded
897 // into smaller operations.
898 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
899 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
900 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
901 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
902 setOperationAction(ISD::AND, MVT::v8i8, Expand);
903 setOperationAction(ISD::AND, MVT::v4i16, Expand);
904 setOperationAction(ISD::AND, MVT::v2i32, Expand);
905 setOperationAction(ISD::AND, MVT::v1i64, Expand);
906 setOperationAction(ISD::OR, MVT::v8i8, Expand);
907 setOperationAction(ISD::OR, MVT::v4i16, Expand);
908 setOperationAction(ISD::OR, MVT::v2i32, Expand);
909 setOperationAction(ISD::OR, MVT::v1i64, Expand);
910 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
911 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
912 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
913 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
914 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
915 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
916 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
917 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
918 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
919 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
920 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
921 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
922 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
923 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
924 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
925 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
926 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
928 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
929 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
931 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
932 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
933 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
934 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
935 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
936 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
937 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
938 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
939 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
940 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
941 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
942 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
943 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
946 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
947 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
949 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
950 // registers cannot be used even for integer operations.
951 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
952 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
953 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
954 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
956 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
957 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
958 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
959 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
960 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
961 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
962 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
963 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
964 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
965 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
966 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
967 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
968 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
969 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
970 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
971 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
972 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
973 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
974 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
975 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
976 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
977 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
979 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
980 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
981 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
982 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
984 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
985 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
986 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
987 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
988 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
990 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
991 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
992 MVT VT = (MVT::SimpleValueType)i;
993 // Do not attempt to custom lower non-power-of-2 vectors
994 if (!isPowerOf2_32(VT.getVectorNumElements()))
996 // Do not attempt to custom lower non-128-bit vectors
997 if (!VT.is128BitVector())
999 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1000 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1001 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1004 // We support custom legalizing of sext and anyext loads for specific
1005 // memory vector types which we can load as a scalar (or sequence of
1006 // scalars) and extend in-register to a legal 128-bit vector type. For sext
1007 // loads these must work with a single scalar load.
1008 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i8, Custom);
1009 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, Custom);
1010 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i8, Custom);
1011 setLoadExtAction(ISD::EXTLOAD, MVT::v2i8, Custom);
1012 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, Custom);
1013 setLoadExtAction(ISD::EXTLOAD, MVT::v2i32, Custom);
1014 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Custom);
1015 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, Custom);
1016 setLoadExtAction(ISD::EXTLOAD, MVT::v8i8, Custom);
1018 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
1019 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
1020 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
1021 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
1022 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
1023 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
1025 if (Subtarget->is64Bit()) {
1026 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1027 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1030 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
1031 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1032 MVT VT = (MVT::SimpleValueType)i;
1034 // Do not attempt to promote non-128-bit vectors
1035 if (!VT.is128BitVector())
1038 setOperationAction(ISD::AND, VT, Promote);
1039 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1040 setOperationAction(ISD::OR, VT, Promote);
1041 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1042 setOperationAction(ISD::XOR, VT, Promote);
1043 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1044 setOperationAction(ISD::LOAD, VT, Promote);
1045 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1046 setOperationAction(ISD::SELECT, VT, Promote);
1047 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1050 // Custom lower v2i64 and v2f64 selects.
1051 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1052 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1053 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1054 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1056 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1057 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1059 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1060 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1061 // As there is no 64-bit GPR available, we need build a special custom
1062 // sequence to convert from v2i32 to v2f32.
1063 if (!Subtarget->is64Bit())
1064 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1066 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1067 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1069 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
1071 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
1072 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
1073 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
1076 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1077 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1078 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1079 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1080 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1081 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1082 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1083 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1084 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1085 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1086 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1088 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1089 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1090 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1091 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1092 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1093 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1094 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1095 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1096 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1097 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1099 // FIXME: Do we need to handle scalar-to-vector here?
1100 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1102 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
1103 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
1104 setOperationAction(ISD::VSELECT, MVT::v4i32, Custom);
1105 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
1106 setOperationAction(ISD::VSELECT, MVT::v8i16, Custom);
1107 // There is no BLENDI for byte vectors. We don't need to custom lower
1108 // some vselects for now.
1109 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1111 // SSE41 brings specific instructions for doing vector sign extend even in
1112 // cases where we don't have SRA.
1113 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i8, Custom);
1114 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, Custom);
1115 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i32, Custom);
1117 // i8 and i16 vectors are custom because the source register and source
1118 // source memory operand types are not the same width. f32 vectors are
1119 // custom since the immediate controlling the insert encodes additional
1121 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1122 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1123 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1124 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1126 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1127 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1128 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1129 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1131 // FIXME: these should be Legal, but that's only for the case where
1132 // the index is constant. For now custom expand to deal with that.
1133 if (Subtarget->is64Bit()) {
1134 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1135 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1139 if (Subtarget->hasSSE2()) {
1140 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1141 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1143 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1144 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1146 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1147 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1149 // In the customized shift lowering, the legal cases in AVX2 will be
1151 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1152 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1154 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1155 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1157 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1160 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1161 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1162 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1163 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1164 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1165 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1166 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1168 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1169 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1170 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1172 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1173 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1174 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1175 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1176 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1177 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1178 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1179 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1180 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1181 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1182 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1183 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1185 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1186 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1187 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1188 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1189 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1190 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1191 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1192 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1193 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1194 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1195 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1196 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1198 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1199 // even though v8i16 is a legal type.
1200 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1201 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1202 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1204 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1205 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1206 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1208 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1209 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1211 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1213 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1214 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1216 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1217 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1219 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1220 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1222 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1223 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1224 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1225 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1227 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1228 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1229 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1231 setOperationAction(ISD::VSELECT, MVT::v4f64, Custom);
1232 setOperationAction(ISD::VSELECT, MVT::v4i64, Custom);
1233 setOperationAction(ISD::VSELECT, MVT::v8i32, Custom);
1234 setOperationAction(ISD::VSELECT, MVT::v8f32, Custom);
1236 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1237 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1238 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1239 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1240 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1241 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1242 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1243 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1244 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1245 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1246 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1247 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1249 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1250 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1251 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1252 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1253 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1254 setOperationAction(ISD::FMA, MVT::f32, Legal);
1255 setOperationAction(ISD::FMA, MVT::f64, Legal);
1258 if (Subtarget->hasInt256()) {
1259 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1260 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1261 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1262 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1264 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1265 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1266 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1267 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1269 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1270 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1271 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1272 // Don't lower v32i8 because there is no 128-bit byte mul
1274 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1275 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1276 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1277 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1279 setOperationAction(ISD::VSELECT, MVT::v16i16, Custom);
1280 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1282 // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1283 // when we have a 256bit-wide blend with immediate.
1284 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom);
1286 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1287 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1288 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1289 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1291 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1292 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1293 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1294 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1296 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1297 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1298 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1299 // Don't lower v32i8 because there is no 128-bit byte mul
1302 // In the customized shift lowering, the legal cases in AVX2 will be
1304 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1305 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1307 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1308 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1310 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1312 // Custom lower several nodes for 256-bit types.
1313 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1314 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1315 MVT VT = (MVT::SimpleValueType)i;
1317 if (VT.getScalarSizeInBits() >= 32) {
1318 setOperationAction(ISD::MLOAD, VT, Legal);
1319 setOperationAction(ISD::MSTORE, VT, Legal);
1321 // Extract subvector is special because the value type
1322 // (result) is 128-bit but the source is 256-bit wide.
1323 if (VT.is128BitVector()) {
1324 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1326 // Do not attempt to custom lower other non-256-bit vectors
1327 if (!VT.is256BitVector())
1330 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1331 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1332 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1333 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1334 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1335 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1336 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1339 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1340 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1341 MVT VT = (MVT::SimpleValueType)i;
1343 // Do not attempt to promote non-256-bit vectors
1344 if (!VT.is256BitVector())
1347 setOperationAction(ISD::AND, VT, Promote);
1348 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1349 setOperationAction(ISD::OR, VT, Promote);
1350 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1351 setOperationAction(ISD::XOR, VT, Promote);
1352 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1353 setOperationAction(ISD::LOAD, VT, Promote);
1354 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1355 setOperationAction(ISD::SELECT, VT, Promote);
1356 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1360 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1361 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1362 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1363 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1364 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1366 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1367 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1368 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1370 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1371 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1372 setOperationAction(ISD::XOR, MVT::i1, Legal);
1373 setOperationAction(ISD::OR, MVT::i1, Legal);
1374 setOperationAction(ISD::AND, MVT::i1, Legal);
1375 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, Legal);
1376 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1377 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1378 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1379 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1380 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1382 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1383 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1384 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1385 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1386 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1387 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1389 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1390 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1391 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1392 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1393 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1394 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1395 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1396 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1398 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1399 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1400 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1401 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1402 if (Subtarget->is64Bit()) {
1403 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1404 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1405 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1406 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1408 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1409 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1410 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1411 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1412 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1413 setOperationAction(ISD::SINT_TO_FP, MVT::v8i1, Custom);
1414 setOperationAction(ISD::SINT_TO_FP, MVT::v16i1, Custom);
1415 setOperationAction(ISD::SINT_TO_FP, MVT::v16i8, Promote);
1416 setOperationAction(ISD::SINT_TO_FP, MVT::v16i16, Promote);
1417 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1418 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1419 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1420 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1421 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1423 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1424 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1425 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1426 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1427 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1428 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1429 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1430 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1431 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1432 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1433 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1434 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1435 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1437 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1438 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1439 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1440 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1441 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1442 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1444 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1445 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1447 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1449 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1450 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1451 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1452 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1453 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1454 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1455 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1456 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1457 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1459 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1460 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1462 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1463 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1465 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1467 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1468 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1470 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1471 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1473 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1474 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1476 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1477 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1478 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1479 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1480 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1481 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1483 if (Subtarget->hasCDI()) {
1484 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1485 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1488 // Custom lower several nodes.
1489 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1490 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1491 MVT VT = (MVT::SimpleValueType)i;
1493 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1494 // Extract subvector is special because the value type
1495 // (result) is 256/128-bit but the source is 512-bit wide.
1496 if (VT.is128BitVector() || VT.is256BitVector()) {
1497 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1499 if (VT.getVectorElementType() == MVT::i1)
1500 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1502 // Do not attempt to custom lower other non-512-bit vectors
1503 if (!VT.is512BitVector())
1506 if ( EltSize >= 32) {
1507 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1508 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1509 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1510 setOperationAction(ISD::VSELECT, VT, Legal);
1511 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1512 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1513 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1514 setOperationAction(ISD::MLOAD, VT, Legal);
1515 setOperationAction(ISD::MSTORE, VT, Legal);
1518 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1519 MVT VT = (MVT::SimpleValueType)i;
1521 // Do not attempt to promote non-256-bit vectors.
1522 if (!VT.is512BitVector())
1525 setOperationAction(ISD::SELECT, VT, Promote);
1526 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1530 if (!TM.Options.UseSoftFloat && Subtarget->hasBWI()) {
1531 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1532 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1534 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1535 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1537 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1538 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1539 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1540 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1541 setOperationAction(ISD::ADD, MVT::v32i16, Legal);
1542 setOperationAction(ISD::ADD, MVT::v64i8, Legal);
1543 setOperationAction(ISD::SUB, MVT::v32i16, Legal);
1544 setOperationAction(ISD::SUB, MVT::v64i8, Legal);
1545 setOperationAction(ISD::MUL, MVT::v32i16, Legal);
1547 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1548 const MVT VT = (MVT::SimpleValueType)i;
1550 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1552 // Do not attempt to promote non-256-bit vectors.
1553 if (!VT.is512BitVector())
1557 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1558 setOperationAction(ISD::VSELECT, VT, Legal);
1563 if (!TM.Options.UseSoftFloat && Subtarget->hasVLX()) {
1564 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1565 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1567 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1568 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1569 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Legal);
1571 setOperationAction(ISD::AND, MVT::v8i32, Legal);
1572 setOperationAction(ISD::OR, MVT::v8i32, Legal);
1573 setOperationAction(ISD::XOR, MVT::v8i32, Legal);
1574 setOperationAction(ISD::AND, MVT::v4i32, Legal);
1575 setOperationAction(ISD::OR, MVT::v4i32, Legal);
1576 setOperationAction(ISD::XOR, MVT::v4i32, Legal);
1579 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1580 // of this type with custom code.
1581 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1582 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1583 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1587 // We want to custom lower some of our intrinsics.
1588 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1589 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1590 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1591 if (!Subtarget->is64Bit())
1592 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1594 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1595 // handle type legalization for these operations here.
1597 // FIXME: We really should do custom legalization for addition and
1598 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1599 // than generic legalization for 64-bit multiplication-with-overflow, though.
1600 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1601 // Add/Sub/Mul with overflow operations are custom lowered.
1603 setOperationAction(ISD::SADDO, VT, Custom);
1604 setOperationAction(ISD::UADDO, VT, Custom);
1605 setOperationAction(ISD::SSUBO, VT, Custom);
1606 setOperationAction(ISD::USUBO, VT, Custom);
1607 setOperationAction(ISD::SMULO, VT, Custom);
1608 setOperationAction(ISD::UMULO, VT, Custom);
1612 if (!Subtarget->is64Bit()) {
1613 // These libcalls are not available in 32-bit.
1614 setLibcallName(RTLIB::SHL_I128, nullptr);
1615 setLibcallName(RTLIB::SRL_I128, nullptr);
1616 setLibcallName(RTLIB::SRA_I128, nullptr);
1619 // Combine sin / cos into one node or libcall if possible.
1620 if (Subtarget->hasSinCos()) {
1621 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1622 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1623 if (Subtarget->isTargetDarwin()) {
1624 // For MacOSX, we don't want the normal expansion of a libcall to sincos.
1625 // We want to issue a libcall to __sincos_stret to avoid memory traffic.
1626 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1627 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1631 if (Subtarget->isTargetWin64()) {
1632 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1633 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1634 setOperationAction(ISD::SREM, MVT::i128, Custom);
1635 setOperationAction(ISD::UREM, MVT::i128, Custom);
1636 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1637 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1640 // We have target-specific dag combine patterns for the following nodes:
1641 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1642 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1643 setTargetDAGCombine(ISD::VSELECT);
1644 setTargetDAGCombine(ISD::SELECT);
1645 setTargetDAGCombine(ISD::SHL);
1646 setTargetDAGCombine(ISD::SRA);
1647 setTargetDAGCombine(ISD::SRL);
1648 setTargetDAGCombine(ISD::OR);
1649 setTargetDAGCombine(ISD::AND);
1650 setTargetDAGCombine(ISD::ADD);
1651 setTargetDAGCombine(ISD::FADD);
1652 setTargetDAGCombine(ISD::FSUB);
1653 setTargetDAGCombine(ISD::FMA);
1654 setTargetDAGCombine(ISD::SUB);
1655 setTargetDAGCombine(ISD::LOAD);
1656 setTargetDAGCombine(ISD::STORE);
1657 setTargetDAGCombine(ISD::ZERO_EXTEND);
1658 setTargetDAGCombine(ISD::ANY_EXTEND);
1659 setTargetDAGCombine(ISD::SIGN_EXTEND);
1660 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1661 setTargetDAGCombine(ISD::TRUNCATE);
1662 setTargetDAGCombine(ISD::SINT_TO_FP);
1663 setTargetDAGCombine(ISD::SETCC);
1664 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1665 setTargetDAGCombine(ISD::BUILD_VECTOR);
1666 if (Subtarget->is64Bit())
1667 setTargetDAGCombine(ISD::MUL);
1668 setTargetDAGCombine(ISD::XOR);
1670 computeRegisterProperties();
1672 // On Darwin, -Os means optimize for size without hurting performance,
1673 // do not reduce the limit.
1674 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1675 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1676 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1677 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1678 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1679 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1680 setPrefLoopAlignment(4); // 2^4 bytes.
1682 // Predictable cmov don't hurt on atom because it's in-order.
1683 PredictableSelectIsExpensive = !Subtarget->isAtom();
1684 EnableExtLdPromotion = true;
1685 setPrefFunctionAlignment(4); // 2^4 bytes.
1687 verifyIntrinsicTables();
1690 // This has so far only been implemented for 64-bit MachO.
1691 bool X86TargetLowering::useLoadStackGuardNode() const {
1692 return Subtarget->isTargetMachO() && Subtarget->is64Bit();
1695 TargetLoweringBase::LegalizeTypeAction
1696 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1697 if (ExperimentalVectorWideningLegalization &&
1698 VT.getVectorNumElements() != 1 &&
1699 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1700 return TypeWidenVector;
1702 return TargetLoweringBase::getPreferredVectorAction(VT);
1705 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1707 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1709 const unsigned NumElts = VT.getVectorNumElements();
1710 const EVT EltVT = VT.getVectorElementType();
1711 if (VT.is512BitVector()) {
1712 if (Subtarget->hasAVX512())
1713 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1714 EltVT == MVT::f32 || EltVT == MVT::f64)
1716 case 8: return MVT::v8i1;
1717 case 16: return MVT::v16i1;
1719 if (Subtarget->hasBWI())
1720 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1722 case 32: return MVT::v32i1;
1723 case 64: return MVT::v64i1;
1727 if (VT.is256BitVector() || VT.is128BitVector()) {
1728 if (Subtarget->hasVLX())
1729 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1730 EltVT == MVT::f32 || EltVT == MVT::f64)
1732 case 2: return MVT::v2i1;
1733 case 4: return MVT::v4i1;
1734 case 8: return MVT::v8i1;
1736 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1737 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1739 case 8: return MVT::v8i1;
1740 case 16: return MVT::v16i1;
1741 case 32: return MVT::v32i1;
1745 return VT.changeVectorElementTypeToInteger();
1748 /// Helper for getByValTypeAlignment to determine
1749 /// the desired ByVal argument alignment.
1750 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1753 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1754 if (VTy->getBitWidth() == 128)
1756 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1757 unsigned EltAlign = 0;
1758 getMaxByValAlign(ATy->getElementType(), EltAlign);
1759 if (EltAlign > MaxAlign)
1760 MaxAlign = EltAlign;
1761 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1762 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1763 unsigned EltAlign = 0;
1764 getMaxByValAlign(STy->getElementType(i), EltAlign);
1765 if (EltAlign > MaxAlign)
1766 MaxAlign = EltAlign;
1773 /// Return the desired alignment for ByVal aggregate
1774 /// function arguments in the caller parameter area. For X86, aggregates
1775 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1776 /// are at 4-byte boundaries.
1777 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1778 if (Subtarget->is64Bit()) {
1779 // Max of 8 and alignment of type.
1780 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1787 if (Subtarget->hasSSE1())
1788 getMaxByValAlign(Ty, Align);
1792 /// Returns the target specific optimal type for load
1793 /// and store operations as a result of memset, memcpy, and memmove
1794 /// lowering. If DstAlign is zero that means it's safe to destination
1795 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1796 /// means there isn't a need to check it against alignment requirement,
1797 /// probably because the source does not need to be loaded. If 'IsMemset' is
1798 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1799 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1800 /// source is constant so it does not need to be loaded.
1801 /// It returns EVT::Other if the type should be determined using generic
1802 /// target-independent logic.
1804 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1805 unsigned DstAlign, unsigned SrcAlign,
1806 bool IsMemset, bool ZeroMemset,
1808 MachineFunction &MF) const {
1809 const Function *F = MF.getFunction();
1810 if ((!IsMemset || ZeroMemset) &&
1811 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1812 Attribute::NoImplicitFloat)) {
1814 (Subtarget->isUnalignedMemAccessFast() ||
1815 ((DstAlign == 0 || DstAlign >= 16) &&
1816 (SrcAlign == 0 || SrcAlign >= 16)))) {
1818 if (Subtarget->hasInt256())
1820 if (Subtarget->hasFp256())
1823 if (Subtarget->hasSSE2())
1825 if (Subtarget->hasSSE1())
1827 } else if (!MemcpyStrSrc && Size >= 8 &&
1828 !Subtarget->is64Bit() &&
1829 Subtarget->hasSSE2()) {
1830 // Do not use f64 to lower memcpy if source is string constant. It's
1831 // better to use i32 to avoid the loads.
1835 if (Subtarget->is64Bit() && Size >= 8)
1840 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1842 return X86ScalarSSEf32;
1843 else if (VT == MVT::f64)
1844 return X86ScalarSSEf64;
1849 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1854 *Fast = Subtarget->isUnalignedMemAccessFast();
1858 /// Return the entry encoding for a jump table in the
1859 /// current function. The returned value is a member of the
1860 /// MachineJumpTableInfo::JTEntryKind enum.
1861 unsigned X86TargetLowering::getJumpTableEncoding() const {
1862 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1864 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1865 Subtarget->isPICStyleGOT())
1866 return MachineJumpTableInfo::EK_Custom32;
1868 // Otherwise, use the normal jump table encoding heuristics.
1869 return TargetLowering::getJumpTableEncoding();
1873 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1874 const MachineBasicBlock *MBB,
1875 unsigned uid,MCContext &Ctx) const{
1876 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1877 Subtarget->isPICStyleGOT());
1878 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1880 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1881 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1884 /// Returns relocation base for the given PIC jumptable.
1885 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1886 SelectionDAG &DAG) const {
1887 if (!Subtarget->is64Bit())
1888 // This doesn't have SDLoc associated with it, but is not really the
1889 // same as a Register.
1890 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1894 /// This returns the relocation base for the given PIC jumptable,
1895 /// the same as getPICJumpTableRelocBase, but as an MCExpr.
1896 const MCExpr *X86TargetLowering::
1897 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1898 MCContext &Ctx) const {
1899 // X86-64 uses RIP relative addressing based on the jump table label.
1900 if (Subtarget->isPICStyleRIPRel())
1901 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1903 // Otherwise, the reference is relative to the PIC base.
1904 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1907 // FIXME: Why this routine is here? Move to RegInfo!
1908 std::pair<const TargetRegisterClass*, uint8_t>
1909 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1910 const TargetRegisterClass *RRC = nullptr;
1912 switch (VT.SimpleTy) {
1914 return TargetLowering::findRepresentativeClass(VT);
1915 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1916 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
1919 RRC = &X86::VR64RegClass;
1921 case MVT::f32: case MVT::f64:
1922 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1923 case MVT::v4f32: case MVT::v2f64:
1924 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1926 RRC = &X86::VR128RegClass;
1929 return std::make_pair(RRC, Cost);
1932 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1933 unsigned &Offset) const {
1934 if (!Subtarget->isTargetLinux())
1937 if (Subtarget->is64Bit()) {
1938 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1940 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1952 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1953 unsigned DestAS) const {
1954 assert(SrcAS != DestAS && "Expected different address spaces!");
1956 return SrcAS < 256 && DestAS < 256;
1959 //===----------------------------------------------------------------------===//
1960 // Return Value Calling Convention Implementation
1961 //===----------------------------------------------------------------------===//
1963 #include "X86GenCallingConv.inc"
1966 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1967 MachineFunction &MF, bool isVarArg,
1968 const SmallVectorImpl<ISD::OutputArg> &Outs,
1969 LLVMContext &Context) const {
1970 SmallVector<CCValAssign, 16> RVLocs;
1971 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1972 return CCInfo.CheckReturn(Outs, RetCC_X86);
1975 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1976 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
1981 X86TargetLowering::LowerReturn(SDValue Chain,
1982 CallingConv::ID CallConv, bool isVarArg,
1983 const SmallVectorImpl<ISD::OutputArg> &Outs,
1984 const SmallVectorImpl<SDValue> &OutVals,
1985 SDLoc dl, SelectionDAG &DAG) const {
1986 MachineFunction &MF = DAG.getMachineFunction();
1987 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1989 SmallVector<CCValAssign, 16> RVLocs;
1990 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
1991 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1994 SmallVector<SDValue, 6> RetOps;
1995 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1996 // Operand #1 = Bytes To Pop
1997 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
2000 // Copy the result values into the output registers.
2001 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2002 CCValAssign &VA = RVLocs[i];
2003 assert(VA.isRegLoc() && "Can only return in registers!");
2004 SDValue ValToCopy = OutVals[i];
2005 EVT ValVT = ValToCopy.getValueType();
2007 // Promote values to the appropriate types.
2008 if (VA.getLocInfo() == CCValAssign::SExt)
2009 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2010 else if (VA.getLocInfo() == CCValAssign::ZExt)
2011 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2012 else if (VA.getLocInfo() == CCValAssign::AExt)
2013 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2014 else if (VA.getLocInfo() == CCValAssign::BCvt)
2015 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
2017 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2018 "Unexpected FP-extend for return value.");
2020 // If this is x86-64, and we disabled SSE, we can't return FP values,
2021 // or SSE or MMX vectors.
2022 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2023 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2024 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2025 report_fatal_error("SSE register return with SSE disabled");
2027 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2028 // llvm-gcc has never done it right and no one has noticed, so this
2029 // should be OK for now.
2030 if (ValVT == MVT::f64 &&
2031 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2032 report_fatal_error("SSE2 register return with SSE2 disabled");
2034 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2035 // the RET instruction and handled by the FP Stackifier.
2036 if (VA.getLocReg() == X86::FP0 ||
2037 VA.getLocReg() == X86::FP1) {
2038 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2039 // change the value to the FP stack register class.
2040 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2041 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2042 RetOps.push_back(ValToCopy);
2043 // Don't emit a copytoreg.
2047 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2048 // which is returned in RAX / RDX.
2049 if (Subtarget->is64Bit()) {
2050 if (ValVT == MVT::x86mmx) {
2051 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2052 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
2053 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2055 // If we don't have SSE2 available, convert to v4f32 so the generated
2056 // register is legal.
2057 if (!Subtarget->hasSSE2())
2058 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
2063 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2064 Flag = Chain.getValue(1);
2065 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2068 // The x86-64 ABIs require that for returning structs by value we copy
2069 // the sret argument into %rax/%eax (depending on ABI) for the return.
2070 // Win32 requires us to put the sret argument to %eax as well.
2071 // We saved the argument into a virtual register in the entry block,
2072 // so now we copy the value out and into %rax/%eax.
2073 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
2074 (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC())) {
2075 MachineFunction &MF = DAG.getMachineFunction();
2076 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2077 unsigned Reg = FuncInfo->getSRetReturnReg();
2079 "SRetReturnReg should have been set in LowerFormalArguments().");
2080 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
2083 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2084 X86::RAX : X86::EAX;
2085 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2086 Flag = Chain.getValue(1);
2088 // RAX/EAX now acts like a return value.
2089 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
2092 RetOps[0] = Chain; // Update chain.
2094 // Add the flag if we have it.
2096 RetOps.push_back(Flag);
2098 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2101 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2102 if (N->getNumValues() != 1)
2104 if (!N->hasNUsesOfValue(1, 0))
2107 SDValue TCChain = Chain;
2108 SDNode *Copy = *N->use_begin();
2109 if (Copy->getOpcode() == ISD::CopyToReg) {
2110 // If the copy has a glue operand, we conservatively assume it isn't safe to
2111 // perform a tail call.
2112 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2114 TCChain = Copy->getOperand(0);
2115 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2118 bool HasRet = false;
2119 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2121 if (UI->getOpcode() != X86ISD::RET_FLAG)
2123 // If we are returning more than one value, we can definitely
2124 // not make a tail call see PR19530
2125 if (UI->getNumOperands() > 4)
2127 if (UI->getNumOperands() == 4 &&
2128 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2141 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2142 ISD::NodeType ExtendKind) const {
2144 // TODO: Is this also valid on 32-bit?
2145 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2146 ReturnMVT = MVT::i8;
2148 ReturnMVT = MVT::i32;
2150 EVT MinVT = getRegisterType(Context, ReturnMVT);
2151 return VT.bitsLT(MinVT) ? MinVT : VT;
2154 /// Lower the result values of a call into the
2155 /// appropriate copies out of appropriate physical registers.
2158 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2159 CallingConv::ID CallConv, bool isVarArg,
2160 const SmallVectorImpl<ISD::InputArg> &Ins,
2161 SDLoc dl, SelectionDAG &DAG,
2162 SmallVectorImpl<SDValue> &InVals) const {
2164 // Assign locations to each value returned by this call.
2165 SmallVector<CCValAssign, 16> RVLocs;
2166 bool Is64Bit = Subtarget->is64Bit();
2167 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2169 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2171 // Copy all of the result registers out of their specified physreg.
2172 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2173 CCValAssign &VA = RVLocs[i];
2174 EVT CopyVT = VA.getValVT();
2176 // If this is x86-64, and we disabled SSE, we can't return FP values
2177 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2178 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2179 report_fatal_error("SSE register return with SSE disabled");
2182 // If we prefer to use the value in xmm registers, copy it out as f80 and
2183 // use a truncate to move it from fp stack reg to xmm reg.
2184 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2185 isScalarFPTypeInSSEReg(VA.getValVT()))
2188 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2189 CopyVT, InFlag).getValue(1);
2190 SDValue Val = Chain.getValue(0);
2192 if (CopyVT != VA.getValVT())
2193 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2194 // This truncation won't change the value.
2195 DAG.getIntPtrConstant(1));
2197 InFlag = Chain.getValue(2);
2198 InVals.push_back(Val);
2204 //===----------------------------------------------------------------------===//
2205 // C & StdCall & Fast Calling Convention implementation
2206 //===----------------------------------------------------------------------===//
2207 // StdCall calling convention seems to be standard for many Windows' API
2208 // routines and around. It differs from C calling convention just a little:
2209 // callee should clean up the stack, not caller. Symbols should be also
2210 // decorated in some fancy way :) It doesn't support any vector arguments.
2211 // For info on fast calling convention see Fast Calling Convention (tail call)
2212 // implementation LowerX86_32FastCCCallTo.
2214 /// CallIsStructReturn - Determines whether a call uses struct return
2216 enum StructReturnType {
2221 static StructReturnType
2222 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2224 return NotStructReturn;
2226 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2227 if (!Flags.isSRet())
2228 return NotStructReturn;
2229 if (Flags.isInReg())
2230 return RegStructReturn;
2231 return StackStructReturn;
2234 /// Determines whether a function uses struct return semantics.
2235 static StructReturnType
2236 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2238 return NotStructReturn;
2240 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2241 if (!Flags.isSRet())
2242 return NotStructReturn;
2243 if (Flags.isInReg())
2244 return RegStructReturn;
2245 return StackStructReturn;
2248 /// Make a copy of an aggregate at address specified by "Src" to address
2249 /// "Dst" with size and alignment information specified by the specific
2250 /// parameter attribute. The copy will be passed as a byval function parameter.
2252 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2253 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2255 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2257 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2258 /*isVolatile*/false, /*AlwaysInline=*/true,
2259 MachinePointerInfo(), MachinePointerInfo());
2262 /// Return true if the calling convention is one that
2263 /// supports tail call optimization.
2264 static bool IsTailCallConvention(CallingConv::ID CC) {
2265 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2266 CC == CallingConv::HiPE);
2269 /// \brief Return true if the calling convention is a C calling convention.
2270 static bool IsCCallConvention(CallingConv::ID CC) {
2271 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2272 CC == CallingConv::X86_64_SysV);
2275 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2276 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2280 CallingConv::ID CalleeCC = CS.getCallingConv();
2281 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2287 /// Return true if the function is being made into
2288 /// a tailcall target by changing its ABI.
2289 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2290 bool GuaranteedTailCallOpt) {
2291 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2295 X86TargetLowering::LowerMemArgument(SDValue Chain,
2296 CallingConv::ID CallConv,
2297 const SmallVectorImpl<ISD::InputArg> &Ins,
2298 SDLoc dl, SelectionDAG &DAG,
2299 const CCValAssign &VA,
2300 MachineFrameInfo *MFI,
2302 // Create the nodes corresponding to a load from this parameter slot.
2303 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2304 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2305 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2306 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2309 // If value is passed by pointer we have address passed instead of the value
2311 if (VA.getLocInfo() == CCValAssign::Indirect)
2312 ValVT = VA.getLocVT();
2314 ValVT = VA.getValVT();
2316 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2317 // changed with more analysis.
2318 // In case of tail call optimization mark all arguments mutable. Since they
2319 // could be overwritten by lowering of arguments in case of a tail call.
2320 if (Flags.isByVal()) {
2321 unsigned Bytes = Flags.getByValSize();
2322 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2323 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2324 return DAG.getFrameIndex(FI, getPointerTy());
2326 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2327 VA.getLocMemOffset(), isImmutable);
2328 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2329 return DAG.getLoad(ValVT, dl, Chain, FIN,
2330 MachinePointerInfo::getFixedStack(FI),
2331 false, false, false, 0);
2335 // FIXME: Get this from tablegen.
2336 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2337 const X86Subtarget *Subtarget) {
2338 assert(Subtarget->is64Bit());
2340 if (Subtarget->isCallingConvWin64(CallConv)) {
2341 static const MCPhysReg GPR64ArgRegsWin64[] = {
2342 X86::RCX, X86::RDX, X86::R8, X86::R9
2344 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2347 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2348 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2350 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2353 // FIXME: Get this from tablegen.
2354 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2355 CallingConv::ID CallConv,
2356 const X86Subtarget *Subtarget) {
2357 assert(Subtarget->is64Bit());
2358 if (Subtarget->isCallingConvWin64(CallConv)) {
2359 // The XMM registers which might contain var arg parameters are shadowed
2360 // in their paired GPR. So we only need to save the GPR to their home
2362 // TODO: __vectorcall will change this.
2366 const Function *Fn = MF.getFunction();
2367 bool NoImplicitFloatOps = Fn->getAttributes().
2368 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2369 assert(!(MF.getTarget().Options.UseSoftFloat && NoImplicitFloatOps) &&
2370 "SSE register cannot be used when SSE is disabled!");
2371 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2372 !Subtarget->hasSSE1())
2373 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2377 static const MCPhysReg XMMArgRegs64Bit[] = {
2378 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2379 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2381 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2385 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2386 CallingConv::ID CallConv,
2388 const SmallVectorImpl<ISD::InputArg> &Ins,
2391 SmallVectorImpl<SDValue> &InVals)
2393 MachineFunction &MF = DAG.getMachineFunction();
2394 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2396 const Function* Fn = MF.getFunction();
2397 if (Fn->hasExternalLinkage() &&
2398 Subtarget->isTargetCygMing() &&
2399 Fn->getName() == "main")
2400 FuncInfo->setForceFramePointer(true);
2402 MachineFrameInfo *MFI = MF.getFrameInfo();
2403 bool Is64Bit = Subtarget->is64Bit();
2404 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2406 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2407 "Var args not supported with calling convention fastcc, ghc or hipe");
2409 // Assign locations to all of the incoming arguments.
2410 SmallVector<CCValAssign, 16> ArgLocs;
2411 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2413 // Allocate shadow area for Win64
2415 CCInfo.AllocateStack(32, 8);
2417 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2419 unsigned LastVal = ~0U;
2421 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2422 CCValAssign &VA = ArgLocs[i];
2423 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2425 assert(VA.getValNo() != LastVal &&
2426 "Don't support value assigned to multiple locs yet");
2428 LastVal = VA.getValNo();
2430 if (VA.isRegLoc()) {
2431 EVT RegVT = VA.getLocVT();
2432 const TargetRegisterClass *RC;
2433 if (RegVT == MVT::i32)
2434 RC = &X86::GR32RegClass;
2435 else if (Is64Bit && RegVT == MVT::i64)
2436 RC = &X86::GR64RegClass;
2437 else if (RegVT == MVT::f32)
2438 RC = &X86::FR32RegClass;
2439 else if (RegVT == MVT::f64)
2440 RC = &X86::FR64RegClass;
2441 else if (RegVT.is512BitVector())
2442 RC = &X86::VR512RegClass;
2443 else if (RegVT.is256BitVector())
2444 RC = &X86::VR256RegClass;
2445 else if (RegVT.is128BitVector())
2446 RC = &X86::VR128RegClass;
2447 else if (RegVT == MVT::x86mmx)
2448 RC = &X86::VR64RegClass;
2449 else if (RegVT == MVT::i1)
2450 RC = &X86::VK1RegClass;
2451 else if (RegVT == MVT::v8i1)
2452 RC = &X86::VK8RegClass;
2453 else if (RegVT == MVT::v16i1)
2454 RC = &X86::VK16RegClass;
2455 else if (RegVT == MVT::v32i1)
2456 RC = &X86::VK32RegClass;
2457 else if (RegVT == MVT::v64i1)
2458 RC = &X86::VK64RegClass;
2460 llvm_unreachable("Unknown argument type!");
2462 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2463 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2465 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2466 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2468 if (VA.getLocInfo() == CCValAssign::SExt)
2469 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2470 DAG.getValueType(VA.getValVT()));
2471 else if (VA.getLocInfo() == CCValAssign::ZExt)
2472 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2473 DAG.getValueType(VA.getValVT()));
2474 else if (VA.getLocInfo() == CCValAssign::BCvt)
2475 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2477 if (VA.isExtInLoc()) {
2478 // Handle MMX values passed in XMM regs.
2479 if (RegVT.isVector())
2480 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2482 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2485 assert(VA.isMemLoc());
2486 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2489 // If value is passed via pointer - do a load.
2490 if (VA.getLocInfo() == CCValAssign::Indirect)
2491 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2492 MachinePointerInfo(), false, false, false, 0);
2494 InVals.push_back(ArgValue);
2497 if (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC()) {
2498 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2499 // The x86-64 ABIs require that for returning structs by value we copy
2500 // the sret argument into %rax/%eax (depending on ABI) for the return.
2501 // Win32 requires us to put the sret argument to %eax as well.
2502 // Save the argument into a virtual register so that we can access it
2503 // from the return points.
2504 if (Ins[i].Flags.isSRet()) {
2505 unsigned Reg = FuncInfo->getSRetReturnReg();
2507 MVT PtrTy = getPointerTy();
2508 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2509 FuncInfo->setSRetReturnReg(Reg);
2511 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2512 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2518 unsigned StackSize = CCInfo.getNextStackOffset();
2519 // Align stack specially for tail calls.
2520 if (FuncIsMadeTailCallSafe(CallConv,
2521 MF.getTarget().Options.GuaranteedTailCallOpt))
2522 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2524 // If the function takes variable number of arguments, make a frame index for
2525 // the start of the first vararg value... for expansion of llvm.va_start. We
2526 // can skip this if there are no va_start calls.
2527 if (MFI->hasVAStart() &&
2528 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2529 CallConv != CallingConv::X86_ThisCall))) {
2530 FuncInfo->setVarArgsFrameIndex(
2531 MFI->CreateFixedObject(1, StackSize, true));
2534 // 64-bit calling conventions support varargs and register parameters, so we
2535 // have to do extra work to spill them in the prologue or forward them to
2537 if (Is64Bit && isVarArg &&
2538 (MFI->hasVAStart() || MFI->hasMustTailInVarArgFunc())) {
2539 // Find the first unallocated argument registers.
2540 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2541 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2542 unsigned NumIntRegs =
2543 CCInfo.getFirstUnallocated(ArgGPRs.data(), ArgGPRs.size());
2544 unsigned NumXMMRegs =
2545 CCInfo.getFirstUnallocated(ArgXMMs.data(), ArgXMMs.size());
2546 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2547 "SSE register cannot be used when SSE is disabled!");
2549 // Gather all the live in physical registers.
2550 SmallVector<SDValue, 6> LiveGPRs;
2551 SmallVector<SDValue, 8> LiveXMMRegs;
2553 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2554 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2556 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2558 if (!ArgXMMs.empty()) {
2559 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2560 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2561 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2562 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2563 LiveXMMRegs.push_back(
2564 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2568 // Store them to the va_list returned by va_start.
2569 if (MFI->hasVAStart()) {
2571 const TargetFrameLowering &TFI = *MF.getSubtarget().getFrameLowering();
2572 // Get to the caller-allocated home save location. Add 8 to account
2573 // for the return address.
2574 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2575 FuncInfo->setRegSaveFrameIndex(
2576 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2577 // Fixup to set vararg frame on shadow area (4 x i64).
2579 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2581 // For X86-64, if there are vararg parameters that are passed via
2582 // registers, then we must store them to their spots on the stack so
2583 // they may be loaded by deferencing the result of va_next.
2584 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2585 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2586 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2587 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2590 // Store the integer parameter registers.
2591 SmallVector<SDValue, 8> MemOps;
2592 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2594 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2595 for (SDValue Val : LiveGPRs) {
2596 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2597 DAG.getIntPtrConstant(Offset));
2599 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2600 MachinePointerInfo::getFixedStack(
2601 FuncInfo->getRegSaveFrameIndex(), Offset),
2603 MemOps.push_back(Store);
2607 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2608 // Now store the XMM (fp + vector) parameter registers.
2609 SmallVector<SDValue, 12> SaveXMMOps;
2610 SaveXMMOps.push_back(Chain);
2611 SaveXMMOps.push_back(ALVal);
2612 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2613 FuncInfo->getRegSaveFrameIndex()));
2614 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2615 FuncInfo->getVarArgsFPOffset()));
2616 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2618 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2619 MVT::Other, SaveXMMOps));
2622 if (!MemOps.empty())
2623 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2625 // Add all GPRs, al, and XMMs to the list of forwards. We will add then
2626 // to the liveout set on a musttail call.
2627 assert(MFI->hasMustTailInVarArgFunc());
2628 auto &Forwards = FuncInfo->getForwardedMustTailRegParms();
2629 typedef X86MachineFunctionInfo::Forward Forward;
2631 for (unsigned I = 0, E = LiveGPRs.size(); I != E; ++I) {
2633 MF.getRegInfo().createVirtualRegister(&X86::GR64RegClass);
2634 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveGPRs[I]);
2635 Forwards.push_back(Forward(VReg, ArgGPRs[NumIntRegs + I], MVT::i64));
2638 if (!ArgXMMs.empty()) {
2640 MF.getRegInfo().createVirtualRegister(&X86::GR8RegClass);
2641 Chain = DAG.getCopyToReg(Chain, dl, ALVReg, ALVal);
2642 Forwards.push_back(Forward(ALVReg, X86::AL, MVT::i8));
2644 for (unsigned I = 0, E = LiveXMMRegs.size(); I != E; ++I) {
2646 MF.getRegInfo().createVirtualRegister(&X86::VR128RegClass);
2647 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveXMMRegs[I]);
2649 Forward(VReg, ArgXMMs[NumXMMRegs + I], MVT::v4f32));
2655 // Some CCs need callee pop.
2656 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2657 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2658 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2660 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2661 // If this is an sret function, the return should pop the hidden pointer.
2662 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2663 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2664 argsAreStructReturn(Ins) == StackStructReturn)
2665 FuncInfo->setBytesToPopOnReturn(4);
2669 // RegSaveFrameIndex is X86-64 only.
2670 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2671 if (CallConv == CallingConv::X86_FastCall ||
2672 CallConv == CallingConv::X86_ThisCall)
2673 // fastcc functions can't have varargs.
2674 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2677 FuncInfo->setArgumentStackSize(StackSize);
2683 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2684 SDValue StackPtr, SDValue Arg,
2685 SDLoc dl, SelectionDAG &DAG,
2686 const CCValAssign &VA,
2687 ISD::ArgFlagsTy Flags) const {
2688 unsigned LocMemOffset = VA.getLocMemOffset();
2689 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2690 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2691 if (Flags.isByVal())
2692 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2694 return DAG.getStore(Chain, dl, Arg, PtrOff,
2695 MachinePointerInfo::getStack(LocMemOffset),
2699 /// Emit a load of return address if tail call
2700 /// optimization is performed and it is required.
2702 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2703 SDValue &OutRetAddr, SDValue Chain,
2704 bool IsTailCall, bool Is64Bit,
2705 int FPDiff, SDLoc dl) const {
2706 // Adjust the Return address stack slot.
2707 EVT VT = getPointerTy();
2708 OutRetAddr = getReturnAddressFrameIndex(DAG);
2710 // Load the "old" Return address.
2711 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2712 false, false, false, 0);
2713 return SDValue(OutRetAddr.getNode(), 1);
2716 /// Emit a store of the return address if tail call
2717 /// optimization is performed and it is required (FPDiff!=0).
2718 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2719 SDValue Chain, SDValue RetAddrFrIdx,
2720 EVT PtrVT, unsigned SlotSize,
2721 int FPDiff, SDLoc dl) {
2722 // Store the return address to the appropriate stack slot.
2723 if (!FPDiff) return Chain;
2724 // Calculate the new stack slot for the return address.
2725 int NewReturnAddrFI =
2726 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2728 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2729 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2730 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2736 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2737 SmallVectorImpl<SDValue> &InVals) const {
2738 SelectionDAG &DAG = CLI.DAG;
2740 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2741 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2742 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2743 SDValue Chain = CLI.Chain;
2744 SDValue Callee = CLI.Callee;
2745 CallingConv::ID CallConv = CLI.CallConv;
2746 bool &isTailCall = CLI.IsTailCall;
2747 bool isVarArg = CLI.IsVarArg;
2749 MachineFunction &MF = DAG.getMachineFunction();
2750 bool Is64Bit = Subtarget->is64Bit();
2751 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2752 StructReturnType SR = callIsStructReturn(Outs);
2753 bool IsSibcall = false;
2754 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2756 if (MF.getTarget().Options.DisableTailCalls)
2759 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2761 // Force this to be a tail call. The verifier rules are enough to ensure
2762 // that we can lower this successfully without moving the return address
2765 } else if (isTailCall) {
2766 // Check if it's really possible to do a tail call.
2767 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2768 isVarArg, SR != NotStructReturn,
2769 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2770 Outs, OutVals, Ins, DAG);
2772 // Sibcalls are automatically detected tailcalls which do not require
2774 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2781 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2782 "Var args not supported with calling convention fastcc, ghc or hipe");
2784 // Analyze operands of the call, assigning locations to each operand.
2785 SmallVector<CCValAssign, 16> ArgLocs;
2786 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2788 // Allocate shadow area for Win64
2790 CCInfo.AllocateStack(32, 8);
2792 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2794 // Get a count of how many bytes are to be pushed on the stack.
2795 unsigned NumBytes = CCInfo.getNextStackOffset();
2797 // This is a sibcall. The memory operands are available in caller's
2798 // own caller's stack.
2800 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2801 IsTailCallConvention(CallConv))
2802 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2805 if (isTailCall && !IsSibcall && !IsMustTail) {
2806 // Lower arguments at fp - stackoffset + fpdiff.
2807 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2809 FPDiff = NumBytesCallerPushed - NumBytes;
2811 // Set the delta of movement of the returnaddr stackslot.
2812 // But only set if delta is greater than previous delta.
2813 if (FPDiff < X86Info->getTCReturnAddrDelta())
2814 X86Info->setTCReturnAddrDelta(FPDiff);
2817 unsigned NumBytesToPush = NumBytes;
2818 unsigned NumBytesToPop = NumBytes;
2820 // If we have an inalloca argument, all stack space has already been allocated
2821 // for us and be right at the top of the stack. We don't support multiple
2822 // arguments passed in memory when using inalloca.
2823 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2825 if (!ArgLocs.back().isMemLoc())
2826 report_fatal_error("cannot use inalloca attribute on a register "
2828 if (ArgLocs.back().getLocMemOffset() != 0)
2829 report_fatal_error("any parameter with the inalloca attribute must be "
2830 "the only memory argument");
2834 Chain = DAG.getCALLSEQ_START(
2835 Chain, DAG.getIntPtrConstant(NumBytesToPush, true), dl);
2837 SDValue RetAddrFrIdx;
2838 // Load return address for tail calls.
2839 if (isTailCall && FPDiff)
2840 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2841 Is64Bit, FPDiff, dl);
2843 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2844 SmallVector<SDValue, 8> MemOpChains;
2847 // Walk the register/memloc assignments, inserting copies/loads. In the case
2848 // of tail call optimization arguments are handle later.
2849 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
2850 DAG.getSubtarget().getRegisterInfo());
2851 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2852 // Skip inalloca arguments, they have already been written.
2853 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2854 if (Flags.isInAlloca())
2857 CCValAssign &VA = ArgLocs[i];
2858 EVT RegVT = VA.getLocVT();
2859 SDValue Arg = OutVals[i];
2860 bool isByVal = Flags.isByVal();
2862 // Promote the value if needed.
2863 switch (VA.getLocInfo()) {
2864 default: llvm_unreachable("Unknown loc info!");
2865 case CCValAssign::Full: break;
2866 case CCValAssign::SExt:
2867 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2869 case CCValAssign::ZExt:
2870 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2872 case CCValAssign::AExt:
2873 if (RegVT.is128BitVector()) {
2874 // Special case: passing MMX values in XMM registers.
2875 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2876 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2877 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2879 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2881 case CCValAssign::BCvt:
2882 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2884 case CCValAssign::Indirect: {
2885 // Store the argument.
2886 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2887 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2888 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2889 MachinePointerInfo::getFixedStack(FI),
2896 if (VA.isRegLoc()) {
2897 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2898 if (isVarArg && IsWin64) {
2899 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2900 // shadow reg if callee is a varargs function.
2901 unsigned ShadowReg = 0;
2902 switch (VA.getLocReg()) {
2903 case X86::XMM0: ShadowReg = X86::RCX; break;
2904 case X86::XMM1: ShadowReg = X86::RDX; break;
2905 case X86::XMM2: ShadowReg = X86::R8; break;
2906 case X86::XMM3: ShadowReg = X86::R9; break;
2909 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2911 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2912 assert(VA.isMemLoc());
2913 if (!StackPtr.getNode())
2914 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2916 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2917 dl, DAG, VA, Flags));
2921 if (!MemOpChains.empty())
2922 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2924 if (Subtarget->isPICStyleGOT()) {
2925 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2928 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2929 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2931 // If we are tail calling and generating PIC/GOT style code load the
2932 // address of the callee into ECX. The value in ecx is used as target of
2933 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2934 // for tail calls on PIC/GOT architectures. Normally we would just put the
2935 // address of GOT into ebx and then call target@PLT. But for tail calls
2936 // ebx would be restored (since ebx is callee saved) before jumping to the
2939 // Note: The actual moving to ECX is done further down.
2940 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2941 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2942 !G->getGlobal()->hasProtectedVisibility())
2943 Callee = LowerGlobalAddress(Callee, DAG);
2944 else if (isa<ExternalSymbolSDNode>(Callee))
2945 Callee = LowerExternalSymbol(Callee, DAG);
2949 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
2950 // From AMD64 ABI document:
2951 // For calls that may call functions that use varargs or stdargs
2952 // (prototype-less calls or calls to functions containing ellipsis (...) in
2953 // the declaration) %al is used as hidden argument to specify the number
2954 // of SSE registers used. The contents of %al do not need to match exactly
2955 // the number of registers, but must be an ubound on the number of SSE
2956 // registers used and is in the range 0 - 8 inclusive.
2958 // Count the number of XMM registers allocated.
2959 static const MCPhysReg XMMArgRegs[] = {
2960 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2961 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2963 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2964 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2965 && "SSE registers cannot be used when SSE is disabled");
2967 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2968 DAG.getConstant(NumXMMRegs, MVT::i8)));
2971 if (Is64Bit && isVarArg && IsMustTail) {
2972 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
2973 for (const auto &F : Forwards) {
2974 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2975 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
2979 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
2980 // don't need this because the eligibility check rejects calls that require
2981 // shuffling arguments passed in memory.
2982 if (!IsSibcall && isTailCall) {
2983 // Force all the incoming stack arguments to be loaded from the stack
2984 // before any new outgoing arguments are stored to the stack, because the
2985 // outgoing stack slots may alias the incoming argument stack slots, and
2986 // the alias isn't otherwise explicit. This is slightly more conservative
2987 // than necessary, because it means that each store effectively depends
2988 // on every argument instead of just those arguments it would clobber.
2989 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2991 SmallVector<SDValue, 8> MemOpChains2;
2994 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2995 CCValAssign &VA = ArgLocs[i];
2998 assert(VA.isMemLoc());
2999 SDValue Arg = OutVals[i];
3000 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3001 // Skip inalloca arguments. They don't require any work.
3002 if (Flags.isInAlloca())
3004 // Create frame index.
3005 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3006 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3007 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3008 FIN = DAG.getFrameIndex(FI, getPointerTy());
3010 if (Flags.isByVal()) {
3011 // Copy relative to framepointer.
3012 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
3013 if (!StackPtr.getNode())
3014 StackPtr = DAG.getCopyFromReg(Chain, dl,
3015 RegInfo->getStackRegister(),
3017 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
3019 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3023 // Store relative to framepointer.
3024 MemOpChains2.push_back(
3025 DAG.getStore(ArgChain, dl, Arg, FIN,
3026 MachinePointerInfo::getFixedStack(FI),
3031 if (!MemOpChains2.empty())
3032 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3034 // Store the return address to the appropriate stack slot.
3035 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3036 getPointerTy(), RegInfo->getSlotSize(),
3040 // Build a sequence of copy-to-reg nodes chained together with token chain
3041 // and flag operands which copy the outgoing args into registers.
3043 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3044 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3045 RegsToPass[i].second, InFlag);
3046 InFlag = Chain.getValue(1);
3049 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3050 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3051 // In the 64-bit large code model, we have to make all calls
3052 // through a register, since the call instruction's 32-bit
3053 // pc-relative offset may not be large enough to hold the whole
3055 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3056 // If the callee is a GlobalAddress node (quite common, every direct call
3057 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3060 // We should use extra load for direct calls to dllimported functions in
3062 const GlobalValue *GV = G->getGlobal();
3063 if (!GV->hasDLLImportStorageClass()) {
3064 unsigned char OpFlags = 0;
3065 bool ExtraLoad = false;
3066 unsigned WrapperKind = ISD::DELETED_NODE;
3068 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3069 // external symbols most go through the PLT in PIC mode. If the symbol
3070 // has hidden or protected visibility, or if it is static or local, then
3071 // we don't need to use the PLT - we can directly call it.
3072 if (Subtarget->isTargetELF() &&
3073 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3074 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3075 OpFlags = X86II::MO_PLT;
3076 } else if (Subtarget->isPICStyleStubAny() &&
3077 (GV->isDeclaration() || GV->isWeakForLinker()) &&
3078 (!Subtarget->getTargetTriple().isMacOSX() ||
3079 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3080 // PC-relative references to external symbols should go through $stub,
3081 // unless we're building with the leopard linker or later, which
3082 // automatically synthesizes these stubs.
3083 OpFlags = X86II::MO_DARWIN_STUB;
3084 } else if (Subtarget->isPICStyleRIPRel() &&
3085 isa<Function>(GV) &&
3086 cast<Function>(GV)->getAttributes().
3087 hasAttribute(AttributeSet::FunctionIndex,
3088 Attribute::NonLazyBind)) {
3089 // If the function is marked as non-lazy, generate an indirect call
3090 // which loads from the GOT directly. This avoids runtime overhead
3091 // at the cost of eager binding (and one extra byte of encoding).
3092 OpFlags = X86II::MO_GOTPCREL;
3093 WrapperKind = X86ISD::WrapperRIP;
3097 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
3098 G->getOffset(), OpFlags);
3100 // Add a wrapper if needed.
3101 if (WrapperKind != ISD::DELETED_NODE)
3102 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
3103 // Add extra indirection if needed.
3105 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
3106 MachinePointerInfo::getGOT(),
3107 false, false, false, 0);
3109 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3110 unsigned char OpFlags = 0;
3112 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3113 // external symbols should go through the PLT.
3114 if (Subtarget->isTargetELF() &&
3115 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3116 OpFlags = X86II::MO_PLT;
3117 } else if (Subtarget->isPICStyleStubAny() &&
3118 (!Subtarget->getTargetTriple().isMacOSX() ||
3119 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3120 // PC-relative references to external symbols should go through $stub,
3121 // unless we're building with the leopard linker or later, which
3122 // automatically synthesizes these stubs.
3123 OpFlags = X86II::MO_DARWIN_STUB;
3126 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
3128 } else if (Subtarget->isTarget64BitILP32() && Callee->getValueType(0) == MVT::i32) {
3129 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3130 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3133 // Returns a chain & a flag for retval copy to use.
3134 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3135 SmallVector<SDValue, 8> Ops;
3137 if (!IsSibcall && isTailCall) {
3138 Chain = DAG.getCALLSEQ_END(Chain,
3139 DAG.getIntPtrConstant(NumBytesToPop, true),
3140 DAG.getIntPtrConstant(0, true), InFlag, dl);
3141 InFlag = Chain.getValue(1);
3144 Ops.push_back(Chain);
3145 Ops.push_back(Callee);
3148 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
3150 // Add argument registers to the end of the list so that they are known live
3152 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3153 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3154 RegsToPass[i].second.getValueType()));
3156 // Add a register mask operand representing the call-preserved registers.
3157 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
3158 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3159 assert(Mask && "Missing call preserved mask for calling convention");
3160 Ops.push_back(DAG.getRegisterMask(Mask));
3162 if (InFlag.getNode())
3163 Ops.push_back(InFlag);
3167 //// If this is the first return lowered for this function, add the regs
3168 //// to the liveout set for the function.
3169 // This isn't right, although it's probably harmless on x86; liveouts
3170 // should be computed from returns not tail calls. Consider a void
3171 // function making a tail call to a function returning int.
3172 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3175 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3176 InFlag = Chain.getValue(1);
3178 // Create the CALLSEQ_END node.
3179 unsigned NumBytesForCalleeToPop;
3180 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3181 DAG.getTarget().Options.GuaranteedTailCallOpt))
3182 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3183 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3184 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3185 SR == StackStructReturn)
3186 // If this is a call to a struct-return function, the callee
3187 // pops the hidden struct pointer, so we have to push it back.
3188 // This is common for Darwin/X86, Linux & Mingw32 targets.
3189 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3190 NumBytesForCalleeToPop = 4;
3192 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3194 // Returns a flag for retval copy to use.
3196 Chain = DAG.getCALLSEQ_END(Chain,
3197 DAG.getIntPtrConstant(NumBytesToPop, true),
3198 DAG.getIntPtrConstant(NumBytesForCalleeToPop,
3201 InFlag = Chain.getValue(1);
3204 // Handle result values, copying them out of physregs into vregs that we
3206 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3207 Ins, dl, DAG, InVals);
3210 //===----------------------------------------------------------------------===//
3211 // Fast Calling Convention (tail call) implementation
3212 //===----------------------------------------------------------------------===//
3214 // Like std call, callee cleans arguments, convention except that ECX is
3215 // reserved for storing the tail called function address. Only 2 registers are
3216 // free for argument passing (inreg). Tail call optimization is performed
3218 // * tailcallopt is enabled
3219 // * caller/callee are fastcc
3220 // On X86_64 architecture with GOT-style position independent code only local
3221 // (within module) calls are supported at the moment.
3222 // To keep the stack aligned according to platform abi the function
3223 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3224 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3225 // If a tail called function callee has more arguments than the caller the
3226 // caller needs to make sure that there is room to move the RETADDR to. This is
3227 // achieved by reserving an area the size of the argument delta right after the
3228 // original RETADDR, but before the saved framepointer or the spilled registers
3229 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3241 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3242 /// for a 16 byte align requirement.
3244 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3245 SelectionDAG& DAG) const {
3246 MachineFunction &MF = DAG.getMachineFunction();
3247 const TargetMachine &TM = MF.getTarget();
3248 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3249 TM.getSubtargetImpl()->getRegisterInfo());
3250 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
3251 unsigned StackAlignment = TFI.getStackAlignment();
3252 uint64_t AlignMask = StackAlignment - 1;
3253 int64_t Offset = StackSize;
3254 unsigned SlotSize = RegInfo->getSlotSize();
3255 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3256 // Number smaller than 12 so just add the difference.
3257 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3259 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3260 Offset = ((~AlignMask) & Offset) + StackAlignment +
3261 (StackAlignment-SlotSize);
3266 /// MatchingStackOffset - Return true if the given stack call argument is
3267 /// already available in the same position (relatively) of the caller's
3268 /// incoming argument stack.
3270 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3271 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3272 const X86InstrInfo *TII) {
3273 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3275 if (Arg.getOpcode() == ISD::CopyFromReg) {
3276 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3277 if (!TargetRegisterInfo::isVirtualRegister(VR))
3279 MachineInstr *Def = MRI->getVRegDef(VR);
3282 if (!Flags.isByVal()) {
3283 if (!TII->isLoadFromStackSlot(Def, FI))
3286 unsigned Opcode = Def->getOpcode();
3287 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
3288 Def->getOperand(1).isFI()) {
3289 FI = Def->getOperand(1).getIndex();
3290 Bytes = Flags.getByValSize();
3294 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3295 if (Flags.isByVal())
3296 // ByVal argument is passed in as a pointer but it's now being
3297 // dereferenced. e.g.
3298 // define @foo(%struct.X* %A) {
3299 // tail call @bar(%struct.X* byval %A)
3302 SDValue Ptr = Ld->getBasePtr();
3303 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3306 FI = FINode->getIndex();
3307 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3308 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3309 FI = FINode->getIndex();
3310 Bytes = Flags.getByValSize();
3314 assert(FI != INT_MAX);
3315 if (!MFI->isFixedObjectIndex(FI))
3317 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3320 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3321 /// for tail call optimization. Targets which want to do tail call
3322 /// optimization should implement this function.
3324 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3325 CallingConv::ID CalleeCC,
3327 bool isCalleeStructRet,
3328 bool isCallerStructRet,
3330 const SmallVectorImpl<ISD::OutputArg> &Outs,
3331 const SmallVectorImpl<SDValue> &OutVals,
3332 const SmallVectorImpl<ISD::InputArg> &Ins,
3333 SelectionDAG &DAG) const {
3334 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3337 // If -tailcallopt is specified, make fastcc functions tail-callable.
3338 const MachineFunction &MF = DAG.getMachineFunction();
3339 const Function *CallerF = MF.getFunction();
3341 // If the function return type is x86_fp80 and the callee return type is not,
3342 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3343 // perform a tailcall optimization here.
3344 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3347 CallingConv::ID CallerCC = CallerF->getCallingConv();
3348 bool CCMatch = CallerCC == CalleeCC;
3349 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3350 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3352 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3353 if (IsTailCallConvention(CalleeCC) && CCMatch)
3358 // Look for obvious safe cases to perform tail call optimization that do not
3359 // require ABI changes. This is what gcc calls sibcall.
3361 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3362 // emit a special epilogue.
3363 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3364 DAG.getSubtarget().getRegisterInfo());
3365 if (RegInfo->needsStackRealignment(MF))
3368 // Also avoid sibcall optimization if either caller or callee uses struct
3369 // return semantics.
3370 if (isCalleeStructRet || isCallerStructRet)
3373 // An stdcall/thiscall caller is expected to clean up its arguments; the
3374 // callee isn't going to do that.
3375 // FIXME: this is more restrictive than needed. We could produce a tailcall
3376 // when the stack adjustment matches. For example, with a thiscall that takes
3377 // only one argument.
3378 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3379 CallerCC == CallingConv::X86_ThisCall))
3382 // Do not sibcall optimize vararg calls unless all arguments are passed via
3384 if (isVarArg && !Outs.empty()) {
3386 // Optimizing for varargs on Win64 is unlikely to be safe without
3387 // additional testing.
3388 if (IsCalleeWin64 || IsCallerWin64)
3391 SmallVector<CCValAssign, 16> ArgLocs;
3392 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3395 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3396 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3397 if (!ArgLocs[i].isRegLoc())
3401 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3402 // stack. Therefore, if it's not used by the call it is not safe to optimize
3403 // this into a sibcall.
3404 bool Unused = false;
3405 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3412 SmallVector<CCValAssign, 16> RVLocs;
3413 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3415 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3416 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3417 CCValAssign &VA = RVLocs[i];
3418 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3423 // If the calling conventions do not match, then we'd better make sure the
3424 // results are returned in the same way as what the caller expects.
3426 SmallVector<CCValAssign, 16> RVLocs1;
3427 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3429 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3431 SmallVector<CCValAssign, 16> RVLocs2;
3432 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3434 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3436 if (RVLocs1.size() != RVLocs2.size())
3438 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3439 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3441 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3443 if (RVLocs1[i].isRegLoc()) {
3444 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3447 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3453 // If the callee takes no arguments then go on to check the results of the
3455 if (!Outs.empty()) {
3456 // Check if stack adjustment is needed. For now, do not do this if any
3457 // argument is passed on the stack.
3458 SmallVector<CCValAssign, 16> ArgLocs;
3459 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3462 // Allocate shadow area for Win64
3464 CCInfo.AllocateStack(32, 8);
3466 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3467 if (CCInfo.getNextStackOffset()) {
3468 MachineFunction &MF = DAG.getMachineFunction();
3469 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3472 // Check if the arguments are already laid out in the right way as
3473 // the caller's fixed stack objects.
3474 MachineFrameInfo *MFI = MF.getFrameInfo();
3475 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3476 const X86InstrInfo *TII =
3477 static_cast<const X86InstrInfo *>(DAG.getSubtarget().getInstrInfo());
3478 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3479 CCValAssign &VA = ArgLocs[i];
3480 SDValue Arg = OutVals[i];
3481 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3482 if (VA.getLocInfo() == CCValAssign::Indirect)
3484 if (!VA.isRegLoc()) {
3485 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3492 // If the tailcall address may be in a register, then make sure it's
3493 // possible to register allocate for it. In 32-bit, the call address can
3494 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3495 // callee-saved registers are restored. These happen to be the same
3496 // registers used to pass 'inreg' arguments so watch out for those.
3497 if (!Subtarget->is64Bit() &&
3498 ((!isa<GlobalAddressSDNode>(Callee) &&
3499 !isa<ExternalSymbolSDNode>(Callee)) ||
3500 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3501 unsigned NumInRegs = 0;
3502 // In PIC we need an extra register to formulate the address computation
3504 unsigned MaxInRegs =
3505 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3507 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3508 CCValAssign &VA = ArgLocs[i];
3511 unsigned Reg = VA.getLocReg();
3514 case X86::EAX: case X86::EDX: case X86::ECX:
3515 if (++NumInRegs == MaxInRegs)
3527 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3528 const TargetLibraryInfo *libInfo) const {
3529 return X86::createFastISel(funcInfo, libInfo);
3532 //===----------------------------------------------------------------------===//
3533 // Other Lowering Hooks
3534 //===----------------------------------------------------------------------===//
3536 static bool MayFoldLoad(SDValue Op) {
3537 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3540 static bool MayFoldIntoStore(SDValue Op) {
3541 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3544 static bool isTargetShuffle(unsigned Opcode) {
3546 default: return false;
3547 case X86ISD::BLENDI:
3548 case X86ISD::PSHUFB:
3549 case X86ISD::PSHUFD:
3550 case X86ISD::PSHUFHW:
3551 case X86ISD::PSHUFLW:
3553 case X86ISD::PALIGNR:
3554 case X86ISD::MOVLHPS:
3555 case X86ISD::MOVLHPD:
3556 case X86ISD::MOVHLPS:
3557 case X86ISD::MOVLPS:
3558 case X86ISD::MOVLPD:
3559 case X86ISD::MOVSHDUP:
3560 case X86ISD::MOVSLDUP:
3561 case X86ISD::MOVDDUP:
3564 case X86ISD::UNPCKL:
3565 case X86ISD::UNPCKH:
3566 case X86ISD::VPERMILPI:
3567 case X86ISD::VPERM2X128:
3568 case X86ISD::VPERMI:
3573 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3574 SDValue V1, SelectionDAG &DAG) {
3576 default: llvm_unreachable("Unknown x86 shuffle node");
3577 case X86ISD::MOVSHDUP:
3578 case X86ISD::MOVSLDUP:
3579 case X86ISD::MOVDDUP:
3580 return DAG.getNode(Opc, dl, VT, V1);
3584 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3585 SDValue V1, unsigned TargetMask,
3586 SelectionDAG &DAG) {
3588 default: llvm_unreachable("Unknown x86 shuffle node");
3589 case X86ISD::PSHUFD:
3590 case X86ISD::PSHUFHW:
3591 case X86ISD::PSHUFLW:
3592 case X86ISD::VPERMILPI:
3593 case X86ISD::VPERMI:
3594 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3598 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3599 SDValue V1, SDValue V2, unsigned TargetMask,
3600 SelectionDAG &DAG) {
3602 default: llvm_unreachable("Unknown x86 shuffle node");
3603 case X86ISD::PALIGNR:
3604 case X86ISD::VALIGN:
3606 case X86ISD::VPERM2X128:
3607 return DAG.getNode(Opc, dl, VT, V1, V2,
3608 DAG.getConstant(TargetMask, MVT::i8));
3612 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3613 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3615 default: llvm_unreachable("Unknown x86 shuffle node");
3616 case X86ISD::MOVLHPS:
3617 case X86ISD::MOVLHPD:
3618 case X86ISD::MOVHLPS:
3619 case X86ISD::MOVLPS:
3620 case X86ISD::MOVLPD:
3623 case X86ISD::UNPCKL:
3624 case X86ISD::UNPCKH:
3625 return DAG.getNode(Opc, dl, VT, V1, V2);
3629 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3630 MachineFunction &MF = DAG.getMachineFunction();
3631 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3632 DAG.getSubtarget().getRegisterInfo());
3633 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3634 int ReturnAddrIndex = FuncInfo->getRAIndex();
3636 if (ReturnAddrIndex == 0) {
3637 // Set up a frame object for the return address.
3638 unsigned SlotSize = RegInfo->getSlotSize();
3639 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3642 FuncInfo->setRAIndex(ReturnAddrIndex);
3645 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3648 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3649 bool hasSymbolicDisplacement) {
3650 // Offset should fit into 32 bit immediate field.
3651 if (!isInt<32>(Offset))
3654 // If we don't have a symbolic displacement - we don't have any extra
3656 if (!hasSymbolicDisplacement)
3659 // FIXME: Some tweaks might be needed for medium code model.
3660 if (M != CodeModel::Small && M != CodeModel::Kernel)
3663 // For small code model we assume that latest object is 16MB before end of 31
3664 // bits boundary. We may also accept pretty large negative constants knowing
3665 // that all objects are in the positive half of address space.
3666 if (M == CodeModel::Small && Offset < 16*1024*1024)
3669 // For kernel code model we know that all object resist in the negative half
3670 // of 32bits address space. We may not accept negative offsets, since they may
3671 // be just off and we may accept pretty large positive ones.
3672 if (M == CodeModel::Kernel && Offset >= 0)
3678 /// isCalleePop - Determines whether the callee is required to pop its
3679 /// own arguments. Callee pop is necessary to support tail calls.
3680 bool X86::isCalleePop(CallingConv::ID CallingConv,
3681 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3682 switch (CallingConv) {
3685 case CallingConv::X86_StdCall:
3686 case CallingConv::X86_FastCall:
3687 case CallingConv::X86_ThisCall:
3689 case CallingConv::Fast:
3690 case CallingConv::GHC:
3691 case CallingConv::HiPE:
3698 /// \brief Return true if the condition is an unsigned comparison operation.
3699 static bool isX86CCUnsigned(unsigned X86CC) {
3701 default: llvm_unreachable("Invalid integer condition!");
3702 case X86::COND_E: return true;
3703 case X86::COND_G: return false;
3704 case X86::COND_GE: return false;
3705 case X86::COND_L: return false;
3706 case X86::COND_LE: return false;
3707 case X86::COND_NE: return true;
3708 case X86::COND_B: return true;
3709 case X86::COND_A: return true;
3710 case X86::COND_BE: return true;
3711 case X86::COND_AE: return true;
3713 llvm_unreachable("covered switch fell through?!");
3716 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3717 /// specific condition code, returning the condition code and the LHS/RHS of the
3718 /// comparison to make.
3719 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3720 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3722 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3723 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3724 // X > -1 -> X == 0, jump !sign.
3725 RHS = DAG.getConstant(0, RHS.getValueType());
3726 return X86::COND_NS;
3728 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3729 // X < 0 -> X == 0, jump on sign.
3732 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3734 RHS = DAG.getConstant(0, RHS.getValueType());
3735 return X86::COND_LE;
3739 switch (SetCCOpcode) {
3740 default: llvm_unreachable("Invalid integer condition!");
3741 case ISD::SETEQ: return X86::COND_E;
3742 case ISD::SETGT: return X86::COND_G;
3743 case ISD::SETGE: return X86::COND_GE;
3744 case ISD::SETLT: return X86::COND_L;
3745 case ISD::SETLE: return X86::COND_LE;
3746 case ISD::SETNE: return X86::COND_NE;
3747 case ISD::SETULT: return X86::COND_B;
3748 case ISD::SETUGT: return X86::COND_A;
3749 case ISD::SETULE: return X86::COND_BE;
3750 case ISD::SETUGE: return X86::COND_AE;
3754 // First determine if it is required or is profitable to flip the operands.
3756 // If LHS is a foldable load, but RHS is not, flip the condition.
3757 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3758 !ISD::isNON_EXTLoad(RHS.getNode())) {
3759 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3760 std::swap(LHS, RHS);
3763 switch (SetCCOpcode) {
3769 std::swap(LHS, RHS);
3773 // On a floating point condition, the flags are set as follows:
3775 // 0 | 0 | 0 | X > Y
3776 // 0 | 0 | 1 | X < Y
3777 // 1 | 0 | 0 | X == Y
3778 // 1 | 1 | 1 | unordered
3779 switch (SetCCOpcode) {
3780 default: llvm_unreachable("Condcode should be pre-legalized away");
3782 case ISD::SETEQ: return X86::COND_E;
3783 case ISD::SETOLT: // flipped
3785 case ISD::SETGT: return X86::COND_A;
3786 case ISD::SETOLE: // flipped
3788 case ISD::SETGE: return X86::COND_AE;
3789 case ISD::SETUGT: // flipped
3791 case ISD::SETLT: return X86::COND_B;
3792 case ISD::SETUGE: // flipped
3794 case ISD::SETLE: return X86::COND_BE;
3796 case ISD::SETNE: return X86::COND_NE;
3797 case ISD::SETUO: return X86::COND_P;
3798 case ISD::SETO: return X86::COND_NP;
3800 case ISD::SETUNE: return X86::COND_INVALID;
3804 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3805 /// code. Current x86 isa includes the following FP cmov instructions:
3806 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3807 static bool hasFPCMov(unsigned X86CC) {
3823 /// isFPImmLegal - Returns true if the target can instruction select the
3824 /// specified FP immediate natively. If false, the legalizer will
3825 /// materialize the FP immediate as a load from a constant pool.
3826 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3827 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3828 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3834 /// \brief Returns true if it is beneficial to convert a load of a constant
3835 /// to just the constant itself.
3836 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3838 assert(Ty->isIntegerTy());
3840 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3841 if (BitSize == 0 || BitSize > 64)
3846 bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT,
3847 unsigned Index) const {
3848 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
3851 return (Index == 0 || Index == ResVT.getVectorNumElements());
3854 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3855 /// the specified range (L, H].
3856 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3857 return (Val < 0) || (Val >= Low && Val < Hi);
3860 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3861 /// specified value.
3862 static bool isUndefOrEqual(int Val, int CmpVal) {
3863 return (Val < 0 || Val == CmpVal);
3866 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3867 /// from position Pos and ending in Pos+Size, falls within the specified
3868 /// sequential range (L, L+Pos]. or is undef.
3869 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3870 unsigned Pos, unsigned Size, int Low) {
3871 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3872 if (!isUndefOrEqual(Mask[i], Low))
3877 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3878 /// is suitable for input to PSHUFD. That is, it doesn't reference the other
3879 /// operand - by default will match for first operand.
3880 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT,
3881 bool TestSecondOperand = false) {
3882 if (VT != MVT::v4f32 && VT != MVT::v4i32 &&
3883 VT != MVT::v2f64 && VT != MVT::v2i64)
3886 unsigned NumElems = VT.getVectorNumElements();
3887 unsigned Lo = TestSecondOperand ? NumElems : 0;
3888 unsigned Hi = Lo + NumElems;
3890 for (unsigned i = 0; i < NumElems; ++i)
3891 if (!isUndefOrInRange(Mask[i], (int)Lo, (int)Hi))
3897 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3898 /// is suitable for input to PSHUFHW.
3899 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3900 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3903 // Lower quadword copied in order or undef.
3904 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3907 // Upper quadword shuffled.
3908 for (unsigned i = 4; i != 8; ++i)
3909 if (!isUndefOrInRange(Mask[i], 4, 8))
3912 if (VT == MVT::v16i16) {
3913 // Lower quadword copied in order or undef.
3914 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3917 // Upper quadword shuffled.
3918 for (unsigned i = 12; i != 16; ++i)
3919 if (!isUndefOrInRange(Mask[i], 12, 16))
3926 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3927 /// is suitable for input to PSHUFLW.
3928 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3929 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3932 // Upper quadword copied in order.
3933 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3936 // Lower quadword shuffled.
3937 for (unsigned i = 0; i != 4; ++i)
3938 if (!isUndefOrInRange(Mask[i], 0, 4))
3941 if (VT == MVT::v16i16) {
3942 // Upper quadword copied in order.
3943 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3946 // Lower quadword shuffled.
3947 for (unsigned i = 8; i != 12; ++i)
3948 if (!isUndefOrInRange(Mask[i], 8, 12))
3955 /// \brief Return true if the mask specifies a shuffle of elements that is
3956 /// suitable for input to intralane (palignr) or interlane (valign) vector
3958 static bool isAlignrMask(ArrayRef<int> Mask, MVT VT, bool InterLane) {
3959 unsigned NumElts = VT.getVectorNumElements();
3960 unsigned NumLanes = InterLane ? 1: VT.getSizeInBits()/128;
3961 unsigned NumLaneElts = NumElts/NumLanes;
3963 // Do not handle 64-bit element shuffles with palignr.
3964 if (NumLaneElts == 2)
3967 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3969 for (i = 0; i != NumLaneElts; ++i) {
3974 // Lane is all undef, go to next lane
3975 if (i == NumLaneElts)
3978 int Start = Mask[i+l];
3980 // Make sure its in this lane in one of the sources
3981 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3982 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3985 // If not lane 0, then we must match lane 0
3986 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3989 // Correct second source to be contiguous with first source
3990 if (Start >= (int)NumElts)
3991 Start -= NumElts - NumLaneElts;
3993 // Make sure we're shifting in the right direction.
3994 if (Start <= (int)(i+l))
3999 // Check the rest of the elements to see if they are consecutive.
4000 for (++i; i != NumLaneElts; ++i) {
4001 int Idx = Mask[i+l];
4003 // Make sure its in this lane
4004 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
4005 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
4008 // If not lane 0, then we must match lane 0
4009 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
4012 if (Idx >= (int)NumElts)
4013 Idx -= NumElts - NumLaneElts;
4015 if (!isUndefOrEqual(Idx, Start+i))
4024 /// \brief Return true if the node specifies a shuffle of elements that is
4025 /// suitable for input to PALIGNR.
4026 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
4027 const X86Subtarget *Subtarget) {
4028 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
4029 (VT.is256BitVector() && !Subtarget->hasInt256()) ||
4030 VT.is512BitVector())
4031 // FIXME: Add AVX512BW.
4034 return isAlignrMask(Mask, VT, false);
4037 /// \brief Return true if the node specifies a shuffle of elements that is
4038 /// suitable for input to VALIGN.
4039 static bool isVALIGNMask(ArrayRef<int> Mask, MVT VT,
4040 const X86Subtarget *Subtarget) {
4041 // FIXME: Add AVX512VL.
4042 if (!VT.is512BitVector() || !Subtarget->hasAVX512())
4044 return isAlignrMask(Mask, VT, true);
4047 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
4048 /// the two vector operands have swapped position.
4049 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
4050 unsigned NumElems) {
4051 for (unsigned i = 0; i != NumElems; ++i) {
4055 else if (idx < (int)NumElems)
4056 Mask[i] = idx + NumElems;
4058 Mask[i] = idx - NumElems;
4062 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
4063 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
4064 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
4065 /// reverse of what x86 shuffles want.
4066 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
4068 unsigned NumElems = VT.getVectorNumElements();
4069 unsigned NumLanes = VT.getSizeInBits()/128;
4070 unsigned NumLaneElems = NumElems/NumLanes;
4072 if (NumLaneElems != 2 && NumLaneElems != 4)
4075 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4076 bool symetricMaskRequired =
4077 (VT.getSizeInBits() >= 256) && (EltSize == 32);
4079 // VSHUFPSY divides the resulting vector into 4 chunks.
4080 // The sources are also splitted into 4 chunks, and each destination
4081 // chunk must come from a different source chunk.
4083 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
4084 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
4086 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
4087 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
4089 // VSHUFPDY divides the resulting vector into 4 chunks.
4090 // The sources are also splitted into 4 chunks, and each destination
4091 // chunk must come from a different source chunk.
4093 // SRC1 => X3 X2 X1 X0
4094 // SRC2 => Y3 Y2 Y1 Y0
4096 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
4098 SmallVector<int, 4> MaskVal(NumLaneElems, -1);
4099 unsigned HalfLaneElems = NumLaneElems/2;
4100 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
4101 for (unsigned i = 0; i != NumLaneElems; ++i) {
4102 int Idx = Mask[i+l];
4103 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
4104 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
4106 // For VSHUFPSY, the mask of the second half must be the same as the
4107 // first but with the appropriate offsets. This works in the same way as
4108 // VPERMILPS works with masks.
4109 if (!symetricMaskRequired || Idx < 0)
4111 if (MaskVal[i] < 0) {
4112 MaskVal[i] = Idx - l;
4115 if ((signed)(Idx - l) != MaskVal[i])
4123 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
4124 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
4125 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
4126 if (!VT.is128BitVector())
4129 unsigned NumElems = VT.getVectorNumElements();
4134 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
4135 return isUndefOrEqual(Mask[0], 6) &&
4136 isUndefOrEqual(Mask[1], 7) &&
4137 isUndefOrEqual(Mask[2], 2) &&
4138 isUndefOrEqual(Mask[3], 3);
4141 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
4142 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
4144 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
4145 if (!VT.is128BitVector())
4148 unsigned NumElems = VT.getVectorNumElements();
4153 return isUndefOrEqual(Mask[0], 2) &&
4154 isUndefOrEqual(Mask[1], 3) &&
4155 isUndefOrEqual(Mask[2], 2) &&
4156 isUndefOrEqual(Mask[3], 3);
4159 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
4160 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
4161 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
4162 if (!VT.is128BitVector())
4165 unsigned NumElems = VT.getVectorNumElements();
4167 if (NumElems != 2 && NumElems != 4)
4170 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4171 if (!isUndefOrEqual(Mask[i], i + NumElems))
4174 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4175 if (!isUndefOrEqual(Mask[i], i))
4181 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
4182 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
4183 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
4184 if (!VT.is128BitVector())
4187 unsigned NumElems = VT.getVectorNumElements();
4189 if (NumElems != 2 && NumElems != 4)
4192 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4193 if (!isUndefOrEqual(Mask[i], i))
4196 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4197 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
4203 /// isINSERTPSMask - Return true if the specified VECTOR_SHUFFLE operand
4204 /// specifies a shuffle of elements that is suitable for input to INSERTPS.
4205 /// i. e: If all but one element come from the same vector.
4206 static bool isINSERTPSMask(ArrayRef<int> Mask, MVT VT) {
4207 // TODO: Deal with AVX's VINSERTPS
4208 if (!VT.is128BitVector() || (VT != MVT::v4f32 && VT != MVT::v4i32))
4211 unsigned CorrectPosV1 = 0;
4212 unsigned CorrectPosV2 = 0;
4213 for (int i = 0, e = (int)VT.getVectorNumElements(); i != e; ++i) {
4214 if (Mask[i] == -1) {
4222 else if (Mask[i] == i + 4)
4226 if (CorrectPosV1 == 3 || CorrectPosV2 == 3)
4227 // We have 3 elements (undefs count as elements from any vector) from one
4228 // vector, and one from another.
4235 // Some special combinations that can be optimized.
4238 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
4239 SelectionDAG &DAG) {
4240 MVT VT = SVOp->getSimpleValueType(0);
4243 if (VT != MVT::v8i32 && VT != MVT::v8f32)
4246 ArrayRef<int> Mask = SVOp->getMask();
4248 // These are the special masks that may be optimized.
4249 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
4250 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
4251 bool MatchEvenMask = true;
4252 bool MatchOddMask = true;
4253 for (int i=0; i<8; ++i) {
4254 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
4255 MatchEvenMask = false;
4256 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
4257 MatchOddMask = false;
4260 if (!MatchEvenMask && !MatchOddMask)
4263 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
4265 SDValue Op0 = SVOp->getOperand(0);
4266 SDValue Op1 = SVOp->getOperand(1);
4268 if (MatchEvenMask) {
4269 // Shift the second operand right to 32 bits.
4270 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
4271 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
4273 // Shift the first operand left to 32 bits.
4274 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
4275 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
4277 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
4278 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
4281 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
4282 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
4283 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
4284 bool HasInt256, bool V2IsSplat = false) {
4286 assert(VT.getSizeInBits() >= 128 &&
4287 "Unsupported vector type for unpckl");
4289 unsigned NumElts = VT.getVectorNumElements();
4290 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4291 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4294 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4295 "Unsupported vector type for unpckh");
4297 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4298 unsigned NumLanes = VT.getSizeInBits()/128;
4299 unsigned NumLaneElts = NumElts/NumLanes;
4301 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4302 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4303 int BitI = Mask[l+i];
4304 int BitI1 = Mask[l+i+1];
4305 if (!isUndefOrEqual(BitI, j))
4308 if (!isUndefOrEqual(BitI1, NumElts))
4311 if (!isUndefOrEqual(BitI1, j + NumElts))
4320 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
4321 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
4322 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
4323 bool HasInt256, bool V2IsSplat = false) {
4324 assert(VT.getSizeInBits() >= 128 &&
4325 "Unsupported vector type for unpckh");
4327 unsigned NumElts = VT.getVectorNumElements();
4328 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4329 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4332 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4333 "Unsupported vector type for unpckh");
4335 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4336 unsigned NumLanes = VT.getSizeInBits()/128;
4337 unsigned NumLaneElts = NumElts/NumLanes;
4339 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4340 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4341 int BitI = Mask[l+i];
4342 int BitI1 = Mask[l+i+1];
4343 if (!isUndefOrEqual(BitI, j))
4346 if (isUndefOrEqual(BitI1, NumElts))
4349 if (!isUndefOrEqual(BitI1, j+NumElts))
4357 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
4358 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
4360 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4361 unsigned NumElts = VT.getVectorNumElements();
4362 bool Is256BitVec = VT.is256BitVector();
4364 if (VT.is512BitVector())
4366 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4367 "Unsupported vector type for unpckh");
4369 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
4370 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4373 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
4374 // FIXME: Need a better way to get rid of this, there's no latency difference
4375 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
4376 // the former later. We should also remove the "_undef" special mask.
4377 if (NumElts == 4 && Is256BitVec)
4380 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4381 // independently on 128-bit lanes.
4382 unsigned NumLanes = VT.getSizeInBits()/128;
4383 unsigned NumLaneElts = NumElts/NumLanes;
4385 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4386 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4387 int BitI = Mask[l+i];
4388 int BitI1 = Mask[l+i+1];
4390 if (!isUndefOrEqual(BitI, j))
4392 if (!isUndefOrEqual(BitI1, j))
4400 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
4401 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
4403 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4404 unsigned NumElts = VT.getVectorNumElements();
4406 if (VT.is512BitVector())
4409 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4410 "Unsupported vector type for unpckh");
4412 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4413 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4416 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4417 // independently on 128-bit lanes.
4418 unsigned NumLanes = VT.getSizeInBits()/128;
4419 unsigned NumLaneElts = NumElts/NumLanes;
4421 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4422 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4423 int BitI = Mask[l+i];
4424 int BitI1 = Mask[l+i+1];
4425 if (!isUndefOrEqual(BitI, j))
4427 if (!isUndefOrEqual(BitI1, j))
4434 // Match for INSERTI64x4 INSERTF64x4 instructions (src0[0], src1[0]) or
4435 // (src1[0], src0[1]), manipulation with 256-bit sub-vectors
4436 static bool isINSERT64x4Mask(ArrayRef<int> Mask, MVT VT, unsigned int *Imm) {
4437 if (!VT.is512BitVector())
4440 unsigned NumElts = VT.getVectorNumElements();
4441 unsigned HalfSize = NumElts/2;
4442 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, 0)) {
4443 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, NumElts)) {
4448 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, NumElts)) {
4449 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, HalfSize)) {
4457 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4458 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4459 /// MOVSD, and MOVD, i.e. setting the lowest element.
4460 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4461 if (VT.getVectorElementType().getSizeInBits() < 32)
4463 if (!VT.is128BitVector())
4466 unsigned NumElts = VT.getVectorNumElements();
4468 if (!isUndefOrEqual(Mask[0], NumElts))
4471 for (unsigned i = 1; i != NumElts; ++i)
4472 if (!isUndefOrEqual(Mask[i], i))
4478 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4479 /// as permutations between 128-bit chunks or halves. As an example: this
4481 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4482 /// The first half comes from the second half of V1 and the second half from the
4483 /// the second half of V2.
4484 static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4485 if (!HasFp256 || !VT.is256BitVector())
4488 // The shuffle result is divided into half A and half B. In total the two
4489 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4490 // B must come from C, D, E or F.
4491 unsigned HalfSize = VT.getVectorNumElements()/2;
4492 bool MatchA = false, MatchB = false;
4494 // Check if A comes from one of C, D, E, F.
4495 for (unsigned Half = 0; Half != 4; ++Half) {
4496 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4502 // Check if B comes from one of C, D, E, F.
4503 for (unsigned Half = 0; Half != 4; ++Half) {
4504 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4510 return MatchA && MatchB;
4513 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4514 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4515 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4516 MVT VT = SVOp->getSimpleValueType(0);
4518 unsigned HalfSize = VT.getVectorNumElements()/2;
4520 unsigned FstHalf = 0, SndHalf = 0;
4521 for (unsigned i = 0; i < HalfSize; ++i) {
4522 if (SVOp->getMaskElt(i) > 0) {
4523 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4527 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4528 if (SVOp->getMaskElt(i) > 0) {
4529 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4534 return (FstHalf | (SndHalf << 4));
4537 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4538 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
4539 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4543 unsigned NumElts = VT.getVectorNumElements();
4545 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4546 for (unsigned i = 0; i != NumElts; ++i) {
4549 Imm8 |= Mask[i] << (i*2);
4554 unsigned LaneSize = 4;
4555 SmallVector<int, 4> MaskVal(LaneSize, -1);
4557 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4558 for (unsigned i = 0; i != LaneSize; ++i) {
4559 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4563 if (MaskVal[i] < 0) {
4564 MaskVal[i] = Mask[i+l] - l;
4565 Imm8 |= MaskVal[i] << (i*2);
4568 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4575 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4576 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4577 /// Note that VPERMIL mask matching is different depending whether theunderlying
4578 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4579 /// to the same elements of the low, but to the higher half of the source.
4580 /// In VPERMILPD the two lanes could be shuffled independently of each other
4581 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4582 static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
4583 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4584 if (VT.getSizeInBits() < 256 || EltSize < 32)
4586 bool symetricMaskRequired = (EltSize == 32);
4587 unsigned NumElts = VT.getVectorNumElements();
4589 unsigned NumLanes = VT.getSizeInBits()/128;
4590 unsigned LaneSize = NumElts/NumLanes;
4591 // 2 or 4 elements in one lane
4593 SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
4594 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4595 for (unsigned i = 0; i != LaneSize; ++i) {
4596 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4598 if (symetricMaskRequired) {
4599 if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) {
4600 ExpectedMaskVal[i] = Mask[i+l] - l;
4603 if (!isUndefOrEqual(Mask[i+l], ExpectedMaskVal[i]+l))
4611 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4612 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4613 /// element of vector 2 and the other elements to come from vector 1 in order.
4614 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4615 bool V2IsSplat = false, bool V2IsUndef = false) {
4616 if (!VT.is128BitVector())
4619 unsigned NumOps = VT.getVectorNumElements();
4620 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4623 if (!isUndefOrEqual(Mask[0], 0))
4626 for (unsigned i = 1; i != NumOps; ++i)
4627 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4628 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4629 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4635 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4636 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4637 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4638 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4639 const X86Subtarget *Subtarget) {
4640 if (!Subtarget->hasSSE3())
4643 unsigned NumElems = VT.getVectorNumElements();
4645 if ((VT.is128BitVector() && NumElems != 4) ||
4646 (VT.is256BitVector() && NumElems != 8) ||
4647 (VT.is512BitVector() && NumElems != 16))
4650 // "i+1" is the value the indexed mask element must have
4651 for (unsigned i = 0; i != NumElems; i += 2)
4652 if (!isUndefOrEqual(Mask[i], i+1) ||
4653 !isUndefOrEqual(Mask[i+1], i+1))
4659 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4660 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4661 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4662 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4663 const X86Subtarget *Subtarget) {
4664 if (!Subtarget->hasSSE3())
4667 unsigned NumElems = VT.getVectorNumElements();
4669 if ((VT.is128BitVector() && NumElems != 4) ||
4670 (VT.is256BitVector() && NumElems != 8) ||
4671 (VT.is512BitVector() && NumElems != 16))
4674 // "i" is the value the indexed mask element must have
4675 for (unsigned i = 0; i != NumElems; i += 2)
4676 if (!isUndefOrEqual(Mask[i], i) ||
4677 !isUndefOrEqual(Mask[i+1], i))
4683 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4684 /// specifies a shuffle of elements that is suitable for input to 256-bit
4685 /// version of MOVDDUP.
4686 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4687 if (!HasFp256 || !VT.is256BitVector())
4690 unsigned NumElts = VT.getVectorNumElements();
4694 for (unsigned i = 0; i != NumElts/2; ++i)
4695 if (!isUndefOrEqual(Mask[i], 0))
4697 for (unsigned i = NumElts/2; i != NumElts; ++i)
4698 if (!isUndefOrEqual(Mask[i], NumElts/2))
4703 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4704 /// specifies a shuffle of elements that is suitable for input to 128-bit
4705 /// version of MOVDDUP.
4706 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4707 if (!VT.is128BitVector())
4710 unsigned e = VT.getVectorNumElements() / 2;
4711 for (unsigned i = 0; i != e; ++i)
4712 if (!isUndefOrEqual(Mask[i], i))
4714 for (unsigned i = 0; i != e; ++i)
4715 if (!isUndefOrEqual(Mask[e+i], i))
4720 /// isVEXTRACTIndex - Return true if the specified
4721 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4722 /// suitable for instruction that extract 128 or 256 bit vectors
4723 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4724 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4725 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4728 // The index should be aligned on a vecWidth-bit boundary.
4730 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4732 MVT VT = N->getSimpleValueType(0);
4733 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4734 bool Result = (Index * ElSize) % vecWidth == 0;
4739 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4740 /// operand specifies a subvector insert that is suitable for input to
4741 /// insertion of 128 or 256-bit subvectors
4742 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4743 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4744 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4746 // The index should be aligned on a vecWidth-bit boundary.
4748 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4750 MVT VT = N->getSimpleValueType(0);
4751 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4752 bool Result = (Index * ElSize) % vecWidth == 0;
4757 bool X86::isVINSERT128Index(SDNode *N) {
4758 return isVINSERTIndex(N, 128);
4761 bool X86::isVINSERT256Index(SDNode *N) {
4762 return isVINSERTIndex(N, 256);
4765 bool X86::isVEXTRACT128Index(SDNode *N) {
4766 return isVEXTRACTIndex(N, 128);
4769 bool X86::isVEXTRACT256Index(SDNode *N) {
4770 return isVEXTRACTIndex(N, 256);
4773 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4774 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4775 /// Handles 128-bit and 256-bit.
4776 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4777 MVT VT = N->getSimpleValueType(0);
4779 assert((VT.getSizeInBits() >= 128) &&
4780 "Unsupported vector type for PSHUF/SHUFP");
4782 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4783 // independently on 128-bit lanes.
4784 unsigned NumElts = VT.getVectorNumElements();
4785 unsigned NumLanes = VT.getSizeInBits()/128;
4786 unsigned NumLaneElts = NumElts/NumLanes;
4788 assert((NumLaneElts == 2 || NumLaneElts == 4 || NumLaneElts == 8) &&
4789 "Only supports 2, 4 or 8 elements per lane");
4791 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0;
4793 for (unsigned i = 0; i != NumElts; ++i) {
4794 int Elt = N->getMaskElt(i);
4795 if (Elt < 0) continue;
4796 Elt &= NumLaneElts - 1;
4797 unsigned ShAmt = (i << Shift) % 8;
4798 Mask |= Elt << ShAmt;
4804 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4805 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4806 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4807 MVT VT = N->getSimpleValueType(0);
4809 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4810 "Unsupported vector type for PSHUFHW");
4812 unsigned NumElts = VT.getVectorNumElements();
4815 for (unsigned l = 0; l != NumElts; l += 8) {
4816 // 8 nodes per lane, but we only care about the last 4.
4817 for (unsigned i = 0; i < 4; ++i) {
4818 int Elt = N->getMaskElt(l+i+4);
4819 if (Elt < 0) continue;
4820 Elt &= 0x3; // only 2-bits.
4821 Mask |= Elt << (i * 2);
4828 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4829 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4830 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4831 MVT VT = N->getSimpleValueType(0);
4833 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4834 "Unsupported vector type for PSHUFHW");
4836 unsigned NumElts = VT.getVectorNumElements();
4839 for (unsigned l = 0; l != NumElts; l += 8) {
4840 // 8 nodes per lane, but we only care about the first 4.
4841 for (unsigned i = 0; i < 4; ++i) {
4842 int Elt = N->getMaskElt(l+i);
4843 if (Elt < 0) continue;
4844 Elt &= 0x3; // only 2-bits
4845 Mask |= Elt << (i * 2);
4852 /// \brief Return the appropriate immediate to shuffle the specified
4853 /// VECTOR_SHUFFLE mask with the PALIGNR (if InterLane is false) or with
4854 /// VALIGN (if Interlane is true) instructions.
4855 static unsigned getShuffleAlignrImmediate(ShuffleVectorSDNode *SVOp,
4857 MVT VT = SVOp->getSimpleValueType(0);
4858 unsigned EltSize = InterLane ? 1 :
4859 VT.getVectorElementType().getSizeInBits() >> 3;
4861 unsigned NumElts = VT.getVectorNumElements();
4862 unsigned NumLanes = VT.is512BitVector() ? 1 : VT.getSizeInBits()/128;
4863 unsigned NumLaneElts = NumElts/NumLanes;
4867 for (i = 0; i != NumElts; ++i) {
4868 Val = SVOp->getMaskElt(i);
4872 if (Val >= (int)NumElts)
4873 Val -= NumElts - NumLaneElts;
4875 assert(Val - i > 0 && "PALIGNR imm should be positive");
4876 return (Val - i) * EltSize;
4879 /// \brief Return the appropriate immediate to shuffle the specified
4880 /// VECTOR_SHUFFLE mask with the PALIGNR instruction.
4881 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4882 return getShuffleAlignrImmediate(SVOp, false);
4885 /// \brief Return the appropriate immediate to shuffle the specified
4886 /// VECTOR_SHUFFLE mask with the VALIGN instruction.
4887 static unsigned getShuffleVALIGNImmediate(ShuffleVectorSDNode *SVOp) {
4888 return getShuffleAlignrImmediate(SVOp, true);
4892 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4893 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4894 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4895 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4898 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4900 MVT VecVT = N->getOperand(0).getSimpleValueType();
4901 MVT ElVT = VecVT.getVectorElementType();
4903 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4904 return Index / NumElemsPerChunk;
4907 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4908 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4909 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4910 llvm_unreachable("Illegal insert subvector for VINSERT");
4913 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4915 MVT VecVT = N->getSimpleValueType(0);
4916 MVT ElVT = VecVT.getVectorElementType();
4918 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4919 return Index / NumElemsPerChunk;
4922 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4923 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4924 /// and VINSERTI128 instructions.
4925 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4926 return getExtractVEXTRACTImmediate(N, 128);
4929 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4930 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4931 /// and VINSERTI64x4 instructions.
4932 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4933 return getExtractVEXTRACTImmediate(N, 256);
4936 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4937 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4938 /// and VINSERTI128 instructions.
4939 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4940 return getInsertVINSERTImmediate(N, 128);
4943 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4944 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4945 /// and VINSERTI64x4 instructions.
4946 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4947 return getInsertVINSERTImmediate(N, 256);
4950 /// isZero - Returns true if Elt is a constant integer zero
4951 static bool isZero(SDValue V) {
4952 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4953 return C && C->isNullValue();
4956 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4958 bool X86::isZeroNode(SDValue Elt) {
4961 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4962 return CFP->getValueAPF().isPosZero();
4966 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4967 /// match movhlps. The lower half elements should come from upper half of
4968 /// V1 (and in order), and the upper half elements should come from the upper
4969 /// half of V2 (and in order).
4970 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
4971 if (!VT.is128BitVector())
4973 if (VT.getVectorNumElements() != 4)
4975 for (unsigned i = 0, e = 2; i != e; ++i)
4976 if (!isUndefOrEqual(Mask[i], i+2))
4978 for (unsigned i = 2; i != 4; ++i)
4979 if (!isUndefOrEqual(Mask[i], i+4))
4984 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4985 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4987 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = nullptr) {
4988 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4990 N = N->getOperand(0).getNode();
4991 if (!ISD::isNON_EXTLoad(N))
4994 *LD = cast<LoadSDNode>(N);
4998 // Test whether the given value is a vector value which will be legalized
5000 static bool WillBeConstantPoolLoad(SDNode *N) {
5001 if (N->getOpcode() != ISD::BUILD_VECTOR)
5004 // Check for any non-constant elements.
5005 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
5006 switch (N->getOperand(i).getNode()->getOpcode()) {
5008 case ISD::ConstantFP:
5015 // Vectors of all-zeros and all-ones are materialized with special
5016 // instructions rather than being loaded.
5017 return !ISD::isBuildVectorAllZeros(N) &&
5018 !ISD::isBuildVectorAllOnes(N);
5021 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
5022 /// match movlp{s|d}. The lower half elements should come from lower half of
5023 /// V1 (and in order), and the upper half elements should come from the upper
5024 /// half of V2 (and in order). And since V1 will become the source of the
5025 /// MOVLP, it must be either a vector load or a scalar load to vector.
5026 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
5027 ArrayRef<int> Mask, MVT VT) {
5028 if (!VT.is128BitVector())
5031 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
5033 // Is V2 is a vector load, don't do this transformation. We will try to use
5034 // load folding shufps op.
5035 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
5038 unsigned NumElems = VT.getVectorNumElements();
5040 if (NumElems != 2 && NumElems != 4)
5042 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
5043 if (!isUndefOrEqual(Mask[i], i))
5045 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
5046 if (!isUndefOrEqual(Mask[i], i+NumElems))
5051 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
5052 /// to an zero vector.
5053 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
5054 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
5055 SDValue V1 = N->getOperand(0);
5056 SDValue V2 = N->getOperand(1);
5057 unsigned NumElems = N->getValueType(0).getVectorNumElements();
5058 for (unsigned i = 0; i != NumElems; ++i) {
5059 int Idx = N->getMaskElt(i);
5060 if (Idx >= (int)NumElems) {
5061 unsigned Opc = V2.getOpcode();
5062 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
5064 if (Opc != ISD::BUILD_VECTOR ||
5065 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
5067 } else if (Idx >= 0) {
5068 unsigned Opc = V1.getOpcode();
5069 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
5071 if (Opc != ISD::BUILD_VECTOR ||
5072 !X86::isZeroNode(V1.getOperand(Idx)))
5079 /// getZeroVector - Returns a vector of specified type with all zero elements.
5081 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
5082 SelectionDAG &DAG, SDLoc dl) {
5083 assert(VT.isVector() && "Expected a vector type");
5085 // Always build SSE zero vectors as <4 x i32> bitcasted
5086 // to their dest type. This ensures they get CSE'd.
5088 if (VT.is128BitVector()) { // SSE
5089 if (Subtarget->hasSSE2()) { // SSE2
5090 SDValue Cst = DAG.getConstant(0, MVT::i32);
5091 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5093 SDValue Cst = DAG.getConstantFP(+0.0, MVT::f32);
5094 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
5096 } else if (VT.is256BitVector()) { // AVX
5097 if (Subtarget->hasInt256()) { // AVX2
5098 SDValue Cst = DAG.getConstant(0, MVT::i32);
5099 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5100 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5102 // 256-bit logic and arithmetic instructions in AVX are all
5103 // floating-point, no support for integer ops. Emit fp zeroed vectors.
5104 SDValue Cst = DAG.getConstantFP(+0.0, MVT::f32);
5105 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5106 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
5108 } else if (VT.is512BitVector()) { // AVX-512
5109 SDValue Cst = DAG.getConstant(0, MVT::i32);
5110 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5111 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5112 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
5113 } else if (VT.getScalarType() == MVT::i1) {
5114 assert(VT.getVectorNumElements() <= 16 && "Unexpected vector type");
5115 SDValue Cst = DAG.getConstant(0, MVT::i1);
5116 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5117 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5119 llvm_unreachable("Unexpected vector type");
5121 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5124 /// getOnesVector - Returns a vector of specified type with all bits set.
5125 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
5126 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
5127 /// Then bitcast to their original type, ensuring they get CSE'd.
5128 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
5130 assert(VT.isVector() && "Expected a vector type");
5132 SDValue Cst = DAG.getConstant(~0U, MVT::i32);
5134 if (VT.is256BitVector()) {
5135 if (HasInt256) { // AVX2
5136 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5137 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5139 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5140 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
5142 } else if (VT.is128BitVector()) {
5143 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5145 llvm_unreachable("Unexpected vector type");
5147 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5150 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
5151 /// that point to V2 points to its first element.
5152 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
5153 for (unsigned i = 0; i != NumElems; ++i) {
5154 if (Mask[i] > (int)NumElems) {
5160 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
5161 /// operation of specified width.
5162 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
5164 unsigned NumElems = VT.getVectorNumElements();
5165 SmallVector<int, 8> Mask;
5166 Mask.push_back(NumElems);
5167 for (unsigned i = 1; i != NumElems; ++i)
5169 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5172 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
5173 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5175 unsigned NumElems = VT.getVectorNumElements();
5176 SmallVector<int, 8> Mask;
5177 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
5179 Mask.push_back(i + NumElems);
5181 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5184 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
5185 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5187 unsigned NumElems = VT.getVectorNumElements();
5188 SmallVector<int, 8> Mask;
5189 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
5190 Mask.push_back(i + Half);
5191 Mask.push_back(i + NumElems + Half);
5193 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5196 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
5197 // a generic shuffle instruction because the target has no such instructions.
5198 // Generate shuffles which repeat i16 and i8 several times until they can be
5199 // represented by v4f32 and then be manipulated by target suported shuffles.
5200 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
5201 MVT VT = V.getSimpleValueType();
5202 int NumElems = VT.getVectorNumElements();
5205 while (NumElems > 4) {
5206 if (EltNo < NumElems/2) {
5207 V = getUnpackl(DAG, dl, VT, V, V);
5209 V = getUnpackh(DAG, dl, VT, V, V);
5210 EltNo -= NumElems/2;
5217 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
5218 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
5219 MVT VT = V.getSimpleValueType();
5222 if (VT.is128BitVector()) {
5223 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
5224 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
5225 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
5227 } else if (VT.is256BitVector()) {
5228 // To use VPERMILPS to splat scalars, the second half of indicies must
5229 // refer to the higher part, which is a duplication of the lower one,
5230 // because VPERMILPS can only handle in-lane permutations.
5231 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
5232 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
5234 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
5235 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
5238 llvm_unreachable("Vector size not supported");
5240 return DAG.getNode(ISD::BITCAST, dl, VT, V);
5243 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
5244 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
5245 MVT SrcVT = SV->getSimpleValueType(0);
5246 SDValue V1 = SV->getOperand(0);
5249 int EltNo = SV->getSplatIndex();
5250 int NumElems = SrcVT.getVectorNumElements();
5251 bool Is256BitVec = SrcVT.is256BitVector();
5253 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
5254 "Unknown how to promote splat for type");
5256 // Extract the 128-bit part containing the splat element and update
5257 // the splat element index when it refers to the higher register.
5259 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
5260 if (EltNo >= NumElems/2)
5261 EltNo -= NumElems/2;
5264 // All i16 and i8 vector types can't be used directly by a generic shuffle
5265 // instruction because the target has no such instruction. Generate shuffles
5266 // which repeat i16 and i8 several times until they fit in i32, and then can
5267 // be manipulated by target suported shuffles.
5268 MVT EltVT = SrcVT.getVectorElementType();
5269 if (EltVT == MVT::i8 || EltVT == MVT::i16)
5270 V1 = PromoteSplati8i16(V1, DAG, EltNo);
5272 // Recreate the 256-bit vector and place the same 128-bit vector
5273 // into the low and high part. This is necessary because we want
5274 // to use VPERM* to shuffle the vectors
5276 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
5279 return getLegalSplat(DAG, V1, EltNo);
5282 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
5283 /// vector of zero or undef vector. This produces a shuffle where the low
5284 /// element of V2 is swizzled into the zero/undef vector, landing at element
5285 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
5286 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
5288 const X86Subtarget *Subtarget,
5289 SelectionDAG &DAG) {
5290 MVT VT = V2.getSimpleValueType();
5292 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
5293 unsigned NumElems = VT.getVectorNumElements();
5294 SmallVector<int, 16> MaskVec;
5295 for (unsigned i = 0; i != NumElems; ++i)
5296 // If this is the insertion idx, put the low elt of V2 here.
5297 MaskVec.push_back(i == Idx ? NumElems : i);
5298 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
5301 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
5302 /// target specific opcode. Returns true if the Mask could be calculated. Sets
5303 /// IsUnary to true if only uses one source. Note that this will set IsUnary for
5304 /// shuffles which use a single input multiple times, and in those cases it will
5305 /// adjust the mask to only have indices within that single input.
5306 static bool getTargetShuffleMask(SDNode *N, MVT VT,
5307 SmallVectorImpl<int> &Mask, bool &IsUnary) {
5308 unsigned NumElems = VT.getVectorNumElements();
5312 bool IsFakeUnary = false;
5313 switch(N->getOpcode()) {
5314 case X86ISD::BLENDI:
5315 ImmN = N->getOperand(N->getNumOperands()-1);
5316 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5319 ImmN = N->getOperand(N->getNumOperands()-1);
5320 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5321 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5323 case X86ISD::UNPCKH:
5324 DecodeUNPCKHMask(VT, Mask);
5325 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5327 case X86ISD::UNPCKL:
5328 DecodeUNPCKLMask(VT, Mask);
5329 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5331 case X86ISD::MOVHLPS:
5332 DecodeMOVHLPSMask(NumElems, Mask);
5333 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5335 case X86ISD::MOVLHPS:
5336 DecodeMOVLHPSMask(NumElems, Mask);
5337 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5339 case X86ISD::PALIGNR:
5340 ImmN = N->getOperand(N->getNumOperands()-1);
5341 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5343 case X86ISD::PSHUFD:
5344 case X86ISD::VPERMILPI:
5345 ImmN = N->getOperand(N->getNumOperands()-1);
5346 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5349 case X86ISD::PSHUFHW:
5350 ImmN = N->getOperand(N->getNumOperands()-1);
5351 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5354 case X86ISD::PSHUFLW:
5355 ImmN = N->getOperand(N->getNumOperands()-1);
5356 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5359 case X86ISD::PSHUFB: {
5361 SDValue MaskNode = N->getOperand(1);
5362 while (MaskNode->getOpcode() == ISD::BITCAST)
5363 MaskNode = MaskNode->getOperand(0);
5365 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
5366 // If we have a build-vector, then things are easy.
5367 EVT VT = MaskNode.getValueType();
5368 assert(VT.isVector() &&
5369 "Can't produce a non-vector with a build_vector!");
5370 if (!VT.isInteger())
5373 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
5375 SmallVector<uint64_t, 32> RawMask;
5376 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
5377 SDValue Op = MaskNode->getOperand(i);
5378 if (Op->getOpcode() == ISD::UNDEF) {
5379 RawMask.push_back((uint64_t)SM_SentinelUndef);
5382 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
5385 APInt MaskElement = CN->getAPIntValue();
5387 // We now have to decode the element which could be any integer size and
5388 // extract each byte of it.
5389 for (int j = 0; j < NumBytesPerElement; ++j) {
5390 // Note that this is x86 and so always little endian: the low byte is
5391 // the first byte of the mask.
5392 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
5393 MaskElement = MaskElement.lshr(8);
5396 DecodePSHUFBMask(RawMask, Mask);
5400 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
5404 SDValue Ptr = MaskLoad->getBasePtr();
5405 if (Ptr->getOpcode() == X86ISD::Wrapper)
5406 Ptr = Ptr->getOperand(0);
5408 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
5409 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
5412 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
5413 // FIXME: Support AVX-512 here.
5414 Type *Ty = C->getType();
5415 if (!Ty->isVectorTy() || (Ty->getVectorNumElements() != 16 &&
5416 Ty->getVectorNumElements() != 32))
5419 DecodePSHUFBMask(C, Mask);
5425 case X86ISD::VPERMI:
5426 ImmN = N->getOperand(N->getNumOperands()-1);
5427 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5431 case X86ISD::MOVSD: {
5432 // The index 0 always comes from the first element of the second source,
5433 // this is why MOVSS and MOVSD are used in the first place. The other
5434 // elements come from the other positions of the first source vector
5435 Mask.push_back(NumElems);
5436 for (unsigned i = 1; i != NumElems; ++i) {
5441 case X86ISD::VPERM2X128:
5442 ImmN = N->getOperand(N->getNumOperands()-1);
5443 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5444 if (Mask.empty()) return false;
5446 case X86ISD::MOVSLDUP:
5447 DecodeMOVSLDUPMask(VT, Mask);
5449 case X86ISD::MOVSHDUP:
5450 DecodeMOVSHDUPMask(VT, Mask);
5452 case X86ISD::MOVDDUP:
5453 case X86ISD::MOVLHPD:
5454 case X86ISD::MOVLPD:
5455 case X86ISD::MOVLPS:
5456 // Not yet implemented
5458 default: llvm_unreachable("unknown target shuffle node");
5461 // If we have a fake unary shuffle, the shuffle mask is spread across two
5462 // inputs that are actually the same node. Re-map the mask to always point
5463 // into the first input.
5466 if (M >= (int)Mask.size())
5472 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
5473 /// element of the result of the vector shuffle.
5474 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
5477 return SDValue(); // Limit search depth.
5479 SDValue V = SDValue(N, 0);
5480 EVT VT = V.getValueType();
5481 unsigned Opcode = V.getOpcode();
5483 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5484 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5485 int Elt = SV->getMaskElt(Index);
5488 return DAG.getUNDEF(VT.getVectorElementType());
5490 unsigned NumElems = VT.getVectorNumElements();
5491 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5492 : SV->getOperand(1);
5493 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5496 // Recurse into target specific vector shuffles to find scalars.
5497 if (isTargetShuffle(Opcode)) {
5498 MVT ShufVT = V.getSimpleValueType();
5499 unsigned NumElems = ShufVT.getVectorNumElements();
5500 SmallVector<int, 16> ShuffleMask;
5503 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5506 int Elt = ShuffleMask[Index];
5508 return DAG.getUNDEF(ShufVT.getVectorElementType());
5510 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5512 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5516 // Actual nodes that may contain scalar elements
5517 if (Opcode == ISD::BITCAST) {
5518 V = V.getOperand(0);
5519 EVT SrcVT = V.getValueType();
5520 unsigned NumElems = VT.getVectorNumElements();
5522 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5526 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5527 return (Index == 0) ? V.getOperand(0)
5528 : DAG.getUNDEF(VT.getVectorElementType());
5530 if (V.getOpcode() == ISD::BUILD_VECTOR)
5531 return V.getOperand(Index);
5536 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5537 /// shuffle operation which come from a consecutively from a zero. The
5538 /// search can start in two different directions, from left or right.
5539 /// We count undefs as zeros until PreferredNum is reached.
5540 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5541 unsigned NumElems, bool ZerosFromLeft,
5543 unsigned PreferredNum = -1U) {
5544 unsigned NumZeros = 0;
5545 for (unsigned i = 0; i != NumElems; ++i) {
5546 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5547 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5551 if (X86::isZeroNode(Elt))
5553 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5554 NumZeros = std::min(NumZeros + 1, PreferredNum);
5562 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5563 /// correspond consecutively to elements from one of the vector operands,
5564 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5566 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5567 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5568 unsigned NumElems, unsigned &OpNum) {
5569 bool SeenV1 = false;
5570 bool SeenV2 = false;
5572 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5573 int Idx = SVOp->getMaskElt(i);
5574 // Ignore undef indicies
5578 if (Idx < (int)NumElems)
5583 // Only accept consecutive elements from the same vector
5584 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5588 OpNum = SeenV1 ? 0 : 1;
5592 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5593 /// logical left shift of a vector.
5594 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5595 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5597 SVOp->getSimpleValueType(0).getVectorNumElements();
5598 unsigned NumZeros = getNumOfConsecutiveZeros(
5599 SVOp, NumElems, false /* check zeros from right */, DAG,
5600 SVOp->getMaskElt(0));
5606 // Considering the elements in the mask that are not consecutive zeros,
5607 // check if they consecutively come from only one of the source vectors.
5609 // V1 = {X, A, B, C} 0
5611 // vector_shuffle V1, V2 <1, 2, 3, X>
5613 if (!isShuffleMaskConsecutive(SVOp,
5614 0, // Mask Start Index
5615 NumElems-NumZeros, // Mask End Index(exclusive)
5616 NumZeros, // Where to start looking in the src vector
5617 NumElems, // Number of elements in vector
5618 OpSrc)) // Which source operand ?
5623 ShVal = SVOp->getOperand(OpSrc);
5627 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5628 /// logical left shift of a vector.
5629 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5630 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5632 SVOp->getSimpleValueType(0).getVectorNumElements();
5633 unsigned NumZeros = getNumOfConsecutiveZeros(
5634 SVOp, NumElems, true /* check zeros from left */, DAG,
5635 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5641 // Considering the elements in the mask that are not consecutive zeros,
5642 // check if they consecutively come from only one of the source vectors.
5644 // 0 { A, B, X, X } = V2
5646 // vector_shuffle V1, V2 <X, X, 4, 5>
5648 if (!isShuffleMaskConsecutive(SVOp,
5649 NumZeros, // Mask Start Index
5650 NumElems, // Mask End Index(exclusive)
5651 0, // Where to start looking in the src vector
5652 NumElems, // Number of elements in vector
5653 OpSrc)) // Which source operand ?
5658 ShVal = SVOp->getOperand(OpSrc);
5662 /// isVectorShift - Returns true if the shuffle can be implemented as a
5663 /// logical left or right shift of a vector.
5664 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5665 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5666 // Although the logic below support any bitwidth size, there are no
5667 // shift instructions which handle more than 128-bit vectors.
5668 if (!SVOp->getSimpleValueType(0).is128BitVector())
5671 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5672 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5678 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5680 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5681 unsigned NumNonZero, unsigned NumZero,
5683 const X86Subtarget* Subtarget,
5684 const TargetLowering &TLI) {
5691 for (unsigned i = 0; i < 16; ++i) {
5692 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5693 if (ThisIsNonZero && First) {
5695 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5697 V = DAG.getUNDEF(MVT::v8i16);
5702 SDValue ThisElt, LastElt;
5703 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5704 if (LastIsNonZero) {
5705 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5706 MVT::i16, Op.getOperand(i-1));
5708 if (ThisIsNonZero) {
5709 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5710 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5711 ThisElt, DAG.getConstant(8, MVT::i8));
5713 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5717 if (ThisElt.getNode())
5718 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5719 DAG.getIntPtrConstant(i/2));
5723 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5726 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5728 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5729 unsigned NumNonZero, unsigned NumZero,
5731 const X86Subtarget* Subtarget,
5732 const TargetLowering &TLI) {
5739 for (unsigned i = 0; i < 8; ++i) {
5740 bool isNonZero = (NonZeros & (1 << i)) != 0;
5744 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5746 V = DAG.getUNDEF(MVT::v8i16);
5749 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5750 MVT::v8i16, V, Op.getOperand(i),
5751 DAG.getIntPtrConstant(i));
5758 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
5759 static SDValue LowerBuildVectorv4x32(SDValue Op, SelectionDAG &DAG,
5760 const X86Subtarget *Subtarget,
5761 const TargetLowering &TLI) {
5762 // Find all zeroable elements.
5764 for (int i=0; i < 4; ++i) {
5765 SDValue Elt = Op->getOperand(i);
5766 Zeroable[i] = (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt));
5768 assert(std::count_if(&Zeroable[0], &Zeroable[4],
5769 [](bool M) { return !M; }) > 1 &&
5770 "We expect at least two non-zero elements!");
5772 // We only know how to deal with build_vector nodes where elements are either
5773 // zeroable or extract_vector_elt with constant index.
5774 SDValue FirstNonZero;
5775 unsigned FirstNonZeroIdx;
5776 for (unsigned i=0; i < 4; ++i) {
5779 SDValue Elt = Op->getOperand(i);
5780 if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5781 !isa<ConstantSDNode>(Elt.getOperand(1)))
5783 // Make sure that this node is extracting from a 128-bit vector.
5784 MVT VT = Elt.getOperand(0).getSimpleValueType();
5785 if (!VT.is128BitVector())
5787 if (!FirstNonZero.getNode()) {
5789 FirstNonZeroIdx = i;
5793 assert(FirstNonZero.getNode() && "Unexpected build vector of all zeros!");
5794 SDValue V1 = FirstNonZero.getOperand(0);
5795 MVT VT = V1.getSimpleValueType();
5797 // See if this build_vector can be lowered as a blend with zero.
5799 unsigned EltMaskIdx, EltIdx;
5801 for (EltIdx = 0; EltIdx < 4; ++EltIdx) {
5802 if (Zeroable[EltIdx]) {
5803 // The zero vector will be on the right hand side.
5804 Mask[EltIdx] = EltIdx+4;
5808 Elt = Op->getOperand(EltIdx);
5809 // By construction, Elt is a EXTRACT_VECTOR_ELT with constant index.
5810 EltMaskIdx = cast<ConstantSDNode>(Elt.getOperand(1))->getZExtValue();
5811 if (Elt.getOperand(0) != V1 || EltMaskIdx != EltIdx)
5813 Mask[EltIdx] = EltIdx;
5817 // Let the shuffle legalizer deal with blend operations.
5818 SDValue VZero = getZeroVector(VT, Subtarget, DAG, SDLoc(Op));
5819 if (V1.getSimpleValueType() != VT)
5820 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), VT, V1);
5821 return DAG.getVectorShuffle(VT, SDLoc(V1), V1, VZero, &Mask[0]);
5824 // See if we can lower this build_vector to a INSERTPS.
5825 if (!Subtarget->hasSSE41())
5828 SDValue V2 = Elt.getOperand(0);
5829 if (Elt == FirstNonZero && EltIdx == FirstNonZeroIdx)
5832 bool CanFold = true;
5833 for (unsigned i = EltIdx + 1; i < 4 && CanFold; ++i) {
5837 SDValue Current = Op->getOperand(i);
5838 SDValue SrcVector = Current->getOperand(0);
5841 CanFold = SrcVector == V1 &&
5842 cast<ConstantSDNode>(Current.getOperand(1))->getZExtValue() == i;
5848 assert(V1.getNode() && "Expected at least two non-zero elements!");
5849 if (V1.getSimpleValueType() != MVT::v4f32)
5850 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), MVT::v4f32, V1);
5851 if (V2.getSimpleValueType() != MVT::v4f32)
5852 V2 = DAG.getNode(ISD::BITCAST, SDLoc(V2), MVT::v4f32, V2);
5854 // Ok, we can emit an INSERTPS instruction.
5856 for (int i = 0; i < 4; ++i)
5860 unsigned InsertPSMask = EltMaskIdx << 6 | EltIdx << 4 | ZMask;
5861 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
5862 SDValue Result = DAG.getNode(X86ISD::INSERTPS, SDLoc(Op), MVT::v4f32, V1, V2,
5863 DAG.getIntPtrConstant(InsertPSMask));
5864 return DAG.getNode(ISD::BITCAST, SDLoc(Op), VT, Result);
5867 /// getVShift - Return a vector logical shift node.
5869 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5870 unsigned NumBits, SelectionDAG &DAG,
5871 const TargetLowering &TLI, SDLoc dl) {
5872 assert(VT.is128BitVector() && "Unknown type for VShift");
5873 EVT ShVT = MVT::v2i64;
5874 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5875 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5876 return DAG.getNode(ISD::BITCAST, dl, VT,
5877 DAG.getNode(Opc, dl, ShVT, SrcOp,
5878 DAG.getConstant(NumBits,
5879 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5883 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5885 // Check if the scalar load can be widened into a vector load. And if
5886 // the address is "base + cst" see if the cst can be "absorbed" into
5887 // the shuffle mask.
5888 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5889 SDValue Ptr = LD->getBasePtr();
5890 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5892 EVT PVT = LD->getValueType(0);
5893 if (PVT != MVT::i32 && PVT != MVT::f32)
5898 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5899 FI = FINode->getIndex();
5901 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5902 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5903 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5904 Offset = Ptr.getConstantOperandVal(1);
5905 Ptr = Ptr.getOperand(0);
5910 // FIXME: 256-bit vector instructions don't require a strict alignment,
5911 // improve this code to support it better.
5912 unsigned RequiredAlign = VT.getSizeInBits()/8;
5913 SDValue Chain = LD->getChain();
5914 // Make sure the stack object alignment is at least 16 or 32.
5915 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5916 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5917 if (MFI->isFixedObjectIndex(FI)) {
5918 // Can't change the alignment. FIXME: It's possible to compute
5919 // the exact stack offset and reference FI + adjust offset instead.
5920 // If someone *really* cares about this. That's the way to implement it.
5923 MFI->setObjectAlignment(FI, RequiredAlign);
5927 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5928 // Ptr + (Offset & ~15).
5931 if ((Offset % RequiredAlign) & 3)
5933 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5935 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5936 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5938 int EltNo = (Offset - StartOffset) >> 2;
5939 unsigned NumElems = VT.getVectorNumElements();
5941 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5942 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5943 LD->getPointerInfo().getWithOffset(StartOffset),
5944 false, false, false, 0);
5946 SmallVector<int, 8> Mask;
5947 for (unsigned i = 0; i != NumElems; ++i)
5948 Mask.push_back(EltNo);
5950 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5956 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5957 /// vector of type 'VT', see if the elements can be replaced by a single large
5958 /// load which has the same value as a build_vector whose operands are 'elts'.
5960 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5962 /// FIXME: we'd also like to handle the case where the last elements are zero
5963 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5964 /// There's even a handy isZeroNode for that purpose.
5965 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
5966 SDLoc &DL, SelectionDAG &DAG,
5967 bool isAfterLegalize) {
5968 EVT EltVT = VT.getVectorElementType();
5969 unsigned NumElems = Elts.size();
5971 LoadSDNode *LDBase = nullptr;
5972 unsigned LastLoadedElt = -1U;
5974 // For each element in the initializer, see if we've found a load or an undef.
5975 // If we don't find an initial load element, or later load elements are
5976 // non-consecutive, bail out.
5977 for (unsigned i = 0; i < NumElems; ++i) {
5978 SDValue Elt = Elts[i];
5980 if (!Elt.getNode() ||
5981 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5984 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5986 LDBase = cast<LoadSDNode>(Elt.getNode());
5990 if (Elt.getOpcode() == ISD::UNDEF)
5993 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5994 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5999 // If we have found an entire vector of loads and undefs, then return a large
6000 // load of the entire vector width starting at the base pointer. If we found
6001 // consecutive loads for the low half, generate a vzext_load node.
6002 if (LastLoadedElt == NumElems - 1) {
6004 if (isAfterLegalize &&
6005 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
6008 SDValue NewLd = SDValue();
6010 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
6011 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
6012 LDBase->getPointerInfo(),
6013 LDBase->isVolatile(), LDBase->isNonTemporal(),
6014 LDBase->isInvariant(), 0);
6015 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
6016 LDBase->getPointerInfo(),
6017 LDBase->isVolatile(), LDBase->isNonTemporal(),
6018 LDBase->isInvariant(), LDBase->getAlignment());
6020 if (LDBase->hasAnyUseOfValue(1)) {
6021 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
6023 SDValue(NewLd.getNode(), 1));
6024 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
6025 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
6026 SDValue(NewLd.getNode(), 1));
6032 //TODO: The code below fires only for for loading the low v2i32 / v2f32
6033 //of a v4i32 / v4f32. It's probably worth generalizing.
6034 if (NumElems == 4 && LastLoadedElt == 1 && (EltVT.getSizeInBits() == 32) &&
6035 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
6036 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
6037 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
6039 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
6040 LDBase->getPointerInfo(),
6041 LDBase->getAlignment(),
6042 false/*isVolatile*/, true/*ReadMem*/,
6045 // Make sure the newly-created LOAD is in the same position as LDBase in
6046 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
6047 // update uses of LDBase's output chain to use the TokenFactor.
6048 if (LDBase->hasAnyUseOfValue(1)) {
6049 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
6050 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
6051 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
6052 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
6053 SDValue(ResNode.getNode(), 1));
6056 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
6061 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
6062 /// to generate a splat value for the following cases:
6063 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
6064 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
6065 /// a scalar load, or a constant.
6066 /// The VBROADCAST node is returned when a pattern is found,
6067 /// or SDValue() otherwise.
6068 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
6069 SelectionDAG &DAG) {
6070 // VBROADCAST requires AVX.
6071 // TODO: Splats could be generated for non-AVX CPUs using SSE
6072 // instructions, but there's less potential gain for only 128-bit vectors.
6073 if (!Subtarget->hasAVX())
6076 MVT VT = Op.getSimpleValueType();
6079 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
6080 "Unsupported vector type for broadcast.");
6085 switch (Op.getOpcode()) {
6087 // Unknown pattern found.
6090 case ISD::BUILD_VECTOR: {
6091 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
6092 BitVector UndefElements;
6093 SDValue Splat = BVOp->getSplatValue(&UndefElements);
6095 // We need a splat of a single value to use broadcast, and it doesn't
6096 // make any sense if the value is only in one element of the vector.
6097 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
6101 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6102 Ld.getOpcode() == ISD::ConstantFP);
6104 // Make sure that all of the users of a non-constant load are from the
6105 // BUILD_VECTOR node.
6106 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
6111 case ISD::VECTOR_SHUFFLE: {
6112 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6114 // Shuffles must have a splat mask where the first element is
6116 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
6119 SDValue Sc = Op.getOperand(0);
6120 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
6121 Sc.getOpcode() != ISD::BUILD_VECTOR) {
6123 if (!Subtarget->hasInt256())
6126 // Use the register form of the broadcast instruction available on AVX2.
6127 if (VT.getSizeInBits() >= 256)
6128 Sc = Extract128BitVector(Sc, 0, DAG, dl);
6129 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
6132 Ld = Sc.getOperand(0);
6133 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6134 Ld.getOpcode() == ISD::ConstantFP);
6136 // The scalar_to_vector node and the suspected
6137 // load node must have exactly one user.
6138 // Constants may have multiple users.
6140 // AVX-512 has register version of the broadcast
6141 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
6142 Ld.getValueType().getSizeInBits() >= 32;
6143 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
6150 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
6151 bool IsGE256 = (VT.getSizeInBits() >= 256);
6153 // When optimizing for size, generate up to 5 extra bytes for a broadcast
6154 // instruction to save 8 or more bytes of constant pool data.
6155 // TODO: If multiple splats are generated to load the same constant,
6156 // it may be detrimental to overall size. There needs to be a way to detect
6157 // that condition to know if this is truly a size win.
6158 const Function *F = DAG.getMachineFunction().getFunction();
6159 bool OptForSize = F->getAttributes().
6160 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
6162 // Handle broadcasting a single constant scalar from the constant pool
6164 // On Sandybridge (no AVX2), it is still better to load a constant vector
6165 // from the constant pool and not to broadcast it from a scalar.
6166 // But override that restriction when optimizing for size.
6167 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
6168 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
6169 EVT CVT = Ld.getValueType();
6170 assert(!CVT.isVector() && "Must not broadcast a vector type");
6172 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
6173 // For size optimization, also splat v2f64 and v2i64, and for size opt
6174 // with AVX2, also splat i8 and i16.
6175 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
6176 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
6177 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
6178 const Constant *C = nullptr;
6179 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
6180 C = CI->getConstantIntValue();
6181 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
6182 C = CF->getConstantFPValue();
6184 assert(C && "Invalid constant type");
6186 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6187 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
6188 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
6189 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
6190 MachinePointerInfo::getConstantPool(),
6191 false, false, false, Alignment);
6193 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6197 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
6199 // Handle AVX2 in-register broadcasts.
6200 if (!IsLoad && Subtarget->hasInt256() &&
6201 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
6202 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6204 // The scalar source must be a normal load.
6208 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
6209 (Subtarget->hasVLX() && ScalarSize == 64))
6210 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6212 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
6213 // double since there is no vbroadcastsd xmm
6214 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
6215 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
6216 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6219 // Unsupported broadcast.
6223 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
6224 /// underlying vector and index.
6226 /// Modifies \p ExtractedFromVec to the real vector and returns the real
6228 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
6230 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
6231 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
6234 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
6236 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
6238 // (extract_vector_elt (vector_shuffle<2,u,u,u>
6239 // (extract_subvector (v8f32 %vreg0), Constant<4>),
6242 // In this case the vector is the extract_subvector expression and the index
6243 // is 2, as specified by the shuffle.
6244 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
6245 SDValue ShuffleVec = SVOp->getOperand(0);
6246 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
6247 assert(ShuffleVecVT.getVectorElementType() ==
6248 ExtractedFromVec.getSimpleValueType().getVectorElementType());
6250 int ShuffleIdx = SVOp->getMaskElt(Idx);
6251 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
6252 ExtractedFromVec = ShuffleVec;
6258 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
6259 MVT VT = Op.getSimpleValueType();
6261 // Skip if insert_vec_elt is not supported.
6262 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6263 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
6267 unsigned NumElems = Op.getNumOperands();
6271 SmallVector<unsigned, 4> InsertIndices;
6272 SmallVector<int, 8> Mask(NumElems, -1);
6274 for (unsigned i = 0; i != NumElems; ++i) {
6275 unsigned Opc = Op.getOperand(i).getOpcode();
6277 if (Opc == ISD::UNDEF)
6280 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
6281 // Quit if more than 1 elements need inserting.
6282 if (InsertIndices.size() > 1)
6285 InsertIndices.push_back(i);
6289 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
6290 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
6291 // Quit if non-constant index.
6292 if (!isa<ConstantSDNode>(ExtIdx))
6294 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
6296 // Quit if extracted from vector of different type.
6297 if (ExtractedFromVec.getValueType() != VT)
6300 if (!VecIn1.getNode())
6301 VecIn1 = ExtractedFromVec;
6302 else if (VecIn1 != ExtractedFromVec) {
6303 if (!VecIn2.getNode())
6304 VecIn2 = ExtractedFromVec;
6305 else if (VecIn2 != ExtractedFromVec)
6306 // Quit if more than 2 vectors to shuffle
6310 if (ExtractedFromVec == VecIn1)
6312 else if (ExtractedFromVec == VecIn2)
6313 Mask[i] = Idx + NumElems;
6316 if (!VecIn1.getNode())
6319 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
6320 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
6321 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
6322 unsigned Idx = InsertIndices[i];
6323 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
6324 DAG.getIntPtrConstant(Idx));
6330 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
6332 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
6334 MVT VT = Op.getSimpleValueType();
6335 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
6336 "Unexpected type in LowerBUILD_VECTORvXi1!");
6339 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6340 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
6341 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6342 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6345 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
6346 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
6347 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6348 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6351 bool AllContants = true;
6352 uint64_t Immediate = 0;
6353 int NonConstIdx = -1;
6354 bool IsSplat = true;
6355 unsigned NumNonConsts = 0;
6356 unsigned NumConsts = 0;
6357 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
6358 SDValue In = Op.getOperand(idx);
6359 if (In.getOpcode() == ISD::UNDEF)
6361 if (!isa<ConstantSDNode>(In)) {
6362 AllContants = false;
6367 if (cast<ConstantSDNode>(In)->getZExtValue())
6368 Immediate |= (1ULL << idx);
6370 if (In != Op.getOperand(0))
6375 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
6376 DAG.getConstant(Immediate, MVT::i16));
6377 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
6378 DAG.getIntPtrConstant(0));
6381 if (NumNonConsts == 1 && NonConstIdx != 0) {
6384 SDValue VecAsImm = DAG.getConstant(Immediate,
6385 MVT::getIntegerVT(VT.getSizeInBits()));
6386 DstVec = DAG.getNode(ISD::BITCAST, dl, VT, VecAsImm);
6389 DstVec = DAG.getUNDEF(VT);
6390 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
6391 Op.getOperand(NonConstIdx),
6392 DAG.getIntPtrConstant(NonConstIdx));
6394 if (!IsSplat && (NonConstIdx != 0))
6395 llvm_unreachable("Unsupported BUILD_VECTOR operation");
6396 MVT SelectVT = (VT == MVT::v16i1)? MVT::i16 : MVT::i8;
6399 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6400 DAG.getConstant(-1, SelectVT),
6401 DAG.getConstant(0, SelectVT));
6403 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6404 DAG.getConstant((Immediate | 1), SelectVT),
6405 DAG.getConstant(Immediate, SelectVT));
6406 return DAG.getNode(ISD::BITCAST, dl, VT, Select);
6409 /// \brief Return true if \p N implements a horizontal binop and return the
6410 /// operands for the horizontal binop into V0 and V1.
6412 /// This is a helper function of PerformBUILD_VECTORCombine.
6413 /// This function checks that the build_vector \p N in input implements a
6414 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
6415 /// operation to match.
6416 /// For example, if \p Opcode is equal to ISD::ADD, then this function
6417 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
6418 /// is equal to ISD::SUB, then this function checks if this is a horizontal
6421 /// This function only analyzes elements of \p N whose indices are
6422 /// in range [BaseIdx, LastIdx).
6423 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
6425 unsigned BaseIdx, unsigned LastIdx,
6426 SDValue &V0, SDValue &V1) {
6427 EVT VT = N->getValueType(0);
6429 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
6430 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
6431 "Invalid Vector in input!");
6433 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
6434 bool CanFold = true;
6435 unsigned ExpectedVExtractIdx = BaseIdx;
6436 unsigned NumElts = LastIdx - BaseIdx;
6437 V0 = DAG.getUNDEF(VT);
6438 V1 = DAG.getUNDEF(VT);
6440 // Check if N implements a horizontal binop.
6441 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
6442 SDValue Op = N->getOperand(i + BaseIdx);
6445 if (Op->getOpcode() == ISD::UNDEF) {
6446 // Update the expected vector extract index.
6447 if (i * 2 == NumElts)
6448 ExpectedVExtractIdx = BaseIdx;
6449 ExpectedVExtractIdx += 2;
6453 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
6458 SDValue Op0 = Op.getOperand(0);
6459 SDValue Op1 = Op.getOperand(1);
6461 // Try to match the following pattern:
6462 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
6463 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6464 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6465 Op0.getOperand(0) == Op1.getOperand(0) &&
6466 isa<ConstantSDNode>(Op0.getOperand(1)) &&
6467 isa<ConstantSDNode>(Op1.getOperand(1)));
6471 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6472 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
6474 if (i * 2 < NumElts) {
6475 if (V0.getOpcode() == ISD::UNDEF)
6476 V0 = Op0.getOperand(0);
6478 if (V1.getOpcode() == ISD::UNDEF)
6479 V1 = Op0.getOperand(0);
6480 if (i * 2 == NumElts)
6481 ExpectedVExtractIdx = BaseIdx;
6484 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
6485 if (I0 == ExpectedVExtractIdx)
6486 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
6487 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
6488 // Try to match the following dag sequence:
6489 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
6490 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
6494 ExpectedVExtractIdx += 2;
6500 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
6501 /// a concat_vector.
6503 /// This is a helper function of PerformBUILD_VECTORCombine.
6504 /// This function expects two 256-bit vectors called V0 and V1.
6505 /// At first, each vector is split into two separate 128-bit vectors.
6506 /// Then, the resulting 128-bit vectors are used to implement two
6507 /// horizontal binary operations.
6509 /// The kind of horizontal binary operation is defined by \p X86Opcode.
6511 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
6512 /// the two new horizontal binop.
6513 /// When Mode is set, the first horizontal binop dag node would take as input
6514 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
6515 /// horizontal binop dag node would take as input the lower 128-bit of V1
6516 /// and the upper 128-bit of V1.
6518 /// HADD V0_LO, V0_HI
6519 /// HADD V1_LO, V1_HI
6521 /// Otherwise, the first horizontal binop dag node takes as input the lower
6522 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
6523 /// dag node takes the the upper 128-bit of V0 and the upper 128-bit of V1.
6525 /// HADD V0_LO, V1_LO
6526 /// HADD V0_HI, V1_HI
6528 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
6529 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
6530 /// the upper 128-bits of the result.
6531 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
6532 SDLoc DL, SelectionDAG &DAG,
6533 unsigned X86Opcode, bool Mode,
6534 bool isUndefLO, bool isUndefHI) {
6535 EVT VT = V0.getValueType();
6536 assert(VT.is256BitVector() && VT == V1.getValueType() &&
6537 "Invalid nodes in input!");
6539 unsigned NumElts = VT.getVectorNumElements();
6540 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
6541 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
6542 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
6543 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
6544 EVT NewVT = V0_LO.getValueType();
6546 SDValue LO = DAG.getUNDEF(NewVT);
6547 SDValue HI = DAG.getUNDEF(NewVT);
6550 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6551 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
6552 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
6553 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
6554 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
6556 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6557 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
6558 V1_LO->getOpcode() != ISD::UNDEF))
6559 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
6561 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
6562 V1_HI->getOpcode() != ISD::UNDEF))
6563 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
6566 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
6569 /// \brief Try to fold a build_vector that performs an 'addsub' into the
6570 /// sequence of 'vadd + vsub + blendi'.
6571 static SDValue matchAddSub(const BuildVectorSDNode *BV, SelectionDAG &DAG,
6572 const X86Subtarget *Subtarget) {
6574 EVT VT = BV->getValueType(0);
6575 unsigned NumElts = VT.getVectorNumElements();
6576 SDValue InVec0 = DAG.getUNDEF(VT);
6577 SDValue InVec1 = DAG.getUNDEF(VT);
6579 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
6580 VT == MVT::v2f64) && "build_vector with an invalid type found!");
6582 // Odd-numbered elements in the input build vector are obtained from
6583 // adding two integer/float elements.
6584 // Even-numbered elements in the input build vector are obtained from
6585 // subtracting two integer/float elements.
6586 unsigned ExpectedOpcode = ISD::FSUB;
6587 unsigned NextExpectedOpcode = ISD::FADD;
6588 bool AddFound = false;
6589 bool SubFound = false;
6591 for (unsigned i = 0, e = NumElts; i != e; i++) {
6592 SDValue Op = BV->getOperand(i);
6594 // Skip 'undef' values.
6595 unsigned Opcode = Op.getOpcode();
6596 if (Opcode == ISD::UNDEF) {
6597 std::swap(ExpectedOpcode, NextExpectedOpcode);
6601 // Early exit if we found an unexpected opcode.
6602 if (Opcode != ExpectedOpcode)
6605 SDValue Op0 = Op.getOperand(0);
6606 SDValue Op1 = Op.getOperand(1);
6608 // Try to match the following pattern:
6609 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
6610 // Early exit if we cannot match that sequence.
6611 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6612 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6613 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
6614 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
6615 Op0.getOperand(1) != Op1.getOperand(1))
6618 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6622 // We found a valid add/sub node. Update the information accordingly.
6628 // Update InVec0 and InVec1.
6629 if (InVec0.getOpcode() == ISD::UNDEF)
6630 InVec0 = Op0.getOperand(0);
6631 if (InVec1.getOpcode() == ISD::UNDEF)
6632 InVec1 = Op1.getOperand(0);
6634 // Make sure that operands in input to each add/sub node always
6635 // come from a same pair of vectors.
6636 if (InVec0 != Op0.getOperand(0)) {
6637 if (ExpectedOpcode == ISD::FSUB)
6640 // FADD is commutable. Try to commute the operands
6641 // and then test again.
6642 std::swap(Op0, Op1);
6643 if (InVec0 != Op0.getOperand(0))
6647 if (InVec1 != Op1.getOperand(0))
6650 // Update the pair of expected opcodes.
6651 std::swap(ExpectedOpcode, NextExpectedOpcode);
6654 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
6655 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
6656 InVec1.getOpcode() != ISD::UNDEF)
6657 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
6662 static SDValue PerformBUILD_VECTORCombine(SDNode *N, SelectionDAG &DAG,
6663 const X86Subtarget *Subtarget) {
6665 EVT VT = N->getValueType(0);
6666 unsigned NumElts = VT.getVectorNumElements();
6667 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
6668 SDValue InVec0, InVec1;
6670 // Try to match an ADDSUB.
6671 if ((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
6672 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) {
6673 SDValue Value = matchAddSub(BV, DAG, Subtarget);
6674 if (Value.getNode())
6678 // Try to match horizontal ADD/SUB.
6679 unsigned NumUndefsLO = 0;
6680 unsigned NumUndefsHI = 0;
6681 unsigned Half = NumElts/2;
6683 // Count the number of UNDEF operands in the build_vector in input.
6684 for (unsigned i = 0, e = Half; i != e; ++i)
6685 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6688 for (unsigned i = Half, e = NumElts; i != e; ++i)
6689 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6692 // Early exit if this is either a build_vector of all UNDEFs or all the
6693 // operands but one are UNDEF.
6694 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
6697 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
6698 // Try to match an SSE3 float HADD/HSUB.
6699 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6700 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6702 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6703 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6704 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
6705 // Try to match an SSSE3 integer HADD/HSUB.
6706 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6707 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
6709 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6710 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
6713 if (!Subtarget->hasAVX())
6716 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
6717 // Try to match an AVX horizontal add/sub of packed single/double
6718 // precision floating point values from 256-bit vectors.
6719 SDValue InVec2, InVec3;
6720 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
6721 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
6722 ((InVec0.getOpcode() == ISD::UNDEF ||
6723 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6724 ((InVec1.getOpcode() == ISD::UNDEF ||
6725 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6726 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6728 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
6729 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
6730 ((InVec0.getOpcode() == ISD::UNDEF ||
6731 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6732 ((InVec1.getOpcode() == ISD::UNDEF ||
6733 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6734 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6735 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6736 // Try to match an AVX2 horizontal add/sub of signed integers.
6737 SDValue InVec2, InVec3;
6739 bool CanFold = true;
6741 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
6742 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6743 ((InVec0.getOpcode() == ISD::UNDEF ||
6744 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6745 ((InVec1.getOpcode() == ISD::UNDEF ||
6746 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6747 X86Opcode = X86ISD::HADD;
6748 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6749 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6750 ((InVec0.getOpcode() == ISD::UNDEF ||
6751 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6752 ((InVec1.getOpcode() == ISD::UNDEF ||
6753 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6754 X86Opcode = X86ISD::HSUB;
6759 // Fold this build_vector into a single horizontal add/sub.
6760 // Do this only if the target has AVX2.
6761 if (Subtarget->hasAVX2())
6762 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6764 // Do not try to expand this build_vector into a pair of horizontal
6765 // add/sub if we can emit a pair of scalar add/sub.
6766 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6769 // Convert this build_vector into a pair of horizontal binop followed by
6771 bool isUndefLO = NumUndefsLO == Half;
6772 bool isUndefHI = NumUndefsHI == Half;
6773 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6774 isUndefLO, isUndefHI);
6778 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6779 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6781 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6782 X86Opcode = X86ISD::HADD;
6783 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6784 X86Opcode = X86ISD::HSUB;
6785 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6786 X86Opcode = X86ISD::FHADD;
6787 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6788 X86Opcode = X86ISD::FHSUB;
6792 // Don't try to expand this build_vector into a pair of horizontal add/sub
6793 // if we can simply emit a pair of scalar add/sub.
6794 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6797 // Convert this build_vector into two horizontal add/sub followed by
6799 bool isUndefLO = NumUndefsLO == Half;
6800 bool isUndefHI = NumUndefsHI == Half;
6801 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6802 isUndefLO, isUndefHI);
6809 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6812 MVT VT = Op.getSimpleValueType();
6813 MVT ExtVT = VT.getVectorElementType();
6814 unsigned NumElems = Op.getNumOperands();
6816 // Generate vectors for predicate vectors.
6817 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
6818 return LowerBUILD_VECTORvXi1(Op, DAG);
6820 // Vectors containing all zeros can be matched by pxor and xorps later
6821 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6822 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6823 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6824 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6827 return getZeroVector(VT, Subtarget, DAG, dl);
6830 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6831 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6832 // vpcmpeqd on 256-bit vectors.
6833 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6834 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6837 if (!VT.is512BitVector())
6838 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
6841 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
6842 if (Broadcast.getNode())
6845 unsigned EVTBits = ExtVT.getSizeInBits();
6847 unsigned NumZero = 0;
6848 unsigned NumNonZero = 0;
6849 unsigned NonZeros = 0;
6850 bool IsAllConstants = true;
6851 SmallSet<SDValue, 8> Values;
6852 for (unsigned i = 0; i < NumElems; ++i) {
6853 SDValue Elt = Op.getOperand(i);
6854 if (Elt.getOpcode() == ISD::UNDEF)
6857 if (Elt.getOpcode() != ISD::Constant &&
6858 Elt.getOpcode() != ISD::ConstantFP)
6859 IsAllConstants = false;
6860 if (X86::isZeroNode(Elt))
6863 NonZeros |= (1 << i);
6868 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6869 if (NumNonZero == 0)
6870 return DAG.getUNDEF(VT);
6872 // Special case for single non-zero, non-undef, element.
6873 if (NumNonZero == 1) {
6874 unsigned Idx = countTrailingZeros(NonZeros);
6875 SDValue Item = Op.getOperand(Idx);
6877 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6878 // the value are obviously zero, truncate the value to i32 and do the
6879 // insertion that way. Only do this if the value is non-constant or if the
6880 // value is a constant being inserted into element 0. It is cheaper to do
6881 // a constant pool load than it is to do a movd + shuffle.
6882 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6883 (!IsAllConstants || Idx == 0)) {
6884 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6886 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6887 EVT VecVT = MVT::v4i32;
6888 unsigned VecElts = 4;
6890 // Truncate the value (which may itself be a constant) to i32, and
6891 // convert it to a vector with movd (S2V+shuffle to zero extend).
6892 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6893 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6895 // If using the new shuffle lowering, just directly insert this.
6896 if (ExperimentalVectorShuffleLowering)
6898 ISD::BITCAST, dl, VT,
6899 getShuffleVectorZeroOrUndef(Item, Idx * 2, true, Subtarget, DAG));
6901 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6903 // Now we have our 32-bit value zero extended in the low element of
6904 // a vector. If Idx != 0, swizzle it into place.
6906 SmallVector<int, 4> Mask;
6907 Mask.push_back(Idx);
6908 for (unsigned i = 1; i != VecElts; ++i)
6910 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
6913 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6917 // If we have a constant or non-constant insertion into the low element of
6918 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6919 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6920 // depending on what the source datatype is.
6923 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6925 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6926 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6927 if (VT.is256BitVector() || VT.is512BitVector()) {
6928 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6929 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6930 Item, DAG.getIntPtrConstant(0));
6932 assert(VT.is128BitVector() && "Expected an SSE value type!");
6933 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6934 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6935 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6938 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6939 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6940 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6941 if (VT.is256BitVector()) {
6942 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6943 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6945 assert(VT.is128BitVector() && "Expected an SSE value type!");
6946 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6948 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6952 // Is it a vector logical left shift?
6953 if (NumElems == 2 && Idx == 1 &&
6954 X86::isZeroNode(Op.getOperand(0)) &&
6955 !X86::isZeroNode(Op.getOperand(1))) {
6956 unsigned NumBits = VT.getSizeInBits();
6957 return getVShift(true, VT,
6958 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6959 VT, Op.getOperand(1)),
6960 NumBits/2, DAG, *this, dl);
6963 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6966 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6967 // is a non-constant being inserted into an element other than the low one,
6968 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6969 // movd/movss) to move this into the low element, then shuffle it into
6971 if (EVTBits == 32) {
6972 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6974 // If using the new shuffle lowering, just directly insert this.
6975 if (ExperimentalVectorShuffleLowering)
6976 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
6978 // Turn it into a shuffle of zero and zero-extended scalar to vector.
6979 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
6980 SmallVector<int, 8> MaskVec;
6981 for (unsigned i = 0; i != NumElems; ++i)
6982 MaskVec.push_back(i == Idx ? 0 : 1);
6983 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
6987 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6988 if (Values.size() == 1) {
6989 if (EVTBits == 32) {
6990 // Instead of a shuffle like this:
6991 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6992 // Check if it's possible to issue this instead.
6993 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6994 unsigned Idx = countTrailingZeros(NonZeros);
6995 SDValue Item = Op.getOperand(Idx);
6996 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6997 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
7002 // A vector full of immediates; various special cases are already
7003 // handled, so this is best done with a single constant-pool load.
7007 // For AVX-length vectors, see if we can use a vector load to get all of the
7008 // elements, otherwise build the individual 128-bit pieces and use
7009 // shuffles to put them in place.
7010 if (VT.is256BitVector() || VT.is512BitVector()) {
7011 SmallVector<SDValue, 64> V;
7012 for (unsigned i = 0; i != NumElems; ++i)
7013 V.push_back(Op.getOperand(i));
7015 // Check for a build vector of consecutive loads.
7016 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
7019 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
7021 // Build both the lower and upper subvector.
7022 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
7023 makeArrayRef(&V[0], NumElems/2));
7024 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
7025 makeArrayRef(&V[NumElems / 2], NumElems/2));
7027 // Recreate the wider vector with the lower and upper part.
7028 if (VT.is256BitVector())
7029 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
7030 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
7033 // Let legalizer expand 2-wide build_vectors.
7034 if (EVTBits == 64) {
7035 if (NumNonZero == 1) {
7036 // One half is zero or undef.
7037 unsigned Idx = countTrailingZeros(NonZeros);
7038 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
7039 Op.getOperand(Idx));
7040 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
7045 // If element VT is < 32 bits, convert it to inserts into a zero vector.
7046 if (EVTBits == 8 && NumElems == 16) {
7047 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
7049 if (V.getNode()) return V;
7052 if (EVTBits == 16 && NumElems == 8) {
7053 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
7055 if (V.getNode()) return V;
7058 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
7059 if (EVTBits == 32 && NumElems == 4) {
7060 SDValue V = LowerBuildVectorv4x32(Op, DAG, Subtarget, *this);
7065 // If element VT is == 32 bits, turn it into a number of shuffles.
7066 SmallVector<SDValue, 8> V(NumElems);
7067 if (NumElems == 4 && NumZero > 0) {
7068 for (unsigned i = 0; i < 4; ++i) {
7069 bool isZero = !(NonZeros & (1 << i));
7071 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
7073 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7076 for (unsigned i = 0; i < 2; ++i) {
7077 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
7080 V[i] = V[i*2]; // Must be a zero vector.
7083 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
7086 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
7089 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
7094 bool Reverse1 = (NonZeros & 0x3) == 2;
7095 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
7099 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
7100 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
7102 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
7105 if (Values.size() > 1 && VT.is128BitVector()) {
7106 // Check for a build vector of consecutive loads.
7107 for (unsigned i = 0; i < NumElems; ++i)
7108 V[i] = Op.getOperand(i);
7110 // Check for elements which are consecutive loads.
7111 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false);
7115 // Check for a build vector from mostly shuffle plus few inserting.
7116 SDValue Sh = buildFromShuffleMostly(Op, DAG);
7120 // For SSE 4.1, use insertps to put the high elements into the low element.
7121 if (getSubtarget()->hasSSE41()) {
7123 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
7124 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
7126 Result = DAG.getUNDEF(VT);
7128 for (unsigned i = 1; i < NumElems; ++i) {
7129 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
7130 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
7131 Op.getOperand(i), DAG.getIntPtrConstant(i));
7136 // Otherwise, expand into a number of unpckl*, start by extending each of
7137 // our (non-undef) elements to the full vector width with the element in the
7138 // bottom slot of the vector (which generates no code for SSE).
7139 for (unsigned i = 0; i < NumElems; ++i) {
7140 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
7141 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7143 V[i] = DAG.getUNDEF(VT);
7146 // Next, we iteratively mix elements, e.g. for v4f32:
7147 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
7148 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
7149 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
7150 unsigned EltStride = NumElems >> 1;
7151 while (EltStride != 0) {
7152 for (unsigned i = 0; i < EltStride; ++i) {
7153 // If V[i+EltStride] is undef and this is the first round of mixing,
7154 // then it is safe to just drop this shuffle: V[i] is already in the
7155 // right place, the one element (since it's the first round) being
7156 // inserted as undef can be dropped. This isn't safe for successive
7157 // rounds because they will permute elements within both vectors.
7158 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
7159 EltStride == NumElems/2)
7162 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
7171 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
7172 // to create 256-bit vectors from two other 128-bit ones.
7173 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7175 MVT ResVT = Op.getSimpleValueType();
7177 assert((ResVT.is256BitVector() ||
7178 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
7180 SDValue V1 = Op.getOperand(0);
7181 SDValue V2 = Op.getOperand(1);
7182 unsigned NumElems = ResVT.getVectorNumElements();
7183 if(ResVT.is256BitVector())
7184 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7186 if (Op.getNumOperands() == 4) {
7187 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
7188 ResVT.getVectorNumElements()/2);
7189 SDValue V3 = Op.getOperand(2);
7190 SDValue V4 = Op.getOperand(3);
7191 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
7192 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
7194 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7197 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7198 MVT LLVM_ATTRIBUTE_UNUSED VT = Op.getSimpleValueType();
7199 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
7200 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
7201 Op.getNumOperands() == 4)));
7203 // AVX can use the vinsertf128 instruction to create 256-bit vectors
7204 // from two other 128-bit ones.
7206 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
7207 return LowerAVXCONCAT_VECTORS(Op, DAG);
7211 //===----------------------------------------------------------------------===//
7212 // Vector shuffle lowering
7214 // This is an experimental code path for lowering vector shuffles on x86. It is
7215 // designed to handle arbitrary vector shuffles and blends, gracefully
7216 // degrading performance as necessary. It works hard to recognize idiomatic
7217 // shuffles and lower them to optimal instruction patterns without leaving
7218 // a framework that allows reasonably efficient handling of all vector shuffle
7220 //===----------------------------------------------------------------------===//
7222 /// \brief Tiny helper function to identify a no-op mask.
7224 /// This is a somewhat boring predicate function. It checks whether the mask
7225 /// array input, which is assumed to be a single-input shuffle mask of the kind
7226 /// used by the X86 shuffle instructions (not a fully general
7227 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
7228 /// in-place shuffle are 'no-op's.
7229 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
7230 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7231 if (Mask[i] != -1 && Mask[i] != i)
7236 /// \brief Helper function to classify a mask as a single-input mask.
7238 /// This isn't a generic single-input test because in the vector shuffle
7239 /// lowering we canonicalize single inputs to be the first input operand. This
7240 /// means we can more quickly test for a single input by only checking whether
7241 /// an input from the second operand exists. We also assume that the size of
7242 /// mask corresponds to the size of the input vectors which isn't true in the
7243 /// fully general case.
7244 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
7246 if (M >= (int)Mask.size())
7251 /// \brief Test whether there are elements crossing 128-bit lanes in this
7254 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
7255 /// and we routinely test for these.
7256 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
7257 int LaneSize = 128 / VT.getScalarSizeInBits();
7258 int Size = Mask.size();
7259 for (int i = 0; i < Size; ++i)
7260 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
7265 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
7267 /// This checks a shuffle mask to see if it is performing the same
7268 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
7269 /// that it is also not lane-crossing. It may however involve a blend from the
7270 /// same lane of a second vector.
7272 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
7273 /// non-trivial to compute in the face of undef lanes. The representation is
7274 /// *not* suitable for use with existing 128-bit shuffles as it will contain
7275 /// entries from both V1 and V2 inputs to the wider mask.
7277 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
7278 SmallVectorImpl<int> &RepeatedMask) {
7279 int LaneSize = 128 / VT.getScalarSizeInBits();
7280 RepeatedMask.resize(LaneSize, -1);
7281 int Size = Mask.size();
7282 for (int i = 0; i < Size; ++i) {
7285 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
7286 // This entry crosses lanes, so there is no way to model this shuffle.
7289 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
7290 if (RepeatedMask[i % LaneSize] == -1)
7291 // This is the first non-undef entry in this slot of a 128-bit lane.
7292 RepeatedMask[i % LaneSize] =
7293 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
7294 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
7295 // Found a mismatch with the repeated mask.
7301 // Hide this symbol with an anonymous namespace instead of 'static' so that MSVC
7302 // 2013 will allow us to use it as a non-type template parameter.
7305 /// \brief Implementation of the \c isShuffleEquivalent variadic functor.
7307 /// See its documentation for details.
7308 bool isShuffleEquivalentImpl(ArrayRef<int> Mask, ArrayRef<const int *> Args) {
7309 if (Mask.size() != Args.size())
7311 for (int i = 0, e = Mask.size(); i < e; ++i) {
7312 assert(*Args[i] >= 0 && "Arguments must be positive integers!");
7313 if (Mask[i] != -1 && Mask[i] != *Args[i])
7321 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
7324 /// This is a fast way to test a shuffle mask against a fixed pattern:
7326 /// if (isShuffleEquivalent(Mask, 3, 2, 1, 0)) { ... }
7328 /// It returns true if the mask is exactly as wide as the argument list, and
7329 /// each element of the mask is either -1 (signifying undef) or the value given
7330 /// in the argument.
7331 static const VariadicFunction1<
7332 bool, ArrayRef<int>, int, isShuffleEquivalentImpl> isShuffleEquivalent = {};
7334 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
7336 /// This helper function produces an 8-bit shuffle immediate corresponding to
7337 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
7338 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
7341 /// NB: We rely heavily on "undef" masks preserving the input lane.
7342 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask,
7343 SelectionDAG &DAG) {
7344 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
7345 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
7346 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
7347 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
7348 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
7351 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
7352 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
7353 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
7354 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
7355 return DAG.getConstant(Imm, MVT::i8);
7358 /// \brief Try to emit a blend instruction for a shuffle.
7360 /// This doesn't do any checks for the availability of instructions for blending
7361 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
7362 /// be matched in the backend with the type given. What it does check for is
7363 /// that the shuffle mask is in fact a blend.
7364 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
7365 SDValue V2, ArrayRef<int> Mask,
7366 const X86Subtarget *Subtarget,
7367 SelectionDAG &DAG) {
7369 unsigned BlendMask = 0;
7370 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7371 if (Mask[i] >= Size) {
7372 if (Mask[i] != i + Size)
7373 return SDValue(); // Shuffled V2 input!
7374 BlendMask |= 1u << i;
7377 if (Mask[i] >= 0 && Mask[i] != i)
7378 return SDValue(); // Shuffled V1 input!
7380 switch (VT.SimpleTy) {
7385 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
7386 DAG.getConstant(BlendMask, MVT::i8));
7390 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7394 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
7395 // that instruction.
7396 if (Subtarget->hasAVX2()) {
7397 // Scale the blend by the number of 32-bit dwords per element.
7398 int Scale = VT.getScalarSizeInBits() / 32;
7400 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7401 if (Mask[i] >= Size)
7402 for (int j = 0; j < Scale; ++j)
7403 BlendMask |= 1u << (i * Scale + j);
7405 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
7406 V1 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V1);
7407 V2 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V2);
7408 return DAG.getNode(ISD::BITCAST, DL, VT,
7409 DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
7410 DAG.getConstant(BlendMask, MVT::i8)));
7414 // For integer shuffles we need to expand the mask and cast the inputs to
7415 // v8i16s prior to blending.
7416 int Scale = 8 / VT.getVectorNumElements();
7418 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7419 if (Mask[i] >= Size)
7420 for (int j = 0; j < Scale; ++j)
7421 BlendMask |= 1u << (i * Scale + j);
7423 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
7424 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
7425 return DAG.getNode(ISD::BITCAST, DL, VT,
7426 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
7427 DAG.getConstant(BlendMask, MVT::i8)));
7431 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7432 SmallVector<int, 8> RepeatedMask;
7433 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
7434 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
7435 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
7437 for (int i = 0; i < 8; ++i)
7438 if (RepeatedMask[i] >= 16)
7439 BlendMask |= 1u << i;
7440 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
7441 DAG.getConstant(BlendMask, MVT::i8));
7446 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7447 // Scale the blend by the number of bytes per element.
7448 int Scale = VT.getScalarSizeInBits() / 8;
7449 assert(Mask.size() * Scale == 32 && "Not a 256-bit vector!");
7451 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
7452 // mix of LLVM's code generator and the x86 backend. We tell the code
7453 // generator that boolean values in the elements of an x86 vector register
7454 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
7455 // mapping a select to operand #1, and 'false' mapping to operand #2. The
7456 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
7457 // of the element (the remaining are ignored) and 0 in that high bit would
7458 // mean operand #1 while 1 in the high bit would mean operand #2. So while
7459 // the LLVM model for boolean values in vector elements gets the relevant
7460 // bit set, it is set backwards and over constrained relative to x86's
7462 SDValue VSELECTMask[32];
7463 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7464 for (int j = 0; j < Scale; ++j)
7465 VSELECTMask[Scale * i + j] =
7466 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
7467 : DAG.getConstant(Mask[i] < Size ? -1 : 0, MVT::i8);
7469 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1);
7470 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V2);
7472 ISD::BITCAST, DL, VT,
7473 DAG.getNode(ISD::VSELECT, DL, MVT::v32i8,
7474 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, VSELECTMask),
7479 llvm_unreachable("Not a supported integer vector type!");
7483 /// \brief Generic routine to lower a shuffle and blend as a decomposed set of
7484 /// unblended shuffles followed by an unshuffled blend.
7486 /// This matches the extremely common pattern for handling combined
7487 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
7489 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
7493 SelectionDAG &DAG) {
7494 // Shuffle the input elements into the desired positions in V1 and V2 and
7495 // blend them together.
7496 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7497 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7498 SmallVector<int, 32> BlendMask(Mask.size(), -1);
7499 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7500 if (Mask[i] >= 0 && Mask[i] < Size) {
7501 V1Mask[i] = Mask[i];
7503 } else if (Mask[i] >= Size) {
7504 V2Mask[i] = Mask[i] - Size;
7505 BlendMask[i] = i + Size;
7508 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7509 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7510 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7513 /// \brief Try to lower a vector shuffle as a byte rotation.
7515 /// SSSE3 has a generic PALIGNR instruction in x86 that will do an arbitrary
7516 /// byte-rotation of the concatenation of two vectors; pre-SSSE3 can use
7517 /// a PSRLDQ/PSLLDQ/POR pattern to get a similar effect. This routine will
7518 /// try to generically lower a vector shuffle through such an pattern. It
7519 /// does not check for the profitability of lowering either as PALIGNR or
7520 /// PSRLDQ/PSLLDQ/POR, only whether the mask is valid to lower in that form.
7521 /// This matches shuffle vectors that look like:
7523 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
7525 /// Essentially it concatenates V1 and V2, shifts right by some number of
7526 /// elements, and takes the low elements as the result. Note that while this is
7527 /// specified as a *right shift* because x86 is little-endian, it is a *left
7528 /// rotate* of the vector lanes.
7530 /// Note that this only handles 128-bit vector widths currently.
7531 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
7534 const X86Subtarget *Subtarget,
7535 SelectionDAG &DAG) {
7536 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7538 // We need to detect various ways of spelling a rotation:
7539 // [11, 12, 13, 14, 15, 0, 1, 2]
7540 // [-1, 12, 13, 14, -1, -1, 1, -1]
7541 // [-1, -1, -1, -1, -1, -1, 1, 2]
7542 // [ 3, 4, 5, 6, 7, 8, 9, 10]
7543 // [-1, 4, 5, 6, -1, -1, 9, -1]
7544 // [-1, 4, 5, 6, -1, -1, -1, -1]
7547 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7550 assert(Mask[i] >= 0 && "Only -1 is a valid negative mask element!");
7552 // Based on the mod-Size value of this mask element determine where
7553 // a rotated vector would have started.
7554 int StartIdx = i - (Mask[i] % Size);
7556 // The identity rotation isn't interesting, stop.
7559 // If we found the tail of a vector the rotation must be the missing
7560 // front. If we found the head of a vector, it must be how much of the head.
7561 int CandidateRotation = StartIdx < 0 ? -StartIdx : Size - StartIdx;
7564 Rotation = CandidateRotation;
7565 else if (Rotation != CandidateRotation)
7566 // The rotations don't match, so we can't match this mask.
7569 // Compute which value this mask is pointing at.
7570 SDValue MaskV = Mask[i] < Size ? V1 : V2;
7572 // Compute which of the two target values this index should be assigned to.
7573 // This reflects whether the high elements are remaining or the low elements
7575 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
7577 // Either set up this value if we've not encountered it before, or check
7578 // that it remains consistent.
7581 else if (TargetV != MaskV)
7582 // This may be a rotation, but it pulls from the inputs in some
7583 // unsupported interleaving.
7587 // Check that we successfully analyzed the mask, and normalize the results.
7588 assert(Rotation != 0 && "Failed to locate a viable rotation!");
7589 assert((Lo || Hi) && "Failed to find a rotated input vector!");
7595 assert(VT.getSizeInBits() == 128 &&
7596 "Rotate-based lowering only supports 128-bit lowering!");
7597 assert(Mask.size() <= 16 &&
7598 "Can shuffle at most 16 bytes in a 128-bit vector!");
7600 // The actual rotate instruction rotates bytes, so we need to scale the
7601 // rotation based on how many bytes are in the vector.
7602 int Scale = 16 / Mask.size();
7604 // SSSE3 targets can use the palignr instruction
7605 if (Subtarget->hasSSSE3()) {
7606 // Cast the inputs to v16i8 to match PALIGNR.
7607 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Lo);
7608 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Hi);
7610 return DAG.getNode(ISD::BITCAST, DL, VT,
7611 DAG.getNode(X86ISD::PALIGNR, DL, MVT::v16i8, Hi, Lo,
7612 DAG.getConstant(Rotation * Scale, MVT::i8)));
7615 // Default SSE2 implementation
7616 int LoByteShift = 16 - Rotation * Scale;
7617 int HiByteShift = Rotation * Scale;
7619 // Cast the inputs to v2i64 to match PSLLDQ/PSRLDQ.
7620 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Lo);
7621 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Hi);
7623 SDValue LoShift = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, Lo,
7624 DAG.getConstant(8 * LoByteShift, MVT::i8));
7625 SDValue HiShift = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, Hi,
7626 DAG.getConstant(8 * HiByteShift, MVT::i8));
7627 return DAG.getNode(ISD::BITCAST, DL, VT,
7628 DAG.getNode(ISD::OR, DL, MVT::v2i64, LoShift, HiShift));
7631 /// \brief Compute whether each element of a shuffle is zeroable.
7633 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
7634 /// Either it is an undef element in the shuffle mask, the element of the input
7635 /// referenced is undef, or the element of the input referenced is known to be
7636 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
7637 /// as many lanes with this technique as possible to simplify the remaining
7639 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
7640 SDValue V1, SDValue V2) {
7641 SmallBitVector Zeroable(Mask.size(), false);
7643 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
7644 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
7646 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7648 // Handle the easy cases.
7649 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
7654 // If this is an index into a build_vector node, dig out the input value and
7656 SDValue V = M < Size ? V1 : V2;
7657 if (V.getOpcode() != ISD::BUILD_VECTOR)
7660 SDValue Input = V.getOperand(M % Size);
7661 // The UNDEF opcode check really should be dead code here, but not quite
7662 // worth asserting on (it isn't invalid, just unexpected).
7663 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
7670 /// \brief Try to lower a vector shuffle as a byte shift (shifts in zeros).
7672 /// Attempts to match a shuffle mask against the PSRLDQ and PSLLDQ SSE2
7673 /// byte-shift instructions. The mask must consist of a shifted sequential
7674 /// shuffle from one of the input vectors and zeroable elements for the
7675 /// remaining 'shifted in' elements.
7677 /// Note that this only handles 128-bit vector widths currently.
7678 static SDValue lowerVectorShuffleAsByteShift(SDLoc DL, MVT VT, SDValue V1,
7679 SDValue V2, ArrayRef<int> Mask,
7680 SelectionDAG &DAG) {
7681 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7683 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7685 int Size = Mask.size();
7686 int Scale = 16 / Size;
7688 auto isSequential = [](int Base, int StartIndex, int EndIndex, int MaskOffset,
7689 ArrayRef<int> Mask) {
7690 for (int i = StartIndex; i < EndIndex; i++) {
7693 if (i + Base != Mask[i] - MaskOffset)
7699 for (int Shift = 1; Shift < Size; Shift++) {
7700 int ByteShift = Shift * Scale;
7702 // PSRLDQ : (little-endian) right byte shift
7703 // [ 5, 6, 7, zz, zz, zz, zz, zz]
7704 // [ -1, 5, 6, 7, zz, zz, zz, zz]
7705 // [ 1, 2, -1, -1, -1, -1, zz, zz]
7706 bool ZeroableRight = true;
7707 for (int i = Size - Shift; i < Size; i++) {
7708 ZeroableRight &= Zeroable[i];
7711 if (ZeroableRight) {
7712 bool ValidShiftRight1 = isSequential(Shift, 0, Size - Shift, 0, Mask);
7713 bool ValidShiftRight2 = isSequential(Shift, 0, Size - Shift, Size, Mask);
7715 if (ValidShiftRight1 || ValidShiftRight2) {
7716 // Cast the inputs to v2i64 to match PSRLDQ.
7717 SDValue &TargetV = ValidShiftRight1 ? V1 : V2;
7718 SDValue V = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, TargetV);
7719 SDValue Shifted = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, V,
7720 DAG.getConstant(ByteShift * 8, MVT::i8));
7721 return DAG.getNode(ISD::BITCAST, DL, VT, Shifted);
7725 // PSLLDQ : (little-endian) left byte shift
7726 // [ zz, 0, 1, 2, 3, 4, 5, 6]
7727 // [ zz, zz, -1, -1, 2, 3, 4, -1]
7728 // [ zz, zz, zz, zz, zz, zz, -1, 1]
7729 bool ZeroableLeft = true;
7730 for (int i = 0; i < Shift; i++) {
7731 ZeroableLeft &= Zeroable[i];
7735 bool ValidShiftLeft1 = isSequential(-Shift, Shift, Size, 0, Mask);
7736 bool ValidShiftLeft2 = isSequential(-Shift, Shift, Size, Size, Mask);
7738 if (ValidShiftLeft1 || ValidShiftLeft2) {
7739 // Cast the inputs to v2i64 to match PSLLDQ.
7740 SDValue &TargetV = ValidShiftLeft1 ? V1 : V2;
7741 SDValue V = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, TargetV);
7742 SDValue Shifted = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, V,
7743 DAG.getConstant(ByteShift * 8, MVT::i8));
7744 return DAG.getNode(ISD::BITCAST, DL, VT, Shifted);
7752 /// \brief Lower a vector shuffle as a zero or any extension.
7754 /// Given a specific number of elements, element bit width, and extension
7755 /// stride, produce either a zero or any extension based on the available
7756 /// features of the subtarget.
7757 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7758 SDLoc DL, MVT VT, int NumElements, int Scale, bool AnyExt, SDValue InputV,
7759 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7760 assert(Scale > 1 && "Need a scale to extend.");
7761 int EltBits = VT.getSizeInBits() / NumElements;
7762 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
7763 "Only 8, 16, and 32 bit elements can be extended.");
7764 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
7766 // Found a valid zext mask! Try various lowering strategies based on the
7767 // input type and available ISA extensions.
7768 if (Subtarget->hasSSE41()) {
7769 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7770 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
7771 NumElements / Scale);
7772 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7773 return DAG.getNode(ISD::BITCAST, DL, VT,
7774 DAG.getNode(X86ISD::VZEXT, DL, ExtVT, InputV));
7777 // For any extends we can cheat for larger element sizes and use shuffle
7778 // instructions that can fold with a load and/or copy.
7779 if (AnyExt && EltBits == 32) {
7780 int PSHUFDMask[4] = {0, -1, 1, -1};
7782 ISD::BITCAST, DL, VT,
7783 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7784 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7785 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
7787 if (AnyExt && EltBits == 16 && Scale > 2) {
7788 int PSHUFDMask[4] = {0, -1, 0, -1};
7789 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7790 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7791 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG));
7792 int PSHUFHWMask[4] = {1, -1, -1, -1};
7794 ISD::BITCAST, DL, VT,
7795 DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16,
7796 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, InputV),
7797 getV4X86ShuffleImm8ForMask(PSHUFHWMask, DAG)));
7800 // If this would require more than 2 unpack instructions to expand, use
7801 // pshufb when available. We can only use more than 2 unpack instructions
7802 // when zero extending i8 elements which also makes it easier to use pshufb.
7803 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
7804 assert(NumElements == 16 && "Unexpected byte vector width!");
7805 SDValue PSHUFBMask[16];
7806 for (int i = 0; i < 16; ++i)
7808 DAG.getConstant((i % Scale == 0) ? i / Scale : 0x80, MVT::i8);
7809 InputV = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, InputV);
7810 return DAG.getNode(ISD::BITCAST, DL, VT,
7811 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
7812 DAG.getNode(ISD::BUILD_VECTOR, DL,
7813 MVT::v16i8, PSHUFBMask)));
7816 // Otherwise emit a sequence of unpacks.
7818 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7819 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
7820 : getZeroVector(InputVT, Subtarget, DAG, DL);
7821 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7822 InputV = DAG.getNode(X86ISD::UNPCKL, DL, InputVT, InputV, Ext);
7826 } while (Scale > 1);
7827 return DAG.getNode(ISD::BITCAST, DL, VT, InputV);
7830 /// \brief Try to lower a vector shuffle as a zero extension on any micrarch.
7832 /// This routine will try to do everything in its power to cleverly lower
7833 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
7834 /// check for the profitability of this lowering, it tries to aggressively
7835 /// match this pattern. It will use all of the micro-architectural details it
7836 /// can to emit an efficient lowering. It handles both blends with all-zero
7837 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
7838 /// masking out later).
7840 /// The reason we have dedicated lowering for zext-style shuffles is that they
7841 /// are both incredibly common and often quite performance sensitive.
7842 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
7843 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7844 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7845 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7847 int Bits = VT.getSizeInBits();
7848 int NumElements = Mask.size();
7850 // Define a helper function to check a particular ext-scale and lower to it if
7852 auto Lower = [&](int Scale) -> SDValue {
7855 for (int i = 0; i < NumElements; ++i) {
7857 continue; // Valid anywhere but doesn't tell us anything.
7858 if (i % Scale != 0) {
7859 // Each of the extend elements needs to be zeroable.
7863 // We no lorger are in the anyext case.
7868 // Each of the base elements needs to be consecutive indices into the
7869 // same input vector.
7870 SDValue V = Mask[i] < NumElements ? V1 : V2;
7873 else if (InputV != V)
7874 return SDValue(); // Flip-flopping inputs.
7876 if (Mask[i] % NumElements != i / Scale)
7877 return SDValue(); // Non-consecutive strided elemenst.
7880 // If we fail to find an input, we have a zero-shuffle which should always
7881 // have already been handled.
7882 // FIXME: Maybe handle this here in case during blending we end up with one?
7886 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7887 DL, VT, NumElements, Scale, AnyExt, InputV, Subtarget, DAG);
7890 // The widest scale possible for extending is to a 64-bit integer.
7891 assert(Bits % 64 == 0 &&
7892 "The number of bits in a vector must be divisible by 64 on x86!");
7893 int NumExtElements = Bits / 64;
7895 // Each iteration, try extending the elements half as much, but into twice as
7897 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7898 assert(NumElements % NumExtElements == 0 &&
7899 "The input vector size must be divisble by the extended size.");
7900 if (SDValue V = Lower(NumElements / NumExtElements))
7904 // No viable ext lowering found.
7908 /// \brief Try to get a scalar value for a specific element of a vector.
7910 /// Looks through BUILD_VECTOR and SCALAR_TO_VECTOR nodes to find a scalar.
7911 static SDValue getScalarValueForVectorElement(SDValue V, int Idx,
7912 SelectionDAG &DAG) {
7913 MVT VT = V.getSimpleValueType();
7914 MVT EltVT = VT.getVectorElementType();
7915 while (V.getOpcode() == ISD::BITCAST)
7916 V = V.getOperand(0);
7917 // If the bitcasts shift the element size, we can't extract an equivalent
7919 MVT NewVT = V.getSimpleValueType();
7920 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
7923 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7924 (Idx == 0 && V.getOpcode() == ISD::SCALAR_TO_VECTOR))
7925 return DAG.getNode(ISD::BITCAST, SDLoc(V), EltVT, V.getOperand(Idx));
7930 /// \brief Helper to test for a load that can be folded with x86 shuffles.
7932 /// This is particularly important because the set of instructions varies
7933 /// significantly based on whether the operand is a load or not.
7934 static bool isShuffleFoldableLoad(SDValue V) {
7935 while (V.getOpcode() == ISD::BITCAST)
7936 V = V.getOperand(0);
7938 return ISD::isNON_EXTLoad(V.getNode());
7941 /// \brief Try to lower insertion of a single element into a zero vector.
7943 /// This is a common pattern that we have especially efficient patterns to lower
7944 /// across all subtarget feature sets.
7945 static SDValue lowerVectorShuffleAsElementInsertion(
7946 MVT VT, SDLoc DL, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7947 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7948 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7950 MVT EltVT = VT.getVectorElementType();
7952 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7953 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7955 bool IsV1Zeroable = true;
7956 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7957 if (i != V2Index && !Zeroable[i]) {
7958 IsV1Zeroable = false;
7962 // Check for a single input from a SCALAR_TO_VECTOR node.
7963 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7964 // all the smarts here sunk into that routine. However, the current
7965 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7966 // vector shuffle lowering is dead.
7967 if (SDValue V2S = getScalarValueForVectorElement(
7968 V2, Mask[V2Index] - Mask.size(), DAG)) {
7969 // We need to zext the scalar if it is smaller than an i32.
7970 V2S = DAG.getNode(ISD::BITCAST, DL, EltVT, V2S);
7971 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7972 // Using zext to expand a narrow element won't work for non-zero
7977 // Zero-extend directly to i32.
7979 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7981 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);
7982 } else if (Mask[V2Index] != (int)Mask.size() || EltVT == MVT::i8 ||
7983 EltVT == MVT::i16) {
7984 // Either not inserting from the low element of the input or the input
7985 // element size is too small to use VZEXT_MOVL to clear the high bits.
7989 if (!IsV1Zeroable) {
7990 // If V1 can't be treated as a zero vector we have fewer options to lower
7991 // this. We can't support integer vectors or non-zero targets cheaply, and
7992 // the V1 elements can't be permuted in any way.
7993 assert(VT == ExtVT && "Cannot change extended type when non-zeroable!");
7994 if (!VT.isFloatingPoint() || V2Index != 0)
7996 SmallVector<int, 8> V1Mask(Mask.begin(), Mask.end());
7997 V1Mask[V2Index] = -1;
7998 if (!isNoopShuffleMask(V1Mask))
8000 // This is essentially a special case blend operation, but if we have
8001 // general purpose blend operations, they are always faster. Bail and let
8002 // the rest of the lowering handle these as blends.
8003 if (Subtarget->hasSSE41())
8006 // Otherwise, use MOVSD or MOVSS.
8007 assert((EltVT == MVT::f32 || EltVT == MVT::f64) &&
8008 "Only two types of floating point element types to handle!");
8009 return DAG.getNode(EltVT == MVT::f32 ? X86ISD::MOVSS : X86ISD::MOVSD, DL,
8013 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2);
8015 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
8018 // If we have 4 or fewer lanes we can cheaply shuffle the element into
8019 // the desired position. Otherwise it is more efficient to do a vector
8020 // shift left. We know that we can do a vector shift left because all
8021 // the inputs are zero.
8022 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
8023 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
8024 V2Shuffle[V2Index] = 0;
8025 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
8027 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, V2);
8029 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
8031 V2Index * EltVT.getSizeInBits(),
8032 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(MVT::v2i64)));
8033 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
8039 /// \brief Try to lower broadcast of a single element.
8041 /// For convenience, this code also bundles all of the subtarget feature set
8042 /// filtering. While a little annoying to re-dispatch on type here, there isn't
8043 /// a convenient way to factor it out.
8044 static SDValue lowerVectorShuffleAsBroadcast(MVT VT, SDLoc DL, SDValue V,
8046 const X86Subtarget *Subtarget,
8047 SelectionDAG &DAG) {
8048 if (!Subtarget->hasAVX())
8050 if (VT.isInteger() && !Subtarget->hasAVX2())
8053 // Check that the mask is a broadcast.
8054 int BroadcastIdx = -1;
8056 if (M >= 0 && BroadcastIdx == -1)
8058 else if (M >= 0 && M != BroadcastIdx)
8061 assert(BroadcastIdx < (int)Mask.size() && "We only expect to be called with "
8062 "a sorted mask where the broadcast "
8065 // Go up the chain of (vector) values to try and find a scalar load that
8066 // we can combine with the broadcast.
8068 switch (V.getOpcode()) {
8069 case ISD::CONCAT_VECTORS: {
8070 int OperandSize = Mask.size() / V.getNumOperands();
8071 V = V.getOperand(BroadcastIdx / OperandSize);
8072 BroadcastIdx %= OperandSize;
8076 case ISD::INSERT_SUBVECTOR: {
8077 SDValue VOuter = V.getOperand(0), VInner = V.getOperand(1);
8078 auto ConstantIdx = dyn_cast<ConstantSDNode>(V.getOperand(2));
8082 int BeginIdx = (int)ConstantIdx->getZExtValue();
8084 BeginIdx + (int)VInner.getValueType().getVectorNumElements();
8085 if (BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx) {
8086 BroadcastIdx -= BeginIdx;
8097 // Check if this is a broadcast of a scalar. We special case lowering
8098 // for scalars so that we can more effectively fold with loads.
8099 if (V.getOpcode() == ISD::BUILD_VECTOR ||
8100 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)) {
8101 V = V.getOperand(BroadcastIdx);
8103 // If the scalar isn't a load we can't broadcast from it in AVX1, only with
8105 if (!Subtarget->hasAVX2() && !isShuffleFoldableLoad(V))
8107 } else if (BroadcastIdx != 0 || !Subtarget->hasAVX2()) {
8108 // We can't broadcast from a vector register w/o AVX2, and we can only
8109 // broadcast from the zero-element of a vector register.
8113 return DAG.getNode(X86ISD::VBROADCAST, DL, VT, V);
8116 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
8118 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
8119 /// support for floating point shuffles but not integer shuffles. These
8120 /// instructions will incur a domain crossing penalty on some chips though so
8121 /// it is better to avoid lowering through this for integer vectors where
8123 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8124 const X86Subtarget *Subtarget,
8125 SelectionDAG &DAG) {
8127 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
8128 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8129 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8130 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8131 ArrayRef<int> Mask = SVOp->getMask();
8132 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8134 if (isSingleInputShuffleMask(Mask)) {
8135 // Straight shuffle of a single input vector. Simulate this by using the
8136 // single input as both of the "inputs" to this instruction..
8137 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
8139 if (Subtarget->hasAVX()) {
8140 // If we have AVX, we can use VPERMILPS which will allow folding a load
8141 // into the shuffle.
8142 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
8143 DAG.getConstant(SHUFPDMask, MVT::i8));
8146 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V1,
8147 DAG.getConstant(SHUFPDMask, MVT::i8));
8149 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
8150 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
8152 // Use dedicated unpack instructions for masks that match their pattern.
8153 if (isShuffleEquivalent(Mask, 0, 2))
8154 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
8155 if (isShuffleEquivalent(Mask, 1, 3))
8156 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
8158 // If we have a single input, insert that into V1 if we can do so cheaply.
8159 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8160 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8161 MVT::v2f64, DL, V1, V2, Mask, Subtarget, DAG))
8163 // Try inverting the insertion since for v2 masks it is easy to do and we
8164 // can't reliably sort the mask one way or the other.
8165 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8166 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8167 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8168 MVT::v2f64, DL, V2, V1, InverseMask, Subtarget, DAG))
8172 // Try to use one of the special instruction patterns to handle two common
8173 // blend patterns if a zero-blend above didn't work.
8174 if (isShuffleEquivalent(Mask, 0, 3) || isShuffleEquivalent(Mask, 1, 3))
8175 if (SDValue V1S = getScalarValueForVectorElement(V1, Mask[0], DAG))
8176 // We can either use a special instruction to load over the low double or
8177 // to move just the low double.
8179 isShuffleFoldableLoad(V1S) ? X86ISD::MOVLPD : X86ISD::MOVSD,
8181 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64, V1S));
8183 if (Subtarget->hasSSE41())
8184 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
8188 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
8189 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V2,
8190 DAG.getConstant(SHUFPDMask, MVT::i8));
8193 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
8195 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
8196 /// the integer unit to minimize domain crossing penalties. However, for blends
8197 /// it falls back to the floating point shuffle operation with appropriate bit
8199 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8200 const X86Subtarget *Subtarget,
8201 SelectionDAG &DAG) {
8203 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
8204 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8205 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8206 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8207 ArrayRef<int> Mask = SVOp->getMask();
8208 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8210 if (isSingleInputShuffleMask(Mask)) {
8211 // Check for being able to broadcast a single element.
8212 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v2i64, DL, V1,
8213 Mask, Subtarget, DAG))
8216 // Straight shuffle of a single input vector. For everything from SSE2
8217 // onward this has a single fast instruction with no scary immediates.
8218 // We have to map the mask as it is actually a v4i32 shuffle instruction.
8219 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V1);
8220 int WidenedMask[4] = {
8221 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
8222 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
8224 ISD::BITCAST, DL, MVT::v2i64,
8225 DAG.getNode(X86ISD::PSHUFD, SDLoc(Op), MVT::v4i32, V1,
8226 getV4X86ShuffleImm8ForMask(WidenedMask, DAG)));
8229 // Try to use byte shift instructions.
8230 if (SDValue Shift = lowerVectorShuffleAsByteShift(
8231 DL, MVT::v2i64, V1, V2, Mask, DAG))
8234 // If we have a single input from V2 insert that into V1 if we can do so
8236 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8237 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8238 MVT::v2i64, DL, V1, V2, Mask, Subtarget, DAG))
8240 // Try inverting the insertion since for v2 masks it is easy to do and we
8241 // can't reliably sort the mask one way or the other.
8242 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8243 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8244 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8245 MVT::v2i64, DL, V2, V1, InverseMask, Subtarget, DAG))
8249 // Use dedicated unpack instructions for masks that match their pattern.
8250 if (isShuffleEquivalent(Mask, 0, 2))
8251 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
8252 if (isShuffleEquivalent(Mask, 1, 3))
8253 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
8255 if (Subtarget->hasSSE41())
8256 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
8260 // Try to use byte rotation instructions.
8261 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8262 if (Subtarget->hasSSSE3())
8263 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8264 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
8267 // We implement this with SHUFPD which is pretty lame because it will likely
8268 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
8269 // However, all the alternatives are still more cycles and newer chips don't
8270 // have this problem. It would be really nice if x86 had better shuffles here.
8271 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V1);
8272 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V2);
8273 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
8274 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
8277 /// \brief Lower a vector shuffle using the SHUFPS instruction.
8279 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
8280 /// It makes no assumptions about whether this is the *best* lowering, it simply
8282 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
8283 ArrayRef<int> Mask, SDValue V1,
8284 SDValue V2, SelectionDAG &DAG) {
8285 SDValue LowV = V1, HighV = V2;
8286 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
8289 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8291 if (NumV2Elements == 1) {
8293 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8296 // Compute the index adjacent to V2Index and in the same half by toggling
8298 int V2AdjIndex = V2Index ^ 1;
8300 if (Mask[V2AdjIndex] == -1) {
8301 // Handles all the cases where we have a single V2 element and an undef.
8302 // This will only ever happen in the high lanes because we commute the
8303 // vector otherwise.
8305 std::swap(LowV, HighV);
8306 NewMask[V2Index] -= 4;
8308 // Handle the case where the V2 element ends up adjacent to a V1 element.
8309 // To make this work, blend them together as the first step.
8310 int V1Index = V2AdjIndex;
8311 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
8312 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
8313 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
8315 // Now proceed to reconstruct the final blend as we have the necessary
8316 // high or low half formed.
8323 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
8324 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
8326 } else if (NumV2Elements == 2) {
8327 if (Mask[0] < 4 && Mask[1] < 4) {
8328 // Handle the easy case where we have V1 in the low lanes and V2 in the
8332 } else if (Mask[2] < 4 && Mask[3] < 4) {
8333 // We also handle the reversed case because this utility may get called
8334 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
8335 // arrange things in the right direction.
8341 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
8342 // trying to place elements directly, just blend them and set up the final
8343 // shuffle to place them.
8345 // The first two blend mask elements are for V1, the second two are for
8347 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
8348 Mask[2] < 4 ? Mask[2] : Mask[3],
8349 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
8350 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
8351 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
8352 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
8354 // Now we do a normal shuffle of V1 by giving V1 as both operands to
8357 NewMask[0] = Mask[0] < 4 ? 0 : 2;
8358 NewMask[1] = Mask[0] < 4 ? 2 : 0;
8359 NewMask[2] = Mask[2] < 4 ? 1 : 3;
8360 NewMask[3] = Mask[2] < 4 ? 3 : 1;
8363 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
8364 getV4X86ShuffleImm8ForMask(NewMask, DAG));
8367 /// \brief Lower 4-lane 32-bit floating point shuffles.
8369 /// Uses instructions exclusively from the floating point unit to minimize
8370 /// domain crossing penalties, as these are sufficient to implement all v4f32
8372 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8373 const X86Subtarget *Subtarget,
8374 SelectionDAG &DAG) {
8376 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8377 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8378 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8379 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8380 ArrayRef<int> Mask = SVOp->getMask();
8381 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8384 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8386 if (NumV2Elements == 0) {
8387 // Check for being able to broadcast a single element.
8388 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4f32, DL, V1,
8389 Mask, Subtarget, DAG))
8392 if (Subtarget->hasAVX()) {
8393 // If we have AVX, we can use VPERMILPS which will allow folding a load
8394 // into the shuffle.
8395 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
8396 getV4X86ShuffleImm8ForMask(Mask, DAG));
8399 // Otherwise, use a straight shuffle of a single input vector. We pass the
8400 // input vector to both operands to simulate this with a SHUFPS.
8401 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
8402 getV4X86ShuffleImm8ForMask(Mask, DAG));
8405 // Use dedicated unpack instructions for masks that match their pattern.
8406 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8407 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
8408 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8409 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
8411 // There are special ways we can lower some single-element blends. However, we
8412 // have custom ways we can lower more complex single-element blends below that
8413 // we defer to if both this and BLENDPS fail to match, so restrict this to
8414 // when the V2 input is targeting element 0 of the mask -- that is the fast
8416 if (NumV2Elements == 1 && Mask[0] >= 4)
8417 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4f32, DL, V1, V2,
8418 Mask, Subtarget, DAG))
8421 if (Subtarget->hasSSE41())
8422 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
8426 // Check for whether we can use INSERTPS to perform the blend. We only use
8427 // INSERTPS when the V1 elements are already in the correct locations
8428 // because otherwise we can just always use two SHUFPS instructions which
8429 // are much smaller to encode than a SHUFPS and an INSERTPS.
8430 if (NumV2Elements == 1 && Subtarget->hasSSE41()) {
8432 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8435 // When using INSERTPS we can zero any lane of the destination. Collect
8436 // the zero inputs into a mask and drop them from the lanes of V1 which
8437 // actually need to be present as inputs to the INSERTPS.
8438 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
8440 // Synthesize a shuffle mask for the non-zero and non-v2 inputs.
8441 bool InsertNeedsShuffle = false;
8443 for (int i = 0; i < 4; ++i)
8447 } else if (Mask[i] != i) {
8448 InsertNeedsShuffle = true;
8453 // We don't want to use INSERTPS or other insertion techniques if it will
8454 // require shuffling anyways.
8455 if (!InsertNeedsShuffle) {
8456 // If all of V1 is zeroable, replace it with undef.
8457 if ((ZMask | 1 << V2Index) == 0xF)
8458 V1 = DAG.getUNDEF(MVT::v4f32);
8460 unsigned InsertPSMask = (Mask[V2Index] - 4) << 6 | V2Index << 4 | ZMask;
8461 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
8463 // Insert the V2 element into the desired position.
8464 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
8465 DAG.getConstant(InsertPSMask, MVT::i8));
8469 // Otherwise fall back to a SHUFPS lowering strategy.
8470 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
8473 /// \brief Lower 4-lane i32 vector shuffles.
8475 /// We try to handle these with integer-domain shuffles where we can, but for
8476 /// blends we use the floating point domain blend instructions.
8477 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8478 const X86Subtarget *Subtarget,
8479 SelectionDAG &DAG) {
8481 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
8482 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8483 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8484 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8485 ArrayRef<int> Mask = SVOp->getMask();
8486 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8488 // Whenever we can lower this as a zext, that instruction is strictly faster
8489 // than any alternative. It also allows us to fold memory operands into the
8490 // shuffle in many cases.
8491 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
8492 Mask, Subtarget, DAG))
8496 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8498 if (NumV2Elements == 0) {
8499 // Check for being able to broadcast a single element.
8500 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4i32, DL, V1,
8501 Mask, Subtarget, DAG))
8504 // Straight shuffle of a single input vector. For everything from SSE2
8505 // onward this has a single fast instruction with no scary immediates.
8506 // We coerce the shuffle pattern to be compatible with UNPCK instructions
8507 // but we aren't actually going to use the UNPCK instruction because doing
8508 // so prevents folding a load into this instruction or making a copy.
8509 const int UnpackLoMask[] = {0, 0, 1, 1};
8510 const int UnpackHiMask[] = {2, 2, 3, 3};
8511 if (isShuffleEquivalent(Mask, 0, 0, 1, 1))
8512 Mask = UnpackLoMask;
8513 else if (isShuffleEquivalent(Mask, 2, 2, 3, 3))
8514 Mask = UnpackHiMask;
8516 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8517 getV4X86ShuffleImm8ForMask(Mask, DAG));
8520 // Try to use byte shift instructions.
8521 if (SDValue Shift = lowerVectorShuffleAsByteShift(
8522 DL, MVT::v4i32, V1, V2, Mask, DAG))
8525 // There are special ways we can lower some single-element blends.
8526 if (NumV2Elements == 1)
8527 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4i32, DL, V1, V2,
8528 Mask, Subtarget, DAG))
8531 // Use dedicated unpack instructions for masks that match their pattern.
8532 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8533 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
8534 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8535 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
8537 if (Subtarget->hasSSE41())
8538 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
8542 // Try to use byte rotation instructions.
8543 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8544 if (Subtarget->hasSSSE3())
8545 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8546 DL, MVT::v4i32, V1, V2, Mask, Subtarget, DAG))
8549 // We implement this with SHUFPS because it can blend from two vectors.
8550 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
8551 // up the inputs, bypassing domain shift penalties that we would encur if we
8552 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
8554 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i32,
8555 DAG.getVectorShuffle(
8557 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V1),
8558 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V2), Mask));
8561 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
8562 /// shuffle lowering, and the most complex part.
8564 /// The lowering strategy is to try to form pairs of input lanes which are
8565 /// targeted at the same half of the final vector, and then use a dword shuffle
8566 /// to place them onto the right half, and finally unpack the paired lanes into
8567 /// their final position.
8569 /// The exact breakdown of how to form these dword pairs and align them on the
8570 /// correct sides is really tricky. See the comments within the function for
8571 /// more of the details.
8572 static SDValue lowerV8I16SingleInputVectorShuffle(
8573 SDLoc DL, SDValue V, MutableArrayRef<int> Mask,
8574 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8575 assert(V.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8576 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8577 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8579 SmallVector<int, 4> LoInputs;
8580 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8581 [](int M) { return M >= 0; });
8582 std::sort(LoInputs.begin(), LoInputs.end());
8583 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8584 SmallVector<int, 4> HiInputs;
8585 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8586 [](int M) { return M >= 0; });
8587 std::sort(HiInputs.begin(), HiInputs.end());
8588 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8590 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8591 int NumHToL = LoInputs.size() - NumLToL;
8593 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8594 int NumHToH = HiInputs.size() - NumLToH;
8595 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8596 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8597 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8598 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8600 // Check for being able to broadcast a single element.
8601 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8i16, DL, V,
8602 Mask, Subtarget, DAG))
8605 // Try to use byte shift instructions.
8606 if (SDValue Shift = lowerVectorShuffleAsByteShift(
8607 DL, MVT::v8i16, V, V, Mask, DAG))
8610 // Use dedicated unpack instructions for masks that match their pattern.
8611 if (isShuffleEquivalent(Mask, 0, 0, 1, 1, 2, 2, 3, 3))
8612 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V, V);
8613 if (isShuffleEquivalent(Mask, 4, 4, 5, 5, 6, 6, 7, 7))
8614 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V, V);
8616 // Try to use byte rotation instructions.
8617 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8618 DL, MVT::v8i16, V, V, Mask, Subtarget, DAG))
8621 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8622 // such inputs we can swap two of the dwords across the half mark and end up
8623 // with <=2 inputs to each half in each half. Once there, we can fall through
8624 // to the generic code below. For example:
8626 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8627 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8629 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8630 // and an existing 2-into-2 on the other half. In this case we may have to
8631 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8632 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8633 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8634 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8635 // half than the one we target for fixing) will be fixed when we re-enter this
8636 // path. We will also combine away any sequence of PSHUFD instructions that
8637 // result into a single instruction. Here is an example of the tricky case:
8639 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8640 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8642 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8644 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8645 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8647 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8648 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8650 // The result is fine to be handled by the generic logic.
8651 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8652 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8653 int AOffset, int BOffset) {
8654 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8655 "Must call this with A having 3 or 1 inputs from the A half.");
8656 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8657 "Must call this with B having 1 or 3 inputs from the B half.");
8658 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8659 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8661 // Compute the index of dword with only one word among the three inputs in
8662 // a half by taking the sum of the half with three inputs and subtracting
8663 // the sum of the actual three inputs. The difference is the remaining
8666 int &TripleDWord = AToAInputs.size() == 3 ? ADWord : BDWord;
8667 int &OneInputDWord = AToAInputs.size() == 3 ? BDWord : ADWord;
8668 int TripleInputOffset = AToAInputs.size() == 3 ? AOffset : BOffset;
8669 ArrayRef<int> TripleInputs = AToAInputs.size() == 3 ? AToAInputs : BToAInputs;
8670 int OneInput = AToAInputs.size() == 3 ? BToAInputs[0] : AToAInputs[0];
8671 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8672 int TripleNonInputIdx =
8673 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8674 TripleDWord = TripleNonInputIdx / 2;
8676 // We use xor with one to compute the adjacent DWord to whichever one the
8678 OneInputDWord = (OneInput / 2) ^ 1;
8680 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8681 // and BToA inputs. If there is also such a problem with the BToB and AToB
8682 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8683 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8684 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8685 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8686 // Compute how many inputs will be flipped by swapping these DWords. We
8688 // to balance this to ensure we don't form a 3-1 shuffle in the other
8690 int NumFlippedAToBInputs =
8691 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8692 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8693 int NumFlippedBToBInputs =
8694 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8695 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8696 if ((NumFlippedAToBInputs == 1 &&
8697 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8698 (NumFlippedBToBInputs == 1 &&
8699 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8700 // We choose whether to fix the A half or B half based on whether that
8701 // half has zero flipped inputs. At zero, we may not be able to fix it
8702 // with that half. We also bias towards fixing the B half because that
8703 // will more commonly be the high half, and we have to bias one way.
8704 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8705 ArrayRef<int> Inputs) {
8706 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8707 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8708 PinnedIdx ^ 1) != Inputs.end();
8709 // Determine whether the free index is in the flipped dword or the
8710 // unflipped dword based on where the pinned index is. We use this bit
8711 // in an xor to conditionally select the adjacent dword.
8712 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8713 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8714 FixFreeIdx) != Inputs.end();
8715 if (IsFixIdxInput == IsFixFreeIdxInput)
8717 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8718 FixFreeIdx) != Inputs.end();
8719 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8720 "We need to be changing the number of flipped inputs!");
8721 int PSHUFHalfMask[] = {0, 1, 2, 3};
8722 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8723 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8725 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DAG));
8728 if (M != -1 && M == FixIdx)
8730 else if (M != -1 && M == FixFreeIdx)
8733 if (NumFlippedBToBInputs != 0) {
8735 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8736 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8738 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8740 AToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8741 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8746 int PSHUFDMask[] = {0, 1, 2, 3};
8747 PSHUFDMask[ADWord] = BDWord;
8748 PSHUFDMask[BDWord] = ADWord;
8749 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8750 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8751 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8752 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8754 // Adjust the mask to match the new locations of A and B.
8756 if (M != -1 && M/2 == ADWord)
8757 M = 2 * BDWord + M % 2;
8758 else if (M != -1 && M/2 == BDWord)
8759 M = 2 * ADWord + M % 2;
8761 // Recurse back into this routine to re-compute state now that this isn't
8762 // a 3 and 1 problem.
8763 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
8766 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8767 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8768 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8769 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8771 // At this point there are at most two inputs to the low and high halves from
8772 // each half. That means the inputs can always be grouped into dwords and
8773 // those dwords can then be moved to the correct half with a dword shuffle.
8774 // We use at most one low and one high word shuffle to collect these paired
8775 // inputs into dwords, and finally a dword shuffle to place them.
8776 int PSHUFLMask[4] = {-1, -1, -1, -1};
8777 int PSHUFHMask[4] = {-1, -1, -1, -1};
8778 int PSHUFDMask[4] = {-1, -1, -1, -1};
8780 // First fix the masks for all the inputs that are staying in their
8781 // original halves. This will then dictate the targets of the cross-half
8783 auto fixInPlaceInputs =
8784 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8785 MutableArrayRef<int> SourceHalfMask,
8786 MutableArrayRef<int> HalfMask, int HalfOffset) {
8787 if (InPlaceInputs.empty())
8789 if (InPlaceInputs.size() == 1) {
8790 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8791 InPlaceInputs[0] - HalfOffset;
8792 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8795 if (IncomingInputs.empty()) {
8796 // Just fix all of the in place inputs.
8797 for (int Input : InPlaceInputs) {
8798 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8799 PSHUFDMask[Input / 2] = Input / 2;
8804 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8805 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8806 InPlaceInputs[0] - HalfOffset;
8807 // Put the second input next to the first so that they are packed into
8808 // a dword. We find the adjacent index by toggling the low bit.
8809 int AdjIndex = InPlaceInputs[0] ^ 1;
8810 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8811 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8812 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8814 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8815 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8817 // Now gather the cross-half inputs and place them into a free dword of
8818 // their target half.
8819 // FIXME: This operation could almost certainly be simplified dramatically to
8820 // look more like the 3-1 fixing operation.
8821 auto moveInputsToRightHalf = [&PSHUFDMask](
8822 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8823 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8824 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8826 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8827 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8829 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8831 int LowWord = Word & ~1;
8832 int HighWord = Word | 1;
8833 return isWordClobbered(SourceHalfMask, LowWord) ||
8834 isWordClobbered(SourceHalfMask, HighWord);
8837 if (IncomingInputs.empty())
8840 if (ExistingInputs.empty()) {
8841 // Map any dwords with inputs from them into the right half.
8842 for (int Input : IncomingInputs) {
8843 // If the source half mask maps over the inputs, turn those into
8844 // swaps and use the swapped lane.
8845 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8846 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8847 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8848 Input - SourceOffset;
8849 // We have to swap the uses in our half mask in one sweep.
8850 for (int &M : HalfMask)
8851 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8853 else if (M == Input)
8854 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8856 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8857 Input - SourceOffset &&
8858 "Previous placement doesn't match!");
8860 // Note that this correctly re-maps both when we do a swap and when
8861 // we observe the other side of the swap above. We rely on that to
8862 // avoid swapping the members of the input list directly.
8863 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8866 // Map the input's dword into the correct half.
8867 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8868 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8870 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8872 "Previous placement doesn't match!");
8875 // And just directly shift any other-half mask elements to be same-half
8876 // as we will have mirrored the dword containing the element into the
8877 // same position within that half.
8878 for (int &M : HalfMask)
8879 if (M >= SourceOffset && M < SourceOffset + 4) {
8880 M = M - SourceOffset + DestOffset;
8881 assert(M >= 0 && "This should never wrap below zero!");
8886 // Ensure we have the input in a viable dword of its current half. This
8887 // is particularly tricky because the original position may be clobbered
8888 // by inputs being moved and *staying* in that half.
8889 if (IncomingInputs.size() == 1) {
8890 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8891 int InputFixed = std::find(std::begin(SourceHalfMask),
8892 std::end(SourceHalfMask), -1) -
8893 std::begin(SourceHalfMask) + SourceOffset;
8894 SourceHalfMask[InputFixed - SourceOffset] =
8895 IncomingInputs[0] - SourceOffset;
8896 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8898 IncomingInputs[0] = InputFixed;
8900 } else if (IncomingInputs.size() == 2) {
8901 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8902 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8903 // We have two non-adjacent or clobbered inputs we need to extract from
8904 // the source half. To do this, we need to map them into some adjacent
8905 // dword slot in the source mask.
8906 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8907 IncomingInputs[1] - SourceOffset};
8909 // If there is a free slot in the source half mask adjacent to one of
8910 // the inputs, place the other input in it. We use (Index XOR 1) to
8911 // compute an adjacent index.
8912 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8913 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8914 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8915 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8916 InputsFixed[1] = InputsFixed[0] ^ 1;
8917 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
8918 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
8919 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
8920 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
8921 InputsFixed[0] = InputsFixed[1] ^ 1;
8922 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
8923 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
8924 // The two inputs are in the same DWord but it is clobbered and the
8925 // adjacent DWord isn't used at all. Move both inputs to the free
8927 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
8928 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
8929 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
8930 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
8932 // The only way we hit this point is if there is no clobbering
8933 // (because there are no off-half inputs to this half) and there is no
8934 // free slot adjacent to one of the inputs. In this case, we have to
8935 // swap an input with a non-input.
8936 for (int i = 0; i < 4; ++i)
8937 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
8938 "We can't handle any clobbers here!");
8939 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
8940 "Cannot have adjacent inputs here!");
8942 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8943 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
8945 // We also have to update the final source mask in this case because
8946 // it may need to undo the above swap.
8947 for (int &M : FinalSourceHalfMask)
8948 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
8949 M = InputsFixed[1] + SourceOffset;
8950 else if (M == InputsFixed[1] + SourceOffset)
8951 M = (InputsFixed[0] ^ 1) + SourceOffset;
8953 InputsFixed[1] = InputsFixed[0] ^ 1;
8956 // Point everything at the fixed inputs.
8957 for (int &M : HalfMask)
8958 if (M == IncomingInputs[0])
8959 M = InputsFixed[0] + SourceOffset;
8960 else if (M == IncomingInputs[1])
8961 M = InputsFixed[1] + SourceOffset;
8963 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
8964 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
8967 llvm_unreachable("Unhandled input size!");
8970 // Now hoist the DWord down to the right half.
8971 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
8972 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
8973 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
8974 for (int &M : HalfMask)
8975 for (int Input : IncomingInputs)
8977 M = FreeDWord * 2 + Input % 2;
8979 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
8980 /*SourceOffset*/ 4, /*DestOffset*/ 0);
8981 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
8982 /*SourceOffset*/ 0, /*DestOffset*/ 4);
8984 // Now enact all the shuffles we've computed to move the inputs into their
8986 if (!isNoopShuffleMask(PSHUFLMask))
8987 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
8988 getV4X86ShuffleImm8ForMask(PSHUFLMask, DAG));
8989 if (!isNoopShuffleMask(PSHUFHMask))
8990 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
8991 getV4X86ShuffleImm8ForMask(PSHUFHMask, DAG));
8992 if (!isNoopShuffleMask(PSHUFDMask))
8993 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8994 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8995 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8996 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8998 // At this point, each half should contain all its inputs, and we can then
8999 // just shuffle them into their final position.
9000 assert(std::count_if(LoMask.begin(), LoMask.end(),
9001 [](int M) { return M >= 4; }) == 0 &&
9002 "Failed to lift all the high half inputs to the low mask!");
9003 assert(std::count_if(HiMask.begin(), HiMask.end(),
9004 [](int M) { return M >= 0 && M < 4; }) == 0 &&
9005 "Failed to lift all the low half inputs to the high mask!");
9007 // Do a half shuffle for the low mask.
9008 if (!isNoopShuffleMask(LoMask))
9009 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
9010 getV4X86ShuffleImm8ForMask(LoMask, DAG));
9012 // Do a half shuffle with the high mask after shifting its values down.
9013 for (int &M : HiMask)
9016 if (!isNoopShuffleMask(HiMask))
9017 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
9018 getV4X86ShuffleImm8ForMask(HiMask, DAG));
9023 /// \brief Detect whether the mask pattern should be lowered through
9026 /// This essentially tests whether viewing the mask as an interleaving of two
9027 /// sub-sequences reduces the cross-input traffic of a blend operation. If so,
9028 /// lowering it through interleaving is a significantly better strategy.
9029 static bool shouldLowerAsInterleaving(ArrayRef<int> Mask) {
9030 int NumEvenInputs[2] = {0, 0};
9031 int NumOddInputs[2] = {0, 0};
9032 int NumLoInputs[2] = {0, 0};
9033 int NumHiInputs[2] = {0, 0};
9034 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
9038 int InputIdx = Mask[i] >= Size;
9041 ++NumLoInputs[InputIdx];
9043 ++NumHiInputs[InputIdx];
9046 ++NumEvenInputs[InputIdx];
9048 ++NumOddInputs[InputIdx];
9051 // The minimum number of cross-input results for both the interleaved and
9052 // split cases. If interleaving results in fewer cross-input results, return
9054 int InterleavedCrosses = std::min(NumEvenInputs[1] + NumOddInputs[0],
9055 NumEvenInputs[0] + NumOddInputs[1]);
9056 int SplitCrosses = std::min(NumLoInputs[1] + NumHiInputs[0],
9057 NumLoInputs[0] + NumHiInputs[1]);
9058 return InterleavedCrosses < SplitCrosses;
9061 /// \brief Blend two v8i16 vectors using a naive unpack strategy.
9063 /// This strategy only works when the inputs from each vector fit into a single
9064 /// half of that vector, and generally there are not so many inputs as to leave
9065 /// the in-place shuffles required highly constrained (and thus expensive). It
9066 /// shifts all the inputs into a single side of both input vectors and then
9067 /// uses an unpack to interleave these inputs in a single vector. At that
9068 /// point, we will fall back on the generic single input shuffle lowering.
9069 static SDValue lowerV8I16BasicBlendVectorShuffle(SDLoc DL, SDValue V1,
9071 MutableArrayRef<int> Mask,
9072 const X86Subtarget *Subtarget,
9073 SelectionDAG &DAG) {
9074 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
9075 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
9076 SmallVector<int, 3> LoV1Inputs, HiV1Inputs, LoV2Inputs, HiV2Inputs;
9077 for (int i = 0; i < 8; ++i)
9078 if (Mask[i] >= 0 && Mask[i] < 4)
9079 LoV1Inputs.push_back(i);
9080 else if (Mask[i] >= 4 && Mask[i] < 8)
9081 HiV1Inputs.push_back(i);
9082 else if (Mask[i] >= 8 && Mask[i] < 12)
9083 LoV2Inputs.push_back(i);
9084 else if (Mask[i] >= 12)
9085 HiV2Inputs.push_back(i);
9087 int NumV1Inputs = LoV1Inputs.size() + HiV1Inputs.size();
9088 int NumV2Inputs = LoV2Inputs.size() + HiV2Inputs.size();
9091 assert(NumV1Inputs > 0 && NumV1Inputs <= 3 && "At most 3 inputs supported");
9092 assert(NumV2Inputs > 0 && NumV2Inputs <= 3 && "At most 3 inputs supported");
9093 assert(NumV1Inputs + NumV2Inputs <= 4 && "At most 4 combined inputs");
9095 bool MergeFromLo = LoV1Inputs.size() + LoV2Inputs.size() >=
9096 HiV1Inputs.size() + HiV2Inputs.size();
9098 auto moveInputsToHalf = [&](SDValue V, ArrayRef<int> LoInputs,
9099 ArrayRef<int> HiInputs, bool MoveToLo,
9101 ArrayRef<int> GoodInputs = MoveToLo ? LoInputs : HiInputs;
9102 ArrayRef<int> BadInputs = MoveToLo ? HiInputs : LoInputs;
9103 if (BadInputs.empty())
9106 int MoveMask[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9107 int MoveOffset = MoveToLo ? 0 : 4;
9109 if (GoodInputs.empty()) {
9110 for (int BadInput : BadInputs) {
9111 MoveMask[Mask[BadInput] % 4 + MoveOffset] = Mask[BadInput] - MaskOffset;
9112 Mask[BadInput] = Mask[BadInput] % 4 + MoveOffset + MaskOffset;
9115 if (GoodInputs.size() == 2) {
9116 // If the low inputs are spread across two dwords, pack them into
9118 MoveMask[MoveOffset] = Mask[GoodInputs[0]] - MaskOffset;
9119 MoveMask[MoveOffset + 1] = Mask[GoodInputs[1]] - MaskOffset;
9120 Mask[GoodInputs[0]] = MoveOffset + MaskOffset;
9121 Mask[GoodInputs[1]] = MoveOffset + 1 + MaskOffset;
9123 // Otherwise pin the good inputs.
9124 for (int GoodInput : GoodInputs)
9125 MoveMask[Mask[GoodInput] - MaskOffset] = Mask[GoodInput] - MaskOffset;
9128 if (BadInputs.size() == 2) {
9129 // If we have two bad inputs then there may be either one or two good
9130 // inputs fixed in place. Find a fixed input, and then find the *other*
9131 // two adjacent indices by using modular arithmetic.
9133 std::find_if(std::begin(MoveMask) + MoveOffset, std::end(MoveMask),
9134 [](int M) { return M >= 0; }) -
9135 std::begin(MoveMask);
9137 ((((GoodMaskIdx - MoveOffset) & ~1) + 2) % 4) + MoveOffset;
9138 assert(MoveMask[MoveMaskIdx] == -1 && "Expected empty slot");
9139 assert(MoveMask[MoveMaskIdx + 1] == -1 && "Expected empty slot");
9140 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
9141 MoveMask[MoveMaskIdx + 1] = Mask[BadInputs[1]] - MaskOffset;
9142 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
9143 Mask[BadInputs[1]] = MoveMaskIdx + 1 + MaskOffset;
9145 assert(BadInputs.size() == 1 && "All sizes handled");
9146 int MoveMaskIdx = std::find(std::begin(MoveMask) + MoveOffset,
9147 std::end(MoveMask), -1) -
9148 std::begin(MoveMask);
9149 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
9150 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
9154 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
9157 V1 = moveInputsToHalf(V1, LoV1Inputs, HiV1Inputs, MergeFromLo,
9159 V2 = moveInputsToHalf(V2, LoV2Inputs, HiV2Inputs, MergeFromLo,
9162 // FIXME: Select an interleaving of the merge of V1 and V2 that minimizes
9163 // cross-half traffic in the final shuffle.
9165 // Munge the mask to be a single-input mask after the unpack merges the
9169 M = 2 * (M % 4) + (M / 8);
9171 return DAG.getVectorShuffle(
9172 MVT::v8i16, DL, DAG.getNode(MergeFromLo ? X86ISD::UNPCKL : X86ISD::UNPCKH,
9173 DL, MVT::v8i16, V1, V2),
9174 DAG.getUNDEF(MVT::v8i16), Mask);
9177 /// \brief Generic lowering of 8-lane i16 shuffles.
9179 /// This handles both single-input shuffles and combined shuffle/blends with
9180 /// two inputs. The single input shuffles are immediately delegated to
9181 /// a dedicated lowering routine.
9183 /// The blends are lowered in one of three fundamental ways. If there are few
9184 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
9185 /// of the input is significantly cheaper when lowered as an interleaving of
9186 /// the two inputs, try to interleave them. Otherwise, blend the low and high
9187 /// halves of the inputs separately (making them have relatively few inputs)
9188 /// and then concatenate them.
9189 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9190 const X86Subtarget *Subtarget,
9191 SelectionDAG &DAG) {
9193 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
9194 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9195 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9196 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9197 ArrayRef<int> OrigMask = SVOp->getMask();
9198 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9199 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
9200 MutableArrayRef<int> Mask(MaskStorage);
9202 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9204 // Whenever we can lower this as a zext, that instruction is strictly faster
9205 // than any alternative.
9206 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9207 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
9210 auto isV1 = [](int M) { return M >= 0 && M < 8; };
9211 auto isV2 = [](int M) { return M >= 8; };
9213 int NumV1Inputs = std::count_if(Mask.begin(), Mask.end(), isV1);
9214 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
9216 if (NumV2Inputs == 0)
9217 return lowerV8I16SingleInputVectorShuffle(DL, V1, Mask, Subtarget, DAG);
9219 assert(NumV1Inputs > 0 && "All single-input shuffles should be canonicalized "
9220 "to be V1-input shuffles.");
9222 // Try to use byte shift instructions.
9223 if (SDValue Shift = lowerVectorShuffleAsByteShift(
9224 DL, MVT::v8i16, V1, V2, Mask, DAG))
9227 // There are special ways we can lower some single-element blends.
9228 if (NumV2Inputs == 1)
9229 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v8i16, DL, V1, V2,
9230 Mask, Subtarget, DAG))
9233 // Use dedicated unpack instructions for masks that match their pattern.
9234 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 2, 10, 3, 11))
9235 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V2);
9236 if (isShuffleEquivalent(Mask, 4, 12, 5, 13, 6, 14, 7, 15))
9237 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V2);
9239 if (Subtarget->hasSSE41())
9240 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
9244 // Try to use byte rotation instructions.
9245 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9246 DL, MVT::v8i16, V1, V2, Mask, Subtarget, DAG))
9249 if (NumV1Inputs + NumV2Inputs <= 4)
9250 return lowerV8I16BasicBlendVectorShuffle(DL, V1, V2, Mask, Subtarget, DAG);
9252 // Check whether an interleaving lowering is likely to be more efficient.
9253 // This isn't perfect but it is a strong heuristic that tends to work well on
9254 // the kinds of shuffles that show up in practice.
9256 // FIXME: Handle 1x, 2x, and 4x interleaving.
9257 if (shouldLowerAsInterleaving(Mask)) {
9258 // FIXME: Figure out whether we should pack these into the low or high
9261 int EMask[8], OMask[8];
9262 for (int i = 0; i < 4; ++i) {
9263 EMask[i] = Mask[2*i];
9264 OMask[i] = Mask[2*i + 1];
9269 SDValue Evens = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, EMask);
9270 SDValue Odds = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, OMask);
9272 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, Evens, Odds);
9275 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9276 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9278 for (int i = 0; i < 4; ++i) {
9279 LoBlendMask[i] = Mask[i];
9280 HiBlendMask[i] = Mask[i + 4];
9283 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9284 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9285 LoV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, LoV);
9286 HiV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, HiV);
9288 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9289 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, LoV, HiV));
9292 /// \brief Check whether a compaction lowering can be done by dropping even
9293 /// elements and compute how many times even elements must be dropped.
9295 /// This handles shuffles which take every Nth element where N is a power of
9296 /// two. Example shuffle masks:
9298 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
9299 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
9300 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
9301 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
9302 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
9303 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
9305 /// Any of these lanes can of course be undef.
9307 /// This routine only supports N <= 3.
9308 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
9311 /// \returns N above, or the number of times even elements must be dropped if
9312 /// there is such a number. Otherwise returns zero.
9313 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
9314 // Figure out whether we're looping over two inputs or just one.
9315 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9317 // The modulus for the shuffle vector entries is based on whether this is
9318 // a single input or not.
9319 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
9320 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
9321 "We should only be called with masks with a power-of-2 size!");
9323 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
9325 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
9326 // and 2^3 simultaneously. This is because we may have ambiguity with
9327 // partially undef inputs.
9328 bool ViableForN[3] = {true, true, true};
9330 for (int i = 0, e = Mask.size(); i < e; ++i) {
9331 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
9336 bool IsAnyViable = false;
9337 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9338 if (ViableForN[j]) {
9341 // The shuffle mask must be equal to (i * 2^N) % M.
9342 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
9345 ViableForN[j] = false;
9347 // Early exit if we exhaust the possible powers of two.
9352 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9356 // Return 0 as there is no viable power of two.
9360 /// \brief Generic lowering of v16i8 shuffles.
9362 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
9363 /// detect any complexity reducing interleaving. If that doesn't help, it uses
9364 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
9365 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
9367 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9368 const X86Subtarget *Subtarget,
9369 SelectionDAG &DAG) {
9371 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
9372 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9373 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9374 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9375 ArrayRef<int> OrigMask = SVOp->getMask();
9376 assert(OrigMask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9378 // Try to use byte shift instructions.
9379 if (SDValue Shift = lowerVectorShuffleAsByteShift(
9380 DL, MVT::v16i8, V1, V2, OrigMask, DAG))
9383 // Try to use byte rotation instructions.
9384 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9385 DL, MVT::v16i8, V1, V2, OrigMask, Subtarget, DAG))
9388 // Try to use a zext lowering.
9389 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9390 DL, MVT::v16i8, V1, V2, OrigMask, Subtarget, DAG))
9393 int MaskStorage[16] = {
9394 OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9395 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7],
9396 OrigMask[8], OrigMask[9], OrigMask[10], OrigMask[11],
9397 OrigMask[12], OrigMask[13], OrigMask[14], OrigMask[15]};
9398 MutableArrayRef<int> Mask(MaskStorage);
9399 MutableArrayRef<int> LoMask = Mask.slice(0, 8);
9400 MutableArrayRef<int> HiMask = Mask.slice(8, 8);
9403 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
9405 // For single-input shuffles, there are some nicer lowering tricks we can use.
9406 if (NumV2Elements == 0) {
9407 // Check for being able to broadcast a single element.
9408 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v16i8, DL, V1,
9409 Mask, Subtarget, DAG))
9412 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
9413 // Notably, this handles splat and partial-splat shuffles more efficiently.
9414 // However, it only makes sense if the pre-duplication shuffle simplifies
9415 // things significantly. Currently, this means we need to be able to
9416 // express the pre-duplication shuffle as an i16 shuffle.
9418 // FIXME: We should check for other patterns which can be widened into an
9419 // i16 shuffle as well.
9420 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
9421 for (int i = 0; i < 16; i += 2)
9422 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
9427 auto tryToWidenViaDuplication = [&]() -> SDValue {
9428 if (!canWidenViaDuplication(Mask))
9430 SmallVector<int, 4> LoInputs;
9431 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
9432 [](int M) { return M >= 0 && M < 8; });
9433 std::sort(LoInputs.begin(), LoInputs.end());
9434 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
9436 SmallVector<int, 4> HiInputs;
9437 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
9438 [](int M) { return M >= 8; });
9439 std::sort(HiInputs.begin(), HiInputs.end());
9440 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
9443 bool TargetLo = LoInputs.size() >= HiInputs.size();
9444 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
9445 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
9447 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9448 SmallDenseMap<int, int, 8> LaneMap;
9449 for (int I : InPlaceInputs) {
9450 PreDupI16Shuffle[I/2] = I/2;
9453 int j = TargetLo ? 0 : 4, je = j + 4;
9454 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
9455 // Check if j is already a shuffle of this input. This happens when
9456 // there are two adjacent bytes after we move the low one.
9457 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
9458 // If we haven't yet mapped the input, search for a slot into which
9460 while (j < je && PreDupI16Shuffle[j] != -1)
9464 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
9467 // Map this input with the i16 shuffle.
9468 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
9471 // Update the lane map based on the mapping we ended up with.
9472 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
9475 ISD::BITCAST, DL, MVT::v16i8,
9476 DAG.getVectorShuffle(MVT::v8i16, DL,
9477 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9478 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
9480 // Unpack the bytes to form the i16s that will be shuffled into place.
9481 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9482 MVT::v16i8, V1, V1);
9484 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9485 for (int i = 0; i < 16; ++i)
9486 if (Mask[i] != -1) {
9487 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
9488 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
9489 if (PostDupI16Shuffle[i / 2] == -1)
9490 PostDupI16Shuffle[i / 2] = MappedMask;
9492 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
9493 "Conflicting entrties in the original shuffle!");
9496 ISD::BITCAST, DL, MVT::v16i8,
9497 DAG.getVectorShuffle(MVT::v8i16, DL,
9498 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9499 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
9501 if (SDValue V = tryToWidenViaDuplication())
9505 // Check whether an interleaving lowering is likely to be more efficient.
9506 // This isn't perfect but it is a strong heuristic that tends to work well on
9507 // the kinds of shuffles that show up in practice.
9509 // FIXME: We need to handle other interleaving widths (i16, i32, ...).
9510 if (shouldLowerAsInterleaving(Mask)) {
9511 int NumLoHalf = std::count_if(Mask.begin(), Mask.end(), [](int M) {
9512 return (M >= 0 && M < 8) || (M >= 16 && M < 24);
9514 int NumHiHalf = std::count_if(Mask.begin(), Mask.end(), [](int M) {
9515 return (M >= 8 && M < 16) || M >= 24;
9517 int EMask[16] = {-1, -1, -1, -1, -1, -1, -1, -1,
9518 -1, -1, -1, -1, -1, -1, -1, -1};
9519 int OMask[16] = {-1, -1, -1, -1, -1, -1, -1, -1,
9520 -1, -1, -1, -1, -1, -1, -1, -1};
9521 bool UnpackLo = NumLoHalf >= NumHiHalf;
9522 MutableArrayRef<int> TargetEMask(UnpackLo ? EMask : EMask + 8, 8);
9523 MutableArrayRef<int> TargetOMask(UnpackLo ? OMask : OMask + 8, 8);
9524 for (int i = 0; i < 8; ++i) {
9525 TargetEMask[i] = Mask[2 * i];
9526 TargetOMask[i] = Mask[2 * i + 1];
9529 SDValue Evens = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, EMask);
9530 SDValue Odds = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, OMask);
9532 return DAG.getNode(UnpackLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9533 MVT::v16i8, Evens, Odds);
9536 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
9537 // with PSHUFB. It is important to do this before we attempt to generate any
9538 // blends but after all of the single-input lowerings. If the single input
9539 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
9540 // want to preserve that and we can DAG combine any longer sequences into
9541 // a PSHUFB in the end. But once we start blending from multiple inputs,
9542 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
9543 // and there are *very* few patterns that would actually be faster than the
9544 // PSHUFB approach because of its ability to zero lanes.
9546 // FIXME: The only exceptions to the above are blends which are exact
9547 // interleavings with direct instructions supporting them. We currently don't
9548 // handle those well here.
9549 if (Subtarget->hasSSSE3()) {
9552 for (int i = 0; i < 16; ++i)
9553 if (Mask[i] == -1) {
9554 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
9556 V1Mask[i] = DAG.getConstant(Mask[i] < 16 ? Mask[i] : 0x80, MVT::i8);
9558 DAG.getConstant(Mask[i] < 16 ? 0x80 : Mask[i] - 16, MVT::i8);
9560 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V1,
9561 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
9562 if (isSingleInputShuffleMask(Mask))
9563 return V1; // Single inputs are easy.
9565 // Otherwise, blend the two.
9566 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V2,
9567 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
9568 return DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
9571 // There are special ways we can lower some single-element blends.
9572 if (NumV2Elements == 1)
9573 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v16i8, DL, V1, V2,
9574 Mask, Subtarget, DAG))
9577 // Check whether a compaction lowering can be done. This handles shuffles
9578 // which take every Nth element for some even N. See the helper function for
9581 // We special case these as they can be particularly efficiently handled with
9582 // the PACKUSB instruction on x86 and they show up in common patterns of
9583 // rearranging bytes to truncate wide elements.
9584 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
9585 // NumEvenDrops is the power of two stride of the elements. Another way of
9586 // thinking about it is that we need to drop the even elements this many
9587 // times to get the original input.
9588 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9590 // First we need to zero all the dropped bytes.
9591 assert(NumEvenDrops <= 3 &&
9592 "No support for dropping even elements more than 3 times.");
9593 // We use the mask type to pick which bytes are preserved based on how many
9594 // elements are dropped.
9595 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
9596 SDValue ByteClearMask =
9597 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8,
9598 DAG.getConstant(0xFF, MaskVTs[NumEvenDrops - 1]));
9599 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
9601 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
9603 // Now pack things back together.
9604 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
9605 V2 = IsSingleInput ? V1 : DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
9606 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
9607 for (int i = 1; i < NumEvenDrops; ++i) {
9608 Result = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, Result);
9609 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
9615 int V1LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9616 int V1HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9617 int V2LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9618 int V2HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9620 auto buildBlendMasks = [](MutableArrayRef<int> HalfMask,
9621 MutableArrayRef<int> V1HalfBlendMask,
9622 MutableArrayRef<int> V2HalfBlendMask) {
9623 for (int i = 0; i < 8; ++i)
9624 if (HalfMask[i] >= 0 && HalfMask[i] < 16) {
9625 V1HalfBlendMask[i] = HalfMask[i];
9627 } else if (HalfMask[i] >= 16) {
9628 V2HalfBlendMask[i] = HalfMask[i] - 16;
9629 HalfMask[i] = i + 8;
9632 buildBlendMasks(LoMask, V1LoBlendMask, V2LoBlendMask);
9633 buildBlendMasks(HiMask, V1HiBlendMask, V2HiBlendMask);
9635 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
9637 auto buildLoAndHiV8s = [&](SDValue V, MutableArrayRef<int> LoBlendMask,
9638 MutableArrayRef<int> HiBlendMask) {
9640 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
9641 // them out and avoid using UNPCK{L,H} to extract the elements of V as
9643 if (std::none_of(LoBlendMask.begin(), LoBlendMask.end(),
9644 [](int M) { return M >= 0 && M % 2 == 1; }) &&
9645 std::none_of(HiBlendMask.begin(), HiBlendMask.end(),
9646 [](int M) { return M >= 0 && M % 2 == 1; })) {
9647 // Use a mask to drop the high bytes.
9648 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
9649 V1 = DAG.getNode(ISD::AND, DL, MVT::v8i16, V1,
9650 DAG.getConstant(0x00FF, MVT::v8i16));
9652 // This will be a single vector shuffle instead of a blend so nuke V2.
9653 V2 = DAG.getUNDEF(MVT::v8i16);
9655 // Squash the masks to point directly into V1.
9656 for (int &M : LoBlendMask)
9659 for (int &M : HiBlendMask)
9663 // Otherwise just unpack the low half of V into V1 and the high half into
9664 // V2 so that we can blend them as i16s.
9665 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9666 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
9667 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9668 DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
9671 SDValue BlendedLo = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9672 SDValue BlendedHi = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9673 return std::make_pair(BlendedLo, BlendedHi);
9675 SDValue V1Lo, V1Hi, V2Lo, V2Hi;
9676 std::tie(V1Lo, V1Hi) = buildLoAndHiV8s(V1, V1LoBlendMask, V1HiBlendMask);
9677 std::tie(V2Lo, V2Hi) = buildLoAndHiV8s(V2, V2LoBlendMask, V2HiBlendMask);
9679 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Lo, V2Lo, LoMask);
9680 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Hi, V2Hi, HiMask);
9682 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
9685 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
9687 /// This routine breaks down the specific type of 128-bit shuffle and
9688 /// dispatches to the lowering routines accordingly.
9689 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9690 MVT VT, const X86Subtarget *Subtarget,
9691 SelectionDAG &DAG) {
9692 switch (VT.SimpleTy) {
9694 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9696 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9698 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9700 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9702 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9704 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9707 llvm_unreachable("Unimplemented!");
9711 /// \brief Helper function to test whether a shuffle mask could be
9712 /// simplified by widening the elements being shuffled.
9714 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
9715 /// leaves it in an unspecified state.
9717 /// NOTE: This must handle normal vector shuffle masks and *target* vector
9718 /// shuffle masks. The latter have the special property of a '-2' representing
9719 /// a zero-ed lane of a vector.
9720 static bool canWidenShuffleElements(ArrayRef<int> Mask,
9721 SmallVectorImpl<int> &WidenedMask) {
9722 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
9723 // If both elements are undef, its trivial.
9724 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
9725 WidenedMask.push_back(SM_SentinelUndef);
9729 // Check for an undef mask and a mask value properly aligned to fit with
9730 // a pair of values. If we find such a case, use the non-undef mask's value.
9731 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
9732 WidenedMask.push_back(Mask[i + 1] / 2);
9735 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
9736 WidenedMask.push_back(Mask[i] / 2);
9740 // When zeroing, we need to spread the zeroing across both lanes to widen.
9741 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
9742 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
9743 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
9744 WidenedMask.push_back(SM_SentinelZero);
9750 // Finally check if the two mask values are adjacent and aligned with
9752 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
9753 WidenedMask.push_back(Mask[i] / 2);
9757 // Otherwise we can't safely widen the elements used in this shuffle.
9760 assert(WidenedMask.size() == Mask.size() / 2 &&
9761 "Incorrect size of mask after widening the elements!");
9766 /// \brief Generic routine to split ector shuffle into half-sized shuffles.
9768 /// This routine just extracts two subvectors, shuffles them independently, and
9769 /// then concatenates them back together. This should work effectively with all
9770 /// AVX vector shuffle types.
9771 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9772 SDValue V2, ArrayRef<int> Mask,
9773 SelectionDAG &DAG) {
9774 assert(VT.getSizeInBits() >= 256 &&
9775 "Only for 256-bit or wider vector shuffles!");
9776 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9777 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9779 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
9780 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
9782 int NumElements = VT.getVectorNumElements();
9783 int SplitNumElements = NumElements / 2;
9784 MVT ScalarVT = VT.getScalarType();
9785 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9787 SDValue LoV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9788 DAG.getIntPtrConstant(0));
9789 SDValue HiV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9790 DAG.getIntPtrConstant(SplitNumElements));
9791 SDValue LoV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9792 DAG.getIntPtrConstant(0));
9793 SDValue HiV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9794 DAG.getIntPtrConstant(SplitNumElements));
9796 // Now create two 4-way blends of these half-width vectors.
9797 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9798 bool UseLoV1 = false, UseHiV1 = false, UseLoV2 = false, UseHiV2 = false;
9799 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
9800 for (int i = 0; i < SplitNumElements; ++i) {
9801 int M = HalfMask[i];
9802 if (M >= NumElements) {
9803 if (M >= NumElements + SplitNumElements)
9807 V2BlendMask.push_back(M - NumElements);
9808 V1BlendMask.push_back(-1);
9809 BlendMask.push_back(SplitNumElements + i);
9810 } else if (M >= 0) {
9811 if (M >= SplitNumElements)
9815 V2BlendMask.push_back(-1);
9816 V1BlendMask.push_back(M);
9817 BlendMask.push_back(i);
9819 V2BlendMask.push_back(-1);
9820 V1BlendMask.push_back(-1);
9821 BlendMask.push_back(-1);
9825 // Because the lowering happens after all combining takes place, we need to
9826 // manually combine these blend masks as much as possible so that we create
9827 // a minimal number of high-level vector shuffle nodes.
9829 // First try just blending the halves of V1 or V2.
9830 if (!UseLoV1 && !UseHiV1 && !UseLoV2 && !UseHiV2)
9831 return DAG.getUNDEF(SplitVT);
9832 if (!UseLoV2 && !UseHiV2)
9833 return DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9834 if (!UseLoV1 && !UseHiV1)
9835 return DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9837 SDValue V1Blend, V2Blend;
9838 if (UseLoV1 && UseHiV1) {
9840 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9842 // We only use half of V1 so map the usage down into the final blend mask.
9843 V1Blend = UseLoV1 ? LoV1 : HiV1;
9844 for (int i = 0; i < SplitNumElements; ++i)
9845 if (BlendMask[i] >= 0 && BlendMask[i] < SplitNumElements)
9846 BlendMask[i] = V1BlendMask[i] - (UseLoV1 ? 0 : SplitNumElements);
9848 if (UseLoV2 && UseHiV2) {
9850 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9852 // We only use half of V2 so map the usage down into the final blend mask.
9853 V2Blend = UseLoV2 ? LoV2 : HiV2;
9854 for (int i = 0; i < SplitNumElements; ++i)
9855 if (BlendMask[i] >= SplitNumElements)
9856 BlendMask[i] = V2BlendMask[i] + (UseLoV2 ? SplitNumElements : 0);
9858 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9860 SDValue Lo = HalfBlend(LoMask);
9861 SDValue Hi = HalfBlend(HiMask);
9862 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9865 /// \brief Either split a vector in halves or decompose the shuffles and the
9868 /// This is provided as a good fallback for many lowerings of non-single-input
9869 /// shuffles with more than one 128-bit lane. In those cases, we want to select
9870 /// between splitting the shuffle into 128-bit components and stitching those
9871 /// back together vs. extracting the single-input shuffles and blending those
9873 static SDValue lowerVectorShuffleAsSplitOrBlend(SDLoc DL, MVT VT, SDValue V1,
9874 SDValue V2, ArrayRef<int> Mask,
9875 SelectionDAG &DAG) {
9876 assert(!isSingleInputShuffleMask(Mask) && "This routine must not be used to "
9877 "lower single-input shuffles as it "
9878 "could then recurse on itself.");
9879 int Size = Mask.size();
9881 // If this can be modeled as a broadcast of two elements followed by a blend,
9882 // prefer that lowering. This is especially important because broadcasts can
9883 // often fold with memory operands.
9884 auto DoBothBroadcast = [&] {
9885 int V1BroadcastIdx = -1, V2BroadcastIdx = -1;
9888 if (V2BroadcastIdx == -1)
9889 V2BroadcastIdx = M - Size;
9890 else if (M - Size != V2BroadcastIdx)
9892 } else if (M >= 0) {
9893 if (V1BroadcastIdx == -1)
9895 else if (M != V1BroadcastIdx)
9900 if (DoBothBroadcast())
9901 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask,
9904 // If the inputs all stem from a single 128-bit lane of each input, then we
9905 // split them rather than blending because the split will decompose to
9906 // unusually few instructions.
9907 int LaneCount = VT.getSizeInBits() / 128;
9908 int LaneSize = Size / LaneCount;
9909 SmallBitVector LaneInputs[2];
9910 LaneInputs[0].resize(LaneCount, false);
9911 LaneInputs[1].resize(LaneCount, false);
9912 for (int i = 0; i < Size; ++i)
9914 LaneInputs[Mask[i] / Size][(Mask[i] % Size) / LaneSize] = true;
9915 if (LaneInputs[0].count() <= 1 && LaneInputs[1].count() <= 1)
9916 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9918 // Otherwise, just fall back to decomposed shuffles and a blend. This requires
9919 // that the decomposed single-input shuffles don't end up here.
9920 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9923 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
9924 /// a permutation and blend of those lanes.
9926 /// This essentially blends the out-of-lane inputs to each lane into the lane
9927 /// from a permuted copy of the vector. This lowering strategy results in four
9928 /// instructions in the worst case for a single-input cross lane shuffle which
9929 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
9930 /// of. Special cases for each particular shuffle pattern should be handled
9931 /// prior to trying this lowering.
9932 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
9933 SDValue V1, SDValue V2,
9935 SelectionDAG &DAG) {
9936 // FIXME: This should probably be generalized for 512-bit vectors as well.
9937 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
9938 int LaneSize = Mask.size() / 2;
9940 // If there are only inputs from one 128-bit lane, splitting will in fact be
9941 // less expensive. The flags track wether the given lane contains an element
9942 // that crosses to another lane.
9943 bool LaneCrossing[2] = {false, false};
9944 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9945 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
9946 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
9947 if (!LaneCrossing[0] || !LaneCrossing[1])
9948 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9950 if (isSingleInputShuffleMask(Mask)) {
9951 SmallVector<int, 32> FlippedBlendMask;
9952 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9953 FlippedBlendMask.push_back(
9954 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
9956 : Mask[i] % LaneSize +
9957 (i / LaneSize) * LaneSize + Size));
9959 // Flip the vector, and blend the results which should now be in-lane. The
9960 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
9961 // 5 for the high source. The value 3 selects the high half of source 2 and
9962 // the value 2 selects the low half of source 2. We only use source 2 to
9963 // allow folding it into a memory operand.
9964 unsigned PERMMask = 3 | 2 << 4;
9965 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
9966 V1, DAG.getConstant(PERMMask, MVT::i8));
9967 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
9970 // This now reduces to two single-input shuffles of V1 and V2 which at worst
9971 // will be handled by the above logic and a blend of the results, much like
9972 // other patterns in AVX.
9973 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9976 /// \brief Handle lowering 2-lane 128-bit shuffles.
9977 static SDValue lowerV2X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9978 SDValue V2, ArrayRef<int> Mask,
9979 const X86Subtarget *Subtarget,
9980 SelectionDAG &DAG) {
9981 // Blends are faster and handle all the non-lane-crossing cases.
9982 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, VT, V1, V2, Mask,
9986 MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(),
9987 VT.getVectorNumElements() / 2);
9988 // Check for patterns which can be matched with a single insert of a 128-bit
9990 if (isShuffleEquivalent(Mask, 0, 1, 0, 1) ||
9991 isShuffleEquivalent(Mask, 0, 1, 4, 5)) {
9992 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
9993 DAG.getIntPtrConstant(0));
9994 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
9995 Mask[2] < 4 ? V1 : V2, DAG.getIntPtrConstant(0));
9996 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
9998 if (isShuffleEquivalent(Mask, 0, 1, 6, 7)) {
9999 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
10000 DAG.getIntPtrConstant(0));
10001 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V2,
10002 DAG.getIntPtrConstant(2));
10003 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
10006 // Otherwise form a 128-bit permutation.
10007 // FIXME: Detect zero-vector inputs and use the VPERM2X128 to zero that half.
10008 unsigned PermMask = Mask[0] / 2 | (Mask[2] / 2) << 4;
10009 return DAG.getNode(X86ISD::VPERM2X128, DL, VT, V1, V2,
10010 DAG.getConstant(PermMask, MVT::i8));
10013 /// \brief Lower a vector shuffle by first fixing the 128-bit lanes and then
10014 /// shuffling each lane.
10016 /// This will only succeed when the result of fixing the 128-bit lanes results
10017 /// in a single-input non-lane-crossing shuffle with a repeating shuffle mask in
10018 /// each 128-bit lanes. This handles many cases where we can quickly blend away
10019 /// the lane crosses early and then use simpler shuffles within each lane.
10021 /// FIXME: It might be worthwhile at some point to support this without
10022 /// requiring the 128-bit lane-relative shuffles to be repeating, but currently
10023 /// in x86 only floating point has interesting non-repeating shuffles, and even
10024 /// those are still *marginally* more expensive.
10025 static SDValue lowerVectorShuffleByMerging128BitLanes(
10026 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
10027 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
10028 assert(!isSingleInputShuffleMask(Mask) &&
10029 "This is only useful with multiple inputs.");
10031 int Size = Mask.size();
10032 int LaneSize = 128 / VT.getScalarSizeInBits();
10033 int NumLanes = Size / LaneSize;
10034 assert(NumLanes > 1 && "Only handles 256-bit and wider shuffles.");
10036 // See if we can build a hypothetical 128-bit lane-fixing shuffle mask. Also
10037 // check whether the in-128-bit lane shuffles share a repeating pattern.
10038 SmallVector<int, 4> Lanes;
10039 Lanes.resize(NumLanes, -1);
10040 SmallVector<int, 4> InLaneMask;
10041 InLaneMask.resize(LaneSize, -1);
10042 for (int i = 0; i < Size; ++i) {
10046 int j = i / LaneSize;
10048 if (Lanes[j] < 0) {
10049 // First entry we've seen for this lane.
10050 Lanes[j] = Mask[i] / LaneSize;
10051 } else if (Lanes[j] != Mask[i] / LaneSize) {
10052 // This doesn't match the lane selected previously!
10056 // Check that within each lane we have a consistent shuffle mask.
10057 int k = i % LaneSize;
10058 if (InLaneMask[k] < 0) {
10059 InLaneMask[k] = Mask[i] % LaneSize;
10060 } else if (InLaneMask[k] != Mask[i] % LaneSize) {
10061 // This doesn't fit a repeating in-lane mask.
10066 // First shuffle the lanes into place.
10067 MVT LaneVT = MVT::getVectorVT(VT.isFloatingPoint() ? MVT::f64 : MVT::i64,
10068 VT.getSizeInBits() / 64);
10069 SmallVector<int, 8> LaneMask;
10070 LaneMask.resize(NumLanes * 2, -1);
10071 for (int i = 0; i < NumLanes; ++i)
10072 if (Lanes[i] >= 0) {
10073 LaneMask[2 * i + 0] = 2*Lanes[i] + 0;
10074 LaneMask[2 * i + 1] = 2*Lanes[i] + 1;
10077 V1 = DAG.getNode(ISD::BITCAST, DL, LaneVT, V1);
10078 V2 = DAG.getNode(ISD::BITCAST, DL, LaneVT, V2);
10079 SDValue LaneShuffle = DAG.getVectorShuffle(LaneVT, DL, V1, V2, LaneMask);
10081 // Cast it back to the type we actually want.
10082 LaneShuffle = DAG.getNode(ISD::BITCAST, DL, VT, LaneShuffle);
10084 // Now do a simple shuffle that isn't lane crossing.
10085 SmallVector<int, 8> NewMask;
10086 NewMask.resize(Size, -1);
10087 for (int i = 0; i < Size; ++i)
10089 NewMask[i] = (i / LaneSize) * LaneSize + Mask[i] % LaneSize;
10090 assert(!is128BitLaneCrossingShuffleMask(VT, NewMask) &&
10091 "Must not introduce lane crosses at this point!");
10093 return DAG.getVectorShuffle(VT, DL, LaneShuffle, DAG.getUNDEF(VT), NewMask);
10096 /// \brief Test whether the specified input (0 or 1) is in-place blended by the
10099 /// This returns true if the elements from a particular input are already in the
10100 /// slot required by the given mask and require no permutation.
10101 static bool isShuffleMaskInputInPlace(int Input, ArrayRef<int> Mask) {
10102 assert((Input == 0 || Input == 1) && "Only two inputs to shuffles.");
10103 int Size = Mask.size();
10104 for (int i = 0; i < Size; ++i)
10105 if (Mask[i] >= 0 && Mask[i] / Size == Input && Mask[i] % Size != i)
10111 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
10113 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
10114 /// isn't available.
10115 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10116 const X86Subtarget *Subtarget,
10117 SelectionDAG &DAG) {
10119 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10120 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10121 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10122 ArrayRef<int> Mask = SVOp->getMask();
10123 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10125 SmallVector<int, 4> WidenedMask;
10126 if (canWidenShuffleElements(Mask, WidenedMask))
10127 return lowerV2X128VectorShuffle(DL, MVT::v4f64, V1, V2, Mask, Subtarget,
10130 if (isSingleInputShuffleMask(Mask)) {
10131 // Check for being able to broadcast a single element.
10132 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4f64, DL, V1,
10133 Mask, Subtarget, DAG))
10136 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
10137 // Non-half-crossing single input shuffles can be lowerid with an
10138 // interleaved permutation.
10139 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
10140 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
10141 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
10142 DAG.getConstant(VPERMILPMask, MVT::i8));
10145 // With AVX2 we have direct support for this permutation.
10146 if (Subtarget->hasAVX2())
10147 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
10148 getV4X86ShuffleImm8ForMask(Mask, DAG));
10150 // Otherwise, fall back.
10151 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
10155 // X86 has dedicated unpack instructions that can handle specific blend
10156 // operations: UNPCKH and UNPCKL.
10157 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
10158 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
10159 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
10160 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
10162 // If we have a single input to the zero element, insert that into V1 if we
10163 // can do so cheaply.
10164 int NumV2Elements =
10165 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
10166 if (NumV2Elements == 1 && Mask[0] >= 4)
10167 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
10168 MVT::v4f64, DL, V1, V2, Mask, Subtarget, DAG))
10171 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
10175 // Check if the blend happens to exactly fit that of SHUFPD.
10176 if ((Mask[0] == -1 || Mask[0] < 2) &&
10177 (Mask[1] == -1 || (Mask[1] >= 4 && Mask[1] < 6)) &&
10178 (Mask[2] == -1 || (Mask[2] >= 2 && Mask[2] < 4)) &&
10179 (Mask[3] == -1 || Mask[3] >= 6)) {
10180 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 5) << 1) |
10181 ((Mask[2] == 3) << 2) | ((Mask[3] == 7) << 3);
10182 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V1, V2,
10183 DAG.getConstant(SHUFPDMask, MVT::i8));
10185 if ((Mask[0] == -1 || (Mask[0] >= 4 && Mask[0] < 6)) &&
10186 (Mask[1] == -1 || Mask[1] < 2) &&
10187 (Mask[2] == -1 || Mask[2] >= 6) &&
10188 (Mask[3] == -1 || (Mask[3] >= 2 && Mask[3] < 4))) {
10189 unsigned SHUFPDMask = (Mask[0] == 5) | ((Mask[1] == 1) << 1) |
10190 ((Mask[2] == 7) << 2) | ((Mask[3] == 3) << 3);
10191 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V2, V1,
10192 DAG.getConstant(SHUFPDMask, MVT::i8));
10195 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10196 // shuffle. However, if we have AVX2 and either inputs are already in place,
10197 // we will be able to shuffle even across lanes the other input in a single
10198 // instruction so skip this pattern.
10199 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10200 isShuffleMaskInputInPlace(1, Mask))))
10201 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10202 DL, MVT::v4f64, V1, V2, Mask, Subtarget, DAG))
10205 // If we have AVX2 then we always want to lower with a blend because an v4 we
10206 // can fully permute the elements.
10207 if (Subtarget->hasAVX2())
10208 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
10211 // Otherwise fall back on generic lowering.
10212 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v4f64, V1, V2, Mask, DAG);
10215 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
10217 /// This routine is only called when we have AVX2 and thus a reasonable
10218 /// instruction set for v4i64 shuffling..
10219 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10220 const X86Subtarget *Subtarget,
10221 SelectionDAG &DAG) {
10223 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10224 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10225 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10226 ArrayRef<int> Mask = SVOp->getMask();
10227 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10228 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
10230 SmallVector<int, 4> WidenedMask;
10231 if (canWidenShuffleElements(Mask, WidenedMask))
10232 return lowerV2X128VectorShuffle(DL, MVT::v4i64, V1, V2, Mask, Subtarget,
10235 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
10239 // Check for being able to broadcast a single element.
10240 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4i64, DL, V1,
10241 Mask, Subtarget, DAG))
10244 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
10245 // use lower latency instructions that will operate on both 128-bit lanes.
10246 SmallVector<int, 2> RepeatedMask;
10247 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
10248 if (isSingleInputShuffleMask(Mask)) {
10249 int PSHUFDMask[] = {-1, -1, -1, -1};
10250 for (int i = 0; i < 2; ++i)
10251 if (RepeatedMask[i] >= 0) {
10252 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
10253 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
10255 return DAG.getNode(
10256 ISD::BITCAST, DL, MVT::v4i64,
10257 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
10258 DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, V1),
10259 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
10262 // Use dedicated unpack instructions for masks that match their pattern.
10263 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
10264 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V1, V2);
10265 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
10266 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V1, V2);
10269 // AVX2 provides a direct instruction for permuting a single input across
10271 if (isSingleInputShuffleMask(Mask))
10272 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
10273 getV4X86ShuffleImm8ForMask(Mask, DAG));
10275 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10276 // shuffle. However, if we have AVX2 and either inputs are already in place,
10277 // we will be able to shuffle even across lanes the other input in a single
10278 // instruction so skip this pattern.
10279 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10280 isShuffleMaskInputInPlace(1, Mask))))
10281 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10282 DL, MVT::v4i64, V1, V2, Mask, Subtarget, DAG))
10285 // Otherwise fall back on generic blend lowering.
10286 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
10290 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
10292 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
10293 /// isn't available.
10294 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10295 const X86Subtarget *Subtarget,
10296 SelectionDAG &DAG) {
10298 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10299 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10300 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10301 ArrayRef<int> Mask = SVOp->getMask();
10302 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10304 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
10308 // Check for being able to broadcast a single element.
10309 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8f32, DL, V1,
10310 Mask, Subtarget, DAG))
10313 // If the shuffle mask is repeated in each 128-bit lane, we have many more
10314 // options to efficiently lower the shuffle.
10315 SmallVector<int, 4> RepeatedMask;
10316 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
10317 assert(RepeatedMask.size() == 4 &&
10318 "Repeated masks must be half the mask width!");
10319 if (isSingleInputShuffleMask(Mask))
10320 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
10321 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
10323 // Use dedicated unpack instructions for masks that match their pattern.
10324 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 4, 12, 5, 13))
10325 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V1, V2);
10326 if (isShuffleEquivalent(Mask, 2, 10, 3, 11, 6, 14, 7, 15))
10327 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V1, V2);
10329 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
10330 // have already handled any direct blends. We also need to squash the
10331 // repeated mask into a simulated v4f32 mask.
10332 for (int i = 0; i < 4; ++i)
10333 if (RepeatedMask[i] >= 8)
10334 RepeatedMask[i] -= 4;
10335 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
10338 // If we have a single input shuffle with different shuffle patterns in the
10339 // two 128-bit lanes use the variable mask to VPERMILPS.
10340 if (isSingleInputShuffleMask(Mask)) {
10341 SDValue VPermMask[8];
10342 for (int i = 0; i < 8; ++i)
10343 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10344 : DAG.getConstant(Mask[i], MVT::i32);
10345 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
10346 return DAG.getNode(
10347 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
10348 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
10350 if (Subtarget->hasAVX2())
10351 return DAG.getNode(X86ISD::VPERMV, DL, MVT::v8f32,
10352 DAG.getNode(ISD::BITCAST, DL, MVT::v8f32,
10353 DAG.getNode(ISD::BUILD_VECTOR, DL,
10354 MVT::v8i32, VPermMask)),
10357 // Otherwise, fall back.
10358 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
10362 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10364 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10365 DL, MVT::v8f32, V1, V2, Mask, Subtarget, DAG))
10368 // If we have AVX2 then we always want to lower with a blend because at v8 we
10369 // can fully permute the elements.
10370 if (Subtarget->hasAVX2())
10371 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
10374 // Otherwise fall back on generic lowering.
10375 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v8f32, V1, V2, Mask, DAG);
10378 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
10380 /// This routine is only called when we have AVX2 and thus a reasonable
10381 /// instruction set for v8i32 shuffling..
10382 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10383 const X86Subtarget *Subtarget,
10384 SelectionDAG &DAG) {
10386 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10387 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10388 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10389 ArrayRef<int> Mask = SVOp->getMask();
10390 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10391 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
10393 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
10397 // Check for being able to broadcast a single element.
10398 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8i32, DL, V1,
10399 Mask, Subtarget, DAG))
10402 // If the shuffle mask is repeated in each 128-bit lane we can use more
10403 // efficient instructions that mirror the shuffles across the two 128-bit
10405 SmallVector<int, 4> RepeatedMask;
10406 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
10407 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
10408 if (isSingleInputShuffleMask(Mask))
10409 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
10410 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
10412 // Use dedicated unpack instructions for masks that match their pattern.
10413 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 4, 12, 5, 13))
10414 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V1, V2);
10415 if (isShuffleEquivalent(Mask, 2, 10, 3, 11, 6, 14, 7, 15))
10416 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V1, V2);
10419 // If the shuffle patterns aren't repeated but it is a single input, directly
10420 // generate a cross-lane VPERMD instruction.
10421 if (isSingleInputShuffleMask(Mask)) {
10422 SDValue VPermMask[8];
10423 for (int i = 0; i < 8; ++i)
10424 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10425 : DAG.getConstant(Mask[i], MVT::i32);
10426 return DAG.getNode(
10427 X86ISD::VPERMV, DL, MVT::v8i32,
10428 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
10431 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10433 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10434 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10437 // Otherwise fall back on generic blend lowering.
10438 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
10442 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
10444 /// This routine is only called when we have AVX2 and thus a reasonable
10445 /// instruction set for v16i16 shuffling..
10446 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10447 const X86Subtarget *Subtarget,
10448 SelectionDAG &DAG) {
10450 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10451 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10452 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10453 ArrayRef<int> Mask = SVOp->getMask();
10454 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10455 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
10457 // Check for being able to broadcast a single element.
10458 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v16i16, DL, V1,
10459 Mask, Subtarget, DAG))
10462 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
10466 // Use dedicated unpack instructions for masks that match their pattern.
10467 if (isShuffleEquivalent(Mask,
10468 // First 128-bit lane:
10469 0, 16, 1, 17, 2, 18, 3, 19,
10470 // Second 128-bit lane:
10471 8, 24, 9, 25, 10, 26, 11, 27))
10472 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i16, V1, V2);
10473 if (isShuffleEquivalent(Mask,
10474 // First 128-bit lane:
10475 4, 20, 5, 21, 6, 22, 7, 23,
10476 // Second 128-bit lane:
10477 12, 28, 13, 29, 14, 30, 15, 31))
10478 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i16, V1, V2);
10480 if (isSingleInputShuffleMask(Mask)) {
10481 // There are no generalized cross-lane shuffle operations available on i16
10483 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
10484 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
10487 SDValue PSHUFBMask[32];
10488 for (int i = 0; i < 16; ++i) {
10489 if (Mask[i] == -1) {
10490 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
10494 int M = i < 8 ? Mask[i] : Mask[i] - 8;
10495 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
10496 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, MVT::i8);
10497 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, MVT::i8);
10499 return DAG.getNode(
10500 ISD::BITCAST, DL, MVT::v16i16,
10502 X86ISD::PSHUFB, DL, MVT::v32i8,
10503 DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1),
10504 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask)));
10507 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10509 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10510 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10513 // Otherwise fall back on generic lowering.
10514 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v16i16, V1, V2, Mask, DAG);
10517 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
10519 /// This routine is only called when we have AVX2 and thus a reasonable
10520 /// instruction set for v32i8 shuffling..
10521 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10522 const X86Subtarget *Subtarget,
10523 SelectionDAG &DAG) {
10525 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10526 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10527 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10528 ArrayRef<int> Mask = SVOp->getMask();
10529 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10530 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
10532 // Check for being able to broadcast a single element.
10533 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v32i8, DL, V1,
10534 Mask, Subtarget, DAG))
10537 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
10541 // Use dedicated unpack instructions for masks that match their pattern.
10542 // Note that these are repeated 128-bit lane unpacks, not unpacks across all
10544 if (isShuffleEquivalent(
10546 // First 128-bit lane:
10547 0, 32, 1, 33, 2, 34, 3, 35, 4, 36, 5, 37, 6, 38, 7, 39,
10548 // Second 128-bit lane:
10549 16, 48, 17, 49, 18, 50, 19, 51, 20, 52, 21, 53, 22, 54, 23, 55))
10550 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v32i8, V1, V2);
10551 if (isShuffleEquivalent(
10553 // First 128-bit lane:
10554 8, 40, 9, 41, 10, 42, 11, 43, 12, 44, 13, 45, 14, 46, 15, 47,
10555 // Second 128-bit lane:
10556 24, 56, 25, 57, 26, 58, 27, 59, 28, 60, 29, 61, 30, 62, 31, 63))
10557 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v32i8, V1, V2);
10559 if (isSingleInputShuffleMask(Mask)) {
10560 // There are no generalized cross-lane shuffle operations available on i8
10562 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
10563 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
10566 SDValue PSHUFBMask[32];
10567 for (int i = 0; i < 32; ++i)
10570 ? DAG.getUNDEF(MVT::i8)
10571 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, MVT::i8);
10573 return DAG.getNode(
10574 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
10575 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
10578 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10580 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10581 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10584 // Otherwise fall back on generic lowering.
10585 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v32i8, V1, V2, Mask, DAG);
10588 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
10590 /// This routine either breaks down the specific type of a 256-bit x86 vector
10591 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
10592 /// together based on the available instructions.
10593 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10594 MVT VT, const X86Subtarget *Subtarget,
10595 SelectionDAG &DAG) {
10597 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10598 ArrayRef<int> Mask = SVOp->getMask();
10600 // There is a really nice hard cut-over between AVX1 and AVX2 that means we can
10601 // check for those subtargets here and avoid much of the subtarget querying in
10602 // the per-vector-type lowering routines. With AVX1 we have essentially *zero*
10603 // ability to manipulate a 256-bit vector with integer types. Since we'll use
10604 // floating point types there eventually, just immediately cast everything to
10605 // a float and operate entirely in that domain.
10606 if (VT.isInteger() && !Subtarget->hasAVX2()) {
10607 int ElementBits = VT.getScalarSizeInBits();
10608 if (ElementBits < 32)
10609 // No floating point type available, decompose into 128-bit vectors.
10610 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10612 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
10613 VT.getVectorNumElements());
10614 V1 = DAG.getNode(ISD::BITCAST, DL, FpVT, V1);
10615 V2 = DAG.getNode(ISD::BITCAST, DL, FpVT, V2);
10616 return DAG.getNode(ISD::BITCAST, DL, VT,
10617 DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
10620 switch (VT.SimpleTy) {
10622 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10624 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10626 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10628 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10630 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10632 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10635 llvm_unreachable("Not a valid 256-bit x86 vector type!");
10639 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
10640 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10641 const X86Subtarget *Subtarget,
10642 SelectionDAG &DAG) {
10644 assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10645 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10646 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10647 ArrayRef<int> Mask = SVOp->getMask();
10648 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10650 // FIXME: Implement direct support for this type!
10651 return splitAndLowerVectorShuffle(DL, MVT::v8f64, V1, V2, Mask, DAG);
10654 /// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
10655 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10656 const X86Subtarget *Subtarget,
10657 SelectionDAG &DAG) {
10659 assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10660 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10661 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10662 ArrayRef<int> Mask = SVOp->getMask();
10663 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10665 // FIXME: Implement direct support for this type!
10666 return splitAndLowerVectorShuffle(DL, MVT::v16f32, V1, V2, Mask, DAG);
10669 /// \brief Handle lowering of 8-lane 64-bit integer shuffles.
10670 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10671 const X86Subtarget *Subtarget,
10672 SelectionDAG &DAG) {
10674 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10675 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10676 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10677 ArrayRef<int> Mask = SVOp->getMask();
10678 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10680 // FIXME: Implement direct support for this type!
10681 return splitAndLowerVectorShuffle(DL, MVT::v8i64, V1, V2, Mask, DAG);
10684 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
10685 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10686 const X86Subtarget *Subtarget,
10687 SelectionDAG &DAG) {
10689 assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10690 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10691 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10692 ArrayRef<int> Mask = SVOp->getMask();
10693 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10695 // FIXME: Implement direct support for this type!
10696 return splitAndLowerVectorShuffle(DL, MVT::v16i32, V1, V2, Mask, DAG);
10699 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
10700 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10701 const X86Subtarget *Subtarget,
10702 SelectionDAG &DAG) {
10704 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10705 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10706 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10707 ArrayRef<int> Mask = SVOp->getMask();
10708 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10709 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
10711 // FIXME: Implement direct support for this type!
10712 return splitAndLowerVectorShuffle(DL, MVT::v32i16, V1, V2, Mask, DAG);
10715 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
10716 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10717 const X86Subtarget *Subtarget,
10718 SelectionDAG &DAG) {
10720 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10721 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10722 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10723 ArrayRef<int> Mask = SVOp->getMask();
10724 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
10725 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
10727 // FIXME: Implement direct support for this type!
10728 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
10731 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
10733 /// This routine either breaks down the specific type of a 512-bit x86 vector
10734 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
10735 /// together based on the available instructions.
10736 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10737 MVT VT, const X86Subtarget *Subtarget,
10738 SelectionDAG &DAG) {
10740 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10741 ArrayRef<int> Mask = SVOp->getMask();
10742 assert(Subtarget->hasAVX512() &&
10743 "Cannot lower 512-bit vectors w/ basic ISA!");
10745 // Check for being able to broadcast a single element.
10746 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(VT.SimpleTy, DL, V1,
10747 Mask, Subtarget, DAG))
10750 // Dispatch to each element type for lowering. If we don't have supprot for
10751 // specific element type shuffles at 512 bits, immediately split them and
10752 // lower them. Each lowering routine of a given type is allowed to assume that
10753 // the requisite ISA extensions for that element type are available.
10754 switch (VT.SimpleTy) {
10756 return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10758 return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10760 return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10762 return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10764 if (Subtarget->hasBWI())
10765 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10768 if (Subtarget->hasBWI())
10769 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10773 llvm_unreachable("Not a valid 512-bit x86 vector type!");
10776 // Otherwise fall back on splitting.
10777 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10780 /// \brief Top-level lowering for x86 vector shuffles.
10782 /// This handles decomposition, canonicalization, and lowering of all x86
10783 /// vector shuffles. Most of the specific lowering strategies are encapsulated
10784 /// above in helper routines. The canonicalization attempts to widen shuffles
10785 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
10786 /// s.t. only one of the two inputs needs to be tested, etc.
10787 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
10788 SelectionDAG &DAG) {
10789 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10790 ArrayRef<int> Mask = SVOp->getMask();
10791 SDValue V1 = Op.getOperand(0);
10792 SDValue V2 = Op.getOperand(1);
10793 MVT VT = Op.getSimpleValueType();
10794 int NumElements = VT.getVectorNumElements();
10797 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
10799 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
10800 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10801 if (V1IsUndef && V2IsUndef)
10802 return DAG.getUNDEF(VT);
10804 // When we create a shuffle node we put the UNDEF node to second operand,
10805 // but in some cases the first operand may be transformed to UNDEF.
10806 // In this case we should just commute the node.
10808 return DAG.getCommutedVectorShuffle(*SVOp);
10810 // Check for non-undef masks pointing at an undef vector and make the masks
10811 // undef as well. This makes it easier to match the shuffle based solely on
10815 if (M >= NumElements) {
10816 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
10817 for (int &M : NewMask)
10818 if (M >= NumElements)
10820 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
10823 // Try to collapse shuffles into using a vector type with fewer elements but
10824 // wider element types. We cap this to not form integers or floating point
10825 // elements wider than 64 bits, but it might be interesting to form i128
10826 // integers to handle flipping the low and high halves of AVX 256-bit vectors.
10827 SmallVector<int, 16> WidenedMask;
10828 if (VT.getScalarSizeInBits() < 64 &&
10829 canWidenShuffleElements(Mask, WidenedMask)) {
10830 MVT NewEltVT = VT.isFloatingPoint()
10831 ? MVT::getFloatingPointVT(VT.getScalarSizeInBits() * 2)
10832 : MVT::getIntegerVT(VT.getScalarSizeInBits() * 2);
10833 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2);
10834 // Make sure that the new vector type is legal. For example, v2f64 isn't
10836 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) {
10837 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
10838 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
10839 return DAG.getNode(ISD::BITCAST, dl, VT,
10840 DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
10844 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
10845 for (int M : SVOp->getMask())
10847 ++NumUndefElements;
10848 else if (M < NumElements)
10853 // Commute the shuffle as needed such that more elements come from V1 than
10854 // V2. This allows us to match the shuffle pattern strictly on how many
10855 // elements come from V1 without handling the symmetric cases.
10856 if (NumV2Elements > NumV1Elements)
10857 return DAG.getCommutedVectorShuffle(*SVOp);
10859 // When the number of V1 and V2 elements are the same, try to minimize the
10860 // number of uses of V2 in the low half of the vector. When that is tied,
10861 // ensure that the sum of indices for V1 is equal to or lower than the sum
10862 // indices for V2. When those are equal, try to ensure that the number of odd
10863 // indices for V1 is lower than the number of odd indices for V2.
10864 if (NumV1Elements == NumV2Elements) {
10865 int LowV1Elements = 0, LowV2Elements = 0;
10866 for (int M : SVOp->getMask().slice(0, NumElements / 2))
10867 if (M >= NumElements)
10871 if (LowV2Elements > LowV1Elements) {
10872 return DAG.getCommutedVectorShuffle(*SVOp);
10873 } else if (LowV2Elements == LowV1Elements) {
10874 int SumV1Indices = 0, SumV2Indices = 0;
10875 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10876 if (SVOp->getMask()[i] >= NumElements)
10878 else if (SVOp->getMask()[i] >= 0)
10880 if (SumV2Indices < SumV1Indices) {
10881 return DAG.getCommutedVectorShuffle(*SVOp);
10882 } else if (SumV2Indices == SumV1Indices) {
10883 int NumV1OddIndices = 0, NumV2OddIndices = 0;
10884 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10885 if (SVOp->getMask()[i] >= NumElements)
10886 NumV2OddIndices += i % 2;
10887 else if (SVOp->getMask()[i] >= 0)
10888 NumV1OddIndices += i % 2;
10889 if (NumV2OddIndices < NumV1OddIndices)
10890 return DAG.getCommutedVectorShuffle(*SVOp);
10895 // For each vector width, delegate to a specialized lowering routine.
10896 if (VT.getSizeInBits() == 128)
10897 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10899 if (VT.getSizeInBits() == 256)
10900 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10902 // Force AVX-512 vectors to be scalarized for now.
10903 // FIXME: Implement AVX-512 support!
10904 if (VT.getSizeInBits() == 512)
10905 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10907 llvm_unreachable("Unimplemented!");
10911 //===----------------------------------------------------------------------===//
10912 // Legacy vector shuffle lowering
10914 // This code is the legacy code handling vector shuffles until the above
10915 // replaces its functionality and performance.
10916 //===----------------------------------------------------------------------===//
10918 static bool isBlendMask(ArrayRef<int> MaskVals, MVT VT, bool hasSSE41,
10919 bool hasInt256, unsigned *MaskOut = nullptr) {
10920 MVT EltVT = VT.getVectorElementType();
10922 // There is no blend with immediate in AVX-512.
10923 if (VT.is512BitVector())
10926 if (!hasSSE41 || EltVT == MVT::i8)
10928 if (!hasInt256 && VT == MVT::v16i16)
10931 unsigned MaskValue = 0;
10932 unsigned NumElems = VT.getVectorNumElements();
10933 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
10934 unsigned NumLanes = (NumElems - 1) / 8 + 1;
10935 unsigned NumElemsInLane = NumElems / NumLanes;
10937 // Blend for v16i16 should be symetric for the both lanes.
10938 for (unsigned i = 0; i < NumElemsInLane; ++i) {
10940 int SndLaneEltIdx = (NumLanes == 2) ? MaskVals[i + NumElemsInLane] : -1;
10941 int EltIdx = MaskVals[i];
10943 if ((EltIdx < 0 || EltIdx == (int)i) &&
10944 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
10947 if (((unsigned)EltIdx == (i + NumElems)) &&
10948 (SndLaneEltIdx < 0 ||
10949 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
10950 MaskValue |= (1 << i);
10956 *MaskOut = MaskValue;
10960 // Try to lower a shuffle node into a simple blend instruction.
10961 // This function assumes isBlendMask returns true for this
10962 // SuffleVectorSDNode
10963 static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
10964 unsigned MaskValue,
10965 const X86Subtarget *Subtarget,
10966 SelectionDAG &DAG) {
10967 MVT VT = SVOp->getSimpleValueType(0);
10968 MVT EltVT = VT.getVectorElementType();
10969 assert(isBlendMask(SVOp->getMask(), VT, Subtarget->hasSSE41(),
10970 Subtarget->hasInt256() && "Trying to lower a "
10971 "VECTOR_SHUFFLE to a Blend but "
10972 "with the wrong mask"));
10973 SDValue V1 = SVOp->getOperand(0);
10974 SDValue V2 = SVOp->getOperand(1);
10976 unsigned NumElems = VT.getVectorNumElements();
10978 // Convert i32 vectors to floating point if it is not AVX2.
10979 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
10981 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
10982 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
10984 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
10985 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
10988 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
10989 DAG.getConstant(MaskValue, MVT::i32));
10990 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
10993 /// In vector type \p VT, return true if the element at index \p InputIdx
10994 /// falls on a different 128-bit lane than \p OutputIdx.
10995 static bool ShuffleCrosses128bitLane(MVT VT, unsigned InputIdx,
10996 unsigned OutputIdx) {
10997 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
10998 return InputIdx * EltSize / 128 != OutputIdx * EltSize / 128;
11001 /// Generate a PSHUFB if possible. Selects elements from \p V1 according to
11002 /// \p MaskVals. MaskVals[OutputIdx] = InputIdx specifies that we want to
11003 /// shuffle the element at InputIdx in V1 to OutputIdx in the result. If \p
11004 /// MaskVals refers to elements outside of \p V1 or is undef (-1), insert a
11006 static SDValue getPSHUFB(ArrayRef<int> MaskVals, SDValue V1, SDLoc &dl,
11007 SelectionDAG &DAG) {
11008 MVT VT = V1.getSimpleValueType();
11009 assert(VT.is128BitVector() || VT.is256BitVector());
11011 MVT EltVT = VT.getVectorElementType();
11012 unsigned EltSizeInBytes = EltVT.getSizeInBits() / 8;
11013 unsigned NumElts = VT.getVectorNumElements();
11015 SmallVector<SDValue, 32> PshufbMask;
11016 for (unsigned OutputIdx = 0; OutputIdx < NumElts; ++OutputIdx) {
11017 int InputIdx = MaskVals[OutputIdx];
11018 unsigned InputByteIdx;
11020 if (InputIdx < 0 || NumElts <= (unsigned)InputIdx)
11021 InputByteIdx = 0x80;
11023 // Cross lane is not allowed.
11024 if (ShuffleCrosses128bitLane(VT, InputIdx, OutputIdx))
11026 InputByteIdx = InputIdx * EltSizeInBytes;
11027 // Index is an byte offset within the 128-bit lane.
11028 InputByteIdx &= 0xf;
11031 for (unsigned j = 0; j < EltSizeInBytes; ++j) {
11032 PshufbMask.push_back(DAG.getConstant(InputByteIdx, MVT::i8));
11033 if (InputByteIdx != 0x80)
11038 MVT ShufVT = MVT::getVectorVT(MVT::i8, PshufbMask.size());
11040 V1 = DAG.getNode(ISD::BITCAST, dl, ShufVT, V1);
11041 return DAG.getNode(X86ISD::PSHUFB, dl, ShufVT, V1,
11042 DAG.getNode(ISD::BUILD_VECTOR, dl, ShufVT, PshufbMask));
11045 // v8i16 shuffles - Prefer shuffles in the following order:
11046 // 1. [all] pshuflw, pshufhw, optional move
11047 // 2. [ssse3] 1 x pshufb
11048 // 3. [ssse3] 2 x pshufb + 1 x por
11049 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
11051 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
11052 SelectionDAG &DAG) {
11053 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11054 SDValue V1 = SVOp->getOperand(0);
11055 SDValue V2 = SVOp->getOperand(1);
11057 SmallVector<int, 8> MaskVals;
11059 // Determine if more than 1 of the words in each of the low and high quadwords
11060 // of the result come from the same quadword of one of the two inputs. Undef
11061 // mask values count as coming from any quadword, for better codegen.
11063 // Lo/HiQuad[i] = j indicates how many words from the ith quad of the input
11064 // feeds this quad. For i, 0 and 1 refer to V1, 2 and 3 refer to V2.
11065 unsigned LoQuad[] = { 0, 0, 0, 0 };
11066 unsigned HiQuad[] = { 0, 0, 0, 0 };
11067 // Indices of quads used.
11068 std::bitset<4> InputQuads;
11069 for (unsigned i = 0; i < 8; ++i) {
11070 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
11071 int EltIdx = SVOp->getMaskElt(i);
11072 MaskVals.push_back(EltIdx);
11080 ++Quad[EltIdx / 4];
11081 InputQuads.set(EltIdx / 4);
11084 int BestLoQuad = -1;
11085 unsigned MaxQuad = 1;
11086 for (unsigned i = 0; i < 4; ++i) {
11087 if (LoQuad[i] > MaxQuad) {
11089 MaxQuad = LoQuad[i];
11093 int BestHiQuad = -1;
11095 for (unsigned i = 0; i < 4; ++i) {
11096 if (HiQuad[i] > MaxQuad) {
11098 MaxQuad = HiQuad[i];
11102 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
11103 // of the two input vectors, shuffle them into one input vector so only a
11104 // single pshufb instruction is necessary. If there are more than 2 input
11105 // quads, disable the next transformation since it does not help SSSE3.
11106 bool V1Used = InputQuads[0] || InputQuads[1];
11107 bool V2Used = InputQuads[2] || InputQuads[3];
11108 if (Subtarget->hasSSSE3()) {
11109 if (InputQuads.count() == 2 && V1Used && V2Used) {
11110 BestLoQuad = InputQuads[0] ? 0 : 1;
11111 BestHiQuad = InputQuads[2] ? 2 : 3;
11113 if (InputQuads.count() > 2) {
11119 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
11120 // the shuffle mask. If a quad is scored as -1, that means that it contains
11121 // words from all 4 input quadwords.
11123 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
11125 BestLoQuad < 0 ? 0 : BestLoQuad,
11126 BestHiQuad < 0 ? 1 : BestHiQuad
11128 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
11129 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
11130 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
11131 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
11133 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
11134 // source words for the shuffle, to aid later transformations.
11135 bool AllWordsInNewV = true;
11136 bool InOrder[2] = { true, true };
11137 for (unsigned i = 0; i != 8; ++i) {
11138 int idx = MaskVals[i];
11140 InOrder[i/4] = false;
11141 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
11143 AllWordsInNewV = false;
11147 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
11148 if (AllWordsInNewV) {
11149 for (int i = 0; i != 8; ++i) {
11150 int idx = MaskVals[i];
11153 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
11154 if ((idx != i) && idx < 4)
11156 if ((idx != i) && idx > 3)
11165 // If we've eliminated the use of V2, and the new mask is a pshuflw or
11166 // pshufhw, that's as cheap as it gets. Return the new shuffle.
11167 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
11168 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
11169 unsigned TargetMask = 0;
11170 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
11171 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
11172 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
11173 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
11174 getShufflePSHUFLWImmediate(SVOp);
11175 V1 = NewV.getOperand(0);
11176 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
11180 // Promote splats to a larger type which usually leads to more efficient code.
11181 // FIXME: Is this true if pshufb is available?
11182 if (SVOp->isSplat())
11183 return PromoteSplat(SVOp, DAG);
11185 // If we have SSSE3, and all words of the result are from 1 input vector,
11186 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
11187 // is present, fall back to case 4.
11188 if (Subtarget->hasSSSE3()) {
11189 SmallVector<SDValue,16> pshufbMask;
11191 // If we have elements from both input vectors, set the high bit of the
11192 // shuffle mask element to zero out elements that come from V2 in the V1
11193 // mask, and elements that come from V1 in the V2 mask, so that the two
11194 // results can be OR'd together.
11195 bool TwoInputs = V1Used && V2Used;
11196 V1 = getPSHUFB(MaskVals, V1, dl, DAG);
11198 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
11200 // Calculate the shuffle mask for the second input, shuffle it, and
11201 // OR it with the first shuffled input.
11202 CommuteVectorShuffleMask(MaskVals, 8);
11203 V2 = getPSHUFB(MaskVals, V2, dl, DAG);
11204 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
11205 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
11208 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
11209 // and update MaskVals with new element order.
11210 std::bitset<8> InOrder;
11211 if (BestLoQuad >= 0) {
11212 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
11213 for (int i = 0; i != 4; ++i) {
11214 int idx = MaskVals[i];
11217 } else if ((idx / 4) == BestLoQuad) {
11218 MaskV[i] = idx & 3;
11222 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
11225 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
11226 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
11227 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
11228 NewV.getOperand(0),
11229 getShufflePSHUFLWImmediate(SVOp), DAG);
11233 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
11234 // and update MaskVals with the new element order.
11235 if (BestHiQuad >= 0) {
11236 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
11237 for (unsigned i = 4; i != 8; ++i) {
11238 int idx = MaskVals[i];
11241 } else if ((idx / 4) == BestHiQuad) {
11242 MaskV[i] = (idx & 3) + 4;
11246 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
11249 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
11250 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
11251 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
11252 NewV.getOperand(0),
11253 getShufflePSHUFHWImmediate(SVOp), DAG);
11257 // In case BestHi & BestLo were both -1, which means each quadword has a word
11258 // from each of the four input quadwords, calculate the InOrder bitvector now
11259 // before falling through to the insert/extract cleanup.
11260 if (BestLoQuad == -1 && BestHiQuad == -1) {
11262 for (int i = 0; i != 8; ++i)
11263 if (MaskVals[i] < 0 || MaskVals[i] == i)
11267 // The other elements are put in the right place using pextrw and pinsrw.
11268 for (unsigned i = 0; i != 8; ++i) {
11271 int EltIdx = MaskVals[i];
11274 SDValue ExtOp = (EltIdx < 8) ?
11275 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
11276 DAG.getIntPtrConstant(EltIdx)) :
11277 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
11278 DAG.getIntPtrConstant(EltIdx - 8));
11279 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
11280 DAG.getIntPtrConstant(i));
11285 /// \brief v16i16 shuffles
11287 /// FIXME: We only support generation of a single pshufb currently. We can
11288 /// generalize the other applicable cases from LowerVECTOR_SHUFFLEv8i16 as
11289 /// well (e.g 2 x pshufb + 1 x por).
11291 LowerVECTOR_SHUFFLEv16i16(SDValue Op, SelectionDAG &DAG) {
11292 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11293 SDValue V1 = SVOp->getOperand(0);
11294 SDValue V2 = SVOp->getOperand(1);
11297 if (V2.getOpcode() != ISD::UNDEF)
11300 SmallVector<int, 16> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
11301 return getPSHUFB(MaskVals, V1, dl, DAG);
11304 // v16i8 shuffles - Prefer shuffles in the following order:
11305 // 1. [ssse3] 1 x pshufb
11306 // 2. [ssse3] 2 x pshufb + 1 x por
11307 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
11308 static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
11309 const X86Subtarget* Subtarget,
11310 SelectionDAG &DAG) {
11311 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11312 SDValue V1 = SVOp->getOperand(0);
11313 SDValue V2 = SVOp->getOperand(1);
11315 ArrayRef<int> MaskVals = SVOp->getMask();
11317 // Promote splats to a larger type which usually leads to more efficient code.
11318 // FIXME: Is this true if pshufb is available?
11319 if (SVOp->isSplat())
11320 return PromoteSplat(SVOp, DAG);
11322 // If we have SSSE3, case 1 is generated when all result bytes come from
11323 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
11324 // present, fall back to case 3.
11326 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
11327 if (Subtarget->hasSSSE3()) {
11328 SmallVector<SDValue,16> pshufbMask;
11330 // If all result elements are from one input vector, then only translate
11331 // undef mask values to 0x80 (zero out result) in the pshufb mask.
11333 // Otherwise, we have elements from both input vectors, and must zero out
11334 // elements that come from V2 in the first mask, and V1 in the second mask
11335 // so that we can OR them together.
11336 for (unsigned i = 0; i != 16; ++i) {
11337 int EltIdx = MaskVals[i];
11338 if (EltIdx < 0 || EltIdx >= 16)
11340 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
11342 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
11343 DAG.getNode(ISD::BUILD_VECTOR, dl,
11344 MVT::v16i8, pshufbMask));
11346 // As PSHUFB will zero elements with negative indices, it's safe to ignore
11347 // the 2nd operand if it's undefined or zero.
11348 if (V2.getOpcode() == ISD::UNDEF ||
11349 ISD::isBuildVectorAllZeros(V2.getNode()))
11352 // Calculate the shuffle mask for the second input, shuffle it, and
11353 // OR it with the first shuffled input.
11354 pshufbMask.clear();
11355 for (unsigned i = 0; i != 16; ++i) {
11356 int EltIdx = MaskVals[i];
11357 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
11358 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
11360 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
11361 DAG.getNode(ISD::BUILD_VECTOR, dl,
11362 MVT::v16i8, pshufbMask));
11363 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
11366 // No SSSE3 - Calculate in place words and then fix all out of place words
11367 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
11368 // the 16 different words that comprise the two doublequadword input vectors.
11369 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
11370 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
11372 for (int i = 0; i != 8; ++i) {
11373 int Elt0 = MaskVals[i*2];
11374 int Elt1 = MaskVals[i*2+1];
11376 // This word of the result is all undef, skip it.
11377 if (Elt0 < 0 && Elt1 < 0)
11380 // This word of the result is already in the correct place, skip it.
11381 if ((Elt0 == i*2) && (Elt1 == i*2+1))
11384 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
11385 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
11388 // If Elt0 and Elt1 are defined, are consecutive, and can be load
11389 // using a single extract together, load it and store it.
11390 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
11391 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
11392 DAG.getIntPtrConstant(Elt1 / 2));
11393 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
11394 DAG.getIntPtrConstant(i));
11398 // If Elt1 is defined, extract it from the appropriate source. If the
11399 // source byte is not also odd, shift the extracted word left 8 bits
11400 // otherwise clear the bottom 8 bits if we need to do an or.
11402 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
11403 DAG.getIntPtrConstant(Elt1 / 2));
11404 if ((Elt1 & 1) == 0)
11405 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
11407 TLI.getShiftAmountTy(InsElt.getValueType())));
11408 else if (Elt0 >= 0)
11409 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
11410 DAG.getConstant(0xFF00, MVT::i16));
11412 // If Elt0 is defined, extract it from the appropriate source. If the
11413 // source byte is not also even, shift the extracted word right 8 bits. If
11414 // Elt1 was also defined, OR the extracted values together before
11415 // inserting them in the result.
11417 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
11418 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
11419 if ((Elt0 & 1) != 0)
11420 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
11422 TLI.getShiftAmountTy(InsElt0.getValueType())));
11423 else if (Elt1 >= 0)
11424 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
11425 DAG.getConstant(0x00FF, MVT::i16));
11426 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
11429 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
11430 DAG.getIntPtrConstant(i));
11432 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
11435 // v32i8 shuffles - Translate to VPSHUFB if possible.
11437 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
11438 const X86Subtarget *Subtarget,
11439 SelectionDAG &DAG) {
11440 MVT VT = SVOp->getSimpleValueType(0);
11441 SDValue V1 = SVOp->getOperand(0);
11442 SDValue V2 = SVOp->getOperand(1);
11444 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
11446 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
11447 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
11448 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
11450 // VPSHUFB may be generated if
11451 // (1) one of input vector is undefined or zeroinitializer.
11452 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
11453 // And (2) the mask indexes don't cross the 128-bit lane.
11454 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
11455 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
11458 if (V1IsAllZero && !V2IsAllZero) {
11459 CommuteVectorShuffleMask(MaskVals, 32);
11462 return getPSHUFB(MaskVals, V1, dl, DAG);
11465 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
11466 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
11467 /// done when every pair / quad of shuffle mask elements point to elements in
11468 /// the right sequence. e.g.
11469 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
11471 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
11472 SelectionDAG &DAG) {
11473 MVT VT = SVOp->getSimpleValueType(0);
11475 unsigned NumElems = VT.getVectorNumElements();
11478 switch (VT.SimpleTy) {
11479 default: llvm_unreachable("Unexpected!");
11482 return SDValue(SVOp, 0);
11483 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
11484 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
11485 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
11486 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
11487 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
11488 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
11491 SmallVector<int, 8> MaskVec;
11492 for (unsigned i = 0; i != NumElems; i += Scale) {
11494 for (unsigned j = 0; j != Scale; ++j) {
11495 int EltIdx = SVOp->getMaskElt(i+j);
11499 StartIdx = (EltIdx / Scale);
11500 if (EltIdx != (int)(StartIdx*Scale + j))
11503 MaskVec.push_back(StartIdx);
11506 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
11507 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
11508 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
11511 /// getVZextMovL - Return a zero-extending vector move low node.
11513 static SDValue getVZextMovL(MVT VT, MVT OpVT,
11514 SDValue SrcOp, SelectionDAG &DAG,
11515 const X86Subtarget *Subtarget, SDLoc dl) {
11516 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
11517 LoadSDNode *LD = nullptr;
11518 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
11519 LD = dyn_cast<LoadSDNode>(SrcOp);
11521 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
11523 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
11524 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
11525 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
11526 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
11527 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
11529 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
11530 return DAG.getNode(ISD::BITCAST, dl, VT,
11531 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
11532 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
11534 SrcOp.getOperand(0)
11540 return DAG.getNode(ISD::BITCAST, dl, VT,
11541 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
11542 DAG.getNode(ISD::BITCAST, dl,
11546 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
11547 /// which could not be matched by any known target speficic shuffle
11549 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
11551 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
11552 if (NewOp.getNode())
11555 MVT VT = SVOp->getSimpleValueType(0);
11557 unsigned NumElems = VT.getVectorNumElements();
11558 unsigned NumLaneElems = NumElems / 2;
11561 MVT EltVT = VT.getVectorElementType();
11562 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
11565 SmallVector<int, 16> Mask;
11566 for (unsigned l = 0; l < 2; ++l) {
11567 // Build a shuffle mask for the output, discovering on the fly which
11568 // input vectors to use as shuffle operands (recorded in InputUsed).
11569 // If building a suitable shuffle vector proves too hard, then bail
11570 // out with UseBuildVector set.
11571 bool UseBuildVector = false;
11572 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
11573 unsigned LaneStart = l * NumLaneElems;
11574 for (unsigned i = 0; i != NumLaneElems; ++i) {
11575 // The mask element. This indexes into the input.
11576 int Idx = SVOp->getMaskElt(i+LaneStart);
11578 // the mask element does not index into any input vector.
11579 Mask.push_back(-1);
11583 // The input vector this mask element indexes into.
11584 int Input = Idx / NumLaneElems;
11586 // Turn the index into an offset from the start of the input vector.
11587 Idx -= Input * NumLaneElems;
11589 // Find or create a shuffle vector operand to hold this input.
11591 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
11592 if (InputUsed[OpNo] == Input)
11593 // This input vector is already an operand.
11595 if (InputUsed[OpNo] < 0) {
11596 // Create a new operand for this input vector.
11597 InputUsed[OpNo] = Input;
11602 if (OpNo >= array_lengthof(InputUsed)) {
11603 // More than two input vectors used! Give up on trying to create a
11604 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
11605 UseBuildVector = true;
11609 // Add the mask index for the new shuffle vector.
11610 Mask.push_back(Idx + OpNo * NumLaneElems);
11613 if (UseBuildVector) {
11614 SmallVector<SDValue, 16> SVOps;
11615 for (unsigned i = 0; i != NumLaneElems; ++i) {
11616 // The mask element. This indexes into the input.
11617 int Idx = SVOp->getMaskElt(i+LaneStart);
11619 SVOps.push_back(DAG.getUNDEF(EltVT));
11623 // The input vector this mask element indexes into.
11624 int Input = Idx / NumElems;
11626 // Turn the index into an offset from the start of the input vector.
11627 Idx -= Input * NumElems;
11629 // Extract the vector element by hand.
11630 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
11631 SVOp->getOperand(Input),
11632 DAG.getIntPtrConstant(Idx)));
11635 // Construct the output using a BUILD_VECTOR.
11636 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, SVOps);
11637 } else if (InputUsed[0] < 0) {
11638 // No input vectors were used! The result is undefined.
11639 Output[l] = DAG.getUNDEF(NVT);
11641 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
11642 (InputUsed[0] % 2) * NumLaneElems,
11644 // If only one input was used, use an undefined vector for the other.
11645 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
11646 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
11647 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
11648 // At least one input vector was used. Create a new shuffle vector.
11649 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
11655 // Concatenate the result back
11656 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
11659 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
11660 /// 4 elements, and match them with several different shuffle types.
11662 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
11663 SDValue V1 = SVOp->getOperand(0);
11664 SDValue V2 = SVOp->getOperand(1);
11666 MVT VT = SVOp->getSimpleValueType(0);
11668 assert(VT.is128BitVector() && "Unsupported vector size");
11670 std::pair<int, int> Locs[4];
11671 int Mask1[] = { -1, -1, -1, -1 };
11672 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
11674 unsigned NumHi = 0;
11675 unsigned NumLo = 0;
11676 for (unsigned i = 0; i != 4; ++i) {
11677 int Idx = PermMask[i];
11679 Locs[i] = std::make_pair(-1, -1);
11681 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
11683 Locs[i] = std::make_pair(0, NumLo);
11684 Mask1[NumLo] = Idx;
11687 Locs[i] = std::make_pair(1, NumHi);
11689 Mask1[2+NumHi] = Idx;
11695 if (NumLo <= 2 && NumHi <= 2) {
11696 // If no more than two elements come from either vector. This can be
11697 // implemented with two shuffles. First shuffle gather the elements.
11698 // The second shuffle, which takes the first shuffle as both of its
11699 // vector operands, put the elements into the right order.
11700 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11702 int Mask2[] = { -1, -1, -1, -1 };
11704 for (unsigned i = 0; i != 4; ++i)
11705 if (Locs[i].first != -1) {
11706 unsigned Idx = (i < 2) ? 0 : 4;
11707 Idx += Locs[i].first * 2 + Locs[i].second;
11711 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
11714 if (NumLo == 3 || NumHi == 3) {
11715 // Otherwise, we must have three elements from one vector, call it X, and
11716 // one element from the other, call it Y. First, use a shufps to build an
11717 // intermediate vector with the one element from Y and the element from X
11718 // that will be in the same half in the final destination (the indexes don't
11719 // matter). Then, use a shufps to build the final vector, taking the half
11720 // containing the element from Y from the intermediate, and the other half
11723 // Normalize it so the 3 elements come from V1.
11724 CommuteVectorShuffleMask(PermMask, 4);
11728 // Find the element from V2.
11730 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
11731 int Val = PermMask[HiIndex];
11738 Mask1[0] = PermMask[HiIndex];
11740 Mask1[2] = PermMask[HiIndex^1];
11742 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11744 if (HiIndex >= 2) {
11745 Mask1[0] = PermMask[0];
11746 Mask1[1] = PermMask[1];
11747 Mask1[2] = HiIndex & 1 ? 6 : 4;
11748 Mask1[3] = HiIndex & 1 ? 4 : 6;
11749 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11752 Mask1[0] = HiIndex & 1 ? 2 : 0;
11753 Mask1[1] = HiIndex & 1 ? 0 : 2;
11754 Mask1[2] = PermMask[2];
11755 Mask1[3] = PermMask[3];
11760 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
11763 // Break it into (shuffle shuffle_hi, shuffle_lo).
11764 int LoMask[] = { -1, -1, -1, -1 };
11765 int HiMask[] = { -1, -1, -1, -1 };
11767 int *MaskPtr = LoMask;
11768 unsigned MaskIdx = 0;
11769 unsigned LoIdx = 0;
11770 unsigned HiIdx = 2;
11771 for (unsigned i = 0; i != 4; ++i) {
11778 int Idx = PermMask[i];
11780 Locs[i] = std::make_pair(-1, -1);
11781 } else if (Idx < 4) {
11782 Locs[i] = std::make_pair(MaskIdx, LoIdx);
11783 MaskPtr[LoIdx] = Idx;
11786 Locs[i] = std::make_pair(MaskIdx, HiIdx);
11787 MaskPtr[HiIdx] = Idx;
11792 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
11793 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
11794 int MaskOps[] = { -1, -1, -1, -1 };
11795 for (unsigned i = 0; i != 4; ++i)
11796 if (Locs[i].first != -1)
11797 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
11798 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
11801 static bool MayFoldVectorLoad(SDValue V) {
11802 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
11803 V = V.getOperand(0);
11805 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
11806 V = V.getOperand(0);
11807 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
11808 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
11809 // BUILD_VECTOR (load), undef
11810 V = V.getOperand(0);
11812 return MayFoldLoad(V);
11816 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
11817 MVT VT = Op.getSimpleValueType();
11819 // Canonizalize to v2f64.
11820 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
11821 return DAG.getNode(ISD::BITCAST, dl, VT,
11822 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
11827 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
11829 SDValue V1 = Op.getOperand(0);
11830 SDValue V2 = Op.getOperand(1);
11831 MVT VT = Op.getSimpleValueType();
11833 assert(VT != MVT::v2i64 && "unsupported shuffle type");
11835 if (HasSSE2 && VT == MVT::v2f64)
11836 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
11838 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
11839 return DAG.getNode(ISD::BITCAST, dl, VT,
11840 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
11841 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
11842 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
11846 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
11847 SDValue V1 = Op.getOperand(0);
11848 SDValue V2 = Op.getOperand(1);
11849 MVT VT = Op.getSimpleValueType();
11851 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
11852 "unsupported shuffle type");
11854 if (V2.getOpcode() == ISD::UNDEF)
11858 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
11862 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
11863 SDValue V1 = Op.getOperand(0);
11864 SDValue V2 = Op.getOperand(1);
11865 MVT VT = Op.getSimpleValueType();
11866 unsigned NumElems = VT.getVectorNumElements();
11868 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
11869 // operand of these instructions is only memory, so check if there's a
11870 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
11872 bool CanFoldLoad = false;
11874 // Trivial case, when V2 comes from a load.
11875 if (MayFoldVectorLoad(V2))
11876 CanFoldLoad = true;
11878 // When V1 is a load, it can be folded later into a store in isel, example:
11879 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
11881 // (MOVLPSmr addr:$src1, VR128:$src2)
11882 // So, recognize this potential and also use MOVLPS or MOVLPD
11883 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
11884 CanFoldLoad = true;
11886 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11888 if (HasSSE2 && NumElems == 2)
11889 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
11892 // If we don't care about the second element, proceed to use movss.
11893 if (SVOp->getMaskElt(1) != -1)
11894 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
11897 // movl and movlp will both match v2i64, but v2i64 is never matched by
11898 // movl earlier because we make it strict to avoid messing with the movlp load
11899 // folding logic (see the code above getMOVLP call). Match it here then,
11900 // this is horrible, but will stay like this until we move all shuffle
11901 // matching to x86 specific nodes. Note that for the 1st condition all
11902 // types are matched with movsd.
11904 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
11905 // as to remove this logic from here, as much as possible
11906 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
11907 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
11908 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
11911 assert(VT != MVT::v4i32 && "unsupported shuffle type");
11913 // Invert the operand order and use SHUFPS to match it.
11914 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
11915 getShuffleSHUFImmediate(SVOp), DAG);
11918 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
11919 SelectionDAG &DAG) {
11921 MVT VT = Load->getSimpleValueType(0);
11922 MVT EVT = VT.getVectorElementType();
11923 SDValue Addr = Load->getOperand(1);
11924 SDValue NewAddr = DAG.getNode(
11925 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
11926 DAG.getConstant(Index * EVT.getStoreSize(), Addr.getSimpleValueType()));
11929 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
11930 DAG.getMachineFunction().getMachineMemOperand(
11931 Load->getMemOperand(), 0, EVT.getStoreSize()));
11935 // It is only safe to call this function if isINSERTPSMask is true for
11936 // this shufflevector mask.
11937 static SDValue getINSERTPS(ShuffleVectorSDNode *SVOp, SDLoc &dl,
11938 SelectionDAG &DAG) {
11939 // Generate an insertps instruction when inserting an f32 from memory onto a
11940 // v4f32 or when copying a member from one v4f32 to another.
11941 // We also use it for transferring i32 from one register to another,
11942 // since it simply copies the same bits.
11943 // If we're transferring an i32 from memory to a specific element in a
11944 // register, we output a generic DAG that will match the PINSRD
11946 MVT VT = SVOp->getSimpleValueType(0);
11947 MVT EVT = VT.getVectorElementType();
11948 SDValue V1 = SVOp->getOperand(0);
11949 SDValue V2 = SVOp->getOperand(1);
11950 auto Mask = SVOp->getMask();
11951 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
11952 "unsupported vector type for insertps/pinsrd");
11954 auto FromV1Predicate = [](const int &i) { return i < 4 && i > -1; };
11955 auto FromV2Predicate = [](const int &i) { return i >= 4; };
11956 int FromV1 = std::count_if(Mask.begin(), Mask.end(), FromV1Predicate);
11960 unsigned DestIndex;
11964 DestIndex = std::find_if(Mask.begin(), Mask.end(), FromV1Predicate) -
11967 // If we have 1 element from each vector, we have to check if we're
11968 // changing V1's element's place. If so, we're done. Otherwise, we
11969 // should assume we're changing V2's element's place and behave
11971 int FromV2 = std::count_if(Mask.begin(), Mask.end(), FromV2Predicate);
11972 assert(DestIndex <= INT32_MAX && "truncated destination index");
11973 if (FromV1 == FromV2 &&
11974 static_cast<int>(DestIndex) == Mask[DestIndex] % 4) {
11978 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
11981 assert(std::count_if(Mask.begin(), Mask.end(), FromV2Predicate) == 1 &&
11982 "More than one element from V1 and from V2, or no elements from one "
11983 "of the vectors. This case should not have returned true from "
11988 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
11991 // Get an index into the source vector in the range [0,4) (the mask is
11992 // in the range [0,8) because it can address V1 and V2)
11993 unsigned SrcIndex = Mask[DestIndex] % 4;
11994 if (MayFoldLoad(From)) {
11995 // Trivial case, when From comes from a load and is only used by the
11996 // shuffle. Make it use insertps from the vector that we need from that
11999 NarrowVectorLoadToElement(cast<LoadSDNode>(From), SrcIndex, DAG);
12000 if (!NewLoad.getNode())
12003 if (EVT == MVT::f32) {
12004 // Create this as a scalar to vector to match the instruction pattern.
12005 SDValue LoadScalarToVector =
12006 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, NewLoad);
12007 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4);
12008 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, LoadScalarToVector,
12010 } else { // EVT == MVT::i32
12011 // If we're getting an i32 from memory, use an INSERT_VECTOR_ELT
12012 // instruction, to match the PINSRD instruction, which loads an i32 to a
12013 // certain vector element.
12014 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, To, NewLoad,
12015 DAG.getConstant(DestIndex, MVT::i32));
12019 // Vector-element-to-vector
12020 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4 | SrcIndex << 6);
12021 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, From, InsertpsMask);
12024 // Reduce a vector shuffle to zext.
12025 static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
12026 SelectionDAG &DAG) {
12027 // PMOVZX is only available from SSE41.
12028 if (!Subtarget->hasSSE41())
12031 MVT VT = Op.getSimpleValueType();
12033 // Only AVX2 support 256-bit vector integer extending.
12034 if (!Subtarget->hasInt256() && VT.is256BitVector())
12037 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
12039 SDValue V1 = Op.getOperand(0);
12040 SDValue V2 = Op.getOperand(1);
12041 unsigned NumElems = VT.getVectorNumElements();
12043 // Extending is an unary operation and the element type of the source vector
12044 // won't be equal to or larger than i64.
12045 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
12046 VT.getVectorElementType() == MVT::i64)
12049 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
12050 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
12051 while ((1U << Shift) < NumElems) {
12052 if (SVOp->getMaskElt(1U << Shift) == 1)
12055 // The maximal ratio is 8, i.e. from i8 to i64.
12060 // Check the shuffle mask.
12061 unsigned Mask = (1U << Shift) - 1;
12062 for (unsigned i = 0; i != NumElems; ++i) {
12063 int EltIdx = SVOp->getMaskElt(i);
12064 if ((i & Mask) != 0 && EltIdx != -1)
12066 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
12070 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
12071 MVT NeVT = MVT::getIntegerVT(NBits);
12072 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift);
12074 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT))
12077 return DAG.getNode(ISD::BITCAST, DL, VT,
12078 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
12081 static SDValue NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
12082 SelectionDAG &DAG) {
12083 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
12084 MVT VT = Op.getSimpleValueType();
12086 SDValue V1 = Op.getOperand(0);
12087 SDValue V2 = Op.getOperand(1);
12089 if (isZeroShuffle(SVOp))
12090 return getZeroVector(VT, Subtarget, DAG, dl);
12092 // Handle splat operations
12093 if (SVOp->isSplat()) {
12094 // Use vbroadcast whenever the splat comes from a foldable load
12095 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
12096 if (Broadcast.getNode())
12100 // Check integer expanding shuffles.
12101 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG);
12102 if (NewOp.getNode())
12105 // If the shuffle can be profitably rewritten as a narrower shuffle, then
12107 if (VT == MVT::v8i16 || VT == MVT::v16i8 || VT == MVT::v16i16 ||
12108 VT == MVT::v32i8) {
12109 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
12110 if (NewOp.getNode())
12111 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
12112 } else if (VT.is128BitVector() && Subtarget->hasSSE2()) {
12113 // FIXME: Figure out a cleaner way to do this.
12114 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
12115 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
12116 if (NewOp.getNode()) {
12117 MVT NewVT = NewOp.getSimpleValueType();
12118 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
12119 NewVT, true, false))
12120 return getVZextMovL(VT, NewVT, NewOp.getOperand(0), DAG, Subtarget,
12123 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
12124 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
12125 if (NewOp.getNode()) {
12126 MVT NewVT = NewOp.getSimpleValueType();
12127 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
12128 return getVZextMovL(VT, NewVT, NewOp.getOperand(1), DAG, Subtarget,
12137 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
12138 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
12139 SDValue V1 = Op.getOperand(0);
12140 SDValue V2 = Op.getOperand(1);
12141 MVT VT = Op.getSimpleValueType();
12143 unsigned NumElems = VT.getVectorNumElements();
12144 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
12145 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
12146 bool V1IsSplat = false;
12147 bool V2IsSplat = false;
12148 bool HasSSE2 = Subtarget->hasSSE2();
12149 bool HasFp256 = Subtarget->hasFp256();
12150 bool HasInt256 = Subtarget->hasInt256();
12151 MachineFunction &MF = DAG.getMachineFunction();
12152 bool OptForSize = MF.getFunction()->getAttributes().
12153 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
12155 // Check if we should use the experimental vector shuffle lowering. If so,
12156 // delegate completely to that code path.
12157 if (ExperimentalVectorShuffleLowering)
12158 return lowerVectorShuffle(Op, Subtarget, DAG);
12160 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
12162 if (V1IsUndef && V2IsUndef)
12163 return DAG.getUNDEF(VT);
12165 // When we create a shuffle node we put the UNDEF node to second operand,
12166 // but in some cases the first operand may be transformed to UNDEF.
12167 // In this case we should just commute the node.
12169 return DAG.getCommutedVectorShuffle(*SVOp);
12171 // Vector shuffle lowering takes 3 steps:
12173 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
12174 // narrowing and commutation of operands should be handled.
12175 // 2) Matching of shuffles with known shuffle masks to x86 target specific
12177 // 3) Rewriting of unmatched masks into new generic shuffle operations,
12178 // so the shuffle can be broken into other shuffles and the legalizer can
12179 // try the lowering again.
12181 // The general idea is that no vector_shuffle operation should be left to
12182 // be matched during isel, all of them must be converted to a target specific
12185 // Normalize the input vectors. Here splats, zeroed vectors, profitable
12186 // narrowing and commutation of operands should be handled. The actual code
12187 // doesn't include all of those, work in progress...
12188 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
12189 if (NewOp.getNode())
12192 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
12194 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
12195 // unpckh_undef). Only use pshufd if speed is more important than size.
12196 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
12197 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
12198 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
12199 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
12201 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
12202 V2IsUndef && MayFoldVectorLoad(V1))
12203 return getMOVDDup(Op, dl, V1, DAG);
12205 if (isMOVHLPS_v_undef_Mask(M, VT))
12206 return getMOVHighToLow(Op, dl, DAG);
12208 // Use to match splats
12209 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
12210 (VT == MVT::v2f64 || VT == MVT::v2i64))
12211 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
12213 if (isPSHUFDMask(M, VT)) {
12214 // The actual implementation will match the mask in the if above and then
12215 // during isel it can match several different instructions, not only pshufd
12216 // as its name says, sad but true, emulate the behavior for now...
12217 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
12218 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
12220 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
12222 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
12223 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
12225 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
12226 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1, TargetMask,
12229 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
12233 if (isPALIGNRMask(M, VT, Subtarget))
12234 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
12235 getShufflePALIGNRImmediate(SVOp),
12238 if (isVALIGNMask(M, VT, Subtarget))
12239 return getTargetShuffleNode(X86ISD::VALIGN, dl, VT, V1, V2,
12240 getShuffleVALIGNImmediate(SVOp),
12243 // Check if this can be converted into a logical shift.
12244 bool isLeft = false;
12245 unsigned ShAmt = 0;
12247 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
12248 if (isShift && ShVal.hasOneUse()) {
12249 // If the shifted value has multiple uses, it may be cheaper to use
12250 // v_set0 + movlhps or movhlps, etc.
12251 MVT EltVT = VT.getVectorElementType();
12252 ShAmt *= EltVT.getSizeInBits();
12253 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
12256 if (isMOVLMask(M, VT)) {
12257 if (ISD::isBuildVectorAllZeros(V1.getNode()))
12258 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
12259 if (!isMOVLPMask(M, VT)) {
12260 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
12261 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
12263 if (VT == MVT::v4i32 || VT == MVT::v4f32)
12264 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
12268 // FIXME: fold these into legal mask.
12269 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
12270 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
12272 if (isMOVHLPSMask(M, VT))
12273 return getMOVHighToLow(Op, dl, DAG);
12275 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
12276 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
12278 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
12279 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
12281 if (isMOVLPMask(M, VT))
12282 return getMOVLP(Op, dl, DAG, HasSSE2);
12284 if (ShouldXformToMOVHLPS(M, VT) ||
12285 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
12286 return DAG.getCommutedVectorShuffle(*SVOp);
12289 // No better options. Use a vshldq / vsrldq.
12290 MVT EltVT = VT.getVectorElementType();
12291 ShAmt *= EltVT.getSizeInBits();
12292 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
12295 bool Commuted = false;
12296 // FIXME: This should also accept a bitcast of a splat? Be careful, not
12297 // 1,1,1,1 -> v8i16 though.
12298 BitVector UndefElements;
12299 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V1.getNode()))
12300 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
12302 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V2.getNode()))
12303 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
12306 // Canonicalize the splat or undef, if present, to be on the RHS.
12307 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
12308 CommuteVectorShuffleMask(M, NumElems);
12310 std::swap(V1IsSplat, V2IsSplat);
12314 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
12315 // Shuffling low element of v1 into undef, just return v1.
12318 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
12319 // the instruction selector will not match, so get a canonical MOVL with
12320 // swapped operands to undo the commute.
12321 return getMOVL(DAG, dl, VT, V2, V1);
12324 if (isUNPCKLMask(M, VT, HasInt256))
12325 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
12327 if (isUNPCKHMask(M, VT, HasInt256))
12328 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
12331 // Normalize mask so all entries that point to V2 points to its first
12332 // element then try to match unpck{h|l} again. If match, return a
12333 // new vector_shuffle with the corrected mask.p
12334 SmallVector<int, 8> NewMask(M.begin(), M.end());
12335 NormalizeMask(NewMask, NumElems);
12336 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
12337 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
12338 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
12339 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
12343 // Commute is back and try unpck* again.
12344 // FIXME: this seems wrong.
12345 CommuteVectorShuffleMask(M, NumElems);
12347 std::swap(V1IsSplat, V2IsSplat);
12349 if (isUNPCKLMask(M, VT, HasInt256))
12350 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
12352 if (isUNPCKHMask(M, VT, HasInt256))
12353 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
12356 // Normalize the node to match x86 shuffle ops if needed
12357 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
12358 return DAG.getCommutedVectorShuffle(*SVOp);
12360 // The checks below are all present in isShuffleMaskLegal, but they are
12361 // inlined here right now to enable us to directly emit target specific
12362 // nodes, and remove one by one until they don't return Op anymore.
12364 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
12365 SVOp->getSplatIndex() == 0 && V2IsUndef) {
12366 if (VT == MVT::v2f64 || VT == MVT::v2i64)
12367 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
12370 if (isPSHUFHWMask(M, VT, HasInt256))
12371 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
12372 getShufflePSHUFHWImmediate(SVOp),
12375 if (isPSHUFLWMask(M, VT, HasInt256))
12376 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
12377 getShufflePSHUFLWImmediate(SVOp),
12380 unsigned MaskValue;
12381 if (isBlendMask(M, VT, Subtarget->hasSSE41(), Subtarget->hasInt256(),
12383 return LowerVECTOR_SHUFFLEtoBlend(SVOp, MaskValue, Subtarget, DAG);
12385 if (isSHUFPMask(M, VT))
12386 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
12387 getShuffleSHUFImmediate(SVOp), DAG);
12389 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
12390 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
12391 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
12392 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
12394 //===--------------------------------------------------------------------===//
12395 // Generate target specific nodes for 128 or 256-bit shuffles only
12396 // supported in the AVX instruction set.
12399 // Handle VMOVDDUPY permutations
12400 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
12401 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
12403 // Handle VPERMILPS/D* permutations
12404 if (isVPERMILPMask(M, VT)) {
12405 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
12406 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
12407 getShuffleSHUFImmediate(SVOp), DAG);
12408 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1,
12409 getShuffleSHUFImmediate(SVOp), DAG);
12413 if (VT.is512BitVector() && isINSERT64x4Mask(M, VT, &Idx))
12414 return Insert256BitVector(V1, Extract256BitVector(V2, 0, DAG, dl),
12415 Idx*(NumElems/2), DAG, dl);
12417 // Handle VPERM2F128/VPERM2I128 permutations
12418 if (isVPERM2X128Mask(M, VT, HasFp256))
12419 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
12420 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
12422 if (Subtarget->hasSSE41() && isINSERTPSMask(M, VT))
12423 return getINSERTPS(SVOp, dl, DAG);
12426 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
12427 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
12429 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
12430 VT.is512BitVector()) {
12431 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
12432 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
12433 SmallVector<SDValue, 16> permclMask;
12434 for (unsigned i = 0; i != NumElems; ++i) {
12435 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
12438 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT, permclMask);
12440 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
12441 return DAG.getNode(X86ISD::VPERMV, dl, VT,
12442 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
12443 return DAG.getNode(X86ISD::VPERMV3, dl, VT, V1,
12444 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V2);
12447 //===--------------------------------------------------------------------===//
12448 // Since no target specific shuffle was selected for this generic one,
12449 // lower it into other known shuffles. FIXME: this isn't true yet, but
12450 // this is the plan.
12453 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
12454 if (VT == MVT::v8i16) {
12455 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
12456 if (NewOp.getNode())
12460 if (VT == MVT::v16i16 && Subtarget->hasInt256()) {
12461 SDValue NewOp = LowerVECTOR_SHUFFLEv16i16(Op, DAG);
12462 if (NewOp.getNode())
12466 if (VT == MVT::v16i8) {
12467 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
12468 if (NewOp.getNode())
12472 if (VT == MVT::v32i8) {
12473 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
12474 if (NewOp.getNode())
12478 // Handle all 128-bit wide vectors with 4 elements, and match them with
12479 // several different shuffle types.
12480 if (NumElems == 4 && VT.is128BitVector())
12481 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
12483 // Handle general 256-bit shuffles
12484 if (VT.is256BitVector())
12485 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
12490 // This function assumes its argument is a BUILD_VECTOR of constants or
12491 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
12493 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
12494 unsigned &MaskValue) {
12496 unsigned NumElems = BuildVector->getNumOperands();
12497 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
12498 unsigned NumLanes = (NumElems - 1) / 8 + 1;
12499 unsigned NumElemsInLane = NumElems / NumLanes;
12501 // Blend for v16i16 should be symetric for the both lanes.
12502 for (unsigned i = 0; i < NumElemsInLane; ++i) {
12503 SDValue EltCond = BuildVector->getOperand(i);
12504 SDValue SndLaneEltCond =
12505 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
12507 int Lane1Cond = -1, Lane2Cond = -1;
12508 if (isa<ConstantSDNode>(EltCond))
12509 Lane1Cond = !isZero(EltCond);
12510 if (isa<ConstantSDNode>(SndLaneEltCond))
12511 Lane2Cond = !isZero(SndLaneEltCond);
12513 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
12514 // Lane1Cond != 0, means we want the first argument.
12515 // Lane1Cond == 0, means we want the second argument.
12516 // The encoding of this argument is 0 for the first argument, 1
12517 // for the second. Therefore, invert the condition.
12518 MaskValue |= !Lane1Cond << i;
12519 else if (Lane1Cond < 0)
12520 MaskValue |= !Lane2Cond << i;
12527 /// \brief Try to lower a VSELECT instruction to an immediate-controlled blend
12529 static SDValue lowerVSELECTtoBLENDI(SDValue Op, const X86Subtarget *Subtarget,
12530 SelectionDAG &DAG) {
12531 SDValue Cond = Op.getOperand(0);
12532 SDValue LHS = Op.getOperand(1);
12533 SDValue RHS = Op.getOperand(2);
12535 MVT VT = Op.getSimpleValueType();
12536 MVT EltVT = VT.getVectorElementType();
12537 unsigned NumElems = VT.getVectorNumElements();
12539 // There is no blend with immediate in AVX-512.
12540 if (VT.is512BitVector())
12543 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
12545 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
12548 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
12551 // Check the mask for BLEND and build the value.
12552 unsigned MaskValue = 0;
12553 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
12556 // Convert i32 vectors to floating point if it is not AVX2.
12557 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
12559 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
12560 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
12562 LHS = DAG.getNode(ISD::BITCAST, dl, VT, LHS);
12563 RHS = DAG.getNode(ISD::BITCAST, dl, VT, RHS);
12566 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, LHS, RHS,
12567 DAG.getConstant(MaskValue, MVT::i32));
12568 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
12571 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
12572 // A vselect where all conditions and data are constants can be optimized into
12573 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
12574 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
12575 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
12576 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
12579 SDValue BlendOp = lowerVSELECTtoBLENDI(Op, Subtarget, DAG);
12580 if (BlendOp.getNode())
12583 // Some types for vselect were previously set to Expand, not Legal or
12584 // Custom. Return an empty SDValue so we fall-through to Expand, after
12585 // the Custom lowering phase.
12586 MVT VT = Op.getSimpleValueType();
12587 switch (VT.SimpleTy) {
12592 if (Subtarget->hasBWI() && Subtarget->hasVLX())
12597 // We couldn't create a "Blend with immediate" node.
12598 // This node should still be legal, but we'll have to emit a blendv*
12603 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
12604 MVT VT = Op.getSimpleValueType();
12607 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
12610 if (VT.getSizeInBits() == 8) {
12611 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
12612 Op.getOperand(0), Op.getOperand(1));
12613 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
12614 DAG.getValueType(VT));
12615 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12618 if (VT.getSizeInBits() == 16) {
12619 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12620 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
12622 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
12623 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12624 DAG.getNode(ISD::BITCAST, dl,
12627 Op.getOperand(1)));
12628 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
12629 Op.getOperand(0), Op.getOperand(1));
12630 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
12631 DAG.getValueType(VT));
12632 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12635 if (VT == MVT::f32) {
12636 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
12637 // the result back to FR32 register. It's only worth matching if the
12638 // result has a single use which is a store or a bitcast to i32. And in
12639 // the case of a store, it's not worth it if the index is a constant 0,
12640 // because a MOVSSmr can be used instead, which is smaller and faster.
12641 if (!Op.hasOneUse())
12643 SDNode *User = *Op.getNode()->use_begin();
12644 if ((User->getOpcode() != ISD::STORE ||
12645 (isa<ConstantSDNode>(Op.getOperand(1)) &&
12646 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
12647 (User->getOpcode() != ISD::BITCAST ||
12648 User->getValueType(0) != MVT::i32))
12650 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12651 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
12654 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
12657 if (VT == MVT::i32 || VT == MVT::i64) {
12658 // ExtractPS/pextrq works with constant index.
12659 if (isa<ConstantSDNode>(Op.getOperand(1)))
12665 /// Extract one bit from mask vector, like v16i1 or v8i1.
12666 /// AVX-512 feature.
12668 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
12669 SDValue Vec = Op.getOperand(0);
12671 MVT VecVT = Vec.getSimpleValueType();
12672 SDValue Idx = Op.getOperand(1);
12673 MVT EltVT = Op.getSimpleValueType();
12675 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
12677 // variable index can't be handled in mask registers,
12678 // extend vector to VR512
12679 if (!isa<ConstantSDNode>(Idx)) {
12680 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
12681 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
12682 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
12683 ExtVT.getVectorElementType(), Ext, Idx);
12684 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
12687 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12688 const TargetRegisterClass* rc = getRegClassFor(VecVT);
12689 unsigned MaxSift = rc->getSize()*8 - 1;
12690 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
12691 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
12692 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
12693 DAG.getConstant(MaxSift, MVT::i8));
12694 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
12695 DAG.getIntPtrConstant(0));
12699 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
12700 SelectionDAG &DAG) const {
12702 SDValue Vec = Op.getOperand(0);
12703 MVT VecVT = Vec.getSimpleValueType();
12704 SDValue Idx = Op.getOperand(1);
12706 if (Op.getSimpleValueType() == MVT::i1)
12707 return ExtractBitFromMaskVector(Op, DAG);
12709 if (!isa<ConstantSDNode>(Idx)) {
12710 if (VecVT.is512BitVector() ||
12711 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
12712 VecVT.getVectorElementType().getSizeInBits() == 32)) {
12715 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
12716 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
12717 MaskEltVT.getSizeInBits());
12719 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
12720 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
12721 getZeroVector(MaskVT, Subtarget, DAG, dl),
12722 Idx, DAG.getConstant(0, getPointerTy()));
12723 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
12724 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
12725 Perm, DAG.getConstant(0, getPointerTy()));
12730 // If this is a 256-bit vector result, first extract the 128-bit vector and
12731 // then extract the element from the 128-bit vector.
12732 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
12734 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12735 // Get the 128-bit vector.
12736 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
12737 MVT EltVT = VecVT.getVectorElementType();
12739 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
12741 //if (IdxVal >= NumElems/2)
12742 // IdxVal -= NumElems/2;
12743 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
12744 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
12745 DAG.getConstant(IdxVal, MVT::i32));
12748 assert(VecVT.is128BitVector() && "Unexpected vector length");
12750 if (Subtarget->hasSSE41()) {
12751 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
12756 MVT VT = Op.getSimpleValueType();
12757 // TODO: handle v16i8.
12758 if (VT.getSizeInBits() == 16) {
12759 SDValue Vec = Op.getOperand(0);
12760 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12762 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
12763 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12764 DAG.getNode(ISD::BITCAST, dl,
12766 Op.getOperand(1)));
12767 // Transform it so it match pextrw which produces a 32-bit result.
12768 MVT EltVT = MVT::i32;
12769 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
12770 Op.getOperand(0), Op.getOperand(1));
12771 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
12772 DAG.getValueType(VT));
12773 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12776 if (VT.getSizeInBits() == 32) {
12777 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12781 // SHUFPS the element to the lowest double word, then movss.
12782 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
12783 MVT VVT = Op.getOperand(0).getSimpleValueType();
12784 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
12785 DAG.getUNDEF(VVT), Mask);
12786 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
12787 DAG.getIntPtrConstant(0));
12790 if (VT.getSizeInBits() == 64) {
12791 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
12792 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
12793 // to match extract_elt for f64.
12794 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12798 // UNPCKHPD the element to the lowest double word, then movsd.
12799 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
12800 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
12801 int Mask[2] = { 1, -1 };
12802 MVT VVT = Op.getOperand(0).getSimpleValueType();
12803 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
12804 DAG.getUNDEF(VVT), Mask);
12805 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
12806 DAG.getIntPtrConstant(0));
12812 /// Insert one bit to mask vector, like v16i1 or v8i1.
12813 /// AVX-512 feature.
12815 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
12817 SDValue Vec = Op.getOperand(0);
12818 SDValue Elt = Op.getOperand(1);
12819 SDValue Idx = Op.getOperand(2);
12820 MVT VecVT = Vec.getSimpleValueType();
12822 if (!isa<ConstantSDNode>(Idx)) {
12823 // Non constant index. Extend source and destination,
12824 // insert element and then truncate the result.
12825 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
12826 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
12827 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
12828 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
12829 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
12830 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
12833 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12834 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
12835 if (Vec.getOpcode() == ISD::UNDEF)
12836 return DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
12837 DAG.getConstant(IdxVal, MVT::i8));
12838 const TargetRegisterClass* rc = getRegClassFor(VecVT);
12839 unsigned MaxSift = rc->getSize()*8 - 1;
12840 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
12841 DAG.getConstant(MaxSift, MVT::i8));
12842 EltInVec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, EltInVec,
12843 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
12844 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
12847 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
12848 SelectionDAG &DAG) const {
12849 MVT VT = Op.getSimpleValueType();
12850 MVT EltVT = VT.getVectorElementType();
12852 if (EltVT == MVT::i1)
12853 return InsertBitToMaskVector(Op, DAG);
12856 SDValue N0 = Op.getOperand(0);
12857 SDValue N1 = Op.getOperand(1);
12858 SDValue N2 = Op.getOperand(2);
12859 if (!isa<ConstantSDNode>(N2))
12861 auto *N2C = cast<ConstantSDNode>(N2);
12862 unsigned IdxVal = N2C->getZExtValue();
12864 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
12865 // into that, and then insert the subvector back into the result.
12866 if (VT.is256BitVector() || VT.is512BitVector()) {
12867 // Get the desired 128-bit vector half.
12868 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
12870 // Insert the element into the desired half.
12871 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
12872 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
12874 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
12875 DAG.getConstant(IdxIn128, MVT::i32));
12877 // Insert the changed part back to the 256-bit vector
12878 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
12880 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
12882 if (Subtarget->hasSSE41()) {
12883 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
12885 if (VT == MVT::v8i16) {
12886 Opc = X86ISD::PINSRW;
12888 assert(VT == MVT::v16i8);
12889 Opc = X86ISD::PINSRB;
12892 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
12894 if (N1.getValueType() != MVT::i32)
12895 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
12896 if (N2.getValueType() != MVT::i32)
12897 N2 = DAG.getIntPtrConstant(IdxVal);
12898 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
12901 if (EltVT == MVT::f32) {
12902 // Bits [7:6] of the constant are the source select. This will always be
12903 // zero here. The DAG Combiner may combine an extract_elt index into
12905 // bits. For example (insert (extract, 3), 2) could be matched by
12907 // the '3' into bits [7:6] of X86ISD::INSERTPS.
12908 // Bits [5:4] of the constant are the destination select. This is the
12909 // value of the incoming immediate.
12910 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
12911 // combine either bitwise AND or insert of float 0.0 to set these bits.
12912 N2 = DAG.getIntPtrConstant(IdxVal << 4);
12913 // Create this as a scalar to vector..
12914 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
12915 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
12918 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
12919 // PINSR* works with constant index.
12924 if (EltVT == MVT::i8)
12927 if (EltVT.getSizeInBits() == 16) {
12928 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
12929 // as its second argument.
12930 if (N1.getValueType() != MVT::i32)
12931 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
12932 if (N2.getValueType() != MVT::i32)
12933 N2 = DAG.getIntPtrConstant(IdxVal);
12934 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
12939 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
12941 MVT OpVT = Op.getSimpleValueType();
12943 // If this is a 256-bit vector result, first insert into a 128-bit
12944 // vector and then insert into the 256-bit vector.
12945 if (!OpVT.is128BitVector()) {
12946 // Insert into a 128-bit vector.
12947 unsigned SizeFactor = OpVT.getSizeInBits()/128;
12948 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
12949 OpVT.getVectorNumElements() / SizeFactor);
12951 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
12953 // Insert the 128-bit vector.
12954 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
12957 if (OpVT == MVT::v1i64 &&
12958 Op.getOperand(0).getValueType() == MVT::i64)
12959 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
12961 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
12962 assert(OpVT.is128BitVector() && "Expected an SSE type!");
12963 return DAG.getNode(ISD::BITCAST, dl, OpVT,
12964 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
12967 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
12968 // a simple subregister reference or explicit instructions to grab
12969 // upper bits of a vector.
12970 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
12971 SelectionDAG &DAG) {
12973 SDValue In = Op.getOperand(0);
12974 SDValue Idx = Op.getOperand(1);
12975 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12976 MVT ResVT = Op.getSimpleValueType();
12977 MVT InVT = In.getSimpleValueType();
12979 if (Subtarget->hasFp256()) {
12980 if (ResVT.is128BitVector() &&
12981 (InVT.is256BitVector() || InVT.is512BitVector()) &&
12982 isa<ConstantSDNode>(Idx)) {
12983 return Extract128BitVector(In, IdxVal, DAG, dl);
12985 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
12986 isa<ConstantSDNode>(Idx)) {
12987 return Extract256BitVector(In, IdxVal, DAG, dl);
12993 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
12994 // simple superregister reference or explicit instructions to insert
12995 // the upper bits of a vector.
12996 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
12997 SelectionDAG &DAG) {
12998 if (Subtarget->hasFp256()) {
12999 SDLoc dl(Op.getNode());
13000 SDValue Vec = Op.getNode()->getOperand(0);
13001 SDValue SubVec = Op.getNode()->getOperand(1);
13002 SDValue Idx = Op.getNode()->getOperand(2);
13004 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() ||
13005 Op.getNode()->getSimpleValueType(0).is512BitVector()) &&
13006 SubVec.getNode()->getSimpleValueType(0).is128BitVector() &&
13007 isa<ConstantSDNode>(Idx)) {
13008 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
13009 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
13012 if (Op.getNode()->getSimpleValueType(0).is512BitVector() &&
13013 SubVec.getNode()->getSimpleValueType(0).is256BitVector() &&
13014 isa<ConstantSDNode>(Idx)) {
13015 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
13016 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
13022 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
13023 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
13024 // one of the above mentioned nodes. It has to be wrapped because otherwise
13025 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
13026 // be used to form addressing mode. These wrapped nodes will be selected
13029 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
13030 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
13032 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13033 // global base reg.
13034 unsigned char OpFlag = 0;
13035 unsigned WrapperKind = X86ISD::Wrapper;
13036 CodeModel::Model M = DAG.getTarget().getCodeModel();
13038 if (Subtarget->isPICStyleRIPRel() &&
13039 (M == CodeModel::Small || M == CodeModel::Kernel))
13040 WrapperKind = X86ISD::WrapperRIP;
13041 else if (Subtarget->isPICStyleGOT())
13042 OpFlag = X86II::MO_GOTOFF;
13043 else if (Subtarget->isPICStyleStubPIC())
13044 OpFlag = X86II::MO_PIC_BASE_OFFSET;
13046 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
13047 CP->getAlignment(),
13048 CP->getOffset(), OpFlag);
13050 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13051 // With PIC, the address is actually $g + Offset.
13053 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13054 DAG.getNode(X86ISD::GlobalBaseReg,
13055 SDLoc(), getPointerTy()),
13062 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
13063 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
13065 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13066 // global base reg.
13067 unsigned char OpFlag = 0;
13068 unsigned WrapperKind = X86ISD::Wrapper;
13069 CodeModel::Model M = DAG.getTarget().getCodeModel();
13071 if (Subtarget->isPICStyleRIPRel() &&
13072 (M == CodeModel::Small || M == CodeModel::Kernel))
13073 WrapperKind = X86ISD::WrapperRIP;
13074 else if (Subtarget->isPICStyleGOT())
13075 OpFlag = X86II::MO_GOTOFF;
13076 else if (Subtarget->isPICStyleStubPIC())
13077 OpFlag = X86II::MO_PIC_BASE_OFFSET;
13079 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
13082 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13084 // With PIC, the address is actually $g + Offset.
13086 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13087 DAG.getNode(X86ISD::GlobalBaseReg,
13088 SDLoc(), getPointerTy()),
13095 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
13096 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
13098 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13099 // global base reg.
13100 unsigned char OpFlag = 0;
13101 unsigned WrapperKind = X86ISD::Wrapper;
13102 CodeModel::Model M = DAG.getTarget().getCodeModel();
13104 if (Subtarget->isPICStyleRIPRel() &&
13105 (M == CodeModel::Small || M == CodeModel::Kernel)) {
13106 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
13107 OpFlag = X86II::MO_GOTPCREL;
13108 WrapperKind = X86ISD::WrapperRIP;
13109 } else if (Subtarget->isPICStyleGOT()) {
13110 OpFlag = X86II::MO_GOT;
13111 } else if (Subtarget->isPICStyleStubPIC()) {
13112 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
13113 } else if (Subtarget->isPICStyleStubNoDynamic()) {
13114 OpFlag = X86II::MO_DARWIN_NONLAZY;
13117 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
13120 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13122 // With PIC, the address is actually $g + Offset.
13123 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
13124 !Subtarget->is64Bit()) {
13125 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13126 DAG.getNode(X86ISD::GlobalBaseReg,
13127 SDLoc(), getPointerTy()),
13131 // For symbols that require a load from a stub to get the address, emit the
13133 if (isGlobalStubReference(OpFlag))
13134 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
13135 MachinePointerInfo::getGOT(), false, false, false, 0);
13141 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
13142 // Create the TargetBlockAddressAddress node.
13143 unsigned char OpFlags =
13144 Subtarget->ClassifyBlockAddressReference();
13145 CodeModel::Model M = DAG.getTarget().getCodeModel();
13146 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
13147 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
13149 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
13152 if (Subtarget->isPICStyleRIPRel() &&
13153 (M == CodeModel::Small || M == CodeModel::Kernel))
13154 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
13156 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
13158 // With PIC, the address is actually $g + Offset.
13159 if (isGlobalRelativeToPICBase(OpFlags)) {
13160 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
13161 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
13169 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
13170 int64_t Offset, SelectionDAG &DAG) const {
13171 // Create the TargetGlobalAddress node, folding in the constant
13172 // offset if it is legal.
13173 unsigned char OpFlags =
13174 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
13175 CodeModel::Model M = DAG.getTarget().getCodeModel();
13177 if (OpFlags == X86II::MO_NO_FLAG &&
13178 X86::isOffsetSuitableForCodeModel(Offset, M)) {
13179 // A direct static reference to a global.
13180 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
13183 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
13186 if (Subtarget->isPICStyleRIPRel() &&
13187 (M == CodeModel::Small || M == CodeModel::Kernel))
13188 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
13190 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
13192 // With PIC, the address is actually $g + Offset.
13193 if (isGlobalRelativeToPICBase(OpFlags)) {
13194 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
13195 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
13199 // For globals that require a load from a stub to get the address, emit the
13201 if (isGlobalStubReference(OpFlags))
13202 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
13203 MachinePointerInfo::getGOT(), false, false, false, 0);
13205 // If there was a non-zero offset that we didn't fold, create an explicit
13206 // addition for it.
13208 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
13209 DAG.getConstant(Offset, getPointerTy()));
13215 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
13216 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
13217 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
13218 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
13222 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
13223 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
13224 unsigned char OperandFlags, bool LocalDynamic = false) {
13225 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
13226 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
13228 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
13229 GA->getValueType(0),
13233 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
13237 SDValue Ops[] = { Chain, TGA, *InFlag };
13238 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
13240 SDValue Ops[] = { Chain, TGA };
13241 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
13244 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
13245 MFI->setAdjustsStack(true);
13246 MFI->setHasCalls(true);
13248 SDValue Flag = Chain.getValue(1);
13249 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
13252 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
13254 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
13257 SDLoc dl(GA); // ? function entry point might be better
13258 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
13259 DAG.getNode(X86ISD::GlobalBaseReg,
13260 SDLoc(), PtrVT), InFlag);
13261 InFlag = Chain.getValue(1);
13263 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
13266 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
13268 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
13270 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
13271 X86::RAX, X86II::MO_TLSGD);
13274 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
13280 // Get the start address of the TLS block for this module.
13281 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
13282 .getInfo<X86MachineFunctionInfo>();
13283 MFI->incNumLocalDynamicTLSAccesses();
13287 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
13288 X86II::MO_TLSLD, /*LocalDynamic=*/true);
13291 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
13292 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
13293 InFlag = Chain.getValue(1);
13294 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
13295 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
13298 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
13302 unsigned char OperandFlags = X86II::MO_DTPOFF;
13303 unsigned WrapperKind = X86ISD::Wrapper;
13304 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
13305 GA->getValueType(0),
13306 GA->getOffset(), OperandFlags);
13307 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
13309 // Add x@dtpoff with the base.
13310 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
13313 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
13314 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
13315 const EVT PtrVT, TLSModel::Model model,
13316 bool is64Bit, bool isPIC) {
13319 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
13320 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
13321 is64Bit ? 257 : 256));
13323 SDValue ThreadPointer =
13324 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
13325 MachinePointerInfo(Ptr), false, false, false, 0);
13327 unsigned char OperandFlags = 0;
13328 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
13330 unsigned WrapperKind = X86ISD::Wrapper;
13331 if (model == TLSModel::LocalExec) {
13332 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
13333 } else if (model == TLSModel::InitialExec) {
13335 OperandFlags = X86II::MO_GOTTPOFF;
13336 WrapperKind = X86ISD::WrapperRIP;
13338 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
13341 llvm_unreachable("Unexpected model");
13344 // emit "addl x@ntpoff,%eax" (local exec)
13345 // or "addl x@indntpoff,%eax" (initial exec)
13346 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
13348 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
13349 GA->getOffset(), OperandFlags);
13350 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
13352 if (model == TLSModel::InitialExec) {
13353 if (isPIC && !is64Bit) {
13354 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
13355 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
13359 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
13360 MachinePointerInfo::getGOT(), false, false, false, 0);
13363 // The address of the thread local variable is the add of the thread
13364 // pointer with the offset of the variable.
13365 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
13369 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
13371 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
13372 const GlobalValue *GV = GA->getGlobal();
13374 if (Subtarget->isTargetELF()) {
13375 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
13378 case TLSModel::GeneralDynamic:
13379 if (Subtarget->is64Bit())
13380 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
13381 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
13382 case TLSModel::LocalDynamic:
13383 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
13384 Subtarget->is64Bit());
13385 case TLSModel::InitialExec:
13386 case TLSModel::LocalExec:
13387 return LowerToTLSExecModel(
13388 GA, DAG, getPointerTy(), model, Subtarget->is64Bit(),
13389 DAG.getTarget().getRelocationModel() == Reloc::PIC_);
13391 llvm_unreachable("Unknown TLS model.");
13394 if (Subtarget->isTargetDarwin()) {
13395 // Darwin only has one model of TLS. Lower to that.
13396 unsigned char OpFlag = 0;
13397 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
13398 X86ISD::WrapperRIP : X86ISD::Wrapper;
13400 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13401 // global base reg.
13402 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
13403 !Subtarget->is64Bit();
13405 OpFlag = X86II::MO_TLVP_PIC_BASE;
13407 OpFlag = X86II::MO_TLVP;
13409 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
13410 GA->getValueType(0),
13411 GA->getOffset(), OpFlag);
13412 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13414 // With PIC32, the address is actually $g + Offset.
13416 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13417 DAG.getNode(X86ISD::GlobalBaseReg,
13418 SDLoc(), getPointerTy()),
13421 // Lowering the machine isd will make sure everything is in the right
13423 SDValue Chain = DAG.getEntryNode();
13424 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
13425 SDValue Args[] = { Chain, Offset };
13426 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
13428 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
13429 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
13430 MFI->setAdjustsStack(true);
13432 // And our return value (tls address) is in the standard call return value
13434 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
13435 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
13436 Chain.getValue(1));
13439 if (Subtarget->isTargetKnownWindowsMSVC() ||
13440 Subtarget->isTargetWindowsGNU()) {
13441 // Just use the implicit TLS architecture
13442 // Need to generate someting similar to:
13443 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
13445 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
13446 // mov rcx, qword [rdx+rcx*8]
13447 // mov eax, .tls$:tlsvar
13448 // [rax+rcx] contains the address
13449 // Windows 64bit: gs:0x58
13450 // Windows 32bit: fs:__tls_array
13453 SDValue Chain = DAG.getEntryNode();
13455 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
13456 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
13457 // use its literal value of 0x2C.
13458 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
13459 ? Type::getInt8PtrTy(*DAG.getContext(),
13461 : Type::getInt32PtrTy(*DAG.getContext(),
13465 Subtarget->is64Bit()
13466 ? DAG.getIntPtrConstant(0x58)
13467 : (Subtarget->isTargetWindowsGNU()
13468 ? DAG.getIntPtrConstant(0x2C)
13469 : DAG.getExternalSymbol("_tls_array", getPointerTy()));
13471 SDValue ThreadPointer =
13472 DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
13473 MachinePointerInfo(Ptr), false, false, false, 0);
13475 // Load the _tls_index variable
13476 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
13477 if (Subtarget->is64Bit())
13478 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
13479 IDX, MachinePointerInfo(), MVT::i32,
13480 false, false, false, 0);
13482 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
13483 false, false, false, 0);
13485 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
13487 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
13489 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
13490 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
13491 false, false, false, 0);
13493 // Get the offset of start of .tls section
13494 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
13495 GA->getValueType(0),
13496 GA->getOffset(), X86II::MO_SECREL);
13497 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
13499 // The address of the thread local variable is the add of the thread
13500 // pointer with the offset of the variable.
13501 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
13504 llvm_unreachable("TLS not implemented for this target.");
13507 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
13508 /// and take a 2 x i32 value to shift plus a shift amount.
13509 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
13510 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
13511 MVT VT = Op.getSimpleValueType();
13512 unsigned VTBits = VT.getSizeInBits();
13514 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
13515 SDValue ShOpLo = Op.getOperand(0);
13516 SDValue ShOpHi = Op.getOperand(1);
13517 SDValue ShAmt = Op.getOperand(2);
13518 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
13519 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
13521 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
13522 DAG.getConstant(VTBits - 1, MVT::i8));
13523 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
13524 DAG.getConstant(VTBits - 1, MVT::i8))
13525 : DAG.getConstant(0, VT);
13527 SDValue Tmp2, Tmp3;
13528 if (Op.getOpcode() == ISD::SHL_PARTS) {
13529 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
13530 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
13532 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
13533 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
13536 // If the shift amount is larger or equal than the width of a part we can't
13537 // rely on the results of shld/shrd. Insert a test and select the appropriate
13538 // values for large shift amounts.
13539 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
13540 DAG.getConstant(VTBits, MVT::i8));
13541 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
13542 AndNode, DAG.getConstant(0, MVT::i8));
13545 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
13546 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
13547 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
13549 if (Op.getOpcode() == ISD::SHL_PARTS) {
13550 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
13551 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
13553 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
13554 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
13557 SDValue Ops[2] = { Lo, Hi };
13558 return DAG.getMergeValues(Ops, dl);
13561 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
13562 SelectionDAG &DAG) const {
13563 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
13566 if (SrcVT.isVector()) {
13567 if (SrcVT.getVectorElementType() == MVT::i1) {
13568 MVT IntegerVT = MVT::getVectorVT(MVT::i32, SrcVT.getVectorNumElements());
13569 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
13570 DAG.getNode(ISD::SIGN_EXTEND, dl, IntegerVT,
13571 Op.getOperand(0)));
13576 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
13577 "Unknown SINT_TO_FP to lower!");
13579 // These are really Legal; return the operand so the caller accepts it as
13581 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
13583 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
13584 Subtarget->is64Bit()) {
13588 unsigned Size = SrcVT.getSizeInBits()/8;
13589 MachineFunction &MF = DAG.getMachineFunction();
13590 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
13591 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13592 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13594 MachinePointerInfo::getFixedStack(SSFI),
13596 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
13599 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
13601 SelectionDAG &DAG) const {
13605 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
13607 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
13609 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
13611 unsigned ByteSize = SrcVT.getSizeInBits()/8;
13613 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
13614 MachineMemOperand *MMO;
13616 int SSFI = FI->getIndex();
13618 DAG.getMachineFunction()
13619 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13620 MachineMemOperand::MOLoad, ByteSize, ByteSize);
13622 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
13623 StackSlot = StackSlot.getOperand(1);
13625 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
13626 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
13628 Tys, Ops, SrcVT, MMO);
13631 Chain = Result.getValue(1);
13632 SDValue InFlag = Result.getValue(2);
13634 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
13635 // shouldn't be necessary except that RFP cannot be live across
13636 // multiple blocks. When stackifier is fixed, they can be uncoupled.
13637 MachineFunction &MF = DAG.getMachineFunction();
13638 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
13639 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
13640 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13641 Tys = DAG.getVTList(MVT::Other);
13643 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
13645 MachineMemOperand *MMO =
13646 DAG.getMachineFunction()
13647 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13648 MachineMemOperand::MOStore, SSFISize, SSFISize);
13650 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
13651 Ops, Op.getValueType(), MMO);
13652 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
13653 MachinePointerInfo::getFixedStack(SSFI),
13654 false, false, false, 0);
13660 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
13661 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
13662 SelectionDAG &DAG) const {
13663 // This algorithm is not obvious. Here it is what we're trying to output:
13666 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
13667 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
13669 haddpd %xmm0, %xmm0
13671 pshufd $0x4e, %xmm0, %xmm1
13677 LLVMContext *Context = DAG.getContext();
13679 // Build some magic constants.
13680 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
13681 Constant *C0 = ConstantDataVector::get(*Context, CV0);
13682 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
13684 SmallVector<Constant*,2> CV1;
13686 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
13687 APInt(64, 0x4330000000000000ULL))));
13689 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
13690 APInt(64, 0x4530000000000000ULL))));
13691 Constant *C1 = ConstantVector::get(CV1);
13692 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
13694 // Load the 64-bit value into an XMM register.
13695 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
13697 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
13698 MachinePointerInfo::getConstantPool(),
13699 false, false, false, 16);
13700 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
13701 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
13704 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
13705 MachinePointerInfo::getConstantPool(),
13706 false, false, false, 16);
13707 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
13708 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
13711 if (Subtarget->hasSSE3()) {
13712 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
13713 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
13715 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
13716 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
13718 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
13719 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
13723 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
13724 DAG.getIntPtrConstant(0));
13727 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
13728 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
13729 SelectionDAG &DAG) const {
13731 // FP constant to bias correct the final result.
13732 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
13735 // Load the 32-bit value into an XMM register.
13736 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
13739 // Zero out the upper parts of the register.
13740 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
13742 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
13743 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
13744 DAG.getIntPtrConstant(0));
13746 // Or the load with the bias.
13747 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
13748 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
13749 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13750 MVT::v2f64, Load)),
13751 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
13752 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13753 MVT::v2f64, Bias)));
13754 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
13755 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
13756 DAG.getIntPtrConstant(0));
13758 // Subtract the bias.
13759 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
13761 // Handle final rounding.
13762 EVT DestVT = Op.getValueType();
13764 if (DestVT.bitsLT(MVT::f64))
13765 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
13766 DAG.getIntPtrConstant(0));
13767 if (DestVT.bitsGT(MVT::f64))
13768 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
13770 // Handle final rounding.
13774 static SDValue lowerUINT_TO_FP_vXi32(SDValue Op, SelectionDAG &DAG,
13775 const X86Subtarget &Subtarget) {
13776 // The algorithm is the following:
13777 // #ifdef __SSE4_1__
13778 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
13779 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
13780 // (uint4) 0x53000000, 0xaa);
13782 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
13783 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
13785 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
13786 // return (float4) lo + fhi;
13789 SDValue V = Op->getOperand(0);
13790 EVT VecIntVT = V.getValueType();
13791 bool Is128 = VecIntVT == MVT::v4i32;
13792 EVT VecFloatVT = Is128 ? MVT::v4f32 : MVT::v8f32;
13793 // If we convert to something else than the supported type, e.g., to v4f64,
13795 if (VecFloatVT != Op->getValueType(0))
13798 unsigned NumElts = VecIntVT.getVectorNumElements();
13799 assert((VecIntVT == MVT::v4i32 || VecIntVT == MVT::v8i32) &&
13800 "Unsupported custom type");
13801 assert(NumElts <= 8 && "The size of the constant array must be fixed");
13803 // In the #idef/#else code, we have in common:
13804 // - The vector of constants:
13810 // Create the splat vector for 0x4b000000.
13811 SDValue CstLow = DAG.getConstant(0x4b000000, MVT::i32);
13812 SDValue CstLowArray[] = {CstLow, CstLow, CstLow, CstLow,
13813 CstLow, CstLow, CstLow, CstLow};
13814 SDValue VecCstLow = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
13815 makeArrayRef(&CstLowArray[0], NumElts));
13816 // Create the splat vector for 0x53000000.
13817 SDValue CstHigh = DAG.getConstant(0x53000000, MVT::i32);
13818 SDValue CstHighArray[] = {CstHigh, CstHigh, CstHigh, CstHigh,
13819 CstHigh, CstHigh, CstHigh, CstHigh};
13820 SDValue VecCstHigh = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
13821 makeArrayRef(&CstHighArray[0], NumElts));
13823 // Create the right shift.
13824 SDValue CstShift = DAG.getConstant(16, MVT::i32);
13825 SDValue CstShiftArray[] = {CstShift, CstShift, CstShift, CstShift,
13826 CstShift, CstShift, CstShift, CstShift};
13827 SDValue VecCstShift = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
13828 makeArrayRef(&CstShiftArray[0], NumElts));
13829 SDValue HighShift = DAG.getNode(ISD::SRL, DL, VecIntVT, V, VecCstShift);
13832 if (Subtarget.hasSSE41()) {
13833 EVT VecI16VT = Is128 ? MVT::v8i16 : MVT::v16i16;
13834 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
13835 SDValue VecCstLowBitcast =
13836 DAG.getNode(ISD::BITCAST, DL, VecI16VT, VecCstLow);
13837 SDValue VecBitcast = DAG.getNode(ISD::BITCAST, DL, VecI16VT, V);
13838 // Low will be bitcasted right away, so do not bother bitcasting back to its
13840 Low = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecBitcast,
13841 VecCstLowBitcast, DAG.getConstant(0xaa, MVT::i32));
13842 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
13843 // (uint4) 0x53000000, 0xaa);
13844 SDValue VecCstHighBitcast =
13845 DAG.getNode(ISD::BITCAST, DL, VecI16VT, VecCstHigh);
13846 SDValue VecShiftBitcast =
13847 DAG.getNode(ISD::BITCAST, DL, VecI16VT, HighShift);
13848 // High will be bitcasted right away, so do not bother bitcasting back to
13849 // its original type.
13850 High = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecShiftBitcast,
13851 VecCstHighBitcast, DAG.getConstant(0xaa, MVT::i32));
13853 SDValue CstMask = DAG.getConstant(0xffff, MVT::i32);
13854 SDValue VecCstMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, CstMask,
13855 CstMask, CstMask, CstMask);
13856 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
13857 SDValue LowAnd = DAG.getNode(ISD::AND, DL, VecIntVT, V, VecCstMask);
13858 Low = DAG.getNode(ISD::OR, DL, VecIntVT, LowAnd, VecCstLow);
13860 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
13861 High = DAG.getNode(ISD::OR, DL, VecIntVT, HighShift, VecCstHigh);
13864 // Create the vector constant for -(0x1.0p39f + 0x1.0p23f).
13865 SDValue CstFAdd = DAG.getConstantFP(
13866 APFloat(APFloat::IEEEsingle, APInt(32, 0xD3000080)), MVT::f32);
13867 SDValue CstFAddArray[] = {CstFAdd, CstFAdd, CstFAdd, CstFAdd,
13868 CstFAdd, CstFAdd, CstFAdd, CstFAdd};
13869 SDValue VecCstFAdd = DAG.getNode(ISD::BUILD_VECTOR, DL, VecFloatVT,
13870 makeArrayRef(&CstFAddArray[0], NumElts));
13872 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
13873 SDValue HighBitcast = DAG.getNode(ISD::BITCAST, DL, VecFloatVT, High);
13875 DAG.getNode(ISD::FADD, DL, VecFloatVT, HighBitcast, VecCstFAdd);
13876 // return (float4) lo + fhi;
13877 SDValue LowBitcast = DAG.getNode(ISD::BITCAST, DL, VecFloatVT, Low);
13878 return DAG.getNode(ISD::FADD, DL, VecFloatVT, LowBitcast, FHigh);
13881 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
13882 SelectionDAG &DAG) const {
13883 SDValue N0 = Op.getOperand(0);
13884 MVT SVT = N0.getSimpleValueType();
13887 switch (SVT.SimpleTy) {
13889 llvm_unreachable("Custom UINT_TO_FP is not supported!");
13894 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
13895 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
13896 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
13900 return lowerUINT_TO_FP_vXi32(Op, DAG, *Subtarget);
13902 llvm_unreachable(nullptr);
13905 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
13906 SelectionDAG &DAG) const {
13907 SDValue N0 = Op.getOperand(0);
13910 if (Op.getValueType().isVector())
13911 return lowerUINT_TO_FP_vec(Op, DAG);
13913 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
13914 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
13915 // the optimization here.
13916 if (DAG.SignBitIsZero(N0))
13917 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
13919 MVT SrcVT = N0.getSimpleValueType();
13920 MVT DstVT = Op.getSimpleValueType();
13921 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
13922 return LowerUINT_TO_FP_i64(Op, DAG);
13923 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
13924 return LowerUINT_TO_FP_i32(Op, DAG);
13925 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
13928 // Make a 64-bit buffer, and use it to build an FILD.
13929 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
13930 if (SrcVT == MVT::i32) {
13931 SDValue WordOff = DAG.getConstant(4, getPointerTy());
13932 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
13933 getPointerTy(), StackSlot, WordOff);
13934 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13935 StackSlot, MachinePointerInfo(),
13937 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
13938 OffsetSlot, MachinePointerInfo(),
13940 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
13944 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
13945 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13946 StackSlot, MachinePointerInfo(),
13948 // For i64 source, we need to add the appropriate power of 2 if the input
13949 // was negative. This is the same as the optimization in
13950 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
13951 // we must be careful to do the computation in x87 extended precision, not
13952 // in SSE. (The generic code can't know it's OK to do this, or how to.)
13953 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
13954 MachineMemOperand *MMO =
13955 DAG.getMachineFunction()
13956 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13957 MachineMemOperand::MOLoad, 8, 8);
13959 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
13960 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
13961 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
13964 APInt FF(32, 0x5F800000ULL);
13966 // Check whether the sign bit is set.
13967 SDValue SignSet = DAG.getSetCC(dl,
13968 getSetCCResultType(*DAG.getContext(), MVT::i64),
13969 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
13972 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
13973 SDValue FudgePtr = DAG.getConstantPool(
13974 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
13977 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
13978 SDValue Zero = DAG.getIntPtrConstant(0);
13979 SDValue Four = DAG.getIntPtrConstant(4);
13980 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
13982 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
13984 // Load the value out, extending it from f32 to f80.
13985 // FIXME: Avoid the extend by constructing the right constant pool?
13986 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
13987 FudgePtr, MachinePointerInfo::getConstantPool(),
13988 MVT::f32, false, false, false, 4);
13989 // Extend everything to 80 bits to force it to be done on x87.
13990 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
13991 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
13994 std::pair<SDValue,SDValue>
13995 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
13996 bool IsSigned, bool IsReplace) const {
13999 EVT DstTy = Op.getValueType();
14001 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
14002 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
14006 assert(DstTy.getSimpleVT() <= MVT::i64 &&
14007 DstTy.getSimpleVT() >= MVT::i16 &&
14008 "Unknown FP_TO_INT to lower!");
14010 // These are really Legal.
14011 if (DstTy == MVT::i32 &&
14012 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
14013 return std::make_pair(SDValue(), SDValue());
14014 if (Subtarget->is64Bit() &&
14015 DstTy == MVT::i64 &&
14016 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
14017 return std::make_pair(SDValue(), SDValue());
14019 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
14020 // stack slot, or into the FTOL runtime function.
14021 MachineFunction &MF = DAG.getMachineFunction();
14022 unsigned MemSize = DstTy.getSizeInBits()/8;
14023 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
14024 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
14027 if (!IsSigned && isIntegerTypeFTOL(DstTy))
14028 Opc = X86ISD::WIN_FTOL;
14030 switch (DstTy.getSimpleVT().SimpleTy) {
14031 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
14032 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
14033 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
14034 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
14037 SDValue Chain = DAG.getEntryNode();
14038 SDValue Value = Op.getOperand(0);
14039 EVT TheVT = Op.getOperand(0).getValueType();
14040 // FIXME This causes a redundant load/store if the SSE-class value is already
14041 // in memory, such as if it is on the callstack.
14042 if (isScalarFPTypeInSSEReg(TheVT)) {
14043 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
14044 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
14045 MachinePointerInfo::getFixedStack(SSFI),
14047 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
14049 Chain, StackSlot, DAG.getValueType(TheVT)
14052 MachineMemOperand *MMO =
14053 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
14054 MachineMemOperand::MOLoad, MemSize, MemSize);
14055 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
14056 Chain = Value.getValue(1);
14057 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
14058 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
14061 MachineMemOperand *MMO =
14062 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
14063 MachineMemOperand::MOStore, MemSize, MemSize);
14065 if (Opc != X86ISD::WIN_FTOL) {
14066 // Build the FP_TO_INT*_IN_MEM
14067 SDValue Ops[] = { Chain, Value, StackSlot };
14068 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
14070 return std::make_pair(FIST, StackSlot);
14072 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
14073 DAG.getVTList(MVT::Other, MVT::Glue),
14075 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
14076 MVT::i32, ftol.getValue(1));
14077 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
14078 MVT::i32, eax.getValue(2));
14079 SDValue Ops[] = { eax, edx };
14080 SDValue pair = IsReplace
14081 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
14082 : DAG.getMergeValues(Ops, DL);
14083 return std::make_pair(pair, SDValue());
14087 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
14088 const X86Subtarget *Subtarget) {
14089 MVT VT = Op->getSimpleValueType(0);
14090 SDValue In = Op->getOperand(0);
14091 MVT InVT = In.getSimpleValueType();
14094 // Optimize vectors in AVX mode:
14097 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
14098 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
14099 // Concat upper and lower parts.
14102 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
14103 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
14104 // Concat upper and lower parts.
14107 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
14108 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
14109 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
14112 if (Subtarget->hasInt256())
14113 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
14115 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
14116 SDValue Undef = DAG.getUNDEF(InVT);
14117 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
14118 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
14119 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
14121 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
14122 VT.getVectorNumElements()/2);
14124 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
14125 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
14127 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14130 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
14131 SelectionDAG &DAG) {
14132 MVT VT = Op->getSimpleValueType(0);
14133 SDValue In = Op->getOperand(0);
14134 MVT InVT = In.getSimpleValueType();
14136 unsigned int NumElts = VT.getVectorNumElements();
14137 if (NumElts != 8 && NumElts != 16)
14140 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
14141 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
14143 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
14144 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14145 // Now we have only mask extension
14146 assert(InVT.getVectorElementType() == MVT::i1);
14147 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
14148 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
14149 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
14150 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
14151 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
14152 MachinePointerInfo::getConstantPool(),
14153 false, false, false, Alignment);
14155 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
14156 if (VT.is512BitVector())
14158 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
14161 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
14162 SelectionDAG &DAG) {
14163 if (Subtarget->hasFp256()) {
14164 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
14172 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
14173 SelectionDAG &DAG) {
14175 MVT VT = Op.getSimpleValueType();
14176 SDValue In = Op.getOperand(0);
14177 MVT SVT = In.getSimpleValueType();
14179 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
14180 return LowerZERO_EXTEND_AVX512(Op, DAG);
14182 if (Subtarget->hasFp256()) {
14183 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
14188 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
14189 VT.getVectorNumElements() != SVT.getVectorNumElements());
14193 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
14195 MVT VT = Op.getSimpleValueType();
14196 SDValue In = Op.getOperand(0);
14197 MVT InVT = In.getSimpleValueType();
14199 if (VT == MVT::i1) {
14200 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
14201 "Invalid scalar TRUNCATE operation");
14202 if (InVT.getSizeInBits() >= 32)
14204 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
14205 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
14207 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
14208 "Invalid TRUNCATE operation");
14210 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
14211 if (VT.getVectorElementType().getSizeInBits() >=8)
14212 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
14214 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
14215 unsigned NumElts = InVT.getVectorNumElements();
14216 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
14217 if (InVT.getSizeInBits() < 512) {
14218 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
14219 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
14223 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
14224 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
14225 SDValue CP = DAG.getConstantPool(C, getPointerTy());
14226 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
14227 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
14228 MachinePointerInfo::getConstantPool(),
14229 false, false, false, Alignment);
14230 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
14231 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
14232 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
14235 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
14236 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
14237 if (Subtarget->hasInt256()) {
14238 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
14239 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
14240 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
14242 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
14243 DAG.getIntPtrConstant(0));
14246 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
14247 DAG.getIntPtrConstant(0));
14248 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
14249 DAG.getIntPtrConstant(2));
14250 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
14251 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
14252 static const int ShufMask[] = {0, 2, 4, 6};
14253 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
14256 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
14257 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
14258 if (Subtarget->hasInt256()) {
14259 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
14261 SmallVector<SDValue,32> pshufbMask;
14262 for (unsigned i = 0; i < 2; ++i) {
14263 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
14264 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
14265 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
14266 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
14267 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
14268 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
14269 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
14270 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
14271 for (unsigned j = 0; j < 8; ++j)
14272 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
14274 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
14275 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
14276 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
14278 static const int ShufMask[] = {0, 2, -1, -1};
14279 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
14281 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
14282 DAG.getIntPtrConstant(0));
14283 return DAG.getNode(ISD::BITCAST, DL, VT, In);
14286 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
14287 DAG.getIntPtrConstant(0));
14289 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
14290 DAG.getIntPtrConstant(4));
14292 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
14293 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
14295 // The PSHUFB mask:
14296 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
14297 -1, -1, -1, -1, -1, -1, -1, -1};
14299 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
14300 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
14301 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
14303 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
14304 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
14306 // The MOVLHPS Mask:
14307 static const int ShufMask2[] = {0, 1, 4, 5};
14308 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
14309 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
14312 // Handle truncation of V256 to V128 using shuffles.
14313 if (!VT.is128BitVector() || !InVT.is256BitVector())
14316 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
14318 unsigned NumElems = VT.getVectorNumElements();
14319 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
14321 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
14322 // Prepare truncation shuffle mask
14323 for (unsigned i = 0; i != NumElems; ++i)
14324 MaskVec[i] = i * 2;
14325 SDValue V = DAG.getVectorShuffle(NVT, DL,
14326 DAG.getNode(ISD::BITCAST, DL, NVT, In),
14327 DAG.getUNDEF(NVT), &MaskVec[0]);
14328 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
14329 DAG.getIntPtrConstant(0));
14332 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
14333 SelectionDAG &DAG) const {
14334 assert(!Op.getSimpleValueType().isVector());
14336 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
14337 /*IsSigned=*/ true, /*IsReplace=*/ false);
14338 SDValue FIST = Vals.first, StackSlot = Vals.second;
14339 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
14340 if (!FIST.getNode()) return Op;
14342 if (StackSlot.getNode())
14343 // Load the result.
14344 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
14345 FIST, StackSlot, MachinePointerInfo(),
14346 false, false, false, 0);
14348 // The node is the result.
14352 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
14353 SelectionDAG &DAG) const {
14354 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
14355 /*IsSigned=*/ false, /*IsReplace=*/ false);
14356 SDValue FIST = Vals.first, StackSlot = Vals.second;
14357 assert(FIST.getNode() && "Unexpected failure");
14359 if (StackSlot.getNode())
14360 // Load the result.
14361 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
14362 FIST, StackSlot, MachinePointerInfo(),
14363 false, false, false, 0);
14365 // The node is the result.
14369 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
14371 MVT VT = Op.getSimpleValueType();
14372 SDValue In = Op.getOperand(0);
14373 MVT SVT = In.getSimpleValueType();
14375 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
14377 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
14378 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
14379 In, DAG.getUNDEF(SVT)));
14382 /// The only differences between FABS and FNEG are the mask and the logic op.
14383 /// FNEG also has a folding opportunity for FNEG(FABS(x)).
14384 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
14385 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
14386 "Wrong opcode for lowering FABS or FNEG.");
14388 bool IsFABS = (Op.getOpcode() == ISD::FABS);
14390 // If this is a FABS and it has an FNEG user, bail out to fold the combination
14391 // into an FNABS. We'll lower the FABS after that if it is still in use.
14393 for (SDNode *User : Op->uses())
14394 if (User->getOpcode() == ISD::FNEG)
14397 SDValue Op0 = Op.getOperand(0);
14398 bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);
14401 MVT VT = Op.getSimpleValueType();
14402 // Assume scalar op for initialization; update for vector if needed.
14403 // Note that there are no scalar bitwise logical SSE/AVX instructions, so we
14404 // generate a 16-byte vector constant and logic op even for the scalar case.
14405 // Using a 16-byte mask allows folding the load of the mask with
14406 // the logic op, so it can save (~4 bytes) on code size.
14408 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
14409 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
14410 // decide if we should generate a 16-byte constant mask when we only need 4 or
14411 // 8 bytes for the scalar case.
14412 if (VT.isVector()) {
14413 EltVT = VT.getVectorElementType();
14414 NumElts = VT.getVectorNumElements();
14417 unsigned EltBits = EltVT.getSizeInBits();
14418 LLVMContext *Context = DAG.getContext();
14419 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
14421 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
14422 Constant *C = ConstantInt::get(*Context, MaskElt);
14423 C = ConstantVector::getSplat(NumElts, C);
14424 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14425 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
14426 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
14427 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
14428 MachinePointerInfo::getConstantPool(),
14429 false, false, false, Alignment);
14431 if (VT.isVector()) {
14432 // For a vector, cast operands to a vector type, perform the logic op,
14433 // and cast the result back to the original value type.
14434 MVT VecVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
14435 SDValue MaskCasted = DAG.getNode(ISD::BITCAST, dl, VecVT, Mask);
14436 SDValue Operand = IsFNABS ?
14437 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0.getOperand(0)) :
14438 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0);
14439 unsigned BitOp = IsFABS ? ISD::AND : IsFNABS ? ISD::OR : ISD::XOR;
14440 return DAG.getNode(ISD::BITCAST, dl, VT,
14441 DAG.getNode(BitOp, dl, VecVT, Operand, MaskCasted));
14444 // If not vector, then scalar.
14445 unsigned BitOp = IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR;
14446 SDValue Operand = IsFNABS ? Op0.getOperand(0) : Op0;
14447 return DAG.getNode(BitOp, dl, VT, Operand, Mask);
14450 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
14451 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14452 LLVMContext *Context = DAG.getContext();
14453 SDValue Op0 = Op.getOperand(0);
14454 SDValue Op1 = Op.getOperand(1);
14456 MVT VT = Op.getSimpleValueType();
14457 MVT SrcVT = Op1.getSimpleValueType();
14459 // If second operand is smaller, extend it first.
14460 if (SrcVT.bitsLT(VT)) {
14461 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
14464 // And if it is bigger, shrink it first.
14465 if (SrcVT.bitsGT(VT)) {
14466 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
14470 // At this point the operands and the result should have the same
14471 // type, and that won't be f80 since that is not custom lowered.
14473 const fltSemantics &Sem =
14474 VT == MVT::f64 ? APFloat::IEEEdouble : APFloat::IEEEsingle;
14475 const unsigned SizeInBits = VT.getSizeInBits();
14477 SmallVector<Constant *, 4> CV(
14478 VT == MVT::f64 ? 2 : 4,
14479 ConstantFP::get(*Context, APFloat(Sem, APInt(SizeInBits, 0))));
14481 // First, clear all bits but the sign bit from the second operand (sign).
14482 CV[0] = ConstantFP::get(*Context,
14483 APFloat(Sem, APInt::getHighBitsSet(SizeInBits, 1)));
14484 Constant *C = ConstantVector::get(CV);
14485 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
14486 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
14487 MachinePointerInfo::getConstantPool(),
14488 false, false, false, 16);
14489 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
14491 // Next, clear the sign bit from the first operand (magnitude).
14492 CV[0] = ConstantFP::get(
14493 *Context, APFloat(Sem, APInt::getLowBitsSet(SizeInBits, SizeInBits - 1)));
14494 C = ConstantVector::get(CV);
14495 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
14496 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
14497 MachinePointerInfo::getConstantPool(),
14498 false, false, false, 16);
14499 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
14501 // OR the magnitude value with the sign bit.
14502 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
14505 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
14506 SDValue N0 = Op.getOperand(0);
14508 MVT VT = Op.getSimpleValueType();
14510 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
14511 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
14512 DAG.getConstant(1, VT));
14513 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
14516 // Check whether an OR'd tree is PTEST-able.
14517 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
14518 SelectionDAG &DAG) {
14519 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
14521 if (!Subtarget->hasSSE41())
14524 if (!Op->hasOneUse())
14527 SDNode *N = Op.getNode();
14530 SmallVector<SDValue, 8> Opnds;
14531 DenseMap<SDValue, unsigned> VecInMap;
14532 SmallVector<SDValue, 8> VecIns;
14533 EVT VT = MVT::Other;
14535 // Recognize a special case where a vector is casted into wide integer to
14537 Opnds.push_back(N->getOperand(0));
14538 Opnds.push_back(N->getOperand(1));
14540 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
14541 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
14542 // BFS traverse all OR'd operands.
14543 if (I->getOpcode() == ISD::OR) {
14544 Opnds.push_back(I->getOperand(0));
14545 Opnds.push_back(I->getOperand(1));
14546 // Re-evaluate the number of nodes to be traversed.
14547 e += 2; // 2 more nodes (LHS and RHS) are pushed.
14551 // Quit if a non-EXTRACT_VECTOR_ELT
14552 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
14555 // Quit if without a constant index.
14556 SDValue Idx = I->getOperand(1);
14557 if (!isa<ConstantSDNode>(Idx))
14560 SDValue ExtractedFromVec = I->getOperand(0);
14561 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
14562 if (M == VecInMap.end()) {
14563 VT = ExtractedFromVec.getValueType();
14564 // Quit if not 128/256-bit vector.
14565 if (!VT.is128BitVector() && !VT.is256BitVector())
14567 // Quit if not the same type.
14568 if (VecInMap.begin() != VecInMap.end() &&
14569 VT != VecInMap.begin()->first.getValueType())
14571 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
14572 VecIns.push_back(ExtractedFromVec);
14574 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
14577 assert((VT.is128BitVector() || VT.is256BitVector()) &&
14578 "Not extracted from 128-/256-bit vector.");
14580 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
14582 for (DenseMap<SDValue, unsigned>::const_iterator
14583 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
14584 // Quit if not all elements are used.
14585 if (I->second != FullMask)
14589 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
14591 // Cast all vectors into TestVT for PTEST.
14592 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
14593 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
14595 // If more than one full vectors are evaluated, OR them first before PTEST.
14596 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
14597 // Each iteration will OR 2 nodes and append the result until there is only
14598 // 1 node left, i.e. the final OR'd value of all vectors.
14599 SDValue LHS = VecIns[Slot];
14600 SDValue RHS = VecIns[Slot + 1];
14601 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
14604 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
14605 VecIns.back(), VecIns.back());
14608 /// \brief return true if \c Op has a use that doesn't just read flags.
14609 static bool hasNonFlagsUse(SDValue Op) {
14610 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
14612 SDNode *User = *UI;
14613 unsigned UOpNo = UI.getOperandNo();
14614 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
14615 // Look pass truncate.
14616 UOpNo = User->use_begin().getOperandNo();
14617 User = *User->use_begin();
14620 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
14621 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
14627 /// Emit nodes that will be selected as "test Op0,Op0", or something
14629 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
14630 SelectionDAG &DAG) const {
14631 if (Op.getValueType() == MVT::i1)
14632 // KORTEST instruction should be selected
14633 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14634 DAG.getConstant(0, Op.getValueType()));
14636 // CF and OF aren't always set the way we want. Determine which
14637 // of these we need.
14638 bool NeedCF = false;
14639 bool NeedOF = false;
14642 case X86::COND_A: case X86::COND_AE:
14643 case X86::COND_B: case X86::COND_BE:
14646 case X86::COND_G: case X86::COND_GE:
14647 case X86::COND_L: case X86::COND_LE:
14648 case X86::COND_O: case X86::COND_NO: {
14649 // Check if we really need to set the
14650 // Overflow flag. If NoSignedWrap is present
14651 // that is not actually needed.
14652 switch (Op->getOpcode()) {
14657 const BinaryWithFlagsSDNode *BinNode =
14658 cast<BinaryWithFlagsSDNode>(Op.getNode());
14659 if (BinNode->hasNoSignedWrap())
14669 // See if we can use the EFLAGS value from the operand instead of
14670 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
14671 // we prove that the arithmetic won't overflow, we can't use OF or CF.
14672 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
14673 // Emit a CMP with 0, which is the TEST pattern.
14674 //if (Op.getValueType() == MVT::i1)
14675 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
14676 // DAG.getConstant(0, MVT::i1));
14677 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14678 DAG.getConstant(0, Op.getValueType()));
14680 unsigned Opcode = 0;
14681 unsigned NumOperands = 0;
14683 // Truncate operations may prevent the merge of the SETCC instruction
14684 // and the arithmetic instruction before it. Attempt to truncate the operands
14685 // of the arithmetic instruction and use a reduced bit-width instruction.
14686 bool NeedTruncation = false;
14687 SDValue ArithOp = Op;
14688 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
14689 SDValue Arith = Op->getOperand(0);
14690 // Both the trunc and the arithmetic op need to have one user each.
14691 if (Arith->hasOneUse())
14692 switch (Arith.getOpcode()) {
14699 NeedTruncation = true;
14705 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
14706 // which may be the result of a CAST. We use the variable 'Op', which is the
14707 // non-casted variable when we check for possible users.
14708 switch (ArithOp.getOpcode()) {
14710 // Due to an isel shortcoming, be conservative if this add is likely to be
14711 // selected as part of a load-modify-store instruction. When the root node
14712 // in a match is a store, isel doesn't know how to remap non-chain non-flag
14713 // uses of other nodes in the match, such as the ADD in this case. This
14714 // leads to the ADD being left around and reselected, with the result being
14715 // two adds in the output. Alas, even if none our users are stores, that
14716 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
14717 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
14718 // climbing the DAG back to the root, and it doesn't seem to be worth the
14720 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14721 UE = Op.getNode()->use_end(); UI != UE; ++UI)
14722 if (UI->getOpcode() != ISD::CopyToReg &&
14723 UI->getOpcode() != ISD::SETCC &&
14724 UI->getOpcode() != ISD::STORE)
14727 if (ConstantSDNode *C =
14728 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
14729 // An add of one will be selected as an INC.
14730 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
14731 Opcode = X86ISD::INC;
14736 // An add of negative one (subtract of one) will be selected as a DEC.
14737 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
14738 Opcode = X86ISD::DEC;
14744 // Otherwise use a regular EFLAGS-setting add.
14745 Opcode = X86ISD::ADD;
14750 // If we have a constant logical shift that's only used in a comparison
14751 // against zero turn it into an equivalent AND. This allows turning it into
14752 // a TEST instruction later.
14753 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
14754 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
14755 EVT VT = Op.getValueType();
14756 unsigned BitWidth = VT.getSizeInBits();
14757 unsigned ShAmt = Op->getConstantOperandVal(1);
14758 if (ShAmt >= BitWidth) // Avoid undefined shifts.
14760 APInt Mask = ArithOp.getOpcode() == ISD::SRL
14761 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
14762 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
14763 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
14765 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
14766 DAG.getConstant(Mask, VT));
14767 DAG.ReplaceAllUsesWith(Op, New);
14773 // If the primary and result isn't used, don't bother using X86ISD::AND,
14774 // because a TEST instruction will be better.
14775 if (!hasNonFlagsUse(Op))
14781 // Due to the ISEL shortcoming noted above, be conservative if this op is
14782 // likely to be selected as part of a load-modify-store instruction.
14783 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14784 UE = Op.getNode()->use_end(); UI != UE; ++UI)
14785 if (UI->getOpcode() == ISD::STORE)
14788 // Otherwise use a regular EFLAGS-setting instruction.
14789 switch (ArithOp.getOpcode()) {
14790 default: llvm_unreachable("unexpected operator!");
14791 case ISD::SUB: Opcode = X86ISD::SUB; break;
14792 case ISD::XOR: Opcode = X86ISD::XOR; break;
14793 case ISD::AND: Opcode = X86ISD::AND; break;
14795 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
14796 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
14797 if (EFLAGS.getNode())
14800 Opcode = X86ISD::OR;
14814 return SDValue(Op.getNode(), 1);
14820 // If we found that truncation is beneficial, perform the truncation and
14822 if (NeedTruncation) {
14823 EVT VT = Op.getValueType();
14824 SDValue WideVal = Op->getOperand(0);
14825 EVT WideVT = WideVal.getValueType();
14826 unsigned ConvertedOp = 0;
14827 // Use a target machine opcode to prevent further DAGCombine
14828 // optimizations that may separate the arithmetic operations
14829 // from the setcc node.
14830 switch (WideVal.getOpcode()) {
14832 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
14833 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
14834 case ISD::AND: ConvertedOp = X86ISD::AND; break;
14835 case ISD::OR: ConvertedOp = X86ISD::OR; break;
14836 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
14840 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14841 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
14842 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
14843 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
14844 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
14850 // Emit a CMP with 0, which is the TEST pattern.
14851 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14852 DAG.getConstant(0, Op.getValueType()));
14854 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
14855 SmallVector<SDValue, 4> Ops;
14856 for (unsigned i = 0; i != NumOperands; ++i)
14857 Ops.push_back(Op.getOperand(i));
14859 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
14860 DAG.ReplaceAllUsesWith(Op, New);
14861 return SDValue(New.getNode(), 1);
14864 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
14866 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
14867 SDLoc dl, SelectionDAG &DAG) const {
14868 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
14869 if (C->getAPIntValue() == 0)
14870 return EmitTest(Op0, X86CC, dl, DAG);
14872 if (Op0.getValueType() == MVT::i1)
14873 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
14876 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
14877 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
14878 // Do the comparison at i32 if it's smaller, besides the Atom case.
14879 // This avoids subregister aliasing issues. Keep the smaller reference
14880 // if we're optimizing for size, however, as that'll allow better folding
14881 // of memory operations.
14882 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
14883 !DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
14884 AttributeSet::FunctionIndex, Attribute::MinSize) &&
14885 !Subtarget->isAtom()) {
14886 unsigned ExtendOp =
14887 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
14888 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
14889 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
14891 // Use SUB instead of CMP to enable CSE between SUB and CMP.
14892 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
14893 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
14895 return SDValue(Sub.getNode(), 1);
14897 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
14900 /// Convert a comparison if required by the subtarget.
14901 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
14902 SelectionDAG &DAG) const {
14903 // If the subtarget does not support the FUCOMI instruction, floating-point
14904 // comparisons have to be converted.
14905 if (Subtarget->hasCMov() ||
14906 Cmp.getOpcode() != X86ISD::CMP ||
14907 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
14908 !Cmp.getOperand(1).getValueType().isFloatingPoint())
14911 // The instruction selector will select an FUCOM instruction instead of
14912 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
14913 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
14914 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
14916 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
14917 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
14918 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
14919 DAG.getConstant(8, MVT::i8));
14920 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
14921 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
14924 /// The minimum architected relative accuracy is 2^-12. We need one
14925 /// Newton-Raphson step to have a good float result (24 bits of precision).
14926 SDValue X86TargetLowering::getRsqrtEstimate(SDValue Op,
14927 DAGCombinerInfo &DCI,
14928 unsigned &RefinementSteps,
14929 bool &UseOneConstNR) const {
14930 // FIXME: We should use instruction latency models to calculate the cost of
14931 // each potential sequence, but this is very hard to do reliably because
14932 // at least Intel's Core* chips have variable timing based on the number of
14933 // significant digits in the divisor and/or sqrt operand.
14934 if (!Subtarget->useSqrtEst())
14937 EVT VT = Op.getValueType();
14939 // SSE1 has rsqrtss and rsqrtps.
14940 // TODO: Add support for AVX512 (v16f32).
14941 // It is likely not profitable to do this for f64 because a double-precision
14942 // rsqrt estimate with refinement on x86 prior to FMA requires at least 16
14943 // instructions: convert to single, rsqrtss, convert back to double, refine
14944 // (3 steps = at least 13 insts). If an 'rsqrtsd' variant was added to the ISA
14945 // along with FMA, this could be a throughput win.
14946 if ((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
14947 (Subtarget->hasAVX() && VT == MVT::v8f32)) {
14948 RefinementSteps = 1;
14949 UseOneConstNR = false;
14950 return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op);
14955 /// The minimum architected relative accuracy is 2^-12. We need one
14956 /// Newton-Raphson step to have a good float result (24 bits of precision).
14957 SDValue X86TargetLowering::getRecipEstimate(SDValue Op,
14958 DAGCombinerInfo &DCI,
14959 unsigned &RefinementSteps) const {
14960 // FIXME: We should use instruction latency models to calculate the cost of
14961 // each potential sequence, but this is very hard to do reliably because
14962 // at least Intel's Core* chips have variable timing based on the number of
14963 // significant digits in the divisor.
14964 if (!Subtarget->useReciprocalEst())
14967 EVT VT = Op.getValueType();
14969 // SSE1 has rcpss and rcpps. AVX adds a 256-bit variant for rcpps.
14970 // TODO: Add support for AVX512 (v16f32).
14971 // It is likely not profitable to do this for f64 because a double-precision
14972 // reciprocal estimate with refinement on x86 prior to FMA requires
14973 // 15 instructions: convert to single, rcpss, convert back to double, refine
14974 // (3 steps = 12 insts). If an 'rcpsd' variant was added to the ISA
14975 // along with FMA, this could be a throughput win.
14976 if ((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
14977 (Subtarget->hasAVX() && VT == MVT::v8f32)) {
14978 RefinementSteps = ReciprocalEstimateRefinementSteps;
14979 return DCI.DAG.getNode(X86ISD::FRCP, SDLoc(Op), VT, Op);
14984 static bool isAllOnes(SDValue V) {
14985 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
14986 return C && C->isAllOnesValue();
14989 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
14990 /// if it's possible.
14991 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
14992 SDLoc dl, SelectionDAG &DAG) const {
14993 SDValue Op0 = And.getOperand(0);
14994 SDValue Op1 = And.getOperand(1);
14995 if (Op0.getOpcode() == ISD::TRUNCATE)
14996 Op0 = Op0.getOperand(0);
14997 if (Op1.getOpcode() == ISD::TRUNCATE)
14998 Op1 = Op1.getOperand(0);
15001 if (Op1.getOpcode() == ISD::SHL)
15002 std::swap(Op0, Op1);
15003 if (Op0.getOpcode() == ISD::SHL) {
15004 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
15005 if (And00C->getZExtValue() == 1) {
15006 // If we looked past a truncate, check that it's only truncating away
15008 unsigned BitWidth = Op0.getValueSizeInBits();
15009 unsigned AndBitWidth = And.getValueSizeInBits();
15010 if (BitWidth > AndBitWidth) {
15012 DAG.computeKnownBits(Op0, Zeros, Ones);
15013 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
15017 RHS = Op0.getOperand(1);
15019 } else if (Op1.getOpcode() == ISD::Constant) {
15020 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
15021 uint64_t AndRHSVal = AndRHS->getZExtValue();
15022 SDValue AndLHS = Op0;
15024 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
15025 LHS = AndLHS.getOperand(0);
15026 RHS = AndLHS.getOperand(1);
15029 // Use BT if the immediate can't be encoded in a TEST instruction.
15030 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
15032 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
15036 if (LHS.getNode()) {
15037 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
15038 // instruction. Since the shift amount is in-range-or-undefined, we know
15039 // that doing a bittest on the i32 value is ok. We extend to i32 because
15040 // the encoding for the i16 version is larger than the i32 version.
15041 // Also promote i16 to i32 for performance / code size reason.
15042 if (LHS.getValueType() == MVT::i8 ||
15043 LHS.getValueType() == MVT::i16)
15044 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
15046 // If the operand types disagree, extend the shift amount to match. Since
15047 // BT ignores high bits (like shifts) we can use anyextend.
15048 if (LHS.getValueType() != RHS.getValueType())
15049 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
15051 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
15052 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
15053 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15054 DAG.getConstant(Cond, MVT::i8), BT);
15060 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
15062 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
15067 // SSE Condition code mapping:
15076 switch (SetCCOpcode) {
15077 default: llvm_unreachable("Unexpected SETCC condition");
15079 case ISD::SETEQ: SSECC = 0; break;
15081 case ISD::SETGT: Swap = true; // Fallthrough
15083 case ISD::SETOLT: SSECC = 1; break;
15085 case ISD::SETGE: Swap = true; // Fallthrough
15087 case ISD::SETOLE: SSECC = 2; break;
15088 case ISD::SETUO: SSECC = 3; break;
15090 case ISD::SETNE: SSECC = 4; break;
15091 case ISD::SETULE: Swap = true; // Fallthrough
15092 case ISD::SETUGE: SSECC = 5; break;
15093 case ISD::SETULT: Swap = true; // Fallthrough
15094 case ISD::SETUGT: SSECC = 6; break;
15095 case ISD::SETO: SSECC = 7; break;
15097 case ISD::SETONE: SSECC = 8; break;
15100 std::swap(Op0, Op1);
15105 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
15106 // ones, and then concatenate the result back.
15107 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
15108 MVT VT = Op.getSimpleValueType();
15110 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
15111 "Unsupported value type for operation");
15113 unsigned NumElems = VT.getVectorNumElements();
15115 SDValue CC = Op.getOperand(2);
15117 // Extract the LHS vectors
15118 SDValue LHS = Op.getOperand(0);
15119 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
15120 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
15122 // Extract the RHS vectors
15123 SDValue RHS = Op.getOperand(1);
15124 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
15125 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
15127 // Issue the operation on the smaller types and concatenate the result back
15128 MVT EltVT = VT.getVectorElementType();
15129 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
15130 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
15131 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
15132 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
15135 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
15136 const X86Subtarget *Subtarget) {
15137 SDValue Op0 = Op.getOperand(0);
15138 SDValue Op1 = Op.getOperand(1);
15139 SDValue CC = Op.getOperand(2);
15140 MVT VT = Op.getSimpleValueType();
15143 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
15144 Op.getValueType().getScalarType() == MVT::i1 &&
15145 "Cannot set masked compare for this operation");
15147 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
15149 bool Unsigned = false;
15152 switch (SetCCOpcode) {
15153 default: llvm_unreachable("Unexpected SETCC condition");
15154 case ISD::SETNE: SSECC = 4; break;
15155 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
15156 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
15157 case ISD::SETLT: Swap = true; //fall-through
15158 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
15159 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
15160 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
15161 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
15162 case ISD::SETULE: Unsigned = true; //fall-through
15163 case ISD::SETLE: SSECC = 2; break;
15167 std::swap(Op0, Op1);
15169 return DAG.getNode(Opc, dl, VT, Op0, Op1);
15170 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
15171 return DAG.getNode(Opc, dl, VT, Op0, Op1,
15172 DAG.getConstant(SSECC, MVT::i8));
15175 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
15176 /// operand \p Op1. If non-trivial (for example because it's not constant)
15177 /// return an empty value.
15178 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
15180 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
15184 MVT VT = Op1.getSimpleValueType();
15185 MVT EVT = VT.getVectorElementType();
15186 unsigned n = VT.getVectorNumElements();
15187 SmallVector<SDValue, 8> ULTOp1;
15189 for (unsigned i = 0; i < n; ++i) {
15190 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
15191 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
15194 // Avoid underflow.
15195 APInt Val = Elt->getAPIntValue();
15199 ULTOp1.push_back(DAG.getConstant(Val - 1, EVT));
15202 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
15205 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
15206 SelectionDAG &DAG) {
15207 SDValue Op0 = Op.getOperand(0);
15208 SDValue Op1 = Op.getOperand(1);
15209 SDValue CC = Op.getOperand(2);
15210 MVT VT = Op.getSimpleValueType();
15211 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
15212 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
15217 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
15218 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
15221 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
15222 unsigned Opc = X86ISD::CMPP;
15223 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
15224 assert(VT.getVectorNumElements() <= 16);
15225 Opc = X86ISD::CMPM;
15227 // In the two special cases we can't handle, emit two comparisons.
15230 unsigned CombineOpc;
15231 if (SetCCOpcode == ISD::SETUEQ) {
15232 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
15234 assert(SetCCOpcode == ISD::SETONE);
15235 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
15238 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
15239 DAG.getConstant(CC0, MVT::i8));
15240 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
15241 DAG.getConstant(CC1, MVT::i8));
15242 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
15244 // Handle all other FP comparisons here.
15245 return DAG.getNode(Opc, dl, VT, Op0, Op1,
15246 DAG.getConstant(SSECC, MVT::i8));
15249 // Break 256-bit integer vector compare into smaller ones.
15250 if (VT.is256BitVector() && !Subtarget->hasInt256())
15251 return Lower256IntVSETCC(Op, DAG);
15253 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
15254 EVT OpVT = Op1.getValueType();
15255 if (Subtarget->hasAVX512()) {
15256 if (Op1.getValueType().is512BitVector() ||
15257 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
15258 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
15259 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
15261 // In AVX-512 architecture setcc returns mask with i1 elements,
15262 // But there is no compare instruction for i8 and i16 elements in KNL.
15263 // We are not talking about 512-bit operands in this case, these
15264 // types are illegal.
15266 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
15267 OpVT.getVectorElementType().getSizeInBits() >= 8))
15268 return DAG.getNode(ISD::TRUNCATE, dl, VT,
15269 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
15272 // We are handling one of the integer comparisons here. Since SSE only has
15273 // GT and EQ comparisons for integer, swapping operands and multiple
15274 // operations may be required for some comparisons.
15276 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
15277 bool Subus = false;
15279 switch (SetCCOpcode) {
15280 default: llvm_unreachable("Unexpected SETCC condition");
15281 case ISD::SETNE: Invert = true;
15282 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
15283 case ISD::SETLT: Swap = true;
15284 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
15285 case ISD::SETGE: Swap = true;
15286 case ISD::SETLE: Opc = X86ISD::PCMPGT;
15287 Invert = true; break;
15288 case ISD::SETULT: Swap = true;
15289 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
15290 FlipSigns = true; break;
15291 case ISD::SETUGE: Swap = true;
15292 case ISD::SETULE: Opc = X86ISD::PCMPGT;
15293 FlipSigns = true; Invert = true; break;
15296 // Special case: Use min/max operations for SETULE/SETUGE
15297 MVT VET = VT.getVectorElementType();
15299 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
15300 || (Subtarget->hasSSE2() && (VET == MVT::i8));
15303 switch (SetCCOpcode) {
15305 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
15306 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
15309 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
15312 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
15313 if (!MinMax && hasSubus) {
15314 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
15316 // t = psubus Op0, Op1
15317 // pcmpeq t, <0..0>
15318 switch (SetCCOpcode) {
15320 case ISD::SETULT: {
15321 // If the comparison is against a constant we can turn this into a
15322 // setule. With psubus, setule does not require a swap. This is
15323 // beneficial because the constant in the register is no longer
15324 // destructed as the destination so it can be hoisted out of a loop.
15325 // Only do this pre-AVX since vpcmp* is no longer destructive.
15326 if (Subtarget->hasAVX())
15328 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
15329 if (ULEOp1.getNode()) {
15331 Subus = true; Invert = false; Swap = false;
15335 // Psubus is better than flip-sign because it requires no inversion.
15336 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
15337 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
15341 Opc = X86ISD::SUBUS;
15347 std::swap(Op0, Op1);
15349 // Check that the operation in question is available (most are plain SSE2,
15350 // but PCMPGTQ and PCMPEQQ have different requirements).
15351 if (VT == MVT::v2i64) {
15352 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
15353 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
15355 // First cast everything to the right type.
15356 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
15357 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
15359 // Since SSE has no unsigned integer comparisons, we need to flip the sign
15360 // bits of the inputs before performing those operations. The lower
15361 // compare is always unsigned.
15364 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
15366 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
15367 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
15368 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
15369 Sign, Zero, Sign, Zero);
15371 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
15372 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
15374 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
15375 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
15376 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
15378 // Create masks for only the low parts/high parts of the 64 bit integers.
15379 static const int MaskHi[] = { 1, 1, 3, 3 };
15380 static const int MaskLo[] = { 0, 0, 2, 2 };
15381 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
15382 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
15383 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
15385 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
15386 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
15389 Result = DAG.getNOT(dl, Result, MVT::v4i32);
15391 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
15394 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
15395 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
15396 // pcmpeqd + pshufd + pand.
15397 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
15399 // First cast everything to the right type.
15400 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
15401 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
15404 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
15406 // Make sure the lower and upper halves are both all-ones.
15407 static const int Mask[] = { 1, 0, 3, 2 };
15408 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
15409 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
15412 Result = DAG.getNOT(dl, Result, MVT::v4i32);
15414 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
15418 // Since SSE has no unsigned integer comparisons, we need to flip the sign
15419 // bits of the inputs before performing those operations.
15421 EVT EltVT = VT.getVectorElementType();
15422 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
15423 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
15424 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
15427 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
15429 // If the logical-not of the result is required, perform that now.
15431 Result = DAG.getNOT(dl, Result, VT);
15434 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
15437 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
15438 getZeroVector(VT, Subtarget, DAG, dl));
15443 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
15445 MVT VT = Op.getSimpleValueType();
15447 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
15449 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
15450 && "SetCC type must be 8-bit or 1-bit integer");
15451 SDValue Op0 = Op.getOperand(0);
15452 SDValue Op1 = Op.getOperand(1);
15454 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
15456 // Optimize to BT if possible.
15457 // Lower (X & (1 << N)) == 0 to BT(X, N).
15458 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
15459 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
15460 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
15461 Op1.getOpcode() == ISD::Constant &&
15462 cast<ConstantSDNode>(Op1)->isNullValue() &&
15463 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15464 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
15465 if (NewSetCC.getNode()) {
15467 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewSetCC);
15472 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
15474 if (Op1.getOpcode() == ISD::Constant &&
15475 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
15476 cast<ConstantSDNode>(Op1)->isNullValue()) &&
15477 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15479 // If the input is a setcc, then reuse the input setcc or use a new one with
15480 // the inverted condition.
15481 if (Op0.getOpcode() == X86ISD::SETCC) {
15482 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
15483 bool Invert = (CC == ISD::SETNE) ^
15484 cast<ConstantSDNode>(Op1)->isNullValue();
15488 CCode = X86::GetOppositeBranchCondition(CCode);
15489 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15490 DAG.getConstant(CCode, MVT::i8),
15491 Op0.getOperand(1));
15493 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
15497 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
15498 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
15499 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15501 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
15502 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, MVT::i1), NewCC);
15505 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
15506 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
15507 if (X86CC == X86::COND_INVALID)
15510 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
15511 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
15512 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15513 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
15515 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
15519 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
15520 static bool isX86LogicalCmp(SDValue Op) {
15521 unsigned Opc = Op.getNode()->getOpcode();
15522 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
15523 Opc == X86ISD::SAHF)
15525 if (Op.getResNo() == 1 &&
15526 (Opc == X86ISD::ADD ||
15527 Opc == X86ISD::SUB ||
15528 Opc == X86ISD::ADC ||
15529 Opc == X86ISD::SBB ||
15530 Opc == X86ISD::SMUL ||
15531 Opc == X86ISD::UMUL ||
15532 Opc == X86ISD::INC ||
15533 Opc == X86ISD::DEC ||
15534 Opc == X86ISD::OR ||
15535 Opc == X86ISD::XOR ||
15536 Opc == X86ISD::AND))
15539 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
15545 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
15546 if (V.getOpcode() != ISD::TRUNCATE)
15549 SDValue VOp0 = V.getOperand(0);
15550 unsigned InBits = VOp0.getValueSizeInBits();
15551 unsigned Bits = V.getValueSizeInBits();
15552 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
15555 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
15556 bool addTest = true;
15557 SDValue Cond = Op.getOperand(0);
15558 SDValue Op1 = Op.getOperand(1);
15559 SDValue Op2 = Op.getOperand(2);
15561 EVT VT = Op1.getValueType();
15564 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
15565 // are available. Otherwise fp cmovs get lowered into a less efficient branch
15566 // sequence later on.
15567 if (Cond.getOpcode() == ISD::SETCC &&
15568 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
15569 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
15570 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
15571 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
15572 int SSECC = translateX86FSETCC(
15573 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
15576 if (Subtarget->hasAVX512()) {
15577 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
15578 DAG.getConstant(SSECC, MVT::i8));
15579 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
15581 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
15582 DAG.getConstant(SSECC, MVT::i8));
15583 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
15584 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
15585 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
15589 if (Cond.getOpcode() == ISD::SETCC) {
15590 SDValue NewCond = LowerSETCC(Cond, DAG);
15591 if (NewCond.getNode())
15595 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
15596 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
15597 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
15598 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
15599 if (Cond.getOpcode() == X86ISD::SETCC &&
15600 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
15601 isZero(Cond.getOperand(1).getOperand(1))) {
15602 SDValue Cmp = Cond.getOperand(1);
15604 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
15606 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
15607 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
15608 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
15610 SDValue CmpOp0 = Cmp.getOperand(0);
15611 // Apply further optimizations for special cases
15612 // (select (x != 0), -1, 0) -> neg & sbb
15613 // (select (x == 0), 0, -1) -> neg & sbb
15614 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
15615 if (YC->isNullValue() &&
15616 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
15617 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
15618 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
15619 DAG.getConstant(0, CmpOp0.getValueType()),
15621 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15622 DAG.getConstant(X86::COND_B, MVT::i8),
15623 SDValue(Neg.getNode(), 1));
15627 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
15628 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
15629 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15631 SDValue Res = // Res = 0 or -1.
15632 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15633 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
15635 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
15636 Res = DAG.getNOT(DL, Res, Res.getValueType());
15638 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
15639 if (!N2C || !N2C->isNullValue())
15640 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
15645 // Look past (and (setcc_carry (cmp ...)), 1).
15646 if (Cond.getOpcode() == ISD::AND &&
15647 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
15648 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
15649 if (C && C->getAPIntValue() == 1)
15650 Cond = Cond.getOperand(0);
15653 // If condition flag is set by a X86ISD::CMP, then use it as the condition
15654 // setting operand in place of the X86ISD::SETCC.
15655 unsigned CondOpcode = Cond.getOpcode();
15656 if (CondOpcode == X86ISD::SETCC ||
15657 CondOpcode == X86ISD::SETCC_CARRY) {
15658 CC = Cond.getOperand(0);
15660 SDValue Cmp = Cond.getOperand(1);
15661 unsigned Opc = Cmp.getOpcode();
15662 MVT VT = Op.getSimpleValueType();
15664 bool IllegalFPCMov = false;
15665 if (VT.isFloatingPoint() && !VT.isVector() &&
15666 !isScalarFPTypeInSSEReg(VT)) // FPStack?
15667 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
15669 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
15670 Opc == X86ISD::BT) { // FIXME
15674 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
15675 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
15676 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
15677 Cond.getOperand(0).getValueType() != MVT::i8)) {
15678 SDValue LHS = Cond.getOperand(0);
15679 SDValue RHS = Cond.getOperand(1);
15680 unsigned X86Opcode;
15683 switch (CondOpcode) {
15684 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
15685 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
15686 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
15687 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
15688 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
15689 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
15690 default: llvm_unreachable("unexpected overflowing operator");
15692 if (CondOpcode == ISD::UMULO)
15693 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
15696 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
15698 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
15700 if (CondOpcode == ISD::UMULO)
15701 Cond = X86Op.getValue(2);
15703 Cond = X86Op.getValue(1);
15705 CC = DAG.getConstant(X86Cond, MVT::i8);
15710 // Look pass the truncate if the high bits are known zero.
15711 if (isTruncWithZeroHighBitsInput(Cond, DAG))
15712 Cond = Cond.getOperand(0);
15714 // We know the result of AND is compared against zero. Try to match
15716 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
15717 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
15718 if (NewSetCC.getNode()) {
15719 CC = NewSetCC.getOperand(0);
15720 Cond = NewSetCC.getOperand(1);
15727 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
15728 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
15731 // a < b ? -1 : 0 -> RES = ~setcc_carry
15732 // a < b ? 0 : -1 -> RES = setcc_carry
15733 // a >= b ? -1 : 0 -> RES = setcc_carry
15734 // a >= b ? 0 : -1 -> RES = ~setcc_carry
15735 if (Cond.getOpcode() == X86ISD::SUB) {
15736 Cond = ConvertCmpIfNecessary(Cond, DAG);
15737 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
15739 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
15740 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
15741 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15742 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
15743 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
15744 return DAG.getNOT(DL, Res, Res.getValueType());
15749 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
15750 // widen the cmov and push the truncate through. This avoids introducing a new
15751 // branch during isel and doesn't add any extensions.
15752 if (Op.getValueType() == MVT::i8 &&
15753 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
15754 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
15755 if (T1.getValueType() == T2.getValueType() &&
15756 // Blacklist CopyFromReg to avoid partial register stalls.
15757 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
15758 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
15759 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
15760 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
15764 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
15765 // condition is true.
15766 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
15767 SDValue Ops[] = { Op2, Op1, CC, Cond };
15768 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
15771 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, const X86Subtarget *Subtarget,
15772 SelectionDAG &DAG) {
15773 MVT VT = Op->getSimpleValueType(0);
15774 SDValue In = Op->getOperand(0);
15775 MVT InVT = In.getSimpleValueType();
15776 MVT VTElt = VT.getVectorElementType();
15777 MVT InVTElt = InVT.getVectorElementType();
15781 if ((InVTElt == MVT::i1) &&
15782 (((Subtarget->hasBWI() && Subtarget->hasVLX() &&
15783 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() <= 16)) ||
15785 ((Subtarget->hasBWI() && VT.is512BitVector() &&
15786 VTElt.getSizeInBits() <= 16)) ||
15788 ((Subtarget->hasDQI() && Subtarget->hasVLX() &&
15789 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() >= 32)) ||
15791 ((Subtarget->hasDQI() && VT.is512BitVector() &&
15792 VTElt.getSizeInBits() >= 32))))
15793 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15795 unsigned int NumElts = VT.getVectorNumElements();
15797 if (NumElts != 8 && NumElts != 16)
15800 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1) {
15801 if (In.getOpcode() == X86ISD::VSEXT || In.getOpcode() == X86ISD::VZEXT)
15802 return DAG.getNode(In.getOpcode(), dl, VT, In.getOperand(0));
15803 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15806 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15807 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
15809 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
15810 Constant *C = ConstantInt::get(*DAG.getContext(),
15811 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
15813 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
15814 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
15815 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
15816 MachinePointerInfo::getConstantPool(),
15817 false, false, false, Alignment);
15818 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
15819 if (VT.is512BitVector())
15821 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
15824 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
15825 SelectionDAG &DAG) {
15826 MVT VT = Op->getSimpleValueType(0);
15827 SDValue In = Op->getOperand(0);
15828 MVT InVT = In.getSimpleValueType();
15831 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
15832 return LowerSIGN_EXTEND_AVX512(Op, Subtarget, DAG);
15834 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
15835 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
15836 (VT != MVT::v16i16 || InVT != MVT::v16i8))
15839 if (Subtarget->hasInt256())
15840 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15842 // Optimize vectors in AVX mode
15843 // Sign extend v8i16 to v8i32 and
15846 // Divide input vector into two parts
15847 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
15848 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
15849 // concat the vectors to original VT
15851 unsigned NumElems = InVT.getVectorNumElements();
15852 SDValue Undef = DAG.getUNDEF(InVT);
15854 SmallVector<int,8> ShufMask1(NumElems, -1);
15855 for (unsigned i = 0; i != NumElems/2; ++i)
15858 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
15860 SmallVector<int,8> ShufMask2(NumElems, -1);
15861 for (unsigned i = 0; i != NumElems/2; ++i)
15862 ShufMask2[i] = i + NumElems/2;
15864 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
15866 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
15867 VT.getVectorNumElements()/2);
15869 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
15870 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
15872 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
15875 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
15876 // may emit an illegal shuffle but the expansion is still better than scalar
15877 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
15878 // we'll emit a shuffle and a arithmetic shift.
15879 // TODO: It is possible to support ZExt by zeroing the undef values during
15880 // the shuffle phase or after the shuffle.
15881 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
15882 SelectionDAG &DAG) {
15883 MVT RegVT = Op.getSimpleValueType();
15884 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
15885 assert(RegVT.isInteger() &&
15886 "We only custom lower integer vector sext loads.");
15888 // Nothing useful we can do without SSE2 shuffles.
15889 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
15891 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
15893 EVT MemVT = Ld->getMemoryVT();
15894 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15895 unsigned RegSz = RegVT.getSizeInBits();
15897 ISD::LoadExtType Ext = Ld->getExtensionType();
15899 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
15900 && "Only anyext and sext are currently implemented.");
15901 assert(MemVT != RegVT && "Cannot extend to the same type");
15902 assert(MemVT.isVector() && "Must load a vector from memory");
15904 unsigned NumElems = RegVT.getVectorNumElements();
15905 unsigned MemSz = MemVT.getSizeInBits();
15906 assert(RegSz > MemSz && "Register size must be greater than the mem size");
15908 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
15909 // The only way in which we have a legal 256-bit vector result but not the
15910 // integer 256-bit operations needed to directly lower a sextload is if we
15911 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
15912 // a 128-bit vector and a normal sign_extend to 256-bits that should get
15913 // correctly legalized. We do this late to allow the canonical form of
15914 // sextload to persist throughout the rest of the DAG combiner -- it wants
15915 // to fold together any extensions it can, and so will fuse a sign_extend
15916 // of an sextload into a sextload targeting a wider value.
15918 if (MemSz == 128) {
15919 // Just switch this to a normal load.
15920 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
15921 "it must be a legal 128-bit vector "
15923 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
15924 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
15925 Ld->isInvariant(), Ld->getAlignment());
15927 assert(MemSz < 128 &&
15928 "Can't extend a type wider than 128 bits to a 256 bit vector!");
15929 // Do an sext load to a 128-bit vector type. We want to use the same
15930 // number of elements, but elements half as wide. This will end up being
15931 // recursively lowered by this routine, but will succeed as we definitely
15932 // have all the necessary features if we're using AVX1.
15934 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
15935 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
15937 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
15938 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
15939 Ld->isNonTemporal(), Ld->isInvariant(),
15940 Ld->getAlignment());
15943 // Replace chain users with the new chain.
15944 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
15945 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
15947 // Finally, do a normal sign-extend to the desired register.
15948 return DAG.getSExtOrTrunc(Load, dl, RegVT);
15951 // All sizes must be a power of two.
15952 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
15953 "Non-power-of-two elements are not custom lowered!");
15955 // Attempt to load the original value using scalar loads.
15956 // Find the largest scalar type that divides the total loaded size.
15957 MVT SclrLoadTy = MVT::i8;
15958 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
15959 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
15960 MVT Tp = (MVT::SimpleValueType)tp;
15961 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
15966 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
15967 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
15969 SclrLoadTy = MVT::f64;
15971 // Calculate the number of scalar loads that we need to perform
15972 // in order to load our vector from memory.
15973 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
15975 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
15976 "Can only lower sext loads with a single scalar load!");
15978 unsigned loadRegZize = RegSz;
15979 if (Ext == ISD::SEXTLOAD && RegSz == 256)
15982 // Represent our vector as a sequence of elements which are the
15983 // largest scalar that we can load.
15984 EVT LoadUnitVecVT = EVT::getVectorVT(
15985 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
15987 // Represent the data using the same element type that is stored in
15988 // memory. In practice, we ''widen'' MemVT.
15990 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
15991 loadRegZize / MemVT.getScalarType().getSizeInBits());
15993 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
15994 "Invalid vector type");
15996 // We can't shuffle using an illegal type.
15997 assert(TLI.isTypeLegal(WideVecVT) &&
15998 "We only lower types that form legal widened vector types");
16000 SmallVector<SDValue, 8> Chains;
16001 SDValue Ptr = Ld->getBasePtr();
16002 SDValue Increment =
16003 DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, TLI.getPointerTy());
16004 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
16006 for (unsigned i = 0; i < NumLoads; ++i) {
16007 // Perform a single load.
16008 SDValue ScalarLoad =
16009 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
16010 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
16011 Ld->getAlignment());
16012 Chains.push_back(ScalarLoad.getValue(1));
16013 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
16014 // another round of DAGCombining.
16016 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
16018 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
16019 ScalarLoad, DAG.getIntPtrConstant(i));
16021 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
16024 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
16026 // Bitcast the loaded value to a vector of the original element type, in
16027 // the size of the target vector type.
16028 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
16029 unsigned SizeRatio = RegSz / MemSz;
16031 if (Ext == ISD::SEXTLOAD) {
16032 // If we have SSE4.1, we can directly emit a VSEXT node.
16033 if (Subtarget->hasSSE41()) {
16034 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
16035 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
16039 // Otherwise we'll shuffle the small elements in the high bits of the
16040 // larger type and perform an arithmetic shift. If the shift is not legal
16041 // it's better to scalarize.
16042 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
16043 "We can't implement a sext load without an arithmetic right shift!");
16045 // Redistribute the loaded elements into the different locations.
16046 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
16047 for (unsigned i = 0; i != NumElems; ++i)
16048 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
16050 SDValue Shuff = DAG.getVectorShuffle(
16051 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
16053 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
16055 // Build the arithmetic shift.
16056 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
16057 MemVT.getVectorElementType().getSizeInBits();
16059 DAG.getNode(ISD::SRA, dl, RegVT, Shuff, DAG.getConstant(Amt, RegVT));
16061 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
16065 // Redistribute the loaded elements into the different locations.
16066 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
16067 for (unsigned i = 0; i != NumElems; ++i)
16068 ShuffleVec[i * SizeRatio] = i;
16070 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
16071 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
16073 // Bitcast to the requested type.
16074 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
16075 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
16079 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
16080 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
16081 // from the AND / OR.
16082 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
16083 Opc = Op.getOpcode();
16084 if (Opc != ISD::OR && Opc != ISD::AND)
16086 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
16087 Op.getOperand(0).hasOneUse() &&
16088 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
16089 Op.getOperand(1).hasOneUse());
16092 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
16093 // 1 and that the SETCC node has a single use.
16094 static bool isXor1OfSetCC(SDValue Op) {
16095 if (Op.getOpcode() != ISD::XOR)
16097 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
16098 if (N1C && N1C->getAPIntValue() == 1) {
16099 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
16100 Op.getOperand(0).hasOneUse();
16105 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
16106 bool addTest = true;
16107 SDValue Chain = Op.getOperand(0);
16108 SDValue Cond = Op.getOperand(1);
16109 SDValue Dest = Op.getOperand(2);
16112 bool Inverted = false;
16114 if (Cond.getOpcode() == ISD::SETCC) {
16115 // Check for setcc([su]{add,sub,mul}o == 0).
16116 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
16117 isa<ConstantSDNode>(Cond.getOperand(1)) &&
16118 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
16119 Cond.getOperand(0).getResNo() == 1 &&
16120 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
16121 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
16122 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
16123 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
16124 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
16125 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
16127 Cond = Cond.getOperand(0);
16129 SDValue NewCond = LowerSETCC(Cond, DAG);
16130 if (NewCond.getNode())
16135 // FIXME: LowerXALUO doesn't handle these!!
16136 else if (Cond.getOpcode() == X86ISD::ADD ||
16137 Cond.getOpcode() == X86ISD::SUB ||
16138 Cond.getOpcode() == X86ISD::SMUL ||
16139 Cond.getOpcode() == X86ISD::UMUL)
16140 Cond = LowerXALUO(Cond, DAG);
16143 // Look pass (and (setcc_carry (cmp ...)), 1).
16144 if (Cond.getOpcode() == ISD::AND &&
16145 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
16146 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
16147 if (C && C->getAPIntValue() == 1)
16148 Cond = Cond.getOperand(0);
16151 // If condition flag is set by a X86ISD::CMP, then use it as the condition
16152 // setting operand in place of the X86ISD::SETCC.
16153 unsigned CondOpcode = Cond.getOpcode();
16154 if (CondOpcode == X86ISD::SETCC ||
16155 CondOpcode == X86ISD::SETCC_CARRY) {
16156 CC = Cond.getOperand(0);
16158 SDValue Cmp = Cond.getOperand(1);
16159 unsigned Opc = Cmp.getOpcode();
16160 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
16161 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
16165 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
16169 // These can only come from an arithmetic instruction with overflow,
16170 // e.g. SADDO, UADDO.
16171 Cond = Cond.getNode()->getOperand(1);
16177 CondOpcode = Cond.getOpcode();
16178 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
16179 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
16180 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
16181 Cond.getOperand(0).getValueType() != MVT::i8)) {
16182 SDValue LHS = Cond.getOperand(0);
16183 SDValue RHS = Cond.getOperand(1);
16184 unsigned X86Opcode;
16187 // Keep this in sync with LowerXALUO, otherwise we might create redundant
16188 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
16190 switch (CondOpcode) {
16191 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
16193 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
16195 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
16198 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
16199 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
16201 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
16203 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
16206 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
16207 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
16208 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
16209 default: llvm_unreachable("unexpected overflowing operator");
16212 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
16213 if (CondOpcode == ISD::UMULO)
16214 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
16217 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
16219 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
16221 if (CondOpcode == ISD::UMULO)
16222 Cond = X86Op.getValue(2);
16224 Cond = X86Op.getValue(1);
16226 CC = DAG.getConstant(X86Cond, MVT::i8);
16230 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
16231 SDValue Cmp = Cond.getOperand(0).getOperand(1);
16232 if (CondOpc == ISD::OR) {
16233 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
16234 // two branches instead of an explicit OR instruction with a
16236 if (Cmp == Cond.getOperand(1).getOperand(1) &&
16237 isX86LogicalCmp(Cmp)) {
16238 CC = Cond.getOperand(0).getOperand(0);
16239 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16240 Chain, Dest, CC, Cmp);
16241 CC = Cond.getOperand(1).getOperand(0);
16245 } else { // ISD::AND
16246 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
16247 // two branches instead of an explicit AND instruction with a
16248 // separate test. However, we only do this if this block doesn't
16249 // have a fall-through edge, because this requires an explicit
16250 // jmp when the condition is false.
16251 if (Cmp == Cond.getOperand(1).getOperand(1) &&
16252 isX86LogicalCmp(Cmp) &&
16253 Op.getNode()->hasOneUse()) {
16254 X86::CondCode CCode =
16255 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
16256 CCode = X86::GetOppositeBranchCondition(CCode);
16257 CC = DAG.getConstant(CCode, MVT::i8);
16258 SDNode *User = *Op.getNode()->use_begin();
16259 // Look for an unconditional branch following this conditional branch.
16260 // We need this because we need to reverse the successors in order
16261 // to implement FCMP_OEQ.
16262 if (User->getOpcode() == ISD::BR) {
16263 SDValue FalseBB = User->getOperand(1);
16265 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
16266 assert(NewBR == User);
16270 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16271 Chain, Dest, CC, Cmp);
16272 X86::CondCode CCode =
16273 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
16274 CCode = X86::GetOppositeBranchCondition(CCode);
16275 CC = DAG.getConstant(CCode, MVT::i8);
16281 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
16282 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
16283 // It should be transformed during dag combiner except when the condition
16284 // is set by a arithmetics with overflow node.
16285 X86::CondCode CCode =
16286 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
16287 CCode = X86::GetOppositeBranchCondition(CCode);
16288 CC = DAG.getConstant(CCode, MVT::i8);
16289 Cond = Cond.getOperand(0).getOperand(1);
16291 } else if (Cond.getOpcode() == ISD::SETCC &&
16292 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
16293 // For FCMP_OEQ, we can emit
16294 // two branches instead of an explicit AND instruction with a
16295 // separate test. However, we only do this if this block doesn't
16296 // have a fall-through edge, because this requires an explicit
16297 // jmp when the condition is false.
16298 if (Op.getNode()->hasOneUse()) {
16299 SDNode *User = *Op.getNode()->use_begin();
16300 // Look for an unconditional branch following this conditional branch.
16301 // We need this because we need to reverse the successors in order
16302 // to implement FCMP_OEQ.
16303 if (User->getOpcode() == ISD::BR) {
16304 SDValue FalseBB = User->getOperand(1);
16306 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
16307 assert(NewBR == User);
16311 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
16312 Cond.getOperand(0), Cond.getOperand(1));
16313 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
16314 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
16315 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16316 Chain, Dest, CC, Cmp);
16317 CC = DAG.getConstant(X86::COND_P, MVT::i8);
16322 } else if (Cond.getOpcode() == ISD::SETCC &&
16323 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
16324 // For FCMP_UNE, we can emit
16325 // two branches instead of an explicit AND instruction with a
16326 // separate test. However, we only do this if this block doesn't
16327 // have a fall-through edge, because this requires an explicit
16328 // jmp when the condition is false.
16329 if (Op.getNode()->hasOneUse()) {
16330 SDNode *User = *Op.getNode()->use_begin();
16331 // Look for an unconditional branch following this conditional branch.
16332 // We need this because we need to reverse the successors in order
16333 // to implement FCMP_UNE.
16334 if (User->getOpcode() == ISD::BR) {
16335 SDValue FalseBB = User->getOperand(1);
16337 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
16338 assert(NewBR == User);
16341 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
16342 Cond.getOperand(0), Cond.getOperand(1));
16343 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
16344 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
16345 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16346 Chain, Dest, CC, Cmp);
16347 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
16357 // Look pass the truncate if the high bits are known zero.
16358 if (isTruncWithZeroHighBitsInput(Cond, DAG))
16359 Cond = Cond.getOperand(0);
16361 // We know the result of AND is compared against zero. Try to match
16363 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
16364 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
16365 if (NewSetCC.getNode()) {
16366 CC = NewSetCC.getOperand(0);
16367 Cond = NewSetCC.getOperand(1);
16374 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
16375 CC = DAG.getConstant(X86Cond, MVT::i8);
16376 Cond = EmitTest(Cond, X86Cond, dl, DAG);
16378 Cond = ConvertCmpIfNecessary(Cond, DAG);
16379 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16380 Chain, Dest, CC, Cond);
16383 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
16384 // Calls to _alloca are needed to probe the stack when allocating more than 4k
16385 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
16386 // that the guard pages used by the OS virtual memory manager are allocated in
16387 // correct sequence.
16389 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
16390 SelectionDAG &DAG) const {
16391 MachineFunction &MF = DAG.getMachineFunction();
16392 bool SplitStack = MF.shouldSplitStack();
16393 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMachO()) ||
16398 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16399 SDNode* Node = Op.getNode();
16401 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
16402 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
16403 " not tell us which reg is the stack pointer!");
16404 EVT VT = Node->getValueType(0);
16405 SDValue Tmp1 = SDValue(Node, 0);
16406 SDValue Tmp2 = SDValue(Node, 1);
16407 SDValue Tmp3 = Node->getOperand(2);
16408 SDValue Chain = Tmp1.getOperand(0);
16410 // Chain the dynamic stack allocation so that it doesn't modify the stack
16411 // pointer when other instructions are using the stack.
16412 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
16415 SDValue Size = Tmp2.getOperand(1);
16416 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
16417 Chain = SP.getValue(1);
16418 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
16419 const TargetFrameLowering &TFI = *DAG.getSubtarget().getFrameLowering();
16420 unsigned StackAlign = TFI.getStackAlignment();
16421 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
16422 if (Align > StackAlign)
16423 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
16424 DAG.getConstant(-(uint64_t)Align, VT));
16425 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
16427 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
16428 DAG.getIntPtrConstant(0, true), SDValue(),
16431 SDValue Ops[2] = { Tmp1, Tmp2 };
16432 return DAG.getMergeValues(Ops, dl);
16436 SDValue Chain = Op.getOperand(0);
16437 SDValue Size = Op.getOperand(1);
16438 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
16439 EVT VT = Op.getNode()->getValueType(0);
16441 bool Is64Bit = Subtarget->is64Bit();
16442 EVT SPTy = getPointerTy();
16445 MachineRegisterInfo &MRI = MF.getRegInfo();
16448 // The 64 bit implementation of segmented stacks needs to clobber both r10
16449 // r11. This makes it impossible to use it along with nested parameters.
16450 const Function *F = MF.getFunction();
16452 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
16454 if (I->hasNestAttr())
16455 report_fatal_error("Cannot use segmented stacks with functions that "
16456 "have nested arguments.");
16459 const TargetRegisterClass *AddrRegClass =
16460 getRegClassFor(getPointerTy());
16461 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
16462 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
16463 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
16464 DAG.getRegister(Vreg, SPTy));
16465 SDValue Ops1[2] = { Value, Chain };
16466 return DAG.getMergeValues(Ops1, dl);
16469 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
16471 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
16472 Flag = Chain.getValue(1);
16473 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
16475 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
16477 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16478 DAG.getSubtarget().getRegisterInfo());
16479 unsigned SPReg = RegInfo->getStackRegister();
16480 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
16481 Chain = SP.getValue(1);
16484 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
16485 DAG.getConstant(-(uint64_t)Align, VT));
16486 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
16489 SDValue Ops1[2] = { SP, Chain };
16490 return DAG.getMergeValues(Ops1, dl);
16494 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
16495 MachineFunction &MF = DAG.getMachineFunction();
16496 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
16498 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
16501 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
16502 // vastart just stores the address of the VarArgsFrameIndex slot into the
16503 // memory location argument.
16504 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
16506 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
16507 MachinePointerInfo(SV), false, false, 0);
16511 // gp_offset (0 - 6 * 8)
16512 // fp_offset (48 - 48 + 8 * 16)
16513 // overflow_arg_area (point to parameters coming in memory).
16515 SmallVector<SDValue, 8> MemOps;
16516 SDValue FIN = Op.getOperand(1);
16518 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
16519 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
16521 FIN, MachinePointerInfo(SV), false, false, 0);
16522 MemOps.push_back(Store);
16525 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16526 FIN, DAG.getIntPtrConstant(4));
16527 Store = DAG.getStore(Op.getOperand(0), DL,
16528 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
16530 FIN, MachinePointerInfo(SV, 4), false, false, 0);
16531 MemOps.push_back(Store);
16533 // Store ptr to overflow_arg_area
16534 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16535 FIN, DAG.getIntPtrConstant(4));
16536 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
16538 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
16539 MachinePointerInfo(SV, 8),
16541 MemOps.push_back(Store);
16543 // Store ptr to reg_save_area.
16544 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16545 FIN, DAG.getIntPtrConstant(8));
16546 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
16548 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
16549 MachinePointerInfo(SV, 16), false, false, 0);
16550 MemOps.push_back(Store);
16551 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
16554 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
16555 assert(Subtarget->is64Bit() &&
16556 "LowerVAARG only handles 64-bit va_arg!");
16557 assert((Subtarget->isTargetLinux() ||
16558 Subtarget->isTargetDarwin()) &&
16559 "Unhandled target in LowerVAARG");
16560 assert(Op.getNode()->getNumOperands() == 4);
16561 SDValue Chain = Op.getOperand(0);
16562 SDValue SrcPtr = Op.getOperand(1);
16563 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
16564 unsigned Align = Op.getConstantOperandVal(3);
16567 EVT ArgVT = Op.getNode()->getValueType(0);
16568 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
16569 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
16572 // Decide which area this value should be read from.
16573 // TODO: Implement the AMD64 ABI in its entirety. This simple
16574 // selection mechanism works only for the basic types.
16575 if (ArgVT == MVT::f80) {
16576 llvm_unreachable("va_arg for f80 not yet implemented");
16577 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
16578 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
16579 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
16580 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
16582 llvm_unreachable("Unhandled argument type in LowerVAARG");
16585 if (ArgMode == 2) {
16586 // Sanity Check: Make sure using fp_offset makes sense.
16587 assert(!DAG.getTarget().Options.UseSoftFloat &&
16588 !(DAG.getMachineFunction()
16589 .getFunction()->getAttributes()
16590 .hasAttribute(AttributeSet::FunctionIndex,
16591 Attribute::NoImplicitFloat)) &&
16592 Subtarget->hasSSE1());
16595 // Insert VAARG_64 node into the DAG
16596 // VAARG_64 returns two values: Variable Argument Address, Chain
16597 SmallVector<SDValue, 11> InstOps;
16598 InstOps.push_back(Chain);
16599 InstOps.push_back(SrcPtr);
16600 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
16601 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
16602 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
16603 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
16604 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
16605 VTs, InstOps, MVT::i64,
16606 MachinePointerInfo(SV),
16608 /*Volatile=*/false,
16610 /*WriteMem=*/true);
16611 Chain = VAARG.getValue(1);
16613 // Load the next argument and return it
16614 return DAG.getLoad(ArgVT, dl,
16617 MachinePointerInfo(),
16618 false, false, false, 0);
16621 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
16622 SelectionDAG &DAG) {
16623 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
16624 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
16625 SDValue Chain = Op.getOperand(0);
16626 SDValue DstPtr = Op.getOperand(1);
16627 SDValue SrcPtr = Op.getOperand(2);
16628 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
16629 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
16632 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
16633 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
16635 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
16638 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
16639 // amount is a constant. Takes immediate version of shift as input.
16640 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
16641 SDValue SrcOp, uint64_t ShiftAmt,
16642 SelectionDAG &DAG) {
16643 MVT ElementType = VT.getVectorElementType();
16645 // Fold this packed shift into its first operand if ShiftAmt is 0.
16649 // Check for ShiftAmt >= element width
16650 if (ShiftAmt >= ElementType.getSizeInBits()) {
16651 if (Opc == X86ISD::VSRAI)
16652 ShiftAmt = ElementType.getSizeInBits() - 1;
16654 return DAG.getConstant(0, VT);
16657 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
16658 && "Unknown target vector shift-by-constant node");
16660 // Fold this packed vector shift into a build vector if SrcOp is a
16661 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
16662 if (VT == SrcOp.getSimpleValueType() &&
16663 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
16664 SmallVector<SDValue, 8> Elts;
16665 unsigned NumElts = SrcOp->getNumOperands();
16666 ConstantSDNode *ND;
16669 default: llvm_unreachable(nullptr);
16670 case X86ISD::VSHLI:
16671 for (unsigned i=0; i!=NumElts; ++i) {
16672 SDValue CurrentOp = SrcOp->getOperand(i);
16673 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16674 Elts.push_back(CurrentOp);
16677 ND = cast<ConstantSDNode>(CurrentOp);
16678 const APInt &C = ND->getAPIntValue();
16679 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), ElementType));
16682 case X86ISD::VSRLI:
16683 for (unsigned i=0; i!=NumElts; ++i) {
16684 SDValue CurrentOp = SrcOp->getOperand(i);
16685 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16686 Elts.push_back(CurrentOp);
16689 ND = cast<ConstantSDNode>(CurrentOp);
16690 const APInt &C = ND->getAPIntValue();
16691 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), ElementType));
16694 case X86ISD::VSRAI:
16695 for (unsigned i=0; i!=NumElts; ++i) {
16696 SDValue CurrentOp = SrcOp->getOperand(i);
16697 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16698 Elts.push_back(CurrentOp);
16701 ND = cast<ConstantSDNode>(CurrentOp);
16702 const APInt &C = ND->getAPIntValue();
16703 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), ElementType));
16708 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
16711 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
16714 // getTargetVShiftNode - Handle vector element shifts where the shift amount
16715 // may or may not be a constant. Takes immediate version of shift as input.
16716 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
16717 SDValue SrcOp, SDValue ShAmt,
16718 SelectionDAG &DAG) {
16719 MVT SVT = ShAmt.getSimpleValueType();
16720 assert((SVT == MVT::i32 || SVT == MVT::i64) && "Unexpected value type!");
16722 // Catch shift-by-constant.
16723 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
16724 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
16725 CShAmt->getZExtValue(), DAG);
16727 // Change opcode to non-immediate version
16729 default: llvm_unreachable("Unknown target vector shift node");
16730 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
16731 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
16732 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
16735 const X86Subtarget &Subtarget =
16736 DAG.getTarget().getSubtarget<X86Subtarget>();
16737 if (Subtarget.hasSSE41() && ShAmt.getOpcode() == ISD::ZERO_EXTEND &&
16738 ShAmt.getOperand(0).getSimpleValueType() == MVT::i16) {
16739 // Let the shuffle legalizer expand this shift amount node.
16740 SDValue Op0 = ShAmt.getOperand(0);
16741 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(Op0), MVT::v8i16, Op0);
16742 ShAmt = getShuffleVectorZeroOrUndef(Op0, 0, true, &Subtarget, DAG);
16744 // Need to build a vector containing shift amount.
16745 // SSE/AVX packed shifts only use the lower 64-bit of the shift count.
16746 SmallVector<SDValue, 4> ShOps;
16747 ShOps.push_back(ShAmt);
16748 if (SVT == MVT::i32) {
16749 ShOps.push_back(DAG.getConstant(0, SVT));
16750 ShOps.push_back(DAG.getUNDEF(SVT));
16752 ShOps.push_back(DAG.getUNDEF(SVT));
16754 MVT BVT = SVT == MVT::i32 ? MVT::v4i32 : MVT::v2i64;
16755 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, BVT, ShOps);
16758 // The return type has to be a 128-bit type with the same element
16759 // type as the input type.
16760 MVT EltVT = VT.getVectorElementType();
16761 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
16763 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
16764 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
16767 /// \brief Return (and \p Op, \p Mask) for compare instructions or
16768 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
16769 /// necessary casting for \p Mask when lowering masking intrinsics.
16770 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
16771 SDValue PreservedSrc,
16772 const X86Subtarget *Subtarget,
16773 SelectionDAG &DAG) {
16774 EVT VT = Op.getValueType();
16775 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
16776 MVT::i1, VT.getVectorNumElements());
16777 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16778 Mask.getValueType().getSizeInBits());
16781 assert(MaskVT.isSimple() && "invalid mask type");
16783 if (isAllOnes(Mask))
16786 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16787 // are extracted by EXTRACT_SUBVECTOR.
16788 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16789 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
16790 DAG.getIntPtrConstant(0));
16792 switch (Op.getOpcode()) {
16794 case X86ISD::PCMPEQM:
16795 case X86ISD::PCMPGTM:
16797 case X86ISD::CMPMU:
16798 return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
16800 if (PreservedSrc.getOpcode() == ISD::UNDEF)
16801 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
16802 return DAG.getNode(ISD::VSELECT, dl, VT, VMask, Op, PreservedSrc);
16805 /// \brief Creates an SDNode for a predicated scalar operation.
16806 /// \returns (X86vselect \p Mask, \p Op, \p PreservedSrc).
16807 /// The mask is comming as MVT::i8 and it should be truncated
16808 /// to MVT::i1 while lowering masking intrinsics.
16809 /// The main difference between ScalarMaskingNode and VectorMaskingNode is using
16810 /// "X86select" instead of "vselect". We just can't create the "vselect" node for
16811 /// a scalar instruction.
16812 static SDValue getScalarMaskingNode(SDValue Op, SDValue Mask,
16813 SDValue PreservedSrc,
16814 const X86Subtarget *Subtarget,
16815 SelectionDAG &DAG) {
16816 if (isAllOnes(Mask))
16819 EVT VT = Op.getValueType();
16821 // The mask should be of type MVT::i1
16822 SDValue IMask = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Mask);
16824 if (PreservedSrc.getOpcode() == ISD::UNDEF)
16825 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
16826 return DAG.getNode(X86ISD::SELECT, dl, VT, IMask, Op, PreservedSrc);
16829 static unsigned getOpcodeForFMAIntrinsic(unsigned IntNo) {
16831 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16832 case Intrinsic::x86_fma_vfmadd_ps:
16833 case Intrinsic::x86_fma_vfmadd_pd:
16834 case Intrinsic::x86_fma_vfmadd_ps_256:
16835 case Intrinsic::x86_fma_vfmadd_pd_256:
16836 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
16837 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
16838 return X86ISD::FMADD;
16839 case Intrinsic::x86_fma_vfmsub_ps:
16840 case Intrinsic::x86_fma_vfmsub_pd:
16841 case Intrinsic::x86_fma_vfmsub_ps_256:
16842 case Intrinsic::x86_fma_vfmsub_pd_256:
16843 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
16844 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
16845 return X86ISD::FMSUB;
16846 case Intrinsic::x86_fma_vfnmadd_ps:
16847 case Intrinsic::x86_fma_vfnmadd_pd:
16848 case Intrinsic::x86_fma_vfnmadd_ps_256:
16849 case Intrinsic::x86_fma_vfnmadd_pd_256:
16850 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
16851 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
16852 return X86ISD::FNMADD;
16853 case Intrinsic::x86_fma_vfnmsub_ps:
16854 case Intrinsic::x86_fma_vfnmsub_pd:
16855 case Intrinsic::x86_fma_vfnmsub_ps_256:
16856 case Intrinsic::x86_fma_vfnmsub_pd_256:
16857 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
16858 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
16859 return X86ISD::FNMSUB;
16860 case Intrinsic::x86_fma_vfmaddsub_ps:
16861 case Intrinsic::x86_fma_vfmaddsub_pd:
16862 case Intrinsic::x86_fma_vfmaddsub_ps_256:
16863 case Intrinsic::x86_fma_vfmaddsub_pd_256:
16864 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
16865 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
16866 return X86ISD::FMADDSUB;
16867 case Intrinsic::x86_fma_vfmsubadd_ps:
16868 case Intrinsic::x86_fma_vfmsubadd_pd:
16869 case Intrinsic::x86_fma_vfmsubadd_ps_256:
16870 case Intrinsic::x86_fma_vfmsubadd_pd_256:
16871 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
16872 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512:
16873 return X86ISD::FMSUBADD;
16877 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
16878 SelectionDAG &DAG) {
16880 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16881 EVT VT = Op.getValueType();
16882 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
16884 switch(IntrData->Type) {
16885 case INTR_TYPE_1OP:
16886 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
16887 case INTR_TYPE_2OP:
16888 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16890 case INTR_TYPE_3OP:
16891 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16892 Op.getOperand(2), Op.getOperand(3));
16893 case INTR_TYPE_1OP_MASK_RM: {
16894 SDValue Src = Op.getOperand(1);
16895 SDValue Src0 = Op.getOperand(2);
16896 SDValue Mask = Op.getOperand(3);
16897 SDValue RoundingMode = Op.getOperand(4);
16898 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src,
16900 Mask, Src0, Subtarget, DAG);
16902 case INTR_TYPE_SCALAR_MASK_RM: {
16903 SDValue Src1 = Op.getOperand(1);
16904 SDValue Src2 = Op.getOperand(2);
16905 SDValue Src0 = Op.getOperand(3);
16906 SDValue Mask = Op.getOperand(4);
16907 SDValue RoundingMode = Op.getOperand(5);
16908 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2,
16910 Mask, Src0, Subtarget, DAG);
16912 case INTR_TYPE_2OP_MASK: {
16913 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Op.getOperand(1),
16915 Op.getOperand(4), Op.getOperand(3), Subtarget, DAG);
16918 case CMP_MASK_CC: {
16919 // Comparison intrinsics with masks.
16920 // Example of transformation:
16921 // (i8 (int_x86_avx512_mask_pcmpeq_q_128
16922 // (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
16924 // (v8i1 (insert_subvector undef,
16925 // (v2i1 (and (PCMPEQM %a, %b),
16926 // (extract_subvector
16927 // (v8i1 (bitcast %mask)), 0))), 0))))
16928 EVT VT = Op.getOperand(1).getValueType();
16929 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16930 VT.getVectorNumElements());
16931 SDValue Mask = Op.getOperand((IntrData->Type == CMP_MASK_CC) ? 4 : 3);
16932 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16933 Mask.getValueType().getSizeInBits());
16935 if (IntrData->Type == CMP_MASK_CC) {
16936 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16937 Op.getOperand(2), Op.getOperand(3));
16939 assert(IntrData->Type == CMP_MASK && "Unexpected intrinsic type!");
16940 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16943 SDValue CmpMask = getVectorMaskingNode(Cmp, Mask,
16944 DAG.getTargetConstant(0, MaskVT),
16946 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16947 DAG.getUNDEF(BitcastVT), CmpMask,
16948 DAG.getIntPtrConstant(0));
16949 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
16951 case COMI: { // Comparison intrinsics
16952 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
16953 SDValue LHS = Op.getOperand(1);
16954 SDValue RHS = Op.getOperand(2);
16955 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
16956 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
16957 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
16958 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16959 DAG.getConstant(X86CC, MVT::i8), Cond);
16960 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16963 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
16964 Op.getOperand(1), Op.getOperand(2), DAG);
16966 return getVectorMaskingNode(getTargetVShiftNode(IntrData->Opc0, dl,
16967 Op.getSimpleValueType(),
16969 Op.getOperand(2), DAG),
16970 Op.getOperand(4), Op.getOperand(3), Subtarget,
16972 case COMPRESS_EXPAND_IN_REG: {
16973 SDValue Mask = Op.getOperand(3);
16974 SDValue DataToCompress = Op.getOperand(1);
16975 SDValue PassThru = Op.getOperand(2);
16976 if (isAllOnes(Mask)) // return data as is
16977 return Op.getOperand(1);
16978 EVT VT = Op.getValueType();
16979 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16980 VT.getVectorNumElements());
16981 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16982 Mask.getValueType().getSizeInBits());
16984 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16985 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
16986 DAG.getIntPtrConstant(0));
16988 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, DataToCompress,
16997 default: return SDValue(); // Don't custom lower most intrinsics.
16999 case Intrinsic::x86_avx512_mask_valign_q_512:
17000 case Intrinsic::x86_avx512_mask_valign_d_512:
17001 // Vector source operands are swapped.
17002 return getVectorMaskingNode(DAG.getNode(X86ISD::VALIGN, dl,
17003 Op.getValueType(), Op.getOperand(2),
17006 Op.getOperand(5), Op.getOperand(4),
17009 // ptest and testp intrinsics. The intrinsic these come from are designed to
17010 // return an integer value, not just an instruction so lower it to the ptest
17011 // or testp pattern and a setcc for the result.
17012 case Intrinsic::x86_sse41_ptestz:
17013 case Intrinsic::x86_sse41_ptestc:
17014 case Intrinsic::x86_sse41_ptestnzc:
17015 case Intrinsic::x86_avx_ptestz_256:
17016 case Intrinsic::x86_avx_ptestc_256:
17017 case Intrinsic::x86_avx_ptestnzc_256:
17018 case Intrinsic::x86_avx_vtestz_ps:
17019 case Intrinsic::x86_avx_vtestc_ps:
17020 case Intrinsic::x86_avx_vtestnzc_ps:
17021 case Intrinsic::x86_avx_vtestz_pd:
17022 case Intrinsic::x86_avx_vtestc_pd:
17023 case Intrinsic::x86_avx_vtestnzc_pd:
17024 case Intrinsic::x86_avx_vtestz_ps_256:
17025 case Intrinsic::x86_avx_vtestc_ps_256:
17026 case Intrinsic::x86_avx_vtestnzc_ps_256:
17027 case Intrinsic::x86_avx_vtestz_pd_256:
17028 case Intrinsic::x86_avx_vtestc_pd_256:
17029 case Intrinsic::x86_avx_vtestnzc_pd_256: {
17030 bool IsTestPacked = false;
17033 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
17034 case Intrinsic::x86_avx_vtestz_ps:
17035 case Intrinsic::x86_avx_vtestz_pd:
17036 case Intrinsic::x86_avx_vtestz_ps_256:
17037 case Intrinsic::x86_avx_vtestz_pd_256:
17038 IsTestPacked = true; // Fallthrough
17039 case Intrinsic::x86_sse41_ptestz:
17040 case Intrinsic::x86_avx_ptestz_256:
17042 X86CC = X86::COND_E;
17044 case Intrinsic::x86_avx_vtestc_ps:
17045 case Intrinsic::x86_avx_vtestc_pd:
17046 case Intrinsic::x86_avx_vtestc_ps_256:
17047 case Intrinsic::x86_avx_vtestc_pd_256:
17048 IsTestPacked = true; // Fallthrough
17049 case Intrinsic::x86_sse41_ptestc:
17050 case Intrinsic::x86_avx_ptestc_256:
17052 X86CC = X86::COND_B;
17054 case Intrinsic::x86_avx_vtestnzc_ps:
17055 case Intrinsic::x86_avx_vtestnzc_pd:
17056 case Intrinsic::x86_avx_vtestnzc_ps_256:
17057 case Intrinsic::x86_avx_vtestnzc_pd_256:
17058 IsTestPacked = true; // Fallthrough
17059 case Intrinsic::x86_sse41_ptestnzc:
17060 case Intrinsic::x86_avx_ptestnzc_256:
17062 X86CC = X86::COND_A;
17066 SDValue LHS = Op.getOperand(1);
17067 SDValue RHS = Op.getOperand(2);
17068 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
17069 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
17070 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
17071 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
17072 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
17074 case Intrinsic::x86_avx512_kortestz_w:
17075 case Intrinsic::x86_avx512_kortestc_w: {
17076 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
17077 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
17078 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
17079 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
17080 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
17081 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
17082 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
17085 case Intrinsic::x86_sse42_pcmpistria128:
17086 case Intrinsic::x86_sse42_pcmpestria128:
17087 case Intrinsic::x86_sse42_pcmpistric128:
17088 case Intrinsic::x86_sse42_pcmpestric128:
17089 case Intrinsic::x86_sse42_pcmpistrio128:
17090 case Intrinsic::x86_sse42_pcmpestrio128:
17091 case Intrinsic::x86_sse42_pcmpistris128:
17092 case Intrinsic::x86_sse42_pcmpestris128:
17093 case Intrinsic::x86_sse42_pcmpistriz128:
17094 case Intrinsic::x86_sse42_pcmpestriz128: {
17098 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
17099 case Intrinsic::x86_sse42_pcmpistria128:
17100 Opcode = X86ISD::PCMPISTRI;
17101 X86CC = X86::COND_A;
17103 case Intrinsic::x86_sse42_pcmpestria128:
17104 Opcode = X86ISD::PCMPESTRI;
17105 X86CC = X86::COND_A;
17107 case Intrinsic::x86_sse42_pcmpistric128:
17108 Opcode = X86ISD::PCMPISTRI;
17109 X86CC = X86::COND_B;
17111 case Intrinsic::x86_sse42_pcmpestric128:
17112 Opcode = X86ISD::PCMPESTRI;
17113 X86CC = X86::COND_B;
17115 case Intrinsic::x86_sse42_pcmpistrio128:
17116 Opcode = X86ISD::PCMPISTRI;
17117 X86CC = X86::COND_O;
17119 case Intrinsic::x86_sse42_pcmpestrio128:
17120 Opcode = X86ISD::PCMPESTRI;
17121 X86CC = X86::COND_O;
17123 case Intrinsic::x86_sse42_pcmpistris128:
17124 Opcode = X86ISD::PCMPISTRI;
17125 X86CC = X86::COND_S;
17127 case Intrinsic::x86_sse42_pcmpestris128:
17128 Opcode = X86ISD::PCMPESTRI;
17129 X86CC = X86::COND_S;
17131 case Intrinsic::x86_sse42_pcmpistriz128:
17132 Opcode = X86ISD::PCMPISTRI;
17133 X86CC = X86::COND_E;
17135 case Intrinsic::x86_sse42_pcmpestriz128:
17136 Opcode = X86ISD::PCMPESTRI;
17137 X86CC = X86::COND_E;
17140 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
17141 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
17142 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
17143 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17144 DAG.getConstant(X86CC, MVT::i8),
17145 SDValue(PCMP.getNode(), 1));
17146 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
17149 case Intrinsic::x86_sse42_pcmpistri128:
17150 case Intrinsic::x86_sse42_pcmpestri128: {
17152 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
17153 Opcode = X86ISD::PCMPISTRI;
17155 Opcode = X86ISD::PCMPESTRI;
17157 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
17158 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
17159 return DAG.getNode(Opcode, dl, VTs, NewOps);
17162 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
17163 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
17164 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
17165 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
17166 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
17167 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
17168 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
17169 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
17170 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
17171 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
17172 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
17173 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512: {
17174 auto *SAE = cast<ConstantSDNode>(Op.getOperand(5));
17175 if (SAE->getZExtValue() == X86::STATIC_ROUNDING::CUR_DIRECTION)
17176 return getVectorMaskingNode(DAG.getNode(getOpcodeForFMAIntrinsic(IntNo),
17177 dl, Op.getValueType(),
17181 Op.getOperand(4), Op.getOperand(1),
17187 case Intrinsic::x86_fma_vfmadd_ps:
17188 case Intrinsic::x86_fma_vfmadd_pd:
17189 case Intrinsic::x86_fma_vfmsub_ps:
17190 case Intrinsic::x86_fma_vfmsub_pd:
17191 case Intrinsic::x86_fma_vfnmadd_ps:
17192 case Intrinsic::x86_fma_vfnmadd_pd:
17193 case Intrinsic::x86_fma_vfnmsub_ps:
17194 case Intrinsic::x86_fma_vfnmsub_pd:
17195 case Intrinsic::x86_fma_vfmaddsub_ps:
17196 case Intrinsic::x86_fma_vfmaddsub_pd:
17197 case Intrinsic::x86_fma_vfmsubadd_ps:
17198 case Intrinsic::x86_fma_vfmsubadd_pd:
17199 case Intrinsic::x86_fma_vfmadd_ps_256:
17200 case Intrinsic::x86_fma_vfmadd_pd_256:
17201 case Intrinsic::x86_fma_vfmsub_ps_256:
17202 case Intrinsic::x86_fma_vfmsub_pd_256:
17203 case Intrinsic::x86_fma_vfnmadd_ps_256:
17204 case Intrinsic::x86_fma_vfnmadd_pd_256:
17205 case Intrinsic::x86_fma_vfnmsub_ps_256:
17206 case Intrinsic::x86_fma_vfnmsub_pd_256:
17207 case Intrinsic::x86_fma_vfmaddsub_ps_256:
17208 case Intrinsic::x86_fma_vfmaddsub_pd_256:
17209 case Intrinsic::x86_fma_vfmsubadd_ps_256:
17210 case Intrinsic::x86_fma_vfmsubadd_pd_256:
17211 return DAG.getNode(getOpcodeForFMAIntrinsic(IntNo), dl, Op.getValueType(),
17212 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
17216 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17217 SDValue Src, SDValue Mask, SDValue Base,
17218 SDValue Index, SDValue ScaleOp, SDValue Chain,
17219 const X86Subtarget * Subtarget) {
17221 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
17222 assert(C && "Invalid scale type");
17223 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
17224 EVT MaskVT = MVT::getVectorVT(MVT::i1,
17225 Index.getSimpleValueType().getVectorNumElements());
17227 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17229 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
17231 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
17232 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
17233 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
17234 SDValue Segment = DAG.getRegister(0, MVT::i32);
17235 if (Src.getOpcode() == ISD::UNDEF)
17236 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
17237 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
17238 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
17239 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
17240 return DAG.getMergeValues(RetOps, dl);
17243 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17244 SDValue Src, SDValue Mask, SDValue Base,
17245 SDValue Index, SDValue ScaleOp, SDValue Chain) {
17247 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
17248 assert(C && "Invalid scale type");
17249 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
17250 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
17251 SDValue Segment = DAG.getRegister(0, MVT::i32);
17252 EVT MaskVT = MVT::getVectorVT(MVT::i1,
17253 Index.getSimpleValueType().getVectorNumElements());
17255 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17257 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
17259 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
17260 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
17261 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
17262 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
17263 return SDValue(Res, 1);
17266 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17267 SDValue Mask, SDValue Base, SDValue Index,
17268 SDValue ScaleOp, SDValue Chain) {
17270 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
17271 assert(C && "Invalid scale type");
17272 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
17273 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
17274 SDValue Segment = DAG.getRegister(0, MVT::i32);
17276 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
17278 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17280 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
17282 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
17283 //SDVTList VTs = DAG.getVTList(MVT::Other);
17284 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
17285 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
17286 return SDValue(Res, 0);
17289 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
17290 // read performance monitor counters (x86_rdpmc).
17291 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
17292 SelectionDAG &DAG, const X86Subtarget *Subtarget,
17293 SmallVectorImpl<SDValue> &Results) {
17294 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
17295 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17298 // The ECX register is used to select the index of the performance counter
17300 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
17302 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
17304 // Reads the content of a 64-bit performance counter and returns it in the
17305 // registers EDX:EAX.
17306 if (Subtarget->is64Bit()) {
17307 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
17308 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
17311 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
17312 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
17315 Chain = HI.getValue(1);
17317 if (Subtarget->is64Bit()) {
17318 // The EAX register is loaded with the low-order 32 bits. The EDX register
17319 // is loaded with the supported high-order bits of the counter.
17320 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
17321 DAG.getConstant(32, MVT::i8));
17322 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
17323 Results.push_back(Chain);
17327 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
17328 SDValue Ops[] = { LO, HI };
17329 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
17330 Results.push_back(Pair);
17331 Results.push_back(Chain);
17334 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
17335 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
17336 // also used to custom lower READCYCLECOUNTER nodes.
17337 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
17338 SelectionDAG &DAG, const X86Subtarget *Subtarget,
17339 SmallVectorImpl<SDValue> &Results) {
17340 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17341 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
17344 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
17345 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
17346 // and the EAX register is loaded with the low-order 32 bits.
17347 if (Subtarget->is64Bit()) {
17348 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
17349 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
17352 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
17353 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
17356 SDValue Chain = HI.getValue(1);
17358 if (Opcode == X86ISD::RDTSCP_DAG) {
17359 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
17361 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
17362 // the ECX register. Add 'ecx' explicitly to the chain.
17363 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
17365 // Explicitly store the content of ECX at the location passed in input
17366 // to the 'rdtscp' intrinsic.
17367 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
17368 MachinePointerInfo(), false, false, 0);
17371 if (Subtarget->is64Bit()) {
17372 // The EDX register is loaded with the high-order 32 bits of the MSR, and
17373 // the EAX register is loaded with the low-order 32 bits.
17374 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
17375 DAG.getConstant(32, MVT::i8));
17376 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
17377 Results.push_back(Chain);
17381 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
17382 SDValue Ops[] = { LO, HI };
17383 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
17384 Results.push_back(Pair);
17385 Results.push_back(Chain);
17388 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
17389 SelectionDAG &DAG) {
17390 SmallVector<SDValue, 2> Results;
17392 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
17394 return DAG.getMergeValues(Results, DL);
17398 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
17399 SelectionDAG &DAG) {
17400 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
17402 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
17407 switch(IntrData->Type) {
17409 llvm_unreachable("Unknown Intrinsic Type");
17413 // Emit the node with the right value type.
17414 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
17415 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17417 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
17418 // Otherwise return the value from Rand, which is always 0, casted to i32.
17419 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
17420 DAG.getConstant(1, Op->getValueType(1)),
17421 DAG.getConstant(X86::COND_B, MVT::i32),
17422 SDValue(Result.getNode(), 1) };
17423 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
17424 DAG.getVTList(Op->getValueType(1), MVT::Glue),
17427 // Return { result, isValid, chain }.
17428 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
17429 SDValue(Result.getNode(), 2));
17432 //gather(v1, mask, index, base, scale);
17433 SDValue Chain = Op.getOperand(0);
17434 SDValue Src = Op.getOperand(2);
17435 SDValue Base = Op.getOperand(3);
17436 SDValue Index = Op.getOperand(4);
17437 SDValue Mask = Op.getOperand(5);
17438 SDValue Scale = Op.getOperand(6);
17439 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
17443 //scatter(base, mask, index, v1, scale);
17444 SDValue Chain = Op.getOperand(0);
17445 SDValue Base = Op.getOperand(2);
17446 SDValue Mask = Op.getOperand(3);
17447 SDValue Index = Op.getOperand(4);
17448 SDValue Src = Op.getOperand(5);
17449 SDValue Scale = Op.getOperand(6);
17450 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
17453 SDValue Hint = Op.getOperand(6);
17455 if (dyn_cast<ConstantSDNode> (Hint) == nullptr ||
17456 (HintVal = dyn_cast<ConstantSDNode> (Hint)->getZExtValue()) > 1)
17457 llvm_unreachable("Wrong prefetch hint in intrinsic: should be 0 or 1");
17458 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
17459 SDValue Chain = Op.getOperand(0);
17460 SDValue Mask = Op.getOperand(2);
17461 SDValue Index = Op.getOperand(3);
17462 SDValue Base = Op.getOperand(4);
17463 SDValue Scale = Op.getOperand(5);
17464 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
17466 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
17468 SmallVector<SDValue, 2> Results;
17469 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget, Results);
17470 return DAG.getMergeValues(Results, dl);
17472 // Read Performance Monitoring Counters.
17474 SmallVector<SDValue, 2> Results;
17475 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
17476 return DAG.getMergeValues(Results, dl);
17478 // XTEST intrinsics.
17480 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17481 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17482 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17483 DAG.getConstant(X86::COND_NE, MVT::i8),
17485 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
17486 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
17487 Ret, SDValue(InTrans.getNode(), 1));
17491 SmallVector<SDValue, 2> Results;
17492 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17493 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
17494 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
17495 DAG.getConstant(-1, MVT::i8));
17496 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
17497 Op.getOperand(4), GenCF.getValue(1));
17498 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
17499 Op.getOperand(5), MachinePointerInfo(),
17501 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17502 DAG.getConstant(X86::COND_B, MVT::i8),
17504 Results.push_back(SetCC);
17505 Results.push_back(Store);
17506 return DAG.getMergeValues(Results, dl);
17508 case COMPRESS_TO_MEM: {
17510 SDValue Mask = Op.getOperand(4);
17511 SDValue DataToCompress = Op.getOperand(3);
17512 SDValue Addr = Op.getOperand(2);
17513 SDValue Chain = Op.getOperand(0);
17515 if (isAllOnes(Mask)) // return just a store
17516 return DAG.getStore(Chain, dl, DataToCompress, Addr,
17517 MachinePointerInfo(), false, false, 0);
17519 EVT VT = DataToCompress.getValueType();
17520 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17521 VT.getVectorNumElements());
17522 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17523 Mask.getValueType().getSizeInBits());
17524 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
17525 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
17526 DAG.getIntPtrConstant(0));
17528 SDValue Compressed = DAG.getNode(IntrData->Opc0, dl, VT, VMask,
17529 DataToCompress, DAG.getUNDEF(VT));
17530 return DAG.getStore(Chain, dl, Compressed, Addr,
17531 MachinePointerInfo(), false, false, 0);
17533 case EXPAND_FROM_MEM: {
17535 SDValue Mask = Op.getOperand(4);
17536 SDValue PathThru = Op.getOperand(3);
17537 SDValue Addr = Op.getOperand(2);
17538 SDValue Chain = Op.getOperand(0);
17539 EVT VT = Op.getValueType();
17541 if (isAllOnes(Mask)) // return just a load
17542 return DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(), false, false,
17544 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17545 VT.getVectorNumElements());
17546 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17547 Mask.getValueType().getSizeInBits());
17548 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
17549 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
17550 DAG.getIntPtrConstant(0));
17552 SDValue DataToExpand = DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(),
17553 false, false, false, 0);
17555 SmallVector<SDValue, 2> Results;
17556 Results.push_back(DAG.getNode(IntrData->Opc0, dl, VT, VMask, DataToExpand,
17558 Results.push_back(Chain);
17559 return DAG.getMergeValues(Results, dl);
17564 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
17565 SelectionDAG &DAG) const {
17566 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
17567 MFI->setReturnAddressIsTaken(true);
17569 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
17572 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17574 EVT PtrVT = getPointerTy();
17577 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
17578 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17579 DAG.getSubtarget().getRegisterInfo());
17580 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
17581 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17582 DAG.getNode(ISD::ADD, dl, PtrVT,
17583 FrameAddr, Offset),
17584 MachinePointerInfo(), false, false, false, 0);
17587 // Just load the return address.
17588 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
17589 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17590 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
17593 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
17594 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
17595 MFI->setFrameAddressIsTaken(true);
17597 EVT VT = Op.getValueType();
17598 SDLoc dl(Op); // FIXME probably not meaningful
17599 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17600 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17601 DAG.getSubtarget().getRegisterInfo());
17602 unsigned FrameReg = RegInfo->getPtrSizedFrameRegister(
17603 DAG.getMachineFunction());
17604 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
17605 (FrameReg == X86::EBP && VT == MVT::i32)) &&
17606 "Invalid Frame Register!");
17607 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
17609 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
17610 MachinePointerInfo(),
17611 false, false, false, 0);
17615 // FIXME? Maybe this could be a TableGen attribute on some registers and
17616 // this table could be generated automatically from RegInfo.
17617 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
17619 unsigned Reg = StringSwitch<unsigned>(RegName)
17620 .Case("esp", X86::ESP)
17621 .Case("rsp", X86::RSP)
17625 report_fatal_error("Invalid register name global variable");
17628 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
17629 SelectionDAG &DAG) const {
17630 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17631 DAG.getSubtarget().getRegisterInfo());
17632 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
17635 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
17636 SDValue Chain = Op.getOperand(0);
17637 SDValue Offset = Op.getOperand(1);
17638 SDValue Handler = Op.getOperand(2);
17641 EVT PtrVT = getPointerTy();
17642 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17643 DAG.getSubtarget().getRegisterInfo());
17644 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
17645 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
17646 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
17647 "Invalid Frame Register!");
17648 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
17649 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
17651 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
17652 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
17653 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
17654 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
17656 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
17658 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
17659 DAG.getRegister(StoreAddrReg, PtrVT));
17662 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
17663 SelectionDAG &DAG) const {
17665 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
17666 DAG.getVTList(MVT::i32, MVT::Other),
17667 Op.getOperand(0), Op.getOperand(1));
17670 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
17671 SelectionDAG &DAG) const {
17673 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
17674 Op.getOperand(0), Op.getOperand(1));
17677 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
17678 return Op.getOperand(0);
17681 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
17682 SelectionDAG &DAG) const {
17683 SDValue Root = Op.getOperand(0);
17684 SDValue Trmp = Op.getOperand(1); // trampoline
17685 SDValue FPtr = Op.getOperand(2); // nested function
17686 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
17689 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
17690 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
17692 if (Subtarget->is64Bit()) {
17693 SDValue OutChains[6];
17695 // Large code-model.
17696 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
17697 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
17699 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
17700 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
17702 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
17704 // Load the pointer to the nested function into R11.
17705 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
17706 SDValue Addr = Trmp;
17707 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17708 Addr, MachinePointerInfo(TrmpAddr),
17711 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17712 DAG.getConstant(2, MVT::i64));
17713 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
17714 MachinePointerInfo(TrmpAddr, 2),
17717 // Load the 'nest' parameter value into R10.
17718 // R10 is specified in X86CallingConv.td
17719 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
17720 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17721 DAG.getConstant(10, MVT::i64));
17722 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17723 Addr, MachinePointerInfo(TrmpAddr, 10),
17726 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17727 DAG.getConstant(12, MVT::i64));
17728 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
17729 MachinePointerInfo(TrmpAddr, 12),
17732 // Jump to the nested function.
17733 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
17734 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17735 DAG.getConstant(20, MVT::i64));
17736 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17737 Addr, MachinePointerInfo(TrmpAddr, 20),
17740 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
17741 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17742 DAG.getConstant(22, MVT::i64));
17743 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
17744 MachinePointerInfo(TrmpAddr, 22),
17747 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17749 const Function *Func =
17750 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
17751 CallingConv::ID CC = Func->getCallingConv();
17756 llvm_unreachable("Unsupported calling convention");
17757 case CallingConv::C:
17758 case CallingConv::X86_StdCall: {
17759 // Pass 'nest' parameter in ECX.
17760 // Must be kept in sync with X86CallingConv.td
17761 NestReg = X86::ECX;
17763 // Check that ECX wasn't needed by an 'inreg' parameter.
17764 FunctionType *FTy = Func->getFunctionType();
17765 const AttributeSet &Attrs = Func->getAttributes();
17767 if (!Attrs.isEmpty() && !Func->isVarArg()) {
17768 unsigned InRegCount = 0;
17771 for (FunctionType::param_iterator I = FTy->param_begin(),
17772 E = FTy->param_end(); I != E; ++I, ++Idx)
17773 if (Attrs.hasAttribute(Idx, Attribute::InReg))
17774 // FIXME: should only count parameters that are lowered to integers.
17775 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
17777 if (InRegCount > 2) {
17778 report_fatal_error("Nest register in use - reduce number of inreg"
17784 case CallingConv::X86_FastCall:
17785 case CallingConv::X86_ThisCall:
17786 case CallingConv::Fast:
17787 // Pass 'nest' parameter in EAX.
17788 // Must be kept in sync with X86CallingConv.td
17789 NestReg = X86::EAX;
17793 SDValue OutChains[4];
17794 SDValue Addr, Disp;
17796 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17797 DAG.getConstant(10, MVT::i32));
17798 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
17800 // This is storing the opcode for MOV32ri.
17801 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
17802 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
17803 OutChains[0] = DAG.getStore(Root, dl,
17804 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
17805 Trmp, MachinePointerInfo(TrmpAddr),
17808 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17809 DAG.getConstant(1, MVT::i32));
17810 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
17811 MachinePointerInfo(TrmpAddr, 1),
17814 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
17815 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17816 DAG.getConstant(5, MVT::i32));
17817 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
17818 MachinePointerInfo(TrmpAddr, 5),
17821 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17822 DAG.getConstant(6, MVT::i32));
17823 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
17824 MachinePointerInfo(TrmpAddr, 6),
17827 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17831 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
17832 SelectionDAG &DAG) const {
17834 The rounding mode is in bits 11:10 of FPSR, and has the following
17836 00 Round to nearest
17841 FLT_ROUNDS, on the other hand, expects the following:
17848 To perform the conversion, we do:
17849 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
17852 MachineFunction &MF = DAG.getMachineFunction();
17853 const TargetMachine &TM = MF.getTarget();
17854 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
17855 unsigned StackAlignment = TFI.getStackAlignment();
17856 MVT VT = Op.getSimpleValueType();
17859 // Save FP Control Word to stack slot
17860 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
17861 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
17863 MachineMemOperand *MMO =
17864 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
17865 MachineMemOperand::MOStore, 2, 2);
17867 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
17868 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
17869 DAG.getVTList(MVT::Other),
17870 Ops, MVT::i16, MMO);
17872 // Load FP Control Word from stack slot
17873 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
17874 MachinePointerInfo(), false, false, false, 0);
17876 // Transform as necessary
17878 DAG.getNode(ISD::SRL, DL, MVT::i16,
17879 DAG.getNode(ISD::AND, DL, MVT::i16,
17880 CWD, DAG.getConstant(0x800, MVT::i16)),
17881 DAG.getConstant(11, MVT::i8));
17883 DAG.getNode(ISD::SRL, DL, MVT::i16,
17884 DAG.getNode(ISD::AND, DL, MVT::i16,
17885 CWD, DAG.getConstant(0x400, MVT::i16)),
17886 DAG.getConstant(9, MVT::i8));
17889 DAG.getNode(ISD::AND, DL, MVT::i16,
17890 DAG.getNode(ISD::ADD, DL, MVT::i16,
17891 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
17892 DAG.getConstant(1, MVT::i16)),
17893 DAG.getConstant(3, MVT::i16));
17895 return DAG.getNode((VT.getSizeInBits() < 16 ?
17896 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
17899 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
17900 MVT VT = Op.getSimpleValueType();
17902 unsigned NumBits = VT.getSizeInBits();
17905 Op = Op.getOperand(0);
17906 if (VT == MVT::i8) {
17907 // Zero extend to i32 since there is not an i8 bsr.
17909 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17912 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
17913 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17914 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17916 // If src is zero (i.e. bsr sets ZF), returns NumBits.
17919 DAG.getConstant(NumBits+NumBits-1, OpVT),
17920 DAG.getConstant(X86::COND_E, MVT::i8),
17923 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
17925 // Finally xor with NumBits-1.
17926 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
17929 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17933 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
17934 MVT VT = Op.getSimpleValueType();
17936 unsigned NumBits = VT.getSizeInBits();
17939 Op = Op.getOperand(0);
17940 if (VT == MVT::i8) {
17941 // Zero extend to i32 since there is not an i8 bsr.
17943 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17946 // Issue a bsr (scan bits in reverse).
17947 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17948 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17950 // And xor with NumBits-1.
17951 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
17954 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17958 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
17959 MVT VT = Op.getSimpleValueType();
17960 unsigned NumBits = VT.getSizeInBits();
17962 Op = Op.getOperand(0);
17964 // Issue a bsf (scan bits forward) which also sets EFLAGS.
17965 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
17966 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
17968 // If src is zero (i.e. bsf sets ZF), returns NumBits.
17971 DAG.getConstant(NumBits, VT),
17972 DAG.getConstant(X86::COND_E, MVT::i8),
17975 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
17978 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
17979 // ones, and then concatenate the result back.
17980 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
17981 MVT VT = Op.getSimpleValueType();
17983 assert(VT.is256BitVector() && VT.isInteger() &&
17984 "Unsupported value type for operation");
17986 unsigned NumElems = VT.getVectorNumElements();
17989 // Extract the LHS vectors
17990 SDValue LHS = Op.getOperand(0);
17991 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
17992 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
17994 // Extract the RHS vectors
17995 SDValue RHS = Op.getOperand(1);
17996 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
17997 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
17999 MVT EltVT = VT.getVectorElementType();
18000 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18002 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
18003 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
18004 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
18007 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
18008 assert(Op.getSimpleValueType().is256BitVector() &&
18009 Op.getSimpleValueType().isInteger() &&
18010 "Only handle AVX 256-bit vector integer operation");
18011 return Lower256IntArith(Op, DAG);
18014 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
18015 assert(Op.getSimpleValueType().is256BitVector() &&
18016 Op.getSimpleValueType().isInteger() &&
18017 "Only handle AVX 256-bit vector integer operation");
18018 return Lower256IntArith(Op, DAG);
18021 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
18022 SelectionDAG &DAG) {
18024 MVT VT = Op.getSimpleValueType();
18026 // Decompose 256-bit ops into smaller 128-bit ops.
18027 if (VT.is256BitVector() && !Subtarget->hasInt256())
18028 return Lower256IntArith(Op, DAG);
18030 SDValue A = Op.getOperand(0);
18031 SDValue B = Op.getOperand(1);
18033 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
18034 if (VT == MVT::v4i32) {
18035 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
18036 "Should not custom lower when pmuldq is available!");
18038 // Extract the odd parts.
18039 static const int UnpackMask[] = { 1, -1, 3, -1 };
18040 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
18041 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
18043 // Multiply the even parts.
18044 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
18045 // Now multiply odd parts.
18046 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
18048 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
18049 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
18051 // Merge the two vectors back together with a shuffle. This expands into 2
18053 static const int ShufMask[] = { 0, 4, 2, 6 };
18054 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
18057 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
18058 "Only know how to lower V2I64/V4I64/V8I64 multiply");
18060 // Ahi = psrlqi(a, 32);
18061 // Bhi = psrlqi(b, 32);
18063 // AloBlo = pmuludq(a, b);
18064 // AloBhi = pmuludq(a, Bhi);
18065 // AhiBlo = pmuludq(Ahi, b);
18067 // AloBhi = psllqi(AloBhi, 32);
18068 // AhiBlo = psllqi(AhiBlo, 32);
18069 // return AloBlo + AloBhi + AhiBlo;
18071 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
18072 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
18074 // Bit cast to 32-bit vectors for MULUDQ
18075 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
18076 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
18077 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
18078 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
18079 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
18080 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
18082 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
18083 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
18084 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
18086 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
18087 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
18089 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
18090 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
18093 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
18094 assert(Subtarget->isTargetWin64() && "Unexpected target");
18095 EVT VT = Op.getValueType();
18096 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
18097 "Unexpected return type for lowering");
18101 switch (Op->getOpcode()) {
18102 default: llvm_unreachable("Unexpected request for libcall!");
18103 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
18104 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
18105 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
18106 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
18107 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
18108 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
18112 SDValue InChain = DAG.getEntryNode();
18114 TargetLowering::ArgListTy Args;
18115 TargetLowering::ArgListEntry Entry;
18116 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
18117 EVT ArgVT = Op->getOperand(i).getValueType();
18118 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
18119 "Unexpected argument type for lowering");
18120 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
18121 Entry.Node = StackPtr;
18122 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
18124 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
18125 Entry.Ty = PointerType::get(ArgTy,0);
18126 Entry.isSExt = false;
18127 Entry.isZExt = false;
18128 Args.push_back(Entry);
18131 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
18134 TargetLowering::CallLoweringInfo CLI(DAG);
18135 CLI.setDebugLoc(dl).setChain(InChain)
18136 .setCallee(getLibcallCallingConv(LC),
18137 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
18138 Callee, std::move(Args), 0)
18139 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
18141 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
18142 return DAG.getNode(ISD::BITCAST, dl, VT, CallInfo.first);
18145 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
18146 SelectionDAG &DAG) {
18147 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
18148 EVT VT = Op0.getValueType();
18151 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
18152 (VT == MVT::v8i32 && Subtarget->hasInt256()));
18154 // PMULxD operations multiply each even value (starting at 0) of LHS with
18155 // the related value of RHS and produce a widen result.
18156 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
18157 // => <2 x i64> <ae|cg>
18159 // In other word, to have all the results, we need to perform two PMULxD:
18160 // 1. one with the even values.
18161 // 2. one with the odd values.
18162 // To achieve #2, with need to place the odd values at an even position.
18164 // Place the odd value at an even position (basically, shift all values 1
18165 // step to the left):
18166 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
18167 // <a|b|c|d> => <b|undef|d|undef>
18168 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
18169 // <e|f|g|h> => <f|undef|h|undef>
18170 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
18172 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
18174 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
18175 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
18177 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
18178 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
18179 // => <2 x i64> <ae|cg>
18180 SDValue Mul1 = DAG.getNode(ISD::BITCAST, dl, VT,
18181 DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
18182 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
18183 // => <2 x i64> <bf|dh>
18184 SDValue Mul2 = DAG.getNode(ISD::BITCAST, dl, VT,
18185 DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
18187 // Shuffle it back into the right order.
18188 SDValue Highs, Lows;
18189 if (VT == MVT::v8i32) {
18190 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
18191 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
18192 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
18193 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
18195 const int HighMask[] = {1, 5, 3, 7};
18196 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
18197 const int LowMask[] = {0, 4, 2, 6};
18198 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
18201 // If we have a signed multiply but no PMULDQ fix up the high parts of a
18202 // unsigned multiply.
18203 if (IsSigned && !Subtarget->hasSSE41()) {
18205 DAG.getConstant(31, DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
18206 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
18207 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
18208 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
18209 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
18211 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
18212 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
18215 // The first result of MUL_LOHI is actually the low value, followed by the
18217 SDValue Ops[] = {Lows, Highs};
18218 return DAG.getMergeValues(Ops, dl);
18221 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
18222 const X86Subtarget *Subtarget) {
18223 MVT VT = Op.getSimpleValueType();
18225 SDValue R = Op.getOperand(0);
18226 SDValue Amt = Op.getOperand(1);
18228 // Optimize shl/srl/sra with constant shift amount.
18229 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
18230 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
18231 uint64_t ShiftAmt = ShiftConst->getZExtValue();
18233 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
18234 (Subtarget->hasInt256() &&
18235 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
18236 (Subtarget->hasAVX512() &&
18237 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
18238 if (Op.getOpcode() == ISD::SHL)
18239 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
18241 if (Op.getOpcode() == ISD::SRL)
18242 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
18244 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
18245 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
18249 if (VT == MVT::v16i8) {
18250 if (Op.getOpcode() == ISD::SHL) {
18251 // Make a large shift.
18252 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
18253 MVT::v8i16, R, ShiftAmt,
18255 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
18256 // Zero out the rightmost bits.
18257 SmallVector<SDValue, 16> V(16,
18258 DAG.getConstant(uint8_t(-1U << ShiftAmt),
18260 return DAG.getNode(ISD::AND, dl, VT, SHL,
18261 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18263 if (Op.getOpcode() == ISD::SRL) {
18264 // Make a large shift.
18265 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
18266 MVT::v8i16, R, ShiftAmt,
18268 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
18269 // Zero out the leftmost bits.
18270 SmallVector<SDValue, 16> V(16,
18271 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
18273 return DAG.getNode(ISD::AND, dl, VT, SRL,
18274 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18276 if (Op.getOpcode() == ISD::SRA) {
18277 if (ShiftAmt == 7) {
18278 // R s>> 7 === R s< 0
18279 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
18280 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
18283 // R s>> a === ((R u>> a) ^ m) - m
18284 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18285 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
18287 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
18288 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
18289 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
18292 llvm_unreachable("Unknown shift opcode.");
18295 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
18296 if (Op.getOpcode() == ISD::SHL) {
18297 // Make a large shift.
18298 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
18299 MVT::v16i16, R, ShiftAmt,
18301 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
18302 // Zero out the rightmost bits.
18303 SmallVector<SDValue, 32> V(32,
18304 DAG.getConstant(uint8_t(-1U << ShiftAmt),
18306 return DAG.getNode(ISD::AND, dl, VT, SHL,
18307 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18309 if (Op.getOpcode() == ISD::SRL) {
18310 // Make a large shift.
18311 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
18312 MVT::v16i16, R, ShiftAmt,
18314 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
18315 // Zero out the leftmost bits.
18316 SmallVector<SDValue, 32> V(32,
18317 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
18319 return DAG.getNode(ISD::AND, dl, VT, SRL,
18320 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18322 if (Op.getOpcode() == ISD::SRA) {
18323 if (ShiftAmt == 7) {
18324 // R s>> 7 === R s< 0
18325 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
18326 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
18329 // R s>> a === ((R u>> a) ^ m) - m
18330 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18331 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
18333 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
18334 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
18335 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
18338 llvm_unreachable("Unknown shift opcode.");
18343 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18344 if (!Subtarget->is64Bit() &&
18345 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
18346 Amt.getOpcode() == ISD::BITCAST &&
18347 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
18348 Amt = Amt.getOperand(0);
18349 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18350 VT.getVectorNumElements();
18351 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
18352 uint64_t ShiftAmt = 0;
18353 for (unsigned i = 0; i != Ratio; ++i) {
18354 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
18358 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
18360 // Check remaining shift amounts.
18361 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18362 uint64_t ShAmt = 0;
18363 for (unsigned j = 0; j != Ratio; ++j) {
18364 ConstantSDNode *C =
18365 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
18369 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
18371 if (ShAmt != ShiftAmt)
18374 switch (Op.getOpcode()) {
18376 llvm_unreachable("Unknown shift opcode!");
18378 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
18381 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
18384 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
18392 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
18393 const X86Subtarget* Subtarget) {
18394 MVT VT = Op.getSimpleValueType();
18396 SDValue R = Op.getOperand(0);
18397 SDValue Amt = Op.getOperand(1);
18399 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
18400 VT == MVT::v4i32 || VT == MVT::v8i16 ||
18401 (Subtarget->hasInt256() &&
18402 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
18403 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
18404 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
18406 EVT EltVT = VT.getVectorElementType();
18408 if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Amt)) {
18409 // Check if this build_vector node is doing a splat.
18410 // If so, then set BaseShAmt equal to the splat value.
18411 BaseShAmt = BV->getSplatValue();
18412 if (BaseShAmt && BaseShAmt.getOpcode() == ISD::UNDEF)
18413 BaseShAmt = SDValue();
18415 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
18416 Amt = Amt.getOperand(0);
18418 ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt);
18419 if (SVN && SVN->isSplat()) {
18420 unsigned SplatIdx = (unsigned)SVN->getSplatIndex();
18421 SDValue InVec = Amt.getOperand(0);
18422 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
18423 assert((SplatIdx < InVec.getValueType().getVectorNumElements()) &&
18424 "Unexpected shuffle index found!");
18425 BaseShAmt = InVec.getOperand(SplatIdx);
18426 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
18427 if (ConstantSDNode *C =
18428 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
18429 if (C->getZExtValue() == SplatIdx)
18430 BaseShAmt = InVec.getOperand(1);
18435 // Avoid introducing an extract element from a shuffle.
18436 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InVec,
18437 DAG.getIntPtrConstant(SplatIdx));
18441 if (BaseShAmt.getNode()) {
18442 assert(EltVT.bitsLE(MVT::i64) && "Unexpected element type!");
18443 if (EltVT != MVT::i64 && EltVT.bitsGT(MVT::i32))
18444 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, BaseShAmt);
18445 else if (EltVT.bitsLT(MVT::i32))
18446 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
18448 switch (Op.getOpcode()) {
18450 llvm_unreachable("Unknown shift opcode!");
18452 switch (VT.SimpleTy) {
18453 default: return SDValue();
18462 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
18465 switch (VT.SimpleTy) {
18466 default: return SDValue();
18473 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
18476 switch (VT.SimpleTy) {
18477 default: return SDValue();
18486 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
18492 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18493 if (!Subtarget->is64Bit() &&
18494 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
18495 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
18496 Amt.getOpcode() == ISD::BITCAST &&
18497 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
18498 Amt = Amt.getOperand(0);
18499 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18500 VT.getVectorNumElements();
18501 std::vector<SDValue> Vals(Ratio);
18502 for (unsigned i = 0; i != Ratio; ++i)
18503 Vals[i] = Amt.getOperand(i);
18504 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18505 for (unsigned j = 0; j != Ratio; ++j)
18506 if (Vals[j] != Amt.getOperand(i + j))
18509 switch (Op.getOpcode()) {
18511 llvm_unreachable("Unknown shift opcode!");
18513 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
18515 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
18517 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
18524 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
18525 SelectionDAG &DAG) {
18526 MVT VT = Op.getSimpleValueType();
18528 SDValue R = Op.getOperand(0);
18529 SDValue Amt = Op.getOperand(1);
18532 assert(VT.isVector() && "Custom lowering only for vector shifts!");
18533 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
18535 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
18539 V = LowerScalarVariableShift(Op, DAG, Subtarget);
18543 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
18545 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
18546 if (Subtarget->hasInt256()) {
18547 if (Op.getOpcode() == ISD::SRL &&
18548 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
18549 VT == MVT::v4i64 || VT == MVT::v8i32))
18551 if (Op.getOpcode() == ISD::SHL &&
18552 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
18553 VT == MVT::v4i64 || VT == MVT::v8i32))
18555 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
18559 // If possible, lower this packed shift into a vector multiply instead of
18560 // expanding it into a sequence of scalar shifts.
18561 // Do this only if the vector shift count is a constant build_vector.
18562 if (Op.getOpcode() == ISD::SHL &&
18563 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
18564 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
18565 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18566 SmallVector<SDValue, 8> Elts;
18567 EVT SVT = VT.getScalarType();
18568 unsigned SVTBits = SVT.getSizeInBits();
18569 const APInt &One = APInt(SVTBits, 1);
18570 unsigned NumElems = VT.getVectorNumElements();
18572 for (unsigned i=0; i !=NumElems; ++i) {
18573 SDValue Op = Amt->getOperand(i);
18574 if (Op->getOpcode() == ISD::UNDEF) {
18575 Elts.push_back(Op);
18579 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
18580 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
18581 uint64_t ShAmt = C.getZExtValue();
18582 if (ShAmt >= SVTBits) {
18583 Elts.push_back(DAG.getUNDEF(SVT));
18586 Elts.push_back(DAG.getConstant(One.shl(ShAmt), SVT));
18588 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
18589 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
18592 // Lower SHL with variable shift amount.
18593 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
18594 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
18596 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
18597 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
18598 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
18599 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
18602 // If possible, lower this shift as a sequence of two shifts by
18603 // constant plus a MOVSS/MOVSD instead of scalarizing it.
18605 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
18607 // Could be rewritten as:
18608 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
18610 // The advantage is that the two shifts from the example would be
18611 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
18612 // the vector shift into four scalar shifts plus four pairs of vector
18614 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
18615 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18616 unsigned TargetOpcode = X86ISD::MOVSS;
18617 bool CanBeSimplified;
18618 // The splat value for the first packed shift (the 'X' from the example).
18619 SDValue Amt1 = Amt->getOperand(0);
18620 // The splat value for the second packed shift (the 'Y' from the example).
18621 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
18622 Amt->getOperand(2);
18624 // See if it is possible to replace this node with a sequence of
18625 // two shifts followed by a MOVSS/MOVSD
18626 if (VT == MVT::v4i32) {
18627 // Check if it is legal to use a MOVSS.
18628 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
18629 Amt2 == Amt->getOperand(3);
18630 if (!CanBeSimplified) {
18631 // Otherwise, check if we can still simplify this node using a MOVSD.
18632 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
18633 Amt->getOperand(2) == Amt->getOperand(3);
18634 TargetOpcode = X86ISD::MOVSD;
18635 Amt2 = Amt->getOperand(2);
18638 // Do similar checks for the case where the machine value type
18640 CanBeSimplified = Amt1 == Amt->getOperand(1);
18641 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
18642 CanBeSimplified = Amt2 == Amt->getOperand(i);
18644 if (!CanBeSimplified) {
18645 TargetOpcode = X86ISD::MOVSD;
18646 CanBeSimplified = true;
18647 Amt2 = Amt->getOperand(4);
18648 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
18649 CanBeSimplified = Amt1 == Amt->getOperand(i);
18650 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
18651 CanBeSimplified = Amt2 == Amt->getOperand(j);
18655 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
18656 isa<ConstantSDNode>(Amt2)) {
18657 // Replace this node with two shifts followed by a MOVSS/MOVSD.
18658 EVT CastVT = MVT::v4i32;
18660 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), VT);
18661 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
18663 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), VT);
18664 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
18665 if (TargetOpcode == X86ISD::MOVSD)
18666 CastVT = MVT::v2i64;
18667 SDValue BitCast1 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift1);
18668 SDValue BitCast2 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift2);
18669 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
18671 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
18675 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
18676 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
18679 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
18680 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
18682 // Turn 'a' into a mask suitable for VSELECT
18683 SDValue VSelM = DAG.getConstant(0x80, VT);
18684 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18685 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18687 SDValue CM1 = DAG.getConstant(0x0f, VT);
18688 SDValue CM2 = DAG.getConstant(0x3f, VT);
18690 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
18691 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
18692 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
18693 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
18694 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
18697 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
18698 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18699 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18701 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
18702 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
18703 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
18704 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
18705 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
18708 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
18709 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18710 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18712 // return VSELECT(r, r+r, a);
18713 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
18714 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
18718 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
18719 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
18720 // solution better.
18721 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
18722 MVT NewVT = VT == MVT::v8i16 ? MVT::v8i32 : MVT::v16i16;
18724 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
18725 R = DAG.getNode(ExtOpc, dl, NewVT, R);
18726 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, NewVT, Amt);
18727 return DAG.getNode(ISD::TRUNCATE, dl, VT,
18728 DAG.getNode(Op.getOpcode(), dl, NewVT, R, Amt));
18731 // Decompose 256-bit shifts into smaller 128-bit shifts.
18732 if (VT.is256BitVector()) {
18733 unsigned NumElems = VT.getVectorNumElements();
18734 MVT EltVT = VT.getVectorElementType();
18735 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18737 // Extract the two vectors
18738 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
18739 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
18741 // Recreate the shift amount vectors
18742 SDValue Amt1, Amt2;
18743 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
18744 // Constant shift amount
18745 SmallVector<SDValue, 4> Amt1Csts;
18746 SmallVector<SDValue, 4> Amt2Csts;
18747 for (unsigned i = 0; i != NumElems/2; ++i)
18748 Amt1Csts.push_back(Amt->getOperand(i));
18749 for (unsigned i = NumElems/2; i != NumElems; ++i)
18750 Amt2Csts.push_back(Amt->getOperand(i));
18752 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
18753 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
18755 // Variable shift amount
18756 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
18757 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
18760 // Issue new vector shifts for the smaller types
18761 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
18762 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
18764 // Concatenate the result back
18765 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
18771 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
18772 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
18773 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
18774 // looks for this combo and may remove the "setcc" instruction if the "setcc"
18775 // has only one use.
18776 SDNode *N = Op.getNode();
18777 SDValue LHS = N->getOperand(0);
18778 SDValue RHS = N->getOperand(1);
18779 unsigned BaseOp = 0;
18782 switch (Op.getOpcode()) {
18783 default: llvm_unreachable("Unknown ovf instruction!");
18785 // A subtract of one will be selected as a INC. Note that INC doesn't
18786 // set CF, so we can't do this for UADDO.
18787 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18789 BaseOp = X86ISD::INC;
18790 Cond = X86::COND_O;
18793 BaseOp = X86ISD::ADD;
18794 Cond = X86::COND_O;
18797 BaseOp = X86ISD::ADD;
18798 Cond = X86::COND_B;
18801 // A subtract of one will be selected as a DEC. Note that DEC doesn't
18802 // set CF, so we can't do this for USUBO.
18803 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18805 BaseOp = X86ISD::DEC;
18806 Cond = X86::COND_O;
18809 BaseOp = X86ISD::SUB;
18810 Cond = X86::COND_O;
18813 BaseOp = X86ISD::SUB;
18814 Cond = X86::COND_B;
18817 BaseOp = N->getValueType(0) == MVT::i8 ? X86ISD::SMUL8 : X86ISD::SMUL;
18818 Cond = X86::COND_O;
18820 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
18821 if (N->getValueType(0) == MVT::i8) {
18822 BaseOp = X86ISD::UMUL8;
18823 Cond = X86::COND_O;
18826 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
18828 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
18831 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
18832 DAG.getConstant(X86::COND_O, MVT::i32),
18833 SDValue(Sum.getNode(), 2));
18835 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18839 // Also sets EFLAGS.
18840 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
18841 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
18844 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
18845 DAG.getConstant(Cond, MVT::i32),
18846 SDValue(Sum.getNode(), 1));
18848 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18851 // Sign extension of the low part of vector elements. This may be used either
18852 // when sign extend instructions are not available or if the vector element
18853 // sizes already match the sign-extended size. If the vector elements are in
18854 // their pre-extended size and sign extend instructions are available, that will
18855 // be handled by LowerSIGN_EXTEND.
18856 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
18857 SelectionDAG &DAG) const {
18859 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
18860 MVT VT = Op.getSimpleValueType();
18862 if (!Subtarget->hasSSE2() || !VT.isVector())
18865 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
18866 ExtraVT.getScalarType().getSizeInBits();
18868 switch (VT.SimpleTy) {
18869 default: return SDValue();
18872 if (!Subtarget->hasFp256())
18874 if (!Subtarget->hasInt256()) {
18875 // needs to be split
18876 unsigned NumElems = VT.getVectorNumElements();
18878 // Extract the LHS vectors
18879 SDValue LHS = Op.getOperand(0);
18880 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
18881 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
18883 MVT EltVT = VT.getVectorElementType();
18884 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18886 EVT ExtraEltVT = ExtraVT.getVectorElementType();
18887 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
18888 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
18890 SDValue Extra = DAG.getValueType(ExtraVT);
18892 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
18893 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
18895 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
18900 SDValue Op0 = Op.getOperand(0);
18902 // This is a sign extension of some low part of vector elements without
18903 // changing the size of the vector elements themselves:
18904 // Shift-Left + Shift-Right-Algebraic.
18905 SDValue Shl = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Op0,
18907 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, Shl, BitsDiff,
18913 /// Returns true if the operand type is exactly twice the native width, and
18914 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
18915 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
18916 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
18917 bool X86TargetLowering::needsCmpXchgNb(const Type *MemType) const {
18918 const X86Subtarget &Subtarget =
18919 getTargetMachine().getSubtarget<X86Subtarget>();
18920 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
18923 return !Subtarget.is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
18924 else if (OpWidth == 128)
18925 return Subtarget.hasCmpxchg16b();
18930 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
18931 return needsCmpXchgNb(SI->getValueOperand()->getType());
18934 // Note: this turns large loads into lock cmpxchg8b/16b.
18935 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
18936 bool X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
18937 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
18938 return needsCmpXchgNb(PTy->getElementType());
18941 bool X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
18942 const X86Subtarget &Subtarget =
18943 getTargetMachine().getSubtarget<X86Subtarget>();
18944 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
18945 const Type *MemType = AI->getType();
18947 // If the operand is too big, we must see if cmpxchg8/16b is available
18948 // and default to library calls otherwise.
18949 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
18950 return needsCmpXchgNb(MemType);
18952 AtomicRMWInst::BinOp Op = AI->getOperation();
18955 llvm_unreachable("Unknown atomic operation");
18956 case AtomicRMWInst::Xchg:
18957 case AtomicRMWInst::Add:
18958 case AtomicRMWInst::Sub:
18959 // It's better to use xadd, xsub or xchg for these in all cases.
18961 case AtomicRMWInst::Or:
18962 case AtomicRMWInst::And:
18963 case AtomicRMWInst::Xor:
18964 // If the atomicrmw's result isn't actually used, we can just add a "lock"
18965 // prefix to a normal instruction for these operations.
18966 return !AI->use_empty();
18967 case AtomicRMWInst::Nand:
18968 case AtomicRMWInst::Max:
18969 case AtomicRMWInst::Min:
18970 case AtomicRMWInst::UMax:
18971 case AtomicRMWInst::UMin:
18972 // These always require a non-trivial set of data operations on x86. We must
18973 // use a cmpxchg loop.
18978 static bool hasMFENCE(const X86Subtarget& Subtarget) {
18979 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
18980 // no-sse2). There isn't any reason to disable it if the target processor
18982 return Subtarget.hasSSE2() || Subtarget.is64Bit();
18986 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
18987 const X86Subtarget &Subtarget =
18988 getTargetMachine().getSubtarget<X86Subtarget>();
18989 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
18990 const Type *MemType = AI->getType();
18991 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
18992 // there is no benefit in turning such RMWs into loads, and it is actually
18993 // harmful as it introduces a mfence.
18994 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
18997 auto Builder = IRBuilder<>(AI);
18998 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
18999 auto SynchScope = AI->getSynchScope();
19000 // We must restrict the ordering to avoid generating loads with Release or
19001 // ReleaseAcquire orderings.
19002 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
19003 auto Ptr = AI->getPointerOperand();
19005 // Before the load we need a fence. Here is an example lifted from
19006 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
19009 // x.store(1, relaxed);
19010 // r1 = y.fetch_add(0, release);
19012 // y.fetch_add(42, acquire);
19013 // r2 = x.load(relaxed);
19014 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
19015 // lowered to just a load without a fence. A mfence flushes the store buffer,
19016 // making the optimization clearly correct.
19017 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
19018 // otherwise, we might be able to be more agressive on relaxed idempotent
19019 // rmw. In practice, they do not look useful, so we don't try to be
19020 // especially clever.
19021 if (SynchScope == SingleThread) {
19022 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
19023 // the IR level, so we must wrap it in an intrinsic.
19025 } else if (hasMFENCE(Subtarget)) {
19026 Function *MFence = llvm::Intrinsic::getDeclaration(M,
19027 Intrinsic::x86_sse2_mfence);
19028 Builder.CreateCall(MFence);
19030 // FIXME: it might make sense to use a locked operation here but on a
19031 // different cache-line to prevent cache-line bouncing. In practice it
19032 // is probably a small win, and x86 processors without mfence are rare
19033 // enough that we do not bother.
19037 // Finally we can emit the atomic load.
19038 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
19039 AI->getType()->getPrimitiveSizeInBits());
19040 Loaded->setAtomic(Order, SynchScope);
19041 AI->replaceAllUsesWith(Loaded);
19042 AI->eraseFromParent();
19046 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
19047 SelectionDAG &DAG) {
19049 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
19050 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
19051 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
19052 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
19054 // The only fence that needs an instruction is a sequentially-consistent
19055 // cross-thread fence.
19056 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
19057 if (hasMFENCE(*Subtarget))
19058 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
19060 SDValue Chain = Op.getOperand(0);
19061 SDValue Zero = DAG.getConstant(0, MVT::i32);
19063 DAG.getRegister(X86::ESP, MVT::i32), // Base
19064 DAG.getTargetConstant(1, MVT::i8), // Scale
19065 DAG.getRegister(0, MVT::i32), // Index
19066 DAG.getTargetConstant(0, MVT::i32), // Disp
19067 DAG.getRegister(0, MVT::i32), // Segment.
19071 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
19072 return SDValue(Res, 0);
19075 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
19076 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
19079 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
19080 SelectionDAG &DAG) {
19081 MVT T = Op.getSimpleValueType();
19085 switch(T.SimpleTy) {
19086 default: llvm_unreachable("Invalid value type!");
19087 case MVT::i8: Reg = X86::AL; size = 1; break;
19088 case MVT::i16: Reg = X86::AX; size = 2; break;
19089 case MVT::i32: Reg = X86::EAX; size = 4; break;
19091 assert(Subtarget->is64Bit() && "Node not type legal!");
19092 Reg = X86::RAX; size = 8;
19095 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
19096 Op.getOperand(2), SDValue());
19097 SDValue Ops[] = { cpIn.getValue(0),
19100 DAG.getTargetConstant(size, MVT::i8),
19101 cpIn.getValue(1) };
19102 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
19103 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
19104 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
19108 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
19109 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
19110 MVT::i32, cpOut.getValue(2));
19111 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
19112 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
19114 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
19115 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
19116 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
19120 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
19121 SelectionDAG &DAG) {
19122 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
19123 MVT DstVT = Op.getSimpleValueType();
19125 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
19126 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19127 if (DstVT != MVT::f64)
19128 // This conversion needs to be expanded.
19131 SDValue InVec = Op->getOperand(0);
19133 unsigned NumElts = SrcVT.getVectorNumElements();
19134 EVT SVT = SrcVT.getVectorElementType();
19136 // Widen the vector in input in the case of MVT::v2i32.
19137 // Example: from MVT::v2i32 to MVT::v4i32.
19138 SmallVector<SDValue, 16> Elts;
19139 for (unsigned i = 0, e = NumElts; i != e; ++i)
19140 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
19141 DAG.getIntPtrConstant(i)));
19143 // Explicitly mark the extra elements as Undef.
19144 SDValue Undef = DAG.getUNDEF(SVT);
19145 for (unsigned i = NumElts, e = NumElts * 2; i != e; ++i)
19146 Elts.push_back(Undef);
19148 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19149 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
19150 SDValue ToV2F64 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, BV);
19151 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
19152 DAG.getIntPtrConstant(0));
19155 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
19156 Subtarget->hasMMX() && "Unexpected custom BITCAST");
19157 assert((DstVT == MVT::i64 ||
19158 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
19159 "Unexpected custom BITCAST");
19160 // i64 <=> MMX conversions are Legal.
19161 if (SrcVT==MVT::i64 && DstVT.isVector())
19163 if (DstVT==MVT::i64 && SrcVT.isVector())
19165 // MMX <=> MMX conversions are Legal.
19166 if (SrcVT.isVector() && DstVT.isVector())
19168 // All other conversions need to be expanded.
19172 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
19173 SDNode *Node = Op.getNode();
19175 EVT T = Node->getValueType(0);
19176 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
19177 DAG.getConstant(0, T), Node->getOperand(2));
19178 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
19179 cast<AtomicSDNode>(Node)->getMemoryVT(),
19180 Node->getOperand(0),
19181 Node->getOperand(1), negOp,
19182 cast<AtomicSDNode>(Node)->getMemOperand(),
19183 cast<AtomicSDNode>(Node)->getOrdering(),
19184 cast<AtomicSDNode>(Node)->getSynchScope());
19187 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
19188 SDNode *Node = Op.getNode();
19190 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
19192 // Convert seq_cst store -> xchg
19193 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
19194 // FIXME: On 32-bit, store -> fist or movq would be more efficient
19195 // (The only way to get a 16-byte store is cmpxchg16b)
19196 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
19197 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
19198 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
19199 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
19200 cast<AtomicSDNode>(Node)->getMemoryVT(),
19201 Node->getOperand(0),
19202 Node->getOperand(1), Node->getOperand(2),
19203 cast<AtomicSDNode>(Node)->getMemOperand(),
19204 cast<AtomicSDNode>(Node)->getOrdering(),
19205 cast<AtomicSDNode>(Node)->getSynchScope());
19206 return Swap.getValue(1);
19208 // Other atomic stores have a simple pattern.
19212 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
19213 EVT VT = Op.getNode()->getSimpleValueType(0);
19215 // Let legalize expand this if it isn't a legal type yet.
19216 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
19219 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
19222 bool ExtraOp = false;
19223 switch (Op.getOpcode()) {
19224 default: llvm_unreachable("Invalid code");
19225 case ISD::ADDC: Opc = X86ISD::ADD; break;
19226 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
19227 case ISD::SUBC: Opc = X86ISD::SUB; break;
19228 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
19232 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19234 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19235 Op.getOperand(1), Op.getOperand(2));
19238 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
19239 SelectionDAG &DAG) {
19240 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
19242 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
19243 // which returns the values as { float, float } (in XMM0) or
19244 // { double, double } (which is returned in XMM0, XMM1).
19246 SDValue Arg = Op.getOperand(0);
19247 EVT ArgVT = Arg.getValueType();
19248 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
19250 TargetLowering::ArgListTy Args;
19251 TargetLowering::ArgListEntry Entry;
19255 Entry.isSExt = false;
19256 Entry.isZExt = false;
19257 Args.push_back(Entry);
19259 bool isF64 = ArgVT == MVT::f64;
19260 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
19261 // the small struct {f32, f32} is returned in (eax, edx). For f64,
19262 // the results are returned via SRet in memory.
19263 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
19264 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19265 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
19267 Type *RetTy = isF64
19268 ? (Type*)StructType::get(ArgTy, ArgTy, nullptr)
19269 : (Type*)VectorType::get(ArgTy, 4);
19271 TargetLowering::CallLoweringInfo CLI(DAG);
19272 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
19273 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
19275 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
19278 // Returned in xmm0 and xmm1.
19279 return CallResult.first;
19281 // Returned in bits 0:31 and 32:64 xmm0.
19282 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19283 CallResult.first, DAG.getIntPtrConstant(0));
19284 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19285 CallResult.first, DAG.getIntPtrConstant(1));
19286 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
19287 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
19290 /// LowerOperation - Provide custom lowering hooks for some operations.
19292 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
19293 switch (Op.getOpcode()) {
19294 default: llvm_unreachable("Should not custom lower this!");
19295 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
19296 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
19297 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
19298 return LowerCMP_SWAP(Op, Subtarget, DAG);
19299 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
19300 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
19301 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
19302 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
19303 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
19304 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
19305 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
19306 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
19307 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
19308 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
19309 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
19310 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
19311 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
19312 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
19313 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
19314 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
19315 case ISD::SHL_PARTS:
19316 case ISD::SRA_PARTS:
19317 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
19318 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
19319 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
19320 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
19321 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
19322 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
19323 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
19324 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
19325 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
19326 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
19327 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
19329 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
19330 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
19331 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
19332 case ISD::SETCC: return LowerSETCC(Op, DAG);
19333 case ISD::SELECT: return LowerSELECT(Op, DAG);
19334 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
19335 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
19336 case ISD::VASTART: return LowerVASTART(Op, DAG);
19337 case ISD::VAARG: return LowerVAARG(Op, DAG);
19338 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
19339 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, Subtarget, DAG);
19340 case ISD::INTRINSIC_VOID:
19341 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
19342 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
19343 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
19344 case ISD::FRAME_TO_ARGS_OFFSET:
19345 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
19346 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
19347 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
19348 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
19349 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
19350 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
19351 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
19352 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
19353 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
19354 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
19355 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
19356 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
19357 case ISD::UMUL_LOHI:
19358 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
19361 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
19367 case ISD::UMULO: return LowerXALUO(Op, DAG);
19368 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
19369 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
19373 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
19374 case ISD::ADD: return LowerADD(Op, DAG);
19375 case ISD::SUB: return LowerSUB(Op, DAG);
19376 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
19380 /// ReplaceNodeResults - Replace a node with an illegal result type
19381 /// with a new node built out of custom code.
19382 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
19383 SmallVectorImpl<SDValue>&Results,
19384 SelectionDAG &DAG) const {
19386 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19387 switch (N->getOpcode()) {
19389 llvm_unreachable("Do not know how to custom type legalize this operation!");
19390 case ISD::SIGN_EXTEND_INREG:
19395 // We don't want to expand or promote these.
19402 case ISD::UDIVREM: {
19403 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
19404 Results.push_back(V);
19407 case ISD::FP_TO_SINT:
19408 case ISD::FP_TO_UINT: {
19409 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
19411 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
19414 std::pair<SDValue,SDValue> Vals =
19415 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
19416 SDValue FIST = Vals.first, StackSlot = Vals.second;
19417 if (FIST.getNode()) {
19418 EVT VT = N->getValueType(0);
19419 // Return a load from the stack slot.
19420 if (StackSlot.getNode())
19421 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
19422 MachinePointerInfo(),
19423 false, false, false, 0));
19425 Results.push_back(FIST);
19429 case ISD::UINT_TO_FP: {
19430 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19431 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
19432 N->getValueType(0) != MVT::v2f32)
19434 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
19436 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
19438 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
19439 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
19440 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
19441 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
19442 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
19443 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
19446 case ISD::FP_ROUND: {
19447 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
19449 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
19450 Results.push_back(V);
19453 case ISD::INTRINSIC_W_CHAIN: {
19454 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
19456 default : llvm_unreachable("Do not know how to custom type "
19457 "legalize this intrinsic operation!");
19458 case Intrinsic::x86_rdtsc:
19459 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19461 case Intrinsic::x86_rdtscp:
19462 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
19464 case Intrinsic::x86_rdpmc:
19465 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
19468 case ISD::READCYCLECOUNTER: {
19469 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19472 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
19473 EVT T = N->getValueType(0);
19474 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
19475 bool Regs64bit = T == MVT::i128;
19476 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
19477 SDValue cpInL, cpInH;
19478 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19479 DAG.getConstant(0, HalfT));
19480 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19481 DAG.getConstant(1, HalfT));
19482 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
19483 Regs64bit ? X86::RAX : X86::EAX,
19485 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
19486 Regs64bit ? X86::RDX : X86::EDX,
19487 cpInH, cpInL.getValue(1));
19488 SDValue swapInL, swapInH;
19489 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19490 DAG.getConstant(0, HalfT));
19491 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19492 DAG.getConstant(1, HalfT));
19493 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
19494 Regs64bit ? X86::RBX : X86::EBX,
19495 swapInL, cpInH.getValue(1));
19496 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
19497 Regs64bit ? X86::RCX : X86::ECX,
19498 swapInH, swapInL.getValue(1));
19499 SDValue Ops[] = { swapInH.getValue(0),
19501 swapInH.getValue(1) };
19502 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
19503 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
19504 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
19505 X86ISD::LCMPXCHG8_DAG;
19506 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
19507 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
19508 Regs64bit ? X86::RAX : X86::EAX,
19509 HalfT, Result.getValue(1));
19510 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
19511 Regs64bit ? X86::RDX : X86::EDX,
19512 HalfT, cpOutL.getValue(2));
19513 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
19515 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
19516 MVT::i32, cpOutH.getValue(2));
19518 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
19519 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
19520 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
19522 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
19523 Results.push_back(Success);
19524 Results.push_back(EFLAGS.getValue(1));
19527 case ISD::ATOMIC_SWAP:
19528 case ISD::ATOMIC_LOAD_ADD:
19529 case ISD::ATOMIC_LOAD_SUB:
19530 case ISD::ATOMIC_LOAD_AND:
19531 case ISD::ATOMIC_LOAD_OR:
19532 case ISD::ATOMIC_LOAD_XOR:
19533 case ISD::ATOMIC_LOAD_NAND:
19534 case ISD::ATOMIC_LOAD_MIN:
19535 case ISD::ATOMIC_LOAD_MAX:
19536 case ISD::ATOMIC_LOAD_UMIN:
19537 case ISD::ATOMIC_LOAD_UMAX:
19538 case ISD::ATOMIC_LOAD: {
19539 // Delegate to generic TypeLegalization. Situations we can really handle
19540 // should have already been dealt with by AtomicExpandPass.cpp.
19543 case ISD::BITCAST: {
19544 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19545 EVT DstVT = N->getValueType(0);
19546 EVT SrcVT = N->getOperand(0)->getValueType(0);
19548 if (SrcVT != MVT::f64 ||
19549 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
19552 unsigned NumElts = DstVT.getVectorNumElements();
19553 EVT SVT = DstVT.getVectorElementType();
19554 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19555 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
19556 MVT::v2f64, N->getOperand(0));
19557 SDValue ToVecInt = DAG.getNode(ISD::BITCAST, dl, WiderVT, Expanded);
19559 if (ExperimentalVectorWideningLegalization) {
19560 // If we are legalizing vectors by widening, we already have the desired
19561 // legal vector type, just return it.
19562 Results.push_back(ToVecInt);
19566 SmallVector<SDValue, 8> Elts;
19567 for (unsigned i = 0, e = NumElts; i != e; ++i)
19568 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
19569 ToVecInt, DAG.getIntPtrConstant(i)));
19571 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
19576 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
19578 default: return nullptr;
19579 case X86ISD::BSF: return "X86ISD::BSF";
19580 case X86ISD::BSR: return "X86ISD::BSR";
19581 case X86ISD::SHLD: return "X86ISD::SHLD";
19582 case X86ISD::SHRD: return "X86ISD::SHRD";
19583 case X86ISD::FAND: return "X86ISD::FAND";
19584 case X86ISD::FANDN: return "X86ISD::FANDN";
19585 case X86ISD::FOR: return "X86ISD::FOR";
19586 case X86ISD::FXOR: return "X86ISD::FXOR";
19587 case X86ISD::FSRL: return "X86ISD::FSRL";
19588 case X86ISD::FILD: return "X86ISD::FILD";
19589 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
19590 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
19591 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
19592 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
19593 case X86ISD::FLD: return "X86ISD::FLD";
19594 case X86ISD::FST: return "X86ISD::FST";
19595 case X86ISD::CALL: return "X86ISD::CALL";
19596 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
19597 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
19598 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
19599 case X86ISD::BT: return "X86ISD::BT";
19600 case X86ISD::CMP: return "X86ISD::CMP";
19601 case X86ISD::COMI: return "X86ISD::COMI";
19602 case X86ISD::UCOMI: return "X86ISD::UCOMI";
19603 case X86ISD::CMPM: return "X86ISD::CMPM";
19604 case X86ISD::CMPMU: return "X86ISD::CMPMU";
19605 case X86ISD::SETCC: return "X86ISD::SETCC";
19606 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
19607 case X86ISD::FSETCC: return "X86ISD::FSETCC";
19608 case X86ISD::CMOV: return "X86ISD::CMOV";
19609 case X86ISD::BRCOND: return "X86ISD::BRCOND";
19610 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
19611 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
19612 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
19613 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
19614 case X86ISD::Wrapper: return "X86ISD::Wrapper";
19615 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
19616 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
19617 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
19618 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
19619 case X86ISD::PINSRB: return "X86ISD::PINSRB";
19620 case X86ISD::PINSRW: return "X86ISD::PINSRW";
19621 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
19622 case X86ISD::ANDNP: return "X86ISD::ANDNP";
19623 case X86ISD::PSIGN: return "X86ISD::PSIGN";
19624 case X86ISD::BLENDI: return "X86ISD::BLENDI";
19625 case X86ISD::SHRUNKBLEND: return "X86ISD::SHRUNKBLEND";
19626 case X86ISD::SUBUS: return "X86ISD::SUBUS";
19627 case X86ISD::HADD: return "X86ISD::HADD";
19628 case X86ISD::HSUB: return "X86ISD::HSUB";
19629 case X86ISD::FHADD: return "X86ISD::FHADD";
19630 case X86ISD::FHSUB: return "X86ISD::FHSUB";
19631 case X86ISD::UMAX: return "X86ISD::UMAX";
19632 case X86ISD::UMIN: return "X86ISD::UMIN";
19633 case X86ISD::SMAX: return "X86ISD::SMAX";
19634 case X86ISD::SMIN: return "X86ISD::SMIN";
19635 case X86ISD::FMAX: return "X86ISD::FMAX";
19636 case X86ISD::FMIN: return "X86ISD::FMIN";
19637 case X86ISD::FMAXC: return "X86ISD::FMAXC";
19638 case X86ISD::FMINC: return "X86ISD::FMINC";
19639 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
19640 case X86ISD::FRCP: return "X86ISD::FRCP";
19641 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
19642 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
19643 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
19644 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
19645 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
19646 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
19647 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
19648 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
19649 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
19650 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
19651 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
19652 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
19653 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
19654 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
19655 case X86ISD::VZEXT: return "X86ISD::VZEXT";
19656 case X86ISD::VSEXT: return "X86ISD::VSEXT";
19657 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
19658 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
19659 case X86ISD::VINSERT: return "X86ISD::VINSERT";
19660 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
19661 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
19662 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
19663 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
19664 case X86ISD::VSHL: return "X86ISD::VSHL";
19665 case X86ISD::VSRL: return "X86ISD::VSRL";
19666 case X86ISD::VSRA: return "X86ISD::VSRA";
19667 case X86ISD::VSHLI: return "X86ISD::VSHLI";
19668 case X86ISD::VSRLI: return "X86ISD::VSRLI";
19669 case X86ISD::VSRAI: return "X86ISD::VSRAI";
19670 case X86ISD::CMPP: return "X86ISD::CMPP";
19671 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
19672 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
19673 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
19674 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
19675 case X86ISD::ADD: return "X86ISD::ADD";
19676 case X86ISD::SUB: return "X86ISD::SUB";
19677 case X86ISD::ADC: return "X86ISD::ADC";
19678 case X86ISD::SBB: return "X86ISD::SBB";
19679 case X86ISD::SMUL: return "X86ISD::SMUL";
19680 case X86ISD::UMUL: return "X86ISD::UMUL";
19681 case X86ISD::SMUL8: return "X86ISD::SMUL8";
19682 case X86ISD::UMUL8: return "X86ISD::UMUL8";
19683 case X86ISD::SDIVREM8_SEXT_HREG: return "X86ISD::SDIVREM8_SEXT_HREG";
19684 case X86ISD::UDIVREM8_ZEXT_HREG: return "X86ISD::UDIVREM8_ZEXT_HREG";
19685 case X86ISD::INC: return "X86ISD::INC";
19686 case X86ISD::DEC: return "X86ISD::DEC";
19687 case X86ISD::OR: return "X86ISD::OR";
19688 case X86ISD::XOR: return "X86ISD::XOR";
19689 case X86ISD::AND: return "X86ISD::AND";
19690 case X86ISD::BEXTR: return "X86ISD::BEXTR";
19691 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
19692 case X86ISD::PTEST: return "X86ISD::PTEST";
19693 case X86ISD::TESTP: return "X86ISD::TESTP";
19694 case X86ISD::TESTM: return "X86ISD::TESTM";
19695 case X86ISD::TESTNM: return "X86ISD::TESTNM";
19696 case X86ISD::KORTEST: return "X86ISD::KORTEST";
19697 case X86ISD::PACKSS: return "X86ISD::PACKSS";
19698 case X86ISD::PACKUS: return "X86ISD::PACKUS";
19699 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
19700 case X86ISD::VALIGN: return "X86ISD::VALIGN";
19701 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
19702 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
19703 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
19704 case X86ISD::SHUFP: return "X86ISD::SHUFP";
19705 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
19706 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
19707 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
19708 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
19709 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
19710 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
19711 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
19712 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
19713 case X86ISD::MOVSD: return "X86ISD::MOVSD";
19714 case X86ISD::MOVSS: return "X86ISD::MOVSS";
19715 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
19716 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
19717 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
19718 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
19719 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
19720 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
19721 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
19722 case X86ISD::VPERMV: return "X86ISD::VPERMV";
19723 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
19724 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
19725 case X86ISD::VPERMI: return "X86ISD::VPERMI";
19726 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
19727 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
19728 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
19729 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
19730 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
19731 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
19732 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
19733 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
19734 case X86ISD::SAHF: return "X86ISD::SAHF";
19735 case X86ISD::RDRAND: return "X86ISD::RDRAND";
19736 case X86ISD::RDSEED: return "X86ISD::RDSEED";
19737 case X86ISD::FMADD: return "X86ISD::FMADD";
19738 case X86ISD::FMSUB: return "X86ISD::FMSUB";
19739 case X86ISD::FNMADD: return "X86ISD::FNMADD";
19740 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
19741 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
19742 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
19743 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
19744 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
19745 case X86ISD::XTEST: return "X86ISD::XTEST";
19746 case X86ISD::COMPRESS: return "X86ISD::COMPRESS";
19747 case X86ISD::EXPAND: return "X86ISD::EXPAND";
19751 // isLegalAddressingMode - Return true if the addressing mode represented
19752 // by AM is legal for this target, for a load/store of the specified type.
19753 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
19755 // X86 supports extremely general addressing modes.
19756 CodeModel::Model M = getTargetMachine().getCodeModel();
19757 Reloc::Model R = getTargetMachine().getRelocationModel();
19759 // X86 allows a sign-extended 32-bit immediate field as a displacement.
19760 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
19765 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
19767 // If a reference to this global requires an extra load, we can't fold it.
19768 if (isGlobalStubReference(GVFlags))
19771 // If BaseGV requires a register for the PIC base, we cannot also have a
19772 // BaseReg specified.
19773 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
19776 // If lower 4G is not available, then we must use rip-relative addressing.
19777 if ((M != CodeModel::Small || R != Reloc::Static) &&
19778 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
19782 switch (AM.Scale) {
19788 // These scales always work.
19793 // These scales are formed with basereg+scalereg. Only accept if there is
19798 default: // Other stuff never works.
19805 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
19806 unsigned Bits = Ty->getScalarSizeInBits();
19808 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
19809 // particularly cheaper than those without.
19813 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
19814 // variable shifts just as cheap as scalar ones.
19815 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
19818 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
19819 // fully general vector.
19823 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
19824 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
19826 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
19827 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
19828 return NumBits1 > NumBits2;
19831 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
19832 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
19835 if (!isTypeLegal(EVT::getEVT(Ty1)))
19838 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
19840 // Assuming the caller doesn't have a zeroext or signext return parameter,
19841 // truncation all the way down to i1 is valid.
19845 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
19846 return isInt<32>(Imm);
19849 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
19850 // Can also use sub to handle negated immediates.
19851 return isInt<32>(Imm);
19854 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
19855 if (!VT1.isInteger() || !VT2.isInteger())
19857 unsigned NumBits1 = VT1.getSizeInBits();
19858 unsigned NumBits2 = VT2.getSizeInBits();
19859 return NumBits1 > NumBits2;
19862 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
19863 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
19864 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
19867 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
19868 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
19869 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
19872 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
19873 EVT VT1 = Val.getValueType();
19874 if (isZExtFree(VT1, VT2))
19877 if (Val.getOpcode() != ISD::LOAD)
19880 if (!VT1.isSimple() || !VT1.isInteger() ||
19881 !VT2.isSimple() || !VT2.isInteger())
19884 switch (VT1.getSimpleVT().SimpleTy) {
19889 // X86 has 8, 16, and 32-bit zero-extending loads.
19897 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
19898 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
19901 VT = VT.getScalarType();
19903 if (!VT.isSimple())
19906 switch (VT.getSimpleVT().SimpleTy) {
19917 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
19918 // i16 instructions are longer (0x66 prefix) and potentially slower.
19919 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
19922 /// isShuffleMaskLegal - Targets can use this to indicate that they only
19923 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
19924 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
19925 /// are assumed to be legal.
19927 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
19929 if (!VT.isSimple())
19932 MVT SVT = VT.getSimpleVT();
19934 // Very little shuffling can be done for 64-bit vectors right now.
19935 if (VT.getSizeInBits() == 64)
19938 // If this is a single-input shuffle with no 128 bit lane crossings we can
19939 // lower it into pshufb.
19940 if ((SVT.is128BitVector() && Subtarget->hasSSSE3()) ||
19941 (SVT.is256BitVector() && Subtarget->hasInt256())) {
19942 bool isLegal = true;
19943 for (unsigned I = 0, E = M.size(); I != E; ++I) {
19944 if (M[I] >= (int)SVT.getVectorNumElements() ||
19945 ShuffleCrosses128bitLane(SVT, I, M[I])) {
19954 // FIXME: blends, shifts.
19955 return (SVT.getVectorNumElements() == 2 ||
19956 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
19957 isMOVLMask(M, SVT) ||
19958 isCommutedMOVLMask(M, SVT) ||
19959 isMOVHLPSMask(M, SVT) ||
19960 isSHUFPMask(M, SVT) ||
19961 isSHUFPMask(M, SVT, /* Commuted */ true) ||
19962 isPSHUFDMask(M, SVT) ||
19963 isPSHUFDMask(M, SVT, /* SecondOperand */ true) ||
19964 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
19965 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
19966 isPALIGNRMask(M, SVT, Subtarget) ||
19967 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
19968 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
19969 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
19970 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
19971 isBlendMask(M, SVT, Subtarget->hasSSE41(), Subtarget->hasInt256()) ||
19972 (Subtarget->hasSSE41() && isINSERTPSMask(M, SVT)));
19976 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
19978 if (!VT.isSimple())
19981 MVT SVT = VT.getSimpleVT();
19982 unsigned NumElts = SVT.getVectorNumElements();
19983 // FIXME: This collection of masks seems suspect.
19986 if (NumElts == 4 && SVT.is128BitVector()) {
19987 return (isMOVLMask(Mask, SVT) ||
19988 isCommutedMOVLMask(Mask, SVT, true) ||
19989 isSHUFPMask(Mask, SVT) ||
19990 isSHUFPMask(Mask, SVT, /* Commuted */ true) ||
19991 isBlendMask(Mask, SVT, Subtarget->hasSSE41(),
19992 Subtarget->hasInt256()));
19997 //===----------------------------------------------------------------------===//
19998 // X86 Scheduler Hooks
19999 //===----------------------------------------------------------------------===//
20001 /// Utility function to emit xbegin specifying the start of an RTM region.
20002 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
20003 const TargetInstrInfo *TII) {
20004 DebugLoc DL = MI->getDebugLoc();
20006 const BasicBlock *BB = MBB->getBasicBlock();
20007 MachineFunction::iterator I = MBB;
20010 // For the v = xbegin(), we generate
20021 MachineBasicBlock *thisMBB = MBB;
20022 MachineFunction *MF = MBB->getParent();
20023 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
20024 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
20025 MF->insert(I, mainMBB);
20026 MF->insert(I, sinkMBB);
20028 // Transfer the remainder of BB and its successor edges to sinkMBB.
20029 sinkMBB->splice(sinkMBB->begin(), MBB,
20030 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20031 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
20035 // # fallthrough to mainMBB
20036 // # abortion to sinkMBB
20037 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
20038 thisMBB->addSuccessor(mainMBB);
20039 thisMBB->addSuccessor(sinkMBB);
20043 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
20044 mainMBB->addSuccessor(sinkMBB);
20047 // EAX is live into the sinkMBB
20048 sinkMBB->addLiveIn(X86::EAX);
20049 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20050 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20053 MI->eraseFromParent();
20057 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
20058 // or XMM0_V32I8 in AVX all of this code can be replaced with that
20059 // in the .td file.
20060 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
20061 const TargetInstrInfo *TII) {
20063 switch (MI->getOpcode()) {
20064 default: llvm_unreachable("illegal opcode!");
20065 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
20066 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
20067 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
20068 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
20069 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
20070 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
20071 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
20072 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
20075 DebugLoc dl = MI->getDebugLoc();
20076 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20078 unsigned NumArgs = MI->getNumOperands();
20079 for (unsigned i = 1; i < NumArgs; ++i) {
20080 MachineOperand &Op = MI->getOperand(i);
20081 if (!(Op.isReg() && Op.isImplicit()))
20082 MIB.addOperand(Op);
20084 if (MI->hasOneMemOperand())
20085 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20087 BuildMI(*BB, MI, dl,
20088 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20089 .addReg(X86::XMM0);
20091 MI->eraseFromParent();
20095 // FIXME: Custom handling because TableGen doesn't support multiple implicit
20096 // defs in an instruction pattern
20097 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
20098 const TargetInstrInfo *TII) {
20100 switch (MI->getOpcode()) {
20101 default: llvm_unreachable("illegal opcode!");
20102 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
20103 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
20104 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
20105 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
20106 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
20107 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
20108 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
20109 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
20112 DebugLoc dl = MI->getDebugLoc();
20113 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20115 unsigned NumArgs = MI->getNumOperands(); // remove the results
20116 for (unsigned i = 1; i < NumArgs; ++i) {
20117 MachineOperand &Op = MI->getOperand(i);
20118 if (!(Op.isReg() && Op.isImplicit()))
20119 MIB.addOperand(Op);
20121 if (MI->hasOneMemOperand())
20122 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20124 BuildMI(*BB, MI, dl,
20125 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20128 MI->eraseFromParent();
20132 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
20133 const TargetInstrInfo *TII,
20134 const X86Subtarget* Subtarget) {
20135 DebugLoc dl = MI->getDebugLoc();
20137 // Address into RAX/EAX, other two args into ECX, EDX.
20138 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
20139 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
20140 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
20141 for (int i = 0; i < X86::AddrNumOperands; ++i)
20142 MIB.addOperand(MI->getOperand(i));
20144 unsigned ValOps = X86::AddrNumOperands;
20145 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
20146 .addReg(MI->getOperand(ValOps).getReg());
20147 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
20148 .addReg(MI->getOperand(ValOps+1).getReg());
20150 // The instruction doesn't actually take any operands though.
20151 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
20153 MI->eraseFromParent(); // The pseudo is gone now.
20157 MachineBasicBlock *
20158 X86TargetLowering::EmitVAARG64WithCustomInserter(
20160 MachineBasicBlock *MBB) const {
20161 // Emit va_arg instruction on X86-64.
20163 // Operands to this pseudo-instruction:
20164 // 0 ) Output : destination address (reg)
20165 // 1-5) Input : va_list address (addr, i64mem)
20166 // 6 ) ArgSize : Size (in bytes) of vararg type
20167 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
20168 // 8 ) Align : Alignment of type
20169 // 9 ) EFLAGS (implicit-def)
20171 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
20172 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
20174 unsigned DestReg = MI->getOperand(0).getReg();
20175 MachineOperand &Base = MI->getOperand(1);
20176 MachineOperand &Scale = MI->getOperand(2);
20177 MachineOperand &Index = MI->getOperand(3);
20178 MachineOperand &Disp = MI->getOperand(4);
20179 MachineOperand &Segment = MI->getOperand(5);
20180 unsigned ArgSize = MI->getOperand(6).getImm();
20181 unsigned ArgMode = MI->getOperand(7).getImm();
20182 unsigned Align = MI->getOperand(8).getImm();
20184 // Memory Reference
20185 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
20186 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20187 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20189 // Machine Information
20190 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
20191 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
20192 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
20193 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
20194 DebugLoc DL = MI->getDebugLoc();
20196 // struct va_list {
20199 // i64 overflow_area (address)
20200 // i64 reg_save_area (address)
20202 // sizeof(va_list) = 24
20203 // alignment(va_list) = 8
20205 unsigned TotalNumIntRegs = 6;
20206 unsigned TotalNumXMMRegs = 8;
20207 bool UseGPOffset = (ArgMode == 1);
20208 bool UseFPOffset = (ArgMode == 2);
20209 unsigned MaxOffset = TotalNumIntRegs * 8 +
20210 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
20212 /* Align ArgSize to a multiple of 8 */
20213 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
20214 bool NeedsAlign = (Align > 8);
20216 MachineBasicBlock *thisMBB = MBB;
20217 MachineBasicBlock *overflowMBB;
20218 MachineBasicBlock *offsetMBB;
20219 MachineBasicBlock *endMBB;
20221 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
20222 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
20223 unsigned OffsetReg = 0;
20225 if (!UseGPOffset && !UseFPOffset) {
20226 // If we only pull from the overflow region, we don't create a branch.
20227 // We don't need to alter control flow.
20228 OffsetDestReg = 0; // unused
20229 OverflowDestReg = DestReg;
20231 offsetMBB = nullptr;
20232 overflowMBB = thisMBB;
20235 // First emit code to check if gp_offset (or fp_offset) is below the bound.
20236 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
20237 // If not, pull from overflow_area. (branch to overflowMBB)
20242 // offsetMBB overflowMBB
20247 // Registers for the PHI in endMBB
20248 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
20249 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
20251 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20252 MachineFunction *MF = MBB->getParent();
20253 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20254 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20255 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20257 MachineFunction::iterator MBBIter = MBB;
20260 // Insert the new basic blocks
20261 MF->insert(MBBIter, offsetMBB);
20262 MF->insert(MBBIter, overflowMBB);
20263 MF->insert(MBBIter, endMBB);
20265 // Transfer the remainder of MBB and its successor edges to endMBB.
20266 endMBB->splice(endMBB->begin(), thisMBB,
20267 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
20268 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
20270 // Make offsetMBB and overflowMBB successors of thisMBB
20271 thisMBB->addSuccessor(offsetMBB);
20272 thisMBB->addSuccessor(overflowMBB);
20274 // endMBB is a successor of both offsetMBB and overflowMBB
20275 offsetMBB->addSuccessor(endMBB);
20276 overflowMBB->addSuccessor(endMBB);
20278 // Load the offset value into a register
20279 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20280 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
20284 .addDisp(Disp, UseFPOffset ? 4 : 0)
20285 .addOperand(Segment)
20286 .setMemRefs(MMOBegin, MMOEnd);
20288 // Check if there is enough room left to pull this argument.
20289 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
20291 .addImm(MaxOffset + 8 - ArgSizeA8);
20293 // Branch to "overflowMBB" if offset >= max
20294 // Fall through to "offsetMBB" otherwise
20295 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
20296 .addMBB(overflowMBB);
20299 // In offsetMBB, emit code to use the reg_save_area.
20301 assert(OffsetReg != 0);
20303 // Read the reg_save_area address.
20304 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
20305 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
20310 .addOperand(Segment)
20311 .setMemRefs(MMOBegin, MMOEnd);
20313 // Zero-extend the offset
20314 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
20315 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
20318 .addImm(X86::sub_32bit);
20320 // Add the offset to the reg_save_area to get the final address.
20321 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
20322 .addReg(OffsetReg64)
20323 .addReg(RegSaveReg);
20325 // Compute the offset for the next argument
20326 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20327 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
20329 .addImm(UseFPOffset ? 16 : 8);
20331 // Store it back into the va_list.
20332 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
20336 .addDisp(Disp, UseFPOffset ? 4 : 0)
20337 .addOperand(Segment)
20338 .addReg(NextOffsetReg)
20339 .setMemRefs(MMOBegin, MMOEnd);
20342 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
20347 // Emit code to use overflow area
20350 // Load the overflow_area address into a register.
20351 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
20352 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
20357 .addOperand(Segment)
20358 .setMemRefs(MMOBegin, MMOEnd);
20360 // If we need to align it, do so. Otherwise, just copy the address
20361 // to OverflowDestReg.
20363 // Align the overflow address
20364 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
20365 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
20367 // aligned_addr = (addr + (align-1)) & ~(align-1)
20368 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
20369 .addReg(OverflowAddrReg)
20372 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
20374 .addImm(~(uint64_t)(Align-1));
20376 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
20377 .addReg(OverflowAddrReg);
20380 // Compute the next overflow address after this argument.
20381 // (the overflow address should be kept 8-byte aligned)
20382 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
20383 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
20384 .addReg(OverflowDestReg)
20385 .addImm(ArgSizeA8);
20387 // Store the new overflow address.
20388 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
20393 .addOperand(Segment)
20394 .addReg(NextAddrReg)
20395 .setMemRefs(MMOBegin, MMOEnd);
20397 // If we branched, emit the PHI to the front of endMBB.
20399 BuildMI(*endMBB, endMBB->begin(), DL,
20400 TII->get(X86::PHI), DestReg)
20401 .addReg(OffsetDestReg).addMBB(offsetMBB)
20402 .addReg(OverflowDestReg).addMBB(overflowMBB);
20405 // Erase the pseudo instruction
20406 MI->eraseFromParent();
20411 MachineBasicBlock *
20412 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
20414 MachineBasicBlock *MBB) const {
20415 // Emit code to save XMM registers to the stack. The ABI says that the
20416 // number of registers to save is given in %al, so it's theoretically
20417 // possible to do an indirect jump trick to avoid saving all of them,
20418 // however this code takes a simpler approach and just executes all
20419 // of the stores if %al is non-zero. It's less code, and it's probably
20420 // easier on the hardware branch predictor, and stores aren't all that
20421 // expensive anyway.
20423 // Create the new basic blocks. One block contains all the XMM stores,
20424 // and one block is the final destination regardless of whether any
20425 // stores were performed.
20426 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20427 MachineFunction *F = MBB->getParent();
20428 MachineFunction::iterator MBBIter = MBB;
20430 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
20431 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
20432 F->insert(MBBIter, XMMSaveMBB);
20433 F->insert(MBBIter, EndMBB);
20435 // Transfer the remainder of MBB and its successor edges to EndMBB.
20436 EndMBB->splice(EndMBB->begin(), MBB,
20437 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20438 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
20440 // The original block will now fall through to the XMM save block.
20441 MBB->addSuccessor(XMMSaveMBB);
20442 // The XMMSaveMBB will fall through to the end block.
20443 XMMSaveMBB->addSuccessor(EndMBB);
20445 // Now add the instructions.
20446 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
20447 DebugLoc DL = MI->getDebugLoc();
20449 unsigned CountReg = MI->getOperand(0).getReg();
20450 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
20451 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
20453 if (!Subtarget->isTargetWin64()) {
20454 // If %al is 0, branch around the XMM save block.
20455 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
20456 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
20457 MBB->addSuccessor(EndMBB);
20460 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
20461 // that was just emitted, but clearly shouldn't be "saved".
20462 assert((MI->getNumOperands() <= 3 ||
20463 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
20464 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
20465 && "Expected last argument to be EFLAGS");
20466 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
20467 // In the XMM save block, save all the XMM argument registers.
20468 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
20469 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
20470 MachineMemOperand *MMO =
20471 F->getMachineMemOperand(
20472 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
20473 MachineMemOperand::MOStore,
20474 /*Size=*/16, /*Align=*/16);
20475 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
20476 .addFrameIndex(RegSaveFrameIndex)
20477 .addImm(/*Scale=*/1)
20478 .addReg(/*IndexReg=*/0)
20479 .addImm(/*Disp=*/Offset)
20480 .addReg(/*Segment=*/0)
20481 .addReg(MI->getOperand(i).getReg())
20482 .addMemOperand(MMO);
20485 MI->eraseFromParent(); // The pseudo instruction is gone now.
20490 // The EFLAGS operand of SelectItr might be missing a kill marker
20491 // because there were multiple uses of EFLAGS, and ISel didn't know
20492 // which to mark. Figure out whether SelectItr should have had a
20493 // kill marker, and set it if it should. Returns the correct kill
20495 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
20496 MachineBasicBlock* BB,
20497 const TargetRegisterInfo* TRI) {
20498 // Scan forward through BB for a use/def of EFLAGS.
20499 MachineBasicBlock::iterator miI(std::next(SelectItr));
20500 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
20501 const MachineInstr& mi = *miI;
20502 if (mi.readsRegister(X86::EFLAGS))
20504 if (mi.definesRegister(X86::EFLAGS))
20505 break; // Should have kill-flag - update below.
20508 // If we hit the end of the block, check whether EFLAGS is live into a
20510 if (miI == BB->end()) {
20511 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
20512 sEnd = BB->succ_end();
20513 sItr != sEnd; ++sItr) {
20514 MachineBasicBlock* succ = *sItr;
20515 if (succ->isLiveIn(X86::EFLAGS))
20520 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
20521 // out. SelectMI should have a kill flag on EFLAGS.
20522 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
20526 MachineBasicBlock *
20527 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
20528 MachineBasicBlock *BB) const {
20529 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
20530 DebugLoc DL = MI->getDebugLoc();
20532 // To "insert" a SELECT_CC instruction, we actually have to insert the
20533 // diamond control-flow pattern. The incoming instruction knows the
20534 // destination vreg to set, the condition code register to branch on, the
20535 // true/false values to select between, and a branch opcode to use.
20536 const BasicBlock *LLVM_BB = BB->getBasicBlock();
20537 MachineFunction::iterator It = BB;
20543 // cmpTY ccX, r1, r2
20545 // fallthrough --> copy0MBB
20546 MachineBasicBlock *thisMBB = BB;
20547 MachineFunction *F = BB->getParent();
20548 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
20549 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
20550 F->insert(It, copy0MBB);
20551 F->insert(It, sinkMBB);
20553 // If the EFLAGS register isn't dead in the terminator, then claim that it's
20554 // live into the sink and copy blocks.
20555 const TargetRegisterInfo *TRI =
20556 BB->getParent()->getSubtarget().getRegisterInfo();
20557 if (!MI->killsRegister(X86::EFLAGS) &&
20558 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
20559 copy0MBB->addLiveIn(X86::EFLAGS);
20560 sinkMBB->addLiveIn(X86::EFLAGS);
20563 // Transfer the remainder of BB and its successor edges to sinkMBB.
20564 sinkMBB->splice(sinkMBB->begin(), BB,
20565 std::next(MachineBasicBlock::iterator(MI)), BB->end());
20566 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
20568 // Add the true and fallthrough blocks as its successors.
20569 BB->addSuccessor(copy0MBB);
20570 BB->addSuccessor(sinkMBB);
20572 // Create the conditional branch instruction.
20574 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
20575 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
20578 // %FalseValue = ...
20579 // # fallthrough to sinkMBB
20580 copy0MBB->addSuccessor(sinkMBB);
20583 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
20585 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20586 TII->get(X86::PHI), MI->getOperand(0).getReg())
20587 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
20588 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
20590 MI->eraseFromParent(); // The pseudo instruction is gone now.
20594 MachineBasicBlock *
20595 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
20596 MachineBasicBlock *BB) const {
20597 MachineFunction *MF = BB->getParent();
20598 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
20599 DebugLoc DL = MI->getDebugLoc();
20600 const BasicBlock *LLVM_BB = BB->getBasicBlock();
20602 assert(MF->shouldSplitStack());
20604 const bool Is64Bit = Subtarget->is64Bit();
20605 const bool IsLP64 = Subtarget->isTarget64BitLP64();
20607 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
20608 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
20611 // ... [Till the alloca]
20612 // If stacklet is not large enough, jump to mallocMBB
20615 // Allocate by subtracting from RSP
20616 // Jump to continueMBB
20619 // Allocate by call to runtime
20623 // [rest of original BB]
20626 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20627 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20628 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20630 MachineRegisterInfo &MRI = MF->getRegInfo();
20631 const TargetRegisterClass *AddrRegClass =
20632 getRegClassFor(getPointerTy());
20634 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
20635 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
20636 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
20637 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
20638 sizeVReg = MI->getOperand(1).getReg(),
20639 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
20641 MachineFunction::iterator MBBIter = BB;
20644 MF->insert(MBBIter, bumpMBB);
20645 MF->insert(MBBIter, mallocMBB);
20646 MF->insert(MBBIter, continueMBB);
20648 continueMBB->splice(continueMBB->begin(), BB,
20649 std::next(MachineBasicBlock::iterator(MI)), BB->end());
20650 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
20652 // Add code to the main basic block to check if the stack limit has been hit,
20653 // and if so, jump to mallocMBB otherwise to bumpMBB.
20654 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
20655 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
20656 .addReg(tmpSPVReg).addReg(sizeVReg);
20657 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
20658 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
20659 .addReg(SPLimitVReg);
20660 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
20662 // bumpMBB simply decreases the stack pointer, since we know the current
20663 // stacklet has enough space.
20664 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
20665 .addReg(SPLimitVReg);
20666 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
20667 .addReg(SPLimitVReg);
20668 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
20670 // Calls into a routine in libgcc to allocate more space from the heap.
20671 const uint32_t *RegMask = MF->getTarget()
20672 .getSubtargetImpl()
20673 ->getRegisterInfo()
20674 ->getCallPreservedMask(CallingConv::C);
20676 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
20678 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
20679 .addExternalSymbol("__morestack_allocate_stack_space")
20680 .addRegMask(RegMask)
20681 .addReg(X86::RDI, RegState::Implicit)
20682 .addReg(X86::RAX, RegState::ImplicitDefine);
20683 } else if (Is64Bit) {
20684 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
20686 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
20687 .addExternalSymbol("__morestack_allocate_stack_space")
20688 .addRegMask(RegMask)
20689 .addReg(X86::EDI, RegState::Implicit)
20690 .addReg(X86::EAX, RegState::ImplicitDefine);
20692 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
20694 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
20695 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
20696 .addExternalSymbol("__morestack_allocate_stack_space")
20697 .addRegMask(RegMask)
20698 .addReg(X86::EAX, RegState::ImplicitDefine);
20702 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
20705 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
20706 .addReg(IsLP64 ? X86::RAX : X86::EAX);
20707 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
20709 // Set up the CFG correctly.
20710 BB->addSuccessor(bumpMBB);
20711 BB->addSuccessor(mallocMBB);
20712 mallocMBB->addSuccessor(continueMBB);
20713 bumpMBB->addSuccessor(continueMBB);
20715 // Take care of the PHI nodes.
20716 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
20717 MI->getOperand(0).getReg())
20718 .addReg(mallocPtrVReg).addMBB(mallocMBB)
20719 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
20721 // Delete the original pseudo instruction.
20722 MI->eraseFromParent();
20725 return continueMBB;
20728 MachineBasicBlock *
20729 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
20730 MachineBasicBlock *BB) const {
20731 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
20732 DebugLoc DL = MI->getDebugLoc();
20734 assert(!Subtarget->isTargetMachO());
20736 // The lowering is pretty easy: we're just emitting the call to _alloca. The
20737 // non-trivial part is impdef of ESP.
20739 if (Subtarget->isTargetWin64()) {
20740 if (Subtarget->isTargetCygMing()) {
20741 // ___chkstk(Mingw64):
20742 // Clobbers R10, R11, RAX and EFLAGS.
20744 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
20745 .addExternalSymbol("___chkstk")
20746 .addReg(X86::RAX, RegState::Implicit)
20747 .addReg(X86::RSP, RegState::Implicit)
20748 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
20749 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
20750 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20752 // __chkstk(MSVCRT): does not update stack pointer.
20753 // Clobbers R10, R11 and EFLAGS.
20754 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
20755 .addExternalSymbol("__chkstk")
20756 .addReg(X86::RAX, RegState::Implicit)
20757 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20758 // RAX has the offset to be subtracted from RSP.
20759 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
20764 const char *StackProbeSymbol = (Subtarget->isTargetKnownWindowsMSVC() ||
20765 Subtarget->isTargetWindowsItanium())
20769 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
20770 .addExternalSymbol(StackProbeSymbol)
20771 .addReg(X86::EAX, RegState::Implicit)
20772 .addReg(X86::ESP, RegState::Implicit)
20773 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
20774 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
20775 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20778 MI->eraseFromParent(); // The pseudo instruction is gone now.
20782 MachineBasicBlock *
20783 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
20784 MachineBasicBlock *BB) const {
20785 // This is pretty easy. We're taking the value that we received from
20786 // our load from the relocation, sticking it in either RDI (x86-64)
20787 // or EAX and doing an indirect call. The return value will then
20788 // be in the normal return register.
20789 MachineFunction *F = BB->getParent();
20790 const X86InstrInfo *TII =
20791 static_cast<const X86InstrInfo *>(F->getSubtarget().getInstrInfo());
20792 DebugLoc DL = MI->getDebugLoc();
20794 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
20795 assert(MI->getOperand(3).isGlobal() && "This should be a global");
20797 // Get a register mask for the lowered call.
20798 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
20799 // proper register mask.
20800 const uint32_t *RegMask = F->getTarget()
20801 .getSubtargetImpl()
20802 ->getRegisterInfo()
20803 ->getCallPreservedMask(CallingConv::C);
20804 if (Subtarget->is64Bit()) {
20805 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20806 TII->get(X86::MOV64rm), X86::RDI)
20808 .addImm(0).addReg(0)
20809 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20810 MI->getOperand(3).getTargetFlags())
20812 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
20813 addDirectMem(MIB, X86::RDI);
20814 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
20815 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
20816 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20817 TII->get(X86::MOV32rm), X86::EAX)
20819 .addImm(0).addReg(0)
20820 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20821 MI->getOperand(3).getTargetFlags())
20823 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
20824 addDirectMem(MIB, X86::EAX);
20825 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
20827 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20828 TII->get(X86::MOV32rm), X86::EAX)
20829 .addReg(TII->getGlobalBaseReg(F))
20830 .addImm(0).addReg(0)
20831 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20832 MI->getOperand(3).getTargetFlags())
20834 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
20835 addDirectMem(MIB, X86::EAX);
20836 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
20839 MI->eraseFromParent(); // The pseudo instruction is gone now.
20843 MachineBasicBlock *
20844 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
20845 MachineBasicBlock *MBB) const {
20846 DebugLoc DL = MI->getDebugLoc();
20847 MachineFunction *MF = MBB->getParent();
20848 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
20849 MachineRegisterInfo &MRI = MF->getRegInfo();
20851 const BasicBlock *BB = MBB->getBasicBlock();
20852 MachineFunction::iterator I = MBB;
20855 // Memory Reference
20856 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20857 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20860 unsigned MemOpndSlot = 0;
20862 unsigned CurOp = 0;
20864 DstReg = MI->getOperand(CurOp++).getReg();
20865 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
20866 assert(RC->hasType(MVT::i32) && "Invalid destination!");
20867 unsigned mainDstReg = MRI.createVirtualRegister(RC);
20868 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
20870 MemOpndSlot = CurOp;
20872 MVT PVT = getPointerTy();
20873 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
20874 "Invalid Pointer Size!");
20876 // For v = setjmp(buf), we generate
20879 // buf[LabelOffset] = restoreMBB
20880 // SjLjSetup restoreMBB
20886 // v = phi(main, restore)
20889 // if base pointer being used, load it from frame
20892 MachineBasicBlock *thisMBB = MBB;
20893 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
20894 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
20895 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
20896 MF->insert(I, mainMBB);
20897 MF->insert(I, sinkMBB);
20898 MF->push_back(restoreMBB);
20900 MachineInstrBuilder MIB;
20902 // Transfer the remainder of BB and its successor edges to sinkMBB.
20903 sinkMBB->splice(sinkMBB->begin(), MBB,
20904 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20905 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
20908 unsigned PtrStoreOpc = 0;
20909 unsigned LabelReg = 0;
20910 const int64_t LabelOffset = 1 * PVT.getStoreSize();
20911 Reloc::Model RM = MF->getTarget().getRelocationModel();
20912 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
20913 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
20915 // Prepare IP either in reg or imm.
20916 if (!UseImmLabel) {
20917 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
20918 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
20919 LabelReg = MRI.createVirtualRegister(PtrRC);
20920 if (Subtarget->is64Bit()) {
20921 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
20925 .addMBB(restoreMBB)
20928 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
20929 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
20930 .addReg(XII->getGlobalBaseReg(MF))
20933 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
20937 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
20939 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
20940 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
20941 if (i == X86::AddrDisp)
20942 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
20944 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
20947 MIB.addReg(LabelReg);
20949 MIB.addMBB(restoreMBB);
20950 MIB.setMemRefs(MMOBegin, MMOEnd);
20952 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
20953 .addMBB(restoreMBB);
20955 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
20956 MF->getSubtarget().getRegisterInfo());
20957 MIB.addRegMask(RegInfo->getNoPreservedMask());
20958 thisMBB->addSuccessor(mainMBB);
20959 thisMBB->addSuccessor(restoreMBB);
20963 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
20964 mainMBB->addSuccessor(sinkMBB);
20967 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20968 TII->get(X86::PHI), DstReg)
20969 .addReg(mainDstReg).addMBB(mainMBB)
20970 .addReg(restoreDstReg).addMBB(restoreMBB);
20973 if (RegInfo->hasBasePointer(*MF)) {
20974 const X86Subtarget &STI = MF->getTarget().getSubtarget<X86Subtarget>();
20975 const bool Uses64BitFramePtr = STI.isTarget64BitLP64() || STI.isTargetNaCl64();
20976 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
20977 X86FI->setRestoreBasePointer(MF);
20978 unsigned FramePtr = RegInfo->getFrameRegister(*MF);
20979 unsigned BasePtr = RegInfo->getBaseRegister();
20980 unsigned Opm = Uses64BitFramePtr ? X86::MOV64rm : X86::MOV32rm;
20981 addRegOffset(BuildMI(restoreMBB, DL, TII->get(Opm), BasePtr),
20982 FramePtr, true, X86FI->getRestoreBasePointerOffset())
20983 .setMIFlag(MachineInstr::FrameSetup);
20985 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
20986 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
20987 restoreMBB->addSuccessor(sinkMBB);
20989 MI->eraseFromParent();
20993 MachineBasicBlock *
20994 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
20995 MachineBasicBlock *MBB) const {
20996 DebugLoc DL = MI->getDebugLoc();
20997 MachineFunction *MF = MBB->getParent();
20998 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
20999 MachineRegisterInfo &MRI = MF->getRegInfo();
21001 // Memory Reference
21002 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
21003 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
21005 MVT PVT = getPointerTy();
21006 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
21007 "Invalid Pointer Size!");
21009 const TargetRegisterClass *RC =
21010 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
21011 unsigned Tmp = MRI.createVirtualRegister(RC);
21012 // Since FP is only updated here but NOT referenced, it's treated as GPR.
21013 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
21014 MF->getSubtarget().getRegisterInfo());
21015 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
21016 unsigned SP = RegInfo->getStackRegister();
21018 MachineInstrBuilder MIB;
21020 const int64_t LabelOffset = 1 * PVT.getStoreSize();
21021 const int64_t SPOffset = 2 * PVT.getStoreSize();
21023 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
21024 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
21027 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
21028 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
21029 MIB.addOperand(MI->getOperand(i));
21030 MIB.setMemRefs(MMOBegin, MMOEnd);
21032 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
21033 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21034 if (i == X86::AddrDisp)
21035 MIB.addDisp(MI->getOperand(i), LabelOffset);
21037 MIB.addOperand(MI->getOperand(i));
21039 MIB.setMemRefs(MMOBegin, MMOEnd);
21041 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
21042 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21043 if (i == X86::AddrDisp)
21044 MIB.addDisp(MI->getOperand(i), SPOffset);
21046 MIB.addOperand(MI->getOperand(i));
21048 MIB.setMemRefs(MMOBegin, MMOEnd);
21050 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
21052 MI->eraseFromParent();
21056 // Replace 213-type (isel default) FMA3 instructions with 231-type for
21057 // accumulator loops. Writing back to the accumulator allows the coalescer
21058 // to remove extra copies in the loop.
21059 MachineBasicBlock *
21060 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
21061 MachineBasicBlock *MBB) const {
21062 MachineOperand &AddendOp = MI->getOperand(3);
21064 // Bail out early if the addend isn't a register - we can't switch these.
21065 if (!AddendOp.isReg())
21068 MachineFunction &MF = *MBB->getParent();
21069 MachineRegisterInfo &MRI = MF.getRegInfo();
21071 // Check whether the addend is defined by a PHI:
21072 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
21073 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
21074 if (!AddendDef.isPHI())
21077 // Look for the following pattern:
21079 // %addend = phi [%entry, 0], [%loop, %result]
21081 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
21085 // %addend = phi [%entry, 0], [%loop, %result]
21087 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
21089 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
21090 assert(AddendDef.getOperand(i).isReg());
21091 MachineOperand PHISrcOp = AddendDef.getOperand(i);
21092 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
21093 if (&PHISrcInst == MI) {
21094 // Found a matching instruction.
21095 unsigned NewFMAOpc = 0;
21096 switch (MI->getOpcode()) {
21097 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
21098 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
21099 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
21100 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
21101 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
21102 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
21103 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
21104 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
21105 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
21106 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
21107 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
21108 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
21109 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
21110 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
21111 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
21112 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
21113 case X86::VFMADDSUBPDr213r: NewFMAOpc = X86::VFMADDSUBPDr231r; break;
21114 case X86::VFMADDSUBPSr213r: NewFMAOpc = X86::VFMADDSUBPSr231r; break;
21115 case X86::VFMSUBADDPDr213r: NewFMAOpc = X86::VFMSUBADDPDr231r; break;
21116 case X86::VFMSUBADDPSr213r: NewFMAOpc = X86::VFMSUBADDPSr231r; break;
21118 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
21119 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
21120 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
21121 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
21122 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
21123 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
21124 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
21125 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
21126 case X86::VFMADDSUBPDr213rY: NewFMAOpc = X86::VFMADDSUBPDr231rY; break;
21127 case X86::VFMADDSUBPSr213rY: NewFMAOpc = X86::VFMADDSUBPSr231rY; break;
21128 case X86::VFMSUBADDPDr213rY: NewFMAOpc = X86::VFMSUBADDPDr231rY; break;
21129 case X86::VFMSUBADDPSr213rY: NewFMAOpc = X86::VFMSUBADDPSr231rY; break;
21130 default: llvm_unreachable("Unrecognized FMA variant.");
21133 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
21134 MachineInstrBuilder MIB =
21135 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
21136 .addOperand(MI->getOperand(0))
21137 .addOperand(MI->getOperand(3))
21138 .addOperand(MI->getOperand(2))
21139 .addOperand(MI->getOperand(1));
21140 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
21141 MI->eraseFromParent();
21148 MachineBasicBlock *
21149 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
21150 MachineBasicBlock *BB) const {
21151 switch (MI->getOpcode()) {
21152 default: llvm_unreachable("Unexpected instr type to insert");
21153 case X86::TAILJMPd64:
21154 case X86::TAILJMPr64:
21155 case X86::TAILJMPm64:
21156 llvm_unreachable("TAILJMP64 would not be touched here.");
21157 case X86::TCRETURNdi64:
21158 case X86::TCRETURNri64:
21159 case X86::TCRETURNmi64:
21161 case X86::WIN_ALLOCA:
21162 return EmitLoweredWinAlloca(MI, BB);
21163 case X86::SEG_ALLOCA_32:
21164 case X86::SEG_ALLOCA_64:
21165 return EmitLoweredSegAlloca(MI, BB);
21166 case X86::TLSCall_32:
21167 case X86::TLSCall_64:
21168 return EmitLoweredTLSCall(MI, BB);
21169 case X86::CMOV_GR8:
21170 case X86::CMOV_FR32:
21171 case X86::CMOV_FR64:
21172 case X86::CMOV_V4F32:
21173 case X86::CMOV_V2F64:
21174 case X86::CMOV_V2I64:
21175 case X86::CMOV_V8F32:
21176 case X86::CMOV_V4F64:
21177 case X86::CMOV_V4I64:
21178 case X86::CMOV_V16F32:
21179 case X86::CMOV_V8F64:
21180 case X86::CMOV_V8I64:
21181 case X86::CMOV_GR16:
21182 case X86::CMOV_GR32:
21183 case X86::CMOV_RFP32:
21184 case X86::CMOV_RFP64:
21185 case X86::CMOV_RFP80:
21186 return EmitLoweredSelect(MI, BB);
21188 case X86::FP32_TO_INT16_IN_MEM:
21189 case X86::FP32_TO_INT32_IN_MEM:
21190 case X86::FP32_TO_INT64_IN_MEM:
21191 case X86::FP64_TO_INT16_IN_MEM:
21192 case X86::FP64_TO_INT32_IN_MEM:
21193 case X86::FP64_TO_INT64_IN_MEM:
21194 case X86::FP80_TO_INT16_IN_MEM:
21195 case X86::FP80_TO_INT32_IN_MEM:
21196 case X86::FP80_TO_INT64_IN_MEM: {
21197 MachineFunction *F = BB->getParent();
21198 const TargetInstrInfo *TII = F->getSubtarget().getInstrInfo();
21199 DebugLoc DL = MI->getDebugLoc();
21201 // Change the floating point control register to use "round towards zero"
21202 // mode when truncating to an integer value.
21203 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
21204 addFrameReference(BuildMI(*BB, MI, DL,
21205 TII->get(X86::FNSTCW16m)), CWFrameIdx);
21207 // Load the old value of the high byte of the control word...
21209 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
21210 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
21213 // Set the high part to be round to zero...
21214 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
21217 // Reload the modified control word now...
21218 addFrameReference(BuildMI(*BB, MI, DL,
21219 TII->get(X86::FLDCW16m)), CWFrameIdx);
21221 // Restore the memory image of control word to original value
21222 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
21225 // Get the X86 opcode to use.
21227 switch (MI->getOpcode()) {
21228 default: llvm_unreachable("illegal opcode!");
21229 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
21230 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
21231 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
21232 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
21233 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
21234 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
21235 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
21236 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
21237 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
21241 MachineOperand &Op = MI->getOperand(0);
21243 AM.BaseType = X86AddressMode::RegBase;
21244 AM.Base.Reg = Op.getReg();
21246 AM.BaseType = X86AddressMode::FrameIndexBase;
21247 AM.Base.FrameIndex = Op.getIndex();
21249 Op = MI->getOperand(1);
21251 AM.Scale = Op.getImm();
21252 Op = MI->getOperand(2);
21254 AM.IndexReg = Op.getImm();
21255 Op = MI->getOperand(3);
21256 if (Op.isGlobal()) {
21257 AM.GV = Op.getGlobal();
21259 AM.Disp = Op.getImm();
21261 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
21262 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
21264 // Reload the original control word now.
21265 addFrameReference(BuildMI(*BB, MI, DL,
21266 TII->get(X86::FLDCW16m)), CWFrameIdx);
21268 MI->eraseFromParent(); // The pseudo instruction is gone now.
21271 // String/text processing lowering.
21272 case X86::PCMPISTRM128REG:
21273 case X86::VPCMPISTRM128REG:
21274 case X86::PCMPISTRM128MEM:
21275 case X86::VPCMPISTRM128MEM:
21276 case X86::PCMPESTRM128REG:
21277 case X86::VPCMPESTRM128REG:
21278 case X86::PCMPESTRM128MEM:
21279 case X86::VPCMPESTRM128MEM:
21280 assert(Subtarget->hasSSE42() &&
21281 "Target must have SSE4.2 or AVX features enabled");
21282 return EmitPCMPSTRM(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
21284 // String/text processing lowering.
21285 case X86::PCMPISTRIREG:
21286 case X86::VPCMPISTRIREG:
21287 case X86::PCMPISTRIMEM:
21288 case X86::VPCMPISTRIMEM:
21289 case X86::PCMPESTRIREG:
21290 case X86::VPCMPESTRIREG:
21291 case X86::PCMPESTRIMEM:
21292 case X86::VPCMPESTRIMEM:
21293 assert(Subtarget->hasSSE42() &&
21294 "Target must have SSE4.2 or AVX features enabled");
21295 return EmitPCMPSTRI(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
21297 // Thread synchronization.
21299 return EmitMonitor(MI, BB, BB->getParent()->getSubtarget().getInstrInfo(),
21304 return EmitXBegin(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
21306 case X86::VASTART_SAVE_XMM_REGS:
21307 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
21309 case X86::VAARG_64:
21310 return EmitVAARG64WithCustomInserter(MI, BB);
21312 case X86::EH_SjLj_SetJmp32:
21313 case X86::EH_SjLj_SetJmp64:
21314 return emitEHSjLjSetJmp(MI, BB);
21316 case X86::EH_SjLj_LongJmp32:
21317 case X86::EH_SjLj_LongJmp64:
21318 return emitEHSjLjLongJmp(MI, BB);
21320 case TargetOpcode::STATEPOINT:
21321 // As an implementation detail, STATEPOINT shares the STACKMAP format at
21322 // this point in the process. We diverge later.
21323 return emitPatchPoint(MI, BB);
21325 case TargetOpcode::STACKMAP:
21326 case TargetOpcode::PATCHPOINT:
21327 return emitPatchPoint(MI, BB);
21329 case X86::VFMADDPDr213r:
21330 case X86::VFMADDPSr213r:
21331 case X86::VFMADDSDr213r:
21332 case X86::VFMADDSSr213r:
21333 case X86::VFMSUBPDr213r:
21334 case X86::VFMSUBPSr213r:
21335 case X86::VFMSUBSDr213r:
21336 case X86::VFMSUBSSr213r:
21337 case X86::VFNMADDPDr213r:
21338 case X86::VFNMADDPSr213r:
21339 case X86::VFNMADDSDr213r:
21340 case X86::VFNMADDSSr213r:
21341 case X86::VFNMSUBPDr213r:
21342 case X86::VFNMSUBPSr213r:
21343 case X86::VFNMSUBSDr213r:
21344 case X86::VFNMSUBSSr213r:
21345 case X86::VFMADDSUBPDr213r:
21346 case X86::VFMADDSUBPSr213r:
21347 case X86::VFMSUBADDPDr213r:
21348 case X86::VFMSUBADDPSr213r:
21349 case X86::VFMADDPDr213rY:
21350 case X86::VFMADDPSr213rY:
21351 case X86::VFMSUBPDr213rY:
21352 case X86::VFMSUBPSr213rY:
21353 case X86::VFNMADDPDr213rY:
21354 case X86::VFNMADDPSr213rY:
21355 case X86::VFNMSUBPDr213rY:
21356 case X86::VFNMSUBPSr213rY:
21357 case X86::VFMADDSUBPDr213rY:
21358 case X86::VFMADDSUBPSr213rY:
21359 case X86::VFMSUBADDPDr213rY:
21360 case X86::VFMSUBADDPSr213rY:
21361 return emitFMA3Instr(MI, BB);
21365 //===----------------------------------------------------------------------===//
21366 // X86 Optimization Hooks
21367 //===----------------------------------------------------------------------===//
21369 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
21372 const SelectionDAG &DAG,
21373 unsigned Depth) const {
21374 unsigned BitWidth = KnownZero.getBitWidth();
21375 unsigned Opc = Op.getOpcode();
21376 assert((Opc >= ISD::BUILTIN_OP_END ||
21377 Opc == ISD::INTRINSIC_WO_CHAIN ||
21378 Opc == ISD::INTRINSIC_W_CHAIN ||
21379 Opc == ISD::INTRINSIC_VOID) &&
21380 "Should use MaskedValueIsZero if you don't know whether Op"
21381 " is a target node!");
21383 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
21397 // These nodes' second result is a boolean.
21398 if (Op.getResNo() == 0)
21401 case X86ISD::SETCC:
21402 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
21404 case ISD::INTRINSIC_WO_CHAIN: {
21405 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
21406 unsigned NumLoBits = 0;
21409 case Intrinsic::x86_sse_movmsk_ps:
21410 case Intrinsic::x86_avx_movmsk_ps_256:
21411 case Intrinsic::x86_sse2_movmsk_pd:
21412 case Intrinsic::x86_avx_movmsk_pd_256:
21413 case Intrinsic::x86_mmx_pmovmskb:
21414 case Intrinsic::x86_sse2_pmovmskb_128:
21415 case Intrinsic::x86_avx2_pmovmskb: {
21416 // High bits of movmskp{s|d}, pmovmskb are known zero.
21418 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
21419 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
21420 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
21421 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
21422 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
21423 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
21424 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
21425 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
21427 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
21436 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
21438 const SelectionDAG &,
21439 unsigned Depth) const {
21440 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
21441 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
21442 return Op.getValueType().getScalarType().getSizeInBits();
21448 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
21449 /// node is a GlobalAddress + offset.
21450 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
21451 const GlobalValue* &GA,
21452 int64_t &Offset) const {
21453 if (N->getOpcode() == X86ISD::Wrapper) {
21454 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
21455 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
21456 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
21460 return TargetLowering::isGAPlusOffset(N, GA, Offset);
21463 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
21464 /// same as extracting the high 128-bit part of 256-bit vector and then
21465 /// inserting the result into the low part of a new 256-bit vector
21466 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
21467 EVT VT = SVOp->getValueType(0);
21468 unsigned NumElems = VT.getVectorNumElements();
21470 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
21471 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
21472 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
21473 SVOp->getMaskElt(j) >= 0)
21479 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
21480 /// same as extracting the low 128-bit part of 256-bit vector and then
21481 /// inserting the result into the high part of a new 256-bit vector
21482 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
21483 EVT VT = SVOp->getValueType(0);
21484 unsigned NumElems = VT.getVectorNumElements();
21486 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
21487 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
21488 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
21489 SVOp->getMaskElt(j) >= 0)
21495 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
21496 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
21497 TargetLowering::DAGCombinerInfo &DCI,
21498 const X86Subtarget* Subtarget) {
21500 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
21501 SDValue V1 = SVOp->getOperand(0);
21502 SDValue V2 = SVOp->getOperand(1);
21503 EVT VT = SVOp->getValueType(0);
21504 unsigned NumElems = VT.getVectorNumElements();
21506 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
21507 V2.getOpcode() == ISD::CONCAT_VECTORS) {
21511 // V UNDEF BUILD_VECTOR UNDEF
21513 // CONCAT_VECTOR CONCAT_VECTOR
21516 // RESULT: V + zero extended
21518 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
21519 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
21520 V1.getOperand(1).getOpcode() != ISD::UNDEF)
21523 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
21526 // To match the shuffle mask, the first half of the mask should
21527 // be exactly the first vector, and all the rest a splat with the
21528 // first element of the second one.
21529 for (unsigned i = 0; i != NumElems/2; ++i)
21530 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
21531 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
21534 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
21535 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
21536 if (Ld->hasNUsesOfValue(1, 0)) {
21537 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
21538 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
21540 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
21542 Ld->getPointerInfo(),
21543 Ld->getAlignment(),
21544 false/*isVolatile*/, true/*ReadMem*/,
21545 false/*WriteMem*/);
21547 // Make sure the newly-created LOAD is in the same position as Ld in
21548 // terms of dependency. We create a TokenFactor for Ld and ResNode,
21549 // and update uses of Ld's output chain to use the TokenFactor.
21550 if (Ld->hasAnyUseOfValue(1)) {
21551 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
21552 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
21553 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
21554 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
21555 SDValue(ResNode.getNode(), 1));
21558 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
21562 // Emit a zeroed vector and insert the desired subvector on its
21564 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
21565 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
21566 return DCI.CombineTo(N, InsV);
21569 //===--------------------------------------------------------------------===//
21570 // Combine some shuffles into subvector extracts and inserts:
21573 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
21574 if (isShuffleHigh128VectorInsertLow(SVOp)) {
21575 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
21576 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
21577 return DCI.CombineTo(N, InsV);
21580 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
21581 if (isShuffleLow128VectorInsertHigh(SVOp)) {
21582 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
21583 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
21584 return DCI.CombineTo(N, InsV);
21590 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
21593 /// This is the leaf of the recursive combinine below. When we have found some
21594 /// chain of single-use x86 shuffle instructions and accumulated the combined
21595 /// shuffle mask represented by them, this will try to pattern match that mask
21596 /// into either a single instruction if there is a special purpose instruction
21597 /// for this operation, or into a PSHUFB instruction which is a fully general
21598 /// instruction but should only be used to replace chains over a certain depth.
21599 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
21600 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
21601 TargetLowering::DAGCombinerInfo &DCI,
21602 const X86Subtarget *Subtarget) {
21603 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
21605 // Find the operand that enters the chain. Note that multiple uses are OK
21606 // here, we're not going to remove the operand we find.
21607 SDValue Input = Op.getOperand(0);
21608 while (Input.getOpcode() == ISD::BITCAST)
21609 Input = Input.getOperand(0);
21611 MVT VT = Input.getSimpleValueType();
21612 MVT RootVT = Root.getSimpleValueType();
21615 // Just remove no-op shuffle masks.
21616 if (Mask.size() == 1) {
21617 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Input),
21622 // Use the float domain if the operand type is a floating point type.
21623 bool FloatDomain = VT.isFloatingPoint();
21625 // For floating point shuffles, we don't have free copies in the shuffle
21626 // instructions or the ability to load as part of the instruction, so
21627 // canonicalize their shuffles to UNPCK or MOV variants.
21629 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
21630 // vectors because it can have a load folded into it that UNPCK cannot. This
21631 // doesn't preclude something switching to the shorter encoding post-RA.
21633 if (Mask.equals(0, 0) || Mask.equals(1, 1)) {
21634 bool Lo = Mask.equals(0, 0);
21637 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
21638 // is no slower than UNPCKLPD but has the option to fold the input operand
21639 // into even an unaligned memory load.
21640 if (Lo && Subtarget->hasSSE3()) {
21641 Shuffle = X86ISD::MOVDDUP;
21642 ShuffleVT = MVT::v2f64;
21644 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
21645 // than the UNPCK variants.
21646 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
21647 ShuffleVT = MVT::v4f32;
21649 if (Depth == 1 && Root->getOpcode() == Shuffle)
21650 return false; // Nothing to do!
21651 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21652 DCI.AddToWorklist(Op.getNode());
21653 if (Shuffle == X86ISD::MOVDDUP)
21654 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
21656 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21657 DCI.AddToWorklist(Op.getNode());
21658 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21662 if (Subtarget->hasSSE3() &&
21663 (Mask.equals(0, 0, 2, 2) || Mask.equals(1, 1, 3, 3))) {
21664 bool Lo = Mask.equals(0, 0, 2, 2);
21665 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
21666 MVT ShuffleVT = MVT::v4f32;
21667 if (Depth == 1 && Root->getOpcode() == Shuffle)
21668 return false; // Nothing to do!
21669 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21670 DCI.AddToWorklist(Op.getNode());
21671 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
21672 DCI.AddToWorklist(Op.getNode());
21673 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21677 if (Mask.equals(0, 0, 1, 1) || Mask.equals(2, 2, 3, 3)) {
21678 bool Lo = Mask.equals(0, 0, 1, 1);
21679 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
21680 MVT ShuffleVT = MVT::v4f32;
21681 if (Depth == 1 && Root->getOpcode() == Shuffle)
21682 return false; // Nothing to do!
21683 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21684 DCI.AddToWorklist(Op.getNode());
21685 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21686 DCI.AddToWorklist(Op.getNode());
21687 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21693 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
21694 // variants as none of these have single-instruction variants that are
21695 // superior to the UNPCK formulation.
21696 if (!FloatDomain &&
21697 (Mask.equals(0, 0, 1, 1, 2, 2, 3, 3) ||
21698 Mask.equals(4, 4, 5, 5, 6, 6, 7, 7) ||
21699 Mask.equals(0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7) ||
21700 Mask.equals(8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15,
21702 bool Lo = Mask[0] == 0;
21703 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
21704 if (Depth == 1 && Root->getOpcode() == Shuffle)
21705 return false; // Nothing to do!
21707 switch (Mask.size()) {
21709 ShuffleVT = MVT::v8i16;
21712 ShuffleVT = MVT::v16i8;
21715 llvm_unreachable("Impossible mask size!");
21717 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21718 DCI.AddToWorklist(Op.getNode());
21719 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21720 DCI.AddToWorklist(Op.getNode());
21721 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21726 // Don't try to re-form single instruction chains under any circumstances now
21727 // that we've done encoding canonicalization for them.
21731 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
21732 // can replace them with a single PSHUFB instruction profitably. Intel's
21733 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
21734 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
21735 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
21736 SmallVector<SDValue, 16> PSHUFBMask;
21737 assert(Mask.size() <= 16 && "Can't shuffle elements smaller than bytes!");
21738 int Ratio = 16 / Mask.size();
21739 for (unsigned i = 0; i < 16; ++i) {
21740 if (Mask[i / Ratio] == SM_SentinelUndef) {
21741 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
21744 int M = Mask[i / Ratio] != SM_SentinelZero
21745 ? Ratio * Mask[i / Ratio] + i % Ratio
21747 PSHUFBMask.push_back(DAG.getConstant(M, MVT::i8));
21749 Op = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Input);
21750 DCI.AddToWorklist(Op.getNode());
21751 SDValue PSHUFBMaskOp =
21752 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, PSHUFBMask);
21753 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
21754 Op = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, Op, PSHUFBMaskOp);
21755 DCI.AddToWorklist(Op.getNode());
21756 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21761 // Failed to find any combines.
21765 /// \brief Fully generic combining of x86 shuffle instructions.
21767 /// This should be the last combine run over the x86 shuffle instructions. Once
21768 /// they have been fully optimized, this will recursively consider all chains
21769 /// of single-use shuffle instructions, build a generic model of the cumulative
21770 /// shuffle operation, and check for simpler instructions which implement this
21771 /// operation. We use this primarily for two purposes:
21773 /// 1) Collapse generic shuffles to specialized single instructions when
21774 /// equivalent. In most cases, this is just an encoding size win, but
21775 /// sometimes we will collapse multiple generic shuffles into a single
21776 /// special-purpose shuffle.
21777 /// 2) Look for sequences of shuffle instructions with 3 or more total
21778 /// instructions, and replace them with the slightly more expensive SSSE3
21779 /// PSHUFB instruction if available. We do this as the last combining step
21780 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
21781 /// a suitable short sequence of other instructions. The PHUFB will either
21782 /// use a register or have to read from memory and so is slightly (but only
21783 /// slightly) more expensive than the other shuffle instructions.
21785 /// Because this is inherently a quadratic operation (for each shuffle in
21786 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
21787 /// This should never be an issue in practice as the shuffle lowering doesn't
21788 /// produce sequences of more than 8 instructions.
21790 /// FIXME: We will currently miss some cases where the redundant shuffling
21791 /// would simplify under the threshold for PSHUFB formation because of
21792 /// combine-ordering. To fix this, we should do the redundant instruction
21793 /// combining in this recursive walk.
21794 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
21795 ArrayRef<int> RootMask,
21796 int Depth, bool HasPSHUFB,
21798 TargetLowering::DAGCombinerInfo &DCI,
21799 const X86Subtarget *Subtarget) {
21800 // Bound the depth of our recursive combine because this is ultimately
21801 // quadratic in nature.
21805 // Directly rip through bitcasts to find the underlying operand.
21806 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
21807 Op = Op.getOperand(0);
21809 MVT VT = Op.getSimpleValueType();
21810 if (!VT.isVector())
21811 return false; // Bail if we hit a non-vector.
21812 // FIXME: This routine should be taught about 256-bit shuffles, or a 256-bit
21813 // version should be added.
21814 if (VT.getSizeInBits() != 128)
21817 assert(Root.getSimpleValueType().isVector() &&
21818 "Shuffles operate on vector types!");
21819 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
21820 "Can only combine shuffles of the same vector register size.");
21822 if (!isTargetShuffle(Op.getOpcode()))
21824 SmallVector<int, 16> OpMask;
21826 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
21827 // We only can combine unary shuffles which we can decode the mask for.
21828 if (!HaveMask || !IsUnary)
21831 assert(VT.getVectorNumElements() == OpMask.size() &&
21832 "Different mask size from vector size!");
21833 assert(((RootMask.size() > OpMask.size() &&
21834 RootMask.size() % OpMask.size() == 0) ||
21835 (OpMask.size() > RootMask.size() &&
21836 OpMask.size() % RootMask.size() == 0) ||
21837 OpMask.size() == RootMask.size()) &&
21838 "The smaller number of elements must divide the larger.");
21839 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
21840 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
21841 assert(((RootRatio == 1 && OpRatio == 1) ||
21842 (RootRatio == 1) != (OpRatio == 1)) &&
21843 "Must not have a ratio for both incoming and op masks!");
21845 SmallVector<int, 16> Mask;
21846 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
21848 // Merge this shuffle operation's mask into our accumulated mask. Note that
21849 // this shuffle's mask will be the first applied to the input, followed by the
21850 // root mask to get us all the way to the root value arrangement. The reason
21851 // for this order is that we are recursing up the operation chain.
21852 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
21853 int RootIdx = i / RootRatio;
21854 if (RootMask[RootIdx] < 0) {
21855 // This is a zero or undef lane, we're done.
21856 Mask.push_back(RootMask[RootIdx]);
21860 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
21861 int OpIdx = RootMaskedIdx / OpRatio;
21862 if (OpMask[OpIdx] < 0) {
21863 // The incoming lanes are zero or undef, it doesn't matter which ones we
21865 Mask.push_back(OpMask[OpIdx]);
21869 // Ok, we have non-zero lanes, map them through.
21870 Mask.push_back(OpMask[OpIdx] * OpRatio +
21871 RootMaskedIdx % OpRatio);
21874 // See if we can recurse into the operand to combine more things.
21875 switch (Op.getOpcode()) {
21876 case X86ISD::PSHUFB:
21878 case X86ISD::PSHUFD:
21879 case X86ISD::PSHUFHW:
21880 case X86ISD::PSHUFLW:
21881 if (Op.getOperand(0).hasOneUse() &&
21882 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
21883 HasPSHUFB, DAG, DCI, Subtarget))
21887 case X86ISD::UNPCKL:
21888 case X86ISD::UNPCKH:
21889 assert(Op.getOperand(0) == Op.getOperand(1) && "We only combine unary shuffles!");
21890 // We can't check for single use, we have to check that this shuffle is the only user.
21891 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
21892 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
21893 HasPSHUFB, DAG, DCI, Subtarget))
21898 // Minor canonicalization of the accumulated shuffle mask to make it easier
21899 // to match below. All this does is detect masks with squential pairs of
21900 // elements, and shrink them to the half-width mask. It does this in a loop
21901 // so it will reduce the size of the mask to the minimal width mask which
21902 // performs an equivalent shuffle.
21903 SmallVector<int, 16> WidenedMask;
21904 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
21905 Mask = std::move(WidenedMask);
21906 WidenedMask.clear();
21909 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
21913 /// \brief Get the PSHUF-style mask from PSHUF node.
21915 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
21916 /// PSHUF-style masks that can be reused with such instructions.
21917 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
21918 SmallVector<int, 4> Mask;
21920 bool HaveMask = getTargetShuffleMask(N.getNode(), N.getSimpleValueType(), Mask, IsUnary);
21924 switch (N.getOpcode()) {
21925 case X86ISD::PSHUFD:
21927 case X86ISD::PSHUFLW:
21930 case X86ISD::PSHUFHW:
21931 Mask.erase(Mask.begin(), Mask.begin() + 4);
21932 for (int &M : Mask)
21936 llvm_unreachable("No valid shuffle instruction found!");
21940 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
21942 /// We walk up the chain and look for a combinable shuffle, skipping over
21943 /// shuffles that we could hoist this shuffle's transformation past without
21944 /// altering anything.
21946 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
21948 TargetLowering::DAGCombinerInfo &DCI) {
21949 assert(N.getOpcode() == X86ISD::PSHUFD &&
21950 "Called with something other than an x86 128-bit half shuffle!");
21953 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
21954 // of the shuffles in the chain so that we can form a fresh chain to replace
21956 SmallVector<SDValue, 8> Chain;
21957 SDValue V = N.getOperand(0);
21958 for (; V.hasOneUse(); V = V.getOperand(0)) {
21959 switch (V.getOpcode()) {
21961 return SDValue(); // Nothing combined!
21964 // Skip bitcasts as we always know the type for the target specific
21968 case X86ISD::PSHUFD:
21969 // Found another dword shuffle.
21972 case X86ISD::PSHUFLW:
21973 // Check that the low words (being shuffled) are the identity in the
21974 // dword shuffle, and the high words are self-contained.
21975 if (Mask[0] != 0 || Mask[1] != 1 ||
21976 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
21979 Chain.push_back(V);
21982 case X86ISD::PSHUFHW:
21983 // Check that the high words (being shuffled) are the identity in the
21984 // dword shuffle, and the low words are self-contained.
21985 if (Mask[2] != 2 || Mask[3] != 3 ||
21986 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
21989 Chain.push_back(V);
21992 case X86ISD::UNPCKL:
21993 case X86ISD::UNPCKH:
21994 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
21995 // shuffle into a preceding word shuffle.
21996 if (V.getValueType() != MVT::v16i8 && V.getValueType() != MVT::v8i16)
21999 // Search for a half-shuffle which we can combine with.
22000 unsigned CombineOp =
22001 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
22002 if (V.getOperand(0) != V.getOperand(1) ||
22003 !V->isOnlyUserOf(V.getOperand(0).getNode()))
22005 Chain.push_back(V);
22006 V = V.getOperand(0);
22008 switch (V.getOpcode()) {
22010 return SDValue(); // Nothing to combine.
22012 case X86ISD::PSHUFLW:
22013 case X86ISD::PSHUFHW:
22014 if (V.getOpcode() == CombineOp)
22017 Chain.push_back(V);
22021 V = V.getOperand(0);
22025 } while (V.hasOneUse());
22028 // Break out of the loop if we break out of the switch.
22032 if (!V.hasOneUse())
22033 // We fell out of the loop without finding a viable combining instruction.
22036 // Merge this node's mask and our incoming mask.
22037 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22038 for (int &M : Mask)
22040 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
22041 getV4X86ShuffleImm8ForMask(Mask, DAG));
22043 // Rebuild the chain around this new shuffle.
22044 while (!Chain.empty()) {
22045 SDValue W = Chain.pop_back_val();
22047 if (V.getValueType() != W.getOperand(0).getValueType())
22048 V = DAG.getNode(ISD::BITCAST, DL, W.getOperand(0).getValueType(), V);
22050 switch (W.getOpcode()) {
22052 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
22054 case X86ISD::UNPCKL:
22055 case X86ISD::UNPCKH:
22056 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
22059 case X86ISD::PSHUFD:
22060 case X86ISD::PSHUFLW:
22061 case X86ISD::PSHUFHW:
22062 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
22066 if (V.getValueType() != N.getValueType())
22067 V = DAG.getNode(ISD::BITCAST, DL, N.getValueType(), V);
22069 // Return the new chain to replace N.
22073 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
22075 /// We walk up the chain, skipping shuffles of the other half and looking
22076 /// through shuffles which switch halves trying to find a shuffle of the same
22077 /// pair of dwords.
22078 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
22080 TargetLowering::DAGCombinerInfo &DCI) {
22082 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
22083 "Called with something other than an x86 128-bit half shuffle!");
22085 unsigned CombineOpcode = N.getOpcode();
22087 // Walk up a single-use chain looking for a combinable shuffle.
22088 SDValue V = N.getOperand(0);
22089 for (; V.hasOneUse(); V = V.getOperand(0)) {
22090 switch (V.getOpcode()) {
22092 return false; // Nothing combined!
22095 // Skip bitcasts as we always know the type for the target specific
22099 case X86ISD::PSHUFLW:
22100 case X86ISD::PSHUFHW:
22101 if (V.getOpcode() == CombineOpcode)
22104 // Other-half shuffles are no-ops.
22107 // Break out of the loop if we break out of the switch.
22111 if (!V.hasOneUse())
22112 // We fell out of the loop without finding a viable combining instruction.
22115 // Combine away the bottom node as its shuffle will be accumulated into
22116 // a preceding shuffle.
22117 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
22119 // Record the old value.
22122 // Merge this node's mask and our incoming mask (adjusted to account for all
22123 // the pshufd instructions encountered).
22124 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22125 for (int &M : Mask)
22127 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
22128 getV4X86ShuffleImm8ForMask(Mask, DAG));
22130 // Check that the shuffles didn't cancel each other out. If not, we need to
22131 // combine to the new one.
22133 // Replace the combinable shuffle with the combined one, updating all users
22134 // so that we re-evaluate the chain here.
22135 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
22140 /// \brief Try to combine x86 target specific shuffles.
22141 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
22142 TargetLowering::DAGCombinerInfo &DCI,
22143 const X86Subtarget *Subtarget) {
22145 MVT VT = N.getSimpleValueType();
22146 SmallVector<int, 4> Mask;
22148 switch (N.getOpcode()) {
22149 case X86ISD::PSHUFD:
22150 case X86ISD::PSHUFLW:
22151 case X86ISD::PSHUFHW:
22152 Mask = getPSHUFShuffleMask(N);
22153 assert(Mask.size() == 4);
22159 // Nuke no-op shuffles that show up after combining.
22160 if (isNoopShuffleMask(Mask))
22161 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
22163 // Look for simplifications involving one or two shuffle instructions.
22164 SDValue V = N.getOperand(0);
22165 switch (N.getOpcode()) {
22168 case X86ISD::PSHUFLW:
22169 case X86ISD::PSHUFHW:
22170 assert(VT == MVT::v8i16);
22173 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
22174 return SDValue(); // We combined away this shuffle, so we're done.
22176 // See if this reduces to a PSHUFD which is no more expensive and can
22177 // combine with more operations. Note that it has to at least flip the
22178 // dwords as otherwise it would have been removed as a no-op.
22179 if (Mask[0] == 2 && Mask[1] == 3 && Mask[2] == 0 && Mask[3] == 1) {
22180 int DMask[] = {0, 1, 2, 3};
22181 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
22182 DMask[DOffset + 0] = DOffset + 1;
22183 DMask[DOffset + 1] = DOffset + 0;
22184 V = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V);
22185 DCI.AddToWorklist(V.getNode());
22186 V = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V,
22187 getV4X86ShuffleImm8ForMask(DMask, DAG));
22188 DCI.AddToWorklist(V.getNode());
22189 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
22192 // Look for shuffle patterns which can be implemented as a single unpack.
22193 // FIXME: This doesn't handle the location of the PSHUFD generically, and
22194 // only works when we have a PSHUFD followed by two half-shuffles.
22195 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
22196 (V.getOpcode() == X86ISD::PSHUFLW ||
22197 V.getOpcode() == X86ISD::PSHUFHW) &&
22198 V.getOpcode() != N.getOpcode() &&
22200 SDValue D = V.getOperand(0);
22201 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
22202 D = D.getOperand(0);
22203 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
22204 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22205 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
22206 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
22207 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
22209 for (int i = 0; i < 4; ++i) {
22210 WordMask[i + NOffset] = Mask[i] + NOffset;
22211 WordMask[i + VOffset] = VMask[i] + VOffset;
22213 // Map the word mask through the DWord mask.
22215 for (int i = 0; i < 8; ++i)
22216 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
22217 const int UnpackLoMask[] = {0, 0, 1, 1, 2, 2, 3, 3};
22218 const int UnpackHiMask[] = {4, 4, 5, 5, 6, 6, 7, 7};
22219 if (std::equal(std::begin(MappedMask), std::end(MappedMask),
22220 std::begin(UnpackLoMask)) ||
22221 std::equal(std::begin(MappedMask), std::end(MappedMask),
22222 std::begin(UnpackHiMask))) {
22223 // We can replace all three shuffles with an unpack.
22224 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, D.getOperand(0));
22225 DCI.AddToWorklist(V.getNode());
22226 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
22228 DL, MVT::v8i16, V, V);
22235 case X86ISD::PSHUFD:
22236 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
22245 /// \brief Try to combine a shuffle into a target-specific add-sub node.
22247 /// We combine this directly on the abstract vector shuffle nodes so it is
22248 /// easier to generically match. We also insert dummy vector shuffle nodes for
22249 /// the operands which explicitly discard the lanes which are unused by this
22250 /// operation to try to flow through the rest of the combiner the fact that
22251 /// they're unused.
22252 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
22254 EVT VT = N->getValueType(0);
22256 // We only handle target-independent shuffles.
22257 // FIXME: It would be easy and harmless to use the target shuffle mask
22258 // extraction tool to support more.
22259 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
22262 auto *SVN = cast<ShuffleVectorSDNode>(N);
22263 ArrayRef<int> Mask = SVN->getMask();
22264 SDValue V1 = N->getOperand(0);
22265 SDValue V2 = N->getOperand(1);
22267 // We require the first shuffle operand to be the SUB node, and the second to
22268 // be the ADD node.
22269 // FIXME: We should support the commuted patterns.
22270 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
22273 // If there are other uses of these operations we can't fold them.
22274 if (!V1->hasOneUse() || !V2->hasOneUse())
22277 // Ensure that both operations have the same operands. Note that we can
22278 // commute the FADD operands.
22279 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
22280 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
22281 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
22284 // We're looking for blends between FADD and FSUB nodes. We insist on these
22285 // nodes being lined up in a specific expected pattern.
22286 if (!(isShuffleEquivalent(Mask, 0, 3) ||
22287 isShuffleEquivalent(Mask, 0, 5, 2, 7) ||
22288 isShuffleEquivalent(Mask, 0, 9, 2, 11, 4, 13, 6, 15)))
22291 // Only specific types are legal at this point, assert so we notice if and
22292 // when these change.
22293 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
22294 VT == MVT::v4f64) &&
22295 "Unknown vector type encountered!");
22297 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
22300 /// PerformShuffleCombine - Performs several different shuffle combines.
22301 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
22302 TargetLowering::DAGCombinerInfo &DCI,
22303 const X86Subtarget *Subtarget) {
22305 SDValue N0 = N->getOperand(0);
22306 SDValue N1 = N->getOperand(1);
22307 EVT VT = N->getValueType(0);
22309 // Don't create instructions with illegal types after legalize types has run.
22310 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22311 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
22314 // If we have legalized the vector types, look for blends of FADD and FSUB
22315 // nodes that we can fuse into an ADDSUB node.
22316 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
22317 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
22320 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
22321 if (Subtarget->hasFp256() && VT.is256BitVector() &&
22322 N->getOpcode() == ISD::VECTOR_SHUFFLE)
22323 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
22325 // During Type Legalization, when promoting illegal vector types,
22326 // the backend might introduce new shuffle dag nodes and bitcasts.
22328 // This code performs the following transformation:
22329 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
22330 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
22332 // We do this only if both the bitcast and the BINOP dag nodes have
22333 // one use. Also, perform this transformation only if the new binary
22334 // operation is legal. This is to avoid introducing dag nodes that
22335 // potentially need to be further expanded (or custom lowered) into a
22336 // less optimal sequence of dag nodes.
22337 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
22338 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
22339 N0.getOpcode() == ISD::BITCAST) {
22340 SDValue BC0 = N0.getOperand(0);
22341 EVT SVT = BC0.getValueType();
22342 unsigned Opcode = BC0.getOpcode();
22343 unsigned NumElts = VT.getVectorNumElements();
22345 if (BC0.hasOneUse() && SVT.isVector() &&
22346 SVT.getVectorNumElements() * 2 == NumElts &&
22347 TLI.isOperationLegal(Opcode, VT)) {
22348 bool CanFold = false;
22360 unsigned SVTNumElts = SVT.getVectorNumElements();
22361 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
22362 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
22363 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
22364 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
22365 CanFold = SVOp->getMaskElt(i) < 0;
22368 SDValue BC00 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(0));
22369 SDValue BC01 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(1));
22370 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
22371 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
22376 // Only handle 128 wide vector from here on.
22377 if (!VT.is128BitVector())
22380 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
22381 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
22382 // consecutive, non-overlapping, and in the right order.
22383 SmallVector<SDValue, 16> Elts;
22384 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
22385 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
22387 SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
22391 if (isTargetShuffle(N->getOpcode())) {
22393 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
22394 if (Shuffle.getNode())
22397 // Try recursively combining arbitrary sequences of x86 shuffle
22398 // instructions into higher-order shuffles. We do this after combining
22399 // specific PSHUF instruction sequences into their minimal form so that we
22400 // can evaluate how many specialized shuffle instructions are involved in
22401 // a particular chain.
22402 SmallVector<int, 1> NonceMask; // Just a placeholder.
22403 NonceMask.push_back(0);
22404 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
22405 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
22407 return SDValue(); // This routine will use CombineTo to replace N.
22413 /// PerformTruncateCombine - Converts truncate operation to
22414 /// a sequence of vector shuffle operations.
22415 /// It is possible when we truncate 256-bit vector to 128-bit vector
22416 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
22417 TargetLowering::DAGCombinerInfo &DCI,
22418 const X86Subtarget *Subtarget) {
22422 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
22423 /// specific shuffle of a load can be folded into a single element load.
22424 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
22425 /// shuffles have been custom lowered so we need to handle those here.
22426 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
22427 TargetLowering::DAGCombinerInfo &DCI) {
22428 if (DCI.isBeforeLegalizeOps())
22431 SDValue InVec = N->getOperand(0);
22432 SDValue EltNo = N->getOperand(1);
22434 if (!isa<ConstantSDNode>(EltNo))
22437 EVT OriginalVT = InVec.getValueType();
22439 if (InVec.getOpcode() == ISD::BITCAST) {
22440 // Don't duplicate a load with other uses.
22441 if (!InVec.hasOneUse())
22443 EVT BCVT = InVec.getOperand(0).getValueType();
22444 if (BCVT.getVectorNumElements() != OriginalVT.getVectorNumElements())
22446 InVec = InVec.getOperand(0);
22449 EVT CurrentVT = InVec.getValueType();
22451 if (!isTargetShuffle(InVec.getOpcode()))
22454 // Don't duplicate a load with other uses.
22455 if (!InVec.hasOneUse())
22458 SmallVector<int, 16> ShuffleMask;
22460 if (!getTargetShuffleMask(InVec.getNode(), CurrentVT.getSimpleVT(),
22461 ShuffleMask, UnaryShuffle))
22464 // Select the input vector, guarding against out of range extract vector.
22465 unsigned NumElems = CurrentVT.getVectorNumElements();
22466 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
22467 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
22468 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
22469 : InVec.getOperand(1);
22471 // If inputs to shuffle are the same for both ops, then allow 2 uses
22472 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
22474 if (LdNode.getOpcode() == ISD::BITCAST) {
22475 // Don't duplicate a load with other uses.
22476 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
22479 AllowedUses = 1; // only allow 1 load use if we have a bitcast
22480 LdNode = LdNode.getOperand(0);
22483 if (!ISD::isNormalLoad(LdNode.getNode()))
22486 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
22488 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
22491 EVT EltVT = N->getValueType(0);
22492 // If there's a bitcast before the shuffle, check if the load type and
22493 // alignment is valid.
22494 unsigned Align = LN0->getAlignment();
22495 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22496 unsigned NewAlign = TLI.getDataLayout()->getABITypeAlignment(
22497 EltVT.getTypeForEVT(*DAG.getContext()));
22499 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
22502 // All checks match so transform back to vector_shuffle so that DAG combiner
22503 // can finish the job
22506 // Create shuffle node taking into account the case that its a unary shuffle
22507 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(CurrentVT)
22508 : InVec.getOperand(1);
22509 Shuffle = DAG.getVectorShuffle(CurrentVT, dl,
22510 InVec.getOperand(0), Shuffle,
22512 Shuffle = DAG.getNode(ISD::BITCAST, dl, OriginalVT, Shuffle);
22513 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
22517 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
22518 /// generation and convert it from being a bunch of shuffles and extracts
22519 /// into a somewhat faster sequence. For i686, the best sequence is apparently
22520 /// storing the value and loading scalars back, while for x64 we should
22521 /// use 64-bit extracts and shifts.
22522 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
22523 TargetLowering::DAGCombinerInfo &DCI) {
22524 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
22525 if (NewOp.getNode())
22528 SDValue InputVector = N->getOperand(0);
22530 // Detect whether we are trying to convert from mmx to i32 and the bitcast
22531 // from mmx to v2i32 has a single usage.
22532 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
22533 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
22534 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
22535 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
22536 N->getValueType(0),
22537 InputVector.getNode()->getOperand(0));
22539 // Only operate on vectors of 4 elements, where the alternative shuffling
22540 // gets to be more expensive.
22541 if (InputVector.getValueType() != MVT::v4i32)
22544 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
22545 // single use which is a sign-extend or zero-extend, and all elements are
22547 SmallVector<SDNode *, 4> Uses;
22548 unsigned ExtractedElements = 0;
22549 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
22550 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
22551 if (UI.getUse().getResNo() != InputVector.getResNo())
22554 SDNode *Extract = *UI;
22555 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
22558 if (Extract->getValueType(0) != MVT::i32)
22560 if (!Extract->hasOneUse())
22562 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
22563 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
22565 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
22568 // Record which element was extracted.
22569 ExtractedElements |=
22570 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
22572 Uses.push_back(Extract);
22575 // If not all the elements were used, this may not be worthwhile.
22576 if (ExtractedElements != 15)
22579 // Ok, we've now decided to do the transformation.
22580 // If 64-bit shifts are legal, use the extract-shift sequence,
22581 // otherwise bounce the vector off the cache.
22582 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22584 SDLoc dl(InputVector);
22586 if (TLI.isOperationLegal(ISD::SRA, MVT::i64)) {
22587 SDValue Cst = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, InputVector);
22588 EVT VecIdxTy = DAG.getTargetLoweringInfo().getVectorIdxTy();
22589 SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
22590 DAG.getConstant(0, VecIdxTy));
22591 SDValue TopHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
22592 DAG.getConstant(1, VecIdxTy));
22594 SDValue ShAmt = DAG.getConstant(32,
22595 DAG.getTargetLoweringInfo().getShiftAmountTy(MVT::i64));
22596 Vals[0] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BottomHalf);
22597 Vals[1] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
22598 DAG.getNode(ISD::SRA, dl, MVT::i64, BottomHalf, ShAmt));
22599 Vals[2] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, TopHalf);
22600 Vals[3] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
22601 DAG.getNode(ISD::SRA, dl, MVT::i64, TopHalf, ShAmt));
22603 // Store the value to a temporary stack slot.
22604 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
22605 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
22606 MachinePointerInfo(), false, false, 0);
22608 EVT ElementType = InputVector.getValueType().getVectorElementType();
22609 unsigned EltSize = ElementType.getSizeInBits() / 8;
22611 // Replace each use (extract) with a load of the appropriate element.
22612 for (unsigned i = 0; i < 4; ++i) {
22613 uint64_t Offset = EltSize * i;
22614 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
22616 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
22617 StackPtr, OffsetVal);
22619 // Load the scalar.
22620 Vals[i] = DAG.getLoad(ElementType, dl, Ch,
22621 ScalarAddr, MachinePointerInfo(),
22622 false, false, false, 0);
22627 // Replace the extracts
22628 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
22629 UE = Uses.end(); UI != UE; ++UI) {
22630 SDNode *Extract = *UI;
22632 SDValue Idx = Extract->getOperand(1);
22633 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
22634 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), Vals[IdxVal]);
22637 // The replacement was made in place; don't return anything.
22641 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
22642 static std::pair<unsigned, bool>
22643 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
22644 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
22645 if (!VT.isVector())
22646 return std::make_pair(0, false);
22648 bool NeedSplit = false;
22649 switch (VT.getSimpleVT().SimpleTy) {
22650 default: return std::make_pair(0, false);
22653 if (!Subtarget->hasVLX())
22654 return std::make_pair(0, false);
22658 if (!Subtarget->hasBWI())
22659 return std::make_pair(0, false);
22663 if (!Subtarget->hasAVX512())
22664 return std::make_pair(0, false);
22669 if (!Subtarget->hasAVX2())
22671 if (!Subtarget->hasAVX())
22672 return std::make_pair(0, false);
22677 if (!Subtarget->hasSSE2())
22678 return std::make_pair(0, false);
22681 // SSE2 has only a small subset of the operations.
22682 bool hasUnsigned = Subtarget->hasSSE41() ||
22683 (Subtarget->hasSSE2() && VT == MVT::v16i8);
22684 bool hasSigned = Subtarget->hasSSE41() ||
22685 (Subtarget->hasSSE2() && VT == MVT::v8i16);
22687 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22690 // Check for x CC y ? x : y.
22691 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
22692 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
22697 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
22700 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
22703 Opc = hasSigned ? X86ISD::SMIN : 0; break;
22706 Opc = hasSigned ? X86ISD::SMAX : 0; break;
22708 // Check for x CC y ? y : x -- a min/max with reversed arms.
22709 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
22710 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
22715 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
22718 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
22721 Opc = hasSigned ? X86ISD::SMAX : 0; break;
22724 Opc = hasSigned ? X86ISD::SMIN : 0; break;
22728 return std::make_pair(Opc, NeedSplit);
22732 transformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
22733 const X86Subtarget *Subtarget) {
22735 SDValue Cond = N->getOperand(0);
22736 SDValue LHS = N->getOperand(1);
22737 SDValue RHS = N->getOperand(2);
22739 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
22740 SDValue CondSrc = Cond->getOperand(0);
22741 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
22742 Cond = CondSrc->getOperand(0);
22745 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
22748 // A vselect where all conditions and data are constants can be optimized into
22749 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
22750 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
22751 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
22754 unsigned MaskValue = 0;
22755 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
22758 MVT VT = N->getSimpleValueType(0);
22759 unsigned NumElems = VT.getVectorNumElements();
22760 SmallVector<int, 8> ShuffleMask(NumElems, -1);
22761 for (unsigned i = 0; i < NumElems; ++i) {
22762 // Be sure we emit undef where we can.
22763 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
22764 ShuffleMask[i] = -1;
22766 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
22769 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22770 if (!TLI.isShuffleMaskLegal(ShuffleMask, VT))
22772 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
22775 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
22777 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
22778 TargetLowering::DAGCombinerInfo &DCI,
22779 const X86Subtarget *Subtarget) {
22781 SDValue Cond = N->getOperand(0);
22782 // Get the LHS/RHS of the select.
22783 SDValue LHS = N->getOperand(1);
22784 SDValue RHS = N->getOperand(2);
22785 EVT VT = LHS.getValueType();
22786 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22788 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
22789 // instructions match the semantics of the common C idiom x<y?x:y but not
22790 // x<=y?x:y, because of how they handle negative zero (which can be
22791 // ignored in unsafe-math mode).
22792 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
22793 VT != MVT::f80 && TLI.isTypeLegal(VT) &&
22794 (Subtarget->hasSSE2() ||
22795 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
22796 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22798 unsigned Opcode = 0;
22799 // Check for x CC y ? x : y.
22800 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
22801 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
22805 // Converting this to a min would handle NaNs incorrectly, and swapping
22806 // the operands would cause it to handle comparisons between positive
22807 // and negative zero incorrectly.
22808 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
22809 if (!DAG.getTarget().Options.UnsafeFPMath &&
22810 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
22812 std::swap(LHS, RHS);
22814 Opcode = X86ISD::FMIN;
22817 // Converting this to a min would handle comparisons between positive
22818 // and negative zero incorrectly.
22819 if (!DAG.getTarget().Options.UnsafeFPMath &&
22820 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
22822 Opcode = X86ISD::FMIN;
22825 // Converting this to a min would handle both negative zeros and NaNs
22826 // incorrectly, but we can swap the operands to fix both.
22827 std::swap(LHS, RHS);
22831 Opcode = X86ISD::FMIN;
22835 // Converting this to a max would handle comparisons between positive
22836 // and negative zero incorrectly.
22837 if (!DAG.getTarget().Options.UnsafeFPMath &&
22838 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
22840 Opcode = X86ISD::FMAX;
22843 // Converting this to a max would handle NaNs incorrectly, and swapping
22844 // the operands would cause it to handle comparisons between positive
22845 // and negative zero incorrectly.
22846 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
22847 if (!DAG.getTarget().Options.UnsafeFPMath &&
22848 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
22850 std::swap(LHS, RHS);
22852 Opcode = X86ISD::FMAX;
22855 // Converting this to a max would handle both negative zeros and NaNs
22856 // incorrectly, but we can swap the operands to fix both.
22857 std::swap(LHS, RHS);
22861 Opcode = X86ISD::FMAX;
22864 // Check for x CC y ? y : x -- a min/max with reversed arms.
22865 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
22866 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
22870 // Converting this to a min would handle comparisons between positive
22871 // and negative zero incorrectly, and swapping the operands would
22872 // cause it to handle NaNs incorrectly.
22873 if (!DAG.getTarget().Options.UnsafeFPMath &&
22874 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
22875 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22877 std::swap(LHS, RHS);
22879 Opcode = X86ISD::FMIN;
22882 // Converting this to a min would handle NaNs incorrectly.
22883 if (!DAG.getTarget().Options.UnsafeFPMath &&
22884 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
22886 Opcode = X86ISD::FMIN;
22889 // Converting this to a min would handle both negative zeros and NaNs
22890 // incorrectly, but we can swap the operands to fix both.
22891 std::swap(LHS, RHS);
22895 Opcode = X86ISD::FMIN;
22899 // Converting this to a max would handle NaNs incorrectly.
22900 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22902 Opcode = X86ISD::FMAX;
22905 // Converting this to a max would handle comparisons between positive
22906 // and negative zero incorrectly, and swapping the operands would
22907 // cause it to handle NaNs incorrectly.
22908 if (!DAG.getTarget().Options.UnsafeFPMath &&
22909 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
22910 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22912 std::swap(LHS, RHS);
22914 Opcode = X86ISD::FMAX;
22917 // Converting this to a max would handle both negative zeros and NaNs
22918 // incorrectly, but we can swap the operands to fix both.
22919 std::swap(LHS, RHS);
22923 Opcode = X86ISD::FMAX;
22929 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
22932 EVT CondVT = Cond.getValueType();
22933 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
22934 CondVT.getVectorElementType() == MVT::i1) {
22935 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
22936 // lowering on KNL. In this case we convert it to
22937 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
22938 // The same situation for all 128 and 256-bit vectors of i8 and i16.
22939 // Since SKX these selects have a proper lowering.
22940 EVT OpVT = LHS.getValueType();
22941 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
22942 (OpVT.getVectorElementType() == MVT::i8 ||
22943 OpVT.getVectorElementType() == MVT::i16) &&
22944 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
22945 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
22946 DCI.AddToWorklist(Cond.getNode());
22947 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
22950 // If this is a select between two integer constants, try to do some
22952 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
22953 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
22954 // Don't do this for crazy integer types.
22955 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
22956 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
22957 // so that TrueC (the true value) is larger than FalseC.
22958 bool NeedsCondInvert = false;
22960 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
22961 // Efficiently invertible.
22962 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
22963 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
22964 isa<ConstantSDNode>(Cond.getOperand(1))))) {
22965 NeedsCondInvert = true;
22966 std::swap(TrueC, FalseC);
22969 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
22970 if (FalseC->getAPIntValue() == 0 &&
22971 TrueC->getAPIntValue().isPowerOf2()) {
22972 if (NeedsCondInvert) // Invert the condition if needed.
22973 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22974 DAG.getConstant(1, Cond.getValueType()));
22976 // Zero extend the condition if needed.
22977 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
22979 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
22980 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
22981 DAG.getConstant(ShAmt, MVT::i8));
22984 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
22985 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
22986 if (NeedsCondInvert) // Invert the condition if needed.
22987 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22988 DAG.getConstant(1, Cond.getValueType()));
22990 // Zero extend the condition if needed.
22991 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
22992 FalseC->getValueType(0), Cond);
22993 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22994 SDValue(FalseC, 0));
22997 // Optimize cases that will turn into an LEA instruction. This requires
22998 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
22999 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
23000 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
23001 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
23003 bool isFastMultiplier = false;
23005 switch ((unsigned char)Diff) {
23007 case 1: // result = add base, cond
23008 case 2: // result = lea base( , cond*2)
23009 case 3: // result = lea base(cond, cond*2)
23010 case 4: // result = lea base( , cond*4)
23011 case 5: // result = lea base(cond, cond*4)
23012 case 8: // result = lea base( , cond*8)
23013 case 9: // result = lea base(cond, cond*8)
23014 isFastMultiplier = true;
23019 if (isFastMultiplier) {
23020 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
23021 if (NeedsCondInvert) // Invert the condition if needed.
23022 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23023 DAG.getConstant(1, Cond.getValueType()));
23025 // Zero extend the condition if needed.
23026 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
23028 // Scale the condition by the difference.
23030 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
23031 DAG.getConstant(Diff, Cond.getValueType()));
23033 // Add the base if non-zero.
23034 if (FalseC->getAPIntValue() != 0)
23035 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23036 SDValue(FalseC, 0));
23043 // Canonicalize max and min:
23044 // (x > y) ? x : y -> (x >= y) ? x : y
23045 // (x < y) ? x : y -> (x <= y) ? x : y
23046 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
23047 // the need for an extra compare
23048 // against zero. e.g.
23049 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
23051 // testl %edi, %edi
23053 // cmovgl %edi, %eax
23057 // cmovsl %eax, %edi
23058 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
23059 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
23060 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
23061 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23066 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
23067 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
23068 Cond.getOperand(0), Cond.getOperand(1), NewCC);
23069 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
23074 // Early exit check
23075 if (!TLI.isTypeLegal(VT))
23078 // Match VSELECTs into subs with unsigned saturation.
23079 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
23080 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
23081 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
23082 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
23083 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23085 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
23086 // left side invert the predicate to simplify logic below.
23088 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
23090 CC = ISD::getSetCCInverse(CC, true);
23091 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
23095 if (Other.getNode() && Other->getNumOperands() == 2 &&
23096 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
23097 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
23098 SDValue CondRHS = Cond->getOperand(1);
23100 // Look for a general sub with unsigned saturation first.
23101 // x >= y ? x-y : 0 --> subus x, y
23102 // x > y ? x-y : 0 --> subus x, y
23103 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
23104 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
23105 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
23107 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
23108 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
23109 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
23110 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
23111 // If the RHS is a constant we have to reverse the const
23112 // canonicalization.
23113 // x > C-1 ? x+-C : 0 --> subus x, C
23114 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
23115 CondRHSConst->getAPIntValue() ==
23116 (-OpRHSConst->getAPIntValue() - 1))
23117 return DAG.getNode(
23118 X86ISD::SUBUS, DL, VT, OpLHS,
23119 DAG.getConstant(-OpRHSConst->getAPIntValue(), VT));
23121 // Another special case: If C was a sign bit, the sub has been
23122 // canonicalized into a xor.
23123 // FIXME: Would it be better to use computeKnownBits to determine
23124 // whether it's safe to decanonicalize the xor?
23125 // x s< 0 ? x^C : 0 --> subus x, C
23126 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
23127 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
23128 OpRHSConst->getAPIntValue().isSignBit())
23129 // Note that we have to rebuild the RHS constant here to ensure we
23130 // don't rely on particular values of undef lanes.
23131 return DAG.getNode(
23132 X86ISD::SUBUS, DL, VT, OpLHS,
23133 DAG.getConstant(OpRHSConst->getAPIntValue(), VT));
23138 // Try to match a min/max vector operation.
23139 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
23140 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
23141 unsigned Opc = ret.first;
23142 bool NeedSplit = ret.second;
23144 if (Opc && NeedSplit) {
23145 unsigned NumElems = VT.getVectorNumElements();
23146 // Extract the LHS vectors
23147 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
23148 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
23150 // Extract the RHS vectors
23151 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
23152 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
23154 // Create min/max for each subvector
23155 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
23156 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
23158 // Merge the result
23159 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
23161 return DAG.getNode(Opc, DL, VT, LHS, RHS);
23164 // Simplify vector selection if condition value type matches vselect
23166 if (N->getOpcode() == ISD::VSELECT && CondVT == VT) {
23167 assert(Cond.getValueType().isVector() &&
23168 "vector select expects a vector selector!");
23170 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
23171 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
23173 // Try invert the condition if true value is not all 1s and false value
23175 if (!TValIsAllOnes && !FValIsAllZeros &&
23176 // Check if the selector will be produced by CMPP*/PCMP*
23177 Cond.getOpcode() == ISD::SETCC &&
23178 // Check if SETCC has already been promoted
23179 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT) {
23180 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
23181 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
23183 if (TValIsAllZeros || FValIsAllOnes) {
23184 SDValue CC = Cond.getOperand(2);
23185 ISD::CondCode NewCC =
23186 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
23187 Cond.getOperand(0).getValueType().isInteger());
23188 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
23189 std::swap(LHS, RHS);
23190 TValIsAllOnes = FValIsAllOnes;
23191 FValIsAllZeros = TValIsAllZeros;
23195 if (TValIsAllOnes || FValIsAllZeros) {
23198 if (TValIsAllOnes && FValIsAllZeros)
23200 else if (TValIsAllOnes)
23201 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
23202 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
23203 else if (FValIsAllZeros)
23204 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
23205 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
23207 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
23211 // If we know that this node is legal then we know that it is going to be
23212 // matched by one of the SSE/AVX BLEND instructions. These instructions only
23213 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
23214 // to simplify previous instructions.
23215 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
23216 !DCI.isBeforeLegalize() &&
23217 // We explicitly check against v8i16 and v16i16 because, although
23218 // they're marked as Custom, they might only be legal when Cond is a
23219 // build_vector of constants. This will be taken care in a later
23221 (TLI.isOperationLegalOrCustom(ISD::VSELECT, VT) && VT != MVT::v16i16 &&
23222 VT != MVT::v8i16) &&
23223 // Don't optimize vector of constants. Those are handled by
23224 // the generic code and all the bits must be properly set for
23225 // the generic optimizer.
23226 !ISD::isBuildVectorOfConstantSDNodes(Cond.getNode())) {
23227 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
23229 // Don't optimize vector selects that map to mask-registers.
23233 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
23234 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
23236 APInt KnownZero, KnownOne;
23237 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
23238 DCI.isBeforeLegalizeOps());
23239 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
23240 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne,
23242 // If we changed the computation somewhere in the DAG, this change
23243 // will affect all users of Cond.
23244 // Make sure it is fine and update all the nodes so that we do not
23245 // use the generic VSELECT anymore. Otherwise, we may perform
23246 // wrong optimizations as we messed up with the actual expectation
23247 // for the vector boolean values.
23248 if (Cond != TLO.Old) {
23249 // Check all uses of that condition operand to check whether it will be
23250 // consumed by non-BLEND instructions, which may depend on all bits are
23252 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
23254 if (I->getOpcode() != ISD::VSELECT)
23255 // TODO: Add other opcodes eventually lowered into BLEND.
23258 // Update all the users of the condition, before committing the change,
23259 // so that the VSELECT optimizations that expect the correct vector
23260 // boolean value will not be triggered.
23261 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
23263 DAG.ReplaceAllUsesOfValueWith(
23265 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(*I), I->getValueType(0),
23266 Cond, I->getOperand(1), I->getOperand(2)));
23267 DCI.CommitTargetLoweringOpt(TLO);
23270 // At this point, only Cond is changed. Change the condition
23271 // just for N to keep the opportunity to optimize all other
23272 // users their own way.
23273 DAG.ReplaceAllUsesOfValueWith(
23275 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(N), N->getValueType(0),
23276 TLO.New, N->getOperand(1), N->getOperand(2)));
23281 // We should generate an X86ISD::BLENDI from a vselect if its argument
23282 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
23283 // constants. This specific pattern gets generated when we split a
23284 // selector for a 512 bit vector in a machine without AVX512 (but with
23285 // 256-bit vectors), during legalization:
23287 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
23289 // Iff we find this pattern and the build_vectors are built from
23290 // constants, we translate the vselect into a shuffle_vector that we
23291 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
23292 if ((N->getOpcode() == ISD::VSELECT ||
23293 N->getOpcode() == X86ISD::SHRUNKBLEND) &&
23294 !DCI.isBeforeLegalize()) {
23295 SDValue Shuffle = transformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
23296 if (Shuffle.getNode())
23303 // Check whether a boolean test is testing a boolean value generated by
23304 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
23307 // Simplify the following patterns:
23308 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
23309 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
23310 // to (Op EFLAGS Cond)
23312 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
23313 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
23314 // to (Op EFLAGS !Cond)
23316 // where Op could be BRCOND or CMOV.
23318 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
23319 // Quit if not CMP and SUB with its value result used.
23320 if (Cmp.getOpcode() != X86ISD::CMP &&
23321 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
23324 // Quit if not used as a boolean value.
23325 if (CC != X86::COND_E && CC != X86::COND_NE)
23328 // Check CMP operands. One of them should be 0 or 1 and the other should be
23329 // an SetCC or extended from it.
23330 SDValue Op1 = Cmp.getOperand(0);
23331 SDValue Op2 = Cmp.getOperand(1);
23334 const ConstantSDNode* C = nullptr;
23335 bool needOppositeCond = (CC == X86::COND_E);
23336 bool checkAgainstTrue = false; // Is it a comparison against 1?
23338 if ((C = dyn_cast<ConstantSDNode>(Op1)))
23340 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
23342 else // Quit if all operands are not constants.
23345 if (C->getZExtValue() == 1) {
23346 needOppositeCond = !needOppositeCond;
23347 checkAgainstTrue = true;
23348 } else if (C->getZExtValue() != 0)
23349 // Quit if the constant is neither 0 or 1.
23352 bool truncatedToBoolWithAnd = false;
23353 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
23354 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
23355 SetCC.getOpcode() == ISD::TRUNCATE ||
23356 SetCC.getOpcode() == ISD::AND) {
23357 if (SetCC.getOpcode() == ISD::AND) {
23359 ConstantSDNode *CS;
23360 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
23361 CS->getZExtValue() == 1)
23363 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
23364 CS->getZExtValue() == 1)
23368 SetCC = SetCC.getOperand(OpIdx);
23369 truncatedToBoolWithAnd = true;
23371 SetCC = SetCC.getOperand(0);
23374 switch (SetCC.getOpcode()) {
23375 case X86ISD::SETCC_CARRY:
23376 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
23377 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
23378 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
23379 // truncated to i1 using 'and'.
23380 if (checkAgainstTrue && !truncatedToBoolWithAnd)
23382 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
23383 "Invalid use of SETCC_CARRY!");
23385 case X86ISD::SETCC:
23386 // Set the condition code or opposite one if necessary.
23387 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
23388 if (needOppositeCond)
23389 CC = X86::GetOppositeBranchCondition(CC);
23390 return SetCC.getOperand(1);
23391 case X86ISD::CMOV: {
23392 // Check whether false/true value has canonical one, i.e. 0 or 1.
23393 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
23394 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
23395 // Quit if true value is not a constant.
23398 // Quit if false value is not a constant.
23400 SDValue Op = SetCC.getOperand(0);
23401 // Skip 'zext' or 'trunc' node.
23402 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
23403 Op.getOpcode() == ISD::TRUNCATE)
23404 Op = Op.getOperand(0);
23405 // A special case for rdrand/rdseed, where 0 is set if false cond is
23407 if ((Op.getOpcode() != X86ISD::RDRAND &&
23408 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
23411 // Quit if false value is not the constant 0 or 1.
23412 bool FValIsFalse = true;
23413 if (FVal && FVal->getZExtValue() != 0) {
23414 if (FVal->getZExtValue() != 1)
23416 // If FVal is 1, opposite cond is needed.
23417 needOppositeCond = !needOppositeCond;
23418 FValIsFalse = false;
23420 // Quit if TVal is not the constant opposite of FVal.
23421 if (FValIsFalse && TVal->getZExtValue() != 1)
23423 if (!FValIsFalse && TVal->getZExtValue() != 0)
23425 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
23426 if (needOppositeCond)
23427 CC = X86::GetOppositeBranchCondition(CC);
23428 return SetCC.getOperand(3);
23435 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
23436 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
23437 TargetLowering::DAGCombinerInfo &DCI,
23438 const X86Subtarget *Subtarget) {
23441 // If the flag operand isn't dead, don't touch this CMOV.
23442 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
23445 SDValue FalseOp = N->getOperand(0);
23446 SDValue TrueOp = N->getOperand(1);
23447 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
23448 SDValue Cond = N->getOperand(3);
23450 if (CC == X86::COND_E || CC == X86::COND_NE) {
23451 switch (Cond.getOpcode()) {
23455 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
23456 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
23457 return (CC == X86::COND_E) ? FalseOp : TrueOp;
23463 Flags = checkBoolTestSetCCCombine(Cond, CC);
23464 if (Flags.getNode() &&
23465 // Extra check as FCMOV only supports a subset of X86 cond.
23466 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
23467 SDValue Ops[] = { FalseOp, TrueOp,
23468 DAG.getConstant(CC, MVT::i8), Flags };
23469 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
23472 // If this is a select between two integer constants, try to do some
23473 // optimizations. Note that the operands are ordered the opposite of SELECT
23475 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
23476 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
23477 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
23478 // larger than FalseC (the false value).
23479 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
23480 CC = X86::GetOppositeBranchCondition(CC);
23481 std::swap(TrueC, FalseC);
23482 std::swap(TrueOp, FalseOp);
23485 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
23486 // This is efficient for any integer data type (including i8/i16) and
23488 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
23489 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23490 DAG.getConstant(CC, MVT::i8), Cond);
23492 // Zero extend the condition if needed.
23493 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
23495 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
23496 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
23497 DAG.getConstant(ShAmt, MVT::i8));
23498 if (N->getNumValues() == 2) // Dead flag value?
23499 return DCI.CombineTo(N, Cond, SDValue());
23503 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
23504 // for any integer data type, including i8/i16.
23505 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
23506 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23507 DAG.getConstant(CC, MVT::i8), Cond);
23509 // Zero extend the condition if needed.
23510 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
23511 FalseC->getValueType(0), Cond);
23512 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23513 SDValue(FalseC, 0));
23515 if (N->getNumValues() == 2) // Dead flag value?
23516 return DCI.CombineTo(N, Cond, SDValue());
23520 // Optimize cases that will turn into an LEA instruction. This requires
23521 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
23522 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
23523 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
23524 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
23526 bool isFastMultiplier = false;
23528 switch ((unsigned char)Diff) {
23530 case 1: // result = add base, cond
23531 case 2: // result = lea base( , cond*2)
23532 case 3: // result = lea base(cond, cond*2)
23533 case 4: // result = lea base( , cond*4)
23534 case 5: // result = lea base(cond, cond*4)
23535 case 8: // result = lea base( , cond*8)
23536 case 9: // result = lea base(cond, cond*8)
23537 isFastMultiplier = true;
23542 if (isFastMultiplier) {
23543 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
23544 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23545 DAG.getConstant(CC, MVT::i8), Cond);
23546 // Zero extend the condition if needed.
23547 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
23549 // Scale the condition by the difference.
23551 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
23552 DAG.getConstant(Diff, Cond.getValueType()));
23554 // Add the base if non-zero.
23555 if (FalseC->getAPIntValue() != 0)
23556 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23557 SDValue(FalseC, 0));
23558 if (N->getNumValues() == 2) // Dead flag value?
23559 return DCI.CombineTo(N, Cond, SDValue());
23566 // Handle these cases:
23567 // (select (x != c), e, c) -> select (x != c), e, x),
23568 // (select (x == c), c, e) -> select (x == c), x, e)
23569 // where the c is an integer constant, and the "select" is the combination
23570 // of CMOV and CMP.
23572 // The rationale for this change is that the conditional-move from a constant
23573 // needs two instructions, however, conditional-move from a register needs
23574 // only one instruction.
23576 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
23577 // some instruction-combining opportunities. This opt needs to be
23578 // postponed as late as possible.
23580 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
23581 // the DCI.xxxx conditions are provided to postpone the optimization as
23582 // late as possible.
23584 ConstantSDNode *CmpAgainst = nullptr;
23585 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
23586 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
23587 !isa<ConstantSDNode>(Cond.getOperand(0))) {
23589 if (CC == X86::COND_NE &&
23590 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
23591 CC = X86::GetOppositeBranchCondition(CC);
23592 std::swap(TrueOp, FalseOp);
23595 if (CC == X86::COND_E &&
23596 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
23597 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
23598 DAG.getConstant(CC, MVT::i8), Cond };
23599 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
23607 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
23608 const X86Subtarget *Subtarget) {
23609 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
23611 default: return SDValue();
23612 // SSE/AVX/AVX2 blend intrinsics.
23613 case Intrinsic::x86_avx2_pblendvb:
23614 case Intrinsic::x86_avx2_pblendw:
23615 case Intrinsic::x86_avx2_pblendd_128:
23616 case Intrinsic::x86_avx2_pblendd_256:
23617 // Don't try to simplify this intrinsic if we don't have AVX2.
23618 if (!Subtarget->hasAVX2())
23621 case Intrinsic::x86_avx_blend_pd_256:
23622 case Intrinsic::x86_avx_blend_ps_256:
23623 case Intrinsic::x86_avx_blendv_pd_256:
23624 case Intrinsic::x86_avx_blendv_ps_256:
23625 // Don't try to simplify this intrinsic if we don't have AVX.
23626 if (!Subtarget->hasAVX())
23629 case Intrinsic::x86_sse41_pblendw:
23630 case Intrinsic::x86_sse41_blendpd:
23631 case Intrinsic::x86_sse41_blendps:
23632 case Intrinsic::x86_sse41_blendvps:
23633 case Intrinsic::x86_sse41_blendvpd:
23634 case Intrinsic::x86_sse41_pblendvb: {
23635 SDValue Op0 = N->getOperand(1);
23636 SDValue Op1 = N->getOperand(2);
23637 SDValue Mask = N->getOperand(3);
23639 // Don't try to simplify this intrinsic if we don't have SSE4.1.
23640 if (!Subtarget->hasSSE41())
23643 // fold (blend A, A, Mask) -> A
23646 // fold (blend A, B, allZeros) -> A
23647 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
23649 // fold (blend A, B, allOnes) -> B
23650 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
23653 // Simplify the case where the mask is a constant i32 value.
23654 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
23655 if (C->isNullValue())
23657 if (C->isAllOnesValue())
23664 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
23665 case Intrinsic::x86_sse2_psrai_w:
23666 case Intrinsic::x86_sse2_psrai_d:
23667 case Intrinsic::x86_avx2_psrai_w:
23668 case Intrinsic::x86_avx2_psrai_d:
23669 case Intrinsic::x86_sse2_psra_w:
23670 case Intrinsic::x86_sse2_psra_d:
23671 case Intrinsic::x86_avx2_psra_w:
23672 case Intrinsic::x86_avx2_psra_d: {
23673 SDValue Op0 = N->getOperand(1);
23674 SDValue Op1 = N->getOperand(2);
23675 EVT VT = Op0.getValueType();
23676 assert(VT.isVector() && "Expected a vector type!");
23678 if (isa<BuildVectorSDNode>(Op1))
23679 Op1 = Op1.getOperand(0);
23681 if (!isa<ConstantSDNode>(Op1))
23684 EVT SVT = VT.getVectorElementType();
23685 unsigned SVTBits = SVT.getSizeInBits();
23687 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
23688 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
23689 uint64_t ShAmt = C.getZExtValue();
23691 // Don't try to convert this shift into a ISD::SRA if the shift
23692 // count is bigger than or equal to the element size.
23693 if (ShAmt >= SVTBits)
23696 // Trivial case: if the shift count is zero, then fold this
23697 // into the first operand.
23701 // Replace this packed shift intrinsic with a target independent
23703 SDValue Splat = DAG.getConstant(C, VT);
23704 return DAG.getNode(ISD::SRA, SDLoc(N), VT, Op0, Splat);
23709 /// PerformMulCombine - Optimize a single multiply with constant into two
23710 /// in order to implement it with two cheaper instructions, e.g.
23711 /// LEA + SHL, LEA + LEA.
23712 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
23713 TargetLowering::DAGCombinerInfo &DCI) {
23714 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
23717 EVT VT = N->getValueType(0);
23718 if (VT != MVT::i64)
23721 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
23724 uint64_t MulAmt = C->getZExtValue();
23725 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
23728 uint64_t MulAmt1 = 0;
23729 uint64_t MulAmt2 = 0;
23730 if ((MulAmt % 9) == 0) {
23732 MulAmt2 = MulAmt / 9;
23733 } else if ((MulAmt % 5) == 0) {
23735 MulAmt2 = MulAmt / 5;
23736 } else if ((MulAmt % 3) == 0) {
23738 MulAmt2 = MulAmt / 3;
23741 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
23744 if (isPowerOf2_64(MulAmt2) &&
23745 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
23746 // If second multiplifer is pow2, issue it first. We want the multiply by
23747 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
23749 std::swap(MulAmt1, MulAmt2);
23752 if (isPowerOf2_64(MulAmt1))
23753 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
23754 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
23756 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
23757 DAG.getConstant(MulAmt1, VT));
23759 if (isPowerOf2_64(MulAmt2))
23760 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
23761 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
23763 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
23764 DAG.getConstant(MulAmt2, VT));
23766 // Do not add new nodes to DAG combiner worklist.
23767 DCI.CombineTo(N, NewMul, false);
23772 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
23773 SDValue N0 = N->getOperand(0);
23774 SDValue N1 = N->getOperand(1);
23775 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
23776 EVT VT = N0.getValueType();
23778 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
23779 // since the result of setcc_c is all zero's or all ones.
23780 if (VT.isInteger() && !VT.isVector() &&
23781 N1C && N0.getOpcode() == ISD::AND &&
23782 N0.getOperand(1).getOpcode() == ISD::Constant) {
23783 SDValue N00 = N0.getOperand(0);
23784 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
23785 ((N00.getOpcode() == ISD::ANY_EXTEND ||
23786 N00.getOpcode() == ISD::ZERO_EXTEND) &&
23787 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
23788 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
23789 APInt ShAmt = N1C->getAPIntValue();
23790 Mask = Mask.shl(ShAmt);
23792 return DAG.getNode(ISD::AND, SDLoc(N), VT,
23793 N00, DAG.getConstant(Mask, VT));
23797 // Hardware support for vector shifts is sparse which makes us scalarize the
23798 // vector operations in many cases. Also, on sandybridge ADD is faster than
23800 // (shl V, 1) -> add V,V
23801 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
23802 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
23803 assert(N0.getValueType().isVector() && "Invalid vector shift type");
23804 // We shift all of the values by one. In many cases we do not have
23805 // hardware support for this operation. This is better expressed as an ADD
23807 if (N1SplatC->getZExtValue() == 1)
23808 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
23814 /// \brief Returns a vector of 0s if the node in input is a vector logical
23815 /// shift by a constant amount which is known to be bigger than or equal
23816 /// to the vector element size in bits.
23817 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
23818 const X86Subtarget *Subtarget) {
23819 EVT VT = N->getValueType(0);
23821 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
23822 (!Subtarget->hasInt256() ||
23823 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
23826 SDValue Amt = N->getOperand(1);
23828 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
23829 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
23830 APInt ShiftAmt = AmtSplat->getAPIntValue();
23831 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
23833 // SSE2/AVX2 logical shifts always return a vector of 0s
23834 // if the shift amount is bigger than or equal to
23835 // the element size. The constant shift amount will be
23836 // encoded as a 8-bit immediate.
23837 if (ShiftAmt.trunc(8).uge(MaxAmount))
23838 return getZeroVector(VT, Subtarget, DAG, DL);
23844 /// PerformShiftCombine - Combine shifts.
23845 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
23846 TargetLowering::DAGCombinerInfo &DCI,
23847 const X86Subtarget *Subtarget) {
23848 if (N->getOpcode() == ISD::SHL) {
23849 SDValue V = PerformSHLCombine(N, DAG);
23850 if (V.getNode()) return V;
23853 if (N->getOpcode() != ISD::SRA) {
23854 // Try to fold this logical shift into a zero vector.
23855 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
23856 if (V.getNode()) return V;
23862 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
23863 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
23864 // and friends. Likewise for OR -> CMPNEQSS.
23865 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
23866 TargetLowering::DAGCombinerInfo &DCI,
23867 const X86Subtarget *Subtarget) {
23870 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
23871 // we're requiring SSE2 for both.
23872 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
23873 SDValue N0 = N->getOperand(0);
23874 SDValue N1 = N->getOperand(1);
23875 SDValue CMP0 = N0->getOperand(1);
23876 SDValue CMP1 = N1->getOperand(1);
23879 // The SETCCs should both refer to the same CMP.
23880 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
23883 SDValue CMP00 = CMP0->getOperand(0);
23884 SDValue CMP01 = CMP0->getOperand(1);
23885 EVT VT = CMP00.getValueType();
23887 if (VT == MVT::f32 || VT == MVT::f64) {
23888 bool ExpectingFlags = false;
23889 // Check for any users that want flags:
23890 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
23891 !ExpectingFlags && UI != UE; ++UI)
23892 switch (UI->getOpcode()) {
23897 ExpectingFlags = true;
23899 case ISD::CopyToReg:
23900 case ISD::SIGN_EXTEND:
23901 case ISD::ZERO_EXTEND:
23902 case ISD::ANY_EXTEND:
23906 if (!ExpectingFlags) {
23907 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
23908 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
23910 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
23911 X86::CondCode tmp = cc0;
23916 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
23917 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
23918 // FIXME: need symbolic constants for these magic numbers.
23919 // See X86ATTInstPrinter.cpp:printSSECC().
23920 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
23921 if (Subtarget->hasAVX512()) {
23922 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
23923 CMP01, DAG.getConstant(x86cc, MVT::i8));
23924 if (N->getValueType(0) != MVT::i1)
23925 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
23929 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
23930 CMP00.getValueType(), CMP00, CMP01,
23931 DAG.getConstant(x86cc, MVT::i8));
23933 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
23934 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
23936 if (is64BitFP && !Subtarget->is64Bit()) {
23937 // On a 32-bit target, we cannot bitcast the 64-bit float to a
23938 // 64-bit integer, since that's not a legal type. Since
23939 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
23940 // bits, but can do this little dance to extract the lowest 32 bits
23941 // and work with those going forward.
23942 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
23944 SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,
23946 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
23947 Vector32, DAG.getIntPtrConstant(0));
23951 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT, OnesOrZeroesF);
23952 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
23953 DAG.getConstant(1, IntVT));
23954 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
23955 return OneBitOfTruth;
23963 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
23964 /// so it can be folded inside ANDNP.
23965 static bool CanFoldXORWithAllOnes(const SDNode *N) {
23966 EVT VT = N->getValueType(0);
23968 // Match direct AllOnes for 128 and 256-bit vectors
23969 if (ISD::isBuildVectorAllOnes(N))
23972 // Look through a bit convert.
23973 if (N->getOpcode() == ISD::BITCAST)
23974 N = N->getOperand(0).getNode();
23976 // Sometimes the operand may come from a insert_subvector building a 256-bit
23978 if (VT.is256BitVector() &&
23979 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
23980 SDValue V1 = N->getOperand(0);
23981 SDValue V2 = N->getOperand(1);
23983 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
23984 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
23985 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
23986 ISD::isBuildVectorAllOnes(V2.getNode()))
23993 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
23994 // register. In most cases we actually compare or select YMM-sized registers
23995 // and mixing the two types creates horrible code. This method optimizes
23996 // some of the transition sequences.
23997 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
23998 TargetLowering::DAGCombinerInfo &DCI,
23999 const X86Subtarget *Subtarget) {
24000 EVT VT = N->getValueType(0);
24001 if (!VT.is256BitVector())
24004 assert((N->getOpcode() == ISD::ANY_EXTEND ||
24005 N->getOpcode() == ISD::ZERO_EXTEND ||
24006 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
24008 SDValue Narrow = N->getOperand(0);
24009 EVT NarrowVT = Narrow->getValueType(0);
24010 if (!NarrowVT.is128BitVector())
24013 if (Narrow->getOpcode() != ISD::XOR &&
24014 Narrow->getOpcode() != ISD::AND &&
24015 Narrow->getOpcode() != ISD::OR)
24018 SDValue N0 = Narrow->getOperand(0);
24019 SDValue N1 = Narrow->getOperand(1);
24022 // The Left side has to be a trunc.
24023 if (N0.getOpcode() != ISD::TRUNCATE)
24026 // The type of the truncated inputs.
24027 EVT WideVT = N0->getOperand(0)->getValueType(0);
24031 // The right side has to be a 'trunc' or a constant vector.
24032 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
24033 ConstantSDNode *RHSConstSplat = nullptr;
24034 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
24035 RHSConstSplat = RHSBV->getConstantSplatNode();
24036 if (!RHSTrunc && !RHSConstSplat)
24039 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24041 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
24044 // Set N0 and N1 to hold the inputs to the new wide operation.
24045 N0 = N0->getOperand(0);
24046 if (RHSConstSplat) {
24047 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
24048 SDValue(RHSConstSplat, 0));
24049 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
24050 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
24051 } else if (RHSTrunc) {
24052 N1 = N1->getOperand(0);
24055 // Generate the wide operation.
24056 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
24057 unsigned Opcode = N->getOpcode();
24059 case ISD::ANY_EXTEND:
24061 case ISD::ZERO_EXTEND: {
24062 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
24063 APInt Mask = APInt::getAllOnesValue(InBits);
24064 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
24065 return DAG.getNode(ISD::AND, DL, VT,
24066 Op, DAG.getConstant(Mask, VT));
24068 case ISD::SIGN_EXTEND:
24069 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
24070 Op, DAG.getValueType(NarrowVT));
24072 llvm_unreachable("Unexpected opcode");
24076 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
24077 TargetLowering::DAGCombinerInfo &DCI,
24078 const X86Subtarget *Subtarget) {
24079 EVT VT = N->getValueType(0);
24080 if (DCI.isBeforeLegalizeOps())
24083 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
24087 // Create BEXTR instructions
24088 // BEXTR is ((X >> imm) & (2**size-1))
24089 if (VT == MVT::i32 || VT == MVT::i64) {
24090 SDValue N0 = N->getOperand(0);
24091 SDValue N1 = N->getOperand(1);
24094 // Check for BEXTR.
24095 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
24096 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
24097 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
24098 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
24099 if (MaskNode && ShiftNode) {
24100 uint64_t Mask = MaskNode->getZExtValue();
24101 uint64_t Shift = ShiftNode->getZExtValue();
24102 if (isMask_64(Mask)) {
24103 uint64_t MaskSize = CountPopulation_64(Mask);
24104 if (Shift + MaskSize <= VT.getSizeInBits())
24105 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
24106 DAG.getConstant(Shift | (MaskSize << 8), VT));
24114 // Want to form ANDNP nodes:
24115 // 1) In the hopes of then easily combining them with OR and AND nodes
24116 // to form PBLEND/PSIGN.
24117 // 2) To match ANDN packed intrinsics
24118 if (VT != MVT::v2i64 && VT != MVT::v4i64)
24121 SDValue N0 = N->getOperand(0);
24122 SDValue N1 = N->getOperand(1);
24125 // Check LHS for vnot
24126 if (N0.getOpcode() == ISD::XOR &&
24127 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
24128 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
24129 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
24131 // Check RHS for vnot
24132 if (N1.getOpcode() == ISD::XOR &&
24133 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
24134 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
24135 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
24140 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
24141 TargetLowering::DAGCombinerInfo &DCI,
24142 const X86Subtarget *Subtarget) {
24143 if (DCI.isBeforeLegalizeOps())
24146 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
24150 SDValue N0 = N->getOperand(0);
24151 SDValue N1 = N->getOperand(1);
24152 EVT VT = N->getValueType(0);
24154 // look for psign/blend
24155 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
24156 if (!Subtarget->hasSSSE3() ||
24157 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
24160 // Canonicalize pandn to RHS
24161 if (N0.getOpcode() == X86ISD::ANDNP)
24163 // or (and (m, y), (pandn m, x))
24164 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
24165 SDValue Mask = N1.getOperand(0);
24166 SDValue X = N1.getOperand(1);
24168 if (N0.getOperand(0) == Mask)
24169 Y = N0.getOperand(1);
24170 if (N0.getOperand(1) == Mask)
24171 Y = N0.getOperand(0);
24173 // Check to see if the mask appeared in both the AND and ANDNP and
24177 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
24178 // Look through mask bitcast.
24179 if (Mask.getOpcode() == ISD::BITCAST)
24180 Mask = Mask.getOperand(0);
24181 if (X.getOpcode() == ISD::BITCAST)
24182 X = X.getOperand(0);
24183 if (Y.getOpcode() == ISD::BITCAST)
24184 Y = Y.getOperand(0);
24186 EVT MaskVT = Mask.getValueType();
24188 // Validate that the Mask operand is a vector sra node.
24189 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
24190 // there is no psrai.b
24191 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
24192 unsigned SraAmt = ~0;
24193 if (Mask.getOpcode() == ISD::SRA) {
24194 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
24195 if (auto *AmtConst = AmtBV->getConstantSplatNode())
24196 SraAmt = AmtConst->getZExtValue();
24197 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
24198 SDValue SraC = Mask.getOperand(1);
24199 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
24201 if ((SraAmt + 1) != EltBits)
24206 // Now we know we at least have a plendvb with the mask val. See if
24207 // we can form a psignb/w/d.
24208 // psign = x.type == y.type == mask.type && y = sub(0, x);
24209 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
24210 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
24211 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
24212 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
24213 "Unsupported VT for PSIGN");
24214 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
24215 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
24217 // PBLENDVB only available on SSE 4.1
24218 if (!Subtarget->hasSSE41())
24221 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
24223 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
24224 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
24225 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
24226 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
24227 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
24231 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
24234 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
24235 MachineFunction &MF = DAG.getMachineFunction();
24236 bool OptForSize = MF.getFunction()->getAttributes().
24237 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
24239 // SHLD/SHRD instructions have lower register pressure, but on some
24240 // platforms they have higher latency than the equivalent
24241 // series of shifts/or that would otherwise be generated.
24242 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
24243 // have higher latencies and we are not optimizing for size.
24244 if (!OptForSize && Subtarget->isSHLDSlow())
24247 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
24249 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
24251 if (!N0.hasOneUse() || !N1.hasOneUse())
24254 SDValue ShAmt0 = N0.getOperand(1);
24255 if (ShAmt0.getValueType() != MVT::i8)
24257 SDValue ShAmt1 = N1.getOperand(1);
24258 if (ShAmt1.getValueType() != MVT::i8)
24260 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
24261 ShAmt0 = ShAmt0.getOperand(0);
24262 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
24263 ShAmt1 = ShAmt1.getOperand(0);
24266 unsigned Opc = X86ISD::SHLD;
24267 SDValue Op0 = N0.getOperand(0);
24268 SDValue Op1 = N1.getOperand(0);
24269 if (ShAmt0.getOpcode() == ISD::SUB) {
24270 Opc = X86ISD::SHRD;
24271 std::swap(Op0, Op1);
24272 std::swap(ShAmt0, ShAmt1);
24275 unsigned Bits = VT.getSizeInBits();
24276 if (ShAmt1.getOpcode() == ISD::SUB) {
24277 SDValue Sum = ShAmt1.getOperand(0);
24278 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
24279 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
24280 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
24281 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
24282 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
24283 return DAG.getNode(Opc, DL, VT,
24285 DAG.getNode(ISD::TRUNCATE, DL,
24288 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
24289 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
24291 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
24292 return DAG.getNode(Opc, DL, VT,
24293 N0.getOperand(0), N1.getOperand(0),
24294 DAG.getNode(ISD::TRUNCATE, DL,
24301 // Generate NEG and CMOV for integer abs.
24302 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
24303 EVT VT = N->getValueType(0);
24305 // Since X86 does not have CMOV for 8-bit integer, we don't convert
24306 // 8-bit integer abs to NEG and CMOV.
24307 if (VT.isInteger() && VT.getSizeInBits() == 8)
24310 SDValue N0 = N->getOperand(0);
24311 SDValue N1 = N->getOperand(1);
24314 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
24315 // and change it to SUB and CMOV.
24316 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
24317 N0.getOpcode() == ISD::ADD &&
24318 N0.getOperand(1) == N1 &&
24319 N1.getOpcode() == ISD::SRA &&
24320 N1.getOperand(0) == N0.getOperand(0))
24321 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
24322 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
24323 // Generate SUB & CMOV.
24324 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
24325 DAG.getConstant(0, VT), N0.getOperand(0));
24327 SDValue Ops[] = { N0.getOperand(0), Neg,
24328 DAG.getConstant(X86::COND_GE, MVT::i8),
24329 SDValue(Neg.getNode(), 1) };
24330 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
24335 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
24336 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
24337 TargetLowering::DAGCombinerInfo &DCI,
24338 const X86Subtarget *Subtarget) {
24339 if (DCI.isBeforeLegalizeOps())
24342 if (Subtarget->hasCMov()) {
24343 SDValue RV = performIntegerAbsCombine(N, DAG);
24351 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
24352 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
24353 TargetLowering::DAGCombinerInfo &DCI,
24354 const X86Subtarget *Subtarget) {
24355 LoadSDNode *Ld = cast<LoadSDNode>(N);
24356 EVT RegVT = Ld->getValueType(0);
24357 EVT MemVT = Ld->getMemoryVT();
24359 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24361 // For chips with slow 32-byte unaligned loads, break the 32-byte operation
24362 // into two 16-byte operations.
24363 ISD::LoadExtType Ext = Ld->getExtensionType();
24364 unsigned Alignment = Ld->getAlignment();
24365 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
24366 if (RegVT.is256BitVector() && Subtarget->isUnalignedMem32Slow() &&
24367 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
24368 unsigned NumElems = RegVT.getVectorNumElements();
24372 SDValue Ptr = Ld->getBasePtr();
24373 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
24375 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
24377 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
24378 Ld->getPointerInfo(), Ld->isVolatile(),
24379 Ld->isNonTemporal(), Ld->isInvariant(),
24381 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
24382 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
24383 Ld->getPointerInfo(), Ld->isVolatile(),
24384 Ld->isNonTemporal(), Ld->isInvariant(),
24385 std::min(16U, Alignment));
24386 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
24388 Load2.getValue(1));
24390 SDValue NewVec = DAG.getUNDEF(RegVT);
24391 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
24392 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
24393 return DCI.CombineTo(N, NewVec, TF, true);
24399 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
24400 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
24401 const X86Subtarget *Subtarget) {
24402 StoreSDNode *St = cast<StoreSDNode>(N);
24403 EVT VT = St->getValue().getValueType();
24404 EVT StVT = St->getMemoryVT();
24406 SDValue StoredVal = St->getOperand(1);
24407 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24409 // If we are saving a concatenation of two XMM registers and 32-byte stores
24410 // are slow, such as on Sandy Bridge, perform two 16-byte stores.
24411 unsigned Alignment = St->getAlignment();
24412 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
24413 if (VT.is256BitVector() && Subtarget->isUnalignedMem32Slow() &&
24414 StVT == VT && !IsAligned) {
24415 unsigned NumElems = VT.getVectorNumElements();
24419 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
24420 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
24422 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
24423 SDValue Ptr0 = St->getBasePtr();
24424 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
24426 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
24427 St->getPointerInfo(), St->isVolatile(),
24428 St->isNonTemporal(), Alignment);
24429 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
24430 St->getPointerInfo(), St->isVolatile(),
24431 St->isNonTemporal(),
24432 std::min(16U, Alignment));
24433 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
24436 // Optimize trunc store (of multiple scalars) to shuffle and store.
24437 // First, pack all of the elements in one place. Next, store to memory
24438 // in fewer chunks.
24439 if (St->isTruncatingStore() && VT.isVector()) {
24440 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24441 unsigned NumElems = VT.getVectorNumElements();
24442 assert(StVT != VT && "Cannot truncate to the same type");
24443 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
24444 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
24446 // From, To sizes and ElemCount must be pow of two
24447 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
24448 // We are going to use the original vector elt for storing.
24449 // Accumulated smaller vector elements must be a multiple of the store size.
24450 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
24452 unsigned SizeRatio = FromSz / ToSz;
24454 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
24456 // Create a type on which we perform the shuffle
24457 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
24458 StVT.getScalarType(), NumElems*SizeRatio);
24460 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
24462 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
24463 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
24464 for (unsigned i = 0; i != NumElems; ++i)
24465 ShuffleVec[i] = i * SizeRatio;
24467 // Can't shuffle using an illegal type.
24468 if (!TLI.isTypeLegal(WideVecVT))
24471 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
24472 DAG.getUNDEF(WideVecVT),
24474 // At this point all of the data is stored at the bottom of the
24475 // register. We now need to save it to mem.
24477 // Find the largest store unit
24478 MVT StoreType = MVT::i8;
24479 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
24480 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
24481 MVT Tp = (MVT::SimpleValueType)tp;
24482 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
24486 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
24487 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
24488 (64 <= NumElems * ToSz))
24489 StoreType = MVT::f64;
24491 // Bitcast the original vector into a vector of store-size units
24492 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
24493 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
24494 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
24495 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
24496 SmallVector<SDValue, 8> Chains;
24497 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
24498 TLI.getPointerTy());
24499 SDValue Ptr = St->getBasePtr();
24501 // Perform one or more big stores into memory.
24502 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
24503 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
24504 StoreType, ShuffWide,
24505 DAG.getIntPtrConstant(i));
24506 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
24507 St->getPointerInfo(), St->isVolatile(),
24508 St->isNonTemporal(), St->getAlignment());
24509 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
24510 Chains.push_back(Ch);
24513 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
24516 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
24517 // the FP state in cases where an emms may be missing.
24518 // A preferable solution to the general problem is to figure out the right
24519 // places to insert EMMS. This qualifies as a quick hack.
24521 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
24522 if (VT.getSizeInBits() != 64)
24525 const Function *F = DAG.getMachineFunction().getFunction();
24526 bool NoImplicitFloatOps = F->getAttributes().
24527 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
24528 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
24529 && Subtarget->hasSSE2();
24530 if ((VT.isVector() ||
24531 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
24532 isa<LoadSDNode>(St->getValue()) &&
24533 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
24534 St->getChain().hasOneUse() && !St->isVolatile()) {
24535 SDNode* LdVal = St->getValue().getNode();
24536 LoadSDNode *Ld = nullptr;
24537 int TokenFactorIndex = -1;
24538 SmallVector<SDValue, 8> Ops;
24539 SDNode* ChainVal = St->getChain().getNode();
24540 // Must be a store of a load. We currently handle two cases: the load
24541 // is a direct child, and it's under an intervening TokenFactor. It is
24542 // possible to dig deeper under nested TokenFactors.
24543 if (ChainVal == LdVal)
24544 Ld = cast<LoadSDNode>(St->getChain());
24545 else if (St->getValue().hasOneUse() &&
24546 ChainVal->getOpcode() == ISD::TokenFactor) {
24547 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
24548 if (ChainVal->getOperand(i).getNode() == LdVal) {
24549 TokenFactorIndex = i;
24550 Ld = cast<LoadSDNode>(St->getValue());
24552 Ops.push_back(ChainVal->getOperand(i));
24556 if (!Ld || !ISD::isNormalLoad(Ld))
24559 // If this is not the MMX case, i.e. we are just turning i64 load/store
24560 // into f64 load/store, avoid the transformation if there are multiple
24561 // uses of the loaded value.
24562 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
24567 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
24568 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
24570 if (Subtarget->is64Bit() || F64IsLegal) {
24571 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
24572 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
24573 Ld->getPointerInfo(), Ld->isVolatile(),
24574 Ld->isNonTemporal(), Ld->isInvariant(),
24575 Ld->getAlignment());
24576 SDValue NewChain = NewLd.getValue(1);
24577 if (TokenFactorIndex != -1) {
24578 Ops.push_back(NewChain);
24579 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
24581 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
24582 St->getPointerInfo(),
24583 St->isVolatile(), St->isNonTemporal(),
24584 St->getAlignment());
24587 // Otherwise, lower to two pairs of 32-bit loads / stores.
24588 SDValue LoAddr = Ld->getBasePtr();
24589 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
24590 DAG.getConstant(4, MVT::i32));
24592 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
24593 Ld->getPointerInfo(),
24594 Ld->isVolatile(), Ld->isNonTemporal(),
24595 Ld->isInvariant(), Ld->getAlignment());
24596 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
24597 Ld->getPointerInfo().getWithOffset(4),
24598 Ld->isVolatile(), Ld->isNonTemporal(),
24600 MinAlign(Ld->getAlignment(), 4));
24602 SDValue NewChain = LoLd.getValue(1);
24603 if (TokenFactorIndex != -1) {
24604 Ops.push_back(LoLd);
24605 Ops.push_back(HiLd);
24606 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
24609 LoAddr = St->getBasePtr();
24610 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
24611 DAG.getConstant(4, MVT::i32));
24613 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
24614 St->getPointerInfo(),
24615 St->isVolatile(), St->isNonTemporal(),
24616 St->getAlignment());
24617 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
24618 St->getPointerInfo().getWithOffset(4),
24620 St->isNonTemporal(),
24621 MinAlign(St->getAlignment(), 4));
24622 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
24627 /// Return 'true' if this vector operation is "horizontal"
24628 /// and return the operands for the horizontal operation in LHS and RHS. A
24629 /// horizontal operation performs the binary operation on successive elements
24630 /// of its first operand, then on successive elements of its second operand,
24631 /// returning the resulting values in a vector. For example, if
24632 /// A = < float a0, float a1, float a2, float a3 >
24634 /// B = < float b0, float b1, float b2, float b3 >
24635 /// then the result of doing a horizontal operation on A and B is
24636 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
24637 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
24638 /// A horizontal-op B, for some already available A and B, and if so then LHS is
24639 /// set to A, RHS to B, and the routine returns 'true'.
24640 /// Note that the binary operation should have the property that if one of the
24641 /// operands is UNDEF then the result is UNDEF.
24642 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
24643 // Look for the following pattern: if
24644 // A = < float a0, float a1, float a2, float a3 >
24645 // B = < float b0, float b1, float b2, float b3 >
24647 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
24648 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
24649 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
24650 // which is A horizontal-op B.
24652 // At least one of the operands should be a vector shuffle.
24653 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
24654 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
24657 MVT VT = LHS.getSimpleValueType();
24659 assert((VT.is128BitVector() || VT.is256BitVector()) &&
24660 "Unsupported vector type for horizontal add/sub");
24662 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
24663 // operate independently on 128-bit lanes.
24664 unsigned NumElts = VT.getVectorNumElements();
24665 unsigned NumLanes = VT.getSizeInBits()/128;
24666 unsigned NumLaneElts = NumElts / NumLanes;
24667 assert((NumLaneElts % 2 == 0) &&
24668 "Vector type should have an even number of elements in each lane");
24669 unsigned HalfLaneElts = NumLaneElts/2;
24671 // View LHS in the form
24672 // LHS = VECTOR_SHUFFLE A, B, LMask
24673 // If LHS is not a shuffle then pretend it is the shuffle
24674 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
24675 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
24678 SmallVector<int, 16> LMask(NumElts);
24679 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
24680 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
24681 A = LHS.getOperand(0);
24682 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
24683 B = LHS.getOperand(1);
24684 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
24685 std::copy(Mask.begin(), Mask.end(), LMask.begin());
24687 if (LHS.getOpcode() != ISD::UNDEF)
24689 for (unsigned i = 0; i != NumElts; ++i)
24693 // Likewise, view RHS in the form
24694 // RHS = VECTOR_SHUFFLE C, D, RMask
24696 SmallVector<int, 16> RMask(NumElts);
24697 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
24698 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
24699 C = RHS.getOperand(0);
24700 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
24701 D = RHS.getOperand(1);
24702 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
24703 std::copy(Mask.begin(), Mask.end(), RMask.begin());
24705 if (RHS.getOpcode() != ISD::UNDEF)
24707 for (unsigned i = 0; i != NumElts; ++i)
24711 // Check that the shuffles are both shuffling the same vectors.
24712 if (!(A == C && B == D) && !(A == D && B == C))
24715 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
24716 if (!A.getNode() && !B.getNode())
24719 // If A and B occur in reverse order in RHS, then "swap" them (which means
24720 // rewriting the mask).
24722 CommuteVectorShuffleMask(RMask, NumElts);
24724 // At this point LHS and RHS are equivalent to
24725 // LHS = VECTOR_SHUFFLE A, B, LMask
24726 // RHS = VECTOR_SHUFFLE A, B, RMask
24727 // Check that the masks correspond to performing a horizontal operation.
24728 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
24729 for (unsigned i = 0; i != NumLaneElts; ++i) {
24730 int LIdx = LMask[i+l], RIdx = RMask[i+l];
24732 // Ignore any UNDEF components.
24733 if (LIdx < 0 || RIdx < 0 ||
24734 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
24735 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
24738 // Check that successive elements are being operated on. If not, this is
24739 // not a horizontal operation.
24740 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
24741 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
24742 if (!(LIdx == Index && RIdx == Index + 1) &&
24743 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
24748 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
24749 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
24753 /// Do target-specific dag combines on floating point adds.
24754 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
24755 const X86Subtarget *Subtarget) {
24756 EVT VT = N->getValueType(0);
24757 SDValue LHS = N->getOperand(0);
24758 SDValue RHS = N->getOperand(1);
24760 // Try to synthesize horizontal adds from adds of shuffles.
24761 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
24762 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
24763 isHorizontalBinOp(LHS, RHS, true))
24764 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
24768 /// Do target-specific dag combines on floating point subs.
24769 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
24770 const X86Subtarget *Subtarget) {
24771 EVT VT = N->getValueType(0);
24772 SDValue LHS = N->getOperand(0);
24773 SDValue RHS = N->getOperand(1);
24775 // Try to synthesize horizontal subs from subs of shuffles.
24776 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
24777 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
24778 isHorizontalBinOp(LHS, RHS, false))
24779 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
24783 /// Do target-specific dag combines on X86ISD::FOR and X86ISD::FXOR nodes.
24784 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
24785 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
24786 // F[X]OR(0.0, x) -> x
24787 // F[X]OR(x, 0.0) -> x
24788 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24789 if (C->getValueAPF().isPosZero())
24790 return N->getOperand(1);
24791 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24792 if (C->getValueAPF().isPosZero())
24793 return N->getOperand(0);
24797 /// Do target-specific dag combines on X86ISD::FMIN and X86ISD::FMAX nodes.
24798 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
24799 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
24801 // Only perform optimizations if UnsafeMath is used.
24802 if (!DAG.getTarget().Options.UnsafeFPMath)
24805 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
24806 // into FMINC and FMAXC, which are Commutative operations.
24807 unsigned NewOp = 0;
24808 switch (N->getOpcode()) {
24809 default: llvm_unreachable("unknown opcode");
24810 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
24811 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
24814 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
24815 N->getOperand(0), N->getOperand(1));
24818 /// Do target-specific dag combines on X86ISD::FAND nodes.
24819 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
24820 // FAND(0.0, x) -> 0.0
24821 // FAND(x, 0.0) -> 0.0
24822 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24823 if (C->getValueAPF().isPosZero())
24824 return N->getOperand(0);
24825 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24826 if (C->getValueAPF().isPosZero())
24827 return N->getOperand(1);
24831 /// Do target-specific dag combines on X86ISD::FANDN nodes
24832 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
24833 // FANDN(x, 0.0) -> 0.0
24834 // FANDN(0.0, x) -> x
24835 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24836 if (C->getValueAPF().isPosZero())
24837 return N->getOperand(1);
24838 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24839 if (C->getValueAPF().isPosZero())
24840 return N->getOperand(1);
24844 static SDValue PerformBTCombine(SDNode *N,
24846 TargetLowering::DAGCombinerInfo &DCI) {
24847 // BT ignores high bits in the bit index operand.
24848 SDValue Op1 = N->getOperand(1);
24849 if (Op1.hasOneUse()) {
24850 unsigned BitWidth = Op1.getValueSizeInBits();
24851 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
24852 APInt KnownZero, KnownOne;
24853 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
24854 !DCI.isBeforeLegalizeOps());
24855 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24856 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
24857 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
24858 DCI.CommitTargetLoweringOpt(TLO);
24863 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
24864 SDValue Op = N->getOperand(0);
24865 if (Op.getOpcode() == ISD::BITCAST)
24866 Op = Op.getOperand(0);
24867 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
24868 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
24869 VT.getVectorElementType().getSizeInBits() ==
24870 OpVT.getVectorElementType().getSizeInBits()) {
24871 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
24876 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
24877 const X86Subtarget *Subtarget) {
24878 EVT VT = N->getValueType(0);
24879 if (!VT.isVector())
24882 SDValue N0 = N->getOperand(0);
24883 SDValue N1 = N->getOperand(1);
24884 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
24887 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
24888 // both SSE and AVX2 since there is no sign-extended shift right
24889 // operation on a vector with 64-bit elements.
24890 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
24891 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
24892 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
24893 N0.getOpcode() == ISD::SIGN_EXTEND)) {
24894 SDValue N00 = N0.getOperand(0);
24896 // EXTLOAD has a better solution on AVX2,
24897 // it may be replaced with X86ISD::VSEXT node.
24898 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
24899 if (!ISD::isNormalLoad(N00.getNode()))
24902 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
24903 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
24905 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
24911 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
24912 TargetLowering::DAGCombinerInfo &DCI,
24913 const X86Subtarget *Subtarget) {
24914 SDValue N0 = N->getOperand(0);
24915 EVT VT = N->getValueType(0);
24917 // (i8,i32 sext (sdivrem (i8 x, i8 y)) ->
24918 // (i8,i32 (sdivrem_sext_hreg (i8 x, i8 y)
24919 // This exposes the sext to the sdivrem lowering, so that it directly extends
24920 // from AH (which we otherwise need to do contortions to access).
24921 if (N0.getOpcode() == ISD::SDIVREM && N0.getResNo() == 1 &&
24922 N0.getValueType() == MVT::i8 && VT == MVT::i32) {
24924 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
24925 SDValue R = DAG.getNode(X86ISD::SDIVREM8_SEXT_HREG, dl, NodeTys,
24926 N0.getOperand(0), N0.getOperand(1));
24927 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
24928 return R.getValue(1);
24931 if (!DCI.isBeforeLegalizeOps())
24934 if (!Subtarget->hasFp256())
24937 if (VT.isVector() && VT.getSizeInBits() == 256) {
24938 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
24946 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
24947 const X86Subtarget* Subtarget) {
24949 EVT VT = N->getValueType(0);
24951 // Let legalize expand this if it isn't a legal type yet.
24952 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
24955 EVT ScalarVT = VT.getScalarType();
24956 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
24957 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
24960 SDValue A = N->getOperand(0);
24961 SDValue B = N->getOperand(1);
24962 SDValue C = N->getOperand(2);
24964 bool NegA = (A.getOpcode() == ISD::FNEG);
24965 bool NegB = (B.getOpcode() == ISD::FNEG);
24966 bool NegC = (C.getOpcode() == ISD::FNEG);
24968 // Negative multiplication when NegA xor NegB
24969 bool NegMul = (NegA != NegB);
24971 A = A.getOperand(0);
24973 B = B.getOperand(0);
24975 C = C.getOperand(0);
24979 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
24981 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
24983 return DAG.getNode(Opcode, dl, VT, A, B, C);
24986 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
24987 TargetLowering::DAGCombinerInfo &DCI,
24988 const X86Subtarget *Subtarget) {
24989 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
24990 // (and (i32 x86isd::setcc_carry), 1)
24991 // This eliminates the zext. This transformation is necessary because
24992 // ISD::SETCC is always legalized to i8.
24994 SDValue N0 = N->getOperand(0);
24995 EVT VT = N->getValueType(0);
24997 if (N0.getOpcode() == ISD::AND &&
24999 N0.getOperand(0).hasOneUse()) {
25000 SDValue N00 = N0.getOperand(0);
25001 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
25002 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
25003 if (!C || C->getZExtValue() != 1)
25005 return DAG.getNode(ISD::AND, dl, VT,
25006 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
25007 N00.getOperand(0), N00.getOperand(1)),
25008 DAG.getConstant(1, VT));
25012 if (N0.getOpcode() == ISD::TRUNCATE &&
25014 N0.getOperand(0).hasOneUse()) {
25015 SDValue N00 = N0.getOperand(0);
25016 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
25017 return DAG.getNode(ISD::AND, dl, VT,
25018 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
25019 N00.getOperand(0), N00.getOperand(1)),
25020 DAG.getConstant(1, VT));
25023 if (VT.is256BitVector()) {
25024 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
25029 // (i8,i32 zext (udivrem (i8 x, i8 y)) ->
25030 // (i8,i32 (udivrem_zext_hreg (i8 x, i8 y)
25031 // This exposes the zext to the udivrem lowering, so that it directly extends
25032 // from AH (which we otherwise need to do contortions to access).
25033 if (N0.getOpcode() == ISD::UDIVREM &&
25034 N0.getResNo() == 1 && N0.getValueType() == MVT::i8 &&
25035 (VT == MVT::i32 || VT == MVT::i64)) {
25036 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
25037 SDValue R = DAG.getNode(X86ISD::UDIVREM8_ZEXT_HREG, dl, NodeTys,
25038 N0.getOperand(0), N0.getOperand(1));
25039 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
25040 return R.getValue(1);
25046 // Optimize x == -y --> x+y == 0
25047 // x != -y --> x+y != 0
25048 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
25049 const X86Subtarget* Subtarget) {
25050 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
25051 SDValue LHS = N->getOperand(0);
25052 SDValue RHS = N->getOperand(1);
25053 EVT VT = N->getValueType(0);
25056 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
25057 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
25058 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
25059 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
25060 LHS.getValueType(), RHS, LHS.getOperand(1));
25061 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
25062 addV, DAG.getConstant(0, addV.getValueType()), CC);
25064 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
25065 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
25066 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
25067 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
25068 RHS.getValueType(), LHS, RHS.getOperand(1));
25069 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
25070 addV, DAG.getConstant(0, addV.getValueType()), CC);
25073 if (VT.getScalarType() == MVT::i1) {
25074 bool IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
25075 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
25076 bool IsVZero0 = ISD::isBuildVectorAllZeros(LHS.getNode());
25077 if (!IsSEXT0 && !IsVZero0)
25079 bool IsSEXT1 = (RHS.getOpcode() == ISD::SIGN_EXTEND) &&
25080 (RHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
25081 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
25083 if (!IsSEXT1 && !IsVZero1)
25086 if (IsSEXT0 && IsVZero1) {
25087 assert(VT == LHS.getOperand(0).getValueType() && "Uexpected operand type");
25088 if (CC == ISD::SETEQ)
25089 return DAG.getNOT(DL, LHS.getOperand(0), VT);
25090 return LHS.getOperand(0);
25092 if (IsSEXT1 && IsVZero0) {
25093 assert(VT == RHS.getOperand(0).getValueType() && "Uexpected operand type");
25094 if (CC == ISD::SETEQ)
25095 return DAG.getNOT(DL, RHS.getOperand(0), VT);
25096 return RHS.getOperand(0);
25103 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
25104 const X86Subtarget *Subtarget) {
25106 MVT VT = N->getOperand(1)->getSimpleValueType(0);
25107 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
25108 "X86insertps is only defined for v4x32");
25110 SDValue Ld = N->getOperand(1);
25111 if (MayFoldLoad(Ld)) {
25112 // Extract the countS bits from the immediate so we can get the proper
25113 // address when narrowing the vector load to a specific element.
25114 // When the second source op is a memory address, interps doesn't use
25115 // countS and just gets an f32 from that address.
25116 unsigned DestIndex =
25117 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
25118 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
25122 // Create this as a scalar to vector to match the instruction pattern.
25123 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
25124 // countS bits are ignored when loading from memory on insertps, which
25125 // means we don't need to explicitly set them to 0.
25126 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
25127 LoadScalarToVector, N->getOperand(2));
25130 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
25131 // as "sbb reg,reg", since it can be extended without zext and produces
25132 // an all-ones bit which is more useful than 0/1 in some cases.
25133 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
25136 return DAG.getNode(ISD::AND, DL, VT,
25137 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
25138 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
25139 DAG.getConstant(1, VT));
25140 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
25141 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
25142 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
25143 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS));
25146 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
25147 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
25148 TargetLowering::DAGCombinerInfo &DCI,
25149 const X86Subtarget *Subtarget) {
25151 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
25152 SDValue EFLAGS = N->getOperand(1);
25154 if (CC == X86::COND_A) {
25155 // Try to convert COND_A into COND_B in an attempt to facilitate
25156 // materializing "setb reg".
25158 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
25159 // cannot take an immediate as its first operand.
25161 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
25162 EFLAGS.getValueType().isInteger() &&
25163 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
25164 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
25165 EFLAGS.getNode()->getVTList(),
25166 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
25167 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
25168 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
25172 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
25173 // a zext and produces an all-ones bit which is more useful than 0/1 in some
25175 if (CC == X86::COND_B)
25176 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
25180 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
25181 if (Flags.getNode()) {
25182 SDValue Cond = DAG.getConstant(CC, MVT::i8);
25183 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
25189 // Optimize branch condition evaluation.
25191 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
25192 TargetLowering::DAGCombinerInfo &DCI,
25193 const X86Subtarget *Subtarget) {
25195 SDValue Chain = N->getOperand(0);
25196 SDValue Dest = N->getOperand(1);
25197 SDValue EFLAGS = N->getOperand(3);
25198 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
25202 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
25203 if (Flags.getNode()) {
25204 SDValue Cond = DAG.getConstant(CC, MVT::i8);
25205 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
25212 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
25213 SelectionDAG &DAG) {
25214 // Take advantage of vector comparisons producing 0 or -1 in each lane to
25215 // optimize away operation when it's from a constant.
25217 // The general transformation is:
25218 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
25219 // AND(VECTOR_CMP(x,y), constant2)
25220 // constant2 = UNARYOP(constant)
25222 // Early exit if this isn't a vector operation, the operand of the
25223 // unary operation isn't a bitwise AND, or if the sizes of the operations
25224 // aren't the same.
25225 EVT VT = N->getValueType(0);
25226 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
25227 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
25228 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
25231 // Now check that the other operand of the AND is a constant. We could
25232 // make the transformation for non-constant splats as well, but it's unclear
25233 // that would be a benefit as it would not eliminate any operations, just
25234 // perform one more step in scalar code before moving to the vector unit.
25235 if (BuildVectorSDNode *BV =
25236 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
25237 // Bail out if the vector isn't a constant.
25238 if (!BV->isConstant())
25241 // Everything checks out. Build up the new and improved node.
25243 EVT IntVT = BV->getValueType(0);
25244 // Create a new constant of the appropriate type for the transformed
25246 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
25247 // The AND node needs bitcasts to/from an integer vector type around it.
25248 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
25249 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
25250 N->getOperand(0)->getOperand(0), MaskConst);
25251 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
25258 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
25259 const X86TargetLowering *XTLI) {
25260 // First try to optimize away the conversion entirely when it's
25261 // conditionally from a constant. Vectors only.
25262 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
25263 if (Res != SDValue())
25266 // Now move on to more general possibilities.
25267 SDValue Op0 = N->getOperand(0);
25268 EVT InVT = Op0->getValueType(0);
25270 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
25271 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
25273 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
25274 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
25275 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
25278 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
25279 // a 32-bit target where SSE doesn't support i64->FP operations.
25280 if (Op0.getOpcode() == ISD::LOAD) {
25281 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
25282 EVT VT = Ld->getValueType(0);
25283 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
25284 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
25285 !XTLI->getSubtarget()->is64Bit() &&
25287 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
25288 Ld->getChain(), Op0, DAG);
25289 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
25296 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
25297 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
25298 X86TargetLowering::DAGCombinerInfo &DCI) {
25299 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
25300 // the result is either zero or one (depending on the input carry bit).
25301 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
25302 if (X86::isZeroNode(N->getOperand(0)) &&
25303 X86::isZeroNode(N->getOperand(1)) &&
25304 // We don't have a good way to replace an EFLAGS use, so only do this when
25306 SDValue(N, 1).use_empty()) {
25308 EVT VT = N->getValueType(0);
25309 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
25310 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
25311 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
25312 DAG.getConstant(X86::COND_B,MVT::i8),
25314 DAG.getConstant(1, VT));
25315 return DCI.CombineTo(N, Res1, CarryOut);
25321 // fold (add Y, (sete X, 0)) -> adc 0, Y
25322 // (add Y, (setne X, 0)) -> sbb -1, Y
25323 // (sub (sete X, 0), Y) -> sbb 0, Y
25324 // (sub (setne X, 0), Y) -> adc -1, Y
25325 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
25328 // Look through ZExts.
25329 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
25330 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
25333 SDValue SetCC = Ext.getOperand(0);
25334 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
25337 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
25338 if (CC != X86::COND_E && CC != X86::COND_NE)
25341 SDValue Cmp = SetCC.getOperand(1);
25342 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
25343 !X86::isZeroNode(Cmp.getOperand(1)) ||
25344 !Cmp.getOperand(0).getValueType().isInteger())
25347 SDValue CmpOp0 = Cmp.getOperand(0);
25348 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
25349 DAG.getConstant(1, CmpOp0.getValueType()));
25351 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
25352 if (CC == X86::COND_NE)
25353 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
25354 DL, OtherVal.getValueType(), OtherVal,
25355 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
25356 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
25357 DL, OtherVal.getValueType(), OtherVal,
25358 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
25361 /// PerformADDCombine - Do target-specific dag combines on integer adds.
25362 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
25363 const X86Subtarget *Subtarget) {
25364 EVT VT = N->getValueType(0);
25365 SDValue Op0 = N->getOperand(0);
25366 SDValue Op1 = N->getOperand(1);
25368 // Try to synthesize horizontal adds from adds of shuffles.
25369 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
25370 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
25371 isHorizontalBinOp(Op0, Op1, true))
25372 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
25374 return OptimizeConditionalInDecrement(N, DAG);
25377 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
25378 const X86Subtarget *Subtarget) {
25379 SDValue Op0 = N->getOperand(0);
25380 SDValue Op1 = N->getOperand(1);
25382 // X86 can't encode an immediate LHS of a sub. See if we can push the
25383 // negation into a preceding instruction.
25384 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
25385 // If the RHS of the sub is a XOR with one use and a constant, invert the
25386 // immediate. Then add one to the LHS of the sub so we can turn
25387 // X-Y -> X+~Y+1, saving one register.
25388 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
25389 isa<ConstantSDNode>(Op1.getOperand(1))) {
25390 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
25391 EVT VT = Op0.getValueType();
25392 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
25394 DAG.getConstant(~XorC, VT));
25395 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
25396 DAG.getConstant(C->getAPIntValue()+1, VT));
25400 // Try to synthesize horizontal adds from adds of shuffles.
25401 EVT VT = N->getValueType(0);
25402 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
25403 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
25404 isHorizontalBinOp(Op0, Op1, true))
25405 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
25407 return OptimizeConditionalInDecrement(N, DAG);
25410 /// performVZEXTCombine - Performs build vector combines
25411 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
25412 TargetLowering::DAGCombinerInfo &DCI,
25413 const X86Subtarget *Subtarget) {
25415 MVT VT = N->getSimpleValueType(0);
25416 SDValue Op = N->getOperand(0);
25417 MVT OpVT = Op.getSimpleValueType();
25418 MVT OpEltVT = OpVT.getVectorElementType();
25419 unsigned InputBits = OpEltVT.getSizeInBits() * VT.getVectorNumElements();
25421 // (vzext (bitcast (vzext (x)) -> (vzext x)
25423 while (V.getOpcode() == ISD::BITCAST)
25424 V = V.getOperand(0);
25426 if (V != Op && V.getOpcode() == X86ISD::VZEXT) {
25427 MVT InnerVT = V.getSimpleValueType();
25428 MVT InnerEltVT = InnerVT.getVectorElementType();
25430 // If the element sizes match exactly, we can just do one larger vzext. This
25431 // is always an exact type match as vzext operates on integer types.
25432 if (OpEltVT == InnerEltVT) {
25433 assert(OpVT == InnerVT && "Types must match for vzext!");
25434 return DAG.getNode(X86ISD::VZEXT, DL, VT, V.getOperand(0));
25437 // The only other way we can combine them is if only a single element of the
25438 // inner vzext is used in the input to the outer vzext.
25439 if (InnerEltVT.getSizeInBits() < InputBits)
25442 // In this case, the inner vzext is completely dead because we're going to
25443 // only look at bits inside of the low element. Just do the outer vzext on
25444 // a bitcast of the input to the inner.
25445 return DAG.getNode(X86ISD::VZEXT, DL, VT,
25446 DAG.getNode(ISD::BITCAST, DL, OpVT, V));
25449 // Check if we can bypass extracting and re-inserting an element of an input
25450 // vector. Essentialy:
25451 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
25452 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
25453 V.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
25454 V.getOperand(0).getSimpleValueType().getSizeInBits() == InputBits) {
25455 SDValue ExtractedV = V.getOperand(0);
25456 SDValue OrigV = ExtractedV.getOperand(0);
25457 if (auto *ExtractIdx = dyn_cast<ConstantSDNode>(ExtractedV.getOperand(1)))
25458 if (ExtractIdx->getZExtValue() == 0) {
25459 MVT OrigVT = OrigV.getSimpleValueType();
25460 // Extract a subvector if necessary...
25461 if (OrigVT.getSizeInBits() > OpVT.getSizeInBits()) {
25462 int Ratio = OrigVT.getSizeInBits() / OpVT.getSizeInBits();
25463 OrigVT = MVT::getVectorVT(OrigVT.getVectorElementType(),
25464 OrigVT.getVectorNumElements() / Ratio);
25465 OrigV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigVT, OrigV,
25466 DAG.getIntPtrConstant(0));
25468 Op = DAG.getNode(ISD::BITCAST, DL, OpVT, OrigV);
25469 return DAG.getNode(X86ISD::VZEXT, DL, VT, Op);
25476 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
25477 DAGCombinerInfo &DCI) const {
25478 SelectionDAG &DAG = DCI.DAG;
25479 switch (N->getOpcode()) {
25481 case ISD::EXTRACT_VECTOR_ELT:
25482 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
25485 case X86ISD::SHRUNKBLEND:
25486 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
25487 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
25488 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
25489 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
25490 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
25491 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
25494 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
25495 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
25496 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
25497 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
25498 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
25499 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
25500 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
25501 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
25502 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
25504 case X86ISD::FOR: return PerformFORCombine(N, DAG);
25506 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
25507 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
25508 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
25509 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
25510 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
25511 case ISD::ANY_EXTEND:
25512 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
25513 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
25514 case ISD::SIGN_EXTEND_INREG:
25515 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
25516 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
25517 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
25518 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
25519 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
25520 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
25521 case X86ISD::SHUFP: // Handle all target specific shuffles
25522 case X86ISD::PALIGNR:
25523 case X86ISD::UNPCKH:
25524 case X86ISD::UNPCKL:
25525 case X86ISD::MOVHLPS:
25526 case X86ISD::MOVLHPS:
25527 case X86ISD::PSHUFB:
25528 case X86ISD::PSHUFD:
25529 case X86ISD::PSHUFHW:
25530 case X86ISD::PSHUFLW:
25531 case X86ISD::MOVSS:
25532 case X86ISD::MOVSD:
25533 case X86ISD::VPERMILPI:
25534 case X86ISD::VPERM2X128:
25535 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
25536 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
25537 case ISD::INTRINSIC_WO_CHAIN:
25538 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
25539 case X86ISD::INSERTPS:
25540 return PerformINSERTPSCombine(N, DAG, Subtarget);
25541 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DAG, Subtarget);
25547 /// isTypeDesirableForOp - Return true if the target has native support for
25548 /// the specified value type and it is 'desirable' to use the type for the
25549 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
25550 /// instruction encodings are longer and some i16 instructions are slow.
25551 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
25552 if (!isTypeLegal(VT))
25554 if (VT != MVT::i16)
25561 case ISD::SIGN_EXTEND:
25562 case ISD::ZERO_EXTEND:
25563 case ISD::ANY_EXTEND:
25576 /// IsDesirableToPromoteOp - This method query the target whether it is
25577 /// beneficial for dag combiner to promote the specified node. If true, it
25578 /// should return the desired promotion type by reference.
25579 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
25580 EVT VT = Op.getValueType();
25581 if (VT != MVT::i16)
25584 bool Promote = false;
25585 bool Commute = false;
25586 switch (Op.getOpcode()) {
25589 LoadSDNode *LD = cast<LoadSDNode>(Op);
25590 // If the non-extending load has a single use and it's not live out, then it
25591 // might be folded.
25592 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
25593 Op.hasOneUse()*/) {
25594 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
25595 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
25596 // The only case where we'd want to promote LOAD (rather then it being
25597 // promoted as an operand is when it's only use is liveout.
25598 if (UI->getOpcode() != ISD::CopyToReg)
25605 case ISD::SIGN_EXTEND:
25606 case ISD::ZERO_EXTEND:
25607 case ISD::ANY_EXTEND:
25612 SDValue N0 = Op.getOperand(0);
25613 // Look out for (store (shl (load), x)).
25614 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
25627 SDValue N0 = Op.getOperand(0);
25628 SDValue N1 = Op.getOperand(1);
25629 if (!Commute && MayFoldLoad(N1))
25631 // Avoid disabling potential load folding opportunities.
25632 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
25634 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
25644 //===----------------------------------------------------------------------===//
25645 // X86 Inline Assembly Support
25646 //===----------------------------------------------------------------------===//
25649 // Helper to match a string separated by whitespace.
25650 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
25651 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
25653 for (unsigned i = 0, e = args.size(); i != e; ++i) {
25654 StringRef piece(*args[i]);
25655 if (!s.startswith(piece)) // Check if the piece matches.
25658 s = s.substr(piece.size());
25659 StringRef::size_type pos = s.find_first_not_of(" \t");
25660 if (pos == 0) // We matched a prefix.
25668 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
25671 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
25673 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
25674 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
25675 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
25676 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
25678 if (AsmPieces.size() == 3)
25680 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
25687 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
25688 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
25690 std::string AsmStr = IA->getAsmString();
25692 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
25693 if (!Ty || Ty->getBitWidth() % 16 != 0)
25696 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
25697 SmallVector<StringRef, 4> AsmPieces;
25698 SplitString(AsmStr, AsmPieces, ";\n");
25700 switch (AsmPieces.size()) {
25701 default: return false;
25703 // FIXME: this should verify that we are targeting a 486 or better. If not,
25704 // we will turn this bswap into something that will be lowered to logical
25705 // ops instead of emitting the bswap asm. For now, we don't support 486 or
25706 // lower so don't worry about this.
25708 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
25709 matchAsm(AsmPieces[0], "bswapl", "$0") ||
25710 matchAsm(AsmPieces[0], "bswapq", "$0") ||
25711 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
25712 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
25713 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
25714 // No need to check constraints, nothing other than the equivalent of
25715 // "=r,0" would be valid here.
25716 return IntrinsicLowering::LowerToByteSwap(CI);
25719 // rorw $$8, ${0:w} --> llvm.bswap.i16
25720 if (CI->getType()->isIntegerTy(16) &&
25721 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
25722 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
25723 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
25725 const std::string &ConstraintsStr = IA->getConstraintString();
25726 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
25727 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
25728 if (clobbersFlagRegisters(AsmPieces))
25729 return IntrinsicLowering::LowerToByteSwap(CI);
25733 if (CI->getType()->isIntegerTy(32) &&
25734 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
25735 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
25736 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
25737 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
25739 const std::string &ConstraintsStr = IA->getConstraintString();
25740 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
25741 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
25742 if (clobbersFlagRegisters(AsmPieces))
25743 return IntrinsicLowering::LowerToByteSwap(CI);
25746 if (CI->getType()->isIntegerTy(64)) {
25747 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
25748 if (Constraints.size() >= 2 &&
25749 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
25750 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
25751 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
25752 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
25753 matchAsm(AsmPieces[1], "bswap", "%edx") &&
25754 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
25755 return IntrinsicLowering::LowerToByteSwap(CI);
25763 /// getConstraintType - Given a constraint letter, return the type of
25764 /// constraint it is for this target.
25765 X86TargetLowering::ConstraintType
25766 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
25767 if (Constraint.size() == 1) {
25768 switch (Constraint[0]) {
25779 return C_RegisterClass;
25803 return TargetLowering::getConstraintType(Constraint);
25806 /// Examine constraint type and operand type and determine a weight value.
25807 /// This object must already have been set up with the operand type
25808 /// and the current alternative constraint selected.
25809 TargetLowering::ConstraintWeight
25810 X86TargetLowering::getSingleConstraintMatchWeight(
25811 AsmOperandInfo &info, const char *constraint) const {
25812 ConstraintWeight weight = CW_Invalid;
25813 Value *CallOperandVal = info.CallOperandVal;
25814 // If we don't have a value, we can't do a match,
25815 // but allow it at the lowest weight.
25816 if (!CallOperandVal)
25818 Type *type = CallOperandVal->getType();
25819 // Look at the constraint type.
25820 switch (*constraint) {
25822 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
25833 if (CallOperandVal->getType()->isIntegerTy())
25834 weight = CW_SpecificReg;
25839 if (type->isFloatingPointTy())
25840 weight = CW_SpecificReg;
25843 if (type->isX86_MMXTy() && Subtarget->hasMMX())
25844 weight = CW_SpecificReg;
25848 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
25849 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
25850 weight = CW_Register;
25853 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
25854 if (C->getZExtValue() <= 31)
25855 weight = CW_Constant;
25859 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25860 if (C->getZExtValue() <= 63)
25861 weight = CW_Constant;
25865 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25866 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
25867 weight = CW_Constant;
25871 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25872 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
25873 weight = CW_Constant;
25877 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25878 if (C->getZExtValue() <= 3)
25879 weight = CW_Constant;
25883 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25884 if (C->getZExtValue() <= 0xff)
25885 weight = CW_Constant;
25890 if (dyn_cast<ConstantFP>(CallOperandVal)) {
25891 weight = CW_Constant;
25895 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25896 if ((C->getSExtValue() >= -0x80000000LL) &&
25897 (C->getSExtValue() <= 0x7fffffffLL))
25898 weight = CW_Constant;
25902 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25903 if (C->getZExtValue() <= 0xffffffff)
25904 weight = CW_Constant;
25911 /// LowerXConstraint - try to replace an X constraint, which matches anything,
25912 /// with another that has more specific requirements based on the type of the
25913 /// corresponding operand.
25914 const char *X86TargetLowering::
25915 LowerXConstraint(EVT ConstraintVT) const {
25916 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
25917 // 'f' like normal targets.
25918 if (ConstraintVT.isFloatingPoint()) {
25919 if (Subtarget->hasSSE2())
25921 if (Subtarget->hasSSE1())
25925 return TargetLowering::LowerXConstraint(ConstraintVT);
25928 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
25929 /// vector. If it is invalid, don't add anything to Ops.
25930 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
25931 std::string &Constraint,
25932 std::vector<SDValue>&Ops,
25933 SelectionDAG &DAG) const {
25936 // Only support length 1 constraints for now.
25937 if (Constraint.length() > 1) return;
25939 char ConstraintLetter = Constraint[0];
25940 switch (ConstraintLetter) {
25943 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25944 if (C->getZExtValue() <= 31) {
25945 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25951 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25952 if (C->getZExtValue() <= 63) {
25953 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25959 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25960 if (isInt<8>(C->getSExtValue())) {
25961 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25967 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25968 if (C->getZExtValue() <= 255) {
25969 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25975 // 32-bit signed value
25976 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25977 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
25978 C->getSExtValue())) {
25979 // Widen to 64 bits here to get it sign extended.
25980 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
25983 // FIXME gcc accepts some relocatable values here too, but only in certain
25984 // memory models; it's complicated.
25989 // 32-bit unsigned value
25990 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25991 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
25992 C->getZExtValue())) {
25993 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25997 // FIXME gcc accepts some relocatable values here too, but only in certain
25998 // memory models; it's complicated.
26002 // Literal immediates are always ok.
26003 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
26004 // Widen to 64 bits here to get it sign extended.
26005 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
26009 // In any sort of PIC mode addresses need to be computed at runtime by
26010 // adding in a register or some sort of table lookup. These can't
26011 // be used as immediates.
26012 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
26015 // If we are in non-pic codegen mode, we allow the address of a global (with
26016 // an optional displacement) to be used with 'i'.
26017 GlobalAddressSDNode *GA = nullptr;
26018 int64_t Offset = 0;
26020 // Match either (GA), (GA+C), (GA+C1+C2), etc.
26022 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
26023 Offset += GA->getOffset();
26025 } else if (Op.getOpcode() == ISD::ADD) {
26026 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
26027 Offset += C->getZExtValue();
26028 Op = Op.getOperand(0);
26031 } else if (Op.getOpcode() == ISD::SUB) {
26032 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
26033 Offset += -C->getZExtValue();
26034 Op = Op.getOperand(0);
26039 // Otherwise, this isn't something we can handle, reject it.
26043 const GlobalValue *GV = GA->getGlobal();
26044 // If we require an extra load to get this address, as in PIC mode, we
26045 // can't accept it.
26046 if (isGlobalStubReference(
26047 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
26050 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
26051 GA->getValueType(0), Offset);
26056 if (Result.getNode()) {
26057 Ops.push_back(Result);
26060 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
26063 std::pair<unsigned, const TargetRegisterClass*>
26064 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
26066 // First, see if this is a constraint that directly corresponds to an LLVM
26068 if (Constraint.size() == 1) {
26069 // GCC Constraint Letters
26070 switch (Constraint[0]) {
26072 // TODO: Slight differences here in allocation order and leaving
26073 // RIP in the class. Do they matter any more here than they do
26074 // in the normal allocation?
26075 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
26076 if (Subtarget->is64Bit()) {
26077 if (VT == MVT::i32 || VT == MVT::f32)
26078 return std::make_pair(0U, &X86::GR32RegClass);
26079 if (VT == MVT::i16)
26080 return std::make_pair(0U, &X86::GR16RegClass);
26081 if (VT == MVT::i8 || VT == MVT::i1)
26082 return std::make_pair(0U, &X86::GR8RegClass);
26083 if (VT == MVT::i64 || VT == MVT::f64)
26084 return std::make_pair(0U, &X86::GR64RegClass);
26087 // 32-bit fallthrough
26088 case 'Q': // Q_REGS
26089 if (VT == MVT::i32 || VT == MVT::f32)
26090 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
26091 if (VT == MVT::i16)
26092 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
26093 if (VT == MVT::i8 || VT == MVT::i1)
26094 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
26095 if (VT == MVT::i64)
26096 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
26098 case 'r': // GENERAL_REGS
26099 case 'l': // INDEX_REGS
26100 if (VT == MVT::i8 || VT == MVT::i1)
26101 return std::make_pair(0U, &X86::GR8RegClass);
26102 if (VT == MVT::i16)
26103 return std::make_pair(0U, &X86::GR16RegClass);
26104 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
26105 return std::make_pair(0U, &X86::GR32RegClass);
26106 return std::make_pair(0U, &X86::GR64RegClass);
26107 case 'R': // LEGACY_REGS
26108 if (VT == MVT::i8 || VT == MVT::i1)
26109 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
26110 if (VT == MVT::i16)
26111 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
26112 if (VT == MVT::i32 || !Subtarget->is64Bit())
26113 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
26114 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
26115 case 'f': // FP Stack registers.
26116 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
26117 // value to the correct fpstack register class.
26118 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
26119 return std::make_pair(0U, &X86::RFP32RegClass);
26120 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
26121 return std::make_pair(0U, &X86::RFP64RegClass);
26122 return std::make_pair(0U, &X86::RFP80RegClass);
26123 case 'y': // MMX_REGS if MMX allowed.
26124 if (!Subtarget->hasMMX()) break;
26125 return std::make_pair(0U, &X86::VR64RegClass);
26126 case 'Y': // SSE_REGS if SSE2 allowed
26127 if (!Subtarget->hasSSE2()) break;
26129 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
26130 if (!Subtarget->hasSSE1()) break;
26132 switch (VT.SimpleTy) {
26134 // Scalar SSE types.
26137 return std::make_pair(0U, &X86::FR32RegClass);
26140 return std::make_pair(0U, &X86::FR64RegClass);
26148 return std::make_pair(0U, &X86::VR128RegClass);
26156 return std::make_pair(0U, &X86::VR256RegClass);
26161 return std::make_pair(0U, &X86::VR512RegClass);
26167 // Use the default implementation in TargetLowering to convert the register
26168 // constraint into a member of a register class.
26169 std::pair<unsigned, const TargetRegisterClass*> Res;
26170 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
26172 // Not found as a standard register?
26174 // Map st(0) -> st(7) -> ST0
26175 if (Constraint.size() == 7 && Constraint[0] == '{' &&
26176 tolower(Constraint[1]) == 's' &&
26177 tolower(Constraint[2]) == 't' &&
26178 Constraint[3] == '(' &&
26179 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
26180 Constraint[5] == ')' &&
26181 Constraint[6] == '}') {
26183 Res.first = X86::FP0+Constraint[4]-'0';
26184 Res.second = &X86::RFP80RegClass;
26188 // GCC allows "st(0)" to be called just plain "st".
26189 if (StringRef("{st}").equals_lower(Constraint)) {
26190 Res.first = X86::FP0;
26191 Res.second = &X86::RFP80RegClass;
26196 if (StringRef("{flags}").equals_lower(Constraint)) {
26197 Res.first = X86::EFLAGS;
26198 Res.second = &X86::CCRRegClass;
26202 // 'A' means EAX + EDX.
26203 if (Constraint == "A") {
26204 Res.first = X86::EAX;
26205 Res.second = &X86::GR32_ADRegClass;
26211 // Otherwise, check to see if this is a register class of the wrong value
26212 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
26213 // turn into {ax},{dx}.
26214 if (Res.second->hasType(VT))
26215 return Res; // Correct type already, nothing to do.
26217 // All of the single-register GCC register classes map their values onto
26218 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
26219 // really want an 8-bit or 32-bit register, map to the appropriate register
26220 // class and return the appropriate register.
26221 if (Res.second == &X86::GR16RegClass) {
26222 if (VT == MVT::i8 || VT == MVT::i1) {
26223 unsigned DestReg = 0;
26224 switch (Res.first) {
26226 case X86::AX: DestReg = X86::AL; break;
26227 case X86::DX: DestReg = X86::DL; break;
26228 case X86::CX: DestReg = X86::CL; break;
26229 case X86::BX: DestReg = X86::BL; break;
26232 Res.first = DestReg;
26233 Res.second = &X86::GR8RegClass;
26235 } else if (VT == MVT::i32 || VT == MVT::f32) {
26236 unsigned DestReg = 0;
26237 switch (Res.first) {
26239 case X86::AX: DestReg = X86::EAX; break;
26240 case X86::DX: DestReg = X86::EDX; break;
26241 case X86::CX: DestReg = X86::ECX; break;
26242 case X86::BX: DestReg = X86::EBX; break;
26243 case X86::SI: DestReg = X86::ESI; break;
26244 case X86::DI: DestReg = X86::EDI; break;
26245 case X86::BP: DestReg = X86::EBP; break;
26246 case X86::SP: DestReg = X86::ESP; break;
26249 Res.first = DestReg;
26250 Res.second = &X86::GR32RegClass;
26252 } else if (VT == MVT::i64 || VT == MVT::f64) {
26253 unsigned DestReg = 0;
26254 switch (Res.first) {
26256 case X86::AX: DestReg = X86::RAX; break;
26257 case X86::DX: DestReg = X86::RDX; break;
26258 case X86::CX: DestReg = X86::RCX; break;
26259 case X86::BX: DestReg = X86::RBX; break;
26260 case X86::SI: DestReg = X86::RSI; break;
26261 case X86::DI: DestReg = X86::RDI; break;
26262 case X86::BP: DestReg = X86::RBP; break;
26263 case X86::SP: DestReg = X86::RSP; break;
26266 Res.first = DestReg;
26267 Res.second = &X86::GR64RegClass;
26270 } else if (Res.second == &X86::FR32RegClass ||
26271 Res.second == &X86::FR64RegClass ||
26272 Res.second == &X86::VR128RegClass ||
26273 Res.second == &X86::VR256RegClass ||
26274 Res.second == &X86::FR32XRegClass ||
26275 Res.second == &X86::FR64XRegClass ||
26276 Res.second == &X86::VR128XRegClass ||
26277 Res.second == &X86::VR256XRegClass ||
26278 Res.second == &X86::VR512RegClass) {
26279 // Handle references to XMM physical registers that got mapped into the
26280 // wrong class. This can happen with constraints like {xmm0} where the
26281 // target independent register mapper will just pick the first match it can
26282 // find, ignoring the required type.
26284 if (VT == MVT::f32 || VT == MVT::i32)
26285 Res.second = &X86::FR32RegClass;
26286 else if (VT == MVT::f64 || VT == MVT::i64)
26287 Res.second = &X86::FR64RegClass;
26288 else if (X86::VR128RegClass.hasType(VT))
26289 Res.second = &X86::VR128RegClass;
26290 else if (X86::VR256RegClass.hasType(VT))
26291 Res.second = &X86::VR256RegClass;
26292 else if (X86::VR512RegClass.hasType(VT))
26293 Res.second = &X86::VR512RegClass;
26299 int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
26301 // Scaling factors are not free at all.
26302 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
26303 // will take 2 allocations in the out of order engine instead of 1
26304 // for plain addressing mode, i.e. inst (reg1).
26306 // vaddps (%rsi,%drx), %ymm0, %ymm1
26307 // Requires two allocations (one for the load, one for the computation)
26309 // vaddps (%rsi), %ymm0, %ymm1
26310 // Requires just 1 allocation, i.e., freeing allocations for other operations
26311 // and having less micro operations to execute.
26313 // For some X86 architectures, this is even worse because for instance for
26314 // stores, the complex addressing mode forces the instruction to use the
26315 // "load" ports instead of the dedicated "store" port.
26316 // E.g., on Haswell:
26317 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
26318 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
26319 if (isLegalAddressingMode(AM, Ty))
26320 // Scale represents reg2 * scale, thus account for 1
26321 // as soon as we use a second register.
26322 return AM.Scale != 0;
26326 bool X86TargetLowering::isTargetFTOL() const {
26327 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();