1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86FrameLowering.h"
19 #include "X86InstrBuilder.h"
20 #include "X86MachineFunctionInfo.h"
21 #include "X86TargetMachine.h"
22 #include "X86TargetObjectFile.h"
23 #include "llvm/ADT/SmallBitVector.h"
24 #include "llvm/ADT/SmallSet.h"
25 #include "llvm/ADT/Statistic.h"
26 #include "llvm/ADT/StringExtras.h"
27 #include "llvm/ADT/StringSwitch.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/WinEHFuncInfo.h"
36 #include "llvm/IR/CallSite.h"
37 #include "llvm/IR/CallingConv.h"
38 #include "llvm/IR/Constants.h"
39 #include "llvm/IR/DerivedTypes.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/IR/GlobalAlias.h"
42 #include "llvm/IR/GlobalVariable.h"
43 #include "llvm/IR/Instructions.h"
44 #include "llvm/IR/Intrinsics.h"
45 #include "llvm/MC/MCAsmInfo.h"
46 #include "llvm/MC/MCContext.h"
47 #include "llvm/MC/MCExpr.h"
48 #include "llvm/MC/MCSymbol.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/Debug.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/MathExtras.h"
53 #include "llvm/Target/TargetOptions.h"
54 #include "X86IntrinsicsInfo.h"
60 #define DEBUG_TYPE "x86-isel"
62 STATISTIC(NumTailCalls, "Number of tail calls");
64 static cl::opt<bool> ExperimentalVectorWideningLegalization(
65 "x86-experimental-vector-widening-legalization", cl::init(false),
66 cl::desc("Enable an experimental vector type legalization through widening "
67 "rather than promotion."),
70 // Forward declarations.
71 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
74 X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
75 const X86Subtarget &STI)
76 : TargetLowering(TM), Subtarget(&STI) {
77 X86ScalarSSEf64 = Subtarget->hasSSE2();
78 X86ScalarSSEf32 = Subtarget->hasSSE1();
81 // Set up the TargetLowering object.
82 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
84 // X86 is weird. It always uses i8 for shift amounts and setcc results.
85 setBooleanContents(ZeroOrOneBooleanContent);
86 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
87 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
89 // For 64-bit, since we have so many registers, use the ILP scheduler.
90 // For 32-bit, use the register pressure specific scheduling.
91 // For Atom, always use ILP scheduling.
92 if (Subtarget->isAtom())
93 setSchedulingPreference(Sched::ILP);
94 else if (Subtarget->is64Bit())
95 setSchedulingPreference(Sched::ILP);
97 setSchedulingPreference(Sched::RegPressure);
98 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
99 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
101 // Bypass expensive divides on Atom when compiling with O2.
102 if (TM.getOptLevel() >= CodeGenOpt::Default) {
103 if (Subtarget->hasSlowDivide32())
104 addBypassSlowDiv(32, 8);
105 if (Subtarget->hasSlowDivide64() && Subtarget->is64Bit())
106 addBypassSlowDiv(64, 16);
109 if (Subtarget->isTargetKnownWindowsMSVC()) {
110 // Setup Windows compiler runtime calls.
111 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
112 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
113 setLibcallName(RTLIB::SREM_I64, "_allrem");
114 setLibcallName(RTLIB::UREM_I64, "_aullrem");
115 setLibcallName(RTLIB::MUL_I64, "_allmul");
116 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
117 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
118 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
119 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
120 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
122 // The _ftol2 runtime function has an unusual calling conv, which
123 // is modeled by a special pseudo-instruction.
124 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
125 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
126 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
127 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
130 if (Subtarget->isTargetDarwin()) {
131 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
132 setUseUnderscoreSetJmp(false);
133 setUseUnderscoreLongJmp(false);
134 } else if (Subtarget->isTargetWindowsGNU()) {
135 // MS runtime is weird: it exports _setjmp, but longjmp!
136 setUseUnderscoreSetJmp(true);
137 setUseUnderscoreLongJmp(false);
139 setUseUnderscoreSetJmp(true);
140 setUseUnderscoreLongJmp(true);
143 // Set up the register classes.
144 addRegisterClass(MVT::i8, &X86::GR8RegClass);
145 addRegisterClass(MVT::i16, &X86::GR16RegClass);
146 addRegisterClass(MVT::i32, &X86::GR32RegClass);
147 if (Subtarget->is64Bit())
148 addRegisterClass(MVT::i64, &X86::GR64RegClass);
150 for (MVT VT : MVT::integer_valuetypes())
151 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
153 // We don't accept any truncstore of integer registers.
154 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
155 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
156 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
157 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
158 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
159 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
161 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
163 // SETOEQ and SETUNE require checking two conditions.
164 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
165 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
166 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
167 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
168 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
169 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
171 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
173 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
174 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
175 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
177 if (Subtarget->is64Bit()) {
178 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
179 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
180 } else if (!Subtarget->useSoftFloat()) {
181 // We have an algorithm for SSE2->double, and we turn this into a
182 // 64-bit FILD followed by conditional FADD for other targets.
183 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
184 // We have an algorithm for SSE2, and we turn this into a 64-bit
185 // FILD for other targets.
186 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
189 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
191 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
192 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
194 if (!Subtarget->useSoftFloat()) {
195 // SSE has no i16 to fp conversion, only i32
196 if (X86ScalarSSEf32) {
197 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
198 // f32 and f64 cases are Legal, f80 case is not
199 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
201 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
202 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
205 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
206 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
209 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
210 // are Legal, f80 is custom lowered.
211 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
212 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
214 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
216 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
217 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
219 if (X86ScalarSSEf32) {
220 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
221 // f32 and f64 cases are Legal, f80 case is not
222 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
224 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
225 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
228 // Handle FP_TO_UINT by promoting the destination to a larger signed
230 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
231 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
232 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
234 if (Subtarget->is64Bit()) {
235 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
236 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
237 } else if (!Subtarget->useSoftFloat()) {
238 // Since AVX is a superset of SSE3, only check for SSE here.
239 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
240 // Expand FP_TO_UINT into a select.
241 // FIXME: We would like to use a Custom expander here eventually to do
242 // the optimal thing for SSE vs. the default expansion in the legalizer.
243 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
245 // With SSE3 we can use fisttpll to convert to a signed i64; without
246 // SSE, we're stuck with a fistpll.
247 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
250 if (isTargetFTOL()) {
251 // Use the _ftol2 runtime function, which has a pseudo-instruction
252 // to handle its weird calling convention.
253 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
256 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
257 if (!X86ScalarSSEf64) {
258 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
259 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
260 if (Subtarget->is64Bit()) {
261 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
262 // Without SSE, i64->f64 goes through memory.
263 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
267 // Scalar integer divide and remainder are lowered to use operations that
268 // produce two results, to match the available instructions. This exposes
269 // the two-result form to trivial CSE, which is able to combine x/y and x%y
270 // into a single instruction.
272 // Scalar integer multiply-high is also lowered to use two-result
273 // operations, to match the available instructions. However, plain multiply
274 // (low) operations are left as Legal, as there are single-result
275 // instructions for this in x86. Using the two-result multiply instructions
276 // when both high and low results are needed must be arranged by dagcombine.
277 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
279 setOperationAction(ISD::MULHS, VT, Expand);
280 setOperationAction(ISD::MULHU, VT, Expand);
281 setOperationAction(ISD::SDIV, VT, Expand);
282 setOperationAction(ISD::UDIV, VT, Expand);
283 setOperationAction(ISD::SREM, VT, Expand);
284 setOperationAction(ISD::UREM, VT, Expand);
286 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
287 setOperationAction(ISD::ADDC, VT, Custom);
288 setOperationAction(ISD::ADDE, VT, Custom);
289 setOperationAction(ISD::SUBC, VT, Custom);
290 setOperationAction(ISD::SUBE, VT, Custom);
293 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
294 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
295 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
296 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
297 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
298 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
299 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
300 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
301 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
302 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
303 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
304 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
305 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
306 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
307 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
308 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
309 if (Subtarget->is64Bit())
310 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
311 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
312 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
313 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
314 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
315 setOperationAction(ISD::FREM , MVT::f32 , Expand);
316 setOperationAction(ISD::FREM , MVT::f64 , Expand);
317 setOperationAction(ISD::FREM , MVT::f80 , Expand);
318 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
320 // Promote the i8 variants and force them on up to i32 which has a shorter
322 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
323 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
324 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
325 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
326 if (Subtarget->hasBMI()) {
327 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
328 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
329 if (Subtarget->is64Bit())
330 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
332 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
333 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
334 if (Subtarget->is64Bit())
335 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
338 if (Subtarget->hasLZCNT()) {
339 // When promoting the i8 variants, force them to i32 for a shorter
341 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
342 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
343 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
344 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
345 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
346 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
347 if (Subtarget->is64Bit())
348 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
350 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
351 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
352 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
353 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
354 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
355 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
356 if (Subtarget->is64Bit()) {
357 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
358 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
362 // Special handling for half-precision floating point conversions.
363 // If we don't have F16C support, then lower half float conversions
364 // into library calls.
365 if (Subtarget->useSoftFloat() || !Subtarget->hasF16C()) {
366 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
367 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
370 // There's never any support for operations beyond MVT::f32.
371 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
372 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
373 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
374 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
376 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
377 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
378 setLoadExtAction(ISD::EXTLOAD, MVT::f80, MVT::f16, Expand);
379 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
380 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
381 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
383 if (Subtarget->hasPOPCNT()) {
384 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
386 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
387 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
388 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
389 if (Subtarget->is64Bit())
390 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
393 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
395 if (!Subtarget->hasMOVBE())
396 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
398 // These should be promoted to a larger select which is supported.
399 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
400 // X86 wants to expand cmov itself.
401 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
402 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
403 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
404 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
405 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
406 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
407 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
408 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
409 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
410 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
411 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
412 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
413 if (Subtarget->is64Bit()) {
414 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
415 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
417 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
418 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
419 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
420 // support continuation, user-level threading, and etc.. As a result, no
421 // other SjLj exception interfaces are implemented and please don't build
422 // your own exception handling based on them.
423 // LLVM/Clang supports zero-cost DWARF exception handling.
424 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
425 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
428 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
429 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
430 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
431 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
432 if (Subtarget->is64Bit())
433 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
434 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
435 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
436 if (Subtarget->is64Bit()) {
437 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
438 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
439 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
440 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
441 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
443 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
444 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
445 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
446 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
447 if (Subtarget->is64Bit()) {
448 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
449 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
450 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
453 if (Subtarget->hasSSE1())
454 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
456 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
458 // Expand certain atomics
459 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
461 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
462 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
463 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
466 if (Subtarget->hasCmpxchg16b()) {
467 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
470 // FIXME - use subtarget debug flags
471 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
472 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
473 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
476 if (Subtarget->is64Bit()) {
477 setExceptionPointerRegister(X86::RAX);
478 setExceptionSelectorRegister(X86::RDX);
480 setExceptionPointerRegister(X86::EAX);
481 setExceptionSelectorRegister(X86::EDX);
483 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
484 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
486 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
487 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
489 setOperationAction(ISD::TRAP, MVT::Other, Legal);
490 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
492 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
493 setOperationAction(ISD::VASTART , MVT::Other, Custom);
494 setOperationAction(ISD::VAEND , MVT::Other, Expand);
495 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
496 // TargetInfo::X86_64ABIBuiltinVaList
497 setOperationAction(ISD::VAARG , MVT::Other, Custom);
498 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
500 // TargetInfo::CharPtrBuiltinVaList
501 setOperationAction(ISD::VAARG , MVT::Other, Expand);
502 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
505 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
506 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
508 setOperationAction(ISD::DYNAMIC_STACKALLOC, getPointerTy(), Custom);
510 // GC_TRANSITION_START and GC_TRANSITION_END need custom lowering.
511 setOperationAction(ISD::GC_TRANSITION_START, MVT::Other, Custom);
512 setOperationAction(ISD::GC_TRANSITION_END, MVT::Other, Custom);
514 if (!Subtarget->useSoftFloat() && X86ScalarSSEf64) {
515 // f32 and f64 use SSE.
516 // Set up the FP register classes.
517 addRegisterClass(MVT::f32, &X86::FR32RegClass);
518 addRegisterClass(MVT::f64, &X86::FR64RegClass);
520 // Use ANDPD to simulate FABS.
521 setOperationAction(ISD::FABS , MVT::f64, Custom);
522 setOperationAction(ISD::FABS , MVT::f32, Custom);
524 // Use XORP to simulate FNEG.
525 setOperationAction(ISD::FNEG , MVT::f64, Custom);
526 setOperationAction(ISD::FNEG , MVT::f32, Custom);
528 // Use ANDPD and ORPD to simulate FCOPYSIGN.
529 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
530 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
532 // Lower this to FGETSIGNx86 plus an AND.
533 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
534 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
536 // We don't support sin/cos/fmod
537 setOperationAction(ISD::FSIN , MVT::f64, Expand);
538 setOperationAction(ISD::FCOS , MVT::f64, Expand);
539 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
540 setOperationAction(ISD::FSIN , MVT::f32, Expand);
541 setOperationAction(ISD::FCOS , MVT::f32, Expand);
542 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
544 // Expand FP immediates into loads from the stack, except for the special
546 addLegalFPImmediate(APFloat(+0.0)); // xorpd
547 addLegalFPImmediate(APFloat(+0.0f)); // xorps
548 } else if (!Subtarget->useSoftFloat() && X86ScalarSSEf32) {
549 // Use SSE for f32, x87 for f64.
550 // Set up the FP register classes.
551 addRegisterClass(MVT::f32, &X86::FR32RegClass);
552 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
554 // Use ANDPS to simulate FABS.
555 setOperationAction(ISD::FABS , MVT::f32, Custom);
557 // Use XORP to simulate FNEG.
558 setOperationAction(ISD::FNEG , MVT::f32, Custom);
560 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
562 // Use ANDPS and ORPS to simulate FCOPYSIGN.
563 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
564 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
566 // We don't support sin/cos/fmod
567 setOperationAction(ISD::FSIN , MVT::f32, Expand);
568 setOperationAction(ISD::FCOS , MVT::f32, Expand);
569 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
571 // Special cases we handle for FP constants.
572 addLegalFPImmediate(APFloat(+0.0f)); // xorps
573 addLegalFPImmediate(APFloat(+0.0)); // FLD0
574 addLegalFPImmediate(APFloat(+1.0)); // FLD1
575 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
576 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
578 if (!TM.Options.UnsafeFPMath) {
579 setOperationAction(ISD::FSIN , MVT::f64, Expand);
580 setOperationAction(ISD::FCOS , MVT::f64, Expand);
581 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
583 } else if (!Subtarget->useSoftFloat()) {
584 // f32 and f64 in x87.
585 // Set up the FP register classes.
586 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
587 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
589 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
590 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
591 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
592 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
594 if (!TM.Options.UnsafeFPMath) {
595 setOperationAction(ISD::FSIN , MVT::f64, Expand);
596 setOperationAction(ISD::FSIN , MVT::f32, Expand);
597 setOperationAction(ISD::FCOS , MVT::f64, Expand);
598 setOperationAction(ISD::FCOS , MVT::f32, Expand);
599 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
600 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
602 addLegalFPImmediate(APFloat(+0.0)); // FLD0
603 addLegalFPImmediate(APFloat(+1.0)); // FLD1
604 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
605 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
606 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
607 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
608 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
609 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
612 // We don't support FMA.
613 setOperationAction(ISD::FMA, MVT::f64, Expand);
614 setOperationAction(ISD::FMA, MVT::f32, Expand);
616 // Long double always uses X87.
617 if (!Subtarget->useSoftFloat()) {
618 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
619 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
620 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
622 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
623 addLegalFPImmediate(TmpFlt); // FLD0
625 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
628 APFloat TmpFlt2(+1.0);
629 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
631 addLegalFPImmediate(TmpFlt2); // FLD1
632 TmpFlt2.changeSign();
633 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
636 if (!TM.Options.UnsafeFPMath) {
637 setOperationAction(ISD::FSIN , MVT::f80, Expand);
638 setOperationAction(ISD::FCOS , MVT::f80, Expand);
639 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
642 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
643 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
644 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
645 setOperationAction(ISD::FRINT, MVT::f80, Expand);
646 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
647 setOperationAction(ISD::FMA, MVT::f80, Expand);
650 // Always use a library call for pow.
651 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
652 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
653 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
655 setOperationAction(ISD::FLOG, MVT::f80, Expand);
656 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
657 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
658 setOperationAction(ISD::FEXP, MVT::f80, Expand);
659 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
660 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
661 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
663 // First set operation action for all vector types to either promote
664 // (for widening) or expand (for scalarization). Then we will selectively
665 // turn on ones that can be effectively codegen'd.
666 for (MVT VT : MVT::vector_valuetypes()) {
667 setOperationAction(ISD::ADD , VT, Expand);
668 setOperationAction(ISD::SUB , VT, Expand);
669 setOperationAction(ISD::FADD, VT, Expand);
670 setOperationAction(ISD::FNEG, VT, Expand);
671 setOperationAction(ISD::FSUB, VT, Expand);
672 setOperationAction(ISD::MUL , VT, Expand);
673 setOperationAction(ISD::FMUL, VT, Expand);
674 setOperationAction(ISD::SDIV, VT, Expand);
675 setOperationAction(ISD::UDIV, VT, Expand);
676 setOperationAction(ISD::FDIV, VT, Expand);
677 setOperationAction(ISD::SREM, VT, Expand);
678 setOperationAction(ISD::UREM, VT, Expand);
679 setOperationAction(ISD::LOAD, VT, Expand);
680 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
681 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
682 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
683 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
684 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
685 setOperationAction(ISD::FABS, VT, Expand);
686 setOperationAction(ISD::FSIN, VT, Expand);
687 setOperationAction(ISD::FSINCOS, VT, Expand);
688 setOperationAction(ISD::FCOS, VT, Expand);
689 setOperationAction(ISD::FSINCOS, VT, Expand);
690 setOperationAction(ISD::FREM, VT, Expand);
691 setOperationAction(ISD::FMA, VT, Expand);
692 setOperationAction(ISD::FPOWI, VT, Expand);
693 setOperationAction(ISD::FSQRT, VT, Expand);
694 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
695 setOperationAction(ISD::FFLOOR, VT, Expand);
696 setOperationAction(ISD::FCEIL, VT, Expand);
697 setOperationAction(ISD::FTRUNC, VT, Expand);
698 setOperationAction(ISD::FRINT, VT, Expand);
699 setOperationAction(ISD::FNEARBYINT, VT, Expand);
700 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
701 setOperationAction(ISD::MULHS, VT, Expand);
702 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
703 setOperationAction(ISD::MULHU, VT, Expand);
704 setOperationAction(ISD::SDIVREM, VT, Expand);
705 setOperationAction(ISD::UDIVREM, VT, Expand);
706 setOperationAction(ISD::FPOW, VT, Expand);
707 setOperationAction(ISD::CTPOP, VT, Expand);
708 setOperationAction(ISD::CTTZ, VT, Expand);
709 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
710 setOperationAction(ISD::CTLZ, VT, Expand);
711 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
712 setOperationAction(ISD::SHL, VT, Expand);
713 setOperationAction(ISD::SRA, VT, Expand);
714 setOperationAction(ISD::SRL, VT, Expand);
715 setOperationAction(ISD::ROTL, VT, Expand);
716 setOperationAction(ISD::ROTR, VT, Expand);
717 setOperationAction(ISD::BSWAP, VT, Expand);
718 setOperationAction(ISD::SETCC, VT, Expand);
719 setOperationAction(ISD::FLOG, VT, Expand);
720 setOperationAction(ISD::FLOG2, VT, Expand);
721 setOperationAction(ISD::FLOG10, VT, Expand);
722 setOperationAction(ISD::FEXP, VT, Expand);
723 setOperationAction(ISD::FEXP2, VT, Expand);
724 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
725 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
726 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
727 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
728 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
729 setOperationAction(ISD::TRUNCATE, VT, Expand);
730 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
731 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
732 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
733 setOperationAction(ISD::VSELECT, VT, Expand);
734 setOperationAction(ISD::SELECT_CC, VT, Expand);
735 for (MVT InnerVT : MVT::vector_valuetypes()) {
736 setTruncStoreAction(InnerVT, VT, Expand);
738 setLoadExtAction(ISD::SEXTLOAD, InnerVT, VT, Expand);
739 setLoadExtAction(ISD::ZEXTLOAD, InnerVT, VT, Expand);
741 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like
742 // types, we have to deal with them whether we ask for Expansion or not.
743 // Setting Expand causes its own optimisation problems though, so leave
745 if (VT.getVectorElementType() == MVT::i1)
746 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
748 // EXTLOAD for MVT::f16 vectors is not legal because f16 vectors are
749 // split/scalarized right now.
750 if (VT.getVectorElementType() == MVT::f16)
751 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
755 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
756 // with -msoft-float, disable use of MMX as well.
757 if (!Subtarget->useSoftFloat() && Subtarget->hasMMX()) {
758 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
759 // No operations on x86mmx supported, everything uses intrinsics.
762 // MMX-sized vectors (other than x86mmx) are expected to be expanded
763 // into smaller operations.
764 for (MVT MMXTy : {MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::v1i64}) {
765 setOperationAction(ISD::MULHS, MMXTy, Expand);
766 setOperationAction(ISD::AND, MMXTy, Expand);
767 setOperationAction(ISD::OR, MMXTy, Expand);
768 setOperationAction(ISD::XOR, MMXTy, Expand);
769 setOperationAction(ISD::SCALAR_TO_VECTOR, MMXTy, Expand);
770 setOperationAction(ISD::SELECT, MMXTy, Expand);
771 setOperationAction(ISD::BITCAST, MMXTy, Expand);
773 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
775 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE1()) {
776 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
778 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
779 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
780 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
781 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
782 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
783 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
784 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
785 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
786 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
787 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
788 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
789 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
790 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
791 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
794 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE2()) {
795 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
797 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
798 // registers cannot be used even for integer operations.
799 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
800 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
801 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
802 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
804 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
805 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
806 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
807 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
808 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
809 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
810 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
811 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
812 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
813 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
814 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
815 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
816 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
817 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
818 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
819 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
820 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
821 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
822 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
823 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
824 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
825 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
826 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
828 setOperationAction(ISD::SMAX, MVT::v8i16, Legal);
829 setOperationAction(ISD::UMAX, MVT::v16i8, Legal);
830 setOperationAction(ISD::SMIN, MVT::v8i16, Legal);
831 setOperationAction(ISD::UMIN, MVT::v16i8, Legal);
833 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
834 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
835 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
836 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
838 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
839 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
840 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
841 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
842 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
844 setOperationAction(ISD::CTPOP, MVT::v16i8, Custom);
845 setOperationAction(ISD::CTPOP, MVT::v8i16, Custom);
846 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
847 setOperationAction(ISD::CTPOP, MVT::v2i64, Custom);
849 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
850 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
851 MVT VT = (MVT::SimpleValueType)i;
852 // Do not attempt to custom lower non-power-of-2 vectors
853 if (!isPowerOf2_32(VT.getVectorNumElements()))
855 // Do not attempt to custom lower non-128-bit vectors
856 if (!VT.is128BitVector())
858 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
859 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
860 setOperationAction(ISD::VSELECT, VT, Custom);
861 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
864 // We support custom legalizing of sext and anyext loads for specific
865 // memory vector types which we can load as a scalar (or sequence of
866 // scalars) and extend in-register to a legal 128-bit vector type. For sext
867 // loads these must work with a single scalar load.
868 for (MVT VT : MVT::integer_vector_valuetypes()) {
869 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Custom);
870 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Custom);
871 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v8i8, Custom);
872 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Custom);
873 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Custom);
874 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i32, Custom);
875 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Custom);
876 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Custom);
877 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8i8, Custom);
880 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
881 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
882 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
883 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
884 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
885 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
886 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
887 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
889 if (Subtarget->is64Bit()) {
890 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
891 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
894 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
895 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
896 MVT VT = (MVT::SimpleValueType)i;
898 // Do not attempt to promote non-128-bit vectors
899 if (!VT.is128BitVector())
902 setOperationAction(ISD::AND, VT, Promote);
903 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
904 setOperationAction(ISD::OR, VT, Promote);
905 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
906 setOperationAction(ISD::XOR, VT, Promote);
907 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
908 setOperationAction(ISD::LOAD, VT, Promote);
909 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
910 setOperationAction(ISD::SELECT, VT, Promote);
911 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
914 // Custom lower v2i64 and v2f64 selects.
915 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
916 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
917 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
918 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
920 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
921 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
923 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
925 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
926 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
927 // As there is no 64-bit GPR available, we need build a special custom
928 // sequence to convert from v2i32 to v2f32.
929 if (!Subtarget->is64Bit())
930 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
932 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
933 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
935 for (MVT VT : MVT::fp_vector_valuetypes())
936 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2f32, Legal);
938 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
939 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
940 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
943 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE41()) {
944 for (MVT RoundedTy : {MVT::f32, MVT::f64, MVT::v4f32, MVT::v2f64}) {
945 setOperationAction(ISD::FFLOOR, RoundedTy, Legal);
946 setOperationAction(ISD::FCEIL, RoundedTy, Legal);
947 setOperationAction(ISD::FTRUNC, RoundedTy, Legal);
948 setOperationAction(ISD::FRINT, RoundedTy, Legal);
949 setOperationAction(ISD::FNEARBYINT, RoundedTy, Legal);
952 setOperationAction(ISD::SMAX, MVT::v16i8, Legal);
953 setOperationAction(ISD::SMAX, MVT::v4i32, Legal);
954 setOperationAction(ISD::UMAX, MVT::v8i16, Legal);
955 setOperationAction(ISD::UMAX, MVT::v4i32, Legal);
956 setOperationAction(ISD::SMIN, MVT::v16i8, Legal);
957 setOperationAction(ISD::SMIN, MVT::v4i32, Legal);
958 setOperationAction(ISD::UMIN, MVT::v8i16, Legal);
959 setOperationAction(ISD::UMIN, MVT::v4i32, Legal);
961 // FIXME: Do we need to handle scalar-to-vector here?
962 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
964 // We directly match byte blends in the backend as they match the VSELECT
966 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
968 // SSE41 brings specific instructions for doing vector sign extend even in
969 // cases where we don't have SRA.
970 for (MVT VT : MVT::integer_vector_valuetypes()) {
971 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Custom);
972 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Custom);
973 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i32, Custom);
976 // SSE41 also has vector sign/zero extending loads, PMOV[SZ]X
977 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
978 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
979 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
980 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
981 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
982 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
984 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
985 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
986 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
987 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
988 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
989 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
991 // i8 and i16 vectors are custom because the source register and source
992 // source memory operand types are not the same width. f32 vectors are
993 // custom since the immediate controlling the insert encodes additional
995 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
996 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
997 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
998 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1000 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1001 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1002 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1003 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1005 // FIXME: these should be Legal, but that's only for the case where
1006 // the index is constant. For now custom expand to deal with that.
1007 if (Subtarget->is64Bit()) {
1008 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1009 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1013 if (Subtarget->hasSSE2()) {
1014 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v2i64, Custom);
1015 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v4i32, Custom);
1016 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v8i16, Custom);
1018 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1019 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1021 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1022 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1024 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1025 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1027 // In the customized shift lowering, the legal cases in AVX2 will be
1029 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1030 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1032 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1033 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1035 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1038 if (!Subtarget->useSoftFloat() && Subtarget->hasFp256()) {
1039 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1040 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1041 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1042 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1043 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1044 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1046 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1047 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1048 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1050 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1051 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1052 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1053 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1054 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1055 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1056 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1057 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1058 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1059 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1060 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1061 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1063 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1064 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1065 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1066 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1067 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1068 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1069 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1070 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1071 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1072 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1073 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1074 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1076 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1077 // even though v8i16 is a legal type.
1078 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1079 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1080 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1082 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1083 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1084 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1086 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1087 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1089 for (MVT VT : MVT::fp_vector_valuetypes())
1090 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4f32, Legal);
1092 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1093 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1095 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1096 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1098 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1099 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1101 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1102 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1103 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1104 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1106 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1107 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1108 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1110 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1111 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1112 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1113 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1114 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1115 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1116 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1117 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1118 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1119 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1120 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1121 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1123 setOperationAction(ISD::CTPOP, MVT::v32i8, Custom);
1124 setOperationAction(ISD::CTPOP, MVT::v16i16, Custom);
1125 setOperationAction(ISD::CTPOP, MVT::v8i32, Custom);
1126 setOperationAction(ISD::CTPOP, MVT::v4i64, Custom);
1128 if (Subtarget->hasFMA() || Subtarget->hasFMA4() || Subtarget->hasAVX512()) {
1129 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1130 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1131 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1132 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1133 setOperationAction(ISD::FMA, MVT::f32, Legal);
1134 setOperationAction(ISD::FMA, MVT::f64, Legal);
1137 if (Subtarget->hasInt256()) {
1138 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1139 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1140 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1141 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1143 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1144 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1145 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1146 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1148 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1149 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1150 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1151 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1153 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1154 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1155 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1156 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1158 setOperationAction(ISD::SMAX, MVT::v32i8, Legal);
1159 setOperationAction(ISD::SMAX, MVT::v16i16, Legal);
1160 setOperationAction(ISD::SMAX, MVT::v8i32, Legal);
1161 setOperationAction(ISD::UMAX, MVT::v32i8, Legal);
1162 setOperationAction(ISD::UMAX, MVT::v16i16, Legal);
1163 setOperationAction(ISD::UMAX, MVT::v8i32, Legal);
1164 setOperationAction(ISD::SMIN, MVT::v32i8, Legal);
1165 setOperationAction(ISD::SMIN, MVT::v16i16, Legal);
1166 setOperationAction(ISD::SMIN, MVT::v8i32, Legal);
1167 setOperationAction(ISD::UMIN, MVT::v32i8, Legal);
1168 setOperationAction(ISD::UMIN, MVT::v16i16, Legal);
1169 setOperationAction(ISD::UMIN, MVT::v8i32, Legal);
1171 // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1172 // when we have a 256bit-wide blend with immediate.
1173 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom);
1175 // AVX2 also has wider vector sign/zero extending loads, VPMOV[SZ]X
1176 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1177 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1178 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1179 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1180 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1181 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1183 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1184 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1185 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1186 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1187 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1188 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1190 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1191 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1192 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1193 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1195 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1196 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1197 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1198 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1200 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1201 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1202 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1203 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1206 // In the customized shift lowering, the legal cases in AVX2 will be
1208 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1209 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1211 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1212 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1214 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1216 // Custom lower several nodes for 256-bit types.
1217 for (MVT VT : MVT::vector_valuetypes()) {
1218 if (VT.getScalarSizeInBits() >= 32) {
1219 setOperationAction(ISD::MLOAD, VT, Legal);
1220 setOperationAction(ISD::MSTORE, VT, Legal);
1222 // Extract subvector is special because the value type
1223 // (result) is 128-bit but the source is 256-bit wide.
1224 if (VT.is128BitVector()) {
1225 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1227 // Do not attempt to custom lower other non-256-bit vectors
1228 if (!VT.is256BitVector())
1231 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1232 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1233 setOperationAction(ISD::VSELECT, VT, Custom);
1234 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1235 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1236 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1237 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1238 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1241 if (Subtarget->hasInt256())
1242 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1245 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1246 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1247 MVT VT = (MVT::SimpleValueType)i;
1249 // Do not attempt to promote non-256-bit vectors
1250 if (!VT.is256BitVector())
1253 setOperationAction(ISD::AND, VT, Promote);
1254 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1255 setOperationAction(ISD::OR, VT, Promote);
1256 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1257 setOperationAction(ISD::XOR, VT, Promote);
1258 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1259 setOperationAction(ISD::LOAD, VT, Promote);
1260 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1261 setOperationAction(ISD::SELECT, VT, Promote);
1262 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1266 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512()) {
1267 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1268 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1269 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1270 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1272 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1273 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1274 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1276 for (MVT VT : MVT::fp_vector_valuetypes())
1277 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8f32, Legal);
1279 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i32, MVT::v16i8, Legal);
1280 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i32, MVT::v16i8, Legal);
1281 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i32, MVT::v16i16, Legal);
1282 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i32, MVT::v16i16, Legal);
1283 setLoadExtAction(ISD::ZEXTLOAD, MVT::v32i16, MVT::v32i8, Legal);
1284 setLoadExtAction(ISD::SEXTLOAD, MVT::v32i16, MVT::v32i8, Legal);
1285 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i8, Legal);
1286 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i8, Legal);
1287 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i16, Legal);
1288 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i16, Legal);
1289 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i32, Legal);
1290 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i32, Legal);
1292 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1293 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1294 setOperationAction(ISD::XOR, MVT::i1, Legal);
1295 setOperationAction(ISD::OR, MVT::i1, Legal);
1296 setOperationAction(ISD::AND, MVT::i1, Legal);
1297 setOperationAction(ISD::SUB, MVT::i1, Custom);
1298 setOperationAction(ISD::ADD, MVT::i1, Custom);
1299 setOperationAction(ISD::MUL, MVT::i1, Custom);
1300 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1301 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1302 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1303 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1304 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1306 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1307 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1308 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1309 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1310 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1311 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1313 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1314 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1315 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1316 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1317 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1318 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1319 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1320 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1322 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1323 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1324 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1325 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1326 if (Subtarget->is64Bit()) {
1327 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1328 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1329 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1330 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1332 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1333 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1334 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1335 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1336 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1337 setOperationAction(ISD::SINT_TO_FP, MVT::v8i1, Custom);
1338 setOperationAction(ISD::SINT_TO_FP, MVT::v16i1, Custom);
1339 setOperationAction(ISD::SINT_TO_FP, MVT::v16i8, Promote);
1340 setOperationAction(ISD::SINT_TO_FP, MVT::v16i16, Promote);
1341 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1342 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1343 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1344 setOperationAction(ISD::UINT_TO_FP, MVT::v16i8, Custom);
1345 setOperationAction(ISD::UINT_TO_FP, MVT::v16i16, Custom);
1346 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1347 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1349 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1350 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1351 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1352 if (Subtarget->hasDQI()) {
1353 setOperationAction(ISD::TRUNCATE, MVT::v2i1, Custom);
1354 setOperationAction(ISD::TRUNCATE, MVT::v4i1, Custom);
1356 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1357 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1358 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1359 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1360 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1361 setOperationAction(ISD::ANY_EXTEND, MVT::v16i32, Custom);
1362 setOperationAction(ISD::ANY_EXTEND, MVT::v8i64, Custom);
1363 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1364 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1365 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1366 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1367 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1368 if (Subtarget->hasDQI()) {
1369 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i32, Custom);
1370 setOperationAction(ISD::SIGN_EXTEND, MVT::v2i64, Custom);
1372 setOperationAction(ISD::FFLOOR, MVT::v16f32, Legal);
1373 setOperationAction(ISD::FFLOOR, MVT::v8f64, Legal);
1374 setOperationAction(ISD::FCEIL, MVT::v16f32, Legal);
1375 setOperationAction(ISD::FCEIL, MVT::v8f64, Legal);
1376 setOperationAction(ISD::FTRUNC, MVT::v16f32, Legal);
1377 setOperationAction(ISD::FTRUNC, MVT::v8f64, Legal);
1378 setOperationAction(ISD::FRINT, MVT::v16f32, Legal);
1379 setOperationAction(ISD::FRINT, MVT::v8f64, Legal);
1380 setOperationAction(ISD::FNEARBYINT, MVT::v16f32, Legal);
1381 setOperationAction(ISD::FNEARBYINT, MVT::v8f64, Legal);
1383 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1384 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1385 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1386 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1387 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1389 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1390 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1392 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1394 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1395 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1396 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1397 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1398 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1399 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1400 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1401 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1402 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1403 setOperationAction(ISD::SELECT, MVT::v16i1, Custom);
1404 setOperationAction(ISD::SELECT, MVT::v8i1, Custom);
1406 setOperationAction(ISD::SMAX, MVT::v16i32, Legal);
1407 setOperationAction(ISD::SMAX, MVT::v8i64, Legal);
1408 setOperationAction(ISD::UMAX, MVT::v16i32, Legal);
1409 setOperationAction(ISD::UMAX, MVT::v8i64, Legal);
1410 setOperationAction(ISD::SMIN, MVT::v16i32, Legal);
1411 setOperationAction(ISD::SMIN, MVT::v8i64, Legal);
1412 setOperationAction(ISD::UMIN, MVT::v16i32, Legal);
1413 setOperationAction(ISD::UMIN, MVT::v8i64, Legal);
1415 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1416 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1418 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1419 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1421 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1423 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1424 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1426 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1427 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1429 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1430 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1432 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1433 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1434 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1435 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1436 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1437 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1439 if (Subtarget->hasCDI()) {
1440 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1441 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1443 if (Subtarget->hasDQI()) {
1444 setOperationAction(ISD::MUL, MVT::v2i64, Legal);
1445 setOperationAction(ISD::MUL, MVT::v4i64, Legal);
1446 setOperationAction(ISD::MUL, MVT::v8i64, Legal);
1448 // Custom lower several nodes.
1449 for (MVT VT : MVT::vector_valuetypes()) {
1450 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1452 setOperationAction(ISD::AND, VT, Legal);
1453 setOperationAction(ISD::OR, VT, Legal);
1454 setOperationAction(ISD::XOR, VT, Legal);
1456 if (EltSize >= 32 && VT.getSizeInBits() <= 512) {
1457 setOperationAction(ISD::MGATHER, VT, Custom);
1458 setOperationAction(ISD::MSCATTER, VT, Custom);
1460 // Extract subvector is special because the value type
1461 // (result) is 256/128-bit but the source is 512-bit wide.
1462 if (VT.is128BitVector() || VT.is256BitVector()) {
1463 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1465 if (VT.getVectorElementType() == MVT::i1)
1466 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1468 // Do not attempt to custom lower other non-512-bit vectors
1469 if (!VT.is512BitVector())
1472 if (EltSize >= 32) {
1473 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1474 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1475 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1476 setOperationAction(ISD::VSELECT, VT, Legal);
1477 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1478 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1479 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1480 setOperationAction(ISD::MLOAD, VT, Legal);
1481 setOperationAction(ISD::MSTORE, VT, Legal);
1484 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1485 MVT VT = (MVT::SimpleValueType)i;
1487 // Do not attempt to promote non-512-bit vectors.
1488 if (!VT.is512BitVector())
1491 setOperationAction(ISD::SELECT, VT, Promote);
1492 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1496 if (!Subtarget->useSoftFloat() && Subtarget->hasBWI()) {
1497 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1498 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1500 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1501 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1503 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1504 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1505 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1506 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1507 setOperationAction(ISD::ADD, MVT::v32i16, Legal);
1508 setOperationAction(ISD::ADD, MVT::v64i8, Legal);
1509 setOperationAction(ISD::SUB, MVT::v32i16, Legal);
1510 setOperationAction(ISD::SUB, MVT::v64i8, Legal);
1511 setOperationAction(ISD::MUL, MVT::v32i16, Legal);
1512 setOperationAction(ISD::MULHS, MVT::v32i16, Legal);
1513 setOperationAction(ISD::MULHU, MVT::v32i16, Legal);
1514 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i1, Custom);
1515 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i1, Custom);
1516 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i1, Custom);
1517 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i1, Custom);
1518 setOperationAction(ISD::SELECT, MVT::v32i1, Custom);
1519 setOperationAction(ISD::SELECT, MVT::v64i1, Custom);
1520 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i8, Custom);
1521 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i8, Custom);
1522 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i16, Custom);
1523 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i16, Custom);
1524 setOperationAction(ISD::SIGN_EXTEND, MVT::v64i8, Custom);
1525 setOperationAction(ISD::ZERO_EXTEND, MVT::v64i8, Custom);
1526 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v32i1, Custom);
1527 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v64i1, Custom);
1528 setOperationAction(ISD::VSELECT, MVT::v32i16, Legal);
1529 setOperationAction(ISD::VSELECT, MVT::v64i8, Legal);
1530 setOperationAction(ISD::TRUNCATE, MVT::v32i1, Custom);
1531 setOperationAction(ISD::TRUNCATE, MVT::v64i1, Custom);
1533 setOperationAction(ISD::SMAX, MVT::v64i8, Legal);
1534 setOperationAction(ISD::SMAX, MVT::v32i16, Legal);
1535 setOperationAction(ISD::UMAX, MVT::v64i8, Legal);
1536 setOperationAction(ISD::UMAX, MVT::v32i16, Legal);
1537 setOperationAction(ISD::SMIN, MVT::v64i8, Legal);
1538 setOperationAction(ISD::SMIN, MVT::v32i16, Legal);
1539 setOperationAction(ISD::UMIN, MVT::v64i8, Legal);
1540 setOperationAction(ISD::UMIN, MVT::v32i16, Legal);
1542 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1543 const MVT VT = (MVT::SimpleValueType)i;
1545 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1547 // Do not attempt to promote non-512-bit vectors.
1548 if (!VT.is512BitVector())
1552 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1553 setOperationAction(ISD::VSELECT, VT, Legal);
1558 if (!Subtarget->useSoftFloat() && Subtarget->hasVLX()) {
1559 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1560 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1562 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1563 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1564 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i1, Custom);
1565 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1566 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Custom);
1567 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v4i1, Custom);
1568 setOperationAction(ISD::SELECT, MVT::v4i1, Custom);
1569 setOperationAction(ISD::SELECT, MVT::v2i1, Custom);
1570 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i1, Custom);
1571 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i1, Custom);
1573 setOperationAction(ISD::AND, MVT::v8i32, Legal);
1574 setOperationAction(ISD::OR, MVT::v8i32, Legal);
1575 setOperationAction(ISD::XOR, MVT::v8i32, Legal);
1576 setOperationAction(ISD::AND, MVT::v4i32, Legal);
1577 setOperationAction(ISD::OR, MVT::v4i32, Legal);
1578 setOperationAction(ISD::XOR, MVT::v4i32, Legal);
1579 setOperationAction(ISD::SRA, MVT::v2i64, Custom);
1580 setOperationAction(ISD::SRA, MVT::v4i64, Custom);
1582 setOperationAction(ISD::SMAX, MVT::v2i64, Legal);
1583 setOperationAction(ISD::SMAX, MVT::v4i64, Legal);
1584 setOperationAction(ISD::UMAX, MVT::v2i64, Legal);
1585 setOperationAction(ISD::UMAX, MVT::v4i64, Legal);
1586 setOperationAction(ISD::SMIN, MVT::v2i64, Legal);
1587 setOperationAction(ISD::SMIN, MVT::v4i64, Legal);
1588 setOperationAction(ISD::UMIN, MVT::v2i64, Legal);
1589 setOperationAction(ISD::UMIN, MVT::v4i64, Legal);
1592 // We want to custom lower some of our intrinsics.
1593 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1594 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1595 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1596 if (!Subtarget->is64Bit())
1597 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1599 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1600 // handle type legalization for these operations here.
1602 // FIXME: We really should do custom legalization for addition and
1603 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1604 // than generic legalization for 64-bit multiplication-with-overflow, though.
1605 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1606 // Add/Sub/Mul with overflow operations are custom lowered.
1608 setOperationAction(ISD::SADDO, VT, Custom);
1609 setOperationAction(ISD::UADDO, VT, Custom);
1610 setOperationAction(ISD::SSUBO, VT, Custom);
1611 setOperationAction(ISD::USUBO, VT, Custom);
1612 setOperationAction(ISD::SMULO, VT, Custom);
1613 setOperationAction(ISD::UMULO, VT, Custom);
1617 if (!Subtarget->is64Bit()) {
1618 // These libcalls are not available in 32-bit.
1619 setLibcallName(RTLIB::SHL_I128, nullptr);
1620 setLibcallName(RTLIB::SRL_I128, nullptr);
1621 setLibcallName(RTLIB::SRA_I128, nullptr);
1624 // Combine sin / cos into one node or libcall if possible.
1625 if (Subtarget->hasSinCos()) {
1626 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1627 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1628 if (Subtarget->isTargetDarwin()) {
1629 // For MacOSX, we don't want the normal expansion of a libcall to sincos.
1630 // We want to issue a libcall to __sincos_stret to avoid memory traffic.
1631 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1632 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1636 if (Subtarget->isTargetWin64()) {
1637 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1638 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1639 setOperationAction(ISD::SREM, MVT::i128, Custom);
1640 setOperationAction(ISD::UREM, MVT::i128, Custom);
1641 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1642 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1645 // We have target-specific dag combine patterns for the following nodes:
1646 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1647 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1648 setTargetDAGCombine(ISD::BITCAST);
1649 setTargetDAGCombine(ISD::VSELECT);
1650 setTargetDAGCombine(ISD::SELECT);
1651 setTargetDAGCombine(ISD::SHL);
1652 setTargetDAGCombine(ISD::SRA);
1653 setTargetDAGCombine(ISD::SRL);
1654 setTargetDAGCombine(ISD::OR);
1655 setTargetDAGCombine(ISD::AND);
1656 setTargetDAGCombine(ISD::ADD);
1657 setTargetDAGCombine(ISD::FADD);
1658 setTargetDAGCombine(ISD::FSUB);
1659 setTargetDAGCombine(ISD::FMA);
1660 setTargetDAGCombine(ISD::SUB);
1661 setTargetDAGCombine(ISD::LOAD);
1662 setTargetDAGCombine(ISD::MLOAD);
1663 setTargetDAGCombine(ISD::STORE);
1664 setTargetDAGCombine(ISD::MSTORE);
1665 setTargetDAGCombine(ISD::ZERO_EXTEND);
1666 setTargetDAGCombine(ISD::ANY_EXTEND);
1667 setTargetDAGCombine(ISD::SIGN_EXTEND);
1668 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1669 setTargetDAGCombine(ISD::SINT_TO_FP);
1670 setTargetDAGCombine(ISD::UINT_TO_FP);
1671 setTargetDAGCombine(ISD::SETCC);
1672 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1673 setTargetDAGCombine(ISD::BUILD_VECTOR);
1674 setTargetDAGCombine(ISD::MUL);
1675 setTargetDAGCombine(ISD::XOR);
1677 computeRegisterProperties(Subtarget->getRegisterInfo());
1679 // On Darwin, -Os means optimize for size without hurting performance,
1680 // do not reduce the limit.
1681 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1682 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1683 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1684 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1685 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1686 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1687 setPrefLoopAlignment(4); // 2^4 bytes.
1689 // Predictable cmov don't hurt on atom because it's in-order.
1690 PredictableSelectIsExpensive = !Subtarget->isAtom();
1691 EnableExtLdPromotion = true;
1692 setPrefFunctionAlignment(4); // 2^4 bytes.
1694 verifyIntrinsicTables();
1697 // This has so far only been implemented for 64-bit MachO.
1698 bool X86TargetLowering::useLoadStackGuardNode() const {
1699 return Subtarget->isTargetMachO() && Subtarget->is64Bit();
1702 TargetLoweringBase::LegalizeTypeAction
1703 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1704 if (ExperimentalVectorWideningLegalization &&
1705 VT.getVectorNumElements() != 1 &&
1706 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1707 return TypeWidenVector;
1709 return TargetLoweringBase::getPreferredVectorAction(VT);
1712 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1714 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1716 const unsigned NumElts = VT.getVectorNumElements();
1717 const EVT EltVT = VT.getVectorElementType();
1718 if (VT.is512BitVector()) {
1719 if (Subtarget->hasAVX512())
1720 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1721 EltVT == MVT::f32 || EltVT == MVT::f64)
1723 case 8: return MVT::v8i1;
1724 case 16: return MVT::v16i1;
1726 if (Subtarget->hasBWI())
1727 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1729 case 32: return MVT::v32i1;
1730 case 64: return MVT::v64i1;
1734 if (VT.is256BitVector() || VT.is128BitVector()) {
1735 if (Subtarget->hasVLX())
1736 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1737 EltVT == MVT::f32 || EltVT == MVT::f64)
1739 case 2: return MVT::v2i1;
1740 case 4: return MVT::v4i1;
1741 case 8: return MVT::v8i1;
1743 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1744 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1746 case 8: return MVT::v8i1;
1747 case 16: return MVT::v16i1;
1748 case 32: return MVT::v32i1;
1752 return VT.changeVectorElementTypeToInteger();
1755 /// Helper for getByValTypeAlignment to determine
1756 /// the desired ByVal argument alignment.
1757 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1760 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1761 if (VTy->getBitWidth() == 128)
1763 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1764 unsigned EltAlign = 0;
1765 getMaxByValAlign(ATy->getElementType(), EltAlign);
1766 if (EltAlign > MaxAlign)
1767 MaxAlign = EltAlign;
1768 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1769 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1770 unsigned EltAlign = 0;
1771 getMaxByValAlign(STy->getElementType(i), EltAlign);
1772 if (EltAlign > MaxAlign)
1773 MaxAlign = EltAlign;
1780 /// Return the desired alignment for ByVal aggregate
1781 /// function arguments in the caller parameter area. For X86, aggregates
1782 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1783 /// are at 4-byte boundaries.
1784 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1785 if (Subtarget->is64Bit()) {
1786 // Max of 8 and alignment of type.
1787 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1794 if (Subtarget->hasSSE1())
1795 getMaxByValAlign(Ty, Align);
1799 /// Returns the target specific optimal type for load
1800 /// and store operations as a result of memset, memcpy, and memmove
1801 /// lowering. If DstAlign is zero that means it's safe to destination
1802 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1803 /// means there isn't a need to check it against alignment requirement,
1804 /// probably because the source does not need to be loaded. If 'IsMemset' is
1805 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1806 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1807 /// source is constant so it does not need to be loaded.
1808 /// It returns EVT::Other if the type should be determined using generic
1809 /// target-independent logic.
1811 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1812 unsigned DstAlign, unsigned SrcAlign,
1813 bool IsMemset, bool ZeroMemset,
1815 MachineFunction &MF) const {
1816 const Function *F = MF.getFunction();
1817 if ((!IsMemset || ZeroMemset) &&
1818 !F->hasFnAttribute(Attribute::NoImplicitFloat)) {
1820 (Subtarget->isUnalignedMemAccessFast() ||
1821 ((DstAlign == 0 || DstAlign >= 16) &&
1822 (SrcAlign == 0 || SrcAlign >= 16)))) {
1824 if (Subtarget->hasInt256())
1826 if (Subtarget->hasFp256())
1829 if (Subtarget->hasSSE2())
1831 if (Subtarget->hasSSE1())
1833 } else if (!MemcpyStrSrc && Size >= 8 &&
1834 !Subtarget->is64Bit() &&
1835 Subtarget->hasSSE2()) {
1836 // Do not use f64 to lower memcpy if source is string constant. It's
1837 // better to use i32 to avoid the loads.
1841 if (Subtarget->is64Bit() && Size >= 8)
1846 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1848 return X86ScalarSSEf32;
1849 else if (VT == MVT::f64)
1850 return X86ScalarSSEf64;
1855 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1860 *Fast = Subtarget->isUnalignedMemAccessFast();
1864 /// Return the entry encoding for a jump table in the
1865 /// current function. The returned value is a member of the
1866 /// MachineJumpTableInfo::JTEntryKind enum.
1867 unsigned X86TargetLowering::getJumpTableEncoding() const {
1868 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1870 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1871 Subtarget->isPICStyleGOT())
1872 return MachineJumpTableInfo::EK_Custom32;
1874 // Otherwise, use the normal jump table encoding heuristics.
1875 return TargetLowering::getJumpTableEncoding();
1878 bool X86TargetLowering::useSoftFloat() const {
1879 return Subtarget->useSoftFloat();
1883 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1884 const MachineBasicBlock *MBB,
1885 unsigned uid,MCContext &Ctx) const{
1886 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1887 Subtarget->isPICStyleGOT());
1888 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1890 return MCSymbolRefExpr::create(MBB->getSymbol(),
1891 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1894 /// Returns relocation base for the given PIC jumptable.
1895 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1896 SelectionDAG &DAG) const {
1897 if (!Subtarget->is64Bit())
1898 // This doesn't have SDLoc associated with it, but is not really the
1899 // same as a Register.
1900 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1904 /// This returns the relocation base for the given PIC jumptable,
1905 /// the same as getPICJumpTableRelocBase, but as an MCExpr.
1906 const MCExpr *X86TargetLowering::
1907 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1908 MCContext &Ctx) const {
1909 // X86-64 uses RIP relative addressing based on the jump table label.
1910 if (Subtarget->isPICStyleRIPRel())
1911 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1913 // Otherwise, the reference is relative to the PIC base.
1914 return MCSymbolRefExpr::create(MF->getPICBaseSymbol(), Ctx);
1917 std::pair<const TargetRegisterClass *, uint8_t>
1918 X86TargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
1920 const TargetRegisterClass *RRC = nullptr;
1922 switch (VT.SimpleTy) {
1924 return TargetLowering::findRepresentativeClass(TRI, VT);
1925 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1926 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
1929 RRC = &X86::VR64RegClass;
1931 case MVT::f32: case MVT::f64:
1932 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1933 case MVT::v4f32: case MVT::v2f64:
1934 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1936 RRC = &X86::VR128RegClass;
1939 return std::make_pair(RRC, Cost);
1942 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1943 unsigned &Offset) const {
1944 if (!Subtarget->isTargetLinux())
1947 if (Subtarget->is64Bit()) {
1948 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1950 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1962 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1963 unsigned DestAS) const {
1964 assert(SrcAS != DestAS && "Expected different address spaces!");
1966 return SrcAS < 256 && DestAS < 256;
1969 //===----------------------------------------------------------------------===//
1970 // Return Value Calling Convention Implementation
1971 //===----------------------------------------------------------------------===//
1973 #include "X86GenCallingConv.inc"
1976 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1977 MachineFunction &MF, bool isVarArg,
1978 const SmallVectorImpl<ISD::OutputArg> &Outs,
1979 LLVMContext &Context) const {
1980 SmallVector<CCValAssign, 16> RVLocs;
1981 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1982 return CCInfo.CheckReturn(Outs, RetCC_X86);
1985 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1986 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
1991 X86TargetLowering::LowerReturn(SDValue Chain,
1992 CallingConv::ID CallConv, bool isVarArg,
1993 const SmallVectorImpl<ISD::OutputArg> &Outs,
1994 const SmallVectorImpl<SDValue> &OutVals,
1995 SDLoc dl, SelectionDAG &DAG) const {
1996 MachineFunction &MF = DAG.getMachineFunction();
1997 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1999 SmallVector<CCValAssign, 16> RVLocs;
2000 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
2001 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
2004 SmallVector<SDValue, 6> RetOps;
2005 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2006 // Operand #1 = Bytes To Pop
2007 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(), dl,
2010 // Copy the result values into the output registers.
2011 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2012 CCValAssign &VA = RVLocs[i];
2013 assert(VA.isRegLoc() && "Can only return in registers!");
2014 SDValue ValToCopy = OutVals[i];
2015 EVT ValVT = ValToCopy.getValueType();
2017 // Promote values to the appropriate types.
2018 if (VA.getLocInfo() == CCValAssign::SExt)
2019 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2020 else if (VA.getLocInfo() == CCValAssign::ZExt)
2021 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2022 else if (VA.getLocInfo() == CCValAssign::AExt) {
2023 if (ValVT.isVector() && ValVT.getScalarType() == MVT::i1)
2024 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2026 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2028 else if (VA.getLocInfo() == CCValAssign::BCvt)
2029 ValToCopy = DAG.getBitcast(VA.getLocVT(), ValToCopy);
2031 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2032 "Unexpected FP-extend for return value.");
2034 // If this is x86-64, and we disabled SSE, we can't return FP values,
2035 // or SSE or MMX vectors.
2036 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2037 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2038 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2039 report_fatal_error("SSE register return with SSE disabled");
2041 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2042 // llvm-gcc has never done it right and no one has noticed, so this
2043 // should be OK for now.
2044 if (ValVT == MVT::f64 &&
2045 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2046 report_fatal_error("SSE2 register return with SSE2 disabled");
2048 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2049 // the RET instruction and handled by the FP Stackifier.
2050 if (VA.getLocReg() == X86::FP0 ||
2051 VA.getLocReg() == X86::FP1) {
2052 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2053 // change the value to the FP stack register class.
2054 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2055 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2056 RetOps.push_back(ValToCopy);
2057 // Don't emit a copytoreg.
2061 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2062 // which is returned in RAX / RDX.
2063 if (Subtarget->is64Bit()) {
2064 if (ValVT == MVT::x86mmx) {
2065 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2066 ValToCopy = DAG.getBitcast(MVT::i64, ValToCopy);
2067 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2069 // If we don't have SSE2 available, convert to v4f32 so the generated
2070 // register is legal.
2071 if (!Subtarget->hasSSE2())
2072 ValToCopy = DAG.getBitcast(MVT::v4f32, ValToCopy);
2077 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2078 Flag = Chain.getValue(1);
2079 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2082 // All x86 ABIs require that for returning structs by value we copy
2083 // the sret argument into %rax/%eax (depending on ABI) for the return.
2084 // We saved the argument into a virtual register in the entry block,
2085 // so now we copy the value out and into %rax/%eax.
2087 // Checking Function.hasStructRetAttr() here is insufficient because the IR
2088 // may not have an explicit sret argument. If FuncInfo.CanLowerReturn is
2089 // false, then an sret argument may be implicitly inserted in the SelDAG. In
2090 // either case FuncInfo->setSRetReturnReg() will have been called.
2091 if (unsigned SRetReg = FuncInfo->getSRetReturnReg()) {
2092 SDValue Val = DAG.getCopyFromReg(Chain, dl, SRetReg, getPointerTy());
2095 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2096 X86::RAX : X86::EAX;
2097 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2098 Flag = Chain.getValue(1);
2100 // RAX/EAX now acts like a return value.
2101 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
2104 RetOps[0] = Chain; // Update chain.
2106 // Add the flag if we have it.
2108 RetOps.push_back(Flag);
2110 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2113 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2114 if (N->getNumValues() != 1)
2116 if (!N->hasNUsesOfValue(1, 0))
2119 SDValue TCChain = Chain;
2120 SDNode *Copy = *N->use_begin();
2121 if (Copy->getOpcode() == ISD::CopyToReg) {
2122 // If the copy has a glue operand, we conservatively assume it isn't safe to
2123 // perform a tail call.
2124 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2126 TCChain = Copy->getOperand(0);
2127 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2130 bool HasRet = false;
2131 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2133 if (UI->getOpcode() != X86ISD::RET_FLAG)
2135 // If we are returning more than one value, we can definitely
2136 // not make a tail call see PR19530
2137 if (UI->getNumOperands() > 4)
2139 if (UI->getNumOperands() == 4 &&
2140 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2153 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2154 ISD::NodeType ExtendKind) const {
2156 // TODO: Is this also valid on 32-bit?
2157 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2158 ReturnMVT = MVT::i8;
2160 ReturnMVT = MVT::i32;
2162 EVT MinVT = getRegisterType(Context, ReturnMVT);
2163 return VT.bitsLT(MinVT) ? MinVT : VT;
2166 /// Lower the result values of a call into the
2167 /// appropriate copies out of appropriate physical registers.
2170 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2171 CallingConv::ID CallConv, bool isVarArg,
2172 const SmallVectorImpl<ISD::InputArg> &Ins,
2173 SDLoc dl, SelectionDAG &DAG,
2174 SmallVectorImpl<SDValue> &InVals) const {
2176 // Assign locations to each value returned by this call.
2177 SmallVector<CCValAssign, 16> RVLocs;
2178 bool Is64Bit = Subtarget->is64Bit();
2179 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2181 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2183 // Copy all of the result registers out of their specified physreg.
2184 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2185 CCValAssign &VA = RVLocs[i];
2186 EVT CopyVT = VA.getLocVT();
2188 // If this is x86-64, and we disabled SSE, we can't return FP values
2189 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2190 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2191 report_fatal_error("SSE register return with SSE disabled");
2194 // If we prefer to use the value in xmm registers, copy it out as f80 and
2195 // use a truncate to move it from fp stack reg to xmm reg.
2196 bool RoundAfterCopy = false;
2197 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2198 isScalarFPTypeInSSEReg(VA.getValVT())) {
2200 RoundAfterCopy = (CopyVT != VA.getLocVT());
2203 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2204 CopyVT, InFlag).getValue(1);
2205 SDValue Val = Chain.getValue(0);
2208 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2209 // This truncation won't change the value.
2210 DAG.getIntPtrConstant(1, dl));
2212 if (VA.isExtInLoc() && VA.getValVT().getScalarType() == MVT::i1)
2213 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
2215 InFlag = Chain.getValue(2);
2216 InVals.push_back(Val);
2222 //===----------------------------------------------------------------------===//
2223 // C & StdCall & Fast Calling Convention implementation
2224 //===----------------------------------------------------------------------===//
2225 // StdCall calling convention seems to be standard for many Windows' API
2226 // routines and around. It differs from C calling convention just a little:
2227 // callee should clean up the stack, not caller. Symbols should be also
2228 // decorated in some fancy way :) It doesn't support any vector arguments.
2229 // For info on fast calling convention see Fast Calling Convention (tail call)
2230 // implementation LowerX86_32FastCCCallTo.
2232 /// CallIsStructReturn - Determines whether a call uses struct return
2234 enum StructReturnType {
2239 static StructReturnType
2240 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2242 return NotStructReturn;
2244 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2245 if (!Flags.isSRet())
2246 return NotStructReturn;
2247 if (Flags.isInReg())
2248 return RegStructReturn;
2249 return StackStructReturn;
2252 /// Determines whether a function uses struct return semantics.
2253 static StructReturnType
2254 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2256 return NotStructReturn;
2258 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2259 if (!Flags.isSRet())
2260 return NotStructReturn;
2261 if (Flags.isInReg())
2262 return RegStructReturn;
2263 return StackStructReturn;
2266 /// Make a copy of an aggregate at address specified by "Src" to address
2267 /// "Dst" with size and alignment information specified by the specific
2268 /// parameter attribute. The copy will be passed as a byval function parameter.
2270 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2271 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2273 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
2275 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2276 /*isVolatile*/false, /*AlwaysInline=*/true,
2277 /*isTailCall*/false,
2278 MachinePointerInfo(), MachinePointerInfo());
2281 /// Return true if the calling convention is one that
2282 /// supports tail call optimization.
2283 static bool IsTailCallConvention(CallingConv::ID CC) {
2284 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2285 CC == CallingConv::HiPE);
2288 /// \brief Return true if the calling convention is a C calling convention.
2289 static bool IsCCallConvention(CallingConv::ID CC) {
2290 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2291 CC == CallingConv::X86_64_SysV);
2294 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2296 CI->getParent()->getParent()->getFnAttribute("disable-tail-calls");
2297 if (!CI->isTailCall() || Attr.getValueAsString() == "true")
2301 CallingConv::ID CalleeCC = CS.getCallingConv();
2302 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2308 /// Return true if the function is being made into
2309 /// a tailcall target by changing its ABI.
2310 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2311 bool GuaranteedTailCallOpt) {
2312 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2316 X86TargetLowering::LowerMemArgument(SDValue Chain,
2317 CallingConv::ID CallConv,
2318 const SmallVectorImpl<ISD::InputArg> &Ins,
2319 SDLoc dl, SelectionDAG &DAG,
2320 const CCValAssign &VA,
2321 MachineFrameInfo *MFI,
2323 // Create the nodes corresponding to a load from this parameter slot.
2324 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2325 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2326 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2327 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2330 // If value is passed by pointer we have address passed instead of the value
2332 bool ExtendedInMem = VA.isExtInLoc() &&
2333 VA.getValVT().getScalarType() == MVT::i1;
2335 if (VA.getLocInfo() == CCValAssign::Indirect || ExtendedInMem)
2336 ValVT = VA.getLocVT();
2338 ValVT = VA.getValVT();
2340 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2341 // changed with more analysis.
2342 // In case of tail call optimization mark all arguments mutable. Since they
2343 // could be overwritten by lowering of arguments in case of a tail call.
2344 if (Flags.isByVal()) {
2345 unsigned Bytes = Flags.getByValSize();
2346 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2347 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2348 return DAG.getFrameIndex(FI, getPointerTy());
2350 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2351 VA.getLocMemOffset(), isImmutable);
2352 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2353 SDValue Val = DAG.getLoad(ValVT, dl, Chain, FIN,
2354 MachinePointerInfo::getFixedStack(FI),
2355 false, false, false, 0);
2356 return ExtendedInMem ?
2357 DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val) : Val;
2361 // FIXME: Get this from tablegen.
2362 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2363 const X86Subtarget *Subtarget) {
2364 assert(Subtarget->is64Bit());
2366 if (Subtarget->isCallingConvWin64(CallConv)) {
2367 static const MCPhysReg GPR64ArgRegsWin64[] = {
2368 X86::RCX, X86::RDX, X86::R8, X86::R9
2370 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2373 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2374 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2376 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2379 // FIXME: Get this from tablegen.
2380 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2381 CallingConv::ID CallConv,
2382 const X86Subtarget *Subtarget) {
2383 assert(Subtarget->is64Bit());
2384 if (Subtarget->isCallingConvWin64(CallConv)) {
2385 // The XMM registers which might contain var arg parameters are shadowed
2386 // in their paired GPR. So we only need to save the GPR to their home
2388 // TODO: __vectorcall will change this.
2392 const Function *Fn = MF.getFunction();
2393 bool NoImplicitFloatOps = Fn->hasFnAttribute(Attribute::NoImplicitFloat);
2394 bool isSoftFloat = Subtarget->useSoftFloat();
2395 assert(!(isSoftFloat && NoImplicitFloatOps) &&
2396 "SSE register cannot be used when SSE is disabled!");
2397 if (isSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1())
2398 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2402 static const MCPhysReg XMMArgRegs64Bit[] = {
2403 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2404 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2406 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2410 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2411 CallingConv::ID CallConv,
2413 const SmallVectorImpl<ISD::InputArg> &Ins,
2416 SmallVectorImpl<SDValue> &InVals)
2418 MachineFunction &MF = DAG.getMachineFunction();
2419 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2420 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
2422 const Function* Fn = MF.getFunction();
2423 if (Fn->hasExternalLinkage() &&
2424 Subtarget->isTargetCygMing() &&
2425 Fn->getName() == "main")
2426 FuncInfo->setForceFramePointer(true);
2428 MachineFrameInfo *MFI = MF.getFrameInfo();
2429 bool Is64Bit = Subtarget->is64Bit();
2430 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2432 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2433 "Var args not supported with calling convention fastcc, ghc or hipe");
2435 // Assign locations to all of the incoming arguments.
2436 SmallVector<CCValAssign, 16> ArgLocs;
2437 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2439 // Allocate shadow area for Win64
2441 CCInfo.AllocateStack(32, 8);
2443 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2445 unsigned LastVal = ~0U;
2447 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2448 CCValAssign &VA = ArgLocs[i];
2449 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2451 assert(VA.getValNo() != LastVal &&
2452 "Don't support value assigned to multiple locs yet");
2454 LastVal = VA.getValNo();
2456 if (VA.isRegLoc()) {
2457 EVT RegVT = VA.getLocVT();
2458 const TargetRegisterClass *RC;
2459 if (RegVT == MVT::i32)
2460 RC = &X86::GR32RegClass;
2461 else if (Is64Bit && RegVT == MVT::i64)
2462 RC = &X86::GR64RegClass;
2463 else if (RegVT == MVT::f32)
2464 RC = &X86::FR32RegClass;
2465 else if (RegVT == MVT::f64)
2466 RC = &X86::FR64RegClass;
2467 else if (RegVT.is512BitVector())
2468 RC = &X86::VR512RegClass;
2469 else if (RegVT.is256BitVector())
2470 RC = &X86::VR256RegClass;
2471 else if (RegVT.is128BitVector())
2472 RC = &X86::VR128RegClass;
2473 else if (RegVT == MVT::x86mmx)
2474 RC = &X86::VR64RegClass;
2475 else if (RegVT == MVT::i1)
2476 RC = &X86::VK1RegClass;
2477 else if (RegVT == MVT::v8i1)
2478 RC = &X86::VK8RegClass;
2479 else if (RegVT == MVT::v16i1)
2480 RC = &X86::VK16RegClass;
2481 else if (RegVT == MVT::v32i1)
2482 RC = &X86::VK32RegClass;
2483 else if (RegVT == MVT::v64i1)
2484 RC = &X86::VK64RegClass;
2486 llvm_unreachable("Unknown argument type!");
2488 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2489 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2491 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2492 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2494 if (VA.getLocInfo() == CCValAssign::SExt)
2495 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2496 DAG.getValueType(VA.getValVT()));
2497 else if (VA.getLocInfo() == CCValAssign::ZExt)
2498 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2499 DAG.getValueType(VA.getValVT()));
2500 else if (VA.getLocInfo() == CCValAssign::BCvt)
2501 ArgValue = DAG.getBitcast(VA.getValVT(), ArgValue);
2503 if (VA.isExtInLoc()) {
2504 // Handle MMX values passed in XMM regs.
2505 if (RegVT.isVector() && VA.getValVT().getScalarType() != MVT::i1)
2506 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2508 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2511 assert(VA.isMemLoc());
2512 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2515 // If value is passed via pointer - do a load.
2516 if (VA.getLocInfo() == CCValAssign::Indirect)
2517 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2518 MachinePointerInfo(), false, false, false, 0);
2520 InVals.push_back(ArgValue);
2523 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2524 // All x86 ABIs require that for returning structs by value we copy the
2525 // sret argument into %rax/%eax (depending on ABI) for the return. Save
2526 // the argument into a virtual register so that we can access it from the
2528 if (Ins[i].Flags.isSRet()) {
2529 unsigned Reg = FuncInfo->getSRetReturnReg();
2531 MVT PtrTy = getPointerTy();
2532 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2533 FuncInfo->setSRetReturnReg(Reg);
2535 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2536 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2541 unsigned StackSize = CCInfo.getNextStackOffset();
2542 // Align stack specially for tail calls.
2543 if (FuncIsMadeTailCallSafe(CallConv,
2544 MF.getTarget().Options.GuaranteedTailCallOpt))
2545 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2547 // If the function takes variable number of arguments, make a frame index for
2548 // the start of the first vararg value... for expansion of llvm.va_start. We
2549 // can skip this if there are no va_start calls.
2550 if (MFI->hasVAStart() &&
2551 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2552 CallConv != CallingConv::X86_ThisCall))) {
2553 FuncInfo->setVarArgsFrameIndex(
2554 MFI->CreateFixedObject(1, StackSize, true));
2557 MachineModuleInfo &MMI = MF.getMMI();
2558 const Function *WinEHParent = nullptr;
2559 if (IsWin64 && MMI.hasWinEHFuncInfo(Fn))
2560 WinEHParent = MMI.getWinEHParent(Fn);
2561 bool IsWinEHOutlined = WinEHParent && WinEHParent != Fn;
2562 bool IsWinEHParent = WinEHParent && WinEHParent == Fn;
2564 // Figure out if XMM registers are in use.
2565 assert(!(Subtarget->useSoftFloat() &&
2566 Fn->hasFnAttribute(Attribute::NoImplicitFloat)) &&
2567 "SSE register cannot be used when SSE is disabled!");
2569 // 64-bit calling conventions support varargs and register parameters, so we
2570 // have to do extra work to spill them in the prologue.
2571 if (Is64Bit && isVarArg && MFI->hasVAStart()) {
2572 // Find the first unallocated argument registers.
2573 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2574 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2575 unsigned NumIntRegs = CCInfo.getFirstUnallocated(ArgGPRs);
2576 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(ArgXMMs);
2577 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2578 "SSE register cannot be used when SSE is disabled!");
2580 // Gather all the live in physical registers.
2581 SmallVector<SDValue, 6> LiveGPRs;
2582 SmallVector<SDValue, 8> LiveXMMRegs;
2584 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2585 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2587 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2589 if (!ArgXMMs.empty()) {
2590 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2591 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2592 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2593 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2594 LiveXMMRegs.push_back(
2595 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2600 // Get to the caller-allocated home save location. Add 8 to account
2601 // for the return address.
2602 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2603 FuncInfo->setRegSaveFrameIndex(
2604 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2605 // Fixup to set vararg frame on shadow area (4 x i64).
2607 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2609 // For X86-64, if there are vararg parameters that are passed via
2610 // registers, then we must store them to their spots on the stack so
2611 // they may be loaded by deferencing the result of va_next.
2612 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2613 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2614 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2615 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2618 // Store the integer parameter registers.
2619 SmallVector<SDValue, 8> MemOps;
2620 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2622 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2623 for (SDValue Val : LiveGPRs) {
2624 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2625 DAG.getIntPtrConstant(Offset, dl));
2627 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2628 MachinePointerInfo::getFixedStack(
2629 FuncInfo->getRegSaveFrameIndex(), Offset),
2631 MemOps.push_back(Store);
2635 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2636 // Now store the XMM (fp + vector) parameter registers.
2637 SmallVector<SDValue, 12> SaveXMMOps;
2638 SaveXMMOps.push_back(Chain);
2639 SaveXMMOps.push_back(ALVal);
2640 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2641 FuncInfo->getRegSaveFrameIndex(), dl));
2642 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2643 FuncInfo->getVarArgsFPOffset(), dl));
2644 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2646 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2647 MVT::Other, SaveXMMOps));
2650 if (!MemOps.empty())
2651 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2652 } else if (IsWinEHOutlined) {
2653 // Get to the caller-allocated home save location. Add 8 to account
2654 // for the return address.
2655 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2656 FuncInfo->setRegSaveFrameIndex(MFI->CreateFixedObject(
2657 /*Size=*/1, /*SPOffset=*/HomeOffset + 8, /*Immutable=*/false));
2659 MMI.getWinEHFuncInfo(Fn)
2660 .CatchHandlerParentFrameObjIdx[const_cast<Function *>(Fn)] =
2661 FuncInfo->getRegSaveFrameIndex();
2663 // Store the second integer parameter (rdx) into rsp+16 relative to the
2664 // stack pointer at the entry of the function.
2666 DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), getPointerTy());
2667 unsigned GPR = MF.addLiveIn(X86::RDX, &X86::GR64RegClass);
2668 SDValue Val = DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64);
2669 Chain = DAG.getStore(
2670 Val.getValue(1), dl, Val, RSFIN,
2671 MachinePointerInfo::getFixedStack(FuncInfo->getRegSaveFrameIndex()),
2672 /*isVolatile=*/true, /*isNonTemporal=*/false, /*Alignment=*/0);
2675 if (isVarArg && MFI->hasMustTailInVarArgFunc()) {
2676 // Find the largest legal vector type.
2677 MVT VecVT = MVT::Other;
2678 // FIXME: Only some x86_32 calling conventions support AVX512.
2679 if (Subtarget->hasAVX512() &&
2680 (Is64Bit || (CallConv == CallingConv::X86_VectorCall ||
2681 CallConv == CallingConv::Intel_OCL_BI)))
2682 VecVT = MVT::v16f32;
2683 else if (Subtarget->hasAVX())
2685 else if (Subtarget->hasSSE2())
2688 // We forward some GPRs and some vector types.
2689 SmallVector<MVT, 2> RegParmTypes;
2690 MVT IntVT = Is64Bit ? MVT::i64 : MVT::i32;
2691 RegParmTypes.push_back(IntVT);
2692 if (VecVT != MVT::Other)
2693 RegParmTypes.push_back(VecVT);
2695 // Compute the set of forwarded registers. The rest are scratch.
2696 SmallVectorImpl<ForwardedRegister> &Forwards =
2697 FuncInfo->getForwardedMustTailRegParms();
2698 CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes, CC_X86);
2700 // Conservatively forward AL on x86_64, since it might be used for varargs.
2701 if (Is64Bit && !CCInfo.isAllocated(X86::AL)) {
2702 unsigned ALVReg = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2703 Forwards.push_back(ForwardedRegister(ALVReg, X86::AL, MVT::i8));
2706 // Copy all forwards from physical to virtual registers.
2707 for (ForwardedRegister &F : Forwards) {
2708 // FIXME: Can we use a less constrained schedule?
2709 SDValue RegVal = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2710 F.VReg = MF.getRegInfo().createVirtualRegister(getRegClassFor(F.VT));
2711 Chain = DAG.getCopyToReg(Chain, dl, F.VReg, RegVal);
2715 // Some CCs need callee pop.
2716 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2717 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2718 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2720 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2721 // If this is an sret function, the return should pop the hidden pointer.
2722 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2723 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2724 argsAreStructReturn(Ins) == StackStructReturn)
2725 FuncInfo->setBytesToPopOnReturn(4);
2729 // RegSaveFrameIndex is X86-64 only.
2730 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2731 if (CallConv == CallingConv::X86_FastCall ||
2732 CallConv == CallingConv::X86_ThisCall)
2733 // fastcc functions can't have varargs.
2734 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2737 FuncInfo->setArgumentStackSize(StackSize);
2739 if (IsWinEHParent) {
2740 int UnwindHelpFI = MFI->CreateStackObject(8, 8, /*isSS=*/false);
2741 SDValue StackSlot = DAG.getFrameIndex(UnwindHelpFI, MVT::i64);
2742 MMI.getWinEHFuncInfo(MF.getFunction()).UnwindHelpFrameIdx = UnwindHelpFI;
2743 SDValue Neg2 = DAG.getConstant(-2, dl, MVT::i64);
2744 Chain = DAG.getStore(Chain, dl, Neg2, StackSlot,
2745 MachinePointerInfo::getFixedStack(UnwindHelpFI),
2746 /*isVolatile=*/true,
2747 /*isNonTemporal=*/false, /*Alignment=*/0);
2754 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2755 SDValue StackPtr, SDValue Arg,
2756 SDLoc dl, SelectionDAG &DAG,
2757 const CCValAssign &VA,
2758 ISD::ArgFlagsTy Flags) const {
2759 unsigned LocMemOffset = VA.getLocMemOffset();
2760 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
2761 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2762 if (Flags.isByVal())
2763 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2765 return DAG.getStore(Chain, dl, Arg, PtrOff,
2766 MachinePointerInfo::getStack(LocMemOffset),
2770 /// Emit a load of return address if tail call
2771 /// optimization is performed and it is required.
2773 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2774 SDValue &OutRetAddr, SDValue Chain,
2775 bool IsTailCall, bool Is64Bit,
2776 int FPDiff, SDLoc dl) const {
2777 // Adjust the Return address stack slot.
2778 EVT VT = getPointerTy();
2779 OutRetAddr = getReturnAddressFrameIndex(DAG);
2781 // Load the "old" Return address.
2782 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2783 false, false, false, 0);
2784 return SDValue(OutRetAddr.getNode(), 1);
2787 /// Emit a store of the return address if tail call
2788 /// optimization is performed and it is required (FPDiff!=0).
2789 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2790 SDValue Chain, SDValue RetAddrFrIdx,
2791 EVT PtrVT, unsigned SlotSize,
2792 int FPDiff, SDLoc dl) {
2793 // Store the return address to the appropriate stack slot.
2794 if (!FPDiff) return Chain;
2795 // Calculate the new stack slot for the return address.
2796 int NewReturnAddrFI =
2797 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2799 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2800 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2801 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2807 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2808 SmallVectorImpl<SDValue> &InVals) const {
2809 SelectionDAG &DAG = CLI.DAG;
2811 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2812 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2813 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2814 SDValue Chain = CLI.Chain;
2815 SDValue Callee = CLI.Callee;
2816 CallingConv::ID CallConv = CLI.CallConv;
2817 bool &isTailCall = CLI.IsTailCall;
2818 bool isVarArg = CLI.IsVarArg;
2820 MachineFunction &MF = DAG.getMachineFunction();
2821 bool Is64Bit = Subtarget->is64Bit();
2822 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2823 StructReturnType SR = callIsStructReturn(Outs);
2824 bool IsSibcall = false;
2825 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2826 auto Attr = MF.getFunction()->getFnAttribute("disable-tail-calls");
2828 if (Attr.getValueAsString() == "true")
2831 if (Subtarget->isPICStyleGOT() &&
2832 !MF.getTarget().Options.GuaranteedTailCallOpt) {
2833 // If we are using a GOT, disable tail calls to external symbols with
2834 // default visibility. Tail calling such a symbol requires using a GOT
2835 // relocation, which forces early binding of the symbol. This breaks code
2836 // that require lazy function symbol resolution. Using musttail or
2837 // GuaranteedTailCallOpt will override this.
2838 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2839 if (!G || (!G->getGlobal()->hasLocalLinkage() &&
2840 G->getGlobal()->hasDefaultVisibility()))
2844 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2846 // Force this to be a tail call. The verifier rules are enough to ensure
2847 // that we can lower this successfully without moving the return address
2850 } else if (isTailCall) {
2851 // Check if it's really possible to do a tail call.
2852 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2853 isVarArg, SR != NotStructReturn,
2854 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2855 Outs, OutVals, Ins, DAG);
2857 // Sibcalls are automatically detected tailcalls which do not require
2859 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2866 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2867 "Var args not supported with calling convention fastcc, ghc or hipe");
2869 // Analyze operands of the call, assigning locations to each operand.
2870 SmallVector<CCValAssign, 16> ArgLocs;
2871 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2873 // Allocate shadow area for Win64
2875 CCInfo.AllocateStack(32, 8);
2877 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2879 // Get a count of how many bytes are to be pushed on the stack.
2880 unsigned NumBytes = CCInfo.getNextStackOffset();
2882 // This is a sibcall. The memory operands are available in caller's
2883 // own caller's stack.
2885 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2886 IsTailCallConvention(CallConv))
2887 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2890 if (isTailCall && !IsSibcall && !IsMustTail) {
2891 // Lower arguments at fp - stackoffset + fpdiff.
2892 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2894 FPDiff = NumBytesCallerPushed - NumBytes;
2896 // Set the delta of movement of the returnaddr stackslot.
2897 // But only set if delta is greater than previous delta.
2898 if (FPDiff < X86Info->getTCReturnAddrDelta())
2899 X86Info->setTCReturnAddrDelta(FPDiff);
2902 unsigned NumBytesToPush = NumBytes;
2903 unsigned NumBytesToPop = NumBytes;
2905 // If we have an inalloca argument, all stack space has already been allocated
2906 // for us and be right at the top of the stack. We don't support multiple
2907 // arguments passed in memory when using inalloca.
2908 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2910 if (!ArgLocs.back().isMemLoc())
2911 report_fatal_error("cannot use inalloca attribute on a register "
2913 if (ArgLocs.back().getLocMemOffset() != 0)
2914 report_fatal_error("any parameter with the inalloca attribute must be "
2915 "the only memory argument");
2919 Chain = DAG.getCALLSEQ_START(
2920 Chain, DAG.getIntPtrConstant(NumBytesToPush, dl, true), dl);
2922 SDValue RetAddrFrIdx;
2923 // Load return address for tail calls.
2924 if (isTailCall && FPDiff)
2925 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2926 Is64Bit, FPDiff, dl);
2928 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2929 SmallVector<SDValue, 8> MemOpChains;
2932 // Walk the register/memloc assignments, inserting copies/loads. In the case
2933 // of tail call optimization arguments are handle later.
2934 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
2935 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2936 // Skip inalloca arguments, they have already been written.
2937 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2938 if (Flags.isInAlloca())
2941 CCValAssign &VA = ArgLocs[i];
2942 EVT RegVT = VA.getLocVT();
2943 SDValue Arg = OutVals[i];
2944 bool isByVal = Flags.isByVal();
2946 // Promote the value if needed.
2947 switch (VA.getLocInfo()) {
2948 default: llvm_unreachable("Unknown loc info!");
2949 case CCValAssign::Full: break;
2950 case CCValAssign::SExt:
2951 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2953 case CCValAssign::ZExt:
2954 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2956 case CCValAssign::AExt:
2957 if (Arg.getValueType().isVector() &&
2958 Arg.getValueType().getScalarType() == MVT::i1)
2959 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2960 else if (RegVT.is128BitVector()) {
2961 // Special case: passing MMX values in XMM registers.
2962 Arg = DAG.getBitcast(MVT::i64, Arg);
2963 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2964 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2966 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2968 case CCValAssign::BCvt:
2969 Arg = DAG.getBitcast(RegVT, Arg);
2971 case CCValAssign::Indirect: {
2972 // Store the argument.
2973 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2974 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2975 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2976 MachinePointerInfo::getFixedStack(FI),
2983 if (VA.isRegLoc()) {
2984 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2985 if (isVarArg && IsWin64) {
2986 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2987 // shadow reg if callee is a varargs function.
2988 unsigned ShadowReg = 0;
2989 switch (VA.getLocReg()) {
2990 case X86::XMM0: ShadowReg = X86::RCX; break;
2991 case X86::XMM1: ShadowReg = X86::RDX; break;
2992 case X86::XMM2: ShadowReg = X86::R8; break;
2993 case X86::XMM3: ShadowReg = X86::R9; break;
2996 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2998 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2999 assert(VA.isMemLoc());
3000 if (!StackPtr.getNode())
3001 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
3003 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
3004 dl, DAG, VA, Flags));
3008 if (!MemOpChains.empty())
3009 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
3011 if (Subtarget->isPICStyleGOT()) {
3012 // ELF / PIC requires GOT in the EBX register before function calls via PLT
3015 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
3016 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
3018 // If we are tail calling and generating PIC/GOT style code load the
3019 // address of the callee into ECX. The value in ecx is used as target of
3020 // the tail jump. This is done to circumvent the ebx/callee-saved problem
3021 // for tail calls on PIC/GOT architectures. Normally we would just put the
3022 // address of GOT into ebx and then call target@PLT. But for tail calls
3023 // ebx would be restored (since ebx is callee saved) before jumping to the
3026 // Note: The actual moving to ECX is done further down.
3027 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
3028 if (G && !G->getGlobal()->hasLocalLinkage() &&
3029 G->getGlobal()->hasDefaultVisibility())
3030 Callee = LowerGlobalAddress(Callee, DAG);
3031 else if (isa<ExternalSymbolSDNode>(Callee))
3032 Callee = LowerExternalSymbol(Callee, DAG);
3036 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
3037 // From AMD64 ABI document:
3038 // For calls that may call functions that use varargs or stdargs
3039 // (prototype-less calls or calls to functions containing ellipsis (...) in
3040 // the declaration) %al is used as hidden argument to specify the number
3041 // of SSE registers used. The contents of %al do not need to match exactly
3042 // the number of registers, but must be an ubound on the number of SSE
3043 // registers used and is in the range 0 - 8 inclusive.
3045 // Count the number of XMM registers allocated.
3046 static const MCPhysReg XMMArgRegs[] = {
3047 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
3048 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
3050 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs);
3051 assert((Subtarget->hasSSE1() || !NumXMMRegs)
3052 && "SSE registers cannot be used when SSE is disabled");
3054 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
3055 DAG.getConstant(NumXMMRegs, dl,
3059 if (isVarArg && IsMustTail) {
3060 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
3061 for (const auto &F : Forwards) {
3062 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
3063 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
3067 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
3068 // don't need this because the eligibility check rejects calls that require
3069 // shuffling arguments passed in memory.
3070 if (!IsSibcall && isTailCall) {
3071 // Force all the incoming stack arguments to be loaded from the stack
3072 // before any new outgoing arguments are stored to the stack, because the
3073 // outgoing stack slots may alias the incoming argument stack slots, and
3074 // the alias isn't otherwise explicit. This is slightly more conservative
3075 // than necessary, because it means that each store effectively depends
3076 // on every argument instead of just those arguments it would clobber.
3077 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
3079 SmallVector<SDValue, 8> MemOpChains2;
3082 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3083 CCValAssign &VA = ArgLocs[i];
3086 assert(VA.isMemLoc());
3087 SDValue Arg = OutVals[i];
3088 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3089 // Skip inalloca arguments. They don't require any work.
3090 if (Flags.isInAlloca())
3092 // Create frame index.
3093 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3094 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3095 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3096 FIN = DAG.getFrameIndex(FI, getPointerTy());
3098 if (Flags.isByVal()) {
3099 // Copy relative to framepointer.
3100 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset(), dl);
3101 if (!StackPtr.getNode())
3102 StackPtr = DAG.getCopyFromReg(Chain, dl,
3103 RegInfo->getStackRegister(),
3105 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
3107 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3111 // Store relative to framepointer.
3112 MemOpChains2.push_back(
3113 DAG.getStore(ArgChain, dl, Arg, FIN,
3114 MachinePointerInfo::getFixedStack(FI),
3119 if (!MemOpChains2.empty())
3120 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3122 // Store the return address to the appropriate stack slot.
3123 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3124 getPointerTy(), RegInfo->getSlotSize(),
3128 // Build a sequence of copy-to-reg nodes chained together with token chain
3129 // and flag operands which copy the outgoing args into registers.
3131 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3132 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3133 RegsToPass[i].second, InFlag);
3134 InFlag = Chain.getValue(1);
3137 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3138 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3139 // In the 64-bit large code model, we have to make all calls
3140 // through a register, since the call instruction's 32-bit
3141 // pc-relative offset may not be large enough to hold the whole
3143 } else if (Callee->getOpcode() == ISD::GlobalAddress) {
3144 // If the callee is a GlobalAddress node (quite common, every direct call
3145 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3147 GlobalAddressSDNode* G = cast<GlobalAddressSDNode>(Callee);
3149 // We should use extra load for direct calls to dllimported functions in
3151 const GlobalValue *GV = G->getGlobal();
3152 if (!GV->hasDLLImportStorageClass()) {
3153 unsigned char OpFlags = 0;
3154 bool ExtraLoad = false;
3155 unsigned WrapperKind = ISD::DELETED_NODE;
3157 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3158 // external symbols most go through the PLT in PIC mode. If the symbol
3159 // has hidden or protected visibility, or if it is static or local, then
3160 // we don't need to use the PLT - we can directly call it.
3161 if (Subtarget->isTargetELF() &&
3162 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3163 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3164 OpFlags = X86II::MO_PLT;
3165 } else if (Subtarget->isPICStyleStubAny() &&
3166 !GV->isStrongDefinitionForLinker() &&
3167 (!Subtarget->getTargetTriple().isMacOSX() ||
3168 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3169 // PC-relative references to external symbols should go through $stub,
3170 // unless we're building with the leopard linker or later, which
3171 // automatically synthesizes these stubs.
3172 OpFlags = X86II::MO_DARWIN_STUB;
3173 } else if (Subtarget->isPICStyleRIPRel() && isa<Function>(GV) &&
3174 cast<Function>(GV)->hasFnAttribute(Attribute::NonLazyBind)) {
3175 // If the function is marked as non-lazy, generate an indirect call
3176 // which loads from the GOT directly. This avoids runtime overhead
3177 // at the cost of eager binding (and one extra byte of encoding).
3178 OpFlags = X86II::MO_GOTPCREL;
3179 WrapperKind = X86ISD::WrapperRIP;
3183 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
3184 G->getOffset(), OpFlags);
3186 // Add a wrapper if needed.
3187 if (WrapperKind != ISD::DELETED_NODE)
3188 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
3189 // Add extra indirection if needed.
3191 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
3192 MachinePointerInfo::getGOT(),
3193 false, false, false, 0);
3195 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3196 unsigned char OpFlags = 0;
3198 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3199 // external symbols should go through the PLT.
3200 if (Subtarget->isTargetELF() &&
3201 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3202 OpFlags = X86II::MO_PLT;
3203 } else if (Subtarget->isPICStyleStubAny() &&
3204 (!Subtarget->getTargetTriple().isMacOSX() ||
3205 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3206 // PC-relative references to external symbols should go through $stub,
3207 // unless we're building with the leopard linker or later, which
3208 // automatically synthesizes these stubs.
3209 OpFlags = X86II::MO_DARWIN_STUB;
3212 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
3214 } else if (Subtarget->isTarget64BitILP32() &&
3215 Callee->getValueType(0) == MVT::i32) {
3216 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3217 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3220 // Returns a chain & a flag for retval copy to use.
3221 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3222 SmallVector<SDValue, 8> Ops;
3224 if (!IsSibcall && isTailCall) {
3225 Chain = DAG.getCALLSEQ_END(Chain,
3226 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3227 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
3228 InFlag = Chain.getValue(1);
3231 Ops.push_back(Chain);
3232 Ops.push_back(Callee);
3235 Ops.push_back(DAG.getConstant(FPDiff, dl, MVT::i32));
3237 // Add argument registers to the end of the list so that they are known live
3239 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3240 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3241 RegsToPass[i].second.getValueType()));
3243 // Add a register mask operand representing the call-preserved registers.
3244 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
3245 const uint32_t *Mask = TRI->getCallPreservedMask(MF, CallConv);
3246 assert(Mask && "Missing call preserved mask for calling convention");
3247 Ops.push_back(DAG.getRegisterMask(Mask));
3249 if (InFlag.getNode())
3250 Ops.push_back(InFlag);
3254 //// If this is the first return lowered for this function, add the regs
3255 //// to the liveout set for the function.
3256 // This isn't right, although it's probably harmless on x86; liveouts
3257 // should be computed from returns not tail calls. Consider a void
3258 // function making a tail call to a function returning int.
3259 MF.getFrameInfo()->setHasTailCall();
3260 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3263 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3264 InFlag = Chain.getValue(1);
3266 // Create the CALLSEQ_END node.
3267 unsigned NumBytesForCalleeToPop;
3268 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3269 DAG.getTarget().Options.GuaranteedTailCallOpt))
3270 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3271 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3272 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3273 SR == StackStructReturn)
3274 // If this is a call to a struct-return function, the callee
3275 // pops the hidden struct pointer, so we have to push it back.
3276 // This is common for Darwin/X86, Linux & Mingw32 targets.
3277 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3278 NumBytesForCalleeToPop = 4;
3280 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3282 // Returns a flag for retval copy to use.
3284 Chain = DAG.getCALLSEQ_END(Chain,
3285 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3286 DAG.getIntPtrConstant(NumBytesForCalleeToPop, dl,
3289 InFlag = Chain.getValue(1);
3292 // Handle result values, copying them out of physregs into vregs that we
3294 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3295 Ins, dl, DAG, InVals);
3298 //===----------------------------------------------------------------------===//
3299 // Fast Calling Convention (tail call) implementation
3300 //===----------------------------------------------------------------------===//
3302 // Like std call, callee cleans arguments, convention except that ECX is
3303 // reserved for storing the tail called function address. Only 2 registers are
3304 // free for argument passing (inreg). Tail call optimization is performed
3306 // * tailcallopt is enabled
3307 // * caller/callee are fastcc
3308 // On X86_64 architecture with GOT-style position independent code only local
3309 // (within module) calls are supported at the moment.
3310 // To keep the stack aligned according to platform abi the function
3311 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3312 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3313 // If a tail called function callee has more arguments than the caller the
3314 // caller needs to make sure that there is room to move the RETADDR to. This is
3315 // achieved by reserving an area the size of the argument delta right after the
3316 // original RETADDR, but before the saved framepointer or the spilled registers
3317 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3329 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3330 /// for a 16 byte align requirement.
3332 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3333 SelectionDAG& DAG) const {
3334 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3335 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
3336 unsigned StackAlignment = TFI.getStackAlignment();
3337 uint64_t AlignMask = StackAlignment - 1;
3338 int64_t Offset = StackSize;
3339 unsigned SlotSize = RegInfo->getSlotSize();
3340 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3341 // Number smaller than 12 so just add the difference.
3342 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3344 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3345 Offset = ((~AlignMask) & Offset) + StackAlignment +
3346 (StackAlignment-SlotSize);
3351 /// MatchingStackOffset - Return true if the given stack call argument is
3352 /// already available in the same position (relatively) of the caller's
3353 /// incoming argument stack.
3355 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3356 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3357 const X86InstrInfo *TII) {
3358 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3360 if (Arg.getOpcode() == ISD::CopyFromReg) {
3361 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3362 if (!TargetRegisterInfo::isVirtualRegister(VR))
3364 MachineInstr *Def = MRI->getVRegDef(VR);
3367 if (!Flags.isByVal()) {
3368 if (!TII->isLoadFromStackSlot(Def, FI))
3371 unsigned Opcode = Def->getOpcode();
3372 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r ||
3373 Opcode == X86::LEA64_32r) &&
3374 Def->getOperand(1).isFI()) {
3375 FI = Def->getOperand(1).getIndex();
3376 Bytes = Flags.getByValSize();
3380 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3381 if (Flags.isByVal())
3382 // ByVal argument is passed in as a pointer but it's now being
3383 // dereferenced. e.g.
3384 // define @foo(%struct.X* %A) {
3385 // tail call @bar(%struct.X* byval %A)
3388 SDValue Ptr = Ld->getBasePtr();
3389 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3392 FI = FINode->getIndex();
3393 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3394 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3395 FI = FINode->getIndex();
3396 Bytes = Flags.getByValSize();
3400 assert(FI != INT_MAX);
3401 if (!MFI->isFixedObjectIndex(FI))
3403 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3406 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3407 /// for tail call optimization. Targets which want to do tail call
3408 /// optimization should implement this function.
3410 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3411 CallingConv::ID CalleeCC,
3413 bool isCalleeStructRet,
3414 bool isCallerStructRet,
3416 const SmallVectorImpl<ISD::OutputArg> &Outs,
3417 const SmallVectorImpl<SDValue> &OutVals,
3418 const SmallVectorImpl<ISD::InputArg> &Ins,
3419 SelectionDAG &DAG) const {
3420 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3423 // If -tailcallopt is specified, make fastcc functions tail-callable.
3424 const MachineFunction &MF = DAG.getMachineFunction();
3425 const Function *CallerF = MF.getFunction();
3427 // If the function return type is x86_fp80 and the callee return type is not,
3428 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3429 // perform a tailcall optimization here.
3430 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3433 CallingConv::ID CallerCC = CallerF->getCallingConv();
3434 bool CCMatch = CallerCC == CalleeCC;
3435 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3436 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3438 // Win64 functions have extra shadow space for argument homing. Don't do the
3439 // sibcall if the caller and callee have mismatched expectations for this
3441 if (IsCalleeWin64 != IsCallerWin64)
3444 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3445 if (IsTailCallConvention(CalleeCC) && CCMatch)
3450 // Look for obvious safe cases to perform tail call optimization that do not
3451 // require ABI changes. This is what gcc calls sibcall.
3453 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3454 // emit a special epilogue.
3455 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3456 if (RegInfo->needsStackRealignment(MF))
3459 // Also avoid sibcall optimization if either caller or callee uses struct
3460 // return semantics.
3461 if (isCalleeStructRet || isCallerStructRet)
3464 // An stdcall/thiscall caller is expected to clean up its arguments; the
3465 // callee isn't going to do that.
3466 // FIXME: this is more restrictive than needed. We could produce a tailcall
3467 // when the stack adjustment matches. For example, with a thiscall that takes
3468 // only one argument.
3469 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3470 CallerCC == CallingConv::X86_ThisCall))
3473 // Do not sibcall optimize vararg calls unless all arguments are passed via
3475 if (isVarArg && !Outs.empty()) {
3477 // Optimizing for varargs on Win64 is unlikely to be safe without
3478 // additional testing.
3479 if (IsCalleeWin64 || IsCallerWin64)
3482 SmallVector<CCValAssign, 16> ArgLocs;
3483 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3486 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3487 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3488 if (!ArgLocs[i].isRegLoc())
3492 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3493 // stack. Therefore, if it's not used by the call it is not safe to optimize
3494 // this into a sibcall.
3495 bool Unused = false;
3496 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3503 SmallVector<CCValAssign, 16> RVLocs;
3504 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3506 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3507 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3508 CCValAssign &VA = RVLocs[i];
3509 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3514 // If the calling conventions do not match, then we'd better make sure the
3515 // results are returned in the same way as what the caller expects.
3517 SmallVector<CCValAssign, 16> RVLocs1;
3518 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3520 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3522 SmallVector<CCValAssign, 16> RVLocs2;
3523 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3525 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3527 if (RVLocs1.size() != RVLocs2.size())
3529 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3530 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3532 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3534 if (RVLocs1[i].isRegLoc()) {
3535 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3538 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3544 // If the callee takes no arguments then go on to check the results of the
3546 if (!Outs.empty()) {
3547 // Check if stack adjustment is needed. For now, do not do this if any
3548 // argument is passed on the stack.
3549 SmallVector<CCValAssign, 16> ArgLocs;
3550 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3553 // Allocate shadow area for Win64
3555 CCInfo.AllocateStack(32, 8);
3557 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3558 if (CCInfo.getNextStackOffset()) {
3559 MachineFunction &MF = DAG.getMachineFunction();
3560 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3563 // Check if the arguments are already laid out in the right way as
3564 // the caller's fixed stack objects.
3565 MachineFrameInfo *MFI = MF.getFrameInfo();
3566 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3567 const X86InstrInfo *TII = Subtarget->getInstrInfo();
3568 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3569 CCValAssign &VA = ArgLocs[i];
3570 SDValue Arg = OutVals[i];
3571 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3572 if (VA.getLocInfo() == CCValAssign::Indirect)
3574 if (!VA.isRegLoc()) {
3575 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3582 // If the tailcall address may be in a register, then make sure it's
3583 // possible to register allocate for it. In 32-bit, the call address can
3584 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3585 // callee-saved registers are restored. These happen to be the same
3586 // registers used to pass 'inreg' arguments so watch out for those.
3587 if (!Subtarget->is64Bit() &&
3588 ((!isa<GlobalAddressSDNode>(Callee) &&
3589 !isa<ExternalSymbolSDNode>(Callee)) ||
3590 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3591 unsigned NumInRegs = 0;
3592 // In PIC we need an extra register to formulate the address computation
3594 unsigned MaxInRegs =
3595 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3597 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3598 CCValAssign &VA = ArgLocs[i];
3601 unsigned Reg = VA.getLocReg();
3604 case X86::EAX: case X86::EDX: case X86::ECX:
3605 if (++NumInRegs == MaxInRegs)
3617 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3618 const TargetLibraryInfo *libInfo) const {
3619 return X86::createFastISel(funcInfo, libInfo);
3622 //===----------------------------------------------------------------------===//
3623 // Other Lowering Hooks
3624 //===----------------------------------------------------------------------===//
3626 static bool MayFoldLoad(SDValue Op) {
3627 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3630 static bool MayFoldIntoStore(SDValue Op) {
3631 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3634 static bool isTargetShuffle(unsigned Opcode) {
3636 default: return false;
3637 case X86ISD::BLENDI:
3638 case X86ISD::PSHUFB:
3639 case X86ISD::PSHUFD:
3640 case X86ISD::PSHUFHW:
3641 case X86ISD::PSHUFLW:
3643 case X86ISD::PALIGNR:
3644 case X86ISD::MOVLHPS:
3645 case X86ISD::MOVLHPD:
3646 case X86ISD::MOVHLPS:
3647 case X86ISD::MOVLPS:
3648 case X86ISD::MOVLPD:
3649 case X86ISD::MOVSHDUP:
3650 case X86ISD::MOVSLDUP:
3651 case X86ISD::MOVDDUP:
3654 case X86ISD::UNPCKL:
3655 case X86ISD::UNPCKH:
3656 case X86ISD::VPERMILPI:
3657 case X86ISD::VPERM2X128:
3658 case X86ISD::VPERMI:
3663 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3664 SDValue V1, unsigned TargetMask,
3665 SelectionDAG &DAG) {
3667 default: llvm_unreachable("Unknown x86 shuffle node");
3668 case X86ISD::PSHUFD:
3669 case X86ISD::PSHUFHW:
3670 case X86ISD::PSHUFLW:
3671 case X86ISD::VPERMILPI:
3672 case X86ISD::VPERMI:
3673 return DAG.getNode(Opc, dl, VT, V1,
3674 DAG.getConstant(TargetMask, dl, MVT::i8));
3678 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3679 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3681 default: llvm_unreachable("Unknown x86 shuffle node");
3682 case X86ISD::MOVLHPS:
3683 case X86ISD::MOVLHPD:
3684 case X86ISD::MOVHLPS:
3685 case X86ISD::MOVLPS:
3686 case X86ISD::MOVLPD:
3689 case X86ISD::UNPCKL:
3690 case X86ISD::UNPCKH:
3691 return DAG.getNode(Opc, dl, VT, V1, V2);
3695 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3696 MachineFunction &MF = DAG.getMachineFunction();
3697 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3698 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3699 int ReturnAddrIndex = FuncInfo->getRAIndex();
3701 if (ReturnAddrIndex == 0) {
3702 // Set up a frame object for the return address.
3703 unsigned SlotSize = RegInfo->getSlotSize();
3704 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3707 FuncInfo->setRAIndex(ReturnAddrIndex);
3710 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3713 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3714 bool hasSymbolicDisplacement) {
3715 // Offset should fit into 32 bit immediate field.
3716 if (!isInt<32>(Offset))
3719 // If we don't have a symbolic displacement - we don't have any extra
3721 if (!hasSymbolicDisplacement)
3724 // FIXME: Some tweaks might be needed for medium code model.
3725 if (M != CodeModel::Small && M != CodeModel::Kernel)
3728 // For small code model we assume that latest object is 16MB before end of 31
3729 // bits boundary. We may also accept pretty large negative constants knowing
3730 // that all objects are in the positive half of address space.
3731 if (M == CodeModel::Small && Offset < 16*1024*1024)
3734 // For kernel code model we know that all object resist in the negative half
3735 // of 32bits address space. We may not accept negative offsets, since they may
3736 // be just off and we may accept pretty large positive ones.
3737 if (M == CodeModel::Kernel && Offset >= 0)
3743 /// isCalleePop - Determines whether the callee is required to pop its
3744 /// own arguments. Callee pop is necessary to support tail calls.
3745 bool X86::isCalleePop(CallingConv::ID CallingConv,
3746 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3747 switch (CallingConv) {
3750 case CallingConv::X86_StdCall:
3751 case CallingConv::X86_FastCall:
3752 case CallingConv::X86_ThisCall:
3754 case CallingConv::Fast:
3755 case CallingConv::GHC:
3756 case CallingConv::HiPE:
3763 /// \brief Return true if the condition is an unsigned comparison operation.
3764 static bool isX86CCUnsigned(unsigned X86CC) {
3766 default: llvm_unreachable("Invalid integer condition!");
3767 case X86::COND_E: return true;
3768 case X86::COND_G: return false;
3769 case X86::COND_GE: return false;
3770 case X86::COND_L: return false;
3771 case X86::COND_LE: return false;
3772 case X86::COND_NE: return true;
3773 case X86::COND_B: return true;
3774 case X86::COND_A: return true;
3775 case X86::COND_BE: return true;
3776 case X86::COND_AE: return true;
3778 llvm_unreachable("covered switch fell through?!");
3781 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3782 /// specific condition code, returning the condition code and the LHS/RHS of the
3783 /// comparison to make.
3784 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, SDLoc DL, bool isFP,
3785 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3787 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3788 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3789 // X > -1 -> X == 0, jump !sign.
3790 RHS = DAG.getConstant(0, DL, RHS.getValueType());
3791 return X86::COND_NS;
3793 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3794 // X < 0 -> X == 0, jump on sign.
3797 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3799 RHS = DAG.getConstant(0, DL, RHS.getValueType());
3800 return X86::COND_LE;
3804 switch (SetCCOpcode) {
3805 default: llvm_unreachable("Invalid integer condition!");
3806 case ISD::SETEQ: return X86::COND_E;
3807 case ISD::SETGT: return X86::COND_G;
3808 case ISD::SETGE: return X86::COND_GE;
3809 case ISD::SETLT: return X86::COND_L;
3810 case ISD::SETLE: return X86::COND_LE;
3811 case ISD::SETNE: return X86::COND_NE;
3812 case ISD::SETULT: return X86::COND_B;
3813 case ISD::SETUGT: return X86::COND_A;
3814 case ISD::SETULE: return X86::COND_BE;
3815 case ISD::SETUGE: return X86::COND_AE;
3819 // First determine if it is required or is profitable to flip the operands.
3821 // If LHS is a foldable load, but RHS is not, flip the condition.
3822 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3823 !ISD::isNON_EXTLoad(RHS.getNode())) {
3824 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3825 std::swap(LHS, RHS);
3828 switch (SetCCOpcode) {
3834 std::swap(LHS, RHS);
3838 // On a floating point condition, the flags are set as follows:
3840 // 0 | 0 | 0 | X > Y
3841 // 0 | 0 | 1 | X < Y
3842 // 1 | 0 | 0 | X == Y
3843 // 1 | 1 | 1 | unordered
3844 switch (SetCCOpcode) {
3845 default: llvm_unreachable("Condcode should be pre-legalized away");
3847 case ISD::SETEQ: return X86::COND_E;
3848 case ISD::SETOLT: // flipped
3850 case ISD::SETGT: return X86::COND_A;
3851 case ISD::SETOLE: // flipped
3853 case ISD::SETGE: return X86::COND_AE;
3854 case ISD::SETUGT: // flipped
3856 case ISD::SETLT: return X86::COND_B;
3857 case ISD::SETUGE: // flipped
3859 case ISD::SETLE: return X86::COND_BE;
3861 case ISD::SETNE: return X86::COND_NE;
3862 case ISD::SETUO: return X86::COND_P;
3863 case ISD::SETO: return X86::COND_NP;
3865 case ISD::SETUNE: return X86::COND_INVALID;
3869 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3870 /// code. Current x86 isa includes the following FP cmov instructions:
3871 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3872 static bool hasFPCMov(unsigned X86CC) {
3888 /// isFPImmLegal - Returns true if the target can instruction select the
3889 /// specified FP immediate natively. If false, the legalizer will
3890 /// materialize the FP immediate as a load from a constant pool.
3891 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3892 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3893 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3899 bool X86TargetLowering::shouldReduceLoadWidth(SDNode *Load,
3900 ISD::LoadExtType ExtTy,
3902 // "ELF Handling for Thread-Local Storage" specifies that R_X86_64_GOTTPOFF
3903 // relocation target a movq or addq instruction: don't let the load shrink.
3904 SDValue BasePtr = cast<LoadSDNode>(Load)->getBasePtr();
3905 if (BasePtr.getOpcode() == X86ISD::WrapperRIP)
3906 if (const auto *GA = dyn_cast<GlobalAddressSDNode>(BasePtr.getOperand(0)))
3907 return GA->getTargetFlags() != X86II::MO_GOTTPOFF;
3911 /// \brief Returns true if it is beneficial to convert a load of a constant
3912 /// to just the constant itself.
3913 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3915 assert(Ty->isIntegerTy());
3917 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3918 if (BitSize == 0 || BitSize > 64)
3923 bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT,
3924 unsigned Index) const {
3925 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
3928 return (Index == 0 || Index == ResVT.getVectorNumElements());
3931 bool X86TargetLowering::isCheapToSpeculateCttz() const {
3932 // Speculate cttz only if we can directly use TZCNT.
3933 return Subtarget->hasBMI();
3936 bool X86TargetLowering::isCheapToSpeculateCtlz() const {
3937 // Speculate ctlz only if we can directly use LZCNT.
3938 return Subtarget->hasLZCNT();
3941 /// isUndefInRange - Return true if every element in Mask, beginning
3942 /// from position Pos and ending in Pos+Size is undef.
3943 static bool isUndefInRange(ArrayRef<int> Mask, unsigned Pos, unsigned Size) {
3944 for (unsigned i = Pos, e = Pos + Size; i != e; ++i)
3950 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3951 /// the specified range (L, H].
3952 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3953 return (Val < 0) || (Val >= Low && Val < Hi);
3956 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3957 /// specified value.
3958 static bool isUndefOrEqual(int Val, int CmpVal) {
3959 return (Val < 0 || Val == CmpVal);
3962 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3963 /// from position Pos and ending in Pos+Size, falls within the specified
3964 /// sequential range (Low, Low+Size]. or is undef.
3965 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3966 unsigned Pos, unsigned Size, int Low) {
3967 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3968 if (!isUndefOrEqual(Mask[i], Low))
3973 /// isVEXTRACTIndex - Return true if the specified
3974 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
3975 /// suitable for instruction that extract 128 or 256 bit vectors
3976 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
3977 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
3978 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3981 // The index should be aligned on a vecWidth-bit boundary.
3983 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3985 MVT VT = N->getSimpleValueType(0);
3986 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
3987 bool Result = (Index * ElSize) % vecWidth == 0;
3992 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
3993 /// operand specifies a subvector insert that is suitable for input to
3994 /// insertion of 128 or 256-bit subvectors
3995 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
3996 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
3997 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3999 // The index should be aligned on a vecWidth-bit boundary.
4001 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4003 MVT VT = N->getSimpleValueType(0);
4004 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4005 bool Result = (Index * ElSize) % vecWidth == 0;
4010 bool X86::isVINSERT128Index(SDNode *N) {
4011 return isVINSERTIndex(N, 128);
4014 bool X86::isVINSERT256Index(SDNode *N) {
4015 return isVINSERTIndex(N, 256);
4018 bool X86::isVEXTRACT128Index(SDNode *N) {
4019 return isVEXTRACTIndex(N, 128);
4022 bool X86::isVEXTRACT256Index(SDNode *N) {
4023 return isVEXTRACTIndex(N, 256);
4026 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4027 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4028 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4029 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4032 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4034 MVT VecVT = N->getOperand(0).getSimpleValueType();
4035 MVT ElVT = VecVT.getVectorElementType();
4037 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4038 return Index / NumElemsPerChunk;
4041 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4042 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4043 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4044 llvm_unreachable("Illegal insert subvector for VINSERT");
4047 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4049 MVT VecVT = N->getSimpleValueType(0);
4050 MVT ElVT = VecVT.getVectorElementType();
4052 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4053 return Index / NumElemsPerChunk;
4056 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4057 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4058 /// and VINSERTI128 instructions.
4059 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4060 return getExtractVEXTRACTImmediate(N, 128);
4063 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4064 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4065 /// and VINSERTI64x4 instructions.
4066 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4067 return getExtractVEXTRACTImmediate(N, 256);
4070 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4071 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4072 /// and VINSERTI128 instructions.
4073 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4074 return getInsertVINSERTImmediate(N, 128);
4077 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4078 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4079 /// and VINSERTI64x4 instructions.
4080 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4081 return getInsertVINSERTImmediate(N, 256);
4084 /// isZero - Returns true if Elt is a constant integer zero
4085 static bool isZero(SDValue V) {
4086 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4087 return C && C->isNullValue();
4090 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4092 bool X86::isZeroNode(SDValue Elt) {
4095 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4096 return CFP->getValueAPF().isPosZero();
4100 /// getZeroVector - Returns a vector of specified type with all zero elements.
4102 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4103 SelectionDAG &DAG, SDLoc dl) {
4104 assert(VT.isVector() && "Expected a vector type");
4106 // Always build SSE zero vectors as <4 x i32> bitcasted
4107 // to their dest type. This ensures they get CSE'd.
4109 if (VT.is128BitVector()) { // SSE
4110 if (Subtarget->hasSSE2()) { // SSE2
4111 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4112 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4114 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
4115 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4117 } else if (VT.is256BitVector()) { // AVX
4118 if (Subtarget->hasInt256()) { // AVX2
4119 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4120 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4121 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4123 // 256-bit logic and arithmetic instructions in AVX are all
4124 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4125 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
4126 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4127 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
4129 } else if (VT.is512BitVector()) { // AVX-512
4130 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4131 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4132 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4133 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
4134 } else if (VT.getScalarType() == MVT::i1) {
4136 assert((Subtarget->hasBWI() || VT.getVectorNumElements() <= 16)
4137 && "Unexpected vector type");
4138 assert((Subtarget->hasVLX() || VT.getVectorNumElements() >= 8)
4139 && "Unexpected vector type");
4140 SDValue Cst = DAG.getConstant(0, dl, MVT::i1);
4141 SmallVector<SDValue, 64> Ops(VT.getVectorNumElements(), Cst);
4142 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
4144 llvm_unreachable("Unexpected vector type");
4146 return DAG.getBitcast(VT, Vec);
4149 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
4150 SelectionDAG &DAG, SDLoc dl,
4151 unsigned vectorWidth) {
4152 assert((vectorWidth == 128 || vectorWidth == 256) &&
4153 "Unsupported vector width");
4154 EVT VT = Vec.getValueType();
4155 EVT ElVT = VT.getVectorElementType();
4156 unsigned Factor = VT.getSizeInBits()/vectorWidth;
4157 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
4158 VT.getVectorNumElements()/Factor);
4160 // Extract from UNDEF is UNDEF.
4161 if (Vec.getOpcode() == ISD::UNDEF)
4162 return DAG.getUNDEF(ResultVT);
4164 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
4165 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
4167 // This is the index of the first element of the vectorWidth-bit chunk
4169 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
4172 // If the input is a buildvector just emit a smaller one.
4173 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
4174 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
4175 makeArrayRef(Vec->op_begin() + NormalizedIdxVal,
4178 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal, dl);
4179 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, VecIdx);
4182 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
4183 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
4184 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
4185 /// instructions or a simple subregister reference. Idx is an index in the
4186 /// 128 bits we want. It need not be aligned to a 128-bit boundary. That makes
4187 /// lowering EXTRACT_VECTOR_ELT operations easier.
4188 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
4189 SelectionDAG &DAG, SDLoc dl) {
4190 assert((Vec.getValueType().is256BitVector() ||
4191 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
4192 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
4195 /// Generate a DAG to grab 256-bits from a 512-bit vector.
4196 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
4197 SelectionDAG &DAG, SDLoc dl) {
4198 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
4199 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
4202 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
4203 unsigned IdxVal, SelectionDAG &DAG,
4204 SDLoc dl, unsigned vectorWidth) {
4205 assert((vectorWidth == 128 || vectorWidth == 256) &&
4206 "Unsupported vector width");
4207 // Inserting UNDEF is Result
4208 if (Vec.getOpcode() == ISD::UNDEF)
4210 EVT VT = Vec.getValueType();
4211 EVT ElVT = VT.getVectorElementType();
4212 EVT ResultVT = Result.getValueType();
4214 // Insert the relevant vectorWidth bits.
4215 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
4217 // This is the index of the first element of the vectorWidth-bit chunk
4219 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
4222 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal, dl);
4223 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, VecIdx);
4226 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
4227 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
4228 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
4229 /// simple superregister reference. Idx is an index in the 128 bits
4230 /// we want. It need not be aligned to a 128-bit boundary. That makes
4231 /// lowering INSERT_VECTOR_ELT operations easier.
4232 static SDValue Insert128BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4233 SelectionDAG &DAG, SDLoc dl) {
4234 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
4236 // For insertion into the zero index (low half) of a 256-bit vector, it is
4237 // more efficient to generate a blend with immediate instead of an insert*128.
4238 // We are still creating an INSERT_SUBVECTOR below with an undef node to
4239 // extend the subvector to the size of the result vector. Make sure that
4240 // we are not recursing on that node by checking for undef here.
4241 if (IdxVal == 0 && Result.getValueType().is256BitVector() &&
4242 Result.getOpcode() != ISD::UNDEF) {
4243 EVT ResultVT = Result.getValueType();
4244 SDValue ZeroIndex = DAG.getIntPtrConstant(0, dl);
4245 SDValue Undef = DAG.getUNDEF(ResultVT);
4246 SDValue Vec256 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Undef,
4249 // The blend instruction, and therefore its mask, depend on the data type.
4250 MVT ScalarType = ResultVT.getScalarType().getSimpleVT();
4251 if (ScalarType.isFloatingPoint()) {
4252 // Choose either vblendps (float) or vblendpd (double).
4253 unsigned ScalarSize = ScalarType.getSizeInBits();
4254 assert((ScalarSize == 64 || ScalarSize == 32) && "Unknown float type");
4255 unsigned MaskVal = (ScalarSize == 64) ? 0x03 : 0x0f;
4256 SDValue Mask = DAG.getConstant(MaskVal, dl, MVT::i8);
4257 return DAG.getNode(X86ISD::BLENDI, dl, ResultVT, Result, Vec256, Mask);
4260 const X86Subtarget &Subtarget =
4261 static_cast<const X86Subtarget &>(DAG.getSubtarget());
4263 // AVX2 is needed for 256-bit integer blend support.
4264 // Integers must be cast to 32-bit because there is only vpblendd;
4265 // vpblendw can't be used for this because it has a handicapped mask.
4267 // If we don't have AVX2, then cast to float. Using a wrong domain blend
4268 // is still more efficient than using the wrong domain vinsertf128 that
4269 // will be created by InsertSubVector().
4270 MVT CastVT = Subtarget.hasAVX2() ? MVT::v8i32 : MVT::v8f32;
4272 SDValue Mask = DAG.getConstant(0x0f, dl, MVT::i8);
4273 Vec256 = DAG.getBitcast(CastVT, Vec256);
4274 Vec256 = DAG.getNode(X86ISD::BLENDI, dl, CastVT, Result, Vec256, Mask);
4275 return DAG.getBitcast(ResultVT, Vec256);
4278 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
4281 static SDValue Insert256BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4282 SelectionDAG &DAG, SDLoc dl) {
4283 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
4284 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
4287 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
4288 /// instructions. This is used because creating CONCAT_VECTOR nodes of
4289 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
4290 /// large BUILD_VECTORS.
4291 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
4292 unsigned NumElems, SelectionDAG &DAG,
4294 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4295 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
4298 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
4299 unsigned NumElems, SelectionDAG &DAG,
4301 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4302 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
4305 /// getOnesVector - Returns a vector of specified type with all bits set.
4306 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4307 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4308 /// Then bitcast to their original type, ensuring they get CSE'd.
4309 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
4311 assert(VT.isVector() && "Expected a vector type");
4313 SDValue Cst = DAG.getConstant(~0U, dl, MVT::i32);
4315 if (VT.is256BitVector()) {
4316 if (HasInt256) { // AVX2
4317 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4318 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4320 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4321 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4323 } else if (VT.is128BitVector()) {
4324 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4326 llvm_unreachable("Unexpected vector type");
4328 return DAG.getBitcast(VT, Vec);
4331 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4332 /// operation of specified width.
4333 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
4335 unsigned NumElems = VT.getVectorNumElements();
4336 SmallVector<int, 8> Mask;
4337 Mask.push_back(NumElems);
4338 for (unsigned i = 1; i != NumElems; ++i)
4340 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4343 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4344 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4346 unsigned NumElems = VT.getVectorNumElements();
4347 SmallVector<int, 8> Mask;
4348 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4350 Mask.push_back(i + NumElems);
4352 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4355 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4356 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4358 unsigned NumElems = VT.getVectorNumElements();
4359 SmallVector<int, 8> Mask;
4360 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4361 Mask.push_back(i + Half);
4362 Mask.push_back(i + NumElems + Half);
4364 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4367 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4368 /// vector of zero or undef vector. This produces a shuffle where the low
4369 /// element of V2 is swizzled into the zero/undef vector, landing at element
4370 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4371 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4373 const X86Subtarget *Subtarget,
4374 SelectionDAG &DAG) {
4375 MVT VT = V2.getSimpleValueType();
4377 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
4378 unsigned NumElems = VT.getVectorNumElements();
4379 SmallVector<int, 16> MaskVec;
4380 for (unsigned i = 0; i != NumElems; ++i)
4381 // If this is the insertion idx, put the low elt of V2 here.
4382 MaskVec.push_back(i == Idx ? NumElems : i);
4383 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
4386 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
4387 /// target specific opcode. Returns true if the Mask could be calculated. Sets
4388 /// IsUnary to true if only uses one source. Note that this will set IsUnary for
4389 /// shuffles which use a single input multiple times, and in those cases it will
4390 /// adjust the mask to only have indices within that single input.
4391 static bool getTargetShuffleMask(SDNode *N, MVT VT,
4392 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4393 unsigned NumElems = VT.getVectorNumElements();
4397 bool IsFakeUnary = false;
4398 switch(N->getOpcode()) {
4399 case X86ISD::BLENDI:
4400 ImmN = N->getOperand(N->getNumOperands()-1);
4401 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4404 ImmN = N->getOperand(N->getNumOperands()-1);
4405 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4406 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4408 case X86ISD::UNPCKH:
4409 DecodeUNPCKHMask(VT, Mask);
4410 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4412 case X86ISD::UNPCKL:
4413 DecodeUNPCKLMask(VT, Mask);
4414 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4416 case X86ISD::MOVHLPS:
4417 DecodeMOVHLPSMask(NumElems, Mask);
4418 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4420 case X86ISD::MOVLHPS:
4421 DecodeMOVLHPSMask(NumElems, Mask);
4422 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4424 case X86ISD::PALIGNR:
4425 ImmN = N->getOperand(N->getNumOperands()-1);
4426 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4428 case X86ISD::PSHUFD:
4429 case X86ISD::VPERMILPI:
4430 ImmN = N->getOperand(N->getNumOperands()-1);
4431 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4434 case X86ISD::PSHUFHW:
4435 ImmN = N->getOperand(N->getNumOperands()-1);
4436 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4439 case X86ISD::PSHUFLW:
4440 ImmN = N->getOperand(N->getNumOperands()-1);
4441 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4444 case X86ISD::PSHUFB: {
4446 SDValue MaskNode = N->getOperand(1);
4447 while (MaskNode->getOpcode() == ISD::BITCAST)
4448 MaskNode = MaskNode->getOperand(0);
4450 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4451 // If we have a build-vector, then things are easy.
4452 EVT VT = MaskNode.getValueType();
4453 assert(VT.isVector() &&
4454 "Can't produce a non-vector with a build_vector!");
4455 if (!VT.isInteger())
4458 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
4460 SmallVector<uint64_t, 32> RawMask;
4461 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
4462 SDValue Op = MaskNode->getOperand(i);
4463 if (Op->getOpcode() == ISD::UNDEF) {
4464 RawMask.push_back((uint64_t)SM_SentinelUndef);
4467 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
4470 APInt MaskElement = CN->getAPIntValue();
4472 // We now have to decode the element which could be any integer size and
4473 // extract each byte of it.
4474 for (int j = 0; j < NumBytesPerElement; ++j) {
4475 // Note that this is x86 and so always little endian: the low byte is
4476 // the first byte of the mask.
4477 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
4478 MaskElement = MaskElement.lshr(8);
4481 DecodePSHUFBMask(RawMask, Mask);
4485 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4489 SDValue Ptr = MaskLoad->getBasePtr();
4490 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4491 Ptr->getOpcode() == X86ISD::WrapperRIP)
4492 Ptr = Ptr->getOperand(0);
4494 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4495 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4498 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
4499 DecodePSHUFBMask(C, Mask);
4507 case X86ISD::VPERMI:
4508 ImmN = N->getOperand(N->getNumOperands()-1);
4509 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4514 DecodeScalarMoveMask(VT, /* IsLoad */ false, Mask);
4516 case X86ISD::VPERM2X128:
4517 ImmN = N->getOperand(N->getNumOperands()-1);
4518 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4519 if (Mask.empty()) return false;
4521 case X86ISD::MOVSLDUP:
4522 DecodeMOVSLDUPMask(VT, Mask);
4525 case X86ISD::MOVSHDUP:
4526 DecodeMOVSHDUPMask(VT, Mask);
4529 case X86ISD::MOVDDUP:
4530 DecodeMOVDDUPMask(VT, Mask);
4533 case X86ISD::MOVLHPD:
4534 case X86ISD::MOVLPD:
4535 case X86ISD::MOVLPS:
4536 // Not yet implemented
4538 default: llvm_unreachable("unknown target shuffle node");
4541 // If we have a fake unary shuffle, the shuffle mask is spread across two
4542 // inputs that are actually the same node. Re-map the mask to always point
4543 // into the first input.
4546 if (M >= (int)Mask.size())
4552 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4553 /// element of the result of the vector shuffle.
4554 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
4557 return SDValue(); // Limit search depth.
4559 SDValue V = SDValue(N, 0);
4560 EVT VT = V.getValueType();
4561 unsigned Opcode = V.getOpcode();
4563 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4564 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4565 int Elt = SV->getMaskElt(Index);
4568 return DAG.getUNDEF(VT.getVectorElementType());
4570 unsigned NumElems = VT.getVectorNumElements();
4571 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
4572 : SV->getOperand(1);
4573 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
4576 // Recurse into target specific vector shuffles to find scalars.
4577 if (isTargetShuffle(Opcode)) {
4578 MVT ShufVT = V.getSimpleValueType();
4579 unsigned NumElems = ShufVT.getVectorNumElements();
4580 SmallVector<int, 16> ShuffleMask;
4583 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
4586 int Elt = ShuffleMask[Index];
4588 return DAG.getUNDEF(ShufVT.getVectorElementType());
4590 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
4592 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
4596 // Actual nodes that may contain scalar elements
4597 if (Opcode == ISD::BITCAST) {
4598 V = V.getOperand(0);
4599 EVT SrcVT = V.getValueType();
4600 unsigned NumElems = VT.getVectorNumElements();
4602 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4606 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4607 return (Index == 0) ? V.getOperand(0)
4608 : DAG.getUNDEF(VT.getVectorElementType());
4610 if (V.getOpcode() == ISD::BUILD_VECTOR)
4611 return V.getOperand(Index);
4616 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
4618 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4619 unsigned NumNonZero, unsigned NumZero,
4621 const X86Subtarget* Subtarget,
4622 const TargetLowering &TLI) {
4630 // SSE4.1 - use PINSRB to insert each byte directly.
4631 if (Subtarget->hasSSE41()) {
4632 for (unsigned i = 0; i < 16; ++i) {
4633 bool isNonZero = (NonZeros & (1 << i)) != 0;
4637 V = getZeroVector(MVT::v16i8, Subtarget, DAG, dl);
4639 V = DAG.getUNDEF(MVT::v16i8);
4642 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4643 MVT::v16i8, V, Op.getOperand(i),
4644 DAG.getIntPtrConstant(i, dl));
4651 // Pre-SSE4.1 - merge byte pairs and insert with PINSRW.
4652 for (unsigned i = 0; i < 16; ++i) {
4653 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4654 if (ThisIsNonZero && First) {
4656 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4658 V = DAG.getUNDEF(MVT::v8i16);
4663 SDValue ThisElt, LastElt;
4664 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4665 if (LastIsNonZero) {
4666 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4667 MVT::i16, Op.getOperand(i-1));
4669 if (ThisIsNonZero) {
4670 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4671 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4672 ThisElt, DAG.getConstant(8, dl, MVT::i8));
4674 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4678 if (ThisElt.getNode())
4679 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
4680 DAG.getIntPtrConstant(i/2, dl));
4684 return DAG.getBitcast(MVT::v16i8, V);
4687 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
4689 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
4690 unsigned NumNonZero, unsigned NumZero,
4692 const X86Subtarget* Subtarget,
4693 const TargetLowering &TLI) {
4700 for (unsigned i = 0; i < 8; ++i) {
4701 bool isNonZero = (NonZeros & (1 << i)) != 0;
4705 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4707 V = DAG.getUNDEF(MVT::v8i16);
4710 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4711 MVT::v8i16, V, Op.getOperand(i),
4712 DAG.getIntPtrConstant(i, dl));
4719 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
4720 static SDValue LowerBuildVectorv4x32(SDValue Op, SelectionDAG &DAG,
4721 const X86Subtarget *Subtarget,
4722 const TargetLowering &TLI) {
4723 // Find all zeroable elements.
4724 std::bitset<4> Zeroable;
4725 for (int i=0; i < 4; ++i) {
4726 SDValue Elt = Op->getOperand(i);
4727 Zeroable[i] = (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt));
4729 assert(Zeroable.size() - Zeroable.count() > 1 &&
4730 "We expect at least two non-zero elements!");
4732 // We only know how to deal with build_vector nodes where elements are either
4733 // zeroable or extract_vector_elt with constant index.
4734 SDValue FirstNonZero;
4735 unsigned FirstNonZeroIdx;
4736 for (unsigned i=0; i < 4; ++i) {
4739 SDValue Elt = Op->getOperand(i);
4740 if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
4741 !isa<ConstantSDNode>(Elt.getOperand(1)))
4743 // Make sure that this node is extracting from a 128-bit vector.
4744 MVT VT = Elt.getOperand(0).getSimpleValueType();
4745 if (!VT.is128BitVector())
4747 if (!FirstNonZero.getNode()) {
4749 FirstNonZeroIdx = i;
4753 assert(FirstNonZero.getNode() && "Unexpected build vector of all zeros!");
4754 SDValue V1 = FirstNonZero.getOperand(0);
4755 MVT VT = V1.getSimpleValueType();
4757 // See if this build_vector can be lowered as a blend with zero.
4759 unsigned EltMaskIdx, EltIdx;
4761 for (EltIdx = 0; EltIdx < 4; ++EltIdx) {
4762 if (Zeroable[EltIdx]) {
4763 // The zero vector will be on the right hand side.
4764 Mask[EltIdx] = EltIdx+4;
4768 Elt = Op->getOperand(EltIdx);
4769 // By construction, Elt is a EXTRACT_VECTOR_ELT with constant index.
4770 EltMaskIdx = cast<ConstantSDNode>(Elt.getOperand(1))->getZExtValue();
4771 if (Elt.getOperand(0) != V1 || EltMaskIdx != EltIdx)
4773 Mask[EltIdx] = EltIdx;
4777 // Let the shuffle legalizer deal with blend operations.
4778 SDValue VZero = getZeroVector(VT, Subtarget, DAG, SDLoc(Op));
4779 if (V1.getSimpleValueType() != VT)
4780 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), VT, V1);
4781 return DAG.getVectorShuffle(VT, SDLoc(V1), V1, VZero, &Mask[0]);
4784 // See if we can lower this build_vector to a INSERTPS.
4785 if (!Subtarget->hasSSE41())
4788 SDValue V2 = Elt.getOperand(0);
4789 if (Elt == FirstNonZero && EltIdx == FirstNonZeroIdx)
4792 bool CanFold = true;
4793 for (unsigned i = EltIdx + 1; i < 4 && CanFold; ++i) {
4797 SDValue Current = Op->getOperand(i);
4798 SDValue SrcVector = Current->getOperand(0);
4801 CanFold = SrcVector == V1 &&
4802 cast<ConstantSDNode>(Current.getOperand(1))->getZExtValue() == i;
4808 assert(V1.getNode() && "Expected at least two non-zero elements!");
4809 if (V1.getSimpleValueType() != MVT::v4f32)
4810 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), MVT::v4f32, V1);
4811 if (V2.getSimpleValueType() != MVT::v4f32)
4812 V2 = DAG.getNode(ISD::BITCAST, SDLoc(V2), MVT::v4f32, V2);
4814 // Ok, we can emit an INSERTPS instruction.
4815 unsigned ZMask = Zeroable.to_ulong();
4817 unsigned InsertPSMask = EltMaskIdx << 6 | EltIdx << 4 | ZMask;
4818 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
4820 SDValue Result = DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
4821 DAG.getIntPtrConstant(InsertPSMask, DL));
4822 return DAG.getBitcast(VT, Result);
4825 /// Return a vector logical shift node.
4826 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
4827 unsigned NumBits, SelectionDAG &DAG,
4828 const TargetLowering &TLI, SDLoc dl) {
4829 assert(VT.is128BitVector() && "Unknown type for VShift");
4830 MVT ShVT = MVT::v2i64;
4831 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
4832 SrcOp = DAG.getBitcast(ShVT, SrcOp);
4833 MVT ScalarShiftTy = TLI.getScalarShiftAmountTy(SrcOp.getValueType());
4834 assert(NumBits % 8 == 0 && "Only support byte sized shifts");
4835 SDValue ShiftVal = DAG.getConstant(NumBits/8, dl, ScalarShiftTy);
4836 return DAG.getBitcast(VT, DAG.getNode(Opc, dl, ShVT, SrcOp, ShiftVal));
4840 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
4842 // Check if the scalar load can be widened into a vector load. And if
4843 // the address is "base + cst" see if the cst can be "absorbed" into
4844 // the shuffle mask.
4845 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
4846 SDValue Ptr = LD->getBasePtr();
4847 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
4849 EVT PVT = LD->getValueType(0);
4850 if (PVT != MVT::i32 && PVT != MVT::f32)
4855 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
4856 FI = FINode->getIndex();
4858 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
4859 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4860 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4861 Offset = Ptr.getConstantOperandVal(1);
4862 Ptr = Ptr.getOperand(0);
4867 // FIXME: 256-bit vector instructions don't require a strict alignment,
4868 // improve this code to support it better.
4869 unsigned RequiredAlign = VT.getSizeInBits()/8;
4870 SDValue Chain = LD->getChain();
4871 // Make sure the stack object alignment is at least 16 or 32.
4872 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4873 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
4874 if (MFI->isFixedObjectIndex(FI)) {
4875 // Can't change the alignment. FIXME: It's possible to compute
4876 // the exact stack offset and reference FI + adjust offset instead.
4877 // If someone *really* cares about this. That's the way to implement it.
4880 MFI->setObjectAlignment(FI, RequiredAlign);
4884 // (Offset % 16 or 32) must be multiple of 4. Then address is then
4885 // Ptr + (Offset & ~15).
4888 if ((Offset % RequiredAlign) & 3)
4890 int64_t StartOffset = Offset & ~(RequiredAlign-1);
4893 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
4894 DAG.getConstant(StartOffset, DL, Ptr.getValueType()));
4897 int EltNo = (Offset - StartOffset) >> 2;
4898 unsigned NumElems = VT.getVectorNumElements();
4900 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
4901 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
4902 LD->getPointerInfo().getWithOffset(StartOffset),
4903 false, false, false, 0);
4905 SmallVector<int, 8> Mask(NumElems, EltNo);
4907 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
4913 /// Given the initializing elements 'Elts' of a vector of type 'VT', see if the
4914 /// elements can be replaced by a single large load which has the same value as
4915 /// a build_vector or insert_subvector whose loaded operands are 'Elts'.
4917 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
4919 /// FIXME: we'd also like to handle the case where the last elements are zero
4920 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
4921 /// There's even a handy isZeroNode for that purpose.
4922 static SDValue EltsFromConsecutiveLoads(EVT VT, ArrayRef<SDValue> Elts,
4923 SDLoc &DL, SelectionDAG &DAG,
4924 bool isAfterLegalize) {
4925 unsigned NumElems = Elts.size();
4927 LoadSDNode *LDBase = nullptr;
4928 unsigned LastLoadedElt = -1U;
4930 // For each element in the initializer, see if we've found a load or an undef.
4931 // If we don't find an initial load element, or later load elements are
4932 // non-consecutive, bail out.
4933 for (unsigned i = 0; i < NumElems; ++i) {
4934 SDValue Elt = Elts[i];
4935 // Look through a bitcast.
4936 if (Elt.getNode() && Elt.getOpcode() == ISD::BITCAST)
4937 Elt = Elt.getOperand(0);
4938 if (!Elt.getNode() ||
4939 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
4942 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
4944 LDBase = cast<LoadSDNode>(Elt.getNode());
4948 if (Elt.getOpcode() == ISD::UNDEF)
4951 LoadSDNode *LD = cast<LoadSDNode>(Elt);
4952 EVT LdVT = Elt.getValueType();
4953 // Each loaded element must be the correct fractional portion of the
4954 // requested vector load.
4955 if (LdVT.getSizeInBits() != VT.getSizeInBits() / NumElems)
4957 if (!DAG.isConsecutiveLoad(LD, LDBase, LdVT.getSizeInBits() / 8, i))
4962 // If we have found an entire vector of loads and undefs, then return a large
4963 // load of the entire vector width starting at the base pointer. If we found
4964 // consecutive loads for the low half, generate a vzext_load node.
4965 if (LastLoadedElt == NumElems - 1) {
4966 assert(LDBase && "Did not find base load for merging consecutive loads");
4967 EVT EltVT = LDBase->getValueType(0);
4968 // Ensure that the input vector size for the merged loads matches the
4969 // cumulative size of the input elements.
4970 if (VT.getSizeInBits() != EltVT.getSizeInBits() * NumElems)
4973 if (isAfterLegalize &&
4974 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
4977 SDValue NewLd = SDValue();
4979 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4980 LDBase->getPointerInfo(), LDBase->isVolatile(),
4981 LDBase->isNonTemporal(), LDBase->isInvariant(),
4982 LDBase->getAlignment());
4984 if (LDBase->hasAnyUseOfValue(1)) {
4985 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
4987 SDValue(NewLd.getNode(), 1));
4988 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
4989 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
4990 SDValue(NewLd.getNode(), 1));
4996 //TODO: The code below fires only for for loading the low v2i32 / v2f32
4997 //of a v4i32 / v4f32. It's probably worth generalizing.
4998 EVT EltVT = VT.getVectorElementType();
4999 if (NumElems == 4 && LastLoadedElt == 1 && (EltVT.getSizeInBits() == 32) &&
5000 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5001 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5002 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5004 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
5005 LDBase->getPointerInfo(),
5006 LDBase->getAlignment(),
5007 false/*isVolatile*/, true/*ReadMem*/,
5010 // Make sure the newly-created LOAD is in the same position as LDBase in
5011 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5012 // update uses of LDBase's output chain to use the TokenFactor.
5013 if (LDBase->hasAnyUseOfValue(1)) {
5014 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5015 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5016 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5017 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5018 SDValue(ResNode.getNode(), 1));
5021 return DAG.getBitcast(VT, ResNode);
5026 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
5027 /// to generate a splat value for the following cases:
5028 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
5029 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
5030 /// a scalar load, or a constant.
5031 /// The VBROADCAST node is returned when a pattern is found,
5032 /// or SDValue() otherwise.
5033 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
5034 SelectionDAG &DAG) {
5035 // VBROADCAST requires AVX.
5036 // TODO: Splats could be generated for non-AVX CPUs using SSE
5037 // instructions, but there's less potential gain for only 128-bit vectors.
5038 if (!Subtarget->hasAVX())
5041 MVT VT = Op.getSimpleValueType();
5044 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
5045 "Unsupported vector type for broadcast.");
5050 switch (Op.getOpcode()) {
5052 // Unknown pattern found.
5055 case ISD::BUILD_VECTOR: {
5056 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
5057 BitVector UndefElements;
5058 SDValue Splat = BVOp->getSplatValue(&UndefElements);
5060 // We need a splat of a single value to use broadcast, and it doesn't
5061 // make any sense if the value is only in one element of the vector.
5062 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
5066 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5067 Ld.getOpcode() == ISD::ConstantFP);
5069 // Make sure that all of the users of a non-constant load are from the
5070 // BUILD_VECTOR node.
5071 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
5076 case ISD::VECTOR_SHUFFLE: {
5077 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5079 // Shuffles must have a splat mask where the first element is
5081 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5084 SDValue Sc = Op.getOperand(0);
5085 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5086 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5088 if (!Subtarget->hasInt256())
5091 // Use the register form of the broadcast instruction available on AVX2.
5092 if (VT.getSizeInBits() >= 256)
5093 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5094 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5097 Ld = Sc.getOperand(0);
5098 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5099 Ld.getOpcode() == ISD::ConstantFP);
5101 // The scalar_to_vector node and the suspected
5102 // load node must have exactly one user.
5103 // Constants may have multiple users.
5105 // AVX-512 has register version of the broadcast
5106 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
5107 Ld.getValueType().getSizeInBits() >= 32;
5108 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
5115 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5116 bool IsGE256 = (VT.getSizeInBits() >= 256);
5118 // When optimizing for size, generate up to 5 extra bytes for a broadcast
5119 // instruction to save 8 or more bytes of constant pool data.
5120 // TODO: If multiple splats are generated to load the same constant,
5121 // it may be detrimental to overall size. There needs to be a way to detect
5122 // that condition to know if this is truly a size win.
5123 const Function *F = DAG.getMachineFunction().getFunction();
5124 bool OptForSize = F->hasFnAttribute(Attribute::OptimizeForSize);
5126 // Handle broadcasting a single constant scalar from the constant pool
5128 // On Sandybridge (no AVX2), it is still better to load a constant vector
5129 // from the constant pool and not to broadcast it from a scalar.
5130 // But override that restriction when optimizing for size.
5131 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
5132 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
5133 EVT CVT = Ld.getValueType();
5134 assert(!CVT.isVector() && "Must not broadcast a vector type");
5136 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
5137 // For size optimization, also splat v2f64 and v2i64, and for size opt
5138 // with AVX2, also splat i8 and i16.
5139 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
5140 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5141 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
5142 const Constant *C = nullptr;
5143 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5144 C = CI->getConstantIntValue();
5145 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5146 C = CF->getConstantFPValue();
5148 assert(C && "Invalid constant type");
5150 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5151 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
5152 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5153 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
5154 MachinePointerInfo::getConstantPool(),
5155 false, false, false, Alignment);
5157 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5161 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5163 // Handle AVX2 in-register broadcasts.
5164 if (!IsLoad && Subtarget->hasInt256() &&
5165 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
5166 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5168 // The scalar source must be a normal load.
5172 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5173 (Subtarget->hasVLX() && ScalarSize == 64))
5174 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5176 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5177 // double since there is no vbroadcastsd xmm
5178 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
5179 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5180 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5183 // Unsupported broadcast.
5187 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
5188 /// underlying vector and index.
5190 /// Modifies \p ExtractedFromVec to the real vector and returns the real
5192 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
5194 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
5195 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
5198 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
5200 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
5202 // (extract_vector_elt (vector_shuffle<2,u,u,u>
5203 // (extract_subvector (v8f32 %vreg0), Constant<4>),
5206 // In this case the vector is the extract_subvector expression and the index
5207 // is 2, as specified by the shuffle.
5208 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
5209 SDValue ShuffleVec = SVOp->getOperand(0);
5210 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
5211 assert(ShuffleVecVT.getVectorElementType() ==
5212 ExtractedFromVec.getSimpleValueType().getVectorElementType());
5214 int ShuffleIdx = SVOp->getMaskElt(Idx);
5215 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
5216 ExtractedFromVec = ShuffleVec;
5222 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
5223 MVT VT = Op.getSimpleValueType();
5225 // Skip if insert_vec_elt is not supported.
5226 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5227 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
5231 unsigned NumElems = Op.getNumOperands();
5235 SmallVector<unsigned, 4> InsertIndices;
5236 SmallVector<int, 8> Mask(NumElems, -1);
5238 for (unsigned i = 0; i != NumElems; ++i) {
5239 unsigned Opc = Op.getOperand(i).getOpcode();
5241 if (Opc == ISD::UNDEF)
5244 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
5245 // Quit if more than 1 elements need inserting.
5246 if (InsertIndices.size() > 1)
5249 InsertIndices.push_back(i);
5253 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
5254 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
5255 // Quit if non-constant index.
5256 if (!isa<ConstantSDNode>(ExtIdx))
5258 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
5260 // Quit if extracted from vector of different type.
5261 if (ExtractedFromVec.getValueType() != VT)
5264 if (!VecIn1.getNode())
5265 VecIn1 = ExtractedFromVec;
5266 else if (VecIn1 != ExtractedFromVec) {
5267 if (!VecIn2.getNode())
5268 VecIn2 = ExtractedFromVec;
5269 else if (VecIn2 != ExtractedFromVec)
5270 // Quit if more than 2 vectors to shuffle
5274 if (ExtractedFromVec == VecIn1)
5276 else if (ExtractedFromVec == VecIn2)
5277 Mask[i] = Idx + NumElems;
5280 if (!VecIn1.getNode())
5283 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5284 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
5285 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
5286 unsigned Idx = InsertIndices[i];
5287 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
5288 DAG.getIntPtrConstant(Idx, DL));
5294 static SDValue ConvertI1VectorToInterger(SDValue Op, SelectionDAG &DAG) {
5295 assert(ISD::isBuildVectorOfConstantSDNodes(Op.getNode()) &&
5296 Op.getScalarValueSizeInBits() == 1 &&
5297 "Can not convert non-constant vector");
5298 uint64_t Immediate = 0;
5299 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5300 SDValue In = Op.getOperand(idx);
5301 if (In.getOpcode() != ISD::UNDEF)
5302 Immediate |= cast<ConstantSDNode>(In)->getZExtValue() << idx;
5306 MVT::getIntegerVT(std::max((int)Op.getValueType().getSizeInBits(), 8));
5307 return DAG.getConstant(Immediate, dl, VT);
5309 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
5311 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
5313 MVT VT = Op.getSimpleValueType();
5314 assert((VT.getVectorElementType() == MVT::i1) &&
5315 "Unexpected type in LowerBUILD_VECTORvXi1!");
5318 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5319 SDValue Cst = DAG.getTargetConstant(0, dl, MVT::i1);
5320 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5321 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5324 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5325 SDValue Cst = DAG.getTargetConstant(1, dl, MVT::i1);
5326 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5327 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5330 if (ISD::isBuildVectorOfConstantSDNodes(Op.getNode())) {
5331 SDValue Imm = ConvertI1VectorToInterger(Op, DAG);
5332 if (Imm.getValueSizeInBits() == VT.getSizeInBits())
5333 return DAG.getBitcast(VT, Imm);
5334 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, Imm);
5335 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec,
5336 DAG.getIntPtrConstant(0, dl));
5339 // Vector has one or more non-const elements
5340 uint64_t Immediate = 0;
5341 SmallVector<unsigned, 16> NonConstIdx;
5342 bool IsSplat = true;
5343 bool HasConstElts = false;
5345 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5346 SDValue In = Op.getOperand(idx);
5347 if (In.getOpcode() == ISD::UNDEF)
5349 if (!isa<ConstantSDNode>(In))
5350 NonConstIdx.push_back(idx);
5352 Immediate |= cast<ConstantSDNode>(In)->getZExtValue() << idx;
5353 HasConstElts = true;
5357 else if (In != Op.getOperand(SplatIdx))
5361 // for splat use " (select i1 splat_elt, all-ones, all-zeroes)"
5363 return DAG.getNode(ISD::SELECT, dl, VT, Op.getOperand(SplatIdx),
5364 DAG.getConstant(1, dl, VT),
5365 DAG.getConstant(0, dl, VT));
5367 // insert elements one by one
5371 MVT ImmVT = MVT::getIntegerVT(std::max((int)VT.getSizeInBits(), 8));
5372 Imm = DAG.getConstant(Immediate, dl, ImmVT);
5374 else if (HasConstElts)
5375 Imm = DAG.getConstant(0, dl, VT);
5377 Imm = DAG.getUNDEF(VT);
5378 if (Imm.getValueSizeInBits() == VT.getSizeInBits())
5379 DstVec = DAG.getBitcast(VT, Imm);
5381 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, Imm);
5382 DstVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec,
5383 DAG.getIntPtrConstant(0, dl));
5386 for (unsigned i = 0; i < NonConstIdx.size(); ++i) {
5387 unsigned InsertIdx = NonConstIdx[i];
5388 DstVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
5389 Op.getOperand(InsertIdx),
5390 DAG.getIntPtrConstant(InsertIdx, dl));
5395 /// \brief Return true if \p N implements a horizontal binop and return the
5396 /// operands for the horizontal binop into V0 and V1.
5398 /// This is a helper function of LowerToHorizontalOp().
5399 /// This function checks that the build_vector \p N in input implements a
5400 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
5401 /// operation to match.
5402 /// For example, if \p Opcode is equal to ISD::ADD, then this function
5403 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
5404 /// is equal to ISD::SUB, then this function checks if this is a horizontal
5407 /// This function only analyzes elements of \p N whose indices are
5408 /// in range [BaseIdx, LastIdx).
5409 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
5411 unsigned BaseIdx, unsigned LastIdx,
5412 SDValue &V0, SDValue &V1) {
5413 EVT VT = N->getValueType(0);
5415 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
5416 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
5417 "Invalid Vector in input!");
5419 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
5420 bool CanFold = true;
5421 unsigned ExpectedVExtractIdx = BaseIdx;
5422 unsigned NumElts = LastIdx - BaseIdx;
5423 V0 = DAG.getUNDEF(VT);
5424 V1 = DAG.getUNDEF(VT);
5426 // Check if N implements a horizontal binop.
5427 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
5428 SDValue Op = N->getOperand(i + BaseIdx);
5431 if (Op->getOpcode() == ISD::UNDEF) {
5432 // Update the expected vector extract index.
5433 if (i * 2 == NumElts)
5434 ExpectedVExtractIdx = BaseIdx;
5435 ExpectedVExtractIdx += 2;
5439 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
5444 SDValue Op0 = Op.getOperand(0);
5445 SDValue Op1 = Op.getOperand(1);
5447 // Try to match the following pattern:
5448 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
5449 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5450 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5451 Op0.getOperand(0) == Op1.getOperand(0) &&
5452 isa<ConstantSDNode>(Op0.getOperand(1)) &&
5453 isa<ConstantSDNode>(Op1.getOperand(1)));
5457 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
5458 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
5460 if (i * 2 < NumElts) {
5461 if (V0.getOpcode() == ISD::UNDEF) {
5462 V0 = Op0.getOperand(0);
5463 if (V0.getValueType() != VT)
5467 if (V1.getOpcode() == ISD::UNDEF) {
5468 V1 = Op0.getOperand(0);
5469 if (V1.getValueType() != VT)
5472 if (i * 2 == NumElts)
5473 ExpectedVExtractIdx = BaseIdx;
5476 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
5477 if (I0 == ExpectedVExtractIdx)
5478 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
5479 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
5480 // Try to match the following dag sequence:
5481 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
5482 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
5486 ExpectedVExtractIdx += 2;
5492 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
5493 /// a concat_vector.
5495 /// This is a helper function of LowerToHorizontalOp().
5496 /// This function expects two 256-bit vectors called V0 and V1.
5497 /// At first, each vector is split into two separate 128-bit vectors.
5498 /// Then, the resulting 128-bit vectors are used to implement two
5499 /// horizontal binary operations.
5501 /// The kind of horizontal binary operation is defined by \p X86Opcode.
5503 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
5504 /// the two new horizontal binop.
5505 /// When Mode is set, the first horizontal binop dag node would take as input
5506 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
5507 /// horizontal binop dag node would take as input the lower 128-bit of V1
5508 /// and the upper 128-bit of V1.
5510 /// HADD V0_LO, V0_HI
5511 /// HADD V1_LO, V1_HI
5513 /// Otherwise, the first horizontal binop dag node takes as input the lower
5514 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
5515 /// dag node takes the upper 128-bit of V0 and the upper 128-bit of V1.
5517 /// HADD V0_LO, V1_LO
5518 /// HADD V0_HI, V1_HI
5520 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
5521 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
5522 /// the upper 128-bits of the result.
5523 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
5524 SDLoc DL, SelectionDAG &DAG,
5525 unsigned X86Opcode, bool Mode,
5526 bool isUndefLO, bool isUndefHI) {
5527 EVT VT = V0.getValueType();
5528 assert(VT.is256BitVector() && VT == V1.getValueType() &&
5529 "Invalid nodes in input!");
5531 unsigned NumElts = VT.getVectorNumElements();
5532 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
5533 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
5534 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
5535 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
5536 EVT NewVT = V0_LO.getValueType();
5538 SDValue LO = DAG.getUNDEF(NewVT);
5539 SDValue HI = DAG.getUNDEF(NewVT);
5542 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5543 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
5544 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
5545 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
5546 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
5548 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5549 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
5550 V1_LO->getOpcode() != ISD::UNDEF))
5551 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
5553 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
5554 V1_HI->getOpcode() != ISD::UNDEF))
5555 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
5558 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
5561 /// Try to fold a build_vector that performs an 'addsub' to an X86ISD::ADDSUB
5563 static SDValue LowerToAddSub(const BuildVectorSDNode *BV,
5564 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
5565 EVT VT = BV->getValueType(0);
5566 if ((!Subtarget->hasSSE3() || (VT != MVT::v4f32 && VT != MVT::v2f64)) &&
5567 (!Subtarget->hasAVX() || (VT != MVT::v8f32 && VT != MVT::v4f64)))
5571 unsigned NumElts = VT.getVectorNumElements();
5572 SDValue InVec0 = DAG.getUNDEF(VT);
5573 SDValue InVec1 = DAG.getUNDEF(VT);
5575 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
5576 VT == MVT::v2f64) && "build_vector with an invalid type found!");
5578 // Odd-numbered elements in the input build vector are obtained from
5579 // adding two integer/float elements.
5580 // Even-numbered elements in the input build vector are obtained from
5581 // subtracting two integer/float elements.
5582 unsigned ExpectedOpcode = ISD::FSUB;
5583 unsigned NextExpectedOpcode = ISD::FADD;
5584 bool AddFound = false;
5585 bool SubFound = false;
5587 for (unsigned i = 0, e = NumElts; i != e; ++i) {
5588 SDValue Op = BV->getOperand(i);
5590 // Skip 'undef' values.
5591 unsigned Opcode = Op.getOpcode();
5592 if (Opcode == ISD::UNDEF) {
5593 std::swap(ExpectedOpcode, NextExpectedOpcode);
5597 // Early exit if we found an unexpected opcode.
5598 if (Opcode != ExpectedOpcode)
5601 SDValue Op0 = Op.getOperand(0);
5602 SDValue Op1 = Op.getOperand(1);
5604 // Try to match the following pattern:
5605 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
5606 // Early exit if we cannot match that sequence.
5607 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5608 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5609 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
5610 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
5611 Op0.getOperand(1) != Op1.getOperand(1))
5614 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
5618 // We found a valid add/sub node. Update the information accordingly.
5624 // Update InVec0 and InVec1.
5625 if (InVec0.getOpcode() == ISD::UNDEF) {
5626 InVec0 = Op0.getOperand(0);
5627 if (InVec0.getValueType() != VT)
5630 if (InVec1.getOpcode() == ISD::UNDEF) {
5631 InVec1 = Op1.getOperand(0);
5632 if (InVec1.getValueType() != VT)
5636 // Make sure that operands in input to each add/sub node always
5637 // come from a same pair of vectors.
5638 if (InVec0 != Op0.getOperand(0)) {
5639 if (ExpectedOpcode == ISD::FSUB)
5642 // FADD is commutable. Try to commute the operands
5643 // and then test again.
5644 std::swap(Op0, Op1);
5645 if (InVec0 != Op0.getOperand(0))
5649 if (InVec1 != Op1.getOperand(0))
5652 // Update the pair of expected opcodes.
5653 std::swap(ExpectedOpcode, NextExpectedOpcode);
5656 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
5657 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
5658 InVec1.getOpcode() != ISD::UNDEF)
5659 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
5664 /// Lower BUILD_VECTOR to a horizontal add/sub operation if possible.
5665 static SDValue LowerToHorizontalOp(const BuildVectorSDNode *BV,
5666 const X86Subtarget *Subtarget,
5667 SelectionDAG &DAG) {
5668 EVT VT = BV->getValueType(0);
5669 unsigned NumElts = VT.getVectorNumElements();
5670 unsigned NumUndefsLO = 0;
5671 unsigned NumUndefsHI = 0;
5672 unsigned Half = NumElts/2;
5674 // Count the number of UNDEF operands in the build_vector in input.
5675 for (unsigned i = 0, e = Half; i != e; ++i)
5676 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
5679 for (unsigned i = Half, e = NumElts; i != e; ++i)
5680 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
5683 // Early exit if this is either a build_vector of all UNDEFs or all the
5684 // operands but one are UNDEF.
5685 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
5689 SDValue InVec0, InVec1;
5690 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
5691 // Try to match an SSE3 float HADD/HSUB.
5692 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
5693 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
5695 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
5696 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
5697 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
5698 // Try to match an SSSE3 integer HADD/HSUB.
5699 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
5700 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
5702 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
5703 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
5706 if (!Subtarget->hasAVX())
5709 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
5710 // Try to match an AVX horizontal add/sub of packed single/double
5711 // precision floating point values from 256-bit vectors.
5712 SDValue InVec2, InVec3;
5713 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
5714 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
5715 ((InVec0.getOpcode() == ISD::UNDEF ||
5716 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5717 ((InVec1.getOpcode() == ISD::UNDEF ||
5718 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5719 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
5721 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
5722 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
5723 ((InVec0.getOpcode() == ISD::UNDEF ||
5724 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5725 ((InVec1.getOpcode() == ISD::UNDEF ||
5726 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5727 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
5728 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
5729 // Try to match an AVX2 horizontal add/sub of signed integers.
5730 SDValue InVec2, InVec3;
5732 bool CanFold = true;
5734 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
5735 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
5736 ((InVec0.getOpcode() == ISD::UNDEF ||
5737 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5738 ((InVec1.getOpcode() == ISD::UNDEF ||
5739 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5740 X86Opcode = X86ISD::HADD;
5741 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
5742 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
5743 ((InVec0.getOpcode() == ISD::UNDEF ||
5744 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5745 ((InVec1.getOpcode() == ISD::UNDEF ||
5746 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5747 X86Opcode = X86ISD::HSUB;
5752 // Fold this build_vector into a single horizontal add/sub.
5753 // Do this only if the target has AVX2.
5754 if (Subtarget->hasAVX2())
5755 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
5757 // Do not try to expand this build_vector into a pair of horizontal
5758 // add/sub if we can emit a pair of scalar add/sub.
5759 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
5762 // Convert this build_vector into a pair of horizontal binop followed by
5764 bool isUndefLO = NumUndefsLO == Half;
5765 bool isUndefHI = NumUndefsHI == Half;
5766 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
5767 isUndefLO, isUndefHI);
5771 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
5772 VT == MVT::v16i16) && Subtarget->hasAVX()) {
5774 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
5775 X86Opcode = X86ISD::HADD;
5776 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
5777 X86Opcode = X86ISD::HSUB;
5778 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
5779 X86Opcode = X86ISD::FHADD;
5780 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
5781 X86Opcode = X86ISD::FHSUB;
5785 // Don't try to expand this build_vector into a pair of horizontal add/sub
5786 // if we can simply emit a pair of scalar add/sub.
5787 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
5790 // Convert this build_vector into two horizontal add/sub followed by
5792 bool isUndefLO = NumUndefsLO == Half;
5793 bool isUndefHI = NumUndefsHI == Half;
5794 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
5795 isUndefLO, isUndefHI);
5802 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5805 MVT VT = Op.getSimpleValueType();
5806 MVT ExtVT = VT.getVectorElementType();
5807 unsigned NumElems = Op.getNumOperands();
5809 // Generate vectors for predicate vectors.
5810 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
5811 return LowerBUILD_VECTORvXi1(Op, DAG);
5813 // Vectors containing all zeros can be matched by pxor and xorps later
5814 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5815 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
5816 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
5817 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
5820 return getZeroVector(VT, Subtarget, DAG, dl);
5823 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
5824 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
5825 // vpcmpeqd on 256-bit vectors.
5826 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
5827 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
5830 if (!VT.is512BitVector())
5831 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
5834 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(Op.getNode());
5835 if (SDValue AddSub = LowerToAddSub(BV, Subtarget, DAG))
5837 if (SDValue HorizontalOp = LowerToHorizontalOp(BV, Subtarget, DAG))
5838 return HorizontalOp;
5839 if (SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG))
5842 unsigned EVTBits = ExtVT.getSizeInBits();
5844 unsigned NumZero = 0;
5845 unsigned NumNonZero = 0;
5846 unsigned NonZeros = 0;
5847 bool IsAllConstants = true;
5848 SmallSet<SDValue, 8> Values;
5849 for (unsigned i = 0; i < NumElems; ++i) {
5850 SDValue Elt = Op.getOperand(i);
5851 if (Elt.getOpcode() == ISD::UNDEF)
5854 if (Elt.getOpcode() != ISD::Constant &&
5855 Elt.getOpcode() != ISD::ConstantFP)
5856 IsAllConstants = false;
5857 if (X86::isZeroNode(Elt))
5860 NonZeros |= (1 << i);
5865 // All undef vector. Return an UNDEF. All zero vectors were handled above.
5866 if (NumNonZero == 0)
5867 return DAG.getUNDEF(VT);
5869 // Special case for single non-zero, non-undef, element.
5870 if (NumNonZero == 1) {
5871 unsigned Idx = countTrailingZeros(NonZeros);
5872 SDValue Item = Op.getOperand(Idx);
5874 // If this is an insertion of an i64 value on x86-32, and if the top bits of
5875 // the value are obviously zero, truncate the value to i32 and do the
5876 // insertion that way. Only do this if the value is non-constant or if the
5877 // value is a constant being inserted into element 0. It is cheaper to do
5878 // a constant pool load than it is to do a movd + shuffle.
5879 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5880 (!IsAllConstants || Idx == 0)) {
5881 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
5883 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5884 EVT VecVT = MVT::v4i32;
5886 // Truncate the value (which may itself be a constant) to i32, and
5887 // convert it to a vector with movd (S2V+shuffle to zero extend).
5888 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5889 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5890 return DAG.getBitcast(VT, getShuffleVectorZeroOrUndef(
5891 Item, Idx * 2, true, Subtarget, DAG));
5895 // If we have a constant or non-constant insertion into the low element of
5896 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5897 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5898 // depending on what the source datatype is.
5901 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5903 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5904 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5905 if (VT.is512BitVector()) {
5906 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
5907 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
5908 Item, DAG.getIntPtrConstant(0, dl));
5910 assert((VT.is128BitVector() || VT.is256BitVector()) &&
5911 "Expected an SSE value type!");
5912 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5913 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
5914 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5917 // We can't directly insert an i8 or i16 into a vector, so zero extend
5919 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
5920 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5921 if (VT.is256BitVector()) {
5922 if (Subtarget->hasAVX()) {
5923 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v8i32, Item);
5924 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5926 // Without AVX, we need to extend to a 128-bit vector and then
5927 // insert into the 256-bit vector.
5928 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5929 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
5930 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
5933 assert(VT.is128BitVector() && "Expected an SSE value type!");
5934 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5935 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5937 return DAG.getBitcast(VT, Item);
5941 // Is it a vector logical left shift?
5942 if (NumElems == 2 && Idx == 1 &&
5943 X86::isZeroNode(Op.getOperand(0)) &&
5944 !X86::isZeroNode(Op.getOperand(1))) {
5945 unsigned NumBits = VT.getSizeInBits();
5946 return getVShift(true, VT,
5947 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5948 VT, Op.getOperand(1)),
5949 NumBits/2, DAG, *this, dl);
5952 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
5955 // Otherwise, if this is a vector with i32 or f32 elements, and the element
5956 // is a non-constant being inserted into an element other than the low one,
5957 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
5958 // movd/movss) to move this into the low element, then shuffle it into
5960 if (EVTBits == 32) {
5961 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5962 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
5966 // Splat is obviously ok. Let legalizer expand it to a shuffle.
5967 if (Values.size() == 1) {
5968 if (EVTBits == 32) {
5969 // Instead of a shuffle like this:
5970 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
5971 // Check if it's possible to issue this instead.
5972 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
5973 unsigned Idx = countTrailingZeros(NonZeros);
5974 SDValue Item = Op.getOperand(Idx);
5975 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
5976 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
5981 // A vector full of immediates; various special cases are already
5982 // handled, so this is best done with a single constant-pool load.
5986 // For AVX-length vectors, see if we can use a vector load to get all of the
5987 // elements, otherwise build the individual 128-bit pieces and use
5988 // shuffles to put them in place.
5989 if (VT.is256BitVector() || VT.is512BitVector()) {
5990 SmallVector<SDValue, 64> V(Op->op_begin(), Op->op_begin() + NumElems);
5992 // Check for a build vector of consecutive loads.
5993 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
5996 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
5998 // Build both the lower and upper subvector.
5999 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6000 makeArrayRef(&V[0], NumElems/2));
6001 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6002 makeArrayRef(&V[NumElems / 2], NumElems/2));
6004 // Recreate the wider vector with the lower and upper part.
6005 if (VT.is256BitVector())
6006 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6007 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6010 // Let legalizer expand 2-wide build_vectors.
6011 if (EVTBits == 64) {
6012 if (NumNonZero == 1) {
6013 // One half is zero or undef.
6014 unsigned Idx = countTrailingZeros(NonZeros);
6015 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6016 Op.getOperand(Idx));
6017 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6022 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6023 if (EVTBits == 8 && NumElems == 16)
6024 if (SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
6028 if (EVTBits == 16 && NumElems == 8)
6029 if (SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
6033 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
6034 if (EVTBits == 32 && NumElems == 4)
6035 if (SDValue V = LowerBuildVectorv4x32(Op, DAG, Subtarget, *this))
6038 // If element VT is == 32 bits, turn it into a number of shuffles.
6039 SmallVector<SDValue, 8> V(NumElems);
6040 if (NumElems == 4 && NumZero > 0) {
6041 for (unsigned i = 0; i < 4; ++i) {
6042 bool isZero = !(NonZeros & (1 << i));
6044 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
6046 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6049 for (unsigned i = 0; i < 2; ++i) {
6050 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
6053 V[i] = V[i*2]; // Must be a zero vector.
6056 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
6059 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
6062 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
6067 bool Reverse1 = (NonZeros & 0x3) == 2;
6068 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
6072 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
6073 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
6075 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
6078 if (Values.size() > 1 && VT.is128BitVector()) {
6079 // Check for a build vector of consecutive loads.
6080 for (unsigned i = 0; i < NumElems; ++i)
6081 V[i] = Op.getOperand(i);
6083 // Check for elements which are consecutive loads.
6084 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
6087 // Check for a build vector from mostly shuffle plus few inserting.
6088 if (SDValue Sh = buildFromShuffleMostly(Op, DAG))
6091 // For SSE 4.1, use insertps to put the high elements into the low element.
6092 if (Subtarget->hasSSE41()) {
6094 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
6095 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
6097 Result = DAG.getUNDEF(VT);
6099 for (unsigned i = 1; i < NumElems; ++i) {
6100 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
6101 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
6102 Op.getOperand(i), DAG.getIntPtrConstant(i, dl));
6107 // Otherwise, expand into a number of unpckl*, start by extending each of
6108 // our (non-undef) elements to the full vector width with the element in the
6109 // bottom slot of the vector (which generates no code for SSE).
6110 for (unsigned i = 0; i < NumElems; ++i) {
6111 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
6112 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6114 V[i] = DAG.getUNDEF(VT);
6117 // Next, we iteratively mix elements, e.g. for v4f32:
6118 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
6119 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
6120 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
6121 unsigned EltStride = NumElems >> 1;
6122 while (EltStride != 0) {
6123 for (unsigned i = 0; i < EltStride; ++i) {
6124 // If V[i+EltStride] is undef and this is the first round of mixing,
6125 // then it is safe to just drop this shuffle: V[i] is already in the
6126 // right place, the one element (since it's the first round) being
6127 // inserted as undef can be dropped. This isn't safe for successive
6128 // rounds because they will permute elements within both vectors.
6129 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
6130 EltStride == NumElems/2)
6133 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
6142 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
6143 // to create 256-bit vectors from two other 128-bit ones.
6144 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6146 MVT ResVT = Op.getSimpleValueType();
6148 assert((ResVT.is256BitVector() ||
6149 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
6151 SDValue V1 = Op.getOperand(0);
6152 SDValue V2 = Op.getOperand(1);
6153 unsigned NumElems = ResVT.getVectorNumElements();
6154 if (ResVT.is256BitVector())
6155 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6157 if (Op.getNumOperands() == 4) {
6158 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
6159 ResVT.getVectorNumElements()/2);
6160 SDValue V3 = Op.getOperand(2);
6161 SDValue V4 = Op.getOperand(3);
6162 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
6163 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
6165 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6168 static SDValue LowerCONCAT_VECTORSvXi1(SDValue Op,
6169 const X86Subtarget *Subtarget,
6170 SelectionDAG & DAG) {
6172 MVT ResVT = Op.getSimpleValueType();
6173 unsigned NumOfOperands = Op.getNumOperands();
6175 assert(isPowerOf2_32(NumOfOperands) &&
6176 "Unexpected number of operands in CONCAT_VECTORS");
6178 if (NumOfOperands > 2) {
6179 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
6180 ResVT.getVectorNumElements()/2);
6181 SmallVector<SDValue, 2> Ops;
6182 for (unsigned i = 0; i < NumOfOperands/2; i++)
6183 Ops.push_back(Op.getOperand(i));
6184 SDValue Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6186 for (unsigned i = NumOfOperands/2; i < NumOfOperands; i++)
6187 Ops.push_back(Op.getOperand(i));
6188 SDValue Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6189 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
6192 SDValue V1 = Op.getOperand(0);
6193 SDValue V2 = Op.getOperand(1);
6194 bool IsZeroV1 = ISD::isBuildVectorAllZeros(V1.getNode());
6195 bool IsZeroV2 = ISD::isBuildVectorAllZeros(V2.getNode());
6197 if (IsZeroV1 && IsZeroV2)
6198 return getZeroVector(ResVT, Subtarget, DAG, dl);
6200 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
6201 SDValue Undef = DAG.getUNDEF(ResVT);
6202 unsigned NumElems = ResVT.getVectorNumElements();
6203 SDValue ShiftBits = DAG.getConstant(NumElems/2, dl, MVT::i8);
6205 V2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V2, ZeroIdx);
6206 V2 = DAG.getNode(X86ISD::VSHLI, dl, ResVT, V2, ShiftBits);
6210 V1 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V1, ZeroIdx);
6211 // Zero the upper bits of V1
6212 V1 = DAG.getNode(X86ISD::VSHLI, dl, ResVT, V1, ShiftBits);
6213 V1 = DAG.getNode(X86ISD::VSRLI, dl, ResVT, V1, ShiftBits);
6216 return DAG.getNode(ISD::OR, dl, ResVT, V1, V2);
6219 static SDValue LowerCONCAT_VECTORS(SDValue Op,
6220 const X86Subtarget *Subtarget,
6221 SelectionDAG &DAG) {
6222 MVT VT = Op.getSimpleValueType();
6223 if (VT.getVectorElementType() == MVT::i1)
6224 return LowerCONCAT_VECTORSvXi1(Op, Subtarget, DAG);
6226 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
6227 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
6228 Op.getNumOperands() == 4)));
6230 // AVX can use the vinsertf128 instruction to create 256-bit vectors
6231 // from two other 128-bit ones.
6233 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
6234 return LowerAVXCONCAT_VECTORS(Op, DAG);
6238 //===----------------------------------------------------------------------===//
6239 // Vector shuffle lowering
6241 // This is an experimental code path for lowering vector shuffles on x86. It is
6242 // designed to handle arbitrary vector shuffles and blends, gracefully
6243 // degrading performance as necessary. It works hard to recognize idiomatic
6244 // shuffles and lower them to optimal instruction patterns without leaving
6245 // a framework that allows reasonably efficient handling of all vector shuffle
6247 //===----------------------------------------------------------------------===//
6249 /// \brief Tiny helper function to identify a no-op mask.
6251 /// This is a somewhat boring predicate function. It checks whether the mask
6252 /// array input, which is assumed to be a single-input shuffle mask of the kind
6253 /// used by the X86 shuffle instructions (not a fully general
6254 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
6255 /// in-place shuffle are 'no-op's.
6256 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
6257 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6258 if (Mask[i] != -1 && Mask[i] != i)
6263 /// \brief Helper function to classify a mask as a single-input mask.
6265 /// This isn't a generic single-input test because in the vector shuffle
6266 /// lowering we canonicalize single inputs to be the first input operand. This
6267 /// means we can more quickly test for a single input by only checking whether
6268 /// an input from the second operand exists. We also assume that the size of
6269 /// mask corresponds to the size of the input vectors which isn't true in the
6270 /// fully general case.
6271 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
6273 if (M >= (int)Mask.size())
6278 /// \brief Test whether there are elements crossing 128-bit lanes in this
6281 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
6282 /// and we routinely test for these.
6283 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
6284 int LaneSize = 128 / VT.getScalarSizeInBits();
6285 int Size = Mask.size();
6286 for (int i = 0; i < Size; ++i)
6287 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
6292 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
6294 /// This checks a shuffle mask to see if it is performing the same
6295 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
6296 /// that it is also not lane-crossing. It may however involve a blend from the
6297 /// same lane of a second vector.
6299 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
6300 /// non-trivial to compute in the face of undef lanes. The representation is
6301 /// *not* suitable for use with existing 128-bit shuffles as it will contain
6302 /// entries from both V1 and V2 inputs to the wider mask.
6304 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
6305 SmallVectorImpl<int> &RepeatedMask) {
6306 int LaneSize = 128 / VT.getScalarSizeInBits();
6307 RepeatedMask.resize(LaneSize, -1);
6308 int Size = Mask.size();
6309 for (int i = 0; i < Size; ++i) {
6312 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
6313 // This entry crosses lanes, so there is no way to model this shuffle.
6316 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
6317 if (RepeatedMask[i % LaneSize] == -1)
6318 // This is the first non-undef entry in this slot of a 128-bit lane.
6319 RepeatedMask[i % LaneSize] =
6320 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
6321 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
6322 // Found a mismatch with the repeated mask.
6328 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
6331 /// This is a fast way to test a shuffle mask against a fixed pattern:
6333 /// if (isShuffleEquivalent(Mask, 3, 2, {1, 0})) { ... }
6335 /// It returns true if the mask is exactly as wide as the argument list, and
6336 /// each element of the mask is either -1 (signifying undef) or the value given
6337 /// in the argument.
6338 static bool isShuffleEquivalent(SDValue V1, SDValue V2, ArrayRef<int> Mask,
6339 ArrayRef<int> ExpectedMask) {
6340 if (Mask.size() != ExpectedMask.size())
6343 int Size = Mask.size();
6345 // If the values are build vectors, we can look through them to find
6346 // equivalent inputs that make the shuffles equivalent.
6347 auto *BV1 = dyn_cast<BuildVectorSDNode>(V1);
6348 auto *BV2 = dyn_cast<BuildVectorSDNode>(V2);
6350 for (int i = 0; i < Size; ++i)
6351 if (Mask[i] != -1 && Mask[i] != ExpectedMask[i]) {
6352 auto *MaskBV = Mask[i] < Size ? BV1 : BV2;
6353 auto *ExpectedBV = ExpectedMask[i] < Size ? BV1 : BV2;
6354 if (!MaskBV || !ExpectedBV ||
6355 MaskBV->getOperand(Mask[i] % Size) !=
6356 ExpectedBV->getOperand(ExpectedMask[i] % Size))
6363 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
6365 /// This helper function produces an 8-bit shuffle immediate corresponding to
6366 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
6367 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
6370 /// NB: We rely heavily on "undef" masks preserving the input lane.
6371 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask, SDLoc DL,
6372 SelectionDAG &DAG) {
6373 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
6374 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
6375 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
6376 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
6377 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
6380 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
6381 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
6382 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
6383 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
6384 return DAG.getConstant(Imm, DL, MVT::i8);
6387 /// \brief Try to emit a blend instruction for a shuffle using bit math.
6389 /// This is used as a fallback approach when first class blend instructions are
6390 /// unavailable. Currently it is only suitable for integer vectors, but could
6391 /// be generalized for floating point vectors if desirable.
6392 static SDValue lowerVectorShuffleAsBitBlend(SDLoc DL, MVT VT, SDValue V1,
6393 SDValue V2, ArrayRef<int> Mask,
6394 SelectionDAG &DAG) {
6395 assert(VT.isInteger() && "Only supports integer vector types!");
6396 MVT EltVT = VT.getScalarType();
6397 int NumEltBits = EltVT.getSizeInBits();
6398 SDValue Zero = DAG.getConstant(0, DL, EltVT);
6399 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
6401 SmallVector<SDValue, 16> MaskOps;
6402 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6403 if (Mask[i] != -1 && Mask[i] != i && Mask[i] != i + Size)
6404 return SDValue(); // Shuffled input!
6405 MaskOps.push_back(Mask[i] < Size ? AllOnes : Zero);
6408 SDValue V1Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, MaskOps);
6409 V1 = DAG.getNode(ISD::AND, DL, VT, V1, V1Mask);
6410 // We have to cast V2 around.
6411 MVT MaskVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
6412 V2 = DAG.getBitcast(VT, DAG.getNode(X86ISD::ANDNP, DL, MaskVT,
6413 DAG.getBitcast(MaskVT, V1Mask),
6414 DAG.getBitcast(MaskVT, V2)));
6415 return DAG.getNode(ISD::OR, DL, VT, V1, V2);
6418 /// \brief Try to emit a blend instruction for a shuffle.
6420 /// This doesn't do any checks for the availability of instructions for blending
6421 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
6422 /// be matched in the backend with the type given. What it does check for is
6423 /// that the shuffle mask is in fact a blend.
6424 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
6425 SDValue V2, ArrayRef<int> Mask,
6426 const X86Subtarget *Subtarget,
6427 SelectionDAG &DAG) {
6428 unsigned BlendMask = 0;
6429 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6430 if (Mask[i] >= Size) {
6431 if (Mask[i] != i + Size)
6432 return SDValue(); // Shuffled V2 input!
6433 BlendMask |= 1u << i;
6436 if (Mask[i] >= 0 && Mask[i] != i)
6437 return SDValue(); // Shuffled V1 input!
6439 switch (VT.SimpleTy) {
6444 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
6445 DAG.getConstant(BlendMask, DL, MVT::i8));
6449 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
6453 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
6454 // that instruction.
6455 if (Subtarget->hasAVX2()) {
6456 // Scale the blend by the number of 32-bit dwords per element.
6457 int Scale = VT.getScalarSizeInBits() / 32;
6459 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6460 if (Mask[i] >= Size)
6461 for (int j = 0; j < Scale; ++j)
6462 BlendMask |= 1u << (i * Scale + j);
6464 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
6465 V1 = DAG.getBitcast(BlendVT, V1);
6466 V2 = DAG.getBitcast(BlendVT, V2);
6467 return DAG.getBitcast(
6468 VT, DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
6469 DAG.getConstant(BlendMask, DL, MVT::i8)));
6473 // For integer shuffles we need to expand the mask and cast the inputs to
6474 // v8i16s prior to blending.
6475 int Scale = 8 / VT.getVectorNumElements();
6477 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6478 if (Mask[i] >= Size)
6479 for (int j = 0; j < Scale; ++j)
6480 BlendMask |= 1u << (i * Scale + j);
6482 V1 = DAG.getBitcast(MVT::v8i16, V1);
6483 V2 = DAG.getBitcast(MVT::v8i16, V2);
6484 return DAG.getBitcast(VT,
6485 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
6486 DAG.getConstant(BlendMask, DL, MVT::i8)));
6490 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
6491 SmallVector<int, 8> RepeatedMask;
6492 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
6493 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
6494 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
6496 for (int i = 0; i < 8; ++i)
6497 if (RepeatedMask[i] >= 16)
6498 BlendMask |= 1u << i;
6499 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
6500 DAG.getConstant(BlendMask, DL, MVT::i8));
6506 assert((VT.getSizeInBits() == 128 || Subtarget->hasAVX2()) &&
6507 "256-bit byte-blends require AVX2 support!");
6509 // Scale the blend by the number of bytes per element.
6510 int Scale = VT.getScalarSizeInBits() / 8;
6512 // This form of blend is always done on bytes. Compute the byte vector
6514 MVT BlendVT = MVT::getVectorVT(MVT::i8, VT.getSizeInBits() / 8);
6516 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
6517 // mix of LLVM's code generator and the x86 backend. We tell the code
6518 // generator that boolean values in the elements of an x86 vector register
6519 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
6520 // mapping a select to operand #1, and 'false' mapping to operand #2. The
6521 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
6522 // of the element (the remaining are ignored) and 0 in that high bit would
6523 // mean operand #1 while 1 in the high bit would mean operand #2. So while
6524 // the LLVM model for boolean values in vector elements gets the relevant
6525 // bit set, it is set backwards and over constrained relative to x86's
6527 SmallVector<SDValue, 32> VSELECTMask;
6528 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6529 for (int j = 0; j < Scale; ++j)
6530 VSELECTMask.push_back(
6531 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
6532 : DAG.getConstant(Mask[i] < Size ? -1 : 0, DL,
6535 V1 = DAG.getBitcast(BlendVT, V1);
6536 V2 = DAG.getBitcast(BlendVT, V2);
6537 return DAG.getBitcast(VT, DAG.getNode(ISD::VSELECT, DL, BlendVT,
6538 DAG.getNode(ISD::BUILD_VECTOR, DL,
6539 BlendVT, VSELECTMask),
6544 llvm_unreachable("Not a supported integer vector type!");
6548 /// \brief Try to lower as a blend of elements from two inputs followed by
6549 /// a single-input permutation.
6551 /// This matches the pattern where we can blend elements from two inputs and
6552 /// then reduce the shuffle to a single-input permutation.
6553 static SDValue lowerVectorShuffleAsBlendAndPermute(SDLoc DL, MVT VT, SDValue V1,
6556 SelectionDAG &DAG) {
6557 // We build up the blend mask while checking whether a blend is a viable way
6558 // to reduce the shuffle.
6559 SmallVector<int, 32> BlendMask(Mask.size(), -1);
6560 SmallVector<int, 32> PermuteMask(Mask.size(), -1);
6562 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6566 assert(Mask[i] < Size * 2 && "Shuffle input is out of bounds.");
6568 if (BlendMask[Mask[i] % Size] == -1)
6569 BlendMask[Mask[i] % Size] = Mask[i];
6570 else if (BlendMask[Mask[i] % Size] != Mask[i])
6571 return SDValue(); // Can't blend in the needed input!
6573 PermuteMask[i] = Mask[i] % Size;
6576 SDValue V = DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
6577 return DAG.getVectorShuffle(VT, DL, V, DAG.getUNDEF(VT), PermuteMask);
6580 /// \brief Generic routine to decompose a shuffle and blend into indepndent
6581 /// blends and permutes.
6583 /// This matches the extremely common pattern for handling combined
6584 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
6585 /// operations. It will try to pick the best arrangement of shuffles and
6587 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
6591 SelectionDAG &DAG) {
6592 // Shuffle the input elements into the desired positions in V1 and V2 and
6593 // blend them together.
6594 SmallVector<int, 32> V1Mask(Mask.size(), -1);
6595 SmallVector<int, 32> V2Mask(Mask.size(), -1);
6596 SmallVector<int, 32> BlendMask(Mask.size(), -1);
6597 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6598 if (Mask[i] >= 0 && Mask[i] < Size) {
6599 V1Mask[i] = Mask[i];
6601 } else if (Mask[i] >= Size) {
6602 V2Mask[i] = Mask[i] - Size;
6603 BlendMask[i] = i + Size;
6606 // Try to lower with the simpler initial blend strategy unless one of the
6607 // input shuffles would be a no-op. We prefer to shuffle inputs as the
6608 // shuffle may be able to fold with a load or other benefit. However, when
6609 // we'll have to do 2x as many shuffles in order to achieve this, blending
6610 // first is a better strategy.
6611 if (!isNoopShuffleMask(V1Mask) && !isNoopShuffleMask(V2Mask))
6612 if (SDValue BlendPerm =
6613 lowerVectorShuffleAsBlendAndPermute(DL, VT, V1, V2, Mask, DAG))
6616 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
6617 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
6618 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
6621 /// \brief Try to lower a vector shuffle as a byte rotation.
6623 /// SSSE3 has a generic PALIGNR instruction in x86 that will do an arbitrary
6624 /// byte-rotation of the concatenation of two vectors; pre-SSSE3 can use
6625 /// a PSRLDQ/PSLLDQ/POR pattern to get a similar effect. This routine will
6626 /// try to generically lower a vector shuffle through such an pattern. It
6627 /// does not check for the profitability of lowering either as PALIGNR or
6628 /// PSRLDQ/PSLLDQ/POR, only whether the mask is valid to lower in that form.
6629 /// This matches shuffle vectors that look like:
6631 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
6633 /// Essentially it concatenates V1 and V2, shifts right by some number of
6634 /// elements, and takes the low elements as the result. Note that while this is
6635 /// specified as a *right shift* because x86 is little-endian, it is a *left
6636 /// rotate* of the vector lanes.
6637 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
6640 const X86Subtarget *Subtarget,
6641 SelectionDAG &DAG) {
6642 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
6644 int NumElts = Mask.size();
6645 int NumLanes = VT.getSizeInBits() / 128;
6646 int NumLaneElts = NumElts / NumLanes;
6648 // We need to detect various ways of spelling a rotation:
6649 // [11, 12, 13, 14, 15, 0, 1, 2]
6650 // [-1, 12, 13, 14, -1, -1, 1, -1]
6651 // [-1, -1, -1, -1, -1, -1, 1, 2]
6652 // [ 3, 4, 5, 6, 7, 8, 9, 10]
6653 // [-1, 4, 5, 6, -1, -1, 9, -1]
6654 // [-1, 4, 5, 6, -1, -1, -1, -1]
6657 for (int l = 0; l < NumElts; l += NumLaneElts) {
6658 for (int i = 0; i < NumLaneElts; ++i) {
6659 if (Mask[l + i] == -1)
6661 assert(Mask[l + i] >= 0 && "Only -1 is a valid negative mask element!");
6663 // Get the mod-Size index and lane correct it.
6664 int LaneIdx = (Mask[l + i] % NumElts) - l;
6665 // Make sure it was in this lane.
6666 if (LaneIdx < 0 || LaneIdx >= NumLaneElts)
6669 // Determine where a rotated vector would have started.
6670 int StartIdx = i - LaneIdx;
6672 // The identity rotation isn't interesting, stop.
6675 // If we found the tail of a vector the rotation must be the missing
6676 // front. If we found the head of a vector, it must be how much of the
6678 int CandidateRotation = StartIdx < 0 ? -StartIdx : NumLaneElts - StartIdx;
6681 Rotation = CandidateRotation;
6682 else if (Rotation != CandidateRotation)
6683 // The rotations don't match, so we can't match this mask.
6686 // Compute which value this mask is pointing at.
6687 SDValue MaskV = Mask[l + i] < NumElts ? V1 : V2;
6689 // Compute which of the two target values this index should be assigned
6690 // to. This reflects whether the high elements are remaining or the low
6691 // elements are remaining.
6692 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
6694 // Either set up this value if we've not encountered it before, or check
6695 // that it remains consistent.
6698 else if (TargetV != MaskV)
6699 // This may be a rotation, but it pulls from the inputs in some
6700 // unsupported interleaving.
6705 // Check that we successfully analyzed the mask, and normalize the results.
6706 assert(Rotation != 0 && "Failed to locate a viable rotation!");
6707 assert((Lo || Hi) && "Failed to find a rotated input vector!");
6713 // The actual rotate instruction rotates bytes, so we need to scale the
6714 // rotation based on how many bytes are in the vector lane.
6715 int Scale = 16 / NumLaneElts;
6717 // SSSE3 targets can use the palignr instruction.
6718 if (Subtarget->hasSSSE3()) {
6719 // Cast the inputs to i8 vector of correct length to match PALIGNR.
6720 MVT AlignVT = MVT::getVectorVT(MVT::i8, 16 * NumLanes);
6721 Lo = DAG.getBitcast(AlignVT, Lo);
6722 Hi = DAG.getBitcast(AlignVT, Hi);
6724 return DAG.getBitcast(
6725 VT, DAG.getNode(X86ISD::PALIGNR, DL, AlignVT, Hi, Lo,
6726 DAG.getConstant(Rotation * Scale, DL, MVT::i8)));
6729 assert(VT.getSizeInBits() == 128 &&
6730 "Rotate-based lowering only supports 128-bit lowering!");
6731 assert(Mask.size() <= 16 &&
6732 "Can shuffle at most 16 bytes in a 128-bit vector!");
6734 // Default SSE2 implementation
6735 int LoByteShift = 16 - Rotation * Scale;
6736 int HiByteShift = Rotation * Scale;
6738 // Cast the inputs to v2i64 to match PSLLDQ/PSRLDQ.
6739 Lo = DAG.getBitcast(MVT::v2i64, Lo);
6740 Hi = DAG.getBitcast(MVT::v2i64, Hi);
6742 SDValue LoShift = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, Lo,
6743 DAG.getConstant(LoByteShift, DL, MVT::i8));
6744 SDValue HiShift = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, Hi,
6745 DAG.getConstant(HiByteShift, DL, MVT::i8));
6746 return DAG.getBitcast(VT,
6747 DAG.getNode(ISD::OR, DL, MVT::v2i64, LoShift, HiShift));
6750 /// \brief Compute whether each element of a shuffle is zeroable.
6752 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
6753 /// Either it is an undef element in the shuffle mask, the element of the input
6754 /// referenced is undef, or the element of the input referenced is known to be
6755 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
6756 /// as many lanes with this technique as possible to simplify the remaining
6758 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
6759 SDValue V1, SDValue V2) {
6760 SmallBitVector Zeroable(Mask.size(), false);
6762 while (V1.getOpcode() == ISD::BITCAST)
6763 V1 = V1->getOperand(0);
6764 while (V2.getOpcode() == ISD::BITCAST)
6765 V2 = V2->getOperand(0);
6767 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
6768 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
6770 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6772 // Handle the easy cases.
6773 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
6778 // If this is an index into a build_vector node (which has the same number
6779 // of elements), dig out the input value and use it.
6780 SDValue V = M < Size ? V1 : V2;
6781 if (V.getOpcode() != ISD::BUILD_VECTOR || Size != (int)V.getNumOperands())
6784 SDValue Input = V.getOperand(M % Size);
6785 // The UNDEF opcode check really should be dead code here, but not quite
6786 // worth asserting on (it isn't invalid, just unexpected).
6787 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
6794 /// \brief Try to emit a bitmask instruction for a shuffle.
6796 /// This handles cases where we can model a blend exactly as a bitmask due to
6797 /// one of the inputs being zeroable.
6798 static SDValue lowerVectorShuffleAsBitMask(SDLoc DL, MVT VT, SDValue V1,
6799 SDValue V2, ArrayRef<int> Mask,
6800 SelectionDAG &DAG) {
6801 MVT EltVT = VT.getScalarType();
6802 int NumEltBits = EltVT.getSizeInBits();
6803 MVT IntEltVT = MVT::getIntegerVT(NumEltBits);
6804 SDValue Zero = DAG.getConstant(0, DL, IntEltVT);
6805 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
6807 if (EltVT.isFloatingPoint()) {
6808 Zero = DAG.getBitcast(EltVT, Zero);
6809 AllOnes = DAG.getBitcast(EltVT, AllOnes);
6811 SmallVector<SDValue, 16> VMaskOps(Mask.size(), Zero);
6812 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6814 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6817 if (Mask[i] % Size != i)
6818 return SDValue(); // Not a blend.
6820 V = Mask[i] < Size ? V1 : V2;
6821 else if (V != (Mask[i] < Size ? V1 : V2))
6822 return SDValue(); // Can only let one input through the mask.
6824 VMaskOps[i] = AllOnes;
6827 return SDValue(); // No non-zeroable elements!
6829 SDValue VMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, VMaskOps);
6830 V = DAG.getNode(VT.isFloatingPoint()
6831 ? (unsigned) X86ISD::FAND : (unsigned) ISD::AND,
6836 /// \brief Try to lower a vector shuffle as a bit shift (shifts in zeros).
6838 /// Attempts to match a shuffle mask against the PSLL(W/D/Q/DQ) and
6839 /// PSRL(W/D/Q/DQ) SSE2 and AVX2 logical bit-shift instructions. The function
6840 /// matches elements from one of the input vectors shuffled to the left or
6841 /// right with zeroable elements 'shifted in'. It handles both the strictly
6842 /// bit-wise element shifts and the byte shift across an entire 128-bit double
6845 /// PSHL : (little-endian) left bit shift.
6846 /// [ zz, 0, zz, 2 ]
6847 /// [ -1, 4, zz, -1 ]
6848 /// PSRL : (little-endian) right bit shift.
6850 /// [ -1, -1, 7, zz]
6851 /// PSLLDQ : (little-endian) left byte shift
6852 /// [ zz, 0, 1, 2, 3, 4, 5, 6]
6853 /// [ zz, zz, -1, -1, 2, 3, 4, -1]
6854 /// [ zz, zz, zz, zz, zz, zz, -1, 1]
6855 /// PSRLDQ : (little-endian) right byte shift
6856 /// [ 5, 6, 7, zz, zz, zz, zz, zz]
6857 /// [ -1, 5, 6, 7, zz, zz, zz, zz]
6858 /// [ 1, 2, -1, -1, -1, -1, zz, zz]
6859 static SDValue lowerVectorShuffleAsShift(SDLoc DL, MVT VT, SDValue V1,
6860 SDValue V2, ArrayRef<int> Mask,
6861 SelectionDAG &DAG) {
6862 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6864 int Size = Mask.size();
6865 assert(Size == (int)VT.getVectorNumElements() && "Unexpected mask size");
6867 auto CheckZeros = [&](int Shift, int Scale, bool Left) {
6868 for (int i = 0; i < Size; i += Scale)
6869 for (int j = 0; j < Shift; ++j)
6870 if (!Zeroable[i + j + (Left ? 0 : (Scale - Shift))])
6876 auto MatchShift = [&](int Shift, int Scale, bool Left, SDValue V) {
6877 for (int i = 0; i != Size; i += Scale) {
6878 unsigned Pos = Left ? i + Shift : i;
6879 unsigned Low = Left ? i : i + Shift;
6880 unsigned Len = Scale - Shift;
6881 if (!isSequentialOrUndefInRange(Mask, Pos, Len,
6882 Low + (V == V1 ? 0 : Size)))
6886 int ShiftEltBits = VT.getScalarSizeInBits() * Scale;
6887 bool ByteShift = ShiftEltBits > 64;
6888 unsigned OpCode = Left ? (ByteShift ? X86ISD::VSHLDQ : X86ISD::VSHLI)
6889 : (ByteShift ? X86ISD::VSRLDQ : X86ISD::VSRLI);
6890 int ShiftAmt = Shift * VT.getScalarSizeInBits() / (ByteShift ? 8 : 1);
6892 // Normalize the scale for byte shifts to still produce an i64 element
6894 Scale = ByteShift ? Scale / 2 : Scale;
6896 // We need to round trip through the appropriate type for the shift.
6897 MVT ShiftSVT = MVT::getIntegerVT(VT.getScalarSizeInBits() * Scale);
6898 MVT ShiftVT = MVT::getVectorVT(ShiftSVT, Size / Scale);
6899 assert(DAG.getTargetLoweringInfo().isTypeLegal(ShiftVT) &&
6900 "Illegal integer vector type");
6901 V = DAG.getBitcast(ShiftVT, V);
6903 V = DAG.getNode(OpCode, DL, ShiftVT, V,
6904 DAG.getConstant(ShiftAmt, DL, MVT::i8));
6905 return DAG.getBitcast(VT, V);
6908 // SSE/AVX supports logical shifts up to 64-bit integers - so we can just
6909 // keep doubling the size of the integer elements up to that. We can
6910 // then shift the elements of the integer vector by whole multiples of
6911 // their width within the elements of the larger integer vector. Test each
6912 // multiple to see if we can find a match with the moved element indices
6913 // and that the shifted in elements are all zeroable.
6914 for (int Scale = 2; Scale * VT.getScalarSizeInBits() <= 128; Scale *= 2)
6915 for (int Shift = 1; Shift != Scale; ++Shift)
6916 for (bool Left : {true, false})
6917 if (CheckZeros(Shift, Scale, Left))
6918 for (SDValue V : {V1, V2})
6919 if (SDValue Match = MatchShift(Shift, Scale, Left, V))
6926 /// \brief Try to lower a vector shuffle using SSE4a EXTRQ/INSERTQ.
6927 static SDValue lowerVectorShuffleWithSSE4A(SDLoc DL, MVT VT, SDValue V1,
6928 SDValue V2, ArrayRef<int> Mask,
6929 SelectionDAG &DAG) {
6930 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6931 assert(!Zeroable.all() && "Fully zeroable shuffle mask");
6933 int Size = Mask.size();
6934 int HalfSize = Size / 2;
6935 assert(Size == (int)VT.getVectorNumElements() && "Unexpected mask size");
6937 // Upper half must be undefined.
6938 if (!isUndefInRange(Mask, HalfSize, HalfSize))
6941 // EXTRQ: Extract Len elements from lower half of source, starting at Idx.
6942 // Remainder of lower half result is zero and upper half is all undef.
6943 auto LowerAsEXTRQ = [&]() {
6944 // Determine the extraction length from the part of the
6945 // lower half that isn't zeroable.
6947 for (; Len >= 0; --Len)
6948 if (!Zeroable[Len - 1])
6950 assert(Len > 0 && "Zeroable shuffle mask");
6952 // Attempt to match first Len sequential elements from the lower half.
6955 for (int i = 0; i != Len; ++i) {
6959 SDValue &V = (M < Size ? V1 : V2);
6962 // All mask elements must be in the lower half.
6966 if (Idx < 0 || (Src == V && Idx == (M - i))) {
6977 assert((Idx + Len) <= HalfSize && "Illegal extraction mask");
6978 int BitLen = (Len * VT.getScalarSizeInBits()) & 0x3f;
6979 int BitIdx = (Idx * VT.getScalarSizeInBits()) & 0x3f;
6980 return DAG.getNode(X86ISD::EXTRQI, DL, VT, Src,
6981 DAG.getConstant(BitLen, DL, MVT::i8),
6982 DAG.getConstant(BitIdx, DL, MVT::i8));
6985 if (SDValue ExtrQ = LowerAsEXTRQ())
6988 // INSERTQ: Extract lowest Len elements from lower half of second source and
6989 // insert over first source, starting at Idx.
6990 // { A[0], .., A[Idx-1], B[0], .., B[Len-1], A[Idx+Len], .., UNDEF, ... }
6991 auto LowerAsInsertQ = [&]() {
6992 for (int Idx = 0; Idx != HalfSize; ++Idx) {
6995 // Attempt to match first source from mask before insertion point.
6996 if (isUndefInRange(Mask, 0, Idx)) {
6998 } else if (isSequentialOrUndefInRange(Mask, 0, Idx, 0)) {
7000 } else if (isSequentialOrUndefInRange(Mask, 0, Idx, Size)) {
7006 // Extend the extraction length looking to match both the insertion of
7007 // the second source and the remaining elements of the first.
7008 for (int Hi = Idx + 1; Hi <= HalfSize; ++Hi) {
7013 if (isSequentialOrUndefInRange(Mask, Idx, Len, 0)) {
7015 } else if (isSequentialOrUndefInRange(Mask, Idx, Len, Size)) {
7021 // Match the remaining elements of the lower half.
7022 if (isUndefInRange(Mask, Hi, HalfSize - Hi)) {
7024 } else if ((!Base || (Base == V1)) &&
7025 isSequentialOrUndefInRange(Mask, Hi, HalfSize - Hi, Hi)) {
7027 } else if ((!Base || (Base == V2)) &&
7028 isSequentialOrUndefInRange(Mask, Hi, HalfSize - Hi,
7035 // We may not have a base (first source) - this can safely be undefined.
7037 Base = DAG.getUNDEF(VT);
7039 int BitLen = (Len * VT.getScalarSizeInBits()) & 0x3f;
7040 int BitIdx = (Idx * VT.getScalarSizeInBits()) & 0x3f;
7041 return DAG.getNode(X86ISD::INSERTQI, DL, VT, Base, Insert,
7042 DAG.getConstant(BitLen, DL, MVT::i8),
7043 DAG.getConstant(BitIdx, DL, MVT::i8));
7050 if (SDValue InsertQ = LowerAsInsertQ())
7056 /// \brief Lower a vector shuffle as a zero or any extension.
7058 /// Given a specific number of elements, element bit width, and extension
7059 /// stride, produce either a zero or any extension based on the available
7060 /// features of the subtarget.
7061 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7062 SDLoc DL, MVT VT, int Scale, bool AnyExt, SDValue InputV,
7063 ArrayRef<int> Mask, const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7064 assert(Scale > 1 && "Need a scale to extend.");
7065 int NumElements = VT.getVectorNumElements();
7066 int EltBits = VT.getScalarSizeInBits();
7067 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
7068 "Only 8, 16, and 32 bit elements can be extended.");
7069 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
7071 // Found a valid zext mask! Try various lowering strategies based on the
7072 // input type and available ISA extensions.
7073 if (Subtarget->hasSSE41()) {
7074 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
7075 NumElements / Scale);
7076 return DAG.getBitcast(VT, DAG.getNode(X86ISD::VZEXT, DL, ExtVT, InputV));
7079 // For any extends we can cheat for larger element sizes and use shuffle
7080 // instructions that can fold with a load and/or copy.
7081 if (AnyExt && EltBits == 32) {
7082 int PSHUFDMask[4] = {0, -1, 1, -1};
7083 return DAG.getBitcast(
7084 VT, DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7085 DAG.getBitcast(MVT::v4i32, InputV),
7086 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
7088 if (AnyExt && EltBits == 16 && Scale > 2) {
7089 int PSHUFDMask[4] = {0, -1, 0, -1};
7090 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7091 DAG.getBitcast(MVT::v4i32, InputV),
7092 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG));
7093 int PSHUFHWMask[4] = {1, -1, -1, -1};
7094 return DAG.getBitcast(
7095 VT, DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16,
7096 DAG.getBitcast(MVT::v8i16, InputV),
7097 getV4X86ShuffleImm8ForMask(PSHUFHWMask, DL, DAG)));
7100 // The SSE4A EXTRQ instruction can efficiently extend the first 2 lanes
7102 if ((Scale * EltBits) == 64 && EltBits < 32 && Subtarget->hasSSE4A()) {
7103 assert(NumElements == (int)Mask.size() && "Unexpected shuffle mask size!");
7104 assert(VT.getSizeInBits() == 128 && "Unexpected vector width!");
7106 SDValue Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7107 DAG.getNode(X86ISD::EXTRQI, DL, VT, InputV,
7108 DAG.getConstant(EltBits, DL, MVT::i8),
7109 DAG.getConstant(0, DL, MVT::i8)));
7110 if (isUndefInRange(Mask, NumElements/2, NumElements/2))
7111 return DAG.getNode(ISD::BITCAST, DL, VT, Lo);
7114 DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7115 DAG.getNode(X86ISD::EXTRQI, DL, VT, InputV,
7116 DAG.getConstant(EltBits, DL, MVT::i8),
7117 DAG.getConstant(EltBits, DL, MVT::i8)));
7118 return DAG.getNode(ISD::BITCAST, DL, VT,
7119 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, Lo, Hi));
7122 // If this would require more than 2 unpack instructions to expand, use
7123 // pshufb when available. We can only use more than 2 unpack instructions
7124 // when zero extending i8 elements which also makes it easier to use pshufb.
7125 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
7126 assert(NumElements == 16 && "Unexpected byte vector width!");
7127 SDValue PSHUFBMask[16];
7128 for (int i = 0; i < 16; ++i)
7130 DAG.getConstant((i % Scale == 0) ? i / Scale : 0x80, DL, MVT::i8);
7131 InputV = DAG.getBitcast(MVT::v16i8, InputV);
7132 return DAG.getBitcast(VT,
7133 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
7134 DAG.getNode(ISD::BUILD_VECTOR, DL,
7135 MVT::v16i8, PSHUFBMask)));
7138 // Otherwise emit a sequence of unpacks.
7140 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7141 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
7142 : getZeroVector(InputVT, Subtarget, DAG, DL);
7143 InputV = DAG.getBitcast(InputVT, InputV);
7144 InputV = DAG.getNode(X86ISD::UNPCKL, DL, InputVT, InputV, Ext);
7148 } while (Scale > 1);
7149 return DAG.getBitcast(VT, InputV);
7152 /// \brief Try to lower a vector shuffle as a zero extension on any microarch.
7154 /// This routine will try to do everything in its power to cleverly lower
7155 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
7156 /// check for the profitability of this lowering, it tries to aggressively
7157 /// match this pattern. It will use all of the micro-architectural details it
7158 /// can to emit an efficient lowering. It handles both blends with all-zero
7159 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
7160 /// masking out later).
7162 /// The reason we have dedicated lowering for zext-style shuffles is that they
7163 /// are both incredibly common and often quite performance sensitive.
7164 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
7165 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7166 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7167 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7169 int Bits = VT.getSizeInBits();
7170 int NumElements = VT.getVectorNumElements();
7171 assert(VT.getScalarSizeInBits() <= 32 &&
7172 "Exceeds 32-bit integer zero extension limit");
7173 assert((int)Mask.size() == NumElements && "Unexpected shuffle mask size");
7175 // Define a helper function to check a particular ext-scale and lower to it if
7177 auto Lower = [&](int Scale) -> SDValue {
7180 for (int i = 0; i < NumElements; ++i) {
7182 continue; // Valid anywhere but doesn't tell us anything.
7183 if (i % Scale != 0) {
7184 // Each of the extended elements need to be zeroable.
7188 // We no longer are in the anyext case.
7193 // Each of the base elements needs to be consecutive indices into the
7194 // same input vector.
7195 SDValue V = Mask[i] < NumElements ? V1 : V2;
7198 else if (InputV != V)
7199 return SDValue(); // Flip-flopping inputs.
7201 if (Mask[i] % NumElements != i / Scale)
7202 return SDValue(); // Non-consecutive strided elements.
7205 // If we fail to find an input, we have a zero-shuffle which should always
7206 // have already been handled.
7207 // FIXME: Maybe handle this here in case during blending we end up with one?
7211 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7212 DL, VT, Scale, AnyExt, InputV, Mask, Subtarget, DAG);
7215 // The widest scale possible for extending is to a 64-bit integer.
7216 assert(Bits % 64 == 0 &&
7217 "The number of bits in a vector must be divisible by 64 on x86!");
7218 int NumExtElements = Bits / 64;
7220 // Each iteration, try extending the elements half as much, but into twice as
7222 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7223 assert(NumElements % NumExtElements == 0 &&
7224 "The input vector size must be divisible by the extended size.");
7225 if (SDValue V = Lower(NumElements / NumExtElements))
7229 // General extends failed, but 128-bit vectors may be able to use MOVQ.
7233 // Returns one of the source operands if the shuffle can be reduced to a
7234 // MOVQ, copying the lower 64-bits and zero-extending to the upper 64-bits.
7235 auto CanZExtLowHalf = [&]() {
7236 for (int i = NumElements / 2; i != NumElements; ++i)
7239 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, 0))
7241 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, NumElements))
7246 if (SDValue V = CanZExtLowHalf()) {
7247 V = DAG.getBitcast(MVT::v2i64, V);
7248 V = DAG.getNode(X86ISD::VZEXT_MOVL, DL, MVT::v2i64, V);
7249 return DAG.getBitcast(VT, V);
7252 // No viable ext lowering found.
7256 /// \brief Try to get a scalar value for a specific element of a vector.
7258 /// Looks through BUILD_VECTOR and SCALAR_TO_VECTOR nodes to find a scalar.
7259 static SDValue getScalarValueForVectorElement(SDValue V, int Idx,
7260 SelectionDAG &DAG) {
7261 MVT VT = V.getSimpleValueType();
7262 MVT EltVT = VT.getVectorElementType();
7263 while (V.getOpcode() == ISD::BITCAST)
7264 V = V.getOperand(0);
7265 // If the bitcasts shift the element size, we can't extract an equivalent
7267 MVT NewVT = V.getSimpleValueType();
7268 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
7271 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7272 (Idx == 0 && V.getOpcode() == ISD::SCALAR_TO_VECTOR)) {
7273 // Ensure the scalar operand is the same size as the destination.
7274 // FIXME: Add support for scalar truncation where possible.
7275 SDValue S = V.getOperand(Idx);
7276 if (EltVT.getSizeInBits() == S.getSimpleValueType().getSizeInBits())
7277 return DAG.getNode(ISD::BITCAST, SDLoc(V), EltVT, S);
7283 /// \brief Helper to test for a load that can be folded with x86 shuffles.
7285 /// This is particularly important because the set of instructions varies
7286 /// significantly based on whether the operand is a load or not.
7287 static bool isShuffleFoldableLoad(SDValue V) {
7288 while (V.getOpcode() == ISD::BITCAST)
7289 V = V.getOperand(0);
7291 return ISD::isNON_EXTLoad(V.getNode());
7294 /// \brief Try to lower insertion of a single element into a zero vector.
7296 /// This is a common pattern that we have especially efficient patterns to lower
7297 /// across all subtarget feature sets.
7298 static SDValue lowerVectorShuffleAsElementInsertion(
7299 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7300 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7301 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7303 MVT EltVT = VT.getVectorElementType();
7305 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7306 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7308 bool IsV1Zeroable = true;
7309 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7310 if (i != V2Index && !Zeroable[i]) {
7311 IsV1Zeroable = false;
7315 // Check for a single input from a SCALAR_TO_VECTOR node.
7316 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7317 // all the smarts here sunk into that routine. However, the current
7318 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7319 // vector shuffle lowering is dead.
7320 if (SDValue V2S = getScalarValueForVectorElement(
7321 V2, Mask[V2Index] - Mask.size(), DAG)) {
7322 // We need to zext the scalar if it is smaller than an i32.
7323 V2S = DAG.getBitcast(EltVT, V2S);
7324 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7325 // Using zext to expand a narrow element won't work for non-zero
7330 // Zero-extend directly to i32.
7332 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7334 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);
7335 } else if (Mask[V2Index] != (int)Mask.size() || EltVT == MVT::i8 ||
7336 EltVT == MVT::i16) {
7337 // Either not inserting from the low element of the input or the input
7338 // element size is too small to use VZEXT_MOVL to clear the high bits.
7342 if (!IsV1Zeroable) {
7343 // If V1 can't be treated as a zero vector we have fewer options to lower
7344 // this. We can't support integer vectors or non-zero targets cheaply, and
7345 // the V1 elements can't be permuted in any way.
7346 assert(VT == ExtVT && "Cannot change extended type when non-zeroable!");
7347 if (!VT.isFloatingPoint() || V2Index != 0)
7349 SmallVector<int, 8> V1Mask(Mask.begin(), Mask.end());
7350 V1Mask[V2Index] = -1;
7351 if (!isNoopShuffleMask(V1Mask))
7353 // This is essentially a special case blend operation, but if we have
7354 // general purpose blend operations, they are always faster. Bail and let
7355 // the rest of the lowering handle these as blends.
7356 if (Subtarget->hasSSE41())
7359 // Otherwise, use MOVSD or MOVSS.
7360 assert((EltVT == MVT::f32 || EltVT == MVT::f64) &&
7361 "Only two types of floating point element types to handle!");
7362 return DAG.getNode(EltVT == MVT::f32 ? X86ISD::MOVSS : X86ISD::MOVSD, DL,
7366 // This lowering only works for the low element with floating point vectors.
7367 if (VT.isFloatingPoint() && V2Index != 0)
7370 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2);
7372 V2 = DAG.getBitcast(VT, V2);
7375 // If we have 4 or fewer lanes we can cheaply shuffle the element into
7376 // the desired position. Otherwise it is more efficient to do a vector
7377 // shift left. We know that we can do a vector shift left because all
7378 // the inputs are zero.
7379 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
7380 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
7381 V2Shuffle[V2Index] = 0;
7382 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
7384 V2 = DAG.getBitcast(MVT::v2i64, V2);
7386 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
7388 V2Index * EltVT.getSizeInBits()/8, DL,
7389 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(MVT::v2i64)));
7390 V2 = DAG.getBitcast(VT, V2);
7396 /// \brief Try to lower broadcast of a single element.
7398 /// For convenience, this code also bundles all of the subtarget feature set
7399 /// filtering. While a little annoying to re-dispatch on type here, there isn't
7400 /// a convenient way to factor it out.
7401 static SDValue lowerVectorShuffleAsBroadcast(SDLoc DL, MVT VT, SDValue V,
7403 const X86Subtarget *Subtarget,
7404 SelectionDAG &DAG) {
7405 if (!Subtarget->hasAVX())
7407 if (VT.isInteger() && !Subtarget->hasAVX2())
7410 // Check that the mask is a broadcast.
7411 int BroadcastIdx = -1;
7413 if (M >= 0 && BroadcastIdx == -1)
7415 else if (M >= 0 && M != BroadcastIdx)
7418 assert(BroadcastIdx < (int)Mask.size() && "We only expect to be called with "
7419 "a sorted mask where the broadcast "
7422 // Go up the chain of (vector) values to find a scalar load that we can
7423 // combine with the broadcast.
7425 switch (V.getOpcode()) {
7426 case ISD::CONCAT_VECTORS: {
7427 int OperandSize = Mask.size() / V.getNumOperands();
7428 V = V.getOperand(BroadcastIdx / OperandSize);
7429 BroadcastIdx %= OperandSize;
7433 case ISD::INSERT_SUBVECTOR: {
7434 SDValue VOuter = V.getOperand(0), VInner = V.getOperand(1);
7435 auto ConstantIdx = dyn_cast<ConstantSDNode>(V.getOperand(2));
7439 int BeginIdx = (int)ConstantIdx->getZExtValue();
7441 BeginIdx + (int)VInner.getValueType().getVectorNumElements();
7442 if (BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx) {
7443 BroadcastIdx -= BeginIdx;
7454 // Check if this is a broadcast of a scalar. We special case lowering
7455 // for scalars so that we can more effectively fold with loads.
7456 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7457 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)) {
7458 V = V.getOperand(BroadcastIdx);
7460 // If the scalar isn't a load, we can't broadcast from it in AVX1.
7461 // Only AVX2 has register broadcasts.
7462 if (!Subtarget->hasAVX2() && !isShuffleFoldableLoad(V))
7464 } else if (BroadcastIdx != 0 || !Subtarget->hasAVX2()) {
7465 // We can't broadcast from a vector register without AVX2, and we can only
7466 // broadcast from the zero-element of a vector register.
7470 return DAG.getNode(X86ISD::VBROADCAST, DL, VT, V);
7473 // Check for whether we can use INSERTPS to perform the shuffle. We only use
7474 // INSERTPS when the V1 elements are already in the correct locations
7475 // because otherwise we can just always use two SHUFPS instructions which
7476 // are much smaller to encode than a SHUFPS and an INSERTPS. We can also
7477 // perform INSERTPS if a single V1 element is out of place and all V2
7478 // elements are zeroable.
7479 static SDValue lowerVectorShuffleAsInsertPS(SDValue Op, SDValue V1, SDValue V2,
7481 SelectionDAG &DAG) {
7482 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
7483 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7484 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7485 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7487 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7490 int V1DstIndex = -1;
7491 int V2DstIndex = -1;
7492 bool V1UsedInPlace = false;
7494 for (int i = 0; i < 4; ++i) {
7495 // Synthesize a zero mask from the zeroable elements (includes undefs).
7501 // Flag if we use any V1 inputs in place.
7503 V1UsedInPlace = true;
7507 // We can only insert a single non-zeroable element.
7508 if (V1DstIndex != -1 || V2DstIndex != -1)
7512 // V1 input out of place for insertion.
7515 // V2 input for insertion.
7520 // Don't bother if we have no (non-zeroable) element for insertion.
7521 if (V1DstIndex == -1 && V2DstIndex == -1)
7524 // Determine element insertion src/dst indices. The src index is from the
7525 // start of the inserted vector, not the start of the concatenated vector.
7526 unsigned V2SrcIndex = 0;
7527 if (V1DstIndex != -1) {
7528 // If we have a V1 input out of place, we use V1 as the V2 element insertion
7529 // and don't use the original V2 at all.
7530 V2SrcIndex = Mask[V1DstIndex];
7531 V2DstIndex = V1DstIndex;
7534 V2SrcIndex = Mask[V2DstIndex] - 4;
7537 // If no V1 inputs are used in place, then the result is created only from
7538 // the zero mask and the V2 insertion - so remove V1 dependency.
7540 V1 = DAG.getUNDEF(MVT::v4f32);
7542 unsigned InsertPSMask = V2SrcIndex << 6 | V2DstIndex << 4 | ZMask;
7543 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
7545 // Insert the V2 element into the desired position.
7547 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
7548 DAG.getConstant(InsertPSMask, DL, MVT::i8));
7551 /// \brief Try to lower a shuffle as a permute of the inputs followed by an
7552 /// UNPCK instruction.
7554 /// This specifically targets cases where we end up with alternating between
7555 /// the two inputs, and so can permute them into something that feeds a single
7556 /// UNPCK instruction. Note that this routine only targets integer vectors
7557 /// because for floating point vectors we have a generalized SHUFPS lowering
7558 /// strategy that handles everything that doesn't *exactly* match an unpack,
7559 /// making this clever lowering unnecessary.
7560 static SDValue lowerVectorShuffleAsUnpack(SDLoc DL, MVT VT, SDValue V1,
7561 SDValue V2, ArrayRef<int> Mask,
7562 SelectionDAG &DAG) {
7563 assert(!VT.isFloatingPoint() &&
7564 "This routine only supports integer vectors.");
7565 assert(!isSingleInputShuffleMask(Mask) &&
7566 "This routine should only be used when blending two inputs.");
7567 assert(Mask.size() >= 2 && "Single element masks are invalid.");
7569 int Size = Mask.size();
7571 int NumLoInputs = std::count_if(Mask.begin(), Mask.end(), [Size](int M) {
7572 return M >= 0 && M % Size < Size / 2;
7574 int NumHiInputs = std::count_if(
7575 Mask.begin(), Mask.end(), [Size](int M) { return M % Size >= Size / 2; });
7577 bool UnpackLo = NumLoInputs >= NumHiInputs;
7579 auto TryUnpack = [&](MVT UnpackVT, int Scale) {
7580 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7581 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7583 for (int i = 0; i < Size; ++i) {
7587 // Each element of the unpack contains Scale elements from this mask.
7588 int UnpackIdx = i / Scale;
7590 // We only handle the case where V1 feeds the first slots of the unpack.
7591 // We rely on canonicalization to ensure this is the case.
7592 if ((UnpackIdx % 2 == 0) != (Mask[i] < Size))
7595 // Setup the mask for this input. The indexing is tricky as we have to
7596 // handle the unpack stride.
7597 SmallVectorImpl<int> &VMask = (UnpackIdx % 2 == 0) ? V1Mask : V2Mask;
7598 VMask[(UnpackIdx / 2) * Scale + i % Scale + (UnpackLo ? 0 : Size / 2)] =
7602 // If we will have to shuffle both inputs to use the unpack, check whether
7603 // we can just unpack first and shuffle the result. If so, skip this unpack.
7604 if ((NumLoInputs == 0 || NumHiInputs == 0) && !isNoopShuffleMask(V1Mask) &&
7605 !isNoopShuffleMask(V2Mask))
7608 // Shuffle the inputs into place.
7609 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7610 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7612 // Cast the inputs to the type we will use to unpack them.
7613 V1 = DAG.getBitcast(UnpackVT, V1);
7614 V2 = DAG.getBitcast(UnpackVT, V2);
7616 // Unpack the inputs and cast the result back to the desired type.
7617 return DAG.getBitcast(
7618 VT, DAG.getNode(UnpackLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
7622 // We try each unpack from the largest to the smallest to try and find one
7623 // that fits this mask.
7624 int OrigNumElements = VT.getVectorNumElements();
7625 int OrigScalarSize = VT.getScalarSizeInBits();
7626 for (int ScalarSize = 64; ScalarSize >= OrigScalarSize; ScalarSize /= 2) {
7627 int Scale = ScalarSize / OrigScalarSize;
7628 int NumElements = OrigNumElements / Scale;
7629 MVT UnpackVT = MVT::getVectorVT(MVT::getIntegerVT(ScalarSize), NumElements);
7630 if (SDValue Unpack = TryUnpack(UnpackVT, Scale))
7634 // If none of the unpack-rooted lowerings worked (or were profitable) try an
7636 if (NumLoInputs == 0 || NumHiInputs == 0) {
7637 assert((NumLoInputs > 0 || NumHiInputs > 0) &&
7638 "We have to have *some* inputs!");
7639 int HalfOffset = NumLoInputs == 0 ? Size / 2 : 0;
7641 // FIXME: We could consider the total complexity of the permute of each
7642 // possible unpacking. Or at the least we should consider how many
7643 // half-crossings are created.
7644 // FIXME: We could consider commuting the unpacks.
7646 SmallVector<int, 32> PermMask;
7647 PermMask.assign(Size, -1);
7648 for (int i = 0; i < Size; ++i) {
7652 assert(Mask[i] % Size >= HalfOffset && "Found input from wrong half!");
7655 2 * ((Mask[i] % Size) - HalfOffset) + (Mask[i] < Size ? 0 : 1);
7657 return DAG.getVectorShuffle(
7658 VT, DL, DAG.getNode(NumLoInputs == 0 ? X86ISD::UNPCKH : X86ISD::UNPCKL,
7660 DAG.getUNDEF(VT), PermMask);
7666 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
7668 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
7669 /// support for floating point shuffles but not integer shuffles. These
7670 /// instructions will incur a domain crossing penalty on some chips though so
7671 /// it is better to avoid lowering through this for integer vectors where
7673 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7674 const X86Subtarget *Subtarget,
7675 SelectionDAG &DAG) {
7677 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
7678 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7679 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7680 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7681 ArrayRef<int> Mask = SVOp->getMask();
7682 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7684 if (isSingleInputShuffleMask(Mask)) {
7685 // Use low duplicate instructions for masks that match their pattern.
7686 if (Subtarget->hasSSE3())
7687 if (isShuffleEquivalent(V1, V2, Mask, {0, 0}))
7688 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v2f64, V1);
7690 // Straight shuffle of a single input vector. Simulate this by using the
7691 // single input as both of the "inputs" to this instruction..
7692 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
7694 if (Subtarget->hasAVX()) {
7695 // If we have AVX, we can use VPERMILPS which will allow folding a load
7696 // into the shuffle.
7697 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
7698 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
7701 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V1,
7702 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
7704 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
7705 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
7707 // If we have a single input, insert that into V1 if we can do so cheaply.
7708 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
7709 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7710 DL, MVT::v2f64, V1, V2, Mask, Subtarget, DAG))
7712 // Try inverting the insertion since for v2 masks it is easy to do and we
7713 // can't reliably sort the mask one way or the other.
7714 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
7715 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
7716 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7717 DL, MVT::v2f64, V2, V1, InverseMask, Subtarget, DAG))
7721 // Try to use one of the special instruction patterns to handle two common
7722 // blend patterns if a zero-blend above didn't work.
7723 if (isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
7724 isShuffleEquivalent(V1, V2, Mask, {1, 3}))
7725 if (SDValue V1S = getScalarValueForVectorElement(V1, Mask[0], DAG))
7726 // We can either use a special instruction to load over the low double or
7727 // to move just the low double.
7729 isShuffleFoldableLoad(V1S) ? X86ISD::MOVLPD : X86ISD::MOVSD,
7731 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64, V1S));
7733 if (Subtarget->hasSSE41())
7734 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
7738 // Use dedicated unpack instructions for masks that match their pattern.
7739 if (isShuffleEquivalent(V1, V2, Mask, {0, 2}))
7740 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
7741 if (isShuffleEquivalent(V1, V2, Mask, {1, 3}))
7742 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
7744 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
7745 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V2,
7746 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
7749 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
7751 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
7752 /// the integer unit to minimize domain crossing penalties. However, for blends
7753 /// it falls back to the floating point shuffle operation with appropriate bit
7755 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7756 const X86Subtarget *Subtarget,
7757 SelectionDAG &DAG) {
7759 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
7760 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7761 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7762 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7763 ArrayRef<int> Mask = SVOp->getMask();
7764 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7766 if (isSingleInputShuffleMask(Mask)) {
7767 // Check for being able to broadcast a single element.
7768 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v2i64, V1,
7769 Mask, Subtarget, DAG))
7772 // Straight shuffle of a single input vector. For everything from SSE2
7773 // onward this has a single fast instruction with no scary immediates.
7774 // We have to map the mask as it is actually a v4i32 shuffle instruction.
7775 V1 = DAG.getBitcast(MVT::v4i32, V1);
7776 int WidenedMask[4] = {
7777 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
7778 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
7779 return DAG.getBitcast(
7781 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
7782 getV4X86ShuffleImm8ForMask(WidenedMask, DL, DAG)));
7784 assert(Mask[0] != -1 && "No undef lanes in multi-input v2 shuffles!");
7785 assert(Mask[1] != -1 && "No undef lanes in multi-input v2 shuffles!");
7786 assert(Mask[0] < 2 && "We sort V1 to be the first input.");
7787 assert(Mask[1] >= 2 && "We sort V2 to be the second input.");
7789 // If we have a blend of two PACKUS operations an the blend aligns with the
7790 // low and half halves, we can just merge the PACKUS operations. This is
7791 // particularly important as it lets us merge shuffles that this routine itself
7793 auto GetPackNode = [](SDValue V) {
7794 while (V.getOpcode() == ISD::BITCAST)
7795 V = V.getOperand(0);
7797 return V.getOpcode() == X86ISD::PACKUS ? V : SDValue();
7799 if (SDValue V1Pack = GetPackNode(V1))
7800 if (SDValue V2Pack = GetPackNode(V2))
7801 return DAG.getBitcast(MVT::v2i64,
7802 DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8,
7803 Mask[0] == 0 ? V1Pack.getOperand(0)
7804 : V1Pack.getOperand(1),
7805 Mask[1] == 2 ? V2Pack.getOperand(0)
7806 : V2Pack.getOperand(1)));
7808 // Try to use shift instructions.
7810 lowerVectorShuffleAsShift(DL, MVT::v2i64, V1, V2, Mask, DAG))
7813 // When loading a scalar and then shuffling it into a vector we can often do
7814 // the insertion cheaply.
7815 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7816 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
7818 // Try inverting the insertion since for v2 masks it is easy to do and we
7819 // can't reliably sort the mask one way or the other.
7820 int InverseMask[2] = {Mask[0] ^ 2, Mask[1] ^ 2};
7821 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7822 DL, MVT::v2i64, V2, V1, InverseMask, Subtarget, DAG))
7825 // We have different paths for blend lowering, but they all must use the
7826 // *exact* same predicate.
7827 bool IsBlendSupported = Subtarget->hasSSE41();
7828 if (IsBlendSupported)
7829 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
7833 // Use dedicated unpack instructions for masks that match their pattern.
7834 if (isShuffleEquivalent(V1, V2, Mask, {0, 2}))
7835 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
7836 if (isShuffleEquivalent(V1, V2, Mask, {1, 3}))
7837 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
7839 // Try to use byte rotation instructions.
7840 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
7841 if (Subtarget->hasSSSE3())
7842 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
7843 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
7846 // If we have direct support for blends, we should lower by decomposing into
7847 // a permute. That will be faster than the domain cross.
7848 if (IsBlendSupported)
7849 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v2i64, V1, V2,
7852 // We implement this with SHUFPD which is pretty lame because it will likely
7853 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
7854 // However, all the alternatives are still more cycles and newer chips don't
7855 // have this problem. It would be really nice if x86 had better shuffles here.
7856 V1 = DAG.getBitcast(MVT::v2f64, V1);
7857 V2 = DAG.getBitcast(MVT::v2f64, V2);
7858 return DAG.getBitcast(MVT::v2i64,
7859 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
7862 /// \brief Test whether this can be lowered with a single SHUFPS instruction.
7864 /// This is used to disable more specialized lowerings when the shufps lowering
7865 /// will happen to be efficient.
7866 static bool isSingleSHUFPSMask(ArrayRef<int> Mask) {
7867 // This routine only handles 128-bit shufps.
7868 assert(Mask.size() == 4 && "Unsupported mask size!");
7870 // To lower with a single SHUFPS we need to have the low half and high half
7871 // each requiring a single input.
7872 if (Mask[0] != -1 && Mask[1] != -1 && (Mask[0] < 4) != (Mask[1] < 4))
7874 if (Mask[2] != -1 && Mask[3] != -1 && (Mask[2] < 4) != (Mask[3] < 4))
7880 /// \brief Lower a vector shuffle using the SHUFPS instruction.
7882 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
7883 /// It makes no assumptions about whether this is the *best* lowering, it simply
7885 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
7886 ArrayRef<int> Mask, SDValue V1,
7887 SDValue V2, SelectionDAG &DAG) {
7888 SDValue LowV = V1, HighV = V2;
7889 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
7892 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7894 if (NumV2Elements == 1) {
7896 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
7899 // Compute the index adjacent to V2Index and in the same half by toggling
7901 int V2AdjIndex = V2Index ^ 1;
7903 if (Mask[V2AdjIndex] == -1) {
7904 // Handles all the cases where we have a single V2 element and an undef.
7905 // This will only ever happen in the high lanes because we commute the
7906 // vector otherwise.
7908 std::swap(LowV, HighV);
7909 NewMask[V2Index] -= 4;
7911 // Handle the case where the V2 element ends up adjacent to a V1 element.
7912 // To make this work, blend them together as the first step.
7913 int V1Index = V2AdjIndex;
7914 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
7915 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
7916 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
7918 // Now proceed to reconstruct the final blend as we have the necessary
7919 // high or low half formed.
7926 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
7927 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
7929 } else if (NumV2Elements == 2) {
7930 if (Mask[0] < 4 && Mask[1] < 4) {
7931 // Handle the easy case where we have V1 in the low lanes and V2 in the
7935 } else if (Mask[2] < 4 && Mask[3] < 4) {
7936 // We also handle the reversed case because this utility may get called
7937 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
7938 // arrange things in the right direction.
7944 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
7945 // trying to place elements directly, just blend them and set up the final
7946 // shuffle to place them.
7948 // The first two blend mask elements are for V1, the second two are for
7950 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
7951 Mask[2] < 4 ? Mask[2] : Mask[3],
7952 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
7953 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
7954 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
7955 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
7957 // Now we do a normal shuffle of V1 by giving V1 as both operands to
7960 NewMask[0] = Mask[0] < 4 ? 0 : 2;
7961 NewMask[1] = Mask[0] < 4 ? 2 : 0;
7962 NewMask[2] = Mask[2] < 4 ? 1 : 3;
7963 NewMask[3] = Mask[2] < 4 ? 3 : 1;
7966 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
7967 getV4X86ShuffleImm8ForMask(NewMask, DL, DAG));
7970 /// \brief Lower 4-lane 32-bit floating point shuffles.
7972 /// Uses instructions exclusively from the floating point unit to minimize
7973 /// domain crossing penalties, as these are sufficient to implement all v4f32
7975 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7976 const X86Subtarget *Subtarget,
7977 SelectionDAG &DAG) {
7979 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
7980 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7981 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7982 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7983 ArrayRef<int> Mask = SVOp->getMask();
7984 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7987 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7989 if (NumV2Elements == 0) {
7990 // Check for being able to broadcast a single element.
7991 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f32, V1,
7992 Mask, Subtarget, DAG))
7995 // Use even/odd duplicate instructions for masks that match their pattern.
7996 if (Subtarget->hasSSE3()) {
7997 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
7998 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v4f32, V1);
7999 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3}))
8000 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v4f32, V1);
8003 if (Subtarget->hasAVX()) {
8004 // If we have AVX, we can use VPERMILPS which will allow folding a load
8005 // into the shuffle.
8006 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
8007 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8010 // Otherwise, use a straight shuffle of a single input vector. We pass the
8011 // input vector to both operands to simulate this with a SHUFPS.
8012 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
8013 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8016 // There are special ways we can lower some single-element blends. However, we
8017 // have custom ways we can lower more complex single-element blends below that
8018 // we defer to if both this and BLENDPS fail to match, so restrict this to
8019 // when the V2 input is targeting element 0 of the mask -- that is the fast
8021 if (NumV2Elements == 1 && Mask[0] >= 4)
8022 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4f32, V1, V2,
8023 Mask, Subtarget, DAG))
8026 if (Subtarget->hasSSE41()) {
8027 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
8031 // Use INSERTPS if we can complete the shuffle efficiently.
8032 if (SDValue V = lowerVectorShuffleAsInsertPS(Op, V1, V2, Mask, DAG))
8035 if (!isSingleSHUFPSMask(Mask))
8036 if (SDValue BlendPerm = lowerVectorShuffleAsBlendAndPermute(
8037 DL, MVT::v4f32, V1, V2, Mask, DAG))
8041 // Use dedicated unpack instructions for masks that match their pattern.
8042 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 1, 5}))
8043 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
8044 if (isShuffleEquivalent(V1, V2, Mask, {2, 6, 3, 7}))
8045 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
8046 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 5, 1}))
8047 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V2, V1);
8048 if (isShuffleEquivalent(V1, V2, Mask, {6, 2, 7, 3}))
8049 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V2, V1);
8051 // Otherwise fall back to a SHUFPS lowering strategy.
8052 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
8055 /// \brief Lower 4-lane i32 vector shuffles.
8057 /// We try to handle these with integer-domain shuffles where we can, but for
8058 /// blends we use the floating point domain blend instructions.
8059 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8060 const X86Subtarget *Subtarget,
8061 SelectionDAG &DAG) {
8063 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
8064 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8065 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8066 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8067 ArrayRef<int> Mask = SVOp->getMask();
8068 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8070 // Whenever we can lower this as a zext, that instruction is strictly faster
8071 // than any alternative. It also allows us to fold memory operands into the
8072 // shuffle in many cases.
8073 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
8074 Mask, Subtarget, DAG))
8078 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8080 if (NumV2Elements == 0) {
8081 // Check for being able to broadcast a single element.
8082 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i32, V1,
8083 Mask, Subtarget, DAG))
8086 // Straight shuffle of a single input vector. For everything from SSE2
8087 // onward this has a single fast instruction with no scary immediates.
8088 // We coerce the shuffle pattern to be compatible with UNPCK instructions
8089 // but we aren't actually going to use the UNPCK instruction because doing
8090 // so prevents folding a load into this instruction or making a copy.
8091 const int UnpackLoMask[] = {0, 0, 1, 1};
8092 const int UnpackHiMask[] = {2, 2, 3, 3};
8093 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 1, 1}))
8094 Mask = UnpackLoMask;
8095 else if (isShuffleEquivalent(V1, V2, Mask, {2, 2, 3, 3}))
8096 Mask = UnpackHiMask;
8098 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8099 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8102 // Try to use shift instructions.
8104 lowerVectorShuffleAsShift(DL, MVT::v4i32, V1, V2, Mask, DAG))
8107 // There are special ways we can lower some single-element blends.
8108 if (NumV2Elements == 1)
8109 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4i32, V1, V2,
8110 Mask, Subtarget, DAG))
8113 // We have different paths for blend lowering, but they all must use the
8114 // *exact* same predicate.
8115 bool IsBlendSupported = Subtarget->hasSSE41();
8116 if (IsBlendSupported)
8117 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
8121 if (SDValue Masked =
8122 lowerVectorShuffleAsBitMask(DL, MVT::v4i32, V1, V2, Mask, DAG))
8125 // Use dedicated unpack instructions for masks that match their pattern.
8126 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 1, 5}))
8127 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
8128 if (isShuffleEquivalent(V1, V2, Mask, {2, 6, 3, 7}))
8129 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
8130 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 5, 1}))
8131 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V2, V1);
8132 if (isShuffleEquivalent(V1, V2, Mask, {6, 2, 7, 3}))
8133 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V2, V1);
8135 // Try to use byte rotation instructions.
8136 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8137 if (Subtarget->hasSSSE3())
8138 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8139 DL, MVT::v4i32, V1, V2, Mask, Subtarget, DAG))
8142 // If we have direct support for blends, we should lower by decomposing into
8143 // a permute. That will be faster than the domain cross.
8144 if (IsBlendSupported)
8145 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i32, V1, V2,
8148 // Try to lower by permuting the inputs into an unpack instruction.
8149 if (SDValue Unpack =
8150 lowerVectorShuffleAsUnpack(DL, MVT::v4i32, V1, V2, Mask, DAG))
8153 // We implement this with SHUFPS because it can blend from two vectors.
8154 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
8155 // up the inputs, bypassing domain shift penalties that we would encur if we
8156 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
8158 return DAG.getBitcast(
8160 DAG.getVectorShuffle(MVT::v4f32, DL, DAG.getBitcast(MVT::v4f32, V1),
8161 DAG.getBitcast(MVT::v4f32, V2), Mask));
8164 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
8165 /// shuffle lowering, and the most complex part.
8167 /// The lowering strategy is to try to form pairs of input lanes which are
8168 /// targeted at the same half of the final vector, and then use a dword shuffle
8169 /// to place them onto the right half, and finally unpack the paired lanes into
8170 /// their final position.
8172 /// The exact breakdown of how to form these dword pairs and align them on the
8173 /// correct sides is really tricky. See the comments within the function for
8174 /// more of the details.
8176 /// This code also handles repeated 128-bit lanes of v8i16 shuffles, but each
8177 /// lane must shuffle the *exact* same way. In fact, you must pass a v8 Mask to
8178 /// this routine for it to work correctly. To shuffle a 256-bit or 512-bit i16
8179 /// vector, form the analogous 128-bit 8-element Mask.
8180 static SDValue lowerV8I16GeneralSingleInputVectorShuffle(
8181 SDLoc DL, MVT VT, SDValue V, MutableArrayRef<int> Mask,
8182 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8183 assert(VT.getScalarType() == MVT::i16 && "Bad input type!");
8184 MVT PSHUFDVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
8186 assert(Mask.size() == 8 && "Shuffle mask length doen't match!");
8187 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8188 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8190 SmallVector<int, 4> LoInputs;
8191 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8192 [](int M) { return M >= 0; });
8193 std::sort(LoInputs.begin(), LoInputs.end());
8194 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8195 SmallVector<int, 4> HiInputs;
8196 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8197 [](int M) { return M >= 0; });
8198 std::sort(HiInputs.begin(), HiInputs.end());
8199 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8201 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8202 int NumHToL = LoInputs.size() - NumLToL;
8204 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8205 int NumHToH = HiInputs.size() - NumLToH;
8206 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8207 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8208 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8209 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8211 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8212 // such inputs we can swap two of the dwords across the half mark and end up
8213 // with <=2 inputs to each half in each half. Once there, we can fall through
8214 // to the generic code below. For example:
8216 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8217 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8219 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8220 // and an existing 2-into-2 on the other half. In this case we may have to
8221 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8222 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8223 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8224 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8225 // half than the one we target for fixing) will be fixed when we re-enter this
8226 // path. We will also combine away any sequence of PSHUFD instructions that
8227 // result into a single instruction. Here is an example of the tricky case:
8229 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8230 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8232 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8234 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8235 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8237 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8238 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8240 // The result is fine to be handled by the generic logic.
8241 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8242 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8243 int AOffset, int BOffset) {
8244 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8245 "Must call this with A having 3 or 1 inputs from the A half.");
8246 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8247 "Must call this with B having 1 or 3 inputs from the B half.");
8248 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8249 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8251 // Compute the index of dword with only one word among the three inputs in
8252 // a half by taking the sum of the half with three inputs and subtracting
8253 // the sum of the actual three inputs. The difference is the remaining
8256 int &TripleDWord = AToAInputs.size() == 3 ? ADWord : BDWord;
8257 int &OneInputDWord = AToAInputs.size() == 3 ? BDWord : ADWord;
8258 int TripleInputOffset = AToAInputs.size() == 3 ? AOffset : BOffset;
8259 ArrayRef<int> TripleInputs = AToAInputs.size() == 3 ? AToAInputs : BToAInputs;
8260 int OneInput = AToAInputs.size() == 3 ? BToAInputs[0] : AToAInputs[0];
8261 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8262 int TripleNonInputIdx =
8263 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8264 TripleDWord = TripleNonInputIdx / 2;
8266 // We use xor with one to compute the adjacent DWord to whichever one the
8268 OneInputDWord = (OneInput / 2) ^ 1;
8270 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8271 // and BToA inputs. If there is also such a problem with the BToB and AToB
8272 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8273 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8274 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8275 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8276 // Compute how many inputs will be flipped by swapping these DWords. We
8278 // to balance this to ensure we don't form a 3-1 shuffle in the other
8280 int NumFlippedAToBInputs =
8281 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8282 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8283 int NumFlippedBToBInputs =
8284 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8285 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8286 if ((NumFlippedAToBInputs == 1 &&
8287 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8288 (NumFlippedBToBInputs == 1 &&
8289 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8290 // We choose whether to fix the A half or B half based on whether that
8291 // half has zero flipped inputs. At zero, we may not be able to fix it
8292 // with that half. We also bias towards fixing the B half because that
8293 // will more commonly be the high half, and we have to bias one way.
8294 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8295 ArrayRef<int> Inputs) {
8296 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8297 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8298 PinnedIdx ^ 1) != Inputs.end();
8299 // Determine whether the free index is in the flipped dword or the
8300 // unflipped dword based on where the pinned index is. We use this bit
8301 // in an xor to conditionally select the adjacent dword.
8302 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8303 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8304 FixFreeIdx) != Inputs.end();
8305 if (IsFixIdxInput == IsFixFreeIdxInput)
8307 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8308 FixFreeIdx) != Inputs.end();
8309 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8310 "We need to be changing the number of flipped inputs!");
8311 int PSHUFHalfMask[] = {0, 1, 2, 3};
8312 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8313 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8315 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DL, DAG));
8318 if (M != -1 && M == FixIdx)
8320 else if (M != -1 && M == FixFreeIdx)
8323 if (NumFlippedBToBInputs != 0) {
8325 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8326 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8328 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8330 AToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8331 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8336 int PSHUFDMask[] = {0, 1, 2, 3};
8337 PSHUFDMask[ADWord] = BDWord;
8338 PSHUFDMask[BDWord] = ADWord;
8341 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT, DAG.getBitcast(PSHUFDVT, V),
8342 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
8344 // Adjust the mask to match the new locations of A and B.
8346 if (M != -1 && M/2 == ADWord)
8347 M = 2 * BDWord + M % 2;
8348 else if (M != -1 && M/2 == BDWord)
8349 M = 2 * ADWord + M % 2;
8351 // Recurse back into this routine to re-compute state now that this isn't
8352 // a 3 and 1 problem.
8353 return lowerV8I16GeneralSingleInputVectorShuffle(DL, VT, V, Mask, Subtarget,
8356 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8357 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8358 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8359 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8361 // At this point there are at most two inputs to the low and high halves from
8362 // each half. That means the inputs can always be grouped into dwords and
8363 // those dwords can then be moved to the correct half with a dword shuffle.
8364 // We use at most one low and one high word shuffle to collect these paired
8365 // inputs into dwords, and finally a dword shuffle to place them.
8366 int PSHUFLMask[4] = {-1, -1, -1, -1};
8367 int PSHUFHMask[4] = {-1, -1, -1, -1};
8368 int PSHUFDMask[4] = {-1, -1, -1, -1};
8370 // First fix the masks for all the inputs that are staying in their
8371 // original halves. This will then dictate the targets of the cross-half
8373 auto fixInPlaceInputs =
8374 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8375 MutableArrayRef<int> SourceHalfMask,
8376 MutableArrayRef<int> HalfMask, int HalfOffset) {
8377 if (InPlaceInputs.empty())
8379 if (InPlaceInputs.size() == 1) {
8380 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8381 InPlaceInputs[0] - HalfOffset;
8382 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8385 if (IncomingInputs.empty()) {
8386 // Just fix all of the in place inputs.
8387 for (int Input : InPlaceInputs) {
8388 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8389 PSHUFDMask[Input / 2] = Input / 2;
8394 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8395 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8396 InPlaceInputs[0] - HalfOffset;
8397 // Put the second input next to the first so that they are packed into
8398 // a dword. We find the adjacent index by toggling the low bit.
8399 int AdjIndex = InPlaceInputs[0] ^ 1;
8400 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8401 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8402 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8404 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8405 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8407 // Now gather the cross-half inputs and place them into a free dword of
8408 // their target half.
8409 // FIXME: This operation could almost certainly be simplified dramatically to
8410 // look more like the 3-1 fixing operation.
8411 auto moveInputsToRightHalf = [&PSHUFDMask](
8412 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8413 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8414 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8416 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8417 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8419 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8421 int LowWord = Word & ~1;
8422 int HighWord = Word | 1;
8423 return isWordClobbered(SourceHalfMask, LowWord) ||
8424 isWordClobbered(SourceHalfMask, HighWord);
8427 if (IncomingInputs.empty())
8430 if (ExistingInputs.empty()) {
8431 // Map any dwords with inputs from them into the right half.
8432 for (int Input : IncomingInputs) {
8433 // If the source half mask maps over the inputs, turn those into
8434 // swaps and use the swapped lane.
8435 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8436 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8437 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8438 Input - SourceOffset;
8439 // We have to swap the uses in our half mask in one sweep.
8440 for (int &M : HalfMask)
8441 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8443 else if (M == Input)
8444 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8446 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8447 Input - SourceOffset &&
8448 "Previous placement doesn't match!");
8450 // Note that this correctly re-maps both when we do a swap and when
8451 // we observe the other side of the swap above. We rely on that to
8452 // avoid swapping the members of the input list directly.
8453 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8456 // Map the input's dword into the correct half.
8457 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8458 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8460 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8462 "Previous placement doesn't match!");
8465 // And just directly shift any other-half mask elements to be same-half
8466 // as we will have mirrored the dword containing the element into the
8467 // same position within that half.
8468 for (int &M : HalfMask)
8469 if (M >= SourceOffset && M < SourceOffset + 4) {
8470 M = M - SourceOffset + DestOffset;
8471 assert(M >= 0 && "This should never wrap below zero!");
8476 // Ensure we have the input in a viable dword of its current half. This
8477 // is particularly tricky because the original position may be clobbered
8478 // by inputs being moved and *staying* in that half.
8479 if (IncomingInputs.size() == 1) {
8480 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8481 int InputFixed = std::find(std::begin(SourceHalfMask),
8482 std::end(SourceHalfMask), -1) -
8483 std::begin(SourceHalfMask) + SourceOffset;
8484 SourceHalfMask[InputFixed - SourceOffset] =
8485 IncomingInputs[0] - SourceOffset;
8486 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8488 IncomingInputs[0] = InputFixed;
8490 } else if (IncomingInputs.size() == 2) {
8491 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8492 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8493 // We have two non-adjacent or clobbered inputs we need to extract from
8494 // the source half. To do this, we need to map them into some adjacent
8495 // dword slot in the source mask.
8496 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8497 IncomingInputs[1] - SourceOffset};
8499 // If there is a free slot in the source half mask adjacent to one of
8500 // the inputs, place the other input in it. We use (Index XOR 1) to
8501 // compute an adjacent index.
8502 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8503 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8504 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8505 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8506 InputsFixed[1] = InputsFixed[0] ^ 1;
8507 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
8508 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
8509 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
8510 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
8511 InputsFixed[0] = InputsFixed[1] ^ 1;
8512 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
8513 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
8514 // The two inputs are in the same DWord but it is clobbered and the
8515 // adjacent DWord isn't used at all. Move both inputs to the free
8517 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
8518 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
8519 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
8520 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
8522 // The only way we hit this point is if there is no clobbering
8523 // (because there are no off-half inputs to this half) and there is no
8524 // free slot adjacent to one of the inputs. In this case, we have to
8525 // swap an input with a non-input.
8526 for (int i = 0; i < 4; ++i)
8527 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
8528 "We can't handle any clobbers here!");
8529 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
8530 "Cannot have adjacent inputs here!");
8532 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8533 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
8535 // We also have to update the final source mask in this case because
8536 // it may need to undo the above swap.
8537 for (int &M : FinalSourceHalfMask)
8538 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
8539 M = InputsFixed[1] + SourceOffset;
8540 else if (M == InputsFixed[1] + SourceOffset)
8541 M = (InputsFixed[0] ^ 1) + SourceOffset;
8543 InputsFixed[1] = InputsFixed[0] ^ 1;
8546 // Point everything at the fixed inputs.
8547 for (int &M : HalfMask)
8548 if (M == IncomingInputs[0])
8549 M = InputsFixed[0] + SourceOffset;
8550 else if (M == IncomingInputs[1])
8551 M = InputsFixed[1] + SourceOffset;
8553 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
8554 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
8557 llvm_unreachable("Unhandled input size!");
8560 // Now hoist the DWord down to the right half.
8561 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
8562 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
8563 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
8564 for (int &M : HalfMask)
8565 for (int Input : IncomingInputs)
8567 M = FreeDWord * 2 + Input % 2;
8569 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
8570 /*SourceOffset*/ 4, /*DestOffset*/ 0);
8571 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
8572 /*SourceOffset*/ 0, /*DestOffset*/ 4);
8574 // Now enact all the shuffles we've computed to move the inputs into their
8576 if (!isNoopShuffleMask(PSHUFLMask))
8577 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
8578 getV4X86ShuffleImm8ForMask(PSHUFLMask, DL, DAG));
8579 if (!isNoopShuffleMask(PSHUFHMask))
8580 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
8581 getV4X86ShuffleImm8ForMask(PSHUFHMask, DL, DAG));
8582 if (!isNoopShuffleMask(PSHUFDMask))
8585 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT, DAG.getBitcast(PSHUFDVT, V),
8586 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
8588 // At this point, each half should contain all its inputs, and we can then
8589 // just shuffle them into their final position.
8590 assert(std::count_if(LoMask.begin(), LoMask.end(),
8591 [](int M) { return M >= 4; }) == 0 &&
8592 "Failed to lift all the high half inputs to the low mask!");
8593 assert(std::count_if(HiMask.begin(), HiMask.end(),
8594 [](int M) { return M >= 0 && M < 4; }) == 0 &&
8595 "Failed to lift all the low half inputs to the high mask!");
8597 // Do a half shuffle for the low mask.
8598 if (!isNoopShuffleMask(LoMask))
8599 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
8600 getV4X86ShuffleImm8ForMask(LoMask, DL, DAG));
8602 // Do a half shuffle with the high mask after shifting its values down.
8603 for (int &M : HiMask)
8606 if (!isNoopShuffleMask(HiMask))
8607 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
8608 getV4X86ShuffleImm8ForMask(HiMask, DL, DAG));
8613 /// \brief Helper to form a PSHUFB-based shuffle+blend.
8614 static SDValue lowerVectorShuffleAsPSHUFB(SDLoc DL, MVT VT, SDValue V1,
8615 SDValue V2, ArrayRef<int> Mask,
8616 SelectionDAG &DAG, bool &V1InUse,
8618 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
8624 int Size = Mask.size();
8625 int Scale = 16 / Size;
8626 for (int i = 0; i < 16; ++i) {
8627 if (Mask[i / Scale] == -1) {
8628 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
8630 const int ZeroMask = 0x80;
8631 int V1Idx = Mask[i / Scale] < Size ? Mask[i / Scale] * Scale + i % Scale
8633 int V2Idx = Mask[i / Scale] < Size
8635 : (Mask[i / Scale] - Size) * Scale + i % Scale;
8636 if (Zeroable[i / Scale])
8637 V1Idx = V2Idx = ZeroMask;
8638 V1Mask[i] = DAG.getConstant(V1Idx, DL, MVT::i8);
8639 V2Mask[i] = DAG.getConstant(V2Idx, DL, MVT::i8);
8640 V1InUse |= (ZeroMask != V1Idx);
8641 V2InUse |= (ZeroMask != V2Idx);
8646 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
8647 DAG.getBitcast(MVT::v16i8, V1),
8648 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
8650 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
8651 DAG.getBitcast(MVT::v16i8, V2),
8652 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
8654 // If we need shuffled inputs from both, blend the two.
8656 if (V1InUse && V2InUse)
8657 V = DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
8659 V = V1InUse ? V1 : V2;
8661 // Cast the result back to the correct type.
8662 return DAG.getBitcast(VT, V);
8665 /// \brief Generic lowering of 8-lane i16 shuffles.
8667 /// This handles both single-input shuffles and combined shuffle/blends with
8668 /// two inputs. The single input shuffles are immediately delegated to
8669 /// a dedicated lowering routine.
8671 /// The blends are lowered in one of three fundamental ways. If there are few
8672 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
8673 /// of the input is significantly cheaper when lowered as an interleaving of
8674 /// the two inputs, try to interleave them. Otherwise, blend the low and high
8675 /// halves of the inputs separately (making them have relatively few inputs)
8676 /// and then concatenate them.
8677 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8678 const X86Subtarget *Subtarget,
8679 SelectionDAG &DAG) {
8681 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
8682 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8683 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8684 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8685 ArrayRef<int> OrigMask = SVOp->getMask();
8686 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
8687 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
8688 MutableArrayRef<int> Mask(MaskStorage);
8690 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
8692 // Whenever we can lower this as a zext, that instruction is strictly faster
8693 // than any alternative.
8694 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
8695 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
8698 auto isV1 = [](int M) { return M >= 0 && M < 8; };
8700 auto isV2 = [](int M) { return M >= 8; };
8702 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
8704 if (NumV2Inputs == 0) {
8705 // Check for being able to broadcast a single element.
8706 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i16, V1,
8707 Mask, Subtarget, DAG))
8710 // Try to use shift instructions.
8712 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V1, Mask, DAG))
8715 // Use dedicated unpack instructions for masks that match their pattern.
8716 if (isShuffleEquivalent(V1, V1, Mask, {0, 0, 1, 1, 2, 2, 3, 3}))
8717 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V1);
8718 if (isShuffleEquivalent(V1, V1, Mask, {4, 4, 5, 5, 6, 6, 7, 7}))
8719 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V1);
8721 // Try to use byte rotation instructions.
8722 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v8i16, V1, V1,
8723 Mask, Subtarget, DAG))
8726 return lowerV8I16GeneralSingleInputVectorShuffle(DL, MVT::v8i16, V1, Mask,
8730 assert(std::any_of(Mask.begin(), Mask.end(), isV1) &&
8731 "All single-input shuffles should be canonicalized to be V1-input "
8734 // Try to use shift instructions.
8736 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V2, Mask, DAG))
8739 // See if we can use SSE4A Extraction / Insertion.
8740 if (Subtarget->hasSSE4A())
8741 if (SDValue V = lowerVectorShuffleWithSSE4A(DL, MVT::v8i16, V1, V2, Mask, DAG))
8744 // There are special ways we can lower some single-element blends.
8745 if (NumV2Inputs == 1)
8746 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v8i16, V1, V2,
8747 Mask, Subtarget, DAG))
8750 // We have different paths for blend lowering, but they all must use the
8751 // *exact* same predicate.
8752 bool IsBlendSupported = Subtarget->hasSSE41();
8753 if (IsBlendSupported)
8754 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
8758 if (SDValue Masked =
8759 lowerVectorShuffleAsBitMask(DL, MVT::v8i16, V1, V2, Mask, DAG))
8762 // Use dedicated unpack instructions for masks that match their pattern.
8763 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 2, 10, 3, 11}))
8764 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V2);
8765 if (isShuffleEquivalent(V1, V2, Mask, {4, 12, 5, 13, 6, 14, 7, 15}))
8766 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V2);
8768 // Try to use byte rotation instructions.
8769 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8770 DL, MVT::v8i16, V1, V2, Mask, Subtarget, DAG))
8773 if (SDValue BitBlend =
8774 lowerVectorShuffleAsBitBlend(DL, MVT::v8i16, V1, V2, Mask, DAG))
8777 if (SDValue Unpack =
8778 lowerVectorShuffleAsUnpack(DL, MVT::v8i16, V1, V2, Mask, DAG))
8781 // If we can't directly blend but can use PSHUFB, that will be better as it
8782 // can both shuffle and set up the inefficient blend.
8783 if (!IsBlendSupported && Subtarget->hasSSSE3()) {
8784 bool V1InUse, V2InUse;
8785 return lowerVectorShuffleAsPSHUFB(DL, MVT::v8i16, V1, V2, Mask, DAG,
8789 // We can always bit-blend if we have to so the fallback strategy is to
8790 // decompose into single-input permutes and blends.
8791 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i16, V1, V2,
8795 /// \brief Check whether a compaction lowering can be done by dropping even
8796 /// elements and compute how many times even elements must be dropped.
8798 /// This handles shuffles which take every Nth element where N is a power of
8799 /// two. Example shuffle masks:
8801 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
8802 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
8803 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
8804 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
8805 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
8806 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
8808 /// Any of these lanes can of course be undef.
8810 /// This routine only supports N <= 3.
8811 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
8814 /// \returns N above, or the number of times even elements must be dropped if
8815 /// there is such a number. Otherwise returns zero.
8816 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
8817 // Figure out whether we're looping over two inputs or just one.
8818 bool IsSingleInput = isSingleInputShuffleMask(Mask);
8820 // The modulus for the shuffle vector entries is based on whether this is
8821 // a single input or not.
8822 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
8823 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
8824 "We should only be called with masks with a power-of-2 size!");
8826 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
8828 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
8829 // and 2^3 simultaneously. This is because we may have ambiguity with
8830 // partially undef inputs.
8831 bool ViableForN[3] = {true, true, true};
8833 for (int i = 0, e = Mask.size(); i < e; ++i) {
8834 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
8839 bool IsAnyViable = false;
8840 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
8841 if (ViableForN[j]) {
8844 // The shuffle mask must be equal to (i * 2^N) % M.
8845 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
8848 ViableForN[j] = false;
8850 // Early exit if we exhaust the possible powers of two.
8855 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
8859 // Return 0 as there is no viable power of two.
8863 /// \brief Generic lowering of v16i8 shuffles.
8865 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
8866 /// detect any complexity reducing interleaving. If that doesn't help, it uses
8867 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
8868 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
8870 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8871 const X86Subtarget *Subtarget,
8872 SelectionDAG &DAG) {
8874 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
8875 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
8876 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
8877 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8878 ArrayRef<int> Mask = SVOp->getMask();
8879 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
8881 // Try to use shift instructions.
8883 lowerVectorShuffleAsShift(DL, MVT::v16i8, V1, V2, Mask, DAG))
8886 // Try to use byte rotation instructions.
8887 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8888 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
8891 // Try to use a zext lowering.
8892 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
8893 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
8896 // See if we can use SSE4A Extraction / Insertion.
8897 if (Subtarget->hasSSE4A())
8898 if (SDValue V = lowerVectorShuffleWithSSE4A(DL, MVT::v16i8, V1, V2, Mask, DAG))
8902 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
8904 // For single-input shuffles, there are some nicer lowering tricks we can use.
8905 if (NumV2Elements == 0) {
8906 // Check for being able to broadcast a single element.
8907 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i8, V1,
8908 Mask, Subtarget, DAG))
8911 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
8912 // Notably, this handles splat and partial-splat shuffles more efficiently.
8913 // However, it only makes sense if the pre-duplication shuffle simplifies
8914 // things significantly. Currently, this means we need to be able to
8915 // express the pre-duplication shuffle as an i16 shuffle.
8917 // FIXME: We should check for other patterns which can be widened into an
8918 // i16 shuffle as well.
8919 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
8920 for (int i = 0; i < 16; i += 2)
8921 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
8926 auto tryToWidenViaDuplication = [&]() -> SDValue {
8927 if (!canWidenViaDuplication(Mask))
8929 SmallVector<int, 4> LoInputs;
8930 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
8931 [](int M) { return M >= 0 && M < 8; });
8932 std::sort(LoInputs.begin(), LoInputs.end());
8933 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
8935 SmallVector<int, 4> HiInputs;
8936 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
8937 [](int M) { return M >= 8; });
8938 std::sort(HiInputs.begin(), HiInputs.end());
8939 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
8942 bool TargetLo = LoInputs.size() >= HiInputs.size();
8943 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
8944 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
8946 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
8947 SmallDenseMap<int, int, 8> LaneMap;
8948 for (int I : InPlaceInputs) {
8949 PreDupI16Shuffle[I/2] = I/2;
8952 int j = TargetLo ? 0 : 4, je = j + 4;
8953 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
8954 // Check if j is already a shuffle of this input. This happens when
8955 // there are two adjacent bytes after we move the low one.
8956 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
8957 // If we haven't yet mapped the input, search for a slot into which
8959 while (j < je && PreDupI16Shuffle[j] != -1)
8963 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
8966 // Map this input with the i16 shuffle.
8967 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
8970 // Update the lane map based on the mapping we ended up with.
8971 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
8973 V1 = DAG.getBitcast(
8975 DAG.getVectorShuffle(MVT::v8i16, DL, DAG.getBitcast(MVT::v8i16, V1),
8976 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
8978 // Unpack the bytes to form the i16s that will be shuffled into place.
8979 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
8980 MVT::v16i8, V1, V1);
8982 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8983 for (int i = 0; i < 16; ++i)
8984 if (Mask[i] != -1) {
8985 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
8986 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
8987 if (PostDupI16Shuffle[i / 2] == -1)
8988 PostDupI16Shuffle[i / 2] = MappedMask;
8990 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
8991 "Conflicting entrties in the original shuffle!");
8993 return DAG.getBitcast(
8995 DAG.getVectorShuffle(MVT::v8i16, DL, DAG.getBitcast(MVT::v8i16, V1),
8996 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
8998 if (SDValue V = tryToWidenViaDuplication())
9002 // Use dedicated unpack instructions for masks that match their pattern.
9003 if (isShuffleEquivalent(V1, V2, Mask, {// Low half.
9004 0, 16, 1, 17, 2, 18, 3, 19,
9006 4, 20, 5, 21, 6, 22, 7, 23}))
9007 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V1, V2);
9008 if (isShuffleEquivalent(V1, V2, Mask, {// Low half.
9009 8, 24, 9, 25, 10, 26, 11, 27,
9011 12, 28, 13, 29, 14, 30, 15, 31}))
9012 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V1, V2);
9014 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
9015 // with PSHUFB. It is important to do this before we attempt to generate any
9016 // blends but after all of the single-input lowerings. If the single input
9017 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
9018 // want to preserve that and we can DAG combine any longer sequences into
9019 // a PSHUFB in the end. But once we start blending from multiple inputs,
9020 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
9021 // and there are *very* few patterns that would actually be faster than the
9022 // PSHUFB approach because of its ability to zero lanes.
9024 // FIXME: The only exceptions to the above are blends which are exact
9025 // interleavings with direct instructions supporting them. We currently don't
9026 // handle those well here.
9027 if (Subtarget->hasSSSE3()) {
9028 bool V1InUse = false;
9029 bool V2InUse = false;
9031 SDValue PSHUFB = lowerVectorShuffleAsPSHUFB(DL, MVT::v16i8, V1, V2, Mask,
9032 DAG, V1InUse, V2InUse);
9034 // If both V1 and V2 are in use and we can use a direct blend or an unpack,
9035 // do so. This avoids using them to handle blends-with-zero which is
9036 // important as a single pshufb is significantly faster for that.
9037 if (V1InUse && V2InUse) {
9038 if (Subtarget->hasSSE41())
9039 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i8, V1, V2,
9040 Mask, Subtarget, DAG))
9043 // We can use an unpack to do the blending rather than an or in some
9044 // cases. Even though the or may be (very minorly) more efficient, we
9045 // preference this lowering because there are common cases where part of
9046 // the complexity of the shuffles goes away when we do the final blend as
9048 // FIXME: It might be worth trying to detect if the unpack-feeding
9049 // shuffles will both be pshufb, in which case we shouldn't bother with
9051 if (SDValue Unpack =
9052 lowerVectorShuffleAsUnpack(DL, MVT::v16i8, V1, V2, Mask, DAG))
9059 // There are special ways we can lower some single-element blends.
9060 if (NumV2Elements == 1)
9061 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v16i8, V1, V2,
9062 Mask, Subtarget, DAG))
9065 if (SDValue BitBlend =
9066 lowerVectorShuffleAsBitBlend(DL, MVT::v16i8, V1, V2, Mask, DAG))
9069 // Check whether a compaction lowering can be done. This handles shuffles
9070 // which take every Nth element for some even N. See the helper function for
9073 // We special case these as they can be particularly efficiently handled with
9074 // the PACKUSB instruction on x86 and they show up in common patterns of
9075 // rearranging bytes to truncate wide elements.
9076 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
9077 // NumEvenDrops is the power of two stride of the elements. Another way of
9078 // thinking about it is that we need to drop the even elements this many
9079 // times to get the original input.
9080 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9082 // First we need to zero all the dropped bytes.
9083 assert(NumEvenDrops <= 3 &&
9084 "No support for dropping even elements more than 3 times.");
9085 // We use the mask type to pick which bytes are preserved based on how many
9086 // elements are dropped.
9087 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
9088 SDValue ByteClearMask = DAG.getBitcast(
9089 MVT::v16i8, DAG.getConstant(0xFF, DL, MaskVTs[NumEvenDrops - 1]));
9090 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
9092 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
9094 // Now pack things back together.
9095 V1 = DAG.getBitcast(MVT::v8i16, V1);
9096 V2 = IsSingleInput ? V1 : DAG.getBitcast(MVT::v8i16, V2);
9097 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
9098 for (int i = 1; i < NumEvenDrops; ++i) {
9099 Result = DAG.getBitcast(MVT::v8i16, Result);
9100 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
9106 // Handle multi-input cases by blending single-input shuffles.
9107 if (NumV2Elements > 0)
9108 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v16i8, V1, V2,
9111 // The fallback path for single-input shuffles widens this into two v8i16
9112 // vectors with unpacks, shuffles those, and then pulls them back together
9116 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9117 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9118 for (int i = 0; i < 16; ++i)
9120 (i < 8 ? LoBlendMask[i] : HiBlendMask[i % 8]) = Mask[i];
9122 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
9124 SDValue VLoHalf, VHiHalf;
9125 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
9126 // them out and avoid using UNPCK{L,H} to extract the elements of V as
9128 if (std::none_of(std::begin(LoBlendMask), std::end(LoBlendMask),
9129 [](int M) { return M >= 0 && M % 2 == 1; }) &&
9130 std::none_of(std::begin(HiBlendMask), std::end(HiBlendMask),
9131 [](int M) { return M >= 0 && M % 2 == 1; })) {
9132 // Use a mask to drop the high bytes.
9133 VLoHalf = DAG.getBitcast(MVT::v8i16, V);
9134 VLoHalf = DAG.getNode(ISD::AND, DL, MVT::v8i16, VLoHalf,
9135 DAG.getConstant(0x00FF, DL, MVT::v8i16));
9137 // This will be a single vector shuffle instead of a blend so nuke VHiHalf.
9138 VHiHalf = DAG.getUNDEF(MVT::v8i16);
9140 // Squash the masks to point directly into VLoHalf.
9141 for (int &M : LoBlendMask)
9144 for (int &M : HiBlendMask)
9148 // Otherwise just unpack the low half of V into VLoHalf and the high half into
9149 // VHiHalf so that we can blend them as i16s.
9150 VLoHalf = DAG.getBitcast(
9151 MVT::v8i16, DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
9152 VHiHalf = DAG.getBitcast(
9153 MVT::v8i16, DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
9156 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, LoBlendMask);
9157 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, HiBlendMask);
9159 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
9162 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
9164 /// This routine breaks down the specific type of 128-bit shuffle and
9165 /// dispatches to the lowering routines accordingly.
9166 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9167 MVT VT, const X86Subtarget *Subtarget,
9168 SelectionDAG &DAG) {
9169 switch (VT.SimpleTy) {
9171 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9173 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9175 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9177 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9179 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9181 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9184 llvm_unreachable("Unimplemented!");
9188 /// \brief Helper function to test whether a shuffle mask could be
9189 /// simplified by widening the elements being shuffled.
9191 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
9192 /// leaves it in an unspecified state.
9194 /// NOTE: This must handle normal vector shuffle masks and *target* vector
9195 /// shuffle masks. The latter have the special property of a '-2' representing
9196 /// a zero-ed lane of a vector.
9197 static bool canWidenShuffleElements(ArrayRef<int> Mask,
9198 SmallVectorImpl<int> &WidenedMask) {
9199 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
9200 // If both elements are undef, its trivial.
9201 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
9202 WidenedMask.push_back(SM_SentinelUndef);
9206 // Check for an undef mask and a mask value properly aligned to fit with
9207 // a pair of values. If we find such a case, use the non-undef mask's value.
9208 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
9209 WidenedMask.push_back(Mask[i + 1] / 2);
9212 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
9213 WidenedMask.push_back(Mask[i] / 2);
9217 // When zeroing, we need to spread the zeroing across both lanes to widen.
9218 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
9219 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
9220 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
9221 WidenedMask.push_back(SM_SentinelZero);
9227 // Finally check if the two mask values are adjacent and aligned with
9229 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
9230 WidenedMask.push_back(Mask[i] / 2);
9234 // Otherwise we can't safely widen the elements used in this shuffle.
9237 assert(WidenedMask.size() == Mask.size() / 2 &&
9238 "Incorrect size of mask after widening the elements!");
9243 /// \brief Generic routine to split vector shuffle into half-sized shuffles.
9245 /// This routine just extracts two subvectors, shuffles them independently, and
9246 /// then concatenates them back together. This should work effectively with all
9247 /// AVX vector shuffle types.
9248 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9249 SDValue V2, ArrayRef<int> Mask,
9250 SelectionDAG &DAG) {
9251 assert(VT.getSizeInBits() >= 256 &&
9252 "Only for 256-bit or wider vector shuffles!");
9253 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9254 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9256 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
9257 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
9259 int NumElements = VT.getVectorNumElements();
9260 int SplitNumElements = NumElements / 2;
9261 MVT ScalarVT = VT.getScalarType();
9262 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9264 // Rather than splitting build-vectors, just build two narrower build
9265 // vectors. This helps shuffling with splats and zeros.
9266 auto SplitVector = [&](SDValue V) {
9267 while (V.getOpcode() == ISD::BITCAST)
9268 V = V->getOperand(0);
9270 MVT OrigVT = V.getSimpleValueType();
9271 int OrigNumElements = OrigVT.getVectorNumElements();
9272 int OrigSplitNumElements = OrigNumElements / 2;
9273 MVT OrigScalarVT = OrigVT.getScalarType();
9274 MVT OrigSplitVT = MVT::getVectorVT(OrigScalarVT, OrigNumElements / 2);
9278 auto *BV = dyn_cast<BuildVectorSDNode>(V);
9280 LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
9281 DAG.getIntPtrConstant(0, DL));
9282 HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
9283 DAG.getIntPtrConstant(OrigSplitNumElements, DL));
9286 SmallVector<SDValue, 16> LoOps, HiOps;
9287 for (int i = 0; i < OrigSplitNumElements; ++i) {
9288 LoOps.push_back(BV->getOperand(i));
9289 HiOps.push_back(BV->getOperand(i + OrigSplitNumElements));
9291 LoV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, LoOps);
9292 HiV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, HiOps);
9294 return std::make_pair(DAG.getBitcast(SplitVT, LoV),
9295 DAG.getBitcast(SplitVT, HiV));
9298 SDValue LoV1, HiV1, LoV2, HiV2;
9299 std::tie(LoV1, HiV1) = SplitVector(V1);
9300 std::tie(LoV2, HiV2) = SplitVector(V2);
9302 // Now create two 4-way blends of these half-width vectors.
9303 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9304 bool UseLoV1 = false, UseHiV1 = false, UseLoV2 = false, UseHiV2 = false;
9305 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
9306 for (int i = 0; i < SplitNumElements; ++i) {
9307 int M = HalfMask[i];
9308 if (M >= NumElements) {
9309 if (M >= NumElements + SplitNumElements)
9313 V2BlendMask.push_back(M - NumElements);
9314 V1BlendMask.push_back(-1);
9315 BlendMask.push_back(SplitNumElements + i);
9316 } else if (M >= 0) {
9317 if (M >= SplitNumElements)
9321 V2BlendMask.push_back(-1);
9322 V1BlendMask.push_back(M);
9323 BlendMask.push_back(i);
9325 V2BlendMask.push_back(-1);
9326 V1BlendMask.push_back(-1);
9327 BlendMask.push_back(-1);
9331 // Because the lowering happens after all combining takes place, we need to
9332 // manually combine these blend masks as much as possible so that we create
9333 // a minimal number of high-level vector shuffle nodes.
9335 // First try just blending the halves of V1 or V2.
9336 if (!UseLoV1 && !UseHiV1 && !UseLoV2 && !UseHiV2)
9337 return DAG.getUNDEF(SplitVT);
9338 if (!UseLoV2 && !UseHiV2)
9339 return DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9340 if (!UseLoV1 && !UseHiV1)
9341 return DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9343 SDValue V1Blend, V2Blend;
9344 if (UseLoV1 && UseHiV1) {
9346 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9348 // We only use half of V1 so map the usage down into the final blend mask.
9349 V1Blend = UseLoV1 ? LoV1 : HiV1;
9350 for (int i = 0; i < SplitNumElements; ++i)
9351 if (BlendMask[i] >= 0 && BlendMask[i] < SplitNumElements)
9352 BlendMask[i] = V1BlendMask[i] - (UseLoV1 ? 0 : SplitNumElements);
9354 if (UseLoV2 && UseHiV2) {
9356 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9358 // We only use half of V2 so map the usage down into the final blend mask.
9359 V2Blend = UseLoV2 ? LoV2 : HiV2;
9360 for (int i = 0; i < SplitNumElements; ++i)
9361 if (BlendMask[i] >= SplitNumElements)
9362 BlendMask[i] = V2BlendMask[i] + (UseLoV2 ? SplitNumElements : 0);
9364 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9366 SDValue Lo = HalfBlend(LoMask);
9367 SDValue Hi = HalfBlend(HiMask);
9368 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9371 /// \brief Either split a vector in halves or decompose the shuffles and the
9374 /// This is provided as a good fallback for many lowerings of non-single-input
9375 /// shuffles with more than one 128-bit lane. In those cases, we want to select
9376 /// between splitting the shuffle into 128-bit components and stitching those
9377 /// back together vs. extracting the single-input shuffles and blending those
9379 static SDValue lowerVectorShuffleAsSplitOrBlend(SDLoc DL, MVT VT, SDValue V1,
9380 SDValue V2, ArrayRef<int> Mask,
9381 SelectionDAG &DAG) {
9382 assert(!isSingleInputShuffleMask(Mask) && "This routine must not be used to "
9383 "lower single-input shuffles as it "
9384 "could then recurse on itself.");
9385 int Size = Mask.size();
9387 // If this can be modeled as a broadcast of two elements followed by a blend,
9388 // prefer that lowering. This is especially important because broadcasts can
9389 // often fold with memory operands.
9390 auto DoBothBroadcast = [&] {
9391 int V1BroadcastIdx = -1, V2BroadcastIdx = -1;
9394 if (V2BroadcastIdx == -1)
9395 V2BroadcastIdx = M - Size;
9396 else if (M - Size != V2BroadcastIdx)
9398 } else if (M >= 0) {
9399 if (V1BroadcastIdx == -1)
9401 else if (M != V1BroadcastIdx)
9406 if (DoBothBroadcast())
9407 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask,
9410 // If the inputs all stem from a single 128-bit lane of each input, then we
9411 // split them rather than blending because the split will decompose to
9412 // unusually few instructions.
9413 int LaneCount = VT.getSizeInBits() / 128;
9414 int LaneSize = Size / LaneCount;
9415 SmallBitVector LaneInputs[2];
9416 LaneInputs[0].resize(LaneCount, false);
9417 LaneInputs[1].resize(LaneCount, false);
9418 for (int i = 0; i < Size; ++i)
9420 LaneInputs[Mask[i] / Size][(Mask[i] % Size) / LaneSize] = true;
9421 if (LaneInputs[0].count() <= 1 && LaneInputs[1].count() <= 1)
9422 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9424 // Otherwise, just fall back to decomposed shuffles and a blend. This requires
9425 // that the decomposed single-input shuffles don't end up here.
9426 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9429 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
9430 /// a permutation and blend of those lanes.
9432 /// This essentially blends the out-of-lane inputs to each lane into the lane
9433 /// from a permuted copy of the vector. This lowering strategy results in four
9434 /// instructions in the worst case for a single-input cross lane shuffle which
9435 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
9436 /// of. Special cases for each particular shuffle pattern should be handled
9437 /// prior to trying this lowering.
9438 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
9439 SDValue V1, SDValue V2,
9441 SelectionDAG &DAG) {
9442 // FIXME: This should probably be generalized for 512-bit vectors as well.
9443 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
9444 int LaneSize = Mask.size() / 2;
9446 // If there are only inputs from one 128-bit lane, splitting will in fact be
9447 // less expensive. The flags track whether the given lane contains an element
9448 // that crosses to another lane.
9449 bool LaneCrossing[2] = {false, false};
9450 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9451 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
9452 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
9453 if (!LaneCrossing[0] || !LaneCrossing[1])
9454 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9456 if (isSingleInputShuffleMask(Mask)) {
9457 SmallVector<int, 32> FlippedBlendMask;
9458 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9459 FlippedBlendMask.push_back(
9460 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
9462 : Mask[i] % LaneSize +
9463 (i / LaneSize) * LaneSize + Size));
9465 // Flip the vector, and blend the results which should now be in-lane. The
9466 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
9467 // 5 for the high source. The value 3 selects the high half of source 2 and
9468 // the value 2 selects the low half of source 2. We only use source 2 to
9469 // allow folding it into a memory operand.
9470 unsigned PERMMask = 3 | 2 << 4;
9471 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
9472 V1, DAG.getConstant(PERMMask, DL, MVT::i8));
9473 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
9476 // This now reduces to two single-input shuffles of V1 and V2 which at worst
9477 // will be handled by the above logic and a blend of the results, much like
9478 // other patterns in AVX.
9479 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9482 /// \brief Handle lowering 2-lane 128-bit shuffles.
9483 static SDValue lowerV2X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9484 SDValue V2, ArrayRef<int> Mask,
9485 const X86Subtarget *Subtarget,
9486 SelectionDAG &DAG) {
9487 // TODO: If minimizing size and one of the inputs is a zero vector and the
9488 // the zero vector has only one use, we could use a VPERM2X128 to save the
9489 // instruction bytes needed to explicitly generate the zero vector.
9491 // Blends are faster and handle all the non-lane-crossing cases.
9492 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, VT, V1, V2, Mask,
9496 bool IsV1Zero = ISD::isBuildVectorAllZeros(V1.getNode());
9497 bool IsV2Zero = ISD::isBuildVectorAllZeros(V2.getNode());
9499 // If either input operand is a zero vector, use VPERM2X128 because its mask
9500 // allows us to replace the zero input with an implicit zero.
9501 if (!IsV1Zero && !IsV2Zero) {
9502 // Check for patterns which can be matched with a single insert of a 128-bit
9504 bool OnlyUsesV1 = isShuffleEquivalent(V1, V2, Mask, {0, 1, 0, 1});
9505 if (OnlyUsesV1 || isShuffleEquivalent(V1, V2, Mask, {0, 1, 4, 5})) {
9506 MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(),
9507 VT.getVectorNumElements() / 2);
9508 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
9509 DAG.getIntPtrConstant(0, DL));
9510 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
9511 OnlyUsesV1 ? V1 : V2,
9512 DAG.getIntPtrConstant(0, DL));
9513 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
9517 // Otherwise form a 128-bit permutation. After accounting for undefs,
9518 // convert the 64-bit shuffle mask selection values into 128-bit
9519 // selection bits by dividing the indexes by 2 and shifting into positions
9520 // defined by a vperm2*128 instruction's immediate control byte.
9522 // The immediate permute control byte looks like this:
9523 // [1:0] - select 128 bits from sources for low half of destination
9525 // [3] - zero low half of destination
9526 // [5:4] - select 128 bits from sources for high half of destination
9528 // [7] - zero high half of destination
9530 int MaskLO = Mask[0];
9531 if (MaskLO == SM_SentinelUndef)
9532 MaskLO = Mask[1] == SM_SentinelUndef ? 0 : Mask[1];
9534 int MaskHI = Mask[2];
9535 if (MaskHI == SM_SentinelUndef)
9536 MaskHI = Mask[3] == SM_SentinelUndef ? 0 : Mask[3];
9538 unsigned PermMask = MaskLO / 2 | (MaskHI / 2) << 4;
9540 // If either input is a zero vector, replace it with an undef input.
9541 // Shuffle mask values < 4 are selecting elements of V1.
9542 // Shuffle mask values >= 4 are selecting elements of V2.
9543 // Adjust each half of the permute mask by clearing the half that was
9544 // selecting the zero vector and setting the zero mask bit.
9546 V1 = DAG.getUNDEF(VT);
9548 PermMask = (PermMask & 0xf0) | 0x08;
9550 PermMask = (PermMask & 0x0f) | 0x80;
9553 V2 = DAG.getUNDEF(VT);
9555 PermMask = (PermMask & 0xf0) | 0x08;
9557 PermMask = (PermMask & 0x0f) | 0x80;
9560 return DAG.getNode(X86ISD::VPERM2X128, DL, VT, V1, V2,
9561 DAG.getConstant(PermMask, DL, MVT::i8));
9564 /// \brief Lower a vector shuffle by first fixing the 128-bit lanes and then
9565 /// shuffling each lane.
9567 /// This will only succeed when the result of fixing the 128-bit lanes results
9568 /// in a single-input non-lane-crossing shuffle with a repeating shuffle mask in
9569 /// each 128-bit lanes. This handles many cases where we can quickly blend away
9570 /// the lane crosses early and then use simpler shuffles within each lane.
9572 /// FIXME: It might be worthwhile at some point to support this without
9573 /// requiring the 128-bit lane-relative shuffles to be repeating, but currently
9574 /// in x86 only floating point has interesting non-repeating shuffles, and even
9575 /// those are still *marginally* more expensive.
9576 static SDValue lowerVectorShuffleByMerging128BitLanes(
9577 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
9578 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
9579 assert(!isSingleInputShuffleMask(Mask) &&
9580 "This is only useful with multiple inputs.");
9582 int Size = Mask.size();
9583 int LaneSize = 128 / VT.getScalarSizeInBits();
9584 int NumLanes = Size / LaneSize;
9585 assert(NumLanes > 1 && "Only handles 256-bit and wider shuffles.");
9587 // See if we can build a hypothetical 128-bit lane-fixing shuffle mask. Also
9588 // check whether the in-128-bit lane shuffles share a repeating pattern.
9589 SmallVector<int, 4> Lanes;
9590 Lanes.resize(NumLanes, -1);
9591 SmallVector<int, 4> InLaneMask;
9592 InLaneMask.resize(LaneSize, -1);
9593 for (int i = 0; i < Size; ++i) {
9597 int j = i / LaneSize;
9600 // First entry we've seen for this lane.
9601 Lanes[j] = Mask[i] / LaneSize;
9602 } else if (Lanes[j] != Mask[i] / LaneSize) {
9603 // This doesn't match the lane selected previously!
9607 // Check that within each lane we have a consistent shuffle mask.
9608 int k = i % LaneSize;
9609 if (InLaneMask[k] < 0) {
9610 InLaneMask[k] = Mask[i] % LaneSize;
9611 } else if (InLaneMask[k] != Mask[i] % LaneSize) {
9612 // This doesn't fit a repeating in-lane mask.
9617 // First shuffle the lanes into place.
9618 MVT LaneVT = MVT::getVectorVT(VT.isFloatingPoint() ? MVT::f64 : MVT::i64,
9619 VT.getSizeInBits() / 64);
9620 SmallVector<int, 8> LaneMask;
9621 LaneMask.resize(NumLanes * 2, -1);
9622 for (int i = 0; i < NumLanes; ++i)
9623 if (Lanes[i] >= 0) {
9624 LaneMask[2 * i + 0] = 2*Lanes[i] + 0;
9625 LaneMask[2 * i + 1] = 2*Lanes[i] + 1;
9628 V1 = DAG.getBitcast(LaneVT, V1);
9629 V2 = DAG.getBitcast(LaneVT, V2);
9630 SDValue LaneShuffle = DAG.getVectorShuffle(LaneVT, DL, V1, V2, LaneMask);
9632 // Cast it back to the type we actually want.
9633 LaneShuffle = DAG.getBitcast(VT, LaneShuffle);
9635 // Now do a simple shuffle that isn't lane crossing.
9636 SmallVector<int, 8> NewMask;
9637 NewMask.resize(Size, -1);
9638 for (int i = 0; i < Size; ++i)
9640 NewMask[i] = (i / LaneSize) * LaneSize + Mask[i] % LaneSize;
9641 assert(!is128BitLaneCrossingShuffleMask(VT, NewMask) &&
9642 "Must not introduce lane crosses at this point!");
9644 return DAG.getVectorShuffle(VT, DL, LaneShuffle, DAG.getUNDEF(VT), NewMask);
9647 /// \brief Test whether the specified input (0 or 1) is in-place blended by the
9650 /// This returns true if the elements from a particular input are already in the
9651 /// slot required by the given mask and require no permutation.
9652 static bool isShuffleMaskInputInPlace(int Input, ArrayRef<int> Mask) {
9653 assert((Input == 0 || Input == 1) && "Only two inputs to shuffles.");
9654 int Size = Mask.size();
9655 for (int i = 0; i < Size; ++i)
9656 if (Mask[i] >= 0 && Mask[i] / Size == Input && Mask[i] % Size != i)
9662 static SDValue lowerVectorShuffleWithSHUFPD(SDLoc DL, MVT VT,
9663 ArrayRef<int> Mask, SDValue V1,
9664 SDValue V2, SelectionDAG &DAG) {
9666 // Mask for V8F64: 0/1, 8/9, 2/3, 10/11, 4/5, ..
9667 // Mask for V4F64; 0/1, 4/5, 2/3, 6/7..
9668 assert(VT.getScalarSizeInBits() == 64 && "Unexpected data type for VSHUFPD");
9669 int NumElts = VT.getVectorNumElements();
9670 bool ShufpdMask = true;
9671 bool CommutableMask = true;
9672 unsigned Immediate = 0;
9673 for (int i = 0; i < NumElts; ++i) {
9676 int Val = (i & 6) + NumElts * (i & 1);
9677 int CommutVal = (i & 0xe) + NumElts * ((i & 1)^1);
9678 if (Mask[i] < Val || Mask[i] > Val + 1)
9680 if (Mask[i] < CommutVal || Mask[i] > CommutVal + 1)
9681 CommutableMask = false;
9682 Immediate |= (Mask[i] % 2) << i;
9685 return DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
9686 DAG.getConstant(Immediate, DL, MVT::i8));
9688 return DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
9689 DAG.getConstant(Immediate, DL, MVT::i8));
9693 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
9695 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
9696 /// isn't available.
9697 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9698 const X86Subtarget *Subtarget,
9699 SelectionDAG &DAG) {
9701 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9702 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9703 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9704 ArrayRef<int> Mask = SVOp->getMask();
9705 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9707 SmallVector<int, 4> WidenedMask;
9708 if (canWidenShuffleElements(Mask, WidenedMask))
9709 return lowerV2X128VectorShuffle(DL, MVT::v4f64, V1, V2, Mask, Subtarget,
9712 if (isSingleInputShuffleMask(Mask)) {
9713 // Check for being able to broadcast a single element.
9714 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f64, V1,
9715 Mask, Subtarget, DAG))
9718 // Use low duplicate instructions for masks that match their pattern.
9719 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
9720 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v4f64, V1);
9722 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
9723 // Non-half-crossing single input shuffles can be lowerid with an
9724 // interleaved permutation.
9725 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
9726 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
9727 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
9728 DAG.getConstant(VPERMILPMask, DL, MVT::i8));
9731 // With AVX2 we have direct support for this permutation.
9732 if (Subtarget->hasAVX2())
9733 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
9734 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
9736 // Otherwise, fall back.
9737 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
9741 // X86 has dedicated unpack instructions that can handle specific blend
9742 // operations: UNPCKH and UNPCKL.
9743 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 2, 6}))
9744 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
9745 if (isShuffleEquivalent(V1, V2, Mask, {1, 5, 3, 7}))
9746 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
9747 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 6, 2}))
9748 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V2, V1);
9749 if (isShuffleEquivalent(V1, V2, Mask, {5, 1, 7, 3}))
9750 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V2, V1);
9752 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
9756 // Check if the blend happens to exactly fit that of SHUFPD.
9758 lowerVectorShuffleWithSHUFPD(DL, MVT::v4f64, Mask, V1, V2, DAG))
9761 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9762 // shuffle. However, if we have AVX2 and either inputs are already in place,
9763 // we will be able to shuffle even across lanes the other input in a single
9764 // instruction so skip this pattern.
9765 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
9766 isShuffleMaskInputInPlace(1, Mask))))
9767 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9768 DL, MVT::v4f64, V1, V2, Mask, Subtarget, DAG))
9771 // If we have AVX2 then we always want to lower with a blend because an v4 we
9772 // can fully permute the elements.
9773 if (Subtarget->hasAVX2())
9774 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
9777 // Otherwise fall back on generic lowering.
9778 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v4f64, V1, V2, Mask, DAG);
9781 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
9783 /// This routine is only called when we have AVX2 and thus a reasonable
9784 /// instruction set for v4i64 shuffling..
9785 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9786 const X86Subtarget *Subtarget,
9787 SelectionDAG &DAG) {
9789 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9790 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9791 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9792 ArrayRef<int> Mask = SVOp->getMask();
9793 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9794 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
9796 SmallVector<int, 4> WidenedMask;
9797 if (canWidenShuffleElements(Mask, WidenedMask))
9798 return lowerV2X128VectorShuffle(DL, MVT::v4i64, V1, V2, Mask, Subtarget,
9801 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
9805 // Check for being able to broadcast a single element.
9806 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i64, V1,
9807 Mask, Subtarget, DAG))
9810 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
9811 // use lower latency instructions that will operate on both 128-bit lanes.
9812 SmallVector<int, 2> RepeatedMask;
9813 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
9814 if (isSingleInputShuffleMask(Mask)) {
9815 int PSHUFDMask[] = {-1, -1, -1, -1};
9816 for (int i = 0; i < 2; ++i)
9817 if (RepeatedMask[i] >= 0) {
9818 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
9819 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
9821 return DAG.getBitcast(
9823 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
9824 DAG.getBitcast(MVT::v8i32, V1),
9825 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
9829 // AVX2 provides a direct instruction for permuting a single input across
9831 if (isSingleInputShuffleMask(Mask))
9832 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
9833 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
9835 // Try to use shift instructions.
9837 lowerVectorShuffleAsShift(DL, MVT::v4i64, V1, V2, Mask, DAG))
9840 // Use dedicated unpack instructions for masks that match their pattern.
9841 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 2, 6}))
9842 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V1, V2);
9843 if (isShuffleEquivalent(V1, V2, Mask, {1, 5, 3, 7}))
9844 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V1, V2);
9845 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 6, 2}))
9846 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V2, V1);
9847 if (isShuffleEquivalent(V1, V2, Mask, {5, 1, 7, 3}))
9848 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V2, V1);
9850 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9851 // shuffle. However, if we have AVX2 and either inputs are already in place,
9852 // we will be able to shuffle even across lanes the other input in a single
9853 // instruction so skip this pattern.
9854 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
9855 isShuffleMaskInputInPlace(1, Mask))))
9856 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9857 DL, MVT::v4i64, V1, V2, Mask, Subtarget, DAG))
9860 // Otherwise fall back on generic blend lowering.
9861 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
9865 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
9867 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
9868 /// isn't available.
9869 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9870 const X86Subtarget *Subtarget,
9871 SelectionDAG &DAG) {
9873 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9874 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9875 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9876 ArrayRef<int> Mask = SVOp->getMask();
9877 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9879 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
9883 // Check for being able to broadcast a single element.
9884 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8f32, V1,
9885 Mask, Subtarget, DAG))
9888 // If the shuffle mask is repeated in each 128-bit lane, we have many more
9889 // options to efficiently lower the shuffle.
9890 SmallVector<int, 4> RepeatedMask;
9891 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
9892 assert(RepeatedMask.size() == 4 &&
9893 "Repeated masks must be half the mask width!");
9895 // Use even/odd duplicate instructions for masks that match their pattern.
9896 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2, 4, 4, 6, 6}))
9897 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v8f32, V1);
9898 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3, 5, 5, 7, 7}))
9899 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v8f32, V1);
9901 if (isSingleInputShuffleMask(Mask))
9902 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
9903 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
9905 // Use dedicated unpack instructions for masks that match their pattern.
9906 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 4, 12, 5, 13}))
9907 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V1, V2);
9908 if (isShuffleEquivalent(V1, V2, Mask, {2, 10, 3, 11, 6, 14, 7, 15}))
9909 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V1, V2);
9910 if (isShuffleEquivalent(V1, V2, Mask, {8, 0, 9, 1, 12, 4, 13, 5}))
9911 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V2, V1);
9912 if (isShuffleEquivalent(V1, V2, Mask, {10, 2, 11, 3, 14, 6, 15, 7}))
9913 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V2, V1);
9915 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
9916 // have already handled any direct blends. We also need to squash the
9917 // repeated mask into a simulated v4f32 mask.
9918 for (int i = 0; i < 4; ++i)
9919 if (RepeatedMask[i] >= 8)
9920 RepeatedMask[i] -= 4;
9921 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
9924 // If we have a single input shuffle with different shuffle patterns in the
9925 // two 128-bit lanes use the variable mask to VPERMILPS.
9926 if (isSingleInputShuffleMask(Mask)) {
9927 SDValue VPermMask[8];
9928 for (int i = 0; i < 8; ++i)
9929 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
9930 : DAG.getConstant(Mask[i], DL, MVT::i32);
9931 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
9933 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
9934 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
9936 if (Subtarget->hasAVX2())
9938 X86ISD::VPERMV, DL, MVT::v8f32,
9939 DAG.getBitcast(MVT::v8f32, DAG.getNode(ISD::BUILD_VECTOR, DL,
9940 MVT::v8i32, VPermMask)),
9943 // Otherwise, fall back.
9944 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
9948 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9950 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9951 DL, MVT::v8f32, V1, V2, Mask, Subtarget, DAG))
9954 // If we have AVX2 then we always want to lower with a blend because at v8 we
9955 // can fully permute the elements.
9956 if (Subtarget->hasAVX2())
9957 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
9960 // Otherwise fall back on generic lowering.
9961 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v8f32, V1, V2, Mask, DAG);
9964 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
9966 /// This routine is only called when we have AVX2 and thus a reasonable
9967 /// instruction set for v8i32 shuffling..
9968 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9969 const X86Subtarget *Subtarget,
9970 SelectionDAG &DAG) {
9972 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
9973 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
9974 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9975 ArrayRef<int> Mask = SVOp->getMask();
9976 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9977 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
9979 // Whenever we can lower this as a zext, that instruction is strictly faster
9980 // than any alternative. It also allows us to fold memory operands into the
9981 // shuffle in many cases.
9982 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v8i32, V1, V2,
9983 Mask, Subtarget, DAG))
9986 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
9990 // Check for being able to broadcast a single element.
9991 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i32, V1,
9992 Mask, Subtarget, DAG))
9995 // If the shuffle mask is repeated in each 128-bit lane we can use more
9996 // efficient instructions that mirror the shuffles across the two 128-bit
9998 SmallVector<int, 4> RepeatedMask;
9999 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
10000 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
10001 if (isSingleInputShuffleMask(Mask))
10002 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
10003 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
10005 // Use dedicated unpack instructions for masks that match their pattern.
10006 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 4, 12, 5, 13}))
10007 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V1, V2);
10008 if (isShuffleEquivalent(V1, V2, Mask, {2, 10, 3, 11, 6, 14, 7, 15}))
10009 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V1, V2);
10010 if (isShuffleEquivalent(V1, V2, Mask, {8, 0, 9, 1, 12, 4, 13, 5}))
10011 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V2, V1);
10012 if (isShuffleEquivalent(V1, V2, Mask, {10, 2, 11, 3, 14, 6, 15, 7}))
10013 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V2, V1);
10016 // Try to use shift instructions.
10017 if (SDValue Shift =
10018 lowerVectorShuffleAsShift(DL, MVT::v8i32, V1, V2, Mask, DAG))
10021 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10022 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10025 // If the shuffle patterns aren't repeated but it is a single input, directly
10026 // generate a cross-lane VPERMD instruction.
10027 if (isSingleInputShuffleMask(Mask)) {
10028 SDValue VPermMask[8];
10029 for (int i = 0; i < 8; ++i)
10030 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10031 : DAG.getConstant(Mask[i], DL, MVT::i32);
10032 return DAG.getNode(
10033 X86ISD::VPERMV, DL, MVT::v8i32,
10034 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
10037 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10039 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10040 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10043 // Otherwise fall back on generic blend lowering.
10044 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
10048 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
10050 /// This routine is only called when we have AVX2 and thus a reasonable
10051 /// instruction set for v16i16 shuffling..
10052 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10053 const X86Subtarget *Subtarget,
10054 SelectionDAG &DAG) {
10056 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10057 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10058 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10059 ArrayRef<int> Mask = SVOp->getMask();
10060 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10061 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
10063 // Whenever we can lower this as a zext, that instruction is strictly faster
10064 // than any alternative. It also allows us to fold memory operands into the
10065 // shuffle in many cases.
10066 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v16i16, V1, V2,
10067 Mask, Subtarget, DAG))
10070 // Check for being able to broadcast a single element.
10071 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i16, V1,
10072 Mask, Subtarget, DAG))
10075 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
10079 // Use dedicated unpack instructions for masks that match their pattern.
10080 if (isShuffleEquivalent(V1, V2, Mask,
10081 {// First 128-bit lane:
10082 0, 16, 1, 17, 2, 18, 3, 19,
10083 // Second 128-bit lane:
10084 8, 24, 9, 25, 10, 26, 11, 27}))
10085 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i16, V1, V2);
10086 if (isShuffleEquivalent(V1, V2, Mask,
10087 {// First 128-bit lane:
10088 4, 20, 5, 21, 6, 22, 7, 23,
10089 // Second 128-bit lane:
10090 12, 28, 13, 29, 14, 30, 15, 31}))
10091 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i16, V1, V2);
10093 // Try to use shift instructions.
10094 if (SDValue Shift =
10095 lowerVectorShuffleAsShift(DL, MVT::v16i16, V1, V2, Mask, DAG))
10098 // Try to use byte rotation instructions.
10099 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10100 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10103 if (isSingleInputShuffleMask(Mask)) {
10104 // There are no generalized cross-lane shuffle operations available on i16
10106 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
10107 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
10110 SmallVector<int, 8> RepeatedMask;
10111 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
10112 // As this is a single-input shuffle, the repeated mask should be
10113 // a strictly valid v8i16 mask that we can pass through to the v8i16
10114 // lowering to handle even the v16 case.
10115 return lowerV8I16GeneralSingleInputVectorShuffle(
10116 DL, MVT::v16i16, V1, RepeatedMask, Subtarget, DAG);
10119 SDValue PSHUFBMask[32];
10120 for (int i = 0; i < 16; ++i) {
10121 if (Mask[i] == -1) {
10122 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
10126 int M = i < 8 ? Mask[i] : Mask[i] - 8;
10127 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
10128 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, DL, MVT::i8);
10129 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, DL, MVT::i8);
10131 return DAG.getBitcast(MVT::v16i16,
10132 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8,
10133 DAG.getBitcast(MVT::v32i8, V1),
10134 DAG.getNode(ISD::BUILD_VECTOR, DL,
10135 MVT::v32i8, PSHUFBMask)));
10138 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10140 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10141 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10144 // Otherwise fall back on generic lowering.
10145 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v16i16, V1, V2, Mask, DAG);
10148 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
10150 /// This routine is only called when we have AVX2 and thus a reasonable
10151 /// instruction set for v32i8 shuffling..
10152 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10153 const X86Subtarget *Subtarget,
10154 SelectionDAG &DAG) {
10156 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10157 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10158 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10159 ArrayRef<int> Mask = SVOp->getMask();
10160 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10161 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
10163 // Whenever we can lower this as a zext, that instruction is strictly faster
10164 // than any alternative. It also allows us to fold memory operands into the
10165 // shuffle in many cases.
10166 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v32i8, V1, V2,
10167 Mask, Subtarget, DAG))
10170 // Check for being able to broadcast a single element.
10171 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v32i8, V1,
10172 Mask, Subtarget, DAG))
10175 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
10179 // Use dedicated unpack instructions for masks that match their pattern.
10180 // Note that these are repeated 128-bit lane unpacks, not unpacks across all
10182 if (isShuffleEquivalent(
10184 {// First 128-bit lane:
10185 0, 32, 1, 33, 2, 34, 3, 35, 4, 36, 5, 37, 6, 38, 7, 39,
10186 // Second 128-bit lane:
10187 16, 48, 17, 49, 18, 50, 19, 51, 20, 52, 21, 53, 22, 54, 23, 55}))
10188 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v32i8, V1, V2);
10189 if (isShuffleEquivalent(
10191 {// First 128-bit lane:
10192 8, 40, 9, 41, 10, 42, 11, 43, 12, 44, 13, 45, 14, 46, 15, 47,
10193 // Second 128-bit lane:
10194 24, 56, 25, 57, 26, 58, 27, 59, 28, 60, 29, 61, 30, 62, 31, 63}))
10195 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v32i8, V1, V2);
10197 // Try to use shift instructions.
10198 if (SDValue Shift =
10199 lowerVectorShuffleAsShift(DL, MVT::v32i8, V1, V2, Mask, DAG))
10202 // Try to use byte rotation instructions.
10203 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10204 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10207 if (isSingleInputShuffleMask(Mask)) {
10208 // There are no generalized cross-lane shuffle operations available on i8
10210 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
10211 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
10214 SDValue PSHUFBMask[32];
10215 for (int i = 0; i < 32; ++i)
10218 ? DAG.getUNDEF(MVT::i8)
10219 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, DL,
10222 return DAG.getNode(
10223 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
10224 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
10227 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10229 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10230 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10233 // Otherwise fall back on generic lowering.
10234 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v32i8, V1, V2, Mask, DAG);
10237 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
10239 /// This routine either breaks down the specific type of a 256-bit x86 vector
10240 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
10241 /// together based on the available instructions.
10242 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10243 MVT VT, const X86Subtarget *Subtarget,
10244 SelectionDAG &DAG) {
10246 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10247 ArrayRef<int> Mask = SVOp->getMask();
10249 // If we have a single input to the zero element, insert that into V1 if we
10250 // can do so cheaply.
10251 int NumElts = VT.getVectorNumElements();
10252 int NumV2Elements = std::count_if(Mask.begin(), Mask.end(), [NumElts](int M) {
10253 return M >= NumElts;
10256 if (NumV2Elements == 1 && Mask[0] >= NumElts)
10257 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
10258 DL, VT, V1, V2, Mask, Subtarget, DAG))
10261 // There is a really nice hard cut-over between AVX1 and AVX2 that means we can
10262 // check for those subtargets here and avoid much of the subtarget querying in
10263 // the per-vector-type lowering routines. With AVX1 we have essentially *zero*
10264 // ability to manipulate a 256-bit vector with integer types. Since we'll use
10265 // floating point types there eventually, just immediately cast everything to
10266 // a float and operate entirely in that domain.
10267 if (VT.isInteger() && !Subtarget->hasAVX2()) {
10268 int ElementBits = VT.getScalarSizeInBits();
10269 if (ElementBits < 32)
10270 // No floating point type available, decompose into 128-bit vectors.
10271 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10273 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
10274 VT.getVectorNumElements());
10275 V1 = DAG.getBitcast(FpVT, V1);
10276 V2 = DAG.getBitcast(FpVT, V2);
10277 return DAG.getBitcast(VT, DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
10280 switch (VT.SimpleTy) {
10282 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10284 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10286 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10288 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10290 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10292 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10295 llvm_unreachable("Not a valid 256-bit x86 vector type!");
10299 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
10300 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10301 const X86Subtarget *Subtarget,
10302 SelectionDAG &DAG) {
10304 assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10305 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10306 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10307 ArrayRef<int> Mask = SVOp->getMask();
10308 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10310 // X86 has dedicated unpack instructions that can handle specific blend
10311 // operations: UNPCKH and UNPCKL.
10312 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 2, 10, 4, 12, 6, 14}))
10313 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f64, V1, V2);
10314 if (isShuffleEquivalent(V1, V2, Mask, {1, 9, 3, 11, 5, 13, 7, 15}))
10315 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f64, V1, V2);
10317 // FIXME: Implement direct support for this type!
10318 return splitAndLowerVectorShuffle(DL, MVT::v8f64, V1, V2, Mask, DAG);
10321 /// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
10322 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10323 const X86Subtarget *Subtarget,
10324 SelectionDAG &DAG) {
10326 assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10327 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10328 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10329 ArrayRef<int> Mask = SVOp->getMask();
10330 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10332 // Use dedicated unpack instructions for masks that match their pattern.
10333 if (isShuffleEquivalent(V1, V2, Mask,
10334 {// First 128-bit lane.
10335 0, 16, 1, 17, 4, 20, 5, 21,
10336 // Second 128-bit lane.
10337 8, 24, 9, 25, 12, 28, 13, 29}))
10338 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16f32, V1, V2);
10339 if (isShuffleEquivalent(V1, V2, Mask,
10340 {// First 128-bit lane.
10341 2, 18, 3, 19, 6, 22, 7, 23,
10342 // Second 128-bit lane.
10343 10, 26, 11, 27, 14, 30, 15, 31}))
10344 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16f32, V1, V2);
10346 // FIXME: Implement direct support for this type!
10347 return splitAndLowerVectorShuffle(DL, MVT::v16f32, V1, V2, Mask, DAG);
10350 /// \brief Handle lowering of 8-lane 64-bit integer shuffles.
10351 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10352 const X86Subtarget *Subtarget,
10353 SelectionDAG &DAG) {
10355 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10356 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10357 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10358 ArrayRef<int> Mask = SVOp->getMask();
10359 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10361 // X86 has dedicated unpack instructions that can handle specific blend
10362 // operations: UNPCKH and UNPCKL.
10363 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 2, 10, 4, 12, 6, 14}))
10364 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i64, V1, V2);
10365 if (isShuffleEquivalent(V1, V2, Mask, {1, 9, 3, 11, 5, 13, 7, 15}))
10366 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i64, V1, V2);
10368 // FIXME: Implement direct support for this type!
10369 return splitAndLowerVectorShuffle(DL, MVT::v8i64, V1, V2, Mask, DAG);
10372 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
10373 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10374 const X86Subtarget *Subtarget,
10375 SelectionDAG &DAG) {
10377 assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10378 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10379 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10380 ArrayRef<int> Mask = SVOp->getMask();
10381 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10383 // Use dedicated unpack instructions for masks that match their pattern.
10384 if (isShuffleEquivalent(V1, V2, Mask,
10385 {// First 128-bit lane.
10386 0, 16, 1, 17, 4, 20, 5, 21,
10387 // Second 128-bit lane.
10388 8, 24, 9, 25, 12, 28, 13, 29}))
10389 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i32, V1, V2);
10390 if (isShuffleEquivalent(V1, V2, Mask,
10391 {// First 128-bit lane.
10392 2, 18, 3, 19, 6, 22, 7, 23,
10393 // Second 128-bit lane.
10394 10, 26, 11, 27, 14, 30, 15, 31}))
10395 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i32, V1, V2);
10397 // FIXME: Implement direct support for this type!
10398 return splitAndLowerVectorShuffle(DL, MVT::v16i32, V1, V2, Mask, DAG);
10401 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
10402 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10403 const X86Subtarget *Subtarget,
10404 SelectionDAG &DAG) {
10406 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10407 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10408 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10409 ArrayRef<int> Mask = SVOp->getMask();
10410 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10411 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
10413 // FIXME: Implement direct support for this type!
10414 return splitAndLowerVectorShuffle(DL, MVT::v32i16, V1, V2, Mask, DAG);
10417 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
10418 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10419 const X86Subtarget *Subtarget,
10420 SelectionDAG &DAG) {
10422 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10423 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10424 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10425 ArrayRef<int> Mask = SVOp->getMask();
10426 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
10427 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
10429 // FIXME: Implement direct support for this type!
10430 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
10433 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
10435 /// This routine either breaks down the specific type of a 512-bit x86 vector
10436 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
10437 /// together based on the available instructions.
10438 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10439 MVT VT, const X86Subtarget *Subtarget,
10440 SelectionDAG &DAG) {
10442 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10443 ArrayRef<int> Mask = SVOp->getMask();
10444 assert(Subtarget->hasAVX512() &&
10445 "Cannot lower 512-bit vectors w/ basic ISA!");
10447 // Check for being able to broadcast a single element.
10448 if (SDValue Broadcast =
10449 lowerVectorShuffleAsBroadcast(DL, VT, V1, Mask, Subtarget, DAG))
10452 // Dispatch to each element type for lowering. If we don't have supprot for
10453 // specific element type shuffles at 512 bits, immediately split them and
10454 // lower them. Each lowering routine of a given type is allowed to assume that
10455 // the requisite ISA extensions for that element type are available.
10456 switch (VT.SimpleTy) {
10458 return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10460 return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10462 return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10464 return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10466 if (Subtarget->hasBWI())
10467 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10470 if (Subtarget->hasBWI())
10471 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10475 llvm_unreachable("Not a valid 512-bit x86 vector type!");
10478 // Otherwise fall back on splitting.
10479 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10482 /// \brief Top-level lowering for x86 vector shuffles.
10484 /// This handles decomposition, canonicalization, and lowering of all x86
10485 /// vector shuffles. Most of the specific lowering strategies are encapsulated
10486 /// above in helper routines. The canonicalization attempts to widen shuffles
10487 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
10488 /// s.t. only one of the two inputs needs to be tested, etc.
10489 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
10490 SelectionDAG &DAG) {
10491 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10492 ArrayRef<int> Mask = SVOp->getMask();
10493 SDValue V1 = Op.getOperand(0);
10494 SDValue V2 = Op.getOperand(1);
10495 MVT VT = Op.getSimpleValueType();
10496 int NumElements = VT.getVectorNumElements();
10499 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
10501 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
10502 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10503 if (V1IsUndef && V2IsUndef)
10504 return DAG.getUNDEF(VT);
10506 // When we create a shuffle node we put the UNDEF node to second operand,
10507 // but in some cases the first operand may be transformed to UNDEF.
10508 // In this case we should just commute the node.
10510 return DAG.getCommutedVectorShuffle(*SVOp);
10512 // Check for non-undef masks pointing at an undef vector and make the masks
10513 // undef as well. This makes it easier to match the shuffle based solely on
10517 if (M >= NumElements) {
10518 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
10519 for (int &M : NewMask)
10520 if (M >= NumElements)
10522 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
10525 // We actually see shuffles that are entirely re-arrangements of a set of
10526 // zero inputs. This mostly happens while decomposing complex shuffles into
10527 // simple ones. Directly lower these as a buildvector of zeros.
10528 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
10529 if (Zeroable.all())
10530 return getZeroVector(VT, Subtarget, DAG, dl);
10532 // Try to collapse shuffles into using a vector type with fewer elements but
10533 // wider element types. We cap this to not form integers or floating point
10534 // elements wider than 64 bits, but it might be interesting to form i128
10535 // integers to handle flipping the low and high halves of AVX 256-bit vectors.
10536 SmallVector<int, 16> WidenedMask;
10537 if (VT.getScalarSizeInBits() < 64 &&
10538 canWidenShuffleElements(Mask, WidenedMask)) {
10539 MVT NewEltVT = VT.isFloatingPoint()
10540 ? MVT::getFloatingPointVT(VT.getScalarSizeInBits() * 2)
10541 : MVT::getIntegerVT(VT.getScalarSizeInBits() * 2);
10542 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2);
10543 // Make sure that the new vector type is legal. For example, v2f64 isn't
10545 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) {
10546 V1 = DAG.getBitcast(NewVT, V1);
10547 V2 = DAG.getBitcast(NewVT, V2);
10548 return DAG.getBitcast(
10549 VT, DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
10553 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
10554 for (int M : SVOp->getMask())
10556 ++NumUndefElements;
10557 else if (M < NumElements)
10562 // Commute the shuffle as needed such that more elements come from V1 than
10563 // V2. This allows us to match the shuffle pattern strictly on how many
10564 // elements come from V1 without handling the symmetric cases.
10565 if (NumV2Elements > NumV1Elements)
10566 return DAG.getCommutedVectorShuffle(*SVOp);
10568 // When the number of V1 and V2 elements are the same, try to minimize the
10569 // number of uses of V2 in the low half of the vector. When that is tied,
10570 // ensure that the sum of indices for V1 is equal to or lower than the sum
10571 // indices for V2. When those are equal, try to ensure that the number of odd
10572 // indices for V1 is lower than the number of odd indices for V2.
10573 if (NumV1Elements == NumV2Elements) {
10574 int LowV1Elements = 0, LowV2Elements = 0;
10575 for (int M : SVOp->getMask().slice(0, NumElements / 2))
10576 if (M >= NumElements)
10580 if (LowV2Elements > LowV1Elements) {
10581 return DAG.getCommutedVectorShuffle(*SVOp);
10582 } else if (LowV2Elements == LowV1Elements) {
10583 int SumV1Indices = 0, SumV2Indices = 0;
10584 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10585 if (SVOp->getMask()[i] >= NumElements)
10587 else if (SVOp->getMask()[i] >= 0)
10589 if (SumV2Indices < SumV1Indices) {
10590 return DAG.getCommutedVectorShuffle(*SVOp);
10591 } else if (SumV2Indices == SumV1Indices) {
10592 int NumV1OddIndices = 0, NumV2OddIndices = 0;
10593 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10594 if (SVOp->getMask()[i] >= NumElements)
10595 NumV2OddIndices += i % 2;
10596 else if (SVOp->getMask()[i] >= 0)
10597 NumV1OddIndices += i % 2;
10598 if (NumV2OddIndices < NumV1OddIndices)
10599 return DAG.getCommutedVectorShuffle(*SVOp);
10604 // For each vector width, delegate to a specialized lowering routine.
10605 if (VT.getSizeInBits() == 128)
10606 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10608 if (VT.getSizeInBits() == 256)
10609 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10611 // Force AVX-512 vectors to be scalarized for now.
10612 // FIXME: Implement AVX-512 support!
10613 if (VT.getSizeInBits() == 512)
10614 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10616 llvm_unreachable("Unimplemented!");
10619 // This function assumes its argument is a BUILD_VECTOR of constants or
10620 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
10622 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
10623 unsigned &MaskValue) {
10625 unsigned NumElems = BuildVector->getNumOperands();
10626 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
10627 unsigned NumLanes = (NumElems - 1) / 8 + 1;
10628 unsigned NumElemsInLane = NumElems / NumLanes;
10630 // Blend for v16i16 should be symetric for the both lanes.
10631 for (unsigned i = 0; i < NumElemsInLane; ++i) {
10632 SDValue EltCond = BuildVector->getOperand(i);
10633 SDValue SndLaneEltCond =
10634 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
10636 int Lane1Cond = -1, Lane2Cond = -1;
10637 if (isa<ConstantSDNode>(EltCond))
10638 Lane1Cond = !isZero(EltCond);
10639 if (isa<ConstantSDNode>(SndLaneEltCond))
10640 Lane2Cond = !isZero(SndLaneEltCond);
10642 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
10643 // Lane1Cond != 0, means we want the first argument.
10644 // Lane1Cond == 0, means we want the second argument.
10645 // The encoding of this argument is 0 for the first argument, 1
10646 // for the second. Therefore, invert the condition.
10647 MaskValue |= !Lane1Cond << i;
10648 else if (Lane1Cond < 0)
10649 MaskValue |= !Lane2Cond << i;
10656 /// \brief Try to lower a VSELECT instruction to a vector shuffle.
10657 static SDValue lowerVSELECTtoVectorShuffle(SDValue Op,
10658 const X86Subtarget *Subtarget,
10659 SelectionDAG &DAG) {
10660 SDValue Cond = Op.getOperand(0);
10661 SDValue LHS = Op.getOperand(1);
10662 SDValue RHS = Op.getOperand(2);
10664 MVT VT = Op.getSimpleValueType();
10666 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
10668 auto *CondBV = cast<BuildVectorSDNode>(Cond);
10670 // Only non-legal VSELECTs reach this lowering, convert those into generic
10671 // shuffles and re-use the shuffle lowering path for blends.
10672 SmallVector<int, 32> Mask;
10673 for (int i = 0, Size = VT.getVectorNumElements(); i < Size; ++i) {
10674 SDValue CondElt = CondBV->getOperand(i);
10676 isa<ConstantSDNode>(CondElt) ? i + (isZero(CondElt) ? Size : 0) : -1);
10678 return DAG.getVectorShuffle(VT, dl, LHS, RHS, Mask);
10681 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
10682 // A vselect where all conditions and data are constants can be optimized into
10683 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
10684 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
10685 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
10686 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
10689 // Try to lower this to a blend-style vector shuffle. This can handle all
10690 // constant condition cases.
10691 if (SDValue BlendOp = lowerVSELECTtoVectorShuffle(Op, Subtarget, DAG))
10694 // Variable blends are only legal from SSE4.1 onward.
10695 if (!Subtarget->hasSSE41())
10698 // Only some types will be legal on some subtargets. If we can emit a legal
10699 // VSELECT-matching blend, return Op, and but if we need to expand, return
10701 switch (Op.getSimpleValueType().SimpleTy) {
10703 // Most of the vector types have blends past SSE4.1.
10707 // The byte blends for AVX vectors were introduced only in AVX2.
10708 if (Subtarget->hasAVX2())
10715 // AVX-512 BWI and VLX features support VSELECT with i16 elements.
10716 if (Subtarget->hasBWI() && Subtarget->hasVLX())
10719 // FIXME: We should custom lower this by fixing the condition and using i8
10725 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
10726 MVT VT = Op.getSimpleValueType();
10729 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
10732 if (VT.getSizeInBits() == 8) {
10733 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
10734 Op.getOperand(0), Op.getOperand(1));
10735 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
10736 DAG.getValueType(VT));
10737 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
10740 if (VT.getSizeInBits() == 16) {
10741 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10742 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
10744 return DAG.getNode(
10745 ISD::TRUNCATE, dl, MVT::i16,
10746 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
10747 DAG.getBitcast(MVT::v4i32, Op.getOperand(0)),
10748 Op.getOperand(1)));
10749 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
10750 Op.getOperand(0), Op.getOperand(1));
10751 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
10752 DAG.getValueType(VT));
10753 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
10756 if (VT == MVT::f32) {
10757 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
10758 // the result back to FR32 register. It's only worth matching if the
10759 // result has a single use which is a store or a bitcast to i32. And in
10760 // the case of a store, it's not worth it if the index is a constant 0,
10761 // because a MOVSSmr can be used instead, which is smaller and faster.
10762 if (!Op.hasOneUse())
10764 SDNode *User = *Op.getNode()->use_begin();
10765 if ((User->getOpcode() != ISD::STORE ||
10766 (isa<ConstantSDNode>(Op.getOperand(1)) &&
10767 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
10768 (User->getOpcode() != ISD::BITCAST ||
10769 User->getValueType(0) != MVT::i32))
10771 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
10772 DAG.getBitcast(MVT::v4i32, Op.getOperand(0)),
10774 return DAG.getBitcast(MVT::f32, Extract);
10777 if (VT == MVT::i32 || VT == MVT::i64) {
10778 // ExtractPS/pextrq works with constant index.
10779 if (isa<ConstantSDNode>(Op.getOperand(1)))
10785 /// Extract one bit from mask vector, like v16i1 or v8i1.
10786 /// AVX-512 feature.
10788 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
10789 SDValue Vec = Op.getOperand(0);
10791 MVT VecVT = Vec.getSimpleValueType();
10792 SDValue Idx = Op.getOperand(1);
10793 MVT EltVT = Op.getSimpleValueType();
10795 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
10796 assert((VecVT.getVectorNumElements() <= 16 || Subtarget->hasBWI()) &&
10797 "Unexpected vector type in ExtractBitFromMaskVector");
10799 // variable index can't be handled in mask registers,
10800 // extend vector to VR512
10801 if (!isa<ConstantSDNode>(Idx)) {
10802 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
10803 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
10804 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
10805 ExtVT.getVectorElementType(), Ext, Idx);
10806 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
10809 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10810 const TargetRegisterClass* rc = getRegClassFor(VecVT);
10811 if (!Subtarget->hasDQI() && (VecVT.getVectorNumElements() <= 8))
10812 rc = getRegClassFor(MVT::v16i1);
10813 unsigned MaxSift = rc->getSize()*8 - 1;
10814 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
10815 DAG.getConstant(MaxSift - IdxVal, dl, MVT::i8));
10816 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
10817 DAG.getConstant(MaxSift, dl, MVT::i8));
10818 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
10819 DAG.getIntPtrConstant(0, dl));
10823 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
10824 SelectionDAG &DAG) const {
10826 SDValue Vec = Op.getOperand(0);
10827 MVT VecVT = Vec.getSimpleValueType();
10828 SDValue Idx = Op.getOperand(1);
10830 if (Op.getSimpleValueType() == MVT::i1)
10831 return ExtractBitFromMaskVector(Op, DAG);
10833 if (!isa<ConstantSDNode>(Idx)) {
10834 if (VecVT.is512BitVector() ||
10835 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
10836 VecVT.getVectorElementType().getSizeInBits() == 32)) {
10839 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
10840 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
10841 MaskEltVT.getSizeInBits());
10843 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
10844 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
10845 getZeroVector(MaskVT, Subtarget, DAG, dl),
10846 Idx, DAG.getConstant(0, dl, getPointerTy()));
10847 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
10848 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
10849 Perm, DAG.getConstant(0, dl, getPointerTy()));
10854 // If this is a 256-bit vector result, first extract the 128-bit vector and
10855 // then extract the element from the 128-bit vector.
10856 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
10858 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10859 // Get the 128-bit vector.
10860 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
10861 MVT EltVT = VecVT.getVectorElementType();
10863 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
10865 //if (IdxVal >= NumElems/2)
10866 // IdxVal -= NumElems/2;
10867 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
10868 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
10869 DAG.getConstant(IdxVal, dl, MVT::i32));
10872 assert(VecVT.is128BitVector() && "Unexpected vector length");
10874 if (Subtarget->hasSSE41())
10875 if (SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG))
10878 MVT VT = Op.getSimpleValueType();
10879 // TODO: handle v16i8.
10880 if (VT.getSizeInBits() == 16) {
10881 SDValue Vec = Op.getOperand(0);
10882 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10884 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
10885 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
10886 DAG.getBitcast(MVT::v4i32, Vec),
10887 Op.getOperand(1)));
10888 // Transform it so it match pextrw which produces a 32-bit result.
10889 MVT EltVT = MVT::i32;
10890 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
10891 Op.getOperand(0), Op.getOperand(1));
10892 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
10893 DAG.getValueType(VT));
10894 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
10897 if (VT.getSizeInBits() == 32) {
10898 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10902 // SHUFPS the element to the lowest double word, then movss.
10903 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
10904 MVT VVT = Op.getOperand(0).getSimpleValueType();
10905 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
10906 DAG.getUNDEF(VVT), Mask);
10907 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
10908 DAG.getIntPtrConstant(0, dl));
10911 if (VT.getSizeInBits() == 64) {
10912 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
10913 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
10914 // to match extract_elt for f64.
10915 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10919 // UNPCKHPD the element to the lowest double word, then movsd.
10920 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
10921 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
10922 int Mask[2] = { 1, -1 };
10923 MVT VVT = Op.getOperand(0).getSimpleValueType();
10924 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
10925 DAG.getUNDEF(VVT), Mask);
10926 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
10927 DAG.getIntPtrConstant(0, dl));
10933 /// Insert one bit to mask vector, like v16i1 or v8i1.
10934 /// AVX-512 feature.
10936 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
10938 SDValue Vec = Op.getOperand(0);
10939 SDValue Elt = Op.getOperand(1);
10940 SDValue Idx = Op.getOperand(2);
10941 MVT VecVT = Vec.getSimpleValueType();
10943 if (!isa<ConstantSDNode>(Idx)) {
10944 // Non constant index. Extend source and destination,
10945 // insert element and then truncate the result.
10946 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
10947 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
10948 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
10949 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
10950 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
10951 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
10954 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10955 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
10957 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
10958 DAG.getConstant(IdxVal, dl, MVT::i8));
10959 if (Vec.getOpcode() == ISD::UNDEF)
10961 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
10964 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
10965 SelectionDAG &DAG) const {
10966 MVT VT = Op.getSimpleValueType();
10967 MVT EltVT = VT.getVectorElementType();
10969 if (EltVT == MVT::i1)
10970 return InsertBitToMaskVector(Op, DAG);
10973 SDValue N0 = Op.getOperand(0);
10974 SDValue N1 = Op.getOperand(1);
10975 SDValue N2 = Op.getOperand(2);
10976 if (!isa<ConstantSDNode>(N2))
10978 auto *N2C = cast<ConstantSDNode>(N2);
10979 unsigned IdxVal = N2C->getZExtValue();
10981 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
10982 // into that, and then insert the subvector back into the result.
10983 if (VT.is256BitVector() || VT.is512BitVector()) {
10984 // With a 256-bit vector, we can insert into the zero element efficiently
10985 // using a blend if we have AVX or AVX2 and the right data type.
10986 if (VT.is256BitVector() && IdxVal == 0) {
10987 // TODO: It is worthwhile to cast integer to floating point and back
10988 // and incur a domain crossing penalty if that's what we'll end up
10989 // doing anyway after extracting to a 128-bit vector.
10990 if ((Subtarget->hasAVX() && (EltVT == MVT::f64 || EltVT == MVT::f32)) ||
10991 (Subtarget->hasAVX2() && EltVT == MVT::i32)) {
10992 SDValue N1Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, N1);
10993 N2 = DAG.getIntPtrConstant(1, dl);
10994 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1Vec, N2);
10998 // Get the desired 128-bit vector chunk.
10999 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
11001 // Insert the element into the desired chunk.
11002 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
11003 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
11005 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
11006 DAG.getConstant(IdxIn128, dl, MVT::i32));
11008 // Insert the changed part back into the bigger vector
11009 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
11011 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
11013 if (Subtarget->hasSSE41()) {
11014 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
11016 if (VT == MVT::v8i16) {
11017 Opc = X86ISD::PINSRW;
11019 assert(VT == MVT::v16i8);
11020 Opc = X86ISD::PINSRB;
11023 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
11025 if (N1.getValueType() != MVT::i32)
11026 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11027 if (N2.getValueType() != MVT::i32)
11028 N2 = DAG.getIntPtrConstant(IdxVal, dl);
11029 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
11032 if (EltVT == MVT::f32) {
11033 // Bits [7:6] of the constant are the source select. This will always be
11034 // zero here. The DAG Combiner may combine an extract_elt index into
11035 // these bits. For example (insert (extract, 3), 2) could be matched by
11036 // putting the '3' into bits [7:6] of X86ISD::INSERTPS.
11037 // Bits [5:4] of the constant are the destination select. This is the
11038 // value of the incoming immediate.
11039 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
11040 // combine either bitwise AND or insert of float 0.0 to set these bits.
11042 const Function *F = DAG.getMachineFunction().getFunction();
11043 bool MinSize = F->hasFnAttribute(Attribute::MinSize);
11044 if (IdxVal == 0 && (!MinSize || !MayFoldLoad(N1))) {
11045 // If this is an insertion of 32-bits into the low 32-bits of
11046 // a vector, we prefer to generate a blend with immediate rather
11047 // than an insertps. Blends are simpler operations in hardware and so
11048 // will always have equal or better performance than insertps.
11049 // But if optimizing for size and there's a load folding opportunity,
11050 // generate insertps because blendps does not have a 32-bit memory
11052 N2 = DAG.getIntPtrConstant(1, dl);
11053 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
11054 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1, N2);
11056 N2 = DAG.getIntPtrConstant(IdxVal << 4, dl);
11057 // Create this as a scalar to vector..
11058 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
11059 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
11062 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
11063 // PINSR* works with constant index.
11068 if (EltVT == MVT::i8)
11071 if (EltVT.getSizeInBits() == 16) {
11072 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
11073 // as its second argument.
11074 if (N1.getValueType() != MVT::i32)
11075 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11076 if (N2.getValueType() != MVT::i32)
11077 N2 = DAG.getIntPtrConstant(IdxVal, dl);
11078 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
11083 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
11085 MVT OpVT = Op.getSimpleValueType();
11087 // If this is a 256-bit vector result, first insert into a 128-bit
11088 // vector and then insert into the 256-bit vector.
11089 if (!OpVT.is128BitVector()) {
11090 // Insert into a 128-bit vector.
11091 unsigned SizeFactor = OpVT.getSizeInBits()/128;
11092 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
11093 OpVT.getVectorNumElements() / SizeFactor);
11095 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
11097 // Insert the 128-bit vector.
11098 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
11101 if (OpVT == MVT::v1i64 &&
11102 Op.getOperand(0).getValueType() == MVT::i64)
11103 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
11105 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
11106 assert(OpVT.is128BitVector() && "Expected an SSE type!");
11107 return DAG.getBitcast(
11108 OpVT, DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, AnyExt));
11111 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
11112 // a simple subregister reference or explicit instructions to grab
11113 // upper bits of a vector.
11114 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11115 SelectionDAG &DAG) {
11117 SDValue In = Op.getOperand(0);
11118 SDValue Idx = Op.getOperand(1);
11119 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11120 MVT ResVT = Op.getSimpleValueType();
11121 MVT InVT = In.getSimpleValueType();
11123 if (Subtarget->hasFp256()) {
11124 if (ResVT.is128BitVector() &&
11125 (InVT.is256BitVector() || InVT.is512BitVector()) &&
11126 isa<ConstantSDNode>(Idx)) {
11127 return Extract128BitVector(In, IdxVal, DAG, dl);
11129 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
11130 isa<ConstantSDNode>(Idx)) {
11131 return Extract256BitVector(In, IdxVal, DAG, dl);
11137 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
11138 // simple superregister reference or explicit instructions to insert
11139 // the upper bits of a vector.
11140 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11141 SelectionDAG &DAG) {
11142 if (!Subtarget->hasAVX())
11146 SDValue Vec = Op.getOperand(0);
11147 SDValue SubVec = Op.getOperand(1);
11148 SDValue Idx = Op.getOperand(2);
11150 if (!isa<ConstantSDNode>(Idx))
11153 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11154 MVT OpVT = Op.getSimpleValueType();
11155 MVT SubVecVT = SubVec.getSimpleValueType();
11157 // Fold two 16-byte subvector loads into one 32-byte load:
11158 // (insert_subvector (insert_subvector undef, (load addr), 0),
11159 // (load addr + 16), Elts/2)
11161 if ((IdxVal == OpVT.getVectorNumElements() / 2) &&
11162 Vec.getOpcode() == ISD::INSERT_SUBVECTOR &&
11163 OpVT.is256BitVector() && SubVecVT.is128BitVector() &&
11164 !Subtarget->isUnalignedMem32Slow()) {
11165 SDValue SubVec2 = Vec.getOperand(1);
11166 if (auto *Idx2 = dyn_cast<ConstantSDNode>(Vec.getOperand(2))) {
11167 if (Idx2->getZExtValue() == 0) {
11168 SDValue Ops[] = { SubVec2, SubVec };
11169 if (SDValue Ld = EltsFromConsecutiveLoads(OpVT, Ops, dl, DAG, false))
11175 if ((OpVT.is256BitVector() || OpVT.is512BitVector()) &&
11176 SubVecVT.is128BitVector())
11177 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
11179 if (OpVT.is512BitVector() && SubVecVT.is256BitVector())
11180 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
11182 if (OpVT.getVectorElementType() == MVT::i1) {
11183 if (IdxVal == 0 && Vec.getOpcode() == ISD::UNDEF) // the operation is legal
11185 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
11186 SDValue Undef = DAG.getUNDEF(OpVT);
11187 unsigned NumElems = OpVT.getVectorNumElements();
11188 SDValue ShiftBits = DAG.getConstant(NumElems/2, dl, MVT::i8);
11190 if (IdxVal == OpVT.getVectorNumElements() / 2) {
11191 // Zero upper bits of the Vec
11192 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
11193 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
11195 SDValue Vec2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef,
11197 Vec2 = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec2, ShiftBits);
11198 return DAG.getNode(ISD::OR, dl, OpVT, Vec, Vec2);
11201 SDValue Vec2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef,
11203 // Zero upper bits of the Vec2
11204 Vec2 = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec2, ShiftBits);
11205 Vec2 = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec2, ShiftBits);
11206 // Zero lower bits of the Vec
11207 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
11208 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
11209 // Merge them together
11210 return DAG.getNode(ISD::OR, dl, OpVT, Vec, Vec2);
11216 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
11217 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
11218 // one of the above mentioned nodes. It has to be wrapped because otherwise
11219 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
11220 // be used to form addressing mode. These wrapped nodes will be selected
11223 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
11224 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
11226 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11227 // global base reg.
11228 unsigned char OpFlag = 0;
11229 unsigned WrapperKind = X86ISD::Wrapper;
11230 CodeModel::Model M = DAG.getTarget().getCodeModel();
11232 if (Subtarget->isPICStyleRIPRel() &&
11233 (M == CodeModel::Small || M == CodeModel::Kernel))
11234 WrapperKind = X86ISD::WrapperRIP;
11235 else if (Subtarget->isPICStyleGOT())
11236 OpFlag = X86II::MO_GOTOFF;
11237 else if (Subtarget->isPICStyleStubPIC())
11238 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11240 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
11241 CP->getAlignment(),
11242 CP->getOffset(), OpFlag);
11244 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
11245 // With PIC, the address is actually $g + Offset.
11247 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11248 DAG.getNode(X86ISD::GlobalBaseReg,
11249 SDLoc(), getPointerTy()),
11256 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
11257 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
11259 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11260 // global base reg.
11261 unsigned char OpFlag = 0;
11262 unsigned WrapperKind = X86ISD::Wrapper;
11263 CodeModel::Model M = DAG.getTarget().getCodeModel();
11265 if (Subtarget->isPICStyleRIPRel() &&
11266 (M == CodeModel::Small || M == CodeModel::Kernel))
11267 WrapperKind = X86ISD::WrapperRIP;
11268 else if (Subtarget->isPICStyleGOT())
11269 OpFlag = X86II::MO_GOTOFF;
11270 else if (Subtarget->isPICStyleStubPIC())
11271 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11273 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
11276 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
11278 // With PIC, the address is actually $g + Offset.
11280 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11281 DAG.getNode(X86ISD::GlobalBaseReg,
11282 SDLoc(), getPointerTy()),
11289 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
11290 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
11292 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11293 // global base reg.
11294 unsigned char OpFlag = 0;
11295 unsigned WrapperKind = X86ISD::Wrapper;
11296 CodeModel::Model M = DAG.getTarget().getCodeModel();
11298 if (Subtarget->isPICStyleRIPRel() &&
11299 (M == CodeModel::Small || M == CodeModel::Kernel)) {
11300 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
11301 OpFlag = X86II::MO_GOTPCREL;
11302 WrapperKind = X86ISD::WrapperRIP;
11303 } else if (Subtarget->isPICStyleGOT()) {
11304 OpFlag = X86II::MO_GOT;
11305 } else if (Subtarget->isPICStyleStubPIC()) {
11306 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
11307 } else if (Subtarget->isPICStyleStubNoDynamic()) {
11308 OpFlag = X86II::MO_DARWIN_NONLAZY;
11311 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
11314 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
11316 // With PIC, the address is actually $g + Offset.
11317 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
11318 !Subtarget->is64Bit()) {
11319 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11320 DAG.getNode(X86ISD::GlobalBaseReg,
11321 SDLoc(), getPointerTy()),
11325 // For symbols that require a load from a stub to get the address, emit the
11327 if (isGlobalStubReference(OpFlag))
11328 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
11329 MachinePointerInfo::getGOT(), false, false, false, 0);
11335 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
11336 // Create the TargetBlockAddressAddress node.
11337 unsigned char OpFlags =
11338 Subtarget->ClassifyBlockAddressReference();
11339 CodeModel::Model M = DAG.getTarget().getCodeModel();
11340 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
11341 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
11343 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
11346 if (Subtarget->isPICStyleRIPRel() &&
11347 (M == CodeModel::Small || M == CodeModel::Kernel))
11348 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
11350 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
11352 // With PIC, the address is actually $g + Offset.
11353 if (isGlobalRelativeToPICBase(OpFlags)) {
11354 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
11355 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
11363 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
11364 int64_t Offset, SelectionDAG &DAG) const {
11365 // Create the TargetGlobalAddress node, folding in the constant
11366 // offset if it is legal.
11367 unsigned char OpFlags =
11368 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
11369 CodeModel::Model M = DAG.getTarget().getCodeModel();
11371 if (OpFlags == X86II::MO_NO_FLAG &&
11372 X86::isOffsetSuitableForCodeModel(Offset, M)) {
11373 // A direct static reference to a global.
11374 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
11377 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
11380 if (Subtarget->isPICStyleRIPRel() &&
11381 (M == CodeModel::Small || M == CodeModel::Kernel))
11382 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
11384 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
11386 // With PIC, the address is actually $g + Offset.
11387 if (isGlobalRelativeToPICBase(OpFlags)) {
11388 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
11389 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
11393 // For globals that require a load from a stub to get the address, emit the
11395 if (isGlobalStubReference(OpFlags))
11396 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
11397 MachinePointerInfo::getGOT(), false, false, false, 0);
11399 // If there was a non-zero offset that we didn't fold, create an explicit
11400 // addition for it.
11402 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
11403 DAG.getConstant(Offset, dl, getPointerTy()));
11409 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
11410 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
11411 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
11412 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
11416 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
11417 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
11418 unsigned char OperandFlags, bool LocalDynamic = false) {
11419 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11420 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
11422 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11423 GA->getValueType(0),
11427 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
11431 SDValue Ops[] = { Chain, TGA, *InFlag };
11432 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
11434 SDValue Ops[] = { Chain, TGA };
11435 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
11438 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
11439 MFI->setAdjustsStack(true);
11440 MFI->setHasCalls(true);
11442 SDValue Flag = Chain.getValue(1);
11443 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
11446 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
11448 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11451 SDLoc dl(GA); // ? function entry point might be better
11452 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
11453 DAG.getNode(X86ISD::GlobalBaseReg,
11454 SDLoc(), PtrVT), InFlag);
11455 InFlag = Chain.getValue(1);
11457 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
11460 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
11462 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11464 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
11465 X86::RAX, X86II::MO_TLSGD);
11468 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
11474 // Get the start address of the TLS block for this module.
11475 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
11476 .getInfo<X86MachineFunctionInfo>();
11477 MFI->incNumLocalDynamicTLSAccesses();
11481 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
11482 X86II::MO_TLSLD, /*LocalDynamic=*/true);
11485 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
11486 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
11487 InFlag = Chain.getValue(1);
11488 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
11489 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
11492 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
11496 unsigned char OperandFlags = X86II::MO_DTPOFF;
11497 unsigned WrapperKind = X86ISD::Wrapper;
11498 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11499 GA->getValueType(0),
11500 GA->getOffset(), OperandFlags);
11501 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
11503 // Add x@dtpoff with the base.
11504 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
11507 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
11508 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11509 const EVT PtrVT, TLSModel::Model model,
11510 bool is64Bit, bool isPIC) {
11513 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
11514 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
11515 is64Bit ? 257 : 256));
11517 SDValue ThreadPointer =
11518 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0, dl),
11519 MachinePointerInfo(Ptr), false, false, false, 0);
11521 unsigned char OperandFlags = 0;
11522 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
11524 unsigned WrapperKind = X86ISD::Wrapper;
11525 if (model == TLSModel::LocalExec) {
11526 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
11527 } else if (model == TLSModel::InitialExec) {
11529 OperandFlags = X86II::MO_GOTTPOFF;
11530 WrapperKind = X86ISD::WrapperRIP;
11532 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
11535 llvm_unreachable("Unexpected model");
11538 // emit "addl x@ntpoff,%eax" (local exec)
11539 // or "addl x@indntpoff,%eax" (initial exec)
11540 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
11542 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
11543 GA->getOffset(), OperandFlags);
11544 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
11546 if (model == TLSModel::InitialExec) {
11547 if (isPIC && !is64Bit) {
11548 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
11549 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
11553 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
11554 MachinePointerInfo::getGOT(), false, false, false, 0);
11557 // The address of the thread local variable is the add of the thread
11558 // pointer with the offset of the variable.
11559 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
11563 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
11565 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
11566 const GlobalValue *GV = GA->getGlobal();
11568 if (Subtarget->isTargetELF()) {
11569 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
11571 case TLSModel::GeneralDynamic:
11572 if (Subtarget->is64Bit())
11573 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
11574 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
11575 case TLSModel::LocalDynamic:
11576 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
11577 Subtarget->is64Bit());
11578 case TLSModel::InitialExec:
11579 case TLSModel::LocalExec:
11580 return LowerToTLSExecModel(
11581 GA, DAG, getPointerTy(), model, Subtarget->is64Bit(),
11582 DAG.getTarget().getRelocationModel() == Reloc::PIC_);
11584 llvm_unreachable("Unknown TLS model.");
11587 if (Subtarget->isTargetDarwin()) {
11588 // Darwin only has one model of TLS. Lower to that.
11589 unsigned char OpFlag = 0;
11590 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
11591 X86ISD::WrapperRIP : X86ISD::Wrapper;
11593 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11594 // global base reg.
11595 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
11596 !Subtarget->is64Bit();
11598 OpFlag = X86II::MO_TLVP_PIC_BASE;
11600 OpFlag = X86II::MO_TLVP;
11602 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
11603 GA->getValueType(0),
11604 GA->getOffset(), OpFlag);
11605 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
11607 // With PIC32, the address is actually $g + Offset.
11609 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11610 DAG.getNode(X86ISD::GlobalBaseReg,
11611 SDLoc(), getPointerTy()),
11614 // Lowering the machine isd will make sure everything is in the right
11616 SDValue Chain = DAG.getEntryNode();
11617 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
11618 SDValue Args[] = { Chain, Offset };
11619 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
11621 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
11622 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11623 MFI->setAdjustsStack(true);
11625 // And our return value (tls address) is in the standard call return value
11627 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
11628 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
11629 Chain.getValue(1));
11632 if (Subtarget->isTargetKnownWindowsMSVC() ||
11633 Subtarget->isTargetWindowsGNU()) {
11634 // Just use the implicit TLS architecture
11635 // Need to generate someting similar to:
11636 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
11638 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
11639 // mov rcx, qword [rdx+rcx*8]
11640 // mov eax, .tls$:tlsvar
11641 // [rax+rcx] contains the address
11642 // Windows 64bit: gs:0x58
11643 // Windows 32bit: fs:__tls_array
11646 SDValue Chain = DAG.getEntryNode();
11648 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
11649 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
11650 // use its literal value of 0x2C.
11651 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
11652 ? Type::getInt8PtrTy(*DAG.getContext(),
11654 : Type::getInt32PtrTy(*DAG.getContext(),
11658 Subtarget->is64Bit()
11659 ? DAG.getIntPtrConstant(0x58, dl)
11660 : (Subtarget->isTargetWindowsGNU()
11661 ? DAG.getIntPtrConstant(0x2C, dl)
11662 : DAG.getExternalSymbol("_tls_array", getPointerTy()));
11664 SDValue ThreadPointer =
11665 DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
11666 MachinePointerInfo(Ptr), false, false, false, 0);
11669 if (GV->getThreadLocalMode() == GlobalVariable::LocalExecTLSModel) {
11670 res = ThreadPointer;
11672 // Load the _tls_index variable
11673 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
11674 if (Subtarget->is64Bit())
11675 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain, IDX,
11676 MachinePointerInfo(), MVT::i32, false, false,
11679 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
11680 false, false, false, 0);
11682 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()), dl,
11684 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
11686 res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
11689 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
11690 false, false, false, 0);
11692 // Get the offset of start of .tls section
11693 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11694 GA->getValueType(0),
11695 GA->getOffset(), X86II::MO_SECREL);
11696 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
11698 // The address of the thread local variable is the add of the thread
11699 // pointer with the offset of the variable.
11700 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
11703 llvm_unreachable("TLS not implemented for this target.");
11706 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
11707 /// and take a 2 x i32 value to shift plus a shift amount.
11708 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
11709 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
11710 MVT VT = Op.getSimpleValueType();
11711 unsigned VTBits = VT.getSizeInBits();
11713 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
11714 SDValue ShOpLo = Op.getOperand(0);
11715 SDValue ShOpHi = Op.getOperand(1);
11716 SDValue ShAmt = Op.getOperand(2);
11717 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
11718 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
11720 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
11721 DAG.getConstant(VTBits - 1, dl, MVT::i8));
11722 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
11723 DAG.getConstant(VTBits - 1, dl, MVT::i8))
11724 : DAG.getConstant(0, dl, VT);
11726 SDValue Tmp2, Tmp3;
11727 if (Op.getOpcode() == ISD::SHL_PARTS) {
11728 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
11729 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
11731 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
11732 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
11735 // If the shift amount is larger or equal than the width of a part we can't
11736 // rely on the results of shld/shrd. Insert a test and select the appropriate
11737 // values for large shift amounts.
11738 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
11739 DAG.getConstant(VTBits, dl, MVT::i8));
11740 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
11741 AndNode, DAG.getConstant(0, dl, MVT::i8));
11744 SDValue CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
11745 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
11746 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
11748 if (Op.getOpcode() == ISD::SHL_PARTS) {
11749 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
11750 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
11752 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
11753 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
11756 SDValue Ops[2] = { Lo, Hi };
11757 return DAG.getMergeValues(Ops, dl);
11760 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
11761 SelectionDAG &DAG) const {
11762 SDValue Src = Op.getOperand(0);
11763 MVT SrcVT = Src.getSimpleValueType();
11764 MVT VT = Op.getSimpleValueType();
11767 if (SrcVT.isVector()) {
11768 if (SrcVT == MVT::v2i32 && VT == MVT::v2f64) {
11769 return DAG.getNode(X86ISD::CVTDQ2PD, dl, VT,
11770 DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4i32, Src,
11771 DAG.getUNDEF(SrcVT)));
11773 if (SrcVT.getVectorElementType() == MVT::i1) {
11774 MVT IntegerVT = MVT::getVectorVT(MVT::i32, SrcVT.getVectorNumElements());
11775 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
11776 DAG.getNode(ISD::SIGN_EXTEND, dl, IntegerVT, Src));
11781 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
11782 "Unknown SINT_TO_FP to lower!");
11784 // These are really Legal; return the operand so the caller accepts it as
11786 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
11788 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
11789 Subtarget->is64Bit()) {
11793 unsigned Size = SrcVT.getSizeInBits()/8;
11794 MachineFunction &MF = DAG.getMachineFunction();
11795 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
11796 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11797 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
11799 MachinePointerInfo::getFixedStack(SSFI),
11801 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
11804 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
11806 SelectionDAG &DAG) const {
11810 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
11812 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
11814 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
11816 unsigned ByteSize = SrcVT.getSizeInBits()/8;
11818 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
11819 MachineMemOperand *MMO;
11821 int SSFI = FI->getIndex();
11823 DAG.getMachineFunction()
11824 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11825 MachineMemOperand::MOLoad, ByteSize, ByteSize);
11827 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
11828 StackSlot = StackSlot.getOperand(1);
11830 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
11831 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
11833 Tys, Ops, SrcVT, MMO);
11836 Chain = Result.getValue(1);
11837 SDValue InFlag = Result.getValue(2);
11839 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
11840 // shouldn't be necessary except that RFP cannot be live across
11841 // multiple blocks. When stackifier is fixed, they can be uncoupled.
11842 MachineFunction &MF = DAG.getMachineFunction();
11843 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
11844 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
11845 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11846 Tys = DAG.getVTList(MVT::Other);
11848 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
11850 MachineMemOperand *MMO =
11851 DAG.getMachineFunction()
11852 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11853 MachineMemOperand::MOStore, SSFISize, SSFISize);
11855 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
11856 Ops, Op.getValueType(), MMO);
11857 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
11858 MachinePointerInfo::getFixedStack(SSFI),
11859 false, false, false, 0);
11865 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
11866 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
11867 SelectionDAG &DAG) const {
11868 // This algorithm is not obvious. Here it is what we're trying to output:
11871 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
11872 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
11874 haddpd %xmm0, %xmm0
11876 pshufd $0x4e, %xmm0, %xmm1
11882 LLVMContext *Context = DAG.getContext();
11884 // Build some magic constants.
11885 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
11886 Constant *C0 = ConstantDataVector::get(*Context, CV0);
11887 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
11889 SmallVector<Constant*,2> CV1;
11891 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
11892 APInt(64, 0x4330000000000000ULL))));
11894 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
11895 APInt(64, 0x4530000000000000ULL))));
11896 Constant *C1 = ConstantVector::get(CV1);
11897 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
11899 // Load the 64-bit value into an XMM register.
11900 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
11902 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
11903 MachinePointerInfo::getConstantPool(),
11904 false, false, false, 16);
11906 getUnpackl(DAG, dl, MVT::v4i32, DAG.getBitcast(MVT::v4i32, XR1), CLod0);
11908 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
11909 MachinePointerInfo::getConstantPool(),
11910 false, false, false, 16);
11911 SDValue XR2F = DAG.getBitcast(MVT::v2f64, Unpck1);
11912 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
11915 if (Subtarget->hasSSE3()) {
11916 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
11917 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
11919 SDValue S2F = DAG.getBitcast(MVT::v4i32, Sub);
11920 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
11922 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
11923 DAG.getBitcast(MVT::v2f64, Shuffle), Sub);
11926 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
11927 DAG.getIntPtrConstant(0, dl));
11930 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
11931 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
11932 SelectionDAG &DAG) const {
11934 // FP constant to bias correct the final result.
11935 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
11938 // Load the 32-bit value into an XMM register.
11939 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
11942 // Zero out the upper parts of the register.
11943 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
11945 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
11946 DAG.getBitcast(MVT::v2f64, Load),
11947 DAG.getIntPtrConstant(0, dl));
11949 // Or the load with the bias.
11950 SDValue Or = DAG.getNode(
11951 ISD::OR, dl, MVT::v2i64,
11952 DAG.getBitcast(MVT::v2i64,
11953 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, Load)),
11954 DAG.getBitcast(MVT::v2i64,
11955 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, Bias)));
11957 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
11958 DAG.getBitcast(MVT::v2f64, Or), DAG.getIntPtrConstant(0, dl));
11960 // Subtract the bias.
11961 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
11963 // Handle final rounding.
11964 EVT DestVT = Op.getValueType();
11966 if (DestVT.bitsLT(MVT::f64))
11967 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
11968 DAG.getIntPtrConstant(0, dl));
11969 if (DestVT.bitsGT(MVT::f64))
11970 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
11972 // Handle final rounding.
11976 static SDValue lowerUINT_TO_FP_vXi32(SDValue Op, SelectionDAG &DAG,
11977 const X86Subtarget &Subtarget) {
11978 // The algorithm is the following:
11979 // #ifdef __SSE4_1__
11980 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
11981 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
11982 // (uint4) 0x53000000, 0xaa);
11984 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
11985 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
11987 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
11988 // return (float4) lo + fhi;
11991 SDValue V = Op->getOperand(0);
11992 EVT VecIntVT = V.getValueType();
11993 bool Is128 = VecIntVT == MVT::v4i32;
11994 EVT VecFloatVT = Is128 ? MVT::v4f32 : MVT::v8f32;
11995 // If we convert to something else than the supported type, e.g., to v4f64,
11997 if (VecFloatVT != Op->getValueType(0))
12000 unsigned NumElts = VecIntVT.getVectorNumElements();
12001 assert((VecIntVT == MVT::v4i32 || VecIntVT == MVT::v8i32) &&
12002 "Unsupported custom type");
12003 assert(NumElts <= 8 && "The size of the constant array must be fixed");
12005 // In the #idef/#else code, we have in common:
12006 // - The vector of constants:
12012 // Create the splat vector for 0x4b000000.
12013 SDValue CstLow = DAG.getConstant(0x4b000000, DL, MVT::i32);
12014 SDValue CstLowArray[] = {CstLow, CstLow, CstLow, CstLow,
12015 CstLow, CstLow, CstLow, CstLow};
12016 SDValue VecCstLow = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12017 makeArrayRef(&CstLowArray[0], NumElts));
12018 // Create the splat vector for 0x53000000.
12019 SDValue CstHigh = DAG.getConstant(0x53000000, DL, MVT::i32);
12020 SDValue CstHighArray[] = {CstHigh, CstHigh, CstHigh, CstHigh,
12021 CstHigh, CstHigh, CstHigh, CstHigh};
12022 SDValue VecCstHigh = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12023 makeArrayRef(&CstHighArray[0], NumElts));
12025 // Create the right shift.
12026 SDValue CstShift = DAG.getConstant(16, DL, MVT::i32);
12027 SDValue CstShiftArray[] = {CstShift, CstShift, CstShift, CstShift,
12028 CstShift, CstShift, CstShift, CstShift};
12029 SDValue VecCstShift = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12030 makeArrayRef(&CstShiftArray[0], NumElts));
12031 SDValue HighShift = DAG.getNode(ISD::SRL, DL, VecIntVT, V, VecCstShift);
12034 if (Subtarget.hasSSE41()) {
12035 EVT VecI16VT = Is128 ? MVT::v8i16 : MVT::v16i16;
12036 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
12037 SDValue VecCstLowBitcast = DAG.getBitcast(VecI16VT, VecCstLow);
12038 SDValue VecBitcast = DAG.getBitcast(VecI16VT, V);
12039 // Low will be bitcasted right away, so do not bother bitcasting back to its
12041 Low = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecBitcast,
12042 VecCstLowBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
12043 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
12044 // (uint4) 0x53000000, 0xaa);
12045 SDValue VecCstHighBitcast = DAG.getBitcast(VecI16VT, VecCstHigh);
12046 SDValue VecShiftBitcast = DAG.getBitcast(VecI16VT, HighShift);
12047 // High will be bitcasted right away, so do not bother bitcasting back to
12048 // its original type.
12049 High = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecShiftBitcast,
12050 VecCstHighBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
12052 SDValue CstMask = DAG.getConstant(0xffff, DL, MVT::i32);
12053 SDValue VecCstMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, CstMask,
12054 CstMask, CstMask, CstMask);
12055 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
12056 SDValue LowAnd = DAG.getNode(ISD::AND, DL, VecIntVT, V, VecCstMask);
12057 Low = DAG.getNode(ISD::OR, DL, VecIntVT, LowAnd, VecCstLow);
12059 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
12060 High = DAG.getNode(ISD::OR, DL, VecIntVT, HighShift, VecCstHigh);
12063 // Create the vector constant for -(0x1.0p39f + 0x1.0p23f).
12064 SDValue CstFAdd = DAG.getConstantFP(
12065 APFloat(APFloat::IEEEsingle, APInt(32, 0xD3000080)), DL, MVT::f32);
12066 SDValue CstFAddArray[] = {CstFAdd, CstFAdd, CstFAdd, CstFAdd,
12067 CstFAdd, CstFAdd, CstFAdd, CstFAdd};
12068 SDValue VecCstFAdd = DAG.getNode(ISD::BUILD_VECTOR, DL, VecFloatVT,
12069 makeArrayRef(&CstFAddArray[0], NumElts));
12071 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
12072 SDValue HighBitcast = DAG.getBitcast(VecFloatVT, High);
12074 DAG.getNode(ISD::FADD, DL, VecFloatVT, HighBitcast, VecCstFAdd);
12075 // return (float4) lo + fhi;
12076 SDValue LowBitcast = DAG.getBitcast(VecFloatVT, Low);
12077 return DAG.getNode(ISD::FADD, DL, VecFloatVT, LowBitcast, FHigh);
12080 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
12081 SelectionDAG &DAG) const {
12082 SDValue N0 = Op.getOperand(0);
12083 MVT SVT = N0.getSimpleValueType();
12086 switch (SVT.SimpleTy) {
12088 llvm_unreachable("Custom UINT_TO_FP is not supported!");
12093 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
12094 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
12095 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
12099 return lowerUINT_TO_FP_vXi32(Op, DAG, *Subtarget);
12102 if (Subtarget->hasAVX512())
12103 return DAG.getNode(ISD::UINT_TO_FP, dl, Op.getValueType(),
12104 DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v16i32, N0));
12106 llvm_unreachable(nullptr);
12109 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
12110 SelectionDAG &DAG) const {
12111 SDValue N0 = Op.getOperand(0);
12114 if (Op.getValueType().isVector())
12115 return lowerUINT_TO_FP_vec(Op, DAG);
12117 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
12118 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
12119 // the optimization here.
12120 if (DAG.SignBitIsZero(N0))
12121 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
12123 MVT SrcVT = N0.getSimpleValueType();
12124 MVT DstVT = Op.getSimpleValueType();
12125 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
12126 return LowerUINT_TO_FP_i64(Op, DAG);
12127 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
12128 return LowerUINT_TO_FP_i32(Op, DAG);
12129 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
12132 // Make a 64-bit buffer, and use it to build an FILD.
12133 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
12134 if (SrcVT == MVT::i32) {
12135 SDValue WordOff = DAG.getConstant(4, dl, getPointerTy());
12136 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
12137 getPointerTy(), StackSlot, WordOff);
12138 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12139 StackSlot, MachinePointerInfo(),
12141 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, dl, MVT::i32),
12142 OffsetSlot, MachinePointerInfo(),
12144 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
12148 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
12149 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12150 StackSlot, MachinePointerInfo(),
12152 // For i64 source, we need to add the appropriate power of 2 if the input
12153 // was negative. This is the same as the optimization in
12154 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
12155 // we must be careful to do the computation in x87 extended precision, not
12156 // in SSE. (The generic code can't know it's OK to do this, or how to.)
12157 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
12158 MachineMemOperand *MMO =
12159 DAG.getMachineFunction()
12160 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12161 MachineMemOperand::MOLoad, 8, 8);
12163 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
12164 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
12165 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
12168 APInt FF(32, 0x5F800000ULL);
12170 // Check whether the sign bit is set.
12171 SDValue SignSet = DAG.getSetCC(dl,
12172 getSetCCResultType(*DAG.getContext(), MVT::i64),
12174 DAG.getConstant(0, dl, MVT::i64), ISD::SETLT);
12176 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
12177 SDValue FudgePtr = DAG.getConstantPool(
12178 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
12181 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
12182 SDValue Zero = DAG.getIntPtrConstant(0, dl);
12183 SDValue Four = DAG.getIntPtrConstant(4, dl);
12184 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
12186 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
12188 // Load the value out, extending it from f32 to f80.
12189 // FIXME: Avoid the extend by constructing the right constant pool?
12190 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
12191 FudgePtr, MachinePointerInfo::getConstantPool(),
12192 MVT::f32, false, false, false, 4);
12193 // Extend everything to 80 bits to force it to be done on x87.
12194 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
12195 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add,
12196 DAG.getIntPtrConstant(0, dl));
12199 std::pair<SDValue,SDValue>
12200 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
12201 bool IsSigned, bool IsReplace) const {
12204 EVT DstTy = Op.getValueType();
12206 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
12207 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
12211 assert(DstTy.getSimpleVT() <= MVT::i64 &&
12212 DstTy.getSimpleVT() >= MVT::i16 &&
12213 "Unknown FP_TO_INT to lower!");
12215 // These are really Legal.
12216 if (DstTy == MVT::i32 &&
12217 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12218 return std::make_pair(SDValue(), SDValue());
12219 if (Subtarget->is64Bit() &&
12220 DstTy == MVT::i64 &&
12221 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12222 return std::make_pair(SDValue(), SDValue());
12224 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
12225 // stack slot, or into the FTOL runtime function.
12226 MachineFunction &MF = DAG.getMachineFunction();
12227 unsigned MemSize = DstTy.getSizeInBits()/8;
12228 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12229 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12232 if (!IsSigned && isIntegerTypeFTOL(DstTy))
12233 Opc = X86ISD::WIN_FTOL;
12235 switch (DstTy.getSimpleVT().SimpleTy) {
12236 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
12237 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
12238 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
12239 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
12242 SDValue Chain = DAG.getEntryNode();
12243 SDValue Value = Op.getOperand(0);
12244 EVT TheVT = Op.getOperand(0).getValueType();
12245 // FIXME This causes a redundant load/store if the SSE-class value is already
12246 // in memory, such as if it is on the callstack.
12247 if (isScalarFPTypeInSSEReg(TheVT)) {
12248 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
12249 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
12250 MachinePointerInfo::getFixedStack(SSFI),
12252 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
12254 Chain, StackSlot, DAG.getValueType(TheVT)
12257 MachineMemOperand *MMO =
12258 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12259 MachineMemOperand::MOLoad, MemSize, MemSize);
12260 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
12261 Chain = Value.getValue(1);
12262 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12263 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12266 MachineMemOperand *MMO =
12267 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12268 MachineMemOperand::MOStore, MemSize, MemSize);
12270 if (Opc != X86ISD::WIN_FTOL) {
12271 // Build the FP_TO_INT*_IN_MEM
12272 SDValue Ops[] = { Chain, Value, StackSlot };
12273 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
12275 return std::make_pair(FIST, StackSlot);
12277 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
12278 DAG.getVTList(MVT::Other, MVT::Glue),
12280 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
12281 MVT::i32, ftol.getValue(1));
12282 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
12283 MVT::i32, eax.getValue(2));
12284 SDValue Ops[] = { eax, edx };
12285 SDValue pair = IsReplace
12286 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
12287 : DAG.getMergeValues(Ops, DL);
12288 return std::make_pair(pair, SDValue());
12292 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
12293 const X86Subtarget *Subtarget) {
12294 MVT VT = Op->getSimpleValueType(0);
12295 SDValue In = Op->getOperand(0);
12296 MVT InVT = In.getSimpleValueType();
12299 if (VT.is512BitVector() || InVT.getScalarType() == MVT::i1)
12300 return DAG.getNode(ISD::ZERO_EXTEND, dl, VT, In);
12302 // Optimize vectors in AVX mode:
12305 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
12306 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
12307 // Concat upper and lower parts.
12310 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
12311 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
12312 // Concat upper and lower parts.
12315 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
12316 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
12317 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
12320 if (Subtarget->hasInt256())
12321 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
12323 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
12324 SDValue Undef = DAG.getUNDEF(InVT);
12325 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
12326 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
12327 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
12329 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
12330 VT.getVectorNumElements()/2);
12332 OpLo = DAG.getBitcast(HVT, OpLo);
12333 OpHi = DAG.getBitcast(HVT, OpHi);
12335 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
12338 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
12339 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
12340 MVT VT = Op->getSimpleValueType(0);
12341 SDValue In = Op->getOperand(0);
12342 MVT InVT = In.getSimpleValueType();
12344 unsigned int NumElts = VT.getVectorNumElements();
12345 if (NumElts != 8 && NumElts != 16 && !Subtarget->hasBWI())
12348 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
12349 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
12351 assert(InVT.getVectorElementType() == MVT::i1);
12352 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
12354 DAG.getConstant(APInt(ExtVT.getScalarSizeInBits(), 1), DL, ExtVT);
12356 DAG.getConstant(APInt::getNullValue(ExtVT.getScalarSizeInBits()), DL, ExtVT);
12358 SDValue V = DAG.getNode(ISD::VSELECT, DL, ExtVT, In, One, Zero);
12359 if (VT.is512BitVector())
12361 return DAG.getNode(X86ISD::VTRUNC, DL, VT, V);
12364 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
12365 SelectionDAG &DAG) {
12366 if (Subtarget->hasFp256())
12367 if (SDValue Res = LowerAVXExtend(Op, DAG, Subtarget))
12373 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
12374 SelectionDAG &DAG) {
12376 MVT VT = Op.getSimpleValueType();
12377 SDValue In = Op.getOperand(0);
12378 MVT SVT = In.getSimpleValueType();
12380 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
12381 return LowerZERO_EXTEND_AVX512(Op, Subtarget, DAG);
12383 if (Subtarget->hasFp256())
12384 if (SDValue Res = LowerAVXExtend(Op, DAG, Subtarget))
12387 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
12388 VT.getVectorNumElements() != SVT.getVectorNumElements());
12392 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
12394 MVT VT = Op.getSimpleValueType();
12395 SDValue In = Op.getOperand(0);
12396 MVT InVT = In.getSimpleValueType();
12398 if (VT == MVT::i1) {
12399 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
12400 "Invalid scalar TRUNCATE operation");
12401 if (InVT.getSizeInBits() >= 32)
12403 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
12404 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
12406 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
12407 "Invalid TRUNCATE operation");
12409 // move vector to mask - truncate solution for SKX
12410 if (VT.getVectorElementType() == MVT::i1) {
12411 if (InVT.is512BitVector() && InVT.getScalarSizeInBits() <= 16 &&
12412 Subtarget->hasBWI())
12413 return Op; // legal, will go to VPMOVB2M, VPMOVW2M
12414 if ((InVT.is256BitVector() || InVT.is128BitVector())
12415 && InVT.getScalarSizeInBits() <= 16 &&
12416 Subtarget->hasBWI() && Subtarget->hasVLX())
12417 return Op; // legal, will go to VPMOVB2M, VPMOVW2M
12418 if (InVT.is512BitVector() && InVT.getScalarSizeInBits() >= 32 &&
12419 Subtarget->hasDQI())
12420 return Op; // legal, will go to VPMOVD2M, VPMOVQ2M
12421 if ((InVT.is256BitVector() || InVT.is128BitVector())
12422 && InVT.getScalarSizeInBits() >= 32 &&
12423 Subtarget->hasDQI() && Subtarget->hasVLX())
12424 return Op; // legal, will go to VPMOVB2M, VPMOVQ2M
12426 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
12427 if (VT.getVectorElementType().getSizeInBits() >=8)
12428 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
12430 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
12431 unsigned NumElts = InVT.getVectorNumElements();
12432 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
12433 if (InVT.getSizeInBits() < 512) {
12434 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
12435 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
12440 DAG.getConstant(APInt::getSignBit(InVT.getScalarSizeInBits()), DL, InVT);
12441 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
12442 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
12445 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
12446 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
12447 if (Subtarget->hasInt256()) {
12448 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
12449 In = DAG.getBitcast(MVT::v8i32, In);
12450 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
12452 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
12453 DAG.getIntPtrConstant(0, DL));
12456 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12457 DAG.getIntPtrConstant(0, DL));
12458 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12459 DAG.getIntPtrConstant(2, DL));
12460 OpLo = DAG.getBitcast(MVT::v4i32, OpLo);
12461 OpHi = DAG.getBitcast(MVT::v4i32, OpHi);
12462 static const int ShufMask[] = {0, 2, 4, 6};
12463 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
12466 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
12467 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
12468 if (Subtarget->hasInt256()) {
12469 In = DAG.getBitcast(MVT::v32i8, In);
12471 SmallVector<SDValue,32> pshufbMask;
12472 for (unsigned i = 0; i < 2; ++i) {
12473 pshufbMask.push_back(DAG.getConstant(0x0, DL, MVT::i8));
12474 pshufbMask.push_back(DAG.getConstant(0x1, DL, MVT::i8));
12475 pshufbMask.push_back(DAG.getConstant(0x4, DL, MVT::i8));
12476 pshufbMask.push_back(DAG.getConstant(0x5, DL, MVT::i8));
12477 pshufbMask.push_back(DAG.getConstant(0x8, DL, MVT::i8));
12478 pshufbMask.push_back(DAG.getConstant(0x9, DL, MVT::i8));
12479 pshufbMask.push_back(DAG.getConstant(0xc, DL, MVT::i8));
12480 pshufbMask.push_back(DAG.getConstant(0xd, DL, MVT::i8));
12481 for (unsigned j = 0; j < 8; ++j)
12482 pshufbMask.push_back(DAG.getConstant(0x80, DL, MVT::i8));
12484 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
12485 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
12486 In = DAG.getBitcast(MVT::v4i64, In);
12488 static const int ShufMask[] = {0, 2, -1, -1};
12489 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
12491 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12492 DAG.getIntPtrConstant(0, DL));
12493 return DAG.getBitcast(VT, In);
12496 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
12497 DAG.getIntPtrConstant(0, DL));
12499 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
12500 DAG.getIntPtrConstant(4, DL));
12502 OpLo = DAG.getBitcast(MVT::v16i8, OpLo);
12503 OpHi = DAG.getBitcast(MVT::v16i8, OpHi);
12505 // The PSHUFB mask:
12506 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
12507 -1, -1, -1, -1, -1, -1, -1, -1};
12509 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
12510 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
12511 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
12513 OpLo = DAG.getBitcast(MVT::v4i32, OpLo);
12514 OpHi = DAG.getBitcast(MVT::v4i32, OpHi);
12516 // The MOVLHPS Mask:
12517 static const int ShufMask2[] = {0, 1, 4, 5};
12518 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
12519 return DAG.getBitcast(MVT::v8i16, res);
12522 // Handle truncation of V256 to V128 using shuffles.
12523 if (!VT.is128BitVector() || !InVT.is256BitVector())
12526 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
12528 unsigned NumElems = VT.getVectorNumElements();
12529 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
12531 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
12532 // Prepare truncation shuffle mask
12533 for (unsigned i = 0; i != NumElems; ++i)
12534 MaskVec[i] = i * 2;
12535 SDValue V = DAG.getVectorShuffle(NVT, DL, DAG.getBitcast(NVT, In),
12536 DAG.getUNDEF(NVT), &MaskVec[0]);
12537 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
12538 DAG.getIntPtrConstant(0, DL));
12541 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
12542 SelectionDAG &DAG) const {
12543 assert(!Op.getSimpleValueType().isVector());
12545 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
12546 /*IsSigned=*/ true, /*IsReplace=*/ false);
12547 SDValue FIST = Vals.first, StackSlot = Vals.second;
12548 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
12549 if (!FIST.getNode()) return Op;
12551 if (StackSlot.getNode())
12552 // Load the result.
12553 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
12554 FIST, StackSlot, MachinePointerInfo(),
12555 false, false, false, 0);
12557 // The node is the result.
12561 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
12562 SelectionDAG &DAG) const {
12563 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
12564 /*IsSigned=*/ false, /*IsReplace=*/ false);
12565 SDValue FIST = Vals.first, StackSlot = Vals.second;
12566 assert(FIST.getNode() && "Unexpected failure");
12568 if (StackSlot.getNode())
12569 // Load the result.
12570 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
12571 FIST, StackSlot, MachinePointerInfo(),
12572 false, false, false, 0);
12574 // The node is the result.
12578 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
12580 MVT VT = Op.getSimpleValueType();
12581 SDValue In = Op.getOperand(0);
12582 MVT SVT = In.getSimpleValueType();
12584 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
12586 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
12587 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
12588 In, DAG.getUNDEF(SVT)));
12591 /// The only differences between FABS and FNEG are the mask and the logic op.
12592 /// FNEG also has a folding opportunity for FNEG(FABS(x)).
12593 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
12594 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
12595 "Wrong opcode for lowering FABS or FNEG.");
12597 bool IsFABS = (Op.getOpcode() == ISD::FABS);
12599 // If this is a FABS and it has an FNEG user, bail out to fold the combination
12600 // into an FNABS. We'll lower the FABS after that if it is still in use.
12602 for (SDNode *User : Op->uses())
12603 if (User->getOpcode() == ISD::FNEG)
12606 SDValue Op0 = Op.getOperand(0);
12607 bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);
12610 MVT VT = Op.getSimpleValueType();
12611 // Assume scalar op for initialization; update for vector if needed.
12612 // Note that there are no scalar bitwise logical SSE/AVX instructions, so we
12613 // generate a 16-byte vector constant and logic op even for the scalar case.
12614 // Using a 16-byte mask allows folding the load of the mask with
12615 // the logic op, so it can save (~4 bytes) on code size.
12617 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
12618 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
12619 // decide if we should generate a 16-byte constant mask when we only need 4 or
12620 // 8 bytes for the scalar case.
12621 if (VT.isVector()) {
12622 EltVT = VT.getVectorElementType();
12623 NumElts = VT.getVectorNumElements();
12626 unsigned EltBits = EltVT.getSizeInBits();
12627 LLVMContext *Context = DAG.getContext();
12628 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
12630 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
12631 Constant *C = ConstantInt::get(*Context, MaskElt);
12632 C = ConstantVector::getSplat(NumElts, C);
12633 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12634 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
12635 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
12636 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
12637 MachinePointerInfo::getConstantPool(),
12638 false, false, false, Alignment);
12640 if (VT.isVector()) {
12641 // For a vector, cast operands to a vector type, perform the logic op,
12642 // and cast the result back to the original value type.
12643 MVT VecVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
12644 SDValue MaskCasted = DAG.getBitcast(VecVT, Mask);
12645 SDValue Operand = IsFNABS ? DAG.getBitcast(VecVT, Op0.getOperand(0))
12646 : DAG.getBitcast(VecVT, Op0);
12647 unsigned BitOp = IsFABS ? ISD::AND : IsFNABS ? ISD::OR : ISD::XOR;
12648 return DAG.getBitcast(VT,
12649 DAG.getNode(BitOp, dl, VecVT, Operand, MaskCasted));
12652 // If not vector, then scalar.
12653 unsigned BitOp = IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR;
12654 SDValue Operand = IsFNABS ? Op0.getOperand(0) : Op0;
12655 return DAG.getNode(BitOp, dl, VT, Operand, Mask);
12658 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
12659 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12660 LLVMContext *Context = DAG.getContext();
12661 SDValue Op0 = Op.getOperand(0);
12662 SDValue Op1 = Op.getOperand(1);
12664 MVT VT = Op.getSimpleValueType();
12665 MVT SrcVT = Op1.getSimpleValueType();
12667 // If second operand is smaller, extend it first.
12668 if (SrcVT.bitsLT(VT)) {
12669 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
12672 // And if it is bigger, shrink it first.
12673 if (SrcVT.bitsGT(VT)) {
12674 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1, dl));
12678 // At this point the operands and the result should have the same
12679 // type, and that won't be f80 since that is not custom lowered.
12681 const fltSemantics &Sem =
12682 VT == MVT::f64 ? APFloat::IEEEdouble : APFloat::IEEEsingle;
12683 const unsigned SizeInBits = VT.getSizeInBits();
12685 SmallVector<Constant *, 4> CV(
12686 VT == MVT::f64 ? 2 : 4,
12687 ConstantFP::get(*Context, APFloat(Sem, APInt(SizeInBits, 0))));
12689 // First, clear all bits but the sign bit from the second operand (sign).
12690 CV[0] = ConstantFP::get(*Context,
12691 APFloat(Sem, APInt::getHighBitsSet(SizeInBits, 1)));
12692 Constant *C = ConstantVector::get(CV);
12693 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
12694 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
12695 MachinePointerInfo::getConstantPool(),
12696 false, false, false, 16);
12697 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
12699 // Next, clear the sign bit from the first operand (magnitude).
12700 // If it's a constant, we can clear it here.
12701 if (ConstantFPSDNode *Op0CN = dyn_cast<ConstantFPSDNode>(Op0)) {
12702 APFloat APF = Op0CN->getValueAPF();
12703 // If the magnitude is a positive zero, the sign bit alone is enough.
12704 if (APF.isPosZero())
12707 CV[0] = ConstantFP::get(*Context, APF);
12709 CV[0] = ConstantFP::get(
12711 APFloat(Sem, APInt::getLowBitsSet(SizeInBits, SizeInBits - 1)));
12713 C = ConstantVector::get(CV);
12714 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
12715 SDValue Val = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
12716 MachinePointerInfo::getConstantPool(),
12717 false, false, false, 16);
12718 // If the magnitude operand wasn't a constant, we need to AND out the sign.
12719 if (!isa<ConstantFPSDNode>(Op0))
12720 Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Val);
12722 // OR the magnitude value with the sign bit.
12723 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
12726 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
12727 SDValue N0 = Op.getOperand(0);
12729 MVT VT = Op.getSimpleValueType();
12731 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
12732 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
12733 DAG.getConstant(1, dl, VT));
12734 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, dl, VT));
12737 // Check whether an OR'd tree is PTEST-able.
12738 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
12739 SelectionDAG &DAG) {
12740 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
12742 if (!Subtarget->hasSSE41())
12745 if (!Op->hasOneUse())
12748 SDNode *N = Op.getNode();
12751 SmallVector<SDValue, 8> Opnds;
12752 DenseMap<SDValue, unsigned> VecInMap;
12753 SmallVector<SDValue, 8> VecIns;
12754 EVT VT = MVT::Other;
12756 // Recognize a special case where a vector is casted into wide integer to
12758 Opnds.push_back(N->getOperand(0));
12759 Opnds.push_back(N->getOperand(1));
12761 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
12762 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
12763 // BFS traverse all OR'd operands.
12764 if (I->getOpcode() == ISD::OR) {
12765 Opnds.push_back(I->getOperand(0));
12766 Opnds.push_back(I->getOperand(1));
12767 // Re-evaluate the number of nodes to be traversed.
12768 e += 2; // 2 more nodes (LHS and RHS) are pushed.
12772 // Quit if a non-EXTRACT_VECTOR_ELT
12773 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
12776 // Quit if without a constant index.
12777 SDValue Idx = I->getOperand(1);
12778 if (!isa<ConstantSDNode>(Idx))
12781 SDValue ExtractedFromVec = I->getOperand(0);
12782 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
12783 if (M == VecInMap.end()) {
12784 VT = ExtractedFromVec.getValueType();
12785 // Quit if not 128/256-bit vector.
12786 if (!VT.is128BitVector() && !VT.is256BitVector())
12788 // Quit if not the same type.
12789 if (VecInMap.begin() != VecInMap.end() &&
12790 VT != VecInMap.begin()->first.getValueType())
12792 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
12793 VecIns.push_back(ExtractedFromVec);
12795 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
12798 assert((VT.is128BitVector() || VT.is256BitVector()) &&
12799 "Not extracted from 128-/256-bit vector.");
12801 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
12803 for (DenseMap<SDValue, unsigned>::const_iterator
12804 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
12805 // Quit if not all elements are used.
12806 if (I->second != FullMask)
12810 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
12812 // Cast all vectors into TestVT for PTEST.
12813 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
12814 VecIns[i] = DAG.getBitcast(TestVT, VecIns[i]);
12816 // If more than one full vectors are evaluated, OR them first before PTEST.
12817 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
12818 // Each iteration will OR 2 nodes and append the result until there is only
12819 // 1 node left, i.e. the final OR'd value of all vectors.
12820 SDValue LHS = VecIns[Slot];
12821 SDValue RHS = VecIns[Slot + 1];
12822 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
12825 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
12826 VecIns.back(), VecIns.back());
12829 /// \brief return true if \c Op has a use that doesn't just read flags.
12830 static bool hasNonFlagsUse(SDValue Op) {
12831 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
12833 SDNode *User = *UI;
12834 unsigned UOpNo = UI.getOperandNo();
12835 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
12836 // Look pass truncate.
12837 UOpNo = User->use_begin().getOperandNo();
12838 User = *User->use_begin();
12841 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
12842 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
12848 /// Emit nodes that will be selected as "test Op0,Op0", or something
12850 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
12851 SelectionDAG &DAG) const {
12852 if (Op.getValueType() == MVT::i1) {
12853 SDValue ExtOp = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i8, Op);
12854 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, ExtOp,
12855 DAG.getConstant(0, dl, MVT::i8));
12857 // CF and OF aren't always set the way we want. Determine which
12858 // of these we need.
12859 bool NeedCF = false;
12860 bool NeedOF = false;
12863 case X86::COND_A: case X86::COND_AE:
12864 case X86::COND_B: case X86::COND_BE:
12867 case X86::COND_G: case X86::COND_GE:
12868 case X86::COND_L: case X86::COND_LE:
12869 case X86::COND_O: case X86::COND_NO: {
12870 // Check if we really need to set the
12871 // Overflow flag. If NoSignedWrap is present
12872 // that is not actually needed.
12873 switch (Op->getOpcode()) {
12878 const auto *BinNode = cast<BinaryWithFlagsSDNode>(Op.getNode());
12879 if (BinNode->Flags.hasNoSignedWrap())
12889 // See if we can use the EFLAGS value from the operand instead of
12890 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
12891 // we prove that the arithmetic won't overflow, we can't use OF or CF.
12892 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
12893 // Emit a CMP with 0, which is the TEST pattern.
12894 //if (Op.getValueType() == MVT::i1)
12895 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
12896 // DAG.getConstant(0, MVT::i1));
12897 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
12898 DAG.getConstant(0, dl, Op.getValueType()));
12900 unsigned Opcode = 0;
12901 unsigned NumOperands = 0;
12903 // Truncate operations may prevent the merge of the SETCC instruction
12904 // and the arithmetic instruction before it. Attempt to truncate the operands
12905 // of the arithmetic instruction and use a reduced bit-width instruction.
12906 bool NeedTruncation = false;
12907 SDValue ArithOp = Op;
12908 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
12909 SDValue Arith = Op->getOperand(0);
12910 // Both the trunc and the arithmetic op need to have one user each.
12911 if (Arith->hasOneUse())
12912 switch (Arith.getOpcode()) {
12919 NeedTruncation = true;
12925 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
12926 // which may be the result of a CAST. We use the variable 'Op', which is the
12927 // non-casted variable when we check for possible users.
12928 switch (ArithOp.getOpcode()) {
12930 // Due to an isel shortcoming, be conservative if this add is likely to be
12931 // selected as part of a load-modify-store instruction. When the root node
12932 // in a match is a store, isel doesn't know how to remap non-chain non-flag
12933 // uses of other nodes in the match, such as the ADD in this case. This
12934 // leads to the ADD being left around and reselected, with the result being
12935 // two adds in the output. Alas, even if none our users are stores, that
12936 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
12937 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
12938 // climbing the DAG back to the root, and it doesn't seem to be worth the
12940 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
12941 UE = Op.getNode()->use_end(); UI != UE; ++UI)
12942 if (UI->getOpcode() != ISD::CopyToReg &&
12943 UI->getOpcode() != ISD::SETCC &&
12944 UI->getOpcode() != ISD::STORE)
12947 if (ConstantSDNode *C =
12948 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
12949 // An add of one will be selected as an INC.
12950 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
12951 Opcode = X86ISD::INC;
12956 // An add of negative one (subtract of one) will be selected as a DEC.
12957 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
12958 Opcode = X86ISD::DEC;
12964 // Otherwise use a regular EFLAGS-setting add.
12965 Opcode = X86ISD::ADD;
12970 // If we have a constant logical shift that's only used in a comparison
12971 // against zero turn it into an equivalent AND. This allows turning it into
12972 // a TEST instruction later.
12973 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
12974 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
12975 EVT VT = Op.getValueType();
12976 unsigned BitWidth = VT.getSizeInBits();
12977 unsigned ShAmt = Op->getConstantOperandVal(1);
12978 if (ShAmt >= BitWidth) // Avoid undefined shifts.
12980 APInt Mask = ArithOp.getOpcode() == ISD::SRL
12981 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
12982 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
12983 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
12985 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
12986 DAG.getConstant(Mask, dl, VT));
12987 DAG.ReplaceAllUsesWith(Op, New);
12993 // If the primary and result isn't used, don't bother using X86ISD::AND,
12994 // because a TEST instruction will be better.
12995 if (!hasNonFlagsUse(Op))
13001 // Due to the ISEL shortcoming noted above, be conservative if this op is
13002 // likely to be selected as part of a load-modify-store instruction.
13003 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13004 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13005 if (UI->getOpcode() == ISD::STORE)
13008 // Otherwise use a regular EFLAGS-setting instruction.
13009 switch (ArithOp.getOpcode()) {
13010 default: llvm_unreachable("unexpected operator!");
13011 case ISD::SUB: Opcode = X86ISD::SUB; break;
13012 case ISD::XOR: Opcode = X86ISD::XOR; break;
13013 case ISD::AND: Opcode = X86ISD::AND; break;
13015 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
13016 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
13017 if (EFLAGS.getNode())
13020 Opcode = X86ISD::OR;
13034 return SDValue(Op.getNode(), 1);
13040 // If we found that truncation is beneficial, perform the truncation and
13042 if (NeedTruncation) {
13043 EVT VT = Op.getValueType();
13044 SDValue WideVal = Op->getOperand(0);
13045 EVT WideVT = WideVal.getValueType();
13046 unsigned ConvertedOp = 0;
13047 // Use a target machine opcode to prevent further DAGCombine
13048 // optimizations that may separate the arithmetic operations
13049 // from the setcc node.
13050 switch (WideVal.getOpcode()) {
13052 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
13053 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
13054 case ISD::AND: ConvertedOp = X86ISD::AND; break;
13055 case ISD::OR: ConvertedOp = X86ISD::OR; break;
13056 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
13060 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13061 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
13062 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
13063 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
13064 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
13070 // Emit a CMP with 0, which is the TEST pattern.
13071 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13072 DAG.getConstant(0, dl, Op.getValueType()));
13074 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
13075 SmallVector<SDValue, 4> Ops(Op->op_begin(), Op->op_begin() + NumOperands);
13077 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
13078 DAG.ReplaceAllUsesWith(Op, New);
13079 return SDValue(New.getNode(), 1);
13082 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
13084 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
13085 SDLoc dl, SelectionDAG &DAG) const {
13086 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
13087 if (C->getAPIntValue() == 0)
13088 return EmitTest(Op0, X86CC, dl, DAG);
13090 if (Op0.getValueType() == MVT::i1)
13091 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
13094 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
13095 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
13096 // Do the comparison at i32 if it's smaller, besides the Atom case.
13097 // This avoids subregister aliasing issues. Keep the smaller reference
13098 // if we're optimizing for size, however, as that'll allow better folding
13099 // of memory operations.
13100 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
13101 !DAG.getMachineFunction().getFunction()->hasFnAttribute(
13102 Attribute::MinSize) &&
13103 !Subtarget->isAtom()) {
13104 unsigned ExtendOp =
13105 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
13106 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
13107 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
13109 // Use SUB instead of CMP to enable CSE between SUB and CMP.
13110 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
13111 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
13113 return SDValue(Sub.getNode(), 1);
13115 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
13118 /// Convert a comparison if required by the subtarget.
13119 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
13120 SelectionDAG &DAG) const {
13121 // If the subtarget does not support the FUCOMI instruction, floating-point
13122 // comparisons have to be converted.
13123 if (Subtarget->hasCMov() ||
13124 Cmp.getOpcode() != X86ISD::CMP ||
13125 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
13126 !Cmp.getOperand(1).getValueType().isFloatingPoint())
13129 // The instruction selector will select an FUCOM instruction instead of
13130 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
13131 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
13132 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
13134 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
13135 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
13136 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
13137 DAG.getConstant(8, dl, MVT::i8));
13138 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
13139 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
13142 /// The minimum architected relative accuracy is 2^-12. We need one
13143 /// Newton-Raphson step to have a good float result (24 bits of precision).
13144 SDValue X86TargetLowering::getRsqrtEstimate(SDValue Op,
13145 DAGCombinerInfo &DCI,
13146 unsigned &RefinementSteps,
13147 bool &UseOneConstNR) const {
13148 EVT VT = Op.getValueType();
13149 const char *RecipOp;
13151 // SSE1 has rsqrtss and rsqrtps. AVX adds a 256-bit variant for rsqrtps.
13152 // TODO: Add support for AVX512 (v16f32).
13153 // It is likely not profitable to do this for f64 because a double-precision
13154 // rsqrt estimate with refinement on x86 prior to FMA requires at least 16
13155 // instructions: convert to single, rsqrtss, convert back to double, refine
13156 // (3 steps = at least 13 insts). If an 'rsqrtsd' variant was added to the ISA
13157 // along with FMA, this could be a throughput win.
13158 if (VT == MVT::f32 && Subtarget->hasSSE1())
13160 else if ((VT == MVT::v4f32 && Subtarget->hasSSE1()) ||
13161 (VT == MVT::v8f32 && Subtarget->hasAVX()))
13162 RecipOp = "vec-sqrtf";
13166 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
13167 if (!Recips.isEnabled(RecipOp))
13170 RefinementSteps = Recips.getRefinementSteps(RecipOp);
13171 UseOneConstNR = false;
13172 return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op);
13175 /// The minimum architected relative accuracy is 2^-12. We need one
13176 /// Newton-Raphson step to have a good float result (24 bits of precision).
13177 SDValue X86TargetLowering::getRecipEstimate(SDValue Op,
13178 DAGCombinerInfo &DCI,
13179 unsigned &RefinementSteps) const {
13180 EVT VT = Op.getValueType();
13181 const char *RecipOp;
13183 // SSE1 has rcpss and rcpps. AVX adds a 256-bit variant for rcpps.
13184 // TODO: Add support for AVX512 (v16f32).
13185 // It is likely not profitable to do this for f64 because a double-precision
13186 // reciprocal estimate with refinement on x86 prior to FMA requires
13187 // 15 instructions: convert to single, rcpss, convert back to double, refine
13188 // (3 steps = 12 insts). If an 'rcpsd' variant was added to the ISA
13189 // along with FMA, this could be a throughput win.
13190 if (VT == MVT::f32 && Subtarget->hasSSE1())
13192 else if ((VT == MVT::v4f32 && Subtarget->hasSSE1()) ||
13193 (VT == MVT::v8f32 && Subtarget->hasAVX()))
13194 RecipOp = "vec-divf";
13198 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
13199 if (!Recips.isEnabled(RecipOp))
13202 RefinementSteps = Recips.getRefinementSteps(RecipOp);
13203 return DCI.DAG.getNode(X86ISD::FRCP, SDLoc(Op), VT, Op);
13206 /// If we have at least two divisions that use the same divisor, convert to
13207 /// multplication by a reciprocal. This may need to be adjusted for a given
13208 /// CPU if a division's cost is not at least twice the cost of a multiplication.
13209 /// This is because we still need one division to calculate the reciprocal and
13210 /// then we need two multiplies by that reciprocal as replacements for the
13211 /// original divisions.
13212 bool X86TargetLowering::combineRepeatedFPDivisors(unsigned NumUsers) const {
13213 return NumUsers > 1;
13216 static bool isAllOnes(SDValue V) {
13217 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
13218 return C && C->isAllOnesValue();
13221 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
13222 /// if it's possible.
13223 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
13224 SDLoc dl, SelectionDAG &DAG) const {
13225 SDValue Op0 = And.getOperand(0);
13226 SDValue Op1 = And.getOperand(1);
13227 if (Op0.getOpcode() == ISD::TRUNCATE)
13228 Op0 = Op0.getOperand(0);
13229 if (Op1.getOpcode() == ISD::TRUNCATE)
13230 Op1 = Op1.getOperand(0);
13233 if (Op1.getOpcode() == ISD::SHL)
13234 std::swap(Op0, Op1);
13235 if (Op0.getOpcode() == ISD::SHL) {
13236 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
13237 if (And00C->getZExtValue() == 1) {
13238 // If we looked past a truncate, check that it's only truncating away
13240 unsigned BitWidth = Op0.getValueSizeInBits();
13241 unsigned AndBitWidth = And.getValueSizeInBits();
13242 if (BitWidth > AndBitWidth) {
13244 DAG.computeKnownBits(Op0, Zeros, Ones);
13245 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
13249 RHS = Op0.getOperand(1);
13251 } else if (Op1.getOpcode() == ISD::Constant) {
13252 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
13253 uint64_t AndRHSVal = AndRHS->getZExtValue();
13254 SDValue AndLHS = Op0;
13256 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
13257 LHS = AndLHS.getOperand(0);
13258 RHS = AndLHS.getOperand(1);
13261 // Use BT if the immediate can't be encoded in a TEST instruction.
13262 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
13264 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), dl, LHS.getValueType());
13268 if (LHS.getNode()) {
13269 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
13270 // instruction. Since the shift amount is in-range-or-undefined, we know
13271 // that doing a bittest on the i32 value is ok. We extend to i32 because
13272 // the encoding for the i16 version is larger than the i32 version.
13273 // Also promote i16 to i32 for performance / code size reason.
13274 if (LHS.getValueType() == MVT::i8 ||
13275 LHS.getValueType() == MVT::i16)
13276 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
13278 // If the operand types disagree, extend the shift amount to match. Since
13279 // BT ignores high bits (like shifts) we can use anyextend.
13280 if (LHS.getValueType() != RHS.getValueType())
13281 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
13283 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
13284 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
13285 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13286 DAG.getConstant(Cond, dl, MVT::i8), BT);
13292 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
13294 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
13299 // SSE Condition code mapping:
13308 switch (SetCCOpcode) {
13309 default: llvm_unreachable("Unexpected SETCC condition");
13311 case ISD::SETEQ: SSECC = 0; break;
13313 case ISD::SETGT: Swap = true; // Fallthrough
13315 case ISD::SETOLT: SSECC = 1; break;
13317 case ISD::SETGE: Swap = true; // Fallthrough
13319 case ISD::SETOLE: SSECC = 2; break;
13320 case ISD::SETUO: SSECC = 3; break;
13322 case ISD::SETNE: SSECC = 4; break;
13323 case ISD::SETULE: Swap = true; // Fallthrough
13324 case ISD::SETUGE: SSECC = 5; break;
13325 case ISD::SETULT: Swap = true; // Fallthrough
13326 case ISD::SETUGT: SSECC = 6; break;
13327 case ISD::SETO: SSECC = 7; break;
13329 case ISD::SETONE: SSECC = 8; break;
13332 std::swap(Op0, Op1);
13337 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
13338 // ones, and then concatenate the result back.
13339 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
13340 MVT VT = Op.getSimpleValueType();
13342 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
13343 "Unsupported value type for operation");
13345 unsigned NumElems = VT.getVectorNumElements();
13347 SDValue CC = Op.getOperand(2);
13349 // Extract the LHS vectors
13350 SDValue LHS = Op.getOperand(0);
13351 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
13352 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
13354 // Extract the RHS vectors
13355 SDValue RHS = Op.getOperand(1);
13356 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
13357 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
13359 // Issue the operation on the smaller types and concatenate the result back
13360 MVT EltVT = VT.getVectorElementType();
13361 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
13362 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
13363 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
13364 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
13367 static SDValue LowerBoolVSETCC_AVX512(SDValue Op, SelectionDAG &DAG) {
13368 SDValue Op0 = Op.getOperand(0);
13369 SDValue Op1 = Op.getOperand(1);
13370 SDValue CC = Op.getOperand(2);
13371 MVT VT = Op.getSimpleValueType();
13374 assert(Op0.getValueType().getVectorElementType() == MVT::i1 &&
13375 "Unexpected type for boolean compare operation");
13376 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
13377 SDValue NotOp0 = DAG.getNode(ISD::XOR, dl, VT, Op0,
13378 DAG.getConstant(-1, dl, VT));
13379 SDValue NotOp1 = DAG.getNode(ISD::XOR, dl, VT, Op1,
13380 DAG.getConstant(-1, dl, VT));
13381 switch (SetCCOpcode) {
13382 default: llvm_unreachable("Unexpected SETCC condition");
13384 // (x == y) -> ~(x ^ y)
13385 return DAG.getNode(ISD::XOR, dl, VT,
13386 DAG.getNode(ISD::XOR, dl, VT, Op0, Op1),
13387 DAG.getConstant(-1, dl, VT));
13389 // (x != y) -> (x ^ y)
13390 return DAG.getNode(ISD::XOR, dl, VT, Op0, Op1);
13393 // (x > y) -> (x & ~y)
13394 return DAG.getNode(ISD::AND, dl, VT, Op0, NotOp1);
13397 // (x < y) -> (~x & y)
13398 return DAG.getNode(ISD::AND, dl, VT, NotOp0, Op1);
13401 // (x <= y) -> (~x | y)
13402 return DAG.getNode(ISD::OR, dl, VT, NotOp0, Op1);
13405 // (x >=y) -> (x | ~y)
13406 return DAG.getNode(ISD::OR, dl, VT, Op0, NotOp1);
13410 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
13411 const X86Subtarget *Subtarget) {
13412 SDValue Op0 = Op.getOperand(0);
13413 SDValue Op1 = Op.getOperand(1);
13414 SDValue CC = Op.getOperand(2);
13415 MVT VT = Op.getSimpleValueType();
13418 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
13419 Op.getValueType().getScalarType() == MVT::i1 &&
13420 "Cannot set masked compare for this operation");
13422 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
13424 bool Unsigned = false;
13427 switch (SetCCOpcode) {
13428 default: llvm_unreachable("Unexpected SETCC condition");
13429 case ISD::SETNE: SSECC = 4; break;
13430 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
13431 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
13432 case ISD::SETLT: Swap = true; //fall-through
13433 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
13434 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
13435 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
13436 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
13437 case ISD::SETULE: Unsigned = true; //fall-through
13438 case ISD::SETLE: SSECC = 2; break;
13442 std::swap(Op0, Op1);
13444 return DAG.getNode(Opc, dl, VT, Op0, Op1);
13445 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
13446 return DAG.getNode(Opc, dl, VT, Op0, Op1,
13447 DAG.getConstant(SSECC, dl, MVT::i8));
13450 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
13451 /// operand \p Op1. If non-trivial (for example because it's not constant)
13452 /// return an empty value.
13453 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
13455 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
13459 MVT VT = Op1.getSimpleValueType();
13460 MVT EVT = VT.getVectorElementType();
13461 unsigned n = VT.getVectorNumElements();
13462 SmallVector<SDValue, 8> ULTOp1;
13464 for (unsigned i = 0; i < n; ++i) {
13465 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
13466 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
13469 // Avoid underflow.
13470 APInt Val = Elt->getAPIntValue();
13474 ULTOp1.push_back(DAG.getConstant(Val - 1, dl, EVT));
13477 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
13480 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
13481 SelectionDAG &DAG) {
13482 SDValue Op0 = Op.getOperand(0);
13483 SDValue Op1 = Op.getOperand(1);
13484 SDValue CC = Op.getOperand(2);
13485 MVT VT = Op.getSimpleValueType();
13486 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
13487 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
13492 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
13493 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
13496 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
13497 unsigned Opc = X86ISD::CMPP;
13498 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
13499 assert(VT.getVectorNumElements() <= 16);
13500 Opc = X86ISD::CMPM;
13502 // In the two special cases we can't handle, emit two comparisons.
13505 unsigned CombineOpc;
13506 if (SetCCOpcode == ISD::SETUEQ) {
13507 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
13509 assert(SetCCOpcode == ISD::SETONE);
13510 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
13513 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
13514 DAG.getConstant(CC0, dl, MVT::i8));
13515 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
13516 DAG.getConstant(CC1, dl, MVT::i8));
13517 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
13519 // Handle all other FP comparisons here.
13520 return DAG.getNode(Opc, dl, VT, Op0, Op1,
13521 DAG.getConstant(SSECC, dl, MVT::i8));
13524 // Break 256-bit integer vector compare into smaller ones.
13525 if (VT.is256BitVector() && !Subtarget->hasInt256())
13526 return Lower256IntVSETCC(Op, DAG);
13528 EVT OpVT = Op1.getValueType();
13529 if (OpVT.getVectorElementType() == MVT::i1)
13530 return LowerBoolVSETCC_AVX512(Op, DAG);
13532 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
13533 if (Subtarget->hasAVX512()) {
13534 if (Op1.getValueType().is512BitVector() ||
13535 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
13536 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
13537 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
13539 // In AVX-512 architecture setcc returns mask with i1 elements,
13540 // But there is no compare instruction for i8 and i16 elements in KNL.
13541 // We are not talking about 512-bit operands in this case, these
13542 // types are illegal.
13544 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
13545 OpVT.getVectorElementType().getSizeInBits() >= 8))
13546 return DAG.getNode(ISD::TRUNCATE, dl, VT,
13547 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
13550 // We are handling one of the integer comparisons here. Since SSE only has
13551 // GT and EQ comparisons for integer, swapping operands and multiple
13552 // operations may be required for some comparisons.
13554 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
13555 bool Subus = false;
13557 switch (SetCCOpcode) {
13558 default: llvm_unreachable("Unexpected SETCC condition");
13559 case ISD::SETNE: Invert = true;
13560 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
13561 case ISD::SETLT: Swap = true;
13562 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
13563 case ISD::SETGE: Swap = true;
13564 case ISD::SETLE: Opc = X86ISD::PCMPGT;
13565 Invert = true; break;
13566 case ISD::SETULT: Swap = true;
13567 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
13568 FlipSigns = true; break;
13569 case ISD::SETUGE: Swap = true;
13570 case ISD::SETULE: Opc = X86ISD::PCMPGT;
13571 FlipSigns = true; Invert = true; break;
13574 // Special case: Use min/max operations for SETULE/SETUGE
13575 MVT VET = VT.getVectorElementType();
13577 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
13578 || (Subtarget->hasSSE2() && (VET == MVT::i8));
13581 switch (SetCCOpcode) {
13583 case ISD::SETULE: Opc = ISD::UMIN; MinMax = true; break;
13584 case ISD::SETUGE: Opc = ISD::UMAX; MinMax = true; break;
13587 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
13590 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
13591 if (!MinMax && hasSubus) {
13592 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
13594 // t = psubus Op0, Op1
13595 // pcmpeq t, <0..0>
13596 switch (SetCCOpcode) {
13598 case ISD::SETULT: {
13599 // If the comparison is against a constant we can turn this into a
13600 // setule. With psubus, setule does not require a swap. This is
13601 // beneficial because the constant in the register is no longer
13602 // destructed as the destination so it can be hoisted out of a loop.
13603 // Only do this pre-AVX since vpcmp* is no longer destructive.
13604 if (Subtarget->hasAVX())
13606 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
13607 if (ULEOp1.getNode()) {
13609 Subus = true; Invert = false; Swap = false;
13613 // Psubus is better than flip-sign because it requires no inversion.
13614 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
13615 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
13619 Opc = X86ISD::SUBUS;
13625 std::swap(Op0, Op1);
13627 // Check that the operation in question is available (most are plain SSE2,
13628 // but PCMPGTQ and PCMPEQQ have different requirements).
13629 if (VT == MVT::v2i64) {
13630 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
13631 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
13633 // First cast everything to the right type.
13634 Op0 = DAG.getBitcast(MVT::v4i32, Op0);
13635 Op1 = DAG.getBitcast(MVT::v4i32, Op1);
13637 // Since SSE has no unsigned integer comparisons, we need to flip the sign
13638 // bits of the inputs before performing those operations. The lower
13639 // compare is always unsigned.
13642 SB = DAG.getConstant(0x80000000U, dl, MVT::v4i32);
13644 SDValue Sign = DAG.getConstant(0x80000000U, dl, MVT::i32);
13645 SDValue Zero = DAG.getConstant(0x00000000U, dl, MVT::i32);
13646 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
13647 Sign, Zero, Sign, Zero);
13649 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
13650 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
13652 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
13653 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
13654 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
13656 // Create masks for only the low parts/high parts of the 64 bit integers.
13657 static const int MaskHi[] = { 1, 1, 3, 3 };
13658 static const int MaskLo[] = { 0, 0, 2, 2 };
13659 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
13660 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
13661 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
13663 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
13664 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
13667 Result = DAG.getNOT(dl, Result, MVT::v4i32);
13669 return DAG.getBitcast(VT, Result);
13672 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
13673 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
13674 // pcmpeqd + pshufd + pand.
13675 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
13677 // First cast everything to the right type.
13678 Op0 = DAG.getBitcast(MVT::v4i32, Op0);
13679 Op1 = DAG.getBitcast(MVT::v4i32, Op1);
13682 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
13684 // Make sure the lower and upper halves are both all-ones.
13685 static const int Mask[] = { 1, 0, 3, 2 };
13686 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
13687 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
13690 Result = DAG.getNOT(dl, Result, MVT::v4i32);
13692 return DAG.getBitcast(VT, Result);
13696 // Since SSE has no unsigned integer comparisons, we need to flip the sign
13697 // bits of the inputs before performing those operations.
13699 EVT EltVT = VT.getVectorElementType();
13700 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), dl,
13702 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
13703 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
13706 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
13708 // If the logical-not of the result is required, perform that now.
13710 Result = DAG.getNOT(dl, Result, VT);
13713 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
13716 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
13717 getZeroVector(VT, Subtarget, DAG, dl));
13722 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
13724 MVT VT = Op.getSimpleValueType();
13726 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
13728 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
13729 && "SetCC type must be 8-bit or 1-bit integer");
13730 SDValue Op0 = Op.getOperand(0);
13731 SDValue Op1 = Op.getOperand(1);
13733 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
13735 // Optimize to BT if possible.
13736 // Lower (X & (1 << N)) == 0 to BT(X, N).
13737 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
13738 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
13739 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
13740 Op1.getOpcode() == ISD::Constant &&
13741 cast<ConstantSDNode>(Op1)->isNullValue() &&
13742 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
13743 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
13744 if (NewSetCC.getNode()) {
13746 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewSetCC);
13751 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
13753 if (Op1.getOpcode() == ISD::Constant &&
13754 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
13755 cast<ConstantSDNode>(Op1)->isNullValue()) &&
13756 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
13758 // If the input is a setcc, then reuse the input setcc or use a new one with
13759 // the inverted condition.
13760 if (Op0.getOpcode() == X86ISD::SETCC) {
13761 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
13762 bool Invert = (CC == ISD::SETNE) ^
13763 cast<ConstantSDNode>(Op1)->isNullValue();
13767 CCode = X86::GetOppositeBranchCondition(CCode);
13768 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13769 DAG.getConstant(CCode, dl, MVT::i8),
13770 Op0.getOperand(1));
13772 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
13776 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
13777 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
13778 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
13780 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
13781 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, dl, MVT::i1), NewCC);
13784 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
13785 unsigned X86CC = TranslateX86CC(CC, dl, isFP, Op0, Op1, DAG);
13786 if (X86CC == X86::COND_INVALID)
13789 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
13790 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
13791 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13792 DAG.getConstant(X86CC, dl, MVT::i8), EFLAGS);
13794 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
13798 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
13799 static bool isX86LogicalCmp(SDValue Op) {
13800 unsigned Opc = Op.getNode()->getOpcode();
13801 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
13802 Opc == X86ISD::SAHF)
13804 if (Op.getResNo() == 1 &&
13805 (Opc == X86ISD::ADD ||
13806 Opc == X86ISD::SUB ||
13807 Opc == X86ISD::ADC ||
13808 Opc == X86ISD::SBB ||
13809 Opc == X86ISD::SMUL ||
13810 Opc == X86ISD::UMUL ||
13811 Opc == X86ISD::INC ||
13812 Opc == X86ISD::DEC ||
13813 Opc == X86ISD::OR ||
13814 Opc == X86ISD::XOR ||
13815 Opc == X86ISD::AND))
13818 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
13824 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
13825 if (V.getOpcode() != ISD::TRUNCATE)
13828 SDValue VOp0 = V.getOperand(0);
13829 unsigned InBits = VOp0.getValueSizeInBits();
13830 unsigned Bits = V.getValueSizeInBits();
13831 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
13834 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
13835 bool addTest = true;
13836 SDValue Cond = Op.getOperand(0);
13837 SDValue Op1 = Op.getOperand(1);
13838 SDValue Op2 = Op.getOperand(2);
13840 EVT VT = Op1.getValueType();
13843 // Lower FP selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
13844 // are available or VBLENDV if AVX is available.
13845 // Otherwise FP cmovs get lowered into a less efficient branch sequence later.
13846 if (Cond.getOpcode() == ISD::SETCC &&
13847 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
13848 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
13849 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
13850 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
13851 int SSECC = translateX86FSETCC(
13852 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
13855 if (Subtarget->hasAVX512()) {
13856 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
13857 DAG.getConstant(SSECC, DL, MVT::i8));
13858 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
13861 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
13862 DAG.getConstant(SSECC, DL, MVT::i8));
13864 // If we have AVX, we can use a variable vector select (VBLENDV) instead
13865 // of 3 logic instructions for size savings and potentially speed.
13866 // Unfortunately, there is no scalar form of VBLENDV.
13868 // If either operand is a constant, don't try this. We can expect to
13869 // optimize away at least one of the logic instructions later in that
13870 // case, so that sequence would be faster than a variable blend.
13872 // BLENDV was introduced with SSE 4.1, but the 2 register form implicitly
13873 // uses XMM0 as the selection register. That may need just as many
13874 // instructions as the AND/ANDN/OR sequence due to register moves, so
13877 if (Subtarget->hasAVX() &&
13878 !isa<ConstantFPSDNode>(Op1) && !isa<ConstantFPSDNode>(Op2)) {
13880 // Convert to vectors, do a VSELECT, and convert back to scalar.
13881 // All of the conversions should be optimized away.
13883 EVT VecVT = VT == MVT::f32 ? MVT::v4f32 : MVT::v2f64;
13884 SDValue VOp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op1);
13885 SDValue VOp2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op2);
13886 SDValue VCmp = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Cmp);
13888 EVT VCmpVT = VT == MVT::f32 ? MVT::v4i32 : MVT::v2i64;
13889 VCmp = DAG.getBitcast(VCmpVT, VCmp);
13891 SDValue VSel = DAG.getNode(ISD::VSELECT, DL, VecVT, VCmp, VOp1, VOp2);
13893 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT,
13894 VSel, DAG.getIntPtrConstant(0, DL));
13896 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
13897 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
13898 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
13902 if (VT.isVector() && VT.getScalarType() == MVT::i1) {
13904 if (ISD::isBuildVectorOfConstantSDNodes(Op1.getNode()))
13905 Op1Scalar = ConvertI1VectorToInterger(Op1, DAG);
13906 else if (Op1.getOpcode() == ISD::BITCAST && Op1.getOperand(0))
13907 Op1Scalar = Op1.getOperand(0);
13909 if (ISD::isBuildVectorOfConstantSDNodes(Op2.getNode()))
13910 Op2Scalar = ConvertI1VectorToInterger(Op2, DAG);
13911 else if (Op2.getOpcode() == ISD::BITCAST && Op2.getOperand(0))
13912 Op2Scalar = Op2.getOperand(0);
13913 if (Op1Scalar.getNode() && Op2Scalar.getNode()) {
13914 SDValue newSelect = DAG.getNode(ISD::SELECT, DL,
13915 Op1Scalar.getValueType(),
13916 Cond, Op1Scalar, Op2Scalar);
13917 if (newSelect.getValueSizeInBits() == VT.getSizeInBits())
13918 return DAG.getBitcast(VT, newSelect);
13919 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, newSelect);
13920 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, ExtVec,
13921 DAG.getIntPtrConstant(0, DL));
13925 if (VT == MVT::v4i1 || VT == MVT::v2i1) {
13926 SDValue zeroConst = DAG.getIntPtrConstant(0, DL);
13927 Op1 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
13928 DAG.getUNDEF(MVT::v8i1), Op1, zeroConst);
13929 Op2 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
13930 DAG.getUNDEF(MVT::v8i1), Op2, zeroConst);
13931 SDValue newSelect = DAG.getNode(ISD::SELECT, DL, MVT::v8i1,
13933 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, newSelect, zeroConst);
13936 if (Cond.getOpcode() == ISD::SETCC) {
13937 SDValue NewCond = LowerSETCC(Cond, DAG);
13938 if (NewCond.getNode())
13942 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
13943 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
13944 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
13945 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
13946 if (Cond.getOpcode() == X86ISD::SETCC &&
13947 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
13948 isZero(Cond.getOperand(1).getOperand(1))) {
13949 SDValue Cmp = Cond.getOperand(1);
13951 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
13953 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
13954 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
13955 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
13957 SDValue CmpOp0 = Cmp.getOperand(0);
13958 // Apply further optimizations for special cases
13959 // (select (x != 0), -1, 0) -> neg & sbb
13960 // (select (x == 0), 0, -1) -> neg & sbb
13961 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
13962 if (YC->isNullValue() &&
13963 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
13964 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
13965 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
13966 DAG.getConstant(0, DL,
13967 CmpOp0.getValueType()),
13969 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
13970 DAG.getConstant(X86::COND_B, DL, MVT::i8),
13971 SDValue(Neg.getNode(), 1));
13975 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
13976 CmpOp0, DAG.getConstant(1, DL, CmpOp0.getValueType()));
13977 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
13979 SDValue Res = // Res = 0 or -1.
13980 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
13981 DAG.getConstant(X86::COND_B, DL, MVT::i8), Cmp);
13983 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
13984 Res = DAG.getNOT(DL, Res, Res.getValueType());
13986 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
13987 if (!N2C || !N2C->isNullValue())
13988 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
13993 // Look past (and (setcc_carry (cmp ...)), 1).
13994 if (Cond.getOpcode() == ISD::AND &&
13995 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
13996 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
13997 if (C && C->getAPIntValue() == 1)
13998 Cond = Cond.getOperand(0);
14001 // If condition flag is set by a X86ISD::CMP, then use it as the condition
14002 // setting operand in place of the X86ISD::SETCC.
14003 unsigned CondOpcode = Cond.getOpcode();
14004 if (CondOpcode == X86ISD::SETCC ||
14005 CondOpcode == X86ISD::SETCC_CARRY) {
14006 CC = Cond.getOperand(0);
14008 SDValue Cmp = Cond.getOperand(1);
14009 unsigned Opc = Cmp.getOpcode();
14010 MVT VT = Op.getSimpleValueType();
14012 bool IllegalFPCMov = false;
14013 if (VT.isFloatingPoint() && !VT.isVector() &&
14014 !isScalarFPTypeInSSEReg(VT)) // FPStack?
14015 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
14017 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
14018 Opc == X86ISD::BT) { // FIXME
14022 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
14023 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
14024 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
14025 Cond.getOperand(0).getValueType() != MVT::i8)) {
14026 SDValue LHS = Cond.getOperand(0);
14027 SDValue RHS = Cond.getOperand(1);
14028 unsigned X86Opcode;
14031 switch (CondOpcode) {
14032 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
14033 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
14034 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
14035 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
14036 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
14037 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
14038 default: llvm_unreachable("unexpected overflowing operator");
14040 if (CondOpcode == ISD::UMULO)
14041 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
14044 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14046 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
14048 if (CondOpcode == ISD::UMULO)
14049 Cond = X86Op.getValue(2);
14051 Cond = X86Op.getValue(1);
14053 CC = DAG.getConstant(X86Cond, DL, MVT::i8);
14058 // Look pass the truncate if the high bits are known zero.
14059 if (isTruncWithZeroHighBitsInput(Cond, DAG))
14060 Cond = Cond.getOperand(0);
14062 // We know the result of AND is compared against zero. Try to match
14064 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
14065 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
14066 if (NewSetCC.getNode()) {
14067 CC = NewSetCC.getOperand(0);
14068 Cond = NewSetCC.getOperand(1);
14075 CC = DAG.getConstant(X86::COND_NE, DL, MVT::i8);
14076 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
14079 // a < b ? -1 : 0 -> RES = ~setcc_carry
14080 // a < b ? 0 : -1 -> RES = setcc_carry
14081 // a >= b ? -1 : 0 -> RES = setcc_carry
14082 // a >= b ? 0 : -1 -> RES = ~setcc_carry
14083 if (Cond.getOpcode() == X86ISD::SUB) {
14084 Cond = ConvertCmpIfNecessary(Cond, DAG);
14085 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
14087 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
14088 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
14089 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14090 DAG.getConstant(X86::COND_B, DL, MVT::i8),
14092 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
14093 return DAG.getNOT(DL, Res, Res.getValueType());
14098 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
14099 // widen the cmov and push the truncate through. This avoids introducing a new
14100 // branch during isel and doesn't add any extensions.
14101 if (Op.getValueType() == MVT::i8 &&
14102 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
14103 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
14104 if (T1.getValueType() == T2.getValueType() &&
14105 // Blacklist CopyFromReg to avoid partial register stalls.
14106 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
14107 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
14108 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
14109 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
14113 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
14114 // condition is true.
14115 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
14116 SDValue Ops[] = { Op2, Op1, CC, Cond };
14117 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
14120 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op,
14121 const X86Subtarget *Subtarget,
14122 SelectionDAG &DAG) {
14123 MVT VT = Op->getSimpleValueType(0);
14124 SDValue In = Op->getOperand(0);
14125 MVT InVT = In.getSimpleValueType();
14126 MVT VTElt = VT.getVectorElementType();
14127 MVT InVTElt = InVT.getVectorElementType();
14131 if ((InVTElt == MVT::i1) &&
14132 (((Subtarget->hasBWI() && Subtarget->hasVLX() &&
14133 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() <= 16)) ||
14135 ((Subtarget->hasBWI() && VT.is512BitVector() &&
14136 VTElt.getSizeInBits() <= 16)) ||
14138 ((Subtarget->hasDQI() && Subtarget->hasVLX() &&
14139 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() >= 32)) ||
14141 ((Subtarget->hasDQI() && VT.is512BitVector() &&
14142 VTElt.getSizeInBits() >= 32))))
14143 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14145 unsigned int NumElts = VT.getVectorNumElements();
14147 if (NumElts != 8 && NumElts != 16 && !Subtarget->hasBWI())
14150 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1) {
14151 if (In.getOpcode() == X86ISD::VSEXT || In.getOpcode() == X86ISD::VZEXT)
14152 return DAG.getNode(In.getOpcode(), dl, VT, In.getOperand(0));
14153 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14156 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
14157 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
14159 DAG.getConstant(APInt::getAllOnesValue(ExtVT.getScalarSizeInBits()), dl,
14162 DAG.getConstant(APInt::getNullValue(ExtVT.getScalarSizeInBits()), dl, ExtVT);
14164 SDValue V = DAG.getNode(ISD::VSELECT, dl, ExtVT, In, NegOne, Zero);
14165 if (VT.is512BitVector())
14167 return DAG.getNode(X86ISD::VTRUNC, dl, VT, V);
14170 static SDValue LowerSIGN_EXTEND_VECTOR_INREG(SDValue Op,
14171 const X86Subtarget *Subtarget,
14172 SelectionDAG &DAG) {
14173 SDValue In = Op->getOperand(0);
14174 MVT VT = Op->getSimpleValueType(0);
14175 MVT InVT = In.getSimpleValueType();
14176 assert(VT.getSizeInBits() == InVT.getSizeInBits());
14178 MVT InSVT = InVT.getScalarType();
14179 assert(VT.getScalarType().getScalarSizeInBits() > InSVT.getScalarSizeInBits());
14181 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
14183 if (InSVT != MVT::i32 && InSVT != MVT::i16 && InSVT != MVT::i8)
14188 // SSE41 targets can use the pmovsx* instructions directly.
14189 if (Subtarget->hasSSE41())
14190 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14192 // pre-SSE41 targets unpack lower lanes and then sign-extend using SRAI.
14196 // As SRAI is only available on i16/i32 types, we expand only up to i32
14197 // and handle i64 separately.
14198 while (CurrVT != VT && CurrVT.getScalarType() != MVT::i32) {
14199 Curr = DAG.getNode(X86ISD::UNPCKL, dl, CurrVT, DAG.getUNDEF(CurrVT), Curr);
14200 MVT CurrSVT = MVT::getIntegerVT(CurrVT.getScalarSizeInBits() * 2);
14201 CurrVT = MVT::getVectorVT(CurrSVT, CurrVT.getVectorNumElements() / 2);
14202 Curr = DAG.getBitcast(CurrVT, Curr);
14205 SDValue SignExt = Curr;
14206 if (CurrVT != InVT) {
14207 unsigned SignExtShift =
14208 CurrVT.getScalarSizeInBits() - InSVT.getScalarSizeInBits();
14209 SignExt = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr,
14210 DAG.getConstant(SignExtShift, dl, MVT::i8));
14216 if (VT == MVT::v2i64 && CurrVT == MVT::v4i32) {
14217 SDValue Sign = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr,
14218 DAG.getConstant(31, dl, MVT::i8));
14219 SDValue Ext = DAG.getVectorShuffle(CurrVT, dl, SignExt, Sign, {0, 4, 1, 5});
14220 return DAG.getBitcast(VT, Ext);
14226 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
14227 SelectionDAG &DAG) {
14228 MVT VT = Op->getSimpleValueType(0);
14229 SDValue In = Op->getOperand(0);
14230 MVT InVT = In.getSimpleValueType();
14233 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
14234 return LowerSIGN_EXTEND_AVX512(Op, Subtarget, DAG);
14236 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
14237 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
14238 (VT != MVT::v16i16 || InVT != MVT::v16i8))
14241 if (Subtarget->hasInt256())
14242 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14244 // Optimize vectors in AVX mode
14245 // Sign extend v8i16 to v8i32 and
14248 // Divide input vector into two parts
14249 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
14250 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
14251 // concat the vectors to original VT
14253 unsigned NumElems = InVT.getVectorNumElements();
14254 SDValue Undef = DAG.getUNDEF(InVT);
14256 SmallVector<int,8> ShufMask1(NumElems, -1);
14257 for (unsigned i = 0; i != NumElems/2; ++i)
14260 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
14262 SmallVector<int,8> ShufMask2(NumElems, -1);
14263 for (unsigned i = 0; i != NumElems/2; ++i)
14264 ShufMask2[i] = i + NumElems/2;
14266 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
14268 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
14269 VT.getVectorNumElements()/2);
14271 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
14272 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
14274 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14277 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
14278 // may emit an illegal shuffle but the expansion is still better than scalar
14279 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
14280 // we'll emit a shuffle and a arithmetic shift.
14281 // FIXME: Is the expansion actually better than scalar code? It doesn't seem so.
14282 // TODO: It is possible to support ZExt by zeroing the undef values during
14283 // the shuffle phase or after the shuffle.
14284 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
14285 SelectionDAG &DAG) {
14286 MVT RegVT = Op.getSimpleValueType();
14287 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
14288 assert(RegVT.isInteger() &&
14289 "We only custom lower integer vector sext loads.");
14291 // Nothing useful we can do without SSE2 shuffles.
14292 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
14294 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
14296 EVT MemVT = Ld->getMemoryVT();
14297 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14298 unsigned RegSz = RegVT.getSizeInBits();
14300 ISD::LoadExtType Ext = Ld->getExtensionType();
14302 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
14303 && "Only anyext and sext are currently implemented.");
14304 assert(MemVT != RegVT && "Cannot extend to the same type");
14305 assert(MemVT.isVector() && "Must load a vector from memory");
14307 unsigned NumElems = RegVT.getVectorNumElements();
14308 unsigned MemSz = MemVT.getSizeInBits();
14309 assert(RegSz > MemSz && "Register size must be greater than the mem size");
14311 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
14312 // The only way in which we have a legal 256-bit vector result but not the
14313 // integer 256-bit operations needed to directly lower a sextload is if we
14314 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
14315 // a 128-bit vector and a normal sign_extend to 256-bits that should get
14316 // correctly legalized. We do this late to allow the canonical form of
14317 // sextload to persist throughout the rest of the DAG combiner -- it wants
14318 // to fold together any extensions it can, and so will fuse a sign_extend
14319 // of an sextload into a sextload targeting a wider value.
14321 if (MemSz == 128) {
14322 // Just switch this to a normal load.
14323 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
14324 "it must be a legal 128-bit vector "
14326 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
14327 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
14328 Ld->isInvariant(), Ld->getAlignment());
14330 assert(MemSz < 128 &&
14331 "Can't extend a type wider than 128 bits to a 256 bit vector!");
14332 // Do an sext load to a 128-bit vector type. We want to use the same
14333 // number of elements, but elements half as wide. This will end up being
14334 // recursively lowered by this routine, but will succeed as we definitely
14335 // have all the necessary features if we're using AVX1.
14337 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
14338 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
14340 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
14341 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
14342 Ld->isNonTemporal(), Ld->isInvariant(),
14343 Ld->getAlignment());
14346 // Replace chain users with the new chain.
14347 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
14348 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
14350 // Finally, do a normal sign-extend to the desired register.
14351 return DAG.getSExtOrTrunc(Load, dl, RegVT);
14354 // All sizes must be a power of two.
14355 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
14356 "Non-power-of-two elements are not custom lowered!");
14358 // Attempt to load the original value using scalar loads.
14359 // Find the largest scalar type that divides the total loaded size.
14360 MVT SclrLoadTy = MVT::i8;
14361 for (MVT Tp : MVT::integer_valuetypes()) {
14362 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
14367 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
14368 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
14370 SclrLoadTy = MVT::f64;
14372 // Calculate the number of scalar loads that we need to perform
14373 // in order to load our vector from memory.
14374 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
14376 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
14377 "Can only lower sext loads with a single scalar load!");
14379 unsigned loadRegZize = RegSz;
14380 if (Ext == ISD::SEXTLOAD && RegSz >= 256)
14383 // Represent our vector as a sequence of elements which are the
14384 // largest scalar that we can load.
14385 EVT LoadUnitVecVT = EVT::getVectorVT(
14386 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
14388 // Represent the data using the same element type that is stored in
14389 // memory. In practice, we ''widen'' MemVT.
14391 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
14392 loadRegZize / MemVT.getScalarType().getSizeInBits());
14394 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
14395 "Invalid vector type");
14397 // We can't shuffle using an illegal type.
14398 assert(TLI.isTypeLegal(WideVecVT) &&
14399 "We only lower types that form legal widened vector types");
14401 SmallVector<SDValue, 8> Chains;
14402 SDValue Ptr = Ld->getBasePtr();
14403 SDValue Increment =
14404 DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, dl, TLI.getPointerTy());
14405 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
14407 for (unsigned i = 0; i < NumLoads; ++i) {
14408 // Perform a single load.
14409 SDValue ScalarLoad =
14410 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
14411 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
14412 Ld->getAlignment());
14413 Chains.push_back(ScalarLoad.getValue(1));
14414 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
14415 // another round of DAGCombining.
14417 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
14419 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
14420 ScalarLoad, DAG.getIntPtrConstant(i, dl));
14422 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
14425 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
14427 // Bitcast the loaded value to a vector of the original element type, in
14428 // the size of the target vector type.
14429 SDValue SlicedVec = DAG.getBitcast(WideVecVT, Res);
14430 unsigned SizeRatio = RegSz / MemSz;
14432 if (Ext == ISD::SEXTLOAD) {
14433 // If we have SSE4.1, we can directly emit a VSEXT node.
14434 if (Subtarget->hasSSE41()) {
14435 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
14436 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14440 // Otherwise we'll shuffle the small elements in the high bits of the
14441 // larger type and perform an arithmetic shift. If the shift is not legal
14442 // it's better to scalarize.
14443 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
14444 "We can't implement a sext load without an arithmetic right shift!");
14446 // Redistribute the loaded elements into the different locations.
14447 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
14448 for (unsigned i = 0; i != NumElems; ++i)
14449 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
14451 SDValue Shuff = DAG.getVectorShuffle(
14452 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
14454 Shuff = DAG.getBitcast(RegVT, Shuff);
14456 // Build the arithmetic shift.
14457 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
14458 MemVT.getVectorElementType().getSizeInBits();
14460 DAG.getNode(ISD::SRA, dl, RegVT, Shuff,
14461 DAG.getConstant(Amt, dl, RegVT));
14463 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14467 // Redistribute the loaded elements into the different locations.
14468 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
14469 for (unsigned i = 0; i != NumElems; ++i)
14470 ShuffleVec[i * SizeRatio] = i;
14472 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
14473 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
14475 // Bitcast to the requested type.
14476 Shuff = DAG.getBitcast(RegVT, Shuff);
14477 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14481 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
14482 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
14483 // from the AND / OR.
14484 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
14485 Opc = Op.getOpcode();
14486 if (Opc != ISD::OR && Opc != ISD::AND)
14488 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
14489 Op.getOperand(0).hasOneUse() &&
14490 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
14491 Op.getOperand(1).hasOneUse());
14494 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
14495 // 1 and that the SETCC node has a single use.
14496 static bool isXor1OfSetCC(SDValue Op) {
14497 if (Op.getOpcode() != ISD::XOR)
14499 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
14500 if (N1C && N1C->getAPIntValue() == 1) {
14501 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
14502 Op.getOperand(0).hasOneUse();
14507 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
14508 bool addTest = true;
14509 SDValue Chain = Op.getOperand(0);
14510 SDValue Cond = Op.getOperand(1);
14511 SDValue Dest = Op.getOperand(2);
14514 bool Inverted = false;
14516 if (Cond.getOpcode() == ISD::SETCC) {
14517 // Check for setcc([su]{add,sub,mul}o == 0).
14518 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
14519 isa<ConstantSDNode>(Cond.getOperand(1)) &&
14520 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
14521 Cond.getOperand(0).getResNo() == 1 &&
14522 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
14523 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
14524 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
14525 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
14526 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
14527 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
14529 Cond = Cond.getOperand(0);
14531 SDValue NewCond = LowerSETCC(Cond, DAG);
14532 if (NewCond.getNode())
14537 // FIXME: LowerXALUO doesn't handle these!!
14538 else if (Cond.getOpcode() == X86ISD::ADD ||
14539 Cond.getOpcode() == X86ISD::SUB ||
14540 Cond.getOpcode() == X86ISD::SMUL ||
14541 Cond.getOpcode() == X86ISD::UMUL)
14542 Cond = LowerXALUO(Cond, DAG);
14545 // Look pass (and (setcc_carry (cmp ...)), 1).
14546 if (Cond.getOpcode() == ISD::AND &&
14547 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
14548 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
14549 if (C && C->getAPIntValue() == 1)
14550 Cond = Cond.getOperand(0);
14553 // If condition flag is set by a X86ISD::CMP, then use it as the condition
14554 // setting operand in place of the X86ISD::SETCC.
14555 unsigned CondOpcode = Cond.getOpcode();
14556 if (CondOpcode == X86ISD::SETCC ||
14557 CondOpcode == X86ISD::SETCC_CARRY) {
14558 CC = Cond.getOperand(0);
14560 SDValue Cmp = Cond.getOperand(1);
14561 unsigned Opc = Cmp.getOpcode();
14562 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
14563 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
14567 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
14571 // These can only come from an arithmetic instruction with overflow,
14572 // e.g. SADDO, UADDO.
14573 Cond = Cond.getNode()->getOperand(1);
14579 CondOpcode = Cond.getOpcode();
14580 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
14581 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
14582 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
14583 Cond.getOperand(0).getValueType() != MVT::i8)) {
14584 SDValue LHS = Cond.getOperand(0);
14585 SDValue RHS = Cond.getOperand(1);
14586 unsigned X86Opcode;
14589 // Keep this in sync with LowerXALUO, otherwise we might create redundant
14590 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
14592 switch (CondOpcode) {
14593 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
14595 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
14597 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
14600 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
14601 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
14603 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
14605 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
14608 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
14609 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
14610 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
14611 default: llvm_unreachable("unexpected overflowing operator");
14614 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
14615 if (CondOpcode == ISD::UMULO)
14616 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
14619 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14621 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
14623 if (CondOpcode == ISD::UMULO)
14624 Cond = X86Op.getValue(2);
14626 Cond = X86Op.getValue(1);
14628 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
14632 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
14633 SDValue Cmp = Cond.getOperand(0).getOperand(1);
14634 if (CondOpc == ISD::OR) {
14635 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
14636 // two branches instead of an explicit OR instruction with a
14638 if (Cmp == Cond.getOperand(1).getOperand(1) &&
14639 isX86LogicalCmp(Cmp)) {
14640 CC = Cond.getOperand(0).getOperand(0);
14641 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14642 Chain, Dest, CC, Cmp);
14643 CC = Cond.getOperand(1).getOperand(0);
14647 } else { // ISD::AND
14648 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
14649 // two branches instead of an explicit AND instruction with a
14650 // separate test. However, we only do this if this block doesn't
14651 // have a fall-through edge, because this requires an explicit
14652 // jmp when the condition is false.
14653 if (Cmp == Cond.getOperand(1).getOperand(1) &&
14654 isX86LogicalCmp(Cmp) &&
14655 Op.getNode()->hasOneUse()) {
14656 X86::CondCode CCode =
14657 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
14658 CCode = X86::GetOppositeBranchCondition(CCode);
14659 CC = DAG.getConstant(CCode, dl, MVT::i8);
14660 SDNode *User = *Op.getNode()->use_begin();
14661 // Look for an unconditional branch following this conditional branch.
14662 // We need this because we need to reverse the successors in order
14663 // to implement FCMP_OEQ.
14664 if (User->getOpcode() == ISD::BR) {
14665 SDValue FalseBB = User->getOperand(1);
14667 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
14668 assert(NewBR == User);
14672 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14673 Chain, Dest, CC, Cmp);
14674 X86::CondCode CCode =
14675 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
14676 CCode = X86::GetOppositeBranchCondition(CCode);
14677 CC = DAG.getConstant(CCode, dl, MVT::i8);
14683 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
14684 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
14685 // It should be transformed during dag combiner except when the condition
14686 // is set by a arithmetics with overflow node.
14687 X86::CondCode CCode =
14688 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
14689 CCode = X86::GetOppositeBranchCondition(CCode);
14690 CC = DAG.getConstant(CCode, dl, MVT::i8);
14691 Cond = Cond.getOperand(0).getOperand(1);
14693 } else if (Cond.getOpcode() == ISD::SETCC &&
14694 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
14695 // For FCMP_OEQ, we can emit
14696 // two branches instead of an explicit AND instruction with a
14697 // separate test. However, we only do this if this block doesn't
14698 // have a fall-through edge, because this requires an explicit
14699 // jmp when the condition is false.
14700 if (Op.getNode()->hasOneUse()) {
14701 SDNode *User = *Op.getNode()->use_begin();
14702 // Look for an unconditional branch following this conditional branch.
14703 // We need this because we need to reverse the successors in order
14704 // to implement FCMP_OEQ.
14705 if (User->getOpcode() == ISD::BR) {
14706 SDValue FalseBB = User->getOperand(1);
14708 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
14709 assert(NewBR == User);
14713 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
14714 Cond.getOperand(0), Cond.getOperand(1));
14715 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14716 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
14717 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14718 Chain, Dest, CC, Cmp);
14719 CC = DAG.getConstant(X86::COND_P, dl, MVT::i8);
14724 } else if (Cond.getOpcode() == ISD::SETCC &&
14725 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
14726 // For FCMP_UNE, we can emit
14727 // two branches instead of an explicit AND instruction with a
14728 // separate test. However, we only do this if this block doesn't
14729 // have a fall-through edge, because this requires an explicit
14730 // jmp when the condition is false.
14731 if (Op.getNode()->hasOneUse()) {
14732 SDNode *User = *Op.getNode()->use_begin();
14733 // Look for an unconditional branch following this conditional branch.
14734 // We need this because we need to reverse the successors in order
14735 // to implement FCMP_UNE.
14736 if (User->getOpcode() == ISD::BR) {
14737 SDValue FalseBB = User->getOperand(1);
14739 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
14740 assert(NewBR == User);
14743 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
14744 Cond.getOperand(0), Cond.getOperand(1));
14745 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14746 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
14747 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14748 Chain, Dest, CC, Cmp);
14749 CC = DAG.getConstant(X86::COND_NP, dl, MVT::i8);
14759 // Look pass the truncate if the high bits are known zero.
14760 if (isTruncWithZeroHighBitsInput(Cond, DAG))
14761 Cond = Cond.getOperand(0);
14763 // We know the result of AND is compared against zero. Try to match
14765 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
14766 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
14767 if (NewSetCC.getNode()) {
14768 CC = NewSetCC.getOperand(0);
14769 Cond = NewSetCC.getOperand(1);
14776 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
14777 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
14778 Cond = EmitTest(Cond, X86Cond, dl, DAG);
14780 Cond = ConvertCmpIfNecessary(Cond, DAG);
14781 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14782 Chain, Dest, CC, Cond);
14785 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
14786 // Calls to _alloca are needed to probe the stack when allocating more than 4k
14787 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
14788 // that the guard pages used by the OS virtual memory manager are allocated in
14789 // correct sequence.
14791 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
14792 SelectionDAG &DAG) const {
14793 MachineFunction &MF = DAG.getMachineFunction();
14794 bool SplitStack = MF.shouldSplitStack();
14795 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMachO()) ||
14800 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14801 SDNode* Node = Op.getNode();
14803 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
14804 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
14805 " not tell us which reg is the stack pointer!");
14806 EVT VT = Node->getValueType(0);
14807 SDValue Tmp1 = SDValue(Node, 0);
14808 SDValue Tmp2 = SDValue(Node, 1);
14809 SDValue Tmp3 = Node->getOperand(2);
14810 SDValue Chain = Tmp1.getOperand(0);
14812 // Chain the dynamic stack allocation so that it doesn't modify the stack
14813 // pointer when other instructions are using the stack.
14814 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, dl, true),
14817 SDValue Size = Tmp2.getOperand(1);
14818 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
14819 Chain = SP.getValue(1);
14820 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
14821 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
14822 unsigned StackAlign = TFI.getStackAlignment();
14823 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
14824 if (Align > StackAlign)
14825 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
14826 DAG.getConstant(-(uint64_t)Align, dl, VT));
14827 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
14829 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, dl, true),
14830 DAG.getIntPtrConstant(0, dl, true), SDValue(),
14833 SDValue Ops[2] = { Tmp1, Tmp2 };
14834 return DAG.getMergeValues(Ops, dl);
14838 SDValue Chain = Op.getOperand(0);
14839 SDValue Size = Op.getOperand(1);
14840 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
14841 EVT VT = Op.getNode()->getValueType(0);
14843 bool Is64Bit = Subtarget->is64Bit();
14844 EVT SPTy = getPointerTy();
14847 MachineRegisterInfo &MRI = MF.getRegInfo();
14850 // The 64 bit implementation of segmented stacks needs to clobber both r10
14851 // r11. This makes it impossible to use it along with nested parameters.
14852 const Function *F = MF.getFunction();
14854 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
14856 if (I->hasNestAttr())
14857 report_fatal_error("Cannot use segmented stacks with functions that "
14858 "have nested arguments.");
14861 const TargetRegisterClass *AddrRegClass =
14862 getRegClassFor(getPointerTy());
14863 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
14864 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
14865 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
14866 DAG.getRegister(Vreg, SPTy));
14867 SDValue Ops1[2] = { Value, Chain };
14868 return DAG.getMergeValues(Ops1, dl);
14871 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
14873 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
14874 Flag = Chain.getValue(1);
14875 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
14877 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
14879 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
14880 unsigned SPReg = RegInfo->getStackRegister();
14881 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
14882 Chain = SP.getValue(1);
14885 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
14886 DAG.getConstant(-(uint64_t)Align, dl, VT));
14887 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
14890 SDValue Ops1[2] = { SP, Chain };
14891 return DAG.getMergeValues(Ops1, dl);
14895 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
14896 MachineFunction &MF = DAG.getMachineFunction();
14897 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
14899 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
14902 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
14903 // vastart just stores the address of the VarArgsFrameIndex slot into the
14904 // memory location argument.
14905 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
14907 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
14908 MachinePointerInfo(SV), false, false, 0);
14912 // gp_offset (0 - 6 * 8)
14913 // fp_offset (48 - 48 + 8 * 16)
14914 // overflow_arg_area (point to parameters coming in memory).
14916 SmallVector<SDValue, 8> MemOps;
14917 SDValue FIN = Op.getOperand(1);
14919 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
14920 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
14922 FIN, MachinePointerInfo(SV), false, false, 0);
14923 MemOps.push_back(Store);
14926 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
14927 FIN, DAG.getIntPtrConstant(4, DL));
14928 Store = DAG.getStore(Op.getOperand(0), DL,
14929 DAG.getConstant(FuncInfo->getVarArgsFPOffset(), DL,
14931 FIN, MachinePointerInfo(SV, 4), false, false, 0);
14932 MemOps.push_back(Store);
14934 // Store ptr to overflow_arg_area
14935 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
14936 FIN, DAG.getIntPtrConstant(4, DL));
14937 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
14939 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
14940 MachinePointerInfo(SV, 8),
14942 MemOps.push_back(Store);
14944 // Store ptr to reg_save_area.
14945 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
14946 FIN, DAG.getIntPtrConstant(8, DL));
14947 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
14949 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
14950 MachinePointerInfo(SV, 16), false, false, 0);
14951 MemOps.push_back(Store);
14952 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
14955 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
14956 assert(Subtarget->is64Bit() &&
14957 "LowerVAARG only handles 64-bit va_arg!");
14958 assert((Subtarget->isTargetLinux() ||
14959 Subtarget->isTargetDarwin()) &&
14960 "Unhandled target in LowerVAARG");
14961 assert(Op.getNode()->getNumOperands() == 4);
14962 SDValue Chain = Op.getOperand(0);
14963 SDValue SrcPtr = Op.getOperand(1);
14964 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
14965 unsigned Align = Op.getConstantOperandVal(3);
14968 EVT ArgVT = Op.getNode()->getValueType(0);
14969 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
14970 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
14973 // Decide which area this value should be read from.
14974 // TODO: Implement the AMD64 ABI in its entirety. This simple
14975 // selection mechanism works only for the basic types.
14976 if (ArgVT == MVT::f80) {
14977 llvm_unreachable("va_arg for f80 not yet implemented");
14978 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
14979 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
14980 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
14981 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
14983 llvm_unreachable("Unhandled argument type in LowerVAARG");
14986 if (ArgMode == 2) {
14987 // Sanity Check: Make sure using fp_offset makes sense.
14988 assert(!Subtarget->useSoftFloat() &&
14989 !(DAG.getMachineFunction().getFunction()->hasFnAttribute(
14990 Attribute::NoImplicitFloat)) &&
14991 Subtarget->hasSSE1());
14994 // Insert VAARG_64 node into the DAG
14995 // VAARG_64 returns two values: Variable Argument Address, Chain
14996 SDValue InstOps[] = {Chain, SrcPtr, DAG.getConstant(ArgSize, dl, MVT::i32),
14997 DAG.getConstant(ArgMode, dl, MVT::i8),
14998 DAG.getConstant(Align, dl, MVT::i32)};
14999 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
15000 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
15001 VTs, InstOps, MVT::i64,
15002 MachinePointerInfo(SV),
15004 /*Volatile=*/false,
15006 /*WriteMem=*/true);
15007 Chain = VAARG.getValue(1);
15009 // Load the next argument and return it
15010 return DAG.getLoad(ArgVT, dl,
15013 MachinePointerInfo(),
15014 false, false, false, 0);
15017 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
15018 SelectionDAG &DAG) {
15019 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
15020 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
15021 SDValue Chain = Op.getOperand(0);
15022 SDValue DstPtr = Op.getOperand(1);
15023 SDValue SrcPtr = Op.getOperand(2);
15024 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
15025 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
15028 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
15029 DAG.getIntPtrConstant(24, DL), 8, /*isVolatile*/false,
15031 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
15034 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
15035 // amount is a constant. Takes immediate version of shift as input.
15036 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
15037 SDValue SrcOp, uint64_t ShiftAmt,
15038 SelectionDAG &DAG) {
15039 MVT ElementType = VT.getVectorElementType();
15041 // Fold this packed shift into its first operand if ShiftAmt is 0.
15045 // Check for ShiftAmt >= element width
15046 if (ShiftAmt >= ElementType.getSizeInBits()) {
15047 if (Opc == X86ISD::VSRAI)
15048 ShiftAmt = ElementType.getSizeInBits() - 1;
15050 return DAG.getConstant(0, dl, VT);
15053 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
15054 && "Unknown target vector shift-by-constant node");
15056 // Fold this packed vector shift into a build vector if SrcOp is a
15057 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
15058 if (VT == SrcOp.getSimpleValueType() &&
15059 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
15060 SmallVector<SDValue, 8> Elts;
15061 unsigned NumElts = SrcOp->getNumOperands();
15062 ConstantSDNode *ND;
15065 default: llvm_unreachable(nullptr);
15066 case X86ISD::VSHLI:
15067 for (unsigned i=0; i!=NumElts; ++i) {
15068 SDValue CurrentOp = SrcOp->getOperand(i);
15069 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15070 Elts.push_back(CurrentOp);
15073 ND = cast<ConstantSDNode>(CurrentOp);
15074 const APInt &C = ND->getAPIntValue();
15075 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), dl, ElementType));
15078 case X86ISD::VSRLI:
15079 for (unsigned i=0; i!=NumElts; ++i) {
15080 SDValue CurrentOp = SrcOp->getOperand(i);
15081 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15082 Elts.push_back(CurrentOp);
15085 ND = cast<ConstantSDNode>(CurrentOp);
15086 const APInt &C = ND->getAPIntValue();
15087 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), dl, ElementType));
15090 case X86ISD::VSRAI:
15091 for (unsigned i=0; i!=NumElts; ++i) {
15092 SDValue CurrentOp = SrcOp->getOperand(i);
15093 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15094 Elts.push_back(CurrentOp);
15097 ND = cast<ConstantSDNode>(CurrentOp);
15098 const APInt &C = ND->getAPIntValue();
15099 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), dl, ElementType));
15104 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
15107 return DAG.getNode(Opc, dl, VT, SrcOp,
15108 DAG.getConstant(ShiftAmt, dl, MVT::i8));
15111 // getTargetVShiftNode - Handle vector element shifts where the shift amount
15112 // may or may not be a constant. Takes immediate version of shift as input.
15113 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
15114 SDValue SrcOp, SDValue ShAmt,
15115 SelectionDAG &DAG) {
15116 MVT SVT = ShAmt.getSimpleValueType();
15117 assert((SVT == MVT::i32 || SVT == MVT::i64) && "Unexpected value type!");
15119 // Catch shift-by-constant.
15120 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
15121 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
15122 CShAmt->getZExtValue(), DAG);
15124 // Change opcode to non-immediate version
15126 default: llvm_unreachable("Unknown target vector shift node");
15127 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
15128 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
15129 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
15132 const X86Subtarget &Subtarget =
15133 static_cast<const X86Subtarget &>(DAG.getSubtarget());
15134 if (Subtarget.hasSSE41() && ShAmt.getOpcode() == ISD::ZERO_EXTEND &&
15135 ShAmt.getOperand(0).getSimpleValueType() == MVT::i16) {
15136 // Let the shuffle legalizer expand this shift amount node.
15137 SDValue Op0 = ShAmt.getOperand(0);
15138 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(Op0), MVT::v8i16, Op0);
15139 ShAmt = getShuffleVectorZeroOrUndef(Op0, 0, true, &Subtarget, DAG);
15141 // Need to build a vector containing shift amount.
15142 // SSE/AVX packed shifts only use the lower 64-bit of the shift count.
15143 SmallVector<SDValue, 4> ShOps;
15144 ShOps.push_back(ShAmt);
15145 if (SVT == MVT::i32) {
15146 ShOps.push_back(DAG.getConstant(0, dl, SVT));
15147 ShOps.push_back(DAG.getUNDEF(SVT));
15149 ShOps.push_back(DAG.getUNDEF(SVT));
15151 MVT BVT = SVT == MVT::i32 ? MVT::v4i32 : MVT::v2i64;
15152 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, BVT, ShOps);
15155 // The return type has to be a 128-bit type with the same element
15156 // type as the input type.
15157 MVT EltVT = VT.getVectorElementType();
15158 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
15160 ShAmt = DAG.getBitcast(ShVT, ShAmt);
15161 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
15164 /// \brief Return (and \p Op, \p Mask) for compare instructions or
15165 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
15166 /// necessary casting for \p Mask when lowering masking intrinsics.
15167 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
15168 SDValue PreservedSrc,
15169 const X86Subtarget *Subtarget,
15170 SelectionDAG &DAG) {
15171 EVT VT = Op.getValueType();
15172 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
15173 MVT::i1, VT.getVectorNumElements());
15174 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15175 Mask.getValueType().getSizeInBits());
15178 assert(MaskVT.isSimple() && "invalid mask type");
15180 if (isAllOnes(Mask))
15183 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
15184 // are extracted by EXTRACT_SUBVECTOR.
15185 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15186 DAG.getBitcast(BitcastVT, Mask),
15187 DAG.getIntPtrConstant(0, dl));
15189 switch (Op.getOpcode()) {
15191 case X86ISD::PCMPEQM:
15192 case X86ISD::PCMPGTM:
15194 case X86ISD::CMPMU:
15195 return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
15197 if (PreservedSrc.getOpcode() == ISD::UNDEF)
15198 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
15199 return DAG.getNode(ISD::VSELECT, dl, VT, VMask, Op, PreservedSrc);
15202 /// \brief Creates an SDNode for a predicated scalar operation.
15203 /// \returns (X86vselect \p Mask, \p Op, \p PreservedSrc).
15204 /// The mask is comming as MVT::i8 and it should be truncated
15205 /// to MVT::i1 while lowering masking intrinsics.
15206 /// The main difference between ScalarMaskingNode and VectorMaskingNode is using
15207 /// "X86select" instead of "vselect". We just can't create the "vselect" node for
15208 /// a scalar instruction.
15209 static SDValue getScalarMaskingNode(SDValue Op, SDValue Mask,
15210 SDValue PreservedSrc,
15211 const X86Subtarget *Subtarget,
15212 SelectionDAG &DAG) {
15213 if (isAllOnes(Mask))
15216 EVT VT = Op.getValueType();
15218 // The mask should be of type MVT::i1
15219 SDValue IMask = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Mask);
15221 if (PreservedSrc.getOpcode() == ISD::UNDEF)
15222 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
15223 return DAG.getNode(X86ISD::SELECT, dl, VT, IMask, Op, PreservedSrc);
15226 /// When the 32-bit MSVC runtime transfers control to us, either to an outlined
15227 /// function or when returning to a parent frame after catching an exception, we
15228 /// recover the parent frame pointer by doing arithmetic on the incoming EBP.
15229 /// Here's the math:
15230 /// RegNodeBase = EntryEBP - RegNodeSize
15231 /// ParentFP = RegNodeBase - RegNodeFrameOffset
15232 /// Subtracting RegNodeSize takes us to the offset of the registration node, and
15233 /// subtracting the offset (negative on x86) takes us back to the parent FP.
15234 static SDValue recoverFramePointer(SelectionDAG &DAG, const Function *Fn,
15235 SDValue EntryEBP) {
15236 MachineFunction &MF = DAG.getMachineFunction();
15239 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15240 MVT PtrVT = TLI.getPointerTy();
15242 // It's possible that the parent function no longer has a personality function
15243 // if the exceptional code was optimized away, in which case we just return
15244 // the incoming EBP.
15245 if (!Fn->hasPersonalityFn())
15248 // The RegNodeSize is 6 32-bit words for SEH and 4 for C++ EH. See
15249 // WinEHStatePass for the full struct definition.
15251 switch (classifyEHPersonality(Fn->getPersonalityFn())) {
15253 report_fatal_error("can only recover FP for MSVC EH personality functions");
15254 case EHPersonality::MSVC_X86SEH: RegNodeSize = 24; break;
15255 case EHPersonality::MSVC_CXX: RegNodeSize = 16; break;
15258 // Get an MCSymbol that will ultimately resolve to the frame offset of the EH
15260 MCSymbol *OffsetSym =
15261 MF.getMMI().getContext().getOrCreateParentFrameOffsetSymbol(
15262 GlobalValue::getRealLinkageName(Fn->getName()));
15263 SDValue OffsetSymVal = DAG.getMCSymbol(OffsetSym, PtrVT);
15264 SDValue RegNodeFrameOffset =
15265 DAG.getNode(ISD::FRAME_ALLOC_RECOVER, dl, PtrVT, OffsetSymVal);
15267 // RegNodeBase = EntryEBP - RegNodeSize
15268 // ParentFP = RegNodeBase - RegNodeFrameOffset
15269 SDValue RegNodeBase = DAG.getNode(ISD::SUB, dl, PtrVT, EntryEBP,
15270 DAG.getConstant(RegNodeSize, dl, PtrVT));
15271 return DAG.getNode(ISD::SUB, dl, PtrVT, RegNodeBase, RegNodeFrameOffset);
15274 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
15275 SelectionDAG &DAG) {
15277 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15278 EVT VT = Op.getValueType();
15279 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
15281 switch(IntrData->Type) {
15282 case INTR_TYPE_1OP:
15283 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
15284 case INTR_TYPE_2OP:
15285 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15287 case INTR_TYPE_3OP:
15288 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15289 Op.getOperand(2), Op.getOperand(3));
15290 case INTR_TYPE_4OP:
15291 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15292 Op.getOperand(2), Op.getOperand(3), Op.getOperand(4));
15293 case INTR_TYPE_1OP_MASK_RM: {
15294 SDValue Src = Op.getOperand(1);
15295 SDValue PassThru = Op.getOperand(2);
15296 SDValue Mask = Op.getOperand(3);
15297 SDValue RoundingMode;
15298 if (Op.getNumOperands() == 4)
15299 RoundingMode = DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
15301 RoundingMode = Op.getOperand(4);
15302 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
15303 if (IntrWithRoundingModeOpcode != 0) {
15304 unsigned Round = cast<ConstantSDNode>(RoundingMode)->getZExtValue();
15305 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION)
15306 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
15307 dl, Op.getValueType(), Src, RoundingMode),
15308 Mask, PassThru, Subtarget, DAG);
15310 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src,
15312 Mask, PassThru, Subtarget, DAG);
15314 case INTR_TYPE_1OP_MASK: {
15315 SDValue Src = Op.getOperand(1);
15316 SDValue Passthru = Op.getOperand(2);
15317 SDValue Mask = Op.getOperand(3);
15318 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src),
15319 Mask, Passthru, Subtarget, DAG);
15321 case INTR_TYPE_SCALAR_MASK_RM: {
15322 SDValue Src1 = Op.getOperand(1);
15323 SDValue Src2 = Op.getOperand(2);
15324 SDValue Src0 = Op.getOperand(3);
15325 SDValue Mask = Op.getOperand(4);
15326 // There are 2 kinds of intrinsics in this group:
15327 // (1) With supress-all-exceptions (sae) or rounding mode- 6 operands
15328 // (2) With rounding mode and sae - 7 operands.
15329 if (Op.getNumOperands() == 6) {
15330 SDValue Sae = Op.getOperand(5);
15331 unsigned Opc = IntrData->Opc1 ? IntrData->Opc1 : IntrData->Opc0;
15332 return getScalarMaskingNode(DAG.getNode(Opc, dl, VT, Src1, Src2,
15334 Mask, Src0, Subtarget, DAG);
15336 assert(Op.getNumOperands() == 7 && "Unexpected intrinsic form");
15337 SDValue RoundingMode = Op.getOperand(5);
15338 SDValue Sae = Op.getOperand(6);
15339 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2,
15340 RoundingMode, Sae),
15341 Mask, Src0, Subtarget, DAG);
15343 case INTR_TYPE_2OP_MASK: {
15344 SDValue Src1 = Op.getOperand(1);
15345 SDValue Src2 = Op.getOperand(2);
15346 SDValue PassThru = Op.getOperand(3);
15347 SDValue Mask = Op.getOperand(4);
15348 // We specify 2 possible opcodes for intrinsics with rounding modes.
15349 // First, we check if the intrinsic may have non-default rounding mode,
15350 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
15351 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
15352 if (IntrWithRoundingModeOpcode != 0) {
15353 SDValue Rnd = Op.getOperand(5);
15354 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
15355 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
15356 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
15357 dl, Op.getValueType(),
15359 Mask, PassThru, Subtarget, DAG);
15362 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
15364 Mask, PassThru, Subtarget, DAG);
15366 case INTR_TYPE_2OP_MASK_RM: {
15367 SDValue Src1 = Op.getOperand(1);
15368 SDValue Src2 = Op.getOperand(2);
15369 SDValue PassThru = Op.getOperand(3);
15370 SDValue Mask = Op.getOperand(4);
15371 // We specify 2 possible modes for intrinsics, with/without rounding modes.
15372 // First, we check if the intrinsic have rounding mode (6 operands),
15373 // if not, we set rounding mode to "current".
15375 if (Op.getNumOperands() == 6)
15376 Rnd = Op.getOperand(5);
15378 Rnd = DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
15379 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
15381 Mask, PassThru, Subtarget, DAG);
15383 case INTR_TYPE_3OP_MASK: {
15384 SDValue Src1 = Op.getOperand(1);
15385 SDValue Src2 = Op.getOperand(2);
15386 SDValue Src3 = Op.getOperand(3);
15387 SDValue PassThru = Op.getOperand(4);
15388 SDValue Mask = Op.getOperand(5);
15389 // We specify 2 possible opcodes for intrinsics with rounding modes.
15390 // First, we check if the intrinsic may have non-default rounding mode,
15391 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
15392 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
15393 if (IntrWithRoundingModeOpcode != 0) {
15394 SDValue Rnd = Op.getOperand(6);
15395 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
15396 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
15397 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
15398 dl, Op.getValueType(),
15399 Src1, Src2, Src3, Rnd),
15400 Mask, PassThru, Subtarget, DAG);
15403 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
15405 Mask, PassThru, Subtarget, DAG);
15407 case VPERM_3OP_MASKZ:
15408 case VPERM_3OP_MASK:
15411 case FMA_OP_MASK: {
15412 SDValue Src1 = Op.getOperand(1);
15413 SDValue Src2 = Op.getOperand(2);
15414 SDValue Src3 = Op.getOperand(3);
15415 SDValue Mask = Op.getOperand(4);
15416 EVT VT = Op.getValueType();
15417 SDValue PassThru = SDValue();
15419 // set PassThru element
15420 if (IntrData->Type == VPERM_3OP_MASKZ || IntrData->Type == FMA_OP_MASKZ)
15421 PassThru = getZeroVector(VT, Subtarget, DAG, dl);
15422 else if (IntrData->Type == FMA_OP_MASK3)
15427 // We specify 2 possible opcodes for intrinsics with rounding modes.
15428 // First, we check if the intrinsic may have non-default rounding mode,
15429 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
15430 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
15431 if (IntrWithRoundingModeOpcode != 0) {
15432 SDValue Rnd = Op.getOperand(5);
15433 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
15434 X86::STATIC_ROUNDING::CUR_DIRECTION)
15435 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
15436 dl, Op.getValueType(),
15437 Src1, Src2, Src3, Rnd),
15438 Mask, PassThru, Subtarget, DAG);
15440 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0,
15441 dl, Op.getValueType(),
15443 Mask, PassThru, Subtarget, DAG);
15446 case CMP_MASK_CC: {
15447 // Comparison intrinsics with masks.
15448 // Example of transformation:
15449 // (i8 (int_x86_avx512_mask_pcmpeq_q_128
15450 // (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
15452 // (v8i1 (insert_subvector undef,
15453 // (v2i1 (and (PCMPEQM %a, %b),
15454 // (extract_subvector
15455 // (v8i1 (bitcast %mask)), 0))), 0))))
15456 EVT VT = Op.getOperand(1).getValueType();
15457 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15458 VT.getVectorNumElements());
15459 SDValue Mask = Op.getOperand((IntrData->Type == CMP_MASK_CC) ? 4 : 3);
15460 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15461 Mask.getValueType().getSizeInBits());
15463 if (IntrData->Type == CMP_MASK_CC) {
15464 SDValue CC = Op.getOperand(3);
15465 CC = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, CC);
15466 // We specify 2 possible opcodes for intrinsics with rounding modes.
15467 // First, we check if the intrinsic may have non-default rounding mode,
15468 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
15469 if (IntrData->Opc1 != 0) {
15470 SDValue Rnd = Op.getOperand(5);
15471 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
15472 X86::STATIC_ROUNDING::CUR_DIRECTION)
15473 Cmp = DAG.getNode(IntrData->Opc1, dl, MaskVT, Op.getOperand(1),
15474 Op.getOperand(2), CC, Rnd);
15476 //default rounding mode
15478 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
15479 Op.getOperand(2), CC);
15482 assert(IntrData->Type == CMP_MASK && "Unexpected intrinsic type!");
15483 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
15486 SDValue CmpMask = getVectorMaskingNode(Cmp, Mask,
15487 DAG.getTargetConstant(0, dl,
15490 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
15491 DAG.getUNDEF(BitcastVT), CmpMask,
15492 DAG.getIntPtrConstant(0, dl));
15493 return DAG.getBitcast(Op.getValueType(), Res);
15495 case COMI: { // Comparison intrinsics
15496 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
15497 SDValue LHS = Op.getOperand(1);
15498 SDValue RHS = Op.getOperand(2);
15499 unsigned X86CC = TranslateX86CC(CC, dl, true, LHS, RHS, DAG);
15500 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
15501 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
15502 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15503 DAG.getConstant(X86CC, dl, MVT::i8), Cond);
15504 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15507 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
15508 Op.getOperand(1), Op.getOperand(2), DAG);
15510 return getVectorMaskingNode(getTargetVShiftNode(IntrData->Opc0, dl,
15511 Op.getSimpleValueType(),
15513 Op.getOperand(2), DAG),
15514 Op.getOperand(4), Op.getOperand(3), Subtarget,
15516 case COMPRESS_EXPAND_IN_REG: {
15517 SDValue Mask = Op.getOperand(3);
15518 SDValue DataToCompress = Op.getOperand(1);
15519 SDValue PassThru = Op.getOperand(2);
15520 if (isAllOnes(Mask)) // return data as is
15521 return Op.getOperand(1);
15523 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
15525 Mask, PassThru, Subtarget, DAG);
15528 SDValue Mask = Op.getOperand(3);
15529 EVT VT = Op.getValueType();
15530 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15531 VT.getVectorNumElements());
15532 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15533 Mask.getValueType().getSizeInBits());
15535 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15536 DAG.getBitcast(BitcastVT, Mask),
15537 DAG.getIntPtrConstant(0, dl));
15538 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, Op.getOperand(1),
15547 default: return SDValue(); // Don't custom lower most intrinsics.
15549 case Intrinsic::x86_avx2_permd:
15550 case Intrinsic::x86_avx2_permps:
15551 // Operands intentionally swapped. Mask is last operand to intrinsic,
15552 // but second operand for node/instruction.
15553 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
15554 Op.getOperand(2), Op.getOperand(1));
15556 // ptest and testp intrinsics. The intrinsic these come from are designed to
15557 // return an integer value, not just an instruction so lower it to the ptest
15558 // or testp pattern and a setcc for the result.
15559 case Intrinsic::x86_sse41_ptestz:
15560 case Intrinsic::x86_sse41_ptestc:
15561 case Intrinsic::x86_sse41_ptestnzc:
15562 case Intrinsic::x86_avx_ptestz_256:
15563 case Intrinsic::x86_avx_ptestc_256:
15564 case Intrinsic::x86_avx_ptestnzc_256:
15565 case Intrinsic::x86_avx_vtestz_ps:
15566 case Intrinsic::x86_avx_vtestc_ps:
15567 case Intrinsic::x86_avx_vtestnzc_ps:
15568 case Intrinsic::x86_avx_vtestz_pd:
15569 case Intrinsic::x86_avx_vtestc_pd:
15570 case Intrinsic::x86_avx_vtestnzc_pd:
15571 case Intrinsic::x86_avx_vtestz_ps_256:
15572 case Intrinsic::x86_avx_vtestc_ps_256:
15573 case Intrinsic::x86_avx_vtestnzc_ps_256:
15574 case Intrinsic::x86_avx_vtestz_pd_256:
15575 case Intrinsic::x86_avx_vtestc_pd_256:
15576 case Intrinsic::x86_avx_vtestnzc_pd_256: {
15577 bool IsTestPacked = false;
15580 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
15581 case Intrinsic::x86_avx_vtestz_ps:
15582 case Intrinsic::x86_avx_vtestz_pd:
15583 case Intrinsic::x86_avx_vtestz_ps_256:
15584 case Intrinsic::x86_avx_vtestz_pd_256:
15585 IsTestPacked = true; // Fallthrough
15586 case Intrinsic::x86_sse41_ptestz:
15587 case Intrinsic::x86_avx_ptestz_256:
15589 X86CC = X86::COND_E;
15591 case Intrinsic::x86_avx_vtestc_ps:
15592 case Intrinsic::x86_avx_vtestc_pd:
15593 case Intrinsic::x86_avx_vtestc_ps_256:
15594 case Intrinsic::x86_avx_vtestc_pd_256:
15595 IsTestPacked = true; // Fallthrough
15596 case Intrinsic::x86_sse41_ptestc:
15597 case Intrinsic::x86_avx_ptestc_256:
15599 X86CC = X86::COND_B;
15601 case Intrinsic::x86_avx_vtestnzc_ps:
15602 case Intrinsic::x86_avx_vtestnzc_pd:
15603 case Intrinsic::x86_avx_vtestnzc_ps_256:
15604 case Intrinsic::x86_avx_vtestnzc_pd_256:
15605 IsTestPacked = true; // Fallthrough
15606 case Intrinsic::x86_sse41_ptestnzc:
15607 case Intrinsic::x86_avx_ptestnzc_256:
15609 X86CC = X86::COND_A;
15613 SDValue LHS = Op.getOperand(1);
15614 SDValue RHS = Op.getOperand(2);
15615 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
15616 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
15617 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
15618 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
15619 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15621 case Intrinsic::x86_avx512_kortestz_w:
15622 case Intrinsic::x86_avx512_kortestc_w: {
15623 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
15624 SDValue LHS = DAG.getBitcast(MVT::v16i1, Op.getOperand(1));
15625 SDValue RHS = DAG.getBitcast(MVT::v16i1, Op.getOperand(2));
15626 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
15627 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
15628 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
15629 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15632 case Intrinsic::x86_sse42_pcmpistria128:
15633 case Intrinsic::x86_sse42_pcmpestria128:
15634 case Intrinsic::x86_sse42_pcmpistric128:
15635 case Intrinsic::x86_sse42_pcmpestric128:
15636 case Intrinsic::x86_sse42_pcmpistrio128:
15637 case Intrinsic::x86_sse42_pcmpestrio128:
15638 case Intrinsic::x86_sse42_pcmpistris128:
15639 case Intrinsic::x86_sse42_pcmpestris128:
15640 case Intrinsic::x86_sse42_pcmpistriz128:
15641 case Intrinsic::x86_sse42_pcmpestriz128: {
15645 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
15646 case Intrinsic::x86_sse42_pcmpistria128:
15647 Opcode = X86ISD::PCMPISTRI;
15648 X86CC = X86::COND_A;
15650 case Intrinsic::x86_sse42_pcmpestria128:
15651 Opcode = X86ISD::PCMPESTRI;
15652 X86CC = X86::COND_A;
15654 case Intrinsic::x86_sse42_pcmpistric128:
15655 Opcode = X86ISD::PCMPISTRI;
15656 X86CC = X86::COND_B;
15658 case Intrinsic::x86_sse42_pcmpestric128:
15659 Opcode = X86ISD::PCMPESTRI;
15660 X86CC = X86::COND_B;
15662 case Intrinsic::x86_sse42_pcmpistrio128:
15663 Opcode = X86ISD::PCMPISTRI;
15664 X86CC = X86::COND_O;
15666 case Intrinsic::x86_sse42_pcmpestrio128:
15667 Opcode = X86ISD::PCMPESTRI;
15668 X86CC = X86::COND_O;
15670 case Intrinsic::x86_sse42_pcmpistris128:
15671 Opcode = X86ISD::PCMPISTRI;
15672 X86CC = X86::COND_S;
15674 case Intrinsic::x86_sse42_pcmpestris128:
15675 Opcode = X86ISD::PCMPESTRI;
15676 X86CC = X86::COND_S;
15678 case Intrinsic::x86_sse42_pcmpistriz128:
15679 Opcode = X86ISD::PCMPISTRI;
15680 X86CC = X86::COND_E;
15682 case Intrinsic::x86_sse42_pcmpestriz128:
15683 Opcode = X86ISD::PCMPESTRI;
15684 X86CC = X86::COND_E;
15687 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
15688 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
15689 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
15690 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15691 DAG.getConstant(X86CC, dl, MVT::i8),
15692 SDValue(PCMP.getNode(), 1));
15693 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15696 case Intrinsic::x86_sse42_pcmpistri128:
15697 case Intrinsic::x86_sse42_pcmpestri128: {
15699 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
15700 Opcode = X86ISD::PCMPISTRI;
15702 Opcode = X86ISD::PCMPESTRI;
15704 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
15705 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
15706 return DAG.getNode(Opcode, dl, VTs, NewOps);
15709 case Intrinsic::x86_seh_lsda: {
15710 // Compute the symbol for the LSDA. We know it'll get emitted later.
15711 MachineFunction &MF = DAG.getMachineFunction();
15712 SDValue Op1 = Op.getOperand(1);
15713 auto *Fn = cast<Function>(cast<GlobalAddressSDNode>(Op1)->getGlobal());
15714 MCSymbol *LSDASym = MF.getMMI().getContext().getOrCreateLSDASymbol(
15715 GlobalValue::getRealLinkageName(Fn->getName()));
15717 // Generate a simple absolute symbol reference. This intrinsic is only
15718 // supported on 32-bit Windows, which isn't PIC.
15719 SDValue Result = DAG.getMCSymbol(LSDASym, VT);
15720 return DAG.getNode(X86ISD::Wrapper, dl, VT, Result);
15723 case Intrinsic::x86_seh_recoverfp: {
15724 SDValue FnOp = Op.getOperand(1);
15725 SDValue IncomingFPOp = Op.getOperand(2);
15726 GlobalAddressSDNode *GSD = dyn_cast<GlobalAddressSDNode>(FnOp);
15727 auto *Fn = dyn_cast_or_null<Function>(GSD ? GSD->getGlobal() : nullptr);
15729 report_fatal_error(
15730 "llvm.x86.seh.recoverfp must take a function as the first argument");
15731 return recoverFramePointer(DAG, Fn, IncomingFPOp);
15736 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15737 SDValue Src, SDValue Mask, SDValue Base,
15738 SDValue Index, SDValue ScaleOp, SDValue Chain,
15739 const X86Subtarget * Subtarget) {
15741 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15743 llvm_unreachable("Invalid scale type");
15744 unsigned ScaleVal = C->getZExtValue();
15745 if (ScaleVal > 2 && ScaleVal != 4 && ScaleVal != 8)
15746 llvm_unreachable("Valid scale values are 1, 2, 4, 8");
15748 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
15749 EVT MaskVT = MVT::getVectorVT(MVT::i1,
15750 Index.getSimpleValueType().getVectorNumElements());
15752 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15754 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
15756 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15757 Mask.getValueType().getSizeInBits());
15759 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
15760 // are extracted by EXTRACT_SUBVECTOR.
15761 MaskInReg = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15762 DAG.getBitcast(BitcastVT, Mask),
15763 DAG.getIntPtrConstant(0, dl));
15765 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
15766 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
15767 SDValue Segment = DAG.getRegister(0, MVT::i32);
15768 if (Src.getOpcode() == ISD::UNDEF)
15769 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
15770 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
15771 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
15772 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
15773 return DAG.getMergeValues(RetOps, dl);
15776 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15777 SDValue Src, SDValue Mask, SDValue Base,
15778 SDValue Index, SDValue ScaleOp, SDValue Chain) {
15780 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15782 llvm_unreachable("Invalid scale type");
15783 unsigned ScaleVal = C->getZExtValue();
15784 if (ScaleVal > 2 && ScaleVal != 4 && ScaleVal != 8)
15785 llvm_unreachable("Valid scale values are 1, 2, 4, 8");
15787 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
15788 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
15789 SDValue Segment = DAG.getRegister(0, MVT::i32);
15790 EVT MaskVT = MVT::getVectorVT(MVT::i1,
15791 Index.getSimpleValueType().getVectorNumElements());
15793 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15795 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
15797 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15798 Mask.getValueType().getSizeInBits());
15800 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
15801 // are extracted by EXTRACT_SUBVECTOR.
15802 MaskInReg = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15803 DAG.getBitcast(BitcastVT, Mask),
15804 DAG.getIntPtrConstant(0, dl));
15806 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
15807 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
15808 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
15809 return SDValue(Res, 1);
15812 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15813 SDValue Mask, SDValue Base, SDValue Index,
15814 SDValue ScaleOp, SDValue Chain) {
15816 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15817 assert(C && "Invalid scale type");
15818 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
15819 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
15820 SDValue Segment = DAG.getRegister(0, MVT::i32);
15822 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
15824 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15826 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
15828 MaskInReg = DAG.getBitcast(MaskVT, Mask);
15829 //SDVTList VTs = DAG.getVTList(MVT::Other);
15830 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
15831 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
15832 return SDValue(Res, 0);
15835 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
15836 // read performance monitor counters (x86_rdpmc).
15837 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
15838 SelectionDAG &DAG, const X86Subtarget *Subtarget,
15839 SmallVectorImpl<SDValue> &Results) {
15840 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
15841 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
15844 // The ECX register is used to select the index of the performance counter
15846 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
15848 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
15850 // Reads the content of a 64-bit performance counter and returns it in the
15851 // registers EDX:EAX.
15852 if (Subtarget->is64Bit()) {
15853 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
15854 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
15857 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
15858 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
15861 Chain = HI.getValue(1);
15863 if (Subtarget->is64Bit()) {
15864 // The EAX register is loaded with the low-order 32 bits. The EDX register
15865 // is loaded with the supported high-order bits of the counter.
15866 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
15867 DAG.getConstant(32, DL, MVT::i8));
15868 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
15869 Results.push_back(Chain);
15873 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
15874 SDValue Ops[] = { LO, HI };
15875 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
15876 Results.push_back(Pair);
15877 Results.push_back(Chain);
15880 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
15881 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
15882 // also used to custom lower READCYCLECOUNTER nodes.
15883 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
15884 SelectionDAG &DAG, const X86Subtarget *Subtarget,
15885 SmallVectorImpl<SDValue> &Results) {
15886 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
15887 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
15890 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
15891 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
15892 // and the EAX register is loaded with the low-order 32 bits.
15893 if (Subtarget->is64Bit()) {
15894 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
15895 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
15898 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
15899 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
15902 SDValue Chain = HI.getValue(1);
15904 if (Opcode == X86ISD::RDTSCP_DAG) {
15905 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
15907 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
15908 // the ECX register. Add 'ecx' explicitly to the chain.
15909 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
15911 // Explicitly store the content of ECX at the location passed in input
15912 // to the 'rdtscp' intrinsic.
15913 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
15914 MachinePointerInfo(), false, false, 0);
15917 if (Subtarget->is64Bit()) {
15918 // The EDX register is loaded with the high-order 32 bits of the MSR, and
15919 // the EAX register is loaded with the low-order 32 bits.
15920 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
15921 DAG.getConstant(32, DL, MVT::i8));
15922 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
15923 Results.push_back(Chain);
15927 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
15928 SDValue Ops[] = { LO, HI };
15929 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
15930 Results.push_back(Pair);
15931 Results.push_back(Chain);
15934 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
15935 SelectionDAG &DAG) {
15936 SmallVector<SDValue, 2> Results;
15938 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
15940 return DAG.getMergeValues(Results, DL);
15943 static SDValue LowerSEHRESTOREFRAME(SDValue Op, const X86Subtarget *Subtarget,
15944 SelectionDAG &DAG) {
15945 MachineFunction &MF = DAG.getMachineFunction();
15947 SDValue Chain = Op.getOperand(0);
15949 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15950 MVT VT = TLI.getPointerTy();
15952 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15953 unsigned FrameReg =
15954 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
15955 unsigned SPReg = RegInfo->getStackRegister();
15957 // Get incoming EBP.
15958 SDValue IncomingEBP =
15959 DAG.getCopyFromReg(Chain, dl, FrameReg, VT);
15961 // Load [EBP-24] into SP.
15963 DAG.getNode(ISD::ADD, dl, VT, IncomingEBP, DAG.getConstant(-24, dl, VT));
15965 DAG.getLoad(VT, dl, Chain, SPAddr, MachinePointerInfo(), false, false,
15966 false, VT.getScalarSizeInBits() / 8);
15967 Chain = DAG.getCopyToReg(Chain, dl, SPReg, NewSP);
15969 // FIXME: Restore the base pointer in case of stack realignment!
15971 // Adjust EBP to point back to the original frame position.
15972 SDValue NewFP = recoverFramePointer(DAG, MF.getFunction(), IncomingEBP);
15973 Chain = DAG.getCopyToReg(Chain, dl, FrameReg, NewFP);
15977 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
15978 SelectionDAG &DAG) {
15979 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
15981 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
15983 if (IntNo == llvm::Intrinsic::x86_seh_restoreframe)
15984 return LowerSEHRESTOREFRAME(Op, Subtarget, DAG);
15989 switch(IntrData->Type) {
15991 llvm_unreachable("Unknown Intrinsic Type");
15995 // Emit the node with the right value type.
15996 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
15997 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
15999 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
16000 // Otherwise return the value from Rand, which is always 0, casted to i32.
16001 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
16002 DAG.getConstant(1, dl, Op->getValueType(1)),
16003 DAG.getConstant(X86::COND_B, dl, MVT::i32),
16004 SDValue(Result.getNode(), 1) };
16005 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
16006 DAG.getVTList(Op->getValueType(1), MVT::Glue),
16009 // Return { result, isValid, chain }.
16010 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
16011 SDValue(Result.getNode(), 2));
16014 //gather(v1, mask, index, base, scale);
16015 SDValue Chain = Op.getOperand(0);
16016 SDValue Src = Op.getOperand(2);
16017 SDValue Base = Op.getOperand(3);
16018 SDValue Index = Op.getOperand(4);
16019 SDValue Mask = Op.getOperand(5);
16020 SDValue Scale = Op.getOperand(6);
16021 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale,
16025 //scatter(base, mask, index, v1, scale);
16026 SDValue Chain = Op.getOperand(0);
16027 SDValue Base = Op.getOperand(2);
16028 SDValue Mask = Op.getOperand(3);
16029 SDValue Index = Op.getOperand(4);
16030 SDValue Src = Op.getOperand(5);
16031 SDValue Scale = Op.getOperand(6);
16032 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index,
16036 SDValue Hint = Op.getOperand(6);
16037 unsigned HintVal = cast<ConstantSDNode>(Hint)->getZExtValue();
16038 assert(HintVal < 2 && "Wrong prefetch hint in intrinsic: should be 0 or 1");
16039 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
16040 SDValue Chain = Op.getOperand(0);
16041 SDValue Mask = Op.getOperand(2);
16042 SDValue Index = Op.getOperand(3);
16043 SDValue Base = Op.getOperand(4);
16044 SDValue Scale = Op.getOperand(5);
16045 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
16047 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
16049 SmallVector<SDValue, 2> Results;
16050 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget,
16052 return DAG.getMergeValues(Results, dl);
16054 // Read Performance Monitoring Counters.
16056 SmallVector<SDValue, 2> Results;
16057 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
16058 return DAG.getMergeValues(Results, dl);
16060 // XTEST intrinsics.
16062 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
16063 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
16064 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16065 DAG.getConstant(X86::COND_NE, dl, MVT::i8),
16067 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
16068 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
16069 Ret, SDValue(InTrans.getNode(), 1));
16073 SmallVector<SDValue, 2> Results;
16074 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
16075 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
16076 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
16077 DAG.getConstant(-1, dl, MVT::i8));
16078 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
16079 Op.getOperand(4), GenCF.getValue(1));
16080 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
16081 Op.getOperand(5), MachinePointerInfo(),
16083 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16084 DAG.getConstant(X86::COND_B, dl, MVT::i8),
16086 Results.push_back(SetCC);
16087 Results.push_back(Store);
16088 return DAG.getMergeValues(Results, dl);
16090 case COMPRESS_TO_MEM: {
16092 SDValue Mask = Op.getOperand(4);
16093 SDValue DataToCompress = Op.getOperand(3);
16094 SDValue Addr = Op.getOperand(2);
16095 SDValue Chain = Op.getOperand(0);
16097 EVT VT = DataToCompress.getValueType();
16098 if (isAllOnes(Mask)) // return just a store
16099 return DAG.getStore(Chain, dl, DataToCompress, Addr,
16100 MachinePointerInfo(), false, false,
16101 VT.getScalarSizeInBits()/8);
16103 SDValue Compressed =
16104 getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, DataToCompress),
16105 Mask, DAG.getUNDEF(VT), Subtarget, DAG);
16106 return DAG.getStore(Chain, dl, Compressed, Addr,
16107 MachinePointerInfo(), false, false,
16108 VT.getScalarSizeInBits()/8);
16110 case EXPAND_FROM_MEM: {
16112 SDValue Mask = Op.getOperand(4);
16113 SDValue PassThru = Op.getOperand(3);
16114 SDValue Addr = Op.getOperand(2);
16115 SDValue Chain = Op.getOperand(0);
16116 EVT VT = Op.getValueType();
16118 if (isAllOnes(Mask)) // return just a load
16119 return DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(), false, false,
16120 false, VT.getScalarSizeInBits()/8);
16122 SDValue DataToExpand = DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(),
16123 false, false, false,
16124 VT.getScalarSizeInBits()/8);
16126 SDValue Results[] = {
16127 getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, DataToExpand),
16128 Mask, PassThru, Subtarget, DAG), Chain};
16129 return DAG.getMergeValues(Results, dl);
16134 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
16135 SelectionDAG &DAG) const {
16136 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
16137 MFI->setReturnAddressIsTaken(true);
16139 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
16142 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16144 EVT PtrVT = getPointerTy();
16147 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
16148 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
16149 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), dl, PtrVT);
16150 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
16151 DAG.getNode(ISD::ADD, dl, PtrVT,
16152 FrameAddr, Offset),
16153 MachinePointerInfo(), false, false, false, 0);
16156 // Just load the return address.
16157 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
16158 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
16159 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
16162 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
16163 MachineFunction &MF = DAG.getMachineFunction();
16164 MachineFrameInfo *MFI = MF.getFrameInfo();
16165 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
16166 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
16167 EVT VT = Op.getValueType();
16169 MFI->setFrameAddressIsTaken(true);
16171 if (MF.getTarget().getMCAsmInfo()->usesWindowsCFI()) {
16172 // Depth > 0 makes no sense on targets which use Windows unwind codes. It
16173 // is not possible to crawl up the stack without looking at the unwind codes
16175 int FrameAddrIndex = FuncInfo->getFAIndex();
16176 if (!FrameAddrIndex) {
16177 // Set up a frame object for the return address.
16178 unsigned SlotSize = RegInfo->getSlotSize();
16179 FrameAddrIndex = MF.getFrameInfo()->CreateFixedObject(
16180 SlotSize, /*Offset=*/0, /*IsImmutable=*/false);
16181 FuncInfo->setFAIndex(FrameAddrIndex);
16183 return DAG.getFrameIndex(FrameAddrIndex, VT);
16186 unsigned FrameReg =
16187 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
16188 SDLoc dl(Op); // FIXME probably not meaningful
16189 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16190 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
16191 (FrameReg == X86::EBP && VT == MVT::i32)) &&
16192 "Invalid Frame Register!");
16193 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
16195 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
16196 MachinePointerInfo(),
16197 false, false, false, 0);
16201 // FIXME? Maybe this could be a TableGen attribute on some registers and
16202 // this table could be generated automatically from RegInfo.
16203 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
16205 unsigned Reg = StringSwitch<unsigned>(RegName)
16206 .Case("esp", X86::ESP)
16207 .Case("rsp", X86::RSP)
16211 report_fatal_error("Invalid register name global variable");
16214 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
16215 SelectionDAG &DAG) const {
16216 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
16217 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize(), SDLoc(Op));
16220 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
16221 SDValue Chain = Op.getOperand(0);
16222 SDValue Offset = Op.getOperand(1);
16223 SDValue Handler = Op.getOperand(2);
16226 EVT PtrVT = getPointerTy();
16227 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
16228 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
16229 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
16230 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
16231 "Invalid Frame Register!");
16232 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
16233 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
16235 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
16236 DAG.getIntPtrConstant(RegInfo->getSlotSize(),
16238 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
16239 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
16241 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
16243 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
16244 DAG.getRegister(StoreAddrReg, PtrVT));
16247 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
16248 SelectionDAG &DAG) const {
16250 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
16251 DAG.getVTList(MVT::i32, MVT::Other),
16252 Op.getOperand(0), Op.getOperand(1));
16255 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
16256 SelectionDAG &DAG) const {
16258 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
16259 Op.getOperand(0), Op.getOperand(1));
16262 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
16263 return Op.getOperand(0);
16266 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
16267 SelectionDAG &DAG) const {
16268 SDValue Root = Op.getOperand(0);
16269 SDValue Trmp = Op.getOperand(1); // trampoline
16270 SDValue FPtr = Op.getOperand(2); // nested function
16271 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
16274 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
16275 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
16277 if (Subtarget->is64Bit()) {
16278 SDValue OutChains[6];
16280 // Large code-model.
16281 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
16282 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
16284 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
16285 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
16287 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
16289 // Load the pointer to the nested function into R11.
16290 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
16291 SDValue Addr = Trmp;
16292 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
16293 Addr, MachinePointerInfo(TrmpAddr),
16296 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16297 DAG.getConstant(2, dl, MVT::i64));
16298 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
16299 MachinePointerInfo(TrmpAddr, 2),
16302 // Load the 'nest' parameter value into R10.
16303 // R10 is specified in X86CallingConv.td
16304 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
16305 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16306 DAG.getConstant(10, dl, MVT::i64));
16307 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
16308 Addr, MachinePointerInfo(TrmpAddr, 10),
16311 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16312 DAG.getConstant(12, dl, MVT::i64));
16313 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
16314 MachinePointerInfo(TrmpAddr, 12),
16317 // Jump to the nested function.
16318 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
16319 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16320 DAG.getConstant(20, dl, MVT::i64));
16321 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
16322 Addr, MachinePointerInfo(TrmpAddr, 20),
16325 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
16326 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16327 DAG.getConstant(22, dl, MVT::i64));
16328 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, dl, MVT::i8),
16329 Addr, MachinePointerInfo(TrmpAddr, 22),
16332 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
16334 const Function *Func =
16335 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
16336 CallingConv::ID CC = Func->getCallingConv();
16341 llvm_unreachable("Unsupported calling convention");
16342 case CallingConv::C:
16343 case CallingConv::X86_StdCall: {
16344 // Pass 'nest' parameter in ECX.
16345 // Must be kept in sync with X86CallingConv.td
16346 NestReg = X86::ECX;
16348 // Check that ECX wasn't needed by an 'inreg' parameter.
16349 FunctionType *FTy = Func->getFunctionType();
16350 const AttributeSet &Attrs = Func->getAttributes();
16352 if (!Attrs.isEmpty() && !Func->isVarArg()) {
16353 unsigned InRegCount = 0;
16356 for (FunctionType::param_iterator I = FTy->param_begin(),
16357 E = FTy->param_end(); I != E; ++I, ++Idx)
16358 if (Attrs.hasAttribute(Idx, Attribute::InReg))
16359 // FIXME: should only count parameters that are lowered to integers.
16360 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
16362 if (InRegCount > 2) {
16363 report_fatal_error("Nest register in use - reduce number of inreg"
16369 case CallingConv::X86_FastCall:
16370 case CallingConv::X86_ThisCall:
16371 case CallingConv::Fast:
16372 // Pass 'nest' parameter in EAX.
16373 // Must be kept in sync with X86CallingConv.td
16374 NestReg = X86::EAX;
16378 SDValue OutChains[4];
16379 SDValue Addr, Disp;
16381 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16382 DAG.getConstant(10, dl, MVT::i32));
16383 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
16385 // This is storing the opcode for MOV32ri.
16386 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
16387 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
16388 OutChains[0] = DAG.getStore(Root, dl,
16389 DAG.getConstant(MOV32ri|N86Reg, dl, MVT::i8),
16390 Trmp, MachinePointerInfo(TrmpAddr),
16393 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16394 DAG.getConstant(1, dl, MVT::i32));
16395 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
16396 MachinePointerInfo(TrmpAddr, 1),
16399 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
16400 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16401 DAG.getConstant(5, dl, MVT::i32));
16402 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, dl, MVT::i8),
16403 Addr, MachinePointerInfo(TrmpAddr, 5),
16406 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16407 DAG.getConstant(6, dl, MVT::i32));
16408 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
16409 MachinePointerInfo(TrmpAddr, 6),
16412 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
16416 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
16417 SelectionDAG &DAG) const {
16419 The rounding mode is in bits 11:10 of FPSR, and has the following
16421 00 Round to nearest
16426 FLT_ROUNDS, on the other hand, expects the following:
16433 To perform the conversion, we do:
16434 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
16437 MachineFunction &MF = DAG.getMachineFunction();
16438 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
16439 unsigned StackAlignment = TFI.getStackAlignment();
16440 MVT VT = Op.getSimpleValueType();
16443 // Save FP Control Word to stack slot
16444 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
16445 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
16447 MachineMemOperand *MMO =
16448 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
16449 MachineMemOperand::MOStore, 2, 2);
16451 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
16452 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
16453 DAG.getVTList(MVT::Other),
16454 Ops, MVT::i16, MMO);
16456 // Load FP Control Word from stack slot
16457 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
16458 MachinePointerInfo(), false, false, false, 0);
16460 // Transform as necessary
16462 DAG.getNode(ISD::SRL, DL, MVT::i16,
16463 DAG.getNode(ISD::AND, DL, MVT::i16,
16464 CWD, DAG.getConstant(0x800, DL, MVT::i16)),
16465 DAG.getConstant(11, DL, MVT::i8));
16467 DAG.getNode(ISD::SRL, DL, MVT::i16,
16468 DAG.getNode(ISD::AND, DL, MVT::i16,
16469 CWD, DAG.getConstant(0x400, DL, MVT::i16)),
16470 DAG.getConstant(9, DL, MVT::i8));
16473 DAG.getNode(ISD::AND, DL, MVT::i16,
16474 DAG.getNode(ISD::ADD, DL, MVT::i16,
16475 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
16476 DAG.getConstant(1, DL, MVT::i16)),
16477 DAG.getConstant(3, DL, MVT::i16));
16479 return DAG.getNode((VT.getSizeInBits() < 16 ?
16480 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
16483 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
16484 MVT VT = Op.getSimpleValueType();
16486 unsigned NumBits = VT.getSizeInBits();
16489 Op = Op.getOperand(0);
16490 if (VT == MVT::i8) {
16491 // Zero extend to i32 since there is not an i8 bsr.
16493 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
16496 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
16497 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
16498 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
16500 // If src is zero (i.e. bsr sets ZF), returns NumBits.
16503 DAG.getConstant(NumBits + NumBits - 1, dl, OpVT),
16504 DAG.getConstant(X86::COND_E, dl, MVT::i8),
16507 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
16509 // Finally xor with NumBits-1.
16510 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
16511 DAG.getConstant(NumBits - 1, dl, OpVT));
16514 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
16518 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
16519 MVT VT = Op.getSimpleValueType();
16521 unsigned NumBits = VT.getSizeInBits();
16524 Op = Op.getOperand(0);
16525 if (VT == MVT::i8) {
16526 // Zero extend to i32 since there is not an i8 bsr.
16528 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
16531 // Issue a bsr (scan bits in reverse).
16532 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
16533 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
16535 // And xor with NumBits-1.
16536 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
16537 DAG.getConstant(NumBits - 1, dl, OpVT));
16540 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
16544 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
16545 MVT VT = Op.getSimpleValueType();
16546 unsigned NumBits = VT.getSizeInBits();
16548 Op = Op.getOperand(0);
16550 // Issue a bsf (scan bits forward) which also sets EFLAGS.
16551 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
16552 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
16554 // If src is zero (i.e. bsf sets ZF), returns NumBits.
16557 DAG.getConstant(NumBits, dl, VT),
16558 DAG.getConstant(X86::COND_E, dl, MVT::i8),
16561 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
16564 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
16565 // ones, and then concatenate the result back.
16566 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
16567 MVT VT = Op.getSimpleValueType();
16569 assert(VT.is256BitVector() && VT.isInteger() &&
16570 "Unsupported value type for operation");
16572 unsigned NumElems = VT.getVectorNumElements();
16575 // Extract the LHS vectors
16576 SDValue LHS = Op.getOperand(0);
16577 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
16578 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
16580 // Extract the RHS vectors
16581 SDValue RHS = Op.getOperand(1);
16582 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
16583 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
16585 MVT EltVT = VT.getVectorElementType();
16586 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
16588 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
16589 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
16590 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
16593 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
16594 if (Op.getValueType() == MVT::i1)
16595 return DAG.getNode(ISD::XOR, SDLoc(Op), Op.getValueType(),
16596 Op.getOperand(0), Op.getOperand(1));
16597 assert(Op.getSimpleValueType().is256BitVector() &&
16598 Op.getSimpleValueType().isInteger() &&
16599 "Only handle AVX 256-bit vector integer operation");
16600 return Lower256IntArith(Op, DAG);
16603 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
16604 if (Op.getValueType() == MVT::i1)
16605 return DAG.getNode(ISD::XOR, SDLoc(Op), Op.getValueType(),
16606 Op.getOperand(0), Op.getOperand(1));
16607 assert(Op.getSimpleValueType().is256BitVector() &&
16608 Op.getSimpleValueType().isInteger() &&
16609 "Only handle AVX 256-bit vector integer operation");
16610 return Lower256IntArith(Op, DAG);
16613 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
16614 SelectionDAG &DAG) {
16616 MVT VT = Op.getSimpleValueType();
16619 return DAG.getNode(ISD::AND, dl, VT, Op.getOperand(0), Op.getOperand(1));
16621 // Decompose 256-bit ops into smaller 128-bit ops.
16622 if (VT.is256BitVector() && !Subtarget->hasInt256())
16623 return Lower256IntArith(Op, DAG);
16625 SDValue A = Op.getOperand(0);
16626 SDValue B = Op.getOperand(1);
16628 // Lower v16i8/v32i8 mul as promotion to v8i16/v16i16 vector
16629 // pairs, multiply and truncate.
16630 if (VT == MVT::v16i8 || VT == MVT::v32i8) {
16631 if (Subtarget->hasInt256()) {
16632 if (VT == MVT::v32i8) {
16633 MVT SubVT = MVT::getVectorVT(MVT::i8, VT.getVectorNumElements() / 2);
16634 SDValue Lo = DAG.getIntPtrConstant(0, dl);
16635 SDValue Hi = DAG.getIntPtrConstant(VT.getVectorNumElements() / 2, dl);
16636 SDValue ALo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Lo);
16637 SDValue BLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Lo);
16638 SDValue AHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Hi);
16639 SDValue BHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Hi);
16640 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
16641 DAG.getNode(ISD::MUL, dl, SubVT, ALo, BLo),
16642 DAG.getNode(ISD::MUL, dl, SubVT, AHi, BHi));
16645 MVT ExVT = MVT::getVectorVT(MVT::i16, VT.getVectorNumElements());
16646 return DAG.getNode(
16647 ISD::TRUNCATE, dl, VT,
16648 DAG.getNode(ISD::MUL, dl, ExVT,
16649 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, A),
16650 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, B)));
16653 assert(VT == MVT::v16i8 &&
16654 "Pre-AVX2 support only supports v16i8 multiplication");
16655 MVT ExVT = MVT::v8i16;
16657 // Extract the lo parts and sign extend to i16
16659 if (Subtarget->hasSSE41()) {
16660 ALo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, A);
16661 BLo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, B);
16663 const int ShufMask[] = {-1, 0, -1, 1, -1, 2, -1, 3,
16664 -1, 4, -1, 5, -1, 6, -1, 7};
16665 ALo = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
16666 BLo = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
16667 ALo = DAG.getBitcast(ExVT, ALo);
16668 BLo = DAG.getBitcast(ExVT, BLo);
16669 ALo = DAG.getNode(ISD::SRA, dl, ExVT, ALo, DAG.getConstant(8, dl, ExVT));
16670 BLo = DAG.getNode(ISD::SRA, dl, ExVT, BLo, DAG.getConstant(8, dl, ExVT));
16673 // Extract the hi parts and sign extend to i16
16675 if (Subtarget->hasSSE41()) {
16676 const int ShufMask[] = {8, 9, 10, 11, 12, 13, 14, 15,
16677 -1, -1, -1, -1, -1, -1, -1, -1};
16678 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
16679 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
16680 AHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, AHi);
16681 BHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, BHi);
16683 const int ShufMask[] = {-1, 8, -1, 9, -1, 10, -1, 11,
16684 -1, 12, -1, 13, -1, 14, -1, 15};
16685 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
16686 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
16687 AHi = DAG.getBitcast(ExVT, AHi);
16688 BHi = DAG.getBitcast(ExVT, BHi);
16689 AHi = DAG.getNode(ISD::SRA, dl, ExVT, AHi, DAG.getConstant(8, dl, ExVT));
16690 BHi = DAG.getNode(ISD::SRA, dl, ExVT, BHi, DAG.getConstant(8, dl, ExVT));
16693 // Multiply, mask the lower 8bits of the lo/hi results and pack
16694 SDValue RLo = DAG.getNode(ISD::MUL, dl, ExVT, ALo, BLo);
16695 SDValue RHi = DAG.getNode(ISD::MUL, dl, ExVT, AHi, BHi);
16696 RLo = DAG.getNode(ISD::AND, dl, ExVT, RLo, DAG.getConstant(255, dl, ExVT));
16697 RHi = DAG.getNode(ISD::AND, dl, ExVT, RHi, DAG.getConstant(255, dl, ExVT));
16698 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);
16701 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
16702 if (VT == MVT::v4i32) {
16703 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
16704 "Should not custom lower when pmuldq is available!");
16706 // Extract the odd parts.
16707 static const int UnpackMask[] = { 1, -1, 3, -1 };
16708 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
16709 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
16711 // Multiply the even parts.
16712 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
16713 // Now multiply odd parts.
16714 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
16716 Evens = DAG.getBitcast(VT, Evens);
16717 Odds = DAG.getBitcast(VT, Odds);
16719 // Merge the two vectors back together with a shuffle. This expands into 2
16721 static const int ShufMask[] = { 0, 4, 2, 6 };
16722 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
16725 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
16726 "Only know how to lower V2I64/V4I64/V8I64 multiply");
16728 // Ahi = psrlqi(a, 32);
16729 // Bhi = psrlqi(b, 32);
16731 // AloBlo = pmuludq(a, b);
16732 // AloBhi = pmuludq(a, Bhi);
16733 // AhiBlo = pmuludq(Ahi, b);
16735 // AloBhi = psllqi(AloBhi, 32);
16736 // AhiBlo = psllqi(AhiBlo, 32);
16737 // return AloBlo + AloBhi + AhiBlo;
16739 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
16740 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
16742 SDValue AhiBlo = Ahi;
16743 SDValue AloBhi = Bhi;
16744 // Bit cast to 32-bit vectors for MULUDQ
16745 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
16746 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
16747 A = DAG.getBitcast(MulVT, A);
16748 B = DAG.getBitcast(MulVT, B);
16749 Ahi = DAG.getBitcast(MulVT, Ahi);
16750 Bhi = DAG.getBitcast(MulVT, Bhi);
16752 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
16753 // After shifting right const values the result may be all-zero.
16754 if (!ISD::isBuildVectorAllZeros(Ahi.getNode())) {
16755 AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
16756 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
16758 if (!ISD::isBuildVectorAllZeros(Bhi.getNode())) {
16759 AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
16760 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
16763 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
16764 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
16767 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
16768 assert(Subtarget->isTargetWin64() && "Unexpected target");
16769 EVT VT = Op.getValueType();
16770 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
16771 "Unexpected return type for lowering");
16775 switch (Op->getOpcode()) {
16776 default: llvm_unreachable("Unexpected request for libcall!");
16777 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
16778 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
16779 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
16780 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
16781 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
16782 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
16786 SDValue InChain = DAG.getEntryNode();
16788 TargetLowering::ArgListTy Args;
16789 TargetLowering::ArgListEntry Entry;
16790 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
16791 EVT ArgVT = Op->getOperand(i).getValueType();
16792 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
16793 "Unexpected argument type for lowering");
16794 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
16795 Entry.Node = StackPtr;
16796 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
16798 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
16799 Entry.Ty = PointerType::get(ArgTy,0);
16800 Entry.isSExt = false;
16801 Entry.isZExt = false;
16802 Args.push_back(Entry);
16805 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
16808 TargetLowering::CallLoweringInfo CLI(DAG);
16809 CLI.setDebugLoc(dl).setChain(InChain)
16810 .setCallee(getLibcallCallingConv(LC),
16811 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
16812 Callee, std::move(Args), 0)
16813 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
16815 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
16816 return DAG.getBitcast(VT, CallInfo.first);
16819 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
16820 SelectionDAG &DAG) {
16821 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
16822 EVT VT = Op0.getValueType();
16825 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
16826 (VT == MVT::v8i32 && Subtarget->hasInt256()));
16828 // PMULxD operations multiply each even value (starting at 0) of LHS with
16829 // the related value of RHS and produce a widen result.
16830 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
16831 // => <2 x i64> <ae|cg>
16833 // In other word, to have all the results, we need to perform two PMULxD:
16834 // 1. one with the even values.
16835 // 2. one with the odd values.
16836 // To achieve #2, with need to place the odd values at an even position.
16838 // Place the odd value at an even position (basically, shift all values 1
16839 // step to the left):
16840 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
16841 // <a|b|c|d> => <b|undef|d|undef>
16842 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
16843 // <e|f|g|h> => <f|undef|h|undef>
16844 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
16846 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
16848 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
16849 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
16851 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
16852 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
16853 // => <2 x i64> <ae|cg>
16854 SDValue Mul1 = DAG.getBitcast(VT, DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
16855 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
16856 // => <2 x i64> <bf|dh>
16857 SDValue Mul2 = DAG.getBitcast(VT, DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
16859 // Shuffle it back into the right order.
16860 SDValue Highs, Lows;
16861 if (VT == MVT::v8i32) {
16862 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
16863 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
16864 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
16865 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
16867 const int HighMask[] = {1, 5, 3, 7};
16868 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
16869 const int LowMask[] = {0, 4, 2, 6};
16870 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
16873 // If we have a signed multiply but no PMULDQ fix up the high parts of a
16874 // unsigned multiply.
16875 if (IsSigned && !Subtarget->hasSSE41()) {
16877 DAG.getConstant(31, dl,
16878 DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
16879 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
16880 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
16881 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
16882 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
16884 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
16885 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
16888 // The first result of MUL_LOHI is actually the low value, followed by the
16890 SDValue Ops[] = {Lows, Highs};
16891 return DAG.getMergeValues(Ops, dl);
16894 // Return true if the requred (according to Opcode) shift-imm form is natively
16895 // supported by the Subtarget
16896 static bool SupportedVectorShiftWithImm(MVT VT, const X86Subtarget *Subtarget,
16898 if (VT.getScalarSizeInBits() < 16)
16901 if (VT.is512BitVector() &&
16902 (VT.getScalarSizeInBits() > 16 || Subtarget->hasBWI()))
16905 bool LShift = VT.is128BitVector() ||
16906 (VT.is256BitVector() && Subtarget->hasInt256());
16908 bool AShift = LShift && (Subtarget->hasVLX() ||
16909 (VT != MVT::v2i64 && VT != MVT::v4i64));
16910 return (Opcode == ISD::SRA) ? AShift : LShift;
16913 // The shift amount is a variable, but it is the same for all vector lanes.
16914 // These instrcutions are defined together with shift-immediate.
16916 bool SupportedVectorShiftWithBaseAmnt(MVT VT, const X86Subtarget *Subtarget,
16918 return SupportedVectorShiftWithImm(VT, Subtarget, Opcode);
16921 // Return true if the requred (according to Opcode) variable-shift form is
16922 // natively supported by the Subtarget
16923 static bool SupportedVectorVarShift(MVT VT, const X86Subtarget *Subtarget,
16926 if (!Subtarget->hasInt256() || VT.getScalarSizeInBits() < 16)
16929 // vXi16 supported only on AVX-512, BWI
16930 if (VT.getScalarSizeInBits() == 16 && !Subtarget->hasBWI())
16933 if (VT.is512BitVector() || Subtarget->hasVLX())
16936 bool LShift = VT.is128BitVector() || VT.is256BitVector();
16937 bool AShift = LShift && VT != MVT::v2i64 && VT != MVT::v4i64;
16938 return (Opcode == ISD::SRA) ? AShift : LShift;
16941 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
16942 const X86Subtarget *Subtarget) {
16943 MVT VT = Op.getSimpleValueType();
16945 SDValue R = Op.getOperand(0);
16946 SDValue Amt = Op.getOperand(1);
16948 unsigned X86Opc = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
16949 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
16951 // Optimize shl/srl/sra with constant shift amount.
16952 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
16953 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
16954 uint64_t ShiftAmt = ShiftConst->getZExtValue();
16956 if (SupportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode()))
16957 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
16959 if (VT == MVT::v16i8 || (Subtarget->hasInt256() && VT == MVT::v32i8)) {
16960 unsigned NumElts = VT.getVectorNumElements();
16961 MVT ShiftVT = MVT::getVectorVT(MVT::i16, NumElts / 2);
16963 if (Op.getOpcode() == ISD::SHL) {
16964 // Simple i8 add case
16966 return DAG.getNode(ISD::ADD, dl, VT, R, R);
16968 // Make a large shift.
16969 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, ShiftVT,
16971 SHL = DAG.getBitcast(VT, SHL);
16972 // Zero out the rightmost bits.
16973 SmallVector<SDValue, 32> V(
16974 NumElts, DAG.getConstant(uint8_t(-1U << ShiftAmt), dl, MVT::i8));
16975 return DAG.getNode(ISD::AND, dl, VT, SHL,
16976 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
16978 if (Op.getOpcode() == ISD::SRL) {
16979 // Make a large shift.
16980 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, ShiftVT,
16982 SRL = DAG.getBitcast(VT, SRL);
16983 // Zero out the leftmost bits.
16984 SmallVector<SDValue, 32> V(
16985 NumElts, DAG.getConstant(uint8_t(-1U) >> ShiftAmt, dl, MVT::i8));
16986 return DAG.getNode(ISD::AND, dl, VT, SRL,
16987 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
16989 if (Op.getOpcode() == ISD::SRA) {
16990 if (ShiftAmt == 7) {
16991 // R s>> 7 === R s< 0
16992 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
16993 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
16996 // R s>> a === ((R u>> a) ^ m) - m
16997 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
16998 SmallVector<SDValue, 32> V(NumElts,
16999 DAG.getConstant(128 >> ShiftAmt, dl,
17001 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
17002 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
17003 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
17006 llvm_unreachable("Unknown shift opcode.");
17011 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
17012 if (!Subtarget->is64Bit() &&
17013 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
17014 Amt.getOpcode() == ISD::BITCAST &&
17015 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
17016 Amt = Amt.getOperand(0);
17017 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
17018 VT.getVectorNumElements();
17019 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
17020 uint64_t ShiftAmt = 0;
17021 for (unsigned i = 0; i != Ratio; ++i) {
17022 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
17026 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
17028 // Check remaining shift amounts.
17029 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
17030 uint64_t ShAmt = 0;
17031 for (unsigned j = 0; j != Ratio; ++j) {
17032 ConstantSDNode *C =
17033 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
17037 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
17039 if (ShAmt != ShiftAmt)
17042 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
17048 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
17049 const X86Subtarget* Subtarget) {
17050 MVT VT = Op.getSimpleValueType();
17052 SDValue R = Op.getOperand(0);
17053 SDValue Amt = Op.getOperand(1);
17055 unsigned X86OpcI = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
17056 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
17058 unsigned X86OpcV = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHL :
17059 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRL : X86ISD::VSRA;
17061 if (SupportedVectorShiftWithBaseAmnt(VT, Subtarget, Op.getOpcode())) {
17063 EVT EltVT = VT.getVectorElementType();
17065 if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Amt)) {
17066 // Check if this build_vector node is doing a splat.
17067 // If so, then set BaseShAmt equal to the splat value.
17068 BaseShAmt = BV->getSplatValue();
17069 if (BaseShAmt && BaseShAmt.getOpcode() == ISD::UNDEF)
17070 BaseShAmt = SDValue();
17072 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
17073 Amt = Amt.getOperand(0);
17075 ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt);
17076 if (SVN && SVN->isSplat()) {
17077 unsigned SplatIdx = (unsigned)SVN->getSplatIndex();
17078 SDValue InVec = Amt.getOperand(0);
17079 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
17080 assert((SplatIdx < InVec.getValueType().getVectorNumElements()) &&
17081 "Unexpected shuffle index found!");
17082 BaseShAmt = InVec.getOperand(SplatIdx);
17083 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
17084 if (ConstantSDNode *C =
17085 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
17086 if (C->getZExtValue() == SplatIdx)
17087 BaseShAmt = InVec.getOperand(1);
17092 // Avoid introducing an extract element from a shuffle.
17093 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InVec,
17094 DAG.getIntPtrConstant(SplatIdx, dl));
17098 if (BaseShAmt.getNode()) {
17099 assert(EltVT.bitsLE(MVT::i64) && "Unexpected element type!");
17100 if (EltVT != MVT::i64 && EltVT.bitsGT(MVT::i32))
17101 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, BaseShAmt);
17102 else if (EltVT.bitsLT(MVT::i32))
17103 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
17105 return getTargetVShiftNode(X86OpcI, dl, VT, R, BaseShAmt, DAG);
17109 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
17110 if (!Subtarget->is64Bit() && VT == MVT::v2i64 &&
17111 Amt.getOpcode() == ISD::BITCAST &&
17112 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
17113 Amt = Amt.getOperand(0);
17114 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
17115 VT.getVectorNumElements();
17116 std::vector<SDValue> Vals(Ratio);
17117 for (unsigned i = 0; i != Ratio; ++i)
17118 Vals[i] = Amt.getOperand(i);
17119 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
17120 for (unsigned j = 0; j != Ratio; ++j)
17121 if (Vals[j] != Amt.getOperand(i + j))
17124 return DAG.getNode(X86OpcV, dl, VT, R, Op.getOperand(1));
17129 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
17130 SelectionDAG &DAG) {
17131 MVT VT = Op.getSimpleValueType();
17133 SDValue R = Op.getOperand(0);
17134 SDValue Amt = Op.getOperand(1);
17136 assert(VT.isVector() && "Custom lowering only for vector shifts!");
17137 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
17139 if (SDValue V = LowerScalarImmediateShift(Op, DAG, Subtarget))
17142 if (SDValue V = LowerScalarVariableShift(Op, DAG, Subtarget))
17145 if (SupportedVectorVarShift(VT, Subtarget, Op.getOpcode()))
17148 // 2i64 vector logical shifts can efficiently avoid scalarization - do the
17149 // shifts per-lane and then shuffle the partial results back together.
17150 if (VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) {
17151 // Splat the shift amounts so the scalar shifts above will catch it.
17152 SDValue Amt0 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {0, 0});
17153 SDValue Amt1 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {1, 1});
17154 SDValue R0 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt0);
17155 SDValue R1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt1);
17156 return DAG.getVectorShuffle(VT, dl, R0, R1, {0, 3});
17159 // If possible, lower this packed shift into a vector multiply instead of
17160 // expanding it into a sequence of scalar shifts.
17161 // Do this only if the vector shift count is a constant build_vector.
17162 if (Op.getOpcode() == ISD::SHL &&
17163 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
17164 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
17165 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
17166 SmallVector<SDValue, 8> Elts;
17167 EVT SVT = VT.getScalarType();
17168 unsigned SVTBits = SVT.getSizeInBits();
17169 const APInt &One = APInt(SVTBits, 1);
17170 unsigned NumElems = VT.getVectorNumElements();
17172 for (unsigned i=0; i !=NumElems; ++i) {
17173 SDValue Op = Amt->getOperand(i);
17174 if (Op->getOpcode() == ISD::UNDEF) {
17175 Elts.push_back(Op);
17179 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
17180 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
17181 uint64_t ShAmt = C.getZExtValue();
17182 if (ShAmt >= SVTBits) {
17183 Elts.push_back(DAG.getUNDEF(SVT));
17186 Elts.push_back(DAG.getConstant(One.shl(ShAmt), dl, SVT));
17188 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
17189 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
17192 // Lower SHL with variable shift amount.
17193 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
17194 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, dl, VT));
17196 Op = DAG.getNode(ISD::ADD, dl, VT, Op,
17197 DAG.getConstant(0x3f800000U, dl, VT));
17198 Op = DAG.getBitcast(MVT::v4f32, Op);
17199 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
17200 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
17203 // If possible, lower this shift as a sequence of two shifts by
17204 // constant plus a MOVSS/MOVSD instead of scalarizing it.
17206 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
17208 // Could be rewritten as:
17209 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
17211 // The advantage is that the two shifts from the example would be
17212 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
17213 // the vector shift into four scalar shifts plus four pairs of vector
17215 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
17216 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
17217 unsigned TargetOpcode = X86ISD::MOVSS;
17218 bool CanBeSimplified;
17219 // The splat value for the first packed shift (the 'X' from the example).
17220 SDValue Amt1 = Amt->getOperand(0);
17221 // The splat value for the second packed shift (the 'Y' from the example).
17222 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
17223 Amt->getOperand(2);
17225 // See if it is possible to replace this node with a sequence of
17226 // two shifts followed by a MOVSS/MOVSD
17227 if (VT == MVT::v4i32) {
17228 // Check if it is legal to use a MOVSS.
17229 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
17230 Amt2 == Amt->getOperand(3);
17231 if (!CanBeSimplified) {
17232 // Otherwise, check if we can still simplify this node using a MOVSD.
17233 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
17234 Amt->getOperand(2) == Amt->getOperand(3);
17235 TargetOpcode = X86ISD::MOVSD;
17236 Amt2 = Amt->getOperand(2);
17239 // Do similar checks for the case where the machine value type
17241 CanBeSimplified = Amt1 == Amt->getOperand(1);
17242 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
17243 CanBeSimplified = Amt2 == Amt->getOperand(i);
17245 if (!CanBeSimplified) {
17246 TargetOpcode = X86ISD::MOVSD;
17247 CanBeSimplified = true;
17248 Amt2 = Amt->getOperand(4);
17249 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
17250 CanBeSimplified = Amt1 == Amt->getOperand(i);
17251 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
17252 CanBeSimplified = Amt2 == Amt->getOperand(j);
17256 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
17257 isa<ConstantSDNode>(Amt2)) {
17258 // Replace this node with two shifts followed by a MOVSS/MOVSD.
17259 EVT CastVT = MVT::v4i32;
17261 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), dl, VT);
17262 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
17264 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), dl, VT);
17265 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
17266 if (TargetOpcode == X86ISD::MOVSD)
17267 CastVT = MVT::v2i64;
17268 SDValue BitCast1 = DAG.getBitcast(CastVT, Shift1);
17269 SDValue BitCast2 = DAG.getBitcast(CastVT, Shift2);
17270 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
17272 return DAG.getBitcast(VT, Result);
17276 if (VT == MVT::v16i8 || (VT == MVT::v32i8 && Subtarget->hasInt256())) {
17277 MVT ExtVT = MVT::getVectorVT(MVT::i16, VT.getVectorNumElements() / 2);
17278 unsigned ShiftOpcode = Op->getOpcode();
17280 auto SignBitSelect = [&](MVT SelVT, SDValue Sel, SDValue V0, SDValue V1) {
17281 // On SSE41 targets we make use of the fact that VSELECT lowers
17282 // to PBLENDVB which selects bytes based just on the sign bit.
17283 if (Subtarget->hasSSE41()) {
17284 V0 = DAG.getBitcast(VT, V0);
17285 V1 = DAG.getBitcast(VT, V1);
17286 Sel = DAG.getBitcast(VT, Sel);
17287 return DAG.getBitcast(SelVT,
17288 DAG.getNode(ISD::VSELECT, dl, VT, Sel, V0, V1));
17290 // On pre-SSE41 targets we test for the sign bit by comparing to
17291 // zero - a negative value will set all bits of the lanes to true
17292 // and VSELECT uses that in its OR(AND(V0,C),AND(V1,~C)) lowering.
17293 SDValue Z = getZeroVector(SelVT, Subtarget, DAG, dl);
17294 SDValue C = DAG.getNode(X86ISD::PCMPGT, dl, SelVT, Z, Sel);
17295 return DAG.getNode(ISD::VSELECT, dl, SelVT, C, V0, V1);
17298 // Turn 'a' into a mask suitable for VSELECT: a = a << 5;
17299 // We can safely do this using i16 shifts as we're only interested in
17300 // the 3 lower bits of each byte.
17301 Amt = DAG.getBitcast(ExtVT, Amt);
17302 Amt = DAG.getNode(ISD::SHL, dl, ExtVT, Amt, DAG.getConstant(5, dl, ExtVT));
17303 Amt = DAG.getBitcast(VT, Amt);
17305 if (Op->getOpcode() == ISD::SHL || Op->getOpcode() == ISD::SRL) {
17306 // r = VSELECT(r, shift(r, 4), a);
17308 DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(4, dl, VT));
17309 R = SignBitSelect(VT, Amt, M, R);
17312 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
17314 // r = VSELECT(r, shift(r, 2), a);
17315 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(2, dl, VT));
17316 R = SignBitSelect(VT, Amt, M, R);
17319 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
17321 // return VSELECT(r, shift(r, 1), a);
17322 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(1, dl, VT));
17323 R = SignBitSelect(VT, Amt, M, R);
17327 if (Op->getOpcode() == ISD::SRA) {
17328 // For SRA we need to unpack each byte to the higher byte of a i16 vector
17329 // so we can correctly sign extend. We don't care what happens to the
17331 SDValue ALo = DAG.getNode(X86ISD::UNPCKL, dl, VT, DAG.getUNDEF(VT), Amt);
17332 SDValue AHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, DAG.getUNDEF(VT), Amt);
17333 SDValue RLo = DAG.getNode(X86ISD::UNPCKL, dl, VT, DAG.getUNDEF(VT), R);
17334 SDValue RHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, DAG.getUNDEF(VT), R);
17335 ALo = DAG.getBitcast(ExtVT, ALo);
17336 AHi = DAG.getBitcast(ExtVT, AHi);
17337 RLo = DAG.getBitcast(ExtVT, RLo);
17338 RHi = DAG.getBitcast(ExtVT, RHi);
17340 // r = VSELECT(r, shift(r, 4), a);
17341 SDValue MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
17342 DAG.getConstant(4, dl, ExtVT));
17343 SDValue MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
17344 DAG.getConstant(4, dl, ExtVT));
17345 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
17346 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
17349 ALo = DAG.getNode(ISD::ADD, dl, ExtVT, ALo, ALo);
17350 AHi = DAG.getNode(ISD::ADD, dl, ExtVT, AHi, AHi);
17352 // r = VSELECT(r, shift(r, 2), a);
17353 MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
17354 DAG.getConstant(2, dl, ExtVT));
17355 MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
17356 DAG.getConstant(2, dl, ExtVT));
17357 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
17358 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
17361 ALo = DAG.getNode(ISD::ADD, dl, ExtVT, ALo, ALo);
17362 AHi = DAG.getNode(ISD::ADD, dl, ExtVT, AHi, AHi);
17364 // r = VSELECT(r, shift(r, 1), a);
17365 MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
17366 DAG.getConstant(1, dl, ExtVT));
17367 MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
17368 DAG.getConstant(1, dl, ExtVT));
17369 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
17370 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
17372 // Logical shift the result back to the lower byte, leaving a zero upper
17374 // meaning that we can safely pack with PACKUSWB.
17376 DAG.getNode(ISD::SRL, dl, ExtVT, RLo, DAG.getConstant(8, dl, ExtVT));
17378 DAG.getNode(ISD::SRL, dl, ExtVT, RHi, DAG.getConstant(8, dl, ExtVT));
17379 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);
17383 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
17384 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
17385 // solution better.
17386 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
17387 MVT ExtVT = MVT::v8i32;
17389 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
17390 R = DAG.getNode(ExtOpc, dl, ExtVT, R);
17391 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, ExtVT, Amt);
17392 return DAG.getNode(ISD::TRUNCATE, dl, VT,
17393 DAG.getNode(Op.getOpcode(), dl, ExtVT, R, Amt));
17396 if (Subtarget->hasInt256() && VT == MVT::v16i16) {
17397 MVT ExtVT = MVT::v8i32;
17398 SDValue Z = getZeroVector(VT, Subtarget, DAG, dl);
17399 SDValue ALo = DAG.getNode(X86ISD::UNPCKL, dl, VT, Amt, Z);
17400 SDValue AHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, Amt, Z);
17401 SDValue RLo = DAG.getNode(X86ISD::UNPCKL, dl, VT, R, R);
17402 SDValue RHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, R, R);
17403 ALo = DAG.getBitcast(ExtVT, ALo);
17404 AHi = DAG.getBitcast(ExtVT, AHi);
17405 RLo = DAG.getBitcast(ExtVT, RLo);
17406 RHi = DAG.getBitcast(ExtVT, RHi);
17407 SDValue Lo = DAG.getNode(Op.getOpcode(), dl, ExtVT, RLo, ALo);
17408 SDValue Hi = DAG.getNode(Op.getOpcode(), dl, ExtVT, RHi, AHi);
17409 Lo = DAG.getNode(ISD::SRL, dl, ExtVT, Lo, DAG.getConstant(16, dl, ExtVT));
17410 Hi = DAG.getNode(ISD::SRL, dl, ExtVT, Hi, DAG.getConstant(16, dl, ExtVT));
17411 return DAG.getNode(X86ISD::PACKUS, dl, VT, Lo, Hi);
17414 if (VT == MVT::v8i16) {
17415 unsigned ShiftOpcode = Op->getOpcode();
17417 auto SignBitSelect = [&](SDValue Sel, SDValue V0, SDValue V1) {
17418 // On SSE41 targets we make use of the fact that VSELECT lowers
17419 // to PBLENDVB which selects bytes based just on the sign bit.
17420 if (Subtarget->hasSSE41()) {
17421 MVT ExtVT = MVT::getVectorVT(MVT::i8, VT.getVectorNumElements() * 2);
17422 V0 = DAG.getBitcast(ExtVT, V0);
17423 V1 = DAG.getBitcast(ExtVT, V1);
17424 Sel = DAG.getBitcast(ExtVT, Sel);
17425 return DAG.getBitcast(
17426 VT, DAG.getNode(ISD::VSELECT, dl, ExtVT, Sel, V0, V1));
17428 // On pre-SSE41 targets we splat the sign bit - a negative value will
17429 // set all bits of the lanes to true and VSELECT uses that in
17430 // its OR(AND(V0,C),AND(V1,~C)) lowering.
17432 DAG.getNode(ISD::SRA, dl, VT, Sel, DAG.getConstant(15, dl, VT));
17433 return DAG.getNode(ISD::VSELECT, dl, VT, C, V0, V1);
17436 // Turn 'a' into a mask suitable for VSELECT: a = a << 12;
17437 if (Subtarget->hasSSE41()) {
17438 // On SSE41 targets we need to replicate the shift mask in both
17439 // bytes for PBLENDVB.
17442 DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(4, dl, VT)),
17443 DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(12, dl, VT)));
17445 Amt = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(12, dl, VT));
17448 // r = VSELECT(r, shift(r, 8), a);
17449 SDValue M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(8, dl, VT));
17450 R = SignBitSelect(Amt, M, R);
17453 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
17455 // r = VSELECT(r, shift(r, 4), a);
17456 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(4, dl, VT));
17457 R = SignBitSelect(Amt, M, R);
17460 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
17462 // r = VSELECT(r, shift(r, 2), a);
17463 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(2, dl, VT));
17464 R = SignBitSelect(Amt, M, R);
17467 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
17469 // return VSELECT(r, shift(r, 1), a);
17470 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(1, dl, VT));
17471 R = SignBitSelect(Amt, M, R);
17475 // Decompose 256-bit shifts into smaller 128-bit shifts.
17476 if (VT.is256BitVector()) {
17477 unsigned NumElems = VT.getVectorNumElements();
17478 MVT EltVT = VT.getVectorElementType();
17479 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17481 // Extract the two vectors
17482 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
17483 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
17485 // Recreate the shift amount vectors
17486 SDValue Amt1, Amt2;
17487 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
17488 // Constant shift amount
17489 SmallVector<SDValue, 8> Ops(Amt->op_begin(), Amt->op_begin() + NumElems);
17490 ArrayRef<SDValue> Amt1Csts = makeArrayRef(Ops).slice(0, NumElems / 2);
17491 ArrayRef<SDValue> Amt2Csts = makeArrayRef(Ops).slice(NumElems / 2);
17493 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
17494 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
17496 // Variable shift amount
17497 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
17498 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
17501 // Issue new vector shifts for the smaller types
17502 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
17503 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
17505 // Concatenate the result back
17506 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
17512 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
17513 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
17514 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
17515 // looks for this combo and may remove the "setcc" instruction if the "setcc"
17516 // has only one use.
17517 SDNode *N = Op.getNode();
17518 SDValue LHS = N->getOperand(0);
17519 SDValue RHS = N->getOperand(1);
17520 unsigned BaseOp = 0;
17523 switch (Op.getOpcode()) {
17524 default: llvm_unreachable("Unknown ovf instruction!");
17526 // A subtract of one will be selected as a INC. Note that INC doesn't
17527 // set CF, so we can't do this for UADDO.
17528 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
17530 BaseOp = X86ISD::INC;
17531 Cond = X86::COND_O;
17534 BaseOp = X86ISD::ADD;
17535 Cond = X86::COND_O;
17538 BaseOp = X86ISD::ADD;
17539 Cond = X86::COND_B;
17542 // A subtract of one will be selected as a DEC. Note that DEC doesn't
17543 // set CF, so we can't do this for USUBO.
17544 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
17546 BaseOp = X86ISD::DEC;
17547 Cond = X86::COND_O;
17550 BaseOp = X86ISD::SUB;
17551 Cond = X86::COND_O;
17554 BaseOp = X86ISD::SUB;
17555 Cond = X86::COND_B;
17558 BaseOp = N->getValueType(0) == MVT::i8 ? X86ISD::SMUL8 : X86ISD::SMUL;
17559 Cond = X86::COND_O;
17561 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
17562 if (N->getValueType(0) == MVT::i8) {
17563 BaseOp = X86ISD::UMUL8;
17564 Cond = X86::COND_O;
17567 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
17569 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
17572 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
17573 DAG.getConstant(X86::COND_O, DL, MVT::i32),
17574 SDValue(Sum.getNode(), 2));
17576 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
17580 // Also sets EFLAGS.
17581 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
17582 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
17585 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
17586 DAG.getConstant(Cond, DL, MVT::i32),
17587 SDValue(Sum.getNode(), 1));
17589 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
17592 /// Returns true if the operand type is exactly twice the native width, and
17593 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
17594 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
17595 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
17596 bool X86TargetLowering::needsCmpXchgNb(const Type *MemType) const {
17597 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
17600 return !Subtarget->is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
17601 else if (OpWidth == 128)
17602 return Subtarget->hasCmpxchg16b();
17607 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
17608 return needsCmpXchgNb(SI->getValueOperand()->getType());
17611 // Note: this turns large loads into lock cmpxchg8b/16b.
17612 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
17613 bool X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
17614 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
17615 return needsCmpXchgNb(PTy->getElementType());
17618 TargetLoweringBase::AtomicRMWExpansionKind
17619 X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
17620 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
17621 const Type *MemType = AI->getType();
17623 // If the operand is too big, we must see if cmpxchg8/16b is available
17624 // and default to library calls otherwise.
17625 if (MemType->getPrimitiveSizeInBits() > NativeWidth) {
17626 return needsCmpXchgNb(MemType) ? AtomicRMWExpansionKind::CmpXChg
17627 : AtomicRMWExpansionKind::None;
17630 AtomicRMWInst::BinOp Op = AI->getOperation();
17633 llvm_unreachable("Unknown atomic operation");
17634 case AtomicRMWInst::Xchg:
17635 case AtomicRMWInst::Add:
17636 case AtomicRMWInst::Sub:
17637 // It's better to use xadd, xsub or xchg for these in all cases.
17638 return AtomicRMWExpansionKind::None;
17639 case AtomicRMWInst::Or:
17640 case AtomicRMWInst::And:
17641 case AtomicRMWInst::Xor:
17642 // If the atomicrmw's result isn't actually used, we can just add a "lock"
17643 // prefix to a normal instruction for these operations.
17644 return !AI->use_empty() ? AtomicRMWExpansionKind::CmpXChg
17645 : AtomicRMWExpansionKind::None;
17646 case AtomicRMWInst::Nand:
17647 case AtomicRMWInst::Max:
17648 case AtomicRMWInst::Min:
17649 case AtomicRMWInst::UMax:
17650 case AtomicRMWInst::UMin:
17651 // These always require a non-trivial set of data operations on x86. We must
17652 // use a cmpxchg loop.
17653 return AtomicRMWExpansionKind::CmpXChg;
17657 static bool hasMFENCE(const X86Subtarget& Subtarget) {
17658 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
17659 // no-sse2). There isn't any reason to disable it if the target processor
17661 return Subtarget.hasSSE2() || Subtarget.is64Bit();
17665 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
17666 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
17667 const Type *MemType = AI->getType();
17668 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
17669 // there is no benefit in turning such RMWs into loads, and it is actually
17670 // harmful as it introduces a mfence.
17671 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
17674 auto Builder = IRBuilder<>(AI);
17675 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
17676 auto SynchScope = AI->getSynchScope();
17677 // We must restrict the ordering to avoid generating loads with Release or
17678 // ReleaseAcquire orderings.
17679 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
17680 auto Ptr = AI->getPointerOperand();
17682 // Before the load we need a fence. Here is an example lifted from
17683 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
17686 // x.store(1, relaxed);
17687 // r1 = y.fetch_add(0, release);
17689 // y.fetch_add(42, acquire);
17690 // r2 = x.load(relaxed);
17691 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
17692 // lowered to just a load without a fence. A mfence flushes the store buffer,
17693 // making the optimization clearly correct.
17694 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
17695 // otherwise, we might be able to be more agressive on relaxed idempotent
17696 // rmw. In practice, they do not look useful, so we don't try to be
17697 // especially clever.
17698 if (SynchScope == SingleThread)
17699 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
17700 // the IR level, so we must wrap it in an intrinsic.
17703 if (!hasMFENCE(*Subtarget))
17704 // FIXME: it might make sense to use a locked operation here but on a
17705 // different cache-line to prevent cache-line bouncing. In practice it
17706 // is probably a small win, and x86 processors without mfence are rare
17707 // enough that we do not bother.
17711 llvm::Intrinsic::getDeclaration(M, Intrinsic::x86_sse2_mfence);
17712 Builder.CreateCall(MFence, {});
17714 // Finally we can emit the atomic load.
17715 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
17716 AI->getType()->getPrimitiveSizeInBits());
17717 Loaded->setAtomic(Order, SynchScope);
17718 AI->replaceAllUsesWith(Loaded);
17719 AI->eraseFromParent();
17723 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
17724 SelectionDAG &DAG) {
17726 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
17727 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
17728 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
17729 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
17731 // The only fence that needs an instruction is a sequentially-consistent
17732 // cross-thread fence.
17733 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
17734 if (hasMFENCE(*Subtarget))
17735 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
17737 SDValue Chain = Op.getOperand(0);
17738 SDValue Zero = DAG.getConstant(0, dl, MVT::i32);
17740 DAG.getRegister(X86::ESP, MVT::i32), // Base
17741 DAG.getTargetConstant(1, dl, MVT::i8), // Scale
17742 DAG.getRegister(0, MVT::i32), // Index
17743 DAG.getTargetConstant(0, dl, MVT::i32), // Disp
17744 DAG.getRegister(0, MVT::i32), // Segment.
17748 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
17749 return SDValue(Res, 0);
17752 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
17753 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
17756 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
17757 SelectionDAG &DAG) {
17758 MVT T = Op.getSimpleValueType();
17762 switch(T.SimpleTy) {
17763 default: llvm_unreachable("Invalid value type!");
17764 case MVT::i8: Reg = X86::AL; size = 1; break;
17765 case MVT::i16: Reg = X86::AX; size = 2; break;
17766 case MVT::i32: Reg = X86::EAX; size = 4; break;
17768 assert(Subtarget->is64Bit() && "Node not type legal!");
17769 Reg = X86::RAX; size = 8;
17772 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
17773 Op.getOperand(2), SDValue());
17774 SDValue Ops[] = { cpIn.getValue(0),
17777 DAG.getTargetConstant(size, DL, MVT::i8),
17778 cpIn.getValue(1) };
17779 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17780 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
17781 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
17785 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
17786 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
17787 MVT::i32, cpOut.getValue(2));
17788 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
17789 DAG.getConstant(X86::COND_E, DL, MVT::i8),
17792 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
17793 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
17794 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
17798 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
17799 SelectionDAG &DAG) {
17800 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
17801 MVT DstVT = Op.getSimpleValueType();
17803 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
17804 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
17805 if (DstVT != MVT::f64)
17806 // This conversion needs to be expanded.
17809 SDValue InVec = Op->getOperand(0);
17811 unsigned NumElts = SrcVT.getVectorNumElements();
17812 EVT SVT = SrcVT.getVectorElementType();
17814 // Widen the vector in input in the case of MVT::v2i32.
17815 // Example: from MVT::v2i32 to MVT::v4i32.
17816 SmallVector<SDValue, 16> Elts;
17817 for (unsigned i = 0, e = NumElts; i != e; ++i)
17818 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
17819 DAG.getIntPtrConstant(i, dl)));
17821 // Explicitly mark the extra elements as Undef.
17822 Elts.append(NumElts, DAG.getUNDEF(SVT));
17824 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
17825 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
17826 SDValue ToV2F64 = DAG.getBitcast(MVT::v2f64, BV);
17827 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
17828 DAG.getIntPtrConstant(0, dl));
17831 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
17832 Subtarget->hasMMX() && "Unexpected custom BITCAST");
17833 assert((DstVT == MVT::i64 ||
17834 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
17835 "Unexpected custom BITCAST");
17836 // i64 <=> MMX conversions are Legal.
17837 if (SrcVT==MVT::i64 && DstVT.isVector())
17839 if (DstVT==MVT::i64 && SrcVT.isVector())
17841 // MMX <=> MMX conversions are Legal.
17842 if (SrcVT.isVector() && DstVT.isVector())
17844 // All other conversions need to be expanded.
17848 /// Compute the horizontal sum of bytes in V for the elements of VT.
17850 /// Requires V to be a byte vector and VT to be an integer vector type with
17851 /// wider elements than V's type. The width of the elements of VT determines
17852 /// how many bytes of V are summed horizontally to produce each element of the
17854 static SDValue LowerHorizontalByteSum(SDValue V, MVT VT,
17855 const X86Subtarget *Subtarget,
17856 SelectionDAG &DAG) {
17858 MVT ByteVecVT = V.getSimpleValueType();
17859 MVT EltVT = VT.getVectorElementType();
17860 int NumElts = VT.getVectorNumElements();
17861 assert(ByteVecVT.getVectorElementType() == MVT::i8 &&
17862 "Expected value to have byte element type.");
17863 assert(EltVT != MVT::i8 &&
17864 "Horizontal byte sum only makes sense for wider elements!");
17865 unsigned VecSize = VT.getSizeInBits();
17866 assert(ByteVecVT.getSizeInBits() == VecSize && "Cannot change vector size!");
17868 // PSADBW instruction horizontally add all bytes and leave the result in i64
17869 // chunks, thus directly computes the pop count for v2i64 and v4i64.
17870 if (EltVT == MVT::i64) {
17871 SDValue Zeros = getZeroVector(ByteVecVT, Subtarget, DAG, DL);
17872 V = DAG.getNode(X86ISD::PSADBW, DL, ByteVecVT, V, Zeros);
17873 return DAG.getBitcast(VT, V);
17876 if (EltVT == MVT::i32) {
17877 // We unpack the low half and high half into i32s interleaved with zeros so
17878 // that we can use PSADBW to horizontally sum them. The most useful part of
17879 // this is that it lines up the results of two PSADBW instructions to be
17880 // two v2i64 vectors which concatenated are the 4 population counts. We can
17881 // then use PACKUSWB to shrink and concatenate them into a v4i32 again.
17882 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, DL);
17883 SDValue Low = DAG.getNode(X86ISD::UNPCKL, DL, VT, V, Zeros);
17884 SDValue High = DAG.getNode(X86ISD::UNPCKH, DL, VT, V, Zeros);
17886 // Do the horizontal sums into two v2i64s.
17887 Zeros = getZeroVector(ByteVecVT, Subtarget, DAG, DL);
17888 Low = DAG.getNode(X86ISD::PSADBW, DL, ByteVecVT,
17889 DAG.getBitcast(ByteVecVT, Low), Zeros);
17890 High = DAG.getNode(X86ISD::PSADBW, DL, ByteVecVT,
17891 DAG.getBitcast(ByteVecVT, High), Zeros);
17893 // Merge them together.
17894 MVT ShortVecVT = MVT::getVectorVT(MVT::i16, VecSize / 16);
17895 V = DAG.getNode(X86ISD::PACKUS, DL, ByteVecVT,
17896 DAG.getBitcast(ShortVecVT, Low),
17897 DAG.getBitcast(ShortVecVT, High));
17899 return DAG.getBitcast(VT, V);
17902 // The only element type left is i16.
17903 assert(EltVT == MVT::i16 && "Unknown how to handle type");
17905 // To obtain pop count for each i16 element starting from the pop count for
17906 // i8 elements, shift the i16s left by 8, sum as i8s, and then shift as i16s
17907 // right by 8. It is important to shift as i16s as i8 vector shift isn't
17908 // directly supported.
17909 SmallVector<SDValue, 16> Shifters(NumElts, DAG.getConstant(8, DL, EltVT));
17910 SDValue Shifter = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Shifters);
17911 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, DAG.getBitcast(VT, V), Shifter);
17912 V = DAG.getNode(ISD::ADD, DL, ByteVecVT, DAG.getBitcast(ByteVecVT, Shl),
17913 DAG.getBitcast(ByteVecVT, V));
17914 return DAG.getNode(ISD::SRL, DL, VT, DAG.getBitcast(VT, V), Shifter);
17917 static SDValue LowerVectorCTPOPInRegLUT(SDValue Op, SDLoc DL,
17918 const X86Subtarget *Subtarget,
17919 SelectionDAG &DAG) {
17920 MVT VT = Op.getSimpleValueType();
17921 MVT EltVT = VT.getVectorElementType();
17922 unsigned VecSize = VT.getSizeInBits();
17924 // Implement a lookup table in register by using an algorithm based on:
17925 // http://wm.ite.pl/articles/sse-popcount.html
17927 // The general idea is that every lower byte nibble in the input vector is an
17928 // index into a in-register pre-computed pop count table. We then split up the
17929 // input vector in two new ones: (1) a vector with only the shifted-right
17930 // higher nibbles for each byte and (2) a vector with the lower nibbles (and
17931 // masked out higher ones) for each byte. PSHUB is used separately with both
17932 // to index the in-register table. Next, both are added and the result is a
17933 // i8 vector where each element contains the pop count for input byte.
17935 // To obtain the pop count for elements != i8, we follow up with the same
17936 // approach and use additional tricks as described below.
17938 const int LUT[16] = {/* 0 */ 0, /* 1 */ 1, /* 2 */ 1, /* 3 */ 2,
17939 /* 4 */ 1, /* 5 */ 2, /* 6 */ 2, /* 7 */ 3,
17940 /* 8 */ 1, /* 9 */ 2, /* a */ 2, /* b */ 3,
17941 /* c */ 2, /* d */ 3, /* e */ 3, /* f */ 4};
17943 int NumByteElts = VecSize / 8;
17944 MVT ByteVecVT = MVT::getVectorVT(MVT::i8, NumByteElts);
17945 SDValue In = DAG.getBitcast(ByteVecVT, Op);
17946 SmallVector<SDValue, 16> LUTVec;
17947 for (int i = 0; i < NumByteElts; ++i)
17948 LUTVec.push_back(DAG.getConstant(LUT[i % 16], DL, MVT::i8));
17949 SDValue InRegLUT = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, LUTVec);
17950 SmallVector<SDValue, 16> Mask0F(NumByteElts,
17951 DAG.getConstant(0x0F, DL, MVT::i8));
17952 SDValue M0F = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, Mask0F);
17955 SmallVector<SDValue, 16> Four(NumByteElts, DAG.getConstant(4, DL, MVT::i8));
17956 SDValue FourV = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, Four);
17957 SDValue HighNibbles = DAG.getNode(ISD::SRL, DL, ByteVecVT, In, FourV);
17960 SDValue LowNibbles = DAG.getNode(ISD::AND, DL, ByteVecVT, In, M0F);
17962 // The input vector is used as the shuffle mask that index elements into the
17963 // LUT. After counting low and high nibbles, add the vector to obtain the
17964 // final pop count per i8 element.
17965 SDValue HighPopCnt =
17966 DAG.getNode(X86ISD::PSHUFB, DL, ByteVecVT, InRegLUT, HighNibbles);
17967 SDValue LowPopCnt =
17968 DAG.getNode(X86ISD::PSHUFB, DL, ByteVecVT, InRegLUT, LowNibbles);
17969 SDValue PopCnt = DAG.getNode(ISD::ADD, DL, ByteVecVT, HighPopCnt, LowPopCnt);
17971 if (EltVT == MVT::i8)
17974 return LowerHorizontalByteSum(PopCnt, VT, Subtarget, DAG);
17977 static SDValue LowerVectorCTPOPBitmath(SDValue Op, SDLoc DL,
17978 const X86Subtarget *Subtarget,
17979 SelectionDAG &DAG) {
17980 MVT VT = Op.getSimpleValueType();
17981 assert(VT.is128BitVector() &&
17982 "Only 128-bit vector bitmath lowering supported.");
17984 int VecSize = VT.getSizeInBits();
17985 MVT EltVT = VT.getVectorElementType();
17986 int Len = EltVT.getSizeInBits();
17988 // This is the vectorized version of the "best" algorithm from
17989 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
17990 // with a minor tweak to use a series of adds + shifts instead of vector
17991 // multiplications. Implemented for all integer vector types. We only use
17992 // this when we don't have SSSE3 which allows a LUT-based lowering that is
17993 // much faster, even faster than using native popcnt instructions.
17995 auto GetShift = [&](unsigned OpCode, SDValue V, int Shifter) {
17996 MVT VT = V.getSimpleValueType();
17997 SmallVector<SDValue, 32> Shifters(
17998 VT.getVectorNumElements(),
17999 DAG.getConstant(Shifter, DL, VT.getVectorElementType()));
18000 return DAG.getNode(OpCode, DL, VT, V,
18001 DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Shifters));
18003 auto GetMask = [&](SDValue V, APInt Mask) {
18004 MVT VT = V.getSimpleValueType();
18005 SmallVector<SDValue, 32> Masks(
18006 VT.getVectorNumElements(),
18007 DAG.getConstant(Mask, DL, VT.getVectorElementType()));
18008 return DAG.getNode(ISD::AND, DL, VT, V,
18009 DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Masks));
18012 // We don't want to incur the implicit masks required to SRL vNi8 vectors on
18013 // x86, so set the SRL type to have elements at least i16 wide. This is
18014 // correct because all of our SRLs are followed immediately by a mask anyways
18015 // that handles any bits that sneak into the high bits of the byte elements.
18016 MVT SrlVT = Len > 8 ? VT : MVT::getVectorVT(MVT::i16, VecSize / 16);
18020 // v = v - ((v >> 1) & 0x55555555...)
18022 DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 1));
18023 SDValue And = GetMask(Srl, APInt::getSplat(Len, APInt(8, 0x55)));
18024 V = DAG.getNode(ISD::SUB, DL, VT, V, And);
18026 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
18027 SDValue AndLHS = GetMask(V, APInt::getSplat(Len, APInt(8, 0x33)));
18028 Srl = DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 2));
18029 SDValue AndRHS = GetMask(Srl, APInt::getSplat(Len, APInt(8, 0x33)));
18030 V = DAG.getNode(ISD::ADD, DL, VT, AndLHS, AndRHS);
18032 // v = (v + (v >> 4)) & 0x0F0F0F0F...
18033 Srl = DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 4));
18034 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, V, Srl);
18035 V = GetMask(Add, APInt::getSplat(Len, APInt(8, 0x0F)));
18037 // At this point, V contains the byte-wise population count, and we are
18038 // merely doing a horizontal sum if necessary to get the wider element
18040 if (EltVT == MVT::i8)
18043 return LowerHorizontalByteSum(
18044 DAG.getBitcast(MVT::getVectorVT(MVT::i8, VecSize / 8), V), VT, Subtarget,
18048 static SDValue LowerVectorCTPOP(SDValue Op, const X86Subtarget *Subtarget,
18049 SelectionDAG &DAG) {
18050 MVT VT = Op.getSimpleValueType();
18051 // FIXME: Need to add AVX-512 support here!
18052 assert((VT.is256BitVector() || VT.is128BitVector()) &&
18053 "Unknown CTPOP type to handle");
18054 SDLoc DL(Op.getNode());
18055 SDValue Op0 = Op.getOperand(0);
18057 if (!Subtarget->hasSSSE3()) {
18058 // We can't use the fast LUT approach, so fall back on vectorized bitmath.
18059 assert(VT.is128BitVector() && "Only 128-bit vectors supported in SSE!");
18060 return LowerVectorCTPOPBitmath(Op0, DL, Subtarget, DAG);
18063 if (VT.is256BitVector() && !Subtarget->hasInt256()) {
18064 unsigned NumElems = VT.getVectorNumElements();
18066 // Extract each 128-bit vector, compute pop count and concat the result.
18067 SDValue LHS = Extract128BitVector(Op0, 0, DAG, DL);
18068 SDValue RHS = Extract128BitVector(Op0, NumElems/2, DAG, DL);
18070 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT,
18071 LowerVectorCTPOPInRegLUT(LHS, DL, Subtarget, DAG),
18072 LowerVectorCTPOPInRegLUT(RHS, DL, Subtarget, DAG));
18075 return LowerVectorCTPOPInRegLUT(Op0, DL, Subtarget, DAG);
18078 static SDValue LowerCTPOP(SDValue Op, const X86Subtarget *Subtarget,
18079 SelectionDAG &DAG) {
18080 assert(Op.getValueType().isVector() &&
18081 "We only do custom lowering for vector population count.");
18082 return LowerVectorCTPOP(Op, Subtarget, DAG);
18085 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
18086 SDNode *Node = Op.getNode();
18088 EVT T = Node->getValueType(0);
18089 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
18090 DAG.getConstant(0, dl, T), Node->getOperand(2));
18091 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
18092 cast<AtomicSDNode>(Node)->getMemoryVT(),
18093 Node->getOperand(0),
18094 Node->getOperand(1), negOp,
18095 cast<AtomicSDNode>(Node)->getMemOperand(),
18096 cast<AtomicSDNode>(Node)->getOrdering(),
18097 cast<AtomicSDNode>(Node)->getSynchScope());
18100 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
18101 SDNode *Node = Op.getNode();
18103 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
18105 // Convert seq_cst store -> xchg
18106 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
18107 // FIXME: On 32-bit, store -> fist or movq would be more efficient
18108 // (The only way to get a 16-byte store is cmpxchg16b)
18109 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
18110 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
18111 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
18112 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
18113 cast<AtomicSDNode>(Node)->getMemoryVT(),
18114 Node->getOperand(0),
18115 Node->getOperand(1), Node->getOperand(2),
18116 cast<AtomicSDNode>(Node)->getMemOperand(),
18117 cast<AtomicSDNode>(Node)->getOrdering(),
18118 cast<AtomicSDNode>(Node)->getSynchScope());
18119 return Swap.getValue(1);
18121 // Other atomic stores have a simple pattern.
18125 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
18126 EVT VT = Op.getNode()->getSimpleValueType(0);
18128 // Let legalize expand this if it isn't a legal type yet.
18129 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
18132 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
18135 bool ExtraOp = false;
18136 switch (Op.getOpcode()) {
18137 default: llvm_unreachable("Invalid code");
18138 case ISD::ADDC: Opc = X86ISD::ADD; break;
18139 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
18140 case ISD::SUBC: Opc = X86ISD::SUB; break;
18141 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
18145 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
18147 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
18148 Op.getOperand(1), Op.getOperand(2));
18151 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
18152 SelectionDAG &DAG) {
18153 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
18155 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
18156 // which returns the values as { float, float } (in XMM0) or
18157 // { double, double } (which is returned in XMM0, XMM1).
18159 SDValue Arg = Op.getOperand(0);
18160 EVT ArgVT = Arg.getValueType();
18161 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
18163 TargetLowering::ArgListTy Args;
18164 TargetLowering::ArgListEntry Entry;
18168 Entry.isSExt = false;
18169 Entry.isZExt = false;
18170 Args.push_back(Entry);
18172 bool isF64 = ArgVT == MVT::f64;
18173 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
18174 // the small struct {f32, f32} is returned in (eax, edx). For f64,
18175 // the results are returned via SRet in memory.
18176 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
18177 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18178 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
18180 Type *RetTy = isF64
18181 ? (Type*)StructType::get(ArgTy, ArgTy, nullptr)
18182 : (Type*)VectorType::get(ArgTy, 4);
18184 TargetLowering::CallLoweringInfo CLI(DAG);
18185 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
18186 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
18188 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
18191 // Returned in xmm0 and xmm1.
18192 return CallResult.first;
18194 // Returned in bits 0:31 and 32:64 xmm0.
18195 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
18196 CallResult.first, DAG.getIntPtrConstant(0, dl));
18197 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
18198 CallResult.first, DAG.getIntPtrConstant(1, dl));
18199 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
18200 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
18203 static SDValue LowerMSCATTER(SDValue Op, const X86Subtarget *Subtarget,
18204 SelectionDAG &DAG) {
18205 assert(Subtarget->hasAVX512() &&
18206 "MGATHER/MSCATTER are supported on AVX-512 arch only");
18208 MaskedScatterSDNode *N = cast<MaskedScatterSDNode>(Op.getNode());
18209 EVT VT = N->getValue().getValueType();
18210 assert(VT.getScalarSizeInBits() >= 32 && "Unsupported scatter op");
18213 // X86 scatter kills mask register, so its type should be added to
18214 // the list of return values
18215 if (N->getNumValues() == 1) {
18216 SDValue Index = N->getIndex();
18217 if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
18218 !Index.getValueType().is512BitVector())
18219 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
18221 SDVTList VTs = DAG.getVTList(N->getMask().getValueType(), MVT::Other);
18222 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
18223 N->getOperand(3), Index };
18225 SDValue NewScatter = DAG.getMaskedScatter(VTs, VT, dl, Ops, N->getMemOperand());
18226 DAG.ReplaceAllUsesWith(Op, SDValue(NewScatter.getNode(), 1));
18227 return SDValue(NewScatter.getNode(), 0);
18232 static SDValue LowerMGATHER(SDValue Op, const X86Subtarget *Subtarget,
18233 SelectionDAG &DAG) {
18234 assert(Subtarget->hasAVX512() &&
18235 "MGATHER/MSCATTER are supported on AVX-512 arch only");
18237 MaskedGatherSDNode *N = cast<MaskedGatherSDNode>(Op.getNode());
18238 EVT VT = Op.getValueType();
18239 assert(VT.getScalarSizeInBits() >= 32 && "Unsupported gather op");
18242 SDValue Index = N->getIndex();
18243 if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
18244 !Index.getValueType().is512BitVector()) {
18245 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
18246 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
18247 N->getOperand(3), Index };
18248 DAG.UpdateNodeOperands(N, Ops);
18253 SDValue X86TargetLowering::LowerGC_TRANSITION_START(SDValue Op,
18254 SelectionDAG &DAG) const {
18255 // TODO: Eventually, the lowering of these nodes should be informed by or
18256 // deferred to the GC strategy for the function in which they appear. For
18257 // now, however, they must be lowered to something. Since they are logically
18258 // no-ops in the case of a null GC strategy (or a GC strategy which does not
18259 // require special handling for these nodes), lower them as literal NOOPs for
18261 SmallVector<SDValue, 2> Ops;
18263 Ops.push_back(Op.getOperand(0));
18264 if (Op->getGluedNode())
18265 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
18268 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
18269 SDValue NOOP(DAG.getMachineNode(X86::NOOP, SDLoc(Op), VTs, Ops), 0);
18274 SDValue X86TargetLowering::LowerGC_TRANSITION_END(SDValue Op,
18275 SelectionDAG &DAG) const {
18276 // TODO: Eventually, the lowering of these nodes should be informed by or
18277 // deferred to the GC strategy for the function in which they appear. For
18278 // now, however, they must be lowered to something. Since they are logically
18279 // no-ops in the case of a null GC strategy (or a GC strategy which does not
18280 // require special handling for these nodes), lower them as literal NOOPs for
18282 SmallVector<SDValue, 2> Ops;
18284 Ops.push_back(Op.getOperand(0));
18285 if (Op->getGluedNode())
18286 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
18289 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
18290 SDValue NOOP(DAG.getMachineNode(X86::NOOP, SDLoc(Op), VTs, Ops), 0);
18295 /// LowerOperation - Provide custom lowering hooks for some operations.
18297 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
18298 switch (Op.getOpcode()) {
18299 default: llvm_unreachable("Should not custom lower this!");
18300 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
18301 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
18302 return LowerCMP_SWAP(Op, Subtarget, DAG);
18303 case ISD::CTPOP: return LowerCTPOP(Op, Subtarget, DAG);
18304 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
18305 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
18306 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
18307 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, Subtarget, DAG);
18308 case ISD::VECTOR_SHUFFLE: return lowerVectorShuffle(Op, Subtarget, DAG);
18309 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
18310 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
18311 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
18312 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
18313 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
18314 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
18315 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
18316 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
18317 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
18318 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
18319 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
18320 case ISD::SHL_PARTS:
18321 case ISD::SRA_PARTS:
18322 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
18323 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
18324 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
18325 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
18326 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
18327 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
18328 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
18329 case ISD::SIGN_EXTEND_VECTOR_INREG:
18330 return LowerSIGN_EXTEND_VECTOR_INREG(Op, Subtarget, DAG);
18331 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
18332 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
18333 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
18334 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
18336 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
18337 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
18338 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
18339 case ISD::SETCC: return LowerSETCC(Op, DAG);
18340 case ISD::SELECT: return LowerSELECT(Op, DAG);
18341 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
18342 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
18343 case ISD::VASTART: return LowerVASTART(Op, DAG);
18344 case ISD::VAARG: return LowerVAARG(Op, DAG);
18345 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
18346 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, Subtarget, DAG);
18347 case ISD::INTRINSIC_VOID:
18348 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
18349 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
18350 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
18351 case ISD::FRAME_TO_ARGS_OFFSET:
18352 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
18353 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
18354 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
18355 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
18356 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
18357 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
18358 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
18359 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
18360 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
18361 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
18362 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
18363 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
18364 case ISD::UMUL_LOHI:
18365 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
18368 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
18374 case ISD::UMULO: return LowerXALUO(Op, DAG);
18375 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
18376 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
18380 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
18381 case ISD::ADD: return LowerADD(Op, DAG);
18382 case ISD::SUB: return LowerSUB(Op, DAG);
18383 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
18384 case ISD::MGATHER: return LowerMGATHER(Op, Subtarget, DAG);
18385 case ISD::MSCATTER: return LowerMSCATTER(Op, Subtarget, DAG);
18386 case ISD::GC_TRANSITION_START:
18387 return LowerGC_TRANSITION_START(Op, DAG);
18388 case ISD::GC_TRANSITION_END: return LowerGC_TRANSITION_END(Op, DAG);
18392 /// ReplaceNodeResults - Replace a node with an illegal result type
18393 /// with a new node built out of custom code.
18394 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
18395 SmallVectorImpl<SDValue>&Results,
18396 SelectionDAG &DAG) const {
18398 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18399 switch (N->getOpcode()) {
18401 llvm_unreachable("Do not know how to custom type legalize this operation!");
18402 // We might have generated v2f32 FMIN/FMAX operations. Widen them to v4f32.
18403 case X86ISD::FMINC:
18405 case X86ISD::FMAXC:
18406 case X86ISD::FMAX: {
18407 EVT VT = N->getValueType(0);
18408 if (VT != MVT::v2f32)
18409 llvm_unreachable("Unexpected type (!= v2f32) on FMIN/FMAX.");
18410 SDValue UNDEF = DAG.getUNDEF(VT);
18411 SDValue LHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
18412 N->getOperand(0), UNDEF);
18413 SDValue RHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
18414 N->getOperand(1), UNDEF);
18415 Results.push_back(DAG.getNode(N->getOpcode(), dl, MVT::v4f32, LHS, RHS));
18418 case ISD::SIGN_EXTEND_INREG:
18423 // We don't want to expand or promote these.
18430 case ISD::UDIVREM: {
18431 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
18432 Results.push_back(V);
18435 case ISD::FP_TO_SINT:
18436 // FP_TO_INT*_IN_MEM is not legal for f16 inputs. Do not convert
18437 // (FP_TO_SINT (load f16)) to FP_TO_INT*.
18438 if (N->getOperand(0).getValueType() == MVT::f16)
18441 case ISD::FP_TO_UINT: {
18442 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
18444 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
18447 std::pair<SDValue,SDValue> Vals =
18448 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
18449 SDValue FIST = Vals.first, StackSlot = Vals.second;
18450 if (FIST.getNode()) {
18451 EVT VT = N->getValueType(0);
18452 // Return a load from the stack slot.
18453 if (StackSlot.getNode())
18454 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
18455 MachinePointerInfo(),
18456 false, false, false, 0));
18458 Results.push_back(FIST);
18462 case ISD::UINT_TO_FP: {
18463 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
18464 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
18465 N->getValueType(0) != MVT::v2f32)
18467 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
18469 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
18471 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
18472 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
18473 DAG.getBitcast(MVT::v2i64, VBias));
18474 Or = DAG.getBitcast(MVT::v2f64, Or);
18475 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
18476 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
18479 case ISD::FP_ROUND: {
18480 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
18482 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
18483 Results.push_back(V);
18486 case ISD::FP_EXTEND: {
18487 // Right now, only MVT::v2f32 has OperationAction for FP_EXTEND.
18488 // No other ValueType for FP_EXTEND should reach this point.
18489 assert(N->getValueType(0) == MVT::v2f32 &&
18490 "Do not know how to legalize this Node");
18493 case ISD::INTRINSIC_W_CHAIN: {
18494 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
18496 default : llvm_unreachable("Do not know how to custom type "
18497 "legalize this intrinsic operation!");
18498 case Intrinsic::x86_rdtsc:
18499 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
18501 case Intrinsic::x86_rdtscp:
18502 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
18504 case Intrinsic::x86_rdpmc:
18505 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
18508 case ISD::READCYCLECOUNTER: {
18509 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
18512 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
18513 EVT T = N->getValueType(0);
18514 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
18515 bool Regs64bit = T == MVT::i128;
18516 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
18517 SDValue cpInL, cpInH;
18518 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
18519 DAG.getConstant(0, dl, HalfT));
18520 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
18521 DAG.getConstant(1, dl, HalfT));
18522 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
18523 Regs64bit ? X86::RAX : X86::EAX,
18525 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
18526 Regs64bit ? X86::RDX : X86::EDX,
18527 cpInH, cpInL.getValue(1));
18528 SDValue swapInL, swapInH;
18529 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
18530 DAG.getConstant(0, dl, HalfT));
18531 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
18532 DAG.getConstant(1, dl, HalfT));
18533 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
18534 Regs64bit ? X86::RBX : X86::EBX,
18535 swapInL, cpInH.getValue(1));
18536 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
18537 Regs64bit ? X86::RCX : X86::ECX,
18538 swapInH, swapInL.getValue(1));
18539 SDValue Ops[] = { swapInH.getValue(0),
18541 swapInH.getValue(1) };
18542 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
18543 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
18544 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
18545 X86ISD::LCMPXCHG8_DAG;
18546 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
18547 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
18548 Regs64bit ? X86::RAX : X86::EAX,
18549 HalfT, Result.getValue(1));
18550 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
18551 Regs64bit ? X86::RDX : X86::EDX,
18552 HalfT, cpOutL.getValue(2));
18553 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
18555 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
18556 MVT::i32, cpOutH.getValue(2));
18558 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
18559 DAG.getConstant(X86::COND_E, dl, MVT::i8), EFLAGS);
18560 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
18562 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
18563 Results.push_back(Success);
18564 Results.push_back(EFLAGS.getValue(1));
18567 case ISD::ATOMIC_SWAP:
18568 case ISD::ATOMIC_LOAD_ADD:
18569 case ISD::ATOMIC_LOAD_SUB:
18570 case ISD::ATOMIC_LOAD_AND:
18571 case ISD::ATOMIC_LOAD_OR:
18572 case ISD::ATOMIC_LOAD_XOR:
18573 case ISD::ATOMIC_LOAD_NAND:
18574 case ISD::ATOMIC_LOAD_MIN:
18575 case ISD::ATOMIC_LOAD_MAX:
18576 case ISD::ATOMIC_LOAD_UMIN:
18577 case ISD::ATOMIC_LOAD_UMAX:
18578 case ISD::ATOMIC_LOAD: {
18579 // Delegate to generic TypeLegalization. Situations we can really handle
18580 // should have already been dealt with by AtomicExpandPass.cpp.
18583 case ISD::BITCAST: {
18584 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
18585 EVT DstVT = N->getValueType(0);
18586 EVT SrcVT = N->getOperand(0)->getValueType(0);
18588 if (SrcVT != MVT::f64 ||
18589 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
18592 unsigned NumElts = DstVT.getVectorNumElements();
18593 EVT SVT = DstVT.getVectorElementType();
18594 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
18595 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
18596 MVT::v2f64, N->getOperand(0));
18597 SDValue ToVecInt = DAG.getBitcast(WiderVT, Expanded);
18599 if (ExperimentalVectorWideningLegalization) {
18600 // If we are legalizing vectors by widening, we already have the desired
18601 // legal vector type, just return it.
18602 Results.push_back(ToVecInt);
18606 SmallVector<SDValue, 8> Elts;
18607 for (unsigned i = 0, e = NumElts; i != e; ++i)
18608 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
18609 ToVecInt, DAG.getIntPtrConstant(i, dl)));
18611 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
18616 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
18617 switch ((X86ISD::NodeType)Opcode) {
18618 case X86ISD::FIRST_NUMBER: break;
18619 case X86ISD::BSF: return "X86ISD::BSF";
18620 case X86ISD::BSR: return "X86ISD::BSR";
18621 case X86ISD::SHLD: return "X86ISD::SHLD";
18622 case X86ISD::SHRD: return "X86ISD::SHRD";
18623 case X86ISD::FAND: return "X86ISD::FAND";
18624 case X86ISD::FANDN: return "X86ISD::FANDN";
18625 case X86ISD::FOR: return "X86ISD::FOR";
18626 case X86ISD::FXOR: return "X86ISD::FXOR";
18627 case X86ISD::FILD: return "X86ISD::FILD";
18628 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
18629 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
18630 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
18631 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
18632 case X86ISD::FLD: return "X86ISD::FLD";
18633 case X86ISD::FST: return "X86ISD::FST";
18634 case X86ISD::CALL: return "X86ISD::CALL";
18635 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
18636 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
18637 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
18638 case X86ISD::BT: return "X86ISD::BT";
18639 case X86ISD::CMP: return "X86ISD::CMP";
18640 case X86ISD::COMI: return "X86ISD::COMI";
18641 case X86ISD::UCOMI: return "X86ISD::UCOMI";
18642 case X86ISD::CMPM: return "X86ISD::CMPM";
18643 case X86ISD::CMPMU: return "X86ISD::CMPMU";
18644 case X86ISD::CMPM_RND: return "X86ISD::CMPM_RND";
18645 case X86ISD::SETCC: return "X86ISD::SETCC";
18646 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
18647 case X86ISD::FSETCC: return "X86ISD::FSETCC";
18648 case X86ISD::FGETSIGNx86: return "X86ISD::FGETSIGNx86";
18649 case X86ISD::CMOV: return "X86ISD::CMOV";
18650 case X86ISD::BRCOND: return "X86ISD::BRCOND";
18651 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
18652 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
18653 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
18654 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
18655 case X86ISD::Wrapper: return "X86ISD::Wrapper";
18656 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
18657 case X86ISD::MOVDQ2Q: return "X86ISD::MOVDQ2Q";
18658 case X86ISD::MMX_MOVD2W: return "X86ISD::MMX_MOVD2W";
18659 case X86ISD::MMX_MOVW2D: return "X86ISD::MMX_MOVW2D";
18660 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
18661 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
18662 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
18663 case X86ISD::PINSRB: return "X86ISD::PINSRB";
18664 case X86ISD::PINSRW: return "X86ISD::PINSRW";
18665 case X86ISD::MMX_PINSRW: return "X86ISD::MMX_PINSRW";
18666 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
18667 case X86ISD::ANDNP: return "X86ISD::ANDNP";
18668 case X86ISD::PSIGN: return "X86ISD::PSIGN";
18669 case X86ISD::BLENDI: return "X86ISD::BLENDI";
18670 case X86ISD::SHRUNKBLEND: return "X86ISD::SHRUNKBLEND";
18671 case X86ISD::ADDUS: return "X86ISD::ADDUS";
18672 case X86ISD::SUBUS: return "X86ISD::SUBUS";
18673 case X86ISD::HADD: return "X86ISD::HADD";
18674 case X86ISD::HSUB: return "X86ISD::HSUB";
18675 case X86ISD::FHADD: return "X86ISD::FHADD";
18676 case X86ISD::FHSUB: return "X86ISD::FHSUB";
18677 case X86ISD::ABS: return "X86ISD::ABS";
18678 case X86ISD::FMAX: return "X86ISD::FMAX";
18679 case X86ISD::FMAX_RND: return "X86ISD::FMAX_RND";
18680 case X86ISD::FMIN: return "X86ISD::FMIN";
18681 case X86ISD::FMIN_RND: return "X86ISD::FMIN_RND";
18682 case X86ISD::FMAXC: return "X86ISD::FMAXC";
18683 case X86ISD::FMINC: return "X86ISD::FMINC";
18684 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
18685 case X86ISD::FRCP: return "X86ISD::FRCP";
18686 case X86ISD::EXTRQI: return "X86ISD::EXTRQI";
18687 case X86ISD::INSERTQI: return "X86ISD::INSERTQI";
18688 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
18689 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
18690 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
18691 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
18692 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
18693 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
18694 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
18695 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
18696 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
18697 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
18698 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
18699 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
18700 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
18701 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
18702 case X86ISD::VZEXT: return "X86ISD::VZEXT";
18703 case X86ISD::VSEXT: return "X86ISD::VSEXT";
18704 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
18705 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
18706 case X86ISD::VINSERT: return "X86ISD::VINSERT";
18707 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
18708 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
18709 case X86ISD::CVTDQ2PD: return "X86ISD::CVTDQ2PD";
18710 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
18711 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
18712 case X86ISD::VSHL: return "X86ISD::VSHL";
18713 case X86ISD::VSRL: return "X86ISD::VSRL";
18714 case X86ISD::VSRA: return "X86ISD::VSRA";
18715 case X86ISD::VSHLI: return "X86ISD::VSHLI";
18716 case X86ISD::VSRLI: return "X86ISD::VSRLI";
18717 case X86ISD::VSRAI: return "X86ISD::VSRAI";
18718 case X86ISD::CMPP: return "X86ISD::CMPP";
18719 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
18720 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
18721 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
18722 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
18723 case X86ISD::ADD: return "X86ISD::ADD";
18724 case X86ISD::SUB: return "X86ISD::SUB";
18725 case X86ISD::ADC: return "X86ISD::ADC";
18726 case X86ISD::SBB: return "X86ISD::SBB";
18727 case X86ISD::SMUL: return "X86ISD::SMUL";
18728 case X86ISD::UMUL: return "X86ISD::UMUL";
18729 case X86ISD::SMUL8: return "X86ISD::SMUL8";
18730 case X86ISD::UMUL8: return "X86ISD::UMUL8";
18731 case X86ISD::SDIVREM8_SEXT_HREG: return "X86ISD::SDIVREM8_SEXT_HREG";
18732 case X86ISD::UDIVREM8_ZEXT_HREG: return "X86ISD::UDIVREM8_ZEXT_HREG";
18733 case X86ISD::INC: return "X86ISD::INC";
18734 case X86ISD::DEC: return "X86ISD::DEC";
18735 case X86ISD::OR: return "X86ISD::OR";
18736 case X86ISD::XOR: return "X86ISD::XOR";
18737 case X86ISD::AND: return "X86ISD::AND";
18738 case X86ISD::BEXTR: return "X86ISD::BEXTR";
18739 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
18740 case X86ISD::PTEST: return "X86ISD::PTEST";
18741 case X86ISD::TESTP: return "X86ISD::TESTP";
18742 case X86ISD::TESTM: return "X86ISD::TESTM";
18743 case X86ISD::TESTNM: return "X86ISD::TESTNM";
18744 case X86ISD::KORTEST: return "X86ISD::KORTEST";
18745 case X86ISD::PACKSS: return "X86ISD::PACKSS";
18746 case X86ISD::PACKUS: return "X86ISD::PACKUS";
18747 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
18748 case X86ISD::VALIGN: return "X86ISD::VALIGN";
18749 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
18750 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
18751 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
18752 case X86ISD::SHUFP: return "X86ISD::SHUFP";
18753 case X86ISD::SHUF128: return "X86ISD::SHUF128";
18754 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
18755 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
18756 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
18757 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
18758 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
18759 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
18760 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
18761 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
18762 case X86ISD::MOVSD: return "X86ISD::MOVSD";
18763 case X86ISD::MOVSS: return "X86ISD::MOVSS";
18764 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
18765 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
18766 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
18767 case X86ISD::SUBV_BROADCAST: return "X86ISD::SUBV_BROADCAST";
18768 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
18769 case X86ISD::VPERMILPV: return "X86ISD::VPERMILPV";
18770 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
18771 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
18772 case X86ISD::VPERMV: return "X86ISD::VPERMV";
18773 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
18774 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
18775 case X86ISD::VPERMI: return "X86ISD::VPERMI";
18776 case X86ISD::VFIXUPIMM: return "X86ISD::VFIXUPIMM";
18777 case X86ISD::VRANGE: return "X86ISD::VRANGE";
18778 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
18779 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
18780 case X86ISD::PSADBW: return "X86ISD::PSADBW";
18781 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
18782 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
18783 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
18784 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
18785 case X86ISD::MFENCE: return "X86ISD::MFENCE";
18786 case X86ISD::SFENCE: return "X86ISD::SFENCE";
18787 case X86ISD::LFENCE: return "X86ISD::LFENCE";
18788 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
18789 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
18790 case X86ISD::SAHF: return "X86ISD::SAHF";
18791 case X86ISD::RDRAND: return "X86ISD::RDRAND";
18792 case X86ISD::RDSEED: return "X86ISD::RDSEED";
18793 case X86ISD::FMADD: return "X86ISD::FMADD";
18794 case X86ISD::FMSUB: return "X86ISD::FMSUB";
18795 case X86ISD::FNMADD: return "X86ISD::FNMADD";
18796 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
18797 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
18798 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
18799 case X86ISD::FMADD_RND: return "X86ISD::FMADD_RND";
18800 case X86ISD::FNMADD_RND: return "X86ISD::FNMADD_RND";
18801 case X86ISD::FMSUB_RND: return "X86ISD::FMSUB_RND";
18802 case X86ISD::FNMSUB_RND: return "X86ISD::FNMSUB_RND";
18803 case X86ISD::FMADDSUB_RND: return "X86ISD::FMADDSUB_RND";
18804 case X86ISD::FMSUBADD_RND: return "X86ISD::FMSUBADD_RND";
18805 case X86ISD::RNDSCALE: return "X86ISD::RNDSCALE";
18806 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
18807 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
18808 case X86ISD::XTEST: return "X86ISD::XTEST";
18809 case X86ISD::COMPRESS: return "X86ISD::COMPRESS";
18810 case X86ISD::EXPAND: return "X86ISD::EXPAND";
18811 case X86ISD::SELECT: return "X86ISD::SELECT";
18812 case X86ISD::ADDSUB: return "X86ISD::ADDSUB";
18813 case X86ISD::RCP28: return "X86ISD::RCP28";
18814 case X86ISD::EXP2: return "X86ISD::EXP2";
18815 case X86ISD::RSQRT28: return "X86ISD::RSQRT28";
18816 case X86ISD::FADD_RND: return "X86ISD::FADD_RND";
18817 case X86ISD::FSUB_RND: return "X86ISD::FSUB_RND";
18818 case X86ISD::FMUL_RND: return "X86ISD::FMUL_RND";
18819 case X86ISD::FDIV_RND: return "X86ISD::FDIV_RND";
18820 case X86ISD::FSQRT_RND: return "X86ISD::FSQRT_RND";
18821 case X86ISD::FGETEXP_RND: return "X86ISD::FGETEXP_RND";
18822 case X86ISD::SCALEF: return "X86ISD::SCALEF";
18823 case X86ISD::ADDS: return "X86ISD::ADDS";
18824 case X86ISD::SUBS: return "X86ISD::SUBS";
18825 case X86ISD::AVG: return "X86ISD::AVG";
18826 case X86ISD::MULHRS: return "X86ISD::MULHRS";
18827 case X86ISD::SINT_TO_FP_RND: return "X86ISD::SINT_TO_FP_RND";
18828 case X86ISD::UINT_TO_FP_RND: return "X86ISD::UINT_TO_FP_RND";
18833 // isLegalAddressingMode - Return true if the addressing mode represented
18834 // by AM is legal for this target, for a load/store of the specified type.
18835 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
18837 unsigned AS) const {
18838 // X86 supports extremely general addressing modes.
18839 CodeModel::Model M = getTargetMachine().getCodeModel();
18840 Reloc::Model R = getTargetMachine().getRelocationModel();
18842 // X86 allows a sign-extended 32-bit immediate field as a displacement.
18843 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
18848 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
18850 // If a reference to this global requires an extra load, we can't fold it.
18851 if (isGlobalStubReference(GVFlags))
18854 // If BaseGV requires a register for the PIC base, we cannot also have a
18855 // BaseReg specified.
18856 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
18859 // If lower 4G is not available, then we must use rip-relative addressing.
18860 if ((M != CodeModel::Small || R != Reloc::Static) &&
18861 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
18865 switch (AM.Scale) {
18871 // These scales always work.
18876 // These scales are formed with basereg+scalereg. Only accept if there is
18881 default: // Other stuff never works.
18888 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
18889 unsigned Bits = Ty->getScalarSizeInBits();
18891 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
18892 // particularly cheaper than those without.
18896 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
18897 // variable shifts just as cheap as scalar ones.
18898 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
18901 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
18902 // fully general vector.
18906 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
18907 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
18909 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
18910 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
18911 return NumBits1 > NumBits2;
18914 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
18915 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
18918 if (!isTypeLegal(EVT::getEVT(Ty1)))
18921 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
18923 // Assuming the caller doesn't have a zeroext or signext return parameter,
18924 // truncation all the way down to i1 is valid.
18928 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
18929 return isInt<32>(Imm);
18932 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
18933 // Can also use sub to handle negated immediates.
18934 return isInt<32>(Imm);
18937 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
18938 if (!VT1.isInteger() || !VT2.isInteger())
18940 unsigned NumBits1 = VT1.getSizeInBits();
18941 unsigned NumBits2 = VT2.getSizeInBits();
18942 return NumBits1 > NumBits2;
18945 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
18946 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
18947 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
18950 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
18951 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
18952 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
18955 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
18956 EVT VT1 = Val.getValueType();
18957 if (isZExtFree(VT1, VT2))
18960 if (Val.getOpcode() != ISD::LOAD)
18963 if (!VT1.isSimple() || !VT1.isInteger() ||
18964 !VT2.isSimple() || !VT2.isInteger())
18967 switch (VT1.getSimpleVT().SimpleTy) {
18972 // X86 has 8, 16, and 32-bit zero-extending loads.
18979 bool X86TargetLowering::isVectorLoadExtDesirable(SDValue) const { return true; }
18982 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
18983 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4() || Subtarget->hasAVX512()))
18986 VT = VT.getScalarType();
18988 if (!VT.isSimple())
18991 switch (VT.getSimpleVT().SimpleTy) {
19002 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
19003 // i16 instructions are longer (0x66 prefix) and potentially slower.
19004 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
19007 /// isShuffleMaskLegal - Targets can use this to indicate that they only
19008 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
19009 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
19010 /// are assumed to be legal.
19012 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
19014 if (!VT.isSimple())
19017 // Not for i1 vectors
19018 if (VT.getScalarType() == MVT::i1)
19021 // Very little shuffling can be done for 64-bit vectors right now.
19022 if (VT.getSizeInBits() == 64)
19025 // We only care that the types being shuffled are legal. The lowering can
19026 // handle any possible shuffle mask that results.
19027 return isTypeLegal(VT.getSimpleVT());
19031 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
19033 // Just delegate to the generic legality, clear masks aren't special.
19034 return isShuffleMaskLegal(Mask, VT);
19037 //===----------------------------------------------------------------------===//
19038 // X86 Scheduler Hooks
19039 //===----------------------------------------------------------------------===//
19041 /// Utility function to emit xbegin specifying the start of an RTM region.
19042 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
19043 const TargetInstrInfo *TII) {
19044 DebugLoc DL = MI->getDebugLoc();
19046 const BasicBlock *BB = MBB->getBasicBlock();
19047 MachineFunction::iterator I = MBB;
19050 // For the v = xbegin(), we generate
19061 MachineBasicBlock *thisMBB = MBB;
19062 MachineFunction *MF = MBB->getParent();
19063 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
19064 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
19065 MF->insert(I, mainMBB);
19066 MF->insert(I, sinkMBB);
19068 // Transfer the remainder of BB and its successor edges to sinkMBB.
19069 sinkMBB->splice(sinkMBB->begin(), MBB,
19070 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
19071 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
19075 // # fallthrough to mainMBB
19076 // # abortion to sinkMBB
19077 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
19078 thisMBB->addSuccessor(mainMBB);
19079 thisMBB->addSuccessor(sinkMBB);
19083 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
19084 mainMBB->addSuccessor(sinkMBB);
19087 // EAX is live into the sinkMBB
19088 sinkMBB->addLiveIn(X86::EAX);
19089 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
19090 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
19093 MI->eraseFromParent();
19097 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
19098 // or XMM0_V32I8 in AVX all of this code can be replaced with that
19099 // in the .td file.
19100 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
19101 const TargetInstrInfo *TII) {
19103 switch (MI->getOpcode()) {
19104 default: llvm_unreachable("illegal opcode!");
19105 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
19106 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
19107 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
19108 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
19109 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
19110 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
19111 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
19112 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
19115 DebugLoc dl = MI->getDebugLoc();
19116 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
19118 unsigned NumArgs = MI->getNumOperands();
19119 for (unsigned i = 1; i < NumArgs; ++i) {
19120 MachineOperand &Op = MI->getOperand(i);
19121 if (!(Op.isReg() && Op.isImplicit()))
19122 MIB.addOperand(Op);
19124 if (MI->hasOneMemOperand())
19125 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
19127 BuildMI(*BB, MI, dl,
19128 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
19129 .addReg(X86::XMM0);
19131 MI->eraseFromParent();
19135 // FIXME: Custom handling because TableGen doesn't support multiple implicit
19136 // defs in an instruction pattern
19137 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
19138 const TargetInstrInfo *TII) {
19140 switch (MI->getOpcode()) {
19141 default: llvm_unreachable("illegal opcode!");
19142 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
19143 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
19144 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
19145 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
19146 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
19147 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
19148 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
19149 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
19152 DebugLoc dl = MI->getDebugLoc();
19153 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
19155 unsigned NumArgs = MI->getNumOperands(); // remove the results
19156 for (unsigned i = 1; i < NumArgs; ++i) {
19157 MachineOperand &Op = MI->getOperand(i);
19158 if (!(Op.isReg() && Op.isImplicit()))
19159 MIB.addOperand(Op);
19161 if (MI->hasOneMemOperand())
19162 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
19164 BuildMI(*BB, MI, dl,
19165 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
19168 MI->eraseFromParent();
19172 static MachineBasicBlock *EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
19173 const X86Subtarget *Subtarget) {
19174 DebugLoc dl = MI->getDebugLoc();
19175 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
19176 // Address into RAX/EAX, other two args into ECX, EDX.
19177 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
19178 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
19179 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
19180 for (int i = 0; i < X86::AddrNumOperands; ++i)
19181 MIB.addOperand(MI->getOperand(i));
19183 unsigned ValOps = X86::AddrNumOperands;
19184 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
19185 .addReg(MI->getOperand(ValOps).getReg());
19186 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
19187 .addReg(MI->getOperand(ValOps+1).getReg());
19189 // The instruction doesn't actually take any operands though.
19190 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
19192 MI->eraseFromParent(); // The pseudo is gone now.
19196 MachineBasicBlock *
19197 X86TargetLowering::EmitVAARG64WithCustomInserter(MachineInstr *MI,
19198 MachineBasicBlock *MBB) const {
19199 // Emit va_arg instruction on X86-64.
19201 // Operands to this pseudo-instruction:
19202 // 0 ) Output : destination address (reg)
19203 // 1-5) Input : va_list address (addr, i64mem)
19204 // 6 ) ArgSize : Size (in bytes) of vararg type
19205 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
19206 // 8 ) Align : Alignment of type
19207 // 9 ) EFLAGS (implicit-def)
19209 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
19210 static_assert(X86::AddrNumOperands == 5,
19211 "VAARG_64 assumes 5 address operands");
19213 unsigned DestReg = MI->getOperand(0).getReg();
19214 MachineOperand &Base = MI->getOperand(1);
19215 MachineOperand &Scale = MI->getOperand(2);
19216 MachineOperand &Index = MI->getOperand(3);
19217 MachineOperand &Disp = MI->getOperand(4);
19218 MachineOperand &Segment = MI->getOperand(5);
19219 unsigned ArgSize = MI->getOperand(6).getImm();
19220 unsigned ArgMode = MI->getOperand(7).getImm();
19221 unsigned Align = MI->getOperand(8).getImm();
19223 // Memory Reference
19224 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
19225 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
19226 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
19228 // Machine Information
19229 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
19230 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
19231 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
19232 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
19233 DebugLoc DL = MI->getDebugLoc();
19235 // struct va_list {
19238 // i64 overflow_area (address)
19239 // i64 reg_save_area (address)
19241 // sizeof(va_list) = 24
19242 // alignment(va_list) = 8
19244 unsigned TotalNumIntRegs = 6;
19245 unsigned TotalNumXMMRegs = 8;
19246 bool UseGPOffset = (ArgMode == 1);
19247 bool UseFPOffset = (ArgMode == 2);
19248 unsigned MaxOffset = TotalNumIntRegs * 8 +
19249 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
19251 /* Align ArgSize to a multiple of 8 */
19252 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
19253 bool NeedsAlign = (Align > 8);
19255 MachineBasicBlock *thisMBB = MBB;
19256 MachineBasicBlock *overflowMBB;
19257 MachineBasicBlock *offsetMBB;
19258 MachineBasicBlock *endMBB;
19260 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
19261 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
19262 unsigned OffsetReg = 0;
19264 if (!UseGPOffset && !UseFPOffset) {
19265 // If we only pull from the overflow region, we don't create a branch.
19266 // We don't need to alter control flow.
19267 OffsetDestReg = 0; // unused
19268 OverflowDestReg = DestReg;
19270 offsetMBB = nullptr;
19271 overflowMBB = thisMBB;
19274 // First emit code to check if gp_offset (or fp_offset) is below the bound.
19275 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
19276 // If not, pull from overflow_area. (branch to overflowMBB)
19281 // offsetMBB overflowMBB
19286 // Registers for the PHI in endMBB
19287 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
19288 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
19290 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
19291 MachineFunction *MF = MBB->getParent();
19292 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19293 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19294 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19296 MachineFunction::iterator MBBIter = MBB;
19299 // Insert the new basic blocks
19300 MF->insert(MBBIter, offsetMBB);
19301 MF->insert(MBBIter, overflowMBB);
19302 MF->insert(MBBIter, endMBB);
19304 // Transfer the remainder of MBB and its successor edges to endMBB.
19305 endMBB->splice(endMBB->begin(), thisMBB,
19306 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
19307 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
19309 // Make offsetMBB and overflowMBB successors of thisMBB
19310 thisMBB->addSuccessor(offsetMBB);
19311 thisMBB->addSuccessor(overflowMBB);
19313 // endMBB is a successor of both offsetMBB and overflowMBB
19314 offsetMBB->addSuccessor(endMBB);
19315 overflowMBB->addSuccessor(endMBB);
19317 // Load the offset value into a register
19318 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
19319 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
19323 .addDisp(Disp, UseFPOffset ? 4 : 0)
19324 .addOperand(Segment)
19325 .setMemRefs(MMOBegin, MMOEnd);
19327 // Check if there is enough room left to pull this argument.
19328 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
19330 .addImm(MaxOffset + 8 - ArgSizeA8);
19332 // Branch to "overflowMBB" if offset >= max
19333 // Fall through to "offsetMBB" otherwise
19334 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
19335 .addMBB(overflowMBB);
19338 // In offsetMBB, emit code to use the reg_save_area.
19340 assert(OffsetReg != 0);
19342 // Read the reg_save_area address.
19343 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
19344 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
19349 .addOperand(Segment)
19350 .setMemRefs(MMOBegin, MMOEnd);
19352 // Zero-extend the offset
19353 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
19354 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
19357 .addImm(X86::sub_32bit);
19359 // Add the offset to the reg_save_area to get the final address.
19360 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
19361 .addReg(OffsetReg64)
19362 .addReg(RegSaveReg);
19364 // Compute the offset for the next argument
19365 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
19366 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
19368 .addImm(UseFPOffset ? 16 : 8);
19370 // Store it back into the va_list.
19371 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
19375 .addDisp(Disp, UseFPOffset ? 4 : 0)
19376 .addOperand(Segment)
19377 .addReg(NextOffsetReg)
19378 .setMemRefs(MMOBegin, MMOEnd);
19381 BuildMI(offsetMBB, DL, TII->get(X86::JMP_1))
19386 // Emit code to use overflow area
19389 // Load the overflow_area address into a register.
19390 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
19391 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
19396 .addOperand(Segment)
19397 .setMemRefs(MMOBegin, MMOEnd);
19399 // If we need to align it, do so. Otherwise, just copy the address
19400 // to OverflowDestReg.
19402 // Align the overflow address
19403 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
19404 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
19406 // aligned_addr = (addr + (align-1)) & ~(align-1)
19407 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
19408 .addReg(OverflowAddrReg)
19411 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
19413 .addImm(~(uint64_t)(Align-1));
19415 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
19416 .addReg(OverflowAddrReg);
19419 // Compute the next overflow address after this argument.
19420 // (the overflow address should be kept 8-byte aligned)
19421 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
19422 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
19423 .addReg(OverflowDestReg)
19424 .addImm(ArgSizeA8);
19426 // Store the new overflow address.
19427 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
19432 .addOperand(Segment)
19433 .addReg(NextAddrReg)
19434 .setMemRefs(MMOBegin, MMOEnd);
19436 // If we branched, emit the PHI to the front of endMBB.
19438 BuildMI(*endMBB, endMBB->begin(), DL,
19439 TII->get(X86::PHI), DestReg)
19440 .addReg(OffsetDestReg).addMBB(offsetMBB)
19441 .addReg(OverflowDestReg).addMBB(overflowMBB);
19444 // Erase the pseudo instruction
19445 MI->eraseFromParent();
19450 MachineBasicBlock *
19451 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
19453 MachineBasicBlock *MBB) const {
19454 // Emit code to save XMM registers to the stack. The ABI says that the
19455 // number of registers to save is given in %al, so it's theoretically
19456 // possible to do an indirect jump trick to avoid saving all of them,
19457 // however this code takes a simpler approach and just executes all
19458 // of the stores if %al is non-zero. It's less code, and it's probably
19459 // easier on the hardware branch predictor, and stores aren't all that
19460 // expensive anyway.
19462 // Create the new basic blocks. One block contains all the XMM stores,
19463 // and one block is the final destination regardless of whether any
19464 // stores were performed.
19465 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
19466 MachineFunction *F = MBB->getParent();
19467 MachineFunction::iterator MBBIter = MBB;
19469 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
19470 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
19471 F->insert(MBBIter, XMMSaveMBB);
19472 F->insert(MBBIter, EndMBB);
19474 // Transfer the remainder of MBB and its successor edges to EndMBB.
19475 EndMBB->splice(EndMBB->begin(), MBB,
19476 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
19477 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
19479 // The original block will now fall through to the XMM save block.
19480 MBB->addSuccessor(XMMSaveMBB);
19481 // The XMMSaveMBB will fall through to the end block.
19482 XMMSaveMBB->addSuccessor(EndMBB);
19484 // Now add the instructions.
19485 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
19486 DebugLoc DL = MI->getDebugLoc();
19488 unsigned CountReg = MI->getOperand(0).getReg();
19489 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
19490 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
19492 if (!Subtarget->isTargetWin64()) {
19493 // If %al is 0, branch around the XMM save block.
19494 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
19495 BuildMI(MBB, DL, TII->get(X86::JE_1)).addMBB(EndMBB);
19496 MBB->addSuccessor(EndMBB);
19499 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
19500 // that was just emitted, but clearly shouldn't be "saved".
19501 assert((MI->getNumOperands() <= 3 ||
19502 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
19503 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
19504 && "Expected last argument to be EFLAGS");
19505 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
19506 // In the XMM save block, save all the XMM argument registers.
19507 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
19508 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
19509 MachineMemOperand *MMO =
19510 F->getMachineMemOperand(
19511 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
19512 MachineMemOperand::MOStore,
19513 /*Size=*/16, /*Align=*/16);
19514 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
19515 .addFrameIndex(RegSaveFrameIndex)
19516 .addImm(/*Scale=*/1)
19517 .addReg(/*IndexReg=*/0)
19518 .addImm(/*Disp=*/Offset)
19519 .addReg(/*Segment=*/0)
19520 .addReg(MI->getOperand(i).getReg())
19521 .addMemOperand(MMO);
19524 MI->eraseFromParent(); // The pseudo instruction is gone now.
19529 // The EFLAGS operand of SelectItr might be missing a kill marker
19530 // because there were multiple uses of EFLAGS, and ISel didn't know
19531 // which to mark. Figure out whether SelectItr should have had a
19532 // kill marker, and set it if it should. Returns the correct kill
19534 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
19535 MachineBasicBlock* BB,
19536 const TargetRegisterInfo* TRI) {
19537 // Scan forward through BB for a use/def of EFLAGS.
19538 MachineBasicBlock::iterator miI(std::next(SelectItr));
19539 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
19540 const MachineInstr& mi = *miI;
19541 if (mi.readsRegister(X86::EFLAGS))
19543 if (mi.definesRegister(X86::EFLAGS))
19544 break; // Should have kill-flag - update below.
19547 // If we hit the end of the block, check whether EFLAGS is live into a
19549 if (miI == BB->end()) {
19550 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
19551 sEnd = BB->succ_end();
19552 sItr != sEnd; ++sItr) {
19553 MachineBasicBlock* succ = *sItr;
19554 if (succ->isLiveIn(X86::EFLAGS))
19559 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
19560 // out. SelectMI should have a kill flag on EFLAGS.
19561 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
19565 MachineBasicBlock *
19566 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
19567 MachineBasicBlock *BB) const {
19568 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
19569 DebugLoc DL = MI->getDebugLoc();
19571 // To "insert" a SELECT_CC instruction, we actually have to insert the
19572 // diamond control-flow pattern. The incoming instruction knows the
19573 // destination vreg to set, the condition code register to branch on, the
19574 // true/false values to select between, and a branch opcode to use.
19575 const BasicBlock *LLVM_BB = BB->getBasicBlock();
19576 MachineFunction::iterator It = BB;
19582 // cmpTY ccX, r1, r2
19584 // fallthrough --> copy0MBB
19585 MachineBasicBlock *thisMBB = BB;
19586 MachineFunction *F = BB->getParent();
19588 // We also lower double CMOVs:
19589 // (CMOV (CMOV F, T, cc1), T, cc2)
19590 // to two successives branches. For that, we look for another CMOV as the
19591 // following instruction.
19593 // Without this, we would add a PHI between the two jumps, which ends up
19594 // creating a few copies all around. For instance, for
19596 // (sitofp (zext (fcmp une)))
19598 // we would generate:
19600 // ucomiss %xmm1, %xmm0
19601 // movss <1.0f>, %xmm0
19602 // movaps %xmm0, %xmm1
19604 // xorps %xmm1, %xmm1
19607 // movaps %xmm1, %xmm0
19611 // because this custom-inserter would have generated:
19623 // A: X = ...; Y = ...
19625 // C: Z = PHI [X, A], [Y, B]
19627 // E: PHI [X, C], [Z, D]
19629 // If we lower both CMOVs in a single step, we can instead generate:
19641 // A: X = ...; Y = ...
19643 // E: PHI [X, A], [X, C], [Y, D]
19645 // Which, in our sitofp/fcmp example, gives us something like:
19647 // ucomiss %xmm1, %xmm0
19648 // movss <1.0f>, %xmm0
19651 // xorps %xmm0, %xmm0
19655 MachineInstr *NextCMOV = nullptr;
19656 MachineBasicBlock::iterator NextMIIt =
19657 std::next(MachineBasicBlock::iterator(MI));
19658 if (NextMIIt != BB->end() && NextMIIt->getOpcode() == MI->getOpcode() &&
19659 NextMIIt->getOperand(2).getReg() == MI->getOperand(2).getReg() &&
19660 NextMIIt->getOperand(1).getReg() == MI->getOperand(0).getReg())
19661 NextCMOV = &*NextMIIt;
19663 MachineBasicBlock *jcc1MBB = nullptr;
19665 // If we have a double CMOV, we lower it to two successive branches to
19666 // the same block. EFLAGS is used by both, so mark it as live in the second.
19668 jcc1MBB = F->CreateMachineBasicBlock(LLVM_BB);
19669 F->insert(It, jcc1MBB);
19670 jcc1MBB->addLiveIn(X86::EFLAGS);
19673 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
19674 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
19675 F->insert(It, copy0MBB);
19676 F->insert(It, sinkMBB);
19678 // If the EFLAGS register isn't dead in the terminator, then claim that it's
19679 // live into the sink and copy blocks.
19680 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
19682 MachineInstr *LastEFLAGSUser = NextCMOV ? NextCMOV : MI;
19683 if (!LastEFLAGSUser->killsRegister(X86::EFLAGS) &&
19684 !checkAndUpdateEFLAGSKill(LastEFLAGSUser, BB, TRI)) {
19685 copy0MBB->addLiveIn(X86::EFLAGS);
19686 sinkMBB->addLiveIn(X86::EFLAGS);
19689 // Transfer the remainder of BB and its successor edges to sinkMBB.
19690 sinkMBB->splice(sinkMBB->begin(), BB,
19691 std::next(MachineBasicBlock::iterator(MI)), BB->end());
19692 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
19694 // Add the true and fallthrough blocks as its successors.
19696 // The fallthrough block may be jcc1MBB, if we have a double CMOV.
19697 BB->addSuccessor(jcc1MBB);
19699 // In that case, jcc1MBB will itself fallthrough the copy0MBB, and
19700 // jump to the sinkMBB.
19701 jcc1MBB->addSuccessor(copy0MBB);
19702 jcc1MBB->addSuccessor(sinkMBB);
19704 BB->addSuccessor(copy0MBB);
19707 // The true block target of the first (or only) branch is always sinkMBB.
19708 BB->addSuccessor(sinkMBB);
19710 // Create the conditional branch instruction.
19712 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
19713 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
19716 unsigned Opc2 = X86::GetCondBranchFromCond(
19717 (X86::CondCode)NextCMOV->getOperand(3).getImm());
19718 BuildMI(jcc1MBB, DL, TII->get(Opc2)).addMBB(sinkMBB);
19722 // %FalseValue = ...
19723 // # fallthrough to sinkMBB
19724 copy0MBB->addSuccessor(sinkMBB);
19727 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
19729 MachineInstrBuilder MIB =
19730 BuildMI(*sinkMBB, sinkMBB->begin(), DL, TII->get(X86::PHI),
19731 MI->getOperand(0).getReg())
19732 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
19733 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
19735 // If we have a double CMOV, the second Jcc provides the same incoming
19736 // value as the first Jcc (the True operand of the SELECT_CC/CMOV nodes).
19738 MIB.addReg(MI->getOperand(2).getReg()).addMBB(jcc1MBB);
19739 // Copy the PHI result to the register defined by the second CMOV.
19740 BuildMI(*sinkMBB, std::next(MachineBasicBlock::iterator(MIB.getInstr())),
19741 DL, TII->get(TargetOpcode::COPY), NextCMOV->getOperand(0).getReg())
19742 .addReg(MI->getOperand(0).getReg());
19743 NextCMOV->eraseFromParent();
19746 MI->eraseFromParent(); // The pseudo instruction is gone now.
19750 MachineBasicBlock *
19751 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
19752 MachineBasicBlock *BB) const {
19753 MachineFunction *MF = BB->getParent();
19754 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
19755 DebugLoc DL = MI->getDebugLoc();
19756 const BasicBlock *LLVM_BB = BB->getBasicBlock();
19758 assert(MF->shouldSplitStack());
19760 const bool Is64Bit = Subtarget->is64Bit();
19761 const bool IsLP64 = Subtarget->isTarget64BitLP64();
19763 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
19764 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
19767 // ... [Till the alloca]
19768 // If stacklet is not large enough, jump to mallocMBB
19771 // Allocate by subtracting from RSP
19772 // Jump to continueMBB
19775 // Allocate by call to runtime
19779 // [rest of original BB]
19782 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19783 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19784 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19786 MachineRegisterInfo &MRI = MF->getRegInfo();
19787 const TargetRegisterClass *AddrRegClass =
19788 getRegClassFor(getPointerTy());
19790 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
19791 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
19792 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
19793 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
19794 sizeVReg = MI->getOperand(1).getReg(),
19795 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
19797 MachineFunction::iterator MBBIter = BB;
19800 MF->insert(MBBIter, bumpMBB);
19801 MF->insert(MBBIter, mallocMBB);
19802 MF->insert(MBBIter, continueMBB);
19804 continueMBB->splice(continueMBB->begin(), BB,
19805 std::next(MachineBasicBlock::iterator(MI)), BB->end());
19806 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
19808 // Add code to the main basic block to check if the stack limit has been hit,
19809 // and if so, jump to mallocMBB otherwise to bumpMBB.
19810 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
19811 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
19812 .addReg(tmpSPVReg).addReg(sizeVReg);
19813 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
19814 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
19815 .addReg(SPLimitVReg);
19816 BuildMI(BB, DL, TII->get(X86::JG_1)).addMBB(mallocMBB);
19818 // bumpMBB simply decreases the stack pointer, since we know the current
19819 // stacklet has enough space.
19820 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
19821 .addReg(SPLimitVReg);
19822 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
19823 .addReg(SPLimitVReg);
19824 BuildMI(bumpMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
19826 // Calls into a routine in libgcc to allocate more space from the heap.
19827 const uint32_t *RegMask =
19828 Subtarget->getRegisterInfo()->getCallPreservedMask(*MF, CallingConv::C);
19830 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
19832 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
19833 .addExternalSymbol("__morestack_allocate_stack_space")
19834 .addRegMask(RegMask)
19835 .addReg(X86::RDI, RegState::Implicit)
19836 .addReg(X86::RAX, RegState::ImplicitDefine);
19837 } else if (Is64Bit) {
19838 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
19840 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
19841 .addExternalSymbol("__morestack_allocate_stack_space")
19842 .addRegMask(RegMask)
19843 .addReg(X86::EDI, RegState::Implicit)
19844 .addReg(X86::EAX, RegState::ImplicitDefine);
19846 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
19848 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
19849 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
19850 .addExternalSymbol("__morestack_allocate_stack_space")
19851 .addRegMask(RegMask)
19852 .addReg(X86::EAX, RegState::ImplicitDefine);
19856 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
19859 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
19860 .addReg(IsLP64 ? X86::RAX : X86::EAX);
19861 BuildMI(mallocMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
19863 // Set up the CFG correctly.
19864 BB->addSuccessor(bumpMBB);
19865 BB->addSuccessor(mallocMBB);
19866 mallocMBB->addSuccessor(continueMBB);
19867 bumpMBB->addSuccessor(continueMBB);
19869 // Take care of the PHI nodes.
19870 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
19871 MI->getOperand(0).getReg())
19872 .addReg(mallocPtrVReg).addMBB(mallocMBB)
19873 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
19875 // Delete the original pseudo instruction.
19876 MI->eraseFromParent();
19879 return continueMBB;
19882 MachineBasicBlock *
19883 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
19884 MachineBasicBlock *BB) const {
19885 DebugLoc DL = MI->getDebugLoc();
19887 assert(!Subtarget->isTargetMachO());
19889 Subtarget->getFrameLowering()->emitStackProbeCall(*BB->getParent(), *BB, MI,
19892 MI->eraseFromParent(); // The pseudo instruction is gone now.
19896 MachineBasicBlock *
19897 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
19898 MachineBasicBlock *BB) const {
19899 // This is pretty easy. We're taking the value that we received from
19900 // our load from the relocation, sticking it in either RDI (x86-64)
19901 // or EAX and doing an indirect call. The return value will then
19902 // be in the normal return register.
19903 MachineFunction *F = BB->getParent();
19904 const X86InstrInfo *TII = Subtarget->getInstrInfo();
19905 DebugLoc DL = MI->getDebugLoc();
19907 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
19908 assert(MI->getOperand(3).isGlobal() && "This should be a global");
19910 // Get a register mask for the lowered call.
19911 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
19912 // proper register mask.
19913 const uint32_t *RegMask =
19914 Subtarget->getRegisterInfo()->getCallPreservedMask(*F, CallingConv::C);
19915 if (Subtarget->is64Bit()) {
19916 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19917 TII->get(X86::MOV64rm), X86::RDI)
19919 .addImm(0).addReg(0)
19920 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
19921 MI->getOperand(3).getTargetFlags())
19923 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
19924 addDirectMem(MIB, X86::RDI);
19925 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
19926 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
19927 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19928 TII->get(X86::MOV32rm), X86::EAX)
19930 .addImm(0).addReg(0)
19931 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
19932 MI->getOperand(3).getTargetFlags())
19934 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
19935 addDirectMem(MIB, X86::EAX);
19936 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
19938 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19939 TII->get(X86::MOV32rm), X86::EAX)
19940 .addReg(TII->getGlobalBaseReg(F))
19941 .addImm(0).addReg(0)
19942 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
19943 MI->getOperand(3).getTargetFlags())
19945 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
19946 addDirectMem(MIB, X86::EAX);
19947 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
19950 MI->eraseFromParent(); // The pseudo instruction is gone now.
19954 MachineBasicBlock *
19955 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
19956 MachineBasicBlock *MBB) const {
19957 DebugLoc DL = MI->getDebugLoc();
19958 MachineFunction *MF = MBB->getParent();
19959 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
19960 MachineRegisterInfo &MRI = MF->getRegInfo();
19962 const BasicBlock *BB = MBB->getBasicBlock();
19963 MachineFunction::iterator I = MBB;
19966 // Memory Reference
19967 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
19968 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
19971 unsigned MemOpndSlot = 0;
19973 unsigned CurOp = 0;
19975 DstReg = MI->getOperand(CurOp++).getReg();
19976 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
19977 assert(RC->hasType(MVT::i32) && "Invalid destination!");
19978 unsigned mainDstReg = MRI.createVirtualRegister(RC);
19979 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
19981 MemOpndSlot = CurOp;
19983 MVT PVT = getPointerTy();
19984 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
19985 "Invalid Pointer Size!");
19987 // For v = setjmp(buf), we generate
19990 // buf[LabelOffset] = restoreMBB
19991 // SjLjSetup restoreMBB
19997 // v = phi(main, restore)
20000 // if base pointer being used, load it from frame
20003 MachineBasicBlock *thisMBB = MBB;
20004 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
20005 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
20006 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
20007 MF->insert(I, mainMBB);
20008 MF->insert(I, sinkMBB);
20009 MF->push_back(restoreMBB);
20011 MachineInstrBuilder MIB;
20013 // Transfer the remainder of BB and its successor edges to sinkMBB.
20014 sinkMBB->splice(sinkMBB->begin(), MBB,
20015 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20016 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
20019 unsigned PtrStoreOpc = 0;
20020 unsigned LabelReg = 0;
20021 const int64_t LabelOffset = 1 * PVT.getStoreSize();
20022 Reloc::Model RM = MF->getTarget().getRelocationModel();
20023 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
20024 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
20026 // Prepare IP either in reg or imm.
20027 if (!UseImmLabel) {
20028 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
20029 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
20030 LabelReg = MRI.createVirtualRegister(PtrRC);
20031 if (Subtarget->is64Bit()) {
20032 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
20036 .addMBB(restoreMBB)
20039 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
20040 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
20041 .addReg(XII->getGlobalBaseReg(MF))
20044 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
20048 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
20050 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
20051 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
20052 if (i == X86::AddrDisp)
20053 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
20055 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
20058 MIB.addReg(LabelReg);
20060 MIB.addMBB(restoreMBB);
20061 MIB.setMemRefs(MMOBegin, MMOEnd);
20063 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
20064 .addMBB(restoreMBB);
20066 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
20067 MIB.addRegMask(RegInfo->getNoPreservedMask());
20068 thisMBB->addSuccessor(mainMBB);
20069 thisMBB->addSuccessor(restoreMBB);
20073 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
20074 mainMBB->addSuccessor(sinkMBB);
20077 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20078 TII->get(X86::PHI), DstReg)
20079 .addReg(mainDstReg).addMBB(mainMBB)
20080 .addReg(restoreDstReg).addMBB(restoreMBB);
20083 if (RegInfo->hasBasePointer(*MF)) {
20084 const bool Uses64BitFramePtr =
20085 Subtarget->isTarget64BitLP64() || Subtarget->isTargetNaCl64();
20086 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
20087 X86FI->setRestoreBasePointer(MF);
20088 unsigned FramePtr = RegInfo->getFrameRegister(*MF);
20089 unsigned BasePtr = RegInfo->getBaseRegister();
20090 unsigned Opm = Uses64BitFramePtr ? X86::MOV64rm : X86::MOV32rm;
20091 addRegOffset(BuildMI(restoreMBB, DL, TII->get(Opm), BasePtr),
20092 FramePtr, true, X86FI->getRestoreBasePointerOffset())
20093 .setMIFlag(MachineInstr::FrameSetup);
20095 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
20096 BuildMI(restoreMBB, DL, TII->get(X86::JMP_1)).addMBB(sinkMBB);
20097 restoreMBB->addSuccessor(sinkMBB);
20099 MI->eraseFromParent();
20103 MachineBasicBlock *
20104 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
20105 MachineBasicBlock *MBB) const {
20106 DebugLoc DL = MI->getDebugLoc();
20107 MachineFunction *MF = MBB->getParent();
20108 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20109 MachineRegisterInfo &MRI = MF->getRegInfo();
20111 // Memory Reference
20112 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20113 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20115 MVT PVT = getPointerTy();
20116 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
20117 "Invalid Pointer Size!");
20119 const TargetRegisterClass *RC =
20120 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
20121 unsigned Tmp = MRI.createVirtualRegister(RC);
20122 // Since FP is only updated here but NOT referenced, it's treated as GPR.
20123 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
20124 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
20125 unsigned SP = RegInfo->getStackRegister();
20127 MachineInstrBuilder MIB;
20129 const int64_t LabelOffset = 1 * PVT.getStoreSize();
20130 const int64_t SPOffset = 2 * PVT.getStoreSize();
20132 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
20133 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
20136 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
20137 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
20138 MIB.addOperand(MI->getOperand(i));
20139 MIB.setMemRefs(MMOBegin, MMOEnd);
20141 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
20142 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
20143 if (i == X86::AddrDisp)
20144 MIB.addDisp(MI->getOperand(i), LabelOffset);
20146 MIB.addOperand(MI->getOperand(i));
20148 MIB.setMemRefs(MMOBegin, MMOEnd);
20150 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
20151 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
20152 if (i == X86::AddrDisp)
20153 MIB.addDisp(MI->getOperand(i), SPOffset);
20155 MIB.addOperand(MI->getOperand(i));
20157 MIB.setMemRefs(MMOBegin, MMOEnd);
20159 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
20161 MI->eraseFromParent();
20165 // Replace 213-type (isel default) FMA3 instructions with 231-type for
20166 // accumulator loops. Writing back to the accumulator allows the coalescer
20167 // to remove extra copies in the loop.
20168 // FIXME: Do this on AVX512. We don't support 231 variants yet (PR23937).
20169 MachineBasicBlock *
20170 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
20171 MachineBasicBlock *MBB) const {
20172 MachineOperand &AddendOp = MI->getOperand(3);
20174 // Bail out early if the addend isn't a register - we can't switch these.
20175 if (!AddendOp.isReg())
20178 MachineFunction &MF = *MBB->getParent();
20179 MachineRegisterInfo &MRI = MF.getRegInfo();
20181 // Check whether the addend is defined by a PHI:
20182 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
20183 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
20184 if (!AddendDef.isPHI())
20187 // Look for the following pattern:
20189 // %addend = phi [%entry, 0], [%loop, %result]
20191 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
20195 // %addend = phi [%entry, 0], [%loop, %result]
20197 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
20199 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
20200 assert(AddendDef.getOperand(i).isReg());
20201 MachineOperand PHISrcOp = AddendDef.getOperand(i);
20202 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
20203 if (&PHISrcInst == MI) {
20204 // Found a matching instruction.
20205 unsigned NewFMAOpc = 0;
20206 switch (MI->getOpcode()) {
20207 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
20208 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
20209 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
20210 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
20211 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
20212 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
20213 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
20214 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
20215 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
20216 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
20217 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
20218 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
20219 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
20220 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
20221 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
20222 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
20223 case X86::VFMADDSUBPDr213r: NewFMAOpc = X86::VFMADDSUBPDr231r; break;
20224 case X86::VFMADDSUBPSr213r: NewFMAOpc = X86::VFMADDSUBPSr231r; break;
20225 case X86::VFMSUBADDPDr213r: NewFMAOpc = X86::VFMSUBADDPDr231r; break;
20226 case X86::VFMSUBADDPSr213r: NewFMAOpc = X86::VFMSUBADDPSr231r; break;
20228 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
20229 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
20230 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
20231 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
20232 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
20233 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
20234 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
20235 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
20236 case X86::VFMADDSUBPDr213rY: NewFMAOpc = X86::VFMADDSUBPDr231rY; break;
20237 case X86::VFMADDSUBPSr213rY: NewFMAOpc = X86::VFMADDSUBPSr231rY; break;
20238 case X86::VFMSUBADDPDr213rY: NewFMAOpc = X86::VFMSUBADDPDr231rY; break;
20239 case X86::VFMSUBADDPSr213rY: NewFMAOpc = X86::VFMSUBADDPSr231rY; break;
20240 default: llvm_unreachable("Unrecognized FMA variant.");
20243 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
20244 MachineInstrBuilder MIB =
20245 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
20246 .addOperand(MI->getOperand(0))
20247 .addOperand(MI->getOperand(3))
20248 .addOperand(MI->getOperand(2))
20249 .addOperand(MI->getOperand(1));
20250 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
20251 MI->eraseFromParent();
20258 MachineBasicBlock *
20259 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
20260 MachineBasicBlock *BB) const {
20261 switch (MI->getOpcode()) {
20262 default: llvm_unreachable("Unexpected instr type to insert");
20263 case X86::TAILJMPd64:
20264 case X86::TAILJMPr64:
20265 case X86::TAILJMPm64:
20266 case X86::TAILJMPd64_REX:
20267 case X86::TAILJMPr64_REX:
20268 case X86::TAILJMPm64_REX:
20269 llvm_unreachable("TAILJMP64 would not be touched here.");
20270 case X86::TCRETURNdi64:
20271 case X86::TCRETURNri64:
20272 case X86::TCRETURNmi64:
20274 case X86::WIN_ALLOCA:
20275 return EmitLoweredWinAlloca(MI, BB);
20276 case X86::SEG_ALLOCA_32:
20277 case X86::SEG_ALLOCA_64:
20278 return EmitLoweredSegAlloca(MI, BB);
20279 case X86::TLSCall_32:
20280 case X86::TLSCall_64:
20281 return EmitLoweredTLSCall(MI, BB);
20282 case X86::CMOV_GR8:
20283 case X86::CMOV_FR32:
20284 case X86::CMOV_FR64:
20285 case X86::CMOV_V4F32:
20286 case X86::CMOV_V2F64:
20287 case X86::CMOV_V2I64:
20288 case X86::CMOV_V8F32:
20289 case X86::CMOV_V4F64:
20290 case X86::CMOV_V4I64:
20291 case X86::CMOV_V16F32:
20292 case X86::CMOV_V8F64:
20293 case X86::CMOV_V8I64:
20294 case X86::CMOV_GR16:
20295 case X86::CMOV_GR32:
20296 case X86::CMOV_RFP32:
20297 case X86::CMOV_RFP64:
20298 case X86::CMOV_RFP80:
20299 case X86::CMOV_V8I1:
20300 case X86::CMOV_V16I1:
20301 case X86::CMOV_V32I1:
20302 case X86::CMOV_V64I1:
20303 return EmitLoweredSelect(MI, BB);
20305 case X86::FP32_TO_INT16_IN_MEM:
20306 case X86::FP32_TO_INT32_IN_MEM:
20307 case X86::FP32_TO_INT64_IN_MEM:
20308 case X86::FP64_TO_INT16_IN_MEM:
20309 case X86::FP64_TO_INT32_IN_MEM:
20310 case X86::FP64_TO_INT64_IN_MEM:
20311 case X86::FP80_TO_INT16_IN_MEM:
20312 case X86::FP80_TO_INT32_IN_MEM:
20313 case X86::FP80_TO_INT64_IN_MEM: {
20314 MachineFunction *F = BB->getParent();
20315 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20316 DebugLoc DL = MI->getDebugLoc();
20318 // Change the floating point control register to use "round towards zero"
20319 // mode when truncating to an integer value.
20320 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
20321 addFrameReference(BuildMI(*BB, MI, DL,
20322 TII->get(X86::FNSTCW16m)), CWFrameIdx);
20324 // Load the old value of the high byte of the control word...
20326 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
20327 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
20330 // Set the high part to be round to zero...
20331 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
20334 // Reload the modified control word now...
20335 addFrameReference(BuildMI(*BB, MI, DL,
20336 TII->get(X86::FLDCW16m)), CWFrameIdx);
20338 // Restore the memory image of control word to original value
20339 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
20342 // Get the X86 opcode to use.
20344 switch (MI->getOpcode()) {
20345 default: llvm_unreachable("illegal opcode!");
20346 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
20347 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
20348 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
20349 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
20350 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
20351 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
20352 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
20353 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
20354 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
20358 MachineOperand &Op = MI->getOperand(0);
20360 AM.BaseType = X86AddressMode::RegBase;
20361 AM.Base.Reg = Op.getReg();
20363 AM.BaseType = X86AddressMode::FrameIndexBase;
20364 AM.Base.FrameIndex = Op.getIndex();
20366 Op = MI->getOperand(1);
20368 AM.Scale = Op.getImm();
20369 Op = MI->getOperand(2);
20371 AM.IndexReg = Op.getImm();
20372 Op = MI->getOperand(3);
20373 if (Op.isGlobal()) {
20374 AM.GV = Op.getGlobal();
20376 AM.Disp = Op.getImm();
20378 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
20379 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
20381 // Reload the original control word now.
20382 addFrameReference(BuildMI(*BB, MI, DL,
20383 TII->get(X86::FLDCW16m)), CWFrameIdx);
20385 MI->eraseFromParent(); // The pseudo instruction is gone now.
20388 // String/text processing lowering.
20389 case X86::PCMPISTRM128REG:
20390 case X86::VPCMPISTRM128REG:
20391 case X86::PCMPISTRM128MEM:
20392 case X86::VPCMPISTRM128MEM:
20393 case X86::PCMPESTRM128REG:
20394 case X86::VPCMPESTRM128REG:
20395 case X86::PCMPESTRM128MEM:
20396 case X86::VPCMPESTRM128MEM:
20397 assert(Subtarget->hasSSE42() &&
20398 "Target must have SSE4.2 or AVX features enabled");
20399 return EmitPCMPSTRM(MI, BB, Subtarget->getInstrInfo());
20401 // String/text processing lowering.
20402 case X86::PCMPISTRIREG:
20403 case X86::VPCMPISTRIREG:
20404 case X86::PCMPISTRIMEM:
20405 case X86::VPCMPISTRIMEM:
20406 case X86::PCMPESTRIREG:
20407 case X86::VPCMPESTRIREG:
20408 case X86::PCMPESTRIMEM:
20409 case X86::VPCMPESTRIMEM:
20410 assert(Subtarget->hasSSE42() &&
20411 "Target must have SSE4.2 or AVX features enabled");
20412 return EmitPCMPSTRI(MI, BB, Subtarget->getInstrInfo());
20414 // Thread synchronization.
20416 return EmitMonitor(MI, BB, Subtarget);
20420 return EmitXBegin(MI, BB, Subtarget->getInstrInfo());
20422 case X86::VASTART_SAVE_XMM_REGS:
20423 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
20425 case X86::VAARG_64:
20426 return EmitVAARG64WithCustomInserter(MI, BB);
20428 case X86::EH_SjLj_SetJmp32:
20429 case X86::EH_SjLj_SetJmp64:
20430 return emitEHSjLjSetJmp(MI, BB);
20432 case X86::EH_SjLj_LongJmp32:
20433 case X86::EH_SjLj_LongJmp64:
20434 return emitEHSjLjLongJmp(MI, BB);
20436 case TargetOpcode::STATEPOINT:
20437 // As an implementation detail, STATEPOINT shares the STACKMAP format at
20438 // this point in the process. We diverge later.
20439 return emitPatchPoint(MI, BB);
20441 case TargetOpcode::STACKMAP:
20442 case TargetOpcode::PATCHPOINT:
20443 return emitPatchPoint(MI, BB);
20445 case X86::VFMADDPDr213r:
20446 case X86::VFMADDPSr213r:
20447 case X86::VFMADDSDr213r:
20448 case X86::VFMADDSSr213r:
20449 case X86::VFMSUBPDr213r:
20450 case X86::VFMSUBPSr213r:
20451 case X86::VFMSUBSDr213r:
20452 case X86::VFMSUBSSr213r:
20453 case X86::VFNMADDPDr213r:
20454 case X86::VFNMADDPSr213r:
20455 case X86::VFNMADDSDr213r:
20456 case X86::VFNMADDSSr213r:
20457 case X86::VFNMSUBPDr213r:
20458 case X86::VFNMSUBPSr213r:
20459 case X86::VFNMSUBSDr213r:
20460 case X86::VFNMSUBSSr213r:
20461 case X86::VFMADDSUBPDr213r:
20462 case X86::VFMADDSUBPSr213r:
20463 case X86::VFMSUBADDPDr213r:
20464 case X86::VFMSUBADDPSr213r:
20465 case X86::VFMADDPDr213rY:
20466 case X86::VFMADDPSr213rY:
20467 case X86::VFMSUBPDr213rY:
20468 case X86::VFMSUBPSr213rY:
20469 case X86::VFNMADDPDr213rY:
20470 case X86::VFNMADDPSr213rY:
20471 case X86::VFNMSUBPDr213rY:
20472 case X86::VFNMSUBPSr213rY:
20473 case X86::VFMADDSUBPDr213rY:
20474 case X86::VFMADDSUBPSr213rY:
20475 case X86::VFMSUBADDPDr213rY:
20476 case X86::VFMSUBADDPSr213rY:
20477 return emitFMA3Instr(MI, BB);
20481 //===----------------------------------------------------------------------===//
20482 // X86 Optimization Hooks
20483 //===----------------------------------------------------------------------===//
20485 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
20488 const SelectionDAG &DAG,
20489 unsigned Depth) const {
20490 unsigned BitWidth = KnownZero.getBitWidth();
20491 unsigned Opc = Op.getOpcode();
20492 assert((Opc >= ISD::BUILTIN_OP_END ||
20493 Opc == ISD::INTRINSIC_WO_CHAIN ||
20494 Opc == ISD::INTRINSIC_W_CHAIN ||
20495 Opc == ISD::INTRINSIC_VOID) &&
20496 "Should use MaskedValueIsZero if you don't know whether Op"
20497 " is a target node!");
20499 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
20513 // These nodes' second result is a boolean.
20514 if (Op.getResNo() == 0)
20517 case X86ISD::SETCC:
20518 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
20520 case ISD::INTRINSIC_WO_CHAIN: {
20521 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
20522 unsigned NumLoBits = 0;
20525 case Intrinsic::x86_sse_movmsk_ps:
20526 case Intrinsic::x86_avx_movmsk_ps_256:
20527 case Intrinsic::x86_sse2_movmsk_pd:
20528 case Intrinsic::x86_avx_movmsk_pd_256:
20529 case Intrinsic::x86_mmx_pmovmskb:
20530 case Intrinsic::x86_sse2_pmovmskb_128:
20531 case Intrinsic::x86_avx2_pmovmskb: {
20532 // High bits of movmskp{s|d}, pmovmskb are known zero.
20534 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
20535 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
20536 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
20537 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
20538 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
20539 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
20540 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
20541 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
20543 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
20552 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
20554 const SelectionDAG &,
20555 unsigned Depth) const {
20556 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
20557 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
20558 return Op.getValueType().getScalarType().getSizeInBits();
20564 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
20565 /// node is a GlobalAddress + offset.
20566 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
20567 const GlobalValue* &GA,
20568 int64_t &Offset) const {
20569 if (N->getOpcode() == X86ISD::Wrapper) {
20570 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
20571 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
20572 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
20576 return TargetLowering::isGAPlusOffset(N, GA, Offset);
20579 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
20580 /// same as extracting the high 128-bit part of 256-bit vector and then
20581 /// inserting the result into the low part of a new 256-bit vector
20582 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
20583 EVT VT = SVOp->getValueType(0);
20584 unsigned NumElems = VT.getVectorNumElements();
20586 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
20587 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
20588 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
20589 SVOp->getMaskElt(j) >= 0)
20595 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
20596 /// same as extracting the low 128-bit part of 256-bit vector and then
20597 /// inserting the result into the high part of a new 256-bit vector
20598 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
20599 EVT VT = SVOp->getValueType(0);
20600 unsigned NumElems = VT.getVectorNumElements();
20602 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
20603 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
20604 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
20605 SVOp->getMaskElt(j) >= 0)
20611 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
20612 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
20613 TargetLowering::DAGCombinerInfo &DCI,
20614 const X86Subtarget* Subtarget) {
20616 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
20617 SDValue V1 = SVOp->getOperand(0);
20618 SDValue V2 = SVOp->getOperand(1);
20619 EVT VT = SVOp->getValueType(0);
20620 unsigned NumElems = VT.getVectorNumElements();
20622 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
20623 V2.getOpcode() == ISD::CONCAT_VECTORS) {
20627 // V UNDEF BUILD_VECTOR UNDEF
20629 // CONCAT_VECTOR CONCAT_VECTOR
20632 // RESULT: V + zero extended
20634 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
20635 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
20636 V1.getOperand(1).getOpcode() != ISD::UNDEF)
20639 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
20642 // To match the shuffle mask, the first half of the mask should
20643 // be exactly the first vector, and all the rest a splat with the
20644 // first element of the second one.
20645 for (unsigned i = 0; i != NumElems/2; ++i)
20646 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
20647 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
20650 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
20651 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
20652 if (Ld->hasNUsesOfValue(1, 0)) {
20653 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
20654 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
20656 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
20658 Ld->getPointerInfo(),
20659 Ld->getAlignment(),
20660 false/*isVolatile*/, true/*ReadMem*/,
20661 false/*WriteMem*/);
20663 // Make sure the newly-created LOAD is in the same position as Ld in
20664 // terms of dependency. We create a TokenFactor for Ld and ResNode,
20665 // and update uses of Ld's output chain to use the TokenFactor.
20666 if (Ld->hasAnyUseOfValue(1)) {
20667 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
20668 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
20669 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
20670 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
20671 SDValue(ResNode.getNode(), 1));
20674 return DAG.getBitcast(VT, ResNode);
20678 // Emit a zeroed vector and insert the desired subvector on its
20680 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
20681 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
20682 return DCI.CombineTo(N, InsV);
20685 //===--------------------------------------------------------------------===//
20686 // Combine some shuffles into subvector extracts and inserts:
20689 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
20690 if (isShuffleHigh128VectorInsertLow(SVOp)) {
20691 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
20692 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
20693 return DCI.CombineTo(N, InsV);
20696 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
20697 if (isShuffleLow128VectorInsertHigh(SVOp)) {
20698 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
20699 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
20700 return DCI.CombineTo(N, InsV);
20706 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
20709 /// This is the leaf of the recursive combinine below. When we have found some
20710 /// chain of single-use x86 shuffle instructions and accumulated the combined
20711 /// shuffle mask represented by them, this will try to pattern match that mask
20712 /// into either a single instruction if there is a special purpose instruction
20713 /// for this operation, or into a PSHUFB instruction which is a fully general
20714 /// instruction but should only be used to replace chains over a certain depth.
20715 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
20716 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
20717 TargetLowering::DAGCombinerInfo &DCI,
20718 const X86Subtarget *Subtarget) {
20719 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
20721 // Find the operand that enters the chain. Note that multiple uses are OK
20722 // here, we're not going to remove the operand we find.
20723 SDValue Input = Op.getOperand(0);
20724 while (Input.getOpcode() == ISD::BITCAST)
20725 Input = Input.getOperand(0);
20727 MVT VT = Input.getSimpleValueType();
20728 MVT RootVT = Root.getSimpleValueType();
20731 // Just remove no-op shuffle masks.
20732 if (Mask.size() == 1) {
20733 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Input),
20738 // Use the float domain if the operand type is a floating point type.
20739 bool FloatDomain = VT.isFloatingPoint();
20741 // For floating point shuffles, we don't have free copies in the shuffle
20742 // instructions or the ability to load as part of the instruction, so
20743 // canonicalize their shuffles to UNPCK or MOV variants.
20745 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
20746 // vectors because it can have a load folded into it that UNPCK cannot. This
20747 // doesn't preclude something switching to the shorter encoding post-RA.
20749 // FIXME: Should teach these routines about AVX vector widths.
20750 if (FloatDomain && VT.getSizeInBits() == 128) {
20751 if (Mask.equals({0, 0}) || Mask.equals({1, 1})) {
20752 bool Lo = Mask.equals({0, 0});
20755 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
20756 // is no slower than UNPCKLPD but has the option to fold the input operand
20757 // into even an unaligned memory load.
20758 if (Lo && Subtarget->hasSSE3()) {
20759 Shuffle = X86ISD::MOVDDUP;
20760 ShuffleVT = MVT::v2f64;
20762 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
20763 // than the UNPCK variants.
20764 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
20765 ShuffleVT = MVT::v4f32;
20767 if (Depth == 1 && Root->getOpcode() == Shuffle)
20768 return false; // Nothing to do!
20769 Op = DAG.getBitcast(ShuffleVT, Input);
20770 DCI.AddToWorklist(Op.getNode());
20771 if (Shuffle == X86ISD::MOVDDUP)
20772 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
20774 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20775 DCI.AddToWorklist(Op.getNode());
20776 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
20780 if (Subtarget->hasSSE3() &&
20781 (Mask.equals({0, 0, 2, 2}) || Mask.equals({1, 1, 3, 3}))) {
20782 bool Lo = Mask.equals({0, 0, 2, 2});
20783 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
20784 MVT ShuffleVT = MVT::v4f32;
20785 if (Depth == 1 && Root->getOpcode() == Shuffle)
20786 return false; // Nothing to do!
20787 Op = DAG.getBitcast(ShuffleVT, Input);
20788 DCI.AddToWorklist(Op.getNode());
20789 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
20790 DCI.AddToWorklist(Op.getNode());
20791 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
20795 if (Mask.equals({0, 0, 1, 1}) || Mask.equals({2, 2, 3, 3})) {
20796 bool Lo = Mask.equals({0, 0, 1, 1});
20797 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
20798 MVT ShuffleVT = MVT::v4f32;
20799 if (Depth == 1 && Root->getOpcode() == Shuffle)
20800 return false; // Nothing to do!
20801 Op = DAG.getBitcast(ShuffleVT, Input);
20802 DCI.AddToWorklist(Op.getNode());
20803 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20804 DCI.AddToWorklist(Op.getNode());
20805 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
20811 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
20812 // variants as none of these have single-instruction variants that are
20813 // superior to the UNPCK formulation.
20814 if (!FloatDomain && VT.getSizeInBits() == 128 &&
20815 (Mask.equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
20816 Mask.equals({4, 4, 5, 5, 6, 6, 7, 7}) ||
20817 Mask.equals({0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7}) ||
20819 {8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}))) {
20820 bool Lo = Mask[0] == 0;
20821 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
20822 if (Depth == 1 && Root->getOpcode() == Shuffle)
20823 return false; // Nothing to do!
20825 switch (Mask.size()) {
20827 ShuffleVT = MVT::v8i16;
20830 ShuffleVT = MVT::v16i8;
20833 llvm_unreachable("Impossible mask size!");
20835 Op = DAG.getBitcast(ShuffleVT, Input);
20836 DCI.AddToWorklist(Op.getNode());
20837 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20838 DCI.AddToWorklist(Op.getNode());
20839 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
20844 // Don't try to re-form single instruction chains under any circumstances now
20845 // that we've done encoding canonicalization for them.
20849 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
20850 // can replace them with a single PSHUFB instruction profitably. Intel's
20851 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
20852 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
20853 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
20854 SmallVector<SDValue, 16> PSHUFBMask;
20855 int NumBytes = VT.getSizeInBits() / 8;
20856 int Ratio = NumBytes / Mask.size();
20857 for (int i = 0; i < NumBytes; ++i) {
20858 if (Mask[i / Ratio] == SM_SentinelUndef) {
20859 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
20862 int M = Mask[i / Ratio] != SM_SentinelZero
20863 ? Ratio * Mask[i / Ratio] + i % Ratio
20865 PSHUFBMask.push_back(DAG.getConstant(M, DL, MVT::i8));
20867 MVT ByteVT = MVT::getVectorVT(MVT::i8, NumBytes);
20868 Op = DAG.getBitcast(ByteVT, Input);
20869 DCI.AddToWorklist(Op.getNode());
20870 SDValue PSHUFBMaskOp =
20871 DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVT, PSHUFBMask);
20872 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
20873 Op = DAG.getNode(X86ISD::PSHUFB, DL, ByteVT, Op, PSHUFBMaskOp);
20874 DCI.AddToWorklist(Op.getNode());
20875 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
20880 // Failed to find any combines.
20884 /// \brief Fully generic combining of x86 shuffle instructions.
20886 /// This should be the last combine run over the x86 shuffle instructions. Once
20887 /// they have been fully optimized, this will recursively consider all chains
20888 /// of single-use shuffle instructions, build a generic model of the cumulative
20889 /// shuffle operation, and check for simpler instructions which implement this
20890 /// operation. We use this primarily for two purposes:
20892 /// 1) Collapse generic shuffles to specialized single instructions when
20893 /// equivalent. In most cases, this is just an encoding size win, but
20894 /// sometimes we will collapse multiple generic shuffles into a single
20895 /// special-purpose shuffle.
20896 /// 2) Look for sequences of shuffle instructions with 3 or more total
20897 /// instructions, and replace them with the slightly more expensive SSSE3
20898 /// PSHUFB instruction if available. We do this as the last combining step
20899 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
20900 /// a suitable short sequence of other instructions. The PHUFB will either
20901 /// use a register or have to read from memory and so is slightly (but only
20902 /// slightly) more expensive than the other shuffle instructions.
20904 /// Because this is inherently a quadratic operation (for each shuffle in
20905 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
20906 /// This should never be an issue in practice as the shuffle lowering doesn't
20907 /// produce sequences of more than 8 instructions.
20909 /// FIXME: We will currently miss some cases where the redundant shuffling
20910 /// would simplify under the threshold for PSHUFB formation because of
20911 /// combine-ordering. To fix this, we should do the redundant instruction
20912 /// combining in this recursive walk.
20913 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
20914 ArrayRef<int> RootMask,
20915 int Depth, bool HasPSHUFB,
20917 TargetLowering::DAGCombinerInfo &DCI,
20918 const X86Subtarget *Subtarget) {
20919 // Bound the depth of our recursive combine because this is ultimately
20920 // quadratic in nature.
20924 // Directly rip through bitcasts to find the underlying operand.
20925 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
20926 Op = Op.getOperand(0);
20928 MVT VT = Op.getSimpleValueType();
20929 if (!VT.isVector())
20930 return false; // Bail if we hit a non-vector.
20932 assert(Root.getSimpleValueType().isVector() &&
20933 "Shuffles operate on vector types!");
20934 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
20935 "Can only combine shuffles of the same vector register size.");
20937 if (!isTargetShuffle(Op.getOpcode()))
20939 SmallVector<int, 16> OpMask;
20941 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
20942 // We only can combine unary shuffles which we can decode the mask for.
20943 if (!HaveMask || !IsUnary)
20946 assert(VT.getVectorNumElements() == OpMask.size() &&
20947 "Different mask size from vector size!");
20948 assert(((RootMask.size() > OpMask.size() &&
20949 RootMask.size() % OpMask.size() == 0) ||
20950 (OpMask.size() > RootMask.size() &&
20951 OpMask.size() % RootMask.size() == 0) ||
20952 OpMask.size() == RootMask.size()) &&
20953 "The smaller number of elements must divide the larger.");
20954 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
20955 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
20956 assert(((RootRatio == 1 && OpRatio == 1) ||
20957 (RootRatio == 1) != (OpRatio == 1)) &&
20958 "Must not have a ratio for both incoming and op masks!");
20960 SmallVector<int, 16> Mask;
20961 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
20963 // Merge this shuffle operation's mask into our accumulated mask. Note that
20964 // this shuffle's mask will be the first applied to the input, followed by the
20965 // root mask to get us all the way to the root value arrangement. The reason
20966 // for this order is that we are recursing up the operation chain.
20967 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
20968 int RootIdx = i / RootRatio;
20969 if (RootMask[RootIdx] < 0) {
20970 // This is a zero or undef lane, we're done.
20971 Mask.push_back(RootMask[RootIdx]);
20975 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
20976 int OpIdx = RootMaskedIdx / OpRatio;
20977 if (OpMask[OpIdx] < 0) {
20978 // The incoming lanes are zero or undef, it doesn't matter which ones we
20980 Mask.push_back(OpMask[OpIdx]);
20984 // Ok, we have non-zero lanes, map them through.
20985 Mask.push_back(OpMask[OpIdx] * OpRatio +
20986 RootMaskedIdx % OpRatio);
20989 // See if we can recurse into the operand to combine more things.
20990 switch (Op.getOpcode()) {
20991 case X86ISD::PSHUFB:
20993 case X86ISD::PSHUFD:
20994 case X86ISD::PSHUFHW:
20995 case X86ISD::PSHUFLW:
20996 if (Op.getOperand(0).hasOneUse() &&
20997 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
20998 HasPSHUFB, DAG, DCI, Subtarget))
21002 case X86ISD::UNPCKL:
21003 case X86ISD::UNPCKH:
21004 assert(Op.getOperand(0) == Op.getOperand(1) && "We only combine unary shuffles!");
21005 // We can't check for single use, we have to check that this shuffle is the only user.
21006 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
21007 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
21008 HasPSHUFB, DAG, DCI, Subtarget))
21013 // Minor canonicalization of the accumulated shuffle mask to make it easier
21014 // to match below. All this does is detect masks with squential pairs of
21015 // elements, and shrink them to the half-width mask. It does this in a loop
21016 // so it will reduce the size of the mask to the minimal width mask which
21017 // performs an equivalent shuffle.
21018 SmallVector<int, 16> WidenedMask;
21019 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
21020 Mask = std::move(WidenedMask);
21021 WidenedMask.clear();
21024 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
21028 /// \brief Get the PSHUF-style mask from PSHUF node.
21030 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
21031 /// PSHUF-style masks that can be reused with such instructions.
21032 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
21033 MVT VT = N.getSimpleValueType();
21034 SmallVector<int, 4> Mask;
21036 bool HaveMask = getTargetShuffleMask(N.getNode(), VT, Mask, IsUnary);
21040 // If we have more than 128-bits, only the low 128-bits of shuffle mask
21041 // matter. Check that the upper masks are repeats and remove them.
21042 if (VT.getSizeInBits() > 128) {
21043 int LaneElts = 128 / VT.getScalarSizeInBits();
21045 for (int i = 1, NumLanes = VT.getSizeInBits() / 128; i < NumLanes; ++i)
21046 for (int j = 0; j < LaneElts; ++j)
21047 assert(Mask[j] == Mask[i * LaneElts + j] - (LaneElts * i) &&
21048 "Mask doesn't repeat in high 128-bit lanes!");
21050 Mask.resize(LaneElts);
21053 switch (N.getOpcode()) {
21054 case X86ISD::PSHUFD:
21056 case X86ISD::PSHUFLW:
21059 case X86ISD::PSHUFHW:
21060 Mask.erase(Mask.begin(), Mask.begin() + 4);
21061 for (int &M : Mask)
21065 llvm_unreachable("No valid shuffle instruction found!");
21069 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
21071 /// We walk up the chain and look for a combinable shuffle, skipping over
21072 /// shuffles that we could hoist this shuffle's transformation past without
21073 /// altering anything.
21075 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
21077 TargetLowering::DAGCombinerInfo &DCI) {
21078 assert(N.getOpcode() == X86ISD::PSHUFD &&
21079 "Called with something other than an x86 128-bit half shuffle!");
21082 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
21083 // of the shuffles in the chain so that we can form a fresh chain to replace
21085 SmallVector<SDValue, 8> Chain;
21086 SDValue V = N.getOperand(0);
21087 for (; V.hasOneUse(); V = V.getOperand(0)) {
21088 switch (V.getOpcode()) {
21090 return SDValue(); // Nothing combined!
21093 // Skip bitcasts as we always know the type for the target specific
21097 case X86ISD::PSHUFD:
21098 // Found another dword shuffle.
21101 case X86ISD::PSHUFLW:
21102 // Check that the low words (being shuffled) are the identity in the
21103 // dword shuffle, and the high words are self-contained.
21104 if (Mask[0] != 0 || Mask[1] != 1 ||
21105 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
21108 Chain.push_back(V);
21111 case X86ISD::PSHUFHW:
21112 // Check that the high words (being shuffled) are the identity in the
21113 // dword shuffle, and the low words are self-contained.
21114 if (Mask[2] != 2 || Mask[3] != 3 ||
21115 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
21118 Chain.push_back(V);
21121 case X86ISD::UNPCKL:
21122 case X86ISD::UNPCKH:
21123 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
21124 // shuffle into a preceding word shuffle.
21125 if (V.getSimpleValueType().getScalarType() != MVT::i8 &&
21126 V.getSimpleValueType().getScalarType() != MVT::i16)
21129 // Search for a half-shuffle which we can combine with.
21130 unsigned CombineOp =
21131 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
21132 if (V.getOperand(0) != V.getOperand(1) ||
21133 !V->isOnlyUserOf(V.getOperand(0).getNode()))
21135 Chain.push_back(V);
21136 V = V.getOperand(0);
21138 switch (V.getOpcode()) {
21140 return SDValue(); // Nothing to combine.
21142 case X86ISD::PSHUFLW:
21143 case X86ISD::PSHUFHW:
21144 if (V.getOpcode() == CombineOp)
21147 Chain.push_back(V);
21151 V = V.getOperand(0);
21155 } while (V.hasOneUse());
21158 // Break out of the loop if we break out of the switch.
21162 if (!V.hasOneUse())
21163 // We fell out of the loop without finding a viable combining instruction.
21166 // Merge this node's mask and our incoming mask.
21167 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
21168 for (int &M : Mask)
21170 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
21171 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
21173 // Rebuild the chain around this new shuffle.
21174 while (!Chain.empty()) {
21175 SDValue W = Chain.pop_back_val();
21177 if (V.getValueType() != W.getOperand(0).getValueType())
21178 V = DAG.getBitcast(W.getOperand(0).getValueType(), V);
21180 switch (W.getOpcode()) {
21182 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
21184 case X86ISD::UNPCKL:
21185 case X86ISD::UNPCKH:
21186 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
21189 case X86ISD::PSHUFD:
21190 case X86ISD::PSHUFLW:
21191 case X86ISD::PSHUFHW:
21192 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
21196 if (V.getValueType() != N.getValueType())
21197 V = DAG.getBitcast(N.getValueType(), V);
21199 // Return the new chain to replace N.
21203 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
21205 /// We walk up the chain, skipping shuffles of the other half and looking
21206 /// through shuffles which switch halves trying to find a shuffle of the same
21207 /// pair of dwords.
21208 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
21210 TargetLowering::DAGCombinerInfo &DCI) {
21212 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
21213 "Called with something other than an x86 128-bit half shuffle!");
21215 unsigned CombineOpcode = N.getOpcode();
21217 // Walk up a single-use chain looking for a combinable shuffle.
21218 SDValue V = N.getOperand(0);
21219 for (; V.hasOneUse(); V = V.getOperand(0)) {
21220 switch (V.getOpcode()) {
21222 return false; // Nothing combined!
21225 // Skip bitcasts as we always know the type for the target specific
21229 case X86ISD::PSHUFLW:
21230 case X86ISD::PSHUFHW:
21231 if (V.getOpcode() == CombineOpcode)
21234 // Other-half shuffles are no-ops.
21237 // Break out of the loop if we break out of the switch.
21241 if (!V.hasOneUse())
21242 // We fell out of the loop without finding a viable combining instruction.
21245 // Combine away the bottom node as its shuffle will be accumulated into
21246 // a preceding shuffle.
21247 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
21249 // Record the old value.
21252 // Merge this node's mask and our incoming mask (adjusted to account for all
21253 // the pshufd instructions encountered).
21254 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
21255 for (int &M : Mask)
21257 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
21258 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
21260 // Check that the shuffles didn't cancel each other out. If not, we need to
21261 // combine to the new one.
21263 // Replace the combinable shuffle with the combined one, updating all users
21264 // so that we re-evaluate the chain here.
21265 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
21270 /// \brief Try to combine x86 target specific shuffles.
21271 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
21272 TargetLowering::DAGCombinerInfo &DCI,
21273 const X86Subtarget *Subtarget) {
21275 MVT VT = N.getSimpleValueType();
21276 SmallVector<int, 4> Mask;
21278 switch (N.getOpcode()) {
21279 case X86ISD::PSHUFD:
21280 case X86ISD::PSHUFLW:
21281 case X86ISD::PSHUFHW:
21282 Mask = getPSHUFShuffleMask(N);
21283 assert(Mask.size() == 4);
21289 // Nuke no-op shuffles that show up after combining.
21290 if (isNoopShuffleMask(Mask))
21291 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
21293 // Look for simplifications involving one or two shuffle instructions.
21294 SDValue V = N.getOperand(0);
21295 switch (N.getOpcode()) {
21298 case X86ISD::PSHUFLW:
21299 case X86ISD::PSHUFHW:
21300 assert(VT.getScalarType() == MVT::i16 && "Bad word shuffle type!");
21302 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
21303 return SDValue(); // We combined away this shuffle, so we're done.
21305 // See if this reduces to a PSHUFD which is no more expensive and can
21306 // combine with more operations. Note that it has to at least flip the
21307 // dwords as otherwise it would have been removed as a no-op.
21308 if (makeArrayRef(Mask).equals({2, 3, 0, 1})) {
21309 int DMask[] = {0, 1, 2, 3};
21310 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
21311 DMask[DOffset + 0] = DOffset + 1;
21312 DMask[DOffset + 1] = DOffset + 0;
21313 MVT DVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
21314 V = DAG.getBitcast(DVT, V);
21315 DCI.AddToWorklist(V.getNode());
21316 V = DAG.getNode(X86ISD::PSHUFD, DL, DVT, V,
21317 getV4X86ShuffleImm8ForMask(DMask, DL, DAG));
21318 DCI.AddToWorklist(V.getNode());
21319 return DAG.getBitcast(VT, V);
21322 // Look for shuffle patterns which can be implemented as a single unpack.
21323 // FIXME: This doesn't handle the location of the PSHUFD generically, and
21324 // only works when we have a PSHUFD followed by two half-shuffles.
21325 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
21326 (V.getOpcode() == X86ISD::PSHUFLW ||
21327 V.getOpcode() == X86ISD::PSHUFHW) &&
21328 V.getOpcode() != N.getOpcode() &&
21330 SDValue D = V.getOperand(0);
21331 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
21332 D = D.getOperand(0);
21333 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
21334 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
21335 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
21336 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
21337 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
21339 for (int i = 0; i < 4; ++i) {
21340 WordMask[i + NOffset] = Mask[i] + NOffset;
21341 WordMask[i + VOffset] = VMask[i] + VOffset;
21343 // Map the word mask through the DWord mask.
21345 for (int i = 0; i < 8; ++i)
21346 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
21347 if (makeArrayRef(MappedMask).equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
21348 makeArrayRef(MappedMask).equals({4, 4, 5, 5, 6, 6, 7, 7})) {
21349 // We can replace all three shuffles with an unpack.
21350 V = DAG.getBitcast(VT, D.getOperand(0));
21351 DCI.AddToWorklist(V.getNode());
21352 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
21361 case X86ISD::PSHUFD:
21362 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
21371 /// \brief Try to combine a shuffle into a target-specific add-sub node.
21373 /// We combine this directly on the abstract vector shuffle nodes so it is
21374 /// easier to generically match. We also insert dummy vector shuffle nodes for
21375 /// the operands which explicitly discard the lanes which are unused by this
21376 /// operation to try to flow through the rest of the combiner the fact that
21377 /// they're unused.
21378 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
21380 EVT VT = N->getValueType(0);
21382 // We only handle target-independent shuffles.
21383 // FIXME: It would be easy and harmless to use the target shuffle mask
21384 // extraction tool to support more.
21385 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
21388 auto *SVN = cast<ShuffleVectorSDNode>(N);
21389 ArrayRef<int> Mask = SVN->getMask();
21390 SDValue V1 = N->getOperand(0);
21391 SDValue V2 = N->getOperand(1);
21393 // We require the first shuffle operand to be the SUB node, and the second to
21394 // be the ADD node.
21395 // FIXME: We should support the commuted patterns.
21396 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
21399 // If there are other uses of these operations we can't fold them.
21400 if (!V1->hasOneUse() || !V2->hasOneUse())
21403 // Ensure that both operations have the same operands. Note that we can
21404 // commute the FADD operands.
21405 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
21406 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
21407 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
21410 // We're looking for blends between FADD and FSUB nodes. We insist on these
21411 // nodes being lined up in a specific expected pattern.
21412 if (!(isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
21413 isShuffleEquivalent(V1, V2, Mask, {0, 5, 2, 7}) ||
21414 isShuffleEquivalent(V1, V2, Mask, {0, 9, 2, 11, 4, 13, 6, 15})))
21417 // Only specific types are legal at this point, assert so we notice if and
21418 // when these change.
21419 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
21420 VT == MVT::v4f64) &&
21421 "Unknown vector type encountered!");
21423 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
21426 /// PerformShuffleCombine - Performs several different shuffle combines.
21427 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
21428 TargetLowering::DAGCombinerInfo &DCI,
21429 const X86Subtarget *Subtarget) {
21431 SDValue N0 = N->getOperand(0);
21432 SDValue N1 = N->getOperand(1);
21433 EVT VT = N->getValueType(0);
21435 // Don't create instructions with illegal types after legalize types has run.
21436 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21437 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
21440 // If we have legalized the vector types, look for blends of FADD and FSUB
21441 // nodes that we can fuse into an ADDSUB node.
21442 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
21443 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
21446 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
21447 if (Subtarget->hasFp256() && VT.is256BitVector() &&
21448 N->getOpcode() == ISD::VECTOR_SHUFFLE)
21449 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
21451 // During Type Legalization, when promoting illegal vector types,
21452 // the backend might introduce new shuffle dag nodes and bitcasts.
21454 // This code performs the following transformation:
21455 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
21456 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
21458 // We do this only if both the bitcast and the BINOP dag nodes have
21459 // one use. Also, perform this transformation only if the new binary
21460 // operation is legal. This is to avoid introducing dag nodes that
21461 // potentially need to be further expanded (or custom lowered) into a
21462 // less optimal sequence of dag nodes.
21463 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
21464 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
21465 N0.getOpcode() == ISD::BITCAST) {
21466 SDValue BC0 = N0.getOperand(0);
21467 EVT SVT = BC0.getValueType();
21468 unsigned Opcode = BC0.getOpcode();
21469 unsigned NumElts = VT.getVectorNumElements();
21471 if (BC0.hasOneUse() && SVT.isVector() &&
21472 SVT.getVectorNumElements() * 2 == NumElts &&
21473 TLI.isOperationLegal(Opcode, VT)) {
21474 bool CanFold = false;
21486 unsigned SVTNumElts = SVT.getVectorNumElements();
21487 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
21488 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
21489 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
21490 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
21491 CanFold = SVOp->getMaskElt(i) < 0;
21494 SDValue BC00 = DAG.getBitcast(VT, BC0.getOperand(0));
21495 SDValue BC01 = DAG.getBitcast(VT, BC0.getOperand(1));
21496 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
21497 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
21502 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
21503 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
21504 // consecutive, non-overlapping, and in the right order.
21505 SmallVector<SDValue, 16> Elts;
21506 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
21507 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
21509 if (SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true))
21512 if (isTargetShuffle(N->getOpcode())) {
21514 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
21515 if (Shuffle.getNode())
21518 // Try recursively combining arbitrary sequences of x86 shuffle
21519 // instructions into higher-order shuffles. We do this after combining
21520 // specific PSHUF instruction sequences into their minimal form so that we
21521 // can evaluate how many specialized shuffle instructions are involved in
21522 // a particular chain.
21523 SmallVector<int, 1> NonceMask; // Just a placeholder.
21524 NonceMask.push_back(0);
21525 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
21526 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
21528 return SDValue(); // This routine will use CombineTo to replace N.
21534 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
21535 /// specific shuffle of a load can be folded into a single element load.
21536 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
21537 /// shuffles have been custom lowered so we need to handle those here.
21538 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
21539 TargetLowering::DAGCombinerInfo &DCI) {
21540 if (DCI.isBeforeLegalizeOps())
21543 SDValue InVec = N->getOperand(0);
21544 SDValue EltNo = N->getOperand(1);
21546 if (!isa<ConstantSDNode>(EltNo))
21549 EVT OriginalVT = InVec.getValueType();
21551 if (InVec.getOpcode() == ISD::BITCAST) {
21552 // Don't duplicate a load with other uses.
21553 if (!InVec.hasOneUse())
21555 EVT BCVT = InVec.getOperand(0).getValueType();
21556 if (!BCVT.isVector() ||
21557 BCVT.getVectorNumElements() != OriginalVT.getVectorNumElements())
21559 InVec = InVec.getOperand(0);
21562 EVT CurrentVT = InVec.getValueType();
21564 if (!isTargetShuffle(InVec.getOpcode()))
21567 // Don't duplicate a load with other uses.
21568 if (!InVec.hasOneUse())
21571 SmallVector<int, 16> ShuffleMask;
21573 if (!getTargetShuffleMask(InVec.getNode(), CurrentVT.getSimpleVT(),
21574 ShuffleMask, UnaryShuffle))
21577 // Select the input vector, guarding against out of range extract vector.
21578 unsigned NumElems = CurrentVT.getVectorNumElements();
21579 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
21580 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
21581 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
21582 : InVec.getOperand(1);
21584 // If inputs to shuffle are the same for both ops, then allow 2 uses
21585 unsigned AllowedUses = InVec.getNumOperands() > 1 &&
21586 InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
21588 if (LdNode.getOpcode() == ISD::BITCAST) {
21589 // Don't duplicate a load with other uses.
21590 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
21593 AllowedUses = 1; // only allow 1 load use if we have a bitcast
21594 LdNode = LdNode.getOperand(0);
21597 if (!ISD::isNormalLoad(LdNode.getNode()))
21600 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
21602 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
21605 EVT EltVT = N->getValueType(0);
21606 // If there's a bitcast before the shuffle, check if the load type and
21607 // alignment is valid.
21608 unsigned Align = LN0->getAlignment();
21609 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21610 unsigned NewAlign = TLI.getDataLayout()->getABITypeAlignment(
21611 EltVT.getTypeForEVT(*DAG.getContext()));
21613 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
21616 // All checks match so transform back to vector_shuffle so that DAG combiner
21617 // can finish the job
21620 // Create shuffle node taking into account the case that its a unary shuffle
21621 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(CurrentVT)
21622 : InVec.getOperand(1);
21623 Shuffle = DAG.getVectorShuffle(CurrentVT, dl,
21624 InVec.getOperand(0), Shuffle,
21626 Shuffle = DAG.getBitcast(OriginalVT, Shuffle);
21627 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
21631 /// \brief Detect bitcasts between i32 to x86mmx low word. Since MMX types are
21632 /// special and don't usually play with other vector types, it's better to
21633 /// handle them early to be sure we emit efficient code by avoiding
21634 /// store-load conversions.
21635 static SDValue PerformBITCASTCombine(SDNode *N, SelectionDAG &DAG) {
21636 if (N->getValueType(0) != MVT::x86mmx ||
21637 N->getOperand(0)->getOpcode() != ISD::BUILD_VECTOR ||
21638 N->getOperand(0)->getValueType(0) != MVT::v2i32)
21641 SDValue V = N->getOperand(0);
21642 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V.getOperand(1));
21643 if (C && C->getZExtValue() == 0 && V.getOperand(0).getValueType() == MVT::i32)
21644 return DAG.getNode(X86ISD::MMX_MOVW2D, SDLoc(V.getOperand(0)),
21645 N->getValueType(0), V.getOperand(0));
21650 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
21651 /// generation and convert it from being a bunch of shuffles and extracts
21652 /// into a somewhat faster sequence. For i686, the best sequence is apparently
21653 /// storing the value and loading scalars back, while for x64 we should
21654 /// use 64-bit extracts and shifts.
21655 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
21656 TargetLowering::DAGCombinerInfo &DCI) {
21657 if (SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI))
21660 SDValue InputVector = N->getOperand(0);
21661 SDLoc dl(InputVector);
21662 // Detect mmx to i32 conversion through a v2i32 elt extract.
21663 if (InputVector.getOpcode() == ISD::BITCAST && InputVector.hasOneUse() &&
21664 N->getValueType(0) == MVT::i32 &&
21665 InputVector.getValueType() == MVT::v2i32) {
21667 // The bitcast source is a direct mmx result.
21668 SDValue MMXSrc = InputVector.getNode()->getOperand(0);
21669 if (MMXSrc.getValueType() == MVT::x86mmx)
21670 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
21671 N->getValueType(0),
21672 InputVector.getNode()->getOperand(0));
21674 // The mmx is indirect: (i64 extract_elt (v1i64 bitcast (x86mmx ...))).
21675 SDValue MMXSrcOp = MMXSrc.getOperand(0);
21676 if (MMXSrc.getOpcode() == ISD::EXTRACT_VECTOR_ELT && MMXSrc.hasOneUse() &&
21677 MMXSrc.getValueType() == MVT::i64 && MMXSrcOp.hasOneUse() &&
21678 MMXSrcOp.getOpcode() == ISD::BITCAST &&
21679 MMXSrcOp.getValueType() == MVT::v1i64 &&
21680 MMXSrcOp.getOperand(0).getValueType() == MVT::x86mmx)
21681 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
21682 N->getValueType(0),
21683 MMXSrcOp.getOperand(0));
21686 EVT VT = N->getValueType(0);
21688 if (VT == MVT::i1 && dyn_cast<ConstantSDNode>(N->getOperand(1)) &&
21689 InputVector.getOpcode() == ISD::BITCAST &&
21690 dyn_cast<ConstantSDNode>(InputVector.getOperand(0))) {
21691 uint64_t ExtractedElt =
21692 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
21693 uint64_t InputValue =
21694 cast<ConstantSDNode>(InputVector.getOperand(0))->getZExtValue();
21695 uint64_t Res = (InputValue >> ExtractedElt) & 1;
21696 return DAG.getConstant(Res, dl, MVT::i1);
21698 // Only operate on vectors of 4 elements, where the alternative shuffling
21699 // gets to be more expensive.
21700 if (InputVector.getValueType() != MVT::v4i32)
21703 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
21704 // single use which is a sign-extend or zero-extend, and all elements are
21706 SmallVector<SDNode *, 4> Uses;
21707 unsigned ExtractedElements = 0;
21708 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
21709 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
21710 if (UI.getUse().getResNo() != InputVector.getResNo())
21713 SDNode *Extract = *UI;
21714 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
21717 if (Extract->getValueType(0) != MVT::i32)
21719 if (!Extract->hasOneUse())
21721 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
21722 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
21724 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
21727 // Record which element was extracted.
21728 ExtractedElements |=
21729 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
21731 Uses.push_back(Extract);
21734 // If not all the elements were used, this may not be worthwhile.
21735 if (ExtractedElements != 15)
21738 // Ok, we've now decided to do the transformation.
21739 // If 64-bit shifts are legal, use the extract-shift sequence,
21740 // otherwise bounce the vector off the cache.
21741 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21744 if (TLI.isOperationLegal(ISD::SRA, MVT::i64)) {
21745 SDValue Cst = DAG.getBitcast(MVT::v2i64, InputVector);
21746 EVT VecIdxTy = DAG.getTargetLoweringInfo().getVectorIdxTy();
21747 SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
21748 DAG.getConstant(0, dl, VecIdxTy));
21749 SDValue TopHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
21750 DAG.getConstant(1, dl, VecIdxTy));
21752 SDValue ShAmt = DAG.getConstant(32, dl,
21753 DAG.getTargetLoweringInfo().getShiftAmountTy(MVT::i64));
21754 Vals[0] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BottomHalf);
21755 Vals[1] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
21756 DAG.getNode(ISD::SRA, dl, MVT::i64, BottomHalf, ShAmt));
21757 Vals[2] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, TopHalf);
21758 Vals[3] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
21759 DAG.getNode(ISD::SRA, dl, MVT::i64, TopHalf, ShAmt));
21761 // Store the value to a temporary stack slot.
21762 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
21763 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
21764 MachinePointerInfo(), false, false, 0);
21766 EVT ElementType = InputVector.getValueType().getVectorElementType();
21767 unsigned EltSize = ElementType.getSizeInBits() / 8;
21769 // Replace each use (extract) with a load of the appropriate element.
21770 for (unsigned i = 0; i < 4; ++i) {
21771 uint64_t Offset = EltSize * i;
21772 SDValue OffsetVal = DAG.getConstant(Offset, dl, TLI.getPointerTy());
21774 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
21775 StackPtr, OffsetVal);
21777 // Load the scalar.
21778 Vals[i] = DAG.getLoad(ElementType, dl, Ch,
21779 ScalarAddr, MachinePointerInfo(),
21780 false, false, false, 0);
21785 // Replace the extracts
21786 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
21787 UE = Uses.end(); UI != UE; ++UI) {
21788 SDNode *Extract = *UI;
21790 SDValue Idx = Extract->getOperand(1);
21791 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
21792 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), Vals[IdxVal]);
21795 // The replacement was made in place; don't return anything.
21799 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
21800 static std::pair<unsigned, bool>
21801 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
21802 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
21803 if (!VT.isVector())
21804 return std::make_pair(0, false);
21806 bool NeedSplit = false;
21807 switch (VT.getSimpleVT().SimpleTy) {
21808 default: return std::make_pair(0, false);
21811 if (!Subtarget->hasVLX())
21812 return std::make_pair(0, false);
21816 if (!Subtarget->hasBWI())
21817 return std::make_pair(0, false);
21821 if (!Subtarget->hasAVX512())
21822 return std::make_pair(0, false);
21827 if (!Subtarget->hasAVX2())
21829 if (!Subtarget->hasAVX())
21830 return std::make_pair(0, false);
21835 if (!Subtarget->hasSSE2())
21836 return std::make_pair(0, false);
21839 // SSE2 has only a small subset of the operations.
21840 bool hasUnsigned = Subtarget->hasSSE41() ||
21841 (Subtarget->hasSSE2() && VT == MVT::v16i8);
21842 bool hasSigned = Subtarget->hasSSE41() ||
21843 (Subtarget->hasSSE2() && VT == MVT::v8i16);
21845 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21848 // Check for x CC y ? x : y.
21849 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21850 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21855 Opc = hasUnsigned ? ISD::UMIN : 0u; break;
21858 Opc = hasUnsigned ? ISD::UMAX : 0u; break;
21861 Opc = hasSigned ? ISD::SMIN : 0u; break;
21864 Opc = hasSigned ? ISD::SMAX : 0u; break;
21866 // Check for x CC y ? y : x -- a min/max with reversed arms.
21867 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
21868 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
21873 Opc = hasUnsigned ? ISD::UMAX : 0u; break;
21876 Opc = hasUnsigned ? ISD::UMIN : 0u; break;
21879 Opc = hasSigned ? ISD::SMAX : 0u; break;
21882 Opc = hasSigned ? ISD::SMIN : 0u; break;
21886 return std::make_pair(Opc, NeedSplit);
21890 transformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
21891 const X86Subtarget *Subtarget) {
21893 SDValue Cond = N->getOperand(0);
21894 SDValue LHS = N->getOperand(1);
21895 SDValue RHS = N->getOperand(2);
21897 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
21898 SDValue CondSrc = Cond->getOperand(0);
21899 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
21900 Cond = CondSrc->getOperand(0);
21903 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
21906 // A vselect where all conditions and data are constants can be optimized into
21907 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
21908 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
21909 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
21912 unsigned MaskValue = 0;
21913 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
21916 MVT VT = N->getSimpleValueType(0);
21917 unsigned NumElems = VT.getVectorNumElements();
21918 SmallVector<int, 8> ShuffleMask(NumElems, -1);
21919 for (unsigned i = 0; i < NumElems; ++i) {
21920 // Be sure we emit undef where we can.
21921 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
21922 ShuffleMask[i] = -1;
21924 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
21927 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21928 if (!TLI.isShuffleMaskLegal(ShuffleMask, VT))
21930 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
21933 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
21935 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
21936 TargetLowering::DAGCombinerInfo &DCI,
21937 const X86Subtarget *Subtarget) {
21939 SDValue Cond = N->getOperand(0);
21940 // Get the LHS/RHS of the select.
21941 SDValue LHS = N->getOperand(1);
21942 SDValue RHS = N->getOperand(2);
21943 EVT VT = LHS.getValueType();
21944 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21946 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
21947 // instructions match the semantics of the common C idiom x<y?x:y but not
21948 // x<=y?x:y, because of how they handle negative zero (which can be
21949 // ignored in unsafe-math mode).
21950 // We also try to create v2f32 min/max nodes, which we later widen to v4f32.
21951 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
21952 VT != MVT::f80 && (TLI.isTypeLegal(VT) || VT == MVT::v2f32) &&
21953 (Subtarget->hasSSE2() ||
21954 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
21955 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21957 unsigned Opcode = 0;
21958 // Check for x CC y ? x : y.
21959 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21960 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21964 // Converting this to a min would handle NaNs incorrectly, and swapping
21965 // the operands would cause it to handle comparisons between positive
21966 // and negative zero incorrectly.
21967 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
21968 if (!DAG.getTarget().Options.UnsafeFPMath &&
21969 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
21971 std::swap(LHS, RHS);
21973 Opcode = X86ISD::FMIN;
21976 // Converting this to a min would handle comparisons between positive
21977 // and negative zero incorrectly.
21978 if (!DAG.getTarget().Options.UnsafeFPMath &&
21979 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
21981 Opcode = X86ISD::FMIN;
21984 // Converting this to a min would handle both negative zeros and NaNs
21985 // incorrectly, but we can swap the operands to fix both.
21986 std::swap(LHS, RHS);
21990 Opcode = X86ISD::FMIN;
21994 // Converting this to a max would handle comparisons between positive
21995 // and negative zero incorrectly.
21996 if (!DAG.getTarget().Options.UnsafeFPMath &&
21997 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
21999 Opcode = X86ISD::FMAX;
22002 // Converting this to a max would handle NaNs incorrectly, and swapping
22003 // the operands would cause it to handle comparisons between positive
22004 // and negative zero incorrectly.
22005 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
22006 if (!DAG.getTarget().Options.UnsafeFPMath &&
22007 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
22009 std::swap(LHS, RHS);
22011 Opcode = X86ISD::FMAX;
22014 // Converting this to a max would handle both negative zeros and NaNs
22015 // incorrectly, but we can swap the operands to fix both.
22016 std::swap(LHS, RHS);
22020 Opcode = X86ISD::FMAX;
22023 // Check for x CC y ? y : x -- a min/max with reversed arms.
22024 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
22025 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
22029 // Converting this to a min would handle comparisons between positive
22030 // and negative zero incorrectly, and swapping the operands would
22031 // cause it to handle NaNs incorrectly.
22032 if (!DAG.getTarget().Options.UnsafeFPMath &&
22033 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
22034 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22036 std::swap(LHS, RHS);
22038 Opcode = X86ISD::FMIN;
22041 // Converting this to a min would handle NaNs incorrectly.
22042 if (!DAG.getTarget().Options.UnsafeFPMath &&
22043 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
22045 Opcode = X86ISD::FMIN;
22048 // Converting this to a min would handle both negative zeros and NaNs
22049 // incorrectly, but we can swap the operands to fix both.
22050 std::swap(LHS, RHS);
22054 Opcode = X86ISD::FMIN;
22058 // Converting this to a max would handle NaNs incorrectly.
22059 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22061 Opcode = X86ISD::FMAX;
22064 // Converting this to a max would handle comparisons between positive
22065 // and negative zero incorrectly, and swapping the operands would
22066 // cause it to handle NaNs incorrectly.
22067 if (!DAG.getTarget().Options.UnsafeFPMath &&
22068 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
22069 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22071 std::swap(LHS, RHS);
22073 Opcode = X86ISD::FMAX;
22076 // Converting this to a max would handle both negative zeros and NaNs
22077 // incorrectly, but we can swap the operands to fix both.
22078 std::swap(LHS, RHS);
22082 Opcode = X86ISD::FMAX;
22088 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
22091 EVT CondVT = Cond.getValueType();
22092 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
22093 CondVT.getVectorElementType() == MVT::i1) {
22094 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
22095 // lowering on KNL. In this case we convert it to
22096 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
22097 // The same situation for all 128 and 256-bit vectors of i8 and i16.
22098 // Since SKX these selects have a proper lowering.
22099 EVT OpVT = LHS.getValueType();
22100 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
22101 (OpVT.getVectorElementType() == MVT::i8 ||
22102 OpVT.getVectorElementType() == MVT::i16) &&
22103 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
22104 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
22105 DCI.AddToWorklist(Cond.getNode());
22106 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
22109 // If this is a select between two integer constants, try to do some
22111 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
22112 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
22113 // Don't do this for crazy integer types.
22114 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
22115 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
22116 // so that TrueC (the true value) is larger than FalseC.
22117 bool NeedsCondInvert = false;
22119 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
22120 // Efficiently invertible.
22121 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
22122 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
22123 isa<ConstantSDNode>(Cond.getOperand(1))))) {
22124 NeedsCondInvert = true;
22125 std::swap(TrueC, FalseC);
22128 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
22129 if (FalseC->getAPIntValue() == 0 &&
22130 TrueC->getAPIntValue().isPowerOf2()) {
22131 if (NeedsCondInvert) // Invert the condition if needed.
22132 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22133 DAG.getConstant(1, DL, Cond.getValueType()));
22135 // Zero extend the condition if needed.
22136 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
22138 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
22139 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
22140 DAG.getConstant(ShAmt, DL, MVT::i8));
22143 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
22144 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
22145 if (NeedsCondInvert) // Invert the condition if needed.
22146 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22147 DAG.getConstant(1, DL, Cond.getValueType()));
22149 // Zero extend the condition if needed.
22150 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
22151 FalseC->getValueType(0), Cond);
22152 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22153 SDValue(FalseC, 0));
22156 // Optimize cases that will turn into an LEA instruction. This requires
22157 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
22158 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
22159 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
22160 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
22162 bool isFastMultiplier = false;
22164 switch ((unsigned char)Diff) {
22166 case 1: // result = add base, cond
22167 case 2: // result = lea base( , cond*2)
22168 case 3: // result = lea base(cond, cond*2)
22169 case 4: // result = lea base( , cond*4)
22170 case 5: // result = lea base(cond, cond*4)
22171 case 8: // result = lea base( , cond*8)
22172 case 9: // result = lea base(cond, cond*8)
22173 isFastMultiplier = true;
22178 if (isFastMultiplier) {
22179 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
22180 if (NeedsCondInvert) // Invert the condition if needed.
22181 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22182 DAG.getConstant(1, DL, Cond.getValueType()));
22184 // Zero extend the condition if needed.
22185 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
22187 // Scale the condition by the difference.
22189 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
22190 DAG.getConstant(Diff, DL,
22191 Cond.getValueType()));
22193 // Add the base if non-zero.
22194 if (FalseC->getAPIntValue() != 0)
22195 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22196 SDValue(FalseC, 0));
22203 // Canonicalize max and min:
22204 // (x > y) ? x : y -> (x >= y) ? x : y
22205 // (x < y) ? x : y -> (x <= y) ? x : y
22206 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
22207 // the need for an extra compare
22208 // against zero. e.g.
22209 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
22211 // testl %edi, %edi
22213 // cmovgl %edi, %eax
22217 // cmovsl %eax, %edi
22218 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
22219 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
22220 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
22221 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22226 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
22227 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
22228 Cond.getOperand(0), Cond.getOperand(1), NewCC);
22229 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
22234 // Early exit check
22235 if (!TLI.isTypeLegal(VT))
22238 // Match VSELECTs into subs with unsigned saturation.
22239 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
22240 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
22241 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
22242 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
22243 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22245 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
22246 // left side invert the predicate to simplify logic below.
22248 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
22250 CC = ISD::getSetCCInverse(CC, true);
22251 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
22255 if (Other.getNode() && Other->getNumOperands() == 2 &&
22256 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
22257 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
22258 SDValue CondRHS = Cond->getOperand(1);
22260 // Look for a general sub with unsigned saturation first.
22261 // x >= y ? x-y : 0 --> subus x, y
22262 // x > y ? x-y : 0 --> subus x, y
22263 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
22264 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
22265 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
22267 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
22268 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
22269 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
22270 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
22271 // If the RHS is a constant we have to reverse the const
22272 // canonicalization.
22273 // x > C-1 ? x+-C : 0 --> subus x, C
22274 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
22275 CondRHSConst->getAPIntValue() ==
22276 (-OpRHSConst->getAPIntValue() - 1))
22277 return DAG.getNode(
22278 X86ISD::SUBUS, DL, VT, OpLHS,
22279 DAG.getConstant(-OpRHSConst->getAPIntValue(), DL, VT));
22281 // Another special case: If C was a sign bit, the sub has been
22282 // canonicalized into a xor.
22283 // FIXME: Would it be better to use computeKnownBits to determine
22284 // whether it's safe to decanonicalize the xor?
22285 // x s< 0 ? x^C : 0 --> subus x, C
22286 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
22287 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
22288 OpRHSConst->getAPIntValue().isSignBit())
22289 // Note that we have to rebuild the RHS constant here to ensure we
22290 // don't rely on particular values of undef lanes.
22291 return DAG.getNode(
22292 X86ISD::SUBUS, DL, VT, OpLHS,
22293 DAG.getConstant(OpRHSConst->getAPIntValue(), DL, VT));
22298 // Try to match a min/max vector operation.
22299 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
22300 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
22301 unsigned Opc = ret.first;
22302 bool NeedSplit = ret.second;
22304 if (Opc && NeedSplit) {
22305 unsigned NumElems = VT.getVectorNumElements();
22306 // Extract the LHS vectors
22307 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
22308 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
22310 // Extract the RHS vectors
22311 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
22312 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
22314 // Create min/max for each subvector
22315 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
22316 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
22318 // Merge the result
22319 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
22321 return DAG.getNode(Opc, DL, VT, LHS, RHS);
22324 // Simplify vector selection if condition value type matches vselect
22326 if (N->getOpcode() == ISD::VSELECT && CondVT == VT) {
22327 assert(Cond.getValueType().isVector() &&
22328 "vector select expects a vector selector!");
22330 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
22331 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
22333 // Try invert the condition if true value is not all 1s and false value
22335 if (!TValIsAllOnes && !FValIsAllZeros &&
22336 // Check if the selector will be produced by CMPP*/PCMP*
22337 Cond.getOpcode() == ISD::SETCC &&
22338 // Check if SETCC has already been promoted
22339 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT) {
22340 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
22341 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
22343 if (TValIsAllZeros || FValIsAllOnes) {
22344 SDValue CC = Cond.getOperand(2);
22345 ISD::CondCode NewCC =
22346 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
22347 Cond.getOperand(0).getValueType().isInteger());
22348 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
22349 std::swap(LHS, RHS);
22350 TValIsAllOnes = FValIsAllOnes;
22351 FValIsAllZeros = TValIsAllZeros;
22355 if (TValIsAllOnes || FValIsAllZeros) {
22358 if (TValIsAllOnes && FValIsAllZeros)
22360 else if (TValIsAllOnes)
22362 DAG.getNode(ISD::OR, DL, CondVT, Cond, DAG.getBitcast(CondVT, RHS));
22363 else if (FValIsAllZeros)
22364 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
22365 DAG.getBitcast(CondVT, LHS));
22367 return DAG.getBitcast(VT, Ret);
22371 // We should generate an X86ISD::BLENDI from a vselect if its argument
22372 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
22373 // constants. This specific pattern gets generated when we split a
22374 // selector for a 512 bit vector in a machine without AVX512 (but with
22375 // 256-bit vectors), during legalization:
22377 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
22379 // Iff we find this pattern and the build_vectors are built from
22380 // constants, we translate the vselect into a shuffle_vector that we
22381 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
22382 if ((N->getOpcode() == ISD::VSELECT ||
22383 N->getOpcode() == X86ISD::SHRUNKBLEND) &&
22384 !DCI.isBeforeLegalize() && !VT.is512BitVector()) {
22385 SDValue Shuffle = transformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
22386 if (Shuffle.getNode())
22390 // If this is a *dynamic* select (non-constant condition) and we can match
22391 // this node with one of the variable blend instructions, restructure the
22392 // condition so that the blends can use the high bit of each element and use
22393 // SimplifyDemandedBits to simplify the condition operand.
22394 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
22395 !DCI.isBeforeLegalize() &&
22396 !ISD::isBuildVectorOfConstantSDNodes(Cond.getNode())) {
22397 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
22399 // Don't optimize vector selects that map to mask-registers.
22403 // We can only handle the cases where VSELECT is directly legal on the
22404 // subtarget. We custom lower VSELECT nodes with constant conditions and
22405 // this makes it hard to see whether a dynamic VSELECT will correctly
22406 // lower, so we both check the operation's status and explicitly handle the
22407 // cases where a *dynamic* blend will fail even though a constant-condition
22408 // blend could be custom lowered.
22409 // FIXME: We should find a better way to handle this class of problems.
22410 // Potentially, we should combine constant-condition vselect nodes
22411 // pre-legalization into shuffles and not mark as many types as custom
22413 if (!TLI.isOperationLegalOrCustom(ISD::VSELECT, VT))
22415 // FIXME: We don't support i16-element blends currently. We could and
22416 // should support them by making *all* the bits in the condition be set
22417 // rather than just the high bit and using an i8-element blend.
22418 if (VT.getScalarType() == MVT::i16)
22420 // Dynamic blending was only available from SSE4.1 onward.
22421 if (VT.getSizeInBits() == 128 && !Subtarget->hasSSE41())
22423 // Byte blends are only available in AVX2
22424 if (VT.getSizeInBits() == 256 && VT.getScalarType() == MVT::i8 &&
22425 !Subtarget->hasAVX2())
22428 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
22429 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
22431 APInt KnownZero, KnownOne;
22432 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
22433 DCI.isBeforeLegalizeOps());
22434 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
22435 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne,
22437 // If we changed the computation somewhere in the DAG, this change
22438 // will affect all users of Cond.
22439 // Make sure it is fine and update all the nodes so that we do not
22440 // use the generic VSELECT anymore. Otherwise, we may perform
22441 // wrong optimizations as we messed up with the actual expectation
22442 // for the vector boolean values.
22443 if (Cond != TLO.Old) {
22444 // Check all uses of that condition operand to check whether it will be
22445 // consumed by non-BLEND instructions, which may depend on all bits are
22447 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
22449 if (I->getOpcode() != ISD::VSELECT)
22450 // TODO: Add other opcodes eventually lowered into BLEND.
22453 // Update all the users of the condition, before committing the change,
22454 // so that the VSELECT optimizations that expect the correct vector
22455 // boolean value will not be triggered.
22456 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
22458 DAG.ReplaceAllUsesOfValueWith(
22460 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(*I), I->getValueType(0),
22461 Cond, I->getOperand(1), I->getOperand(2)));
22462 DCI.CommitTargetLoweringOpt(TLO);
22465 // At this point, only Cond is changed. Change the condition
22466 // just for N to keep the opportunity to optimize all other
22467 // users their own way.
22468 DAG.ReplaceAllUsesOfValueWith(
22470 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(N), N->getValueType(0),
22471 TLO.New, N->getOperand(1), N->getOperand(2)));
22479 // Check whether a boolean test is testing a boolean value generated by
22480 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
22483 // Simplify the following patterns:
22484 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
22485 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
22486 // to (Op EFLAGS Cond)
22488 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
22489 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
22490 // to (Op EFLAGS !Cond)
22492 // where Op could be BRCOND or CMOV.
22494 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
22495 // Quit if not CMP and SUB with its value result used.
22496 if (Cmp.getOpcode() != X86ISD::CMP &&
22497 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
22500 // Quit if not used as a boolean value.
22501 if (CC != X86::COND_E && CC != X86::COND_NE)
22504 // Check CMP operands. One of them should be 0 or 1 and the other should be
22505 // an SetCC or extended from it.
22506 SDValue Op1 = Cmp.getOperand(0);
22507 SDValue Op2 = Cmp.getOperand(1);
22510 const ConstantSDNode* C = nullptr;
22511 bool needOppositeCond = (CC == X86::COND_E);
22512 bool checkAgainstTrue = false; // Is it a comparison against 1?
22514 if ((C = dyn_cast<ConstantSDNode>(Op1)))
22516 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
22518 else // Quit if all operands are not constants.
22521 if (C->getZExtValue() == 1) {
22522 needOppositeCond = !needOppositeCond;
22523 checkAgainstTrue = true;
22524 } else if (C->getZExtValue() != 0)
22525 // Quit if the constant is neither 0 or 1.
22528 bool truncatedToBoolWithAnd = false;
22529 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
22530 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
22531 SetCC.getOpcode() == ISD::TRUNCATE ||
22532 SetCC.getOpcode() == ISD::AND) {
22533 if (SetCC.getOpcode() == ISD::AND) {
22535 ConstantSDNode *CS;
22536 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
22537 CS->getZExtValue() == 1)
22539 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
22540 CS->getZExtValue() == 1)
22544 SetCC = SetCC.getOperand(OpIdx);
22545 truncatedToBoolWithAnd = true;
22547 SetCC = SetCC.getOperand(0);
22550 switch (SetCC.getOpcode()) {
22551 case X86ISD::SETCC_CARRY:
22552 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
22553 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
22554 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
22555 // truncated to i1 using 'and'.
22556 if (checkAgainstTrue && !truncatedToBoolWithAnd)
22558 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
22559 "Invalid use of SETCC_CARRY!");
22561 case X86ISD::SETCC:
22562 // Set the condition code or opposite one if necessary.
22563 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
22564 if (needOppositeCond)
22565 CC = X86::GetOppositeBranchCondition(CC);
22566 return SetCC.getOperand(1);
22567 case X86ISD::CMOV: {
22568 // Check whether false/true value has canonical one, i.e. 0 or 1.
22569 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
22570 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
22571 // Quit if true value is not a constant.
22574 // Quit if false value is not a constant.
22576 SDValue Op = SetCC.getOperand(0);
22577 // Skip 'zext' or 'trunc' node.
22578 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
22579 Op.getOpcode() == ISD::TRUNCATE)
22580 Op = Op.getOperand(0);
22581 // A special case for rdrand/rdseed, where 0 is set if false cond is
22583 if ((Op.getOpcode() != X86ISD::RDRAND &&
22584 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
22587 // Quit if false value is not the constant 0 or 1.
22588 bool FValIsFalse = true;
22589 if (FVal && FVal->getZExtValue() != 0) {
22590 if (FVal->getZExtValue() != 1)
22592 // If FVal is 1, opposite cond is needed.
22593 needOppositeCond = !needOppositeCond;
22594 FValIsFalse = false;
22596 // Quit if TVal is not the constant opposite of FVal.
22597 if (FValIsFalse && TVal->getZExtValue() != 1)
22599 if (!FValIsFalse && TVal->getZExtValue() != 0)
22601 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
22602 if (needOppositeCond)
22603 CC = X86::GetOppositeBranchCondition(CC);
22604 return SetCC.getOperand(3);
22611 /// Check whether Cond is an AND/OR of SETCCs off of the same EFLAGS.
22613 /// (X86or (X86setcc) (X86setcc))
22614 /// (X86cmp (and (X86setcc) (X86setcc)), 0)
22615 static bool checkBoolTestAndOrSetCCCombine(SDValue Cond, X86::CondCode &CC0,
22616 X86::CondCode &CC1, SDValue &Flags,
22618 if (Cond->getOpcode() == X86ISD::CMP) {
22619 ConstantSDNode *CondOp1C = dyn_cast<ConstantSDNode>(Cond->getOperand(1));
22620 if (!CondOp1C || !CondOp1C->isNullValue())
22623 Cond = Cond->getOperand(0);
22628 SDValue SetCC0, SetCC1;
22629 switch (Cond->getOpcode()) {
22630 default: return false;
22637 SetCC0 = Cond->getOperand(0);
22638 SetCC1 = Cond->getOperand(1);
22642 // Make sure we have SETCC nodes, using the same flags value.
22643 if (SetCC0.getOpcode() != X86ISD::SETCC ||
22644 SetCC1.getOpcode() != X86ISD::SETCC ||
22645 SetCC0->getOperand(1) != SetCC1->getOperand(1))
22648 CC0 = (X86::CondCode)SetCC0->getConstantOperandVal(0);
22649 CC1 = (X86::CondCode)SetCC1->getConstantOperandVal(0);
22650 Flags = SetCC0->getOperand(1);
22654 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
22655 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
22656 TargetLowering::DAGCombinerInfo &DCI,
22657 const X86Subtarget *Subtarget) {
22660 // If the flag operand isn't dead, don't touch this CMOV.
22661 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
22664 SDValue FalseOp = N->getOperand(0);
22665 SDValue TrueOp = N->getOperand(1);
22666 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
22667 SDValue Cond = N->getOperand(3);
22669 if (CC == X86::COND_E || CC == X86::COND_NE) {
22670 switch (Cond.getOpcode()) {
22674 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
22675 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
22676 return (CC == X86::COND_E) ? FalseOp : TrueOp;
22682 Flags = checkBoolTestSetCCCombine(Cond, CC);
22683 if (Flags.getNode() &&
22684 // Extra check as FCMOV only supports a subset of X86 cond.
22685 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
22686 SDValue Ops[] = { FalseOp, TrueOp,
22687 DAG.getConstant(CC, DL, MVT::i8), Flags };
22688 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
22691 // If this is a select between two integer constants, try to do some
22692 // optimizations. Note that the operands are ordered the opposite of SELECT
22694 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
22695 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
22696 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
22697 // larger than FalseC (the false value).
22698 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
22699 CC = X86::GetOppositeBranchCondition(CC);
22700 std::swap(TrueC, FalseC);
22701 std::swap(TrueOp, FalseOp);
22704 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
22705 // This is efficient for any integer data type (including i8/i16) and
22707 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
22708 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
22709 DAG.getConstant(CC, DL, MVT::i8), Cond);
22711 // Zero extend the condition if needed.
22712 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
22714 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
22715 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
22716 DAG.getConstant(ShAmt, DL, MVT::i8));
22717 if (N->getNumValues() == 2) // Dead flag value?
22718 return DCI.CombineTo(N, Cond, SDValue());
22722 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
22723 // for any integer data type, including i8/i16.
22724 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
22725 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
22726 DAG.getConstant(CC, DL, MVT::i8), Cond);
22728 // Zero extend the condition if needed.
22729 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
22730 FalseC->getValueType(0), Cond);
22731 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22732 SDValue(FalseC, 0));
22734 if (N->getNumValues() == 2) // Dead flag value?
22735 return DCI.CombineTo(N, Cond, SDValue());
22739 // Optimize cases that will turn into an LEA instruction. This requires
22740 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
22741 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
22742 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
22743 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
22745 bool isFastMultiplier = false;
22747 switch ((unsigned char)Diff) {
22749 case 1: // result = add base, cond
22750 case 2: // result = lea base( , cond*2)
22751 case 3: // result = lea base(cond, cond*2)
22752 case 4: // result = lea base( , cond*4)
22753 case 5: // result = lea base(cond, cond*4)
22754 case 8: // result = lea base( , cond*8)
22755 case 9: // result = lea base(cond, cond*8)
22756 isFastMultiplier = true;
22761 if (isFastMultiplier) {
22762 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
22763 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
22764 DAG.getConstant(CC, DL, MVT::i8), Cond);
22765 // Zero extend the condition if needed.
22766 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
22768 // Scale the condition by the difference.
22770 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
22771 DAG.getConstant(Diff, DL, Cond.getValueType()));
22773 // Add the base if non-zero.
22774 if (FalseC->getAPIntValue() != 0)
22775 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22776 SDValue(FalseC, 0));
22777 if (N->getNumValues() == 2) // Dead flag value?
22778 return DCI.CombineTo(N, Cond, SDValue());
22785 // Handle these cases:
22786 // (select (x != c), e, c) -> select (x != c), e, x),
22787 // (select (x == c), c, e) -> select (x == c), x, e)
22788 // where the c is an integer constant, and the "select" is the combination
22789 // of CMOV and CMP.
22791 // The rationale for this change is that the conditional-move from a constant
22792 // needs two instructions, however, conditional-move from a register needs
22793 // only one instruction.
22795 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
22796 // some instruction-combining opportunities. This opt needs to be
22797 // postponed as late as possible.
22799 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
22800 // the DCI.xxxx conditions are provided to postpone the optimization as
22801 // late as possible.
22803 ConstantSDNode *CmpAgainst = nullptr;
22804 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
22805 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
22806 !isa<ConstantSDNode>(Cond.getOperand(0))) {
22808 if (CC == X86::COND_NE &&
22809 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
22810 CC = X86::GetOppositeBranchCondition(CC);
22811 std::swap(TrueOp, FalseOp);
22814 if (CC == X86::COND_E &&
22815 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
22816 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
22817 DAG.getConstant(CC, DL, MVT::i8), Cond };
22818 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
22823 // Fold and/or of setcc's to double CMOV:
22824 // (CMOV F, T, ((cc1 | cc2) != 0)) -> (CMOV (CMOV F, T, cc1), T, cc2)
22825 // (CMOV F, T, ((cc1 & cc2) != 0)) -> (CMOV (CMOV T, F, !cc1), F, !cc2)
22827 // This combine lets us generate:
22828 // cmovcc1 (jcc1 if we don't have CMOV)
22834 // cmovne (jne if we don't have CMOV)
22835 // When we can't use the CMOV instruction, it might increase branch
22837 // When we can use CMOV, or when there is no mispredict, this improves
22838 // throughput and reduces register pressure.
22840 if (CC == X86::COND_NE) {
22842 X86::CondCode CC0, CC1;
22844 if (checkBoolTestAndOrSetCCCombine(Cond, CC0, CC1, Flags, isAndSetCC)) {
22846 std::swap(FalseOp, TrueOp);
22847 CC0 = X86::GetOppositeBranchCondition(CC0);
22848 CC1 = X86::GetOppositeBranchCondition(CC1);
22851 SDValue LOps[] = {FalseOp, TrueOp, DAG.getConstant(CC0, DL, MVT::i8),
22853 SDValue LCMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), LOps);
22854 SDValue Ops[] = {LCMOV, TrueOp, DAG.getConstant(CC1, DL, MVT::i8), Flags};
22855 SDValue CMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
22856 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SDValue(CMOV.getNode(), 1));
22864 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
22865 const X86Subtarget *Subtarget) {
22866 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
22868 default: return SDValue();
22869 // SSE/AVX/AVX2 blend intrinsics.
22870 case Intrinsic::x86_avx2_pblendvb:
22871 // Don't try to simplify this intrinsic if we don't have AVX2.
22872 if (!Subtarget->hasAVX2())
22875 case Intrinsic::x86_avx_blendv_pd_256:
22876 case Intrinsic::x86_avx_blendv_ps_256:
22877 // Don't try to simplify this intrinsic if we don't have AVX.
22878 if (!Subtarget->hasAVX())
22881 case Intrinsic::x86_sse41_blendvps:
22882 case Intrinsic::x86_sse41_blendvpd:
22883 case Intrinsic::x86_sse41_pblendvb: {
22884 SDValue Op0 = N->getOperand(1);
22885 SDValue Op1 = N->getOperand(2);
22886 SDValue Mask = N->getOperand(3);
22888 // Don't try to simplify this intrinsic if we don't have SSE4.1.
22889 if (!Subtarget->hasSSE41())
22892 // fold (blend A, A, Mask) -> A
22895 // fold (blend A, B, allZeros) -> A
22896 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
22898 // fold (blend A, B, allOnes) -> B
22899 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
22902 // Simplify the case where the mask is a constant i32 value.
22903 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
22904 if (C->isNullValue())
22906 if (C->isAllOnesValue())
22913 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
22914 case Intrinsic::x86_sse2_psrai_w:
22915 case Intrinsic::x86_sse2_psrai_d:
22916 case Intrinsic::x86_avx2_psrai_w:
22917 case Intrinsic::x86_avx2_psrai_d:
22918 case Intrinsic::x86_sse2_psra_w:
22919 case Intrinsic::x86_sse2_psra_d:
22920 case Intrinsic::x86_avx2_psra_w:
22921 case Intrinsic::x86_avx2_psra_d: {
22922 SDValue Op0 = N->getOperand(1);
22923 SDValue Op1 = N->getOperand(2);
22924 EVT VT = Op0.getValueType();
22925 assert(VT.isVector() && "Expected a vector type!");
22927 if (isa<BuildVectorSDNode>(Op1))
22928 Op1 = Op1.getOperand(0);
22930 if (!isa<ConstantSDNode>(Op1))
22933 EVT SVT = VT.getVectorElementType();
22934 unsigned SVTBits = SVT.getSizeInBits();
22936 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
22937 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
22938 uint64_t ShAmt = C.getZExtValue();
22940 // Don't try to convert this shift into a ISD::SRA if the shift
22941 // count is bigger than or equal to the element size.
22942 if (ShAmt >= SVTBits)
22945 // Trivial case: if the shift count is zero, then fold this
22946 // into the first operand.
22950 // Replace this packed shift intrinsic with a target independent
22953 SDValue Splat = DAG.getConstant(C, DL, VT);
22954 return DAG.getNode(ISD::SRA, DL, VT, Op0, Splat);
22959 /// PerformMulCombine - Optimize a single multiply with constant into two
22960 /// in order to implement it with two cheaper instructions, e.g.
22961 /// LEA + SHL, LEA + LEA.
22962 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
22963 TargetLowering::DAGCombinerInfo &DCI) {
22964 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
22967 EVT VT = N->getValueType(0);
22968 if (VT != MVT::i64 && VT != MVT::i32)
22971 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
22974 uint64_t MulAmt = C->getZExtValue();
22975 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
22978 uint64_t MulAmt1 = 0;
22979 uint64_t MulAmt2 = 0;
22980 if ((MulAmt % 9) == 0) {
22982 MulAmt2 = MulAmt / 9;
22983 } else if ((MulAmt % 5) == 0) {
22985 MulAmt2 = MulAmt / 5;
22986 } else if ((MulAmt % 3) == 0) {
22988 MulAmt2 = MulAmt / 3;
22991 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
22994 if (isPowerOf2_64(MulAmt2) &&
22995 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
22996 // If second multiplifer is pow2, issue it first. We want the multiply by
22997 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
22999 std::swap(MulAmt1, MulAmt2);
23002 if (isPowerOf2_64(MulAmt1))
23003 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
23004 DAG.getConstant(Log2_64(MulAmt1), DL, MVT::i8));
23006 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
23007 DAG.getConstant(MulAmt1, DL, VT));
23009 if (isPowerOf2_64(MulAmt2))
23010 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
23011 DAG.getConstant(Log2_64(MulAmt2), DL, MVT::i8));
23013 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
23014 DAG.getConstant(MulAmt2, DL, VT));
23016 // Do not add new nodes to DAG combiner worklist.
23017 DCI.CombineTo(N, NewMul, false);
23022 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
23023 SDValue N0 = N->getOperand(0);
23024 SDValue N1 = N->getOperand(1);
23025 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
23026 EVT VT = N0.getValueType();
23028 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
23029 // since the result of setcc_c is all zero's or all ones.
23030 if (VT.isInteger() && !VT.isVector() &&
23031 N1C && N0.getOpcode() == ISD::AND &&
23032 N0.getOperand(1).getOpcode() == ISD::Constant) {
23033 SDValue N00 = N0.getOperand(0);
23034 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
23035 ((N00.getOpcode() == ISD::ANY_EXTEND ||
23036 N00.getOpcode() == ISD::ZERO_EXTEND) &&
23037 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
23038 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
23039 APInt ShAmt = N1C->getAPIntValue();
23040 Mask = Mask.shl(ShAmt);
23043 return DAG.getNode(ISD::AND, DL, VT,
23044 N00, DAG.getConstant(Mask, DL, VT));
23049 // Hardware support for vector shifts is sparse which makes us scalarize the
23050 // vector operations in many cases. Also, on sandybridge ADD is faster than
23052 // (shl V, 1) -> add V,V
23053 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
23054 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
23055 assert(N0.getValueType().isVector() && "Invalid vector shift type");
23056 // We shift all of the values by one. In many cases we do not have
23057 // hardware support for this operation. This is better expressed as an ADD
23059 if (N1SplatC->getZExtValue() == 1)
23060 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
23066 /// \brief Returns a vector of 0s if the node in input is a vector logical
23067 /// shift by a constant amount which is known to be bigger than or equal
23068 /// to the vector element size in bits.
23069 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
23070 const X86Subtarget *Subtarget) {
23071 EVT VT = N->getValueType(0);
23073 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
23074 (!Subtarget->hasInt256() ||
23075 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
23078 SDValue Amt = N->getOperand(1);
23080 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
23081 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
23082 APInt ShiftAmt = AmtSplat->getAPIntValue();
23083 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
23085 // SSE2/AVX2 logical shifts always return a vector of 0s
23086 // if the shift amount is bigger than or equal to
23087 // the element size. The constant shift amount will be
23088 // encoded as a 8-bit immediate.
23089 if (ShiftAmt.trunc(8).uge(MaxAmount))
23090 return getZeroVector(VT, Subtarget, DAG, DL);
23096 /// PerformShiftCombine - Combine shifts.
23097 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
23098 TargetLowering::DAGCombinerInfo &DCI,
23099 const X86Subtarget *Subtarget) {
23100 if (N->getOpcode() == ISD::SHL)
23101 if (SDValue V = PerformSHLCombine(N, DAG))
23104 // Try to fold this logical shift into a zero vector.
23105 if (N->getOpcode() != ISD::SRA)
23106 if (SDValue V = performShiftToAllZeros(N, DAG, Subtarget))
23112 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
23113 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
23114 // and friends. Likewise for OR -> CMPNEQSS.
23115 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
23116 TargetLowering::DAGCombinerInfo &DCI,
23117 const X86Subtarget *Subtarget) {
23120 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
23121 // we're requiring SSE2 for both.
23122 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
23123 SDValue N0 = N->getOperand(0);
23124 SDValue N1 = N->getOperand(1);
23125 SDValue CMP0 = N0->getOperand(1);
23126 SDValue CMP1 = N1->getOperand(1);
23129 // The SETCCs should both refer to the same CMP.
23130 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
23133 SDValue CMP00 = CMP0->getOperand(0);
23134 SDValue CMP01 = CMP0->getOperand(1);
23135 EVT VT = CMP00.getValueType();
23137 if (VT == MVT::f32 || VT == MVT::f64) {
23138 bool ExpectingFlags = false;
23139 // Check for any users that want flags:
23140 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
23141 !ExpectingFlags && UI != UE; ++UI)
23142 switch (UI->getOpcode()) {
23147 ExpectingFlags = true;
23149 case ISD::CopyToReg:
23150 case ISD::SIGN_EXTEND:
23151 case ISD::ZERO_EXTEND:
23152 case ISD::ANY_EXTEND:
23156 if (!ExpectingFlags) {
23157 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
23158 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
23160 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
23161 X86::CondCode tmp = cc0;
23166 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
23167 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
23168 // FIXME: need symbolic constants for these magic numbers.
23169 // See X86ATTInstPrinter.cpp:printSSECC().
23170 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
23171 if (Subtarget->hasAVX512()) {
23172 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
23174 DAG.getConstant(x86cc, DL, MVT::i8));
23175 if (N->getValueType(0) != MVT::i1)
23176 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
23180 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
23181 CMP00.getValueType(), CMP00, CMP01,
23182 DAG.getConstant(x86cc, DL,
23185 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
23186 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
23188 if (is64BitFP && !Subtarget->is64Bit()) {
23189 // On a 32-bit target, we cannot bitcast the 64-bit float to a
23190 // 64-bit integer, since that's not a legal type. Since
23191 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
23192 // bits, but can do this little dance to extract the lowest 32 bits
23193 // and work with those going forward.
23194 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
23196 SDValue Vector32 = DAG.getBitcast(MVT::v4f32, Vector64);
23197 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
23198 Vector32, DAG.getIntPtrConstant(0, DL));
23202 SDValue OnesOrZeroesI = DAG.getBitcast(IntVT, OnesOrZeroesF);
23203 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
23204 DAG.getConstant(1, DL, IntVT));
23205 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8,
23207 return OneBitOfTruth;
23215 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
23216 /// so it can be folded inside ANDNP.
23217 static bool CanFoldXORWithAllOnes(const SDNode *N) {
23218 EVT VT = N->getValueType(0);
23220 // Match direct AllOnes for 128 and 256-bit vectors
23221 if (ISD::isBuildVectorAllOnes(N))
23224 // Look through a bit convert.
23225 if (N->getOpcode() == ISD::BITCAST)
23226 N = N->getOperand(0).getNode();
23228 // Sometimes the operand may come from a insert_subvector building a 256-bit
23230 if (VT.is256BitVector() &&
23231 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
23232 SDValue V1 = N->getOperand(0);
23233 SDValue V2 = N->getOperand(1);
23235 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
23236 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
23237 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
23238 ISD::isBuildVectorAllOnes(V2.getNode()))
23245 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
23246 // register. In most cases we actually compare or select YMM-sized registers
23247 // and mixing the two types creates horrible code. This method optimizes
23248 // some of the transition sequences.
23249 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
23250 TargetLowering::DAGCombinerInfo &DCI,
23251 const X86Subtarget *Subtarget) {
23252 EVT VT = N->getValueType(0);
23253 if (!VT.is256BitVector())
23256 assert((N->getOpcode() == ISD::ANY_EXTEND ||
23257 N->getOpcode() == ISD::ZERO_EXTEND ||
23258 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
23260 SDValue Narrow = N->getOperand(0);
23261 EVT NarrowVT = Narrow->getValueType(0);
23262 if (!NarrowVT.is128BitVector())
23265 if (Narrow->getOpcode() != ISD::XOR &&
23266 Narrow->getOpcode() != ISD::AND &&
23267 Narrow->getOpcode() != ISD::OR)
23270 SDValue N0 = Narrow->getOperand(0);
23271 SDValue N1 = Narrow->getOperand(1);
23274 // The Left side has to be a trunc.
23275 if (N0.getOpcode() != ISD::TRUNCATE)
23278 // The type of the truncated inputs.
23279 EVT WideVT = N0->getOperand(0)->getValueType(0);
23283 // The right side has to be a 'trunc' or a constant vector.
23284 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
23285 ConstantSDNode *RHSConstSplat = nullptr;
23286 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
23287 RHSConstSplat = RHSBV->getConstantSplatNode();
23288 if (!RHSTrunc && !RHSConstSplat)
23291 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23293 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
23296 // Set N0 and N1 to hold the inputs to the new wide operation.
23297 N0 = N0->getOperand(0);
23298 if (RHSConstSplat) {
23299 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
23300 SDValue(RHSConstSplat, 0));
23301 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
23302 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
23303 } else if (RHSTrunc) {
23304 N1 = N1->getOperand(0);
23307 // Generate the wide operation.
23308 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
23309 unsigned Opcode = N->getOpcode();
23311 case ISD::ANY_EXTEND:
23313 case ISD::ZERO_EXTEND: {
23314 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
23315 APInt Mask = APInt::getAllOnesValue(InBits);
23316 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
23317 return DAG.getNode(ISD::AND, DL, VT,
23318 Op, DAG.getConstant(Mask, DL, VT));
23320 case ISD::SIGN_EXTEND:
23321 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
23322 Op, DAG.getValueType(NarrowVT));
23324 llvm_unreachable("Unexpected opcode");
23328 static SDValue VectorZextCombine(SDNode *N, SelectionDAG &DAG,
23329 TargetLowering::DAGCombinerInfo &DCI,
23330 const X86Subtarget *Subtarget) {
23331 SDValue N0 = N->getOperand(0);
23332 SDValue N1 = N->getOperand(1);
23335 // A vector zext_in_reg may be represented as a shuffle,
23336 // feeding into a bitcast (this represents anyext) feeding into
23337 // an and with a mask.
23338 // We'd like to try to combine that into a shuffle with zero
23339 // plus a bitcast, removing the and.
23340 if (N0.getOpcode() != ISD::BITCAST ||
23341 N0.getOperand(0).getOpcode() != ISD::VECTOR_SHUFFLE)
23344 // The other side of the AND should be a splat of 2^C, where C
23345 // is the number of bits in the source type.
23346 if (N1.getOpcode() == ISD::BITCAST)
23347 N1 = N1.getOperand(0);
23348 if (N1.getOpcode() != ISD::BUILD_VECTOR)
23350 BuildVectorSDNode *Vector = cast<BuildVectorSDNode>(N1);
23352 ShuffleVectorSDNode *Shuffle = cast<ShuffleVectorSDNode>(N0.getOperand(0));
23353 EVT SrcType = Shuffle->getValueType(0);
23355 // We expect a single-source shuffle
23356 if (Shuffle->getOperand(1)->getOpcode() != ISD::UNDEF)
23359 unsigned SrcSize = SrcType.getScalarSizeInBits();
23361 APInt SplatValue, SplatUndef;
23362 unsigned SplatBitSize;
23364 if (!Vector->isConstantSplat(SplatValue, SplatUndef,
23365 SplatBitSize, HasAnyUndefs))
23368 unsigned ResSize = N1.getValueType().getScalarSizeInBits();
23369 // Make sure the splat matches the mask we expect
23370 if (SplatBitSize > ResSize ||
23371 (SplatValue + 1).exactLogBase2() != (int)SrcSize)
23374 // Make sure the input and output size make sense
23375 if (SrcSize >= ResSize || ResSize % SrcSize)
23378 // We expect a shuffle of the form <0, u, u, u, 1, u, u, u...>
23379 // The number of u's between each two values depends on the ratio between
23380 // the source and dest type.
23381 unsigned ZextRatio = ResSize / SrcSize;
23382 bool IsZext = true;
23383 for (unsigned i = 0; i < SrcType.getVectorNumElements(); ++i) {
23384 if (i % ZextRatio) {
23385 if (Shuffle->getMaskElt(i) > 0) {
23391 if (Shuffle->getMaskElt(i) != (int)(i / ZextRatio)) {
23392 // Expected element number
23402 // Ok, perform the transformation - replace the shuffle with
23403 // a shuffle of the form <0, k, k, k, 1, k, k, k> with zero
23404 // (instead of undef) where the k elements come from the zero vector.
23405 SmallVector<int, 8> Mask;
23406 unsigned NumElems = SrcType.getVectorNumElements();
23407 for (unsigned i = 0; i < NumElems; ++i)
23409 Mask.push_back(NumElems);
23411 Mask.push_back(i / ZextRatio);
23413 SDValue NewShuffle = DAG.getVectorShuffle(Shuffle->getValueType(0), DL,
23414 Shuffle->getOperand(0), DAG.getConstant(0, DL, SrcType), Mask);
23415 return DAG.getBitcast(N0.getValueType(), NewShuffle);
23418 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
23419 TargetLowering::DAGCombinerInfo &DCI,
23420 const X86Subtarget *Subtarget) {
23421 if (DCI.isBeforeLegalizeOps())
23424 if (SDValue Zext = VectorZextCombine(N, DAG, DCI, Subtarget))
23427 if (SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget))
23430 EVT VT = N->getValueType(0);
23431 SDValue N0 = N->getOperand(0);
23432 SDValue N1 = N->getOperand(1);
23435 // Create BEXTR instructions
23436 // BEXTR is ((X >> imm) & (2**size-1))
23437 if (VT == MVT::i32 || VT == MVT::i64) {
23438 // Check for BEXTR.
23439 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
23440 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
23441 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
23442 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
23443 if (MaskNode && ShiftNode) {
23444 uint64_t Mask = MaskNode->getZExtValue();
23445 uint64_t Shift = ShiftNode->getZExtValue();
23446 if (isMask_64(Mask)) {
23447 uint64_t MaskSize = countPopulation(Mask);
23448 if (Shift + MaskSize <= VT.getSizeInBits())
23449 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
23450 DAG.getConstant(Shift | (MaskSize << 8), DL,
23459 // Want to form ANDNP nodes:
23460 // 1) In the hopes of then easily combining them with OR and AND nodes
23461 // to form PBLEND/PSIGN.
23462 // 2) To match ANDN packed intrinsics
23463 if (VT != MVT::v2i64 && VT != MVT::v4i64)
23466 // Check LHS for vnot
23467 if (N0.getOpcode() == ISD::XOR &&
23468 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
23469 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
23470 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
23472 // Check RHS for vnot
23473 if (N1.getOpcode() == ISD::XOR &&
23474 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
23475 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
23476 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
23481 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
23482 TargetLowering::DAGCombinerInfo &DCI,
23483 const X86Subtarget *Subtarget) {
23484 if (DCI.isBeforeLegalizeOps())
23487 if (SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget))
23490 SDValue N0 = N->getOperand(0);
23491 SDValue N1 = N->getOperand(1);
23492 EVT VT = N->getValueType(0);
23494 // look for psign/blend
23495 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
23496 if (!Subtarget->hasSSSE3() ||
23497 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
23500 // Canonicalize pandn to RHS
23501 if (N0.getOpcode() == X86ISD::ANDNP)
23503 // or (and (m, y), (pandn m, x))
23504 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
23505 SDValue Mask = N1.getOperand(0);
23506 SDValue X = N1.getOperand(1);
23508 if (N0.getOperand(0) == Mask)
23509 Y = N0.getOperand(1);
23510 if (N0.getOperand(1) == Mask)
23511 Y = N0.getOperand(0);
23513 // Check to see if the mask appeared in both the AND and ANDNP and
23517 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
23518 // Look through mask bitcast.
23519 if (Mask.getOpcode() == ISD::BITCAST)
23520 Mask = Mask.getOperand(0);
23521 if (X.getOpcode() == ISD::BITCAST)
23522 X = X.getOperand(0);
23523 if (Y.getOpcode() == ISD::BITCAST)
23524 Y = Y.getOperand(0);
23526 EVT MaskVT = Mask.getValueType();
23528 // Validate that the Mask operand is a vector sra node.
23529 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
23530 // there is no psrai.b
23531 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
23532 unsigned SraAmt = ~0;
23533 if (Mask.getOpcode() == ISD::SRA) {
23534 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
23535 if (auto *AmtConst = AmtBV->getConstantSplatNode())
23536 SraAmt = AmtConst->getZExtValue();
23537 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
23538 SDValue SraC = Mask.getOperand(1);
23539 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
23541 if ((SraAmt + 1) != EltBits)
23546 // Now we know we at least have a plendvb with the mask val. See if
23547 // we can form a psignb/w/d.
23548 // psign = x.type == y.type == mask.type && y = sub(0, x);
23549 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
23550 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
23551 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
23552 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
23553 "Unsupported VT for PSIGN");
23554 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
23555 return DAG.getBitcast(VT, Mask);
23557 // PBLENDVB only available on SSE 4.1
23558 if (!Subtarget->hasSSE41())
23561 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
23563 X = DAG.getBitcast(BlendVT, X);
23564 Y = DAG.getBitcast(BlendVT, Y);
23565 Mask = DAG.getBitcast(BlendVT, Mask);
23566 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
23567 return DAG.getBitcast(VT, Mask);
23571 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
23574 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
23575 MachineFunction &MF = DAG.getMachineFunction();
23577 MF.getFunction()->hasFnAttribute(Attribute::OptimizeForSize);
23579 // SHLD/SHRD instructions have lower register pressure, but on some
23580 // platforms they have higher latency than the equivalent
23581 // series of shifts/or that would otherwise be generated.
23582 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
23583 // have higher latencies and we are not optimizing for size.
23584 if (!OptForSize && Subtarget->isSHLDSlow())
23587 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
23589 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
23591 if (!N0.hasOneUse() || !N1.hasOneUse())
23594 SDValue ShAmt0 = N0.getOperand(1);
23595 if (ShAmt0.getValueType() != MVT::i8)
23597 SDValue ShAmt1 = N1.getOperand(1);
23598 if (ShAmt1.getValueType() != MVT::i8)
23600 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
23601 ShAmt0 = ShAmt0.getOperand(0);
23602 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
23603 ShAmt1 = ShAmt1.getOperand(0);
23606 unsigned Opc = X86ISD::SHLD;
23607 SDValue Op0 = N0.getOperand(0);
23608 SDValue Op1 = N1.getOperand(0);
23609 if (ShAmt0.getOpcode() == ISD::SUB) {
23610 Opc = X86ISD::SHRD;
23611 std::swap(Op0, Op1);
23612 std::swap(ShAmt0, ShAmt1);
23615 unsigned Bits = VT.getSizeInBits();
23616 if (ShAmt1.getOpcode() == ISD::SUB) {
23617 SDValue Sum = ShAmt1.getOperand(0);
23618 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
23619 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
23620 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
23621 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
23622 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
23623 return DAG.getNode(Opc, DL, VT,
23625 DAG.getNode(ISD::TRUNCATE, DL,
23628 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
23629 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
23631 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
23632 return DAG.getNode(Opc, DL, VT,
23633 N0.getOperand(0), N1.getOperand(0),
23634 DAG.getNode(ISD::TRUNCATE, DL,
23641 // Generate NEG and CMOV for integer abs.
23642 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
23643 EVT VT = N->getValueType(0);
23645 // Since X86 does not have CMOV for 8-bit integer, we don't convert
23646 // 8-bit integer abs to NEG and CMOV.
23647 if (VT.isInteger() && VT.getSizeInBits() == 8)
23650 SDValue N0 = N->getOperand(0);
23651 SDValue N1 = N->getOperand(1);
23654 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
23655 // and change it to SUB and CMOV.
23656 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
23657 N0.getOpcode() == ISD::ADD &&
23658 N0.getOperand(1) == N1 &&
23659 N1.getOpcode() == ISD::SRA &&
23660 N1.getOperand(0) == N0.getOperand(0))
23661 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
23662 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
23663 // Generate SUB & CMOV.
23664 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
23665 DAG.getConstant(0, DL, VT), N0.getOperand(0));
23667 SDValue Ops[] = { N0.getOperand(0), Neg,
23668 DAG.getConstant(X86::COND_GE, DL, MVT::i8),
23669 SDValue(Neg.getNode(), 1) };
23670 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
23675 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
23676 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
23677 TargetLowering::DAGCombinerInfo &DCI,
23678 const X86Subtarget *Subtarget) {
23679 if (DCI.isBeforeLegalizeOps())
23682 if (Subtarget->hasCMov())
23683 if (SDValue RV = performIntegerAbsCombine(N, DAG))
23689 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
23690 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
23691 TargetLowering::DAGCombinerInfo &DCI,
23692 const X86Subtarget *Subtarget) {
23693 LoadSDNode *Ld = cast<LoadSDNode>(N);
23694 EVT RegVT = Ld->getValueType(0);
23695 EVT MemVT = Ld->getMemoryVT();
23697 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23699 // For chips with slow 32-byte unaligned loads, break the 32-byte operation
23700 // into two 16-byte operations.
23701 ISD::LoadExtType Ext = Ld->getExtensionType();
23702 unsigned Alignment = Ld->getAlignment();
23703 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
23704 if (RegVT.is256BitVector() && Subtarget->isUnalignedMem32Slow() &&
23705 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
23706 unsigned NumElems = RegVT.getVectorNumElements();
23710 SDValue Ptr = Ld->getBasePtr();
23711 SDValue Increment = DAG.getConstant(16, dl, TLI.getPointerTy());
23713 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
23715 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
23716 Ld->getPointerInfo(), Ld->isVolatile(),
23717 Ld->isNonTemporal(), Ld->isInvariant(),
23719 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
23720 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
23721 Ld->getPointerInfo(), Ld->isVolatile(),
23722 Ld->isNonTemporal(), Ld->isInvariant(),
23723 std::min(16U, Alignment));
23724 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
23726 Load2.getValue(1));
23728 SDValue NewVec = DAG.getUNDEF(RegVT);
23729 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
23730 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
23731 return DCI.CombineTo(N, NewVec, TF, true);
23737 /// PerformMLOADCombine - Resolve extending loads
23738 static SDValue PerformMLOADCombine(SDNode *N, SelectionDAG &DAG,
23739 TargetLowering::DAGCombinerInfo &DCI,
23740 const X86Subtarget *Subtarget) {
23741 MaskedLoadSDNode *Mld = cast<MaskedLoadSDNode>(N);
23742 if (Mld->getExtensionType() != ISD::SEXTLOAD)
23745 EVT VT = Mld->getValueType(0);
23746 unsigned NumElems = VT.getVectorNumElements();
23747 EVT LdVT = Mld->getMemoryVT();
23750 assert(LdVT != VT && "Cannot extend to the same type");
23751 unsigned ToSz = VT.getVectorElementType().getSizeInBits();
23752 unsigned FromSz = LdVT.getVectorElementType().getSizeInBits();
23753 // From, To sizes and ElemCount must be pow of two
23754 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
23755 "Unexpected size for extending masked load");
23757 unsigned SizeRatio = ToSz / FromSz;
23758 assert(SizeRatio * NumElems * FromSz == VT.getSizeInBits());
23760 // Create a type on which we perform the shuffle
23761 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
23762 LdVT.getScalarType(), NumElems*SizeRatio);
23763 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
23765 // Convert Src0 value
23766 SDValue WideSrc0 = DAG.getBitcast(WideVecVT, Mld->getSrc0());
23767 if (Mld->getSrc0().getOpcode() != ISD::UNDEF) {
23768 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
23769 for (unsigned i = 0; i != NumElems; ++i)
23770 ShuffleVec[i] = i * SizeRatio;
23772 // Can't shuffle using an illegal type.
23773 assert (DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT)
23774 && "WideVecVT should be legal");
23775 WideSrc0 = DAG.getVectorShuffle(WideVecVT, dl, WideSrc0,
23776 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
23778 // Prepare the new mask
23780 SDValue Mask = Mld->getMask();
23781 if (Mask.getValueType() == VT) {
23782 // Mask and original value have the same type
23783 NewMask = DAG.getBitcast(WideVecVT, Mask);
23784 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
23785 for (unsigned i = 0; i != NumElems; ++i)
23786 ShuffleVec[i] = i * SizeRatio;
23787 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
23788 ShuffleVec[i] = NumElems*SizeRatio;
23789 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
23790 DAG.getConstant(0, dl, WideVecVT),
23794 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
23795 unsigned WidenNumElts = NumElems*SizeRatio;
23796 unsigned MaskNumElts = VT.getVectorNumElements();
23797 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
23800 unsigned NumConcat = WidenNumElts / MaskNumElts;
23801 SmallVector<SDValue, 16> Ops(NumConcat);
23802 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
23804 for (unsigned i = 1; i != NumConcat; ++i)
23807 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
23810 SDValue WideLd = DAG.getMaskedLoad(WideVecVT, dl, Mld->getChain(),
23811 Mld->getBasePtr(), NewMask, WideSrc0,
23812 Mld->getMemoryVT(), Mld->getMemOperand(),
23814 SDValue NewVec = DAG.getNode(X86ISD::VSEXT, dl, VT, WideLd);
23815 return DCI.CombineTo(N, NewVec, WideLd.getValue(1), true);
23818 /// PerformMSTORECombine - Resolve truncating stores
23819 static SDValue PerformMSTORECombine(SDNode *N, SelectionDAG &DAG,
23820 const X86Subtarget *Subtarget) {
23821 MaskedStoreSDNode *Mst = cast<MaskedStoreSDNode>(N);
23822 if (!Mst->isTruncatingStore())
23825 EVT VT = Mst->getValue().getValueType();
23826 unsigned NumElems = VT.getVectorNumElements();
23827 EVT StVT = Mst->getMemoryVT();
23830 assert(StVT != VT && "Cannot truncate to the same type");
23831 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
23832 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
23834 // From, To sizes and ElemCount must be pow of two
23835 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
23836 "Unexpected size for truncating masked store");
23837 // We are going to use the original vector elt for storing.
23838 // Accumulated smaller vector elements must be a multiple of the store size.
23839 assert (((NumElems * FromSz) % ToSz) == 0 &&
23840 "Unexpected ratio for truncating masked store");
23842 unsigned SizeRatio = FromSz / ToSz;
23843 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
23845 // Create a type on which we perform the shuffle
23846 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
23847 StVT.getScalarType(), NumElems*SizeRatio);
23849 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
23851 SDValue WideVec = DAG.getBitcast(WideVecVT, Mst->getValue());
23852 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
23853 for (unsigned i = 0; i != NumElems; ++i)
23854 ShuffleVec[i] = i * SizeRatio;
23856 // Can't shuffle using an illegal type.
23857 assert (DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT)
23858 && "WideVecVT should be legal");
23860 SDValue TruncatedVal = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
23861 DAG.getUNDEF(WideVecVT),
23865 SDValue Mask = Mst->getMask();
23866 if (Mask.getValueType() == VT) {
23867 // Mask and original value have the same type
23868 NewMask = DAG.getBitcast(WideVecVT, Mask);
23869 for (unsigned i = 0; i != NumElems; ++i)
23870 ShuffleVec[i] = i * SizeRatio;
23871 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
23872 ShuffleVec[i] = NumElems*SizeRatio;
23873 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
23874 DAG.getConstant(0, dl, WideVecVT),
23878 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
23879 unsigned WidenNumElts = NumElems*SizeRatio;
23880 unsigned MaskNumElts = VT.getVectorNumElements();
23881 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
23884 unsigned NumConcat = WidenNumElts / MaskNumElts;
23885 SmallVector<SDValue, 16> Ops(NumConcat);
23886 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
23888 for (unsigned i = 1; i != NumConcat; ++i)
23891 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
23894 return DAG.getMaskedStore(Mst->getChain(), dl, TruncatedVal, Mst->getBasePtr(),
23895 NewMask, StVT, Mst->getMemOperand(), false);
23897 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
23898 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
23899 const X86Subtarget *Subtarget) {
23900 StoreSDNode *St = cast<StoreSDNode>(N);
23901 EVT VT = St->getValue().getValueType();
23902 EVT StVT = St->getMemoryVT();
23904 SDValue StoredVal = St->getOperand(1);
23905 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23907 // If we are saving a concatenation of two XMM registers and 32-byte stores
23908 // are slow, such as on Sandy Bridge, perform two 16-byte stores.
23909 unsigned Alignment = St->getAlignment();
23910 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
23911 if (VT.is256BitVector() && Subtarget->isUnalignedMem32Slow() &&
23912 StVT == VT && !IsAligned) {
23913 unsigned NumElems = VT.getVectorNumElements();
23917 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
23918 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
23920 SDValue Stride = DAG.getConstant(16, dl, TLI.getPointerTy());
23921 SDValue Ptr0 = St->getBasePtr();
23922 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
23924 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
23925 St->getPointerInfo(), St->isVolatile(),
23926 St->isNonTemporal(), Alignment);
23927 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
23928 St->getPointerInfo(), St->isVolatile(),
23929 St->isNonTemporal(),
23930 std::min(16U, Alignment));
23931 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
23934 // Optimize trunc store (of multiple scalars) to shuffle and store.
23935 // First, pack all of the elements in one place. Next, store to memory
23936 // in fewer chunks.
23937 if (St->isTruncatingStore() && VT.isVector()) {
23938 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23939 unsigned NumElems = VT.getVectorNumElements();
23940 assert(StVT != VT && "Cannot truncate to the same type");
23941 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
23942 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
23944 // From, To sizes and ElemCount must be pow of two
23945 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
23946 // We are going to use the original vector elt for storing.
23947 // Accumulated smaller vector elements must be a multiple of the store size.
23948 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
23950 unsigned SizeRatio = FromSz / ToSz;
23952 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
23954 // Create a type on which we perform the shuffle
23955 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
23956 StVT.getScalarType(), NumElems*SizeRatio);
23958 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
23960 SDValue WideVec = DAG.getBitcast(WideVecVT, St->getValue());
23961 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
23962 for (unsigned i = 0; i != NumElems; ++i)
23963 ShuffleVec[i] = i * SizeRatio;
23965 // Can't shuffle using an illegal type.
23966 if (!TLI.isTypeLegal(WideVecVT))
23969 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
23970 DAG.getUNDEF(WideVecVT),
23972 // At this point all of the data is stored at the bottom of the
23973 // register. We now need to save it to mem.
23975 // Find the largest store unit
23976 MVT StoreType = MVT::i8;
23977 for (MVT Tp : MVT::integer_valuetypes()) {
23978 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
23982 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
23983 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
23984 (64 <= NumElems * ToSz))
23985 StoreType = MVT::f64;
23987 // Bitcast the original vector into a vector of store-size units
23988 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
23989 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
23990 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
23991 SDValue ShuffWide = DAG.getBitcast(StoreVecVT, Shuff);
23992 SmallVector<SDValue, 8> Chains;
23993 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8, dl,
23994 TLI.getPointerTy());
23995 SDValue Ptr = St->getBasePtr();
23997 // Perform one or more big stores into memory.
23998 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
23999 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
24000 StoreType, ShuffWide,
24001 DAG.getIntPtrConstant(i, dl));
24002 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
24003 St->getPointerInfo(), St->isVolatile(),
24004 St->isNonTemporal(), St->getAlignment());
24005 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
24006 Chains.push_back(Ch);
24009 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
24012 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
24013 // the FP state in cases where an emms may be missing.
24014 // A preferable solution to the general problem is to figure out the right
24015 // places to insert EMMS. This qualifies as a quick hack.
24017 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
24018 if (VT.getSizeInBits() != 64)
24021 const Function *F = DAG.getMachineFunction().getFunction();
24022 bool NoImplicitFloatOps = F->hasFnAttribute(Attribute::NoImplicitFloat);
24024 !Subtarget->useSoftFloat() && !NoImplicitFloatOps && Subtarget->hasSSE2();
24025 if ((VT.isVector() ||
24026 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
24027 isa<LoadSDNode>(St->getValue()) &&
24028 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
24029 St->getChain().hasOneUse() && !St->isVolatile()) {
24030 SDNode* LdVal = St->getValue().getNode();
24031 LoadSDNode *Ld = nullptr;
24032 int TokenFactorIndex = -1;
24033 SmallVector<SDValue, 8> Ops;
24034 SDNode* ChainVal = St->getChain().getNode();
24035 // Must be a store of a load. We currently handle two cases: the load
24036 // is a direct child, and it's under an intervening TokenFactor. It is
24037 // possible to dig deeper under nested TokenFactors.
24038 if (ChainVal == LdVal)
24039 Ld = cast<LoadSDNode>(St->getChain());
24040 else if (St->getValue().hasOneUse() &&
24041 ChainVal->getOpcode() == ISD::TokenFactor) {
24042 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
24043 if (ChainVal->getOperand(i).getNode() == LdVal) {
24044 TokenFactorIndex = i;
24045 Ld = cast<LoadSDNode>(St->getValue());
24047 Ops.push_back(ChainVal->getOperand(i));
24051 if (!Ld || !ISD::isNormalLoad(Ld))
24054 // If this is not the MMX case, i.e. we are just turning i64 load/store
24055 // into f64 load/store, avoid the transformation if there are multiple
24056 // uses of the loaded value.
24057 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
24062 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
24063 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
24065 if (Subtarget->is64Bit() || F64IsLegal) {
24066 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
24067 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
24068 Ld->getPointerInfo(), Ld->isVolatile(),
24069 Ld->isNonTemporal(), Ld->isInvariant(),
24070 Ld->getAlignment());
24071 SDValue NewChain = NewLd.getValue(1);
24072 if (TokenFactorIndex != -1) {
24073 Ops.push_back(NewChain);
24074 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
24076 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
24077 St->getPointerInfo(),
24078 St->isVolatile(), St->isNonTemporal(),
24079 St->getAlignment());
24082 // Otherwise, lower to two pairs of 32-bit loads / stores.
24083 SDValue LoAddr = Ld->getBasePtr();
24084 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
24085 DAG.getConstant(4, LdDL, MVT::i32));
24087 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
24088 Ld->getPointerInfo(),
24089 Ld->isVolatile(), Ld->isNonTemporal(),
24090 Ld->isInvariant(), Ld->getAlignment());
24091 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
24092 Ld->getPointerInfo().getWithOffset(4),
24093 Ld->isVolatile(), Ld->isNonTemporal(),
24095 MinAlign(Ld->getAlignment(), 4));
24097 SDValue NewChain = LoLd.getValue(1);
24098 if (TokenFactorIndex != -1) {
24099 Ops.push_back(LoLd);
24100 Ops.push_back(HiLd);
24101 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
24104 LoAddr = St->getBasePtr();
24105 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
24106 DAG.getConstant(4, StDL, MVT::i32));
24108 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
24109 St->getPointerInfo(),
24110 St->isVolatile(), St->isNonTemporal(),
24111 St->getAlignment());
24112 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
24113 St->getPointerInfo().getWithOffset(4),
24115 St->isNonTemporal(),
24116 MinAlign(St->getAlignment(), 4));
24117 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
24120 // This is similar to the above case, but here we handle a scalar 64-bit
24121 // integer store that is extracted from a vector on a 32-bit target.
24122 // If we have SSE2, then we can treat it like a floating-point double
24123 // to get past legalization. The execution dependencies fixup pass will
24124 // choose the optimal machine instruction for the store if this really is
24125 // an integer or v2f32 rather than an f64.
24126 if (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit() &&
24127 St->getOperand(1).getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
24128 SDValue OldExtract = St->getOperand(1);
24129 SDValue ExtOp0 = OldExtract.getOperand(0);
24130 unsigned VecSize = ExtOp0.getValueSizeInBits();
24131 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, VecSize / 64);
24132 SDValue BitCast = DAG.getBitcast(VecVT, ExtOp0);
24133 SDValue NewExtract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
24134 BitCast, OldExtract.getOperand(1));
24135 return DAG.getStore(St->getChain(), dl, NewExtract, St->getBasePtr(),
24136 St->getPointerInfo(), St->isVolatile(),
24137 St->isNonTemporal(), St->getAlignment());
24143 /// Return 'true' if this vector operation is "horizontal"
24144 /// and return the operands for the horizontal operation in LHS and RHS. A
24145 /// horizontal operation performs the binary operation on successive elements
24146 /// of its first operand, then on successive elements of its second operand,
24147 /// returning the resulting values in a vector. For example, if
24148 /// A = < float a0, float a1, float a2, float a3 >
24150 /// B = < float b0, float b1, float b2, float b3 >
24151 /// then the result of doing a horizontal operation on A and B is
24152 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
24153 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
24154 /// A horizontal-op B, for some already available A and B, and if so then LHS is
24155 /// set to A, RHS to B, and the routine returns 'true'.
24156 /// Note that the binary operation should have the property that if one of the
24157 /// operands is UNDEF then the result is UNDEF.
24158 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
24159 // Look for the following pattern: if
24160 // A = < float a0, float a1, float a2, float a3 >
24161 // B = < float b0, float b1, float b2, float b3 >
24163 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
24164 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
24165 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
24166 // which is A horizontal-op B.
24168 // At least one of the operands should be a vector shuffle.
24169 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
24170 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
24173 MVT VT = LHS.getSimpleValueType();
24175 assert((VT.is128BitVector() || VT.is256BitVector()) &&
24176 "Unsupported vector type for horizontal add/sub");
24178 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
24179 // operate independently on 128-bit lanes.
24180 unsigned NumElts = VT.getVectorNumElements();
24181 unsigned NumLanes = VT.getSizeInBits()/128;
24182 unsigned NumLaneElts = NumElts / NumLanes;
24183 assert((NumLaneElts % 2 == 0) &&
24184 "Vector type should have an even number of elements in each lane");
24185 unsigned HalfLaneElts = NumLaneElts/2;
24187 // View LHS in the form
24188 // LHS = VECTOR_SHUFFLE A, B, LMask
24189 // If LHS is not a shuffle then pretend it is the shuffle
24190 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
24191 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
24194 SmallVector<int, 16> LMask(NumElts);
24195 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
24196 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
24197 A = LHS.getOperand(0);
24198 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
24199 B = LHS.getOperand(1);
24200 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
24201 std::copy(Mask.begin(), Mask.end(), LMask.begin());
24203 if (LHS.getOpcode() != ISD::UNDEF)
24205 for (unsigned i = 0; i != NumElts; ++i)
24209 // Likewise, view RHS in the form
24210 // RHS = VECTOR_SHUFFLE C, D, RMask
24212 SmallVector<int, 16> RMask(NumElts);
24213 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
24214 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
24215 C = RHS.getOperand(0);
24216 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
24217 D = RHS.getOperand(1);
24218 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
24219 std::copy(Mask.begin(), Mask.end(), RMask.begin());
24221 if (RHS.getOpcode() != ISD::UNDEF)
24223 for (unsigned i = 0; i != NumElts; ++i)
24227 // Check that the shuffles are both shuffling the same vectors.
24228 if (!(A == C && B == D) && !(A == D && B == C))
24231 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
24232 if (!A.getNode() && !B.getNode())
24235 // If A and B occur in reverse order in RHS, then "swap" them (which means
24236 // rewriting the mask).
24238 ShuffleVectorSDNode::commuteMask(RMask);
24240 // At this point LHS and RHS are equivalent to
24241 // LHS = VECTOR_SHUFFLE A, B, LMask
24242 // RHS = VECTOR_SHUFFLE A, B, RMask
24243 // Check that the masks correspond to performing a horizontal operation.
24244 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
24245 for (unsigned i = 0; i != NumLaneElts; ++i) {
24246 int LIdx = LMask[i+l], RIdx = RMask[i+l];
24248 // Ignore any UNDEF components.
24249 if (LIdx < 0 || RIdx < 0 ||
24250 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
24251 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
24254 // Check that successive elements are being operated on. If not, this is
24255 // not a horizontal operation.
24256 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
24257 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
24258 if (!(LIdx == Index && RIdx == Index + 1) &&
24259 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
24264 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
24265 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
24269 /// Do target-specific dag combines on floating point adds.
24270 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
24271 const X86Subtarget *Subtarget) {
24272 EVT VT = N->getValueType(0);
24273 SDValue LHS = N->getOperand(0);
24274 SDValue RHS = N->getOperand(1);
24276 // Try to synthesize horizontal adds from adds of shuffles.
24277 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
24278 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
24279 isHorizontalBinOp(LHS, RHS, true))
24280 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
24284 /// Do target-specific dag combines on floating point subs.
24285 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
24286 const X86Subtarget *Subtarget) {
24287 EVT VT = N->getValueType(0);
24288 SDValue LHS = N->getOperand(0);
24289 SDValue RHS = N->getOperand(1);
24291 // Try to synthesize horizontal subs from subs of shuffles.
24292 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
24293 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
24294 isHorizontalBinOp(LHS, RHS, false))
24295 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
24299 /// Do target-specific dag combines on X86ISD::FOR and X86ISD::FXOR nodes.
24300 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
24301 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
24303 // F[X]OR(0.0, x) -> x
24304 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24305 if (C->getValueAPF().isPosZero())
24306 return N->getOperand(1);
24308 // F[X]OR(x, 0.0) -> x
24309 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24310 if (C->getValueAPF().isPosZero())
24311 return N->getOperand(0);
24315 /// Do target-specific dag combines on X86ISD::FMIN and X86ISD::FMAX nodes.
24316 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
24317 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
24319 // Only perform optimizations if UnsafeMath is used.
24320 if (!DAG.getTarget().Options.UnsafeFPMath)
24323 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
24324 // into FMINC and FMAXC, which are Commutative operations.
24325 unsigned NewOp = 0;
24326 switch (N->getOpcode()) {
24327 default: llvm_unreachable("unknown opcode");
24328 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
24329 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
24332 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
24333 N->getOperand(0), N->getOperand(1));
24336 /// Do target-specific dag combines on X86ISD::FAND nodes.
24337 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
24338 // FAND(0.0, x) -> 0.0
24339 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24340 if (C->getValueAPF().isPosZero())
24341 return N->getOperand(0);
24343 // FAND(x, 0.0) -> 0.0
24344 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24345 if (C->getValueAPF().isPosZero())
24346 return N->getOperand(1);
24351 /// Do target-specific dag combines on X86ISD::FANDN nodes
24352 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
24353 // FANDN(0.0, x) -> x
24354 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24355 if (C->getValueAPF().isPosZero())
24356 return N->getOperand(1);
24358 // FANDN(x, 0.0) -> 0.0
24359 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24360 if (C->getValueAPF().isPosZero())
24361 return N->getOperand(1);
24366 static SDValue PerformBTCombine(SDNode *N,
24368 TargetLowering::DAGCombinerInfo &DCI) {
24369 // BT ignores high bits in the bit index operand.
24370 SDValue Op1 = N->getOperand(1);
24371 if (Op1.hasOneUse()) {
24372 unsigned BitWidth = Op1.getValueSizeInBits();
24373 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
24374 APInt KnownZero, KnownOne;
24375 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
24376 !DCI.isBeforeLegalizeOps());
24377 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24378 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
24379 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
24380 DCI.CommitTargetLoweringOpt(TLO);
24385 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
24386 SDValue Op = N->getOperand(0);
24387 if (Op.getOpcode() == ISD::BITCAST)
24388 Op = Op.getOperand(0);
24389 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
24390 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
24391 VT.getVectorElementType().getSizeInBits() ==
24392 OpVT.getVectorElementType().getSizeInBits()) {
24393 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
24398 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
24399 const X86Subtarget *Subtarget) {
24400 EVT VT = N->getValueType(0);
24401 if (!VT.isVector())
24404 SDValue N0 = N->getOperand(0);
24405 SDValue N1 = N->getOperand(1);
24406 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
24409 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
24410 // both SSE and AVX2 since there is no sign-extended shift right
24411 // operation on a vector with 64-bit elements.
24412 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
24413 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
24414 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
24415 N0.getOpcode() == ISD::SIGN_EXTEND)) {
24416 SDValue N00 = N0.getOperand(0);
24418 // EXTLOAD has a better solution on AVX2,
24419 // it may be replaced with X86ISD::VSEXT node.
24420 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
24421 if (!ISD::isNormalLoad(N00.getNode()))
24424 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
24425 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
24427 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
24433 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
24434 TargetLowering::DAGCombinerInfo &DCI,
24435 const X86Subtarget *Subtarget) {
24436 SDValue N0 = N->getOperand(0);
24437 EVT VT = N->getValueType(0);
24438 EVT SVT = VT.getScalarType();
24439 EVT InVT = N0.getValueType();
24440 EVT InSVT = InVT.getScalarType();
24443 // (i8,i32 sext (sdivrem (i8 x, i8 y)) ->
24444 // (i8,i32 (sdivrem_sext_hreg (i8 x, i8 y)
24445 // This exposes the sext to the sdivrem lowering, so that it directly extends
24446 // from AH (which we otherwise need to do contortions to access).
24447 if (N0.getOpcode() == ISD::SDIVREM && N0.getResNo() == 1 &&
24448 InVT == MVT::i8 && VT == MVT::i32) {
24449 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
24450 SDValue R = DAG.getNode(X86ISD::SDIVREM8_SEXT_HREG, DL, NodeTys,
24451 N0.getOperand(0), N0.getOperand(1));
24452 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
24453 return R.getValue(1);
24456 if (!DCI.isBeforeLegalizeOps()) {
24457 if (InVT == MVT::i1) {
24458 SDValue Zero = DAG.getConstant(0, DL, VT);
24460 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), DL, VT);
24461 return DAG.getNode(ISD::SELECT, DL, VT, N0, AllOnes, Zero);
24466 if (VT.isVector() && Subtarget->hasSSE2()) {
24467 auto ExtendVecSize = [&DAG](SDLoc DL, SDValue N, unsigned Size) {
24468 EVT InVT = N.getValueType();
24469 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), InVT.getScalarType(),
24470 Size / InVT.getScalarSizeInBits());
24471 SmallVector<SDValue, 8> Opnds(Size / InVT.getSizeInBits(),
24472 DAG.getUNDEF(InVT));
24474 return DAG.getNode(ISD::CONCAT_VECTORS, DL, OutVT, Opnds);
24477 // If target-size is less than 128-bits, extend to a type that would extend
24478 // to 128 bits, extend that and extract the original target vector.
24479 if (VT.getSizeInBits() < 128 && !(128 % VT.getSizeInBits()) &&
24480 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
24481 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
24482 unsigned Scale = 128 / VT.getSizeInBits();
24484 EVT::getVectorVT(*DAG.getContext(), SVT, 128 / SVT.getSizeInBits());
24485 SDValue Ex = ExtendVecSize(DL, N0, Scale * InVT.getSizeInBits());
24486 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND, DL, ExVT, Ex);
24487 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, SExt,
24488 DAG.getIntPtrConstant(0, DL));
24491 // If target-size is 128-bits, then convert to ISD::SIGN_EXTEND_VECTOR_INREG
24492 // which ensures lowering to X86ISD::VSEXT (pmovsx*).
24493 if (VT.getSizeInBits() == 128 &&
24494 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
24495 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
24496 SDValue ExOp = ExtendVecSize(DL, N0, 128);
24497 return DAG.getSignExtendVectorInReg(ExOp, DL, VT);
24500 // On pre-AVX2 targets, split into 128-bit nodes of
24501 // ISD::SIGN_EXTEND_VECTOR_INREG.
24502 if (!Subtarget->hasInt256() && !(VT.getSizeInBits() % 128) &&
24503 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
24504 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
24505 unsigned NumVecs = VT.getSizeInBits() / 128;
24506 unsigned NumSubElts = 128 / SVT.getSizeInBits();
24507 EVT SubVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumSubElts);
24508 EVT InSubVT = EVT::getVectorVT(*DAG.getContext(), InSVT, NumSubElts);
24510 SmallVector<SDValue, 8> Opnds;
24511 for (unsigned i = 0, Offset = 0; i != NumVecs;
24512 ++i, Offset += NumSubElts) {
24513 SDValue SrcVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InSubVT, N0,
24514 DAG.getIntPtrConstant(Offset, DL));
24515 SrcVec = ExtendVecSize(DL, SrcVec, 128);
24516 SrcVec = DAG.getSignExtendVectorInReg(SrcVec, DL, SubVT);
24517 Opnds.push_back(SrcVec);
24519 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Opnds);
24523 if (!Subtarget->hasFp256())
24526 if (VT.isVector() && VT.getSizeInBits() == 256)
24527 if (SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget))
24533 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
24534 const X86Subtarget* Subtarget) {
24536 EVT VT = N->getValueType(0);
24538 // Let legalize expand this if it isn't a legal type yet.
24539 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
24542 EVT ScalarVT = VT.getScalarType();
24543 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
24544 (!Subtarget->hasFMA() && !Subtarget->hasFMA4() &&
24545 !Subtarget->hasAVX512()))
24548 SDValue A = N->getOperand(0);
24549 SDValue B = N->getOperand(1);
24550 SDValue C = N->getOperand(2);
24552 bool NegA = (A.getOpcode() == ISD::FNEG);
24553 bool NegB = (B.getOpcode() == ISD::FNEG);
24554 bool NegC = (C.getOpcode() == ISD::FNEG);
24556 // Negative multiplication when NegA xor NegB
24557 bool NegMul = (NegA != NegB);
24559 A = A.getOperand(0);
24561 B = B.getOperand(0);
24563 C = C.getOperand(0);
24567 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
24569 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
24571 return DAG.getNode(Opcode, dl, VT, A, B, C);
24574 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
24575 TargetLowering::DAGCombinerInfo &DCI,
24576 const X86Subtarget *Subtarget) {
24577 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
24578 // (and (i32 x86isd::setcc_carry), 1)
24579 // This eliminates the zext. This transformation is necessary because
24580 // ISD::SETCC is always legalized to i8.
24582 SDValue N0 = N->getOperand(0);
24583 EVT VT = N->getValueType(0);
24585 if (N0.getOpcode() == ISD::AND &&
24587 N0.getOperand(0).hasOneUse()) {
24588 SDValue N00 = N0.getOperand(0);
24589 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
24590 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
24591 if (!C || C->getZExtValue() != 1)
24593 return DAG.getNode(ISD::AND, dl, VT,
24594 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
24595 N00.getOperand(0), N00.getOperand(1)),
24596 DAG.getConstant(1, dl, VT));
24600 if (N0.getOpcode() == ISD::TRUNCATE &&
24602 N0.getOperand(0).hasOneUse()) {
24603 SDValue N00 = N0.getOperand(0);
24604 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
24605 return DAG.getNode(ISD::AND, dl, VT,
24606 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
24607 N00.getOperand(0), N00.getOperand(1)),
24608 DAG.getConstant(1, dl, VT));
24612 if (VT.is256BitVector())
24613 if (SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget))
24616 // (i8,i32 zext (udivrem (i8 x, i8 y)) ->
24617 // (i8,i32 (udivrem_zext_hreg (i8 x, i8 y)
24618 // This exposes the zext to the udivrem lowering, so that it directly extends
24619 // from AH (which we otherwise need to do contortions to access).
24620 if (N0.getOpcode() == ISD::UDIVREM &&
24621 N0.getResNo() == 1 && N0.getValueType() == MVT::i8 &&
24622 (VT == MVT::i32 || VT == MVT::i64)) {
24623 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
24624 SDValue R = DAG.getNode(X86ISD::UDIVREM8_ZEXT_HREG, dl, NodeTys,
24625 N0.getOperand(0), N0.getOperand(1));
24626 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
24627 return R.getValue(1);
24633 // Optimize x == -y --> x+y == 0
24634 // x != -y --> x+y != 0
24635 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
24636 const X86Subtarget* Subtarget) {
24637 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
24638 SDValue LHS = N->getOperand(0);
24639 SDValue RHS = N->getOperand(1);
24640 EVT VT = N->getValueType(0);
24643 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
24644 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
24645 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
24646 SDValue addV = DAG.getNode(ISD::ADD, DL, LHS.getValueType(), RHS,
24647 LHS.getOperand(1));
24648 return DAG.getSetCC(DL, N->getValueType(0), addV,
24649 DAG.getConstant(0, DL, addV.getValueType()), CC);
24651 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
24652 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
24653 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
24654 SDValue addV = DAG.getNode(ISD::ADD, DL, RHS.getValueType(), LHS,
24655 RHS.getOperand(1));
24656 return DAG.getSetCC(DL, N->getValueType(0), addV,
24657 DAG.getConstant(0, DL, addV.getValueType()), CC);
24660 if (VT.getScalarType() == MVT::i1 &&
24661 (CC == ISD::SETNE || CC == ISD::SETEQ || ISD::isSignedIntSetCC(CC))) {
24663 (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
24664 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
24665 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
24667 if (!IsSEXT0 || !IsVZero1) {
24668 // Swap the operands and update the condition code.
24669 std::swap(LHS, RHS);
24670 CC = ISD::getSetCCSwappedOperands(CC);
24672 IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
24673 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
24674 IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
24677 if (IsSEXT0 && IsVZero1) {
24678 assert(VT == LHS.getOperand(0).getValueType() &&
24679 "Uexpected operand type");
24680 if (CC == ISD::SETGT)
24681 return DAG.getConstant(0, DL, VT);
24682 if (CC == ISD::SETLE)
24683 return DAG.getConstant(1, DL, VT);
24684 if (CC == ISD::SETEQ || CC == ISD::SETGE)
24685 return DAG.getNOT(DL, LHS.getOperand(0), VT);
24687 assert((CC == ISD::SETNE || CC == ISD::SETLT) &&
24688 "Unexpected condition code!");
24689 return LHS.getOperand(0);
24696 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
24697 SelectionDAG &DAG) {
24699 MVT VT = Load->getSimpleValueType(0);
24700 MVT EVT = VT.getVectorElementType();
24701 SDValue Addr = Load->getOperand(1);
24702 SDValue NewAddr = DAG.getNode(
24703 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
24704 DAG.getConstant(Index * EVT.getStoreSize(), dl,
24705 Addr.getSimpleValueType()));
24708 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
24709 DAG.getMachineFunction().getMachineMemOperand(
24710 Load->getMemOperand(), 0, EVT.getStoreSize()));
24714 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
24715 const X86Subtarget *Subtarget) {
24717 MVT VT = N->getOperand(1)->getSimpleValueType(0);
24718 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
24719 "X86insertps is only defined for v4x32");
24721 SDValue Ld = N->getOperand(1);
24722 if (MayFoldLoad(Ld)) {
24723 // Extract the countS bits from the immediate so we can get the proper
24724 // address when narrowing the vector load to a specific element.
24725 // When the second source op is a memory address, insertps doesn't use
24726 // countS and just gets an f32 from that address.
24727 unsigned DestIndex =
24728 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
24730 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
24732 // Create this as a scalar to vector to match the instruction pattern.
24733 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
24734 // countS bits are ignored when loading from memory on insertps, which
24735 // means we don't need to explicitly set them to 0.
24736 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
24737 LoadScalarToVector, N->getOperand(2));
24742 static SDValue PerformBLENDICombine(SDNode *N, SelectionDAG &DAG) {
24743 SDValue V0 = N->getOperand(0);
24744 SDValue V1 = N->getOperand(1);
24746 EVT VT = N->getValueType(0);
24748 // Canonicalize a v2f64 blend with a mask of 2 by swapping the vector
24749 // operands and changing the mask to 1. This saves us a bunch of
24750 // pattern-matching possibilities related to scalar math ops in SSE/AVX.
24751 // x86InstrInfo knows how to commute this back after instruction selection
24752 // if it would help register allocation.
24754 // TODO: If optimizing for size or a processor that doesn't suffer from
24755 // partial register update stalls, this should be transformed into a MOVSD
24756 // instruction because a MOVSD is 1-2 bytes smaller than a BLENDPD.
24758 if (VT == MVT::v2f64)
24759 if (auto *Mask = dyn_cast<ConstantSDNode>(N->getOperand(2)))
24760 if (Mask->getZExtValue() == 2 && !isShuffleFoldableLoad(V0)) {
24761 SDValue NewMask = DAG.getConstant(1, DL, MVT::i8);
24762 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V0, NewMask);
24768 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
24769 // as "sbb reg,reg", since it can be extended without zext and produces
24770 // an all-ones bit which is more useful than 0/1 in some cases.
24771 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
24774 return DAG.getNode(ISD::AND, DL, VT,
24775 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
24776 DAG.getConstant(X86::COND_B, DL, MVT::i8),
24778 DAG.getConstant(1, DL, VT));
24779 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
24780 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
24781 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
24782 DAG.getConstant(X86::COND_B, DL, MVT::i8),
24786 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
24787 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
24788 TargetLowering::DAGCombinerInfo &DCI,
24789 const X86Subtarget *Subtarget) {
24791 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
24792 SDValue EFLAGS = N->getOperand(1);
24794 if (CC == X86::COND_A) {
24795 // Try to convert COND_A into COND_B in an attempt to facilitate
24796 // materializing "setb reg".
24798 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
24799 // cannot take an immediate as its first operand.
24801 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
24802 EFLAGS.getValueType().isInteger() &&
24803 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
24804 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
24805 EFLAGS.getNode()->getVTList(),
24806 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
24807 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
24808 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
24812 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
24813 // a zext and produces an all-ones bit which is more useful than 0/1 in some
24815 if (CC == X86::COND_B)
24816 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
24818 if (SDValue Flags = checkBoolTestSetCCCombine(EFLAGS, CC)) {
24819 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
24820 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
24826 // Optimize branch condition evaluation.
24828 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
24829 TargetLowering::DAGCombinerInfo &DCI,
24830 const X86Subtarget *Subtarget) {
24832 SDValue Chain = N->getOperand(0);
24833 SDValue Dest = N->getOperand(1);
24834 SDValue EFLAGS = N->getOperand(3);
24835 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
24837 if (SDValue Flags = checkBoolTestSetCCCombine(EFLAGS, CC)) {
24838 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
24839 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
24846 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
24847 SelectionDAG &DAG) {
24848 // Take advantage of vector comparisons producing 0 or -1 in each lane to
24849 // optimize away operation when it's from a constant.
24851 // The general transformation is:
24852 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
24853 // AND(VECTOR_CMP(x,y), constant2)
24854 // constant2 = UNARYOP(constant)
24856 // Early exit if this isn't a vector operation, the operand of the
24857 // unary operation isn't a bitwise AND, or if the sizes of the operations
24858 // aren't the same.
24859 EVT VT = N->getValueType(0);
24860 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
24861 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
24862 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
24865 // Now check that the other operand of the AND is a constant. We could
24866 // make the transformation for non-constant splats as well, but it's unclear
24867 // that would be a benefit as it would not eliminate any operations, just
24868 // perform one more step in scalar code before moving to the vector unit.
24869 if (BuildVectorSDNode *BV =
24870 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
24871 // Bail out if the vector isn't a constant.
24872 if (!BV->isConstant())
24875 // Everything checks out. Build up the new and improved node.
24877 EVT IntVT = BV->getValueType(0);
24878 // Create a new constant of the appropriate type for the transformed
24880 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
24881 // The AND node needs bitcasts to/from an integer vector type around it.
24882 SDValue MaskConst = DAG.getBitcast(IntVT, SourceConst);
24883 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
24884 N->getOperand(0)->getOperand(0), MaskConst);
24885 SDValue Res = DAG.getBitcast(VT, NewAnd);
24892 static SDValue PerformUINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
24893 const X86Subtarget *Subtarget) {
24894 SDValue Op0 = N->getOperand(0);
24895 EVT VT = N->getValueType(0);
24896 EVT InVT = Op0.getValueType();
24897 EVT InSVT = InVT.getScalarType();
24898 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24900 // UINT_TO_FP(vXi8) -> SINT_TO_FP(ZEXT(vXi8 to vXi32))
24901 // UINT_TO_FP(vXi16) -> SINT_TO_FP(ZEXT(vXi16 to vXi32))
24902 if (InVT.isVector() && (InSVT == MVT::i8 || InSVT == MVT::i16)) {
24904 EVT DstVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
24905 InVT.getVectorNumElements());
24906 SDValue P = DAG.getNode(ISD::ZERO_EXTEND, dl, DstVT, Op0);
24908 if (TLI.isOperationLegal(ISD::UINT_TO_FP, DstVT))
24909 return DAG.getNode(ISD::UINT_TO_FP, dl, VT, P);
24911 return DAG.getNode(ISD::SINT_TO_FP, dl, VT, P);
24917 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
24918 const X86Subtarget *Subtarget) {
24919 // First try to optimize away the conversion entirely when it's
24920 // conditionally from a constant. Vectors only.
24921 if (SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG))
24924 // Now move on to more general possibilities.
24925 SDValue Op0 = N->getOperand(0);
24926 EVT VT = N->getValueType(0);
24927 EVT InVT = Op0.getValueType();
24928 EVT InSVT = InVT.getScalarType();
24930 // SINT_TO_FP(vXi8) -> SINT_TO_FP(SEXT(vXi8 to vXi32))
24931 // SINT_TO_FP(vXi16) -> SINT_TO_FP(SEXT(vXi16 to vXi32))
24932 if (InVT.isVector() && (InSVT == MVT::i8 || InSVT == MVT::i16)) {
24934 EVT DstVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
24935 InVT.getVectorNumElements());
24936 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
24937 return DAG.getNode(ISD::SINT_TO_FP, dl, VT, P);
24940 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
24941 // a 32-bit target where SSE doesn't support i64->FP operations.
24942 if (Op0.getOpcode() == ISD::LOAD) {
24943 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
24944 EVT LdVT = Ld->getValueType(0);
24946 // This transformation is not supported if the result type is f16
24947 if (VT == MVT::f16)
24950 if (!Ld->isVolatile() && !VT.isVector() &&
24951 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
24952 !Subtarget->is64Bit() && LdVT == MVT::i64) {
24953 SDValue FILDChain = Subtarget->getTargetLowering()->BuildFILD(
24954 SDValue(N, 0), LdVT, Ld->getChain(), Op0, DAG);
24955 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
24962 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
24963 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
24964 X86TargetLowering::DAGCombinerInfo &DCI) {
24965 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
24966 // the result is either zero or one (depending on the input carry bit).
24967 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
24968 if (X86::isZeroNode(N->getOperand(0)) &&
24969 X86::isZeroNode(N->getOperand(1)) &&
24970 // We don't have a good way to replace an EFLAGS use, so only do this when
24972 SDValue(N, 1).use_empty()) {
24974 EVT VT = N->getValueType(0);
24975 SDValue CarryOut = DAG.getConstant(0, DL, N->getValueType(1));
24976 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
24977 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
24978 DAG.getConstant(X86::COND_B, DL,
24981 DAG.getConstant(1, DL, VT));
24982 return DCI.CombineTo(N, Res1, CarryOut);
24988 // fold (add Y, (sete X, 0)) -> adc 0, Y
24989 // (add Y, (setne X, 0)) -> sbb -1, Y
24990 // (sub (sete X, 0), Y) -> sbb 0, Y
24991 // (sub (setne X, 0), Y) -> adc -1, Y
24992 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
24995 // Look through ZExts.
24996 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
24997 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
25000 SDValue SetCC = Ext.getOperand(0);
25001 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
25004 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
25005 if (CC != X86::COND_E && CC != X86::COND_NE)
25008 SDValue Cmp = SetCC.getOperand(1);
25009 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
25010 !X86::isZeroNode(Cmp.getOperand(1)) ||
25011 !Cmp.getOperand(0).getValueType().isInteger())
25014 SDValue CmpOp0 = Cmp.getOperand(0);
25015 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
25016 DAG.getConstant(1, DL, CmpOp0.getValueType()));
25018 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
25019 if (CC == X86::COND_NE)
25020 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
25021 DL, OtherVal.getValueType(), OtherVal,
25022 DAG.getConstant(-1ULL, DL, OtherVal.getValueType()),
25024 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
25025 DL, OtherVal.getValueType(), OtherVal,
25026 DAG.getConstant(0, DL, OtherVal.getValueType()), NewCmp);
25029 /// PerformADDCombine - Do target-specific dag combines on integer adds.
25030 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
25031 const X86Subtarget *Subtarget) {
25032 EVT VT = N->getValueType(0);
25033 SDValue Op0 = N->getOperand(0);
25034 SDValue Op1 = N->getOperand(1);
25036 // Try to synthesize horizontal adds from adds of shuffles.
25037 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
25038 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
25039 isHorizontalBinOp(Op0, Op1, true))
25040 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
25042 return OptimizeConditionalInDecrement(N, DAG);
25045 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
25046 const X86Subtarget *Subtarget) {
25047 SDValue Op0 = N->getOperand(0);
25048 SDValue Op1 = N->getOperand(1);
25050 // X86 can't encode an immediate LHS of a sub. See if we can push the
25051 // negation into a preceding instruction.
25052 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
25053 // If the RHS of the sub is a XOR with one use and a constant, invert the
25054 // immediate. Then add one to the LHS of the sub so we can turn
25055 // X-Y -> X+~Y+1, saving one register.
25056 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
25057 isa<ConstantSDNode>(Op1.getOperand(1))) {
25058 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
25059 EVT VT = Op0.getValueType();
25060 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
25062 DAG.getConstant(~XorC, SDLoc(Op1), VT));
25063 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
25064 DAG.getConstant(C->getAPIntValue() + 1, SDLoc(N), VT));
25068 // Try to synthesize horizontal adds from adds of shuffles.
25069 EVT VT = N->getValueType(0);
25070 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
25071 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
25072 isHorizontalBinOp(Op0, Op1, true))
25073 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
25075 return OptimizeConditionalInDecrement(N, DAG);
25078 /// performVZEXTCombine - Performs build vector combines
25079 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
25080 TargetLowering::DAGCombinerInfo &DCI,
25081 const X86Subtarget *Subtarget) {
25083 MVT VT = N->getSimpleValueType(0);
25084 SDValue Op = N->getOperand(0);
25085 MVT OpVT = Op.getSimpleValueType();
25086 MVT OpEltVT = OpVT.getVectorElementType();
25087 unsigned InputBits = OpEltVT.getSizeInBits() * VT.getVectorNumElements();
25089 // (vzext (bitcast (vzext (x)) -> (vzext x)
25091 while (V.getOpcode() == ISD::BITCAST)
25092 V = V.getOperand(0);
25094 if (V != Op && V.getOpcode() == X86ISD::VZEXT) {
25095 MVT InnerVT = V.getSimpleValueType();
25096 MVT InnerEltVT = InnerVT.getVectorElementType();
25098 // If the element sizes match exactly, we can just do one larger vzext. This
25099 // is always an exact type match as vzext operates on integer types.
25100 if (OpEltVT == InnerEltVT) {
25101 assert(OpVT == InnerVT && "Types must match for vzext!");
25102 return DAG.getNode(X86ISD::VZEXT, DL, VT, V.getOperand(0));
25105 // The only other way we can combine them is if only a single element of the
25106 // inner vzext is used in the input to the outer vzext.
25107 if (InnerEltVT.getSizeInBits() < InputBits)
25110 // In this case, the inner vzext is completely dead because we're going to
25111 // only look at bits inside of the low element. Just do the outer vzext on
25112 // a bitcast of the input to the inner.
25113 return DAG.getNode(X86ISD::VZEXT, DL, VT, DAG.getBitcast(OpVT, V));
25116 // Check if we can bypass extracting and re-inserting an element of an input
25117 // vector. Essentialy:
25118 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
25119 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
25120 V.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
25121 V.getOperand(0).getSimpleValueType().getSizeInBits() == InputBits) {
25122 SDValue ExtractedV = V.getOperand(0);
25123 SDValue OrigV = ExtractedV.getOperand(0);
25124 if (auto *ExtractIdx = dyn_cast<ConstantSDNode>(ExtractedV.getOperand(1)))
25125 if (ExtractIdx->getZExtValue() == 0) {
25126 MVT OrigVT = OrigV.getSimpleValueType();
25127 // Extract a subvector if necessary...
25128 if (OrigVT.getSizeInBits() > OpVT.getSizeInBits()) {
25129 int Ratio = OrigVT.getSizeInBits() / OpVT.getSizeInBits();
25130 OrigVT = MVT::getVectorVT(OrigVT.getVectorElementType(),
25131 OrigVT.getVectorNumElements() / Ratio);
25132 OrigV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigVT, OrigV,
25133 DAG.getIntPtrConstant(0, DL));
25135 Op = DAG.getBitcast(OpVT, OrigV);
25136 return DAG.getNode(X86ISD::VZEXT, DL, VT, Op);
25143 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
25144 DAGCombinerInfo &DCI) const {
25145 SelectionDAG &DAG = DCI.DAG;
25146 switch (N->getOpcode()) {
25148 case ISD::EXTRACT_VECTOR_ELT:
25149 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
25152 case X86ISD::SHRUNKBLEND:
25153 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
25154 case ISD::BITCAST: return PerformBITCASTCombine(N, DAG);
25155 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
25156 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
25157 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
25158 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
25159 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
25162 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
25163 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
25164 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
25165 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
25166 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
25167 case ISD::MLOAD: return PerformMLOADCombine(N, DAG, DCI, Subtarget);
25168 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
25169 case ISD::MSTORE: return PerformMSTORECombine(N, DAG, Subtarget);
25170 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, Subtarget);
25171 case ISD::UINT_TO_FP: return PerformUINT_TO_FPCombine(N, DAG, Subtarget);
25172 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
25173 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
25175 case X86ISD::FOR: return PerformFORCombine(N, DAG);
25177 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
25178 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
25179 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
25180 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
25181 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
25182 case ISD::ANY_EXTEND:
25183 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
25184 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
25185 case ISD::SIGN_EXTEND_INREG:
25186 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
25187 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
25188 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
25189 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
25190 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
25191 case X86ISD::SHUFP: // Handle all target specific shuffles
25192 case X86ISD::PALIGNR:
25193 case X86ISD::UNPCKH:
25194 case X86ISD::UNPCKL:
25195 case X86ISD::MOVHLPS:
25196 case X86ISD::MOVLHPS:
25197 case X86ISD::PSHUFB:
25198 case X86ISD::PSHUFD:
25199 case X86ISD::PSHUFHW:
25200 case X86ISD::PSHUFLW:
25201 case X86ISD::MOVSS:
25202 case X86ISD::MOVSD:
25203 case X86ISD::VPERMILPI:
25204 case X86ISD::VPERM2X128:
25205 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
25206 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
25207 case ISD::INTRINSIC_WO_CHAIN:
25208 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
25209 case X86ISD::INSERTPS: {
25210 if (getTargetMachine().getOptLevel() > CodeGenOpt::None)
25211 return PerformINSERTPSCombine(N, DAG, Subtarget);
25214 case X86ISD::BLENDI: return PerformBLENDICombine(N, DAG);
25220 /// isTypeDesirableForOp - Return true if the target has native support for
25221 /// the specified value type and it is 'desirable' to use the type for the
25222 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
25223 /// instruction encodings are longer and some i16 instructions are slow.
25224 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
25225 if (!isTypeLegal(VT))
25227 if (VT != MVT::i16)
25234 case ISD::SIGN_EXTEND:
25235 case ISD::ZERO_EXTEND:
25236 case ISD::ANY_EXTEND:
25249 /// IsDesirableToPromoteOp - This method query the target whether it is
25250 /// beneficial for dag combiner to promote the specified node. If true, it
25251 /// should return the desired promotion type by reference.
25252 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
25253 EVT VT = Op.getValueType();
25254 if (VT != MVT::i16)
25257 bool Promote = false;
25258 bool Commute = false;
25259 switch (Op.getOpcode()) {
25262 LoadSDNode *LD = cast<LoadSDNode>(Op);
25263 // If the non-extending load has a single use and it's not live out, then it
25264 // might be folded.
25265 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
25266 Op.hasOneUse()*/) {
25267 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
25268 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
25269 // The only case where we'd want to promote LOAD (rather then it being
25270 // promoted as an operand is when it's only use is liveout.
25271 if (UI->getOpcode() != ISD::CopyToReg)
25278 case ISD::SIGN_EXTEND:
25279 case ISD::ZERO_EXTEND:
25280 case ISD::ANY_EXTEND:
25285 SDValue N0 = Op.getOperand(0);
25286 // Look out for (store (shl (load), x)).
25287 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
25300 SDValue N0 = Op.getOperand(0);
25301 SDValue N1 = Op.getOperand(1);
25302 if (!Commute && MayFoldLoad(N1))
25304 // Avoid disabling potential load folding opportunities.
25305 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
25307 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
25317 //===----------------------------------------------------------------------===//
25318 // X86 Inline Assembly Support
25319 //===----------------------------------------------------------------------===//
25321 // Helper to match a string separated by whitespace.
25322 static bool matchAsm(StringRef S, ArrayRef<const char *> Pieces) {
25323 S = S.substr(S.find_first_not_of(" \t")); // Skip leading whitespace.
25325 for (StringRef Piece : Pieces) {
25326 if (!S.startswith(Piece)) // Check if the piece matches.
25329 S = S.substr(Piece.size());
25330 StringRef::size_type Pos = S.find_first_not_of(" \t");
25331 if (Pos == 0) // We matched a prefix.
25340 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
25342 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
25343 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
25344 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
25345 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
25347 if (AsmPieces.size() == 3)
25349 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
25356 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
25357 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
25359 std::string AsmStr = IA->getAsmString();
25361 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
25362 if (!Ty || Ty->getBitWidth() % 16 != 0)
25365 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
25366 SmallVector<StringRef, 4> AsmPieces;
25367 SplitString(AsmStr, AsmPieces, ";\n");
25369 switch (AsmPieces.size()) {
25370 default: return false;
25372 // FIXME: this should verify that we are targeting a 486 or better. If not,
25373 // we will turn this bswap into something that will be lowered to logical
25374 // ops instead of emitting the bswap asm. For now, we don't support 486 or
25375 // lower so don't worry about this.
25377 if (matchAsm(AsmPieces[0], {"bswap", "$0"}) ||
25378 matchAsm(AsmPieces[0], {"bswapl", "$0"}) ||
25379 matchAsm(AsmPieces[0], {"bswapq", "$0"}) ||
25380 matchAsm(AsmPieces[0], {"bswap", "${0:q}"}) ||
25381 matchAsm(AsmPieces[0], {"bswapl", "${0:q}"}) ||
25382 matchAsm(AsmPieces[0], {"bswapq", "${0:q}"})) {
25383 // No need to check constraints, nothing other than the equivalent of
25384 // "=r,0" would be valid here.
25385 return IntrinsicLowering::LowerToByteSwap(CI);
25388 // rorw $$8, ${0:w} --> llvm.bswap.i16
25389 if (CI->getType()->isIntegerTy(16) &&
25390 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
25391 (matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) ||
25392 matchAsm(AsmPieces[0], {"rolw", "$$8,", "${0:w}"}))) {
25394 StringRef ConstraintsStr = IA->getConstraintString();
25395 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
25396 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
25397 if (clobbersFlagRegisters(AsmPieces))
25398 return IntrinsicLowering::LowerToByteSwap(CI);
25402 if (CI->getType()->isIntegerTy(32) &&
25403 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
25404 matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) &&
25405 matchAsm(AsmPieces[1], {"rorl", "$$16,", "$0"}) &&
25406 matchAsm(AsmPieces[2], {"rorw", "$$8,", "${0:w}"})) {
25408 StringRef ConstraintsStr = IA->getConstraintString();
25409 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
25410 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
25411 if (clobbersFlagRegisters(AsmPieces))
25412 return IntrinsicLowering::LowerToByteSwap(CI);
25415 if (CI->getType()->isIntegerTy(64)) {
25416 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
25417 if (Constraints.size() >= 2 &&
25418 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
25419 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
25420 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
25421 if (matchAsm(AsmPieces[0], {"bswap", "%eax"}) &&
25422 matchAsm(AsmPieces[1], {"bswap", "%edx"}) &&
25423 matchAsm(AsmPieces[2], {"xchgl", "%eax,", "%edx"}))
25424 return IntrinsicLowering::LowerToByteSwap(CI);
25432 /// getConstraintType - Given a constraint letter, return the type of
25433 /// constraint it is for this target.
25434 X86TargetLowering::ConstraintType
25435 X86TargetLowering::getConstraintType(StringRef Constraint) const {
25436 if (Constraint.size() == 1) {
25437 switch (Constraint[0]) {
25448 return C_RegisterClass;
25472 return TargetLowering::getConstraintType(Constraint);
25475 /// Examine constraint type and operand type and determine a weight value.
25476 /// This object must already have been set up with the operand type
25477 /// and the current alternative constraint selected.
25478 TargetLowering::ConstraintWeight
25479 X86TargetLowering::getSingleConstraintMatchWeight(
25480 AsmOperandInfo &info, const char *constraint) const {
25481 ConstraintWeight weight = CW_Invalid;
25482 Value *CallOperandVal = info.CallOperandVal;
25483 // If we don't have a value, we can't do a match,
25484 // but allow it at the lowest weight.
25485 if (!CallOperandVal)
25487 Type *type = CallOperandVal->getType();
25488 // Look at the constraint type.
25489 switch (*constraint) {
25491 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
25502 if (CallOperandVal->getType()->isIntegerTy())
25503 weight = CW_SpecificReg;
25508 if (type->isFloatingPointTy())
25509 weight = CW_SpecificReg;
25512 if (type->isX86_MMXTy() && Subtarget->hasMMX())
25513 weight = CW_SpecificReg;
25517 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
25518 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
25519 weight = CW_Register;
25522 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
25523 if (C->getZExtValue() <= 31)
25524 weight = CW_Constant;
25528 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25529 if (C->getZExtValue() <= 63)
25530 weight = CW_Constant;
25534 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25535 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
25536 weight = CW_Constant;
25540 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25541 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
25542 weight = CW_Constant;
25546 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25547 if (C->getZExtValue() <= 3)
25548 weight = CW_Constant;
25552 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25553 if (C->getZExtValue() <= 0xff)
25554 weight = CW_Constant;
25559 if (isa<ConstantFP>(CallOperandVal)) {
25560 weight = CW_Constant;
25564 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25565 if ((C->getSExtValue() >= -0x80000000LL) &&
25566 (C->getSExtValue() <= 0x7fffffffLL))
25567 weight = CW_Constant;
25571 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25572 if (C->getZExtValue() <= 0xffffffff)
25573 weight = CW_Constant;
25580 /// LowerXConstraint - try to replace an X constraint, which matches anything,
25581 /// with another that has more specific requirements based on the type of the
25582 /// corresponding operand.
25583 const char *X86TargetLowering::
25584 LowerXConstraint(EVT ConstraintVT) const {
25585 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
25586 // 'f' like normal targets.
25587 if (ConstraintVT.isFloatingPoint()) {
25588 if (Subtarget->hasSSE2())
25590 if (Subtarget->hasSSE1())
25594 return TargetLowering::LowerXConstraint(ConstraintVT);
25597 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
25598 /// vector. If it is invalid, don't add anything to Ops.
25599 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
25600 std::string &Constraint,
25601 std::vector<SDValue>&Ops,
25602 SelectionDAG &DAG) const {
25605 // Only support length 1 constraints for now.
25606 if (Constraint.length() > 1) return;
25608 char ConstraintLetter = Constraint[0];
25609 switch (ConstraintLetter) {
25612 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25613 if (C->getZExtValue() <= 31) {
25614 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
25615 Op.getValueType());
25621 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25622 if (C->getZExtValue() <= 63) {
25623 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
25624 Op.getValueType());
25630 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25631 if (isInt<8>(C->getSExtValue())) {
25632 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
25633 Op.getValueType());
25639 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25640 if (C->getZExtValue() == 0xff || C->getZExtValue() == 0xffff ||
25641 (Subtarget->is64Bit() && C->getZExtValue() == 0xffffffff)) {
25642 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
25643 Op.getValueType());
25649 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25650 if (C->getZExtValue() <= 3) {
25651 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
25652 Op.getValueType());
25658 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25659 if (C->getZExtValue() <= 255) {
25660 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
25661 Op.getValueType());
25667 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25668 if (C->getZExtValue() <= 127) {
25669 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
25670 Op.getValueType());
25676 // 32-bit signed value
25677 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25678 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
25679 C->getSExtValue())) {
25680 // Widen to 64 bits here to get it sign extended.
25681 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op), MVT::i64);
25684 // FIXME gcc accepts some relocatable values here too, but only in certain
25685 // memory models; it's complicated.
25690 // 32-bit unsigned value
25691 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25692 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
25693 C->getZExtValue())) {
25694 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
25695 Op.getValueType());
25699 // FIXME gcc accepts some relocatable values here too, but only in certain
25700 // memory models; it's complicated.
25704 // Literal immediates are always ok.
25705 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
25706 // Widen to 64 bits here to get it sign extended.
25707 Result = DAG.getTargetConstant(CST->getSExtValue(), SDLoc(Op), MVT::i64);
25711 // In any sort of PIC mode addresses need to be computed at runtime by
25712 // adding in a register or some sort of table lookup. These can't
25713 // be used as immediates.
25714 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
25717 // If we are in non-pic codegen mode, we allow the address of a global (with
25718 // an optional displacement) to be used with 'i'.
25719 GlobalAddressSDNode *GA = nullptr;
25720 int64_t Offset = 0;
25722 // Match either (GA), (GA+C), (GA+C1+C2), etc.
25724 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
25725 Offset += GA->getOffset();
25727 } else if (Op.getOpcode() == ISD::ADD) {
25728 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
25729 Offset += C->getZExtValue();
25730 Op = Op.getOperand(0);
25733 } else if (Op.getOpcode() == ISD::SUB) {
25734 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
25735 Offset += -C->getZExtValue();
25736 Op = Op.getOperand(0);
25741 // Otherwise, this isn't something we can handle, reject it.
25745 const GlobalValue *GV = GA->getGlobal();
25746 // If we require an extra load to get this address, as in PIC mode, we
25747 // can't accept it.
25748 if (isGlobalStubReference(
25749 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
25752 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
25753 GA->getValueType(0), Offset);
25758 if (Result.getNode()) {
25759 Ops.push_back(Result);
25762 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
25765 std::pair<unsigned, const TargetRegisterClass *>
25766 X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
25767 StringRef Constraint,
25769 // First, see if this is a constraint that directly corresponds to an LLVM
25771 if (Constraint.size() == 1) {
25772 // GCC Constraint Letters
25773 switch (Constraint[0]) {
25775 // TODO: Slight differences here in allocation order and leaving
25776 // RIP in the class. Do they matter any more here than they do
25777 // in the normal allocation?
25778 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
25779 if (Subtarget->is64Bit()) {
25780 if (VT == MVT::i32 || VT == MVT::f32)
25781 return std::make_pair(0U, &X86::GR32RegClass);
25782 if (VT == MVT::i16)
25783 return std::make_pair(0U, &X86::GR16RegClass);
25784 if (VT == MVT::i8 || VT == MVT::i1)
25785 return std::make_pair(0U, &X86::GR8RegClass);
25786 if (VT == MVT::i64 || VT == MVT::f64)
25787 return std::make_pair(0U, &X86::GR64RegClass);
25790 // 32-bit fallthrough
25791 case 'Q': // Q_REGS
25792 if (VT == MVT::i32 || VT == MVT::f32)
25793 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
25794 if (VT == MVT::i16)
25795 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
25796 if (VT == MVT::i8 || VT == MVT::i1)
25797 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
25798 if (VT == MVT::i64)
25799 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
25801 case 'r': // GENERAL_REGS
25802 case 'l': // INDEX_REGS
25803 if (VT == MVT::i8 || VT == MVT::i1)
25804 return std::make_pair(0U, &X86::GR8RegClass);
25805 if (VT == MVT::i16)
25806 return std::make_pair(0U, &X86::GR16RegClass);
25807 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
25808 return std::make_pair(0U, &X86::GR32RegClass);
25809 return std::make_pair(0U, &X86::GR64RegClass);
25810 case 'R': // LEGACY_REGS
25811 if (VT == MVT::i8 || VT == MVT::i1)
25812 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
25813 if (VT == MVT::i16)
25814 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
25815 if (VT == MVT::i32 || !Subtarget->is64Bit())
25816 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
25817 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
25818 case 'f': // FP Stack registers.
25819 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
25820 // value to the correct fpstack register class.
25821 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
25822 return std::make_pair(0U, &X86::RFP32RegClass);
25823 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
25824 return std::make_pair(0U, &X86::RFP64RegClass);
25825 return std::make_pair(0U, &X86::RFP80RegClass);
25826 case 'y': // MMX_REGS if MMX allowed.
25827 if (!Subtarget->hasMMX()) break;
25828 return std::make_pair(0U, &X86::VR64RegClass);
25829 case 'Y': // SSE_REGS if SSE2 allowed
25830 if (!Subtarget->hasSSE2()) break;
25832 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
25833 if (!Subtarget->hasSSE1()) break;
25835 switch (VT.SimpleTy) {
25837 // Scalar SSE types.
25840 return std::make_pair(0U, &X86::FR32RegClass);
25843 return std::make_pair(0U, &X86::FR64RegClass);
25851 return std::make_pair(0U, &X86::VR128RegClass);
25859 return std::make_pair(0U, &X86::VR256RegClass);
25864 return std::make_pair(0U, &X86::VR512RegClass);
25870 // Use the default implementation in TargetLowering to convert the register
25871 // constraint into a member of a register class.
25872 std::pair<unsigned, const TargetRegisterClass*> Res;
25873 Res = TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
25875 // Not found as a standard register?
25877 // Map st(0) -> st(7) -> ST0
25878 if (Constraint.size() == 7 && Constraint[0] == '{' &&
25879 tolower(Constraint[1]) == 's' &&
25880 tolower(Constraint[2]) == 't' &&
25881 Constraint[3] == '(' &&
25882 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
25883 Constraint[5] == ')' &&
25884 Constraint[6] == '}') {
25886 Res.first = X86::FP0+Constraint[4]-'0';
25887 Res.second = &X86::RFP80RegClass;
25891 // GCC allows "st(0)" to be called just plain "st".
25892 if (StringRef("{st}").equals_lower(Constraint)) {
25893 Res.first = X86::FP0;
25894 Res.second = &X86::RFP80RegClass;
25899 if (StringRef("{flags}").equals_lower(Constraint)) {
25900 Res.first = X86::EFLAGS;
25901 Res.second = &X86::CCRRegClass;
25905 // 'A' means EAX + EDX.
25906 if (Constraint == "A") {
25907 Res.first = X86::EAX;
25908 Res.second = &X86::GR32_ADRegClass;
25914 // Otherwise, check to see if this is a register class of the wrong value
25915 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
25916 // turn into {ax},{dx}.
25917 // MVT::Other is used to specify clobber names.
25918 if (Res.second->hasType(VT) || VT == MVT::Other)
25919 return Res; // Correct type already, nothing to do.
25921 // Get a matching integer of the correct size. i.e. "ax" with MVT::32 should
25922 // return "eax". This should even work for things like getting 64bit integer
25923 // registers when given an f64 type.
25924 const TargetRegisterClass *Class = Res.second;
25925 if (Class == &X86::GR8RegClass || Class == &X86::GR16RegClass ||
25926 Class == &X86::GR32RegClass || Class == &X86::GR64RegClass) {
25927 unsigned Size = VT.getSizeInBits();
25928 MVT::SimpleValueType SimpleTy = Size == 1 || Size == 8 ? MVT::i8
25929 : Size == 16 ? MVT::i16
25930 : Size == 32 ? MVT::i32
25931 : Size == 64 ? MVT::i64
25933 unsigned DestReg = getX86SubSuperRegisterOrZero(Res.first, SimpleTy);
25935 Res.first = DestReg;
25936 Res.second = SimpleTy == MVT::i8 ? &X86::GR8RegClass
25937 : SimpleTy == MVT::i16 ? &X86::GR16RegClass
25938 : SimpleTy == MVT::i32 ? &X86::GR32RegClass
25939 : &X86::GR64RegClass;
25940 assert(Res.second->contains(Res.first) && "Register in register class");
25942 // No register found/type mismatch.
25944 Res.second = nullptr;
25946 } else if (Class == &X86::FR32RegClass || Class == &X86::FR64RegClass ||
25947 Class == &X86::VR128RegClass || Class == &X86::VR256RegClass ||
25948 Class == &X86::FR32XRegClass || Class == &X86::FR64XRegClass ||
25949 Class == &X86::VR128XRegClass || Class == &X86::VR256XRegClass ||
25950 Class == &X86::VR512RegClass) {
25951 // Handle references to XMM physical registers that got mapped into the
25952 // wrong class. This can happen with constraints like {xmm0} where the
25953 // target independent register mapper will just pick the first match it can
25954 // find, ignoring the required type.
25956 if (VT == MVT::f32 || VT == MVT::i32)
25957 Res.second = &X86::FR32RegClass;
25958 else if (VT == MVT::f64 || VT == MVT::i64)
25959 Res.second = &X86::FR64RegClass;
25960 else if (X86::VR128RegClass.hasType(VT))
25961 Res.second = &X86::VR128RegClass;
25962 else if (X86::VR256RegClass.hasType(VT))
25963 Res.second = &X86::VR256RegClass;
25964 else if (X86::VR512RegClass.hasType(VT))
25965 Res.second = &X86::VR512RegClass;
25967 // Type mismatch and not a clobber: Return an error;
25969 Res.second = nullptr;
25976 int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
25978 unsigned AS) const {
25979 // Scaling factors are not free at all.
25980 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
25981 // will take 2 allocations in the out of order engine instead of 1
25982 // for plain addressing mode, i.e. inst (reg1).
25984 // vaddps (%rsi,%drx), %ymm0, %ymm1
25985 // Requires two allocations (one for the load, one for the computation)
25987 // vaddps (%rsi), %ymm0, %ymm1
25988 // Requires just 1 allocation, i.e., freeing allocations for other operations
25989 // and having less micro operations to execute.
25991 // For some X86 architectures, this is even worse because for instance for
25992 // stores, the complex addressing mode forces the instruction to use the
25993 // "load" ports instead of the dedicated "store" port.
25994 // E.g., on Haswell:
25995 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
25996 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
25997 if (isLegalAddressingMode(AM, Ty, AS))
25998 // Scale represents reg2 * scale, thus account for 1
25999 // as soon as we use a second register.
26000 return AM.Scale != 0;
26004 bool X86TargetLowering::isTargetFTOL() const {
26005 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();