1 //===- X86ISelDAGToDAG.cpp - A DAG pattern matching inst selector for X86 -===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the Evan Cheng and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a DAG pattern matching instruction selector for X86,
11 // converting from a legalized dag to a X86 dag.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "isel"
17 #include "X86InstrBuilder.h"
18 #include "X86ISelLowering.h"
19 #include "X86RegisterInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/GlobalValue.h"
23 #include "llvm/Instructions.h"
24 #include "llvm/Support/CFG.h"
25 #include "llvm/CodeGen/MachineConstantPool.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineInstrBuilder.h"
29 #include "llvm/CodeGen/SSARegMap.h"
30 #include "llvm/CodeGen/SelectionDAGISel.h"
31 #include "llvm/Target/TargetMachine.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/ADT/Statistic.h"
38 //===----------------------------------------------------------------------===//
39 // Pattern Matcher Implementation
40 //===----------------------------------------------------------------------===//
43 /// X86ISelAddressMode - This corresponds to X86AddressMode, but uses
44 /// SDOperand's instead of register numbers for the leaves of the matched
46 struct X86ISelAddressMode {
52 struct { // This is really a union, discriminated by BaseType!
62 unsigned Align; // CP alignment.
65 : BaseType(RegBase), Scale(1), IndexReg(), Disp(0), GV(0),
73 NumFPKill("x86-codegen", "Number of FP_REG_KILL instructions added");
75 //===--------------------------------------------------------------------===//
76 /// ISel - X86 specific code to select X86 machine instructions for
77 /// SelectionDAG operations.
79 class X86DAGToDAGISel : public SelectionDAGISel {
80 /// ContainsFPCode - Every instruction we select that uses or defines a FP
81 /// register should set this to true.
84 /// X86Lowering - This object fully describes how to lower LLVM code to an
85 /// X86-specific SelectionDAG.
86 X86TargetLowering X86Lowering;
88 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
89 /// make the right decision when generating code for different targets.
90 const X86Subtarget *Subtarget;
92 unsigned GlobalBaseReg;
94 X86DAGToDAGISel(X86TargetMachine &TM)
95 : SelectionDAGISel(X86Lowering),
96 X86Lowering(*TM.getTargetLowering()) {
97 Subtarget = &TM.getSubtarget<X86Subtarget>();
100 virtual bool runOnFunction(Function &Fn) {
101 // Make sure we re-emit a set of the global base reg if necessary
103 return SelectionDAGISel::runOnFunction(Fn);
106 virtual const char *getPassName() const {
107 return "X86 DAG->DAG Instruction Selection";
110 /// InstructionSelectBasicBlock - This callback is invoked by
111 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
112 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
114 virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF);
116 // Include the pieces autogenerated from the target description.
117 #include "X86GenDAGISel.inc"
120 void Select(SDOperand &Result, SDOperand N);
122 bool MatchAddress(SDOperand N, X86ISelAddressMode &AM, bool isRoot = true);
123 bool SelectAddr(SDOperand N, SDOperand &Base, SDOperand &Scale,
124 SDOperand &Index, SDOperand &Disp);
125 bool SelectLEAAddr(SDOperand N, SDOperand &Base, SDOperand &Scale,
126 SDOperand &Index, SDOperand &Disp);
127 bool TryFoldLoad(SDOperand P, SDOperand N,
128 SDOperand &Base, SDOperand &Scale,
129 SDOperand &Index, SDOperand &Disp);
131 inline void getAddressOperands(X86ISelAddressMode &AM, SDOperand &Base,
132 SDOperand &Scale, SDOperand &Index,
134 Base = (AM.BaseType == X86ISelAddressMode::FrameIndexBase) ?
135 CurDAG->getTargetFrameIndex(AM.Base.FrameIndex, MVT::i32) : AM.Base.Reg;
136 Scale = getI8Imm(AM.Scale);
138 Disp = AM.GV ? CurDAG->getTargetGlobalAddress(AM.GV, MVT::i32, AM.Disp)
140 CurDAG->getTargetConstantPool(AM.CP, MVT::i32, AM.Align, AM.Disp)
141 : getI32Imm(AM.Disp));
144 /// getI8Imm - Return a target constant with the specified value, of type
146 inline SDOperand getI8Imm(unsigned Imm) {
147 return CurDAG->getTargetConstant(Imm, MVT::i8);
150 /// getI16Imm - Return a target constant with the specified value, of type
152 inline SDOperand getI16Imm(unsigned Imm) {
153 return CurDAG->getTargetConstant(Imm, MVT::i16);
156 /// getI32Imm - Return a target constant with the specified value, of type
158 inline SDOperand getI32Imm(unsigned Imm) {
159 return CurDAG->getTargetConstant(Imm, MVT::i32);
162 /// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC
163 /// base register. Return the virtual register that holds this value.
164 SDOperand getGlobalBaseReg();
172 /// InstructionSelectBasicBlock - This callback is invoked by SelectionDAGISel
173 /// when it has created a SelectionDAG for us to codegen.
174 void X86DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
176 MachineFunction::iterator FirstMBB = BB;
178 // Codegen the basic block.
180 DEBUG(std::cerr << "===== Instruction selection begins:\n");
183 DAG.setRoot(SelectRoot(DAG.getRoot()));
185 DEBUG(std::cerr << "===== Instruction selection ends:\n");
188 DAG.RemoveDeadNodes();
190 // Emit machine code to BB.
191 ScheduleAndEmitDAG(DAG);
193 // If we are emitting FP stack code, scan the basic block to determine if this
194 // block defines any FP values. If so, put an FP_REG_KILL instruction before
195 // the terminator of the block.
196 if (!Subtarget->hasSSE2()) {
197 // Note that FP stack instructions *are* used in SSE code when returning
198 // values, but these are not live out of the basic block, so we don't need
199 // an FP_REG_KILL in this case either.
200 bool ContainsFPCode = false;
202 // Scan all of the machine instructions in these MBBs, checking for FP
204 MachineFunction::iterator MBBI = FirstMBB;
206 for (MachineBasicBlock::iterator I = MBBI->begin(), E = MBBI->end();
207 !ContainsFPCode && I != E; ++I) {
208 for (unsigned op = 0, e = I->getNumOperands(); op != e; ++op) {
209 if (I->getOperand(op).isRegister() && I->getOperand(op).isDef() &&
210 MRegisterInfo::isVirtualRegister(I->getOperand(op).getReg()) &&
211 RegMap->getRegClass(I->getOperand(0).getReg()) ==
212 X86::RFPRegisterClass) {
213 ContainsFPCode = true;
218 } while (!ContainsFPCode && &*(MBBI++) != BB);
220 // Check PHI nodes in successor blocks. These PHI's will be lowered to have
221 // a copy of the input value in this block.
222 if (!ContainsFPCode) {
223 // Final check, check LLVM BB's that are successors to the LLVM BB
224 // corresponding to BB for FP PHI nodes.
225 const BasicBlock *LLVMBB = BB->getBasicBlock();
227 for (succ_const_iterator SI = succ_begin(LLVMBB), E = succ_end(LLVMBB);
228 !ContainsFPCode && SI != E; ++SI) {
229 for (BasicBlock::const_iterator II = SI->begin();
230 (PN = dyn_cast<PHINode>(II)); ++II) {
231 if (PN->getType()->isFloatingPoint()) {
232 ContainsFPCode = true;
239 // Finally, if we found any FP code, emit the FP_REG_KILL instruction.
240 if (ContainsFPCode) {
241 BuildMI(*BB, BB->getFirstTerminator(), X86::FP_REG_KILL, 0);
247 /// EmitSpecialCodeForMain - Emit any code that needs to be executed only in
248 /// the main function.
249 static void EmitSpecialCodeForMain(MachineBasicBlock *BB,
250 MachineFrameInfo *MFI) {
251 // Switch the FPU to 64-bit precision mode for better compatibility and speed.
252 int CWFrameIdx = MFI->CreateStackObject(2, 2);
253 addFrameReference(BuildMI(BB, X86::FNSTCW16m, 4), CWFrameIdx);
255 // Set the high part to be 64-bit precision.
256 addFrameReference(BuildMI(BB, X86::MOV8mi, 5),
257 CWFrameIdx, 1).addImm(2);
259 // Reload the modified control word now.
260 addFrameReference(BuildMI(BB, X86::FLDCW16m, 4), CWFrameIdx);
263 void X86DAGToDAGISel::EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {
264 // If this is main, emit special code for main.
265 MachineBasicBlock *BB = MF.begin();
266 if (Fn.hasExternalLinkage() && Fn.getName() == "main")
267 EmitSpecialCodeForMain(BB, MF.getFrameInfo());
270 /// MatchAddress - Add the specified node to the specified addressing mode,
271 /// returning true if it cannot be done. This just pattern matches for the
273 bool X86DAGToDAGISel::MatchAddress(SDOperand N, X86ISelAddressMode &AM,
275 bool Available = false;
276 // If N has already been selected, reuse the result unless in some very
278 std::map<SDOperand, SDOperand>::iterator CGMI= CodeGenMap.find(N.getValue(0));
279 if (CGMI != CodeGenMap.end()) {
283 switch (N.getOpcode()) {
286 AM.Disp += cast<ConstantSDNode>(N)->getValue();
289 case X86ISD::Wrapper:
290 // If both base and index components have been picked, we can't fit
291 // the result available in the register in the addressing mode. Duplicate
292 // GlobalAddress or ConstantPool as displacement.
293 if (!Available || (AM.Base.Reg.Val && AM.IndexReg.Val)) {
294 if (ConstantPoolSDNode *CP =
295 dyn_cast<ConstantPoolSDNode>(N.getOperand(0))) {
298 AM.Align = CP->getAlignment();
299 AM.Disp += CP->getOffset();
302 } else if (GlobalAddressSDNode *G =
303 dyn_cast<GlobalAddressSDNode>(N.getOperand(0))) {
305 AM.GV = G->getGlobal();
306 AM.Disp += G->getOffset();
313 case ISD::FrameIndex:
314 if (AM.BaseType == X86ISelAddressMode::RegBase && AM.Base.Reg.Val == 0) {
315 AM.BaseType = X86ISelAddressMode::FrameIndexBase;
316 AM.Base.FrameIndex = cast<FrameIndexSDNode>(N)->getIndex();
322 if (!Available && AM.IndexReg.Val == 0 && AM.Scale == 1)
323 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.Val->getOperand(1))) {
324 unsigned Val = CN->getValue();
325 if (Val == 1 || Val == 2 || Val == 3) {
327 SDOperand ShVal = N.Val->getOperand(0);
329 // Okay, we know that we have a scale by now. However, if the scaled
330 // value is an add of something and a constant, we can fold the
331 // constant into the disp field here.
332 if (ShVal.Val->getOpcode() == ISD::ADD && ShVal.hasOneUse() &&
333 isa<ConstantSDNode>(ShVal.Val->getOperand(1))) {
334 AM.IndexReg = ShVal.Val->getOperand(0);
335 ConstantSDNode *AddVal =
336 cast<ConstantSDNode>(ShVal.Val->getOperand(1));
337 AM.Disp += AddVal->getValue() << Val;
347 // X*[3,5,9] -> X+X*[2,4,8]
349 AM.BaseType == X86ISelAddressMode::RegBase &&
350 AM.Base.Reg.Val == 0 &&
351 AM.IndexReg.Val == 0)
352 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.Val->getOperand(1)))
353 if (CN->getValue() == 3 || CN->getValue() == 5 || CN->getValue() == 9) {
354 AM.Scale = unsigned(CN->getValue())-1;
356 SDOperand MulVal = N.Val->getOperand(0);
359 // Okay, we know that we have a scale by now. However, if the scaled
360 // value is an add of something and a constant, we can fold the
361 // constant into the disp field here.
362 if (MulVal.Val->getOpcode() == ISD::ADD && MulVal.hasOneUse() &&
363 isa<ConstantSDNode>(MulVal.Val->getOperand(1))) {
364 Reg = MulVal.Val->getOperand(0);
365 ConstantSDNode *AddVal =
366 cast<ConstantSDNode>(MulVal.Val->getOperand(1));
367 AM.Disp += AddVal->getValue() * CN->getValue();
369 Reg = N.Val->getOperand(0);
372 AM.IndexReg = AM.Base.Reg = Reg;
379 X86ISelAddressMode Backup = AM;
380 if (!MatchAddress(N.Val->getOperand(0), AM, false) &&
381 !MatchAddress(N.Val->getOperand(1), AM, false))
384 if (!MatchAddress(N.Val->getOperand(1), AM, false) &&
385 !MatchAddress(N.Val->getOperand(0), AM, false))
393 // Is the base register already occupied?
394 if (AM.BaseType != X86ISelAddressMode::RegBase || AM.Base.Reg.Val) {
395 // If so, check to see if the scale index register is set.
396 if (AM.IndexReg.Val == 0) {
402 // Otherwise, we cannot select it.
406 // Default, generate it as a register.
407 AM.BaseType = X86ISelAddressMode::RegBase;
412 /// SelectAddr - returns true if it is able pattern match an addressing mode.
413 /// It returns the operands which make up the maximal addressing mode it can
414 /// match by reference.
415 bool X86DAGToDAGISel::SelectAddr(SDOperand N, SDOperand &Base, SDOperand &Scale,
416 SDOperand &Index, SDOperand &Disp) {
417 X86ISelAddressMode AM;
418 if (MatchAddress(N, AM))
421 if (AM.BaseType == X86ISelAddressMode::RegBase) {
422 if (!AM.Base.Reg.Val)
423 AM.Base.Reg = CurDAG->getRegister(0, MVT::i32);
426 if (!AM.IndexReg.Val)
427 AM.IndexReg = CurDAG->getRegister(0, MVT::i32);
429 getAddressOperands(AM, Base, Scale, Index, Disp);
434 /// SelectLEAAddr - it calls SelectAddr and determines if the maximal addressing
435 /// mode it matches can be cost effectively emitted as an LEA instruction.
436 /// For X86, it always is unless it's just a (Reg + const).
437 bool X86DAGToDAGISel::SelectLEAAddr(SDOperand N, SDOperand &Base,
439 SDOperand &Index, SDOperand &Disp) {
440 X86ISelAddressMode AM;
441 if (MatchAddress(N, AM))
444 unsigned Complexity = 0;
445 if (AM.BaseType == X86ISelAddressMode::RegBase)
449 AM.Base.Reg = CurDAG->getRegister(0, MVT::i32);
450 else if (AM.BaseType == X86ISelAddressMode::FrameIndexBase)
456 AM.IndexReg = CurDAG->getRegister(0, MVT::i32);
460 // Don't match just leal(,%reg,2). It's cheaper to do addl %reg, %reg
461 else if (AM.Scale > 1)
464 // FIXME: We are artificially lowering the criteria to turn ADD %reg, $GA
465 // to a LEA. This is determined with some expermentation but is by no means
466 // optimal (especially for code size consideration). LEA is nice because of
467 // its three-address nature. Tweak the cost function again when we can run
468 // convertToThreeAddress() at register allocation time.
472 if (AM.Disp && (AM.Base.Reg.Val || AM.IndexReg.Val))
475 if (Complexity > 2) {
476 getAddressOperands(AM, Base, Scale, Index, Disp);
483 bool X86DAGToDAGISel::TryFoldLoad(SDOperand P, SDOperand N,
484 SDOperand &Base, SDOperand &Scale,
485 SDOperand &Index, SDOperand &Disp) {
486 if (N.getOpcode() == ISD::LOAD &&
488 !CodeGenMap.count(N.getValue(0)) &&
489 (P.getNumOperands() == 1 || !isNonImmUse(P.Val, N.Val)))
490 return SelectAddr(N.getOperand(1), Base, Scale, Index, Disp);
494 static bool isRegister0(SDOperand Op) {
495 if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op))
496 return (R->getReg() == 0);
500 /// getGlobalBaseReg - Output the instructions required to put the
501 /// base address to use for accessing globals into a register.
503 SDOperand X86DAGToDAGISel::getGlobalBaseReg() {
504 if (!GlobalBaseReg) {
505 // Insert the set of GlobalBaseReg into the first MBB of the function
506 MachineBasicBlock &FirstMBB = BB->getParent()->front();
507 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
508 SSARegMap *RegMap = BB->getParent()->getSSARegMap();
509 // FIXME: when we get to LP64, we will need to create the appropriate
510 // type of register here.
511 GlobalBaseReg = RegMap->createVirtualRegister(X86::R32RegisterClass);
512 BuildMI(FirstMBB, MBBI, X86::MovePCtoStack, 0);
513 BuildMI(FirstMBB, MBBI, X86::POP32r, 1, GlobalBaseReg);
515 return CurDAG->getRegister(GlobalBaseReg, MVT::i32);
518 void X86DAGToDAGISel::Select(SDOperand &Result, SDOperand N) {
519 SDNode *Node = N.Val;
520 MVT::ValueType NVT = Node->getValueType(0);
522 unsigned Opcode = Node->getOpcode();
525 DEBUG(std::cerr << std::string(Indent, ' '));
526 DEBUG(std::cerr << "Selecting: ");
527 DEBUG(Node->dump(CurDAG));
528 DEBUG(std::cerr << "\n");
532 if (Opcode >= ISD::BUILTIN_OP_END && Opcode < X86ISD::FIRST_NUMBER) {
535 DEBUG(std::cerr << std::string(Indent-2, ' '));
536 DEBUG(std::cerr << "== ");
537 DEBUG(Node->dump(CurDAG));
538 DEBUG(std::cerr << "\n");
541 return; // Already selected.
544 std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(N);
545 if (CGMI != CodeGenMap.end()) {
546 Result = CGMI->second;
548 DEBUG(std::cerr << std::string(Indent-2, ' '));
549 DEBUG(std::cerr << "== ");
550 DEBUG(Result.Val->dump(CurDAG));
551 DEBUG(std::cerr << "\n");
559 case X86ISD::GlobalBaseReg:
560 Result = getGlobalBaseReg();
564 // Turn ADD X, c to MOV32ri X+c. This cannot be done with tblgen'd
565 // code and is matched first so to prevent it from being turned into
567 SDOperand N0 = N.getOperand(0);
568 SDOperand N1 = N.getOperand(1);
569 if (N.Val->getValueType(0) == MVT::i32 &&
570 N0.getOpcode() == X86ISD::Wrapper &&
571 N1.getOpcode() == ISD::Constant) {
572 unsigned Offset = (unsigned)cast<ConstantSDNode>(N1)->getValue();
574 // TODO: handle ExternalSymbolSDNode.
575 if (GlobalAddressSDNode *G =
576 dyn_cast<GlobalAddressSDNode>(N0.getOperand(0))) {
577 C = CurDAG->getTargetGlobalAddress(G->getGlobal(), MVT::i32,
578 G->getOffset() + Offset);
579 } else if (ConstantPoolSDNode *CP =
580 dyn_cast<ConstantPoolSDNode>(N0.getOperand(0))) {
581 C = CurDAG->getTargetConstantPool(CP->get(), MVT::i32,
583 CP->getOffset()+Offset);
587 if (N.Val->hasOneUse()) {
588 Result = CurDAG->SelectNodeTo(N.Val, X86::MOV32ri, MVT::i32, C);
590 SDNode *ResNode = CurDAG->getTargetNode(X86::MOV32ri, MVT::i32, C);
591 Result = CodeGenMap[N] = SDOperand(ResNode, 0);
597 // Other cases are handled by auto-generated code.
603 if (Opcode == ISD::MULHU)
605 default: assert(0 && "Unsupported VT!");
606 case MVT::i8: Opc = X86::MUL8r; MOpc = X86::MUL8m; break;
607 case MVT::i16: Opc = X86::MUL16r; MOpc = X86::MUL16m; break;
608 case MVT::i32: Opc = X86::MUL32r; MOpc = X86::MUL32m; break;
612 default: assert(0 && "Unsupported VT!");
613 case MVT::i8: Opc = X86::IMUL8r; MOpc = X86::IMUL8m; break;
614 case MVT::i16: Opc = X86::IMUL16r; MOpc = X86::IMUL16m; break;
615 case MVT::i32: Opc = X86::IMUL32r; MOpc = X86::IMUL32m; break;
618 unsigned LoReg, HiReg;
620 default: assert(0 && "Unsupported VT!");
621 case MVT::i8: LoReg = X86::AL; HiReg = X86::AH; break;
622 case MVT::i16: LoReg = X86::AX; HiReg = X86::DX; break;
623 case MVT::i32: LoReg = X86::EAX; HiReg = X86::EDX; break;
626 SDOperand N0 = Node->getOperand(0);
627 SDOperand N1 = Node->getOperand(1);
629 bool foldedLoad = false;
630 SDOperand Tmp0, Tmp1, Tmp2, Tmp3;
631 foldedLoad = TryFoldLoad(N, N1, Tmp0, Tmp1, Tmp2, Tmp3);
632 // MULHU and MULHS are commmutative
634 foldedLoad = TryFoldLoad(N, N0, Tmp0, Tmp1, Tmp2, Tmp3);
636 N0 = Node->getOperand(1);
637 N1 = Node->getOperand(0);
643 Select(Chain, N1.getOperand(0));
645 Chain = CurDAG->getEntryNode();
647 SDOperand InFlag(0, 0);
649 Chain = CurDAG->getCopyToReg(Chain, CurDAG->getRegister(LoReg, NVT),
651 InFlag = Chain.getValue(1);
659 CurDAG->getTargetNode(MOpc, MVT::Other, MVT::Flag, Tmp0, Tmp1,
660 Tmp2, Tmp3, Chain, InFlag);
661 Chain = SDOperand(CNode, 0);
662 InFlag = SDOperand(CNode, 1);
666 SDOperand(CurDAG->getTargetNode(Opc, MVT::Flag, N1, InFlag), 0);
669 Result = CurDAG->getCopyFromReg(Chain, HiReg, NVT, InFlag);
670 CodeGenMap[N.getValue(0)] = Result;
672 CodeGenMap[N1.getValue(1)] = Result.getValue(1);
673 AddHandleReplacement(N1.Val, 1, Result.Val, 1);
677 DEBUG(std::cerr << std::string(Indent-2, ' '));
678 DEBUG(std::cerr << "== ");
679 DEBUG(Result.Val->dump(CurDAG));
680 DEBUG(std::cerr << "\n");
690 bool isSigned = Opcode == ISD::SDIV || Opcode == ISD::SREM;
691 bool isDiv = Opcode == ISD::SDIV || Opcode == ISD::UDIV;
694 default: assert(0 && "Unsupported VT!");
695 case MVT::i8: Opc = X86::DIV8r; MOpc = X86::DIV8m; break;
696 case MVT::i16: Opc = X86::DIV16r; MOpc = X86::DIV16m; break;
697 case MVT::i32: Opc = X86::DIV32r; MOpc = X86::DIV32m; break;
701 default: assert(0 && "Unsupported VT!");
702 case MVT::i8: Opc = X86::IDIV8r; MOpc = X86::IDIV8m; break;
703 case MVT::i16: Opc = X86::IDIV16r; MOpc = X86::IDIV16m; break;
704 case MVT::i32: Opc = X86::IDIV32r; MOpc = X86::IDIV32m; break;
707 unsigned LoReg, HiReg;
708 unsigned ClrOpcode, SExtOpcode;
710 default: assert(0 && "Unsupported VT!");
712 LoReg = X86::AL; HiReg = X86::AH;
713 ClrOpcode = X86::MOV8ri;
714 SExtOpcode = X86::CBW;
717 LoReg = X86::AX; HiReg = X86::DX;
718 ClrOpcode = X86::MOV16ri;
719 SExtOpcode = X86::CWD;
722 LoReg = X86::EAX; HiReg = X86::EDX;
723 ClrOpcode = X86::MOV32ri;
724 SExtOpcode = X86::CDQ;
728 SDOperand N0 = Node->getOperand(0);
729 SDOperand N1 = Node->getOperand(1);
731 bool foldedLoad = false;
732 SDOperand Tmp0, Tmp1, Tmp2, Tmp3;
733 foldedLoad = TryFoldLoad(N, N1, Tmp0, Tmp1, Tmp2, Tmp3);
736 Select(Chain, N1.getOperand(0));
738 Chain = CurDAG->getEntryNode();
740 SDOperand InFlag(0, 0);
742 Chain = CurDAG->getCopyToReg(Chain, CurDAG->getRegister(LoReg, NVT),
744 InFlag = Chain.getValue(1);
747 // Sign extend the low part into the high part.
749 SDOperand(CurDAG->getTargetNode(SExtOpcode, MVT::Flag, InFlag), 0);
751 // Zero out the high part, effectively zero extending the input.
753 SDOperand(CurDAG->getTargetNode(ClrOpcode, NVT,
754 CurDAG->getTargetConstant(0, NVT)), 0);
755 Chain = CurDAG->getCopyToReg(Chain, CurDAG->getRegister(HiReg, NVT),
757 InFlag = Chain.getValue(1);
766 CurDAG->getTargetNode(MOpc, MVT::Other, MVT::Flag, Tmp0, Tmp1,
767 Tmp2, Tmp3, Chain, InFlag);
768 Chain = SDOperand(CNode, 0);
769 InFlag = SDOperand(CNode, 1);
773 SDOperand(CurDAG->getTargetNode(Opc, MVT::Flag, N1, InFlag), 0);
776 Result = CurDAG->getCopyFromReg(Chain, isDiv ? LoReg : HiReg,
778 CodeGenMap[N.getValue(0)] = Result;
780 CodeGenMap[N1.getValue(1)] = Result.getValue(1);
781 AddHandleReplacement(N1.Val, 1, Result.Val, 1);
785 DEBUG(std::cerr << std::string(Indent-2, ' '));
786 DEBUG(std::cerr << "== ");
787 DEBUG(Result.Val->dump(CurDAG));
788 DEBUG(std::cerr << "\n");
794 case ISD::TRUNCATE: {
797 switch (Node->getOperand(0).getValueType()) {
798 default: assert(0 && "Unknown truncate!");
799 case MVT::i16: Reg = X86::AX; Opc = X86::MOV16rr; VT = MVT::i16; break;
800 case MVT::i32: Reg = X86::EAX; Opc = X86::MOV32rr; VT = MVT::i32; break;
802 SDOperand Tmp0, Tmp1;
803 Select(Tmp0, Node->getOperand(0));
804 Select(Tmp1, SDOperand(CurDAG->getTargetNode(Opc, VT, Tmp0), 0));
805 SDOperand InFlag = SDOperand(0,0);
806 Result = CurDAG->getCopyToReg(CurDAG->getEntryNode(), Reg, Tmp1, InFlag);
807 SDOperand Chain = Result.getValue(0);
808 InFlag = Result.getValue(1);
811 default: assert(0 && "Unknown truncate!");
812 case MVT::i8: Reg = X86::AL; Opc = X86::MOV8rr; VT = MVT::i8; break;
813 case MVT::i16: Reg = X86::AX; Opc = X86::MOV16rr; VT = MVT::i16; break;
816 Result = CurDAG->getCopyFromReg(Chain, Reg, VT, InFlag);
817 if (N.Val->hasOneUse())
818 Result = CurDAG->SelectNodeTo(N.Val, Opc, VT, Result);
820 Result = CodeGenMap[N] =
821 SDOperand(CurDAG->getTargetNode(Opc, VT, Result), 0);
824 DEBUG(std::cerr << std::string(Indent-2, ' '));
825 DEBUG(std::cerr << "== ");
826 DEBUG(Result.Val->dump(CurDAG));
827 DEBUG(std::cerr << "\n");
834 SelectCode(Result, N);
836 DEBUG(std::cerr << std::string(Indent-2, ' '));
837 DEBUG(std::cerr << "=> ");
838 DEBUG(Result.Val->dump(CurDAG));
839 DEBUG(std::cerr << "\n");
844 /// createX86ISelDag - This pass converts a legalized DAG into a
845 /// X86-specific DAG, ready for instruction scheduling.
847 FunctionPass *llvm::createX86ISelDag(X86TargetMachine &TM) {
848 return new X86DAGToDAGISel(TM);