1 //===- X86ISelDAGToDAG.cpp - A DAG pattern matching inst selector for X86 -===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a DAG pattern matching instruction selector for X86,
11 // converting from a legalized dag to a X86 dag.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
17 #include "X86InstrBuilder.h"
18 #include "X86ISelLowering.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86RegisterInfo.h"
21 #include "X86Subtarget.h"
22 #include "X86TargetMachine.h"
23 #include "llvm/GlobalValue.h"
24 #include "llvm/Instructions.h"
25 #include "llvm/Intrinsics.h"
26 #include "llvm/Support/CFG.h"
27 #include "llvm/Type.h"
28 #include "llvm/CodeGen/MachineConstantPool.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/CodeGen/SelectionDAGISel.h"
34 #include "llvm/Target/TargetMachine.h"
35 #include "llvm/Support/Compiler.h"
36 #include "llvm/Support/Debug.h"
37 #include "llvm/Support/MathExtras.h"
38 #include "llvm/ADT/Statistic.h"
43 STATISTIC(NumFPKill , "Number of FP_REG_KILL instructions added");
44 STATISTIC(NumLoadMoved, "Number of loads moved below TokenFactor");
47 //===----------------------------------------------------------------------===//
48 // Pattern Matcher Implementation
49 //===----------------------------------------------------------------------===//
52 /// X86ISelAddressMode - This corresponds to X86AddressMode, but uses
53 /// SDOperand's instead of register numbers for the leaves of the matched
55 struct X86ISelAddressMode {
61 struct { // This is really a union, discriminated by BaseType!
66 bool isRIPRel; // RIP relative?
74 unsigned Align; // CP alignment.
77 : BaseType(RegBase), isRIPRel(false), Scale(1), IndexReg(), Disp(0),
78 GV(0), CP(0), ES(0), JT(-1), Align(0) {
84 //===--------------------------------------------------------------------===//
85 /// ISel - X86 specific code to select X86 machine instructions for
86 /// SelectionDAG operations.
88 class VISIBILITY_HIDDEN X86DAGToDAGISel : public SelectionDAGISel {
89 /// ContainsFPCode - Every instruction we select that uses or defines a FP
90 /// register should set this to true.
93 /// FastISel - Enable fast(er) instruction selection.
97 /// TM - Keep a reference to X86TargetMachine.
101 /// X86Lowering - This object fully describes how to lower LLVM code to an
102 /// X86-specific SelectionDAG.
103 X86TargetLowering X86Lowering;
105 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
106 /// make the right decision when generating code for different targets.
107 const X86Subtarget *Subtarget;
109 /// GlobalBaseReg - keeps track of the virtual register mapped onto global
111 unsigned GlobalBaseReg;
114 X86DAGToDAGISel(X86TargetMachine &tm, bool fast)
115 : SelectionDAGISel(X86Lowering),
116 ContainsFPCode(false), FastISel(fast), TM(tm),
117 X86Lowering(*TM.getTargetLowering()),
118 Subtarget(&TM.getSubtarget<X86Subtarget>()) {}
120 virtual bool runOnFunction(Function &Fn) {
121 // Make sure we re-emit a set of the global base reg if necessary
123 return SelectionDAGISel::runOnFunction(Fn);
126 virtual const char *getPassName() const {
127 return "X86 DAG->DAG Instruction Selection";
130 /// InstructionSelectBasicBlock - This callback is invoked by
131 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
132 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
134 virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF);
136 virtual bool CanBeFoldedBy(SDNode *N, SDNode *U, SDNode *Root) const;
138 // Include the pieces autogenerated from the target description.
139 #include "X86GenDAGISel.inc"
142 SDNode *Select(SDOperand N);
144 bool MatchAddress(SDOperand N, X86ISelAddressMode &AM,
145 bool isRoot = true, unsigned Depth = 0);
146 bool MatchAddressBase(SDOperand N, X86ISelAddressMode &AM,
147 bool isRoot, unsigned Depth);
148 bool SelectAddr(SDOperand Op, SDOperand N, SDOperand &Base,
149 SDOperand &Scale, SDOperand &Index, SDOperand &Disp);
150 bool SelectLEAAddr(SDOperand Op, SDOperand N, SDOperand &Base,
151 SDOperand &Scale, SDOperand &Index, SDOperand &Disp);
152 bool SelectScalarSSELoad(SDOperand Op, SDOperand Pred,
153 SDOperand N, SDOperand &Base, SDOperand &Scale,
154 SDOperand &Index, SDOperand &Disp,
155 SDOperand &InChain, SDOperand &OutChain);
156 bool TryFoldLoad(SDOperand P, SDOperand N,
157 SDOperand &Base, SDOperand &Scale,
158 SDOperand &Index, SDOperand &Disp);
159 void PreprocessForRMW(SelectionDAG &DAG);
160 void PreprocessForFPConvert(SelectionDAG &DAG);
162 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
163 /// inline asm expressions.
164 virtual bool SelectInlineAsmMemoryOperand(const SDOperand &Op,
166 std::vector<SDOperand> &OutOps,
169 void EmitSpecialCodeForMain(MachineBasicBlock *BB, MachineFrameInfo *MFI);
171 inline void getAddressOperands(X86ISelAddressMode &AM, SDOperand &Base,
172 SDOperand &Scale, SDOperand &Index,
174 Base = (AM.BaseType == X86ISelAddressMode::FrameIndexBase) ?
175 CurDAG->getTargetFrameIndex(AM.Base.FrameIndex, TLI.getPointerTy()) :
177 Scale = getI8Imm(AM.Scale);
179 // These are 32-bit even in 64-bit mode since RIP relative offset
182 Disp = CurDAG->getTargetGlobalAddress(AM.GV, MVT::i32, AM.Disp);
184 Disp = CurDAG->getTargetConstantPool(AM.CP, MVT::i32, AM.Align, AM.Disp);
186 Disp = CurDAG->getTargetExternalSymbol(AM.ES, MVT::i32);
187 else if (AM.JT != -1)
188 Disp = CurDAG->getTargetJumpTable(AM.JT, MVT::i32);
190 Disp = getI32Imm(AM.Disp);
193 /// getI8Imm - Return a target constant with the specified value, of type
195 inline SDOperand getI8Imm(unsigned Imm) {
196 return CurDAG->getTargetConstant(Imm, MVT::i8);
199 /// getI16Imm - Return a target constant with the specified value, of type
201 inline SDOperand getI16Imm(unsigned Imm) {
202 return CurDAG->getTargetConstant(Imm, MVT::i16);
205 /// getI32Imm - Return a target constant with the specified value, of type
207 inline SDOperand getI32Imm(unsigned Imm) {
208 return CurDAG->getTargetConstant(Imm, MVT::i32);
211 /// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC
212 /// base register. Return the virtual register that holds this value.
213 SDNode *getGlobalBaseReg();
215 /// getTruncate - return an SDNode that implements a subreg based truncate
216 /// of the specified operand to the the specified value type.
217 SDNode *getTruncate(SDOperand N0, MVT::ValueType VT);
225 static SDNode *findFlagUse(SDNode *N) {
226 unsigned FlagResNo = N->getNumValues()-1;
227 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
229 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
230 SDOperand Op = User->getOperand(i);
231 if (Op.Val == N && Op.ResNo == FlagResNo)
238 static void findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
239 SDNode *Root, SDNode *Skip, bool &found,
240 std::set<SDNode *> &Visited) {
242 Use->getNodeId() > Def->getNodeId() ||
243 !Visited.insert(Use).second)
246 for (unsigned i = 0, e = Use->getNumOperands(); !found && i != e; ++i) {
247 SDNode *N = Use->getOperand(i).Val;
252 continue; // Immediate use is ok.
254 assert(Use->getOpcode() == ISD::STORE ||
255 Use->getOpcode() == X86ISD::CMP);
261 findNonImmUse(N, Def, ImmedUse, Root, Skip, found, Visited);
265 /// isNonImmUse - Start searching from Root up the DAG to check is Def can
266 /// be reached. Return true if that's the case. However, ignore direct uses
267 /// by ImmedUse (which would be U in the example illustrated in
268 /// CanBeFoldedBy) and by Root (which can happen in the store case).
269 /// FIXME: to be really generic, we should allow direct use by any node
270 /// that is being folded. But realisticly since we only fold loads which
271 /// have one non-chain use, we only need to watch out for load/op/store
272 /// and load/op/cmp case where the root (store / cmp) may reach the load via
273 /// its chain operand.
274 static inline bool isNonImmUse(SDNode *Root, SDNode *Def, SDNode *ImmedUse,
275 SDNode *Skip = NULL) {
276 std::set<SDNode *> Visited;
278 findNonImmUse(Root, Def, ImmedUse, Root, Skip, found, Visited);
283 bool X86DAGToDAGISel::CanBeFoldedBy(SDNode *N, SDNode *U, SDNode *Root) const {
284 if (FastISel) return false;
286 // If U use can somehow reach N through another path then U can't fold N or
287 // it will create a cycle. e.g. In the following diagram, U can reach N
288 // through X. If N is folded into into U, then X is both a predecessor and
299 if (isNonImmUse(Root, N, U))
302 // If U produces a flag, then it gets (even more) interesting. Since it
303 // would have been "glued" together with its flag use, we need to check if
316 // If FU (flag use) indirectly reach N (the load), and U fold N (call it
317 // NU), then TF is a predecessor of FU and a successor of NU. But since
318 // NU and FU are flagged together, this effectively creates a cycle.
319 bool HasFlagUse = false;
320 MVT::ValueType VT = Root->getValueType(Root->getNumValues()-1);
321 while ((VT == MVT::Flag && !Root->use_empty())) {
322 SDNode *FU = findFlagUse(Root);
329 VT = Root->getValueType(Root->getNumValues()-1);
333 return !isNonImmUse(Root, N, Root, U);
337 /// MoveBelowTokenFactor - Replace TokenFactor operand with load's chain operand
338 /// and move load below the TokenFactor. Replace store's chain operand with
339 /// load's chain result.
340 static void MoveBelowTokenFactor(SelectionDAG &DAG, SDOperand Load,
341 SDOperand Store, SDOperand TF) {
342 std::vector<SDOperand> Ops;
343 for (unsigned i = 0, e = TF.Val->getNumOperands(); i != e; ++i)
344 if (Load.Val == TF.Val->getOperand(i).Val)
345 Ops.push_back(Load.Val->getOperand(0));
347 Ops.push_back(TF.Val->getOperand(i));
348 DAG.UpdateNodeOperands(TF, &Ops[0], Ops.size());
349 DAG.UpdateNodeOperands(Load, TF, Load.getOperand(1), Load.getOperand(2));
350 DAG.UpdateNodeOperands(Store, Load.getValue(1), Store.getOperand(1),
351 Store.getOperand(2), Store.getOperand(3));
354 /// PreprocessForRMW - Preprocess the DAG to make instruction selection better.
355 /// This is only run if not in -fast mode (aka -O0).
356 /// This allows the instruction selector to pick more read-modify-write
357 /// instructions. This is a common case:
367 /// [TokenFactor] [Op]
374 /// The fact the store's chain operand != load's chain will prevent the
375 /// (store (op (load))) instruction from being selected. We can transform it to:
394 void X86DAGToDAGISel::PreprocessForRMW(SelectionDAG &DAG) {
395 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
396 E = DAG.allnodes_end(); I != E; ++I) {
397 if (!ISD::isNON_TRUNCStore(I))
399 SDOperand Chain = I->getOperand(0);
400 if (Chain.Val->getOpcode() != ISD::TokenFactor)
403 SDOperand N1 = I->getOperand(1);
404 SDOperand N2 = I->getOperand(2);
405 if (MVT::isFloatingPoint(N1.getValueType()) ||
406 MVT::isVector(N1.getValueType()) ||
412 unsigned Opcode = N1.Val->getOpcode();
421 SDOperand N10 = N1.getOperand(0);
422 SDOperand N11 = N1.getOperand(1);
423 if (ISD::isNON_EXTLoad(N10.Val))
425 else if (ISD::isNON_EXTLoad(N11.Val)) {
429 RModW = RModW && N10.Val->isOperand(Chain.Val) && N10.hasOneUse() &&
430 (N10.getOperand(1) == N2) &&
431 (N10.Val->getValueType(0) == N1.getValueType());
446 SDOperand N10 = N1.getOperand(0);
447 if (ISD::isNON_EXTLoad(N10.Val))
448 RModW = N10.Val->isOperand(Chain.Val) && N10.hasOneUse() &&
449 (N10.getOperand(1) == N2) &&
450 (N10.Val->getValueType(0) == N1.getValueType());
458 MoveBelowTokenFactor(DAG, Load, SDOperand(I, 0), Chain);
465 /// PreprocessForFPConvert - Walk over the dag lowering fpround and fpextend
466 /// nodes that target the FP stack to be store and load to the stack. This is a
467 /// gross hack. We would like to simply mark these as being illegal, but when
468 /// we do that, legalize produces these when it expands calls, then expands
469 /// these in the same legalize pass. We would like dag combine to be able to
470 /// hack on these between the call expansion and the node legalization. As such
471 /// this pass basically does "really late" legalization of these inline with the
473 void X86DAGToDAGISel::PreprocessForFPConvert(SelectionDAG &DAG) {
474 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
475 E = DAG.allnodes_end(); I != E; ) {
476 SDNode *N = I++; // Preincrement iterator to avoid invalidation issues.
477 if (N->getOpcode() != ISD::FP_ROUND && N->getOpcode() != ISD::FP_EXTEND)
480 // If the source and destination are SSE registers, then this is a legal
481 // conversion that should not be lowered.
482 MVT::ValueType SrcVT = N->getOperand(0).getValueType();
483 MVT::ValueType DstVT = N->getValueType(0);
484 bool SrcIsSSE = X86Lowering.isScalarFPTypeInSSEReg(SrcVT);
485 bool DstIsSSE = X86Lowering.isScalarFPTypeInSSEReg(DstVT);
486 if (SrcIsSSE && DstIsSSE)
489 // If this is an FPStack extension (but not a truncation), it is a noop.
490 if (!SrcIsSSE && !DstIsSSE && N->getOpcode() == ISD::FP_EXTEND)
493 // Here we could have an FP stack truncation or an FPStack <-> SSE convert.
494 // FPStack has extload and truncstore. SSE can fold direct loads into other
495 // operations. Based on this, decide what we want to do.
496 MVT::ValueType MemVT;
497 if (N->getOpcode() == ISD::FP_ROUND)
498 MemVT = DstVT; // FP_ROUND must use DstVT, we can't do a 'trunc load'.
500 MemVT = SrcIsSSE ? SrcVT : DstVT;
502 SDOperand MemTmp = DAG.CreateStackTemporary(MemVT);
504 // FIXME: optimize the case where the src/dest is a load or store?
505 SDOperand Store = DAG.getTruncStore(DAG.getEntryNode(), N->getOperand(0),
506 MemTmp, NULL, 0, MemVT);
507 SDOperand Result = DAG.getExtLoad(ISD::EXTLOAD, DstVT, Store, MemTmp,
510 // We're about to replace all uses of the FP_ROUND/FP_EXTEND with the
511 // extload we created. This will cause general havok on the dag because
512 // anything below the conversion could be folded into other existing nodes.
513 // To avoid invalidating 'I', back it up to the convert node.
515 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result);
517 // Now that we did that, the node is dead. Increment the iterator to the
518 // next node to process, then delete N.
524 /// InstructionSelectBasicBlock - This callback is invoked by SelectionDAGISel
525 /// when it has created a SelectionDAG for us to codegen.
526 void X86DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
528 MachineFunction::iterator FirstMBB = BB;
531 PreprocessForRMW(DAG);
533 // FIXME: This should only happen when not -fast.
534 PreprocessForFPConvert(DAG);
536 // Codegen the basic block.
538 DOUT << "===== Instruction selection begins:\n";
541 DAG.setRoot(SelectRoot(DAG.getRoot()));
543 DOUT << "===== Instruction selection ends:\n";
546 DAG.RemoveDeadNodes();
548 // Emit machine code to BB.
549 ScheduleAndEmitDAG(DAG);
551 // If we are emitting FP stack code, scan the basic block to determine if this
552 // block defines any FP values. If so, put an FP_REG_KILL instruction before
553 // the terminator of the block.
555 // Note that FP stack instructions are used in all modes for long double,
556 // so we always need to do this check.
557 // Also note that it's possible for an FP stack register to be live across
558 // an instruction that produces multiple basic blocks (SSE CMOV) so we
559 // must check all the generated basic blocks.
561 // Scan all of the machine instructions in these MBBs, checking for FP
562 // stores. (RFP32 and RFP64 will not exist in SSE mode, but RFP80 might.)
563 MachineFunction::iterator MBBI = FirstMBB;
565 bool ContainsFPCode = false;
566 for (MachineBasicBlock::iterator I = MBBI->begin(), E = MBBI->end();
567 !ContainsFPCode && I != E; ++I) {
568 if (I->getNumOperands() != 0 && I->getOperand(0).isRegister()) {
569 const TargetRegisterClass *clas;
570 for (unsigned op = 0, e = I->getNumOperands(); op != e; ++op) {
571 if (I->getOperand(op).isRegister() && I->getOperand(op).isDef() &&
572 MRegisterInfo::isVirtualRegister(I->getOperand(op).getReg()) &&
573 ((clas = RegInfo->getRegClass(I->getOperand(0).getReg())) ==
574 X86::RFP32RegisterClass ||
575 clas == X86::RFP64RegisterClass ||
576 clas == X86::RFP80RegisterClass)) {
577 ContainsFPCode = true;
583 // Check PHI nodes in successor blocks. These PHI's will be lowered to have
584 // a copy of the input value in this block. In SSE mode, we only care about
586 if (!ContainsFPCode) {
587 // Final check, check LLVM BB's that are successors to the LLVM BB
588 // corresponding to BB for FP PHI nodes.
589 const BasicBlock *LLVMBB = BB->getBasicBlock();
591 for (succ_const_iterator SI = succ_begin(LLVMBB), E = succ_end(LLVMBB);
592 !ContainsFPCode && SI != E; ++SI) {
593 for (BasicBlock::const_iterator II = SI->begin();
594 (PN = dyn_cast<PHINode>(II)); ++II) {
595 if (PN->getType()==Type::X86_FP80Ty ||
596 (!Subtarget->hasSSE1() && PN->getType()->isFloatingPoint()) ||
597 (!Subtarget->hasSSE2() && PN->getType()==Type::DoubleTy)) {
598 ContainsFPCode = true;
604 // Finally, if we found any FP code, emit the FP_REG_KILL instruction.
605 if (ContainsFPCode) {
606 BuildMI(*MBBI, MBBI->getFirstTerminator(),
607 TM.getInstrInfo()->get(X86::FP_REG_KILL));
610 } while (&*(MBBI++) != BB);
613 /// EmitSpecialCodeForMain - Emit any code that needs to be executed only in
614 /// the main function.
615 void X86DAGToDAGISel::EmitSpecialCodeForMain(MachineBasicBlock *BB,
616 MachineFrameInfo *MFI) {
617 const TargetInstrInfo *TII = TM.getInstrInfo();
618 if (Subtarget->isTargetCygMing())
619 BuildMI(BB, TII->get(X86::CALLpcrel32)).addExternalSymbol("__main");
622 void X86DAGToDAGISel::EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {
623 // If this is main, emit special code for main.
624 MachineBasicBlock *BB = MF.begin();
625 if (Fn.hasExternalLinkage() && Fn.getName() == "main")
626 EmitSpecialCodeForMain(BB, MF.getFrameInfo());
629 /// MatchAddress - Add the specified node to the specified addressing mode,
630 /// returning true if it cannot be done. This just pattern matches for the
632 bool X86DAGToDAGISel::MatchAddress(SDOperand N, X86ISelAddressMode &AM,
633 bool isRoot, unsigned Depth) {
636 return MatchAddressBase(N, AM, isRoot, Depth);
638 // RIP relative addressing: %rip + 32-bit displacement!
640 if (!AM.ES && AM.JT != -1 && N.getOpcode() == ISD::Constant) {
641 int64_t Val = cast<ConstantSDNode>(N)->getSignExtended();
642 if (isInt32(AM.Disp + Val)) {
650 int id = N.Val->getNodeId();
651 bool AlreadySelected = isSelected(id); // Already selected, not yet replaced.
653 switch (N.getOpcode()) {
655 case ISD::Constant: {
656 int64_t Val = cast<ConstantSDNode>(N)->getSignExtended();
657 if (isInt32(AM.Disp + Val)) {
664 case X86ISD::Wrapper: {
665 bool is64Bit = Subtarget->is64Bit();
666 // Under X86-64 non-small code model, GV (and friends) are 64-bits.
667 if (is64Bit && TM.getCodeModel() != CodeModel::Small)
669 if (AM.GV != 0 || AM.CP != 0 || AM.ES != 0 || AM.JT != -1)
671 // If value is available in a register both base and index components have
672 // been picked, we can't fit the result available in the register in the
673 // addressing mode. Duplicate GlobalAddress or ConstantPool as displacement.
674 if (!AlreadySelected || (AM.Base.Reg.Val && AM.IndexReg.Val)) {
675 bool isStatic = TM.getRelocationModel() == Reloc::Static;
676 SDOperand N0 = N.getOperand(0);
677 // Mac OS X X86-64 lower 4G address is not available.
678 bool isAbs32 = !is64Bit ||
679 (isStatic && Subtarget->hasLow4GUserSpaceAddress());
680 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
681 GlobalValue *GV = G->getGlobal();
682 if (isAbs32 || isRoot) {
684 AM.Disp += G->getOffset();
685 AM.isRIPRel = !isAbs32;
688 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) {
689 if (isAbs32 || isRoot) {
690 AM.CP = CP->getConstVal();
691 AM.Align = CP->getAlignment();
692 AM.Disp += CP->getOffset();
693 AM.isRIPRel = !isAbs32;
696 } else if (ExternalSymbolSDNode *S =dyn_cast<ExternalSymbolSDNode>(N0)) {
697 if (isAbs32 || isRoot) {
698 AM.ES = S->getSymbol();
699 AM.isRIPRel = !isAbs32;
702 } else if (JumpTableSDNode *J = dyn_cast<JumpTableSDNode>(N0)) {
703 if (isAbs32 || isRoot) {
704 AM.JT = J->getIndex();
705 AM.isRIPRel = !isAbs32;
713 case ISD::FrameIndex:
714 if (AM.BaseType == X86ISelAddressMode::RegBase && AM.Base.Reg.Val == 0) {
715 AM.BaseType = X86ISelAddressMode::FrameIndexBase;
716 AM.Base.FrameIndex = cast<FrameIndexSDNode>(N)->getIndex();
722 if (AlreadySelected || AM.IndexReg.Val != 0 || AM.Scale != 1)
725 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.Val->getOperand(1))) {
726 unsigned Val = CN->getValue();
727 if (Val == 1 || Val == 2 || Val == 3) {
729 SDOperand ShVal = N.Val->getOperand(0);
731 // Okay, we know that we have a scale by now. However, if the scaled
732 // value is an add of something and a constant, we can fold the
733 // constant into the disp field here.
734 if (ShVal.Val->getOpcode() == ISD::ADD && ShVal.hasOneUse() &&
735 isa<ConstantSDNode>(ShVal.Val->getOperand(1))) {
736 AM.IndexReg = ShVal.Val->getOperand(0);
737 ConstantSDNode *AddVal =
738 cast<ConstantSDNode>(ShVal.Val->getOperand(1));
739 uint64_t Disp = AM.Disp + (AddVal->getValue() << Val);
754 // A mul_lohi where we need the low part can be folded as a plain multiply.
755 if (N.ResNo != 0) break;
758 // X*[3,5,9] -> X+X*[2,4,8]
759 if (!AlreadySelected &&
760 AM.BaseType == X86ISelAddressMode::RegBase &&
761 AM.Base.Reg.Val == 0 &&
762 AM.IndexReg.Val == 0) {
763 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.Val->getOperand(1)))
764 if (CN->getValue() == 3 || CN->getValue() == 5 || CN->getValue() == 9) {
765 AM.Scale = unsigned(CN->getValue())-1;
767 SDOperand MulVal = N.Val->getOperand(0);
770 // Okay, we know that we have a scale by now. However, if the scaled
771 // value is an add of something and a constant, we can fold the
772 // constant into the disp field here.
773 if (MulVal.Val->getOpcode() == ISD::ADD && MulVal.hasOneUse() &&
774 isa<ConstantSDNode>(MulVal.Val->getOperand(1))) {
775 Reg = MulVal.Val->getOperand(0);
776 ConstantSDNode *AddVal =
777 cast<ConstantSDNode>(MulVal.Val->getOperand(1));
778 uint64_t Disp = AM.Disp + AddVal->getValue() * CN->getValue();
782 Reg = N.Val->getOperand(0);
784 Reg = N.Val->getOperand(0);
787 AM.IndexReg = AM.Base.Reg = Reg;
794 if (!AlreadySelected) {
795 X86ISelAddressMode Backup = AM;
796 if (!MatchAddress(N.Val->getOperand(0), AM, false, Depth+1) &&
797 !MatchAddress(N.Val->getOperand(1), AM, false, Depth+1))
800 if (!MatchAddress(N.Val->getOperand(1), AM, false, Depth+1) &&
801 !MatchAddress(N.Val->getOperand(0), AM, false, Depth+1))
808 // Handle "X | C" as "X + C" iff X is known to have C bits clear.
809 if (AlreadySelected) break;
811 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
812 X86ISelAddressMode Backup = AM;
813 // Start with the LHS as an addr mode.
814 if (!MatchAddress(N.getOperand(0), AM, false) &&
815 // Address could not have picked a GV address for the displacement.
817 // On x86-64, the resultant disp must fit in 32-bits.
818 isInt32(AM.Disp + CN->getSignExtended()) &&
819 // Check to see if the LHS & C is zero.
820 CurDAG->MaskedValueIsZero(N.getOperand(0), CN->getValue())) {
821 AM.Disp += CN->getValue();
829 // Handle "(x << C1) & C2" as "(X & (C2>>C1)) << C1" if safe and if this
830 // allows us to fold the shift into this addressing mode.
831 if (AlreadySelected) break;
832 SDOperand Shift = N.getOperand(0);
833 if (Shift.getOpcode() != ISD::SHL) break;
835 // Scale must not be used already.
836 if (AM.IndexReg.Val != 0 || AM.Scale != 1) break;
838 ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N.getOperand(1));
839 ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(Shift.getOperand(1));
840 if (!C1 || !C2) break;
842 // Not likely to be profitable if either the AND or SHIFT node has more
843 // than one use (unless all uses are for address computation). Besides,
844 // isel mechanism requires their node ids to be reused.
845 if (!N.hasOneUse() || !Shift.hasOneUse())
848 // Verify that the shift amount is something we can fold.
849 unsigned ShiftCst = C1->getValue();
850 if (ShiftCst != 1 && ShiftCst != 2 && ShiftCst != 3)
853 // Get the new AND mask, this folds to a constant.
854 SDOperand NewANDMask = CurDAG->getNode(ISD::SRL, N.getValueType(),
855 SDOperand(C2, 0), SDOperand(C1, 0));
856 SDOperand NewAND = CurDAG->getNode(ISD::AND, N.getValueType(),
857 Shift.getOperand(0), NewANDMask);
858 NewANDMask.Val->setNodeId(Shift.Val->getNodeId());
859 NewAND.Val->setNodeId(N.Val->getNodeId());
861 AM.Scale = 1 << ShiftCst;
862 AM.IndexReg = NewAND;
867 return MatchAddressBase(N, AM, isRoot, Depth);
870 /// MatchAddressBase - Helper for MatchAddress. Add the specified node to the
871 /// specified addressing mode without any further recursion.
872 bool X86DAGToDAGISel::MatchAddressBase(SDOperand N, X86ISelAddressMode &AM,
873 bool isRoot, unsigned Depth) {
874 // Is the base register already occupied?
875 if (AM.BaseType != X86ISelAddressMode::RegBase || AM.Base.Reg.Val) {
876 // If so, check to see if the scale index register is set.
877 if (AM.IndexReg.Val == 0) {
883 // Otherwise, we cannot select it.
887 // Default, generate it as a register.
888 AM.BaseType = X86ISelAddressMode::RegBase;
893 /// SelectAddr - returns true if it is able pattern match an addressing mode.
894 /// It returns the operands which make up the maximal addressing mode it can
895 /// match by reference.
896 bool X86DAGToDAGISel::SelectAddr(SDOperand Op, SDOperand N, SDOperand &Base,
897 SDOperand &Scale, SDOperand &Index,
899 X86ISelAddressMode AM;
900 if (MatchAddress(N, AM))
903 MVT::ValueType VT = N.getValueType();
904 if (AM.BaseType == X86ISelAddressMode::RegBase) {
905 if (!AM.Base.Reg.Val)
906 AM.Base.Reg = CurDAG->getRegister(0, VT);
909 if (!AM.IndexReg.Val)
910 AM.IndexReg = CurDAG->getRegister(0, VT);
912 getAddressOperands(AM, Base, Scale, Index, Disp);
916 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
918 static inline bool isZeroNode(SDOperand Elt) {
919 return ((isa<ConstantSDNode>(Elt) &&
920 cast<ConstantSDNode>(Elt)->getValue() == 0) ||
921 (isa<ConstantFPSDNode>(Elt) &&
922 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
926 /// SelectScalarSSELoad - Match a scalar SSE load. In particular, we want to
927 /// match a load whose top elements are either undef or zeros. The load flavor
928 /// is derived from the type of N, which is either v4f32 or v2f64.
929 bool X86DAGToDAGISel::SelectScalarSSELoad(SDOperand Op, SDOperand Pred,
930 SDOperand N, SDOperand &Base,
931 SDOperand &Scale, SDOperand &Index,
932 SDOperand &Disp, SDOperand &InChain,
933 SDOperand &OutChain) {
934 if (N.getOpcode() == ISD::SCALAR_TO_VECTOR) {
935 InChain = N.getOperand(0).getValue(1);
936 if (ISD::isNON_EXTLoad(InChain.Val) &&
937 InChain.getValue(0).hasOneUse() &&
939 CanBeFoldedBy(N.Val, Pred.Val, Op.Val)) {
940 LoadSDNode *LD = cast<LoadSDNode>(InChain);
941 if (!SelectAddr(Op, LD->getBasePtr(), Base, Scale, Index, Disp))
943 OutChain = LD->getChain();
948 // Also handle the case where we explicitly require zeros in the top
949 // elements. This is a vector shuffle from the zero vector.
950 if (N.getOpcode() == ISD::VECTOR_SHUFFLE && N.Val->hasOneUse() &&
951 // Check to see if the top elements are all zeros (or bitcast of zeros).
952 ISD::isBuildVectorAllZeros(N.getOperand(0).Val) &&
953 N.getOperand(1).getOpcode() == ISD::SCALAR_TO_VECTOR &&
954 N.getOperand(1).Val->hasOneUse() &&
955 ISD::isNON_EXTLoad(N.getOperand(1).getOperand(0).Val) &&
956 N.getOperand(1).getOperand(0).hasOneUse()) {
957 // Check to see if the shuffle mask is 4/L/L/L or 2/L, where L is something
959 unsigned VecWidth=MVT::getVectorNumElements(N.getOperand(0).getValueType());
960 SDOperand ShufMask = N.getOperand(2);
961 assert(ShufMask.getOpcode() == ISD::BUILD_VECTOR && "Invalid shuf mask!");
962 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(ShufMask.getOperand(0))) {
963 if (C->getValue() == VecWidth) {
964 for (unsigned i = 1; i != VecWidth; ++i) {
965 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF) {
968 ConstantSDNode *C = cast<ConstantSDNode>(ShufMask.getOperand(i));
969 if (C->getValue() >= VecWidth) return false;
974 // Okay, this is a zero extending load. Fold it.
975 LoadSDNode *LD = cast<LoadSDNode>(N.getOperand(1).getOperand(0));
976 if (!SelectAddr(Op, LD->getBasePtr(), Base, Scale, Index, Disp))
978 OutChain = LD->getChain();
979 InChain = SDOperand(LD, 1);
987 /// SelectLEAAddr - it calls SelectAddr and determines if the maximal addressing
988 /// mode it matches can be cost effectively emitted as an LEA instruction.
989 bool X86DAGToDAGISel::SelectLEAAddr(SDOperand Op, SDOperand N,
990 SDOperand &Base, SDOperand &Scale,
991 SDOperand &Index, SDOperand &Disp) {
992 X86ISelAddressMode AM;
993 if (MatchAddress(N, AM))
996 MVT::ValueType VT = N.getValueType();
997 unsigned Complexity = 0;
998 if (AM.BaseType == X86ISelAddressMode::RegBase)
1002 AM.Base.Reg = CurDAG->getRegister(0, VT);
1003 else if (AM.BaseType == X86ISelAddressMode::FrameIndexBase)
1006 if (AM.IndexReg.Val)
1009 AM.IndexReg = CurDAG->getRegister(0, VT);
1011 // Don't match just leal(,%reg,2). It's cheaper to do addl %reg, %reg, or with
1016 // FIXME: We are artificially lowering the criteria to turn ADD %reg, $GA
1017 // to a LEA. This is determined with some expermentation but is by no means
1018 // optimal (especially for code size consideration). LEA is nice because of
1019 // its three-address nature. Tweak the cost function again when we can run
1020 // convertToThreeAddress() at register allocation time.
1021 if (AM.GV || AM.CP || AM.ES || AM.JT != -1) {
1022 // For X86-64, we should always use lea to materialize RIP relative
1024 if (Subtarget->is64Bit())
1030 if (AM.Disp && (AM.Base.Reg.Val || AM.IndexReg.Val))
1033 if (Complexity > 2) {
1034 getAddressOperands(AM, Base, Scale, Index, Disp);
1040 bool X86DAGToDAGISel::TryFoldLoad(SDOperand P, SDOperand N,
1041 SDOperand &Base, SDOperand &Scale,
1042 SDOperand &Index, SDOperand &Disp) {
1043 if (ISD::isNON_EXTLoad(N.Val) &&
1045 CanBeFoldedBy(N.Val, P.Val, P.Val))
1046 return SelectAddr(P, N.getOperand(1), Base, Scale, Index, Disp);
1050 /// getGlobalBaseReg - Output the instructions required to put the
1051 /// base address to use for accessing globals into a register.
1053 SDNode *X86DAGToDAGISel::getGlobalBaseReg() {
1054 assert(!Subtarget->is64Bit() && "X86-64 PIC uses RIP relative addressing");
1055 if (!GlobalBaseReg) {
1056 // Insert the set of GlobalBaseReg into the first MBB of the function
1057 MachineFunction *MF = BB->getParent();
1058 MachineBasicBlock &FirstMBB = MF->front();
1059 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
1060 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1061 unsigned PC = RegInfo.createVirtualRegister(X86::GR32RegisterClass);
1063 const TargetInstrInfo *TII = TM.getInstrInfo();
1064 // Operand of MovePCtoStack is completely ignored by asm printer. It's
1065 // only used in JIT code emission as displacement to pc.
1066 BuildMI(FirstMBB, MBBI, TII->get(X86::MOVPC32r), PC).addImm(0);
1068 // If we're using vanilla 'GOT' PIC style, we should use relative addressing
1069 // not to pc, but to _GLOBAL_ADDRESS_TABLE_ external
1070 if (TM.getRelocationModel() == Reloc::PIC_ &&
1071 Subtarget->isPICStyleGOT()) {
1072 GlobalBaseReg = RegInfo.createVirtualRegister(X86::GR32RegisterClass);
1073 BuildMI(FirstMBB, MBBI, TII->get(X86::ADD32ri), GlobalBaseReg)
1074 .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_");
1080 return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).Val;
1083 static SDNode *FindCallStartFromCall(SDNode *Node) {
1084 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
1085 assert(Node->getOperand(0).getValueType() == MVT::Other &&
1086 "Node doesn't have a token chain argument!");
1087 return FindCallStartFromCall(Node->getOperand(0).Val);
1090 SDNode *X86DAGToDAGISel::getTruncate(SDOperand N0, MVT::ValueType VT) {
1094 SRIdx = CurDAG->getTargetConstant(1, MVT::i32); // SubRegSet 1
1095 // Ensure that the source register has an 8-bit subreg on 32-bit targets
1096 if (!Subtarget->is64Bit()) {
1099 switch (N0.getValueType()) {
1100 default: assert(0 && "Unknown truncate!");
1102 Opc = X86::MOV16to16_;
1106 Opc = X86::MOV32to32_;
1110 N0 = SDOperand(CurDAG->getTargetNode(Opc, VT, MVT::Flag, N0), 0);
1111 return CurDAG->getTargetNode(X86::EXTRACT_SUBREG,
1112 VT, N0, SRIdx, N0.getValue(1));
1116 SRIdx = CurDAG->getTargetConstant(2, MVT::i32); // SubRegSet 2
1119 SRIdx = CurDAG->getTargetConstant(3, MVT::i32); // SubRegSet 3
1121 default: assert(0 && "Unknown truncate!"); break;
1123 return CurDAG->getTargetNode(X86::EXTRACT_SUBREG, VT, N0, SRIdx);
1127 SDNode *X86DAGToDAGISel::Select(SDOperand N) {
1128 SDNode *Node = N.Val;
1129 MVT::ValueType NVT = Node->getValueType(0);
1131 unsigned Opcode = Node->getOpcode();
1134 DOUT << std::string(Indent, ' ') << "Selecting: ";
1135 DEBUG(Node->dump(CurDAG));
1140 if (Opcode >= ISD::BUILTIN_OP_END && Opcode < X86ISD::FIRST_NUMBER) {
1142 DOUT << std::string(Indent-2, ' ') << "== ";
1143 DEBUG(Node->dump(CurDAG));
1147 return NULL; // Already selected.
1152 case X86ISD::GlobalBaseReg:
1153 return getGlobalBaseReg();
1156 // Turn ADD X, c to MOV32ri X+c. This cannot be done with tblgen'd
1157 // code and is matched first so to prevent it from being turned into
1159 // In 64-bit small code size mode, use LEA to take advantage of
1160 // RIP-relative addressing.
1161 if (TM.getCodeModel() != CodeModel::Small)
1163 MVT::ValueType PtrVT = TLI.getPointerTy();
1164 SDOperand N0 = N.getOperand(0);
1165 SDOperand N1 = N.getOperand(1);
1166 if (N.Val->getValueType(0) == PtrVT &&
1167 N0.getOpcode() == X86ISD::Wrapper &&
1168 N1.getOpcode() == ISD::Constant) {
1169 unsigned Offset = (unsigned)cast<ConstantSDNode>(N1)->getValue();
1171 // TODO: handle ExternalSymbolSDNode.
1172 if (GlobalAddressSDNode *G =
1173 dyn_cast<GlobalAddressSDNode>(N0.getOperand(0))) {
1174 C = CurDAG->getTargetGlobalAddress(G->getGlobal(), PtrVT,
1175 G->getOffset() + Offset);
1176 } else if (ConstantPoolSDNode *CP =
1177 dyn_cast<ConstantPoolSDNode>(N0.getOperand(0))) {
1178 C = CurDAG->getTargetConstantPool(CP->getConstVal(), PtrVT,
1180 CP->getOffset()+Offset);
1184 if (Subtarget->is64Bit()) {
1185 SDOperand Ops[] = { CurDAG->getRegister(0, PtrVT), getI8Imm(1),
1186 CurDAG->getRegister(0, PtrVT), C };
1187 return CurDAG->SelectNodeTo(N.Val, X86::LEA64r, MVT::i64, Ops, 4);
1189 return CurDAG->SelectNodeTo(N.Val, X86::MOV32ri, PtrVT, C);
1193 // Other cases are handled by auto-generated code.
1197 case ISD::SMUL_LOHI:
1198 case ISD::UMUL_LOHI: {
1199 SDOperand N0 = Node->getOperand(0);
1200 SDOperand N1 = Node->getOperand(1);
1202 // There are several forms of IMUL that just return the low part and
1203 // don't have fixed-register operands. If we don't need the high part,
1204 // use these instead. They can be selected with the generated ISel code.
1205 if (NVT != MVT::i8 &&
1206 N.getValue(1).use_empty()) {
1207 N = CurDAG->getNode(ISD::MUL, NVT, N0, N1);
1211 bool isSigned = Opcode == ISD::SMUL_LOHI;
1214 default: assert(0 && "Unsupported VT!");
1215 case MVT::i8: Opc = X86::MUL8r; MOpc = X86::MUL8m; break;
1216 case MVT::i16: Opc = X86::MUL16r; MOpc = X86::MUL16m; break;
1217 case MVT::i32: Opc = X86::MUL32r; MOpc = X86::MUL32m; break;
1218 case MVT::i64: Opc = X86::MUL64r; MOpc = X86::MUL64m; break;
1222 default: assert(0 && "Unsupported VT!");
1223 case MVT::i8: Opc = X86::IMUL8r; MOpc = X86::IMUL8m; break;
1224 case MVT::i16: Opc = X86::IMUL16r; MOpc = X86::IMUL16m; break;
1225 case MVT::i32: Opc = X86::IMUL32r; MOpc = X86::IMUL32m; break;
1226 case MVT::i64: Opc = X86::IMUL64r; MOpc = X86::IMUL64m; break;
1229 unsigned LoReg, HiReg;
1231 default: assert(0 && "Unsupported VT!");
1232 case MVT::i8: LoReg = X86::AL; HiReg = X86::AH; break;
1233 case MVT::i16: LoReg = X86::AX; HiReg = X86::DX; break;
1234 case MVT::i32: LoReg = X86::EAX; HiReg = X86::EDX; break;
1235 case MVT::i64: LoReg = X86::RAX; HiReg = X86::RDX; break;
1238 SDOperand Tmp0, Tmp1, Tmp2, Tmp3;
1239 bool foldedLoad = TryFoldLoad(N, N1, Tmp0, Tmp1, Tmp2, Tmp3);
1240 // multiplty is commmutative
1242 foldedLoad = TryFoldLoad(N, N0, Tmp0, Tmp1, Tmp2, Tmp3);
1248 SDOperand InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), LoReg,
1249 N0, SDOperand()).getValue(1);
1252 AddToISelQueue(N1.getOperand(0));
1253 AddToISelQueue(Tmp0);
1254 AddToISelQueue(Tmp1);
1255 AddToISelQueue(Tmp2);
1256 AddToISelQueue(Tmp3);
1257 SDOperand Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, N1.getOperand(0), InFlag };
1259 CurDAG->getTargetNode(MOpc, MVT::Other, MVT::Flag, Ops, 6);
1260 InFlag = SDOperand(CNode, 1);
1261 // Update the chain.
1262 ReplaceUses(N1.getValue(1), SDOperand(CNode, 0));
1266 SDOperand(CurDAG->getTargetNode(Opc, MVT::Flag, N1, InFlag), 0);
1269 // Copy the low half of the result, if it is needed.
1270 if (!N.getValue(0).use_empty()) {
1271 SDOperand Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
1272 LoReg, NVT, InFlag);
1273 InFlag = Result.getValue(2);
1274 ReplaceUses(N.getValue(0), Result);
1276 DOUT << std::string(Indent-2, ' ') << "=> ";
1277 DEBUG(Result.Val->dump(CurDAG));
1281 // Copy the high half of the result, if it is needed.
1282 if (!N.getValue(1).use_empty()) {
1284 if (HiReg == X86::AH && Subtarget->is64Bit()) {
1285 // Prevent use of AH in a REX instruction by referencing AX instead.
1286 // Shift it down 8 bits.
1287 Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
1288 X86::AX, MVT::i16, InFlag);
1289 InFlag = Result.getValue(2);
1290 Result = SDOperand(CurDAG->getTargetNode(X86::SHR16ri, MVT::i16, Result,
1291 CurDAG->getTargetConstant(8, MVT::i8)), 0);
1292 // Then truncate it down to i8.
1293 SDOperand SRIdx = CurDAG->getTargetConstant(1, MVT::i32); // SubRegSet 1
1294 Result = SDOperand(CurDAG->getTargetNode(X86::EXTRACT_SUBREG,
1295 MVT::i8, Result, SRIdx), 0);
1297 Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
1298 HiReg, NVT, InFlag);
1299 InFlag = Result.getValue(2);
1301 ReplaceUses(N.getValue(1), Result);
1303 DOUT << std::string(Indent-2, ' ') << "=> ";
1304 DEBUG(Result.Val->dump(CurDAG));
1317 case ISD::UDIVREM: {
1318 SDOperand N0 = Node->getOperand(0);
1319 SDOperand N1 = Node->getOperand(1);
1321 bool isSigned = Opcode == ISD::SDIVREM;
1324 default: assert(0 && "Unsupported VT!");
1325 case MVT::i8: Opc = X86::DIV8r; MOpc = X86::DIV8m; break;
1326 case MVT::i16: Opc = X86::DIV16r; MOpc = X86::DIV16m; break;
1327 case MVT::i32: Opc = X86::DIV32r; MOpc = X86::DIV32m; break;
1328 case MVT::i64: Opc = X86::DIV64r; MOpc = X86::DIV64m; break;
1332 default: assert(0 && "Unsupported VT!");
1333 case MVT::i8: Opc = X86::IDIV8r; MOpc = X86::IDIV8m; break;
1334 case MVT::i16: Opc = X86::IDIV16r; MOpc = X86::IDIV16m; break;
1335 case MVT::i32: Opc = X86::IDIV32r; MOpc = X86::IDIV32m; break;
1336 case MVT::i64: Opc = X86::IDIV64r; MOpc = X86::IDIV64m; break;
1339 unsigned LoReg, HiReg;
1340 unsigned ClrOpcode, SExtOpcode;
1342 default: assert(0 && "Unsupported VT!");
1344 LoReg = X86::AL; HiReg = X86::AH;
1346 SExtOpcode = X86::CBW;
1349 LoReg = X86::AX; HiReg = X86::DX;
1350 ClrOpcode = X86::MOV16r0;
1351 SExtOpcode = X86::CWD;
1354 LoReg = X86::EAX; HiReg = X86::EDX;
1355 ClrOpcode = X86::MOV32r0;
1356 SExtOpcode = X86::CDQ;
1359 LoReg = X86::RAX; HiReg = X86::RDX;
1360 ClrOpcode = X86::MOV64r0;
1361 SExtOpcode = X86::CQO;
1365 SDOperand Tmp0, Tmp1, Tmp2, Tmp3;
1366 bool foldedLoad = TryFoldLoad(N, N1, Tmp0, Tmp1, Tmp2, Tmp3);
1369 if (NVT == MVT::i8 && !isSigned) {
1370 // Special case for div8, just use a move with zero extension to AX to
1371 // clear the upper 8 bits (AH).
1372 SDOperand Tmp0, Tmp1, Tmp2, Tmp3, Move, Chain;
1373 if (TryFoldLoad(N, N0, Tmp0, Tmp1, Tmp2, Tmp3)) {
1374 SDOperand Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, N0.getOperand(0) };
1375 AddToISelQueue(N0.getOperand(0));
1376 AddToISelQueue(Tmp0);
1377 AddToISelQueue(Tmp1);
1378 AddToISelQueue(Tmp2);
1379 AddToISelQueue(Tmp3);
1381 SDOperand(CurDAG->getTargetNode(X86::MOVZX16rm8, MVT::i16, MVT::Other,
1383 Chain = Move.getValue(1);
1384 ReplaceUses(N0.getValue(1), Chain);
1388 SDOperand(CurDAG->getTargetNode(X86::MOVZX16rr8, MVT::i16, N0), 0);
1389 Chain = CurDAG->getEntryNode();
1391 Chain = CurDAG->getCopyToReg(Chain, X86::AX, Move, SDOperand());
1392 InFlag = Chain.getValue(1);
1396 CurDAG->getCopyToReg(CurDAG->getEntryNode(),
1397 LoReg, N0, SDOperand()).getValue(1);
1399 // Sign extend the low part into the high part.
1401 SDOperand(CurDAG->getTargetNode(SExtOpcode, MVT::Flag, InFlag), 0);
1403 // Zero out the high part, effectively zero extending the input.
1404 SDOperand ClrNode = SDOperand(CurDAG->getTargetNode(ClrOpcode, NVT), 0);
1405 InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), HiReg,
1406 ClrNode, InFlag).getValue(1);
1411 AddToISelQueue(N1.getOperand(0));
1412 AddToISelQueue(Tmp0);
1413 AddToISelQueue(Tmp1);
1414 AddToISelQueue(Tmp2);
1415 AddToISelQueue(Tmp3);
1416 SDOperand Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, N1.getOperand(0), InFlag };
1418 CurDAG->getTargetNode(MOpc, MVT::Other, MVT::Flag, Ops, 6);
1419 InFlag = SDOperand(CNode, 1);
1420 // Update the chain.
1421 ReplaceUses(N1.getValue(1), SDOperand(CNode, 0));
1425 SDOperand(CurDAG->getTargetNode(Opc, MVT::Flag, N1, InFlag), 0);
1428 // Copy the division (low) result, if it is needed.
1429 if (!N.getValue(0).use_empty()) {
1430 SDOperand Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
1431 LoReg, NVT, InFlag);
1432 InFlag = Result.getValue(2);
1433 ReplaceUses(N.getValue(0), Result);
1435 DOUT << std::string(Indent-2, ' ') << "=> ";
1436 DEBUG(Result.Val->dump(CurDAG));
1440 // Copy the remainder (high) result, if it is needed.
1441 if (!N.getValue(1).use_empty()) {
1443 if (HiReg == X86::AH && Subtarget->is64Bit()) {
1444 // Prevent use of AH in a REX instruction by referencing AX instead.
1445 // Shift it down 8 bits.
1446 Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
1447 X86::AX, MVT::i16, InFlag);
1448 InFlag = Result.getValue(2);
1449 Result = SDOperand(CurDAG->getTargetNode(X86::SHR16ri, MVT::i16, Result,
1450 CurDAG->getTargetConstant(8, MVT::i8)), 0);
1451 // Then truncate it down to i8.
1452 SDOperand SRIdx = CurDAG->getTargetConstant(1, MVT::i32); // SubRegSet 1
1453 Result = SDOperand(CurDAG->getTargetNode(X86::EXTRACT_SUBREG,
1454 MVT::i8, Result, SRIdx), 0);
1456 Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
1457 HiReg, NVT, InFlag);
1458 InFlag = Result.getValue(2);
1460 ReplaceUses(N.getValue(1), Result);
1462 DOUT << std::string(Indent-2, ' ') << "=> ";
1463 DEBUG(Result.Val->dump(CurDAG));
1475 case ISD::ANY_EXTEND: {
1476 SDOperand N0 = Node->getOperand(0);
1478 if (NVT == MVT::i64 || NVT == MVT::i32 || NVT == MVT::i16) {
1480 switch(N0.getValueType()) {
1482 SRIdx = CurDAG->getTargetConstant(3, MVT::i32); // SubRegSet 3
1485 SRIdx = CurDAG->getTargetConstant(2, MVT::i32); // SubRegSet 2
1488 if (Subtarget->is64Bit())
1489 SRIdx = CurDAG->getTargetConstant(1, MVT::i32); // SubRegSet 1
1491 default: assert(0 && "Unknown any_extend!");
1494 SDNode *ResNode = CurDAG->getTargetNode(X86::INSERT_SUBREG,
1498 DOUT << std::string(Indent-2, ' ') << "=> ";
1499 DEBUG(ResNode->dump(CurDAG));
1504 } // Otherwise let generated ISel handle it.
1509 case ISD::SIGN_EXTEND_INREG: {
1510 SDOperand N0 = Node->getOperand(0);
1513 MVT::ValueType SVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
1514 SDOperand TruncOp = SDOperand(getTruncate(N0, SVT), 0);
1518 if (SVT == MVT::i8) Opc = X86::MOVSX16rr8;
1519 else assert(0 && "Unknown sign_extend_inreg!");
1523 case MVT::i8: Opc = X86::MOVSX32rr8; break;
1524 case MVT::i16: Opc = X86::MOVSX32rr16; break;
1525 default: assert(0 && "Unknown sign_extend_inreg!");
1530 case MVT::i8: Opc = X86::MOVSX64rr8; break;
1531 case MVT::i16: Opc = X86::MOVSX64rr16; break;
1532 case MVT::i32: Opc = X86::MOVSX64rr32; break;
1533 default: assert(0 && "Unknown sign_extend_inreg!");
1536 default: assert(0 && "Unknown sign_extend_inreg!");
1539 SDNode *ResNode = CurDAG->getTargetNode(Opc, NVT, TruncOp);
1542 DOUT << std::string(Indent-2, ' ') << "=> ";
1543 DEBUG(TruncOp.Val->dump(CurDAG));
1545 DOUT << std::string(Indent-2, ' ') << "=> ";
1546 DEBUG(ResNode->dump(CurDAG));
1554 case ISD::TRUNCATE: {
1555 SDOperand Input = Node->getOperand(0);
1556 AddToISelQueue(Node->getOperand(0));
1557 SDNode *ResNode = getTruncate(Input, NVT);
1560 DOUT << std::string(Indent-2, ' ') << "=> ";
1561 DEBUG(ResNode->dump(CurDAG));
1570 SDNode *ResNode = SelectCode(N);
1573 DOUT << std::string(Indent-2, ' ') << "=> ";
1574 if (ResNode == NULL || ResNode == N.Val)
1575 DEBUG(N.Val->dump(CurDAG));
1577 DEBUG(ResNode->dump(CurDAG));
1585 bool X86DAGToDAGISel::
1586 SelectInlineAsmMemoryOperand(const SDOperand &Op, char ConstraintCode,
1587 std::vector<SDOperand> &OutOps, SelectionDAG &DAG){
1588 SDOperand Op0, Op1, Op2, Op3;
1589 switch (ConstraintCode) {
1590 case 'o': // offsetable ??
1591 case 'v': // not offsetable ??
1592 default: return true;
1594 if (!SelectAddr(Op, Op, Op0, Op1, Op2, Op3))
1599 OutOps.push_back(Op0);
1600 OutOps.push_back(Op1);
1601 OutOps.push_back(Op2);
1602 OutOps.push_back(Op3);
1603 AddToISelQueue(Op0);
1604 AddToISelQueue(Op1);
1605 AddToISelQueue(Op2);
1606 AddToISelQueue(Op3);
1610 /// createX86ISelDag - This pass converts a legalized DAG into a
1611 /// X86-specific DAG, ready for instruction scheduling.
1613 FunctionPass *llvm::createX86ISelDag(X86TargetMachine &TM, bool Fast) {
1614 return new X86DAGToDAGISel(TM, Fast);