1 //===- X86ISelDAGToDAG.cpp - A DAG pattern matching inst selector for X86 -===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the Evan Cheng and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a DAG pattern matching instruction selector for X86,
11 // converting from a legalized dag to a X86 dag.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
17 #include "X86InstrBuilder.h"
18 #include "X86ISelLowering.h"
19 #include "X86RegisterInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/GlobalValue.h"
23 #include "llvm/Instructions.h"
24 #include "llvm/Intrinsics.h"
25 #include "llvm/Support/CFG.h"
26 #include "llvm/Type.h"
27 #include "llvm/CodeGen/MachineConstantPool.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/SSARegMap.h"
32 #include "llvm/CodeGen/SelectionDAGISel.h"
33 #include "llvm/Target/TargetMachine.h"
34 #include "llvm/Support/Compiler.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/MathExtras.h"
37 #include "llvm/ADT/Statistic.h"
42 STATISTIC(NumFPKill , "Number of FP_REG_KILL instructions added");
43 STATISTIC(NumLoadMoved, "Number of loads moved below TokenFactor");
46 //===----------------------------------------------------------------------===//
47 // Pattern Matcher Implementation
48 //===----------------------------------------------------------------------===//
51 /// X86ISelAddressMode - This corresponds to X86AddressMode, but uses
52 /// SDOperand's instead of register numbers for the leaves of the matched
54 struct X86ISelAddressMode {
60 struct { // This is really a union, discriminated by BaseType!
65 bool isRIPRel; // RIP relative?
73 unsigned Align; // CP alignment.
76 : BaseType(RegBase), isRIPRel(false), Scale(1), IndexReg(), Disp(0),
77 GV(0), CP(0), ES(0), JT(-1), Align(0) {
83 //===--------------------------------------------------------------------===//
84 /// ISel - X86 specific code to select X86 machine instructions for
85 /// SelectionDAG operations.
87 class VISIBILITY_HIDDEN X86DAGToDAGISel : public SelectionDAGISel {
88 /// ContainsFPCode - Every instruction we select that uses or defines a FP
89 /// register should set this to true.
92 /// FastISel - Enable fast(er) instruction selection.
96 /// TM - Keep a reference to X86TargetMachine.
100 /// X86Lowering - This object fully describes how to lower LLVM code to an
101 /// X86-specific SelectionDAG.
102 X86TargetLowering X86Lowering;
104 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
105 /// make the right decision when generating code for different targets.
106 const X86Subtarget *Subtarget;
108 /// GlobalBaseReg - keeps track of the virtual register mapped onto global
110 unsigned GlobalBaseReg;
113 X86DAGToDAGISel(X86TargetMachine &tm, bool fast)
114 : SelectionDAGISel(X86Lowering),
115 ContainsFPCode(false), FastISel(fast), TM(tm),
116 X86Lowering(*TM.getTargetLowering()),
117 Subtarget(&TM.getSubtarget<X86Subtarget>()) {}
119 virtual bool runOnFunction(Function &Fn) {
120 // Make sure we re-emit a set of the global base reg if necessary
122 return SelectionDAGISel::runOnFunction(Fn);
125 virtual const char *getPassName() const {
126 return "X86 DAG->DAG Instruction Selection";
129 /// InstructionSelectBasicBlock - This callback is invoked by
130 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
131 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
133 virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF);
135 virtual bool CanBeFoldedBy(SDNode *N, SDNode *U, SDNode *Root) const;
137 // Include the pieces autogenerated from the target description.
138 #include "X86GenDAGISel.inc"
141 SDNode *Select(SDOperand N);
143 bool MatchAddress(SDOperand N, X86ISelAddressMode &AM,
144 bool isRoot = true, unsigned Depth = 0);
145 bool MatchAddressBase(SDOperand N, X86ISelAddressMode &AM,
146 bool isRoot, unsigned Depth);
147 bool SelectAddr(SDOperand Op, SDOperand N, SDOperand &Base,
148 SDOperand &Scale, SDOperand &Index, SDOperand &Disp);
149 bool SelectLEAAddr(SDOperand Op, SDOperand N, SDOperand &Base,
150 SDOperand &Scale, SDOperand &Index, SDOperand &Disp);
151 bool SelectScalarSSELoad(SDOperand Op, SDOperand Pred,
152 SDOperand N, SDOperand &Base, SDOperand &Scale,
153 SDOperand &Index, SDOperand &Disp,
154 SDOperand &InChain, SDOperand &OutChain);
155 bool TryFoldLoad(SDOperand P, SDOperand N,
156 SDOperand &Base, SDOperand &Scale,
157 SDOperand &Index, SDOperand &Disp);
158 void InstructionSelectPreprocess(SelectionDAG &DAG);
160 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
161 /// inline asm expressions.
162 virtual bool SelectInlineAsmMemoryOperand(const SDOperand &Op,
164 std::vector<SDOperand> &OutOps,
167 void EmitSpecialCodeForMain(MachineBasicBlock *BB, MachineFrameInfo *MFI);
169 inline void getAddressOperands(X86ISelAddressMode &AM, SDOperand &Base,
170 SDOperand &Scale, SDOperand &Index,
172 Base = (AM.BaseType == X86ISelAddressMode::FrameIndexBase) ?
173 CurDAG->getTargetFrameIndex(AM.Base.FrameIndex, TLI.getPointerTy()) :
175 Scale = getI8Imm(AM.Scale);
177 // These are 32-bit even in 64-bit mode since RIP relative offset
180 Disp = CurDAG->getTargetGlobalAddress(AM.GV, MVT::i32, AM.Disp);
182 Disp = CurDAG->getTargetConstantPool(AM.CP, MVT::i32, AM.Align, AM.Disp);
184 Disp = CurDAG->getTargetExternalSymbol(AM.ES, MVT::i32);
185 else if (AM.JT != -1)
186 Disp = CurDAG->getTargetJumpTable(AM.JT, MVT::i32);
188 Disp = getI32Imm(AM.Disp);
191 /// getI8Imm - Return a target constant with the specified value, of type
193 inline SDOperand getI8Imm(unsigned Imm) {
194 return CurDAG->getTargetConstant(Imm, MVT::i8);
197 /// getI16Imm - Return a target constant with the specified value, of type
199 inline SDOperand getI16Imm(unsigned Imm) {
200 return CurDAG->getTargetConstant(Imm, MVT::i16);
203 /// getI32Imm - Return a target constant with the specified value, of type
205 inline SDOperand getI32Imm(unsigned Imm) {
206 return CurDAG->getTargetConstant(Imm, MVT::i32);
209 /// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC
210 /// base register. Return the virtual register that holds this value.
211 SDNode *getGlobalBaseReg();
213 /// getTruncate - return an SDNode that implements a subreg based truncate
214 /// of the specified operand to the the specified value type.
215 SDNode *getTruncate(SDOperand N0, MVT::ValueType VT);
223 static SDNode *findFlagUse(SDNode *N) {
224 unsigned FlagResNo = N->getNumValues()-1;
225 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
227 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
228 SDOperand Op = User->getOperand(i);
229 if (Op.Val == N && Op.ResNo == FlagResNo)
236 static void findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
237 SDNode *Root, SDNode *Skip, bool &found,
238 std::set<SDNode *> &Visited) {
240 Use->getNodeId() > Def->getNodeId() ||
241 !Visited.insert(Use).second)
244 for (unsigned i = 0, e = Use->getNumOperands(); !found && i != e; ++i) {
245 SDNode *N = Use->getOperand(i).Val;
250 continue; // Immediate use is ok.
252 assert(Use->getOpcode() == ISD::STORE ||
253 Use->getOpcode() == X86ISD::CMP);
259 findNonImmUse(N, Def, ImmedUse, Root, Skip, found, Visited);
263 /// isNonImmUse - Start searching from Root up the DAG to check is Def can
264 /// be reached. Return true if that's the case. However, ignore direct uses
265 /// by ImmedUse (which would be U in the example illustrated in
266 /// CanBeFoldedBy) and by Root (which can happen in the store case).
267 /// FIXME: to be really generic, we should allow direct use by any node
268 /// that is being folded. But realisticly since we only fold loads which
269 /// have one non-chain use, we only need to watch out for load/op/store
270 /// and load/op/cmp case where the root (store / cmp) may reach the load via
271 /// its chain operand.
272 static inline bool isNonImmUse(SDNode *Root, SDNode *Def, SDNode *ImmedUse,
273 SDNode *Skip = NULL) {
274 std::set<SDNode *> Visited;
276 findNonImmUse(Root, Def, ImmedUse, Root, Skip, found, Visited);
281 bool X86DAGToDAGISel::CanBeFoldedBy(SDNode *N, SDNode *U, SDNode *Root) const {
282 if (FastISel) return false;
284 // If U use can somehow reach N through another path then U can't fold N or
285 // it will create a cycle. e.g. In the following diagram, U can reach N
286 // through X. If N is folded into into U, then X is both a predecessor and
297 if (isNonImmUse(Root, N, U))
300 // If U produces a flag, then it gets (even more) interesting. Since it
301 // would have been "glued" together with its flag use, we need to check if
314 // If FU (flag use) indirectly reach N (the load), and U fold N (call it
315 // NU), then TF is a predecessor of FU and a successor of NU. But since
316 // NU and FU are flagged together, this effectively creates a cycle.
317 bool HasFlagUse = false;
318 MVT::ValueType VT = Root->getValueType(Root->getNumValues()-1);
319 while ((VT == MVT::Flag && !Root->use_empty())) {
320 SDNode *FU = findFlagUse(Root);
327 VT = Root->getValueType(Root->getNumValues()-1);
331 return !isNonImmUse(Root, N, Root, U);
335 /// MoveBelowTokenFactor - Replace TokenFactor operand with load's chain operand
336 /// and move load below the TokenFactor. Replace store's chain operand with
337 /// load's chain result.
338 static void MoveBelowTokenFactor(SelectionDAG &DAG, SDOperand Load,
339 SDOperand Store, SDOperand TF) {
340 std::vector<SDOperand> Ops;
341 for (unsigned i = 0, e = TF.Val->getNumOperands(); i != e; ++i)
342 if (Load.Val == TF.Val->getOperand(i).Val)
343 Ops.push_back(Load.Val->getOperand(0));
345 Ops.push_back(TF.Val->getOperand(i));
346 DAG.UpdateNodeOperands(TF, &Ops[0], Ops.size());
347 DAG.UpdateNodeOperands(Load, TF, Load.getOperand(1), Load.getOperand(2));
348 DAG.UpdateNodeOperands(Store, Load.getValue(1), Store.getOperand(1),
349 Store.getOperand(2), Store.getOperand(3));
352 /// InstructionSelectPreprocess - Preprocess the DAG to allow the instruction
353 /// selector to pick more load-modify-store instructions. This is a common
364 /// [TokenFactor] [Op]
371 /// The fact the store's chain operand != load's chain will prevent the
372 /// (store (op (load))) instruction from being selected. We can transform it to:
391 void X86DAGToDAGISel::InstructionSelectPreprocess(SelectionDAG &DAG) {
392 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
393 E = DAG.allnodes_end(); I != E; ++I) {
394 if (!ISD::isNON_TRUNCStore(I))
396 SDOperand Chain = I->getOperand(0);
397 if (Chain.Val->getOpcode() != ISD::TokenFactor)
400 SDOperand N1 = I->getOperand(1);
401 SDOperand N2 = I->getOperand(2);
402 if (MVT::isFloatingPoint(N1.getValueType()) ||
403 MVT::isVector(N1.getValueType()) ||
409 unsigned Opcode = N1.Val->getOpcode();
418 SDOperand N10 = N1.getOperand(0);
419 SDOperand N11 = N1.getOperand(1);
420 if (ISD::isNON_EXTLoad(N10.Val))
422 else if (ISD::isNON_EXTLoad(N11.Val)) {
426 RModW = RModW && N10.Val->isOperand(Chain.Val) && N10.hasOneUse() &&
427 (N10.getOperand(1) == N2) &&
428 (N10.Val->getValueType(0) == N1.getValueType());
443 SDOperand N10 = N1.getOperand(0);
444 if (ISD::isNON_EXTLoad(N10.Val))
445 RModW = N10.Val->isOperand(Chain.Val) && N10.hasOneUse() &&
446 (N10.getOperand(1) == N2) &&
447 (N10.Val->getValueType(0) == N1.getValueType());
455 MoveBelowTokenFactor(DAG, Load, SDOperand(I, 0), Chain);
461 /// InstructionSelectBasicBlock - This callback is invoked by SelectionDAGISel
462 /// when it has created a SelectionDAG for us to codegen.
463 void X86DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
465 MachineFunction::iterator FirstMBB = BB;
468 InstructionSelectPreprocess(DAG);
470 // Codegen the basic block.
472 DOUT << "===== Instruction selection begins:\n";
475 DAG.setRoot(SelectRoot(DAG.getRoot()));
477 DOUT << "===== Instruction selection ends:\n";
480 DAG.RemoveDeadNodes();
482 // Emit machine code to BB.
483 ScheduleAndEmitDAG(DAG);
485 // If we are emitting FP stack code, scan the basic block to determine if this
486 // block defines any FP values. If so, put an FP_REG_KILL instruction before
487 // the terminator of the block.
489 // Note that FP stack instructions are used in all modes for long double,
490 // so we always need to do this check.
491 // Also note that it's possible for an FP stack register to be live across
492 // an instruction that produces multiple basic blocks (SSE CMOV) so we
493 // must check all the generated basic blocks.
495 // Scan all of the machine instructions in these MBBs, checking for FP
496 // stores. (RFP32 and RFP64 will not exist in SSE mode, but RFP80 might.)
497 MachineFunction::iterator MBBI = FirstMBB;
499 bool ContainsFPCode = false;
500 for (MachineBasicBlock::iterator I = MBBI->begin(), E = MBBI->end();
501 !ContainsFPCode && I != E; ++I) {
502 if (I->getNumOperands() != 0 && I->getOperand(0).isRegister()) {
503 const TargetRegisterClass *clas;
504 for (unsigned op = 0, e = I->getNumOperands(); op != e; ++op) {
505 if (I->getOperand(op).isRegister() && I->getOperand(op).isDef() &&
506 MRegisterInfo::isVirtualRegister(I->getOperand(op).getReg()) &&
507 ((clas = RegMap->getRegClass(I->getOperand(0).getReg())) ==
508 X86::RFP32RegisterClass ||
509 clas == X86::RFP64RegisterClass ||
510 clas == X86::RFP80RegisterClass)) {
511 ContainsFPCode = true;
517 // Check PHI nodes in successor blocks. These PHI's will be lowered to have
518 // a copy of the input value in this block. In SSE mode, we only care about
520 if (!ContainsFPCode) {
521 // Final check, check LLVM BB's that are successors to the LLVM BB
522 // corresponding to BB for FP PHI nodes.
523 const BasicBlock *LLVMBB = BB->getBasicBlock();
525 for (succ_const_iterator SI = succ_begin(LLVMBB), E = succ_end(LLVMBB);
526 !ContainsFPCode && SI != E; ++SI) {
527 for (BasicBlock::const_iterator II = SI->begin();
528 (PN = dyn_cast<PHINode>(II)); ++II) {
529 if (PN->getType()==Type::X86_FP80Ty ||
530 (!Subtarget->hasSSE1() && PN->getType()->isFloatingPoint()) ||
531 (!Subtarget->hasSSE2() && PN->getType()==Type::DoubleTy)) {
532 ContainsFPCode = true;
538 // Finally, if we found any FP code, emit the FP_REG_KILL instruction.
539 if (ContainsFPCode) {
540 BuildMI(*MBBI, MBBI->getFirstTerminator(),
541 TM.getInstrInfo()->get(X86::FP_REG_KILL));
544 } while (&*(MBBI++) != BB);
547 /// EmitSpecialCodeForMain - Emit any code that needs to be executed only in
548 /// the main function.
549 void X86DAGToDAGISel::EmitSpecialCodeForMain(MachineBasicBlock *BB,
550 MachineFrameInfo *MFI) {
551 const TargetInstrInfo *TII = TM.getInstrInfo();
552 if (Subtarget->isTargetCygMing())
553 BuildMI(BB, TII->get(X86::CALLpcrel32)).addExternalSymbol("__main");
556 void X86DAGToDAGISel::EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {
557 // If this is main, emit special code for main.
558 MachineBasicBlock *BB = MF.begin();
559 if (Fn.hasExternalLinkage() && Fn.getName() == "main")
560 EmitSpecialCodeForMain(BB, MF.getFrameInfo());
563 /// MatchAddress - Add the specified node to the specified addressing mode,
564 /// returning true if it cannot be done. This just pattern matches for the
566 bool X86DAGToDAGISel::MatchAddress(SDOperand N, X86ISelAddressMode &AM,
567 bool isRoot, unsigned Depth) {
570 return MatchAddressBase(N, AM, isRoot, Depth);
572 // RIP relative addressing: %rip + 32-bit displacement!
574 if (!AM.ES && AM.JT != -1 && N.getOpcode() == ISD::Constant) {
575 int64_t Val = cast<ConstantSDNode>(N)->getSignExtended();
576 if (isInt32(AM.Disp + Val)) {
584 int id = N.Val->getNodeId();
585 bool Available = isSelected(id);
587 switch (N.getOpcode()) {
589 case ISD::Constant: {
590 int64_t Val = cast<ConstantSDNode>(N)->getSignExtended();
591 if (isInt32(AM.Disp + Val)) {
598 case X86ISD::Wrapper: {
599 bool is64Bit = Subtarget->is64Bit();
600 // Under X86-64 non-small code model, GV (and friends) are 64-bits.
601 if (is64Bit && TM.getCodeModel() != CodeModel::Small)
603 if (AM.GV != 0 || AM.CP != 0 || AM.ES != 0 || AM.JT != -1)
605 // If value is available in a register both base and index components have
606 // been picked, we can't fit the result available in the register in the
607 // addressing mode. Duplicate GlobalAddress or ConstantPool as displacement.
608 if (!Available || (AM.Base.Reg.Val && AM.IndexReg.Val)) {
609 bool isStatic = TM.getRelocationModel() == Reloc::Static;
610 SDOperand N0 = N.getOperand(0);
611 // Mac OS X X86-64 lower 4G address is not available.
612 bool isAbs32 = !is64Bit ||
613 (isStatic && Subtarget->hasLow4GUserSpaceAddress());
614 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
615 GlobalValue *GV = G->getGlobal();
616 if (isAbs32 || isRoot) {
618 AM.Disp += G->getOffset();
619 AM.isRIPRel = !isAbs32;
622 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) {
623 if (isAbs32 || isRoot) {
624 AM.CP = CP->getConstVal();
625 AM.Align = CP->getAlignment();
626 AM.Disp += CP->getOffset();
627 AM.isRIPRel = !isAbs32;
630 } else if (ExternalSymbolSDNode *S =dyn_cast<ExternalSymbolSDNode>(N0)) {
631 if (isAbs32 || isRoot) {
632 AM.ES = S->getSymbol();
633 AM.isRIPRel = !isAbs32;
636 } else if (JumpTableSDNode *J = dyn_cast<JumpTableSDNode>(N0)) {
637 if (isAbs32 || isRoot) {
638 AM.JT = J->getIndex();
639 AM.isRIPRel = !isAbs32;
647 case ISD::FrameIndex:
648 if (AM.BaseType == X86ISelAddressMode::RegBase && AM.Base.Reg.Val == 0) {
649 AM.BaseType = X86ISelAddressMode::FrameIndexBase;
650 AM.Base.FrameIndex = cast<FrameIndexSDNode>(N)->getIndex();
656 if (Available || AM.IndexReg.Val != 0 || AM.Scale != 1)
659 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.Val->getOperand(1))) {
660 unsigned Val = CN->getValue();
661 if (Val == 1 || Val == 2 || Val == 3) {
663 SDOperand ShVal = N.Val->getOperand(0);
665 // Okay, we know that we have a scale by now. However, if the scaled
666 // value is an add of something and a constant, we can fold the
667 // constant into the disp field here.
668 if (ShVal.Val->getOpcode() == ISD::ADD && ShVal.hasOneUse() &&
669 isa<ConstantSDNode>(ShVal.Val->getOperand(1))) {
670 AM.IndexReg = ShVal.Val->getOperand(0);
671 ConstantSDNode *AddVal =
672 cast<ConstantSDNode>(ShVal.Val->getOperand(1));
673 uint64_t Disp = AM.Disp + (AddVal->getValue() << Val);
688 // A mul_lohi where we need the low part can be folded as a plain multiply.
689 if (N.ResNo != 0) break;
692 // X*[3,5,9] -> X+X*[2,4,8]
694 AM.BaseType == X86ISelAddressMode::RegBase &&
695 AM.Base.Reg.Val == 0 &&
696 AM.IndexReg.Val == 0) {
697 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.Val->getOperand(1)))
698 if (CN->getValue() == 3 || CN->getValue() == 5 || CN->getValue() == 9) {
699 AM.Scale = unsigned(CN->getValue())-1;
701 SDOperand MulVal = N.Val->getOperand(0);
704 // Okay, we know that we have a scale by now. However, if the scaled
705 // value is an add of something and a constant, we can fold the
706 // constant into the disp field here.
707 if (MulVal.Val->getOpcode() == ISD::ADD && MulVal.hasOneUse() &&
708 isa<ConstantSDNode>(MulVal.Val->getOperand(1))) {
709 Reg = MulVal.Val->getOperand(0);
710 ConstantSDNode *AddVal =
711 cast<ConstantSDNode>(MulVal.Val->getOperand(1));
712 uint64_t Disp = AM.Disp + AddVal->getValue() * CN->getValue();
716 Reg = N.Val->getOperand(0);
718 Reg = N.Val->getOperand(0);
721 AM.IndexReg = AM.Base.Reg = Reg;
729 X86ISelAddressMode Backup = AM;
730 if (!MatchAddress(N.Val->getOperand(0), AM, false, Depth+1) &&
731 !MatchAddress(N.Val->getOperand(1), AM, false, Depth+1))
734 if (!MatchAddress(N.Val->getOperand(1), AM, false, Depth+1) &&
735 !MatchAddress(N.Val->getOperand(0), AM, false, Depth+1))
742 // Handle "X | C" as "X + C" iff X is known to have C bits clear.
743 if (Available) break;
745 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
746 X86ISelAddressMode Backup = AM;
747 // Start with the LHS as an addr mode.
748 if (!MatchAddress(N.getOperand(0), AM, false) &&
749 // Address could not have picked a GV address for the displacement.
751 // On x86-64, the resultant disp must fit in 32-bits.
752 isInt32(AM.Disp + CN->getSignExtended()) &&
753 // Check to see if the LHS & C is zero.
754 CurDAG->MaskedValueIsZero(N.getOperand(0), CN->getValue())) {
755 AM.Disp += CN->getValue();
763 return MatchAddressBase(N, AM, isRoot, Depth);
766 /// MatchAddressBase - Helper for MatchAddress. Add the specified node to the
767 /// specified addressing mode without any further recursion.
768 bool X86DAGToDAGISel::MatchAddressBase(SDOperand N, X86ISelAddressMode &AM,
769 bool isRoot, unsigned Depth) {
770 // Is the base register already occupied?
771 if (AM.BaseType != X86ISelAddressMode::RegBase || AM.Base.Reg.Val) {
772 // If so, check to see if the scale index register is set.
773 if (AM.IndexReg.Val == 0) {
779 // Otherwise, we cannot select it.
783 // Default, generate it as a register.
784 AM.BaseType = X86ISelAddressMode::RegBase;
789 /// SelectAddr - returns true if it is able pattern match an addressing mode.
790 /// It returns the operands which make up the maximal addressing mode it can
791 /// match by reference.
792 bool X86DAGToDAGISel::SelectAddr(SDOperand Op, SDOperand N, SDOperand &Base,
793 SDOperand &Scale, SDOperand &Index,
795 X86ISelAddressMode AM;
796 if (MatchAddress(N, AM))
799 MVT::ValueType VT = N.getValueType();
800 if (AM.BaseType == X86ISelAddressMode::RegBase) {
801 if (!AM.Base.Reg.Val)
802 AM.Base.Reg = CurDAG->getRegister(0, VT);
805 if (!AM.IndexReg.Val)
806 AM.IndexReg = CurDAG->getRegister(0, VT);
808 getAddressOperands(AM, Base, Scale, Index, Disp);
812 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
814 static inline bool isZeroNode(SDOperand Elt) {
815 return ((isa<ConstantSDNode>(Elt) &&
816 cast<ConstantSDNode>(Elt)->getValue() == 0) ||
817 (isa<ConstantFPSDNode>(Elt) &&
818 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
822 /// SelectScalarSSELoad - Match a scalar SSE load. In particular, we want to
823 /// match a load whose top elements are either undef or zeros. The load flavor
824 /// is derived from the type of N, which is either v4f32 or v2f64.
825 bool X86DAGToDAGISel::SelectScalarSSELoad(SDOperand Op, SDOperand Pred,
826 SDOperand N, SDOperand &Base,
827 SDOperand &Scale, SDOperand &Index,
828 SDOperand &Disp, SDOperand &InChain,
829 SDOperand &OutChain) {
830 if (N.getOpcode() == ISD::SCALAR_TO_VECTOR) {
831 InChain = N.getOperand(0).getValue(1);
832 if (ISD::isNON_EXTLoad(InChain.Val) &&
833 InChain.getValue(0).hasOneUse() &&
835 CanBeFoldedBy(N.Val, Pred.Val, Op.Val)) {
836 LoadSDNode *LD = cast<LoadSDNode>(InChain);
837 if (!SelectAddr(Op, LD->getBasePtr(), Base, Scale, Index, Disp))
839 OutChain = LD->getChain();
844 // Also handle the case where we explicitly require zeros in the top
845 // elements. This is a vector shuffle from the zero vector.
846 if (N.getOpcode() == ISD::VECTOR_SHUFFLE && N.Val->hasOneUse() &&
847 // Check to see if the top elements are all zeros (or bitcast of zeros).
848 ISD::isBuildVectorAllZeros(N.getOperand(0).Val) &&
849 N.getOperand(1).getOpcode() == ISD::SCALAR_TO_VECTOR &&
850 N.getOperand(1).Val->hasOneUse() &&
851 ISD::isNON_EXTLoad(N.getOperand(1).getOperand(0).Val) &&
852 N.getOperand(1).getOperand(0).hasOneUse()) {
853 // Check to see if the shuffle mask is 4/L/L/L or 2/L, where L is something
855 unsigned VecWidth=MVT::getVectorNumElements(N.getOperand(0).getValueType());
856 SDOperand ShufMask = N.getOperand(2);
857 assert(ShufMask.getOpcode() == ISD::BUILD_VECTOR && "Invalid shuf mask!");
858 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(ShufMask.getOperand(0))) {
859 if (C->getValue() == VecWidth) {
860 for (unsigned i = 1; i != VecWidth; ++i) {
861 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF) {
864 ConstantSDNode *C = cast<ConstantSDNode>(ShufMask.getOperand(i));
865 if (C->getValue() >= VecWidth) return false;
870 // Okay, this is a zero extending load. Fold it.
871 LoadSDNode *LD = cast<LoadSDNode>(N.getOperand(1).getOperand(0));
872 if (!SelectAddr(Op, LD->getBasePtr(), Base, Scale, Index, Disp))
874 OutChain = LD->getChain();
875 InChain = SDOperand(LD, 1);
883 /// SelectLEAAddr - it calls SelectAddr and determines if the maximal addressing
884 /// mode it matches can be cost effectively emitted as an LEA instruction.
885 bool X86DAGToDAGISel::SelectLEAAddr(SDOperand Op, SDOperand N,
886 SDOperand &Base, SDOperand &Scale,
887 SDOperand &Index, SDOperand &Disp) {
888 X86ISelAddressMode AM;
889 if (MatchAddress(N, AM))
892 MVT::ValueType VT = N.getValueType();
893 unsigned Complexity = 0;
894 if (AM.BaseType == X86ISelAddressMode::RegBase)
898 AM.Base.Reg = CurDAG->getRegister(0, VT);
899 else if (AM.BaseType == X86ISelAddressMode::FrameIndexBase)
905 AM.IndexReg = CurDAG->getRegister(0, VT);
907 // Don't match just leal(,%reg,2). It's cheaper to do addl %reg, %reg, or with
912 // FIXME: We are artificially lowering the criteria to turn ADD %reg, $GA
913 // to a LEA. This is determined with some expermentation but is by no means
914 // optimal (especially for code size consideration). LEA is nice because of
915 // its three-address nature. Tweak the cost function again when we can run
916 // convertToThreeAddress() at register allocation time.
917 if (AM.GV || AM.CP || AM.ES || AM.JT != -1) {
918 // For X86-64, we should always use lea to materialize RIP relative
920 if (Subtarget->is64Bit())
926 if (AM.Disp && (AM.Base.Reg.Val || AM.IndexReg.Val))
929 if (Complexity > 2) {
930 getAddressOperands(AM, Base, Scale, Index, Disp);
936 bool X86DAGToDAGISel::TryFoldLoad(SDOperand P, SDOperand N,
937 SDOperand &Base, SDOperand &Scale,
938 SDOperand &Index, SDOperand &Disp) {
939 if (ISD::isNON_EXTLoad(N.Val) &&
941 CanBeFoldedBy(N.Val, P.Val, P.Val))
942 return SelectAddr(P, N.getOperand(1), Base, Scale, Index, Disp);
946 /// getGlobalBaseReg - Output the instructions required to put the
947 /// base address to use for accessing globals into a register.
949 SDNode *X86DAGToDAGISel::getGlobalBaseReg() {
950 assert(!Subtarget->is64Bit() && "X86-64 PIC uses RIP relative addressing");
951 if (!GlobalBaseReg) {
952 // Insert the set of GlobalBaseReg into the first MBB of the function
953 MachineBasicBlock &FirstMBB = BB->getParent()->front();
954 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
955 SSARegMap *RegMap = BB->getParent()->getSSARegMap();
956 unsigned PC = RegMap->createVirtualRegister(X86::GR32RegisterClass);
958 const TargetInstrInfo *TII = TM.getInstrInfo();
959 BuildMI(FirstMBB, MBBI, TII->get(X86::MovePCtoStack));
960 BuildMI(FirstMBB, MBBI, TII->get(X86::POP32r), PC);
962 // If we're using vanilla 'GOT' PIC style, we should use relative addressing
963 // not to pc, but to _GLOBAL_ADDRESS_TABLE_ external
964 if (TM.getRelocationModel() == Reloc::PIC_ &&
965 Subtarget->isPICStyleGOT()) {
966 GlobalBaseReg = RegMap->createVirtualRegister(X86::GR32RegisterClass);
967 BuildMI(FirstMBB, MBBI, TII->get(X86::ADD32ri), GlobalBaseReg).
969 addExternalSymbol("_GLOBAL_OFFSET_TABLE_");
975 return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).Val;
978 static SDNode *FindCallStartFromCall(SDNode *Node) {
979 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
980 assert(Node->getOperand(0).getValueType() == MVT::Other &&
981 "Node doesn't have a token chain argument!");
982 return FindCallStartFromCall(Node->getOperand(0).Val);
985 SDNode *X86DAGToDAGISel::getTruncate(SDOperand N0, MVT::ValueType VT) {
989 SRIdx = CurDAG->getTargetConstant(1, MVT::i32); // SubRegSet 1
990 // Ensure that the source register has an 8-bit subreg on 32-bit targets
991 if (!Subtarget->is64Bit()) {
994 switch (N0.getValueType()) {
995 default: assert(0 && "Unknown truncate!");
997 Opc = X86::MOV16to16_;
1001 Opc = X86::MOV32to32_;
1005 N0 = SDOperand(CurDAG->getTargetNode(Opc, VT, MVT::Flag, N0), 0);
1006 return CurDAG->getTargetNode(X86::EXTRACT_SUBREG,
1007 VT, N0, SRIdx, N0.getValue(1));
1011 SRIdx = CurDAG->getTargetConstant(2, MVT::i32); // SubRegSet 2
1014 SRIdx = CurDAG->getTargetConstant(3, MVT::i32); // SubRegSet 3
1016 default: assert(0 && "Unknown truncate!"); break;
1018 return CurDAG->getTargetNode(X86::EXTRACT_SUBREG, VT, N0, SRIdx);
1022 SDNode *X86DAGToDAGISel::Select(SDOperand N) {
1023 SDNode *Node = N.Val;
1024 MVT::ValueType NVT = Node->getValueType(0);
1026 unsigned Opcode = Node->getOpcode();
1029 DOUT << std::string(Indent, ' ') << "Selecting: ";
1030 DEBUG(Node->dump(CurDAG));
1035 if (Opcode >= ISD::BUILTIN_OP_END && Opcode < X86ISD::FIRST_NUMBER) {
1037 DOUT << std::string(Indent-2, ' ') << "== ";
1038 DEBUG(Node->dump(CurDAG));
1042 return NULL; // Already selected.
1047 case X86ISD::GlobalBaseReg:
1048 return getGlobalBaseReg();
1051 // Turn ADD X, c to MOV32ri X+c. This cannot be done with tblgen'd
1052 // code and is matched first so to prevent it from being turned into
1054 // In 64-bit mode, use LEA to take advantage of RIP-relative addressing.
1055 MVT::ValueType PtrVT = TLI.getPointerTy();
1056 SDOperand N0 = N.getOperand(0);
1057 SDOperand N1 = N.getOperand(1);
1058 if (N.Val->getValueType(0) == PtrVT &&
1059 N0.getOpcode() == X86ISD::Wrapper &&
1060 N1.getOpcode() == ISD::Constant) {
1061 unsigned Offset = (unsigned)cast<ConstantSDNode>(N1)->getValue();
1063 // TODO: handle ExternalSymbolSDNode.
1064 if (GlobalAddressSDNode *G =
1065 dyn_cast<GlobalAddressSDNode>(N0.getOperand(0))) {
1066 C = CurDAG->getTargetGlobalAddress(G->getGlobal(), PtrVT,
1067 G->getOffset() + Offset);
1068 } else if (ConstantPoolSDNode *CP =
1069 dyn_cast<ConstantPoolSDNode>(N0.getOperand(0))) {
1070 C = CurDAG->getTargetConstantPool(CP->getConstVal(), PtrVT,
1072 CP->getOffset()+Offset);
1076 if (Subtarget->is64Bit()) {
1077 SDOperand Ops[] = { CurDAG->getRegister(0, PtrVT), getI8Imm(1),
1078 CurDAG->getRegister(0, PtrVT), C };
1079 return CurDAG->SelectNodeTo(N.Val, X86::LEA64r, MVT::i64, Ops, 4);
1081 return CurDAG->SelectNodeTo(N.Val, X86::MOV32ri, PtrVT, C);
1085 // Other cases are handled by auto-generated code.
1089 case ISD::SMUL_LOHI:
1090 case ISD::UMUL_LOHI: {
1091 SDOperand N0 = Node->getOperand(0);
1092 SDOperand N1 = Node->getOperand(1);
1094 // There are several forms of IMUL that just return the low part and
1095 // don't have fixed-register operands. If we don't need the high part,
1096 // use these instead. They can be selected with the generated ISel code.
1097 if (NVT != MVT::i8 &&
1098 N.getValue(1).use_empty()) {
1099 N = CurDAG->getNode(ISD::MUL, NVT, N0, N1);
1103 bool isSigned = Opcode == ISD::SMUL_LOHI;
1106 default: assert(0 && "Unsupported VT!");
1107 case MVT::i8: Opc = X86::MUL8r; MOpc = X86::MUL8m; break;
1108 case MVT::i16: Opc = X86::MUL16r; MOpc = X86::MUL16m; break;
1109 case MVT::i32: Opc = X86::MUL32r; MOpc = X86::MUL32m; break;
1110 case MVT::i64: Opc = X86::MUL64r; MOpc = X86::MUL64m; break;
1114 default: assert(0 && "Unsupported VT!");
1115 case MVT::i8: Opc = X86::IMUL8r; MOpc = X86::IMUL8m; break;
1116 case MVT::i16: Opc = X86::IMUL16r; MOpc = X86::IMUL16m; break;
1117 case MVT::i32: Opc = X86::IMUL32r; MOpc = X86::IMUL32m; break;
1118 case MVT::i64: Opc = X86::IMUL64r; MOpc = X86::IMUL64m; break;
1121 unsigned LoReg, HiReg;
1123 default: assert(0 && "Unsupported VT!");
1124 case MVT::i8: LoReg = X86::AL; HiReg = X86::AH; break;
1125 case MVT::i16: LoReg = X86::AX; HiReg = X86::DX; break;
1126 case MVT::i32: LoReg = X86::EAX; HiReg = X86::EDX; break;
1127 case MVT::i64: LoReg = X86::RAX; HiReg = X86::RDX; break;
1130 SDOperand Tmp0, Tmp1, Tmp2, Tmp3;
1131 bool foldedLoad = TryFoldLoad(N, N1, Tmp0, Tmp1, Tmp2, Tmp3);
1132 // multiplty is commmutative
1134 foldedLoad = TryFoldLoad(N, N0, Tmp0, Tmp1, Tmp2, Tmp3);
1140 SDOperand InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), LoReg,
1141 N0, SDOperand()).getValue(1);
1144 AddToISelQueue(N1.getOperand(0));
1145 AddToISelQueue(Tmp0);
1146 AddToISelQueue(Tmp1);
1147 AddToISelQueue(Tmp2);
1148 AddToISelQueue(Tmp3);
1149 SDOperand Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, N1.getOperand(0), InFlag };
1151 CurDAG->getTargetNode(MOpc, MVT::Other, MVT::Flag, Ops, 6);
1152 InFlag = SDOperand(CNode, 1);
1153 // Update the chain.
1154 ReplaceUses(N1.getValue(1), SDOperand(CNode, 0));
1158 SDOperand(CurDAG->getTargetNode(Opc, MVT::Flag, N1, InFlag), 0);
1161 // Copy the low half of the result, if it is needed.
1162 if (!N.getValue(0).use_empty()) {
1163 SDOperand Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
1164 LoReg, NVT, InFlag);
1165 InFlag = Result.getValue(2);
1166 ReplaceUses(N.getValue(0), Result);
1168 DOUT << std::string(Indent-2, ' ') << "=> ";
1169 DEBUG(Result.Val->dump(CurDAG));
1173 // Copy the high half of the result, if it is needed.
1174 if (!N.getValue(1).use_empty()) {
1176 if (HiReg == X86::AH && Subtarget->is64Bit()) {
1177 // Prevent use of AH in a REX instruction by referencing AX instead.
1178 // Shift it down 8 bits.
1179 Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
1180 X86::AX, MVT::i16, InFlag);
1181 InFlag = Result.getValue(2);
1182 Result = SDOperand(CurDAG->getTargetNode(X86::SHR16ri, MVT::i16, Result,
1183 CurDAG->getTargetConstant(8, MVT::i8)), 0);
1184 // Then truncate it down to i8.
1185 SDOperand SRIdx = CurDAG->getTargetConstant(1, MVT::i32); // SubRegSet 1
1186 Result = SDOperand(CurDAG->getTargetNode(X86::EXTRACT_SUBREG,
1187 MVT::i8, Result, SRIdx), 0);
1189 Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
1190 HiReg, NVT, InFlag);
1191 InFlag = Result.getValue(2);
1193 ReplaceUses(N.getValue(1), Result);
1195 DOUT << std::string(Indent-2, ' ') << "=> ";
1196 DEBUG(Result.Val->dump(CurDAG));
1209 case ISD::UDIVREM: {
1210 SDOperand N0 = Node->getOperand(0);
1211 SDOperand N1 = Node->getOperand(1);
1213 bool isSigned = Opcode == ISD::SDIVREM;
1216 default: assert(0 && "Unsupported VT!");
1217 case MVT::i8: Opc = X86::DIV8r; MOpc = X86::DIV8m; break;
1218 case MVT::i16: Opc = X86::DIV16r; MOpc = X86::DIV16m; break;
1219 case MVT::i32: Opc = X86::DIV32r; MOpc = X86::DIV32m; break;
1220 case MVT::i64: Opc = X86::DIV64r; MOpc = X86::DIV64m; break;
1224 default: assert(0 && "Unsupported VT!");
1225 case MVT::i8: Opc = X86::IDIV8r; MOpc = X86::IDIV8m; break;
1226 case MVT::i16: Opc = X86::IDIV16r; MOpc = X86::IDIV16m; break;
1227 case MVT::i32: Opc = X86::IDIV32r; MOpc = X86::IDIV32m; break;
1228 case MVT::i64: Opc = X86::IDIV64r; MOpc = X86::IDIV64m; break;
1231 unsigned LoReg, HiReg;
1232 unsigned ClrOpcode, SExtOpcode;
1234 default: assert(0 && "Unsupported VT!");
1236 LoReg = X86::AL; HiReg = X86::AH;
1238 SExtOpcode = X86::CBW;
1241 LoReg = X86::AX; HiReg = X86::DX;
1242 ClrOpcode = X86::MOV16r0;
1243 SExtOpcode = X86::CWD;
1246 LoReg = X86::EAX; HiReg = X86::EDX;
1247 ClrOpcode = X86::MOV32r0;
1248 SExtOpcode = X86::CDQ;
1251 LoReg = X86::RAX; HiReg = X86::RDX;
1252 ClrOpcode = X86::MOV64r0;
1253 SExtOpcode = X86::CQO;
1257 SDOperand Tmp0, Tmp1, Tmp2, Tmp3;
1258 bool foldedLoad = TryFoldLoad(N, N1, Tmp0, Tmp1, Tmp2, Tmp3);
1261 if (NVT == MVT::i8 && !isSigned) {
1262 // Special case for div8, just use a move with zero extension to AX to
1263 // clear the upper 8 bits (AH).
1264 SDOperand Tmp0, Tmp1, Tmp2, Tmp3, Move, Chain;
1265 if (TryFoldLoad(N, N0, Tmp0, Tmp1, Tmp2, Tmp3)) {
1266 SDOperand Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, N0.getOperand(0) };
1267 AddToISelQueue(N0.getOperand(0));
1268 AddToISelQueue(Tmp0);
1269 AddToISelQueue(Tmp1);
1270 AddToISelQueue(Tmp2);
1271 AddToISelQueue(Tmp3);
1273 SDOperand(CurDAG->getTargetNode(X86::MOVZX16rm8, MVT::i16, MVT::Other,
1275 Chain = Move.getValue(1);
1276 ReplaceUses(N0.getValue(1), Chain);
1280 SDOperand(CurDAG->getTargetNode(X86::MOVZX16rr8, MVT::i16, N0), 0);
1281 Chain = CurDAG->getEntryNode();
1283 Chain = CurDAG->getCopyToReg(Chain, X86::AX, Move, SDOperand());
1284 InFlag = Chain.getValue(1);
1288 CurDAG->getCopyToReg(CurDAG->getEntryNode(),
1289 LoReg, N0, SDOperand()).getValue(1);
1291 // Sign extend the low part into the high part.
1293 SDOperand(CurDAG->getTargetNode(SExtOpcode, MVT::Flag, InFlag), 0);
1295 // Zero out the high part, effectively zero extending the input.
1296 SDOperand ClrNode = SDOperand(CurDAG->getTargetNode(ClrOpcode, NVT), 0);
1297 InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), HiReg,
1298 ClrNode, InFlag).getValue(1);
1303 AddToISelQueue(N1.getOperand(0));
1304 AddToISelQueue(Tmp0);
1305 AddToISelQueue(Tmp1);
1306 AddToISelQueue(Tmp2);
1307 AddToISelQueue(Tmp3);
1308 SDOperand Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, N1.getOperand(0), InFlag };
1310 CurDAG->getTargetNode(MOpc, MVT::Other, MVT::Flag, Ops, 6);
1311 InFlag = SDOperand(CNode, 1);
1312 // Update the chain.
1313 ReplaceUses(N1.getValue(1), SDOperand(CNode, 0));
1317 SDOperand(CurDAG->getTargetNode(Opc, MVT::Flag, N1, InFlag), 0);
1320 // Copy the division (low) result, if it is needed.
1321 if (!N.getValue(0).use_empty()) {
1322 SDOperand Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
1323 LoReg, NVT, InFlag);
1324 InFlag = Result.getValue(2);
1325 ReplaceUses(N.getValue(0), Result);
1327 DOUT << std::string(Indent-2, ' ') << "=> ";
1328 DEBUG(Result.Val->dump(CurDAG));
1332 // Copy the remainder (high) result, if it is needed.
1333 if (!N.getValue(1).use_empty()) {
1335 if (HiReg == X86::AH && Subtarget->is64Bit()) {
1336 // Prevent use of AH in a REX instruction by referencing AX instead.
1337 // Shift it down 8 bits.
1338 Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
1339 X86::AX, MVT::i16, InFlag);
1340 InFlag = Result.getValue(2);
1341 Result = SDOperand(CurDAG->getTargetNode(X86::SHR16ri, MVT::i16, Result,
1342 CurDAG->getTargetConstant(8, MVT::i8)), 0);
1343 // Then truncate it down to i8.
1344 SDOperand SRIdx = CurDAG->getTargetConstant(1, MVT::i32); // SubRegSet 1
1345 Result = SDOperand(CurDAG->getTargetNode(X86::EXTRACT_SUBREG,
1346 MVT::i8, Result, SRIdx), 0);
1348 Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
1349 HiReg, NVT, InFlag);
1350 InFlag = Result.getValue(2);
1352 ReplaceUses(N.getValue(1), Result);
1354 DOUT << std::string(Indent-2, ' ') << "=> ";
1355 DEBUG(Result.Val->dump(CurDAG));
1367 case ISD::ANY_EXTEND: {
1368 SDOperand N0 = Node->getOperand(0);
1370 if (NVT == MVT::i64 || NVT == MVT::i32 || NVT == MVT::i16) {
1372 switch(N0.getValueType()) {
1374 SRIdx = CurDAG->getTargetConstant(3, MVT::i32); // SubRegSet 3
1377 SRIdx = CurDAG->getTargetConstant(2, MVT::i32); // SubRegSet 2
1380 if (Subtarget->is64Bit())
1381 SRIdx = CurDAG->getTargetConstant(1, MVT::i32); // SubRegSet 1
1383 default: assert(0 && "Unknown any_extend!");
1386 SDNode *ResNode = CurDAG->getTargetNode(X86::INSERT_SUBREG,
1390 DOUT << std::string(Indent-2, ' ') << "=> ";
1391 DEBUG(ResNode->dump(CurDAG));
1396 } // Otherwise let generated ISel handle it.
1401 case ISD::SIGN_EXTEND_INREG: {
1402 SDOperand N0 = Node->getOperand(0);
1405 MVT::ValueType SVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
1406 SDOperand TruncOp = SDOperand(getTruncate(N0, SVT), 0);
1410 if (SVT == MVT::i8) Opc = X86::MOVSX16rr8;
1411 else assert(0 && "Unknown sign_extend_inreg!");
1415 case MVT::i8: Opc = X86::MOVSX32rr8; break;
1416 case MVT::i16: Opc = X86::MOVSX32rr16; break;
1417 default: assert(0 && "Unknown sign_extend_inreg!");
1422 case MVT::i8: Opc = X86::MOVSX64rr8; break;
1423 case MVT::i16: Opc = X86::MOVSX64rr16; break;
1424 case MVT::i32: Opc = X86::MOVSX64rr32; break;
1425 default: assert(0 && "Unknown sign_extend_inreg!");
1428 default: assert(0 && "Unknown sign_extend_inreg!");
1431 SDNode *ResNode = CurDAG->getTargetNode(Opc, NVT, TruncOp);
1434 DOUT << std::string(Indent-2, ' ') << "=> ";
1435 DEBUG(TruncOp.Val->dump(CurDAG));
1437 DOUT << std::string(Indent-2, ' ') << "=> ";
1438 DEBUG(ResNode->dump(CurDAG));
1446 case ISD::TRUNCATE: {
1447 SDOperand Input = Node->getOperand(0);
1448 AddToISelQueue(Node->getOperand(0));
1449 SDNode *ResNode = getTruncate(Input, NVT);
1452 DOUT << std::string(Indent-2, ' ') << "=> ";
1453 DEBUG(ResNode->dump(CurDAG));
1462 SDNode *ResNode = SelectCode(N);
1465 DOUT << std::string(Indent-2, ' ') << "=> ";
1466 if (ResNode == NULL || ResNode == N.Val)
1467 DEBUG(N.Val->dump(CurDAG));
1469 DEBUG(ResNode->dump(CurDAG));
1477 bool X86DAGToDAGISel::
1478 SelectInlineAsmMemoryOperand(const SDOperand &Op, char ConstraintCode,
1479 std::vector<SDOperand> &OutOps, SelectionDAG &DAG){
1480 SDOperand Op0, Op1, Op2, Op3;
1481 switch (ConstraintCode) {
1482 case 'o': // offsetable ??
1483 case 'v': // not offsetable ??
1484 default: return true;
1486 if (!SelectAddr(Op, Op, Op0, Op1, Op2, Op3))
1491 OutOps.push_back(Op0);
1492 OutOps.push_back(Op1);
1493 OutOps.push_back(Op2);
1494 OutOps.push_back(Op3);
1495 AddToISelQueue(Op0);
1496 AddToISelQueue(Op1);
1497 AddToISelQueue(Op2);
1498 AddToISelQueue(Op3);
1502 /// createX86ISelDag - This pass converts a legalized DAG into a
1503 /// X86-specific DAG, ready for instruction scheduling.
1505 FunctionPass *llvm::createX86ISelDag(X86TargetMachine &TM, bool Fast) {
1506 return new X86DAGToDAGISel(TM, Fast);