1 //===- X86ISelDAGToDAG.cpp - A DAG pattern matching inst selector for X86 -===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a DAG pattern matching instruction selector for X86,
11 // converting from a legalized dag to a X86 dag.
13 //===----------------------------------------------------------------------===//
16 #include "X86InstrBuilder.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86RegisterInfo.h"
19 #include "X86Subtarget.h"
20 #include "X86TargetMachine.h"
21 #include "llvm/ADT/Statistic.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/SelectionDAGISel.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/IR/Instructions.h"
29 #include "llvm/IR/Intrinsics.h"
30 #include "llvm/IR/Type.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/MathExtras.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/Target/TargetMachine.h"
36 #include "llvm/Target/TargetOptions.h"
40 #define DEBUG_TYPE "x86-isel"
42 STATISTIC(NumLoadMoved, "Number of loads moved below TokenFactor");
44 //===----------------------------------------------------------------------===//
45 // Pattern Matcher Implementation
46 //===----------------------------------------------------------------------===//
49 /// X86ISelAddressMode - This corresponds to X86AddressMode, but uses
50 /// SDValue's instead of register numbers for the leaves of the matched
52 struct X86ISelAddressMode {
58 // This is really a union, discriminated by BaseType!
66 const GlobalValue *GV;
68 const BlockAddress *BlockAddr;
71 unsigned Align; // CP alignment.
72 unsigned char SymbolFlags; // X86II::MO_*
75 : BaseType(RegBase), Base_FrameIndex(0), Scale(1), IndexReg(), Disp(0),
76 Segment(), GV(nullptr), CP(nullptr), BlockAddr(nullptr), ES(nullptr),
77 JT(-1), Align(0), SymbolFlags(X86II::MO_NO_FLAG) {
80 bool hasSymbolicDisplacement() const {
81 return GV != nullptr || CP != nullptr || ES != nullptr ||
82 JT != -1 || BlockAddr != nullptr;
85 bool hasBaseOrIndexReg() const {
86 return BaseType == FrameIndexBase ||
87 IndexReg.getNode() != nullptr || Base_Reg.getNode() != nullptr;
90 /// isRIPRelative - Return true if this addressing mode is already RIP
92 bool isRIPRelative() const {
93 if (BaseType != RegBase) return false;
94 if (RegisterSDNode *RegNode =
95 dyn_cast_or_null<RegisterSDNode>(Base_Reg.getNode()))
96 return RegNode->getReg() == X86::RIP;
100 void setBaseReg(SDValue Reg) {
105 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
107 dbgs() << "X86ISelAddressMode " << this << '\n';
108 dbgs() << "Base_Reg ";
109 if (Base_Reg.getNode())
110 Base_Reg.getNode()->dump();
113 dbgs() << " Base.FrameIndex " << Base_FrameIndex << '\n'
114 << " Scale" << Scale << '\n'
116 if (IndexReg.getNode())
117 IndexReg.getNode()->dump();
120 dbgs() << " Disp " << Disp << '\n'
137 dbgs() << " JT" << JT << " Align" << Align << '\n';
144 //===--------------------------------------------------------------------===//
145 /// ISel - X86 specific code to select X86 machine instructions for
146 /// SelectionDAG operations.
148 class X86DAGToDAGISel final : public SelectionDAGISel {
149 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
150 /// make the right decision when generating code for different targets.
151 const X86Subtarget *Subtarget;
153 /// OptForSize - If true, selector should try to optimize for code size
154 /// instead of performance.
158 explicit X86DAGToDAGISel(X86TargetMachine &tm, CodeGenOpt::Level OptLevel)
159 : SelectionDAGISel(tm, OptLevel), OptForSize(false) {}
161 const char *getPassName() const override {
162 return "X86 DAG->DAG Instruction Selection";
165 bool runOnMachineFunction(MachineFunction &MF) override {
166 // Reset the subtarget each time through.
167 Subtarget = &MF.getSubtarget<X86Subtarget>();
168 SelectionDAGISel::runOnMachineFunction(MF);
172 void EmitFunctionEntryCode() override;
174 bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const override;
176 void PreprocessISelDAG() override;
178 inline bool immSext8(SDNode *N) const {
179 return isInt<8>(cast<ConstantSDNode>(N)->getSExtValue());
182 // i64immSExt32 predicate - True if the 64-bit immediate fits in a 32-bit
183 // sign extended field.
184 inline bool i64immSExt32(SDNode *N) const {
185 uint64_t v = cast<ConstantSDNode>(N)->getZExtValue();
186 return (int64_t)v == (int32_t)v;
189 // Include the pieces autogenerated from the target description.
190 #include "X86GenDAGISel.inc"
193 SDNode *Select(SDNode *N) override;
194 SDNode *SelectGather(SDNode *N, unsigned Opc);
195 SDNode *SelectAtomicLoadArith(SDNode *Node, MVT NVT);
197 bool FoldOffsetIntoAddress(uint64_t Offset, X86ISelAddressMode &AM);
198 bool MatchLoadInAddress(LoadSDNode *N, X86ISelAddressMode &AM);
199 bool MatchWrapper(SDValue N, X86ISelAddressMode &AM);
200 bool MatchAddress(SDValue N, X86ISelAddressMode &AM);
201 bool MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM,
203 bool MatchAddressBase(SDValue N, X86ISelAddressMode &AM);
204 bool SelectAddr(SDNode *Parent, SDValue N, SDValue &Base,
205 SDValue &Scale, SDValue &Index, SDValue &Disp,
207 bool SelectMOV64Imm32(SDValue N, SDValue &Imm);
208 bool SelectLEAAddr(SDValue N, SDValue &Base,
209 SDValue &Scale, SDValue &Index, SDValue &Disp,
211 bool SelectLEA64_32Addr(SDValue N, SDValue &Base,
212 SDValue &Scale, SDValue &Index, SDValue &Disp,
214 bool SelectTLSADDRAddr(SDValue N, SDValue &Base,
215 SDValue &Scale, SDValue &Index, SDValue &Disp,
217 bool SelectScalarSSELoad(SDNode *Root, SDValue N,
218 SDValue &Base, SDValue &Scale,
219 SDValue &Index, SDValue &Disp,
221 SDValue &NodeWithChain);
223 bool TryFoldLoad(SDNode *P, SDValue N,
224 SDValue &Base, SDValue &Scale,
225 SDValue &Index, SDValue &Disp,
228 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
229 /// inline asm expressions.
230 bool SelectInlineAsmMemoryOperand(const SDValue &Op,
232 std::vector<SDValue> &OutOps) override;
234 void EmitSpecialCodeForMain(MachineBasicBlock *BB, MachineFrameInfo *MFI);
236 inline void getAddressOperands(X86ISelAddressMode &AM, SDValue &Base,
237 SDValue &Scale, SDValue &Index,
238 SDValue &Disp, SDValue &Segment) {
239 Base = (AM.BaseType == X86ISelAddressMode::FrameIndexBase)
240 ? CurDAG->getTargetFrameIndex(AM.Base_FrameIndex,
243 Scale = getI8Imm(AM.Scale);
245 // These are 32-bit even in 64-bit mode since RIP relative offset
248 Disp = CurDAG->getTargetGlobalAddress(AM.GV, SDLoc(),
252 Disp = CurDAG->getTargetConstantPool(AM.CP, MVT::i32,
253 AM.Align, AM.Disp, AM.SymbolFlags);
255 assert(!AM.Disp && "Non-zero displacement is ignored with ES.");
256 Disp = CurDAG->getTargetExternalSymbol(AM.ES, MVT::i32, AM.SymbolFlags);
257 } else if (AM.JT != -1) {
258 assert(!AM.Disp && "Non-zero displacement is ignored with JT.");
259 Disp = CurDAG->getTargetJumpTable(AM.JT, MVT::i32, AM.SymbolFlags);
260 } else if (AM.BlockAddr)
261 Disp = CurDAG->getTargetBlockAddress(AM.BlockAddr, MVT::i32, AM.Disp,
264 Disp = CurDAG->getTargetConstant(AM.Disp, MVT::i32);
266 if (AM.Segment.getNode())
267 Segment = AM.Segment;
269 Segment = CurDAG->getRegister(0, MVT::i32);
272 /// getI8Imm - Return a target constant with the specified value, of type
274 inline SDValue getI8Imm(unsigned Imm) {
275 return CurDAG->getTargetConstant(Imm, MVT::i8);
278 /// getI32Imm - Return a target constant with the specified value, of type
280 inline SDValue getI32Imm(unsigned Imm) {
281 return CurDAG->getTargetConstant(Imm, MVT::i32);
284 /// getGlobalBaseReg - Return an SDNode that returns the value of
285 /// the global base register. Output instructions required to
286 /// initialize the global base register, if necessary.
288 SDNode *getGlobalBaseReg();
290 /// getTargetMachine - Return a reference to the TargetMachine, casted
291 /// to the target-specific type.
292 const X86TargetMachine &getTargetMachine() const {
293 return static_cast<const X86TargetMachine &>(TM);
296 /// getInstrInfo - Return a reference to the TargetInstrInfo, casted
297 /// to the target-specific type.
298 const X86InstrInfo *getInstrInfo() const {
299 return Subtarget->getInstrInfo();
302 /// \brief Address-mode matching performs shift-of-and to and-of-shift
303 /// reassociation in order to expose more scaled addressing
305 bool ComplexPatternFuncMutatesDAG() const override {
313 X86DAGToDAGISel::IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const {
314 if (OptLevel == CodeGenOpt::None) return false;
319 if (N.getOpcode() != ISD::LOAD)
322 // If N is a load, do additional profitability checks.
324 switch (U->getOpcode()) {
337 SDValue Op1 = U->getOperand(1);
339 // If the other operand is a 8-bit immediate we should fold the immediate
340 // instead. This reduces code size.
342 // movl 4(%esp), %eax
346 // addl 4(%esp), %eax
347 // The former is 2 bytes shorter. In case where the increment is 1, then
348 // the saving can be 4 bytes (by using incl %eax).
349 if (ConstantSDNode *Imm = dyn_cast<ConstantSDNode>(Op1))
350 if (Imm->getAPIntValue().isSignedIntN(8))
353 // If the other operand is a TLS address, we should fold it instead.
356 // leal i@NTPOFF(%eax), %eax
358 // movl $i@NTPOFF, %eax
360 // if the block also has an access to a second TLS address this will save
362 // FIXME: This is probably also true for non-TLS addresses.
363 if (Op1.getOpcode() == X86ISD::Wrapper) {
364 SDValue Val = Op1.getOperand(0);
365 if (Val.getOpcode() == ISD::TargetGlobalTLSAddress)
375 /// MoveBelowCallOrigChain - Replace the original chain operand of the call with
376 /// load's chain operand and move load below the call's chain operand.
377 static void MoveBelowOrigChain(SelectionDAG *CurDAG, SDValue Load,
378 SDValue Call, SDValue OrigChain) {
379 SmallVector<SDValue, 8> Ops;
380 SDValue Chain = OrigChain.getOperand(0);
381 if (Chain.getNode() == Load.getNode())
382 Ops.push_back(Load.getOperand(0));
384 assert(Chain.getOpcode() == ISD::TokenFactor &&
385 "Unexpected chain operand");
386 for (unsigned i = 0, e = Chain.getNumOperands(); i != e; ++i)
387 if (Chain.getOperand(i).getNode() == Load.getNode())
388 Ops.push_back(Load.getOperand(0));
390 Ops.push_back(Chain.getOperand(i));
392 CurDAG->getNode(ISD::TokenFactor, SDLoc(Load), MVT::Other, Ops);
394 Ops.push_back(NewChain);
396 for (unsigned i = 1, e = OrigChain.getNumOperands(); i != e; ++i)
397 Ops.push_back(OrigChain.getOperand(i));
398 CurDAG->UpdateNodeOperands(OrigChain.getNode(), Ops);
399 CurDAG->UpdateNodeOperands(Load.getNode(), Call.getOperand(0),
400 Load.getOperand(1), Load.getOperand(2));
402 unsigned NumOps = Call.getNode()->getNumOperands();
404 Ops.push_back(SDValue(Load.getNode(), 1));
405 for (unsigned i = 1, e = NumOps; i != e; ++i)
406 Ops.push_back(Call.getOperand(i));
407 CurDAG->UpdateNodeOperands(Call.getNode(), Ops);
410 /// isCalleeLoad - Return true if call address is a load and it can be
411 /// moved below CALLSEQ_START and the chains leading up to the call.
412 /// Return the CALLSEQ_START by reference as a second output.
413 /// In the case of a tail call, there isn't a callseq node between the call
414 /// chain and the load.
415 static bool isCalleeLoad(SDValue Callee, SDValue &Chain, bool HasCallSeq) {
416 // The transformation is somewhat dangerous if the call's chain was glued to
417 // the call. After MoveBelowOrigChain the load is moved between the call and
418 // the chain, this can create a cycle if the load is not folded. So it is
419 // *really* important that we are sure the load will be folded.
420 if (Callee.getNode() == Chain.getNode() || !Callee.hasOneUse())
422 LoadSDNode *LD = dyn_cast<LoadSDNode>(Callee.getNode());
425 LD->getAddressingMode() != ISD::UNINDEXED ||
426 LD->getExtensionType() != ISD::NON_EXTLOAD)
429 // Now let's find the callseq_start.
430 while (HasCallSeq && Chain.getOpcode() != ISD::CALLSEQ_START) {
431 if (!Chain.hasOneUse())
433 Chain = Chain.getOperand(0);
436 if (!Chain.getNumOperands())
438 // Since we are not checking for AA here, conservatively abort if the chain
439 // writes to memory. It's not safe to move the callee (a load) across a store.
440 if (isa<MemSDNode>(Chain.getNode()) &&
441 cast<MemSDNode>(Chain.getNode())->writeMem())
443 if (Chain.getOperand(0).getNode() == Callee.getNode())
445 if (Chain.getOperand(0).getOpcode() == ISD::TokenFactor &&
446 Callee.getValue(1).isOperandOf(Chain.getOperand(0).getNode()) &&
447 Callee.getValue(1).hasOneUse())
452 void X86DAGToDAGISel::PreprocessISelDAG() {
453 // OptForSize is used in pattern predicates that isel is matching.
454 OptForSize = MF->getFunction()->hasFnAttribute(Attribute::OptimizeForSize);
456 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
457 E = CurDAG->allnodes_end(); I != E; ) {
458 SDNode *N = I++; // Preincrement iterator to avoid invalidation issues.
460 if (OptLevel != CodeGenOpt::None &&
461 // Only does this when target favors doesn't favor register indirect
463 ((N->getOpcode() == X86ISD::CALL && !Subtarget->callRegIndirect()) ||
464 (N->getOpcode() == X86ISD::TC_RETURN &&
465 // Only does this if load can be folded into TC_RETURN.
466 (Subtarget->is64Bit() ||
467 getTargetMachine().getRelocationModel() != Reloc::PIC_)))) {
468 /// Also try moving call address load from outside callseq_start to just
469 /// before the call to allow it to be folded.
487 bool HasCallSeq = N->getOpcode() == X86ISD::CALL;
488 SDValue Chain = N->getOperand(0);
489 SDValue Load = N->getOperand(1);
490 if (!isCalleeLoad(Load, Chain, HasCallSeq))
492 MoveBelowOrigChain(CurDAG, Load, SDValue(N, 0), Chain);
497 // Lower fpround and fpextend nodes that target the FP stack to be store and
498 // load to the stack. This is a gross hack. We would like to simply mark
499 // these as being illegal, but when we do that, legalize produces these when
500 // it expands calls, then expands these in the same legalize pass. We would
501 // like dag combine to be able to hack on these between the call expansion
502 // and the node legalization. As such this pass basically does "really
503 // late" legalization of these inline with the X86 isel pass.
504 // FIXME: This should only happen when not compiled with -O0.
505 if (N->getOpcode() != ISD::FP_ROUND && N->getOpcode() != ISD::FP_EXTEND)
508 MVT SrcVT = N->getOperand(0).getSimpleValueType();
509 MVT DstVT = N->getSimpleValueType(0);
511 // If any of the sources are vectors, no fp stack involved.
512 if (SrcVT.isVector() || DstVT.isVector())
515 // If the source and destination are SSE registers, then this is a legal
516 // conversion that should not be lowered.
517 const X86TargetLowering *X86Lowering =
518 static_cast<const X86TargetLowering *>(TLI);
519 bool SrcIsSSE = X86Lowering->isScalarFPTypeInSSEReg(SrcVT);
520 bool DstIsSSE = X86Lowering->isScalarFPTypeInSSEReg(DstVT);
521 if (SrcIsSSE && DstIsSSE)
524 if (!SrcIsSSE && !DstIsSSE) {
525 // If this is an FPStack extension, it is a noop.
526 if (N->getOpcode() == ISD::FP_EXTEND)
528 // If this is a value-preserving FPStack truncation, it is a noop.
529 if (N->getConstantOperandVal(1))
533 // Here we could have an FP stack truncation or an FPStack <-> SSE convert.
534 // FPStack has extload and truncstore. SSE can fold direct loads into other
535 // operations. Based on this, decide what we want to do.
537 if (N->getOpcode() == ISD::FP_ROUND)
538 MemVT = DstVT; // FP_ROUND must use DstVT, we can't do a 'trunc load'.
540 MemVT = SrcIsSSE ? SrcVT : DstVT;
542 SDValue MemTmp = CurDAG->CreateStackTemporary(MemVT);
545 // FIXME: optimize the case where the src/dest is a load or store?
546 SDValue Store = CurDAG->getTruncStore(CurDAG->getEntryNode(), dl,
548 MemTmp, MachinePointerInfo(), MemVT,
550 SDValue Result = CurDAG->getExtLoad(ISD::EXTLOAD, dl, DstVT, Store, MemTmp,
551 MachinePointerInfo(),
552 MemVT, false, false, false, 0);
554 // We're about to replace all uses of the FP_ROUND/FP_EXTEND with the
555 // extload we created. This will cause general havok on the dag because
556 // anything below the conversion could be folded into other existing nodes.
557 // To avoid invalidating 'I', back it up to the convert node.
559 CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 0), Result);
561 // Now that we did that, the node is dead. Increment the iterator to the
562 // next node to process, then delete N.
564 CurDAG->DeleteNode(N);
569 /// EmitSpecialCodeForMain - Emit any code that needs to be executed only in
570 /// the main function.
571 void X86DAGToDAGISel::EmitSpecialCodeForMain(MachineBasicBlock *BB,
572 MachineFrameInfo *MFI) {
573 const TargetInstrInfo *TII = getInstrInfo();
574 if (Subtarget->isTargetCygMing()) {
576 Subtarget->is64Bit() ? X86::CALL64pcrel32 : X86::CALLpcrel32;
577 BuildMI(BB, DebugLoc(),
578 TII->get(CallOp)).addExternalSymbol("__main");
582 void X86DAGToDAGISel::EmitFunctionEntryCode() {
583 // If this is main, emit special code for main.
584 if (const Function *Fn = MF->getFunction())
585 if (Fn->hasExternalLinkage() && Fn->getName() == "main")
586 EmitSpecialCodeForMain(MF->begin(), MF->getFrameInfo());
589 static bool isDispSafeForFrameIndex(int64_t Val) {
590 // On 64-bit platforms, we can run into an issue where a frame index
591 // includes a displacement that, when added to the explicit displacement,
592 // will overflow the displacement field. Assuming that the frame index
593 // displacement fits into a 31-bit integer (which is only slightly more
594 // aggressive than the current fundamental assumption that it fits into
595 // a 32-bit integer), a 31-bit disp should always be safe.
596 return isInt<31>(Val);
599 bool X86DAGToDAGISel::FoldOffsetIntoAddress(uint64_t Offset,
600 X86ISelAddressMode &AM) {
601 int64_t Val = AM.Disp + Offset;
602 CodeModel::Model M = TM.getCodeModel();
603 if (Subtarget->is64Bit()) {
604 if (!X86::isOffsetSuitableForCodeModel(Val, M,
605 AM.hasSymbolicDisplacement()))
607 // In addition to the checks required for a register base, check that
608 // we do not try to use an unsafe Disp with a frame index.
609 if (AM.BaseType == X86ISelAddressMode::FrameIndexBase &&
610 !isDispSafeForFrameIndex(Val))
618 bool X86DAGToDAGISel::MatchLoadInAddress(LoadSDNode *N, X86ISelAddressMode &AM){
619 SDValue Address = N->getOperand(1);
621 // load gs:0 -> GS segment register.
622 // load fs:0 -> FS segment register.
624 // This optimization is valid because the GNU TLS model defines that
625 // gs:0 (or fs:0 on X86-64) contains its own address.
626 // For more information see http://people.redhat.com/drepper/tls.pdf
627 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Address))
628 if (C->getSExtValue() == 0 && AM.Segment.getNode() == nullptr &&
629 Subtarget->isTargetLinux())
630 switch (N->getPointerInfo().getAddrSpace()) {
632 AM.Segment = CurDAG->getRegister(X86::GS, MVT::i16);
635 AM.Segment = CurDAG->getRegister(X86::FS, MVT::i16);
642 /// MatchWrapper - Try to match X86ISD::Wrapper and X86ISD::WrapperRIP nodes
643 /// into an addressing mode. These wrap things that will resolve down into a
644 /// symbol reference. If no match is possible, this returns true, otherwise it
646 bool X86DAGToDAGISel::MatchWrapper(SDValue N, X86ISelAddressMode &AM) {
647 // If the addressing mode already has a symbol as the displacement, we can
648 // never match another symbol.
649 if (AM.hasSymbolicDisplacement())
652 SDValue N0 = N.getOperand(0);
653 CodeModel::Model M = TM.getCodeModel();
655 // Handle X86-64 rip-relative addresses. We check this before checking direct
656 // folding because RIP is preferable to non-RIP accesses.
657 if (Subtarget->is64Bit() && N.getOpcode() == X86ISD::WrapperRIP &&
658 // Under X86-64 non-small code model, GV (and friends) are 64-bits, so
659 // they cannot be folded into immediate fields.
660 // FIXME: This can be improved for kernel and other models?
661 (M == CodeModel::Small || M == CodeModel::Kernel)) {
662 // Base and index reg must be 0 in order to use %rip as base.
663 if (AM.hasBaseOrIndexReg())
665 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
666 X86ISelAddressMode Backup = AM;
667 AM.GV = G->getGlobal();
668 AM.SymbolFlags = G->getTargetFlags();
669 if (FoldOffsetIntoAddress(G->getOffset(), AM)) {
673 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) {
674 X86ISelAddressMode Backup = AM;
675 AM.CP = CP->getConstVal();
676 AM.Align = CP->getAlignment();
677 AM.SymbolFlags = CP->getTargetFlags();
678 if (FoldOffsetIntoAddress(CP->getOffset(), AM)) {
682 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(N0)) {
683 AM.ES = S->getSymbol();
684 AM.SymbolFlags = S->getTargetFlags();
685 } else if (JumpTableSDNode *J = dyn_cast<JumpTableSDNode>(N0)) {
686 AM.JT = J->getIndex();
687 AM.SymbolFlags = J->getTargetFlags();
688 } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(N0)) {
689 X86ISelAddressMode Backup = AM;
690 AM.BlockAddr = BA->getBlockAddress();
691 AM.SymbolFlags = BA->getTargetFlags();
692 if (FoldOffsetIntoAddress(BA->getOffset(), AM)) {
697 llvm_unreachable("Unhandled symbol reference node.");
699 if (N.getOpcode() == X86ISD::WrapperRIP)
700 AM.setBaseReg(CurDAG->getRegister(X86::RIP, MVT::i64));
704 // Handle the case when globals fit in our immediate field: This is true for
705 // X86-32 always and X86-64 when in -mcmodel=small mode. In 64-bit
706 // mode, this only applies to a non-RIP-relative computation.
707 if (!Subtarget->is64Bit() ||
708 M == CodeModel::Small || M == CodeModel::Kernel) {
709 assert(N.getOpcode() != X86ISD::WrapperRIP &&
710 "RIP-relative addressing already handled");
711 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
712 AM.GV = G->getGlobal();
713 AM.Disp += G->getOffset();
714 AM.SymbolFlags = G->getTargetFlags();
715 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) {
716 AM.CP = CP->getConstVal();
717 AM.Align = CP->getAlignment();
718 AM.Disp += CP->getOffset();
719 AM.SymbolFlags = CP->getTargetFlags();
720 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(N0)) {
721 AM.ES = S->getSymbol();
722 AM.SymbolFlags = S->getTargetFlags();
723 } else if (JumpTableSDNode *J = dyn_cast<JumpTableSDNode>(N0)) {
724 AM.JT = J->getIndex();
725 AM.SymbolFlags = J->getTargetFlags();
726 } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(N0)) {
727 AM.BlockAddr = BA->getBlockAddress();
728 AM.Disp += BA->getOffset();
729 AM.SymbolFlags = BA->getTargetFlags();
731 llvm_unreachable("Unhandled symbol reference node.");
738 /// MatchAddress - Add the specified node to the specified addressing mode,
739 /// returning true if it cannot be done. This just pattern matches for the
741 bool X86DAGToDAGISel::MatchAddress(SDValue N, X86ISelAddressMode &AM) {
742 if (MatchAddressRecursively(N, AM, 0))
745 // Post-processing: Convert lea(,%reg,2) to lea(%reg,%reg), which has
746 // a smaller encoding and avoids a scaled-index.
748 AM.BaseType == X86ISelAddressMode::RegBase &&
749 AM.Base_Reg.getNode() == nullptr) {
750 AM.Base_Reg = AM.IndexReg;
754 // Post-processing: Convert foo to foo(%rip), even in non-PIC mode,
755 // because it has a smaller encoding.
756 // TODO: Which other code models can use this?
757 if (TM.getCodeModel() == CodeModel::Small &&
758 Subtarget->is64Bit() &&
760 AM.BaseType == X86ISelAddressMode::RegBase &&
761 AM.Base_Reg.getNode() == nullptr &&
762 AM.IndexReg.getNode() == nullptr &&
763 AM.SymbolFlags == X86II::MO_NO_FLAG &&
764 AM.hasSymbolicDisplacement())
765 AM.Base_Reg = CurDAG->getRegister(X86::RIP, MVT::i64);
770 // Insert a node into the DAG at least before the Pos node's position. This
771 // will reposition the node as needed, and will assign it a node ID that is <=
772 // the Pos node's ID. Note that this does *not* preserve the uniqueness of node
773 // IDs! The selection DAG must no longer depend on their uniqueness when this
775 static void InsertDAGNode(SelectionDAG &DAG, SDValue Pos, SDValue N) {
776 if (N.getNode()->getNodeId() == -1 ||
777 N.getNode()->getNodeId() > Pos.getNode()->getNodeId()) {
778 DAG.RepositionNode(Pos.getNode(), N.getNode());
779 N.getNode()->setNodeId(Pos.getNode()->getNodeId());
783 // Transform "(X >> (8-C1)) & (0xff << C1)" to "((X >> 8) & 0xff) << C1" if
784 // safe. This allows us to convert the shift and and into an h-register
785 // extract and a scaled index. Returns false if the simplification is
787 static bool FoldMaskAndShiftToExtract(SelectionDAG &DAG, SDValue N,
789 SDValue Shift, SDValue X,
790 X86ISelAddressMode &AM) {
791 if (Shift.getOpcode() != ISD::SRL ||
792 !isa<ConstantSDNode>(Shift.getOperand(1)) ||
796 int ScaleLog = 8 - Shift.getConstantOperandVal(1);
797 if (ScaleLog <= 0 || ScaleLog >= 4 ||
798 Mask != (0xffu << ScaleLog))
801 MVT VT = N.getSimpleValueType();
803 SDValue Eight = DAG.getConstant(8, MVT::i8);
804 SDValue NewMask = DAG.getConstant(0xff, VT);
805 SDValue Srl = DAG.getNode(ISD::SRL, DL, VT, X, Eight);
806 SDValue And = DAG.getNode(ISD::AND, DL, VT, Srl, NewMask);
807 SDValue ShlCount = DAG.getConstant(ScaleLog, MVT::i8);
808 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, And, ShlCount);
810 // Insert the new nodes into the topological ordering. We must do this in
811 // a valid topological ordering as nothing is going to go back and re-sort
812 // these nodes. We continually insert before 'N' in sequence as this is
813 // essentially a pre-flattened and pre-sorted sequence of nodes. There is no
814 // hierarchy left to express.
815 InsertDAGNode(DAG, N, Eight);
816 InsertDAGNode(DAG, N, Srl);
817 InsertDAGNode(DAG, N, NewMask);
818 InsertDAGNode(DAG, N, And);
819 InsertDAGNode(DAG, N, ShlCount);
820 InsertDAGNode(DAG, N, Shl);
821 DAG.ReplaceAllUsesWith(N, Shl);
823 AM.Scale = (1 << ScaleLog);
827 // Transforms "(X << C1) & C2" to "(X & (C2>>C1)) << C1" if safe and if this
828 // allows us to fold the shift into this addressing mode. Returns false if the
829 // transform succeeded.
830 static bool FoldMaskedShiftToScaledMask(SelectionDAG &DAG, SDValue N,
832 SDValue Shift, SDValue X,
833 X86ISelAddressMode &AM) {
834 if (Shift.getOpcode() != ISD::SHL ||
835 !isa<ConstantSDNode>(Shift.getOperand(1)))
838 // Not likely to be profitable if either the AND or SHIFT node has more
839 // than one use (unless all uses are for address computation). Besides,
840 // isel mechanism requires their node ids to be reused.
841 if (!N.hasOneUse() || !Shift.hasOneUse())
844 // Verify that the shift amount is something we can fold.
845 unsigned ShiftAmt = Shift.getConstantOperandVal(1);
846 if (ShiftAmt != 1 && ShiftAmt != 2 && ShiftAmt != 3)
849 MVT VT = N.getSimpleValueType();
851 SDValue NewMask = DAG.getConstant(Mask >> ShiftAmt, VT);
852 SDValue NewAnd = DAG.getNode(ISD::AND, DL, VT, X, NewMask);
853 SDValue NewShift = DAG.getNode(ISD::SHL, DL, VT, NewAnd, Shift.getOperand(1));
855 // Insert the new nodes into the topological ordering. We must do this in
856 // a valid topological ordering as nothing is going to go back and re-sort
857 // these nodes. We continually insert before 'N' in sequence as this is
858 // essentially a pre-flattened and pre-sorted sequence of nodes. There is no
859 // hierarchy left to express.
860 InsertDAGNode(DAG, N, NewMask);
861 InsertDAGNode(DAG, N, NewAnd);
862 InsertDAGNode(DAG, N, NewShift);
863 DAG.ReplaceAllUsesWith(N, NewShift);
865 AM.Scale = 1 << ShiftAmt;
866 AM.IndexReg = NewAnd;
870 // Implement some heroics to detect shifts of masked values where the mask can
871 // be replaced by extending the shift and undoing that in the addressing mode
872 // scale. Patterns such as (shl (srl x, c1), c2) are canonicalized into (and
873 // (srl x, SHIFT), MASK) by DAGCombines that don't know the shl can be done in
874 // the addressing mode. This results in code such as:
876 // int f(short *y, int *lookup_table) {
878 // return *y + lookup_table[*y >> 11];
882 // movzwl (%rdi), %eax
885 // addl (%rsi,%rcx,4), %eax
888 // movzwl (%rdi), %eax
892 // addl (%rsi,%rcx), %eax
894 // Note that this function assumes the mask is provided as a mask *after* the
895 // value is shifted. The input chain may or may not match that, but computing
896 // such a mask is trivial.
897 static bool FoldMaskAndShiftToScale(SelectionDAG &DAG, SDValue N,
899 SDValue Shift, SDValue X,
900 X86ISelAddressMode &AM) {
901 if (Shift.getOpcode() != ISD::SRL || !Shift.hasOneUse() ||
902 !isa<ConstantSDNode>(Shift.getOperand(1)))
905 unsigned ShiftAmt = Shift.getConstantOperandVal(1);
906 unsigned MaskLZ = countLeadingZeros(Mask);
907 unsigned MaskTZ = countTrailingZeros(Mask);
909 // The amount of shift we're trying to fit into the addressing mode is taken
910 // from the trailing zeros of the mask.
911 unsigned AMShiftAmt = MaskTZ;
913 // There is nothing we can do here unless the mask is removing some bits.
914 // Also, the addressing mode can only represent shifts of 1, 2, or 3 bits.
915 if (AMShiftAmt <= 0 || AMShiftAmt > 3) return true;
917 // We also need to ensure that mask is a continuous run of bits.
918 if (countTrailingOnes(Mask >> MaskTZ) + MaskTZ + MaskLZ != 64) return true;
920 // Scale the leading zero count down based on the actual size of the value.
921 // Also scale it down based on the size of the shift.
922 MaskLZ -= (64 - X.getSimpleValueType().getSizeInBits()) + ShiftAmt;
924 // The final check is to ensure that any masked out high bits of X are
925 // already known to be zero. Otherwise, the mask has a semantic impact
926 // other than masking out a couple of low bits. Unfortunately, because of
927 // the mask, zero extensions will be removed from operands in some cases.
928 // This code works extra hard to look through extensions because we can
929 // replace them with zero extensions cheaply if necessary.
930 bool ReplacingAnyExtend = false;
931 if (X.getOpcode() == ISD::ANY_EXTEND) {
932 unsigned ExtendBits = X.getSimpleValueType().getSizeInBits() -
933 X.getOperand(0).getSimpleValueType().getSizeInBits();
934 // Assume that we'll replace the any-extend with a zero-extend, and
935 // narrow the search to the extended value.
937 MaskLZ = ExtendBits > MaskLZ ? 0 : MaskLZ - ExtendBits;
938 ReplacingAnyExtend = true;
940 APInt MaskedHighBits =
941 APInt::getHighBitsSet(X.getSimpleValueType().getSizeInBits(), MaskLZ);
942 APInt KnownZero, KnownOne;
943 DAG.computeKnownBits(X, KnownZero, KnownOne);
944 if (MaskedHighBits != KnownZero) return true;
946 // We've identified a pattern that can be transformed into a single shift
947 // and an addressing mode. Make it so.
948 MVT VT = N.getSimpleValueType();
949 if (ReplacingAnyExtend) {
950 assert(X.getValueType() != VT);
951 // We looked through an ANY_EXTEND node, insert a ZERO_EXTEND.
952 SDValue NewX = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(X), VT, X);
953 InsertDAGNode(DAG, N, NewX);
957 SDValue NewSRLAmt = DAG.getConstant(ShiftAmt + AMShiftAmt, MVT::i8);
958 SDValue NewSRL = DAG.getNode(ISD::SRL, DL, VT, X, NewSRLAmt);
959 SDValue NewSHLAmt = DAG.getConstant(AMShiftAmt, MVT::i8);
960 SDValue NewSHL = DAG.getNode(ISD::SHL, DL, VT, NewSRL, NewSHLAmt);
962 // Insert the new nodes into the topological ordering. We must do this in
963 // a valid topological ordering as nothing is going to go back and re-sort
964 // these nodes. We continually insert before 'N' in sequence as this is
965 // essentially a pre-flattened and pre-sorted sequence of nodes. There is no
966 // hierarchy left to express.
967 InsertDAGNode(DAG, N, NewSRLAmt);
968 InsertDAGNode(DAG, N, NewSRL);
969 InsertDAGNode(DAG, N, NewSHLAmt);
970 InsertDAGNode(DAG, N, NewSHL);
971 DAG.ReplaceAllUsesWith(N, NewSHL);
973 AM.Scale = 1 << AMShiftAmt;
974 AM.IndexReg = NewSRL;
978 bool X86DAGToDAGISel::MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM,
982 dbgs() << "MatchAddress: ";
987 return MatchAddressBase(N, AM);
989 // If this is already a %rip relative address, we can only merge immediates
990 // into it. Instead of handling this in every case, we handle it here.
991 // RIP relative addressing: %rip + 32-bit displacement!
992 if (AM.isRIPRelative()) {
993 // FIXME: JumpTable and ExternalSymbol address currently don't like
994 // displacements. It isn't very important, but this should be fixed for
996 if (!AM.ES && AM.JT != -1) return true;
998 if (ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(N))
999 if (!FoldOffsetIntoAddress(Cst->getSExtValue(), AM))
1004 switch (N.getOpcode()) {
1006 case ISD::Constant: {
1007 uint64_t Val = cast<ConstantSDNode>(N)->getSExtValue();
1008 if (!FoldOffsetIntoAddress(Val, AM))
1013 case X86ISD::Wrapper:
1014 case X86ISD::WrapperRIP:
1015 if (!MatchWrapper(N, AM))
1020 if (!MatchLoadInAddress(cast<LoadSDNode>(N), AM))
1024 case ISD::FrameIndex:
1025 if (AM.BaseType == X86ISelAddressMode::RegBase &&
1026 AM.Base_Reg.getNode() == nullptr &&
1027 (!Subtarget->is64Bit() || isDispSafeForFrameIndex(AM.Disp))) {
1028 AM.BaseType = X86ISelAddressMode::FrameIndexBase;
1029 AM.Base_FrameIndex = cast<FrameIndexSDNode>(N)->getIndex();
1035 if (AM.IndexReg.getNode() != nullptr || AM.Scale != 1)
1039 *CN = dyn_cast<ConstantSDNode>(N.getNode()->getOperand(1))) {
1040 unsigned Val = CN->getZExtValue();
1041 // Note that we handle x<<1 as (,x,2) rather than (x,x) here so
1042 // that the base operand remains free for further matching. If
1043 // the base doesn't end up getting used, a post-processing step
1044 // in MatchAddress turns (,x,2) into (x,x), which is cheaper.
1045 if (Val == 1 || Val == 2 || Val == 3) {
1046 AM.Scale = 1 << Val;
1047 SDValue ShVal = N.getNode()->getOperand(0);
1049 // Okay, we know that we have a scale by now. However, if the scaled
1050 // value is an add of something and a constant, we can fold the
1051 // constant into the disp field here.
1052 if (CurDAG->isBaseWithConstantOffset(ShVal)) {
1053 AM.IndexReg = ShVal.getNode()->getOperand(0);
1054 ConstantSDNode *AddVal =
1055 cast<ConstantSDNode>(ShVal.getNode()->getOperand(1));
1056 uint64_t Disp = (uint64_t)AddVal->getSExtValue() << Val;
1057 if (!FoldOffsetIntoAddress(Disp, AM))
1061 AM.IndexReg = ShVal;
1068 // Scale must not be used already.
1069 if (AM.IndexReg.getNode() != nullptr || AM.Scale != 1) break;
1071 SDValue And = N.getOperand(0);
1072 if (And.getOpcode() != ISD::AND) break;
1073 SDValue X = And.getOperand(0);
1075 // We only handle up to 64-bit values here as those are what matter for
1076 // addressing mode optimizations.
1077 if (X.getSimpleValueType().getSizeInBits() > 64) break;
1079 // The mask used for the transform is expected to be post-shift, but we
1080 // found the shift first so just apply the shift to the mask before passing
1082 if (!isa<ConstantSDNode>(N.getOperand(1)) ||
1083 !isa<ConstantSDNode>(And.getOperand(1)))
1085 uint64_t Mask = And.getConstantOperandVal(1) >> N.getConstantOperandVal(1);
1087 // Try to fold the mask and shift into the scale, and return false if we
1089 if (!FoldMaskAndShiftToScale(*CurDAG, N, Mask, N, X, AM))
1094 case ISD::SMUL_LOHI:
1095 case ISD::UMUL_LOHI:
1096 // A mul_lohi where we need the low part can be folded as a plain multiply.
1097 if (N.getResNo() != 0) break;
1100 case X86ISD::MUL_IMM:
1101 // X*[3,5,9] -> X+X*[2,4,8]
1102 if (AM.BaseType == X86ISelAddressMode::RegBase &&
1103 AM.Base_Reg.getNode() == nullptr &&
1104 AM.IndexReg.getNode() == nullptr) {
1106 *CN = dyn_cast<ConstantSDNode>(N.getNode()->getOperand(1)))
1107 if (CN->getZExtValue() == 3 || CN->getZExtValue() == 5 ||
1108 CN->getZExtValue() == 9) {
1109 AM.Scale = unsigned(CN->getZExtValue())-1;
1111 SDValue MulVal = N.getNode()->getOperand(0);
1114 // Okay, we know that we have a scale by now. However, if the scaled
1115 // value is an add of something and a constant, we can fold the
1116 // constant into the disp field here.
1117 if (MulVal.getNode()->getOpcode() == ISD::ADD && MulVal.hasOneUse() &&
1118 isa<ConstantSDNode>(MulVal.getNode()->getOperand(1))) {
1119 Reg = MulVal.getNode()->getOperand(0);
1120 ConstantSDNode *AddVal =
1121 cast<ConstantSDNode>(MulVal.getNode()->getOperand(1));
1122 uint64_t Disp = AddVal->getSExtValue() * CN->getZExtValue();
1123 if (FoldOffsetIntoAddress(Disp, AM))
1124 Reg = N.getNode()->getOperand(0);
1126 Reg = N.getNode()->getOperand(0);
1129 AM.IndexReg = AM.Base_Reg = Reg;
1136 // Given A-B, if A can be completely folded into the address and
1137 // the index field with the index field unused, use -B as the index.
1138 // This is a win if a has multiple parts that can be folded into
1139 // the address. Also, this saves a mov if the base register has
1140 // other uses, since it avoids a two-address sub instruction, however
1141 // it costs an additional mov if the index register has other uses.
1143 // Add an artificial use to this node so that we can keep track of
1144 // it if it gets CSE'd with a different node.
1145 HandleSDNode Handle(N);
1147 // Test if the LHS of the sub can be folded.
1148 X86ISelAddressMode Backup = AM;
1149 if (MatchAddressRecursively(N.getNode()->getOperand(0), AM, Depth+1)) {
1153 // Test if the index field is free for use.
1154 if (AM.IndexReg.getNode() || AM.isRIPRelative()) {
1160 SDValue RHS = Handle.getValue().getNode()->getOperand(1);
1161 // If the RHS involves a register with multiple uses, this
1162 // transformation incurs an extra mov, due to the neg instruction
1163 // clobbering its operand.
1164 if (!RHS.getNode()->hasOneUse() ||
1165 RHS.getNode()->getOpcode() == ISD::CopyFromReg ||
1166 RHS.getNode()->getOpcode() == ISD::TRUNCATE ||
1167 RHS.getNode()->getOpcode() == ISD::ANY_EXTEND ||
1168 (RHS.getNode()->getOpcode() == ISD::ZERO_EXTEND &&
1169 RHS.getNode()->getOperand(0).getValueType() == MVT::i32))
1171 // If the base is a register with multiple uses, this
1172 // transformation may save a mov.
1173 if ((AM.BaseType == X86ISelAddressMode::RegBase &&
1174 AM.Base_Reg.getNode() &&
1175 !AM.Base_Reg.getNode()->hasOneUse()) ||
1176 AM.BaseType == X86ISelAddressMode::FrameIndexBase)
1178 // If the folded LHS was interesting, this transformation saves
1179 // address arithmetic.
1180 if ((AM.hasSymbolicDisplacement() && !Backup.hasSymbolicDisplacement()) +
1181 ((AM.Disp != 0) && (Backup.Disp == 0)) +
1182 (AM.Segment.getNode() && !Backup.Segment.getNode()) >= 2)
1184 // If it doesn't look like it may be an overall win, don't do it.
1190 // Ok, the transformation is legal and appears profitable. Go for it.
1191 SDValue Zero = CurDAG->getConstant(0, N.getValueType());
1192 SDValue Neg = CurDAG->getNode(ISD::SUB, dl, N.getValueType(), Zero, RHS);
1196 // Insert the new nodes into the topological ordering.
1197 InsertDAGNode(*CurDAG, N, Zero);
1198 InsertDAGNode(*CurDAG, N, Neg);
1203 // Add an artificial use to this node so that we can keep track of
1204 // it if it gets CSE'd with a different node.
1205 HandleSDNode Handle(N);
1207 X86ISelAddressMode Backup = AM;
1208 if (!MatchAddressRecursively(N.getOperand(0), AM, Depth+1) &&
1209 !MatchAddressRecursively(Handle.getValue().getOperand(1), AM, Depth+1))
1213 // Try again after commuting the operands.
1214 if (!MatchAddressRecursively(Handle.getValue().getOperand(1), AM, Depth+1)&&
1215 !MatchAddressRecursively(Handle.getValue().getOperand(0), AM, Depth+1))
1219 // If we couldn't fold both operands into the address at the same time,
1220 // see if we can just put each operand into a register and fold at least
1222 if (AM.BaseType == X86ISelAddressMode::RegBase &&
1223 !AM.Base_Reg.getNode() &&
1224 !AM.IndexReg.getNode()) {
1225 N = Handle.getValue();
1226 AM.Base_Reg = N.getOperand(0);
1227 AM.IndexReg = N.getOperand(1);
1231 N = Handle.getValue();
1236 // Handle "X | C" as "X + C" iff X is known to have C bits clear.
1237 if (CurDAG->isBaseWithConstantOffset(N)) {
1238 X86ISelAddressMode Backup = AM;
1239 ConstantSDNode *CN = cast<ConstantSDNode>(N.getOperand(1));
1241 // Start with the LHS as an addr mode.
1242 if (!MatchAddressRecursively(N.getOperand(0), AM, Depth+1) &&
1243 !FoldOffsetIntoAddress(CN->getSExtValue(), AM))
1250 // Perform some heroic transforms on an and of a constant-count shift
1251 // with a constant to enable use of the scaled offset field.
1253 // Scale must not be used already.
1254 if (AM.IndexReg.getNode() != nullptr || AM.Scale != 1) break;
1256 SDValue Shift = N.getOperand(0);
1257 if (Shift.getOpcode() != ISD::SRL && Shift.getOpcode() != ISD::SHL) break;
1258 SDValue X = Shift.getOperand(0);
1260 // We only handle up to 64-bit values here as those are what matter for
1261 // addressing mode optimizations.
1262 if (X.getSimpleValueType().getSizeInBits() > 64) break;
1264 if (!isa<ConstantSDNode>(N.getOperand(1)))
1266 uint64_t Mask = N.getConstantOperandVal(1);
1268 // Try to fold the mask and shift into an extract and scale.
1269 if (!FoldMaskAndShiftToExtract(*CurDAG, N, Mask, Shift, X, AM))
1272 // Try to fold the mask and shift directly into the scale.
1273 if (!FoldMaskAndShiftToScale(*CurDAG, N, Mask, Shift, X, AM))
1276 // Try to swap the mask and shift to place shifts which can be done as
1277 // a scale on the outside of the mask.
1278 if (!FoldMaskedShiftToScaledMask(*CurDAG, N, Mask, Shift, X, AM))
1284 return MatchAddressBase(N, AM);
1287 /// MatchAddressBase - Helper for MatchAddress. Add the specified node to the
1288 /// specified addressing mode without any further recursion.
1289 bool X86DAGToDAGISel::MatchAddressBase(SDValue N, X86ISelAddressMode &AM) {
1290 // Is the base register already occupied?
1291 if (AM.BaseType != X86ISelAddressMode::RegBase || AM.Base_Reg.getNode()) {
1292 // If so, check to see if the scale index register is set.
1293 if (!AM.IndexReg.getNode()) {
1299 // Otherwise, we cannot select it.
1303 // Default, generate it as a register.
1304 AM.BaseType = X86ISelAddressMode::RegBase;
1309 /// SelectAddr - returns true if it is able pattern match an addressing mode.
1310 /// It returns the operands which make up the maximal addressing mode it can
1311 /// match by reference.
1313 /// Parent is the parent node of the addr operand that is being matched. It
1314 /// is always a load, store, atomic node, or null. It is only null when
1315 /// checking memory operands for inline asm nodes.
1316 bool X86DAGToDAGISel::SelectAddr(SDNode *Parent, SDValue N, SDValue &Base,
1317 SDValue &Scale, SDValue &Index,
1318 SDValue &Disp, SDValue &Segment) {
1319 X86ISelAddressMode AM;
1322 // This list of opcodes are all the nodes that have an "addr:$ptr" operand
1323 // that are not a MemSDNode, and thus don't have proper addrspace info.
1324 Parent->getOpcode() != ISD::INTRINSIC_W_CHAIN && // unaligned loads, fixme
1325 Parent->getOpcode() != ISD::INTRINSIC_VOID && // nontemporal stores
1326 Parent->getOpcode() != X86ISD::TLSCALL && // Fixme
1327 Parent->getOpcode() != X86ISD::EH_SJLJ_SETJMP && // setjmp
1328 Parent->getOpcode() != X86ISD::EH_SJLJ_LONGJMP) { // longjmp
1329 unsigned AddrSpace =
1330 cast<MemSDNode>(Parent)->getPointerInfo().getAddrSpace();
1331 // AddrSpace 256 -> GS, 257 -> FS.
1332 if (AddrSpace == 256)
1333 AM.Segment = CurDAG->getRegister(X86::GS, MVT::i16);
1334 if (AddrSpace == 257)
1335 AM.Segment = CurDAG->getRegister(X86::FS, MVT::i16);
1338 if (MatchAddress(N, AM))
1341 MVT VT = N.getSimpleValueType();
1342 if (AM.BaseType == X86ISelAddressMode::RegBase) {
1343 if (!AM.Base_Reg.getNode())
1344 AM.Base_Reg = CurDAG->getRegister(0, VT);
1347 if (!AM.IndexReg.getNode())
1348 AM.IndexReg = CurDAG->getRegister(0, VT);
1350 getAddressOperands(AM, Base, Scale, Index, Disp, Segment);
1354 /// SelectScalarSSELoad - Match a scalar SSE load. In particular, we want to
1355 /// match a load whose top elements are either undef or zeros. The load flavor
1356 /// is derived from the type of N, which is either v4f32 or v2f64.
1359 /// PatternChainNode: this is the matched node that has a chain input and
1361 bool X86DAGToDAGISel::SelectScalarSSELoad(SDNode *Root,
1362 SDValue N, SDValue &Base,
1363 SDValue &Scale, SDValue &Index,
1364 SDValue &Disp, SDValue &Segment,
1365 SDValue &PatternNodeWithChain) {
1366 if (N.getOpcode() == ISD::SCALAR_TO_VECTOR) {
1367 PatternNodeWithChain = N.getOperand(0);
1368 if (ISD::isNON_EXTLoad(PatternNodeWithChain.getNode()) &&
1369 PatternNodeWithChain.hasOneUse() &&
1370 IsProfitableToFold(N.getOperand(0), N.getNode(), Root) &&
1371 IsLegalToFold(N.getOperand(0), N.getNode(), Root, OptLevel)) {
1372 LoadSDNode *LD = cast<LoadSDNode>(PatternNodeWithChain);
1373 if (!SelectAddr(LD, LD->getBasePtr(), Base, Scale, Index, Disp, Segment))
1379 // Also handle the case where we explicitly require zeros in the top
1380 // elements. This is a vector shuffle from the zero vector.
1381 if (N.getOpcode() == X86ISD::VZEXT_MOVL && N.getNode()->hasOneUse() &&
1382 // Check to see if the top elements are all zeros (or bitcast of zeros).
1383 N.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
1384 N.getOperand(0).getNode()->hasOneUse() &&
1385 ISD::isNON_EXTLoad(N.getOperand(0).getOperand(0).getNode()) &&
1386 N.getOperand(0).getOperand(0).hasOneUse() &&
1387 IsProfitableToFold(N.getOperand(0), N.getNode(), Root) &&
1388 IsLegalToFold(N.getOperand(0), N.getNode(), Root, OptLevel)) {
1389 // Okay, this is a zero extending load. Fold it.
1390 LoadSDNode *LD = cast<LoadSDNode>(N.getOperand(0).getOperand(0));
1391 if (!SelectAddr(LD, LD->getBasePtr(), Base, Scale, Index, Disp, Segment))
1393 PatternNodeWithChain = SDValue(LD, 0);
1400 bool X86DAGToDAGISel::SelectMOV64Imm32(SDValue N, SDValue &Imm) {
1401 if (const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1402 uint64_t ImmVal = CN->getZExtValue();
1403 if ((uint32_t)ImmVal != (uint64_t)ImmVal)
1406 Imm = CurDAG->getTargetConstant(ImmVal, MVT::i64);
1410 // In static codegen with small code model, we can get the address of a label
1411 // into a register with 'movl'. TableGen has already made sure we're looking
1412 // at a label of some kind.
1413 assert(N->getOpcode() == X86ISD::Wrapper &&
1414 "Unexpected node type for MOV32ri64");
1415 N = N.getOperand(0);
1417 if (N->getOpcode() != ISD::TargetConstantPool &&
1418 N->getOpcode() != ISD::TargetJumpTable &&
1419 N->getOpcode() != ISD::TargetGlobalAddress &&
1420 N->getOpcode() != ISD::TargetExternalSymbol &&
1421 N->getOpcode() != ISD::TargetBlockAddress)
1425 return TM.getCodeModel() == CodeModel::Small;
1428 bool X86DAGToDAGISel::SelectLEA64_32Addr(SDValue N, SDValue &Base,
1429 SDValue &Scale, SDValue &Index,
1430 SDValue &Disp, SDValue &Segment) {
1431 if (!SelectLEAAddr(N, Base, Scale, Index, Disp, Segment))
1435 RegisterSDNode *RN = dyn_cast<RegisterSDNode>(Base);
1436 if (RN && RN->getReg() == 0)
1437 Base = CurDAG->getRegister(0, MVT::i64);
1438 else if (Base.getValueType() == MVT::i32 && !dyn_cast<FrameIndexSDNode>(Base)) {
1439 // Base could already be %rip, particularly in the x32 ABI.
1440 Base = SDValue(CurDAG->getMachineNode(
1441 TargetOpcode::SUBREG_TO_REG, DL, MVT::i64,
1442 CurDAG->getTargetConstant(0, MVT::i64),
1444 CurDAG->getTargetConstant(X86::sub_32bit, MVT::i32)),
1448 RN = dyn_cast<RegisterSDNode>(Index);
1449 if (RN && RN->getReg() == 0)
1450 Index = CurDAG->getRegister(0, MVT::i64);
1452 assert(Index.getValueType() == MVT::i32 &&
1453 "Expect to be extending 32-bit registers for use in LEA");
1454 Index = SDValue(CurDAG->getMachineNode(
1455 TargetOpcode::SUBREG_TO_REG, DL, MVT::i64,
1456 CurDAG->getTargetConstant(0, MVT::i64),
1458 CurDAG->getTargetConstant(X86::sub_32bit, MVT::i32)),
1465 /// SelectLEAAddr - it calls SelectAddr and determines if the maximal addressing
1466 /// mode it matches can be cost effectively emitted as an LEA instruction.
1467 bool X86DAGToDAGISel::SelectLEAAddr(SDValue N,
1468 SDValue &Base, SDValue &Scale,
1469 SDValue &Index, SDValue &Disp,
1471 X86ISelAddressMode AM;
1473 // Set AM.Segment to prevent MatchAddress from using one. LEA doesn't support
1475 SDValue Copy = AM.Segment;
1476 SDValue T = CurDAG->getRegister(0, MVT::i32);
1478 if (MatchAddress(N, AM))
1480 assert (T == AM.Segment);
1483 MVT VT = N.getSimpleValueType();
1484 unsigned Complexity = 0;
1485 if (AM.BaseType == X86ISelAddressMode::RegBase)
1486 if (AM.Base_Reg.getNode())
1489 AM.Base_Reg = CurDAG->getRegister(0, VT);
1490 else if (AM.BaseType == X86ISelAddressMode::FrameIndexBase)
1493 if (AM.IndexReg.getNode())
1496 AM.IndexReg = CurDAG->getRegister(0, VT);
1498 // Don't match just leal(,%reg,2). It's cheaper to do addl %reg, %reg, or with
1503 // FIXME: We are artificially lowering the criteria to turn ADD %reg, $GA
1504 // to a LEA. This is determined with some expermentation but is by no means
1505 // optimal (especially for code size consideration). LEA is nice because of
1506 // its three-address nature. Tweak the cost function again when we can run
1507 // convertToThreeAddress() at register allocation time.
1508 if (AM.hasSymbolicDisplacement()) {
1509 // For X86-64, we should always use lea to materialize RIP relative
1511 if (Subtarget->is64Bit())
1517 if (AM.Disp && (AM.Base_Reg.getNode() || AM.IndexReg.getNode()))
1520 // If it isn't worth using an LEA, reject it.
1521 if (Complexity <= 2)
1524 getAddressOperands(AM, Base, Scale, Index, Disp, Segment);
1528 /// SelectTLSADDRAddr - This is only run on TargetGlobalTLSAddress nodes.
1529 bool X86DAGToDAGISel::SelectTLSADDRAddr(SDValue N, SDValue &Base,
1530 SDValue &Scale, SDValue &Index,
1531 SDValue &Disp, SDValue &Segment) {
1532 assert(N.getOpcode() == ISD::TargetGlobalTLSAddress);
1533 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(N);
1535 X86ISelAddressMode AM;
1536 AM.GV = GA->getGlobal();
1537 AM.Disp += GA->getOffset();
1538 AM.Base_Reg = CurDAG->getRegister(0, N.getValueType());
1539 AM.SymbolFlags = GA->getTargetFlags();
1541 if (N.getValueType() == MVT::i32) {
1543 AM.IndexReg = CurDAG->getRegister(X86::EBX, MVT::i32);
1545 AM.IndexReg = CurDAG->getRegister(0, MVT::i64);
1548 getAddressOperands(AM, Base, Scale, Index, Disp, Segment);
1553 bool X86DAGToDAGISel::TryFoldLoad(SDNode *P, SDValue N,
1554 SDValue &Base, SDValue &Scale,
1555 SDValue &Index, SDValue &Disp,
1557 if (!ISD::isNON_EXTLoad(N.getNode()) ||
1558 !IsProfitableToFold(N, P, P) ||
1559 !IsLegalToFold(N, P, P, OptLevel))
1562 return SelectAddr(N.getNode(),
1563 N.getOperand(1), Base, Scale, Index, Disp, Segment);
1566 /// getGlobalBaseReg - Return an SDNode that returns the value of
1567 /// the global base register. Output instructions required to
1568 /// initialize the global base register, if necessary.
1570 SDNode *X86DAGToDAGISel::getGlobalBaseReg() {
1571 unsigned GlobalBaseReg = getInstrInfo()->getGlobalBaseReg(MF);
1572 return CurDAG->getRegister(GlobalBaseReg, TLI->getPointerTy()).getNode();
1575 /// Atomic opcode table
1603 static const uint16_t AtomicOpcTbl[AtomicOpcEnd][AtomicSzEnd] = {
1614 X86::LOCK_ADD64mi32,
1627 X86::LOCK_SUB64mi32,
1679 X86::LOCK_AND64mi32,
1692 X86::LOCK_XOR64mi32,
1697 // Return the target constant operand for atomic-load-op and do simple
1698 // translations, such as from atomic-load-add to lock-sub. The return value is
1699 // one of the following 3 cases:
1700 // + target-constant, the operand could be supported as a target constant.
1701 // + empty, the operand is not needed any more with the new op selected.
1702 // + non-empty, otherwise.
1703 static SDValue getAtomicLoadArithTargetConstant(SelectionDAG *CurDAG,
1705 enum AtomicOpc &Op, MVT NVT,
1707 const X86Subtarget *Subtarget) {
1708 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Val)) {
1709 int64_t CNVal = CN->getSExtValue();
1710 // Quit if not 32-bit imm.
1711 if ((int32_t)CNVal != CNVal)
1713 // Quit if INT32_MIN: it would be negated as it is negative and overflow,
1714 // producing an immediate that does not fit in the 32 bits available for
1715 // an immediate operand to sub. However, it still fits in 32 bits for the
1716 // add (since it is not negated) so we can return target-constant.
1717 if (CNVal == INT32_MIN)
1718 return CurDAG->getTargetConstant(CNVal, NVT);
1719 // For atomic-load-add, we could do some optimizations.
1721 // Translate to INC/DEC if ADD by 1 or -1.
1722 if (((CNVal == 1) || (CNVal == -1)) && !Subtarget->slowIncDec()) {
1723 Op = (CNVal == 1) ? INC : DEC;
1724 // No more constant operand after being translated into INC/DEC.
1727 // Translate to SUB if ADD by negative value.
1733 return CurDAG->getTargetConstant(CNVal, NVT);
1736 // If the value operand is single-used, try to optimize it.
1737 if (Op == ADD && Val.hasOneUse()) {
1738 // Translate (atomic-load-add ptr (sub 0 x)) back to (lock-sub x).
1739 if (Val.getOpcode() == ISD::SUB && X86::isZeroNode(Val.getOperand(0))) {
1741 return Val.getOperand(1);
1743 // A special case for i16, which needs truncating as, in most cases, it's
1744 // promoted to i32. We will translate
1745 // (atomic-load-add (truncate (sub 0 x))) to (lock-sub (EXTRACT_SUBREG x))
1746 if (Val.getOpcode() == ISD::TRUNCATE && NVT == MVT::i16 &&
1747 Val.getOperand(0).getOpcode() == ISD::SUB &&
1748 X86::isZeroNode(Val.getOperand(0).getOperand(0))) {
1750 Val = Val.getOperand(0);
1751 return CurDAG->getTargetExtractSubreg(X86::sub_16bit, dl, NVT,
1759 SDNode *X86DAGToDAGISel::SelectAtomicLoadArith(SDNode *Node, MVT NVT) {
1760 if (Node->hasAnyUseOfValue(0))
1765 // Optimize common patterns for __sync_or_and_fetch and similar arith
1766 // operations where the result is not used. This allows us to use the "lock"
1767 // version of the arithmetic instruction.
1768 SDValue Chain = Node->getOperand(0);
1769 SDValue Ptr = Node->getOperand(1);
1770 SDValue Val = Node->getOperand(2);
1771 SDValue Base, Scale, Index, Disp, Segment;
1772 if (!SelectAddr(Node, Ptr, Base, Scale, Index, Disp, Segment))
1775 // Which index into the table.
1777 switch (Node->getOpcode()) {
1780 case ISD::ATOMIC_LOAD_OR:
1783 case ISD::ATOMIC_LOAD_AND:
1786 case ISD::ATOMIC_LOAD_XOR:
1789 case ISD::ATOMIC_LOAD_ADD:
1794 Val = getAtomicLoadArithTargetConstant(CurDAG, dl, Op, NVT, Val, Subtarget);
1795 bool isUnOp = !Val.getNode();
1796 bool isCN = Val.getNode() && (Val.getOpcode() == ISD::TargetConstant);
1799 switch (NVT.SimpleTy) {
1800 default: return nullptr;
1803 Opc = AtomicOpcTbl[Op][ConstantI8];
1805 Opc = AtomicOpcTbl[Op][I8];
1809 if (immSext8(Val.getNode()))
1810 Opc = AtomicOpcTbl[Op][SextConstantI16];
1812 Opc = AtomicOpcTbl[Op][ConstantI16];
1814 Opc = AtomicOpcTbl[Op][I16];
1818 if (immSext8(Val.getNode()))
1819 Opc = AtomicOpcTbl[Op][SextConstantI32];
1821 Opc = AtomicOpcTbl[Op][ConstantI32];
1823 Opc = AtomicOpcTbl[Op][I32];
1827 if (immSext8(Val.getNode()))
1828 Opc = AtomicOpcTbl[Op][SextConstantI64];
1829 else if (i64immSExt32(Val.getNode()))
1830 Opc = AtomicOpcTbl[Op][ConstantI64];
1832 llvm_unreachable("True 64 bits constant in SelectAtomicLoadArith");
1834 Opc = AtomicOpcTbl[Op][I64];
1838 assert(Opc != 0 && "Invalid arith lock transform!");
1840 // Building the new node.
1843 SDValue Ops[] = { Base, Scale, Index, Disp, Segment, Chain };
1844 Ret = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops), 0);
1846 SDValue Ops[] = { Base, Scale, Index, Disp, Segment, Val, Chain };
1847 Ret = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops), 0);
1850 // Copying the MachineMemOperand.
1851 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1852 MemOp[0] = cast<MemSDNode>(Node)->getMemOperand();
1853 cast<MachineSDNode>(Ret)->setMemRefs(MemOp, MemOp + 1);
1855 // We need to have two outputs as that is what the original instruction had.
1856 // So we add a dummy, undefined output. This is safe as we checked first
1857 // that no-one uses our output anyway.
1858 SDValue Undef = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
1860 SDValue RetVals[] = { Undef, Ret };
1861 return CurDAG->getMergeValues(RetVals, dl).getNode();
1864 /// HasNoSignedComparisonUses - Test whether the given X86ISD::CMP node has
1865 /// any uses which require the SF or OF bits to be accurate.
1866 static bool HasNoSignedComparisonUses(SDNode *N) {
1867 // Examine each user of the node.
1868 for (SDNode::use_iterator UI = N->use_begin(),
1869 UE = N->use_end(); UI != UE; ++UI) {
1870 // Only examine CopyToReg uses.
1871 if (UI->getOpcode() != ISD::CopyToReg)
1873 // Only examine CopyToReg uses that copy to EFLAGS.
1874 if (cast<RegisterSDNode>(UI->getOperand(1))->getReg() !=
1877 // Examine each user of the CopyToReg use.
1878 for (SDNode::use_iterator FlagUI = UI->use_begin(),
1879 FlagUE = UI->use_end(); FlagUI != FlagUE; ++FlagUI) {
1880 // Only examine the Flag result.
1881 if (FlagUI.getUse().getResNo() != 1) continue;
1882 // Anything unusual: assume conservatively.
1883 if (!FlagUI->isMachineOpcode()) return false;
1884 // Examine the opcode of the user.
1885 switch (FlagUI->getMachineOpcode()) {
1886 // These comparisons don't treat the most significant bit specially.
1887 case X86::SETAr: case X86::SETAEr: case X86::SETBr: case X86::SETBEr:
1888 case X86::SETEr: case X86::SETNEr: case X86::SETPr: case X86::SETNPr:
1889 case X86::SETAm: case X86::SETAEm: case X86::SETBm: case X86::SETBEm:
1890 case X86::SETEm: case X86::SETNEm: case X86::SETPm: case X86::SETNPm:
1891 case X86::JA_1: case X86::JAE_1: case X86::JB_1: case X86::JBE_1:
1892 case X86::JE_1: case X86::JNE_1: case X86::JP_1: case X86::JNP_1:
1893 case X86::CMOVA16rr: case X86::CMOVA16rm:
1894 case X86::CMOVA32rr: case X86::CMOVA32rm:
1895 case X86::CMOVA64rr: case X86::CMOVA64rm:
1896 case X86::CMOVAE16rr: case X86::CMOVAE16rm:
1897 case X86::CMOVAE32rr: case X86::CMOVAE32rm:
1898 case X86::CMOVAE64rr: case X86::CMOVAE64rm:
1899 case X86::CMOVB16rr: case X86::CMOVB16rm:
1900 case X86::CMOVB32rr: case X86::CMOVB32rm:
1901 case X86::CMOVB64rr: case X86::CMOVB64rm:
1902 case X86::CMOVBE16rr: case X86::CMOVBE16rm:
1903 case X86::CMOVBE32rr: case X86::CMOVBE32rm:
1904 case X86::CMOVBE64rr: case X86::CMOVBE64rm:
1905 case X86::CMOVE16rr: case X86::CMOVE16rm:
1906 case X86::CMOVE32rr: case X86::CMOVE32rm:
1907 case X86::CMOVE64rr: case X86::CMOVE64rm:
1908 case X86::CMOVNE16rr: case X86::CMOVNE16rm:
1909 case X86::CMOVNE32rr: case X86::CMOVNE32rm:
1910 case X86::CMOVNE64rr: case X86::CMOVNE64rm:
1911 case X86::CMOVNP16rr: case X86::CMOVNP16rm:
1912 case X86::CMOVNP32rr: case X86::CMOVNP32rm:
1913 case X86::CMOVNP64rr: case X86::CMOVNP64rm:
1914 case X86::CMOVP16rr: case X86::CMOVP16rm:
1915 case X86::CMOVP32rr: case X86::CMOVP32rm:
1916 case X86::CMOVP64rr: case X86::CMOVP64rm:
1918 // Anything else: assume conservatively.
1919 default: return false;
1926 /// isLoadIncOrDecStore - Check whether or not the chain ending in StoreNode
1927 /// is suitable for doing the {load; increment or decrement; store} to modify
1929 static bool isLoadIncOrDecStore(StoreSDNode *StoreNode, unsigned Opc,
1930 SDValue StoredVal, SelectionDAG *CurDAG,
1931 LoadSDNode* &LoadNode, SDValue &InputChain) {
1933 // is the value stored the result of a DEC or INC?
1934 if (!(Opc == X86ISD::DEC || Opc == X86ISD::INC)) return false;
1936 // is the stored value result 0 of the load?
1937 if (StoredVal.getResNo() != 0) return false;
1939 // are there other uses of the loaded value than the inc or dec?
1940 if (!StoredVal.getNode()->hasNUsesOfValue(1, 0)) return false;
1942 // is the store non-extending and non-indexed?
1943 if (!ISD::isNormalStore(StoreNode) || StoreNode->isNonTemporal())
1946 SDValue Load = StoredVal->getOperand(0);
1947 // Is the stored value a non-extending and non-indexed load?
1948 if (!ISD::isNormalLoad(Load.getNode())) return false;
1950 // Return LoadNode by reference.
1951 LoadNode = cast<LoadSDNode>(Load);
1952 // is the size of the value one that we can handle? (i.e. 64, 32, 16, or 8)
1953 EVT LdVT = LoadNode->getMemoryVT();
1954 if (LdVT != MVT::i64 && LdVT != MVT::i32 && LdVT != MVT::i16 &&
1958 // Is store the only read of the loaded value?
1959 if (!Load.hasOneUse())
1962 // Is the address of the store the same as the load?
1963 if (LoadNode->getBasePtr() != StoreNode->getBasePtr() ||
1964 LoadNode->getOffset() != StoreNode->getOffset())
1967 // Check if the chain is produced by the load or is a TokenFactor with
1968 // the load output chain as an operand. Return InputChain by reference.
1969 SDValue Chain = StoreNode->getChain();
1971 bool ChainCheck = false;
1972 if (Chain == Load.getValue(1)) {
1974 InputChain = LoadNode->getChain();
1975 } else if (Chain.getOpcode() == ISD::TokenFactor) {
1976 SmallVector<SDValue, 4> ChainOps;
1977 for (unsigned i = 0, e = Chain.getNumOperands(); i != e; ++i) {
1978 SDValue Op = Chain.getOperand(i);
1979 if (Op == Load.getValue(1)) {
1984 // Make sure using Op as part of the chain would not cause a cycle here.
1985 // In theory, we could check whether the chain node is a predecessor of
1986 // the load. But that can be very expensive. Instead visit the uses and
1987 // make sure they all have smaller node id than the load.
1988 int LoadId = LoadNode->getNodeId();
1989 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
1990 UE = UI->use_end(); UI != UE; ++UI) {
1991 if (UI.getUse().getResNo() != 0)
1993 if (UI->getNodeId() > LoadId)
1997 ChainOps.push_back(Op);
2001 // Make a new TokenFactor with all the other input chains except
2003 InputChain = CurDAG->getNode(ISD::TokenFactor, SDLoc(Chain),
2004 MVT::Other, ChainOps);
2012 /// getFusedLdStOpcode - Get the appropriate X86 opcode for an in memory
2013 /// increment or decrement. Opc should be X86ISD::DEC or X86ISD::INC.
2014 static unsigned getFusedLdStOpcode(EVT &LdVT, unsigned Opc) {
2015 if (Opc == X86ISD::DEC) {
2016 if (LdVT == MVT::i64) return X86::DEC64m;
2017 if (LdVT == MVT::i32) return X86::DEC32m;
2018 if (LdVT == MVT::i16) return X86::DEC16m;
2019 if (LdVT == MVT::i8) return X86::DEC8m;
2021 assert(Opc == X86ISD::INC && "unrecognized opcode");
2022 if (LdVT == MVT::i64) return X86::INC64m;
2023 if (LdVT == MVT::i32) return X86::INC32m;
2024 if (LdVT == MVT::i16) return X86::INC16m;
2025 if (LdVT == MVT::i8) return X86::INC8m;
2027 llvm_unreachable("unrecognized size for LdVT");
2030 /// SelectGather - Customized ISel for GATHER operations.
2032 SDNode *X86DAGToDAGISel::SelectGather(SDNode *Node, unsigned Opc) {
2033 // Operands of Gather: VSrc, Base, VIdx, VMask, Scale
2034 SDValue Chain = Node->getOperand(0);
2035 SDValue VSrc = Node->getOperand(2);
2036 SDValue Base = Node->getOperand(3);
2037 SDValue VIdx = Node->getOperand(4);
2038 SDValue VMask = Node->getOperand(5);
2039 ConstantSDNode *Scale = dyn_cast<ConstantSDNode>(Node->getOperand(6));
2043 SDVTList VTs = CurDAG->getVTList(VSrc.getValueType(), VSrc.getValueType(),
2046 // Memory Operands: Base, Scale, Index, Disp, Segment
2047 SDValue Disp = CurDAG->getTargetConstant(0, MVT::i32);
2048 SDValue Segment = CurDAG->getRegister(0, MVT::i32);
2049 const SDValue Ops[] = { VSrc, Base, getI8Imm(Scale->getSExtValue()), VIdx,
2050 Disp, Segment, VMask, Chain};
2051 SDNode *ResNode = CurDAG->getMachineNode(Opc, SDLoc(Node), VTs, Ops);
2052 // Node has 2 outputs: VDst and MVT::Other.
2053 // ResNode has 3 outputs: VDst, VMask_wb, and MVT::Other.
2054 // We replace VDst of Node with VDst of ResNode, and Other of Node with Other
2056 ReplaceUses(SDValue(Node, 0), SDValue(ResNode, 0));
2057 ReplaceUses(SDValue(Node, 1), SDValue(ResNode, 2));
2061 SDNode *X86DAGToDAGISel::Select(SDNode *Node) {
2062 MVT NVT = Node->getSimpleValueType(0);
2064 unsigned Opcode = Node->getOpcode();
2067 DEBUG(dbgs() << "Selecting: "; Node->dump(CurDAG); dbgs() << '\n');
2069 if (Node->isMachineOpcode()) {
2070 DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << '\n');
2071 Node->setNodeId(-1);
2072 return nullptr; // Already selected.
2077 case ISD::INTRINSIC_W_CHAIN: {
2078 unsigned IntNo = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
2081 case Intrinsic::x86_avx2_gather_d_pd:
2082 case Intrinsic::x86_avx2_gather_d_pd_256:
2083 case Intrinsic::x86_avx2_gather_q_pd:
2084 case Intrinsic::x86_avx2_gather_q_pd_256:
2085 case Intrinsic::x86_avx2_gather_d_ps:
2086 case Intrinsic::x86_avx2_gather_d_ps_256:
2087 case Intrinsic::x86_avx2_gather_q_ps:
2088 case Intrinsic::x86_avx2_gather_q_ps_256:
2089 case Intrinsic::x86_avx2_gather_d_q:
2090 case Intrinsic::x86_avx2_gather_d_q_256:
2091 case Intrinsic::x86_avx2_gather_q_q:
2092 case Intrinsic::x86_avx2_gather_q_q_256:
2093 case Intrinsic::x86_avx2_gather_d_d:
2094 case Intrinsic::x86_avx2_gather_d_d_256:
2095 case Intrinsic::x86_avx2_gather_q_d:
2096 case Intrinsic::x86_avx2_gather_q_d_256: {
2097 if (!Subtarget->hasAVX2())
2101 default: llvm_unreachable("Impossible intrinsic");
2102 case Intrinsic::x86_avx2_gather_d_pd: Opc = X86::VGATHERDPDrm; break;
2103 case Intrinsic::x86_avx2_gather_d_pd_256: Opc = X86::VGATHERDPDYrm; break;
2104 case Intrinsic::x86_avx2_gather_q_pd: Opc = X86::VGATHERQPDrm; break;
2105 case Intrinsic::x86_avx2_gather_q_pd_256: Opc = X86::VGATHERQPDYrm; break;
2106 case Intrinsic::x86_avx2_gather_d_ps: Opc = X86::VGATHERDPSrm; break;
2107 case Intrinsic::x86_avx2_gather_d_ps_256: Opc = X86::VGATHERDPSYrm; break;
2108 case Intrinsic::x86_avx2_gather_q_ps: Opc = X86::VGATHERQPSrm; break;
2109 case Intrinsic::x86_avx2_gather_q_ps_256: Opc = X86::VGATHERQPSYrm; break;
2110 case Intrinsic::x86_avx2_gather_d_q: Opc = X86::VPGATHERDQrm; break;
2111 case Intrinsic::x86_avx2_gather_d_q_256: Opc = X86::VPGATHERDQYrm; break;
2112 case Intrinsic::x86_avx2_gather_q_q: Opc = X86::VPGATHERQQrm; break;
2113 case Intrinsic::x86_avx2_gather_q_q_256: Opc = X86::VPGATHERQQYrm; break;
2114 case Intrinsic::x86_avx2_gather_d_d: Opc = X86::VPGATHERDDrm; break;
2115 case Intrinsic::x86_avx2_gather_d_d_256: Opc = X86::VPGATHERDDYrm; break;
2116 case Intrinsic::x86_avx2_gather_q_d: Opc = X86::VPGATHERQDrm; break;
2117 case Intrinsic::x86_avx2_gather_q_d_256: Opc = X86::VPGATHERQDYrm; break;
2119 SDNode *RetVal = SelectGather(Node, Opc);
2121 // We already called ReplaceUses inside SelectGather.
2128 case X86ISD::GlobalBaseReg:
2129 return getGlobalBaseReg();
2131 case X86ISD::SHRUNKBLEND: {
2132 // SHRUNKBLEND selects like a regular VSELECT.
2133 SDValue VSelect = CurDAG->getNode(
2134 ISD::VSELECT, SDLoc(Node), Node->getValueType(0), Node->getOperand(0),
2135 Node->getOperand(1), Node->getOperand(2));
2136 ReplaceUses(SDValue(Node, 0), VSelect);
2137 SelectCode(VSelect.getNode());
2138 // We already called ReplaceUses.
2142 case ISD::ATOMIC_LOAD_XOR:
2143 case ISD::ATOMIC_LOAD_AND:
2144 case ISD::ATOMIC_LOAD_OR:
2145 case ISD::ATOMIC_LOAD_ADD: {
2146 SDNode *RetVal = SelectAtomicLoadArith(Node, NVT);
2154 // For operations of the form (x << C1) op C2, check if we can use a smaller
2155 // encoding for C2 by transforming it into (x op (C2>>C1)) << C1.
2156 SDValue N0 = Node->getOperand(0);
2157 SDValue N1 = Node->getOperand(1);
2159 if (N0->getOpcode() != ISD::SHL || !N0->hasOneUse())
2162 // i8 is unshrinkable, i16 should be promoted to i32.
2163 if (NVT != MVT::i32 && NVT != MVT::i64)
2166 ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(N1);
2167 ConstantSDNode *ShlCst = dyn_cast<ConstantSDNode>(N0->getOperand(1));
2168 if (!Cst || !ShlCst)
2171 int64_t Val = Cst->getSExtValue();
2172 uint64_t ShlVal = ShlCst->getZExtValue();
2174 // Make sure that we don't change the operation by removing bits.
2175 // This only matters for OR and XOR, AND is unaffected.
2176 uint64_t RemovedBitsMask = (1ULL << ShlVal) - 1;
2177 if (Opcode != ISD::AND && (Val & RemovedBitsMask) != 0)
2183 // Check the minimum bitwidth for the new constant.
2184 // TODO: AND32ri is the same as AND64ri32 with zext imm.
2185 // TODO: MOV32ri+OR64r is cheaper than MOV64ri64+OR64rr
2186 // TODO: Using 16 and 8 bit operations is also possible for or32 & xor32.
2187 if (!isInt<8>(Val) && isInt<8>(Val >> ShlVal))
2189 else if (!isInt<32>(Val) && isInt<32>(Val >> ShlVal))
2192 // Bail if there is no smaller encoding.
2196 switch (NVT.SimpleTy) {
2197 default: llvm_unreachable("Unsupported VT!");
2199 assert(CstVT == MVT::i8);
2200 ShlOp = X86::SHL32ri;
2203 default: llvm_unreachable("Impossible opcode");
2204 case ISD::AND: Op = X86::AND32ri8; break;
2205 case ISD::OR: Op = X86::OR32ri8; break;
2206 case ISD::XOR: Op = X86::XOR32ri8; break;
2210 assert(CstVT == MVT::i8 || CstVT == MVT::i32);
2211 ShlOp = X86::SHL64ri;
2214 default: llvm_unreachable("Impossible opcode");
2215 case ISD::AND: Op = CstVT==MVT::i8? X86::AND64ri8 : X86::AND64ri32; break;
2216 case ISD::OR: Op = CstVT==MVT::i8? X86::OR64ri8 : X86::OR64ri32; break;
2217 case ISD::XOR: Op = CstVT==MVT::i8? X86::XOR64ri8 : X86::XOR64ri32; break;
2222 // Emit the smaller op and the shift.
2223 SDValue NewCst = CurDAG->getTargetConstant(Val >> ShlVal, CstVT);
2224 SDNode *New = CurDAG->getMachineNode(Op, dl, NVT, N0->getOperand(0),NewCst);
2225 return CurDAG->SelectNodeTo(Node, ShlOp, NVT, SDValue(New, 0),
2229 case X86ISD::SMUL8: {
2230 SDValue N0 = Node->getOperand(0);
2231 SDValue N1 = Node->getOperand(1);
2233 Opc = (Opcode == X86ISD::SMUL8 ? X86::IMUL8r : X86::MUL8r);
2235 SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, X86::AL,
2236 N0, SDValue()).getValue(1);
2238 SDVTList VTs = CurDAG->getVTList(NVT, MVT::i32);
2239 SDValue Ops[] = {N1, InFlag};
2240 SDNode *CNode = CurDAG->getMachineNode(Opc, dl, VTs, Ops);
2242 ReplaceUses(SDValue(Node, 0), SDValue(CNode, 0));
2243 ReplaceUses(SDValue(Node, 1), SDValue(CNode, 1));
2247 case X86ISD::UMUL: {
2248 SDValue N0 = Node->getOperand(0);
2249 SDValue N1 = Node->getOperand(1);
2252 switch (NVT.SimpleTy) {
2253 default: llvm_unreachable("Unsupported VT!");
2254 case MVT::i8: LoReg = X86::AL; Opc = X86::MUL8r; break;
2255 case MVT::i16: LoReg = X86::AX; Opc = X86::MUL16r; break;
2256 case MVT::i32: LoReg = X86::EAX; Opc = X86::MUL32r; break;
2257 case MVT::i64: LoReg = X86::RAX; Opc = X86::MUL64r; break;
2260 SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, LoReg,
2261 N0, SDValue()).getValue(1);
2263 SDVTList VTs = CurDAG->getVTList(NVT, NVT, MVT::i32);
2264 SDValue Ops[] = {N1, InFlag};
2265 SDNode *CNode = CurDAG->getMachineNode(Opc, dl, VTs, Ops);
2267 ReplaceUses(SDValue(Node, 0), SDValue(CNode, 0));
2268 ReplaceUses(SDValue(Node, 1), SDValue(CNode, 1));
2269 ReplaceUses(SDValue(Node, 2), SDValue(CNode, 2));
2273 case ISD::SMUL_LOHI:
2274 case ISD::UMUL_LOHI: {
2275 SDValue N0 = Node->getOperand(0);
2276 SDValue N1 = Node->getOperand(1);
2278 bool isSigned = Opcode == ISD::SMUL_LOHI;
2279 bool hasBMI2 = Subtarget->hasBMI2();
2281 switch (NVT.SimpleTy) {
2282 default: llvm_unreachable("Unsupported VT!");
2283 case MVT::i8: Opc = X86::MUL8r; MOpc = X86::MUL8m; break;
2284 case MVT::i16: Opc = X86::MUL16r; MOpc = X86::MUL16m; break;
2285 case MVT::i32: Opc = hasBMI2 ? X86::MULX32rr : X86::MUL32r;
2286 MOpc = hasBMI2 ? X86::MULX32rm : X86::MUL32m; break;
2287 case MVT::i64: Opc = hasBMI2 ? X86::MULX64rr : X86::MUL64r;
2288 MOpc = hasBMI2 ? X86::MULX64rm : X86::MUL64m; break;
2291 switch (NVT.SimpleTy) {
2292 default: llvm_unreachable("Unsupported VT!");
2293 case MVT::i8: Opc = X86::IMUL8r; MOpc = X86::IMUL8m; break;
2294 case MVT::i16: Opc = X86::IMUL16r; MOpc = X86::IMUL16m; break;
2295 case MVT::i32: Opc = X86::IMUL32r; MOpc = X86::IMUL32m; break;
2296 case MVT::i64: Opc = X86::IMUL64r; MOpc = X86::IMUL64m; break;
2300 unsigned SrcReg, LoReg, HiReg;
2302 default: llvm_unreachable("Unknown MUL opcode!");
2305 SrcReg = LoReg = X86::AL; HiReg = X86::AH;
2309 SrcReg = LoReg = X86::AX; HiReg = X86::DX;
2313 SrcReg = LoReg = X86::EAX; HiReg = X86::EDX;
2317 SrcReg = LoReg = X86::RAX; HiReg = X86::RDX;
2320 SrcReg = X86::EDX; LoReg = HiReg = 0;
2323 SrcReg = X86::RDX; LoReg = HiReg = 0;
2327 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
2328 bool foldedLoad = TryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
2329 // Multiply is commmutative.
2331 foldedLoad = TryFoldLoad(Node, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
2336 SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, SrcReg,
2337 N0, SDValue()).getValue(1);
2338 SDValue ResHi, ResLo;
2342 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0),
2344 if (MOpc == X86::MULX32rm || MOpc == X86::MULX64rm) {
2345 SDVTList VTs = CurDAG->getVTList(NVT, NVT, MVT::Other, MVT::Glue);
2346 SDNode *CNode = CurDAG->getMachineNode(MOpc, dl, VTs, Ops);
2347 ResHi = SDValue(CNode, 0);
2348 ResLo = SDValue(CNode, 1);
2349 Chain = SDValue(CNode, 2);
2350 InFlag = SDValue(CNode, 3);
2352 SDVTList VTs = CurDAG->getVTList(MVT::Other, MVT::Glue);
2353 SDNode *CNode = CurDAG->getMachineNode(MOpc, dl, VTs, Ops);
2354 Chain = SDValue(CNode, 0);
2355 InFlag = SDValue(CNode, 1);
2358 // Update the chain.
2359 ReplaceUses(N1.getValue(1), Chain);
2361 SDValue Ops[] = { N1, InFlag };
2362 if (Opc == X86::MULX32rr || Opc == X86::MULX64rr) {
2363 SDVTList VTs = CurDAG->getVTList(NVT, NVT, MVT::Glue);
2364 SDNode *CNode = CurDAG->getMachineNode(Opc, dl, VTs, Ops);
2365 ResHi = SDValue(CNode, 0);
2366 ResLo = SDValue(CNode, 1);
2367 InFlag = SDValue(CNode, 2);
2369 SDVTList VTs = CurDAG->getVTList(MVT::Glue);
2370 SDNode *CNode = CurDAG->getMachineNode(Opc, dl, VTs, Ops);
2371 InFlag = SDValue(CNode, 0);
2375 // Prevent use of AH in a REX instruction by referencing AX instead.
2376 if (HiReg == X86::AH && Subtarget->is64Bit() &&
2377 !SDValue(Node, 1).use_empty()) {
2378 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2379 X86::AX, MVT::i16, InFlag);
2380 InFlag = Result.getValue(2);
2381 // Get the low part if needed. Don't use getCopyFromReg for aliasing
2383 if (!SDValue(Node, 0).use_empty())
2384 ReplaceUses(SDValue(Node, 1),
2385 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result));
2387 // Shift AX down 8 bits.
2388 Result = SDValue(CurDAG->getMachineNode(X86::SHR16ri, dl, MVT::i16,
2390 CurDAG->getTargetConstant(8, MVT::i8)), 0);
2391 // Then truncate it down to i8.
2392 ReplaceUses(SDValue(Node, 1),
2393 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result));
2395 // Copy the low half of the result, if it is needed.
2396 if (!SDValue(Node, 0).use_empty()) {
2397 if (!ResLo.getNode()) {
2398 assert(LoReg && "Register for low half is not defined!");
2399 ResLo = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, LoReg, NVT,
2401 InFlag = ResLo.getValue(2);
2403 ReplaceUses(SDValue(Node, 0), ResLo);
2404 DEBUG(dbgs() << "=> "; ResLo.getNode()->dump(CurDAG); dbgs() << '\n');
2406 // Copy the high half of the result, if it is needed.
2407 if (!SDValue(Node, 1).use_empty()) {
2408 if (!ResHi.getNode()) {
2409 assert(HiReg && "Register for high half is not defined!");
2410 ResHi = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, HiReg, NVT,
2412 InFlag = ResHi.getValue(2);
2414 ReplaceUses(SDValue(Node, 1), ResHi);
2415 DEBUG(dbgs() << "=> "; ResHi.getNode()->dump(CurDAG); dbgs() << '\n');
2423 case X86ISD::SDIVREM8_SEXT_HREG:
2424 case X86ISD::UDIVREM8_ZEXT_HREG: {
2425 SDValue N0 = Node->getOperand(0);
2426 SDValue N1 = Node->getOperand(1);
2428 bool isSigned = (Opcode == ISD::SDIVREM ||
2429 Opcode == X86ISD::SDIVREM8_SEXT_HREG);
2431 switch (NVT.SimpleTy) {
2432 default: llvm_unreachable("Unsupported VT!");
2433 case MVT::i8: Opc = X86::DIV8r; MOpc = X86::DIV8m; break;
2434 case MVT::i16: Opc = X86::DIV16r; MOpc = X86::DIV16m; break;
2435 case MVT::i32: Opc = X86::DIV32r; MOpc = X86::DIV32m; break;
2436 case MVT::i64: Opc = X86::DIV64r; MOpc = X86::DIV64m; break;
2439 switch (NVT.SimpleTy) {
2440 default: llvm_unreachable("Unsupported VT!");
2441 case MVT::i8: Opc = X86::IDIV8r; MOpc = X86::IDIV8m; break;
2442 case MVT::i16: Opc = X86::IDIV16r; MOpc = X86::IDIV16m; break;
2443 case MVT::i32: Opc = X86::IDIV32r; MOpc = X86::IDIV32m; break;
2444 case MVT::i64: Opc = X86::IDIV64r; MOpc = X86::IDIV64m; break;
2448 unsigned LoReg, HiReg, ClrReg;
2449 unsigned SExtOpcode;
2450 switch (NVT.SimpleTy) {
2451 default: llvm_unreachable("Unsupported VT!");
2453 LoReg = X86::AL; ClrReg = HiReg = X86::AH;
2454 SExtOpcode = X86::CBW;
2457 LoReg = X86::AX; HiReg = X86::DX;
2459 SExtOpcode = X86::CWD;
2462 LoReg = X86::EAX; ClrReg = HiReg = X86::EDX;
2463 SExtOpcode = X86::CDQ;
2466 LoReg = X86::RAX; ClrReg = HiReg = X86::RDX;
2467 SExtOpcode = X86::CQO;
2471 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
2472 bool foldedLoad = TryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
2473 bool signBitIsZero = CurDAG->SignBitIsZero(N0);
2476 if (NVT == MVT::i8 && (!isSigned || signBitIsZero)) {
2477 // Special case for div8, just use a move with zero extension to AX to
2478 // clear the upper 8 bits (AH).
2479 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Move, Chain;
2480 if (TryFoldLoad(Node, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) {
2481 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N0.getOperand(0) };
2483 SDValue(CurDAG->getMachineNode(X86::MOVZX32rm8, dl, MVT::i32,
2484 MVT::Other, Ops), 0);
2485 Chain = Move.getValue(1);
2486 ReplaceUses(N0.getValue(1), Chain);
2489 SDValue(CurDAG->getMachineNode(X86::MOVZX32rr8, dl, MVT::i32, N0),0);
2490 Chain = CurDAG->getEntryNode();
2492 Chain = CurDAG->getCopyToReg(Chain, dl, X86::EAX, Move, SDValue());
2493 InFlag = Chain.getValue(1);
2496 CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl,
2497 LoReg, N0, SDValue()).getValue(1);
2498 if (isSigned && !signBitIsZero) {
2499 // Sign extend the low part into the high part.
2501 SDValue(CurDAG->getMachineNode(SExtOpcode, dl, MVT::Glue, InFlag),0);
2503 // Zero out the high part, effectively zero extending the input.
2504 SDValue ClrNode = SDValue(CurDAG->getMachineNode(X86::MOV32r0, dl, NVT), 0);
2505 switch (NVT.SimpleTy) {
2508 SDValue(CurDAG->getMachineNode(
2509 TargetOpcode::EXTRACT_SUBREG, dl, MVT::i16, ClrNode,
2510 CurDAG->getTargetConstant(X86::sub_16bit, MVT::i32)),
2517 SDValue(CurDAG->getMachineNode(
2518 TargetOpcode::SUBREG_TO_REG, dl, MVT::i64,
2519 CurDAG->getTargetConstant(0, MVT::i64), ClrNode,
2520 CurDAG->getTargetConstant(X86::sub_32bit, MVT::i32)),
2524 llvm_unreachable("Unexpected division source");
2527 InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, ClrReg,
2528 ClrNode, InFlag).getValue(1);
2533 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0),
2536 CurDAG->getMachineNode(MOpc, dl, MVT::Other, MVT::Glue, Ops);
2537 InFlag = SDValue(CNode, 1);
2538 // Update the chain.
2539 ReplaceUses(N1.getValue(1), SDValue(CNode, 0));
2542 SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Glue, N1, InFlag), 0);
2545 // Prevent use of AH in a REX instruction by explicitly copying it to
2546 // an ABCD_L register.
2548 // The current assumption of the register allocator is that isel
2549 // won't generate explicit references to the GR8_ABCD_H registers. If
2550 // the allocator and/or the backend get enhanced to be more robust in
2551 // that regard, this can be, and should be, removed.
2552 if (HiReg == X86::AH && !SDValue(Node, 1).use_empty()) {
2553 SDValue AHCopy = CurDAG->getRegister(X86::AH, MVT::i8);
2554 unsigned AHExtOpcode =
2555 isSigned ? X86::MOVSX32_NOREXrr8 : X86::MOVZX32_NOREXrr8;
2557 SDNode *RNode = CurDAG->getMachineNode(AHExtOpcode, dl, MVT::i32,
2558 MVT::Glue, AHCopy, InFlag);
2559 SDValue Result(RNode, 0);
2560 InFlag = SDValue(RNode, 1);
2562 if (Opcode == X86ISD::UDIVREM8_ZEXT_HREG ||
2563 Opcode == X86ISD::SDIVREM8_SEXT_HREG) {
2564 if (Node->getValueType(1) == MVT::i64) {
2565 // It's not possible to directly movsx AH to a 64bit register, because
2566 // the latter needs the REX prefix, but the former can't have it.
2567 assert(Opcode != X86ISD::SDIVREM8_SEXT_HREG &&
2568 "Unexpected i64 sext of h-register");
2570 SDValue(CurDAG->getMachineNode(
2571 TargetOpcode::SUBREG_TO_REG, dl, MVT::i64,
2572 CurDAG->getTargetConstant(0, MVT::i64), Result,
2573 CurDAG->getTargetConstant(X86::sub_32bit, MVT::i32)),
2578 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result);
2580 ReplaceUses(SDValue(Node, 1), Result);
2581 DEBUG(dbgs() << "=> "; Result.getNode()->dump(CurDAG); dbgs() << '\n');
2583 // Copy the division (low) result, if it is needed.
2584 if (!SDValue(Node, 0).use_empty()) {
2585 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2586 LoReg, NVT, InFlag);
2587 InFlag = Result.getValue(2);
2588 ReplaceUses(SDValue(Node, 0), Result);
2589 DEBUG(dbgs() << "=> "; Result.getNode()->dump(CurDAG); dbgs() << '\n');
2591 // Copy the remainder (high) result, if it is needed.
2592 if (!SDValue(Node, 1).use_empty()) {
2593 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2594 HiReg, NVT, InFlag);
2595 InFlag = Result.getValue(2);
2596 ReplaceUses(SDValue(Node, 1), Result);
2597 DEBUG(dbgs() << "=> "; Result.getNode()->dump(CurDAG); dbgs() << '\n');
2604 // Sometimes a SUB is used to perform comparison.
2605 if (Opcode == X86ISD::SUB && Node->hasAnyUseOfValue(0))
2606 // This node is not a CMP.
2608 SDValue N0 = Node->getOperand(0);
2609 SDValue N1 = Node->getOperand(1);
2611 if (N0.getOpcode() == ISD::TRUNCATE && N0.hasOneUse() &&
2612 HasNoSignedComparisonUses(Node))
2613 N0 = N0.getOperand(0);
2615 // Look for (X86cmp (and $op, $imm), 0) and see if we can convert it to
2616 // use a smaller encoding.
2617 // Look past the truncate if CMP is the only use of it.
2618 if ((N0.getNode()->getOpcode() == ISD::AND ||
2619 (N0.getResNo() == 0 && N0.getNode()->getOpcode() == X86ISD::AND)) &&
2620 N0.getNode()->hasOneUse() &&
2621 N0.getValueType() != MVT::i8 &&
2622 X86::isZeroNode(N1)) {
2623 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getNode()->getOperand(1));
2626 // For example, convert "testl %eax, $8" to "testb %al, $8"
2627 if ((C->getZExtValue() & ~UINT64_C(0xff)) == 0 &&
2628 (!(C->getZExtValue() & 0x80) ||
2629 HasNoSignedComparisonUses(Node))) {
2630 SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i8);
2631 SDValue Reg = N0.getNode()->getOperand(0);
2633 // On x86-32, only the ABCD registers have 8-bit subregisters.
2634 if (!Subtarget->is64Bit()) {
2635 const TargetRegisterClass *TRC;
2636 switch (N0.getSimpleValueType().SimpleTy) {
2637 case MVT::i32: TRC = &X86::GR32_ABCDRegClass; break;
2638 case MVT::i16: TRC = &X86::GR16_ABCDRegClass; break;
2639 default: llvm_unreachable("Unsupported TEST operand type!");
2641 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), MVT::i32);
2642 Reg = SDValue(CurDAG->getMachineNode(X86::COPY_TO_REGCLASS, dl,
2643 Reg.getValueType(), Reg, RC), 0);
2646 // Extract the l-register.
2647 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl,
2651 SDNode *NewNode = CurDAG->getMachineNode(X86::TEST8ri, dl, MVT::i32,
2653 // Replace SUB|CMP with TEST, since SUB has two outputs while TEST has
2654 // one, do not call ReplaceAllUsesWith.
2655 ReplaceUses(SDValue(Node, (Opcode == X86ISD::SUB ? 1 : 0)),
2656 SDValue(NewNode, 0));
2660 // For example, "testl %eax, $2048" to "testb %ah, $8".
2661 if ((C->getZExtValue() & ~UINT64_C(0xff00)) == 0 &&
2662 (!(C->getZExtValue() & 0x8000) ||
2663 HasNoSignedComparisonUses(Node))) {
2664 // Shift the immediate right by 8 bits.
2665 SDValue ShiftedImm = CurDAG->getTargetConstant(C->getZExtValue() >> 8,
2667 SDValue Reg = N0.getNode()->getOperand(0);
2669 // Put the value in an ABCD register.
2670 const TargetRegisterClass *TRC;
2671 switch (N0.getSimpleValueType().SimpleTy) {
2672 case MVT::i64: TRC = &X86::GR64_ABCDRegClass; break;
2673 case MVT::i32: TRC = &X86::GR32_ABCDRegClass; break;
2674 case MVT::i16: TRC = &X86::GR16_ABCDRegClass; break;
2675 default: llvm_unreachable("Unsupported TEST operand type!");
2677 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), MVT::i32);
2678 Reg = SDValue(CurDAG->getMachineNode(X86::COPY_TO_REGCLASS, dl,
2679 Reg.getValueType(), Reg, RC), 0);
2681 // Extract the h-register.
2682 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_8bit_hi, dl,
2685 // Emit a testb. The EXTRACT_SUBREG becomes a COPY that can only
2686 // target GR8_NOREX registers, so make sure the register class is
2688 SDNode *NewNode = CurDAG->getMachineNode(X86::TEST8ri_NOREX, dl,
2689 MVT::i32, Subreg, ShiftedImm);
2690 // Replace SUB|CMP with TEST, since SUB has two outputs while TEST has
2691 // one, do not call ReplaceAllUsesWith.
2692 ReplaceUses(SDValue(Node, (Opcode == X86ISD::SUB ? 1 : 0)),
2693 SDValue(NewNode, 0));
2697 // For example, "testl %eax, $32776" to "testw %ax, $32776".
2698 if ((C->getZExtValue() & ~UINT64_C(0xffff)) == 0 &&
2699 N0.getValueType() != MVT::i16 &&
2700 (!(C->getZExtValue() & 0x8000) ||
2701 HasNoSignedComparisonUses(Node))) {
2702 SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i16);
2703 SDValue Reg = N0.getNode()->getOperand(0);
2705 // Extract the 16-bit subregister.
2706 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_16bit, dl,
2710 SDNode *NewNode = CurDAG->getMachineNode(X86::TEST16ri, dl, MVT::i32,
2712 // Replace SUB|CMP with TEST, since SUB has two outputs while TEST has
2713 // one, do not call ReplaceAllUsesWith.
2714 ReplaceUses(SDValue(Node, (Opcode == X86ISD::SUB ? 1 : 0)),
2715 SDValue(NewNode, 0));
2719 // For example, "testq %rax, $268468232" to "testl %eax, $268468232".
2720 if ((C->getZExtValue() & ~UINT64_C(0xffffffff)) == 0 &&
2721 N0.getValueType() == MVT::i64 &&
2722 (!(C->getZExtValue() & 0x80000000) ||
2723 HasNoSignedComparisonUses(Node))) {
2724 SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i32);
2725 SDValue Reg = N0.getNode()->getOperand(0);
2727 // Extract the 32-bit subregister.
2728 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_32bit, dl,
2732 SDNode *NewNode = CurDAG->getMachineNode(X86::TEST32ri, dl, MVT::i32,
2734 // Replace SUB|CMP with TEST, since SUB has two outputs while TEST has
2735 // one, do not call ReplaceAllUsesWith.
2736 ReplaceUses(SDValue(Node, (Opcode == X86ISD::SUB ? 1 : 0)),
2737 SDValue(NewNode, 0));
2744 // Change a chain of {load; incr or dec; store} of the same value into
2745 // a simple increment or decrement through memory of that value, if the
2746 // uses of the modified value and its address are suitable.
2747 // The DEC64m tablegen pattern is currently not able to match the case where
2748 // the EFLAGS on the original DEC are used. (This also applies to
2749 // {INC,DEC}X{64,32,16,8}.)
2750 // We'll need to improve tablegen to allow flags to be transferred from a
2751 // node in the pattern to the result node. probably with a new keyword
2752 // for example, we have this
2753 // def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",
2754 // [(store (add (loadi64 addr:$dst), -1), addr:$dst),
2755 // (implicit EFLAGS)]>;
2756 // but maybe need something like this
2757 // def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",
2758 // [(store (add (loadi64 addr:$dst), -1), addr:$dst),
2759 // (transferrable EFLAGS)]>;
2761 StoreSDNode *StoreNode = cast<StoreSDNode>(Node);
2762 SDValue StoredVal = StoreNode->getOperand(1);
2763 unsigned Opc = StoredVal->getOpcode();
2765 LoadSDNode *LoadNode = nullptr;
2767 if (!isLoadIncOrDecStore(StoreNode, Opc, StoredVal, CurDAG,
2768 LoadNode, InputChain))
2771 SDValue Base, Scale, Index, Disp, Segment;
2772 if (!SelectAddr(LoadNode, LoadNode->getBasePtr(),
2773 Base, Scale, Index, Disp, Segment))
2776 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(2);
2777 MemOp[0] = StoreNode->getMemOperand();
2778 MemOp[1] = LoadNode->getMemOperand();
2779 const SDValue Ops[] = { Base, Scale, Index, Disp, Segment, InputChain };
2780 EVT LdVT = LoadNode->getMemoryVT();
2781 unsigned newOpc = getFusedLdStOpcode(LdVT, Opc);
2782 MachineSDNode *Result = CurDAG->getMachineNode(newOpc,
2784 MVT::i32, MVT::Other, Ops);
2785 Result->setMemRefs(MemOp, MemOp + 2);
2787 ReplaceUses(SDValue(StoreNode, 0), SDValue(Result, 1));
2788 ReplaceUses(SDValue(StoredVal.getNode(), 1), SDValue(Result, 0));
2794 SDNode *ResNode = SelectCode(Node);
2796 DEBUG(dbgs() << "=> ";
2797 if (ResNode == nullptr || ResNode == Node)
2800 ResNode->dump(CurDAG);
2806 bool X86DAGToDAGISel::
2807 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
2808 std::vector<SDValue> &OutOps) {
2809 SDValue Op0, Op1, Op2, Op3, Op4;
2810 switch (ConstraintCode) {
2811 case 'o': // offsetable ??
2812 case 'v': // not offsetable ??
2813 default: return true;
2815 if (!SelectAddr(nullptr, Op, Op0, Op1, Op2, Op3, Op4))
2820 OutOps.push_back(Op0);
2821 OutOps.push_back(Op1);
2822 OutOps.push_back(Op2);
2823 OutOps.push_back(Op3);
2824 OutOps.push_back(Op4);
2828 /// createX86ISelDag - This pass converts a legalized DAG into a
2829 /// X86-specific DAG, ready for instruction scheduling.
2831 FunctionPass *llvm::createX86ISelDag(X86TargetMachine &TM,
2832 CodeGenOpt::Level OptLevel) {
2833 return new X86DAGToDAGISel(TM, OptLevel);