1 //===-- X86FrameLowering.cpp - X86 Frame Information ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of TargetFrameLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "X86FrameLowering.h"
15 #include "X86InstrBuilder.h"
16 #include "X86InstrInfo.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/ADT/SmallSet.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineModuleInfo.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/IR/DataLayout.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/MC/MCAsmInfo.h"
29 #include "llvm/MC/MCSymbol.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Target/TargetOptions.h"
32 #include "llvm/Support/Debug.h"
37 // FIXME: completely move here.
38 extern cl::opt<bool> ForceStackAlign;
40 bool X86FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
41 return !MF.getFrameInfo()->hasVarSizedObjects();
44 /// hasFP - Return true if the specified function should have a dedicated frame
45 /// pointer register. This is true if the function has variable sized allocas
46 /// or if frame pointer elimination is disabled.
47 bool X86FrameLowering::hasFP(const MachineFunction &MF) const {
48 const MachineFrameInfo *MFI = MF.getFrameInfo();
49 const MachineModuleInfo &MMI = MF.getMMI();
50 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
52 return (MF.getTarget().Options.DisableFramePointerElim(MF) ||
53 RegInfo->needsStackRealignment(MF) ||
54 MFI->hasVarSizedObjects() ||
55 MFI->isFrameAddressTaken() || MFI->hasInlineAsmWithSPAdjust() ||
56 MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
57 MMI.callsUnwindInit() || MMI.callsEHReturn() ||
58 MFI->hasStackMap() || MFI->hasPatchPoint());
61 static unsigned getSUBriOpcode(unsigned IsLP64, int64_t Imm) {
65 return X86::SUB64ri32;
73 static unsigned getADDriOpcode(unsigned IsLP64, int64_t Imm) {
77 return X86::ADD64ri32;
85 static unsigned getANDriOpcode(bool IsLP64, int64_t Imm) {
89 return X86::AND64ri32;
96 static unsigned getPUSHiOpcode(bool IsLP64, int64_t Imm) {
97 // We don't support LP64 for now.
101 return X86::PUSH32i8;
105 static unsigned getLEArOpcode(unsigned IsLP64) {
106 return IsLP64 ? X86::LEA64r : X86::LEA32r;
109 /// findDeadCallerSavedReg - Return a caller-saved register that isn't live
110 /// when it reaches the "return" instruction. We can then pop a stack object
111 /// to this register without worry about clobbering it.
112 static unsigned findDeadCallerSavedReg(MachineBasicBlock &MBB,
113 MachineBasicBlock::iterator &MBBI,
114 const TargetRegisterInfo &TRI,
116 const MachineFunction *MF = MBB.getParent();
117 const Function *F = MF->getFunction();
118 if (!F || MF->getMMI().callsEHReturn())
121 static const uint16_t CallerSavedRegs32Bit[] = {
122 X86::EAX, X86::EDX, X86::ECX, 0
125 static const uint16_t CallerSavedRegs64Bit[] = {
126 X86::RAX, X86::RDX, X86::RCX, X86::RSI, X86::RDI,
127 X86::R8, X86::R9, X86::R10, X86::R11, 0
130 unsigned Opc = MBBI->getOpcode();
137 case X86::TCRETURNdi:
138 case X86::TCRETURNri:
139 case X86::TCRETURNmi:
140 case X86::TCRETURNdi64:
141 case X86::TCRETURNri64:
142 case X86::TCRETURNmi64:
144 case X86::EH_RETURN64: {
145 SmallSet<uint16_t, 8> Uses;
146 for (unsigned i = 0, e = MBBI->getNumOperands(); i != e; ++i) {
147 MachineOperand &MO = MBBI->getOperand(i);
148 if (!MO.isReg() || MO.isDef())
150 unsigned Reg = MO.getReg();
153 for (MCRegAliasIterator AI(Reg, &TRI, true); AI.isValid(); ++AI)
157 const uint16_t *CS = Is64Bit ? CallerSavedRegs64Bit : CallerSavedRegs32Bit;
159 if (!Uses.count(*CS))
168 /// emitSPUpdate - Emit a series of instructions to increment / decrement the
169 /// stack pointer by a constant value.
171 void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
172 unsigned StackPtr, int64_t NumBytes,
173 bool Is64BitTarget, bool Is64BitStackPtr, bool UseLEA,
174 const TargetInstrInfo &TII, const TargetRegisterInfo &TRI) {
175 bool isSub = NumBytes < 0;
176 uint64_t Offset = isSub ? -NumBytes : NumBytes;
179 Opc = getLEArOpcode(Is64BitStackPtr);
182 ? getSUBriOpcode(Is64BitStackPtr, Offset)
183 : getADDriOpcode(Is64BitStackPtr, Offset);
185 uint64_t Chunk = (1LL << 31) - 1;
186 DebugLoc DL = MBB.findDebugLoc(MBBI);
189 uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset;
190 if (ThisVal == (Is64BitTarget ? 8 : 4)) {
191 // Use push / pop instead.
193 ? (unsigned)(Is64BitTarget ? X86::RAX : X86::EAX)
194 : findDeadCallerSavedReg(MBB, MBBI, TRI, Is64BitTarget);
197 ? (Is64BitTarget ? X86::PUSH64r : X86::PUSH32r)
198 : (Is64BitTarget ? X86::POP64r : X86::POP32r);
199 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc))
200 .addReg(Reg, getDefRegState(!isSub) | getUndefRegState(isSub));
202 MI->setFlag(MachineInstr::FrameSetup);
208 MachineInstr *MI = nullptr;
211 MI = addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr),
212 StackPtr, false, isSub ? -ThisVal : ThisVal);
214 MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
217 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
221 MI->setFlag(MachineInstr::FrameSetup);
227 /// mergeSPUpdatesUp - Merge two stack-manipulating instructions upper iterator.
229 void mergeSPUpdatesUp(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
230 unsigned StackPtr, uint64_t *NumBytes = nullptr) {
231 if (MBBI == MBB.begin()) return;
233 MachineBasicBlock::iterator PI = std::prev(MBBI);
234 unsigned Opc = PI->getOpcode();
235 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
236 Opc == X86::ADD32ri || Opc == X86::ADD32ri8 ||
237 Opc == X86::LEA32r || Opc == X86::LEA64_32r) &&
238 PI->getOperand(0).getReg() == StackPtr) {
240 *NumBytes += PI->getOperand(2).getImm();
242 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
243 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
244 PI->getOperand(0).getReg() == StackPtr) {
246 *NumBytes -= PI->getOperand(2).getImm();
251 /// mergeSPUpdatesDown - Merge two stack-manipulating instructions lower
254 void mergeSPUpdatesDown(MachineBasicBlock &MBB,
255 MachineBasicBlock::iterator &MBBI,
256 unsigned StackPtr, uint64_t *NumBytes = nullptr) {
257 // FIXME: THIS ISN'T RUN!!!
260 if (MBBI == MBB.end()) return;
262 MachineBasicBlock::iterator NI = std::next(MBBI);
263 if (NI == MBB.end()) return;
265 unsigned Opc = NI->getOpcode();
266 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
267 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
268 NI->getOperand(0).getReg() == StackPtr) {
270 *NumBytes -= NI->getOperand(2).getImm();
273 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
274 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
275 NI->getOperand(0).getReg() == StackPtr) {
277 *NumBytes += NI->getOperand(2).getImm();
283 /// mergeSPUpdates - Checks the instruction before/after the passed
284 /// instruction. If it is an ADD/SUB/LEA instruction it is deleted argument and
285 /// the stack adjustment is returned as a positive value for ADD/LEA and a
286 /// negative for SUB.
287 static int mergeSPUpdates(MachineBasicBlock &MBB,
288 MachineBasicBlock::iterator &MBBI, unsigned StackPtr,
289 bool doMergeWithPrevious) {
290 if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
291 (!doMergeWithPrevious && MBBI == MBB.end()))
294 MachineBasicBlock::iterator PI = doMergeWithPrevious ? std::prev(MBBI) : MBBI;
295 MachineBasicBlock::iterator NI = doMergeWithPrevious ? nullptr
297 unsigned Opc = PI->getOpcode();
300 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
301 Opc == X86::ADD32ri || Opc == X86::ADD32ri8 ||
302 Opc == X86::LEA32r || Opc == X86::LEA64_32r) &&
303 PI->getOperand(0).getReg() == StackPtr){
304 Offset += PI->getOperand(2).getImm();
306 if (!doMergeWithPrevious) MBBI = NI;
307 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
308 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
309 PI->getOperand(0).getReg() == StackPtr) {
310 Offset -= PI->getOperand(2).getImm();
312 if (!doMergeWithPrevious) MBBI = NI;
318 static bool isEAXLiveIn(MachineFunction &MF) {
319 for (MachineRegisterInfo::livein_iterator II = MF.getRegInfo().livein_begin(),
320 EE = MF.getRegInfo().livein_end(); II != EE; ++II) {
321 unsigned Reg = II->first;
323 if (Reg == X86::EAX || Reg == X86::AX ||
324 Reg == X86::AH || Reg == X86::AL)
332 X86FrameLowering::emitCalleeSavedFrameMoves(MachineBasicBlock &MBB,
333 MachineBasicBlock::iterator MBBI,
335 MachineFunction &MF = *MBB.getParent();
336 MachineFrameInfo *MFI = MF.getFrameInfo();
337 MachineModuleInfo &MMI = MF.getMMI();
338 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
339 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
341 // Add callee saved registers to move list.
342 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
343 if (CSI.empty()) return;
345 // Calculate offsets.
346 for (std::vector<CalleeSavedInfo>::const_iterator
347 I = CSI.begin(), E = CSI.end(); I != E; ++I) {
348 int64_t Offset = MFI->getObjectOffset(I->getFrameIdx());
349 unsigned Reg = I->getReg();
351 unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true);
353 MMI.addFrameInst(MCCFIInstruction::createOffset(nullptr, DwarfReg,
355 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
356 .addCFIIndex(CFIIndex);
360 /// usesTheStack - This function checks if any of the users of EFLAGS
361 /// copies the EFLAGS. We know that the code that lowers COPY of EFLAGS has
362 /// to use the stack, and if we don't adjust the stack we clobber the first
364 /// See X86InstrInfo::copyPhysReg.
365 static bool usesTheStack(const MachineFunction &MF) {
366 const MachineRegisterInfo &MRI = MF.getRegInfo();
368 for (MachineRegisterInfo::reg_instr_iterator
369 ri = MRI.reg_instr_begin(X86::EFLAGS), re = MRI.reg_instr_end();
377 void X86FrameLowering::getStackProbeFunction(const X86Subtarget &STI,
379 const char *&Symbol) {
380 CallOp = STI.is64Bit() ? X86::W64ALLOCA : X86::CALLpcrel32;
383 if (STI.isTargetCygMing()) {
384 Symbol = "___chkstk_ms";
388 } else if (STI.isTargetCygMing())
394 /// emitPrologue - Push callee-saved registers onto the stack, which
395 /// automatically adjust the stack pointer. Adjust the stack pointer to allocate
396 /// space for local variables. Also emit labels used by the exception handler to
397 /// generate the exception handling frames.
400 Here's a gist of what gets emitted:
402 ; Establish frame pointer, if needed
405 .cfi_def_cfa_offset 16
406 .cfi_offset %rbp, -16
409 .cfi_def_cfa_register %rbp
411 ; Spill general-purpose registers
412 [for all callee-saved GPRs]
415 .cfi_def_cfa_offset (offset from RETADDR)
418 ; If the required stack alignment > default stack alignment
419 ; rsp needs to be re-aligned. This creates a "re-alignment gap"
420 ; of unknown size in the stack frame.
421 [if stack needs re-alignment]
424 ; Allocate space for locals
425 [if target is Windows and allocated space > 4096 bytes]
426 ; Windows needs special care for allocations larger
429 call ___chkstk_ms/___chkstk
435 .seh_stackalloc (size of XMM spill slots)
436 .seh_setframe %rbp, SEHFrameOffset ; = size of all spill slots
441 ; Note, that while only Windows 64 ABI specifies XMMs as callee-preserved,
442 ; they may get spilled on any platform, if the current function
443 ; calls @llvm.eh.unwind.init
445 [for all callee-saved XMM registers]
446 movaps %<xmm reg>, -MMM(%rbp)
447 [for all callee-saved XMM registers]
448 .seh_savexmm %<xmm reg>, (-MMM + SEHFrameOffset)
449 ; i.e. the offset relative to (%rbp - SEHFrameOffset)
451 [for all callee-saved XMM registers]
452 movaps %<xmm reg>, KKK(%rsp)
453 [for all callee-saved XMM registers]
454 .seh_savexmm %<xmm reg>, KKK
458 [if needs base pointer]
460 [if needs to restore base pointer]
465 [for all callee-saved registers]
466 .cfi_offset %<reg>, (offset from %rbp)
468 .cfi_def_cfa_offset (offset from RETADDR)
469 [for all callee-saved registers]
470 .cfi_offset %<reg>, (offset from %rsp)
473 - .seh directives are emitted only for Windows 64 ABI
474 - .cfi directives are emitted for all other ABIs
475 - for 32-bit code, substitute %e?? registers for %r??
478 void X86FrameLowering::emitPrologue(MachineFunction &MF) const {
479 MachineBasicBlock &MBB = MF.front(); // Prologue goes in entry BB.
480 MachineBasicBlock::iterator MBBI = MBB.begin();
481 MachineFrameInfo *MFI = MF.getFrameInfo();
482 const Function *Fn = MF.getFunction();
483 const X86RegisterInfo *RegInfo =
484 static_cast<const X86RegisterInfo *>(MF.getSubtarget().getRegisterInfo());
485 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
486 MachineModuleInfo &MMI = MF.getMMI();
487 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
488 uint64_t MaxAlign = MFI->getMaxAlignment(); // Desired stack alignment.
489 uint64_t StackSize = MFI->getStackSize(); // Number of bytes to allocate.
490 bool HasFP = hasFP(MF);
491 const X86Subtarget &STI = MF.getTarget().getSubtarget<X86Subtarget>();
492 bool Is64Bit = STI.is64Bit();
493 // standard x86_64 and NaCl use 64-bit frame/stack pointers, x32 - 32-bit.
494 const bool Uses64BitFramePtr = STI.isTarget64BitLP64() || STI.isTargetNaCl64();
495 bool IsWin64 = STI.isTargetWin64();
496 // Not necessarily synonymous with IsWin64.
497 bool IsWinEH = MF.getTarget().getMCAsmInfo()->getExceptionHandlingType() ==
498 ExceptionHandling::ItaniumWinEH;
499 bool NeedsWinEH = IsWinEH && Fn->needsUnwindTableEntry();
501 !IsWinEH && (MMI.hasDebugInfo() || Fn->needsUnwindTableEntry());
502 bool UseLEA = STI.useLeaForSP();
503 unsigned StackAlign = getStackAlignment();
504 unsigned SlotSize = RegInfo->getSlotSize();
505 unsigned FramePtr = RegInfo->getFrameRegister(MF);
506 const unsigned MachineFramePtr = STI.isTarget64BitILP32() ?
507 getX86SubSuperRegister(FramePtr, MVT::i64, false) : FramePtr;
508 unsigned StackPtr = RegInfo->getStackRegister();
509 unsigned BasePtr = RegInfo->getBaseRegister();
512 // If we're forcing a stack realignment we can't rely on just the frame
513 // info, we need to know the ABI stack alignment as well in case we
514 // have a call out. Otherwise just make sure we have some alignment - we'll
515 // go with the minimum SlotSize.
516 if (ForceStackAlign) {
518 MaxAlign = (StackAlign > MaxAlign) ? StackAlign : MaxAlign;
519 else if (MaxAlign < SlotSize)
523 // Add RETADDR move area to callee saved frame size.
524 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
525 if (TailCallReturnAddrDelta < 0)
526 X86FI->setCalleeSavedFrameSize(
527 X86FI->getCalleeSavedFrameSize() - TailCallReturnAddrDelta);
529 bool UseStackProbe = (STI.isOSWindows() && !STI.isTargetMachO());
531 // If this is x86-64 and the Red Zone is not disabled, if we are a leaf
532 // function, and use up to 128 bytes of stack space, don't have a frame
533 // pointer, calls, or dynamic alloca then we do not need to adjust the
534 // stack pointer (we fit in the Red Zone). We also check that we don't
535 // push and pop from the stack.
536 if (Is64Bit && !Fn->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
537 Attribute::NoRedZone) &&
538 !RegInfo->needsStackRealignment(MF) &&
539 !MFI->hasVarSizedObjects() && // No dynamic alloca.
540 !MFI->adjustsStack() && // No calls.
541 !IsWin64 && // Win64 has no Red Zone
542 !usesTheStack(MF) && // Don't push and pop.
543 !MF.shouldSplitStack()) { // Regular stack
544 uint64_t MinSize = X86FI->getCalleeSavedFrameSize();
545 if (HasFP) MinSize += SlotSize;
546 StackSize = std::max(MinSize, StackSize > 128 ? StackSize - 128 : 0);
547 MFI->setStackSize(StackSize);
550 // Insert stack pointer adjustment for later moving of return addr. Only
551 // applies to tail call optimized functions where the callee argument stack
552 // size is bigger than the callers.
553 if (TailCallReturnAddrDelta < 0) {
555 BuildMI(MBB, MBBI, DL,
556 TII.get(getSUBriOpcode(Uses64BitFramePtr, -TailCallReturnAddrDelta)),
559 .addImm(-TailCallReturnAddrDelta)
560 .setMIFlag(MachineInstr::FrameSetup);
561 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
564 // Mapping for machine moves:
566 // DST: VirtualFP AND
567 // SRC: VirtualFP => DW_CFA_def_cfa_offset
568 // ELSE => DW_CFA_def_cfa
570 // SRC: VirtualFP AND
571 // DST: Register => DW_CFA_def_cfa_register
574 // OFFSET < 0 => DW_CFA_offset_extended_sf
575 // REG < 64 => DW_CFA_offset + Reg
576 // ELSE => DW_CFA_offset_extended
578 uint64_t NumBytes = 0;
579 int stackGrowth = -SlotSize;
582 // Calculate required stack adjustment.
583 uint64_t FrameSize = StackSize - SlotSize;
584 // If required, include space for extra hidden slot for stashing base pointer.
585 if (X86FI->getRestoreBasePointer())
586 FrameSize += SlotSize;
587 if (RegInfo->needsStackRealignment(MF)) {
588 // Callee-saved registers are pushed on stack before the stack
590 FrameSize -= X86FI->getCalleeSavedFrameSize();
591 NumBytes = (FrameSize + MaxAlign - 1) / MaxAlign * MaxAlign;
593 NumBytes = FrameSize - X86FI->getCalleeSavedFrameSize();
596 // Get the offset of the stack slot for the EBP register, which is
597 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
598 // Update the frame offset adjustment.
599 MFI->setOffsetAdjustment(-NumBytes);
601 // Save EBP/RBP into the appropriate stack slot.
602 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
603 .addReg(MachineFramePtr, RegState::Kill)
604 .setMIFlag(MachineInstr::FrameSetup);
607 // Mark the place where EBP/RBP was saved.
608 // Define the current CFA rule to use the provided offset.
610 unsigned CFIIndex = MMI.addFrameInst(
611 MCCFIInstruction::createDefCfaOffset(nullptr, 2 * stackGrowth));
612 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
613 .addCFIIndex(CFIIndex);
615 // Change the rule for the FramePtr to be an "offset" rule.
616 unsigned DwarfFramePtr = RegInfo->getDwarfRegNum(MachineFramePtr, true);
617 CFIIndex = MMI.addFrameInst(
618 MCCFIInstruction::createOffset(nullptr,
619 DwarfFramePtr, 2 * stackGrowth));
620 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
621 .addCFIIndex(CFIIndex);
625 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_PushReg))
627 .setMIFlag(MachineInstr::FrameSetup);
630 // Update EBP with the new base value.
631 BuildMI(MBB, MBBI, DL,
632 TII.get(Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr), FramePtr)
634 .setMIFlag(MachineInstr::FrameSetup);
637 // Mark effective beginning of when frame pointer becomes valid.
638 // Define the current CFA to use the EBP/RBP register.
639 unsigned DwarfFramePtr = RegInfo->getDwarfRegNum(MachineFramePtr, true);
640 unsigned CFIIndex = MMI.addFrameInst(
641 MCCFIInstruction::createDefCfaRegister(nullptr, DwarfFramePtr));
642 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
643 .addCFIIndex(CFIIndex);
646 // Mark the FramePtr as live-in in every block.
647 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
648 I->addLiveIn(MachineFramePtr);
650 NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
653 // Skip the callee-saved push instructions.
654 bool PushedRegs = false;
655 int StackOffset = 2 * stackGrowth;
657 while (MBBI != MBB.end() &&
658 (MBBI->getOpcode() == X86::PUSH32r ||
659 MBBI->getOpcode() == X86::PUSH64r)) {
661 unsigned Reg = MBBI->getOperand(0).getReg();
664 if (!HasFP && NeedsDwarfCFI) {
665 // Mark callee-saved push instruction.
666 // Define the current CFA rule to use the provided offset.
668 unsigned CFIIndex = MMI.addFrameInst(
669 MCCFIInstruction::createDefCfaOffset(nullptr, StackOffset));
670 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
671 .addCFIIndex(CFIIndex);
672 StackOffset += stackGrowth;
676 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_PushReg)).addImm(Reg).setMIFlag(
677 MachineInstr::FrameSetup);
681 // Realign stack after we pushed callee-saved registers (so that we'll be
682 // able to calculate their offsets from the frame pointer).
683 if (RegInfo->needsStackRealignment(MF)) {
684 assert(HasFP && "There should be a frame pointer if stack is realigned.");
685 uint64_t Val = -MaxAlign;
687 BuildMI(MBB, MBBI, DL,
688 TII.get(getANDriOpcode(Uses64BitFramePtr, Val)), StackPtr)
691 .setMIFlag(MachineInstr::FrameSetup);
693 // The EFLAGS implicit def is dead.
694 MI->getOperand(3).setIsDead();
697 // If there is an SUB32ri of ESP immediately before this instruction, merge
698 // the two. This can be the case when tail call elimination is enabled and
699 // the callee has more arguments then the caller.
700 NumBytes -= mergeSPUpdates(MBB, MBBI, StackPtr, true);
702 // If there is an ADD32ri or SUB32ri of ESP immediately after this
703 // instruction, merge the two instructions.
704 mergeSPUpdatesDown(MBB, MBBI, StackPtr, &NumBytes);
706 // Adjust stack pointer: ESP -= numbytes.
708 static const size_t PageSize = 4096;
710 // Windows and cygwin/mingw require a prologue helper routine when allocating
711 // more than 4K bytes on the stack. Windows uses __chkstk and cygwin/mingw
712 // uses __alloca. __alloca and the 32-bit version of __chkstk will probe the
713 // stack and adjust the stack pointer in one go. The 64-bit version of
714 // __chkstk is only responsible for probing the stack. The 64-bit prologue is
715 // responsible for adjusting the stack pointer. Touching the stack at 4K
716 // increments is necessary to ensure that the guard pages used by the OS
717 // virtual memory manager are allocated in correct sequence.
718 if (NumBytes >= PageSize && UseStackProbe) {
719 const char *StackProbeSymbol;
722 getStackProbeFunction(STI, CallOp, StackProbeSymbol);
724 // Check whether EAX is livein for this function.
725 bool isEAXAlive = isEAXLiveIn(MF);
728 // Sanity check that EAX is not livein for this function.
729 // It should not be, so throw an assert.
730 assert(!Is64Bit && "EAX is livein in x64 case!");
733 BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH32r))
734 .addReg(X86::EAX, RegState::Kill)
735 .setMIFlag(MachineInstr::FrameSetup);
739 // Handle the 64-bit Windows ABI case where we need to call __chkstk.
740 // Function prologue is responsible for adjusting the stack pointer.
741 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri), X86::RAX)
743 .setMIFlag(MachineInstr::FrameSetup);
745 // Allocate NumBytes-4 bytes on stack in case of isEAXAlive.
746 // We'll also use 4 already allocated bytes for EAX.
747 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
748 .addImm(isEAXAlive ? NumBytes - 4 : NumBytes)
749 .setMIFlag(MachineInstr::FrameSetup);
752 BuildMI(MBB, MBBI, DL,
754 .addExternalSymbol(StackProbeSymbol)
755 .addReg(StackPtr, RegState::Define | RegState::Implicit)
756 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit)
757 .setMIFlag(MachineInstr::FrameSetup);
760 // MSVC x64's __chkstk and cygwin/mingw's ___chkstk_ms do not adjust %rsp
761 // themself. It also does not clobber %rax so we can reuse it when
763 BuildMI(MBB, MBBI, DL, TII.get(X86::SUB64rr), StackPtr)
766 .setMIFlag(MachineInstr::FrameSetup);
770 MachineInstr *MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV32rm),
772 StackPtr, false, NumBytes - 4);
773 MI->setFlag(MachineInstr::FrameSetup);
774 MBB.insert(MBBI, MI);
776 } else if (NumBytes) {
777 emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, Uses64BitFramePtr,
778 UseLEA, TII, *RegInfo);
781 int SEHFrameOffset = 0;
784 // We need to set frame base offset low enough such that all saved
785 // register offsets would be positive relative to it, but we can't
786 // just use NumBytes, because .seh_setframe offset must be <=240.
787 // So we pretend to have only allocated enough space to spill the
788 // non-volatile registers.
789 // We don't care about the rest of stack allocation, because unwinder
790 // will restore SP to (BP - SEHFrameOffset)
791 for (const CalleeSavedInfo &Info : MFI->getCalleeSavedInfo()) {
792 int offset = MFI->getObjectOffset(Info.getFrameIdx());
793 SEHFrameOffset = std::max(SEHFrameOffset, std::abs(offset));
795 SEHFrameOffset += SEHFrameOffset % 16; // ensure alignmant
797 // This only needs to account for XMM spill slots, GPR slots
798 // are covered by the .seh_pushreg's emitted above.
799 unsigned Size = SEHFrameOffset - X86FI->getCalleeSavedFrameSize();
801 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_StackAlloc))
803 .setMIFlag(MachineInstr::FrameSetup);
806 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_SetFrame))
808 .addImm(SEHFrameOffset)
809 .setMIFlag(MachineInstr::FrameSetup);
811 // SP will be the base register for restoring XMMs
813 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_StackAlloc))
815 .setMIFlag(MachineInstr::FrameSetup);
820 // Skip the rest of register spilling code
821 while (MBBI != MBB.end() && MBBI->getFlag(MachineInstr::FrameSetup))
824 // Emit SEH info for non-GPRs
826 for (const CalleeSavedInfo &Info : MFI->getCalleeSavedInfo()) {
827 unsigned Reg = Info.getReg();
828 if (X86::GR64RegClass.contains(Reg) || X86::GR32RegClass.contains(Reg))
830 assert(X86::FR64RegClass.contains(Reg) && "Unexpected register class");
832 int Offset = getFrameIndexOffset(MF, Info.getFrameIdx());
833 Offset += SEHFrameOffset;
835 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_SaveXMM))
838 .setMIFlag(MachineInstr::FrameSetup);
841 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_EndPrologue))
842 .setMIFlag(MachineInstr::FrameSetup);
845 // If we need a base pointer, set it up here. It's whatever the value
846 // of the stack pointer is at this point. Any variable size objects
847 // will be allocated after this, so we can still use the base pointer
848 // to reference locals.
849 if (RegInfo->hasBasePointer(MF)) {
850 // Update the base pointer with the current stack pointer.
851 unsigned Opc = Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr;
852 BuildMI(MBB, MBBI, DL, TII.get(Opc), BasePtr)
854 .setMIFlag(MachineInstr::FrameSetup);
855 if (X86FI->getRestoreBasePointer()) {
856 // Stash value of base pointer. Saving RSP instead of EBP shortens dependence chain.
857 unsigned Opm = Uses64BitFramePtr ? X86::MOV64mr : X86::MOV32mr;
858 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opm)),
859 FramePtr, true, X86FI->getRestoreBasePointerOffset())
861 .setMIFlag(MachineInstr::FrameSetup);
865 if (((!HasFP && NumBytes) || PushedRegs) && NeedsDwarfCFI) {
866 // Mark end of stack pointer adjustment.
867 if (!HasFP && NumBytes) {
868 // Define the current CFA rule to use the provided offset.
870 unsigned CFIIndex = MMI.addFrameInst(
871 MCCFIInstruction::createDefCfaOffset(nullptr,
872 -StackSize + stackGrowth));
874 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
875 .addCFIIndex(CFIIndex);
878 // Emit DWARF info specifying the offsets of the callee-saved registers.
880 emitCalleeSavedFrameMoves(MBB, MBBI, DL);
884 void X86FrameLowering::emitEpilogue(MachineFunction &MF,
885 MachineBasicBlock &MBB) const {
886 const MachineFrameInfo *MFI = MF.getFrameInfo();
887 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
888 const X86RegisterInfo *RegInfo =
889 static_cast<const X86RegisterInfo *>(MF.getSubtarget().getRegisterInfo());
890 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
891 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
892 assert(MBBI != MBB.end() && "Returning block has no instructions");
893 unsigned RetOpcode = MBBI->getOpcode();
894 DebugLoc DL = MBBI->getDebugLoc();
895 const X86Subtarget &STI = MF.getTarget().getSubtarget<X86Subtarget>();
896 bool Is64Bit = STI.is64Bit();
897 // standard x86_64 and NaCl use 64-bit frame/stack pointers, x32 - 32-bit.
898 const bool Uses64BitFramePtr = STI.isTarget64BitLP64() || STI.isTargetNaCl64();
899 const bool Is64BitILP32 = STI.isTarget64BitILP32();
900 bool UseLEA = STI.useLeaForSP();
901 unsigned StackAlign = getStackAlignment();
902 unsigned SlotSize = RegInfo->getSlotSize();
903 unsigned FramePtr = RegInfo->getFrameRegister(MF);
904 unsigned MachineFramePtr = Is64BitILP32 ?
905 getX86SubSuperRegister(FramePtr, MVT::i64, false) : FramePtr;
906 unsigned StackPtr = RegInfo->getStackRegister();
908 bool IsWinEH = MF.getTarget().getMCAsmInfo()->getExceptionHandlingType() ==
909 ExceptionHandling::ItaniumWinEH;
910 bool NeedsWinEH = IsWinEH && MF.getFunction()->needsUnwindTableEntry();
914 llvm_unreachable("Can only insert epilog into returning blocks");
919 case X86::TCRETURNdi:
920 case X86::TCRETURNri:
921 case X86::TCRETURNmi:
922 case X86::TCRETURNdi64:
923 case X86::TCRETURNri64:
924 case X86::TCRETURNmi64:
926 case X86::EH_RETURN64:
927 break; // These are ok
930 // Get the number of bytes to allocate from the FrameInfo.
931 uint64_t StackSize = MFI->getStackSize();
932 uint64_t MaxAlign = MFI->getMaxAlignment();
933 unsigned CSSize = X86FI->getCalleeSavedFrameSize();
934 uint64_t NumBytes = 0;
936 // If we're forcing a stack realignment we can't rely on just the frame
937 // info, we need to know the ABI stack alignment as well in case we
938 // have a call out. Otherwise just make sure we have some alignment - we'll
939 // go with the minimum.
940 if (ForceStackAlign) {
942 MaxAlign = (StackAlign > MaxAlign) ? StackAlign : MaxAlign;
944 MaxAlign = MaxAlign ? MaxAlign : 4;
948 // Calculate required stack adjustment.
949 uint64_t FrameSize = StackSize - SlotSize;
950 if (RegInfo->needsStackRealignment(MF)) {
951 // Callee-saved registers were pushed on stack before the stack
954 NumBytes = (FrameSize + MaxAlign - 1) / MaxAlign * MaxAlign;
956 NumBytes = FrameSize - CSSize;
960 BuildMI(MBB, MBBI, DL,
961 TII.get(Is64Bit ? X86::POP64r : X86::POP32r), MachineFramePtr);
963 NumBytes = StackSize - CSSize;
966 // Skip the callee-saved pop instructions.
967 while (MBBI != MBB.begin()) {
968 MachineBasicBlock::iterator PI = std::prev(MBBI);
969 unsigned Opc = PI->getOpcode();
971 if (Opc != X86::POP32r && Opc != X86::POP64r && Opc != X86::DBG_VALUE &&
977 MachineBasicBlock::iterator FirstCSPop = MBBI;
979 DL = MBBI->getDebugLoc();
981 // If there is an ADD32ri or SUB32ri of ESP immediately before this
982 // instruction, merge the two instructions.
983 if (NumBytes || MFI->hasVarSizedObjects())
984 mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
986 // If dynamic alloca is used, then reset esp to point to the last callee-saved
987 // slot before popping them off! Same applies for the case, when stack was
989 if (RegInfo->needsStackRealignment(MF) || MFI->hasVarSizedObjects()) {
990 if (RegInfo->needsStackRealignment(MF))
993 unsigned Opc = getLEArOpcode(Uses64BitFramePtr);
994 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr),
995 FramePtr, false, -CSSize);
998 unsigned Opc = (Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr);
999 BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
1003 } else if (NumBytes) {
1004 // Adjust stack pointer back: ESP += numbytes.
1005 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, Uses64BitFramePtr, UseLEA,
1010 // Windows unwinder will not invoke function's exception handler if IP is
1011 // either in prologue or in epilogue. This behavior causes a problem when a
1012 // call immediately precedes an epilogue, because the return address points
1013 // into the epilogue. To cope with that, we insert an epilogue marker here,
1014 // then replace it with a 'nop' if it ends up immediately after a CALL in the
1015 // final emitted code.
1017 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_Epilogue));
1019 // We're returning from function via eh_return.
1020 if (RetOpcode == X86::EH_RETURN || RetOpcode == X86::EH_RETURN64) {
1021 MBBI = MBB.getLastNonDebugInstr();
1022 MachineOperand &DestAddr = MBBI->getOperand(0);
1023 assert(DestAddr.isReg() && "Offset should be in register!");
1024 BuildMI(MBB, MBBI, DL,
1025 TII.get(Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr),
1026 StackPtr).addReg(DestAddr.getReg());
1027 } else if (RetOpcode == X86::TCRETURNri || RetOpcode == X86::TCRETURNdi ||
1028 RetOpcode == X86::TCRETURNmi ||
1029 RetOpcode == X86::TCRETURNri64 || RetOpcode == X86::TCRETURNdi64 ||
1030 RetOpcode == X86::TCRETURNmi64) {
1031 bool isMem = RetOpcode == X86::TCRETURNmi || RetOpcode == X86::TCRETURNmi64;
1032 // Tail call return: adjust the stack pointer and jump to callee.
1033 MBBI = MBB.getLastNonDebugInstr();
1034 MachineOperand &JumpTarget = MBBI->getOperand(0);
1035 MachineOperand &StackAdjust = MBBI->getOperand(isMem ? 5 : 1);
1036 assert(StackAdjust.isImm() && "Expecting immediate value.");
1038 // Adjust stack pointer.
1039 int StackAdj = StackAdjust.getImm();
1040 int MaxTCDelta = X86FI->getTCReturnAddrDelta();
1042 assert(MaxTCDelta <= 0 && "MaxTCDelta should never be positive");
1044 // Incoporate the retaddr area.
1045 Offset = StackAdj-MaxTCDelta;
1046 assert(Offset >= 0 && "Offset should never be negative");
1049 // Check for possible merge with preceding ADD instruction.
1050 Offset += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1051 emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, Uses64BitFramePtr,
1052 UseLEA, TII, *RegInfo);
1055 // Jump to label or value in register.
1056 if (RetOpcode == X86::TCRETURNdi || RetOpcode == X86::TCRETURNdi64) {
1057 MachineInstrBuilder MIB =
1058 BuildMI(MBB, MBBI, DL, TII.get((RetOpcode == X86::TCRETURNdi)
1059 ? X86::TAILJMPd : X86::TAILJMPd64));
1060 if (JumpTarget.isGlobal())
1061 MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
1062 JumpTarget.getTargetFlags());
1064 assert(JumpTarget.isSymbol());
1065 MIB.addExternalSymbol(JumpTarget.getSymbolName(),
1066 JumpTarget.getTargetFlags());
1068 } else if (RetOpcode == X86::TCRETURNmi || RetOpcode == X86::TCRETURNmi64) {
1069 MachineInstrBuilder MIB =
1070 BuildMI(MBB, MBBI, DL, TII.get((RetOpcode == X86::TCRETURNmi)
1071 ? X86::TAILJMPm : X86::TAILJMPm64));
1072 for (unsigned i = 0; i != 5; ++i)
1073 MIB.addOperand(MBBI->getOperand(i));
1074 } else if (RetOpcode == X86::TCRETURNri64) {
1075 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr64)).
1076 addReg(JumpTarget.getReg(), RegState::Kill);
1078 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr)).
1079 addReg(JumpTarget.getReg(), RegState::Kill);
1082 MachineInstr *NewMI = std::prev(MBBI);
1083 NewMI->copyImplicitOps(MF, MBBI);
1085 // Delete the pseudo instruction TCRETURN.
1087 } else if ((RetOpcode == X86::RETQ || RetOpcode == X86::RETL ||
1088 RetOpcode == X86::RETIQ || RetOpcode == X86::RETIL) &&
1089 (X86FI->getTCReturnAddrDelta() < 0)) {
1090 // Add the return addr area delta back since we are not tail calling.
1091 int delta = -1*X86FI->getTCReturnAddrDelta();
1092 MBBI = MBB.getLastNonDebugInstr();
1094 // Check for possible merge with preceding ADD instruction.
1095 delta += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1096 emitSPUpdate(MBB, MBBI, StackPtr, delta, Is64Bit, Uses64BitFramePtr, UseLEA, TII,
1101 int X86FrameLowering::getFrameIndexOffset(const MachineFunction &MF,
1103 const X86RegisterInfo *RegInfo =
1104 static_cast<const X86RegisterInfo *>(MF.getSubtarget().getRegisterInfo());
1105 const MachineFrameInfo *MFI = MF.getFrameInfo();
1106 int Offset = MFI->getObjectOffset(FI) - getOffsetOfLocalArea();
1107 uint64_t StackSize = MFI->getStackSize();
1109 if (RegInfo->hasBasePointer(MF)) {
1110 assert (hasFP(MF) && "VLAs and dynamic stack realign, but no FP?!");
1112 // Skip the saved EBP.
1113 return Offset + RegInfo->getSlotSize();
1115 assert((-(Offset + StackSize)) % MFI->getObjectAlignment(FI) == 0);
1116 return Offset + StackSize;
1118 } else if (RegInfo->needsStackRealignment(MF)) {
1120 // Skip the saved EBP.
1121 return Offset + RegInfo->getSlotSize();
1123 assert((-(Offset + StackSize)) % MFI->getObjectAlignment(FI) == 0);
1124 return Offset + StackSize;
1126 // FIXME: Support tail calls
1129 return Offset + StackSize;
1131 // Skip the saved EBP.
1132 Offset += RegInfo->getSlotSize();
1134 // Skip the RETADDR move area
1135 const X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1136 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
1137 if (TailCallReturnAddrDelta < 0)
1138 Offset -= TailCallReturnAddrDelta;
1144 int X86FrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI,
1145 unsigned &FrameReg) const {
1146 const X86RegisterInfo *RegInfo =
1147 static_cast<const X86RegisterInfo *>(MF.getSubtarget().getRegisterInfo());
1148 // We can't calculate offset from frame pointer if the stack is realigned,
1149 // so enforce usage of stack/base pointer. The base pointer is used when we
1150 // have dynamic allocas in addition to dynamic realignment.
1151 if (RegInfo->hasBasePointer(MF))
1152 FrameReg = RegInfo->getBaseRegister();
1153 else if (RegInfo->needsStackRealignment(MF))
1154 FrameReg = RegInfo->getStackRegister();
1156 FrameReg = RegInfo->getFrameRegister(MF);
1157 return getFrameIndexOffset(MF, FI);
1160 // Simplified from getFrameIndexOffset keeping only StackPointer cases
1161 int X86FrameLowering::getFrameIndexOffsetFromSP(const MachineFunction &MF, int FI) const {
1162 const MachineFrameInfo *MFI = MF.getFrameInfo();
1163 // Does not include any dynamic realign.
1164 const uint64_t StackSize = MFI->getStackSize();
1167 const X86RegisterInfo *RegInfo =
1168 static_cast<const X86RegisterInfo*>(MF.getSubtarget().getRegisterInfo());
1169 // Note: LLVM arranges the stack as:
1170 // Args > Saved RetPC (<--FP) > CSRs > dynamic alignment (<--BP)
1171 // > "Stack Slots" (<--SP)
1172 // We can always address StackSlots from RSP. We can usually (unless
1173 // needsStackRealignment) address CSRs from RSP, but sometimes need to
1174 // address them from RBP. FixedObjects can be placed anywhere in the stack
1175 // frame depending on their specific requirements (i.e. we can actually
1176 // refer to arguments to the function which are stored in the *callers*
1177 // frame). As a result, THE RESULT OF THIS CALL IS MEANINGLESS FOR CSRs
1178 // AND FixedObjects IFF needsStackRealignment or hasVarSizedObject.
1180 assert(!RegInfo->hasBasePointer(MF) && "we don't handle this case");
1182 // We don't handle tail calls, and shouldn't be seeing them
1184 int TailCallReturnAddrDelta =
1185 MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta();
1186 assert(!(TailCallReturnAddrDelta < 0) && "we don't handle this case!");
1190 // This is how the math works out:
1192 // %rsp grows (i.e. gets lower) left to right. Each box below is
1193 // one word (eight bytes). Obj0 is the stack slot we're trying to
1196 // ----------------------------------
1197 // | BP | Obj0 | Obj1 | ... | ObjN |
1198 // ----------------------------------
1202 // A is the incoming stack pointer.
1203 // (B - A) is the local area offset (-8 for x86-64) [1]
1204 // (C - A) is the Offset returned by MFI->getObjectOffset for Obj0 [2]
1206 // |(E - B)| is the StackSize (absolute value, positive). For a
1207 // stack that grown down, this works out to be (B - E). [3]
1209 // E is also the value of %rsp after stack has been set up, and we
1210 // want (C - E) -- the value we can add to %rsp to get to Obj0. Now
1211 // (C - E) == (C - A) - (B - A) + (B - E)
1212 // { Using [1], [2] and [3] above }
1213 // == getObjectOffset - LocalAreaOffset + StackSize
1216 // Get the Offset from the StackPointer
1217 int Offset = MFI->getObjectOffset(FI) - getOffsetOfLocalArea();
1219 return Offset + StackSize;
1221 // Simplified from getFrameIndexReference keeping only StackPointer cases
1222 int X86FrameLowering::getFrameIndexReferenceFromSP(const MachineFunction &MF, int FI,
1223 unsigned &FrameReg) const {
1224 const X86RegisterInfo *RegInfo =
1225 static_cast<const X86RegisterInfo*>(MF.getSubtarget().getRegisterInfo());
1227 assert(!RegInfo->hasBasePointer(MF) && "we don't handle this case");
1229 FrameReg = RegInfo->getStackRegister();
1230 return getFrameIndexOffsetFromSP(MF, FI);
1233 bool X86FrameLowering::assignCalleeSavedSpillSlots(
1234 MachineFunction &MF, const TargetRegisterInfo *TRI,
1235 std::vector<CalleeSavedInfo> &CSI) const {
1236 MachineFrameInfo *MFI = MF.getFrameInfo();
1237 const X86RegisterInfo *RegInfo =
1238 static_cast<const X86RegisterInfo *>(MF.getSubtarget().getRegisterInfo());
1239 unsigned SlotSize = RegInfo->getSlotSize();
1240 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1242 unsigned CalleeSavedFrameSize = 0;
1243 int SpillSlotOffset = getOffsetOfLocalArea() + X86FI->getTCReturnAddrDelta();
1246 // emitPrologue always spills frame register the first thing.
1247 SpillSlotOffset -= SlotSize;
1248 MFI->CreateFixedSpillStackObject(SlotSize, SpillSlotOffset);
1250 // Since emitPrologue and emitEpilogue will handle spilling and restoring of
1251 // the frame register, we can delete it from CSI list and not have to worry
1252 // about avoiding it later.
1253 unsigned FPReg = RegInfo->getFrameRegister(MF);
1254 for (unsigned i = 0; i < CSI.size(); ++i) {
1255 if (TRI->regsOverlap(CSI[i].getReg(),FPReg)) {
1256 CSI.erase(CSI.begin() + i);
1262 // Assign slots for GPRs. It increases frame size.
1263 for (unsigned i = CSI.size(); i != 0; --i) {
1264 unsigned Reg = CSI[i - 1].getReg();
1266 if (!X86::GR64RegClass.contains(Reg) && !X86::GR32RegClass.contains(Reg))
1269 SpillSlotOffset -= SlotSize;
1270 CalleeSavedFrameSize += SlotSize;
1272 int SlotIndex = MFI->CreateFixedSpillStackObject(SlotSize, SpillSlotOffset);
1273 CSI[i - 1].setFrameIdx(SlotIndex);
1276 X86FI->setCalleeSavedFrameSize(CalleeSavedFrameSize);
1278 // Assign slots for XMMs.
1279 for (unsigned i = CSI.size(); i != 0; --i) {
1280 unsigned Reg = CSI[i - 1].getReg();
1281 if (X86::GR64RegClass.contains(Reg) || X86::GR32RegClass.contains(Reg))
1284 const TargetRegisterClass *RC = RegInfo->getMinimalPhysRegClass(Reg);
1286 SpillSlotOffset -= std::abs(SpillSlotOffset) % RC->getAlignment();
1288 SpillSlotOffset -= RC->getSize();
1290 MFI->CreateFixedSpillStackObject(RC->getSize(), SpillSlotOffset);
1291 CSI[i - 1].setFrameIdx(SlotIndex);
1292 MFI->ensureMaxAlignment(RC->getAlignment());
1298 bool X86FrameLowering::spillCalleeSavedRegisters(
1299 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
1300 const std::vector<CalleeSavedInfo> &CSI,
1301 const TargetRegisterInfo *TRI) const {
1302 DebugLoc DL = MBB.findDebugLoc(MI);
1304 MachineFunction &MF = *MBB.getParent();
1305 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
1306 const X86Subtarget &STI = MF.getTarget().getSubtarget<X86Subtarget>();
1308 // Push GPRs. It increases frame size.
1309 unsigned Opc = STI.is64Bit() ? X86::PUSH64r : X86::PUSH32r;
1310 for (unsigned i = CSI.size(); i != 0; --i) {
1311 unsigned Reg = CSI[i - 1].getReg();
1313 if (!X86::GR64RegClass.contains(Reg) && !X86::GR32RegClass.contains(Reg))
1315 // Add the callee-saved register as live-in. It's killed at the spill.
1318 BuildMI(MBB, MI, DL, TII.get(Opc)).addReg(Reg, RegState::Kill)
1319 .setMIFlag(MachineInstr::FrameSetup);
1322 // Make XMM regs spilled. X86 does not have ability of push/pop XMM.
1323 // It can be done by spilling XMMs to stack frame.
1324 for (unsigned i = CSI.size(); i != 0; --i) {
1325 unsigned Reg = CSI[i-1].getReg();
1326 if (X86::GR64RegClass.contains(Reg) ||
1327 X86::GR32RegClass.contains(Reg))
1329 // Add the callee-saved register as live-in. It's killed at the spill.
1331 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1333 TII.storeRegToStackSlot(MBB, MI, Reg, true, CSI[i - 1].getFrameIdx(), RC,
1336 MI->setFlag(MachineInstr::FrameSetup);
1343 bool X86FrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
1344 MachineBasicBlock::iterator MI,
1345 const std::vector<CalleeSavedInfo> &CSI,
1346 const TargetRegisterInfo *TRI) const {
1350 DebugLoc DL = MBB.findDebugLoc(MI);
1352 MachineFunction &MF = *MBB.getParent();
1353 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
1354 const X86Subtarget &STI = MF.getTarget().getSubtarget<X86Subtarget>();
1356 // Reload XMMs from stack frame.
1357 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1358 unsigned Reg = CSI[i].getReg();
1359 if (X86::GR64RegClass.contains(Reg) ||
1360 X86::GR32RegClass.contains(Reg))
1363 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1364 TII.loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(), RC, TRI);
1368 unsigned Opc = STI.is64Bit() ? X86::POP64r : X86::POP32r;
1369 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1370 unsigned Reg = CSI[i].getReg();
1371 if (!X86::GR64RegClass.contains(Reg) &&
1372 !X86::GR32RegClass.contains(Reg))
1375 BuildMI(MBB, MI, DL, TII.get(Opc), Reg);
1381 X86FrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
1382 RegScavenger *RS) const {
1383 MachineFrameInfo *MFI = MF.getFrameInfo();
1384 const X86RegisterInfo *RegInfo =
1385 static_cast<const X86RegisterInfo *>(MF.getSubtarget().getRegisterInfo());
1386 unsigned SlotSize = RegInfo->getSlotSize();
1388 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1389 int64_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
1391 if (TailCallReturnAddrDelta < 0) {
1392 // create RETURNADDR area
1401 MFI->CreateFixedObject(-TailCallReturnAddrDelta,
1402 TailCallReturnAddrDelta - SlotSize, true);
1405 // Spill the BasePtr if it's used.
1406 if (RegInfo->hasBasePointer(MF))
1407 MF.getRegInfo().setPhysRegUsed(RegInfo->getBaseRegister());
1411 HasNestArgument(const MachineFunction *MF) {
1412 const Function *F = MF->getFunction();
1413 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
1415 if (I->hasNestAttr())
1421 /// GetScratchRegister - Get a temp register for performing work in the
1422 /// segmented stack and the Erlang/HiPE stack prologue. Depending on platform
1423 /// and the properties of the function either one or two registers will be
1424 /// needed. Set primary to true for the first register, false for the second.
1426 GetScratchRegister(bool Is64Bit, bool IsLP64, const MachineFunction &MF, bool Primary) {
1427 CallingConv::ID CallingConvention = MF.getFunction()->getCallingConv();
1430 if (CallingConvention == CallingConv::HiPE) {
1432 return Primary ? X86::R14 : X86::R13;
1434 return Primary ? X86::EBX : X86::EDI;
1439 return Primary ? X86::R11 : X86::R12;
1441 return Primary ? X86::R11D : X86::R12D;
1444 bool IsNested = HasNestArgument(&MF);
1446 if (CallingConvention == CallingConv::X86_FastCall ||
1447 CallingConvention == CallingConv::Fast) {
1449 report_fatal_error("Segmented stacks does not support fastcall with "
1450 "nested function.");
1451 return Primary ? X86::EAX : X86::ECX;
1454 return Primary ? X86::EDX : X86::EAX;
1455 return Primary ? X86::ECX : X86::EAX;
1458 // The stack limit in the TCB is set to this many bytes above the actual stack
1460 static const uint64_t kSplitStackAvailable = 256;
1463 X86FrameLowering::adjustForSegmentedStacks(MachineFunction &MF) const {
1464 MachineBasicBlock &prologueMBB = MF.front();
1465 MachineFrameInfo *MFI = MF.getFrameInfo();
1466 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
1468 const X86Subtarget &STI = MF.getTarget().getSubtarget<X86Subtarget>();
1469 bool Is64Bit = STI.is64Bit();
1470 const bool IsLP64 = STI.isTarget64BitLP64();
1471 unsigned TlsReg, TlsOffset;
1474 unsigned ScratchReg = GetScratchRegister(Is64Bit, IsLP64, MF, true);
1475 assert(!MF.getRegInfo().isLiveIn(ScratchReg) &&
1476 "Scratch register is live-in");
1478 if (MF.getFunction()->isVarArg())
1479 report_fatal_error("Segmented stacks do not support vararg functions.");
1480 if (!STI.isTargetLinux() && !STI.isTargetDarwin() &&
1481 !STI.isTargetWin32() && !STI.isTargetWin64() && !STI.isTargetFreeBSD())
1482 report_fatal_error("Segmented stacks not supported on this platform.");
1484 // Eventually StackSize will be calculated by a link-time pass; which will
1485 // also decide whether checking code needs to be injected into this particular
1487 StackSize = MFI->getStackSize();
1489 // Do not generate a prologue for functions with a stack of size zero
1493 MachineBasicBlock *allocMBB = MF.CreateMachineBasicBlock();
1494 MachineBasicBlock *checkMBB = MF.CreateMachineBasicBlock();
1495 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1496 bool IsNested = false;
1498 // We need to know if the function has a nest argument only in 64 bit mode.
1500 IsNested = HasNestArgument(&MF);
1502 // The MOV R10, RAX needs to be in a different block, since the RET we emit in
1503 // allocMBB needs to be last (terminating) instruction.
1505 for (MachineBasicBlock::livein_iterator i = prologueMBB.livein_begin(),
1506 e = prologueMBB.livein_end(); i != e; i++) {
1507 allocMBB->addLiveIn(*i);
1508 checkMBB->addLiveIn(*i);
1512 allocMBB->addLiveIn(IsLP64 ? X86::R10 : X86::R10D);
1514 MF.push_front(allocMBB);
1515 MF.push_front(checkMBB);
1517 // When the frame size is less than 256 we just compare the stack
1518 // boundary directly to the value of the stack pointer, per gcc.
1519 bool CompareStackPointer = StackSize < kSplitStackAvailable;
1521 // Read the limit off the current stacklet off the stack_guard location.
1523 if (STI.isTargetLinux()) {
1525 TlsOffset = IsLP64 ? 0x70 : 0x40;
1526 } else if (STI.isTargetDarwin()) {
1528 TlsOffset = 0x60 + 90*8; // See pthread_machdep.h. Steal TLS slot 90.
1529 } else if (STI.isTargetWin64()) {
1531 TlsOffset = 0x28; // pvArbitrary, reserved for application use
1532 } else if (STI.isTargetFreeBSD()) {
1536 report_fatal_error("Segmented stacks not supported on this platform.");
1539 if (CompareStackPointer)
1540 ScratchReg = IsLP64 ? X86::RSP : X86::ESP;
1542 BuildMI(checkMBB, DL, TII.get(IsLP64 ? X86::LEA64r : X86::LEA64_32r), ScratchReg).addReg(X86::RSP)
1543 .addImm(1).addReg(0).addImm(-StackSize).addReg(0);
1545 BuildMI(checkMBB, DL, TII.get(IsLP64 ? X86::CMP64rm : X86::CMP32rm)).addReg(ScratchReg)
1546 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg);
1548 if (STI.isTargetLinux()) {
1551 } else if (STI.isTargetDarwin()) {
1553 TlsOffset = 0x48 + 90*4;
1554 } else if (STI.isTargetWin32()) {
1556 TlsOffset = 0x14; // pvArbitrary, reserved for application use
1557 } else if (STI.isTargetFreeBSD()) {
1558 report_fatal_error("Segmented stacks not supported on FreeBSD i386.");
1560 report_fatal_error("Segmented stacks not supported on this platform.");
1563 if (CompareStackPointer)
1564 ScratchReg = X86::ESP;
1566 BuildMI(checkMBB, DL, TII.get(X86::LEA32r), ScratchReg).addReg(X86::ESP)
1567 .addImm(1).addReg(0).addImm(-StackSize).addReg(0);
1569 if (STI.isTargetLinux() || STI.isTargetWin32() || STI.isTargetWin64()) {
1570 BuildMI(checkMBB, DL, TII.get(X86::CMP32rm)).addReg(ScratchReg)
1571 .addReg(0).addImm(0).addReg(0).addImm(TlsOffset).addReg(TlsReg);
1572 } else if (STI.isTargetDarwin()) {
1574 // TlsOffset doesn't fit into a mod r/m byte so we need an extra register.
1575 unsigned ScratchReg2;
1577 if (CompareStackPointer) {
1578 // The primary scratch register is available for holding the TLS offset.
1579 ScratchReg2 = GetScratchRegister(Is64Bit, IsLP64, MF, true);
1580 SaveScratch2 = false;
1582 // Need to use a second register to hold the TLS offset
1583 ScratchReg2 = GetScratchRegister(Is64Bit, IsLP64, MF, false);
1585 // Unfortunately, with fastcc the second scratch register may hold an
1587 SaveScratch2 = MF.getRegInfo().isLiveIn(ScratchReg2);
1590 // If Scratch2 is live-in then it needs to be saved.
1591 assert((!MF.getRegInfo().isLiveIn(ScratchReg2) || SaveScratch2) &&
1592 "Scratch register is live-in and not saved");
1595 BuildMI(checkMBB, DL, TII.get(X86::PUSH32r))
1596 .addReg(ScratchReg2, RegState::Kill);
1598 BuildMI(checkMBB, DL, TII.get(X86::MOV32ri), ScratchReg2)
1600 BuildMI(checkMBB, DL, TII.get(X86::CMP32rm))
1602 .addReg(ScratchReg2).addImm(1).addReg(0)
1607 BuildMI(checkMBB, DL, TII.get(X86::POP32r), ScratchReg2);
1611 // This jump is taken if SP >= (Stacklet Limit + Stack Space required).
1612 // It jumps to normal execution of the function body.
1613 BuildMI(checkMBB, DL, TII.get(X86::JA_4)).addMBB(&prologueMBB);
1615 // On 32 bit we first push the arguments size and then the frame size. On 64
1616 // bit, we pass the stack frame size in r10 and the argument size in r11.
1618 // Functions with nested arguments use R10, so it needs to be saved across
1619 // the call to _morestack
1621 const unsigned RegAX = IsLP64 ? X86::RAX : X86::EAX;
1622 const unsigned Reg10 = IsLP64 ? X86::R10 : X86::R10D;
1623 const unsigned Reg11 = IsLP64 ? X86::R11 : X86::R11D;
1624 const unsigned MOVrr = IsLP64 ? X86::MOV64rr : X86::MOV32rr;
1625 const unsigned MOVri = IsLP64 ? X86::MOV64ri : X86::MOV32ri;
1628 BuildMI(allocMBB, DL, TII.get(MOVrr), RegAX).addReg(Reg10);
1630 BuildMI(allocMBB, DL, TII.get(MOVri), Reg10)
1632 BuildMI(allocMBB, DL, TII.get(MOVri), Reg11)
1633 .addImm(X86FI->getArgumentStackSize());
1634 MF.getRegInfo().setPhysRegUsed(Reg10);
1635 MF.getRegInfo().setPhysRegUsed(Reg11);
1637 BuildMI(allocMBB, DL, TII.get(X86::PUSHi32))
1638 .addImm(X86FI->getArgumentStackSize());
1639 BuildMI(allocMBB, DL, TII.get(X86::PUSHi32))
1643 // __morestack is in libgcc
1645 BuildMI(allocMBB, DL, TII.get(X86::CALL64pcrel32))
1646 .addExternalSymbol("__morestack");
1648 BuildMI(allocMBB, DL, TII.get(X86::CALLpcrel32))
1649 .addExternalSymbol("__morestack");
1652 BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET_RESTORE_R10));
1654 BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET));
1656 allocMBB->addSuccessor(&prologueMBB);
1658 checkMBB->addSuccessor(allocMBB);
1659 checkMBB->addSuccessor(&prologueMBB);
1666 /// Erlang programs may need a special prologue to handle the stack size they
1667 /// might need at runtime. That is because Erlang/OTP does not implement a C
1668 /// stack but uses a custom implementation of hybrid stack/heap architecture.
1669 /// (for more information see Eric Stenman's Ph.D. thesis:
1670 /// http://publications.uu.se/uu/fulltext/nbn_se_uu_diva-2688.pdf)
1673 /// temp0 = sp - MaxStack
1674 /// if( temp0 < SP_LIMIT(P) ) goto IncStack else goto OldStart
1678 /// call inc_stack # doubles the stack space
1679 /// temp0 = sp - MaxStack
1680 /// if( temp0 < SP_LIMIT(P) ) goto IncStack else goto OldStart
1681 void X86FrameLowering::adjustForHiPEPrologue(MachineFunction &MF) const {
1682 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
1683 MachineFrameInfo *MFI = MF.getFrameInfo();
1684 const unsigned SlotSize =
1685 static_cast<const X86RegisterInfo *>(MF.getSubtarget().getRegisterInfo())
1687 const X86Subtarget &STI = MF.getTarget().getSubtarget<X86Subtarget>();
1688 const bool Is64Bit = STI.is64Bit();
1689 const bool IsLP64 = STI.isTarget64BitLP64();
1691 // HiPE-specific values
1692 const unsigned HipeLeafWords = 24;
1693 const unsigned CCRegisteredArgs = Is64Bit ? 6 : 5;
1694 const unsigned Guaranteed = HipeLeafWords * SlotSize;
1695 unsigned CallerStkArity = MF.getFunction()->arg_size() > CCRegisteredArgs ?
1696 MF.getFunction()->arg_size() - CCRegisteredArgs : 0;
1697 unsigned MaxStack = MFI->getStackSize() + CallerStkArity*SlotSize + SlotSize;
1699 assert(STI.isTargetLinux() &&
1700 "HiPE prologue is only supported on Linux operating systems.");
1702 // Compute the largest caller's frame that is needed to fit the callees'
1703 // frames. This 'MaxStack' is computed from:
1705 // a) the fixed frame size, which is the space needed for all spilled temps,
1706 // b) outgoing on-stack parameter areas, and
1707 // c) the minimum stack space this function needs to make available for the
1708 // functions it calls (a tunable ABI property).
1709 if (MFI->hasCalls()) {
1710 unsigned MoreStackForCalls = 0;
1712 for (MachineFunction::iterator MBBI = MF.begin(), MBBE = MF.end();
1713 MBBI != MBBE; ++MBBI)
1714 for (MachineBasicBlock::iterator MI = MBBI->begin(), ME = MBBI->end();
1719 // Get callee operand.
1720 const MachineOperand &MO = MI->getOperand(0);
1722 // Only take account of global function calls (no closures etc.).
1726 const Function *F = dyn_cast<Function>(MO.getGlobal());
1730 // Do not update 'MaxStack' for primitive and built-in functions
1731 // (encoded with names either starting with "erlang."/"bif_" or not
1732 // having a ".", such as a simple <Module>.<Function>.<Arity>, or an
1733 // "_", such as the BIF "suspend_0") as they are executed on another
1735 if (F->getName().find("erlang.") != StringRef::npos ||
1736 F->getName().find("bif_") != StringRef::npos ||
1737 F->getName().find_first_of("._") == StringRef::npos)
1740 unsigned CalleeStkArity =
1741 F->arg_size() > CCRegisteredArgs ? F->arg_size()-CCRegisteredArgs : 0;
1742 if (HipeLeafWords - 1 > CalleeStkArity)
1743 MoreStackForCalls = std::max(MoreStackForCalls,
1744 (HipeLeafWords - 1 - CalleeStkArity) * SlotSize);
1746 MaxStack += MoreStackForCalls;
1749 // If the stack frame needed is larger than the guaranteed then runtime checks
1750 // and calls to "inc_stack_0" BIF should be inserted in the assembly prologue.
1751 if (MaxStack > Guaranteed) {
1752 MachineBasicBlock &prologueMBB = MF.front();
1753 MachineBasicBlock *stackCheckMBB = MF.CreateMachineBasicBlock();
1754 MachineBasicBlock *incStackMBB = MF.CreateMachineBasicBlock();
1756 for (MachineBasicBlock::livein_iterator I = prologueMBB.livein_begin(),
1757 E = prologueMBB.livein_end(); I != E; I++) {
1758 stackCheckMBB->addLiveIn(*I);
1759 incStackMBB->addLiveIn(*I);
1762 MF.push_front(incStackMBB);
1763 MF.push_front(stackCheckMBB);
1765 unsigned ScratchReg, SPReg, PReg, SPLimitOffset;
1766 unsigned LEAop, CMPop, CALLop;
1770 LEAop = X86::LEA64r;
1771 CMPop = X86::CMP64rm;
1772 CALLop = X86::CALL64pcrel32;
1773 SPLimitOffset = 0x90;
1777 LEAop = X86::LEA32r;
1778 CMPop = X86::CMP32rm;
1779 CALLop = X86::CALLpcrel32;
1780 SPLimitOffset = 0x4c;
1783 ScratchReg = GetScratchRegister(Is64Bit, IsLP64, MF, true);
1784 assert(!MF.getRegInfo().isLiveIn(ScratchReg) &&
1785 "HiPE prologue scratch register is live-in");
1787 // Create new MBB for StackCheck:
1788 addRegOffset(BuildMI(stackCheckMBB, DL, TII.get(LEAop), ScratchReg),
1789 SPReg, false, -MaxStack);
1790 // SPLimitOffset is in a fixed heap location (pointed by BP).
1791 addRegOffset(BuildMI(stackCheckMBB, DL, TII.get(CMPop))
1792 .addReg(ScratchReg), PReg, false, SPLimitOffset);
1793 BuildMI(stackCheckMBB, DL, TII.get(X86::JAE_4)).addMBB(&prologueMBB);
1795 // Create new MBB for IncStack:
1796 BuildMI(incStackMBB, DL, TII.get(CALLop)).
1797 addExternalSymbol("inc_stack_0");
1798 addRegOffset(BuildMI(incStackMBB, DL, TII.get(LEAop), ScratchReg),
1799 SPReg, false, -MaxStack);
1800 addRegOffset(BuildMI(incStackMBB, DL, TII.get(CMPop))
1801 .addReg(ScratchReg), PReg, false, SPLimitOffset);
1802 BuildMI(incStackMBB, DL, TII.get(X86::JLE_4)).addMBB(incStackMBB);
1804 stackCheckMBB->addSuccessor(&prologueMBB, 99);
1805 stackCheckMBB->addSuccessor(incStackMBB, 1);
1806 incStackMBB->addSuccessor(&prologueMBB, 99);
1807 incStackMBB->addSuccessor(incStackMBB, 1);
1814 bool X86FrameLowering::
1815 convertArgMovsToPushes(MachineFunction &MF, MachineBasicBlock &MBB,
1816 MachineBasicBlock::iterator I, uint64_t Amount) const {
1817 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
1818 const X86RegisterInfo &RegInfo = *static_cast<const X86RegisterInfo *>(
1819 MF.getSubtarget().getRegisterInfo());
1820 unsigned StackPtr = RegInfo.getStackRegister();
1822 // Scan the call setup sequence for the pattern we're looking for.
1823 // We only handle a simple case now - a sequence of MOV32mi or MOV32mr
1824 // instructions, that push a sequence of 32-bit values onto the stack, with
1826 std::map<int64_t, MachineBasicBlock::iterator> MovMap;
1828 int Opcode = I->getOpcode();
1829 if (Opcode != X86::MOV32mi && Opcode != X86::MOV32mr)
1832 // We only want movs of the form:
1833 // movl imm/r32, k(%ecx)
1834 // If we run into something else, bail
1835 // Note that AddrBaseReg may, counterintuitively, not be a register...
1836 if (!I->getOperand(X86::AddrBaseReg).isReg() ||
1837 (I->getOperand(X86::AddrBaseReg).getReg() != StackPtr) ||
1838 !I->getOperand(X86::AddrScaleAmt).isImm() ||
1839 (I->getOperand(X86::AddrScaleAmt).getImm() != 1) ||
1840 (I->getOperand(X86::AddrIndexReg).getReg() != X86::NoRegister) ||
1841 (I->getOperand(X86::AddrSegmentReg).getReg() != X86::NoRegister) ||
1842 !I->getOperand(X86::AddrDisp).isImm())
1845 int64_t StackDisp = I->getOperand(X86::AddrDisp).getImm();
1847 // We don't want to consider the unaligned case.
1851 // If the same stack slot is being filled twice, something's fishy.
1852 if (!MovMap.insert(std::pair<int64_t, MachineInstr*>(StackDisp, I)).second)
1856 } while (I != MBB.end());
1858 // We now expect the end of the sequence - a call and a stack adjust.
1863 MachineBasicBlock::iterator Call = I;
1864 if ((++I)->getOpcode() != TII.getCallFrameDestroyOpcode())
1867 // Now, go through the map, and see that we don't have any gaps,
1868 // but only a series of 32-bit MOVs.
1869 // Since std::map provides ordered iteration, the original order
1870 // of the MOVs doesn't matter.
1871 int64_t ExpectedDist = 0;
1872 for (auto MMI = MovMap.begin(), MME = MovMap.end(); MMI != MME;
1873 ++MMI, ExpectedDist += 4)
1874 if (MMI->first != ExpectedDist)
1877 // Ok, everything looks fine. Do the transformation.
1878 DebugLoc DL = I->getDebugLoc();
1880 // It's possible the original stack adjustment amount was larger than
1881 // that done by the pushes. If so, we still need a SUB.
1882 Amount -= ExpectedDist;
1884 MachineInstr* Sub = BuildMI(MBB, Call, DL,
1885 TII.get(getSUBriOpcode(false, Amount)), StackPtr)
1886 .addReg(StackPtr).addImm(Amount);
1887 Sub->getOperand(3).setIsDead();
1890 // Now, iterate through the map in reverse order, and replace the movs
1891 // with pushes. MOVmi/MOVmr doesn't have any defs, so need to replace uses.
1892 for (auto MMI = MovMap.rbegin(), MME = MovMap.rend(); MMI != MME; ++MMI) {
1893 MachineBasicBlock::iterator MOV = MMI->second;
1894 MachineOperand PushOp = MOV->getOperand(X86::AddrNumOperands);
1895 if (MOV->getOpcode() == X86::MOV32mi) {
1896 int64_t Val = PushOp.getImm();
1897 BuildMI(MBB, Call, DL, TII.get(getPUSHiOpcode(false, Val)))
1900 BuildMI(MBB, Call, DL, TII.get(X86::PUSH32r))
1901 .addReg(PushOp.getReg());
1909 void X86FrameLowering::
1910 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
1911 MachineBasicBlock::iterator I) const {
1912 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
1913 const X86RegisterInfo &RegInfo = *static_cast<const X86RegisterInfo *>(
1914 MF.getSubtarget().getRegisterInfo());
1915 unsigned StackPtr = RegInfo.getStackRegister();
1916 bool reserveCallFrame = hasReservedCallFrame(MF);
1917 int Opcode = I->getOpcode();
1918 bool isDestroy = Opcode == TII.getCallFrameDestroyOpcode();
1919 const X86Subtarget &STI = MF.getTarget().getSubtarget<X86Subtarget>();
1920 bool IsLP64 = STI.isTarget64BitLP64();
1921 DebugLoc DL = I->getDebugLoc();
1922 uint64_t Amount = !reserveCallFrame ? I->getOperand(0).getImm() : 0;
1923 uint64_t CalleeAmt = isDestroy ? I->getOperand(1).getImm() : 0;
1926 if (!reserveCallFrame) {
1927 // If the stack pointer can be changed after prologue, turn the
1928 // adjcallstackup instruction into a 'sub ESP, <amt>' and the
1929 // adjcallstackdown instruction into 'add ESP, <amt>'
1933 // We need to keep the stack aligned properly. To do this, we round the
1934 // amount of space needed for the outgoing arguments up to the next
1935 // alignment boundary.
1936 unsigned StackAlign = MF.getTarget()
1938 ->getFrameLowering()
1939 ->getStackAlignment();
1940 Amount = (Amount + StackAlign - 1) / StackAlign * StackAlign;
1942 MachineInstr *New = nullptr;
1943 if (Opcode == TII.getCallFrameSetupOpcode()) {
1944 // Try to convert movs to the stack into pushes.
1945 // We currently only look for a pattern that appears in 32-bit
1946 // calling conventions.
1947 if (!IsLP64 && convertArgMovsToPushes(MF, MBB, I, Amount))
1950 New = BuildMI(MF, DL, TII.get(getSUBriOpcode(IsLP64, Amount)),
1955 assert(Opcode == TII.getCallFrameDestroyOpcode());
1957 // Factor out the amount the callee already popped.
1958 Amount -= CalleeAmt;
1961 unsigned Opc = getADDriOpcode(IsLP64, Amount);
1962 New = BuildMI(MF, DL, TII.get(Opc), StackPtr)
1963 .addReg(StackPtr).addImm(Amount);
1968 // The EFLAGS implicit def is dead.
1969 New->getOperand(3).setIsDead();
1971 // Replace the pseudo instruction with a new instruction.
1978 if (Opcode == TII.getCallFrameDestroyOpcode() && CalleeAmt) {
1979 // If we are performing frame pointer elimination and if the callee pops
1980 // something off the stack pointer, add it back. We do this until we have
1981 // more advanced stack pointer tracking ability.
1982 unsigned Opc = getSUBriOpcode(IsLP64, CalleeAmt);
1983 MachineInstr *New = BuildMI(MF, DL, TII.get(Opc), StackPtr)
1984 .addReg(StackPtr).addImm(CalleeAmt);
1986 // The EFLAGS implicit def is dead.
1987 New->getOperand(3).setIsDead();
1989 // We are not tracking the stack pointer adjustment by the callee, so make
1990 // sure we restore the stack pointer immediately after the call, there may
1991 // be spill code inserted between the CALL and ADJCALLSTACKUP instructions.
1992 MachineBasicBlock::iterator B = MBB.begin();
1993 while (I != B && !std::prev(I)->isCall())