1 //===-- X86FrameLowering.cpp - X86 Frame Information ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of TargetFrameLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "X86FrameLowering.h"
15 #include "X86InstrBuilder.h"
16 #include "X86InstrInfo.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/ADT/SmallSet.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineModuleInfo.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/WinEHFuncInfo.h"
27 #include "llvm/IR/DataLayout.h"
28 #include "llvm/IR/Function.h"
29 #include "llvm/MC/MCAsmInfo.h"
30 #include "llvm/MC/MCSymbol.h"
31 #include "llvm/Target/TargetOptions.h"
32 #include "llvm/Support/Debug.h"
37 X86FrameLowering::X86FrameLowering(const X86Subtarget &STI,
38 unsigned StackAlignOverride)
39 : TargetFrameLowering(StackGrowsDown, StackAlignOverride,
40 STI.is64Bit() ? -8 : -4),
41 STI(STI), TII(*STI.getInstrInfo()), TRI(STI.getRegisterInfo()) {
42 // Cache a bunch of frame-related predicates for this subtarget.
43 SlotSize = TRI->getSlotSize();
44 Is64Bit = STI.is64Bit();
45 IsLP64 = STI.isTarget64BitLP64();
46 // standard x86_64 and NaCl use 64-bit frame/stack pointers, x32 - 32-bit.
47 Uses64BitFramePtr = STI.isTarget64BitLP64() || STI.isTargetNaCl64();
48 StackPtr = TRI->getStackRegister();
51 bool X86FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
52 return !MF.getFrameInfo()->hasVarSizedObjects() &&
53 !MF.getInfo<X86MachineFunctionInfo>()->getHasPushSequences();
56 /// canSimplifyCallFramePseudos - If there is a reserved call frame, the
57 /// call frame pseudos can be simplified. Having a FP, as in the default
58 /// implementation, is not sufficient here since we can't always use it.
59 /// Use a more nuanced condition.
61 X86FrameLowering::canSimplifyCallFramePseudos(const MachineFunction &MF) const {
62 return hasReservedCallFrame(MF) ||
63 (hasFP(MF) && !TRI->needsStackRealignment(MF)) ||
64 TRI->hasBasePointer(MF);
67 // needsFrameIndexResolution - Do we need to perform FI resolution for
68 // this function. Normally, this is required only when the function
69 // has any stack objects. However, FI resolution actually has another job,
70 // not apparent from the title - it resolves callframesetup/destroy
71 // that were not simplified earlier.
72 // So, this is required for x86 functions that have push sequences even
73 // when there are no stack objects.
75 X86FrameLowering::needsFrameIndexResolution(const MachineFunction &MF) const {
76 return MF.getFrameInfo()->hasStackObjects() ||
77 MF.getInfo<X86MachineFunctionInfo>()->getHasPushSequences();
80 /// hasFP - Return true if the specified function should have a dedicated frame
81 /// pointer register. This is true if the function has variable sized allocas
82 /// or if frame pointer elimination is disabled.
83 bool X86FrameLowering::hasFP(const MachineFunction &MF) const {
84 const MachineFrameInfo *MFI = MF.getFrameInfo();
85 const MachineModuleInfo &MMI = MF.getMMI();
87 return (MF.getTarget().Options.DisableFramePointerElim(MF) ||
88 TRI->needsStackRealignment(MF) ||
89 MFI->hasVarSizedObjects() ||
90 MFI->isFrameAddressTaken() || MFI->hasOpaqueSPAdjustment() ||
91 MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
92 MMI.callsUnwindInit() || MMI.hasEHFunclets() || MMI.callsEHReturn() ||
93 MFI->hasStackMap() || MFI->hasPatchPoint());
96 static unsigned getSUBriOpcode(unsigned IsLP64, int64_t Imm) {
100 return X86::SUB64ri32;
103 return X86::SUB32ri8;
108 static unsigned getADDriOpcode(unsigned IsLP64, int64_t Imm) {
111 return X86::ADD64ri8;
112 return X86::ADD64ri32;
115 return X86::ADD32ri8;
120 static unsigned getSUBrrOpcode(unsigned isLP64) {
121 return isLP64 ? X86::SUB64rr : X86::SUB32rr;
124 static unsigned getADDrrOpcode(unsigned isLP64) {
125 return isLP64 ? X86::ADD64rr : X86::ADD32rr;
128 static unsigned getANDriOpcode(bool IsLP64, int64_t Imm) {
131 return X86::AND64ri8;
132 return X86::AND64ri32;
135 return X86::AND32ri8;
139 static unsigned getLEArOpcode(unsigned IsLP64) {
140 return IsLP64 ? X86::LEA64r : X86::LEA32r;
143 /// findDeadCallerSavedReg - Return a caller-saved register that isn't live
144 /// when it reaches the "return" instruction. We can then pop a stack object
145 /// to this register without worry about clobbering it.
146 static unsigned findDeadCallerSavedReg(MachineBasicBlock &MBB,
147 MachineBasicBlock::iterator &MBBI,
148 const TargetRegisterInfo *TRI,
150 const MachineFunction *MF = MBB.getParent();
151 const Function *F = MF->getFunction();
152 if (!F || MF->getMMI().callsEHReturn())
155 static const uint16_t CallerSavedRegs32Bit[] = {
156 X86::EAX, X86::EDX, X86::ECX, 0
159 static const uint16_t CallerSavedRegs64Bit[] = {
160 X86::RAX, X86::RDX, X86::RCX, X86::RSI, X86::RDI,
161 X86::R8, X86::R9, X86::R10, X86::R11, 0
164 unsigned Opc = MBBI->getOpcode();
171 case X86::TCRETURNdi:
172 case X86::TCRETURNri:
173 case X86::TCRETURNmi:
174 case X86::TCRETURNdi64:
175 case X86::TCRETURNri64:
176 case X86::TCRETURNmi64:
178 case X86::EH_RETURN64: {
179 SmallSet<uint16_t, 8> Uses;
180 for (unsigned i = 0, e = MBBI->getNumOperands(); i != e; ++i) {
181 MachineOperand &MO = MBBI->getOperand(i);
182 if (!MO.isReg() || MO.isDef())
184 unsigned Reg = MO.getReg();
187 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
191 const uint16_t *CS = Is64Bit ? CallerSavedRegs64Bit : CallerSavedRegs32Bit;
193 if (!Uses.count(*CS))
201 static bool isEAXLiveIn(MachineFunction &MF) {
202 for (MachineRegisterInfo::livein_iterator II = MF.getRegInfo().livein_begin(),
203 EE = MF.getRegInfo().livein_end(); II != EE; ++II) {
204 unsigned Reg = II->first;
206 if (Reg == X86::RAX || Reg == X86::EAX || Reg == X86::AX ||
207 Reg == X86::AH || Reg == X86::AL)
214 /// Check whether or not the terminators of \p MBB needs to read EFLAGS.
215 static bool terminatorsNeedFlagsAsInput(const MachineBasicBlock &MBB) {
216 for (const MachineInstr &MI : MBB.terminators()) {
217 bool BreakNext = false;
218 for (const MachineOperand &MO : MI.operands()) {
221 unsigned Reg = MO.getReg();
222 if (Reg != X86::EFLAGS)
225 // This terminator needs an eflag that is not defined
226 // by a previous terminator.
237 /// emitSPUpdate - Emit a series of instructions to increment / decrement the
238 /// stack pointer by a constant value.
239 void X86FrameLowering::emitSPUpdate(MachineBasicBlock &MBB,
240 MachineBasicBlock::iterator &MBBI,
241 int64_t NumBytes, bool InEpilogue) const {
242 bool isSub = NumBytes < 0;
243 uint64_t Offset = isSub ? -NumBytes : NumBytes;
245 uint64_t Chunk = (1LL << 31) - 1;
246 DebugLoc DL = MBB.findDebugLoc(MBBI);
249 if (Offset > Chunk) {
250 // Rather than emit a long series of instructions for large offsets,
251 // load the offset into a register and do one sub/add
254 if (isSub && !isEAXLiveIn(*MBB.getParent()))
255 Reg = (unsigned)(Is64Bit ? X86::RAX : X86::EAX);
257 Reg = findDeadCallerSavedReg(MBB, MBBI, TRI, Is64Bit);
260 unsigned Opc = Is64Bit ? X86::MOV64ri : X86::MOV32ri;
261 BuildMI(MBB, MBBI, DL, TII.get(Opc), Reg)
264 ? getSUBrrOpcode(Is64Bit)
265 : getADDrrOpcode(Is64Bit);
266 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
269 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
275 uint64_t ThisVal = std::min(Offset, Chunk);
276 if (ThisVal == (Is64Bit ? 8 : 4)) {
277 // Use push / pop instead.
279 ? (unsigned)(Is64Bit ? X86::RAX : X86::EAX)
280 : findDeadCallerSavedReg(MBB, MBBI, TRI, Is64Bit);
283 ? (Is64Bit ? X86::PUSH64r : X86::PUSH32r)
284 : (Is64Bit ? X86::POP64r : X86::POP32r);
285 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc))
286 .addReg(Reg, getDefRegState(!isSub) | getUndefRegState(isSub));
288 MI->setFlag(MachineInstr::FrameSetup);
290 MI->setFlag(MachineInstr::FrameDestroy);
296 MachineInstrBuilder MI = BuildStackAdjustment(
297 MBB, MBBI, DL, isSub ? -ThisVal : ThisVal, InEpilogue);
299 MI.setMIFlag(MachineInstr::FrameSetup);
301 MI.setMIFlag(MachineInstr::FrameDestroy);
307 MachineInstrBuilder X86FrameLowering::BuildStackAdjustment(
308 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, DebugLoc DL,
309 int64_t Offset, bool InEpilogue) const {
310 assert(Offset != 0 && "zero offset stack adjustment requested");
312 // On Atom, using LEA to adjust SP is preferred, but using it in the epilogue
316 UseLEA = STI.useLeaForSP();
318 // If we can use LEA for SP but we shouldn't, check that none
319 // of the terminators uses the eflags. Otherwise we will insert
320 // a ADD that will redefine the eflags and break the condition.
321 // Alternatively, we could move the ADD, but this may not be possible
322 // and is an optimization anyway.
323 UseLEA = canUseLEAForSPInEpilogue(*MBB.getParent());
324 if (UseLEA && !STI.useLeaForSP())
325 UseLEA = terminatorsNeedFlagsAsInput(MBB);
326 // If that assert breaks, that means we do not do the right thing
327 // in canUseAsEpilogue.
328 assert((UseLEA || !terminatorsNeedFlagsAsInput(MBB)) &&
329 "We shouldn't have allowed this insertion point");
332 MachineInstrBuilder MI;
334 MI = addRegOffset(BuildMI(MBB, MBBI, DL,
335 TII.get(getLEArOpcode(Uses64BitFramePtr)),
337 StackPtr, false, Offset);
339 bool IsSub = Offset < 0;
340 uint64_t AbsOffset = IsSub ? -Offset : Offset;
341 unsigned Opc = IsSub ? getSUBriOpcode(Uses64BitFramePtr, AbsOffset)
342 : getADDriOpcode(Uses64BitFramePtr, AbsOffset);
343 MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
346 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
351 int X86FrameLowering::mergeSPUpdates(MachineBasicBlock &MBB,
352 MachineBasicBlock::iterator &MBBI,
353 bool doMergeWithPrevious) const {
354 if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
355 (!doMergeWithPrevious && MBBI == MBB.end()))
358 MachineBasicBlock::iterator PI = doMergeWithPrevious ? std::prev(MBBI) : MBBI;
359 MachineBasicBlock::iterator NI = doMergeWithPrevious ? nullptr
361 unsigned Opc = PI->getOpcode();
364 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
365 Opc == X86::ADD32ri || Opc == X86::ADD32ri8 ||
366 Opc == X86::LEA32r || Opc == X86::LEA64_32r) &&
367 PI->getOperand(0).getReg() == StackPtr){
368 Offset += PI->getOperand(2).getImm();
370 if (!doMergeWithPrevious) MBBI = NI;
371 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
372 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
373 PI->getOperand(0).getReg() == StackPtr) {
374 Offset -= PI->getOperand(2).getImm();
376 if (!doMergeWithPrevious) MBBI = NI;
382 void X86FrameLowering::BuildCFI(MachineBasicBlock &MBB,
383 MachineBasicBlock::iterator MBBI, DebugLoc DL,
384 MCCFIInstruction CFIInst) const {
385 MachineFunction &MF = *MBB.getParent();
386 unsigned CFIIndex = MF.getMMI().addFrameInst(CFIInst);
387 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
388 .addCFIIndex(CFIIndex);
392 X86FrameLowering::emitCalleeSavedFrameMoves(MachineBasicBlock &MBB,
393 MachineBasicBlock::iterator MBBI,
395 MachineFunction &MF = *MBB.getParent();
396 MachineFrameInfo *MFI = MF.getFrameInfo();
397 MachineModuleInfo &MMI = MF.getMMI();
398 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
400 // Add callee saved registers to move list.
401 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
402 if (CSI.empty()) return;
404 // Calculate offsets.
405 for (std::vector<CalleeSavedInfo>::const_iterator
406 I = CSI.begin(), E = CSI.end(); I != E; ++I) {
407 int64_t Offset = MFI->getObjectOffset(I->getFrameIdx());
408 unsigned Reg = I->getReg();
410 unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true);
411 BuildCFI(MBB, MBBI, DL,
412 MCCFIInstruction::createOffset(nullptr, DwarfReg, Offset));
416 /// usesTheStack - This function checks if any of the users of EFLAGS
417 /// copies the EFLAGS. We know that the code that lowers COPY of EFLAGS has
418 /// to use the stack, and if we don't adjust the stack we clobber the first
420 /// See X86InstrInfo::copyPhysReg.
421 static bool usesTheStack(const MachineFunction &MF) {
422 const MachineRegisterInfo &MRI = MF.getRegInfo();
424 for (MachineRegisterInfo::reg_instr_iterator
425 ri = MRI.reg_instr_begin(X86::EFLAGS), re = MRI.reg_instr_end();
433 void X86FrameLowering::emitStackProbeCall(MachineFunction &MF,
434 MachineBasicBlock &MBB,
435 MachineBasicBlock::iterator MBBI,
437 bool IsLargeCodeModel = MF.getTarget().getCodeModel() == CodeModel::Large;
441 CallOp = IsLargeCodeModel ? X86::CALL64r : X86::CALL64pcrel32;
443 CallOp = X86::CALLpcrel32;
447 if (STI.isTargetCygMing()) {
448 Symbol = "___chkstk_ms";
452 } else if (STI.isTargetCygMing())
457 MachineInstrBuilder CI;
459 // All current stack probes take AX and SP as input, clobber flags, and
460 // preserve all registers. x86_64 probes leave RSP unmodified.
461 if (Is64Bit && MF.getTarget().getCodeModel() == CodeModel::Large) {
462 // For the large code model, we have to call through a register. Use R11,
463 // as it is scratch in all supported calling conventions.
464 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri), X86::R11)
465 .addExternalSymbol(Symbol);
466 CI = BuildMI(MBB, MBBI, DL, TII.get(CallOp)).addReg(X86::R11);
468 CI = BuildMI(MBB, MBBI, DL, TII.get(CallOp)).addExternalSymbol(Symbol);
471 unsigned AX = Is64Bit ? X86::RAX : X86::EAX;
472 unsigned SP = Is64Bit ? X86::RSP : X86::ESP;
473 CI.addReg(AX, RegState::Implicit)
474 .addReg(SP, RegState::Implicit)
475 .addReg(AX, RegState::Define | RegState::Implicit)
476 .addReg(SP, RegState::Define | RegState::Implicit)
477 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
480 // MSVC x64's __chkstk and cygwin/mingw's ___chkstk_ms do not adjust %rsp
481 // themselves. It also does not clobber %rax so we can reuse it when
483 BuildMI(MBB, MBBI, DL, TII.get(X86::SUB64rr), X86::RSP)
489 static unsigned calculateSetFPREG(uint64_t SPAdjust) {
490 // Win64 ABI has a less restrictive limitation of 240; 128 works equally well
491 // and might require smaller successive adjustments.
492 const uint64_t Win64MaxSEHOffset = 128;
493 uint64_t SEHFrameOffset = std::min(SPAdjust, Win64MaxSEHOffset);
494 // Win64 ABI requires 16-byte alignment for the UWOP_SET_FPREG opcode.
495 return SEHFrameOffset & -16;
498 // If we're forcing a stack realignment we can't rely on just the frame
499 // info, we need to know the ABI stack alignment as well in case we
500 // have a call out. Otherwise just make sure we have some alignment - we'll
501 // go with the minimum SlotSize.
502 uint64_t X86FrameLowering::calculateMaxStackAlign(const MachineFunction &MF) const {
503 const MachineFrameInfo *MFI = MF.getFrameInfo();
504 uint64_t MaxAlign = MFI->getMaxAlignment(); // Desired stack alignment.
505 unsigned StackAlign = getStackAlignment();
506 if (MF.getFunction()->hasFnAttribute("stackrealign")) {
508 MaxAlign = (StackAlign > MaxAlign) ? StackAlign : MaxAlign;
509 else if (MaxAlign < SlotSize)
515 void X86FrameLowering::BuildStackAlignAND(MachineBasicBlock &MBB,
516 MachineBasicBlock::iterator MBBI,
518 uint64_t MaxAlign) const {
519 uint64_t Val = -MaxAlign;
521 BuildMI(MBB, MBBI, DL, TII.get(getANDriOpcode(Uses64BitFramePtr, Val)),
525 .setMIFlag(MachineInstr::FrameSetup);
527 // The EFLAGS implicit def is dead.
528 MI->getOperand(3).setIsDead();
531 /// emitPrologue - Push callee-saved registers onto the stack, which
532 /// automatically adjust the stack pointer. Adjust the stack pointer to allocate
533 /// space for local variables. Also emit labels used by the exception handler to
534 /// generate the exception handling frames.
537 Here's a gist of what gets emitted:
539 ; Establish frame pointer, if needed
542 .cfi_def_cfa_offset 16
543 .cfi_offset %rbp, -16
546 .cfi_def_cfa_register %rbp
548 ; Spill general-purpose registers
549 [for all callee-saved GPRs]
552 .cfi_def_cfa_offset (offset from RETADDR)
555 ; If the required stack alignment > default stack alignment
556 ; rsp needs to be re-aligned. This creates a "re-alignment gap"
557 ; of unknown size in the stack frame.
558 [if stack needs re-alignment]
561 ; Allocate space for locals
562 [if target is Windows and allocated space > 4096 bytes]
563 ; Windows needs special care for allocations larger
566 call ___chkstk_ms/___chkstk
572 .seh_stackalloc (size of XMM spill slots)
573 .seh_setframe %rbp, SEHFrameOffset ; = size of all spill slots
578 ; Note, that while only Windows 64 ABI specifies XMMs as callee-preserved,
579 ; they may get spilled on any platform, if the current function
580 ; calls @llvm.eh.unwind.init
582 [for all callee-saved XMM registers]
583 movaps %<xmm reg>, -MMM(%rbp)
584 [for all callee-saved XMM registers]
585 .seh_savexmm %<xmm reg>, (-MMM + SEHFrameOffset)
586 ; i.e. the offset relative to (%rbp - SEHFrameOffset)
588 [for all callee-saved XMM registers]
589 movaps %<xmm reg>, KKK(%rsp)
590 [for all callee-saved XMM registers]
591 .seh_savexmm %<xmm reg>, KKK
595 [if needs base pointer]
597 [if needs to restore base pointer]
602 [for all callee-saved registers]
603 .cfi_offset %<reg>, (offset from %rbp)
605 .cfi_def_cfa_offset (offset from RETADDR)
606 [for all callee-saved registers]
607 .cfi_offset %<reg>, (offset from %rsp)
610 - .seh directives are emitted only for Windows 64 ABI
611 - .cfi directives are emitted for all other ABIs
612 - for 32-bit code, substitute %e?? registers for %r??
615 void X86FrameLowering::emitPrologue(MachineFunction &MF,
616 MachineBasicBlock &MBB) const {
617 assert(&STI == &MF.getSubtarget<X86Subtarget>() &&
618 "MF used frame lowering for wrong subtarget");
619 MachineBasicBlock::iterator MBBI = MBB.begin();
620 MachineFrameInfo *MFI = MF.getFrameInfo();
621 const Function *Fn = MF.getFunction();
622 MachineModuleInfo &MMI = MF.getMMI();
623 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
624 uint64_t MaxAlign = calculateMaxStackAlign(MF); // Desired stack alignment.
625 uint64_t StackSize = MFI->getStackSize(); // Number of bytes to allocate.
626 bool IsFunclet = MBB.isEHFuncletEntry();
627 bool HasFP = hasFP(MF);
628 bool IsWin64CC = STI.isCallingConvWin64(Fn->getCallingConv());
629 bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
630 bool NeedsWinCFI = IsWin64Prologue && Fn->needsUnwindTableEntry();
632 !IsWin64Prologue && (MMI.hasDebugInfo() || Fn->needsUnwindTableEntry());
633 unsigned FramePtr = TRI->getFrameRegister(MF);
634 const unsigned MachineFramePtr =
635 STI.isTarget64BitILP32()
636 ? getX86SubSuperRegister(FramePtr, MVT::i64, false)
638 unsigned BasePtr = TRI->getBaseRegister();
641 // Add RETADDR move area to callee saved frame size.
642 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
643 if (TailCallReturnAddrDelta && IsWin64Prologue)
644 report_fatal_error("Can't handle guaranteed tail call under win64 yet");
646 if (TailCallReturnAddrDelta < 0)
647 X86FI->setCalleeSavedFrameSize(
648 X86FI->getCalleeSavedFrameSize() - TailCallReturnAddrDelta);
650 bool UseStackProbe = (STI.isOSWindows() && !STI.isTargetMachO());
652 // The default stack probe size is 4096 if the function has no stackprobesize
654 unsigned StackProbeSize = 4096;
655 if (Fn->hasFnAttribute("stack-probe-size"))
656 Fn->getFnAttribute("stack-probe-size")
658 .getAsInteger(0, StackProbeSize);
660 // If this is x86-64 and the Red Zone is not disabled, if we are a leaf
661 // function, and use up to 128 bytes of stack space, don't have a frame
662 // pointer, calls, or dynamic alloca then we do not need to adjust the
663 // stack pointer (we fit in the Red Zone). We also check that we don't
664 // push and pop from the stack.
665 if (Is64Bit && !Fn->hasFnAttribute(Attribute::NoRedZone) &&
666 !TRI->needsStackRealignment(MF) &&
667 !MFI->hasVarSizedObjects() && // No dynamic alloca.
668 !MFI->adjustsStack() && // No calls.
669 !IsWin64CC && // Win64 has no Red Zone
670 !usesTheStack(MF) && // Don't push and pop.
671 !MF.shouldSplitStack()) { // Regular stack
672 uint64_t MinSize = X86FI->getCalleeSavedFrameSize();
673 if (HasFP) MinSize += SlotSize;
674 StackSize = std::max(MinSize, StackSize > 128 ? StackSize - 128 : 0);
675 MFI->setStackSize(StackSize);
678 // Insert stack pointer adjustment for later moving of return addr. Only
679 // applies to tail call optimized functions where the callee argument stack
680 // size is bigger than the callers.
681 if (TailCallReturnAddrDelta < 0) {
682 BuildStackAdjustment(MBB, MBBI, DL, TailCallReturnAddrDelta,
683 /*InEpilogue=*/false)
684 .setMIFlag(MachineInstr::FrameSetup);
687 // Mapping for machine moves:
689 // DST: VirtualFP AND
690 // SRC: VirtualFP => DW_CFA_def_cfa_offset
691 // ELSE => DW_CFA_def_cfa
693 // SRC: VirtualFP AND
694 // DST: Register => DW_CFA_def_cfa_register
697 // OFFSET < 0 => DW_CFA_offset_extended_sf
698 // REG < 64 => DW_CFA_offset + Reg
699 // ELSE => DW_CFA_offset_extended
701 uint64_t NumBytes = 0;
702 int stackGrowth = -SlotSize;
704 unsigned RDX = Uses64BitFramePtr ? X86::RDX : X86::EDX;
705 if (IsWin64Prologue && IsFunclet) {
706 // Immediately spill RDX into the home slot. The runtime cares about this.
707 // MOV64mr %rdx, 16(%rsp)
708 unsigned MOVmr = Uses64BitFramePtr ? X86::MOV64mr : X86::MOV32mr;
709 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(MOVmr)), StackPtr, true, 16)
711 .setMIFlag(MachineInstr::FrameSetup);
715 // Calculate required stack adjustment.
716 uint64_t FrameSize = StackSize - SlotSize;
717 // If required, include space for extra hidden slot for stashing base pointer.
718 if (X86FI->getRestoreBasePointer())
719 FrameSize += SlotSize;
721 NumBytes = FrameSize - X86FI->getCalleeSavedFrameSize();
723 // Callee-saved registers are pushed on stack before the stack is realigned.
724 if (TRI->needsStackRealignment(MF) && !IsWin64Prologue)
725 NumBytes = RoundUpToAlignment(NumBytes, MaxAlign);
727 // Get the offset of the stack slot for the EBP register, which is
728 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
729 // Update the frame offset adjustment.
731 MFI->setOffsetAdjustment(-NumBytes);
733 assert(MFI->getOffsetAdjustment() == -(int)NumBytes &&
734 "should calculate same local variable offset for funclets");
736 // Save EBP/RBP into the appropriate stack slot.
737 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
738 .addReg(MachineFramePtr, RegState::Kill)
739 .setMIFlag(MachineInstr::FrameSetup);
742 // Mark the place where EBP/RBP was saved.
743 // Define the current CFA rule to use the provided offset.
745 BuildCFI(MBB, MBBI, DL,
746 MCCFIInstruction::createDefCfaOffset(nullptr, 2 * stackGrowth));
748 // Change the rule for the FramePtr to be an "offset" rule.
749 unsigned DwarfFramePtr = TRI->getDwarfRegNum(MachineFramePtr, true);
750 BuildCFI(MBB, MBBI, DL, MCCFIInstruction::createOffset(
751 nullptr, DwarfFramePtr, 2 * stackGrowth));
755 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_PushReg))
757 .setMIFlag(MachineInstr::FrameSetup);
760 if (!IsWin64Prologue && !IsFunclet) {
761 // Update EBP with the new base value.
762 BuildMI(MBB, MBBI, DL,
763 TII.get(Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr),
766 .setMIFlag(MachineInstr::FrameSetup);
769 // Mark effective beginning of when frame pointer becomes valid.
770 // Define the current CFA to use the EBP/RBP register.
771 unsigned DwarfFramePtr = TRI->getDwarfRegNum(MachineFramePtr, true);
772 BuildCFI(MBB, MBBI, DL, MCCFIInstruction::createDefCfaRegister(
773 nullptr, DwarfFramePtr));
777 // Mark the FramePtr as live-in in every block.
778 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
779 I->addLiveIn(MachineFramePtr);
781 assert(!IsFunclet && "funclets without FPs not yet implemented");
782 NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
785 // For EH funclets, only allocate enough space for outgoing calls. Save the
786 // NumBytes value that we would've used for the parent frame.
787 unsigned ParentFrameNumBytes = NumBytes;
789 NumBytes = MFI->getMaxCallFrameSize();
791 // Skip the callee-saved push instructions.
792 bool PushedRegs = false;
793 int StackOffset = 2 * stackGrowth;
795 while (MBBI != MBB.end() &&
796 MBBI->getFlag(MachineInstr::FrameSetup) &&
797 (MBBI->getOpcode() == X86::PUSH32r ||
798 MBBI->getOpcode() == X86::PUSH64r)) {
800 unsigned Reg = MBBI->getOperand(0).getReg();
803 if (!HasFP && NeedsDwarfCFI) {
804 // Mark callee-saved push instruction.
805 // Define the current CFA rule to use the provided offset.
807 BuildCFI(MBB, MBBI, DL,
808 MCCFIInstruction::createDefCfaOffset(nullptr, StackOffset));
809 StackOffset += stackGrowth;
813 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_PushReg)).addImm(Reg).setMIFlag(
814 MachineInstr::FrameSetup);
818 // Realign stack after we pushed callee-saved registers (so that we'll be
819 // able to calculate their offsets from the frame pointer).
820 // Don't do this for Win64, it needs to realign the stack after the prologue.
821 if (!IsWin64Prologue && !IsFunclet && TRI->needsStackRealignment(MF)) {
822 assert(HasFP && "There should be a frame pointer if stack is realigned.");
823 BuildStackAlignAND(MBB, MBBI, DL, MaxAlign);
826 // If there is an SUB32ri of ESP immediately before this instruction, merge
827 // the two. This can be the case when tail call elimination is enabled and
828 // the callee has more arguments then the caller.
829 NumBytes -= mergeSPUpdates(MBB, MBBI, true);
831 // Adjust stack pointer: ESP -= numbytes.
833 // Windows and cygwin/mingw require a prologue helper routine when allocating
834 // more than 4K bytes on the stack. Windows uses __chkstk and cygwin/mingw
835 // uses __alloca. __alloca and the 32-bit version of __chkstk will probe the
836 // stack and adjust the stack pointer in one go. The 64-bit version of
837 // __chkstk is only responsible for probing the stack. The 64-bit prologue is
838 // responsible for adjusting the stack pointer. Touching the stack at 4K
839 // increments is necessary to ensure that the guard pages used by the OS
840 // virtual memory manager are allocated in correct sequence.
841 uint64_t AlignedNumBytes = NumBytes;
842 if (IsWin64Prologue && !IsFunclet && TRI->needsStackRealignment(MF))
843 AlignedNumBytes = RoundUpToAlignment(AlignedNumBytes, MaxAlign);
844 if (AlignedNumBytes >= StackProbeSize && UseStackProbe) {
845 // Check whether EAX is livein for this function.
846 bool isEAXAlive = isEAXLiveIn(MF);
849 // Sanity check that EAX is not livein for this function.
850 // It should not be, so throw an assert.
851 assert(!Is64Bit && "EAX is livein in x64 case!");
854 BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH32r))
855 .addReg(X86::EAX, RegState::Kill)
856 .setMIFlag(MachineInstr::FrameSetup);
860 // Handle the 64-bit Windows ABI case where we need to call __chkstk.
861 // Function prologue is responsible for adjusting the stack pointer.
862 if (isUInt<32>(NumBytes)) {
863 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
865 .setMIFlag(MachineInstr::FrameSetup);
866 } else if (isInt<32>(NumBytes)) {
867 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri32), X86::RAX)
869 .setMIFlag(MachineInstr::FrameSetup);
871 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri), X86::RAX)
873 .setMIFlag(MachineInstr::FrameSetup);
876 // Allocate NumBytes-4 bytes on stack in case of isEAXAlive.
877 // We'll also use 4 already allocated bytes for EAX.
878 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
879 .addImm(isEAXAlive ? NumBytes - 4 : NumBytes)
880 .setMIFlag(MachineInstr::FrameSetup);
883 // Save a pointer to the MI where we set AX.
884 MachineBasicBlock::iterator SetRAX = MBBI;
887 // Call __chkstk, __chkstk_ms, or __alloca.
888 emitStackProbeCall(MF, MBB, MBBI, DL);
890 // Apply the frame setup flag to all inserted instrs.
891 for (; SetRAX != MBBI; ++SetRAX)
892 SetRAX->setFlag(MachineInstr::FrameSetup);
896 MachineInstr *MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV32rm),
898 StackPtr, false, NumBytes - 4);
899 MI->setFlag(MachineInstr::FrameSetup);
900 MBB.insert(MBBI, MI);
902 } else if (NumBytes) {
903 emitSPUpdate(MBB, MBBI, -(int64_t)NumBytes, /*InEpilogue=*/false);
906 if (NeedsWinCFI && NumBytes)
907 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_StackAlloc))
909 .setMIFlag(MachineInstr::FrameSetup);
911 int SEHFrameOffset = 0;
912 if (IsWin64Prologue && HasFP) {
913 // Set RBP to a small fixed offset from RSP. In the funclet case, we base
914 // this calculation on the incoming RDX, which holds the value of RSP from
915 // the parent frame at the end of the prologue.
916 unsigned SPOrRDX = !IsFunclet ? StackPtr : RDX;
917 SEHFrameOffset = calculateSetFPREG(ParentFrameNumBytes);
919 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::LEA64r), FramePtr),
920 SPOrRDX, false, SEHFrameOffset);
922 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64rr), FramePtr)
925 // If this is not a funclet, emit the CFI describing our frame pointer.
926 if (NeedsWinCFI && !IsFunclet)
927 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_SetFrame))
929 .addImm(SEHFrameOffset)
930 .setMIFlag(MachineInstr::FrameSetup);
931 } else if (IsFunclet && STI.is32Bit()) {
932 // Reset EBP / ESI to something good for funclets.
933 MBBI = restoreWin32EHStackPointers(MBB, MBBI, DL);
936 while (MBBI != MBB.end() && MBBI->getFlag(MachineInstr::FrameSetup)) {
937 const MachineInstr *FrameInstr = &*MBBI;
942 if (unsigned Reg = TII.isStoreToStackSlot(FrameInstr, FI)) {
943 if (X86::FR64RegClass.contains(Reg)) {
944 unsigned IgnoredFrameReg;
945 int Offset = getFrameIndexReference(MF, FI, IgnoredFrameReg);
946 Offset += SEHFrameOffset;
948 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_SaveXMM))
951 .setMIFlag(MachineInstr::FrameSetup);
958 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_EndPrologue))
959 .setMIFlag(MachineInstr::FrameSetup);
961 // Realign stack after we spilled callee-saved registers (so that we'll be
962 // able to calculate their offsets from the frame pointer).
963 // Win64 requires aligning the stack after the prologue.
964 if (IsWin64Prologue && TRI->needsStackRealignment(MF)) {
965 assert(HasFP && "There should be a frame pointer if stack is realigned.");
966 BuildStackAlignAND(MBB, MBBI, DL, MaxAlign);
969 // If we need a base pointer, set it up here. It's whatever the value
970 // of the stack pointer is at this point. Any variable size objects
971 // will be allocated after this, so we can still use the base pointer
972 // to reference locals.
973 if (TRI->hasBasePointer(MF)) {
974 // Update the base pointer with the current stack pointer.
975 unsigned Opc = Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr;
976 BuildMI(MBB, MBBI, DL, TII.get(Opc), BasePtr)
978 .setMIFlag(MachineInstr::FrameSetup);
979 if (X86FI->getRestoreBasePointer()) {
980 // Stash value of base pointer. Saving RSP instead of EBP shortens
981 // dependence chain. Used by SjLj EH.
982 unsigned Opm = Uses64BitFramePtr ? X86::MOV64mr : X86::MOV32mr;
983 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opm)),
984 FramePtr, true, X86FI->getRestoreBasePointerOffset())
986 .setMIFlag(MachineInstr::FrameSetup);
989 if (X86FI->getHasSEHFramePtrSave()) {
990 // Stash the value of the frame pointer relative to the base pointer for
991 // Win32 EH. This supports Win32 EH, which does the inverse of the above:
992 // it recovers the frame pointer from the base pointer rather than the
994 unsigned Opm = Uses64BitFramePtr ? X86::MOV64mr : X86::MOV32mr;
997 getFrameIndexReference(MF, X86FI->getSEHFramePtrSaveIndex(), UsedReg);
998 assert(UsedReg == BasePtr);
999 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opm)), UsedReg, true, Offset)
1001 .setMIFlag(MachineInstr::FrameSetup);
1005 if (((!HasFP && NumBytes) || PushedRegs) && NeedsDwarfCFI) {
1006 // Mark end of stack pointer adjustment.
1007 if (!HasFP && NumBytes) {
1008 // Define the current CFA rule to use the provided offset.
1010 BuildCFI(MBB, MBBI, DL, MCCFIInstruction::createDefCfaOffset(
1011 nullptr, -StackSize + stackGrowth));
1014 // Emit DWARF info specifying the offsets of the callee-saved registers.
1016 emitCalleeSavedFrameMoves(MBB, MBBI, DL);
1020 bool X86FrameLowering::canUseLEAForSPInEpilogue(
1021 const MachineFunction &MF) const {
1022 // We can't use LEA instructions for adjusting the stack pointer if this is a
1023 // leaf function in the Win64 ABI. Only ADD instructions may be used to
1024 // deallocate the stack.
1025 // This means that we can use LEA for SP in two situations:
1026 // 1. We *aren't* using the Win64 ABI which means we are free to use LEA.
1027 // 2. We *have* a frame pointer which means we are permitted to use LEA.
1028 return !MF.getTarget().getMCAsmInfo()->usesWindowsCFI() || hasFP(MF);
1031 static bool isFuncletReturnInstr(MachineInstr *MI) {
1032 switch (MI->getOpcode()) {
1034 case X86::CLEANUPRET:
1039 llvm_unreachable("impossible");
1042 void X86FrameLowering::emitEpilogue(MachineFunction &MF,
1043 MachineBasicBlock &MBB) const {
1044 const MachineFrameInfo *MFI = MF.getFrameInfo();
1045 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1046 MachineBasicBlock::iterator MBBI = MBB.getFirstTerminator();
1048 if (MBBI != MBB.end())
1049 DL = MBBI->getDebugLoc();
1050 // standard x86_64 and NaCl use 64-bit frame/stack pointers, x32 - 32-bit.
1051 const bool Is64BitILP32 = STI.isTarget64BitILP32();
1052 unsigned FramePtr = TRI->getFrameRegister(MF);
1053 unsigned MachineFramePtr =
1054 Is64BitILP32 ? getX86SubSuperRegister(FramePtr, MVT::i64, false)
1057 bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
1059 IsWin64Prologue && MF.getFunction()->needsUnwindTableEntry();
1060 bool IsFunclet = isFuncletReturnInstr(MBBI);
1062 // Get the number of bytes to allocate from the FrameInfo.
1063 uint64_t StackSize = MFI->getStackSize();
1064 uint64_t MaxAlign = calculateMaxStackAlign(MF);
1065 unsigned CSSize = X86FI->getCalleeSavedFrameSize();
1066 uint64_t NumBytes = 0;
1068 if (MBBI->getOpcode() == X86::CATCHRET) {
1069 NumBytes = MFI->getMaxCallFrameSize();
1070 assert(hasFP(MF) && "EH funclets without FP not yet implemented");
1071 MachineBasicBlock *TargetMBB = MBBI->getOperand(0).getMBB();
1073 // If this is SEH, this isn't really a funclet return.
1074 bool IsSEH = isAsynchronousEHPersonality(
1075 classifyEHPersonality(MF.getFunction()->getPersonalityFn()));
1078 restoreWin32EHStackPointers(MBB, MBBI, DL, /*RestoreSP=*/true);
1079 BuildMI(MBB, MBBI, DL, TII.get(X86::JMP_4)).addMBB(TargetMBB);
1080 MBBI->eraseFromParent();
1084 // For 32-bit, create a new block for the restore code.
1085 MachineBasicBlock *RestoreMBB = TargetMBB;
1086 if (STI.is32Bit()) {
1087 RestoreMBB = MF.CreateMachineBasicBlock(MBB.getBasicBlock());
1088 MF.insert(TargetMBB, RestoreMBB);
1089 MBB.removeSuccessor(TargetMBB);
1090 MBB.addSuccessor(RestoreMBB);
1091 RestoreMBB->addSuccessor(TargetMBB);
1092 MBBI->getOperand(0).setMBB(RestoreMBB);
1095 // Fill EAX/RAX with the address of the target block.
1096 unsigned ReturnReg = STI.is64Bit() ? X86::RAX : X86::EAX;
1097 if (STI.is64Bit()) {
1098 // LEA64r RestoreMBB(%rip), %rax
1099 BuildMI(MBB, MBBI, DL, TII.get(X86::LEA64r), ReturnReg)
1106 // MOV32ri $RestoreMBB, %eax
1107 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri))
1109 .addMBB(RestoreMBB);
1113 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::POP64r : X86::POP32r),
1115 .setMIFlag(MachineInstr::FrameDestroy);
1117 // Insert frame restoration code in a new block.
1118 if (STI.is32Bit()) {
1119 auto RestoreMBBI = RestoreMBB->begin();
1120 restoreWin32EHStackPointers(*RestoreMBB, RestoreMBBI, DL,
1121 /*RestoreSP=*/true);
1122 BuildMI(*RestoreMBB, RestoreMBBI, DL, TII.get(X86::JMP_4))
1125 } else if (MBBI->getOpcode() == X86::CLEANUPRET) {
1126 NumBytes = MFI->getMaxCallFrameSize();
1127 assert(hasFP(MF) && "EH funclets without FP not yet implemented");
1128 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::POP64r : X86::POP32r),
1130 .setMIFlag(MachineInstr::FrameDestroy);
1131 } else if (hasFP(MF)) {
1132 // Calculate required stack adjustment.
1133 uint64_t FrameSize = StackSize - SlotSize;
1134 NumBytes = FrameSize - CSSize;
1136 // Callee-saved registers were pushed on stack before the stack was
1138 if (TRI->needsStackRealignment(MF) && !IsWin64Prologue)
1139 NumBytes = RoundUpToAlignment(FrameSize, MaxAlign);
1142 BuildMI(MBB, MBBI, DL,
1143 TII.get(Is64Bit ? X86::POP64r : X86::POP32r), MachineFramePtr)
1144 .setMIFlag(MachineInstr::FrameDestroy);
1146 NumBytes = StackSize - CSSize;
1148 uint64_t SEHStackAllocAmt = NumBytes;
1150 // Skip the callee-saved pop instructions.
1151 while (MBBI != MBB.begin()) {
1152 MachineBasicBlock::iterator PI = std::prev(MBBI);
1153 unsigned Opc = PI->getOpcode();
1155 if ((Opc != X86::POP32r || !PI->getFlag(MachineInstr::FrameDestroy)) &&
1156 (Opc != X86::POP64r || !PI->getFlag(MachineInstr::FrameDestroy)) &&
1157 Opc != X86::DBG_VALUE && !PI->isTerminator())
1162 MachineBasicBlock::iterator FirstCSPop = MBBI;
1164 if (MBBI != MBB.end())
1165 DL = MBBI->getDebugLoc();
1167 // If there is an ADD32ri or SUB32ri of ESP immediately before this
1168 // instruction, merge the two instructions.
1169 if (NumBytes || MFI->hasVarSizedObjects())
1170 NumBytes += mergeSPUpdates(MBB, MBBI, true);
1172 // If dynamic alloca is used, then reset esp to point to the last callee-saved
1173 // slot before popping them off! Same applies for the case, when stack was
1174 // realigned. Don't do this if this was a funclet epilogue, since the funclets
1175 // will not do realignment or dynamic stack allocation.
1176 if ((TRI->needsStackRealignment(MF) || MFI->hasVarSizedObjects()) &&
1178 if (TRI->needsStackRealignment(MF))
1180 unsigned SEHFrameOffset = calculateSetFPREG(SEHStackAllocAmt);
1181 uint64_t LEAAmount =
1182 IsWin64Prologue ? SEHStackAllocAmt - SEHFrameOffset : -CSSize;
1184 // There are only two legal forms of epilogue:
1185 // - add SEHAllocationSize, %rsp
1186 // - lea SEHAllocationSize(%FramePtr), %rsp
1188 // 'mov %FramePtr, %rsp' will not be recognized as an epilogue sequence.
1189 // However, we may use this sequence if we have a frame pointer because the
1190 // effects of the prologue can safely be undone.
1191 if (LEAAmount != 0) {
1192 unsigned Opc = getLEArOpcode(Uses64BitFramePtr);
1193 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr),
1194 FramePtr, false, LEAAmount);
1197 unsigned Opc = (Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr);
1198 BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
1202 } else if (NumBytes) {
1203 // Adjust stack pointer back: ESP += numbytes.
1204 emitSPUpdate(MBB, MBBI, NumBytes, /*InEpilogue=*/true);
1208 // Windows unwinder will not invoke function's exception handler if IP is
1209 // either in prologue or in epilogue. This behavior causes a problem when a
1210 // call immediately precedes an epilogue, because the return address points
1211 // into the epilogue. To cope with that, we insert an epilogue marker here,
1212 // then replace it with a 'nop' if it ends up immediately after a CALL in the
1213 // final emitted code.
1215 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_Epilogue));
1217 // Add the return addr area delta back since we are not tail calling.
1218 int Offset = -1 * X86FI->getTCReturnAddrDelta();
1219 assert(Offset >= 0 && "TCDelta should never be positive");
1221 MBBI = MBB.getFirstTerminator();
1223 // Check for possible merge with preceding ADD instruction.
1224 Offset += mergeSPUpdates(MBB, MBBI, true);
1225 emitSPUpdate(MBB, MBBI, Offset, /*InEpilogue=*/true);
1229 // NOTE: this only has a subset of the full frame index logic. In
1230 // particular, the FI < 0 and AfterFPPop logic is handled in
1231 // X86RegisterInfo::eliminateFrameIndex, but not here. Possibly
1232 // (probably?) it should be moved into here.
1233 int X86FrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI,
1234 unsigned &FrameReg) const {
1235 const MachineFrameInfo *MFI = MF.getFrameInfo();
1237 // We can't calculate offset from frame pointer if the stack is realigned,
1238 // so enforce usage of stack/base pointer. The base pointer is used when we
1239 // have dynamic allocas in addition to dynamic realignment.
1240 if (TRI->hasBasePointer(MF))
1241 FrameReg = TRI->getBaseRegister();
1242 else if (TRI->needsStackRealignment(MF))
1243 FrameReg = TRI->getStackRegister();
1245 FrameReg = TRI->getFrameRegister(MF);
1247 // Offset will hold the offset from the stack pointer at function entry to the
1249 // We need to factor in additional offsets applied during the prologue to the
1250 // frame, base, and stack pointer depending on which is used.
1251 int Offset = MFI->getObjectOffset(FI) - getOffsetOfLocalArea();
1252 const X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1253 unsigned CSSize = X86FI->getCalleeSavedFrameSize();
1254 uint64_t StackSize = MFI->getStackSize();
1255 bool HasFP = hasFP(MF);
1256 bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
1257 int64_t FPDelta = 0;
1259 if (IsWin64Prologue) {
1260 assert(!MFI->hasCalls() || (StackSize % 16) == 8);
1262 // Calculate required stack adjustment.
1263 uint64_t FrameSize = StackSize - SlotSize;
1264 // If required, include space for extra hidden slot for stashing base pointer.
1265 if (X86FI->getRestoreBasePointer())
1266 FrameSize += SlotSize;
1267 uint64_t NumBytes = FrameSize - CSSize;
1269 uint64_t SEHFrameOffset = calculateSetFPREG(NumBytes);
1270 if (FI && FI == X86FI->getFAIndex())
1271 return -SEHFrameOffset;
1273 // FPDelta is the offset from the "traditional" FP location of the old base
1274 // pointer followed by return address and the location required by the
1275 // restricted Win64 prologue.
1276 // Add FPDelta to all offsets below that go through the frame pointer.
1277 FPDelta = FrameSize - SEHFrameOffset;
1278 assert((!MFI->hasCalls() || (FPDelta % 16) == 0) &&
1279 "FPDelta isn't aligned per the Win64 ABI!");
1283 if (TRI->hasBasePointer(MF)) {
1284 assert(HasFP && "VLAs and dynamic stack realign, but no FP?!");
1286 // Skip the saved EBP.
1287 return Offset + SlotSize + FPDelta;
1289 assert((-(Offset + StackSize)) % MFI->getObjectAlignment(FI) == 0);
1290 return Offset + StackSize;
1292 } else if (TRI->needsStackRealignment(MF)) {
1294 // Skip the saved EBP.
1295 return Offset + SlotSize + FPDelta;
1297 assert((-(Offset + StackSize)) % MFI->getObjectAlignment(FI) == 0);
1298 return Offset + StackSize;
1300 // FIXME: Support tail calls
1303 return Offset + StackSize;
1305 // Skip the saved EBP.
1308 // Skip the RETADDR move area
1309 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
1310 if (TailCallReturnAddrDelta < 0)
1311 Offset -= TailCallReturnAddrDelta;
1314 return Offset + FPDelta;
1317 // Simplified from getFrameIndexReference keeping only StackPointer cases
1318 int X86FrameLowering::getFrameIndexReferenceFromSP(const MachineFunction &MF,
1320 unsigned &FrameReg) const {
1321 const MachineFrameInfo *MFI = MF.getFrameInfo();
1322 // Does not include any dynamic realign.
1323 const uint64_t StackSize = MFI->getStackSize();
1326 // Note: LLVM arranges the stack as:
1327 // Args > Saved RetPC (<--FP) > CSRs > dynamic alignment (<--BP)
1328 // > "Stack Slots" (<--SP)
1329 // We can always address StackSlots from RSP. We can usually (unless
1330 // needsStackRealignment) address CSRs from RSP, but sometimes need to
1331 // address them from RBP. FixedObjects can be placed anywhere in the stack
1332 // frame depending on their specific requirements (i.e. we can actually
1333 // refer to arguments to the function which are stored in the *callers*
1334 // frame). As a result, THE RESULT OF THIS CALL IS MEANINGLESS FOR CSRs
1335 // AND FixedObjects IFF needsStackRealignment or hasVarSizedObject.
1337 assert(!TRI->hasBasePointer(MF) && "we don't handle this case");
1339 // We don't handle tail calls, and shouldn't be seeing them
1341 int TailCallReturnAddrDelta =
1342 MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta();
1343 assert(!(TailCallReturnAddrDelta < 0) && "we don't handle this case!");
1347 // Fill in FrameReg output argument.
1348 FrameReg = TRI->getStackRegister();
1350 // This is how the math works out:
1352 // %rsp grows (i.e. gets lower) left to right. Each box below is
1353 // one word (eight bytes). Obj0 is the stack slot we're trying to
1356 // ----------------------------------
1357 // | BP | Obj0 | Obj1 | ... | ObjN |
1358 // ----------------------------------
1362 // A is the incoming stack pointer.
1363 // (B - A) is the local area offset (-8 for x86-64) [1]
1364 // (C - A) is the Offset returned by MFI->getObjectOffset for Obj0 [2]
1366 // |(E - B)| is the StackSize (absolute value, positive). For a
1367 // stack that grown down, this works out to be (B - E). [3]
1369 // E is also the value of %rsp after stack has been set up, and we
1370 // want (C - E) -- the value we can add to %rsp to get to Obj0. Now
1371 // (C - E) == (C - A) - (B - A) + (B - E)
1372 // { Using [1], [2] and [3] above }
1373 // == getObjectOffset - LocalAreaOffset + StackSize
1376 // Get the Offset from the StackPointer
1377 int Offset = MFI->getObjectOffset(FI) - getOffsetOfLocalArea();
1379 return Offset + StackSize;
1382 bool X86FrameLowering::assignCalleeSavedSpillSlots(
1383 MachineFunction &MF, const TargetRegisterInfo *TRI,
1384 std::vector<CalleeSavedInfo> &CSI) const {
1385 MachineFrameInfo *MFI = MF.getFrameInfo();
1386 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1388 unsigned CalleeSavedFrameSize = 0;
1389 int SpillSlotOffset = getOffsetOfLocalArea() + X86FI->getTCReturnAddrDelta();
1392 // emitPrologue always spills frame register the first thing.
1393 SpillSlotOffset -= SlotSize;
1394 MFI->CreateFixedSpillStackObject(SlotSize, SpillSlotOffset);
1396 // Since emitPrologue and emitEpilogue will handle spilling and restoring of
1397 // the frame register, we can delete it from CSI list and not have to worry
1398 // about avoiding it later.
1399 unsigned FPReg = TRI->getFrameRegister(MF);
1400 for (unsigned i = 0; i < CSI.size(); ++i) {
1401 if (TRI->regsOverlap(CSI[i].getReg(),FPReg)) {
1402 CSI.erase(CSI.begin() + i);
1408 // Assign slots for GPRs. It increases frame size.
1409 for (unsigned i = CSI.size(); i != 0; --i) {
1410 unsigned Reg = CSI[i - 1].getReg();
1412 if (!X86::GR64RegClass.contains(Reg) && !X86::GR32RegClass.contains(Reg))
1415 SpillSlotOffset -= SlotSize;
1416 CalleeSavedFrameSize += SlotSize;
1418 int SlotIndex = MFI->CreateFixedSpillStackObject(SlotSize, SpillSlotOffset);
1419 CSI[i - 1].setFrameIdx(SlotIndex);
1422 X86FI->setCalleeSavedFrameSize(CalleeSavedFrameSize);
1424 // Assign slots for XMMs.
1425 for (unsigned i = CSI.size(); i != 0; --i) {
1426 unsigned Reg = CSI[i - 1].getReg();
1427 if (X86::GR64RegClass.contains(Reg) || X86::GR32RegClass.contains(Reg))
1430 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1432 SpillSlotOffset -= std::abs(SpillSlotOffset) % RC->getAlignment();
1434 SpillSlotOffset -= RC->getSize();
1436 MFI->CreateFixedSpillStackObject(RC->getSize(), SpillSlotOffset);
1437 CSI[i - 1].setFrameIdx(SlotIndex);
1438 MFI->ensureMaxAlignment(RC->getAlignment());
1444 bool X86FrameLowering::spillCalleeSavedRegisters(
1445 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
1446 const std::vector<CalleeSavedInfo> &CSI,
1447 const TargetRegisterInfo *TRI) const {
1448 DebugLoc DL = MBB.findDebugLoc(MI);
1450 // Don't save CSRs in 32-bit EH funclets. The caller saves EBX, EBP, ESI, EDI
1451 // for us, and there are no XMM CSRs on Win32.
1452 if (MBB.isEHFuncletEntry() && STI.is32Bit() && STI.isOSWindows())
1455 // Push GPRs. It increases frame size.
1456 unsigned Opc = STI.is64Bit() ? X86::PUSH64r : X86::PUSH32r;
1457 for (unsigned i = CSI.size(); i != 0; --i) {
1458 unsigned Reg = CSI[i - 1].getReg();
1460 if (!X86::GR64RegClass.contains(Reg) && !X86::GR32RegClass.contains(Reg))
1462 // Add the callee-saved register as live-in. It's killed at the spill.
1465 BuildMI(MBB, MI, DL, TII.get(Opc)).addReg(Reg, RegState::Kill)
1466 .setMIFlag(MachineInstr::FrameSetup);
1469 // Make XMM regs spilled. X86 does not have ability of push/pop XMM.
1470 // It can be done by spilling XMMs to stack frame.
1471 for (unsigned i = CSI.size(); i != 0; --i) {
1472 unsigned Reg = CSI[i-1].getReg();
1473 if (X86::GR64RegClass.contains(Reg) || X86::GR32RegClass.contains(Reg))
1475 // Add the callee-saved register as live-in. It's killed at the spill.
1477 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1479 TII.storeRegToStackSlot(MBB, MI, Reg, true, CSI[i - 1].getFrameIdx(), RC,
1482 MI->setFlag(MachineInstr::FrameSetup);
1489 bool X86FrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
1490 MachineBasicBlock::iterator MI,
1491 const std::vector<CalleeSavedInfo> &CSI,
1492 const TargetRegisterInfo *TRI) const {
1496 if (isFuncletReturnInstr(MI) && STI.isOSWindows()) {
1497 // Don't restore CSRs in 32-bit EH funclets. Matches
1498 // spillCalleeSavedRegisters.
1501 // Don't restore CSRs before an SEH catchret. SEH except blocks do not form
1502 // funclets. emitEpilogue transforms these to normal jumps.
1503 if (MI->getOpcode() == X86::CATCHRET) {
1504 const Function *Func = MBB.getParent()->getFunction();
1505 bool IsSEH = isAsynchronousEHPersonality(
1506 classifyEHPersonality(Func->getPersonalityFn()));
1512 DebugLoc DL = MBB.findDebugLoc(MI);
1514 // Reload XMMs from stack frame.
1515 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1516 unsigned Reg = CSI[i].getReg();
1517 if (X86::GR64RegClass.contains(Reg) ||
1518 X86::GR32RegClass.contains(Reg))
1521 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1522 TII.loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(), RC, TRI);
1526 unsigned Opc = STI.is64Bit() ? X86::POP64r : X86::POP32r;
1527 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1528 unsigned Reg = CSI[i].getReg();
1529 if (!X86::GR64RegClass.contains(Reg) &&
1530 !X86::GR32RegClass.contains(Reg))
1533 BuildMI(MBB, MI, DL, TII.get(Opc), Reg)
1534 .setMIFlag(MachineInstr::FrameDestroy);
1539 void X86FrameLowering::determineCalleeSaves(MachineFunction &MF,
1540 BitVector &SavedRegs,
1541 RegScavenger *RS) const {
1542 TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
1544 MachineFrameInfo *MFI = MF.getFrameInfo();
1546 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1547 int64_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
1549 if (TailCallReturnAddrDelta < 0) {
1550 // create RETURNADDR area
1559 MFI->CreateFixedObject(-TailCallReturnAddrDelta,
1560 TailCallReturnAddrDelta - SlotSize, true);
1563 // Spill the BasePtr if it's used.
1564 if (TRI->hasBasePointer(MF)) {
1565 SavedRegs.set(TRI->getBaseRegister());
1567 // Allocate a spill slot for EBP if we have a base pointer and EH funclets.
1568 if (MF.getMMI().hasEHFunclets()) {
1569 int FI = MFI->CreateSpillStackObject(SlotSize, SlotSize);
1570 X86FI->setHasSEHFramePtrSave(true);
1571 X86FI->setSEHFramePtrSaveIndex(FI);
1577 HasNestArgument(const MachineFunction *MF) {
1578 const Function *F = MF->getFunction();
1579 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
1581 if (I->hasNestAttr())
1587 /// GetScratchRegister - Get a temp register for performing work in the
1588 /// segmented stack and the Erlang/HiPE stack prologue. Depending on platform
1589 /// and the properties of the function either one or two registers will be
1590 /// needed. Set primary to true for the first register, false for the second.
1592 GetScratchRegister(bool Is64Bit, bool IsLP64, const MachineFunction &MF, bool Primary) {
1593 CallingConv::ID CallingConvention = MF.getFunction()->getCallingConv();
1596 if (CallingConvention == CallingConv::HiPE) {
1598 return Primary ? X86::R14 : X86::R13;
1600 return Primary ? X86::EBX : X86::EDI;
1605 return Primary ? X86::R11 : X86::R12;
1607 return Primary ? X86::R11D : X86::R12D;
1610 bool IsNested = HasNestArgument(&MF);
1612 if (CallingConvention == CallingConv::X86_FastCall ||
1613 CallingConvention == CallingConv::Fast) {
1615 report_fatal_error("Segmented stacks does not support fastcall with "
1616 "nested function.");
1617 return Primary ? X86::EAX : X86::ECX;
1620 return Primary ? X86::EDX : X86::EAX;
1621 return Primary ? X86::ECX : X86::EAX;
1624 // The stack limit in the TCB is set to this many bytes above the actual stack
1626 static const uint64_t kSplitStackAvailable = 256;
1628 void X86FrameLowering::adjustForSegmentedStacks(
1629 MachineFunction &MF, MachineBasicBlock &PrologueMBB) const {
1630 MachineFrameInfo *MFI = MF.getFrameInfo();
1632 unsigned TlsReg, TlsOffset;
1635 unsigned ScratchReg = GetScratchRegister(Is64Bit, IsLP64, MF, true);
1636 assert(!MF.getRegInfo().isLiveIn(ScratchReg) &&
1637 "Scratch register is live-in");
1639 if (MF.getFunction()->isVarArg())
1640 report_fatal_error("Segmented stacks do not support vararg functions.");
1641 if (!STI.isTargetLinux() && !STI.isTargetDarwin() && !STI.isTargetWin32() &&
1642 !STI.isTargetWin64() && !STI.isTargetFreeBSD() &&
1643 !STI.isTargetDragonFly())
1644 report_fatal_error("Segmented stacks not supported on this platform.");
1646 // Eventually StackSize will be calculated by a link-time pass; which will
1647 // also decide whether checking code needs to be injected into this particular
1649 StackSize = MFI->getStackSize();
1651 // Do not generate a prologue for functions with a stack of size zero
1655 MachineBasicBlock *allocMBB = MF.CreateMachineBasicBlock();
1656 MachineBasicBlock *checkMBB = MF.CreateMachineBasicBlock();
1657 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1658 bool IsNested = false;
1660 // We need to know if the function has a nest argument only in 64 bit mode.
1662 IsNested = HasNestArgument(&MF);
1664 // The MOV R10, RAX needs to be in a different block, since the RET we emit in
1665 // allocMBB needs to be last (terminating) instruction.
1667 for (const auto &LI : PrologueMBB.liveins()) {
1668 allocMBB->addLiveIn(LI);
1669 checkMBB->addLiveIn(LI);
1673 allocMBB->addLiveIn(IsLP64 ? X86::R10 : X86::R10D);
1675 MF.push_front(allocMBB);
1676 MF.push_front(checkMBB);
1678 // When the frame size is less than 256 we just compare the stack
1679 // boundary directly to the value of the stack pointer, per gcc.
1680 bool CompareStackPointer = StackSize < kSplitStackAvailable;
1682 // Read the limit off the current stacklet off the stack_guard location.
1684 if (STI.isTargetLinux()) {
1686 TlsOffset = IsLP64 ? 0x70 : 0x40;
1687 } else if (STI.isTargetDarwin()) {
1689 TlsOffset = 0x60 + 90*8; // See pthread_machdep.h. Steal TLS slot 90.
1690 } else if (STI.isTargetWin64()) {
1692 TlsOffset = 0x28; // pvArbitrary, reserved for application use
1693 } else if (STI.isTargetFreeBSD()) {
1696 } else if (STI.isTargetDragonFly()) {
1698 TlsOffset = 0x20; // use tls_tcb.tcb_segstack
1700 report_fatal_error("Segmented stacks not supported on this platform.");
1703 if (CompareStackPointer)
1704 ScratchReg = IsLP64 ? X86::RSP : X86::ESP;
1706 BuildMI(checkMBB, DL, TII.get(IsLP64 ? X86::LEA64r : X86::LEA64_32r), ScratchReg).addReg(X86::RSP)
1707 .addImm(1).addReg(0).addImm(-StackSize).addReg(0);
1709 BuildMI(checkMBB, DL, TII.get(IsLP64 ? X86::CMP64rm : X86::CMP32rm)).addReg(ScratchReg)
1710 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg);
1712 if (STI.isTargetLinux()) {
1715 } else if (STI.isTargetDarwin()) {
1717 TlsOffset = 0x48 + 90*4;
1718 } else if (STI.isTargetWin32()) {
1720 TlsOffset = 0x14; // pvArbitrary, reserved for application use
1721 } else if (STI.isTargetDragonFly()) {
1723 TlsOffset = 0x10; // use tls_tcb.tcb_segstack
1724 } else if (STI.isTargetFreeBSD()) {
1725 report_fatal_error("Segmented stacks not supported on FreeBSD i386.");
1727 report_fatal_error("Segmented stacks not supported on this platform.");
1730 if (CompareStackPointer)
1731 ScratchReg = X86::ESP;
1733 BuildMI(checkMBB, DL, TII.get(X86::LEA32r), ScratchReg).addReg(X86::ESP)
1734 .addImm(1).addReg(0).addImm(-StackSize).addReg(0);
1736 if (STI.isTargetLinux() || STI.isTargetWin32() || STI.isTargetWin64() ||
1737 STI.isTargetDragonFly()) {
1738 BuildMI(checkMBB, DL, TII.get(X86::CMP32rm)).addReg(ScratchReg)
1739 .addReg(0).addImm(0).addReg(0).addImm(TlsOffset).addReg(TlsReg);
1740 } else if (STI.isTargetDarwin()) {
1742 // TlsOffset doesn't fit into a mod r/m byte so we need an extra register.
1743 unsigned ScratchReg2;
1745 if (CompareStackPointer) {
1746 // The primary scratch register is available for holding the TLS offset.
1747 ScratchReg2 = GetScratchRegister(Is64Bit, IsLP64, MF, true);
1748 SaveScratch2 = false;
1750 // Need to use a second register to hold the TLS offset
1751 ScratchReg2 = GetScratchRegister(Is64Bit, IsLP64, MF, false);
1753 // Unfortunately, with fastcc the second scratch register may hold an
1755 SaveScratch2 = MF.getRegInfo().isLiveIn(ScratchReg2);
1758 // If Scratch2 is live-in then it needs to be saved.
1759 assert((!MF.getRegInfo().isLiveIn(ScratchReg2) || SaveScratch2) &&
1760 "Scratch register is live-in and not saved");
1763 BuildMI(checkMBB, DL, TII.get(X86::PUSH32r))
1764 .addReg(ScratchReg2, RegState::Kill);
1766 BuildMI(checkMBB, DL, TII.get(X86::MOV32ri), ScratchReg2)
1768 BuildMI(checkMBB, DL, TII.get(X86::CMP32rm))
1770 .addReg(ScratchReg2).addImm(1).addReg(0)
1775 BuildMI(checkMBB, DL, TII.get(X86::POP32r), ScratchReg2);
1779 // This jump is taken if SP >= (Stacklet Limit + Stack Space required).
1780 // It jumps to normal execution of the function body.
1781 BuildMI(checkMBB, DL, TII.get(X86::JA_1)).addMBB(&PrologueMBB);
1783 // On 32 bit we first push the arguments size and then the frame size. On 64
1784 // bit, we pass the stack frame size in r10 and the argument size in r11.
1786 // Functions with nested arguments use R10, so it needs to be saved across
1787 // the call to _morestack
1789 const unsigned RegAX = IsLP64 ? X86::RAX : X86::EAX;
1790 const unsigned Reg10 = IsLP64 ? X86::R10 : X86::R10D;
1791 const unsigned Reg11 = IsLP64 ? X86::R11 : X86::R11D;
1792 const unsigned MOVrr = IsLP64 ? X86::MOV64rr : X86::MOV32rr;
1793 const unsigned MOVri = IsLP64 ? X86::MOV64ri : X86::MOV32ri;
1796 BuildMI(allocMBB, DL, TII.get(MOVrr), RegAX).addReg(Reg10);
1798 BuildMI(allocMBB, DL, TII.get(MOVri), Reg10)
1800 BuildMI(allocMBB, DL, TII.get(MOVri), Reg11)
1801 .addImm(X86FI->getArgumentStackSize());
1803 BuildMI(allocMBB, DL, TII.get(X86::PUSHi32))
1804 .addImm(X86FI->getArgumentStackSize());
1805 BuildMI(allocMBB, DL, TII.get(X86::PUSHi32))
1809 // __morestack is in libgcc
1810 if (Is64Bit && MF.getTarget().getCodeModel() == CodeModel::Large) {
1811 // Under the large code model, we cannot assume that __morestack lives
1812 // within 2^31 bytes of the call site, so we cannot use pc-relative
1813 // addressing. We cannot perform the call via a temporary register,
1814 // as the rax register may be used to store the static chain, and all
1815 // other suitable registers may be either callee-save or used for
1816 // parameter passing. We cannot use the stack at this point either
1817 // because __morestack manipulates the stack directly.
1819 // To avoid these issues, perform an indirect call via a read-only memory
1820 // location containing the address.
1822 // This solution is not perfect, as it assumes that the .rodata section
1823 // is laid out within 2^31 bytes of each function body, but this seems
1824 // to be sufficient for JIT.
1825 BuildMI(allocMBB, DL, TII.get(X86::CALL64m))
1829 .addExternalSymbol("__morestack_addr")
1831 MF.getMMI().setUsesMorestackAddr(true);
1834 BuildMI(allocMBB, DL, TII.get(X86::CALL64pcrel32))
1835 .addExternalSymbol("__morestack");
1837 BuildMI(allocMBB, DL, TII.get(X86::CALLpcrel32))
1838 .addExternalSymbol("__morestack");
1842 BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET_RESTORE_R10));
1844 BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET));
1846 allocMBB->addSuccessor(&PrologueMBB);
1848 checkMBB->addSuccessor(allocMBB);
1849 checkMBB->addSuccessor(&PrologueMBB);
1856 /// Erlang programs may need a special prologue to handle the stack size they
1857 /// might need at runtime. That is because Erlang/OTP does not implement a C
1858 /// stack but uses a custom implementation of hybrid stack/heap architecture.
1859 /// (for more information see Eric Stenman's Ph.D. thesis:
1860 /// http://publications.uu.se/uu/fulltext/nbn_se_uu_diva-2688.pdf)
1863 /// temp0 = sp - MaxStack
1864 /// if( temp0 < SP_LIMIT(P) ) goto IncStack else goto OldStart
1868 /// call inc_stack # doubles the stack space
1869 /// temp0 = sp - MaxStack
1870 /// if( temp0 < SP_LIMIT(P) ) goto IncStack else goto OldStart
1871 void X86FrameLowering::adjustForHiPEPrologue(
1872 MachineFunction &MF, MachineBasicBlock &PrologueMBB) const {
1873 MachineFrameInfo *MFI = MF.getFrameInfo();
1875 // HiPE-specific values
1876 const unsigned HipeLeafWords = 24;
1877 const unsigned CCRegisteredArgs = Is64Bit ? 6 : 5;
1878 const unsigned Guaranteed = HipeLeafWords * SlotSize;
1879 unsigned CallerStkArity = MF.getFunction()->arg_size() > CCRegisteredArgs ?
1880 MF.getFunction()->arg_size() - CCRegisteredArgs : 0;
1881 unsigned MaxStack = MFI->getStackSize() + CallerStkArity*SlotSize + SlotSize;
1883 assert(STI.isTargetLinux() &&
1884 "HiPE prologue is only supported on Linux operating systems.");
1886 // Compute the largest caller's frame that is needed to fit the callees'
1887 // frames. This 'MaxStack' is computed from:
1889 // a) the fixed frame size, which is the space needed for all spilled temps,
1890 // b) outgoing on-stack parameter areas, and
1891 // c) the minimum stack space this function needs to make available for the
1892 // functions it calls (a tunable ABI property).
1893 if (MFI->hasCalls()) {
1894 unsigned MoreStackForCalls = 0;
1896 for (MachineFunction::iterator MBBI = MF.begin(), MBBE = MF.end();
1897 MBBI != MBBE; ++MBBI)
1898 for (MachineBasicBlock::iterator MI = MBBI->begin(), ME = MBBI->end();
1903 // Get callee operand.
1904 const MachineOperand &MO = MI->getOperand(0);
1906 // Only take account of global function calls (no closures etc.).
1910 const Function *F = dyn_cast<Function>(MO.getGlobal());
1914 // Do not update 'MaxStack' for primitive and built-in functions
1915 // (encoded with names either starting with "erlang."/"bif_" or not
1916 // having a ".", such as a simple <Module>.<Function>.<Arity>, or an
1917 // "_", such as the BIF "suspend_0") as they are executed on another
1919 if (F->getName().find("erlang.") != StringRef::npos ||
1920 F->getName().find("bif_") != StringRef::npos ||
1921 F->getName().find_first_of("._") == StringRef::npos)
1924 unsigned CalleeStkArity =
1925 F->arg_size() > CCRegisteredArgs ? F->arg_size()-CCRegisteredArgs : 0;
1926 if (HipeLeafWords - 1 > CalleeStkArity)
1927 MoreStackForCalls = std::max(MoreStackForCalls,
1928 (HipeLeafWords - 1 - CalleeStkArity) * SlotSize);
1930 MaxStack += MoreStackForCalls;
1933 // If the stack frame needed is larger than the guaranteed then runtime checks
1934 // and calls to "inc_stack_0" BIF should be inserted in the assembly prologue.
1935 if (MaxStack > Guaranteed) {
1936 MachineBasicBlock *stackCheckMBB = MF.CreateMachineBasicBlock();
1937 MachineBasicBlock *incStackMBB = MF.CreateMachineBasicBlock();
1939 for (const auto &LI : PrologueMBB.liveins()) {
1940 stackCheckMBB->addLiveIn(LI);
1941 incStackMBB->addLiveIn(LI);
1944 MF.push_front(incStackMBB);
1945 MF.push_front(stackCheckMBB);
1947 unsigned ScratchReg, SPReg, PReg, SPLimitOffset;
1948 unsigned LEAop, CMPop, CALLop;
1952 LEAop = X86::LEA64r;
1953 CMPop = X86::CMP64rm;
1954 CALLop = X86::CALL64pcrel32;
1955 SPLimitOffset = 0x90;
1959 LEAop = X86::LEA32r;
1960 CMPop = X86::CMP32rm;
1961 CALLop = X86::CALLpcrel32;
1962 SPLimitOffset = 0x4c;
1965 ScratchReg = GetScratchRegister(Is64Bit, IsLP64, MF, true);
1966 assert(!MF.getRegInfo().isLiveIn(ScratchReg) &&
1967 "HiPE prologue scratch register is live-in");
1969 // Create new MBB for StackCheck:
1970 addRegOffset(BuildMI(stackCheckMBB, DL, TII.get(LEAop), ScratchReg),
1971 SPReg, false, -MaxStack);
1972 // SPLimitOffset is in a fixed heap location (pointed by BP).
1973 addRegOffset(BuildMI(stackCheckMBB, DL, TII.get(CMPop))
1974 .addReg(ScratchReg), PReg, false, SPLimitOffset);
1975 BuildMI(stackCheckMBB, DL, TII.get(X86::JAE_1)).addMBB(&PrologueMBB);
1977 // Create new MBB for IncStack:
1978 BuildMI(incStackMBB, DL, TII.get(CALLop)).
1979 addExternalSymbol("inc_stack_0");
1980 addRegOffset(BuildMI(incStackMBB, DL, TII.get(LEAop), ScratchReg),
1981 SPReg, false, -MaxStack);
1982 addRegOffset(BuildMI(incStackMBB, DL, TII.get(CMPop))
1983 .addReg(ScratchReg), PReg, false, SPLimitOffset);
1984 BuildMI(incStackMBB, DL, TII.get(X86::JLE_1)).addMBB(incStackMBB);
1986 stackCheckMBB->addSuccessor(&PrologueMBB, 99);
1987 stackCheckMBB->addSuccessor(incStackMBB, 1);
1988 incStackMBB->addSuccessor(&PrologueMBB, 99);
1989 incStackMBB->addSuccessor(incStackMBB, 1);
1996 bool X86FrameLowering::adjustStackWithPops(MachineBasicBlock &MBB,
1997 MachineBasicBlock::iterator MBBI, DebugLoc DL, int Offset) const {
2002 if (Offset % SlotSize)
2005 int NumPops = Offset / SlotSize;
2006 // This is only worth it if we have at most 2 pops.
2007 if (NumPops != 1 && NumPops != 2)
2010 // Handle only the trivial case where the adjustment directly follows
2011 // a call. This is the most common one, anyway.
2012 if (MBBI == MBB.begin())
2014 MachineBasicBlock::iterator Prev = std::prev(MBBI);
2015 if (!Prev->isCall() || !Prev->getOperand(1).isRegMask())
2019 unsigned FoundRegs = 0;
2021 auto RegMask = Prev->getOperand(1);
2024 Is64Bit ? X86::GR64_NOREX_NOSPRegClass : X86::GR32_NOREX_NOSPRegClass;
2025 // Try to find up to NumPops free registers.
2026 for (auto Candidate : RegClass) {
2028 // Poor man's liveness:
2029 // Since we're immediately after a call, any register that is clobbered
2030 // by the call and not defined by it can be considered dead.
2031 if (!RegMask.clobbersPhysReg(Candidate))
2035 for (const MachineOperand &MO : Prev->implicit_operands()) {
2036 if (MO.isReg() && MO.isDef() && MO.getReg() == Candidate) {
2045 Regs[FoundRegs++] = Candidate;
2046 if (FoundRegs == (unsigned)NumPops)
2053 // If we found only one free register, but need two, reuse the same one twice.
2054 while (FoundRegs < (unsigned)NumPops)
2055 Regs[FoundRegs++] = Regs[0];
2057 for (int i = 0; i < NumPops; ++i)
2058 BuildMI(MBB, MBBI, DL,
2059 TII.get(STI.is64Bit() ? X86::POP64r : X86::POP32r), Regs[i]);
2064 void X86FrameLowering::
2065 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
2066 MachineBasicBlock::iterator I) const {
2067 bool reserveCallFrame = hasReservedCallFrame(MF);
2068 unsigned Opcode = I->getOpcode();
2069 bool isDestroy = Opcode == TII.getCallFrameDestroyOpcode();
2070 DebugLoc DL = I->getDebugLoc();
2071 uint64_t Amount = !reserveCallFrame ? I->getOperand(0).getImm() : 0;
2072 uint64_t InternalAmt = (isDestroy || Amount) ? I->getOperand(1).getImm() : 0;
2075 if (!reserveCallFrame) {
2076 // If the stack pointer can be changed after prologue, turn the
2077 // adjcallstackup instruction into a 'sub ESP, <amt>' and the
2078 // adjcallstackdown instruction into 'add ESP, <amt>'
2080 // We need to keep the stack aligned properly. To do this, we round the
2081 // amount of space needed for the outgoing arguments up to the next
2082 // alignment boundary.
2083 unsigned StackAlign = getStackAlignment();
2084 Amount = RoundUpToAlignment(Amount, StackAlign);
2086 // If we have any exception handlers in this function, and we adjust
2087 // the SP before calls, we may need to indicate this to the unwinder,
2088 // using GNU_ARGS_SIZE. Note that this may be necessary
2089 // even when Amount == 0, because the preceding function may have
2090 // set a non-0 GNU_ARGS_SIZE.
2091 // TODO: We don't need to reset this between subsequent functions,
2092 // if it didn't change.
2093 bool HasDwarfEHHandlers =
2094 !MF.getTarget().getMCAsmInfo()->usesWindowsCFI() &&
2095 !MF.getMMI().getLandingPads().empty();
2097 if (HasDwarfEHHandlers && !isDestroy &&
2098 MF.getInfo<X86MachineFunctionInfo>()->getHasPushSequences())
2099 BuildCFI(MBB, I, DL,
\r
2100 MCCFIInstruction::createGnuArgsSize(nullptr, Amount));
\r
2105 // Factor out the amount that gets handled inside the sequence
2106 // (Pushes of argument for frame setup, callee pops for frame destroy)
2107 Amount -= InternalAmt;
2110 // Add Amount to SP to destroy a frame, and subtract to setup.
2111 int Offset = isDestroy ? Amount : -Amount;
2113 if (!(MF.getFunction()->optForMinSize() &&
2114 adjustStackWithPops(MBB, I, DL, Offset)))
2115 BuildStackAdjustment(MBB, I, DL, Offset, /*InEpilogue=*/false);
2121 if (isDestroy && InternalAmt) {
2122 // If we are performing frame pointer elimination and if the callee pops
2123 // something off the stack pointer, add it back. We do this until we have
2124 // more advanced stack pointer tracking ability.
2125 // We are not tracking the stack pointer adjustment by the callee, so make
2126 // sure we restore the stack pointer immediately after the call, there may
2127 // be spill code inserted between the CALL and ADJCALLSTACKUP instructions.
2128 MachineBasicBlock::iterator B = MBB.begin();
2129 while (I != B && !std::prev(I)->isCall())
2131 BuildStackAdjustment(MBB, I, DL, -InternalAmt, /*InEpilogue=*/false);
2135 bool X86FrameLowering::canUseAsEpilogue(const MachineBasicBlock &MBB) const {
2136 assert(MBB.getParent() && "Block is not attached to a function!");
2138 if (canUseLEAForSPInEpilogue(*MBB.getParent()))
2141 // If we cannot use LEA to adjust SP, we may need to use ADD, which
2142 // clobbers the EFLAGS. Check that none of the terminators reads the
2143 // EFLAGS, and if one uses it, conservatively assume this is not
2144 // safe to insert the epilogue here.
2145 return !terminatorsNeedFlagsAsInput(MBB);
2148 MachineBasicBlock::iterator X86FrameLowering::restoreWin32EHStackPointers(
2149 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
2150 DebugLoc DL, bool RestoreSP) const {
2151 assert(STI.isTargetWindowsMSVC() && "funclets only supported in MSVC env");
2152 assert(STI.isTargetWin32() && "EBP/ESI restoration only required on win32");
2153 assert(STI.is32Bit() && !Uses64BitFramePtr &&
2154 "restoring EBP/ESI on non-32-bit target");
2156 MachineFunction &MF = *MBB.getParent();
2157 unsigned FramePtr = TRI->getFrameRegister(MF);
2158 unsigned BasePtr = TRI->getBaseRegister();
2159 MachineModuleInfo &MMI = MF.getMMI();
2160 const Function *Fn = MF.getFunction();
2161 WinEHFuncInfo &FuncInfo = MMI.getWinEHFuncInfo(Fn);
2162 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
2163 MachineFrameInfo *MFI = MF.getFrameInfo();
2165 // FIXME: Don't set FrameSetup flag in catchret case.
2167 int FI = FuncInfo.EHRegNodeFrameIndex;
2168 int EHRegSize = MFI->getObjectSize(FI);
2171 // MOV32rm -EHRegSize(%ebp), %esp
2172 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32rm), X86::ESP),
2173 X86::EBP, true, -EHRegSize)
2174 .setMIFlag(MachineInstr::FrameSetup);
2178 int EHRegOffset = getFrameIndexReference(MF, FI, UsedReg);
2179 int EndOffset = -EHRegOffset - EHRegSize;
2180 FuncInfo.EHRegNodeEndOffset = EndOffset;
2181 assert(EndOffset >= 0 &&
2182 "end of registration object above normal EBP position!");
2184 if (UsedReg == FramePtr) {
2185 // ADD $offset, %ebp
2186 assert(UsedReg == FramePtr);
2187 unsigned ADDri = getADDriOpcode(false, EndOffset);
2188 BuildMI(MBB, MBBI, DL, TII.get(ADDri), FramePtr)
2191 .setMIFlag(MachineInstr::FrameSetup)
2195 assert(UsedReg == BasePtr);
2196 // LEA offset(%ebp), %esi
2197 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::LEA32r), BasePtr),
2198 FramePtr, false, EndOffset)
2199 .setMIFlag(MachineInstr::FrameSetup);
2200 // MOV32rm SavedEBPOffset(%esi), %ebp
2201 assert(X86FI->getHasSEHFramePtrSave());
2203 getFrameIndexReference(MF, X86FI->getSEHFramePtrSaveIndex(), UsedReg);
2204 assert(UsedReg == BasePtr);
2205 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32rm), FramePtr),
2206 UsedReg, true, Offset)
2207 .setMIFlag(MachineInstr::FrameSetup);