1 //===-- X86FrameLowering.cpp - X86 Frame Information ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of TargetFrameLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "X86FrameLowering.h"
15 #include "X86InstrBuilder.h"
16 #include "X86InstrInfo.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/ADT/SmallSet.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineModuleInfo.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/IR/DataLayout.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/MC/MCAsmInfo.h"
29 #include "llvm/MC/MCSymbol.h"
30 #include "llvm/Target/TargetOptions.h"
31 #include "llvm/Support/Debug.h"
36 X86FrameLowering::X86FrameLowering(const X86Subtarget &STI,
37 unsigned StackAlignOverride)
38 : TargetFrameLowering(StackGrowsDown, StackAlignOverride,
39 STI.is64Bit() ? -8 : -4),
40 STI(STI), TII(*STI.getInstrInfo()), TRI(STI.getRegisterInfo()) {
41 // Cache a bunch of frame-related predicates for this subtarget.
42 SlotSize = TRI->getSlotSize();
43 Is64Bit = STI.is64Bit();
44 IsLP64 = STI.isTarget64BitLP64();
45 // standard x86_64 and NaCl use 64-bit frame/stack pointers, x32 - 32-bit.
46 Uses64BitFramePtr = STI.isTarget64BitLP64() || STI.isTargetNaCl64();
47 StackPtr = TRI->getStackRegister();
50 bool X86FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
51 return !MF.getFrameInfo()->hasVarSizedObjects() &&
52 !MF.getInfo<X86MachineFunctionInfo>()->getHasPushSequences();
55 /// canSimplifyCallFramePseudos - If there is a reserved call frame, the
56 /// call frame pseudos can be simplified. Having a FP, as in the default
57 /// implementation, is not sufficient here since we can't always use it.
58 /// Use a more nuanced condition.
60 X86FrameLowering::canSimplifyCallFramePseudos(const MachineFunction &MF) const {
61 return hasReservedCallFrame(MF) ||
62 (hasFP(MF) && !TRI->needsStackRealignment(MF)) ||
63 TRI->hasBasePointer(MF);
66 // needsFrameIndexResolution - Do we need to perform FI resolution for
67 // this function. Normally, this is required only when the function
68 // has any stack objects. However, FI resolution actually has another job,
69 // not apparent from the title - it resolves callframesetup/destroy
70 // that were not simplified earlier.
71 // So, this is required for x86 functions that have push sequences even
72 // when there are no stack objects.
74 X86FrameLowering::needsFrameIndexResolution(const MachineFunction &MF) const {
75 return MF.getFrameInfo()->hasStackObjects() ||
76 MF.getInfo<X86MachineFunctionInfo>()->getHasPushSequences();
79 /// hasFP - Return true if the specified function should have a dedicated frame
80 /// pointer register. This is true if the function has variable sized allocas
81 /// or if frame pointer elimination is disabled.
82 bool X86FrameLowering::hasFP(const MachineFunction &MF) const {
83 const MachineFrameInfo *MFI = MF.getFrameInfo();
84 const MachineModuleInfo &MMI = MF.getMMI();
86 return (MF.getTarget().Options.DisableFramePointerElim(MF) ||
87 TRI->needsStackRealignment(MF) ||
88 MFI->hasVarSizedObjects() ||
89 MFI->isFrameAddressTaken() || MFI->hasOpaqueSPAdjustment() ||
90 MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
91 MMI.callsUnwindInit() || MMI.callsEHReturn() ||
92 MFI->hasStackMap() || MFI->hasPatchPoint());
95 static unsigned getSUBriOpcode(unsigned IsLP64, int64_t Imm) {
99 return X86::SUB64ri32;
102 return X86::SUB32ri8;
107 static unsigned getADDriOpcode(unsigned IsLP64, int64_t Imm) {
110 return X86::ADD64ri8;
111 return X86::ADD64ri32;
114 return X86::ADD32ri8;
119 static unsigned getSUBrrOpcode(unsigned isLP64) {
120 return isLP64 ? X86::SUB64rr : X86::SUB32rr;
123 static unsigned getADDrrOpcode(unsigned isLP64) {
124 return isLP64 ? X86::ADD64rr : X86::ADD32rr;
127 static unsigned getANDriOpcode(bool IsLP64, int64_t Imm) {
130 return X86::AND64ri8;
131 return X86::AND64ri32;
134 return X86::AND32ri8;
138 static unsigned getLEArOpcode(unsigned IsLP64) {
139 return IsLP64 ? X86::LEA64r : X86::LEA32r;
142 /// findDeadCallerSavedReg - Return a caller-saved register that isn't live
143 /// when it reaches the "return" instruction. We can then pop a stack object
144 /// to this register without worry about clobbering it.
145 static unsigned findDeadCallerSavedReg(MachineBasicBlock &MBB,
146 MachineBasicBlock::iterator &MBBI,
147 const TargetRegisterInfo *TRI,
149 const MachineFunction *MF = MBB.getParent();
150 const Function *F = MF->getFunction();
151 if (!F || MF->getMMI().callsEHReturn())
154 static const uint16_t CallerSavedRegs32Bit[] = {
155 X86::EAX, X86::EDX, X86::ECX, 0
158 static const uint16_t CallerSavedRegs64Bit[] = {
159 X86::RAX, X86::RDX, X86::RCX, X86::RSI, X86::RDI,
160 X86::R8, X86::R9, X86::R10, X86::R11, 0
163 unsigned Opc = MBBI->getOpcode();
170 case X86::TCRETURNdi:
171 case X86::TCRETURNri:
172 case X86::TCRETURNmi:
173 case X86::TCRETURNdi64:
174 case X86::TCRETURNri64:
175 case X86::TCRETURNmi64:
177 case X86::EH_RETURN64: {
178 SmallSet<uint16_t, 8> Uses;
179 for (unsigned i = 0, e = MBBI->getNumOperands(); i != e; ++i) {
180 MachineOperand &MO = MBBI->getOperand(i);
181 if (!MO.isReg() || MO.isDef())
183 unsigned Reg = MO.getReg();
186 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
190 const uint16_t *CS = Is64Bit ? CallerSavedRegs64Bit : CallerSavedRegs32Bit;
192 if (!Uses.count(*CS))
200 static bool isEAXLiveIn(MachineFunction &MF) {
201 for (MachineRegisterInfo::livein_iterator II = MF.getRegInfo().livein_begin(),
202 EE = MF.getRegInfo().livein_end(); II != EE; ++II) {
203 unsigned Reg = II->first;
205 if (Reg == X86::RAX || Reg == X86::EAX || Reg == X86::AX ||
206 Reg == X86::AH || Reg == X86::AL)
213 /// Check whether or not the terminators of \p MBB needs to read EFLAGS.
214 static bool terminatorsNeedFlagsAsInput(const MachineBasicBlock &MBB) {
215 for (const MachineInstr &MI : MBB.terminators()) {
216 bool BreakNext = false;
217 for (const MachineOperand &MO : MI.operands()) {
220 unsigned Reg = MO.getReg();
221 if (Reg != X86::EFLAGS)
224 // This terminator needs an eflag that is not defined
225 // by a previous terminator.
236 /// emitSPUpdate - Emit a series of instructions to increment / decrement the
237 /// stack pointer by a constant value.
238 void X86FrameLowering::emitSPUpdate(MachineBasicBlock &MBB,
239 MachineBasicBlock::iterator &MBBI,
240 int64_t NumBytes, bool InEpilogue) const {
241 bool isSub = NumBytes < 0;
242 uint64_t Offset = isSub ? -NumBytes : NumBytes;
244 uint64_t Chunk = (1LL << 31) - 1;
245 DebugLoc DL = MBB.findDebugLoc(MBBI);
248 if (Offset > Chunk) {
249 // Rather than emit a long series of instructions for large offsets,
250 // load the offset into a register and do one sub/add
253 if (isSub && !isEAXLiveIn(*MBB.getParent()))
254 Reg = (unsigned)(Is64Bit ? X86::RAX : X86::EAX);
256 Reg = findDeadCallerSavedReg(MBB, MBBI, TRI, Is64Bit);
259 unsigned Opc = Is64Bit ? X86::MOV64ri : X86::MOV32ri;
260 BuildMI(MBB, MBBI, DL, TII.get(Opc), Reg)
263 ? getSUBrrOpcode(Is64Bit)
264 : getADDrrOpcode(Is64Bit);
265 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
268 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
274 uint64_t ThisVal = std::min(Offset, Chunk);
275 if (ThisVal == (Is64Bit ? 8 : 4)) {
276 // Use push / pop instead.
278 ? (unsigned)(Is64Bit ? X86::RAX : X86::EAX)
279 : findDeadCallerSavedReg(MBB, MBBI, TRI, Is64Bit);
282 ? (Is64Bit ? X86::PUSH64r : X86::PUSH32r)
283 : (Is64Bit ? X86::POP64r : X86::POP32r);
284 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc))
285 .addReg(Reg, getDefRegState(!isSub) | getUndefRegState(isSub));
287 MI->setFlag(MachineInstr::FrameSetup);
293 MachineInstrBuilder MI = BuildStackAdjustment(
294 MBB, MBBI, DL, isSub ? -ThisVal : ThisVal, InEpilogue);
296 MI.setMIFlag(MachineInstr::FrameSetup);
302 MachineInstrBuilder X86FrameLowering::BuildStackAdjustment(
303 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, DebugLoc DL,
304 int64_t Offset, bool InEpilogue) const {
305 assert(Offset != 0 && "zero offset stack adjustment requested");
307 // On Atom, using LEA to adjust SP is preferred, but using it in the epilogue
311 UseLEA = STI.useLeaForSP();
313 // If we can use LEA for SP but we shouldn't, check that none
314 // of the terminators uses the eflags. Otherwise we will insert
315 // a ADD that will redefine the eflags and break the condition.
316 // Alternatively, we could move the ADD, but this may not be possible
317 // and is an optimization anyway.
318 UseLEA = canUseLEAForSPInEpilogue(*MBB.getParent());
319 if (UseLEA && !STI.useLeaForSP())
320 UseLEA = terminatorsNeedFlagsAsInput(MBB);
321 // If that assert breaks, that means we do not do the right thing
322 // in canUseAsEpilogue.
323 assert((UseLEA || !terminatorsNeedFlagsAsInput(MBB)) &&
324 "We shouldn't have allowed this insertion point");
327 MachineInstrBuilder MI;
329 MI = addRegOffset(BuildMI(MBB, MBBI, DL,
330 TII.get(getLEArOpcode(Uses64BitFramePtr)),
332 StackPtr, false, Offset);
334 bool IsSub = Offset < 0;
335 uint64_t AbsOffset = IsSub ? -Offset : Offset;
336 unsigned Opc = IsSub ? getSUBriOpcode(Uses64BitFramePtr, AbsOffset)
337 : getADDriOpcode(Uses64BitFramePtr, AbsOffset);
338 MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
341 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
346 /// mergeSPUpdatesUp - Merge two stack-manipulating instructions upper iterator.
348 void mergeSPUpdatesUp(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
349 unsigned StackPtr, uint64_t *NumBytes = nullptr) {
350 if (MBBI == MBB.begin()) return;
352 MachineBasicBlock::iterator PI = std::prev(MBBI);
353 unsigned Opc = PI->getOpcode();
354 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
355 Opc == X86::ADD32ri || Opc == X86::ADD32ri8 ||
356 Opc == X86::LEA32r || Opc == X86::LEA64_32r) &&
357 PI->getOperand(0).getReg() == StackPtr) {
359 *NumBytes += PI->getOperand(2).getImm();
361 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
362 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
363 PI->getOperand(0).getReg() == StackPtr) {
365 *NumBytes -= PI->getOperand(2).getImm();
370 int X86FrameLowering::mergeSPUpdates(MachineBasicBlock &MBB,
371 MachineBasicBlock::iterator &MBBI,
372 bool doMergeWithPrevious) const {
373 if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
374 (!doMergeWithPrevious && MBBI == MBB.end()))
377 MachineBasicBlock::iterator PI = doMergeWithPrevious ? std::prev(MBBI) : MBBI;
378 MachineBasicBlock::iterator NI = doMergeWithPrevious ? nullptr
380 unsigned Opc = PI->getOpcode();
383 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
384 Opc == X86::ADD32ri || Opc == X86::ADD32ri8 ||
385 Opc == X86::LEA32r || Opc == X86::LEA64_32r) &&
386 PI->getOperand(0).getReg() == StackPtr){
387 Offset += PI->getOperand(2).getImm();
389 if (!doMergeWithPrevious) MBBI = NI;
390 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
391 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
392 PI->getOperand(0).getReg() == StackPtr) {
393 Offset -= PI->getOperand(2).getImm();
395 if (!doMergeWithPrevious) MBBI = NI;
401 void X86FrameLowering::BuildCFI(MachineBasicBlock &MBB,
402 MachineBasicBlock::iterator MBBI, DebugLoc DL,
403 MCCFIInstruction CFIInst) const {
404 MachineFunction &MF = *MBB.getParent();
405 unsigned CFIIndex = MF.getMMI().addFrameInst(CFIInst);
406 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
407 .addCFIIndex(CFIIndex);
411 X86FrameLowering::emitCalleeSavedFrameMoves(MachineBasicBlock &MBB,
412 MachineBasicBlock::iterator MBBI,
414 MachineFunction &MF = *MBB.getParent();
415 MachineFrameInfo *MFI = MF.getFrameInfo();
416 MachineModuleInfo &MMI = MF.getMMI();
417 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
419 // Add callee saved registers to move list.
420 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
421 if (CSI.empty()) return;
423 // Calculate offsets.
424 for (std::vector<CalleeSavedInfo>::const_iterator
425 I = CSI.begin(), E = CSI.end(); I != E; ++I) {
426 int64_t Offset = MFI->getObjectOffset(I->getFrameIdx());
427 unsigned Reg = I->getReg();
429 unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true);
430 BuildCFI(MBB, MBBI, DL,
431 MCCFIInstruction::createOffset(nullptr, DwarfReg, Offset));
435 /// usesTheStack - This function checks if any of the users of EFLAGS
436 /// copies the EFLAGS. We know that the code that lowers COPY of EFLAGS has
437 /// to use the stack, and if we don't adjust the stack we clobber the first
439 /// See X86InstrInfo::copyPhysReg.
440 static bool usesTheStack(const MachineFunction &MF) {
441 const MachineRegisterInfo &MRI = MF.getRegInfo();
443 for (MachineRegisterInfo::reg_instr_iterator
444 ri = MRI.reg_instr_begin(X86::EFLAGS), re = MRI.reg_instr_end();
452 void X86FrameLowering::emitStackProbeCall(MachineFunction &MF,
453 MachineBasicBlock &MBB,
454 MachineBasicBlock::iterator MBBI,
456 bool IsLargeCodeModel = MF.getTarget().getCodeModel() == CodeModel::Large;
460 CallOp = IsLargeCodeModel ? X86::CALL64r : X86::CALL64pcrel32;
462 CallOp = X86::CALLpcrel32;
466 if (STI.isTargetCygMing()) {
467 Symbol = "___chkstk_ms";
471 } else if (STI.isTargetCygMing())
476 MachineInstrBuilder CI;
478 // All current stack probes take AX and SP as input, clobber flags, and
479 // preserve all registers. x86_64 probes leave RSP unmodified.
480 if (Is64Bit && MF.getTarget().getCodeModel() == CodeModel::Large) {
481 // For the large code model, we have to call through a register. Use R11,
482 // as it is scratch in all supported calling conventions.
483 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri), X86::R11)
484 .addExternalSymbol(Symbol);
485 CI = BuildMI(MBB, MBBI, DL, TII.get(CallOp)).addReg(X86::R11);
487 CI = BuildMI(MBB, MBBI, DL, TII.get(CallOp)).addExternalSymbol(Symbol);
490 unsigned AX = Is64Bit ? X86::RAX : X86::EAX;
491 unsigned SP = Is64Bit ? X86::RSP : X86::ESP;
492 CI.addReg(AX, RegState::Implicit)
493 .addReg(SP, RegState::Implicit)
494 .addReg(AX, RegState::Define | RegState::Implicit)
495 .addReg(SP, RegState::Define | RegState::Implicit)
496 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
499 // MSVC x64's __chkstk and cygwin/mingw's ___chkstk_ms do not adjust %rsp
500 // themselves. It also does not clobber %rax so we can reuse it when
502 BuildMI(MBB, MBBI, DL, TII.get(X86::SUB64rr), X86::RSP)
508 static unsigned calculateSetFPREG(uint64_t SPAdjust) {
509 // Win64 ABI has a less restrictive limitation of 240; 128 works equally well
510 // and might require smaller successive adjustments.
511 const uint64_t Win64MaxSEHOffset = 128;
512 uint64_t SEHFrameOffset = std::min(SPAdjust, Win64MaxSEHOffset);
513 // Win64 ABI requires 16-byte alignment for the UWOP_SET_FPREG opcode.
514 return SEHFrameOffset & -16;
517 // If we're forcing a stack realignment we can't rely on just the frame
518 // info, we need to know the ABI stack alignment as well in case we
519 // have a call out. Otherwise just make sure we have some alignment - we'll
520 // go with the minimum SlotSize.
521 uint64_t X86FrameLowering::calculateMaxStackAlign(const MachineFunction &MF) const {
522 const MachineFrameInfo *MFI = MF.getFrameInfo();
523 uint64_t MaxAlign = MFI->getMaxAlignment(); // Desired stack alignment.
524 unsigned StackAlign = getStackAlignment();
525 if (ForceStackAlign) {
527 MaxAlign = (StackAlign > MaxAlign) ? StackAlign : MaxAlign;
528 else if (MaxAlign < SlotSize)
534 void X86FrameLowering::BuildStackAlignAND(MachineBasicBlock &MBB,
535 MachineBasicBlock::iterator MBBI,
537 uint64_t MaxAlign) const {
538 uint64_t Val = -MaxAlign;
540 BuildMI(MBB, MBBI, DL, TII.get(getANDriOpcode(Uses64BitFramePtr, Val)),
544 .setMIFlag(MachineInstr::FrameSetup);
546 // The EFLAGS implicit def is dead.
547 MI->getOperand(3).setIsDead();
550 /// emitPrologue - Push callee-saved registers onto the stack, which
551 /// automatically adjust the stack pointer. Adjust the stack pointer to allocate
552 /// space for local variables. Also emit labels used by the exception handler to
553 /// generate the exception handling frames.
556 Here's a gist of what gets emitted:
558 ; Establish frame pointer, if needed
561 .cfi_def_cfa_offset 16
562 .cfi_offset %rbp, -16
565 .cfi_def_cfa_register %rbp
567 ; Spill general-purpose registers
568 [for all callee-saved GPRs]
571 .cfi_def_cfa_offset (offset from RETADDR)
574 ; If the required stack alignment > default stack alignment
575 ; rsp needs to be re-aligned. This creates a "re-alignment gap"
576 ; of unknown size in the stack frame.
577 [if stack needs re-alignment]
580 ; Allocate space for locals
581 [if target is Windows and allocated space > 4096 bytes]
582 ; Windows needs special care for allocations larger
585 call ___chkstk_ms/___chkstk
591 .seh_stackalloc (size of XMM spill slots)
592 .seh_setframe %rbp, SEHFrameOffset ; = size of all spill slots
597 ; Note, that while only Windows 64 ABI specifies XMMs as callee-preserved,
598 ; they may get spilled on any platform, if the current function
599 ; calls @llvm.eh.unwind.init
601 [for all callee-saved XMM registers]
602 movaps %<xmm reg>, -MMM(%rbp)
603 [for all callee-saved XMM registers]
604 .seh_savexmm %<xmm reg>, (-MMM + SEHFrameOffset)
605 ; i.e. the offset relative to (%rbp - SEHFrameOffset)
607 [for all callee-saved XMM registers]
608 movaps %<xmm reg>, KKK(%rsp)
609 [for all callee-saved XMM registers]
610 .seh_savexmm %<xmm reg>, KKK
614 [if needs base pointer]
616 [if needs to restore base pointer]
621 [for all callee-saved registers]
622 .cfi_offset %<reg>, (offset from %rbp)
624 .cfi_def_cfa_offset (offset from RETADDR)
625 [for all callee-saved registers]
626 .cfi_offset %<reg>, (offset from %rsp)
629 - .seh directives are emitted only for Windows 64 ABI
630 - .cfi directives are emitted for all other ABIs
631 - for 32-bit code, substitute %e?? registers for %r??
634 void X86FrameLowering::emitPrologue(MachineFunction &MF,
635 MachineBasicBlock &MBB) const {
636 assert(&STI == &MF.getSubtarget<X86Subtarget>() &&
637 "MF used frame lowering for wrong subtarget");
638 MachineBasicBlock::iterator MBBI = MBB.begin();
639 MachineFrameInfo *MFI = MF.getFrameInfo();
640 const Function *Fn = MF.getFunction();
641 MachineModuleInfo &MMI = MF.getMMI();
642 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
643 uint64_t MaxAlign = calculateMaxStackAlign(MF); // Desired stack alignment.
644 uint64_t StackSize = MFI->getStackSize(); // Number of bytes to allocate.
645 bool HasFP = hasFP(MF);
646 bool IsWin64CC = STI.isCallingConvWin64(Fn->getCallingConv());
647 bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
648 bool NeedsWinCFI = IsWin64Prologue && Fn->needsUnwindTableEntry();
650 !IsWin64Prologue && (MMI.hasDebugInfo() || Fn->needsUnwindTableEntry());
651 unsigned FramePtr = TRI->getFrameRegister(MF);
652 const unsigned MachineFramePtr =
653 STI.isTarget64BitILP32()
654 ? getX86SubSuperRegister(FramePtr, MVT::i64, false)
656 unsigned BasePtr = TRI->getBaseRegister();
659 // Add RETADDR move area to callee saved frame size.
660 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
661 if (TailCallReturnAddrDelta && IsWin64Prologue)
662 report_fatal_error("Can't handle guaranteed tail call under win64 yet");
664 if (TailCallReturnAddrDelta < 0)
665 X86FI->setCalleeSavedFrameSize(
666 X86FI->getCalleeSavedFrameSize() - TailCallReturnAddrDelta);
668 bool UseStackProbe = (STI.isOSWindows() && !STI.isTargetMachO());
670 // The default stack probe size is 4096 if the function has no stackprobesize
672 unsigned StackProbeSize = 4096;
673 if (Fn->hasFnAttribute("stack-probe-size"))
674 Fn->getFnAttribute("stack-probe-size")
676 .getAsInteger(0, StackProbeSize);
678 // If this is x86-64 and the Red Zone is not disabled, if we are a leaf
679 // function, and use up to 128 bytes of stack space, don't have a frame
680 // pointer, calls, or dynamic alloca then we do not need to adjust the
681 // stack pointer (we fit in the Red Zone). We also check that we don't
682 // push and pop from the stack.
683 if (Is64Bit && !Fn->hasFnAttribute(Attribute::NoRedZone) &&
684 !TRI->needsStackRealignment(MF) &&
685 !MFI->hasVarSizedObjects() && // No dynamic alloca.
686 !MFI->adjustsStack() && // No calls.
687 !IsWin64CC && // Win64 has no Red Zone
688 !usesTheStack(MF) && // Don't push and pop.
689 !MF.shouldSplitStack()) { // Regular stack
690 uint64_t MinSize = X86FI->getCalleeSavedFrameSize();
691 if (HasFP) MinSize += SlotSize;
692 StackSize = std::max(MinSize, StackSize > 128 ? StackSize - 128 : 0);
693 MFI->setStackSize(StackSize);
696 // Insert stack pointer adjustment for later moving of return addr. Only
697 // applies to tail call optimized functions where the callee argument stack
698 // size is bigger than the callers.
699 if (TailCallReturnAddrDelta < 0) {
700 BuildStackAdjustment(MBB, MBBI, DL, TailCallReturnAddrDelta,
701 /*InEpilogue=*/false)
702 .setMIFlag(MachineInstr::FrameSetup);
705 // Mapping for machine moves:
707 // DST: VirtualFP AND
708 // SRC: VirtualFP => DW_CFA_def_cfa_offset
709 // ELSE => DW_CFA_def_cfa
711 // SRC: VirtualFP AND
712 // DST: Register => DW_CFA_def_cfa_register
715 // OFFSET < 0 => DW_CFA_offset_extended_sf
716 // REG < 64 => DW_CFA_offset + Reg
717 // ELSE => DW_CFA_offset_extended
719 uint64_t NumBytes = 0;
720 int stackGrowth = -SlotSize;
723 // Calculate required stack adjustment.
724 uint64_t FrameSize = StackSize - SlotSize;
725 // If required, include space for extra hidden slot for stashing base pointer.
726 if (X86FI->getRestoreBasePointer())
727 FrameSize += SlotSize;
729 NumBytes = FrameSize - X86FI->getCalleeSavedFrameSize();
731 // Callee-saved registers are pushed on stack before the stack is realigned.
732 if (TRI->needsStackRealignment(MF) && !IsWin64Prologue)
733 NumBytes = RoundUpToAlignment(NumBytes, MaxAlign);
735 // Get the offset of the stack slot for the EBP register, which is
736 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
737 // Update the frame offset adjustment.
738 MFI->setOffsetAdjustment(-NumBytes);
740 // Save EBP/RBP into the appropriate stack slot.
741 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
742 .addReg(MachineFramePtr, RegState::Kill)
743 .setMIFlag(MachineInstr::FrameSetup);
746 // Mark the place where EBP/RBP was saved.
747 // Define the current CFA rule to use the provided offset.
749 BuildCFI(MBB, MBBI, DL,
750 MCCFIInstruction::createDefCfaOffset(nullptr, 2 * stackGrowth));
752 // Change the rule for the FramePtr to be an "offset" rule.
753 unsigned DwarfFramePtr = TRI->getDwarfRegNum(MachineFramePtr, true);
754 BuildCFI(MBB, MBBI, DL, MCCFIInstruction::createOffset(
755 nullptr, DwarfFramePtr, 2 * stackGrowth));
759 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_PushReg))
761 .setMIFlag(MachineInstr::FrameSetup);
764 if (!IsWin64Prologue) {
765 // Update EBP with the new base value.
766 BuildMI(MBB, MBBI, DL,
767 TII.get(Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr),
770 .setMIFlag(MachineInstr::FrameSetup);
774 // Mark effective beginning of when frame pointer becomes valid.
775 // Define the current CFA to use the EBP/RBP register.
776 unsigned DwarfFramePtr = TRI->getDwarfRegNum(MachineFramePtr, true);
777 BuildCFI(MBB, MBBI, DL,
778 MCCFIInstruction::createDefCfaRegister(nullptr, DwarfFramePtr));
781 // Mark the FramePtr as live-in in every block.
782 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
783 I->addLiveIn(MachineFramePtr);
785 NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
788 // Skip the callee-saved push instructions.
789 bool PushedRegs = false;
790 int StackOffset = 2 * stackGrowth;
792 while (MBBI != MBB.end() &&
793 MBBI->getFlag(MachineInstr::FrameSetup) &&
794 (MBBI->getOpcode() == X86::PUSH32r ||
795 MBBI->getOpcode() == X86::PUSH64r)) {
797 unsigned Reg = MBBI->getOperand(0).getReg();
800 if (!HasFP && NeedsDwarfCFI) {
801 // Mark callee-saved push instruction.
802 // Define the current CFA rule to use the provided offset.
804 BuildCFI(MBB, MBBI, DL,
805 MCCFIInstruction::createDefCfaOffset(nullptr, StackOffset));
806 StackOffset += stackGrowth;
810 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_PushReg)).addImm(Reg).setMIFlag(
811 MachineInstr::FrameSetup);
815 // Realign stack after we pushed callee-saved registers (so that we'll be
816 // able to calculate their offsets from the frame pointer).
817 // Don't do this for Win64, it needs to realign the stack after the prologue.
818 if (!IsWin64Prologue && TRI->needsStackRealignment(MF)) {
819 assert(HasFP && "There should be a frame pointer if stack is realigned.");
820 BuildStackAlignAND(MBB, MBBI, DL, MaxAlign);
823 // If there is an SUB32ri of ESP immediately before this instruction, merge
824 // the two. This can be the case when tail call elimination is enabled and
825 // the callee has more arguments then the caller.
826 NumBytes -= mergeSPUpdates(MBB, MBBI, true);
828 // Adjust stack pointer: ESP -= numbytes.
830 // Windows and cygwin/mingw require a prologue helper routine when allocating
831 // more than 4K bytes on the stack. Windows uses __chkstk and cygwin/mingw
832 // uses __alloca. __alloca and the 32-bit version of __chkstk will probe the
833 // stack and adjust the stack pointer in one go. The 64-bit version of
834 // __chkstk is only responsible for probing the stack. The 64-bit prologue is
835 // responsible for adjusting the stack pointer. Touching the stack at 4K
836 // increments is necessary to ensure that the guard pages used by the OS
837 // virtual memory manager are allocated in correct sequence.
838 uint64_t AlignedNumBytes = NumBytes;
839 if (IsWin64Prologue && TRI->needsStackRealignment(MF))
840 AlignedNumBytes = RoundUpToAlignment(AlignedNumBytes, MaxAlign);
841 if (AlignedNumBytes >= StackProbeSize && UseStackProbe) {
842 // Check whether EAX is livein for this function.
843 bool isEAXAlive = isEAXLiveIn(MF);
846 // Sanity check that EAX is not livein for this function.
847 // It should not be, so throw an assert.
848 assert(!Is64Bit && "EAX is livein in x64 case!");
851 BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH32r))
852 .addReg(X86::EAX, RegState::Kill)
853 .setMIFlag(MachineInstr::FrameSetup);
857 // Handle the 64-bit Windows ABI case where we need to call __chkstk.
858 // Function prologue is responsible for adjusting the stack pointer.
859 if (isUInt<32>(NumBytes)) {
860 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
862 .setMIFlag(MachineInstr::FrameSetup);
863 } else if (isInt<32>(NumBytes)) {
864 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri32), X86::RAX)
866 .setMIFlag(MachineInstr::FrameSetup);
868 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri), X86::RAX)
870 .setMIFlag(MachineInstr::FrameSetup);
873 // Allocate NumBytes-4 bytes on stack in case of isEAXAlive.
874 // We'll also use 4 already allocated bytes for EAX.
875 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
876 .addImm(isEAXAlive ? NumBytes - 4 : NumBytes)
877 .setMIFlag(MachineInstr::FrameSetup);
880 // Save a pointer to the MI where we set AX.
881 MachineBasicBlock::iterator SetRAX = MBBI;
884 // Call __chkstk, __chkstk_ms, or __alloca.
885 emitStackProbeCall(MF, MBB, MBBI, DL);
887 // Apply the frame setup flag to all inserted instrs.
888 for (; SetRAX != MBBI; ++SetRAX)
889 SetRAX->setFlag(MachineInstr::FrameSetup);
893 MachineInstr *MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV32rm),
895 StackPtr, false, NumBytes - 4);
896 MI->setFlag(MachineInstr::FrameSetup);
897 MBB.insert(MBBI, MI);
899 } else if (NumBytes) {
900 emitSPUpdate(MBB, MBBI, -(int64_t)NumBytes, /*InEpilogue=*/false);
903 if (NeedsWinCFI && NumBytes)
904 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_StackAlloc))
906 .setMIFlag(MachineInstr::FrameSetup);
908 int SEHFrameOffset = 0;
909 if (IsWin64Prologue && HasFP) {
910 SEHFrameOffset = calculateSetFPREG(NumBytes);
912 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::LEA64r), FramePtr),
913 StackPtr, false, SEHFrameOffset);
915 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64rr), FramePtr).addReg(StackPtr);
918 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_SetFrame))
920 .addImm(SEHFrameOffset)
921 .setMIFlag(MachineInstr::FrameSetup);
924 while (MBBI != MBB.end() && MBBI->getFlag(MachineInstr::FrameSetup)) {
925 const MachineInstr *FrameInstr = &*MBBI;
930 if (unsigned Reg = TII.isStoreToStackSlot(FrameInstr, FI)) {
931 if (X86::FR64RegClass.contains(Reg)) {
932 int Offset = getFrameIndexOffset(MF, FI);
933 Offset += SEHFrameOffset;
935 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_SaveXMM))
938 .setMIFlag(MachineInstr::FrameSetup);
945 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_EndPrologue))
946 .setMIFlag(MachineInstr::FrameSetup);
948 // Realign stack after we spilled callee-saved registers (so that we'll be
949 // able to calculate their offsets from the frame pointer).
950 // Win64 requires aligning the stack after the prologue.
951 if (IsWin64Prologue && TRI->needsStackRealignment(MF)) {
952 assert(HasFP && "There should be a frame pointer if stack is realigned.");
953 BuildStackAlignAND(MBB, MBBI, DL, MaxAlign);
956 // If we need a base pointer, set it up here. It's whatever the value
957 // of the stack pointer is at this point. Any variable size objects
958 // will be allocated after this, so we can still use the base pointer
959 // to reference locals.
960 if (TRI->hasBasePointer(MF)) {
961 // Update the base pointer with the current stack pointer.
962 unsigned Opc = Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr;
963 BuildMI(MBB, MBBI, DL, TII.get(Opc), BasePtr)
965 .setMIFlag(MachineInstr::FrameSetup);
966 if (X86FI->getRestoreBasePointer()) {
967 // Stash value of base pointer. Saving RSP instead of EBP shortens
968 // dependence chain. Used by SjLj EH.
969 unsigned Opm = Uses64BitFramePtr ? X86::MOV64mr : X86::MOV32mr;
970 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opm)),
971 FramePtr, true, X86FI->getRestoreBasePointerOffset())
973 .setMIFlag(MachineInstr::FrameSetup);
976 if (X86FI->getHasSEHFramePtrSave()) {
977 // Stash the value of the frame pointer relative to the base pointer for
978 // Win32 EH. This supports Win32 EH, which does the inverse of the above:
979 // it recovers the frame pointer from the base pointer rather than the
981 unsigned Opm = Uses64BitFramePtr ? X86::MOV64mr : X86::MOV32mr;
982 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opm)), BasePtr, true,
983 getFrameIndexOffset(MF, X86FI->getSEHFramePtrSaveIndex()))
985 .setMIFlag(MachineInstr::FrameSetup);
989 if (((!HasFP && NumBytes) || PushedRegs) && NeedsDwarfCFI) {
990 // Mark end of stack pointer adjustment.
991 if (!HasFP && NumBytes) {
992 // Define the current CFA rule to use the provided offset.
994 BuildCFI(MBB, MBBI, DL, MCCFIInstruction::createDefCfaOffset(
995 nullptr, -StackSize + stackGrowth));
998 // Emit DWARF info specifying the offsets of the callee-saved registers.
1000 emitCalleeSavedFrameMoves(MBB, MBBI, DL);
1004 bool X86FrameLowering::canUseLEAForSPInEpilogue(
1005 const MachineFunction &MF) const {
1006 // We can't use LEA instructions for adjusting the stack pointer if this is a
1007 // leaf function in the Win64 ABI. Only ADD instructions may be used to
1008 // deallocate the stack.
1009 // This means that we can use LEA for SP in two situations:
1010 // 1. We *aren't* using the Win64 ABI which means we are free to use LEA.
1011 // 2. We *have* a frame pointer which means we are permitted to use LEA.
1012 return !MF.getTarget().getMCAsmInfo()->usesWindowsCFI() || hasFP(MF);
1015 void X86FrameLowering::emitEpilogue(MachineFunction &MF,
1016 MachineBasicBlock &MBB) const {
1017 const MachineFrameInfo *MFI = MF.getFrameInfo();
1018 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1019 MachineBasicBlock::iterator MBBI = MBB.getFirstTerminator();
1021 if (MBBI != MBB.end())
1022 DL = MBBI->getDebugLoc();
1023 // standard x86_64 and NaCl use 64-bit frame/stack pointers, x32 - 32-bit.
1024 const bool Is64BitILP32 = STI.isTarget64BitILP32();
1025 unsigned FramePtr = TRI->getFrameRegister(MF);
1026 unsigned MachineFramePtr =
1027 Is64BitILP32 ? getX86SubSuperRegister(FramePtr, MVT::i64, false)
1030 bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
1032 IsWin64Prologue && MF.getFunction()->needsUnwindTableEntry();
1034 // Get the number of bytes to allocate from the FrameInfo.
1035 uint64_t StackSize = MFI->getStackSize();
1036 uint64_t MaxAlign = calculateMaxStackAlign(MF);
1037 unsigned CSSize = X86FI->getCalleeSavedFrameSize();
1038 uint64_t NumBytes = 0;
1041 // Calculate required stack adjustment.
1042 uint64_t FrameSize = StackSize - SlotSize;
1043 NumBytes = FrameSize - CSSize;
1045 // Callee-saved registers were pushed on stack before the stack was
1047 if (TRI->needsStackRealignment(MF) && !IsWin64Prologue)
1048 NumBytes = RoundUpToAlignment(FrameSize, MaxAlign);
1051 BuildMI(MBB, MBBI, DL,
1052 TII.get(Is64Bit ? X86::POP64r : X86::POP32r), MachineFramePtr);
1054 NumBytes = StackSize - CSSize;
1056 uint64_t SEHStackAllocAmt = NumBytes;
1058 // Skip the callee-saved pop instructions.
1059 while (MBBI != MBB.begin()) {
1060 MachineBasicBlock::iterator PI = std::prev(MBBI);
1061 unsigned Opc = PI->getOpcode();
1063 if (Opc != X86::POP32r && Opc != X86::POP64r && Opc != X86::DBG_VALUE &&
1064 !PI->isTerminator())
1069 MachineBasicBlock::iterator FirstCSPop = MBBI;
1071 if (MBBI != MBB.end())
1072 DL = MBBI->getDebugLoc();
1074 // If there is an ADD32ri or SUB32ri of ESP immediately before this
1075 // instruction, merge the two instructions.
1076 if (NumBytes || MFI->hasVarSizedObjects())
1077 mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
1079 // If dynamic alloca is used, then reset esp to point to the last callee-saved
1080 // slot before popping them off! Same applies for the case, when stack was
1082 if (TRI->needsStackRealignment(MF) || MFI->hasVarSizedObjects()) {
1083 if (TRI->needsStackRealignment(MF))
1085 unsigned SEHFrameOffset = calculateSetFPREG(SEHStackAllocAmt);
1086 uint64_t LEAAmount =
1087 IsWin64Prologue ? SEHStackAllocAmt - SEHFrameOffset : -CSSize;
1089 // There are only two legal forms of epilogue:
1090 // - add SEHAllocationSize, %rsp
1091 // - lea SEHAllocationSize(%FramePtr), %rsp
1093 // 'mov %FramePtr, %rsp' will not be recognized as an epilogue sequence.
1094 // However, we may use this sequence if we have a frame pointer because the
1095 // effects of the prologue can safely be undone.
1096 if (LEAAmount != 0) {
1097 unsigned Opc = getLEArOpcode(Uses64BitFramePtr);
1098 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr),
1099 FramePtr, false, LEAAmount);
1102 unsigned Opc = (Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr);
1103 BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
1107 } else if (NumBytes) {
1108 // Adjust stack pointer back: ESP += numbytes.
1109 emitSPUpdate(MBB, MBBI, NumBytes, /*InEpilogue=*/true);
1113 // Windows unwinder will not invoke function's exception handler if IP is
1114 // either in prologue or in epilogue. This behavior causes a problem when a
1115 // call immediately precedes an epilogue, because the return address points
1116 // into the epilogue. To cope with that, we insert an epilogue marker here,
1117 // then replace it with a 'nop' if it ends up immediately after a CALL in the
1118 // final emitted code.
1120 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_Epilogue));
1122 // Add the return addr area delta back since we are not tail calling.
1123 int Offset = -1 * X86FI->getTCReturnAddrDelta();
1124 assert(Offset >= 0 && "TCDelta should never be positive");
1126 MBBI = MBB.getFirstTerminator();
1128 // Check for possible merge with preceding ADD instruction.
1129 Offset += mergeSPUpdates(MBB, MBBI, true);
1130 emitSPUpdate(MBB, MBBI, Offset, /*InEpilogue=*/true);
1134 int X86FrameLowering::getFrameIndexOffset(const MachineFunction &MF,
1136 const MachineFrameInfo *MFI = MF.getFrameInfo();
1137 // Offset will hold the offset from the stack pointer at function entry to the
1139 // We need to factor in additional offsets applied during the prologue to the
1140 // frame, base, and stack pointer depending on which is used.
1141 int Offset = MFI->getObjectOffset(FI) - getOffsetOfLocalArea();
1142 const X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1143 unsigned CSSize = X86FI->getCalleeSavedFrameSize();
1144 uint64_t StackSize = MFI->getStackSize();
1145 bool HasFP = hasFP(MF);
1146 bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
1147 int64_t FPDelta = 0;
1149 if (IsWin64Prologue) {
1150 assert(!MFI->hasCalls() || (StackSize % 16) == 8);
1152 // Calculate required stack adjustment.
1153 uint64_t FrameSize = StackSize - SlotSize;
1154 // If required, include space for extra hidden slot for stashing base pointer.
1155 if (X86FI->getRestoreBasePointer())
1156 FrameSize += SlotSize;
1157 uint64_t NumBytes = FrameSize - CSSize;
1159 uint64_t SEHFrameOffset = calculateSetFPREG(NumBytes);
1160 if (FI && FI == X86FI->getFAIndex())
1161 return -SEHFrameOffset;
1163 // FPDelta is the offset from the "traditional" FP location of the old base
1164 // pointer followed by return address and the location required by the
1165 // restricted Win64 prologue.
1166 // Add FPDelta to all offsets below that go through the frame pointer.
1167 FPDelta = FrameSize - SEHFrameOffset;
1168 assert((!MFI->hasCalls() || (FPDelta % 16) == 0) &&
1169 "FPDelta isn't aligned per the Win64 ABI!");
1173 if (TRI->hasBasePointer(MF)) {
1174 assert(HasFP && "VLAs and dynamic stack realign, but no FP?!");
1176 // Skip the saved EBP.
1177 return Offset + SlotSize + FPDelta;
1179 assert((-(Offset + StackSize)) % MFI->getObjectAlignment(FI) == 0);
1180 return Offset + StackSize;
1182 } else if (TRI->needsStackRealignment(MF)) {
1184 // Skip the saved EBP.
1185 return Offset + SlotSize + FPDelta;
1187 assert((-(Offset + StackSize)) % MFI->getObjectAlignment(FI) == 0);
1188 return Offset + StackSize;
1190 // FIXME: Support tail calls
1193 return Offset + StackSize;
1195 // Skip the saved EBP.
1198 // Skip the RETADDR move area
1199 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
1200 if (TailCallReturnAddrDelta < 0)
1201 Offset -= TailCallReturnAddrDelta;
1204 return Offset + FPDelta;
1207 int X86FrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI,
1208 unsigned &FrameReg) const {
1209 // We can't calculate offset from frame pointer if the stack is realigned,
1210 // so enforce usage of stack/base pointer. The base pointer is used when we
1211 // have dynamic allocas in addition to dynamic realignment.
1212 if (TRI->hasBasePointer(MF))
1213 FrameReg = TRI->getBaseRegister();
1214 else if (TRI->needsStackRealignment(MF))
1215 FrameReg = TRI->getStackRegister();
1217 FrameReg = TRI->getFrameRegister(MF);
1218 return getFrameIndexOffset(MF, FI);
1221 // Simplified from getFrameIndexOffset keeping only StackPointer cases
1222 int X86FrameLowering::getFrameIndexOffsetFromSP(const MachineFunction &MF, int FI) const {
1223 const MachineFrameInfo *MFI = MF.getFrameInfo();
1224 // Does not include any dynamic realign.
1225 const uint64_t StackSize = MFI->getStackSize();
1228 // Note: LLVM arranges the stack as:
1229 // Args > Saved RetPC (<--FP) > CSRs > dynamic alignment (<--BP)
1230 // > "Stack Slots" (<--SP)
1231 // We can always address StackSlots from RSP. We can usually (unless
1232 // needsStackRealignment) address CSRs from RSP, but sometimes need to
1233 // address them from RBP. FixedObjects can be placed anywhere in the stack
1234 // frame depending on their specific requirements (i.e. we can actually
1235 // refer to arguments to the function which are stored in the *callers*
1236 // frame). As a result, THE RESULT OF THIS CALL IS MEANINGLESS FOR CSRs
1237 // AND FixedObjects IFF needsStackRealignment or hasVarSizedObject.
1239 assert(!TRI->hasBasePointer(MF) && "we don't handle this case");
1241 // We don't handle tail calls, and shouldn't be seeing them
1243 int TailCallReturnAddrDelta =
1244 MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta();
1245 assert(!(TailCallReturnAddrDelta < 0) && "we don't handle this case!");
1249 // This is how the math works out:
1251 // %rsp grows (i.e. gets lower) left to right. Each box below is
1252 // one word (eight bytes). Obj0 is the stack slot we're trying to
1255 // ----------------------------------
1256 // | BP | Obj0 | Obj1 | ... | ObjN |
1257 // ----------------------------------
1261 // A is the incoming stack pointer.
1262 // (B - A) is the local area offset (-8 for x86-64) [1]
1263 // (C - A) is the Offset returned by MFI->getObjectOffset for Obj0 [2]
1265 // |(E - B)| is the StackSize (absolute value, positive). For a
1266 // stack that grown down, this works out to be (B - E). [3]
1268 // E is also the value of %rsp after stack has been set up, and we
1269 // want (C - E) -- the value we can add to %rsp to get to Obj0. Now
1270 // (C - E) == (C - A) - (B - A) + (B - E)
1271 // { Using [1], [2] and [3] above }
1272 // == getObjectOffset - LocalAreaOffset + StackSize
1275 // Get the Offset from the StackPointer
1276 int Offset = MFI->getObjectOffset(FI) - getOffsetOfLocalArea();
1278 return Offset + StackSize;
1280 // Simplified from getFrameIndexReference keeping only StackPointer cases
1281 int X86FrameLowering::getFrameIndexReferenceFromSP(const MachineFunction &MF,
1283 unsigned &FrameReg) const {
1284 assert(!TRI->hasBasePointer(MF) && "we don't handle this case");
1286 FrameReg = TRI->getStackRegister();
1287 return getFrameIndexOffsetFromSP(MF, FI);
1290 bool X86FrameLowering::assignCalleeSavedSpillSlots(
1291 MachineFunction &MF, const TargetRegisterInfo *TRI,
1292 std::vector<CalleeSavedInfo> &CSI) const {
1293 MachineFrameInfo *MFI = MF.getFrameInfo();
1294 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1296 unsigned CalleeSavedFrameSize = 0;
1297 int SpillSlotOffset = getOffsetOfLocalArea() + X86FI->getTCReturnAddrDelta();
1300 // emitPrologue always spills frame register the first thing.
1301 SpillSlotOffset -= SlotSize;
1302 MFI->CreateFixedSpillStackObject(SlotSize, SpillSlotOffset);
1304 // Since emitPrologue and emitEpilogue will handle spilling and restoring of
1305 // the frame register, we can delete it from CSI list and not have to worry
1306 // about avoiding it later.
1307 unsigned FPReg = TRI->getFrameRegister(MF);
1308 for (unsigned i = 0; i < CSI.size(); ++i) {
1309 if (TRI->regsOverlap(CSI[i].getReg(),FPReg)) {
1310 CSI.erase(CSI.begin() + i);
1316 // Assign slots for GPRs. It increases frame size.
1317 for (unsigned i = CSI.size(); i != 0; --i) {
1318 unsigned Reg = CSI[i - 1].getReg();
1320 if (!X86::GR64RegClass.contains(Reg) && !X86::GR32RegClass.contains(Reg))
1323 SpillSlotOffset -= SlotSize;
1324 CalleeSavedFrameSize += SlotSize;
1326 int SlotIndex = MFI->CreateFixedSpillStackObject(SlotSize, SpillSlotOffset);
1327 CSI[i - 1].setFrameIdx(SlotIndex);
1330 X86FI->setCalleeSavedFrameSize(CalleeSavedFrameSize);
1332 // Assign slots for XMMs.
1333 for (unsigned i = CSI.size(); i != 0; --i) {
1334 unsigned Reg = CSI[i - 1].getReg();
1335 if (X86::GR64RegClass.contains(Reg) || X86::GR32RegClass.contains(Reg))
1338 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1340 SpillSlotOffset -= std::abs(SpillSlotOffset) % RC->getAlignment();
1342 SpillSlotOffset -= RC->getSize();
1344 MFI->CreateFixedSpillStackObject(RC->getSize(), SpillSlotOffset);
1345 CSI[i - 1].setFrameIdx(SlotIndex);
1346 MFI->ensureMaxAlignment(RC->getAlignment());
1352 bool X86FrameLowering::spillCalleeSavedRegisters(
1353 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
1354 const std::vector<CalleeSavedInfo> &CSI,
1355 const TargetRegisterInfo *TRI) const {
1356 DebugLoc DL = MBB.findDebugLoc(MI);
1358 // Push GPRs. It increases frame size.
1359 unsigned Opc = STI.is64Bit() ? X86::PUSH64r : X86::PUSH32r;
1360 for (unsigned i = CSI.size(); i != 0; --i) {
1361 unsigned Reg = CSI[i - 1].getReg();
1363 if (!X86::GR64RegClass.contains(Reg) && !X86::GR32RegClass.contains(Reg))
1365 // Add the callee-saved register as live-in. It's killed at the spill.
1368 BuildMI(MBB, MI, DL, TII.get(Opc)).addReg(Reg, RegState::Kill)
1369 .setMIFlag(MachineInstr::FrameSetup);
1372 // Make XMM regs spilled. X86 does not have ability of push/pop XMM.
1373 // It can be done by spilling XMMs to stack frame.
1374 for (unsigned i = CSI.size(); i != 0; --i) {
1375 unsigned Reg = CSI[i-1].getReg();
1376 if (X86::GR64RegClass.contains(Reg) || X86::GR32RegClass.contains(Reg))
1378 // Add the callee-saved register as live-in. It's killed at the spill.
1380 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1382 TII.storeRegToStackSlot(MBB, MI, Reg, true, CSI[i - 1].getFrameIdx(), RC,
1385 MI->setFlag(MachineInstr::FrameSetup);
1392 bool X86FrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
1393 MachineBasicBlock::iterator MI,
1394 const std::vector<CalleeSavedInfo> &CSI,
1395 const TargetRegisterInfo *TRI) const {
1399 DebugLoc DL = MBB.findDebugLoc(MI);
1401 // Reload XMMs from stack frame.
1402 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1403 unsigned Reg = CSI[i].getReg();
1404 if (X86::GR64RegClass.contains(Reg) ||
1405 X86::GR32RegClass.contains(Reg))
1408 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1409 TII.loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(), RC, TRI);
1413 unsigned Opc = STI.is64Bit() ? X86::POP64r : X86::POP32r;
1414 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1415 unsigned Reg = CSI[i].getReg();
1416 if (!X86::GR64RegClass.contains(Reg) &&
1417 !X86::GR32RegClass.contains(Reg))
1420 BuildMI(MBB, MI, DL, TII.get(Opc), Reg);
1425 void X86FrameLowering::determineCalleeSaves(MachineFunction &MF,
1426 BitVector &SavedRegs,
1427 RegScavenger *RS) const {
1428 TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
1430 MachineFrameInfo *MFI = MF.getFrameInfo();
1432 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1433 int64_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
1435 if (TailCallReturnAddrDelta < 0) {
1436 // create RETURNADDR area
1445 MFI->CreateFixedObject(-TailCallReturnAddrDelta,
1446 TailCallReturnAddrDelta - SlotSize, true);
1449 // Spill the BasePtr if it's used.
1450 if (TRI->hasBasePointer(MF))
1451 SavedRegs.set(TRI->getBaseRegister());
1455 HasNestArgument(const MachineFunction *MF) {
1456 const Function *F = MF->getFunction();
1457 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
1459 if (I->hasNestAttr())
1465 /// GetScratchRegister - Get a temp register for performing work in the
1466 /// segmented stack and the Erlang/HiPE stack prologue. Depending on platform
1467 /// and the properties of the function either one or two registers will be
1468 /// needed. Set primary to true for the first register, false for the second.
1470 GetScratchRegister(bool Is64Bit, bool IsLP64, const MachineFunction &MF, bool Primary) {
1471 CallingConv::ID CallingConvention = MF.getFunction()->getCallingConv();
1474 if (CallingConvention == CallingConv::HiPE) {
1476 return Primary ? X86::R14 : X86::R13;
1478 return Primary ? X86::EBX : X86::EDI;
1483 return Primary ? X86::R11 : X86::R12;
1485 return Primary ? X86::R11D : X86::R12D;
1488 bool IsNested = HasNestArgument(&MF);
1490 if (CallingConvention == CallingConv::X86_FastCall ||
1491 CallingConvention == CallingConv::Fast) {
1493 report_fatal_error("Segmented stacks does not support fastcall with "
1494 "nested function.");
1495 return Primary ? X86::EAX : X86::ECX;
1498 return Primary ? X86::EDX : X86::EAX;
1499 return Primary ? X86::ECX : X86::EAX;
1502 // The stack limit in the TCB is set to this many bytes above the actual stack
1504 static const uint64_t kSplitStackAvailable = 256;
1506 void X86FrameLowering::adjustForSegmentedStacks(
1507 MachineFunction &MF, MachineBasicBlock &PrologueMBB) const {
1508 MachineFrameInfo *MFI = MF.getFrameInfo();
1510 unsigned TlsReg, TlsOffset;
1513 unsigned ScratchReg = GetScratchRegister(Is64Bit, IsLP64, MF, true);
1514 assert(!MF.getRegInfo().isLiveIn(ScratchReg) &&
1515 "Scratch register is live-in");
1517 if (MF.getFunction()->isVarArg())
1518 report_fatal_error("Segmented stacks do not support vararg functions.");
1519 if (!STI.isTargetLinux() && !STI.isTargetDarwin() && !STI.isTargetWin32() &&
1520 !STI.isTargetWin64() && !STI.isTargetFreeBSD() &&
1521 !STI.isTargetDragonFly())
1522 report_fatal_error("Segmented stacks not supported on this platform.");
1524 // Eventually StackSize will be calculated by a link-time pass; which will
1525 // also decide whether checking code needs to be injected into this particular
1527 StackSize = MFI->getStackSize();
1529 // Do not generate a prologue for functions with a stack of size zero
1533 MachineBasicBlock *allocMBB = MF.CreateMachineBasicBlock();
1534 MachineBasicBlock *checkMBB = MF.CreateMachineBasicBlock();
1535 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1536 bool IsNested = false;
1538 // We need to know if the function has a nest argument only in 64 bit mode.
1540 IsNested = HasNestArgument(&MF);
1542 // The MOV R10, RAX needs to be in a different block, since the RET we emit in
1543 // allocMBB needs to be last (terminating) instruction.
1545 for (MachineBasicBlock::livein_iterator i = PrologueMBB.livein_begin(),
1546 e = PrologueMBB.livein_end();
1548 allocMBB->addLiveIn(*i);
1549 checkMBB->addLiveIn(*i);
1553 allocMBB->addLiveIn(IsLP64 ? X86::R10 : X86::R10D);
1555 MF.push_front(allocMBB);
1556 MF.push_front(checkMBB);
1558 // When the frame size is less than 256 we just compare the stack
1559 // boundary directly to the value of the stack pointer, per gcc.
1560 bool CompareStackPointer = StackSize < kSplitStackAvailable;
1562 // Read the limit off the current stacklet off the stack_guard location.
1564 if (STI.isTargetLinux()) {
1566 TlsOffset = IsLP64 ? 0x70 : 0x40;
1567 } else if (STI.isTargetDarwin()) {
1569 TlsOffset = 0x60 + 90*8; // See pthread_machdep.h. Steal TLS slot 90.
1570 } else if (STI.isTargetWin64()) {
1572 TlsOffset = 0x28; // pvArbitrary, reserved for application use
1573 } else if (STI.isTargetFreeBSD()) {
1576 } else if (STI.isTargetDragonFly()) {
1578 TlsOffset = 0x20; // use tls_tcb.tcb_segstack
1580 report_fatal_error("Segmented stacks not supported on this platform.");
1583 if (CompareStackPointer)
1584 ScratchReg = IsLP64 ? X86::RSP : X86::ESP;
1586 BuildMI(checkMBB, DL, TII.get(IsLP64 ? X86::LEA64r : X86::LEA64_32r), ScratchReg).addReg(X86::RSP)
1587 .addImm(1).addReg(0).addImm(-StackSize).addReg(0);
1589 BuildMI(checkMBB, DL, TII.get(IsLP64 ? X86::CMP64rm : X86::CMP32rm)).addReg(ScratchReg)
1590 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg);
1592 if (STI.isTargetLinux()) {
1595 } else if (STI.isTargetDarwin()) {
1597 TlsOffset = 0x48 + 90*4;
1598 } else if (STI.isTargetWin32()) {
1600 TlsOffset = 0x14; // pvArbitrary, reserved for application use
1601 } else if (STI.isTargetDragonFly()) {
1603 TlsOffset = 0x10; // use tls_tcb.tcb_segstack
1604 } else if (STI.isTargetFreeBSD()) {
1605 report_fatal_error("Segmented stacks not supported on FreeBSD i386.");
1607 report_fatal_error("Segmented stacks not supported on this platform.");
1610 if (CompareStackPointer)
1611 ScratchReg = X86::ESP;
1613 BuildMI(checkMBB, DL, TII.get(X86::LEA32r), ScratchReg).addReg(X86::ESP)
1614 .addImm(1).addReg(0).addImm(-StackSize).addReg(0);
1616 if (STI.isTargetLinux() || STI.isTargetWin32() || STI.isTargetWin64() ||
1617 STI.isTargetDragonFly()) {
1618 BuildMI(checkMBB, DL, TII.get(X86::CMP32rm)).addReg(ScratchReg)
1619 .addReg(0).addImm(0).addReg(0).addImm(TlsOffset).addReg(TlsReg);
1620 } else if (STI.isTargetDarwin()) {
1622 // TlsOffset doesn't fit into a mod r/m byte so we need an extra register.
1623 unsigned ScratchReg2;
1625 if (CompareStackPointer) {
1626 // The primary scratch register is available for holding the TLS offset.
1627 ScratchReg2 = GetScratchRegister(Is64Bit, IsLP64, MF, true);
1628 SaveScratch2 = false;
1630 // Need to use a second register to hold the TLS offset
1631 ScratchReg2 = GetScratchRegister(Is64Bit, IsLP64, MF, false);
1633 // Unfortunately, with fastcc the second scratch register may hold an
1635 SaveScratch2 = MF.getRegInfo().isLiveIn(ScratchReg2);
1638 // If Scratch2 is live-in then it needs to be saved.
1639 assert((!MF.getRegInfo().isLiveIn(ScratchReg2) || SaveScratch2) &&
1640 "Scratch register is live-in and not saved");
1643 BuildMI(checkMBB, DL, TII.get(X86::PUSH32r))
1644 .addReg(ScratchReg2, RegState::Kill);
1646 BuildMI(checkMBB, DL, TII.get(X86::MOV32ri), ScratchReg2)
1648 BuildMI(checkMBB, DL, TII.get(X86::CMP32rm))
1650 .addReg(ScratchReg2).addImm(1).addReg(0)
1655 BuildMI(checkMBB, DL, TII.get(X86::POP32r), ScratchReg2);
1659 // This jump is taken if SP >= (Stacklet Limit + Stack Space required).
1660 // It jumps to normal execution of the function body.
1661 BuildMI(checkMBB, DL, TII.get(X86::JA_1)).addMBB(&PrologueMBB);
1663 // On 32 bit we first push the arguments size and then the frame size. On 64
1664 // bit, we pass the stack frame size in r10 and the argument size in r11.
1666 // Functions with nested arguments use R10, so it needs to be saved across
1667 // the call to _morestack
1669 const unsigned RegAX = IsLP64 ? X86::RAX : X86::EAX;
1670 const unsigned Reg10 = IsLP64 ? X86::R10 : X86::R10D;
1671 const unsigned Reg11 = IsLP64 ? X86::R11 : X86::R11D;
1672 const unsigned MOVrr = IsLP64 ? X86::MOV64rr : X86::MOV32rr;
1673 const unsigned MOVri = IsLP64 ? X86::MOV64ri : X86::MOV32ri;
1676 BuildMI(allocMBB, DL, TII.get(MOVrr), RegAX).addReg(Reg10);
1678 BuildMI(allocMBB, DL, TII.get(MOVri), Reg10)
1680 BuildMI(allocMBB, DL, TII.get(MOVri), Reg11)
1681 .addImm(X86FI->getArgumentStackSize());
1683 BuildMI(allocMBB, DL, TII.get(X86::PUSHi32))
1684 .addImm(X86FI->getArgumentStackSize());
1685 BuildMI(allocMBB, DL, TII.get(X86::PUSHi32))
1689 // __morestack is in libgcc
1690 if (Is64Bit && MF.getTarget().getCodeModel() == CodeModel::Large) {
1691 // Under the large code model, we cannot assume that __morestack lives
1692 // within 2^31 bytes of the call site, so we cannot use pc-relative
1693 // addressing. We cannot perform the call via a temporary register,
1694 // as the rax register may be used to store the static chain, and all
1695 // other suitable registers may be either callee-save or used for
1696 // parameter passing. We cannot use the stack at this point either
1697 // because __morestack manipulates the stack directly.
1699 // To avoid these issues, perform an indirect call via a read-only memory
1700 // location containing the address.
1702 // This solution is not perfect, as it assumes that the .rodata section
1703 // is laid out within 2^31 bytes of each function body, but this seems
1704 // to be sufficient for JIT.
1705 BuildMI(allocMBB, DL, TII.get(X86::CALL64m))
1709 .addExternalSymbol("__morestack_addr")
1711 MF.getMMI().setUsesMorestackAddr(true);
1714 BuildMI(allocMBB, DL, TII.get(X86::CALL64pcrel32))
1715 .addExternalSymbol("__morestack");
1717 BuildMI(allocMBB, DL, TII.get(X86::CALLpcrel32))
1718 .addExternalSymbol("__morestack");
1722 BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET_RESTORE_R10));
1724 BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET));
1726 allocMBB->addSuccessor(&PrologueMBB);
1728 checkMBB->addSuccessor(allocMBB);
1729 checkMBB->addSuccessor(&PrologueMBB);
1736 /// Erlang programs may need a special prologue to handle the stack size they
1737 /// might need at runtime. That is because Erlang/OTP does not implement a C
1738 /// stack but uses a custom implementation of hybrid stack/heap architecture.
1739 /// (for more information see Eric Stenman's Ph.D. thesis:
1740 /// http://publications.uu.se/uu/fulltext/nbn_se_uu_diva-2688.pdf)
1743 /// temp0 = sp - MaxStack
1744 /// if( temp0 < SP_LIMIT(P) ) goto IncStack else goto OldStart
1748 /// call inc_stack # doubles the stack space
1749 /// temp0 = sp - MaxStack
1750 /// if( temp0 < SP_LIMIT(P) ) goto IncStack else goto OldStart
1751 void X86FrameLowering::adjustForHiPEPrologue(
1752 MachineFunction &MF, MachineBasicBlock &PrologueMBB) const {
1753 MachineFrameInfo *MFI = MF.getFrameInfo();
1755 // HiPE-specific values
1756 const unsigned HipeLeafWords = 24;
1757 const unsigned CCRegisteredArgs = Is64Bit ? 6 : 5;
1758 const unsigned Guaranteed = HipeLeafWords * SlotSize;
1759 unsigned CallerStkArity = MF.getFunction()->arg_size() > CCRegisteredArgs ?
1760 MF.getFunction()->arg_size() - CCRegisteredArgs : 0;
1761 unsigned MaxStack = MFI->getStackSize() + CallerStkArity*SlotSize + SlotSize;
1763 assert(STI.isTargetLinux() &&
1764 "HiPE prologue is only supported on Linux operating systems.");
1766 // Compute the largest caller's frame that is needed to fit the callees'
1767 // frames. This 'MaxStack' is computed from:
1769 // a) the fixed frame size, which is the space needed for all spilled temps,
1770 // b) outgoing on-stack parameter areas, and
1771 // c) the minimum stack space this function needs to make available for the
1772 // functions it calls (a tunable ABI property).
1773 if (MFI->hasCalls()) {
1774 unsigned MoreStackForCalls = 0;
1776 for (MachineFunction::iterator MBBI = MF.begin(), MBBE = MF.end();
1777 MBBI != MBBE; ++MBBI)
1778 for (MachineBasicBlock::iterator MI = MBBI->begin(), ME = MBBI->end();
1783 // Get callee operand.
1784 const MachineOperand &MO = MI->getOperand(0);
1786 // Only take account of global function calls (no closures etc.).
1790 const Function *F = dyn_cast<Function>(MO.getGlobal());
1794 // Do not update 'MaxStack' for primitive and built-in functions
1795 // (encoded with names either starting with "erlang."/"bif_" or not
1796 // having a ".", such as a simple <Module>.<Function>.<Arity>, or an
1797 // "_", such as the BIF "suspend_0") as they are executed on another
1799 if (F->getName().find("erlang.") != StringRef::npos ||
1800 F->getName().find("bif_") != StringRef::npos ||
1801 F->getName().find_first_of("._") == StringRef::npos)
1804 unsigned CalleeStkArity =
1805 F->arg_size() > CCRegisteredArgs ? F->arg_size()-CCRegisteredArgs : 0;
1806 if (HipeLeafWords - 1 > CalleeStkArity)
1807 MoreStackForCalls = std::max(MoreStackForCalls,
1808 (HipeLeafWords - 1 - CalleeStkArity) * SlotSize);
1810 MaxStack += MoreStackForCalls;
1813 // If the stack frame needed is larger than the guaranteed then runtime checks
1814 // and calls to "inc_stack_0" BIF should be inserted in the assembly prologue.
1815 if (MaxStack > Guaranteed) {
1816 MachineBasicBlock *stackCheckMBB = MF.CreateMachineBasicBlock();
1817 MachineBasicBlock *incStackMBB = MF.CreateMachineBasicBlock();
1819 for (MachineBasicBlock::livein_iterator I = PrologueMBB.livein_begin(),
1820 E = PrologueMBB.livein_end();
1822 stackCheckMBB->addLiveIn(*I);
1823 incStackMBB->addLiveIn(*I);
1826 MF.push_front(incStackMBB);
1827 MF.push_front(stackCheckMBB);
1829 unsigned ScratchReg, SPReg, PReg, SPLimitOffset;
1830 unsigned LEAop, CMPop, CALLop;
1834 LEAop = X86::LEA64r;
1835 CMPop = X86::CMP64rm;
1836 CALLop = X86::CALL64pcrel32;
1837 SPLimitOffset = 0x90;
1841 LEAop = X86::LEA32r;
1842 CMPop = X86::CMP32rm;
1843 CALLop = X86::CALLpcrel32;
1844 SPLimitOffset = 0x4c;
1847 ScratchReg = GetScratchRegister(Is64Bit, IsLP64, MF, true);
1848 assert(!MF.getRegInfo().isLiveIn(ScratchReg) &&
1849 "HiPE prologue scratch register is live-in");
1851 // Create new MBB for StackCheck:
1852 addRegOffset(BuildMI(stackCheckMBB, DL, TII.get(LEAop), ScratchReg),
1853 SPReg, false, -MaxStack);
1854 // SPLimitOffset is in a fixed heap location (pointed by BP).
1855 addRegOffset(BuildMI(stackCheckMBB, DL, TII.get(CMPop))
1856 .addReg(ScratchReg), PReg, false, SPLimitOffset);
1857 BuildMI(stackCheckMBB, DL, TII.get(X86::JAE_1)).addMBB(&PrologueMBB);
1859 // Create new MBB for IncStack:
1860 BuildMI(incStackMBB, DL, TII.get(CALLop)).
1861 addExternalSymbol("inc_stack_0");
1862 addRegOffset(BuildMI(incStackMBB, DL, TII.get(LEAop), ScratchReg),
1863 SPReg, false, -MaxStack);
1864 addRegOffset(BuildMI(incStackMBB, DL, TII.get(CMPop))
1865 .addReg(ScratchReg), PReg, false, SPLimitOffset);
1866 BuildMI(incStackMBB, DL, TII.get(X86::JLE_1)).addMBB(incStackMBB);
1868 stackCheckMBB->addSuccessor(&PrologueMBB, 99);
1869 stackCheckMBB->addSuccessor(incStackMBB, 1);
1870 incStackMBB->addSuccessor(&PrologueMBB, 99);
1871 incStackMBB->addSuccessor(incStackMBB, 1);
1878 void X86FrameLowering::
1879 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
1880 MachineBasicBlock::iterator I) const {
1881 bool reserveCallFrame = hasReservedCallFrame(MF);
1882 unsigned Opcode = I->getOpcode();
1883 bool isDestroy = Opcode == TII.getCallFrameDestroyOpcode();
1884 DebugLoc DL = I->getDebugLoc();
1885 uint64_t Amount = !reserveCallFrame ? I->getOperand(0).getImm() : 0;
1886 uint64_t InternalAmt = (isDestroy || Amount) ? I->getOperand(1).getImm() : 0;
1889 if (!reserveCallFrame) {
1890 // If the stack pointer can be changed after prologue, turn the
1891 // adjcallstackup instruction into a 'sub ESP, <amt>' and the
1892 // adjcallstackdown instruction into 'add ESP, <amt>'
1896 // We need to keep the stack aligned properly. To do this, we round the
1897 // amount of space needed for the outgoing arguments up to the next
1898 // alignment boundary.
1899 unsigned StackAlign = getStackAlignment();
1900 Amount = RoundUpToAlignment(Amount, StackAlign);
1902 // Factor out the amount that gets handled inside the sequence
1903 // (Pushes of argument for frame setup, callee pops for frame destroy)
1904 Amount -= InternalAmt;
1907 // Add Amount to SP to destroy a frame, and subtract to setup.
1908 int Offset = isDestroy ? Amount : -Amount;
1909 BuildStackAdjustment(MBB, I, DL, Offset, /*InEpilogue=*/false);
1914 if (isDestroy && InternalAmt) {
1915 // If we are performing frame pointer elimination and if the callee pops
1916 // something off the stack pointer, add it back. We do this until we have
1917 // more advanced stack pointer tracking ability.
1918 // We are not tracking the stack pointer adjustment by the callee, so make
1919 // sure we restore the stack pointer immediately after the call, there may
1920 // be spill code inserted between the CALL and ADJCALLSTACKUP instructions.
1921 MachineBasicBlock::iterator B = MBB.begin();
1922 while (I != B && !std::prev(I)->isCall())
1924 BuildStackAdjustment(MBB, I, DL, -InternalAmt, /*InEpilogue=*/false);
1928 bool X86FrameLowering::canUseAsEpilogue(const MachineBasicBlock &MBB) const {
1929 assert(MBB.getParent() && "Block is not attached to a function!");
1931 if (canUseLEAForSPInEpilogue(*MBB.getParent()))
1934 // If we cannot use LEA to adjust SP, we may need to use ADD, which
1935 // clobbers the EFLAGS. Check that none of the terminators reads the
1936 // EFLAGS, and if one uses it, conservatively assume this is not
1937 // safe to insert the epilogue here.
1938 return !terminatorsNeedFlagsAsInput(MBB);