1 //===-- X86FrameLowering.cpp - X86 Frame Information ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of TargetFrameLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "X86FrameLowering.h"
15 #include "X86InstrBuilder.h"
16 #include "X86InstrInfo.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/ADT/SmallSet.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineModuleInfo.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/IR/DataLayout.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/MC/MCAsmInfo.h"
29 #include "llvm/MC/MCSymbol.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Target/TargetOptions.h"
35 // FIXME: completely move here.
36 extern cl::opt<bool> ForceStackAlign;
38 bool X86FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
39 return !MF.getFrameInfo()->hasVarSizedObjects();
42 /// hasFP - Return true if the specified function should have a dedicated frame
43 /// pointer register. This is true if the function has variable sized allocas
44 /// or if frame pointer elimination is disabled.
45 bool X86FrameLowering::hasFP(const MachineFunction &MF) const {
46 const MachineFrameInfo *MFI = MF.getFrameInfo();
47 const MachineModuleInfo &MMI = MF.getMMI();
48 const TargetRegisterInfo *RegInfo = TM.getRegisterInfo();
50 return (MF.getTarget().Options.DisableFramePointerElim(MF) ||
51 RegInfo->needsStackRealignment(MF) ||
52 MFI->hasVarSizedObjects() ||
53 MFI->isFrameAddressTaken() || MF.hasMSInlineAsm() ||
54 MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
55 MMI.callsUnwindInit() || MMI.callsEHReturn());
58 static unsigned getSUBriOpcode(unsigned IsLP64, int64_t Imm) {
62 return X86::SUB64ri32;
70 static unsigned getADDriOpcode(unsigned IsLP64, int64_t Imm) {
74 return X86::ADD64ri32;
82 static unsigned getLEArOpcode(unsigned IsLP64) {
83 return IsLP64 ? X86::LEA64r : X86::LEA32r;
86 /// findDeadCallerSavedReg - Return a caller-saved register that isn't live
87 /// when it reaches the "return" instruction. We can then pop a stack object
88 /// to this register without worry about clobbering it.
89 static unsigned findDeadCallerSavedReg(MachineBasicBlock &MBB,
90 MachineBasicBlock::iterator &MBBI,
91 const TargetRegisterInfo &TRI,
93 const MachineFunction *MF = MBB.getParent();
94 const Function *F = MF->getFunction();
95 if (!F || MF->getMMI().callsEHReturn())
98 static const uint16_t CallerSavedRegs32Bit[] = {
99 X86::EAX, X86::EDX, X86::ECX, 0
102 static const uint16_t CallerSavedRegs64Bit[] = {
103 X86::RAX, X86::RDX, X86::RCX, X86::RSI, X86::RDI,
104 X86::R8, X86::R9, X86::R10, X86::R11, 0
107 unsigned Opc = MBBI->getOpcode();
112 case X86::TCRETURNdi:
113 case X86::TCRETURNri:
114 case X86::TCRETURNmi:
115 case X86::TCRETURNdi64:
116 case X86::TCRETURNri64:
117 case X86::TCRETURNmi64:
119 case X86::EH_RETURN64: {
120 SmallSet<uint16_t, 8> Uses;
121 for (unsigned i = 0, e = MBBI->getNumOperands(); i != e; ++i) {
122 MachineOperand &MO = MBBI->getOperand(i);
123 if (!MO.isReg() || MO.isDef())
125 unsigned Reg = MO.getReg();
128 for (MCRegAliasIterator AI(Reg, &TRI, true); AI.isValid(); ++AI)
132 const uint16_t *CS = Is64Bit ? CallerSavedRegs64Bit : CallerSavedRegs32Bit;
134 if (!Uses.count(*CS))
143 /// emitSPUpdate - Emit a series of instructions to increment / decrement the
144 /// stack pointer by a constant value.
146 void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
147 unsigned StackPtr, int64_t NumBytes,
148 bool Is64Bit, bool IsLP64, bool UseLEA,
149 const TargetInstrInfo &TII, const TargetRegisterInfo &TRI) {
150 bool isSub = NumBytes < 0;
151 uint64_t Offset = isSub ? -NumBytes : NumBytes;
154 Opc = getLEArOpcode(IsLP64);
157 ? getSUBriOpcode(IsLP64, Offset)
158 : getADDriOpcode(IsLP64, Offset);
160 uint64_t Chunk = (1LL << 31) - 1;
161 DebugLoc DL = MBB.findDebugLoc(MBBI);
164 uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset;
165 if (ThisVal == (Is64Bit ? 8 : 4)) {
166 // Use push / pop instead.
168 ? (unsigned)(Is64Bit ? X86::RAX : X86::EAX)
169 : findDeadCallerSavedReg(MBB, MBBI, TRI, Is64Bit);
172 ? (Is64Bit ? X86::PUSH64r : X86::PUSH32r)
173 : (Is64Bit ? X86::POP64r : X86::POP32r);
174 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc))
175 .addReg(Reg, getDefRegState(!isSub) | getUndefRegState(isSub));
177 MI->setFlag(MachineInstr::FrameSetup);
183 MachineInstr *MI = NULL;
186 MI = addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr),
187 StackPtr, false, isSub ? -ThisVal : ThisVal);
189 MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
192 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
196 MI->setFlag(MachineInstr::FrameSetup);
202 /// mergeSPUpdatesUp - Merge two stack-manipulating instructions upper iterator.
204 void mergeSPUpdatesUp(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
205 unsigned StackPtr, uint64_t *NumBytes = NULL) {
206 if (MBBI == MBB.begin()) return;
208 MachineBasicBlock::iterator PI = prior(MBBI);
209 unsigned Opc = PI->getOpcode();
210 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
211 Opc == X86::ADD32ri || Opc == X86::ADD32ri8 ||
212 Opc == X86::LEA32r || Opc == X86::LEA64_32r) &&
213 PI->getOperand(0).getReg() == StackPtr) {
215 *NumBytes += PI->getOperand(2).getImm();
217 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
218 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
219 PI->getOperand(0).getReg() == StackPtr) {
221 *NumBytes -= PI->getOperand(2).getImm();
226 /// mergeSPUpdatesDown - Merge two stack-manipulating instructions lower iterator.
228 void mergeSPUpdatesDown(MachineBasicBlock &MBB,
229 MachineBasicBlock::iterator &MBBI,
230 unsigned StackPtr, uint64_t *NumBytes = NULL) {
231 // FIXME: THIS ISN'T RUN!!!
234 if (MBBI == MBB.end()) return;
236 MachineBasicBlock::iterator NI = llvm::next(MBBI);
237 if (NI == MBB.end()) return;
239 unsigned Opc = NI->getOpcode();
240 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
241 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
242 NI->getOperand(0).getReg() == StackPtr) {
244 *NumBytes -= NI->getOperand(2).getImm();
247 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
248 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
249 NI->getOperand(0).getReg() == StackPtr) {
251 *NumBytes += NI->getOperand(2).getImm();
257 /// mergeSPUpdates - Checks the instruction before/after the passed
258 /// instruction. If it is an ADD/SUB/LEA instruction it is deleted argument and the
259 /// stack adjustment is returned as a positive value for ADD/LEA and a negative for
261 static int mergeSPUpdates(MachineBasicBlock &MBB,
262 MachineBasicBlock::iterator &MBBI,
264 bool doMergeWithPrevious) {
265 if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
266 (!doMergeWithPrevious && MBBI == MBB.end()))
269 MachineBasicBlock::iterator PI = doMergeWithPrevious ? prior(MBBI) : MBBI;
270 MachineBasicBlock::iterator NI = doMergeWithPrevious ? 0 : llvm::next(MBBI);
271 unsigned Opc = PI->getOpcode();
274 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
275 Opc == X86::ADD32ri || Opc == X86::ADD32ri8 ||
276 Opc == X86::LEA32r || Opc == X86::LEA64_32r) &&
277 PI->getOperand(0).getReg() == StackPtr){
278 Offset += PI->getOperand(2).getImm();
280 if (!doMergeWithPrevious) MBBI = NI;
281 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
282 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
283 PI->getOperand(0).getReg() == StackPtr) {
284 Offset -= PI->getOperand(2).getImm();
286 if (!doMergeWithPrevious) MBBI = NI;
292 static bool isEAXLiveIn(MachineFunction &MF) {
293 for (MachineRegisterInfo::livein_iterator II = MF.getRegInfo().livein_begin(),
294 EE = MF.getRegInfo().livein_end(); II != EE; ++II) {
295 unsigned Reg = II->first;
297 if (Reg == X86::EAX || Reg == X86::AX ||
298 Reg == X86::AH || Reg == X86::AL)
305 void X86FrameLowering::emitCalleeSavedFrameMoves(MachineFunction &MF,
307 unsigned FramePtr) const {
308 MachineFrameInfo *MFI = MF.getFrameInfo();
309 MachineModuleInfo &MMI = MF.getMMI();
311 // Add callee saved registers to move list.
312 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
313 if (CSI.empty()) return;
315 std::vector<MachineMove> &Moves = MMI.getFrameMoves();
316 const X86RegisterInfo *RegInfo = TM.getRegisterInfo();
317 bool HasFP = hasFP(MF);
319 // Calculate amount of bytes used for return address storing.
320 int stackGrowth = -RegInfo->getSlotSize();
322 // FIXME: This is dirty hack. The code itself is pretty mess right now.
323 // It should be rewritten from scratch and generalized sometimes.
325 // Determine maximum offset (minimum due to stack growth).
326 int64_t MaxOffset = 0;
327 for (std::vector<CalleeSavedInfo>::const_iterator
328 I = CSI.begin(), E = CSI.end(); I != E; ++I)
329 MaxOffset = std::min(MaxOffset,
330 MFI->getObjectOffset(I->getFrameIdx()));
332 // Calculate offsets.
333 int64_t saveAreaOffset = (HasFP ? 3 : 2) * stackGrowth;
334 for (std::vector<CalleeSavedInfo>::const_iterator
335 I = CSI.begin(), E = CSI.end(); I != E; ++I) {
336 int64_t Offset = MFI->getObjectOffset(I->getFrameIdx());
337 unsigned Reg = I->getReg();
338 Offset = MaxOffset - Offset + saveAreaOffset;
340 // Don't output a new machine move if we're re-saving the frame
341 // pointer. This happens when the PrologEpilogInserter has inserted an extra
342 // "PUSH" of the frame pointer -- the "emitPrologue" method automatically
343 // generates one when frame pointers are used. If we generate a "machine
344 // move" for this extra "PUSH", the linker will lose track of the fact that
345 // the frame pointer should have the value of the first "PUSH" when it's
348 // FIXME: This looks inelegant. It's possibly correct, but it's covering up
349 // another bug. I.e., one where we generate a prolog like this:
357 // The immediate re-push of EBP is unnecessary. At the least, it's an
358 // optimization bug. EBP can be used as a scratch register in certain
359 // cases, but probably not when we have a frame pointer.
360 if (HasFP && FramePtr == Reg)
363 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
364 MachineLocation CSSrc(Reg);
365 Moves.push_back(MachineMove(Label, CSDst, CSSrc));
369 /// getCompactUnwindRegNum - Get the compact unwind number for a given
370 /// register. The number corresponds to the enum lists in
371 /// compact_unwind_encoding.h.
372 static int getCompactUnwindRegNum(const uint16_t *CURegs, unsigned Reg) {
373 for (int Idx = 1; *CURegs; ++CURegs, ++Idx)
380 // Number of registers that can be saved in a compact unwind encoding.
381 #define CU_NUM_SAVED_REGS 6
383 /// encodeCompactUnwindRegistersWithoutFrame - Create the permutation encoding
384 /// used with frameless stacks. It is passed the number of registers to be saved
385 /// and an array of the registers saved.
387 encodeCompactUnwindRegistersWithoutFrame(unsigned SavedRegs[CU_NUM_SAVED_REGS],
388 unsigned RegCount, bool Is64Bit) {
389 // The saved registers are numbered from 1 to 6. In order to encode the order
390 // in which they were saved, we re-number them according to their place in the
391 // register order. The re-numbering is relative to the last re-numbered
392 // register. E.g., if we have registers {6, 2, 4, 5} saved in that order:
401 static const uint16_t CU32BitRegs[] = {
402 X86::EBX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::EBP, 0
404 static const uint16_t CU64BitRegs[] = {
405 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
407 const uint16_t *CURegs = (Is64Bit ? CU64BitRegs : CU32BitRegs);
409 for (unsigned i = 0; i != CU_NUM_SAVED_REGS; ++i) {
410 int CUReg = getCompactUnwindRegNum(CURegs, SavedRegs[i]);
411 if (CUReg == -1) return ~0U;
412 SavedRegs[i] = CUReg;
416 std::swap(SavedRegs[0], SavedRegs[5]);
417 std::swap(SavedRegs[1], SavedRegs[4]);
418 std::swap(SavedRegs[2], SavedRegs[3]);
420 uint32_t RenumRegs[CU_NUM_SAVED_REGS];
421 for (unsigned i = CU_NUM_SAVED_REGS - RegCount; i < CU_NUM_SAVED_REGS; ++i) {
422 unsigned Countless = 0;
423 for (unsigned j = CU_NUM_SAVED_REGS - RegCount; j < i; ++j)
424 if (SavedRegs[j] < SavedRegs[i])
427 RenumRegs[i] = SavedRegs[i] - Countless - 1;
430 // Take the renumbered values and encode them into a 10-bit number.
431 uint32_t permutationEncoding = 0;
434 permutationEncoding |= 120 * RenumRegs[0] + 24 * RenumRegs[1]
435 + 6 * RenumRegs[2] + 2 * RenumRegs[3]
439 permutationEncoding |= 120 * RenumRegs[1] + 24 * RenumRegs[2]
440 + 6 * RenumRegs[3] + 2 * RenumRegs[4]
444 permutationEncoding |= 60 * RenumRegs[2] + 12 * RenumRegs[3]
445 + 3 * RenumRegs[4] + RenumRegs[5];
448 permutationEncoding |= 20 * RenumRegs[3] + 4 * RenumRegs[4]
452 permutationEncoding |= 5 * RenumRegs[4] + RenumRegs[5];
455 permutationEncoding |= RenumRegs[5];
459 assert((permutationEncoding & 0x3FF) == permutationEncoding &&
460 "Invalid compact register encoding!");
461 return permutationEncoding;
464 /// encodeCompactUnwindRegistersWithFrame - Return the registers encoded for a
465 /// compact encoding with a frame pointer.
467 encodeCompactUnwindRegistersWithFrame(unsigned SavedRegs[CU_NUM_SAVED_REGS],
469 static const uint16_t CU32BitRegs[] = {
470 X86::EBX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::EBP, 0
472 static const uint16_t CU64BitRegs[] = {
473 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
475 const uint16_t *CURegs = (Is64Bit ? CU64BitRegs : CU32BitRegs);
477 // Encode the registers in the order they were saved, 3-bits per register. The
478 // registers are numbered from 1 to CU_NUM_SAVED_REGS.
480 for (int I = CU_NUM_SAVED_REGS - 1, Idx = 0; I != -1; --I) {
481 unsigned Reg = SavedRegs[I];
482 if (Reg == 0) continue;
484 int CURegNum = getCompactUnwindRegNum(CURegs, Reg);
485 if (CURegNum == -1) return ~0U;
487 // Encode the 3-bit register number in order, skipping over 3-bits for each
489 RegEnc |= (CURegNum & 0x7) << (Idx++ * 3);
492 assert((RegEnc & 0x3FFFF) == RegEnc && "Invalid compact register encoding!");
496 uint32_t X86FrameLowering::getCompactUnwindEncoding(MachineFunction &MF) const {
497 const X86RegisterInfo *RegInfo = TM.getRegisterInfo();
498 unsigned FramePtr = RegInfo->getFrameRegister(MF);
499 unsigned StackPtr = RegInfo->getStackRegister();
501 bool Is64Bit = STI.is64Bit();
502 bool HasFP = hasFP(MF);
504 unsigned SavedRegs[CU_NUM_SAVED_REGS] = { 0, 0, 0, 0, 0, 0 };
505 unsigned SavedRegIdx = 0;
507 unsigned OffsetSize = (Is64Bit ? 8 : 4);
509 unsigned PushInstr = (Is64Bit ? X86::PUSH64r : X86::PUSH32r);
510 unsigned PushInstrSize = 1;
511 unsigned MoveInstr = (Is64Bit ? X86::MOV64rr : X86::MOV32rr);
512 unsigned MoveInstrSize = (Is64Bit ? 3 : 2);
513 unsigned SubtractInstrIdx = (Is64Bit ? 3 : 2);
515 unsigned StackDivide = (Is64Bit ? 8 : 4);
517 unsigned InstrOffset = 0;
518 unsigned StackAdjust = 0;
519 unsigned StackSize = 0;
521 MachineBasicBlock &MBB = MF.front(); // Prologue is in entry BB.
522 bool ExpectEnd = false;
523 for (MachineBasicBlock::iterator
524 MBBI = MBB.begin(), MBBE = MBB.end(); MBBI != MBBE; ++MBBI) {
525 MachineInstr &MI = *MBBI;
526 unsigned Opc = MI.getOpcode();
527 if (Opc == X86::PROLOG_LABEL) continue;
528 if (!MI.getFlag(MachineInstr::FrameSetup)) break;
530 // We don't exect any more prolog instructions.
531 if (ExpectEnd) return CU::UNWIND_MODE_DWARF;
533 if (Opc == PushInstr) {
534 // If there are too many saved registers, we cannot use compact encoding.
535 if (SavedRegIdx >= CU_NUM_SAVED_REGS) return CU::UNWIND_MODE_DWARF;
537 SavedRegs[SavedRegIdx++] = MI.getOperand(0).getReg();
538 StackAdjust += OffsetSize;
539 InstrOffset += PushInstrSize;
540 } else if (Opc == MoveInstr) {
541 unsigned SrcReg = MI.getOperand(1).getReg();
542 unsigned DstReg = MI.getOperand(0).getReg();
544 if (DstReg != FramePtr || SrcReg != StackPtr)
545 return CU::UNWIND_MODE_DWARF;
548 memset(SavedRegs, 0, sizeof(SavedRegs));
550 InstrOffset += MoveInstrSize;
551 } else if (Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
552 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) {
554 // We already have a stack size.
555 return CU::UNWIND_MODE_DWARF;
557 if (!MI.getOperand(0).isReg() ||
558 MI.getOperand(0).getReg() != MI.getOperand(1).getReg() ||
559 MI.getOperand(0).getReg() != StackPtr || !MI.getOperand(2).isImm())
560 // We need this to be a stack adjustment pointer. Something like:
562 // %RSP<def> = SUB64ri8 %RSP, 48
563 return CU::UNWIND_MODE_DWARF;
565 StackSize = MI.getOperand(2).getImm() / StackDivide;
566 SubtractInstrIdx += InstrOffset;
571 // Encode that we are using EBP/RBP as the frame pointer.
572 uint32_t CompactUnwindEncoding = 0;
573 StackAdjust /= StackDivide;
575 if ((StackAdjust & 0xFF) != StackAdjust)
576 // Offset was too big for compact encoding.
577 return CU::UNWIND_MODE_DWARF;
579 // Get the encoding of the saved registers when we have a frame pointer.
580 uint32_t RegEnc = encodeCompactUnwindRegistersWithFrame(SavedRegs, Is64Bit);
581 if (RegEnc == ~0U) return CU::UNWIND_MODE_DWARF;
583 CompactUnwindEncoding |= CU::UNWIND_MODE_BP_FRAME;
584 CompactUnwindEncoding |= (StackAdjust & 0xFF) << 16;
585 CompactUnwindEncoding |= RegEnc & CU::UNWIND_BP_FRAME_REGISTERS;
588 uint32_t TotalStackSize = StackAdjust + StackSize;
589 if ((TotalStackSize & 0xFF) == TotalStackSize) {
590 // Frameless stack with a small stack size.
591 CompactUnwindEncoding |= CU::UNWIND_MODE_STACK_IMMD;
593 // Encode the stack size.
594 CompactUnwindEncoding |= (TotalStackSize & 0xFF) << 16;
596 if ((StackAdjust & 0x7) != StackAdjust)
597 // The extra stack adjustments are too big for us to handle.
598 return CU::UNWIND_MODE_DWARF;
600 // Frameless stack with an offset too large for us to encode compactly.
601 CompactUnwindEncoding |= CU::UNWIND_MODE_STACK_IND;
603 // Encode the offset to the nnnnnn value in the 'subl $nnnnnn, ESP'
605 CompactUnwindEncoding |= (SubtractInstrIdx & 0xFF) << 16;
607 // Encode any extra stack stack adjustments (done via push instructions).
608 CompactUnwindEncoding |= (StackAdjust & 0x7) << 13;
611 // Encode the number of registers saved.
612 CompactUnwindEncoding |= (SavedRegIdx & 0x7) << 10;
614 // Get the encoding of the saved registers when we don't have a frame
617 encodeCompactUnwindRegistersWithoutFrame(SavedRegs, SavedRegIdx,
619 if (RegEnc == ~0U) return CU::UNWIND_MODE_DWARF;
621 // Encode the register encoding.
622 CompactUnwindEncoding |=
623 RegEnc & CU::UNWIND_FRAMELESS_STACK_REG_PERMUTATION;
626 return CompactUnwindEncoding;
629 /// usesTheStack - This function checks if any of the users of EFLAGS
630 /// copies the EFLAGS. We know that the code that lowers COPY of EFLAGS has
631 /// to use the stack, and if we don't adjust the stack we clobber the first
633 /// See X86InstrInfo::copyPhysReg.
634 static bool usesTheStack(MachineFunction &MF) {
635 MachineRegisterInfo &MRI = MF.getRegInfo();
637 for (MachineRegisterInfo::reg_iterator ri = MRI.reg_begin(X86::EFLAGS),
638 re = MRI.reg_end(); ri != re; ++ri)
645 /// emitPrologue - Push callee-saved registers onto the stack, which
646 /// automatically adjust the stack pointer. Adjust the stack pointer to allocate
647 /// space for local variables. Also emit labels used by the exception handler to
648 /// generate the exception handling frames.
649 void X86FrameLowering::emitPrologue(MachineFunction &MF) const {
650 MachineBasicBlock &MBB = MF.front(); // Prologue goes in entry BB.
651 MachineBasicBlock::iterator MBBI = MBB.begin();
652 MachineFrameInfo *MFI = MF.getFrameInfo();
653 const Function *Fn = MF.getFunction();
654 const X86RegisterInfo *RegInfo = TM.getRegisterInfo();
655 const X86InstrInfo &TII = *TM.getInstrInfo();
656 MachineModuleInfo &MMI = MF.getMMI();
657 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
658 bool needsFrameMoves = MMI.hasDebugInfo() ||
659 Fn->needsUnwindTableEntry();
660 uint64_t MaxAlign = MFI->getMaxAlignment(); // Desired stack alignment.
661 uint64_t StackSize = MFI->getStackSize(); // Number of bytes to allocate.
662 bool HasFP = hasFP(MF);
663 bool Is64Bit = STI.is64Bit();
664 bool IsLP64 = STI.isTarget64BitLP64();
665 bool IsWin64 = STI.isTargetWin64();
666 bool UseLEA = STI.useLeaForSP();
667 unsigned StackAlign = getStackAlignment();
668 unsigned SlotSize = RegInfo->getSlotSize();
669 unsigned FramePtr = RegInfo->getFrameRegister(MF);
670 unsigned StackPtr = RegInfo->getStackRegister();
671 unsigned BasePtr = RegInfo->getBaseRegister();
674 // If we're forcing a stack realignment we can't rely on just the frame
675 // info, we need to know the ABI stack alignment as well in case we
676 // have a call out. Otherwise just make sure we have some alignment - we'll
677 // go with the minimum SlotSize.
678 if (ForceStackAlign) {
680 MaxAlign = (StackAlign > MaxAlign) ? StackAlign : MaxAlign;
681 else if (MaxAlign < SlotSize)
685 // Add RETADDR move area to callee saved frame size.
686 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
687 if (TailCallReturnAddrDelta < 0)
688 X86FI->setCalleeSavedFrameSize(
689 X86FI->getCalleeSavedFrameSize() - TailCallReturnAddrDelta);
691 // If this is x86-64 and the Red Zone is not disabled, if we are a leaf
692 // function, and use up to 128 bytes of stack space, don't have a frame
693 // pointer, calls, or dynamic alloca then we do not need to adjust the
694 // stack pointer (we fit in the Red Zone). We also check that we don't
695 // push and pop from the stack.
696 if (Is64Bit && !Fn->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
697 Attribute::NoRedZone) &&
698 !RegInfo->needsStackRealignment(MF) &&
699 !MFI->hasVarSizedObjects() && // No dynamic alloca.
700 !MFI->adjustsStack() && // No calls.
701 !IsWin64 && // Win64 has no Red Zone
702 !usesTheStack(MF) && // Don't push and pop.
703 !MF.getTarget().Options.EnableSegmentedStacks) { // Regular stack
704 uint64_t MinSize = X86FI->getCalleeSavedFrameSize();
705 if (HasFP) MinSize += SlotSize;
706 StackSize = std::max(MinSize, StackSize > 128 ? StackSize - 128 : 0);
707 MFI->setStackSize(StackSize);
710 // Insert stack pointer adjustment for later moving of return addr. Only
711 // applies to tail call optimized functions where the callee argument stack
712 // size is bigger than the callers.
713 if (TailCallReturnAddrDelta < 0) {
715 BuildMI(MBB, MBBI, DL,
716 TII.get(getSUBriOpcode(IsLP64, -TailCallReturnAddrDelta)),
719 .addImm(-TailCallReturnAddrDelta)
720 .setMIFlag(MachineInstr::FrameSetup);
721 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
724 // Mapping for machine moves:
726 // DST: VirtualFP AND
727 // SRC: VirtualFP => DW_CFA_def_cfa_offset
728 // ELSE => DW_CFA_def_cfa
730 // SRC: VirtualFP AND
731 // DST: Register => DW_CFA_def_cfa_register
734 // OFFSET < 0 => DW_CFA_offset_extended_sf
735 // REG < 64 => DW_CFA_offset + Reg
736 // ELSE => DW_CFA_offset_extended
738 std::vector<MachineMove> &Moves = MMI.getFrameMoves();
739 uint64_t NumBytes = 0;
740 int stackGrowth = -SlotSize;
743 // Calculate required stack adjustment.
744 uint64_t FrameSize = StackSize - SlotSize;
745 if (RegInfo->needsStackRealignment(MF)) {
746 // Callee-saved registers are pushed on stack before the stack
748 FrameSize -= X86FI->getCalleeSavedFrameSize();
749 NumBytes = (FrameSize + MaxAlign - 1) / MaxAlign * MaxAlign;
751 NumBytes = FrameSize - X86FI->getCalleeSavedFrameSize();
754 // Get the offset of the stack slot for the EBP register, which is
755 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
756 // Update the frame offset adjustment.
757 MFI->setOffsetAdjustment(-NumBytes);
759 // Save EBP/RBP into the appropriate stack slot.
760 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
761 .addReg(FramePtr, RegState::Kill)
762 .setMIFlag(MachineInstr::FrameSetup);
764 if (needsFrameMoves) {
765 // Mark the place where EBP/RBP was saved.
766 MCSymbol *FrameLabel = MMI.getContext().CreateTempSymbol();
767 BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL))
770 // Define the current CFA rule to use the provided offset.
772 MachineLocation SPDst(MachineLocation::VirtualFP);
773 MachineLocation SPSrc(MachineLocation::VirtualFP, 2 * stackGrowth);
774 Moves.push_back(MachineMove(FrameLabel, SPDst, SPSrc));
776 MachineLocation SPDst(StackPtr);
777 MachineLocation SPSrc(StackPtr, stackGrowth);
778 Moves.push_back(MachineMove(FrameLabel, SPDst, SPSrc));
781 // Change the rule for the FramePtr to be an "offset" rule.
782 MachineLocation FPDst(MachineLocation::VirtualFP, 2 * stackGrowth);
783 MachineLocation FPSrc(FramePtr);
784 Moves.push_back(MachineMove(FrameLabel, FPDst, FPSrc));
787 // Update EBP with the new base value.
788 BuildMI(MBB, MBBI, DL,
789 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr)
791 .setMIFlag(MachineInstr::FrameSetup);
793 if (needsFrameMoves) {
794 // Mark effective beginning of when frame pointer becomes valid.
795 MCSymbol *FrameLabel = MMI.getContext().CreateTempSymbol();
796 BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL))
799 // Define the current CFA to use the EBP/RBP register.
800 MachineLocation FPDst(FramePtr);
801 MachineLocation FPSrc(MachineLocation::VirtualFP);
802 Moves.push_back(MachineMove(FrameLabel, FPDst, FPSrc));
805 // Mark the FramePtr as live-in in every block except the entry.
806 for (MachineFunction::iterator I = llvm::next(MF.begin()), E = MF.end();
808 I->addLiveIn(FramePtr);
810 NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
813 // Skip the callee-saved push instructions.
814 bool PushedRegs = false;
815 int StackOffset = 2 * stackGrowth;
817 while (MBBI != MBB.end() &&
818 (MBBI->getOpcode() == X86::PUSH32r ||
819 MBBI->getOpcode() == X86::PUSH64r)) {
821 MBBI->setFlag(MachineInstr::FrameSetup);
824 if (!HasFP && needsFrameMoves) {
825 // Mark callee-saved push instruction.
826 MCSymbol *Label = MMI.getContext().CreateTempSymbol();
827 BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL)).addSym(Label);
829 // Define the current CFA rule to use the provided offset.
830 unsigned Ptr = StackSize ? MachineLocation::VirtualFP : StackPtr;
831 MachineLocation SPDst(Ptr);
832 MachineLocation SPSrc(Ptr, StackOffset);
833 Moves.push_back(MachineMove(Label, SPDst, SPSrc));
834 StackOffset += stackGrowth;
838 // Realign stack after we pushed callee-saved registers (so that we'll be
839 // able to calculate their offsets from the frame pointer).
841 // NOTE: We push the registers before realigning the stack, so
842 // vector callee-saved (xmm) registers may be saved w/o proper
843 // alignment in this way. However, currently these regs are saved in
844 // stack slots (see X86FrameLowering::spillCalleeSavedRegisters()), so
845 // this shouldn't be a problem.
846 if (RegInfo->needsStackRealignment(MF)) {
847 assert(HasFP && "There should be a frame pointer if stack is realigned.");
849 BuildMI(MBB, MBBI, DL,
850 TII.get(Is64Bit ? X86::AND64ri32 : X86::AND32ri), StackPtr)
853 .setMIFlag(MachineInstr::FrameSetup);
855 // The EFLAGS implicit def is dead.
856 MI->getOperand(3).setIsDead();
859 // If there is an SUB32ri of ESP immediately before this instruction, merge
860 // the two. This can be the case when tail call elimination is enabled and
861 // the callee has more arguments then the caller.
862 NumBytes -= mergeSPUpdates(MBB, MBBI, StackPtr, true);
864 // If there is an ADD32ri or SUB32ri of ESP immediately after this
865 // instruction, merge the two instructions.
866 mergeSPUpdatesDown(MBB, MBBI, StackPtr, &NumBytes);
868 // Adjust stack pointer: ESP -= numbytes.
870 // Windows and cygwin/mingw require a prologue helper routine when allocating
871 // more than 4K bytes on the stack. Windows uses __chkstk and cygwin/mingw
872 // uses __alloca. __alloca and the 32-bit version of __chkstk will probe the
873 // stack and adjust the stack pointer in one go. The 64-bit version of
874 // __chkstk is only responsible for probing the stack. The 64-bit prologue is
875 // responsible for adjusting the stack pointer. Touching the stack at 4K
876 // increments is necessary to ensure that the guard pages used by the OS
877 // virtual memory manager are allocated in correct sequence.
878 if (NumBytes >= 4096 && STI.isTargetCOFF() && !STI.isTargetEnvMacho()) {
879 const char *StackProbeSymbol;
880 bool isSPUpdateNeeded = false;
883 if (STI.isTargetCygMing())
884 StackProbeSymbol = "___chkstk";
886 StackProbeSymbol = "__chkstk";
887 isSPUpdateNeeded = true;
889 } else if (STI.isTargetCygMing())
890 StackProbeSymbol = "_alloca";
892 StackProbeSymbol = "_chkstk";
894 // Check whether EAX is livein for this function.
895 bool isEAXAlive = isEAXLiveIn(MF);
898 // Sanity check that EAX is not livein for this function.
899 // It should not be, so throw an assert.
900 assert(!Is64Bit && "EAX is livein in x64 case!");
903 BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH32r))
904 .addReg(X86::EAX, RegState::Kill)
905 .setMIFlag(MachineInstr::FrameSetup);
909 // Handle the 64-bit Windows ABI case where we need to call __chkstk.
910 // Function prologue is responsible for adjusting the stack pointer.
911 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri), X86::RAX)
913 .setMIFlag(MachineInstr::FrameSetup);
915 // Allocate NumBytes-4 bytes on stack in case of isEAXAlive.
916 // We'll also use 4 already allocated bytes for EAX.
917 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
918 .addImm(isEAXAlive ? NumBytes - 4 : NumBytes)
919 .setMIFlag(MachineInstr::FrameSetup);
922 BuildMI(MBB, MBBI, DL,
923 TII.get(Is64Bit ? X86::W64ALLOCA : X86::CALLpcrel32))
924 .addExternalSymbol(StackProbeSymbol)
925 .addReg(StackPtr, RegState::Define | RegState::Implicit)
926 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit)
927 .setMIFlag(MachineInstr::FrameSetup);
929 // MSVC x64's __chkstk needs to adjust %rsp.
930 // FIXME: %rax preserves the offset and should be available.
931 if (isSPUpdateNeeded)
932 emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, IsLP64,
933 UseLEA, TII, *RegInfo);
937 MachineInstr *MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV32rm),
939 StackPtr, false, NumBytes - 4);
940 MI->setFlag(MachineInstr::FrameSetup);
941 MBB.insert(MBBI, MI);
944 emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, IsLP64,
945 UseLEA, TII, *RegInfo);
947 // If we need a base pointer, set it up here. It's whatever the value
948 // of the stack pointer is at this point. Any variable size objects
949 // will be allocated after this, so we can still use the base pointer
950 // to reference locals.
951 if (RegInfo->hasBasePointer(MF)) {
952 // Update the frame pointer with the current stack pointer.
953 unsigned Opc = Is64Bit ? X86::MOV64rr : X86::MOV32rr;
954 BuildMI(MBB, MBBI, DL, TII.get(Opc), BasePtr)
956 .setMIFlag(MachineInstr::FrameSetup);
959 if (( (!HasFP && NumBytes) || PushedRegs) && needsFrameMoves) {
960 // Mark end of stack pointer adjustment.
961 MCSymbol *Label = MMI.getContext().CreateTempSymbol();
962 BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL))
965 if (!HasFP && NumBytes) {
966 // Define the current CFA rule to use the provided offset.
968 MachineLocation SPDst(MachineLocation::VirtualFP);
969 MachineLocation SPSrc(MachineLocation::VirtualFP,
970 -StackSize + stackGrowth);
971 Moves.push_back(MachineMove(Label, SPDst, SPSrc));
973 MachineLocation SPDst(StackPtr);
974 MachineLocation SPSrc(StackPtr, stackGrowth);
975 Moves.push_back(MachineMove(Label, SPDst, SPSrc));
979 // Emit DWARF info specifying the offsets of the callee-saved registers.
981 emitCalleeSavedFrameMoves(MF, Label, HasFP ? FramePtr : StackPtr);
984 // Darwin 10.7 and greater has support for compact unwind encoding.
985 if (STI.getTargetTriple().isMacOSX() &&
986 !STI.getTargetTriple().isMacOSXVersionLT(10, 7))
987 MMI.setCompactUnwindEncoding(getCompactUnwindEncoding(MF));
990 void X86FrameLowering::emitEpilogue(MachineFunction &MF,
991 MachineBasicBlock &MBB) const {
992 const MachineFrameInfo *MFI = MF.getFrameInfo();
993 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
994 const X86RegisterInfo *RegInfo = TM.getRegisterInfo();
995 const X86InstrInfo &TII = *TM.getInstrInfo();
996 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
997 assert(MBBI != MBB.end() && "Returning block has no instructions");
998 unsigned RetOpcode = MBBI->getOpcode();
999 DebugLoc DL = MBBI->getDebugLoc();
1000 bool Is64Bit = STI.is64Bit();
1001 bool IsLP64 = STI.isTarget64BitLP64();
1002 bool UseLEA = STI.useLeaForSP();
1003 unsigned StackAlign = getStackAlignment();
1004 unsigned SlotSize = RegInfo->getSlotSize();
1005 unsigned FramePtr = RegInfo->getFrameRegister(MF);
1006 unsigned StackPtr = RegInfo->getStackRegister();
1008 switch (RetOpcode) {
1010 llvm_unreachable("Can only insert epilog into returning blocks");
1013 case X86::TCRETURNdi:
1014 case X86::TCRETURNri:
1015 case X86::TCRETURNmi:
1016 case X86::TCRETURNdi64:
1017 case X86::TCRETURNri64:
1018 case X86::TCRETURNmi64:
1019 case X86::EH_RETURN:
1020 case X86::EH_RETURN64:
1021 break; // These are ok
1024 // Get the number of bytes to allocate from the FrameInfo.
1025 uint64_t StackSize = MFI->getStackSize();
1026 uint64_t MaxAlign = MFI->getMaxAlignment();
1027 unsigned CSSize = X86FI->getCalleeSavedFrameSize();
1028 uint64_t NumBytes = 0;
1030 // If we're forcing a stack realignment we can't rely on just the frame
1031 // info, we need to know the ABI stack alignment as well in case we
1032 // have a call out. Otherwise just make sure we have some alignment - we'll
1033 // go with the minimum.
1034 if (ForceStackAlign) {
1035 if (MFI->hasCalls())
1036 MaxAlign = (StackAlign > MaxAlign) ? StackAlign : MaxAlign;
1038 MaxAlign = MaxAlign ? MaxAlign : 4;
1042 // Calculate required stack adjustment.
1043 uint64_t FrameSize = StackSize - SlotSize;
1044 if (RegInfo->needsStackRealignment(MF)) {
1045 // Callee-saved registers were pushed on stack before the stack
1047 FrameSize -= CSSize;
1048 NumBytes = (FrameSize + MaxAlign - 1) / MaxAlign * MaxAlign;
1050 NumBytes = FrameSize - CSSize;
1054 BuildMI(MBB, MBBI, DL,
1055 TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr);
1057 NumBytes = StackSize - CSSize;
1060 // Skip the callee-saved pop instructions.
1061 while (MBBI != MBB.begin()) {
1062 MachineBasicBlock::iterator PI = prior(MBBI);
1063 unsigned Opc = PI->getOpcode();
1065 if (Opc != X86::POP32r && Opc != X86::POP64r && Opc != X86::DBG_VALUE &&
1066 !PI->isTerminator())
1071 MachineBasicBlock::iterator FirstCSPop = MBBI;
1073 DL = MBBI->getDebugLoc();
1075 // If there is an ADD32ri or SUB32ri of ESP immediately before this
1076 // instruction, merge the two instructions.
1077 if (NumBytes || MFI->hasVarSizedObjects())
1078 mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
1080 // If dynamic alloca is used, then reset esp to point to the last callee-saved
1081 // slot before popping them off! Same applies for the case, when stack was
1083 if (RegInfo->needsStackRealignment(MF) || MFI->hasVarSizedObjects()) {
1084 if (RegInfo->needsStackRealignment(MF))
1087 unsigned Opc = getLEArOpcode(IsLP64);
1088 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr),
1089 FramePtr, false, -CSSize);
1091 unsigned Opc = (Is64Bit ? X86::MOV64rr : X86::MOV32rr);
1092 BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
1095 } else if (NumBytes) {
1096 // Adjust stack pointer back: ESP += numbytes.
1097 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, IsLP64, UseLEA,
1101 // We're returning from function via eh_return.
1102 if (RetOpcode == X86::EH_RETURN || RetOpcode == X86::EH_RETURN64) {
1103 MBBI = MBB.getLastNonDebugInstr();
1104 MachineOperand &DestAddr = MBBI->getOperand(0);
1105 assert(DestAddr.isReg() && "Offset should be in register!");
1106 BuildMI(MBB, MBBI, DL,
1107 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
1108 StackPtr).addReg(DestAddr.getReg());
1109 } else if (RetOpcode == X86::TCRETURNri || RetOpcode == X86::TCRETURNdi ||
1110 RetOpcode == X86::TCRETURNmi ||
1111 RetOpcode == X86::TCRETURNri64 || RetOpcode == X86::TCRETURNdi64 ||
1112 RetOpcode == X86::TCRETURNmi64) {
1113 bool isMem = RetOpcode == X86::TCRETURNmi || RetOpcode == X86::TCRETURNmi64;
1114 // Tail call return: adjust the stack pointer and jump to callee.
1115 MBBI = MBB.getLastNonDebugInstr();
1116 MachineOperand &JumpTarget = MBBI->getOperand(0);
1117 MachineOperand &StackAdjust = MBBI->getOperand(isMem ? 5 : 1);
1118 assert(StackAdjust.isImm() && "Expecting immediate value.");
1120 // Adjust stack pointer.
1121 int StackAdj = StackAdjust.getImm();
1122 int MaxTCDelta = X86FI->getTCReturnAddrDelta();
1124 assert(MaxTCDelta <= 0 && "MaxTCDelta should never be positive");
1126 // Incoporate the retaddr area.
1127 Offset = StackAdj-MaxTCDelta;
1128 assert(Offset >= 0 && "Offset should never be negative");
1131 // Check for possible merge with preceding ADD instruction.
1132 Offset += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1133 emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, IsLP64,
1134 UseLEA, TII, *RegInfo);
1137 // Jump to label or value in register.
1138 if (RetOpcode == X86::TCRETURNdi || RetOpcode == X86::TCRETURNdi64) {
1139 MachineInstrBuilder MIB =
1140 BuildMI(MBB, MBBI, DL, TII.get((RetOpcode == X86::TCRETURNdi)
1141 ? X86::TAILJMPd : X86::TAILJMPd64));
1142 if (JumpTarget.isGlobal())
1143 MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
1144 JumpTarget.getTargetFlags());
1146 assert(JumpTarget.isSymbol());
1147 MIB.addExternalSymbol(JumpTarget.getSymbolName(),
1148 JumpTarget.getTargetFlags());
1150 } else if (RetOpcode == X86::TCRETURNmi || RetOpcode == X86::TCRETURNmi64) {
1151 MachineInstrBuilder MIB =
1152 BuildMI(MBB, MBBI, DL, TII.get((RetOpcode == X86::TCRETURNmi)
1153 ? X86::TAILJMPm : X86::TAILJMPm64));
1154 for (unsigned i = 0; i != 5; ++i)
1155 MIB.addOperand(MBBI->getOperand(i));
1156 } else if (RetOpcode == X86::TCRETURNri64) {
1157 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr64)).
1158 addReg(JumpTarget.getReg(), RegState::Kill);
1160 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr)).
1161 addReg(JumpTarget.getReg(), RegState::Kill);
1164 MachineInstr *NewMI = prior(MBBI);
1165 NewMI->copyImplicitOps(MF, MBBI);
1167 // Delete the pseudo instruction TCRETURN.
1169 } else if ((RetOpcode == X86::RET || RetOpcode == X86::RETI) &&
1170 (X86FI->getTCReturnAddrDelta() < 0)) {
1171 // Add the return addr area delta back since we are not tail calling.
1172 int delta = -1*X86FI->getTCReturnAddrDelta();
1173 MBBI = MBB.getLastNonDebugInstr();
1175 // Check for possible merge with preceding ADD instruction.
1176 delta += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1177 emitSPUpdate(MBB, MBBI, StackPtr, delta, Is64Bit, IsLP64, UseLEA, TII,
1182 int X86FrameLowering::getFrameIndexOffset(const MachineFunction &MF, int FI) const {
1183 const X86RegisterInfo *RegInfo =
1184 static_cast<const X86RegisterInfo*>(MF.getTarget().getRegisterInfo());
1185 const MachineFrameInfo *MFI = MF.getFrameInfo();
1186 int Offset = MFI->getObjectOffset(FI) - getOffsetOfLocalArea();
1187 uint64_t StackSize = MFI->getStackSize();
1189 if (RegInfo->hasBasePointer(MF)) {
1190 assert (hasFP(MF) && "VLAs and dynamic stack realign, but no FP?!");
1192 // Skip the saved EBP.
1193 return Offset + RegInfo->getSlotSize();
1195 assert((-(Offset + StackSize)) % MFI->getObjectAlignment(FI) == 0);
1196 return Offset + StackSize;
1198 } else if (RegInfo->needsStackRealignment(MF)) {
1200 // Skip the saved EBP.
1201 return Offset + RegInfo->getSlotSize();
1203 assert((-(Offset + StackSize)) % MFI->getObjectAlignment(FI) == 0);
1204 return Offset + StackSize;
1206 // FIXME: Support tail calls
1209 return Offset + StackSize;
1211 // Skip the saved EBP.
1212 Offset += RegInfo->getSlotSize();
1214 // Skip the RETADDR move area
1215 const X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1216 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
1217 if (TailCallReturnAddrDelta < 0)
1218 Offset -= TailCallReturnAddrDelta;
1224 int X86FrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI,
1225 unsigned &FrameReg) const {
1226 const X86RegisterInfo *RegInfo =
1227 static_cast<const X86RegisterInfo*>(MF.getTarget().getRegisterInfo());
1228 // We can't calculate offset from frame pointer if the stack is realigned,
1229 // so enforce usage of stack/base pointer. The base pointer is used when we
1230 // have dynamic allocas in addition to dynamic realignment.
1231 if (RegInfo->hasBasePointer(MF))
1232 FrameReg = RegInfo->getBaseRegister();
1233 else if (RegInfo->needsStackRealignment(MF))
1234 FrameReg = RegInfo->getStackRegister();
1236 FrameReg = RegInfo->getFrameRegister(MF);
1237 return getFrameIndexOffset(MF, FI);
1240 bool X86FrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
1241 MachineBasicBlock::iterator MI,
1242 const std::vector<CalleeSavedInfo> &CSI,
1243 const TargetRegisterInfo *TRI) const {
1247 DebugLoc DL = MBB.findDebugLoc(MI);
1249 MachineFunction &MF = *MBB.getParent();
1251 unsigned SlotSize = STI.is64Bit() ? 8 : 4;
1252 unsigned FPReg = TRI->getFrameRegister(MF);
1253 unsigned CalleeFrameSize = 0;
1255 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
1256 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1258 // Push GPRs. It increases frame size.
1259 unsigned Opc = STI.is64Bit() ? X86::PUSH64r : X86::PUSH32r;
1260 for (unsigned i = CSI.size(); i != 0; --i) {
1261 unsigned Reg = CSI[i-1].getReg();
1262 if (!X86::GR64RegClass.contains(Reg) &&
1263 !X86::GR32RegClass.contains(Reg))
1265 // Add the callee-saved register as live-in. It's killed at the spill.
1268 // X86RegisterInfo::emitPrologue will handle spilling of frame register.
1270 CalleeFrameSize += SlotSize;
1271 BuildMI(MBB, MI, DL, TII.get(Opc)).addReg(Reg, RegState::Kill)
1272 .setMIFlag(MachineInstr::FrameSetup);
1275 X86FI->setCalleeSavedFrameSize(CalleeFrameSize);
1277 // Make XMM regs spilled. X86 does not have ability of push/pop XMM.
1278 // It can be done by spilling XMMs to stack frame.
1279 // Note that only Win64 ABI might spill XMMs.
1280 for (unsigned i = CSI.size(); i != 0; --i) {
1281 unsigned Reg = CSI[i-1].getReg();
1282 if (X86::GR64RegClass.contains(Reg) ||
1283 X86::GR32RegClass.contains(Reg))
1285 // Add the callee-saved register as live-in. It's killed at the spill.
1287 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1288 TII.storeRegToStackSlot(MBB, MI, Reg, true, CSI[i-1].getFrameIdx(),
1295 bool X86FrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
1296 MachineBasicBlock::iterator MI,
1297 const std::vector<CalleeSavedInfo> &CSI,
1298 const TargetRegisterInfo *TRI) const {
1302 DebugLoc DL = MBB.findDebugLoc(MI);
1304 MachineFunction &MF = *MBB.getParent();
1305 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
1307 // Reload XMMs from stack frame.
1308 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1309 unsigned Reg = CSI[i].getReg();
1310 if (X86::GR64RegClass.contains(Reg) ||
1311 X86::GR32RegClass.contains(Reg))
1313 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1314 TII.loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(),
1319 unsigned FPReg = TRI->getFrameRegister(MF);
1320 unsigned Opc = STI.is64Bit() ? X86::POP64r : X86::POP32r;
1321 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1322 unsigned Reg = CSI[i].getReg();
1323 if (!X86::GR64RegClass.contains(Reg) &&
1324 !X86::GR32RegClass.contains(Reg))
1327 // X86RegisterInfo::emitEpilogue will handle restoring of frame register.
1329 BuildMI(MBB, MI, DL, TII.get(Opc), Reg);
1335 X86FrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
1336 RegScavenger *RS) const {
1337 MachineFrameInfo *MFI = MF.getFrameInfo();
1338 const X86RegisterInfo *RegInfo = TM.getRegisterInfo();
1339 unsigned SlotSize = RegInfo->getSlotSize();
1341 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1342 int32_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
1344 if (TailCallReturnAddrDelta < 0) {
1345 // create RETURNADDR area
1354 MFI->CreateFixedObject(-TailCallReturnAddrDelta,
1355 (-1U*SlotSize)+TailCallReturnAddrDelta, true);
1359 assert((TailCallReturnAddrDelta <= 0) &&
1360 "The Delta should always be zero or negative");
1361 const TargetFrameLowering &TFI = *MF.getTarget().getFrameLowering();
1363 // Create a frame entry for the EBP register that must be saved.
1364 int FrameIdx = MFI->CreateFixedObject(SlotSize,
1366 TFI.getOffsetOfLocalArea() +
1367 TailCallReturnAddrDelta,
1369 assert(FrameIdx == MFI->getObjectIndexBegin() &&
1370 "Slot for EBP register must be last in order to be found!");
1374 // Spill the BasePtr if it's used.
1375 if (RegInfo->hasBasePointer(MF))
1376 MF.getRegInfo().setPhysRegUsed(RegInfo->getBaseRegister());
1380 HasNestArgument(const MachineFunction *MF) {
1381 const Function *F = MF->getFunction();
1382 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
1384 if (I->hasNestAttr())
1390 /// GetScratchRegister - Get a temp register for performing work in the
1391 /// segmented stack and the Erlang/HiPE stack prologue. Depending on platform
1392 /// and the properties of the function either one or two registers will be
1393 /// needed. Set primary to true for the first register, false for the second.
1395 GetScratchRegister(bool Is64Bit, const MachineFunction &MF, bool Primary) {
1396 CallingConv::ID CallingConvention = MF.getFunction()->getCallingConv();
1399 if (CallingConvention == CallingConv::HiPE) {
1401 return Primary ? X86::R14 : X86::R13;
1403 return Primary ? X86::EBX : X86::EDI;
1407 return Primary ? X86::R11 : X86::R12;
1409 bool IsNested = HasNestArgument(&MF);
1411 if (CallingConvention == CallingConv::X86_FastCall ||
1412 CallingConvention == CallingConv::Fast) {
1414 report_fatal_error("Segmented stacks does not support fastcall with "
1415 "nested function.");
1416 return Primary ? X86::EAX : X86::ECX;
1419 return Primary ? X86::EDX : X86::EAX;
1420 return Primary ? X86::ECX : X86::EAX;
1423 // The stack limit in the TCB is set to this many bytes above the actual stack
1425 static const uint64_t kSplitStackAvailable = 256;
1428 X86FrameLowering::adjustForSegmentedStacks(MachineFunction &MF) const {
1429 MachineBasicBlock &prologueMBB = MF.front();
1430 MachineFrameInfo *MFI = MF.getFrameInfo();
1431 const X86InstrInfo &TII = *TM.getInstrInfo();
1433 bool Is64Bit = STI.is64Bit();
1434 unsigned TlsReg, TlsOffset;
1437 unsigned ScratchReg = GetScratchRegister(Is64Bit, MF, true);
1438 assert(!MF.getRegInfo().isLiveIn(ScratchReg) &&
1439 "Scratch register is live-in");
1441 if (MF.getFunction()->isVarArg())
1442 report_fatal_error("Segmented stacks do not support vararg functions.");
1443 if (!STI.isTargetLinux() && !STI.isTargetDarwin() &&
1444 !STI.isTargetWin32() && !STI.isTargetFreeBSD())
1445 report_fatal_error("Segmented stacks not supported on this platform.");
1447 MachineBasicBlock *allocMBB = MF.CreateMachineBasicBlock();
1448 MachineBasicBlock *checkMBB = MF.CreateMachineBasicBlock();
1449 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1450 bool IsNested = false;
1452 // We need to know if the function has a nest argument only in 64 bit mode.
1454 IsNested = HasNestArgument(&MF);
1456 // The MOV R10, RAX needs to be in a different block, since the RET we emit in
1457 // allocMBB needs to be last (terminating) instruction.
1459 for (MachineBasicBlock::livein_iterator i = prologueMBB.livein_begin(),
1460 e = prologueMBB.livein_end(); i != e; i++) {
1461 allocMBB->addLiveIn(*i);
1462 checkMBB->addLiveIn(*i);
1466 allocMBB->addLiveIn(X86::R10);
1468 MF.push_front(allocMBB);
1469 MF.push_front(checkMBB);
1471 // Eventually StackSize will be calculated by a link-time pass; which will
1472 // also decide whether checking code needs to be injected into this particular
1474 StackSize = MFI->getStackSize();
1476 // When the frame size is less than 256 we just compare the stack
1477 // boundary directly to the value of the stack pointer, per gcc.
1478 bool CompareStackPointer = StackSize < kSplitStackAvailable;
1480 // Read the limit off the current stacklet off the stack_guard location.
1482 if (STI.isTargetLinux()) {
1485 } else if (STI.isTargetDarwin()) {
1487 TlsOffset = 0x60 + 90*8; // See pthread_machdep.h. Steal TLS slot 90.
1488 } else if (STI.isTargetFreeBSD()) {
1492 report_fatal_error("Segmented stacks not supported on this platform.");
1495 if (CompareStackPointer)
1496 ScratchReg = X86::RSP;
1498 BuildMI(checkMBB, DL, TII.get(X86::LEA64r), ScratchReg).addReg(X86::RSP)
1499 .addImm(1).addReg(0).addImm(-StackSize).addReg(0);
1501 BuildMI(checkMBB, DL, TII.get(X86::CMP64rm)).addReg(ScratchReg)
1502 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg);
1504 if (STI.isTargetLinux()) {
1507 } else if (STI.isTargetDarwin()) {
1509 TlsOffset = 0x48 + 90*4;
1510 } else if (STI.isTargetWin32()) {
1512 TlsOffset = 0x14; // pvArbitrary, reserved for application use
1513 } else if (STI.isTargetFreeBSD()) {
1514 report_fatal_error("Segmented stacks not supported on FreeBSD i386.");
1516 report_fatal_error("Segmented stacks not supported on this platform.");
1519 if (CompareStackPointer)
1520 ScratchReg = X86::ESP;
1522 BuildMI(checkMBB, DL, TII.get(X86::LEA32r), ScratchReg).addReg(X86::ESP)
1523 .addImm(1).addReg(0).addImm(-StackSize).addReg(0);
1525 if (STI.isTargetLinux() || STI.isTargetWin32()) {
1526 BuildMI(checkMBB, DL, TII.get(X86::CMP32rm)).addReg(ScratchReg)
1527 .addReg(0).addImm(0).addReg(0).addImm(TlsOffset).addReg(TlsReg);
1528 } else if (STI.isTargetDarwin()) {
1530 // TlsOffset doesn't fit into a mod r/m byte so we need an extra register
1531 unsigned ScratchReg2;
1533 if (CompareStackPointer) {
1534 // The primary scratch register is available for holding the TLS offset
1535 ScratchReg2 = GetScratchRegister(Is64Bit, MF, true);
1536 SaveScratch2 = false;
1538 // Need to use a second register to hold the TLS offset
1539 ScratchReg2 = GetScratchRegister(Is64Bit, MF, false);
1541 // Unfortunately, with fastcc the second scratch register may hold an arg
1542 SaveScratch2 = MF.getRegInfo().isLiveIn(ScratchReg2);
1545 // If Scratch2 is live-in then it needs to be saved
1546 assert((!MF.getRegInfo().isLiveIn(ScratchReg2) || SaveScratch2) &&
1547 "Scratch register is live-in and not saved");
1550 BuildMI(checkMBB, DL, TII.get(X86::PUSH32r))
1551 .addReg(ScratchReg2, RegState::Kill);
1553 BuildMI(checkMBB, DL, TII.get(X86::MOV32ri), ScratchReg2)
1555 BuildMI(checkMBB, DL, TII.get(X86::CMP32rm))
1557 .addReg(ScratchReg2).addImm(1).addReg(0)
1562 BuildMI(checkMBB, DL, TII.get(X86::POP32r), ScratchReg2);
1566 // This jump is taken if SP >= (Stacklet Limit + Stack Space required).
1567 // It jumps to normal execution of the function body.
1568 BuildMI(checkMBB, DL, TII.get(X86::JA_4)).addMBB(&prologueMBB);
1570 // On 32 bit we first push the arguments size and then the frame size. On 64
1571 // bit, we pass the stack frame size in r10 and the argument size in r11.
1573 // Functions with nested arguments use R10, so it needs to be saved across
1574 // the call to _morestack
1577 BuildMI(allocMBB, DL, TII.get(X86::MOV64rr), X86::RAX).addReg(X86::R10);
1579 BuildMI(allocMBB, DL, TII.get(X86::MOV64ri), X86::R10)
1581 BuildMI(allocMBB, DL, TII.get(X86::MOV64ri), X86::R11)
1582 .addImm(X86FI->getArgumentStackSize());
1583 MF.getRegInfo().setPhysRegUsed(X86::R10);
1584 MF.getRegInfo().setPhysRegUsed(X86::R11);
1586 BuildMI(allocMBB, DL, TII.get(X86::PUSHi32))
1587 .addImm(X86FI->getArgumentStackSize());
1588 BuildMI(allocMBB, DL, TII.get(X86::PUSHi32))
1592 // __morestack is in libgcc
1594 BuildMI(allocMBB, DL, TII.get(X86::CALL64pcrel32))
1595 .addExternalSymbol("__morestack");
1597 BuildMI(allocMBB, DL, TII.get(X86::CALLpcrel32))
1598 .addExternalSymbol("__morestack");
1601 BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET_RESTORE_R10));
1603 BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET));
1605 allocMBB->addSuccessor(&prologueMBB);
1607 checkMBB->addSuccessor(allocMBB);
1608 checkMBB->addSuccessor(&prologueMBB);
1615 /// Erlang programs may need a special prologue to handle the stack size they
1616 /// might need at runtime. That is because Erlang/OTP does not implement a C
1617 /// stack but uses a custom implementation of hybrid stack/heap architecture.
1618 /// (for more information see Eric Stenman's Ph.D. thesis:
1619 /// http://publications.uu.se/uu/fulltext/nbn_se_uu_diva-2688.pdf)
1622 /// temp0 = sp - MaxStack
1623 /// if( temp0 < SP_LIMIT(P) ) goto IncStack else goto OldStart
1627 /// call inc_stack # doubles the stack space
1628 /// temp0 = sp - MaxStack
1629 /// if( temp0 < SP_LIMIT(P) ) goto IncStack else goto OldStart
1630 void X86FrameLowering::adjustForHiPEPrologue(MachineFunction &MF) const {
1631 const X86InstrInfo &TII = *TM.getInstrInfo();
1632 MachineFrameInfo *MFI = MF.getFrameInfo();
1633 const unsigned SlotSize = TM.getRegisterInfo()->getSlotSize();
1634 const bool Is64Bit = STI.is64Bit();
1636 // HiPE-specific values
1637 const unsigned HipeLeafWords = 24;
1638 const unsigned CCRegisteredArgs = Is64Bit ? 6 : 5;
1639 const unsigned Guaranteed = HipeLeafWords * SlotSize;
1640 unsigned CallerStkArity = MF.getFunction()->arg_size() > CCRegisteredArgs ?
1641 MF.getFunction()->arg_size() - CCRegisteredArgs : 0;
1642 unsigned MaxStack = MFI->getStackSize() + CallerStkArity*SlotSize + SlotSize;
1644 assert(STI.isTargetLinux() &&
1645 "HiPE prologue is only supported on Linux operating systems.");
1647 // Compute the largest caller's frame that is needed to fit the callees'
1648 // frames. This 'MaxStack' is computed from:
1650 // a) the fixed frame size, which is the space needed for all spilled temps,
1651 // b) outgoing on-stack parameter areas, and
1652 // c) the minimum stack space this function needs to make available for the
1653 // functions it calls (a tunable ABI property).
1654 if (MFI->hasCalls()) {
1655 unsigned MoreStackForCalls = 0;
1657 for (MachineFunction::iterator MBBI = MF.begin(), MBBE = MF.end();
1658 MBBI != MBBE; ++MBBI)
1659 for (MachineBasicBlock::iterator MI = MBBI->begin(), ME = MBBI->end();
1664 // Get callee operand.
1665 const MachineOperand &MO = MI->getOperand(0);
1667 // Only take account of global function calls (no closures etc.).
1671 const Function *F = dyn_cast<Function>(MO.getGlobal());
1675 // Do not update 'MaxStack' for primitive and built-in functions
1676 // (encoded with names either starting with "erlang."/"bif_" or not
1677 // having a ".", such as a simple <Module>.<Function>.<Arity>, or an
1678 // "_", such as the BIF "suspend_0") as they are executed on another
1680 if (F->getName().find("erlang.") != StringRef::npos ||
1681 F->getName().find("bif_") != StringRef::npos ||
1682 F->getName().find_first_of("._") == StringRef::npos)
1685 unsigned CalleeStkArity =
1686 F->arg_size() > CCRegisteredArgs ? F->arg_size()-CCRegisteredArgs : 0;
1687 if (HipeLeafWords - 1 > CalleeStkArity)
1688 MoreStackForCalls = std::max(MoreStackForCalls,
1689 (HipeLeafWords - 1 - CalleeStkArity) * SlotSize);
1691 MaxStack += MoreStackForCalls;
1694 // If the stack frame needed is larger than the guaranteed then runtime checks
1695 // and calls to "inc_stack_0" BIF should be inserted in the assembly prologue.
1696 if (MaxStack > Guaranteed) {
1697 MachineBasicBlock &prologueMBB = MF.front();
1698 MachineBasicBlock *stackCheckMBB = MF.CreateMachineBasicBlock();
1699 MachineBasicBlock *incStackMBB = MF.CreateMachineBasicBlock();
1701 for (MachineBasicBlock::livein_iterator I = prologueMBB.livein_begin(),
1702 E = prologueMBB.livein_end(); I != E; I++) {
1703 stackCheckMBB->addLiveIn(*I);
1704 incStackMBB->addLiveIn(*I);
1707 MF.push_front(incStackMBB);
1708 MF.push_front(stackCheckMBB);
1710 unsigned ScratchReg, SPReg, PReg, SPLimitOffset;
1711 unsigned LEAop, CMPop, CALLop;
1715 LEAop = X86::LEA64r;
1716 CMPop = X86::CMP64rm;
1717 CALLop = X86::CALL64pcrel32;
1718 SPLimitOffset = 0x90;
1722 LEAop = X86::LEA32r;
1723 CMPop = X86::CMP32rm;
1724 CALLop = X86::CALLpcrel32;
1725 SPLimitOffset = 0x4c;
1728 ScratchReg = GetScratchRegister(Is64Bit, MF, true);
1729 assert(!MF.getRegInfo().isLiveIn(ScratchReg) &&
1730 "HiPE prologue scratch register is live-in");
1732 // Create new MBB for StackCheck:
1733 addRegOffset(BuildMI(stackCheckMBB, DL, TII.get(LEAop), ScratchReg),
1734 SPReg, false, -MaxStack);
1735 // SPLimitOffset is in a fixed heap location (pointed by BP).
1736 addRegOffset(BuildMI(stackCheckMBB, DL, TII.get(CMPop))
1737 .addReg(ScratchReg), PReg, false, SPLimitOffset);
1738 BuildMI(stackCheckMBB, DL, TII.get(X86::JAE_4)).addMBB(&prologueMBB);
1740 // Create new MBB for IncStack:
1741 BuildMI(incStackMBB, DL, TII.get(CALLop)).
1742 addExternalSymbol("inc_stack_0");
1743 addRegOffset(BuildMI(incStackMBB, DL, TII.get(LEAop), ScratchReg),
1744 SPReg, false, -MaxStack);
1745 addRegOffset(BuildMI(incStackMBB, DL, TII.get(CMPop))
1746 .addReg(ScratchReg), PReg, false, SPLimitOffset);
1747 BuildMI(incStackMBB, DL, TII.get(X86::JLE_4)).addMBB(incStackMBB);
1749 stackCheckMBB->addSuccessor(&prologueMBB, 99);
1750 stackCheckMBB->addSuccessor(incStackMBB, 1);
1751 incStackMBB->addSuccessor(&prologueMBB, 99);
1752 incStackMBB->addSuccessor(incStackMBB, 1);
1759 void X86FrameLowering::
1760 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
1761 MachineBasicBlock::iterator I) const {
1762 const X86InstrInfo &TII = *TM.getInstrInfo();
1763 const X86RegisterInfo &RegInfo = *TM.getRegisterInfo();
1764 unsigned StackPtr = RegInfo.getStackRegister();
1765 bool reseveCallFrame = hasReservedCallFrame(MF);
1766 int Opcode = I->getOpcode();
1767 bool isDestroy = Opcode == TII.getCallFrameDestroyOpcode();
1768 bool IsLP64 = STI.isTarget64BitLP64();
1769 DebugLoc DL = I->getDebugLoc();
1770 uint64_t Amount = !reseveCallFrame ? I->getOperand(0).getImm() : 0;
1771 uint64_t CalleeAmt = isDestroy ? I->getOperand(1).getImm() : 0;
1774 if (!reseveCallFrame) {
1775 // If the stack pointer can be changed after prologue, turn the
1776 // adjcallstackup instruction into a 'sub ESP, <amt>' and the
1777 // adjcallstackdown instruction into 'add ESP, <amt>'
1778 // TODO: consider using push / pop instead of sub + store / add
1782 // We need to keep the stack aligned properly. To do this, we round the
1783 // amount of space needed for the outgoing arguments up to the next
1784 // alignment boundary.
1785 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
1786 Amount = (Amount + StackAlign - 1) / StackAlign * StackAlign;
1788 MachineInstr *New = 0;
1789 if (Opcode == TII.getCallFrameSetupOpcode()) {
1790 New = BuildMI(MF, DL, TII.get(getSUBriOpcode(IsLP64, Amount)),
1795 assert(Opcode == TII.getCallFrameDestroyOpcode());
1797 // Factor out the amount the callee already popped.
1798 Amount -= CalleeAmt;
1801 unsigned Opc = getADDriOpcode(IsLP64, Amount);
1802 New = BuildMI(MF, DL, TII.get(Opc), StackPtr)
1803 .addReg(StackPtr).addImm(Amount);
1808 // The EFLAGS implicit def is dead.
1809 New->getOperand(3).setIsDead();
1811 // Replace the pseudo instruction with a new instruction.
1818 if (Opcode == TII.getCallFrameDestroyOpcode() && CalleeAmt) {
1819 // If we are performing frame pointer elimination and if the callee pops
1820 // something off the stack pointer, add it back. We do this until we have
1821 // more advanced stack pointer tracking ability.
1822 unsigned Opc = getSUBriOpcode(IsLP64, CalleeAmt);
1823 MachineInstr *New = BuildMI(MF, DL, TII.get(Opc), StackPtr)
1824 .addReg(StackPtr).addImm(CalleeAmt);
1826 // The EFLAGS implicit def is dead.
1827 New->getOperand(3).setIsDead();
1829 // We are not tracking the stack pointer adjustment by the callee, so make
1830 // sure we restore the stack pointer immediately after the call, there may
1831 // be spill code inserted between the CALL and ADJCALLSTACKUP instructions.
1832 MachineBasicBlock::iterator B = MBB.begin();
1833 while (I != B && !llvm::prior(I)->isCall())