1 //===-- X86FrameLowering.cpp - X86 Frame Information ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of TargetFrameLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "X86FrameLowering.h"
15 #include "X86InstrBuilder.h"
16 #include "X86InstrInfo.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/ADT/SmallSet.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineModuleInfo.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/IR/DataLayout.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/MC/MCAsmInfo.h"
29 #include "llvm/MC/MCSymbol.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Target/TargetOptions.h"
32 #include "llvm/Support/Debug.h"
36 // FIXME: completely move here.
37 extern cl::opt<bool> ForceStackAlign;
39 bool X86FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
40 return !MF.getFrameInfo()->hasVarSizedObjects();
43 /// hasFP - Return true if the specified function should have a dedicated frame
44 /// pointer register. This is true if the function has variable sized allocas
45 /// or if frame pointer elimination is disabled.
46 bool X86FrameLowering::hasFP(const MachineFunction &MF) const {
47 const MachineFrameInfo *MFI = MF.getFrameInfo();
48 const MachineModuleInfo &MMI = MF.getMMI();
49 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
51 return (MF.getTarget().Options.DisableFramePointerElim(MF) ||
52 RegInfo->needsStackRealignment(MF) ||
53 MFI->hasVarSizedObjects() ||
54 MFI->isFrameAddressTaken() || MFI->hasInlineAsmWithSPAdjust() ||
55 MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
56 MMI.callsUnwindInit() || MMI.callsEHReturn());
59 static unsigned getSUBriOpcode(unsigned IsLP64, int64_t Imm) {
63 return X86::SUB64ri32;
71 static unsigned getADDriOpcode(unsigned IsLP64, int64_t Imm) {
75 return X86::ADD64ri32;
83 static unsigned getLEArOpcode(unsigned IsLP64) {
84 return IsLP64 ? X86::LEA64r : X86::LEA32r;
87 /// findDeadCallerSavedReg - Return a caller-saved register that isn't live
88 /// when it reaches the "return" instruction. We can then pop a stack object
89 /// to this register without worry about clobbering it.
90 static unsigned findDeadCallerSavedReg(MachineBasicBlock &MBB,
91 MachineBasicBlock::iterator &MBBI,
92 const TargetRegisterInfo &TRI,
94 const MachineFunction *MF = MBB.getParent();
95 const Function *F = MF->getFunction();
96 if (!F || MF->getMMI().callsEHReturn())
99 static const uint16_t CallerSavedRegs32Bit[] = {
100 X86::EAX, X86::EDX, X86::ECX, 0
103 static const uint16_t CallerSavedRegs64Bit[] = {
104 X86::RAX, X86::RDX, X86::RCX, X86::RSI, X86::RDI,
105 X86::R8, X86::R9, X86::R10, X86::R11, 0
108 unsigned Opc = MBBI->getOpcode();
115 case X86::TCRETURNdi:
116 case X86::TCRETURNri:
117 case X86::TCRETURNmi:
118 case X86::TCRETURNdi64:
119 case X86::TCRETURNri64:
120 case X86::TCRETURNmi64:
122 case X86::EH_RETURN64: {
123 SmallSet<uint16_t, 8> Uses;
124 for (unsigned i = 0, e = MBBI->getNumOperands(); i != e; ++i) {
125 MachineOperand &MO = MBBI->getOperand(i);
126 if (!MO.isReg() || MO.isDef())
128 unsigned Reg = MO.getReg();
131 for (MCRegAliasIterator AI(Reg, &TRI, true); AI.isValid(); ++AI)
135 const uint16_t *CS = Is64Bit ? CallerSavedRegs64Bit : CallerSavedRegs32Bit;
137 if (!Uses.count(*CS))
146 /// emitSPUpdate - Emit a series of instructions to increment / decrement the
147 /// stack pointer by a constant value.
149 void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
150 unsigned StackPtr, int64_t NumBytes,
151 bool Is64Bit, bool IsLP64, bool UseLEA,
152 const TargetInstrInfo &TII, const TargetRegisterInfo &TRI) {
153 bool isSub = NumBytes < 0;
154 uint64_t Offset = isSub ? -NumBytes : NumBytes;
157 Opc = getLEArOpcode(IsLP64);
160 ? getSUBriOpcode(IsLP64, Offset)
161 : getADDriOpcode(IsLP64, Offset);
163 uint64_t Chunk = (1LL << 31) - 1;
164 DebugLoc DL = MBB.findDebugLoc(MBBI);
167 uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset;
168 if (ThisVal == (Is64Bit ? 8 : 4)) {
169 // Use push / pop instead.
171 ? (unsigned)(Is64Bit ? X86::RAX : X86::EAX)
172 : findDeadCallerSavedReg(MBB, MBBI, TRI, Is64Bit);
175 ? (Is64Bit ? X86::PUSH64r : X86::PUSH32r)
176 : (Is64Bit ? X86::POP64r : X86::POP32r);
177 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc))
178 .addReg(Reg, getDefRegState(!isSub) | getUndefRegState(isSub));
180 MI->setFlag(MachineInstr::FrameSetup);
186 MachineInstr *MI = nullptr;
189 MI = addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr),
190 StackPtr, false, isSub ? -ThisVal : ThisVal);
192 MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
195 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
199 MI->setFlag(MachineInstr::FrameSetup);
205 /// mergeSPUpdatesUp - Merge two stack-manipulating instructions upper iterator.
207 void mergeSPUpdatesUp(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
208 unsigned StackPtr, uint64_t *NumBytes = nullptr) {
209 if (MBBI == MBB.begin()) return;
211 MachineBasicBlock::iterator PI = std::prev(MBBI);
212 unsigned Opc = PI->getOpcode();
213 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
214 Opc == X86::ADD32ri || Opc == X86::ADD32ri8 ||
215 Opc == X86::LEA32r || Opc == X86::LEA64_32r) &&
216 PI->getOperand(0).getReg() == StackPtr) {
218 *NumBytes += PI->getOperand(2).getImm();
220 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
221 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
222 PI->getOperand(0).getReg() == StackPtr) {
224 *NumBytes -= PI->getOperand(2).getImm();
229 /// mergeSPUpdatesDown - Merge two stack-manipulating instructions lower
232 void mergeSPUpdatesDown(MachineBasicBlock &MBB,
233 MachineBasicBlock::iterator &MBBI,
234 unsigned StackPtr, uint64_t *NumBytes = nullptr) {
235 // FIXME: THIS ISN'T RUN!!!
238 if (MBBI == MBB.end()) return;
240 MachineBasicBlock::iterator NI = std::next(MBBI);
241 if (NI == MBB.end()) return;
243 unsigned Opc = NI->getOpcode();
244 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
245 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
246 NI->getOperand(0).getReg() == StackPtr) {
248 *NumBytes -= NI->getOperand(2).getImm();
251 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
252 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
253 NI->getOperand(0).getReg() == StackPtr) {
255 *NumBytes += NI->getOperand(2).getImm();
261 /// mergeSPUpdates - Checks the instruction before/after the passed
262 /// instruction. If it is an ADD/SUB/LEA instruction it is deleted argument and
263 /// the stack adjustment is returned as a positive value for ADD/LEA and a
264 /// negative for SUB.
265 static int mergeSPUpdates(MachineBasicBlock &MBB,
266 MachineBasicBlock::iterator &MBBI, unsigned StackPtr,
267 bool doMergeWithPrevious) {
268 if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
269 (!doMergeWithPrevious && MBBI == MBB.end()))
272 MachineBasicBlock::iterator PI = doMergeWithPrevious ? std::prev(MBBI) : MBBI;
273 MachineBasicBlock::iterator NI = doMergeWithPrevious ? nullptr
275 unsigned Opc = PI->getOpcode();
278 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
279 Opc == X86::ADD32ri || Opc == X86::ADD32ri8 ||
280 Opc == X86::LEA32r || Opc == X86::LEA64_32r) &&
281 PI->getOperand(0).getReg() == StackPtr){
282 Offset += PI->getOperand(2).getImm();
284 if (!doMergeWithPrevious) MBBI = NI;
285 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
286 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
287 PI->getOperand(0).getReg() == StackPtr) {
288 Offset -= PI->getOperand(2).getImm();
290 if (!doMergeWithPrevious) MBBI = NI;
296 static bool isEAXLiveIn(MachineFunction &MF) {
297 for (MachineRegisterInfo::livein_iterator II = MF.getRegInfo().livein_begin(),
298 EE = MF.getRegInfo().livein_end(); II != EE; ++II) {
299 unsigned Reg = II->first;
301 if (Reg == X86::EAX || Reg == X86::AX ||
302 Reg == X86::AH || Reg == X86::AL)
310 X86FrameLowering::emitCalleeSavedFrameMoves(MachineBasicBlock &MBB,
311 MachineBasicBlock::iterator MBBI,
313 MachineFunction &MF = *MBB.getParent();
314 MachineFrameInfo *MFI = MF.getFrameInfo();
315 MachineModuleInfo &MMI = MF.getMMI();
316 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
317 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
319 // Add callee saved registers to move list.
320 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
321 if (CSI.empty()) return;
323 // Calculate offsets.
324 for (std::vector<CalleeSavedInfo>::const_iterator
325 I = CSI.begin(), E = CSI.end(); I != E; ++I) {
326 int64_t Offset = MFI->getObjectOffset(I->getFrameIdx());
327 unsigned Reg = I->getReg();
329 unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true);
331 MMI.addFrameInst(MCCFIInstruction::createOffset(nullptr, DwarfReg,
333 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
334 .addCFIIndex(CFIIndex);
338 /// usesTheStack - This function checks if any of the users of EFLAGS
339 /// copies the EFLAGS. We know that the code that lowers COPY of EFLAGS has
340 /// to use the stack, and if we don't adjust the stack we clobber the first
342 /// See X86InstrInfo::copyPhysReg.
343 static bool usesTheStack(const MachineFunction &MF) {
344 const MachineRegisterInfo &MRI = MF.getRegInfo();
346 for (MachineRegisterInfo::reg_instr_iterator
347 ri = MRI.reg_instr_begin(X86::EFLAGS), re = MRI.reg_instr_end();
355 /// emitPrologue - Push callee-saved registers onto the stack, which
356 /// automatically adjust the stack pointer. Adjust the stack pointer to allocate
357 /// space for local variables. Also emit labels used by the exception handler to
358 /// generate the exception handling frames.
361 Here's a gist of what gets emitted:
363 ; Establish frame pointer, if needed
366 .cfi_def_cfa_offset 16
367 .cfi_offset %rbp, -16
370 .cfi_def_cfa_register %rbp
372 ; Spill general-purpose registers
373 [for all callee-saved GPRs]
376 .cfi_def_cfa_offset (offset from RETADDR)
379 ; If the required stack alignment > default stack alignment
380 ; rsp needs to be re-aligned. This creates a "re-alignment gap"
381 ; of unknown size in the stack frame.
382 [if stack needs re-alignment]
385 ; Allocate space for locals
386 [if target is Windows and allocated space > 4096 bytes]
387 ; Windows needs special care for allocations larger
390 call ___chkstk_ms/___chkstk
396 .seh_stackalloc (size of XMM spill slots)
397 .seh_setframe %rbp, SEHFrameOffset ; = size of all spill slots
402 ; Note, that while only Windows 64 ABI specifies XMMs as callee-preserved,
403 ; they may get spilled on any platform, if the current function
404 ; calls @llvm.eh.unwind.init
406 [for all callee-saved XMM registers]
407 movaps %<xmm reg>, -MMM(%rbp)
408 [for all callee-saved XMM registers]
409 .seh_savexmm %<xmm reg>, (-MMM + SEHFrameOffset)
410 ; i.e. the offset relative to (%rbp - SEHFrameOffset)
412 [for all callee-saved XMM registers]
413 movaps %<xmm reg>, KKK(%rsp)
414 [for all callee-saved XMM registers]
415 .seh_savexmm %<xmm reg>, KKK
419 [if needs base pointer]
424 [for all callee-saved registers]
425 .cfi_offset %<reg>, (offset from %rbp)
427 .cfi_def_cfa_offset (offset from RETADDR)
428 [for all callee-saved registers]
429 .cfi_offset %<reg>, (offset from %rsp)
432 - .seh directives are emitted only for Windows 64 ABI
433 - .cfi directives are emitted for all other ABIs
434 - for 32-bit code, substitute %e?? registers for %r??
437 void X86FrameLowering::emitPrologue(MachineFunction &MF) const {
438 MachineBasicBlock &MBB = MF.front(); // Prologue goes in entry BB.
439 MachineBasicBlock::iterator MBBI = MBB.begin();
440 MachineFrameInfo *MFI = MF.getFrameInfo();
441 const Function *Fn = MF.getFunction();
442 const X86RegisterInfo *RegInfo =
443 static_cast<const X86RegisterInfo *>(MF.getTarget().getRegisterInfo());
444 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
445 MachineModuleInfo &MMI = MF.getMMI();
446 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
447 uint64_t MaxAlign = MFI->getMaxAlignment(); // Desired stack alignment.
448 uint64_t StackSize = MFI->getStackSize(); // Number of bytes to allocate.
449 bool HasFP = hasFP(MF);
450 const X86Subtarget &STI = MF.getTarget().getSubtarget<X86Subtarget>();
451 bool Is64Bit = STI.is64Bit();
452 bool IsLP64 = STI.isTarget64BitLP64();
453 bool IsWin64 = STI.isTargetWin64();
455 MF.getTarget().getMCAsmInfo()->getExceptionHandlingType() ==
456 ExceptionHandling::WinEH; // Not necessarily synonymous with IsWin64.
457 bool NeedsWinEH = IsWinEH && Fn->needsUnwindTableEntry();
459 !IsWinEH && (MMI.hasDebugInfo() || Fn->needsUnwindTableEntry());
460 bool UseLEA = STI.useLeaForSP();
461 unsigned StackAlign = getStackAlignment();
462 unsigned SlotSize = RegInfo->getSlotSize();
463 unsigned FramePtr = RegInfo->getFrameRegister(MF);
464 unsigned StackPtr = RegInfo->getStackRegister();
465 unsigned BasePtr = RegInfo->getBaseRegister();
468 // If we're forcing a stack realignment we can't rely on just the frame
469 // info, we need to know the ABI stack alignment as well in case we
470 // have a call out. Otherwise just make sure we have some alignment - we'll
471 // go with the minimum SlotSize.
472 if (ForceStackAlign) {
474 MaxAlign = (StackAlign > MaxAlign) ? StackAlign : MaxAlign;
475 else if (MaxAlign < SlotSize)
479 // Add RETADDR move area to callee saved frame size.
480 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
481 if (TailCallReturnAddrDelta < 0)
482 X86FI->setCalleeSavedFrameSize(
483 X86FI->getCalleeSavedFrameSize() - TailCallReturnAddrDelta);
485 // If this is x86-64 and the Red Zone is not disabled, if we are a leaf
486 // function, and use up to 128 bytes of stack space, don't have a frame
487 // pointer, calls, or dynamic alloca then we do not need to adjust the
488 // stack pointer (we fit in the Red Zone). We also check that we don't
489 // push and pop from the stack.
490 if (Is64Bit && !Fn->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
491 Attribute::NoRedZone) &&
492 !RegInfo->needsStackRealignment(MF) &&
493 !MFI->hasVarSizedObjects() && // No dynamic alloca.
494 !MFI->adjustsStack() && // No calls.
495 !IsWin64 && // Win64 has no Red Zone
496 !usesTheStack(MF) && // Don't push and pop.
497 !MF.shouldSplitStack()) { // Regular stack
498 uint64_t MinSize = X86FI->getCalleeSavedFrameSize();
499 if (HasFP) MinSize += SlotSize;
500 StackSize = std::max(MinSize, StackSize > 128 ? StackSize - 128 : 0);
501 MFI->setStackSize(StackSize);
504 // Insert stack pointer adjustment for later moving of return addr. Only
505 // applies to tail call optimized functions where the callee argument stack
506 // size is bigger than the callers.
507 if (TailCallReturnAddrDelta < 0) {
509 BuildMI(MBB, MBBI, DL,
510 TII.get(getSUBriOpcode(IsLP64, -TailCallReturnAddrDelta)),
513 .addImm(-TailCallReturnAddrDelta)
514 .setMIFlag(MachineInstr::FrameSetup);
515 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
518 // Mapping for machine moves:
520 // DST: VirtualFP AND
521 // SRC: VirtualFP => DW_CFA_def_cfa_offset
522 // ELSE => DW_CFA_def_cfa
524 // SRC: VirtualFP AND
525 // DST: Register => DW_CFA_def_cfa_register
528 // OFFSET < 0 => DW_CFA_offset_extended_sf
529 // REG < 64 => DW_CFA_offset + Reg
530 // ELSE => DW_CFA_offset_extended
532 uint64_t NumBytes = 0;
533 int stackGrowth = -SlotSize;
536 // Calculate required stack adjustment.
537 uint64_t FrameSize = StackSize - SlotSize;
538 if (RegInfo->needsStackRealignment(MF)) {
539 // Callee-saved registers are pushed on stack before the stack
541 FrameSize -= X86FI->getCalleeSavedFrameSize();
542 NumBytes = (FrameSize + MaxAlign - 1) / MaxAlign * MaxAlign;
544 NumBytes = FrameSize - X86FI->getCalleeSavedFrameSize();
547 // Get the offset of the stack slot for the EBP register, which is
548 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
549 // Update the frame offset adjustment.
550 MFI->setOffsetAdjustment(-NumBytes);
552 // Save EBP/RBP into the appropriate stack slot.
553 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
554 .addReg(FramePtr, RegState::Kill)
555 .setMIFlag(MachineInstr::FrameSetup);
558 // Mark the place where EBP/RBP was saved.
559 // Define the current CFA rule to use the provided offset.
561 unsigned CFIIndex = MMI.addFrameInst(
562 MCCFIInstruction::createDefCfaOffset(nullptr, 2 * stackGrowth));
563 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
564 .addCFIIndex(CFIIndex);
566 // Change the rule for the FramePtr to be an "offset" rule.
567 unsigned DwarfFramePtr = RegInfo->getDwarfRegNum(FramePtr, true);
568 CFIIndex = MMI.addFrameInst(
569 MCCFIInstruction::createOffset(nullptr,
570 DwarfFramePtr, 2 * stackGrowth));
571 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
572 .addCFIIndex(CFIIndex);
576 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_PushReg))
578 .setMIFlag(MachineInstr::FrameSetup);
581 // Update EBP with the new base value.
582 BuildMI(MBB, MBBI, DL,
583 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr)
585 .setMIFlag(MachineInstr::FrameSetup);
588 // Mark effective beginning of when frame pointer becomes valid.
589 // Define the current CFA to use the EBP/RBP register.
590 unsigned DwarfFramePtr = RegInfo->getDwarfRegNum(FramePtr, true);
591 unsigned CFIIndex = MMI.addFrameInst(
592 MCCFIInstruction::createDefCfaRegister(nullptr, DwarfFramePtr));
593 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
594 .addCFIIndex(CFIIndex);
597 // Mark the FramePtr as live-in in every block.
598 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
599 I->addLiveIn(FramePtr);
601 NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
604 // Skip the callee-saved push instructions.
605 bool PushedRegs = false;
606 int StackOffset = 2 * stackGrowth;
608 while (MBBI != MBB.end() &&
609 (MBBI->getOpcode() == X86::PUSH32r ||
610 MBBI->getOpcode() == X86::PUSH64r)) {
612 unsigned Reg = MBBI->getOperand(0).getReg();
615 if (!HasFP && NeedsDwarfCFI) {
616 // Mark callee-saved push instruction.
617 // Define the current CFA rule to use the provided offset.
619 unsigned CFIIndex = MMI.addFrameInst(
620 MCCFIInstruction::createDefCfaOffset(nullptr, StackOffset));
621 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
622 .addCFIIndex(CFIIndex);
623 StackOffset += stackGrowth;
627 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_PushReg)).addImm(Reg).setMIFlag(
628 MachineInstr::FrameSetup);
632 // Realign stack after we pushed callee-saved registers (so that we'll be
633 // able to calculate their offsets from the frame pointer).
634 if (RegInfo->needsStackRealignment(MF)) {
635 assert(HasFP && "There should be a frame pointer if stack is realigned.");
637 BuildMI(MBB, MBBI, DL,
638 TII.get(Is64Bit ? X86::AND64ri32 : X86::AND32ri), StackPtr)
641 .setMIFlag(MachineInstr::FrameSetup);
643 // The EFLAGS implicit def is dead.
644 MI->getOperand(3).setIsDead();
647 // If there is an SUB32ri of ESP immediately before this instruction, merge
648 // the two. This can be the case when tail call elimination is enabled and
649 // the callee has more arguments then the caller.
650 NumBytes -= mergeSPUpdates(MBB, MBBI, StackPtr, true);
652 // If there is an ADD32ri or SUB32ri of ESP immediately after this
653 // instruction, merge the two instructions.
654 mergeSPUpdatesDown(MBB, MBBI, StackPtr, &NumBytes);
656 // Adjust stack pointer: ESP -= numbytes.
658 // Windows and cygwin/mingw require a prologue helper routine when allocating
659 // more than 4K bytes on the stack. Windows uses __chkstk and cygwin/mingw
660 // uses __alloca. __alloca and the 32-bit version of __chkstk will probe the
661 // stack and adjust the stack pointer in one go. The 64-bit version of
662 // __chkstk is only responsible for probing the stack. The 64-bit prologue is
663 // responsible for adjusting the stack pointer. Touching the stack at 4K
664 // increments is necessary to ensure that the guard pages used by the OS
665 // virtual memory manager are allocated in correct sequence.
666 if (NumBytes >= 4096 && STI.isOSWindows() && !STI.isTargetMacho()) {
667 const char *StackProbeSymbol;
670 if (STI.isTargetCygMing()) {
671 StackProbeSymbol = "___chkstk_ms";
673 StackProbeSymbol = "__chkstk";
675 } else if (STI.isTargetCygMing())
676 StackProbeSymbol = "_alloca";
678 StackProbeSymbol = "_chkstk";
680 // Check whether EAX is livein for this function.
681 bool isEAXAlive = isEAXLiveIn(MF);
684 // Sanity check that EAX is not livein for this function.
685 // It should not be, so throw an assert.
686 assert(!Is64Bit && "EAX is livein in x64 case!");
689 BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH32r))
690 .addReg(X86::EAX, RegState::Kill)
691 .setMIFlag(MachineInstr::FrameSetup);
695 // Handle the 64-bit Windows ABI case where we need to call __chkstk.
696 // Function prologue is responsible for adjusting the stack pointer.
697 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri), X86::RAX)
699 .setMIFlag(MachineInstr::FrameSetup);
701 // Allocate NumBytes-4 bytes on stack in case of isEAXAlive.
702 // We'll also use 4 already allocated bytes for EAX.
703 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
704 .addImm(isEAXAlive ? NumBytes - 4 : NumBytes)
705 .setMIFlag(MachineInstr::FrameSetup);
708 BuildMI(MBB, MBBI, DL,
709 TII.get(Is64Bit ? X86::W64ALLOCA : X86::CALLpcrel32))
710 .addExternalSymbol(StackProbeSymbol)
711 .addReg(StackPtr, RegState::Define | RegState::Implicit)
712 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit)
713 .setMIFlag(MachineInstr::FrameSetup);
716 // MSVC x64's __chkstk and cygwin/mingw's ___chkstk_ms do not adjust %rsp
717 // themself. It also does not clobber %rax so we can reuse it when
719 BuildMI(MBB, MBBI, DL, TII.get(X86::SUB64rr), StackPtr)
722 .setMIFlag(MachineInstr::FrameSetup);
726 MachineInstr *MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV32rm),
728 StackPtr, false, NumBytes - 4);
729 MI->setFlag(MachineInstr::FrameSetup);
730 MBB.insert(MBBI, MI);
732 } else if (NumBytes) {
733 emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, IsLP64,
734 UseLEA, TII, *RegInfo);
737 int SEHFrameOffset = 0;
740 // We need to set frame base offset low enough such that all saved
741 // register offsets would be positive relative to it, but we can't
742 // just use NumBytes, because .seh_setframe offset must be <=240.
743 // So we pretend to have only allocated enough space to spill the
744 // non-volatile registers.
745 // We don't care about the rest of stack allocation, because unwinder
746 // will restore SP to (BP - SEHFrameOffset)
747 for (const CalleeSavedInfo &Info : MFI->getCalleeSavedInfo()) {
748 int offset = MFI->getObjectOffset(Info.getFrameIdx());
749 SEHFrameOffset = std::max(SEHFrameOffset, abs(offset));
751 SEHFrameOffset += SEHFrameOffset % 16; // ensure alignmant
753 // This only needs to account for XMM spill slots, GPR slots
754 // are covered by .seh_pushreg's emitted above.
755 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_StackAlloc))
756 .addImm(SEHFrameOffset - X86FI->getCalleeSavedFrameSize())
757 .setMIFlag(MachineInstr::FrameSetup);
759 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_SetFrame))
761 .addImm(SEHFrameOffset)
762 .setMIFlag(MachineInstr::FrameSetup);
764 // SP will be the base register for restoring XMMs
766 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_StackAlloc))
768 .setMIFlag(MachineInstr::FrameSetup);
773 // Skip the rest of register spilling code
774 while (MBBI != MBB.end() && MBBI->getFlag(MachineInstr::FrameSetup))
777 // Emit SEH info for non-GPRs
779 for (const CalleeSavedInfo &Info : MFI->getCalleeSavedInfo()) {
780 unsigned Reg = Info.getReg();
781 if (X86::GR64RegClass.contains(Reg) || X86::GR32RegClass.contains(Reg))
783 assert(X86::FR64RegClass.contains(Reg) && "Unexpected register class");
785 int Offset = getFrameIndexOffset(MF, Info.getFrameIdx());
786 Offset += SEHFrameOffset;
788 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_SaveXMM))
791 .setMIFlag(MachineInstr::FrameSetup);
794 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_EndPrologue))
795 .setMIFlag(MachineInstr::FrameSetup);
798 // If we need a base pointer, set it up here. It's whatever the value
799 // of the stack pointer is at this point. Any variable size objects
800 // will be allocated after this, so we can still use the base pointer
801 // to reference locals.
802 if (RegInfo->hasBasePointer(MF)) {
803 // Update the base pointer with the current stack pointer.
804 unsigned Opc = Is64Bit ? X86::MOV64rr : X86::MOV32rr;
805 BuildMI(MBB, MBBI, DL, TII.get(Opc), BasePtr)
807 .setMIFlag(MachineInstr::FrameSetup);
810 if (((!HasFP && NumBytes) || PushedRegs) && NeedsDwarfCFI) {
811 // Mark end of stack pointer adjustment.
812 if (!HasFP && NumBytes) {
813 // Define the current CFA rule to use the provided offset.
815 unsigned CFIIndex = MMI.addFrameInst(
816 MCCFIInstruction::createDefCfaOffset(nullptr,
817 -StackSize + stackGrowth));
819 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
820 .addCFIIndex(CFIIndex);
823 // Emit DWARF info specifying the offsets of the callee-saved registers.
825 emitCalleeSavedFrameMoves(MBB, MBBI, DL);
829 void X86FrameLowering::emitEpilogue(MachineFunction &MF,
830 MachineBasicBlock &MBB) const {
831 const MachineFrameInfo *MFI = MF.getFrameInfo();
832 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
833 const X86RegisterInfo *RegInfo =
834 static_cast<const X86RegisterInfo *>(MF.getTarget().getRegisterInfo());
835 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
836 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
837 assert(MBBI != MBB.end() && "Returning block has no instructions");
838 unsigned RetOpcode = MBBI->getOpcode();
839 DebugLoc DL = MBBI->getDebugLoc();
840 const X86Subtarget &STI = MF.getTarget().getSubtarget<X86Subtarget>();
841 bool Is64Bit = STI.is64Bit();
842 bool IsLP64 = STI.isTarget64BitLP64();
843 bool UseLEA = STI.useLeaForSP();
844 unsigned StackAlign = getStackAlignment();
845 unsigned SlotSize = RegInfo->getSlotSize();
846 unsigned FramePtr = RegInfo->getFrameRegister(MF);
847 unsigned StackPtr = RegInfo->getStackRegister();
851 llvm_unreachable("Can only insert epilog into returning blocks");
856 case X86::TCRETURNdi:
857 case X86::TCRETURNri:
858 case X86::TCRETURNmi:
859 case X86::TCRETURNdi64:
860 case X86::TCRETURNri64:
861 case X86::TCRETURNmi64:
863 case X86::EH_RETURN64:
864 break; // These are ok
867 // Get the number of bytes to allocate from the FrameInfo.
868 uint64_t StackSize = MFI->getStackSize();
869 uint64_t MaxAlign = MFI->getMaxAlignment();
870 unsigned CSSize = X86FI->getCalleeSavedFrameSize();
871 uint64_t NumBytes = 0;
873 // If we're forcing a stack realignment we can't rely on just the frame
874 // info, we need to know the ABI stack alignment as well in case we
875 // have a call out. Otherwise just make sure we have some alignment - we'll
876 // go with the minimum.
877 if (ForceStackAlign) {
879 MaxAlign = (StackAlign > MaxAlign) ? StackAlign : MaxAlign;
881 MaxAlign = MaxAlign ? MaxAlign : 4;
885 // Calculate required stack adjustment.
886 uint64_t FrameSize = StackSize - SlotSize;
887 if (RegInfo->needsStackRealignment(MF)) {
888 // Callee-saved registers were pushed on stack before the stack
891 NumBytes = (FrameSize + MaxAlign - 1) / MaxAlign * MaxAlign;
893 NumBytes = FrameSize - CSSize;
897 BuildMI(MBB, MBBI, DL,
898 TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr);
900 NumBytes = StackSize - CSSize;
903 // Skip the callee-saved pop instructions.
904 while (MBBI != MBB.begin()) {
905 MachineBasicBlock::iterator PI = std::prev(MBBI);
906 unsigned Opc = PI->getOpcode();
908 if (Opc != X86::POP32r && Opc != X86::POP64r && Opc != X86::DBG_VALUE &&
914 MachineBasicBlock::iterator FirstCSPop = MBBI;
916 DL = MBBI->getDebugLoc();
918 // If there is an ADD32ri or SUB32ri of ESP immediately before this
919 // instruction, merge the two instructions.
920 if (NumBytes || MFI->hasVarSizedObjects())
921 mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
923 // If dynamic alloca is used, then reset esp to point to the last callee-saved
924 // slot before popping them off! Same applies for the case, when stack was
926 if (RegInfo->needsStackRealignment(MF) || MFI->hasVarSizedObjects()) {
927 if (RegInfo->needsStackRealignment(MF))
930 unsigned Opc = getLEArOpcode(IsLP64);
931 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr),
932 FramePtr, false, -CSSize);
934 unsigned Opc = (Is64Bit ? X86::MOV64rr : X86::MOV32rr);
935 BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
938 } else if (NumBytes) {
939 // Adjust stack pointer back: ESP += numbytes.
940 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, IsLP64, UseLEA,
944 // We're returning from function via eh_return.
945 if (RetOpcode == X86::EH_RETURN || RetOpcode == X86::EH_RETURN64) {
946 MBBI = MBB.getLastNonDebugInstr();
947 MachineOperand &DestAddr = MBBI->getOperand(0);
948 assert(DestAddr.isReg() && "Offset should be in register!");
949 BuildMI(MBB, MBBI, DL,
950 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
951 StackPtr).addReg(DestAddr.getReg());
952 } else if (RetOpcode == X86::TCRETURNri || RetOpcode == X86::TCRETURNdi ||
953 RetOpcode == X86::TCRETURNmi ||
954 RetOpcode == X86::TCRETURNri64 || RetOpcode == X86::TCRETURNdi64 ||
955 RetOpcode == X86::TCRETURNmi64) {
956 bool isMem = RetOpcode == X86::TCRETURNmi || RetOpcode == X86::TCRETURNmi64;
957 // Tail call return: adjust the stack pointer and jump to callee.
958 MBBI = MBB.getLastNonDebugInstr();
959 MachineOperand &JumpTarget = MBBI->getOperand(0);
960 MachineOperand &StackAdjust = MBBI->getOperand(isMem ? 5 : 1);
961 assert(StackAdjust.isImm() && "Expecting immediate value.");
963 // Adjust stack pointer.
964 int StackAdj = StackAdjust.getImm();
965 int MaxTCDelta = X86FI->getTCReturnAddrDelta();
967 assert(MaxTCDelta <= 0 && "MaxTCDelta should never be positive");
969 // Incoporate the retaddr area.
970 Offset = StackAdj-MaxTCDelta;
971 assert(Offset >= 0 && "Offset should never be negative");
974 // Check for possible merge with preceding ADD instruction.
975 Offset += mergeSPUpdates(MBB, MBBI, StackPtr, true);
976 emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, IsLP64,
977 UseLEA, TII, *RegInfo);
980 // Jump to label or value in register.
981 if (RetOpcode == X86::TCRETURNdi || RetOpcode == X86::TCRETURNdi64) {
982 MachineInstrBuilder MIB =
983 BuildMI(MBB, MBBI, DL, TII.get((RetOpcode == X86::TCRETURNdi)
984 ? X86::TAILJMPd : X86::TAILJMPd64));
985 if (JumpTarget.isGlobal())
986 MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
987 JumpTarget.getTargetFlags());
989 assert(JumpTarget.isSymbol());
990 MIB.addExternalSymbol(JumpTarget.getSymbolName(),
991 JumpTarget.getTargetFlags());
993 } else if (RetOpcode == X86::TCRETURNmi || RetOpcode == X86::TCRETURNmi64) {
994 MachineInstrBuilder MIB =
995 BuildMI(MBB, MBBI, DL, TII.get((RetOpcode == X86::TCRETURNmi)
996 ? X86::TAILJMPm : X86::TAILJMPm64));
997 for (unsigned i = 0; i != 5; ++i)
998 MIB.addOperand(MBBI->getOperand(i));
999 } else if (RetOpcode == X86::TCRETURNri64) {
1000 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr64)).
1001 addReg(JumpTarget.getReg(), RegState::Kill);
1003 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr)).
1004 addReg(JumpTarget.getReg(), RegState::Kill);
1007 MachineInstr *NewMI = std::prev(MBBI);
1008 NewMI->copyImplicitOps(MF, MBBI);
1010 // Delete the pseudo instruction TCRETURN.
1012 } else if ((RetOpcode == X86::RETQ || RetOpcode == X86::RETL ||
1013 RetOpcode == X86::RETIQ || RetOpcode == X86::RETIL) &&
1014 (X86FI->getTCReturnAddrDelta() < 0)) {
1015 // Add the return addr area delta back since we are not tail calling.
1016 int delta = -1*X86FI->getTCReturnAddrDelta();
1017 MBBI = MBB.getLastNonDebugInstr();
1019 // Check for possible merge with preceding ADD instruction.
1020 delta += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1021 emitSPUpdate(MBB, MBBI, StackPtr, delta, Is64Bit, IsLP64, UseLEA, TII,
1026 int X86FrameLowering::getFrameIndexOffset(const MachineFunction &MF,
1028 const X86RegisterInfo *RegInfo =
1029 static_cast<const X86RegisterInfo*>(MF.getTarget().getRegisterInfo());
1030 const MachineFrameInfo *MFI = MF.getFrameInfo();
1031 int Offset = MFI->getObjectOffset(FI) - getOffsetOfLocalArea();
1032 uint64_t StackSize = MFI->getStackSize();
1034 if (RegInfo->hasBasePointer(MF)) {
1035 assert (hasFP(MF) && "VLAs and dynamic stack realign, but no FP?!");
1037 // Skip the saved EBP.
1038 return Offset + RegInfo->getSlotSize();
1040 assert((-(Offset + StackSize)) % MFI->getObjectAlignment(FI) == 0);
1041 return Offset + StackSize;
1043 } else if (RegInfo->needsStackRealignment(MF)) {
1045 // Skip the saved EBP.
1046 return Offset + RegInfo->getSlotSize();
1048 assert((-(Offset + StackSize)) % MFI->getObjectAlignment(FI) == 0);
1049 return Offset + StackSize;
1051 // FIXME: Support tail calls
1054 return Offset + StackSize;
1056 // Skip the saved EBP.
1057 Offset += RegInfo->getSlotSize();
1059 // Skip the RETADDR move area
1060 const X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1061 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
1062 if (TailCallReturnAddrDelta < 0)
1063 Offset -= TailCallReturnAddrDelta;
1069 int X86FrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI,
1070 unsigned &FrameReg) const {
1071 const X86RegisterInfo *RegInfo =
1072 static_cast<const X86RegisterInfo*>(MF.getTarget().getRegisterInfo());
1073 // We can't calculate offset from frame pointer if the stack is realigned,
1074 // so enforce usage of stack/base pointer. The base pointer is used when we
1075 // have dynamic allocas in addition to dynamic realignment.
1076 if (RegInfo->hasBasePointer(MF))
1077 FrameReg = RegInfo->getBaseRegister();
1078 else if (RegInfo->needsStackRealignment(MF))
1079 FrameReg = RegInfo->getStackRegister();
1081 FrameReg = RegInfo->getFrameRegister(MF);
1082 return getFrameIndexOffset(MF, FI);
1085 bool X86FrameLowering::assignCalleeSavedSpillSlots(
1086 MachineFunction &MF, const TargetRegisterInfo *TRI,
1087 std::vector<CalleeSavedInfo> &CSI) const {
1088 MachineFrameInfo *MFI = MF.getFrameInfo();
1089 const X86RegisterInfo *RegInfo =
1090 static_cast<const X86RegisterInfo *>(MF.getTarget().getRegisterInfo());
1091 unsigned SlotSize = RegInfo->getSlotSize();
1092 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1094 unsigned CalleeSavedFrameSize = 0;
1095 int SpillSlotOffset = getOffsetOfLocalArea() + X86FI->getTCReturnAddrDelta();
1098 // emitPrologue always spills frame register the first thing.
1099 SpillSlotOffset -= SlotSize;
1100 MFI->CreateFixedSpillStackObject(SlotSize, SpillSlotOffset);
1102 // Since emitPrologue and emitEpilogue will handle spilling and restoring of
1103 // the frame register, we can delete it from CSI list and not have to worry
1104 // about avoiding it later.
1105 unsigned FPReg = RegInfo->getFrameRegister(MF);
1106 for (unsigned i = 0; i < CSI.size(); ++i) {
1107 if (CSI[i].getReg() == FPReg) {
1108 CSI.erase(CSI.begin() + i);
1114 // Assign slots for GPRs. It increases frame size.
1115 for (unsigned i = CSI.size(); i != 0; --i) {
1116 unsigned Reg = CSI[i - 1].getReg();
1118 if (!X86::GR64RegClass.contains(Reg) && !X86::GR32RegClass.contains(Reg))
1121 SpillSlotOffset -= SlotSize;
1122 CalleeSavedFrameSize += SlotSize;
1124 int SlotIndex = MFI->CreateFixedSpillStackObject(SlotSize, SpillSlotOffset);
1125 CSI[i - 1].setFrameIdx(SlotIndex);
1128 X86FI->setCalleeSavedFrameSize(CalleeSavedFrameSize);
1130 // Assign slots for XMMs.
1131 for (unsigned i = CSI.size(); i != 0; --i) {
1132 unsigned Reg = CSI[i - 1].getReg();
1133 if (X86::GR64RegClass.contains(Reg) || X86::GR32RegClass.contains(Reg))
1136 const TargetRegisterClass *RC = RegInfo->getMinimalPhysRegClass(Reg);
1138 SpillSlotOffset -= abs(SpillSlotOffset) % RC->getAlignment();
1140 SpillSlotOffset -= RC->getSize();
1142 MFI->CreateFixedSpillStackObject(RC->getSize(), SpillSlotOffset);
1143 CSI[i - 1].setFrameIdx(SlotIndex);
1144 MFI->ensureMaxAlignment(RC->getAlignment());
1150 bool X86FrameLowering::spillCalleeSavedRegisters(
1151 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
1152 const std::vector<CalleeSavedInfo> &CSI,
1153 const TargetRegisterInfo *TRI) const {
1154 DebugLoc DL = MBB.findDebugLoc(MI);
1156 MachineFunction &MF = *MBB.getParent();
1157 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
1158 const X86Subtarget &STI = MF.getTarget().getSubtarget<X86Subtarget>();
1160 // Push GPRs. It increases frame size.
1161 unsigned Opc = STI.is64Bit() ? X86::PUSH64r : X86::PUSH32r;
1162 for (unsigned i = CSI.size(); i != 0; --i) {
1163 unsigned Reg = CSI[i - 1].getReg();
1165 if (!X86::GR64RegClass.contains(Reg) && !X86::GR32RegClass.contains(Reg))
1167 // Add the callee-saved register as live-in. It's killed at the spill.
1170 BuildMI(MBB, MI, DL, TII.get(Opc)).addReg(Reg, RegState::Kill)
1171 .setMIFlag(MachineInstr::FrameSetup);
1174 // Make XMM regs spilled. X86 does not have ability of push/pop XMM.
1175 // It can be done by spilling XMMs to stack frame.
1176 for (unsigned i = CSI.size(); i != 0; --i) {
1177 unsigned Reg = CSI[i-1].getReg();
1178 if (X86::GR64RegClass.contains(Reg) ||
1179 X86::GR32RegClass.contains(Reg))
1181 // Add the callee-saved register as live-in. It's killed at the spill.
1183 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1185 TII.storeRegToStackSlot(MBB, MI, Reg, true, CSI[i - 1].getFrameIdx(), RC,
1188 MI->setFlag(MachineInstr::FrameSetup);
1195 bool X86FrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
1196 MachineBasicBlock::iterator MI,
1197 const std::vector<CalleeSavedInfo> &CSI,
1198 const TargetRegisterInfo *TRI) const {
1202 DebugLoc DL = MBB.findDebugLoc(MI);
1204 MachineFunction &MF = *MBB.getParent();
1205 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
1206 const X86Subtarget &STI = MF.getTarget().getSubtarget<X86Subtarget>();
1208 // Reload XMMs from stack frame.
1209 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1210 unsigned Reg = CSI[i].getReg();
1211 if (X86::GR64RegClass.contains(Reg) ||
1212 X86::GR32RegClass.contains(Reg))
1215 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1216 TII.loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(), RC, TRI);
1220 unsigned Opc = STI.is64Bit() ? X86::POP64r : X86::POP32r;
1221 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1222 unsigned Reg = CSI[i].getReg();
1223 if (!X86::GR64RegClass.contains(Reg) &&
1224 !X86::GR32RegClass.contains(Reg))
1227 BuildMI(MBB, MI, DL, TII.get(Opc), Reg);
1233 X86FrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
1234 RegScavenger *RS) const {
1235 MachineFrameInfo *MFI = MF.getFrameInfo();
1236 const X86RegisterInfo *RegInfo =
1237 static_cast<const X86RegisterInfo *>(MF.getTarget().getRegisterInfo());
1238 unsigned SlotSize = RegInfo->getSlotSize();
1240 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1241 int64_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
1243 if (TailCallReturnAddrDelta < 0) {
1244 // create RETURNADDR area
1253 MFI->CreateFixedObject(-TailCallReturnAddrDelta,
1254 TailCallReturnAddrDelta - SlotSize, true);
1257 // Spill the BasePtr if it's used.
1258 if (RegInfo->hasBasePointer(MF))
1259 MF.getRegInfo().setPhysRegUsed(RegInfo->getBaseRegister());
1263 HasNestArgument(const MachineFunction *MF) {
1264 const Function *F = MF->getFunction();
1265 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
1267 if (I->hasNestAttr())
1273 /// GetScratchRegister - Get a temp register for performing work in the
1274 /// segmented stack and the Erlang/HiPE stack prologue. Depending on platform
1275 /// and the properties of the function either one or two registers will be
1276 /// needed. Set primary to true for the first register, false for the second.
1278 GetScratchRegister(bool Is64Bit, const MachineFunction &MF, bool Primary) {
1279 CallingConv::ID CallingConvention = MF.getFunction()->getCallingConv();
1282 if (CallingConvention == CallingConv::HiPE) {
1284 return Primary ? X86::R14 : X86::R13;
1286 return Primary ? X86::EBX : X86::EDI;
1290 return Primary ? X86::R11 : X86::R12;
1292 bool IsNested = HasNestArgument(&MF);
1294 if (CallingConvention == CallingConv::X86_FastCall ||
1295 CallingConvention == CallingConv::Fast) {
1297 report_fatal_error("Segmented stacks does not support fastcall with "
1298 "nested function.");
1299 return Primary ? X86::EAX : X86::ECX;
1302 return Primary ? X86::EDX : X86::EAX;
1303 return Primary ? X86::ECX : X86::EAX;
1306 // The stack limit in the TCB is set to this many bytes above the actual stack
1308 static const uint64_t kSplitStackAvailable = 256;
1311 X86FrameLowering::adjustForSegmentedStacks(MachineFunction &MF) const {
1312 MachineBasicBlock &prologueMBB = MF.front();
1313 MachineFrameInfo *MFI = MF.getFrameInfo();
1314 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
1316 const X86Subtarget &STI = MF.getTarget().getSubtarget<X86Subtarget>();
1317 bool Is64Bit = STI.is64Bit();
1318 unsigned TlsReg, TlsOffset;
1321 unsigned ScratchReg = GetScratchRegister(Is64Bit, MF, true);
1322 assert(!MF.getRegInfo().isLiveIn(ScratchReg) &&
1323 "Scratch register is live-in");
1325 if (MF.getFunction()->isVarArg())
1326 report_fatal_error("Segmented stacks do not support vararg functions.");
1327 if (!STI.isTargetLinux() && !STI.isTargetDarwin() &&
1328 !STI.isTargetWin32() && !STI.isTargetWin64() && !STI.isTargetFreeBSD())
1329 report_fatal_error("Segmented stacks not supported on this platform.");
1331 // Eventually StackSize will be calculated by a link-time pass; which will
1332 // also decide whether checking code needs to be injected into this particular
1334 StackSize = MFI->getStackSize();
1336 // Do not generate a prologue for functions with a stack of size zero
1340 MachineBasicBlock *allocMBB = MF.CreateMachineBasicBlock();
1341 MachineBasicBlock *checkMBB = MF.CreateMachineBasicBlock();
1342 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1343 bool IsNested = false;
1345 // We need to know if the function has a nest argument only in 64 bit mode.
1347 IsNested = HasNestArgument(&MF);
1349 // The MOV R10, RAX needs to be in a different block, since the RET we emit in
1350 // allocMBB needs to be last (terminating) instruction.
1352 for (MachineBasicBlock::livein_iterator i = prologueMBB.livein_begin(),
1353 e = prologueMBB.livein_end(); i != e; i++) {
1354 allocMBB->addLiveIn(*i);
1355 checkMBB->addLiveIn(*i);
1359 allocMBB->addLiveIn(X86::R10);
1361 MF.push_front(allocMBB);
1362 MF.push_front(checkMBB);
1364 // When the frame size is less than 256 we just compare the stack
1365 // boundary directly to the value of the stack pointer, per gcc.
1366 bool CompareStackPointer = StackSize < kSplitStackAvailable;
1368 // Read the limit off the current stacklet off the stack_guard location.
1370 if (STI.isTargetLinux()) {
1373 } else if (STI.isTargetDarwin()) {
1375 TlsOffset = 0x60 + 90*8; // See pthread_machdep.h. Steal TLS slot 90.
1376 } else if (STI.isTargetWin64()) {
1378 TlsOffset = 0x28; // pvArbitrary, reserved for application use
1379 } else if (STI.isTargetFreeBSD()) {
1383 report_fatal_error("Segmented stacks not supported on this platform.");
1386 if (CompareStackPointer)
1387 ScratchReg = X86::RSP;
1389 BuildMI(checkMBB, DL, TII.get(X86::LEA64r), ScratchReg).addReg(X86::RSP)
1390 .addImm(1).addReg(0).addImm(-StackSize).addReg(0);
1392 BuildMI(checkMBB, DL, TII.get(X86::CMP64rm)).addReg(ScratchReg)
1393 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg);
1395 if (STI.isTargetLinux()) {
1398 } else if (STI.isTargetDarwin()) {
1400 TlsOffset = 0x48 + 90*4;
1401 } else if (STI.isTargetWin32()) {
1403 TlsOffset = 0x14; // pvArbitrary, reserved for application use
1404 } else if (STI.isTargetFreeBSD()) {
1405 report_fatal_error("Segmented stacks not supported on FreeBSD i386.");
1407 report_fatal_error("Segmented stacks not supported on this platform.");
1410 if (CompareStackPointer)
1411 ScratchReg = X86::ESP;
1413 BuildMI(checkMBB, DL, TII.get(X86::LEA32r), ScratchReg).addReg(X86::ESP)
1414 .addImm(1).addReg(0).addImm(-StackSize).addReg(0);
1416 if (STI.isTargetLinux() || STI.isTargetWin32() || STI.isTargetWin64()) {
1417 BuildMI(checkMBB, DL, TII.get(X86::CMP32rm)).addReg(ScratchReg)
1418 .addReg(0).addImm(0).addReg(0).addImm(TlsOffset).addReg(TlsReg);
1419 } else if (STI.isTargetDarwin()) {
1421 // TlsOffset doesn't fit into a mod r/m byte so we need an extra register.
1422 unsigned ScratchReg2;
1424 if (CompareStackPointer) {
1425 // The primary scratch register is available for holding the TLS offset.
1426 ScratchReg2 = GetScratchRegister(Is64Bit, MF, true);
1427 SaveScratch2 = false;
1429 // Need to use a second register to hold the TLS offset
1430 ScratchReg2 = GetScratchRegister(Is64Bit, MF, false);
1432 // Unfortunately, with fastcc the second scratch register may hold an
1434 SaveScratch2 = MF.getRegInfo().isLiveIn(ScratchReg2);
1437 // If Scratch2 is live-in then it needs to be saved.
1438 assert((!MF.getRegInfo().isLiveIn(ScratchReg2) || SaveScratch2) &&
1439 "Scratch register is live-in and not saved");
1442 BuildMI(checkMBB, DL, TII.get(X86::PUSH32r))
1443 .addReg(ScratchReg2, RegState::Kill);
1445 BuildMI(checkMBB, DL, TII.get(X86::MOV32ri), ScratchReg2)
1447 BuildMI(checkMBB, DL, TII.get(X86::CMP32rm))
1449 .addReg(ScratchReg2).addImm(1).addReg(0)
1454 BuildMI(checkMBB, DL, TII.get(X86::POP32r), ScratchReg2);
1458 // This jump is taken if SP >= (Stacklet Limit + Stack Space required).
1459 // It jumps to normal execution of the function body.
1460 BuildMI(checkMBB, DL, TII.get(X86::JA_4)).addMBB(&prologueMBB);
1462 // On 32 bit we first push the arguments size and then the frame size. On 64
1463 // bit, we pass the stack frame size in r10 and the argument size in r11.
1465 // Functions with nested arguments use R10, so it needs to be saved across
1466 // the call to _morestack
1469 BuildMI(allocMBB, DL, TII.get(X86::MOV64rr), X86::RAX).addReg(X86::R10);
1471 BuildMI(allocMBB, DL, TII.get(X86::MOV64ri), X86::R10)
1473 BuildMI(allocMBB, DL, TII.get(X86::MOV64ri), X86::R11)
1474 .addImm(X86FI->getArgumentStackSize());
1475 MF.getRegInfo().setPhysRegUsed(X86::R10);
1476 MF.getRegInfo().setPhysRegUsed(X86::R11);
1478 BuildMI(allocMBB, DL, TII.get(X86::PUSHi32))
1479 .addImm(X86FI->getArgumentStackSize());
1480 BuildMI(allocMBB, DL, TII.get(X86::PUSHi32))
1484 // __morestack is in libgcc
1486 BuildMI(allocMBB, DL, TII.get(X86::CALL64pcrel32))
1487 .addExternalSymbol("__morestack");
1489 BuildMI(allocMBB, DL, TII.get(X86::CALLpcrel32))
1490 .addExternalSymbol("__morestack");
1493 BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET_RESTORE_R10));
1495 BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET));
1497 allocMBB->addSuccessor(&prologueMBB);
1499 checkMBB->addSuccessor(allocMBB);
1500 checkMBB->addSuccessor(&prologueMBB);
1507 /// Erlang programs may need a special prologue to handle the stack size they
1508 /// might need at runtime. That is because Erlang/OTP does not implement a C
1509 /// stack but uses a custom implementation of hybrid stack/heap architecture.
1510 /// (for more information see Eric Stenman's Ph.D. thesis:
1511 /// http://publications.uu.se/uu/fulltext/nbn_se_uu_diva-2688.pdf)
1514 /// temp0 = sp - MaxStack
1515 /// if( temp0 < SP_LIMIT(P) ) goto IncStack else goto OldStart
1519 /// call inc_stack # doubles the stack space
1520 /// temp0 = sp - MaxStack
1521 /// if( temp0 < SP_LIMIT(P) ) goto IncStack else goto OldStart
1522 void X86FrameLowering::adjustForHiPEPrologue(MachineFunction &MF) const {
1523 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
1524 MachineFrameInfo *MFI = MF.getFrameInfo();
1525 const unsigned SlotSize =
1526 static_cast<const X86RegisterInfo *>(MF.getTarget().getRegisterInfo())
1528 const X86Subtarget &STI = MF.getTarget().getSubtarget<X86Subtarget>();
1529 const bool Is64Bit = STI.is64Bit();
1531 // HiPE-specific values
1532 const unsigned HipeLeafWords = 24;
1533 const unsigned CCRegisteredArgs = Is64Bit ? 6 : 5;
1534 const unsigned Guaranteed = HipeLeafWords * SlotSize;
1535 unsigned CallerStkArity = MF.getFunction()->arg_size() > CCRegisteredArgs ?
1536 MF.getFunction()->arg_size() - CCRegisteredArgs : 0;
1537 unsigned MaxStack = MFI->getStackSize() + CallerStkArity*SlotSize + SlotSize;
1539 assert(STI.isTargetLinux() &&
1540 "HiPE prologue is only supported on Linux operating systems.");
1542 // Compute the largest caller's frame that is needed to fit the callees'
1543 // frames. This 'MaxStack' is computed from:
1545 // a) the fixed frame size, which is the space needed for all spilled temps,
1546 // b) outgoing on-stack parameter areas, and
1547 // c) the minimum stack space this function needs to make available for the
1548 // functions it calls (a tunable ABI property).
1549 if (MFI->hasCalls()) {
1550 unsigned MoreStackForCalls = 0;
1552 for (MachineFunction::iterator MBBI = MF.begin(), MBBE = MF.end();
1553 MBBI != MBBE; ++MBBI)
1554 for (MachineBasicBlock::iterator MI = MBBI->begin(), ME = MBBI->end();
1559 // Get callee operand.
1560 const MachineOperand &MO = MI->getOperand(0);
1562 // Only take account of global function calls (no closures etc.).
1566 const Function *F = dyn_cast<Function>(MO.getGlobal());
1570 // Do not update 'MaxStack' for primitive and built-in functions
1571 // (encoded with names either starting with "erlang."/"bif_" or not
1572 // having a ".", such as a simple <Module>.<Function>.<Arity>, or an
1573 // "_", such as the BIF "suspend_0") as they are executed on another
1575 if (F->getName().find("erlang.") != StringRef::npos ||
1576 F->getName().find("bif_") != StringRef::npos ||
1577 F->getName().find_first_of("._") == StringRef::npos)
1580 unsigned CalleeStkArity =
1581 F->arg_size() > CCRegisteredArgs ? F->arg_size()-CCRegisteredArgs : 0;
1582 if (HipeLeafWords - 1 > CalleeStkArity)
1583 MoreStackForCalls = std::max(MoreStackForCalls,
1584 (HipeLeafWords - 1 - CalleeStkArity) * SlotSize);
1586 MaxStack += MoreStackForCalls;
1589 // If the stack frame needed is larger than the guaranteed then runtime checks
1590 // and calls to "inc_stack_0" BIF should be inserted in the assembly prologue.
1591 if (MaxStack > Guaranteed) {
1592 MachineBasicBlock &prologueMBB = MF.front();
1593 MachineBasicBlock *stackCheckMBB = MF.CreateMachineBasicBlock();
1594 MachineBasicBlock *incStackMBB = MF.CreateMachineBasicBlock();
1596 for (MachineBasicBlock::livein_iterator I = prologueMBB.livein_begin(),
1597 E = prologueMBB.livein_end(); I != E; I++) {
1598 stackCheckMBB->addLiveIn(*I);
1599 incStackMBB->addLiveIn(*I);
1602 MF.push_front(incStackMBB);
1603 MF.push_front(stackCheckMBB);
1605 unsigned ScratchReg, SPReg, PReg, SPLimitOffset;
1606 unsigned LEAop, CMPop, CALLop;
1610 LEAop = X86::LEA64r;
1611 CMPop = X86::CMP64rm;
1612 CALLop = X86::CALL64pcrel32;
1613 SPLimitOffset = 0x90;
1617 LEAop = X86::LEA32r;
1618 CMPop = X86::CMP32rm;
1619 CALLop = X86::CALLpcrel32;
1620 SPLimitOffset = 0x4c;
1623 ScratchReg = GetScratchRegister(Is64Bit, MF, true);
1624 assert(!MF.getRegInfo().isLiveIn(ScratchReg) &&
1625 "HiPE prologue scratch register is live-in");
1627 // Create new MBB for StackCheck:
1628 addRegOffset(BuildMI(stackCheckMBB, DL, TII.get(LEAop), ScratchReg),
1629 SPReg, false, -MaxStack);
1630 // SPLimitOffset is in a fixed heap location (pointed by BP).
1631 addRegOffset(BuildMI(stackCheckMBB, DL, TII.get(CMPop))
1632 .addReg(ScratchReg), PReg, false, SPLimitOffset);
1633 BuildMI(stackCheckMBB, DL, TII.get(X86::JAE_4)).addMBB(&prologueMBB);
1635 // Create new MBB for IncStack:
1636 BuildMI(incStackMBB, DL, TII.get(CALLop)).
1637 addExternalSymbol("inc_stack_0");
1638 addRegOffset(BuildMI(incStackMBB, DL, TII.get(LEAop), ScratchReg),
1639 SPReg, false, -MaxStack);
1640 addRegOffset(BuildMI(incStackMBB, DL, TII.get(CMPop))
1641 .addReg(ScratchReg), PReg, false, SPLimitOffset);
1642 BuildMI(incStackMBB, DL, TII.get(X86::JLE_4)).addMBB(incStackMBB);
1644 stackCheckMBB->addSuccessor(&prologueMBB, 99);
1645 stackCheckMBB->addSuccessor(incStackMBB, 1);
1646 incStackMBB->addSuccessor(&prologueMBB, 99);
1647 incStackMBB->addSuccessor(incStackMBB, 1);
1654 void X86FrameLowering::
1655 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
1656 MachineBasicBlock::iterator I) const {
1657 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
1658 const X86RegisterInfo &RegInfo =
1659 *static_cast<const X86RegisterInfo *>(MF.getTarget().getRegisterInfo());
1660 unsigned StackPtr = RegInfo.getStackRegister();
1661 bool reseveCallFrame = hasReservedCallFrame(MF);
1662 int Opcode = I->getOpcode();
1663 bool isDestroy = Opcode == TII.getCallFrameDestroyOpcode();
1664 const X86Subtarget &STI = MF.getTarget().getSubtarget<X86Subtarget>();
1665 bool IsLP64 = STI.isTarget64BitLP64();
1666 DebugLoc DL = I->getDebugLoc();
1667 uint64_t Amount = !reseveCallFrame ? I->getOperand(0).getImm() : 0;
1668 uint64_t CalleeAmt = isDestroy ? I->getOperand(1).getImm() : 0;
1671 if (!reseveCallFrame) {
1672 // If the stack pointer can be changed after prologue, turn the
1673 // adjcallstackup instruction into a 'sub ESP, <amt>' and the
1674 // adjcallstackdown instruction into 'add ESP, <amt>'
1675 // TODO: consider using push / pop instead of sub + store / add
1679 // We need to keep the stack aligned properly. To do this, we round the
1680 // amount of space needed for the outgoing arguments up to the next
1681 // alignment boundary.
1682 unsigned StackAlign =
1683 MF.getTarget().getFrameLowering()->getStackAlignment();
1684 Amount = (Amount + StackAlign - 1) / StackAlign * StackAlign;
1686 MachineInstr *New = nullptr;
1687 if (Opcode == TII.getCallFrameSetupOpcode()) {
1688 New = BuildMI(MF, DL, TII.get(getSUBriOpcode(IsLP64, Amount)),
1693 assert(Opcode == TII.getCallFrameDestroyOpcode());
1695 // Factor out the amount the callee already popped.
1696 Amount -= CalleeAmt;
1699 unsigned Opc = getADDriOpcode(IsLP64, Amount);
1700 New = BuildMI(MF, DL, TII.get(Opc), StackPtr)
1701 .addReg(StackPtr).addImm(Amount);
1706 // The EFLAGS implicit def is dead.
1707 New->getOperand(3).setIsDead();
1709 // Replace the pseudo instruction with a new instruction.
1716 if (Opcode == TII.getCallFrameDestroyOpcode() && CalleeAmt) {
1717 // If we are performing frame pointer elimination and if the callee pops
1718 // something off the stack pointer, add it back. We do this until we have
1719 // more advanced stack pointer tracking ability.
1720 unsigned Opc = getSUBriOpcode(IsLP64, CalleeAmt);
1721 MachineInstr *New = BuildMI(MF, DL, TII.get(Opc), StackPtr)
1722 .addReg(StackPtr).addImm(CalleeAmt);
1724 // The EFLAGS implicit def is dead.
1725 New->getOperand(3).setIsDead();
1727 // We are not tracking the stack pointer adjustment by the callee, so make
1728 // sure we restore the stack pointer immediately after the call, there may
1729 // be spill code inserted between the CALL and ADJCALLSTACKUP instructions.
1730 MachineBasicBlock::iterator B = MBB.begin();
1731 while (I != B && !std::prev(I)->isCall())