1 //===-- X86FrameLowering.cpp - X86 Frame Information ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of TargetFrameLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "X86FrameLowering.h"
15 #include "X86InstrBuilder.h"
16 #include "X86InstrInfo.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/ADT/SmallSet.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineModuleInfo.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/IR/DataLayout.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/MC/MCAsmInfo.h"
29 #include "llvm/MC/MCSymbol.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Target/TargetOptions.h"
32 #include "llvm/Support/Debug.h"
37 // FIXME: completely move here.
38 extern cl::opt<bool> ForceStackAlign;
40 bool X86FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
41 return !MF.getFrameInfo()->hasVarSizedObjects() &&
42 !MF.getInfo<X86MachineFunctionInfo>()->getHasPushSequences();
45 /// canSimplifyCallFramePseudos - If there is a reserved call frame, the
46 /// call frame pseudos can be simplified. Having a FP, as in the default
47 /// implementation, is not sufficient here since we can't always use it.
48 /// Use a more nuanced condition.
50 X86FrameLowering::canSimplifyCallFramePseudos(const MachineFunction &MF) const {
51 const X86RegisterInfo *TRI = static_cast<const X86RegisterInfo *>
52 (MF.getSubtarget().getRegisterInfo());
53 return hasReservedCallFrame(MF) ||
54 (hasFP(MF) && !TRI->needsStackRealignment(MF))
55 || TRI->hasBasePointer(MF);
58 // needsFrameIndexResolution - Do we need to perform FI resolution for
59 // this function. Normally, this is required only when the function
60 // has any stack objects. However, FI resolution actually has another job,
61 // not apparent from the title - it resolves callframesetup/destroy
62 // that were not simplified earlier.
63 // So, this is required for x86 functions that have push sequences even
64 // when there are no stack objects.
66 X86FrameLowering::needsFrameIndexResolution(const MachineFunction &MF) const {
67 return MF.getFrameInfo()->hasStackObjects() ||
68 MF.getInfo<X86MachineFunctionInfo>()->getHasPushSequences();
71 /// hasFP - Return true if the specified function should have a dedicated frame
72 /// pointer register. This is true if the function has variable sized allocas
73 /// or if frame pointer elimination is disabled.
74 bool X86FrameLowering::hasFP(const MachineFunction &MF) const {
75 const MachineFrameInfo *MFI = MF.getFrameInfo();
76 const MachineModuleInfo &MMI = MF.getMMI();
77 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
79 return (MF.getTarget().Options.DisableFramePointerElim(MF) ||
80 RegInfo->needsStackRealignment(MF) ||
81 MFI->hasVarSizedObjects() ||
82 MFI->isFrameAddressTaken() || MFI->hasInlineAsmWithSPAdjust() ||
83 MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
84 MMI.callsUnwindInit() || MMI.callsEHReturn() ||
85 MFI->hasStackMap() || MFI->hasPatchPoint());
88 static unsigned getSUBriOpcode(unsigned IsLP64, int64_t Imm) {
92 return X86::SUB64ri32;
100 static unsigned getADDriOpcode(unsigned IsLP64, int64_t Imm) {
103 return X86::ADD64ri8;
104 return X86::ADD64ri32;
107 return X86::ADD32ri8;
112 static unsigned getSUBrrOpcode(unsigned isLP64) {
113 return isLP64 ? X86::SUB64rr : X86::SUB32rr;
116 static unsigned getADDrrOpcode(unsigned isLP64) {
117 return isLP64 ? X86::ADD64rr : X86::ADD32rr;
120 static unsigned getANDriOpcode(bool IsLP64, int64_t Imm) {
123 return X86::AND64ri8;
124 return X86::AND64ri32;
127 return X86::AND32ri8;
131 static unsigned getLEArOpcode(unsigned IsLP64) {
132 return IsLP64 ? X86::LEA64r : X86::LEA32r;
135 /// findDeadCallerSavedReg - Return a caller-saved register that isn't live
136 /// when it reaches the "return" instruction. We can then pop a stack object
137 /// to this register without worry about clobbering it.
138 static unsigned findDeadCallerSavedReg(MachineBasicBlock &MBB,
139 MachineBasicBlock::iterator &MBBI,
140 const TargetRegisterInfo &TRI,
142 const MachineFunction *MF = MBB.getParent();
143 const Function *F = MF->getFunction();
144 if (!F || MF->getMMI().callsEHReturn())
147 static const uint16_t CallerSavedRegs32Bit[] = {
148 X86::EAX, X86::EDX, X86::ECX, 0
151 static const uint16_t CallerSavedRegs64Bit[] = {
152 X86::RAX, X86::RDX, X86::RCX, X86::RSI, X86::RDI,
153 X86::R8, X86::R9, X86::R10, X86::R11, 0
156 unsigned Opc = MBBI->getOpcode();
163 case X86::TCRETURNdi:
164 case X86::TCRETURNri:
165 case X86::TCRETURNmi:
166 case X86::TCRETURNdi64:
167 case X86::TCRETURNri64:
168 case X86::TCRETURNmi64:
170 case X86::EH_RETURN64: {
171 SmallSet<uint16_t, 8> Uses;
172 for (unsigned i = 0, e = MBBI->getNumOperands(); i != e; ++i) {
173 MachineOperand &MO = MBBI->getOperand(i);
174 if (!MO.isReg() || MO.isDef())
176 unsigned Reg = MO.getReg();
179 for (MCRegAliasIterator AI(Reg, &TRI, true); AI.isValid(); ++AI)
183 const uint16_t *CS = Is64Bit ? CallerSavedRegs64Bit : CallerSavedRegs32Bit;
185 if (!Uses.count(*CS))
193 static bool isEAXLiveIn(MachineFunction &MF) {
194 for (MachineRegisterInfo::livein_iterator II = MF.getRegInfo().livein_begin(),
195 EE = MF.getRegInfo().livein_end(); II != EE; ++II) {
196 unsigned Reg = II->first;
198 if (Reg == X86::RAX || Reg == X86::EAX || Reg == X86::AX ||
199 Reg == X86::AH || Reg == X86::AL)
206 /// emitSPUpdate - Emit a series of instructions to increment / decrement the
207 /// stack pointer by a constant value.
209 void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
210 unsigned StackPtr, int64_t NumBytes,
211 bool Is64BitTarget, bool Is64BitStackPtr, bool UseLEA,
212 const TargetInstrInfo &TII, const TargetRegisterInfo &TRI) {
213 bool isSub = NumBytes < 0;
214 uint64_t Offset = isSub ? -NumBytes : NumBytes;
217 Opc = getLEArOpcode(Is64BitStackPtr);
220 ? getSUBriOpcode(Is64BitStackPtr, Offset)
221 : getADDriOpcode(Is64BitStackPtr, Offset);
223 uint64_t Chunk = (1LL << 31) - 1;
224 DebugLoc DL = MBB.findDebugLoc(MBBI);
227 if (Offset > Chunk) {
228 // Rather than emit a long series of instructions for large offsets,
229 // load the offset into a register and do one sub/add
232 if (isSub && !isEAXLiveIn(*MBB.getParent()))
233 Reg = (unsigned)(Is64BitTarget ? X86::RAX : X86::EAX);
235 Reg = findDeadCallerSavedReg(MBB, MBBI, TRI, Is64BitTarget);
238 Opc = Is64BitTarget ? X86::MOV64ri : X86::MOV32ri;
239 BuildMI(MBB, MBBI, DL, TII.get(Opc), Reg)
242 ? getSUBrrOpcode(Is64BitTarget)
243 : getADDrrOpcode(Is64BitTarget);
244 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
247 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
253 uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset;
254 if (ThisVal == (Is64BitTarget ? 8 : 4)) {
255 // Use push / pop instead.
257 ? (unsigned)(Is64BitTarget ? X86::RAX : X86::EAX)
258 : findDeadCallerSavedReg(MBB, MBBI, TRI, Is64BitTarget);
261 ? (Is64BitTarget ? X86::PUSH64r : X86::PUSH32r)
262 : (Is64BitTarget ? X86::POP64r : X86::POP32r);
263 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc))
264 .addReg(Reg, getDefRegState(!isSub) | getUndefRegState(isSub));
266 MI->setFlag(MachineInstr::FrameSetup);
272 MachineInstr *MI = nullptr;
275 MI = addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr),
276 StackPtr, false, isSub ? -ThisVal : ThisVal);
278 MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
281 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
285 MI->setFlag(MachineInstr::FrameSetup);
291 /// mergeSPUpdatesUp - Merge two stack-manipulating instructions upper iterator.
293 void mergeSPUpdatesUp(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
294 unsigned StackPtr, uint64_t *NumBytes = nullptr) {
295 if (MBBI == MBB.begin()) return;
297 MachineBasicBlock::iterator PI = std::prev(MBBI);
298 unsigned Opc = PI->getOpcode();
299 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
300 Opc == X86::ADD32ri || Opc == X86::ADD32ri8 ||
301 Opc == X86::LEA32r || Opc == X86::LEA64_32r) &&
302 PI->getOperand(0).getReg() == StackPtr) {
304 *NumBytes += PI->getOperand(2).getImm();
306 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
307 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
308 PI->getOperand(0).getReg() == StackPtr) {
310 *NumBytes -= PI->getOperand(2).getImm();
315 /// mergeSPUpdates - Checks the instruction before/after the passed
316 /// instruction. If it is an ADD/SUB/LEA instruction it is deleted argument and
317 /// the stack adjustment is returned as a positive value for ADD/LEA and a
318 /// negative for SUB.
319 static int mergeSPUpdates(MachineBasicBlock &MBB,
320 MachineBasicBlock::iterator &MBBI, unsigned StackPtr,
321 bool doMergeWithPrevious) {
322 if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
323 (!doMergeWithPrevious && MBBI == MBB.end()))
326 MachineBasicBlock::iterator PI = doMergeWithPrevious ? std::prev(MBBI) : MBBI;
327 MachineBasicBlock::iterator NI = doMergeWithPrevious ? nullptr
329 unsigned Opc = PI->getOpcode();
332 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
333 Opc == X86::ADD32ri || Opc == X86::ADD32ri8 ||
334 Opc == X86::LEA32r || Opc == X86::LEA64_32r) &&
335 PI->getOperand(0).getReg() == StackPtr){
336 Offset += PI->getOperand(2).getImm();
338 if (!doMergeWithPrevious) MBBI = NI;
339 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
340 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
341 PI->getOperand(0).getReg() == StackPtr) {
342 Offset -= PI->getOperand(2).getImm();
344 if (!doMergeWithPrevious) MBBI = NI;
351 X86FrameLowering::emitCalleeSavedFrameMoves(MachineBasicBlock &MBB,
352 MachineBasicBlock::iterator MBBI,
354 MachineFunction &MF = *MBB.getParent();
355 MachineFrameInfo *MFI = MF.getFrameInfo();
356 MachineModuleInfo &MMI = MF.getMMI();
357 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
358 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
360 // Add callee saved registers to move list.
361 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
362 if (CSI.empty()) return;
364 // Calculate offsets.
365 for (std::vector<CalleeSavedInfo>::const_iterator
366 I = CSI.begin(), E = CSI.end(); I != E; ++I) {
367 int64_t Offset = MFI->getObjectOffset(I->getFrameIdx());
368 unsigned Reg = I->getReg();
370 unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true);
372 MMI.addFrameInst(MCCFIInstruction::createOffset(nullptr, DwarfReg,
374 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
375 .addCFIIndex(CFIIndex);
379 /// usesTheStack - This function checks if any of the users of EFLAGS
380 /// copies the EFLAGS. We know that the code that lowers COPY of EFLAGS has
381 /// to use the stack, and if we don't adjust the stack we clobber the first
383 /// See X86InstrInfo::copyPhysReg.
384 static bool usesTheStack(const MachineFunction &MF) {
385 const MachineRegisterInfo &MRI = MF.getRegInfo();
387 for (MachineRegisterInfo::reg_instr_iterator
388 ri = MRI.reg_instr_begin(X86::EFLAGS), re = MRI.reg_instr_end();
396 void X86FrameLowering::emitStackProbeCall(MachineFunction &MF,
397 MachineBasicBlock &MBB,
398 MachineBasicBlock::iterator MBBI,
400 const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
401 const TargetInstrInfo &TII = *STI.getInstrInfo();
402 bool Is64Bit = STI.is64Bit();
403 bool IsLargeCodeModel = MF.getTarget().getCodeModel() == CodeModel::Large;
407 CallOp = IsLargeCodeModel ? X86::CALL64r : X86::CALL64pcrel32;
409 CallOp = X86::CALLpcrel32;
413 if (STI.isTargetCygMing()) {
414 Symbol = "___chkstk_ms";
418 } else if (STI.isTargetCygMing())
423 MachineInstrBuilder CI;
425 // All current stack probes take AX and SP as input, clobber flags, and
426 // preserve all registers. x86_64 probes leave RSP unmodified.
427 if (Is64Bit && MF.getTarget().getCodeModel() == CodeModel::Large) {
428 // For the large code model, we have to call through a register. Use R11,
429 // as it is scratch in all supported calling conventions.
430 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri), X86::R11)
431 .addExternalSymbol(Symbol);
432 CI = BuildMI(MBB, MBBI, DL, TII.get(CallOp)).addReg(X86::R11);
434 CI = BuildMI(MBB, MBBI, DL, TII.get(CallOp)).addExternalSymbol(Symbol);
437 unsigned AX = Is64Bit ? X86::RAX : X86::EAX;
438 unsigned SP = Is64Bit ? X86::RSP : X86::ESP;
439 CI.addReg(AX, RegState::Implicit)
440 .addReg(SP, RegState::Implicit)
441 .addReg(AX, RegState::Define | RegState::Implicit)
442 .addReg(SP, RegState::Define | RegState::Implicit)
443 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
446 // MSVC x64's __chkstk and cygwin/mingw's ___chkstk_ms do not adjust %rsp
447 // themselves. It also does not clobber %rax so we can reuse it when
449 BuildMI(MBB, MBBI, DL, TII.get(X86::SUB64rr), X86::RSP)
455 static unsigned calculateSetFPREG(uint64_t SPAdjust) {
456 // Win64 ABI has a less restrictive limitation of 240; 128 works equally well
457 // and might require smaller successive adjustments.
458 const uint64_t Win64MaxSEHOffset = 128;
459 uint64_t SEHFrameOffset = std::min(SPAdjust, Win64MaxSEHOffset);
460 // Win64 ABI requires 16-byte alignment for the UWOP_SET_FPREG opcode.
461 return SEHFrameOffset & -16;
464 // If we're forcing a stack realignment we can't rely on just the frame
465 // info, we need to know the ABI stack alignment as well in case we
466 // have a call out. Otherwise just make sure we have some alignment - we'll
467 // go with the minimum SlotSize.
468 static uint64_t calculateMaxStackAlign(const MachineFunction &MF) {
469 const MachineFrameInfo *MFI = MF.getFrameInfo();
470 uint64_t MaxAlign = MFI->getMaxAlignment(); // Desired stack alignment.
471 const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
472 const X86RegisterInfo *RegInfo = STI.getRegisterInfo();
473 unsigned SlotSize = RegInfo->getSlotSize();
474 unsigned StackAlign = STI.getFrameLowering()->getStackAlignment();
475 if (ForceStackAlign) {
477 MaxAlign = (StackAlign > MaxAlign) ? StackAlign : MaxAlign;
478 else if (MaxAlign < SlotSize)
484 /// emitPrologue - Push callee-saved registers onto the stack, which
485 /// automatically adjust the stack pointer. Adjust the stack pointer to allocate
486 /// space for local variables. Also emit labels used by the exception handler to
487 /// generate the exception handling frames.
490 Here's a gist of what gets emitted:
492 ; Establish frame pointer, if needed
495 .cfi_def_cfa_offset 16
496 .cfi_offset %rbp, -16
499 .cfi_def_cfa_register %rbp
501 ; Spill general-purpose registers
502 [for all callee-saved GPRs]
505 .cfi_def_cfa_offset (offset from RETADDR)
508 ; If the required stack alignment > default stack alignment
509 ; rsp needs to be re-aligned. This creates a "re-alignment gap"
510 ; of unknown size in the stack frame.
511 [if stack needs re-alignment]
514 ; Allocate space for locals
515 [if target is Windows and allocated space > 4096 bytes]
516 ; Windows needs special care for allocations larger
519 call ___chkstk_ms/___chkstk
525 .seh_stackalloc (size of XMM spill slots)
526 .seh_setframe %rbp, SEHFrameOffset ; = size of all spill slots
531 ; Note, that while only Windows 64 ABI specifies XMMs as callee-preserved,
532 ; they may get spilled on any platform, if the current function
533 ; calls @llvm.eh.unwind.init
535 [for all callee-saved XMM registers]
536 movaps %<xmm reg>, -MMM(%rbp)
537 [for all callee-saved XMM registers]
538 .seh_savexmm %<xmm reg>, (-MMM + SEHFrameOffset)
539 ; i.e. the offset relative to (%rbp - SEHFrameOffset)
541 [for all callee-saved XMM registers]
542 movaps %<xmm reg>, KKK(%rsp)
543 [for all callee-saved XMM registers]
544 .seh_savexmm %<xmm reg>, KKK
548 [if needs base pointer]
550 [if needs to restore base pointer]
555 [for all callee-saved registers]
556 .cfi_offset %<reg>, (offset from %rbp)
558 .cfi_def_cfa_offset (offset from RETADDR)
559 [for all callee-saved registers]
560 .cfi_offset %<reg>, (offset from %rsp)
563 - .seh directives are emitted only for Windows 64 ABI
564 - .cfi directives are emitted for all other ABIs
565 - for 32-bit code, substitute %e?? registers for %r??
568 void X86FrameLowering::emitPrologue(MachineFunction &MF) const {
569 MachineBasicBlock &MBB = MF.front(); // Prologue goes in entry BB.
570 MachineBasicBlock::iterator MBBI = MBB.begin();
571 MachineFrameInfo *MFI = MF.getFrameInfo();
572 const Function *Fn = MF.getFunction();
573 const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
574 const X86RegisterInfo *RegInfo = STI.getRegisterInfo();
575 const TargetInstrInfo &TII = *STI.getInstrInfo();
576 MachineModuleInfo &MMI = MF.getMMI();
577 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
578 uint64_t MaxAlign = calculateMaxStackAlign(MF); // Desired stack alignment.
579 uint64_t StackSize = MFI->getStackSize(); // Number of bytes to allocate.
580 bool HasFP = hasFP(MF);
581 bool Is64Bit = STI.is64Bit();
582 // standard x86_64 and NaCl use 64-bit frame/stack pointers, x32 - 32-bit.
583 const bool Uses64BitFramePtr = STI.isTarget64BitLP64() || STI.isTargetNaCl64();
584 bool IsWin64 = STI.isTargetWin64();
585 // Not necessarily synonymous with IsWin64.
586 bool IsWinEH = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
587 bool NeedsWinEH = IsWinEH && Fn->needsUnwindTableEntry();
589 !IsWinEH && (MMI.hasDebugInfo() || Fn->needsUnwindTableEntry());
590 bool UseLEA = STI.useLeaForSP();
591 unsigned SlotSize = RegInfo->getSlotSize();
592 unsigned FramePtr = RegInfo->getFrameRegister(MF);
593 const unsigned MachineFramePtr =
594 STI.isTarget64BitILP32()
595 ? getX86SubSuperRegister(FramePtr, MVT::i64, false)
597 unsigned StackPtr = RegInfo->getStackRegister();
598 unsigned BasePtr = RegInfo->getBaseRegister();
601 // Add RETADDR move area to callee saved frame size.
602 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
603 if (TailCallReturnAddrDelta && IsWinEH)
604 report_fatal_error("Can't handle guaranteed tail call under win64 yet");
606 if (TailCallReturnAddrDelta < 0)
607 X86FI->setCalleeSavedFrameSize(
608 X86FI->getCalleeSavedFrameSize() - TailCallReturnAddrDelta);
610 bool UseStackProbe = (STI.isOSWindows() && !STI.isTargetMachO());
612 // The default stack probe size is 4096 if the function has no stackprobesize
614 unsigned StackProbeSize = 4096;
615 if (Fn->hasFnAttribute("stack-probe-size"))
616 Fn->getFnAttribute("stack-probe-size")
618 .getAsInteger(0, StackProbeSize);
620 // If this is x86-64 and the Red Zone is not disabled, if we are a leaf
621 // function, and use up to 128 bytes of stack space, don't have a frame
622 // pointer, calls, or dynamic alloca then we do not need to adjust the
623 // stack pointer (we fit in the Red Zone). We also check that we don't
624 // push and pop from the stack.
625 if (Is64Bit && !Fn->hasFnAttribute(Attribute::NoRedZone) &&
626 !RegInfo->needsStackRealignment(MF) &&
627 !MFI->hasVarSizedObjects() && // No dynamic alloca.
628 !MFI->adjustsStack() && // No calls.
629 !IsWin64 && // Win64 has no Red Zone
630 !usesTheStack(MF) && // Don't push and pop.
631 !MF.shouldSplitStack()) { // Regular stack
632 uint64_t MinSize = X86FI->getCalleeSavedFrameSize();
633 if (HasFP) MinSize += SlotSize;
634 StackSize = std::max(MinSize, StackSize > 128 ? StackSize - 128 : 0);
635 MFI->setStackSize(StackSize);
638 // Insert stack pointer adjustment for later moving of return addr. Only
639 // applies to tail call optimized functions where the callee argument stack
640 // size is bigger than the callers.
641 if (TailCallReturnAddrDelta < 0) {
643 BuildMI(MBB, MBBI, DL,
644 TII.get(getSUBriOpcode(Uses64BitFramePtr, -TailCallReturnAddrDelta)),
647 .addImm(-TailCallReturnAddrDelta)
648 .setMIFlag(MachineInstr::FrameSetup);
649 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
652 // Mapping for machine moves:
654 // DST: VirtualFP AND
655 // SRC: VirtualFP => DW_CFA_def_cfa_offset
656 // ELSE => DW_CFA_def_cfa
658 // SRC: VirtualFP AND
659 // DST: Register => DW_CFA_def_cfa_register
662 // OFFSET < 0 => DW_CFA_offset_extended_sf
663 // REG < 64 => DW_CFA_offset + Reg
664 // ELSE => DW_CFA_offset_extended
666 uint64_t NumBytes = 0;
667 int stackGrowth = -SlotSize;
670 // Calculate required stack adjustment.
671 uint64_t FrameSize = StackSize - SlotSize;
672 // If required, include space for extra hidden slot for stashing base pointer.
673 if (X86FI->getRestoreBasePointer())
674 FrameSize += SlotSize;
676 NumBytes = FrameSize - X86FI->getCalleeSavedFrameSize();
678 // Callee-saved registers are pushed on stack before the stack is realigned.
679 if (RegInfo->needsStackRealignment(MF) && !IsWinEH)
680 NumBytes = RoundUpToAlignment(NumBytes, MaxAlign);
682 // Get the offset of the stack slot for the EBP register, which is
683 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
684 // Update the frame offset adjustment.
685 MFI->setOffsetAdjustment(-NumBytes);
687 // Save EBP/RBP into the appropriate stack slot.
688 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
689 .addReg(MachineFramePtr, RegState::Kill)
690 .setMIFlag(MachineInstr::FrameSetup);
693 // Mark the place where EBP/RBP was saved.
694 // Define the current CFA rule to use the provided offset.
696 unsigned CFIIndex = MMI.addFrameInst(
697 MCCFIInstruction::createDefCfaOffset(nullptr, 2 * stackGrowth));
698 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
699 .addCFIIndex(CFIIndex);
701 // Change the rule for the FramePtr to be an "offset" rule.
702 unsigned DwarfFramePtr = RegInfo->getDwarfRegNum(MachineFramePtr, true);
703 CFIIndex = MMI.addFrameInst(
704 MCCFIInstruction::createOffset(nullptr,
705 DwarfFramePtr, 2 * stackGrowth));
706 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
707 .addCFIIndex(CFIIndex);
711 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_PushReg))
713 .setMIFlag(MachineInstr::FrameSetup);
717 // Update EBP with the new base value.
718 BuildMI(MBB, MBBI, DL,
719 TII.get(Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr),
722 .setMIFlag(MachineInstr::FrameSetup);
726 // Mark effective beginning of when frame pointer becomes valid.
727 // Define the current CFA to use the EBP/RBP register.
728 unsigned DwarfFramePtr = RegInfo->getDwarfRegNum(MachineFramePtr, true);
729 unsigned CFIIndex = MMI.addFrameInst(
730 MCCFIInstruction::createDefCfaRegister(nullptr, DwarfFramePtr));
731 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
732 .addCFIIndex(CFIIndex);
735 // Mark the FramePtr as live-in in every block.
736 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
737 I->addLiveIn(MachineFramePtr);
739 NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
742 // Skip the callee-saved push instructions.
743 bool PushedRegs = false;
744 int StackOffset = 2 * stackGrowth;
746 while (MBBI != MBB.end() &&
747 (MBBI->getOpcode() == X86::PUSH32r ||
748 MBBI->getOpcode() == X86::PUSH64r)) {
750 unsigned Reg = MBBI->getOperand(0).getReg();
753 if (!HasFP && NeedsDwarfCFI) {
754 // Mark callee-saved push instruction.
755 // Define the current CFA rule to use the provided offset.
757 unsigned CFIIndex = MMI.addFrameInst(
758 MCCFIInstruction::createDefCfaOffset(nullptr, StackOffset));
759 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
760 .addCFIIndex(CFIIndex);
761 StackOffset += stackGrowth;
765 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_PushReg)).addImm(Reg).setMIFlag(
766 MachineInstr::FrameSetup);
770 // Realign stack after we pushed callee-saved registers (so that we'll be
771 // able to calculate their offsets from the frame pointer).
772 // Don't do this for Win64, it needs to realign the stack after the prologue.
773 if (!IsWinEH && RegInfo->needsStackRealignment(MF)) {
774 assert(HasFP && "There should be a frame pointer if stack is realigned.");
775 uint64_t Val = -MaxAlign;
777 BuildMI(MBB, MBBI, DL, TII.get(getANDriOpcode(Uses64BitFramePtr, Val)),
781 .setMIFlag(MachineInstr::FrameSetup);
783 // The EFLAGS implicit def is dead.
784 MI->getOperand(3).setIsDead();
787 // If there is an SUB32ri of ESP immediately before this instruction, merge
788 // the two. This can be the case when tail call elimination is enabled and
789 // the callee has more arguments then the caller.
790 NumBytes -= mergeSPUpdates(MBB, MBBI, StackPtr, true);
792 // Adjust stack pointer: ESP -= numbytes.
794 // Windows and cygwin/mingw require a prologue helper routine when allocating
795 // more than 4K bytes on the stack. Windows uses __chkstk and cygwin/mingw
796 // uses __alloca. __alloca and the 32-bit version of __chkstk will probe the
797 // stack and adjust the stack pointer in one go. The 64-bit version of
798 // __chkstk is only responsible for probing the stack. The 64-bit prologue is
799 // responsible for adjusting the stack pointer. Touching the stack at 4K
800 // increments is necessary to ensure that the guard pages used by the OS
801 // virtual memory manager are allocated in correct sequence.
802 uint64_t AlignedNumBytes = NumBytes;
803 if (IsWinEH && RegInfo->needsStackRealignment(MF))
804 AlignedNumBytes = RoundUpToAlignment(AlignedNumBytes, MaxAlign);
805 if (AlignedNumBytes >= StackProbeSize && UseStackProbe) {
806 // Check whether EAX is livein for this function.
807 bool isEAXAlive = isEAXLiveIn(MF);
810 // Sanity check that EAX is not livein for this function.
811 // It should not be, so throw an assert.
812 assert(!Is64Bit && "EAX is livein in x64 case!");
815 BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH32r))
816 .addReg(X86::EAX, RegState::Kill)
817 .setMIFlag(MachineInstr::FrameSetup);
821 // Handle the 64-bit Windows ABI case where we need to call __chkstk.
822 // Function prologue is responsible for adjusting the stack pointer.
823 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri), X86::RAX)
825 .setMIFlag(MachineInstr::FrameSetup);
827 // Allocate NumBytes-4 bytes on stack in case of isEAXAlive.
828 // We'll also use 4 already allocated bytes for EAX.
829 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
830 .addImm(isEAXAlive ? NumBytes - 4 : NumBytes)
831 .setMIFlag(MachineInstr::FrameSetup);
834 // Save a pointer to the MI where we set AX.
835 MachineBasicBlock::iterator SetRAX = MBBI;
838 // Call __chkstk, __chkstk_ms, or __alloca.
839 emitStackProbeCall(MF, MBB, MBBI, DL);
841 // Apply the frame setup flag to all inserted instrs.
842 for (; SetRAX != MBBI; ++SetRAX)
843 SetRAX->setFlag(MachineInstr::FrameSetup);
847 MachineInstr *MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV32rm),
849 StackPtr, false, NumBytes - 4);
850 MI->setFlag(MachineInstr::FrameSetup);
851 MBB.insert(MBBI, MI);
853 } else if (NumBytes) {
854 emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, Uses64BitFramePtr,
855 UseLEA, TII, *RegInfo);
858 if (NeedsWinEH && NumBytes)
859 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_StackAlloc))
861 .setMIFlag(MachineInstr::FrameSetup);
863 int SEHFrameOffset = 0;
864 if (IsWinEH && HasFP) {
865 SEHFrameOffset = calculateSetFPREG(NumBytes);
866 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::LEA64r), FramePtr),
867 StackPtr, false, SEHFrameOffset);
870 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_SetFrame))
872 .addImm(SEHFrameOffset)
873 .setMIFlag(MachineInstr::FrameSetup);
876 while (MBBI != MBB.end() && MBBI->getFlag(MachineInstr::FrameSetup)) {
877 const MachineInstr *FrameInstr = &*MBBI;
882 if (unsigned Reg = TII.isStoreToStackSlot(FrameInstr, FI)) {
883 if (X86::FR64RegClass.contains(Reg)) {
884 int Offset = getFrameIndexOffset(MF, FI);
885 Offset += SEHFrameOffset;
887 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_SaveXMM))
890 .setMIFlag(MachineInstr::FrameSetup);
897 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_EndPrologue))
898 .setMIFlag(MachineInstr::FrameSetup);
900 // Realign stack after we spilled callee-saved registers (so that we'll be
901 // able to calculate their offsets from the frame pointer).
902 // Win64 requires aligning the stack after the prologue.
903 if (IsWinEH && RegInfo->needsStackRealignment(MF)) {
904 assert(HasFP && "There should be a frame pointer if stack is realigned.");
905 uint64_t Val = -MaxAlign;
907 BuildMI(MBB, MBBI, DL, TII.get(getANDriOpcode(Uses64BitFramePtr, Val)),
911 .setMIFlag(MachineInstr::FrameSetup);
913 // The EFLAGS implicit def is dead.
914 MI->getOperand(3).setIsDead();
917 // If we need a base pointer, set it up here. It's whatever the value
918 // of the stack pointer is at this point. Any variable size objects
919 // will be allocated after this, so we can still use the base pointer
920 // to reference locals.
921 if (RegInfo->hasBasePointer(MF)) {
922 // Update the base pointer with the current stack pointer.
923 unsigned Opc = Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr;
924 BuildMI(MBB, MBBI, DL, TII.get(Opc), BasePtr)
926 .setMIFlag(MachineInstr::FrameSetup);
927 if (X86FI->getRestoreBasePointer()) {
928 // Stash value of base pointer. Saving RSP instead of EBP shortens dependence chain.
929 unsigned Opm = Uses64BitFramePtr ? X86::MOV64mr : X86::MOV32mr;
930 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opm)),
931 FramePtr, true, X86FI->getRestoreBasePointerOffset())
933 .setMIFlag(MachineInstr::FrameSetup);
937 if (((!HasFP && NumBytes) || PushedRegs) && NeedsDwarfCFI) {
938 // Mark end of stack pointer adjustment.
939 if (!HasFP && NumBytes) {
940 // Define the current CFA rule to use the provided offset.
942 unsigned CFIIndex = MMI.addFrameInst(
943 MCCFIInstruction::createDefCfaOffset(nullptr,
944 -StackSize + stackGrowth));
946 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
947 .addCFIIndex(CFIIndex);
950 // Emit DWARF info specifying the offsets of the callee-saved registers.
952 emitCalleeSavedFrameMoves(MBB, MBBI, DL);
956 void X86FrameLowering::emitEpilogue(MachineFunction &MF,
957 MachineBasicBlock &MBB) const {
958 const MachineFrameInfo *MFI = MF.getFrameInfo();
959 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
960 const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
961 const X86RegisterInfo *RegInfo = STI.getRegisterInfo();
962 const TargetInstrInfo &TII = *STI.getInstrInfo();
963 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
964 assert(MBBI != MBB.end() && "Returning block has no instructions");
965 unsigned RetOpcode = MBBI->getOpcode();
966 DebugLoc DL = MBBI->getDebugLoc();
967 bool Is64Bit = STI.is64Bit();
968 // standard x86_64 and NaCl use 64-bit frame/stack pointers, x32 - 32-bit.
969 const bool Uses64BitFramePtr = STI.isTarget64BitLP64() || STI.isTargetNaCl64();
970 const bool Is64BitILP32 = STI.isTarget64BitILP32();
971 bool UseLEA = STI.useLeaForSP();
972 unsigned SlotSize = RegInfo->getSlotSize();
973 unsigned FramePtr = RegInfo->getFrameRegister(MF);
974 unsigned MachineFramePtr =
975 Is64BitILP32 ? getX86SubSuperRegister(FramePtr, MVT::i64, false)
977 unsigned StackPtr = RegInfo->getStackRegister();
979 bool IsWinEH = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
980 bool NeedsWinEH = IsWinEH && MF.getFunction()->needsUnwindTableEntry();
984 llvm_unreachable("Can only insert epilog into returning blocks");
989 case X86::TCRETURNdi:
990 case X86::TCRETURNri:
991 case X86::TCRETURNmi:
992 case X86::TCRETURNdi64:
993 case X86::TCRETURNri64:
994 case X86::TCRETURNmi64:
996 case X86::EH_RETURN64:
997 break; // These are ok
1000 // Get the number of bytes to allocate from the FrameInfo.
1001 uint64_t StackSize = MFI->getStackSize();
1002 uint64_t MaxAlign = calculateMaxStackAlign(MF);
1003 unsigned CSSize = X86FI->getCalleeSavedFrameSize();
1004 uint64_t NumBytes = 0;
1007 // Calculate required stack adjustment.
1008 uint64_t FrameSize = StackSize - SlotSize;
1009 NumBytes = FrameSize - CSSize;
1011 // Callee-saved registers were pushed on stack before the stack was
1013 if (RegInfo->needsStackRealignment(MF) && !IsWinEH)
1014 NumBytes = RoundUpToAlignment(FrameSize, MaxAlign);
1017 BuildMI(MBB, MBBI, DL,
1018 TII.get(Is64Bit ? X86::POP64r : X86::POP32r), MachineFramePtr);
1020 NumBytes = StackSize - CSSize;
1022 uint64_t SEHStackAllocAmt = NumBytes;
1024 // Skip the callee-saved pop instructions.
1025 while (MBBI != MBB.begin()) {
1026 MachineBasicBlock::iterator PI = std::prev(MBBI);
1027 unsigned Opc = PI->getOpcode();
1029 if (Opc != X86::POP32r && Opc != X86::POP64r && Opc != X86::DBG_VALUE &&
1030 !PI->isTerminator())
1035 MachineBasicBlock::iterator FirstCSPop = MBBI;
1037 DL = MBBI->getDebugLoc();
1039 // If there is an ADD32ri or SUB32ri of ESP immediately before this
1040 // instruction, merge the two instructions.
1041 if (NumBytes || MFI->hasVarSizedObjects())
1042 mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
1044 // If dynamic alloca is used, then reset esp to point to the last callee-saved
1045 // slot before popping them off! Same applies for the case, when stack was
1047 if (RegInfo->needsStackRealignment(MF) || MFI->hasVarSizedObjects()) {
1048 if (RegInfo->needsStackRealignment(MF))
1051 unsigned SEHFrameOffset = calculateSetFPREG(SEHStackAllocAmt);
1052 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::LEA64r), StackPtr),
1053 FramePtr, false, SEHStackAllocAmt - SEHFrameOffset);
1055 } else if (CSSize != 0) {
1056 unsigned Opc = getLEArOpcode(Uses64BitFramePtr);
1057 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr),
1058 FramePtr, false, -CSSize);
1061 unsigned Opc = (Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr);
1062 BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
1066 } else if (NumBytes) {
1067 // Adjust stack pointer back: ESP += numbytes.
1068 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, Uses64BitFramePtr, UseLEA,
1073 // Windows unwinder will not invoke function's exception handler if IP is
1074 // either in prologue or in epilogue. This behavior causes a problem when a
1075 // call immediately precedes an epilogue, because the return address points
1076 // into the epilogue. To cope with that, we insert an epilogue marker here,
1077 // then replace it with a 'nop' if it ends up immediately after a CALL in the
1078 // final emitted code.
1080 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_Epilogue));
1082 // We're returning from function via eh_return.
1083 if (RetOpcode == X86::EH_RETURN || RetOpcode == X86::EH_RETURN64) {
1084 MBBI = MBB.getLastNonDebugInstr();
1085 MachineOperand &DestAddr = MBBI->getOperand(0);
1086 assert(DestAddr.isReg() && "Offset should be in register!");
1087 BuildMI(MBB, MBBI, DL,
1088 TII.get(Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr),
1089 StackPtr).addReg(DestAddr.getReg());
1090 } else if (RetOpcode == X86::TCRETURNri || RetOpcode == X86::TCRETURNdi ||
1091 RetOpcode == X86::TCRETURNmi ||
1092 RetOpcode == X86::TCRETURNri64 || RetOpcode == X86::TCRETURNdi64 ||
1093 RetOpcode == X86::TCRETURNmi64) {
1094 bool isMem = RetOpcode == X86::TCRETURNmi || RetOpcode == X86::TCRETURNmi64;
1095 // Tail call return: adjust the stack pointer and jump to callee.
1096 MBBI = MBB.getLastNonDebugInstr();
1097 MachineOperand &JumpTarget = MBBI->getOperand(0);
1098 MachineOperand &StackAdjust = MBBI->getOperand(isMem ? 5 : 1);
1099 assert(StackAdjust.isImm() && "Expecting immediate value.");
1101 // Adjust stack pointer.
1102 int StackAdj = StackAdjust.getImm();
1103 int MaxTCDelta = X86FI->getTCReturnAddrDelta();
1105 assert(MaxTCDelta <= 0 && "MaxTCDelta should never be positive");
1107 // Incoporate the retaddr area.
1108 Offset = StackAdj-MaxTCDelta;
1109 assert(Offset >= 0 && "Offset should never be negative");
1112 // Check for possible merge with preceding ADD instruction.
1113 Offset += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1114 emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, Uses64BitFramePtr,
1115 UseLEA, TII, *RegInfo);
1118 // Jump to label or value in register.
1119 bool IsWin64 = STI.isTargetWin64();
1120 if (RetOpcode == X86::TCRETURNdi || RetOpcode == X86::TCRETURNdi64) {
1121 unsigned Op = (RetOpcode == X86::TCRETURNdi)
1123 : (IsWin64 ? X86::TAILJMPd64_REX : X86::TAILJMPd64);
1124 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII.get(Op));
1125 if (JumpTarget.isGlobal())
1126 MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
1127 JumpTarget.getTargetFlags());
1129 assert(JumpTarget.isSymbol());
1130 MIB.addExternalSymbol(JumpTarget.getSymbolName(),
1131 JumpTarget.getTargetFlags());
1133 } else if (RetOpcode == X86::TCRETURNmi || RetOpcode == X86::TCRETURNmi64) {
1134 unsigned Op = (RetOpcode == X86::TCRETURNmi)
1136 : (IsWin64 ? X86::TAILJMPm64_REX : X86::TAILJMPm64);
1137 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII.get(Op));
1138 for (unsigned i = 0; i != 5; ++i)
1139 MIB.addOperand(MBBI->getOperand(i));
1140 } else if (RetOpcode == X86::TCRETURNri64) {
1141 BuildMI(MBB, MBBI, DL,
1142 TII.get(IsWin64 ? X86::TAILJMPr64_REX : X86::TAILJMPr64))
1143 .addReg(JumpTarget.getReg(), RegState::Kill);
1145 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr)).
1146 addReg(JumpTarget.getReg(), RegState::Kill);
1149 MachineInstr *NewMI = std::prev(MBBI);
1150 NewMI->copyImplicitOps(MF, MBBI);
1152 // Delete the pseudo instruction TCRETURN.
1154 } else if ((RetOpcode == X86::RETQ || RetOpcode == X86::RETL ||
1155 RetOpcode == X86::RETIQ || RetOpcode == X86::RETIL) &&
1156 (X86FI->getTCReturnAddrDelta() < 0)) {
1157 // Add the return addr area delta back since we are not tail calling.
1158 int delta = -1*X86FI->getTCReturnAddrDelta();
1159 MBBI = MBB.getLastNonDebugInstr();
1161 // Check for possible merge with preceding ADD instruction.
1162 delta += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1163 emitSPUpdate(MBB, MBBI, StackPtr, delta, Is64Bit, Uses64BitFramePtr, UseLEA, TII,
1168 int X86FrameLowering::getFrameIndexOffset(const MachineFunction &MF,
1170 const X86RegisterInfo *RegInfo =
1171 MF.getSubtarget<X86Subtarget>().getRegisterInfo();
1172 const MachineFrameInfo *MFI = MF.getFrameInfo();
1173 // Offset will hold the offset from the stack pointer at function entry to the
1175 // We need to factor in additional offsets applied during the prologue to the
1176 // frame, base, and stack pointer depending on which is used.
1177 int Offset = MFI->getObjectOffset(FI) - getOffsetOfLocalArea();
1178 const X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1179 unsigned CSSize = X86FI->getCalleeSavedFrameSize();
1180 uint64_t StackSize = MFI->getStackSize();
1181 unsigned SlotSize = RegInfo->getSlotSize();
1182 bool HasFP = hasFP(MF);
1183 bool IsWinEH = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
1184 int64_t FPDelta = 0;
1187 assert(!MFI->hasCalls() || (StackSize % 16) == 8);
1189 // Calculate required stack adjustment.
1190 uint64_t FrameSize = StackSize - SlotSize;
1191 // If required, include space for extra hidden slot for stashing base pointer.
1192 if (X86FI->getRestoreBasePointer())
1193 FrameSize += SlotSize;
1194 uint64_t NumBytes = FrameSize - CSSize;
1196 uint64_t SEHFrameOffset = calculateSetFPREG(NumBytes);
1197 if (FI && FI == X86FI->getFAIndex())
1198 return -SEHFrameOffset;
1200 // FPDelta is the offset from the "traditional" FP location of the old base
1201 // pointer followed by return address and the location required by the
1202 // restricted Win64 prologue.
1203 // Add FPDelta to all offsets below that go through the frame pointer.
1204 FPDelta = FrameSize - SEHFrameOffset;
1205 assert((!MFI->hasCalls() || (FPDelta % 16) == 0) &&
1206 "FPDelta isn't aligned per the Win64 ABI!");
1210 if (RegInfo->hasBasePointer(MF)) {
1211 assert(HasFP && "VLAs and dynamic stack realign, but no FP?!");
1213 // Skip the saved EBP.
1214 return Offset + SlotSize + FPDelta;
1216 assert((-(Offset + StackSize)) % MFI->getObjectAlignment(FI) == 0);
1217 return Offset + StackSize;
1219 } else if (RegInfo->needsStackRealignment(MF)) {
1221 // Skip the saved EBP.
1222 return Offset + SlotSize + FPDelta;
1224 assert((-(Offset + StackSize)) % MFI->getObjectAlignment(FI) == 0);
1225 return Offset + StackSize;
1227 // FIXME: Support tail calls
1230 return Offset + StackSize;
1232 // Skip the saved EBP.
1235 // Skip the RETADDR move area
1236 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
1237 if (TailCallReturnAddrDelta < 0)
1238 Offset -= TailCallReturnAddrDelta;
1241 return Offset + FPDelta;
1244 int X86FrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI,
1245 unsigned &FrameReg) const {
1246 const X86RegisterInfo *RegInfo =
1247 MF.getSubtarget<X86Subtarget>().getRegisterInfo();
1248 // We can't calculate offset from frame pointer if the stack is realigned,
1249 // so enforce usage of stack/base pointer. The base pointer is used when we
1250 // have dynamic allocas in addition to dynamic realignment.
1251 if (RegInfo->hasBasePointer(MF))
1252 FrameReg = RegInfo->getBaseRegister();
1253 else if (RegInfo->needsStackRealignment(MF))
1254 FrameReg = RegInfo->getStackRegister();
1256 FrameReg = RegInfo->getFrameRegister(MF);
1257 return getFrameIndexOffset(MF, FI);
1260 // Simplified from getFrameIndexOffset keeping only StackPointer cases
1261 int X86FrameLowering::getFrameIndexOffsetFromSP(const MachineFunction &MF, int FI) const {
1262 const MachineFrameInfo *MFI = MF.getFrameInfo();
1263 // Does not include any dynamic realign.
1264 const uint64_t StackSize = MFI->getStackSize();
1267 const X86RegisterInfo *RegInfo =
1268 MF.getSubtarget<X86Subtarget>().getRegisterInfo();
1269 // Note: LLVM arranges the stack as:
1270 // Args > Saved RetPC (<--FP) > CSRs > dynamic alignment (<--BP)
1271 // > "Stack Slots" (<--SP)
1272 // We can always address StackSlots from RSP. We can usually (unless
1273 // needsStackRealignment) address CSRs from RSP, but sometimes need to
1274 // address them from RBP. FixedObjects can be placed anywhere in the stack
1275 // frame depending on their specific requirements (i.e. we can actually
1276 // refer to arguments to the function which are stored in the *callers*
1277 // frame). As a result, THE RESULT OF THIS CALL IS MEANINGLESS FOR CSRs
1278 // AND FixedObjects IFF needsStackRealignment or hasVarSizedObject.
1280 assert(!RegInfo->hasBasePointer(MF) && "we don't handle this case");
1282 // We don't handle tail calls, and shouldn't be seeing them
1284 int TailCallReturnAddrDelta =
1285 MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta();
1286 assert(!(TailCallReturnAddrDelta < 0) && "we don't handle this case!");
1290 // This is how the math works out:
1292 // %rsp grows (i.e. gets lower) left to right. Each box below is
1293 // one word (eight bytes). Obj0 is the stack slot we're trying to
1296 // ----------------------------------
1297 // | BP | Obj0 | Obj1 | ... | ObjN |
1298 // ----------------------------------
1302 // A is the incoming stack pointer.
1303 // (B - A) is the local area offset (-8 for x86-64) [1]
1304 // (C - A) is the Offset returned by MFI->getObjectOffset for Obj0 [2]
1306 // |(E - B)| is the StackSize (absolute value, positive). For a
1307 // stack that grown down, this works out to be (B - E). [3]
1309 // E is also the value of %rsp after stack has been set up, and we
1310 // want (C - E) -- the value we can add to %rsp to get to Obj0. Now
1311 // (C - E) == (C - A) - (B - A) + (B - E)
1312 // { Using [1], [2] and [3] above }
1313 // == getObjectOffset - LocalAreaOffset + StackSize
1316 // Get the Offset from the StackPointer
1317 int Offset = MFI->getObjectOffset(FI) - getOffsetOfLocalArea();
1319 return Offset + StackSize;
1321 // Simplified from getFrameIndexReference keeping only StackPointer cases
1322 int X86FrameLowering::getFrameIndexReferenceFromSP(const MachineFunction &MF,
1324 unsigned &FrameReg) const {
1325 const X86RegisterInfo *RegInfo =
1326 MF.getSubtarget<X86Subtarget>().getRegisterInfo();
1327 assert(!RegInfo->hasBasePointer(MF) && "we don't handle this case");
1329 FrameReg = RegInfo->getStackRegister();
1330 return getFrameIndexOffsetFromSP(MF, FI);
1333 bool X86FrameLowering::assignCalleeSavedSpillSlots(
1334 MachineFunction &MF, const TargetRegisterInfo *TRI,
1335 std::vector<CalleeSavedInfo> &CSI) const {
1336 MachineFrameInfo *MFI = MF.getFrameInfo();
1337 const X86RegisterInfo *RegInfo =
1338 MF.getSubtarget<X86Subtarget>().getRegisterInfo();
1339 unsigned SlotSize = RegInfo->getSlotSize();
1340 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1342 unsigned CalleeSavedFrameSize = 0;
1343 int SpillSlotOffset = getOffsetOfLocalArea() + X86FI->getTCReturnAddrDelta();
1346 // emitPrologue always spills frame register the first thing.
1347 SpillSlotOffset -= SlotSize;
1348 MFI->CreateFixedSpillStackObject(SlotSize, SpillSlotOffset);
1350 // Since emitPrologue and emitEpilogue will handle spilling and restoring of
1351 // the frame register, we can delete it from CSI list and not have to worry
1352 // about avoiding it later.
1353 unsigned FPReg = RegInfo->getFrameRegister(MF);
1354 for (unsigned i = 0; i < CSI.size(); ++i) {
1355 if (TRI->regsOverlap(CSI[i].getReg(),FPReg)) {
1356 CSI.erase(CSI.begin() + i);
1362 // Assign slots for GPRs. It increases frame size.
1363 for (unsigned i = CSI.size(); i != 0; --i) {
1364 unsigned Reg = CSI[i - 1].getReg();
1366 if (!X86::GR64RegClass.contains(Reg) && !X86::GR32RegClass.contains(Reg))
1369 SpillSlotOffset -= SlotSize;
1370 CalleeSavedFrameSize += SlotSize;
1372 int SlotIndex = MFI->CreateFixedSpillStackObject(SlotSize, SpillSlotOffset);
1373 CSI[i - 1].setFrameIdx(SlotIndex);
1376 X86FI->setCalleeSavedFrameSize(CalleeSavedFrameSize);
1378 // Assign slots for XMMs.
1379 for (unsigned i = CSI.size(); i != 0; --i) {
1380 unsigned Reg = CSI[i - 1].getReg();
1381 if (X86::GR64RegClass.contains(Reg) || X86::GR32RegClass.contains(Reg))
1384 const TargetRegisterClass *RC = RegInfo->getMinimalPhysRegClass(Reg);
1386 SpillSlotOffset -= std::abs(SpillSlotOffset) % RC->getAlignment();
1388 SpillSlotOffset -= RC->getSize();
1390 MFI->CreateFixedSpillStackObject(RC->getSize(), SpillSlotOffset);
1391 CSI[i - 1].setFrameIdx(SlotIndex);
1392 MFI->ensureMaxAlignment(RC->getAlignment());
1398 bool X86FrameLowering::spillCalleeSavedRegisters(
1399 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
1400 const std::vector<CalleeSavedInfo> &CSI,
1401 const TargetRegisterInfo *TRI) const {
1402 DebugLoc DL = MBB.findDebugLoc(MI);
1404 MachineFunction &MF = *MBB.getParent();
1405 const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
1406 const TargetInstrInfo &TII = *STI.getInstrInfo();
1408 // Push GPRs. It increases frame size.
1409 unsigned Opc = STI.is64Bit() ? X86::PUSH64r : X86::PUSH32r;
1410 for (unsigned i = CSI.size(); i != 0; --i) {
1411 unsigned Reg = CSI[i - 1].getReg();
1413 if (!X86::GR64RegClass.contains(Reg) && !X86::GR32RegClass.contains(Reg))
1415 // Add the callee-saved register as live-in. It's killed at the spill.
1418 BuildMI(MBB, MI, DL, TII.get(Opc)).addReg(Reg, RegState::Kill)
1419 .setMIFlag(MachineInstr::FrameSetup);
1422 // Make XMM regs spilled. X86 does not have ability of push/pop XMM.
1423 // It can be done by spilling XMMs to stack frame.
1424 for (unsigned i = CSI.size(); i != 0; --i) {
1425 unsigned Reg = CSI[i-1].getReg();
1426 if (X86::GR64RegClass.contains(Reg) || X86::GR32RegClass.contains(Reg))
1428 // Add the callee-saved register as live-in. It's killed at the spill.
1430 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1432 TII.storeRegToStackSlot(MBB, MI, Reg, true, CSI[i - 1].getFrameIdx(), RC,
1435 MI->setFlag(MachineInstr::FrameSetup);
1442 bool X86FrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
1443 MachineBasicBlock::iterator MI,
1444 const std::vector<CalleeSavedInfo> &CSI,
1445 const TargetRegisterInfo *TRI) const {
1449 DebugLoc DL = MBB.findDebugLoc(MI);
1451 MachineFunction &MF = *MBB.getParent();
1452 const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
1453 const TargetInstrInfo &TII = *STI.getInstrInfo();
1455 // Reload XMMs from stack frame.
1456 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1457 unsigned Reg = CSI[i].getReg();
1458 if (X86::GR64RegClass.contains(Reg) ||
1459 X86::GR32RegClass.contains(Reg))
1462 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1463 TII.loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(), RC, TRI);
1467 unsigned Opc = STI.is64Bit() ? X86::POP64r : X86::POP32r;
1468 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1469 unsigned Reg = CSI[i].getReg();
1470 if (!X86::GR64RegClass.contains(Reg) &&
1471 !X86::GR32RegClass.contains(Reg))
1474 BuildMI(MBB, MI, DL, TII.get(Opc), Reg);
1480 X86FrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
1481 RegScavenger *RS) const {
1482 MachineFrameInfo *MFI = MF.getFrameInfo();
1483 const X86RegisterInfo *RegInfo =
1484 MF.getSubtarget<X86Subtarget>().getRegisterInfo();
1485 unsigned SlotSize = RegInfo->getSlotSize();
1487 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1488 int64_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
1490 if (TailCallReturnAddrDelta < 0) {
1491 // create RETURNADDR area
1500 MFI->CreateFixedObject(-TailCallReturnAddrDelta,
1501 TailCallReturnAddrDelta - SlotSize, true);
1504 // Spill the BasePtr if it's used.
1505 if (RegInfo->hasBasePointer(MF))
1506 MF.getRegInfo().setPhysRegUsed(RegInfo->getBaseRegister());
1510 HasNestArgument(const MachineFunction *MF) {
1511 const Function *F = MF->getFunction();
1512 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
1514 if (I->hasNestAttr())
1520 /// GetScratchRegister - Get a temp register for performing work in the
1521 /// segmented stack and the Erlang/HiPE stack prologue. Depending on platform
1522 /// and the properties of the function either one or two registers will be
1523 /// needed. Set primary to true for the first register, false for the second.
1525 GetScratchRegister(bool Is64Bit, bool IsLP64, const MachineFunction &MF, bool Primary) {
1526 CallingConv::ID CallingConvention = MF.getFunction()->getCallingConv();
1529 if (CallingConvention == CallingConv::HiPE) {
1531 return Primary ? X86::R14 : X86::R13;
1533 return Primary ? X86::EBX : X86::EDI;
1538 return Primary ? X86::R11 : X86::R12;
1540 return Primary ? X86::R11D : X86::R12D;
1543 bool IsNested = HasNestArgument(&MF);
1545 if (CallingConvention == CallingConv::X86_FastCall ||
1546 CallingConvention == CallingConv::Fast) {
1548 report_fatal_error("Segmented stacks does not support fastcall with "
1549 "nested function.");
1550 return Primary ? X86::EAX : X86::ECX;
1553 return Primary ? X86::EDX : X86::EAX;
1554 return Primary ? X86::ECX : X86::EAX;
1557 // The stack limit in the TCB is set to this many bytes above the actual stack
1559 static const uint64_t kSplitStackAvailable = 256;
1562 X86FrameLowering::adjustForSegmentedStacks(MachineFunction &MF) const {
1563 MachineBasicBlock &prologueMBB = MF.front();
1564 MachineFrameInfo *MFI = MF.getFrameInfo();
1565 const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
1566 const TargetInstrInfo &TII = *STI.getInstrInfo();
1568 bool Is64Bit = STI.is64Bit();
1569 const bool IsLP64 = STI.isTarget64BitLP64();
1570 unsigned TlsReg, TlsOffset;
1573 unsigned ScratchReg = GetScratchRegister(Is64Bit, IsLP64, MF, true);
1574 assert(!MF.getRegInfo().isLiveIn(ScratchReg) &&
1575 "Scratch register is live-in");
1577 if (MF.getFunction()->isVarArg())
1578 report_fatal_error("Segmented stacks do not support vararg functions.");
1579 if (!STI.isTargetLinux() && !STI.isTargetDarwin() && !STI.isTargetWin32() &&
1580 !STI.isTargetWin64() && !STI.isTargetFreeBSD() &&
1581 !STI.isTargetDragonFly())
1582 report_fatal_error("Segmented stacks not supported on this platform.");
1584 // Eventually StackSize will be calculated by a link-time pass; which will
1585 // also decide whether checking code needs to be injected into this particular
1587 StackSize = MFI->getStackSize();
1589 // Do not generate a prologue for functions with a stack of size zero
1593 MachineBasicBlock *allocMBB = MF.CreateMachineBasicBlock();
1594 MachineBasicBlock *checkMBB = MF.CreateMachineBasicBlock();
1595 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1596 bool IsNested = false;
1598 // We need to know if the function has a nest argument only in 64 bit mode.
1600 IsNested = HasNestArgument(&MF);
1602 // The MOV R10, RAX needs to be in a different block, since the RET we emit in
1603 // allocMBB needs to be last (terminating) instruction.
1605 for (MachineBasicBlock::livein_iterator i = prologueMBB.livein_begin(),
1606 e = prologueMBB.livein_end(); i != e; i++) {
1607 allocMBB->addLiveIn(*i);
1608 checkMBB->addLiveIn(*i);
1612 allocMBB->addLiveIn(IsLP64 ? X86::R10 : X86::R10D);
1614 MF.push_front(allocMBB);
1615 MF.push_front(checkMBB);
1617 // When the frame size is less than 256 we just compare the stack
1618 // boundary directly to the value of the stack pointer, per gcc.
1619 bool CompareStackPointer = StackSize < kSplitStackAvailable;
1621 // Read the limit off the current stacklet off the stack_guard location.
1623 if (STI.isTargetLinux()) {
1625 TlsOffset = IsLP64 ? 0x70 : 0x40;
1626 } else if (STI.isTargetDarwin()) {
1628 TlsOffset = 0x60 + 90*8; // See pthread_machdep.h. Steal TLS slot 90.
1629 } else if (STI.isTargetWin64()) {
1631 TlsOffset = 0x28; // pvArbitrary, reserved for application use
1632 } else if (STI.isTargetFreeBSD()) {
1635 } else if (STI.isTargetDragonFly()) {
1637 TlsOffset = 0x20; // use tls_tcb.tcb_segstack
1639 report_fatal_error("Segmented stacks not supported on this platform.");
1642 if (CompareStackPointer)
1643 ScratchReg = IsLP64 ? X86::RSP : X86::ESP;
1645 BuildMI(checkMBB, DL, TII.get(IsLP64 ? X86::LEA64r : X86::LEA64_32r), ScratchReg).addReg(X86::RSP)
1646 .addImm(1).addReg(0).addImm(-StackSize).addReg(0);
1648 BuildMI(checkMBB, DL, TII.get(IsLP64 ? X86::CMP64rm : X86::CMP32rm)).addReg(ScratchReg)
1649 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg);
1651 if (STI.isTargetLinux()) {
1654 } else if (STI.isTargetDarwin()) {
1656 TlsOffset = 0x48 + 90*4;
1657 } else if (STI.isTargetWin32()) {
1659 TlsOffset = 0x14; // pvArbitrary, reserved for application use
1660 } else if (STI.isTargetDragonFly()) {
1662 TlsOffset = 0x10; // use tls_tcb.tcb_segstack
1663 } else if (STI.isTargetFreeBSD()) {
1664 report_fatal_error("Segmented stacks not supported on FreeBSD i386.");
1666 report_fatal_error("Segmented stacks not supported on this platform.");
1669 if (CompareStackPointer)
1670 ScratchReg = X86::ESP;
1672 BuildMI(checkMBB, DL, TII.get(X86::LEA32r), ScratchReg).addReg(X86::ESP)
1673 .addImm(1).addReg(0).addImm(-StackSize).addReg(0);
1675 if (STI.isTargetLinux() || STI.isTargetWin32() || STI.isTargetWin64() ||
1676 STI.isTargetDragonFly()) {
1677 BuildMI(checkMBB, DL, TII.get(X86::CMP32rm)).addReg(ScratchReg)
1678 .addReg(0).addImm(0).addReg(0).addImm(TlsOffset).addReg(TlsReg);
1679 } else if (STI.isTargetDarwin()) {
1681 // TlsOffset doesn't fit into a mod r/m byte so we need an extra register.
1682 unsigned ScratchReg2;
1684 if (CompareStackPointer) {
1685 // The primary scratch register is available for holding the TLS offset.
1686 ScratchReg2 = GetScratchRegister(Is64Bit, IsLP64, MF, true);
1687 SaveScratch2 = false;
1689 // Need to use a second register to hold the TLS offset
1690 ScratchReg2 = GetScratchRegister(Is64Bit, IsLP64, MF, false);
1692 // Unfortunately, with fastcc the second scratch register may hold an
1694 SaveScratch2 = MF.getRegInfo().isLiveIn(ScratchReg2);
1697 // If Scratch2 is live-in then it needs to be saved.
1698 assert((!MF.getRegInfo().isLiveIn(ScratchReg2) || SaveScratch2) &&
1699 "Scratch register is live-in and not saved");
1702 BuildMI(checkMBB, DL, TII.get(X86::PUSH32r))
1703 .addReg(ScratchReg2, RegState::Kill);
1705 BuildMI(checkMBB, DL, TII.get(X86::MOV32ri), ScratchReg2)
1707 BuildMI(checkMBB, DL, TII.get(X86::CMP32rm))
1709 .addReg(ScratchReg2).addImm(1).addReg(0)
1714 BuildMI(checkMBB, DL, TII.get(X86::POP32r), ScratchReg2);
1718 // This jump is taken if SP >= (Stacklet Limit + Stack Space required).
1719 // It jumps to normal execution of the function body.
1720 BuildMI(checkMBB, DL, TII.get(X86::JA_1)).addMBB(&prologueMBB);
1722 // On 32 bit we first push the arguments size and then the frame size. On 64
1723 // bit, we pass the stack frame size in r10 and the argument size in r11.
1725 // Functions with nested arguments use R10, so it needs to be saved across
1726 // the call to _morestack
1728 const unsigned RegAX = IsLP64 ? X86::RAX : X86::EAX;
1729 const unsigned Reg10 = IsLP64 ? X86::R10 : X86::R10D;
1730 const unsigned Reg11 = IsLP64 ? X86::R11 : X86::R11D;
1731 const unsigned MOVrr = IsLP64 ? X86::MOV64rr : X86::MOV32rr;
1732 const unsigned MOVri = IsLP64 ? X86::MOV64ri : X86::MOV32ri;
1735 BuildMI(allocMBB, DL, TII.get(MOVrr), RegAX).addReg(Reg10);
1737 BuildMI(allocMBB, DL, TII.get(MOVri), Reg10)
1739 BuildMI(allocMBB, DL, TII.get(MOVri), Reg11)
1740 .addImm(X86FI->getArgumentStackSize());
1741 MF.getRegInfo().setPhysRegUsed(Reg10);
1742 MF.getRegInfo().setPhysRegUsed(Reg11);
1744 BuildMI(allocMBB, DL, TII.get(X86::PUSHi32))
1745 .addImm(X86FI->getArgumentStackSize());
1746 BuildMI(allocMBB, DL, TII.get(X86::PUSHi32))
1750 // __morestack is in libgcc
1751 if (Is64Bit && MF.getTarget().getCodeModel() == CodeModel::Large) {
1752 // Under the large code model, we cannot assume that __morestack lives
1753 // within 2^31 bytes of the call site, so we cannot use pc-relative
1754 // addressing. We cannot perform the call via a temporary register,
1755 // as the rax register may be used to store the static chain, and all
1756 // other suitable registers may be either callee-save or used for
1757 // parameter passing. We cannot use the stack at this point either
1758 // because __morestack manipulates the stack directly.
1760 // To avoid these issues, perform an indirect call via a read-only memory
1761 // location containing the address.
1763 // This solution is not perfect, as it assumes that the .rodata section
1764 // is laid out within 2^31 bytes of each function body, but this seems
1765 // to be sufficient for JIT.
1766 BuildMI(allocMBB, DL, TII.get(X86::CALL64m))
1770 .addExternalSymbol("__morestack_addr")
1772 MF.getMMI().setUsesMorestackAddr(true);
1775 BuildMI(allocMBB, DL, TII.get(X86::CALL64pcrel32))
1776 .addExternalSymbol("__morestack");
1778 BuildMI(allocMBB, DL, TII.get(X86::CALLpcrel32))
1779 .addExternalSymbol("__morestack");
1783 BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET_RESTORE_R10));
1785 BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET));
1787 allocMBB->addSuccessor(&prologueMBB);
1789 checkMBB->addSuccessor(allocMBB);
1790 checkMBB->addSuccessor(&prologueMBB);
1797 /// Erlang programs may need a special prologue to handle the stack size they
1798 /// might need at runtime. That is because Erlang/OTP does not implement a C
1799 /// stack but uses a custom implementation of hybrid stack/heap architecture.
1800 /// (for more information see Eric Stenman's Ph.D. thesis:
1801 /// http://publications.uu.se/uu/fulltext/nbn_se_uu_diva-2688.pdf)
1804 /// temp0 = sp - MaxStack
1805 /// if( temp0 < SP_LIMIT(P) ) goto IncStack else goto OldStart
1809 /// call inc_stack # doubles the stack space
1810 /// temp0 = sp - MaxStack
1811 /// if( temp0 < SP_LIMIT(P) ) goto IncStack else goto OldStart
1812 void X86FrameLowering::adjustForHiPEPrologue(MachineFunction &MF) const {
1813 const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
1814 const TargetInstrInfo &TII = *STI.getInstrInfo();
1815 MachineFrameInfo *MFI = MF.getFrameInfo();
1816 const unsigned SlotSize = STI.getRegisterInfo()->getSlotSize();
1817 const bool Is64Bit = STI.is64Bit();
1818 const bool IsLP64 = STI.isTarget64BitLP64();
1820 // HiPE-specific values
1821 const unsigned HipeLeafWords = 24;
1822 const unsigned CCRegisteredArgs = Is64Bit ? 6 : 5;
1823 const unsigned Guaranteed = HipeLeafWords * SlotSize;
1824 unsigned CallerStkArity = MF.getFunction()->arg_size() > CCRegisteredArgs ?
1825 MF.getFunction()->arg_size() - CCRegisteredArgs : 0;
1826 unsigned MaxStack = MFI->getStackSize() + CallerStkArity*SlotSize + SlotSize;
1828 assert(STI.isTargetLinux() &&
1829 "HiPE prologue is only supported on Linux operating systems.");
1831 // Compute the largest caller's frame that is needed to fit the callees'
1832 // frames. This 'MaxStack' is computed from:
1834 // a) the fixed frame size, which is the space needed for all spilled temps,
1835 // b) outgoing on-stack parameter areas, and
1836 // c) the minimum stack space this function needs to make available for the
1837 // functions it calls (a tunable ABI property).
1838 if (MFI->hasCalls()) {
1839 unsigned MoreStackForCalls = 0;
1841 for (MachineFunction::iterator MBBI = MF.begin(), MBBE = MF.end();
1842 MBBI != MBBE; ++MBBI)
1843 for (MachineBasicBlock::iterator MI = MBBI->begin(), ME = MBBI->end();
1848 // Get callee operand.
1849 const MachineOperand &MO = MI->getOperand(0);
1851 // Only take account of global function calls (no closures etc.).
1855 const Function *F = dyn_cast<Function>(MO.getGlobal());
1859 // Do not update 'MaxStack' for primitive and built-in functions
1860 // (encoded with names either starting with "erlang."/"bif_" or not
1861 // having a ".", such as a simple <Module>.<Function>.<Arity>, or an
1862 // "_", such as the BIF "suspend_0") as they are executed on another
1864 if (F->getName().find("erlang.") != StringRef::npos ||
1865 F->getName().find("bif_") != StringRef::npos ||
1866 F->getName().find_first_of("._") == StringRef::npos)
1869 unsigned CalleeStkArity =
1870 F->arg_size() > CCRegisteredArgs ? F->arg_size()-CCRegisteredArgs : 0;
1871 if (HipeLeafWords - 1 > CalleeStkArity)
1872 MoreStackForCalls = std::max(MoreStackForCalls,
1873 (HipeLeafWords - 1 - CalleeStkArity) * SlotSize);
1875 MaxStack += MoreStackForCalls;
1878 // If the stack frame needed is larger than the guaranteed then runtime checks
1879 // and calls to "inc_stack_0" BIF should be inserted in the assembly prologue.
1880 if (MaxStack > Guaranteed) {
1881 MachineBasicBlock &prologueMBB = MF.front();
1882 MachineBasicBlock *stackCheckMBB = MF.CreateMachineBasicBlock();
1883 MachineBasicBlock *incStackMBB = MF.CreateMachineBasicBlock();
1885 for (MachineBasicBlock::livein_iterator I = prologueMBB.livein_begin(),
1886 E = prologueMBB.livein_end(); I != E; I++) {
1887 stackCheckMBB->addLiveIn(*I);
1888 incStackMBB->addLiveIn(*I);
1891 MF.push_front(incStackMBB);
1892 MF.push_front(stackCheckMBB);
1894 unsigned ScratchReg, SPReg, PReg, SPLimitOffset;
1895 unsigned LEAop, CMPop, CALLop;
1899 LEAop = X86::LEA64r;
1900 CMPop = X86::CMP64rm;
1901 CALLop = X86::CALL64pcrel32;
1902 SPLimitOffset = 0x90;
1906 LEAop = X86::LEA32r;
1907 CMPop = X86::CMP32rm;
1908 CALLop = X86::CALLpcrel32;
1909 SPLimitOffset = 0x4c;
1912 ScratchReg = GetScratchRegister(Is64Bit, IsLP64, MF, true);
1913 assert(!MF.getRegInfo().isLiveIn(ScratchReg) &&
1914 "HiPE prologue scratch register is live-in");
1916 // Create new MBB for StackCheck:
1917 addRegOffset(BuildMI(stackCheckMBB, DL, TII.get(LEAop), ScratchReg),
1918 SPReg, false, -MaxStack);
1919 // SPLimitOffset is in a fixed heap location (pointed by BP).
1920 addRegOffset(BuildMI(stackCheckMBB, DL, TII.get(CMPop))
1921 .addReg(ScratchReg), PReg, false, SPLimitOffset);
1922 BuildMI(stackCheckMBB, DL, TII.get(X86::JAE_1)).addMBB(&prologueMBB);
1924 // Create new MBB for IncStack:
1925 BuildMI(incStackMBB, DL, TII.get(CALLop)).
1926 addExternalSymbol("inc_stack_0");
1927 addRegOffset(BuildMI(incStackMBB, DL, TII.get(LEAop), ScratchReg),
1928 SPReg, false, -MaxStack);
1929 addRegOffset(BuildMI(incStackMBB, DL, TII.get(CMPop))
1930 .addReg(ScratchReg), PReg, false, SPLimitOffset);
1931 BuildMI(incStackMBB, DL, TII.get(X86::JLE_1)).addMBB(incStackMBB);
1933 stackCheckMBB->addSuccessor(&prologueMBB, 99);
1934 stackCheckMBB->addSuccessor(incStackMBB, 1);
1935 incStackMBB->addSuccessor(&prologueMBB, 99);
1936 incStackMBB->addSuccessor(incStackMBB, 1);
1943 void X86FrameLowering::
1944 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
1945 MachineBasicBlock::iterator I) const {
1946 const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
1947 const TargetInstrInfo &TII = *STI.getInstrInfo();
1948 const X86RegisterInfo &RegInfo = *STI.getRegisterInfo();
1949 unsigned StackPtr = RegInfo.getStackRegister();
1950 bool reserveCallFrame = hasReservedCallFrame(MF);
1951 int Opcode = I->getOpcode();
1952 bool isDestroy = Opcode == TII.getCallFrameDestroyOpcode();
1953 bool IsLP64 = STI.isTarget64BitLP64();
1954 DebugLoc DL = I->getDebugLoc();
1955 uint64_t Amount = !reserveCallFrame ? I->getOperand(0).getImm() : 0;
1956 uint64_t InternalAmt = (isDestroy || Amount) ? I->getOperand(1).getImm() : 0;
1959 if (!reserveCallFrame) {
1960 // If the stack pointer can be changed after prologue, turn the
1961 // adjcallstackup instruction into a 'sub ESP, <amt>' and the
1962 // adjcallstackdown instruction into 'add ESP, <amt>'
1966 // We need to keep the stack aligned properly. To do this, we round the
1967 // amount of space needed for the outgoing arguments up to the next
1968 // alignment boundary.
1969 unsigned StackAlign = getStackAlignment();
1970 Amount = RoundUpToAlignment(Amount, StackAlign);
1972 MachineInstr *New = nullptr;
1974 // Factor out the amount that gets handled inside the sequence
1975 // (Pushes of argument for frame setup, callee pops for frame destroy)
1976 Amount -= InternalAmt;
1979 if (Opcode == TII.getCallFrameSetupOpcode()) {
1980 New = BuildMI(MF, DL, TII.get(getSUBriOpcode(IsLP64, Amount)), StackPtr)
1981 .addReg(StackPtr).addImm(Amount);
1983 assert(Opcode == TII.getCallFrameDestroyOpcode());
1985 unsigned Opc = getADDriOpcode(IsLP64, Amount);
1986 New = BuildMI(MF, DL, TII.get(Opc), StackPtr)
1987 .addReg(StackPtr).addImm(Amount);
1992 // The EFLAGS implicit def is dead.
1993 New->getOperand(3).setIsDead();
1995 // Replace the pseudo instruction with a new instruction.
2002 if (Opcode == TII.getCallFrameDestroyOpcode() && InternalAmt) {
2003 // If we are performing frame pointer elimination and if the callee pops
2004 // something off the stack pointer, add it back. We do this until we have
2005 // more advanced stack pointer tracking ability.
2006 unsigned Opc = getSUBriOpcode(IsLP64, InternalAmt);
2007 MachineInstr *New = BuildMI(MF, DL, TII.get(Opc), StackPtr)
2008 .addReg(StackPtr).addImm(InternalAmt);
2010 // The EFLAGS implicit def is dead.
2011 New->getOperand(3).setIsDead();
2013 // We are not tracking the stack pointer adjustment by the callee, so make
2014 // sure we restore the stack pointer immediately after the call, there may
2015 // be spill code inserted between the CALL and ADJCALLSTACKUP instructions.
2016 MachineBasicBlock::iterator B = MBB.begin();
2017 while (I != B && !std::prev(I)->isCall())