1 //===-- X86FloatingPoint.cpp - Floating point Reg -> Stack converter ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the pass which converts floating point instructions from
11 // virtual registers into register stack instructions. This pass uses live
12 // variable information to indicate where the FPn registers are used and their
15 // This pass is hampered by the lack of decent CFG manipulation routines for
16 // machine code. In particular, this wants to be able to split critical edges
17 // as necessary, traverse the machine basic block CFG in depth-first order, and
18 // allow there to be multiple machine basic blocks for each LLVM basicblock
19 // (needed for critical edge splitting).
21 // In particular, this pass currently barfs on critical edges. Because of this,
22 // it requires the instruction selector to insert FP_REG_KILL instructions on
23 // the exits of any basic block that has critical edges going from it, or which
24 // branch to a critical basic block.
26 // FIXME: this is not implemented yet. The stackifier pass only works on local
29 //===----------------------------------------------------------------------===//
31 #define DEBUG_TYPE "x86-codegen"
33 #include "X86InstrInfo.h"
34 #include "llvm/CodeGen/MachineFunctionPass.h"
35 #include "llvm/CodeGen/MachineInstrBuilder.h"
36 #include "llvm/CodeGen/MachineRegisterInfo.h"
37 #include "llvm/CodeGen/Passes.h"
38 #include "llvm/Target/TargetInstrInfo.h"
39 #include "llvm/Target/TargetMachine.h"
40 #include "llvm/Support/Debug.h"
41 #include "llvm/Support/Compiler.h"
42 #include "llvm/ADT/DepthFirstIterator.h"
43 #include "llvm/ADT/SmallPtrSet.h"
44 #include "llvm/ADT/SmallVector.h"
45 #include "llvm/ADT/Statistic.h"
46 #include "llvm/ADT/STLExtras.h"
50 STATISTIC(NumFXCH, "Number of fxch instructions inserted");
51 STATISTIC(NumFP , "Number of floating point instructions");
54 struct VISIBILITY_HIDDEN FPS : public MachineFunctionPass {
56 FPS() : MachineFunctionPass(&ID) {}
58 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
60 MachineFunctionPass::getAnalysisUsage(AU);
63 virtual bool runOnMachineFunction(MachineFunction &MF);
65 virtual const char *getPassName() const { return "X86 FP Stackifier"; }
68 const TargetInstrInfo *TII; // Machine instruction info.
69 MachineBasicBlock *MBB; // Current basic block
70 unsigned Stack[8]; // FP<n> Registers in each stack slot...
71 unsigned RegMap[8]; // Track which stack slot contains each register
72 unsigned StackTop; // The current top of the FP stack.
74 void dumpStack() const {
75 cerr << "Stack contents:";
76 for (unsigned i = 0; i != StackTop; ++i) {
77 cerr << " FP" << Stack[i];
78 assert(RegMap[Stack[i]] == i && "Stack[] doesn't match RegMap[]!");
83 /// isStackEmpty - Return true if the FP stack is empty.
84 bool isStackEmpty() const {
88 // getSlot - Return the stack slot number a particular register number is
90 unsigned getSlot(unsigned RegNo) const {
91 assert(RegNo < 8 && "Regno out of range!");
95 // getStackEntry - Return the X86::FP<n> register in register ST(i).
96 unsigned getStackEntry(unsigned STi) const {
97 assert(STi < StackTop && "Access past stack top!");
98 return Stack[StackTop-1-STi];
101 // getSTReg - Return the X86::ST(i) register which contains the specified
102 // FP<RegNo> register.
103 unsigned getSTReg(unsigned RegNo) const {
104 return StackTop - 1 - getSlot(RegNo) + llvm::X86::ST0;
107 // pushReg - Push the specified FP<n> register onto the stack.
108 void pushReg(unsigned Reg) {
109 assert(Reg < 8 && "Register number out of range!");
110 assert(StackTop < 8 && "Stack overflow!");
111 Stack[StackTop] = Reg;
112 RegMap[Reg] = StackTop++;
115 bool isAtTop(unsigned RegNo) const { return getSlot(RegNo) == StackTop-1; }
116 void moveToTop(unsigned RegNo, MachineBasicBlock::iterator I) {
117 if (isAtTop(RegNo)) return;
119 unsigned STReg = getSTReg(RegNo);
120 unsigned RegOnTop = getStackEntry(0);
122 // Swap the slots the regs are in.
123 std::swap(RegMap[RegNo], RegMap[RegOnTop]);
125 // Swap stack slot contents.
126 assert(RegMap[RegOnTop] < StackTop);
127 std::swap(Stack[RegMap[RegOnTop]], Stack[StackTop-1]);
129 // Emit an fxch to update the runtime processors version of the state.
130 BuildMI(*MBB, I, TII->get(X86::XCH_F)).addReg(STReg);
134 void duplicateToTop(unsigned RegNo, unsigned AsReg, MachineInstr *I) {
135 unsigned STReg = getSTReg(RegNo);
136 pushReg(AsReg); // New register on top of stack
138 BuildMI(*MBB, I, TII->get(X86::LD_Frr)).addReg(STReg);
141 // popStackAfter - Pop the current value off of the top of the FP stack
142 // after the specified instruction.
143 void popStackAfter(MachineBasicBlock::iterator &I);
145 // freeStackSlotAfter - Free the specified register from the register stack,
146 // so that it is no longer in a register. If the register is currently at
147 // the top of the stack, we just pop the current instruction, otherwise we
148 // store the current top-of-stack into the specified slot, then pop the top
150 void freeStackSlotAfter(MachineBasicBlock::iterator &I, unsigned Reg);
152 bool processBasicBlock(MachineFunction &MF, MachineBasicBlock &MBB);
154 void handleZeroArgFP(MachineBasicBlock::iterator &I);
155 void handleOneArgFP(MachineBasicBlock::iterator &I);
156 void handleOneArgFPRW(MachineBasicBlock::iterator &I);
157 void handleTwoArgFP(MachineBasicBlock::iterator &I);
158 void handleCompareFP(MachineBasicBlock::iterator &I);
159 void handleCondMovFP(MachineBasicBlock::iterator &I);
160 void handleSpecialFP(MachineBasicBlock::iterator &I);
165 FunctionPass *llvm::createX86FloatingPointStackifierPass() { return new FPS(); }
167 /// getFPReg - Return the X86::FPx register number for the specified operand.
168 /// For example, this returns 3 for X86::FP3.
169 static unsigned getFPReg(const MachineOperand &MO) {
170 assert(MO.isRegister() && "Expected an FP register!");
171 unsigned Reg = MO.getReg();
172 assert(Reg >= X86::FP0 && Reg <= X86::FP6 && "Expected FP register!");
173 return Reg - X86::FP0;
177 /// runOnMachineFunction - Loop over all of the basic blocks, transforming FP
178 /// register references into FP stack references.
180 bool FPS::runOnMachineFunction(MachineFunction &MF) {
181 // We only need to run this pass if there are any FP registers used in this
182 // function. If it is all integer, there is nothing for us to do!
183 bool FPIsUsed = false;
185 assert(X86::FP6 == X86::FP0+6 && "Register enums aren't sorted right!");
186 for (unsigned i = 0; i <= 6; ++i)
187 if (MF.getRegInfo().isPhysRegUsed(X86::FP0+i)) {
193 if (!FPIsUsed) return false;
195 TII = MF.getTarget().getInstrInfo();
198 // Process the function in depth first order so that we process at least one
199 // of the predecessors for every reachable block in the function.
200 SmallPtrSet<MachineBasicBlock*, 8> Processed;
201 MachineBasicBlock *Entry = MF.begin();
203 bool Changed = false;
204 for (df_ext_iterator<MachineBasicBlock*, SmallPtrSet<MachineBasicBlock*, 8> >
205 I = df_ext_begin(Entry, Processed), E = df_ext_end(Entry, Processed);
207 Changed |= processBasicBlock(MF, **I);
212 /// processBasicBlock - Loop over all of the instructions in the basic block,
213 /// transforming FP instructions into their stack form.
215 bool FPS::processBasicBlock(MachineFunction &MF, MachineBasicBlock &BB) {
216 bool Changed = false;
219 for (MachineBasicBlock::iterator I = BB.begin(); I != BB.end(); ++I) {
220 MachineInstr *MI = I;
221 unsigned Flags = MI->getDesc().TSFlags;
223 unsigned FPInstClass = Flags & X86II::FPTypeMask;
224 if (MI->getOpcode() == TargetInstrInfo::INLINEASM)
225 FPInstClass = X86II::SpecialFP;
227 if (FPInstClass == X86II::NotFP)
228 continue; // Efficiently ignore non-fp insts!
230 MachineInstr *PrevMI = 0;
234 ++NumFP; // Keep track of # of pseudo instrs
235 DOUT << "\nFPInst:\t" << *MI;
237 // Get dead variables list now because the MI pointer may be deleted as part
239 SmallVector<unsigned, 8> DeadRegs;
240 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
241 const MachineOperand &MO = MI->getOperand(i);
242 if (MO.isRegister() && MO.isDead())
243 DeadRegs.push_back(MO.getReg());
246 switch (FPInstClass) {
247 case X86II::ZeroArgFP: handleZeroArgFP(I); break;
248 case X86II::OneArgFP: handleOneArgFP(I); break; // fstp ST(0)
249 case X86II::OneArgFPRW: handleOneArgFPRW(I); break; // ST(0) = fsqrt(ST(0))
250 case X86II::TwoArgFP: handleTwoArgFP(I); break;
251 case X86II::CompareFP: handleCompareFP(I); break;
252 case X86II::CondMovFP: handleCondMovFP(I); break;
253 case X86II::SpecialFP: handleSpecialFP(I); break;
254 default: assert(0 && "Unknown FP Type!");
257 // Check to see if any of the values defined by this instruction are dead
258 // after definition. If so, pop them.
259 for (unsigned i = 0, e = DeadRegs.size(); i != e; ++i) {
260 unsigned Reg = DeadRegs[i];
261 if (Reg >= X86::FP0 && Reg <= X86::FP6) {
262 DOUT << "Register FP#" << Reg-X86::FP0 << " is dead!\n";
263 freeStackSlotAfter(I, Reg-X86::FP0);
267 // Print out all of the instructions expanded to if -debug
269 MachineBasicBlock::iterator PrevI(PrevMI);
271 cerr << "Just deleted pseudo instruction\n";
273 MachineBasicBlock::iterator Start = I;
274 // Rewind to first instruction newly inserted.
275 while (Start != BB.begin() && prior(Start) != PrevI) --Start;
276 cerr << "Inserted instructions:\n\t";
277 Start->print(*cerr.stream(), &MF.getTarget());
278 while (++Start != next(I)) {}
286 assert(isStackEmpty() && "Stack not empty at end of basic block?");
290 //===----------------------------------------------------------------------===//
291 // Efficient Lookup Table Support
292 //===----------------------------------------------------------------------===//
298 bool operator<(const TableEntry &TE) const { return from < TE.from; }
299 friend bool operator<(const TableEntry &TE, unsigned V) {
302 friend bool operator<(unsigned V, const TableEntry &TE) {
309 static bool TableIsSorted(const TableEntry *Table, unsigned NumEntries) {
310 for (unsigned i = 0; i != NumEntries-1; ++i)
311 if (!(Table[i] < Table[i+1])) return false;
316 static int Lookup(const TableEntry *Table, unsigned N, unsigned Opcode) {
317 const TableEntry *I = std::lower_bound(Table, Table+N, Opcode);
318 if (I != Table+N && I->from == Opcode)
324 #define ASSERT_SORTED(TABLE)
326 #define ASSERT_SORTED(TABLE) \
327 { static bool TABLE##Checked = false; \
328 if (!TABLE##Checked) { \
329 assert(TableIsSorted(TABLE, array_lengthof(TABLE)) && \
330 "All lookup tables must be sorted for efficient access!"); \
331 TABLE##Checked = true; \
336 //===----------------------------------------------------------------------===//
337 // Register File -> Register Stack Mapping Methods
338 //===----------------------------------------------------------------------===//
340 // OpcodeTable - Sorted map of register instructions to their stack version.
341 // The first element is an register file pseudo instruction, the second is the
342 // concrete X86 instruction which uses the register stack.
344 static const TableEntry OpcodeTable[] = {
345 { X86::ABS_Fp32 , X86::ABS_F },
346 { X86::ABS_Fp64 , X86::ABS_F },
347 { X86::ABS_Fp80 , X86::ABS_F },
348 { X86::ADD_Fp32m , X86::ADD_F32m },
349 { X86::ADD_Fp64m , X86::ADD_F64m },
350 { X86::ADD_Fp64m32 , X86::ADD_F32m },
351 { X86::ADD_Fp80m32 , X86::ADD_F32m },
352 { X86::ADD_Fp80m64 , X86::ADD_F64m },
353 { X86::ADD_FpI16m32 , X86::ADD_FI16m },
354 { X86::ADD_FpI16m64 , X86::ADD_FI16m },
355 { X86::ADD_FpI16m80 , X86::ADD_FI16m },
356 { X86::ADD_FpI32m32 , X86::ADD_FI32m },
357 { X86::ADD_FpI32m64 , X86::ADD_FI32m },
358 { X86::ADD_FpI32m80 , X86::ADD_FI32m },
359 { X86::CHS_Fp32 , X86::CHS_F },
360 { X86::CHS_Fp64 , X86::CHS_F },
361 { X86::CHS_Fp80 , X86::CHS_F },
362 { X86::CMOVBE_Fp32 , X86::CMOVBE_F },
363 { X86::CMOVBE_Fp64 , X86::CMOVBE_F },
364 { X86::CMOVBE_Fp80 , X86::CMOVBE_F },
365 { X86::CMOVB_Fp32 , X86::CMOVB_F },
366 { X86::CMOVB_Fp64 , X86::CMOVB_F },
367 { X86::CMOVB_Fp80 , X86::CMOVB_F },
368 { X86::CMOVE_Fp32 , X86::CMOVE_F },
369 { X86::CMOVE_Fp64 , X86::CMOVE_F },
370 { X86::CMOVE_Fp80 , X86::CMOVE_F },
371 { X86::CMOVNBE_Fp32 , X86::CMOVNBE_F },
372 { X86::CMOVNBE_Fp64 , X86::CMOVNBE_F },
373 { X86::CMOVNBE_Fp80 , X86::CMOVNBE_F },
374 { X86::CMOVNB_Fp32 , X86::CMOVNB_F },
375 { X86::CMOVNB_Fp64 , X86::CMOVNB_F },
376 { X86::CMOVNB_Fp80 , X86::CMOVNB_F },
377 { X86::CMOVNE_Fp32 , X86::CMOVNE_F },
378 { X86::CMOVNE_Fp64 , X86::CMOVNE_F },
379 { X86::CMOVNE_Fp80 , X86::CMOVNE_F },
380 { X86::CMOVNP_Fp32 , X86::CMOVNP_F },
381 { X86::CMOVNP_Fp64 , X86::CMOVNP_F },
382 { X86::CMOVNP_Fp80 , X86::CMOVNP_F },
383 { X86::CMOVP_Fp32 , X86::CMOVP_F },
384 { X86::CMOVP_Fp64 , X86::CMOVP_F },
385 { X86::CMOVP_Fp80 , X86::CMOVP_F },
386 { X86::COS_Fp32 , X86::COS_F },
387 { X86::COS_Fp64 , X86::COS_F },
388 { X86::COS_Fp80 , X86::COS_F },
389 { X86::DIVR_Fp32m , X86::DIVR_F32m },
390 { X86::DIVR_Fp64m , X86::DIVR_F64m },
391 { X86::DIVR_Fp64m32 , X86::DIVR_F32m },
392 { X86::DIVR_Fp80m32 , X86::DIVR_F32m },
393 { X86::DIVR_Fp80m64 , X86::DIVR_F64m },
394 { X86::DIVR_FpI16m32, X86::DIVR_FI16m},
395 { X86::DIVR_FpI16m64, X86::DIVR_FI16m},
396 { X86::DIVR_FpI16m80, X86::DIVR_FI16m},
397 { X86::DIVR_FpI32m32, X86::DIVR_FI32m},
398 { X86::DIVR_FpI32m64, X86::DIVR_FI32m},
399 { X86::DIVR_FpI32m80, X86::DIVR_FI32m},
400 { X86::DIV_Fp32m , X86::DIV_F32m },
401 { X86::DIV_Fp64m , X86::DIV_F64m },
402 { X86::DIV_Fp64m32 , X86::DIV_F32m },
403 { X86::DIV_Fp80m32 , X86::DIV_F32m },
404 { X86::DIV_Fp80m64 , X86::DIV_F64m },
405 { X86::DIV_FpI16m32 , X86::DIV_FI16m },
406 { X86::DIV_FpI16m64 , X86::DIV_FI16m },
407 { X86::DIV_FpI16m80 , X86::DIV_FI16m },
408 { X86::DIV_FpI32m32 , X86::DIV_FI32m },
409 { X86::DIV_FpI32m64 , X86::DIV_FI32m },
410 { X86::DIV_FpI32m80 , X86::DIV_FI32m },
411 { X86::ILD_Fp16m32 , X86::ILD_F16m },
412 { X86::ILD_Fp16m64 , X86::ILD_F16m },
413 { X86::ILD_Fp16m80 , X86::ILD_F16m },
414 { X86::ILD_Fp32m32 , X86::ILD_F32m },
415 { X86::ILD_Fp32m64 , X86::ILD_F32m },
416 { X86::ILD_Fp32m80 , X86::ILD_F32m },
417 { X86::ILD_Fp64m32 , X86::ILD_F64m },
418 { X86::ILD_Fp64m64 , X86::ILD_F64m },
419 { X86::ILD_Fp64m80 , X86::ILD_F64m },
420 { X86::ISTT_Fp16m32 , X86::ISTT_FP16m},
421 { X86::ISTT_Fp16m64 , X86::ISTT_FP16m},
422 { X86::ISTT_Fp16m80 , X86::ISTT_FP16m},
423 { X86::ISTT_Fp32m32 , X86::ISTT_FP32m},
424 { X86::ISTT_Fp32m64 , X86::ISTT_FP32m},
425 { X86::ISTT_Fp32m80 , X86::ISTT_FP32m},
426 { X86::ISTT_Fp64m32 , X86::ISTT_FP64m},
427 { X86::ISTT_Fp64m64 , X86::ISTT_FP64m},
428 { X86::ISTT_Fp64m80 , X86::ISTT_FP64m},
429 { X86::IST_Fp16m32 , X86::IST_F16m },
430 { X86::IST_Fp16m64 , X86::IST_F16m },
431 { X86::IST_Fp16m80 , X86::IST_F16m },
432 { X86::IST_Fp32m32 , X86::IST_F32m },
433 { X86::IST_Fp32m64 , X86::IST_F32m },
434 { X86::IST_Fp32m80 , X86::IST_F32m },
435 { X86::IST_Fp64m32 , X86::IST_FP64m },
436 { X86::IST_Fp64m64 , X86::IST_FP64m },
437 { X86::IST_Fp64m80 , X86::IST_FP64m },
438 { X86::LD_Fp032 , X86::LD_F0 },
439 { X86::LD_Fp064 , X86::LD_F0 },
440 { X86::LD_Fp080 , X86::LD_F0 },
441 { X86::LD_Fp132 , X86::LD_F1 },
442 { X86::LD_Fp164 , X86::LD_F1 },
443 { X86::LD_Fp180 , X86::LD_F1 },
444 { X86::LD_Fp32m , X86::LD_F32m },
445 { X86::LD_Fp32m64 , X86::LD_F32m },
446 { X86::LD_Fp32m80 , X86::LD_F32m },
447 { X86::LD_Fp64m , X86::LD_F64m },
448 { X86::LD_Fp64m80 , X86::LD_F64m },
449 { X86::LD_Fp80m , X86::LD_F80m },
450 { X86::MUL_Fp32m , X86::MUL_F32m },
451 { X86::MUL_Fp64m , X86::MUL_F64m },
452 { X86::MUL_Fp64m32 , X86::MUL_F32m },
453 { X86::MUL_Fp80m32 , X86::MUL_F32m },
454 { X86::MUL_Fp80m64 , X86::MUL_F64m },
455 { X86::MUL_FpI16m32 , X86::MUL_FI16m },
456 { X86::MUL_FpI16m64 , X86::MUL_FI16m },
457 { X86::MUL_FpI16m80 , X86::MUL_FI16m },
458 { X86::MUL_FpI32m32 , X86::MUL_FI32m },
459 { X86::MUL_FpI32m64 , X86::MUL_FI32m },
460 { X86::MUL_FpI32m80 , X86::MUL_FI32m },
461 { X86::SIN_Fp32 , X86::SIN_F },
462 { X86::SIN_Fp64 , X86::SIN_F },
463 { X86::SIN_Fp80 , X86::SIN_F },
464 { X86::SQRT_Fp32 , X86::SQRT_F },
465 { X86::SQRT_Fp64 , X86::SQRT_F },
466 { X86::SQRT_Fp80 , X86::SQRT_F },
467 { X86::ST_Fp32m , X86::ST_F32m },
468 { X86::ST_Fp64m , X86::ST_F64m },
469 { X86::ST_Fp64m32 , X86::ST_F32m },
470 { X86::ST_Fp80m32 , X86::ST_F32m },
471 { X86::ST_Fp80m64 , X86::ST_F64m },
472 { X86::ST_FpP80m , X86::ST_FP80m },
473 { X86::SUBR_Fp32m , X86::SUBR_F32m },
474 { X86::SUBR_Fp64m , X86::SUBR_F64m },
475 { X86::SUBR_Fp64m32 , X86::SUBR_F32m },
476 { X86::SUBR_Fp80m32 , X86::SUBR_F32m },
477 { X86::SUBR_Fp80m64 , X86::SUBR_F64m },
478 { X86::SUBR_FpI16m32, X86::SUBR_FI16m},
479 { X86::SUBR_FpI16m64, X86::SUBR_FI16m},
480 { X86::SUBR_FpI16m80, X86::SUBR_FI16m},
481 { X86::SUBR_FpI32m32, X86::SUBR_FI32m},
482 { X86::SUBR_FpI32m64, X86::SUBR_FI32m},
483 { X86::SUBR_FpI32m80, X86::SUBR_FI32m},
484 { X86::SUB_Fp32m , X86::SUB_F32m },
485 { X86::SUB_Fp64m , X86::SUB_F64m },
486 { X86::SUB_Fp64m32 , X86::SUB_F32m },
487 { X86::SUB_Fp80m32 , X86::SUB_F32m },
488 { X86::SUB_Fp80m64 , X86::SUB_F64m },
489 { X86::SUB_FpI16m32 , X86::SUB_FI16m },
490 { X86::SUB_FpI16m64 , X86::SUB_FI16m },
491 { X86::SUB_FpI16m80 , X86::SUB_FI16m },
492 { X86::SUB_FpI32m32 , X86::SUB_FI32m },
493 { X86::SUB_FpI32m64 , X86::SUB_FI32m },
494 { X86::SUB_FpI32m80 , X86::SUB_FI32m },
495 { X86::TST_Fp32 , X86::TST_F },
496 { X86::TST_Fp64 , X86::TST_F },
497 { X86::TST_Fp80 , X86::TST_F },
498 { X86::UCOM_FpIr32 , X86::UCOM_FIr },
499 { X86::UCOM_FpIr64 , X86::UCOM_FIr },
500 { X86::UCOM_FpIr80 , X86::UCOM_FIr },
501 { X86::UCOM_Fpr32 , X86::UCOM_Fr },
502 { X86::UCOM_Fpr64 , X86::UCOM_Fr },
503 { X86::UCOM_Fpr80 , X86::UCOM_Fr },
506 static unsigned getConcreteOpcode(unsigned Opcode) {
507 ASSERT_SORTED(OpcodeTable);
508 int Opc = Lookup(OpcodeTable, array_lengthof(OpcodeTable), Opcode);
509 assert(Opc != -1 && "FP Stack instruction not in OpcodeTable!");
513 //===----------------------------------------------------------------------===//
515 //===----------------------------------------------------------------------===//
517 // PopTable - Sorted map of instructions to their popping version. The first
518 // element is an instruction, the second is the version which pops.
520 static const TableEntry PopTable[] = {
521 { X86::ADD_FrST0 , X86::ADD_FPrST0 },
523 { X86::DIVR_FrST0, X86::DIVR_FPrST0 },
524 { X86::DIV_FrST0 , X86::DIV_FPrST0 },
526 { X86::IST_F16m , X86::IST_FP16m },
527 { X86::IST_F32m , X86::IST_FP32m },
529 { X86::MUL_FrST0 , X86::MUL_FPrST0 },
531 { X86::ST_F32m , X86::ST_FP32m },
532 { X86::ST_F64m , X86::ST_FP64m },
533 { X86::ST_Frr , X86::ST_FPrr },
535 { X86::SUBR_FrST0, X86::SUBR_FPrST0 },
536 { X86::SUB_FrST0 , X86::SUB_FPrST0 },
538 { X86::UCOM_FIr , X86::UCOM_FIPr },
540 { X86::UCOM_FPr , X86::UCOM_FPPr },
541 { X86::UCOM_Fr , X86::UCOM_FPr },
544 /// popStackAfter - Pop the current value off of the top of the FP stack after
545 /// the specified instruction. This attempts to be sneaky and combine the pop
546 /// into the instruction itself if possible. The iterator is left pointing to
547 /// the last instruction, be it a new pop instruction inserted, or the old
548 /// instruction if it was modified in place.
550 void FPS::popStackAfter(MachineBasicBlock::iterator &I) {
551 ASSERT_SORTED(PopTable);
552 assert(StackTop > 0 && "Cannot pop empty stack!");
553 RegMap[Stack[--StackTop]] = ~0; // Update state
555 // Check to see if there is a popping version of this instruction...
556 int Opcode = Lookup(PopTable, array_lengthof(PopTable), I->getOpcode());
558 I->setDesc(TII->get(Opcode));
559 if (Opcode == X86::UCOM_FPPr)
561 } else { // Insert an explicit pop
562 I = BuildMI(*MBB, ++I, TII->get(X86::ST_FPrr)).addReg(X86::ST0);
566 /// freeStackSlotAfter - Free the specified register from the register stack, so
567 /// that it is no longer in a register. If the register is currently at the top
568 /// of the stack, we just pop the current instruction, otherwise we store the
569 /// current top-of-stack into the specified slot, then pop the top of stack.
570 void FPS::freeStackSlotAfter(MachineBasicBlock::iterator &I, unsigned FPRegNo) {
571 if (getStackEntry(0) == FPRegNo) { // already at the top of stack? easy.
576 // Otherwise, store the top of stack into the dead slot, killing the operand
577 // without having to add in an explicit xchg then pop.
579 unsigned STReg = getSTReg(FPRegNo);
580 unsigned OldSlot = getSlot(FPRegNo);
581 unsigned TopReg = Stack[StackTop-1];
582 Stack[OldSlot] = TopReg;
583 RegMap[TopReg] = OldSlot;
584 RegMap[FPRegNo] = ~0;
585 Stack[--StackTop] = ~0;
586 I = BuildMI(*MBB, ++I, TII->get(X86::ST_FPrr)).addReg(STReg);
590 //===----------------------------------------------------------------------===//
591 // Instruction transformation implementation
592 //===----------------------------------------------------------------------===//
594 /// handleZeroArgFP - ST(0) = fld0 ST(0) = flds <mem>
596 void FPS::handleZeroArgFP(MachineBasicBlock::iterator &I) {
597 MachineInstr *MI = I;
598 unsigned DestReg = getFPReg(MI->getOperand(0));
600 // Change from the pseudo instruction to the concrete instruction.
601 MI->RemoveOperand(0); // Remove the explicit ST(0) operand
602 MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode())));
604 // Result gets pushed on the stack.
608 /// handleOneArgFP - fst <mem>, ST(0)
610 void FPS::handleOneArgFP(MachineBasicBlock::iterator &I) {
611 MachineInstr *MI = I;
612 unsigned NumOps = MI->getDesc().getNumOperands();
613 assert((NumOps == 5 || NumOps == 1) &&
614 "Can only handle fst* & ftst instructions!");
616 // Is this the last use of the source register?
617 unsigned Reg = getFPReg(MI->getOperand(NumOps-1));
618 bool KillsSrc = MI->killsRegister(X86::FP0+Reg);
620 // FISTP64m is strange because there isn't a non-popping versions.
621 // If we have one _and_ we don't want to pop the operand, duplicate the value
622 // on the stack instead of moving it. This ensure that popping the value is
624 // Ditto FISTTP16m, FISTTP32m, FISTTP64m, ST_FpP80m.
627 (MI->getOpcode() == X86::IST_Fp64m32 ||
628 MI->getOpcode() == X86::ISTT_Fp16m32 ||
629 MI->getOpcode() == X86::ISTT_Fp32m32 ||
630 MI->getOpcode() == X86::ISTT_Fp64m32 ||
631 MI->getOpcode() == X86::IST_Fp64m64 ||
632 MI->getOpcode() == X86::ISTT_Fp16m64 ||
633 MI->getOpcode() == X86::ISTT_Fp32m64 ||
634 MI->getOpcode() == X86::ISTT_Fp64m64 ||
635 MI->getOpcode() == X86::IST_Fp64m80 ||
636 MI->getOpcode() == X86::ISTT_Fp16m80 ||
637 MI->getOpcode() == X86::ISTT_Fp32m80 ||
638 MI->getOpcode() == X86::ISTT_Fp64m80 ||
639 MI->getOpcode() == X86::ST_FpP80m)) {
640 duplicateToTop(Reg, 7 /*temp register*/, I);
642 moveToTop(Reg, I); // Move to the top of the stack...
645 // Convert from the pseudo instruction to the concrete instruction.
646 MI->RemoveOperand(NumOps-1); // Remove explicit ST(0) operand
647 MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode())));
649 if (MI->getOpcode() == X86::IST_FP64m ||
650 MI->getOpcode() == X86::ISTT_FP16m ||
651 MI->getOpcode() == X86::ISTT_FP32m ||
652 MI->getOpcode() == X86::ISTT_FP64m ||
653 MI->getOpcode() == X86::ST_FP80m) {
654 assert(StackTop > 0 && "Stack empty??");
656 } else if (KillsSrc) { // Last use of operand?
662 /// handleOneArgFPRW: Handle instructions that read from the top of stack and
663 /// replace the value with a newly computed value. These instructions may have
664 /// non-fp operands after their FP operands.
668 /// R1 = fadd R2, [mem]
670 void FPS::handleOneArgFPRW(MachineBasicBlock::iterator &I) {
671 MachineInstr *MI = I;
673 unsigned NumOps = MI->getDesc().getNumOperands();
674 assert(NumOps >= 2 && "FPRW instructions must have 2 ops!!");
677 // Is this the last use of the source register?
678 unsigned Reg = getFPReg(MI->getOperand(1));
679 bool KillsSrc = MI->killsRegister(X86::FP0+Reg);
682 // If this is the last use of the source register, just make sure it's on
683 // the top of the stack.
685 assert(StackTop > 0 && "Stack cannot be empty!");
687 pushReg(getFPReg(MI->getOperand(0)));
689 // If this is not the last use of the source register, _copy_ it to the top
691 duplicateToTop(Reg, getFPReg(MI->getOperand(0)), I);
694 // Change from the pseudo instruction to the concrete instruction.
695 MI->RemoveOperand(1); // Drop the source operand.
696 MI->RemoveOperand(0); // Drop the destination operand.
697 MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode())));
701 //===----------------------------------------------------------------------===//
702 // Define tables of various ways to map pseudo instructions
705 // ForwardST0Table - Map: A = B op C into: ST(0) = ST(0) op ST(i)
706 static const TableEntry ForwardST0Table[] = {
707 { X86::ADD_Fp32 , X86::ADD_FST0r },
708 { X86::ADD_Fp64 , X86::ADD_FST0r },
709 { X86::ADD_Fp80 , X86::ADD_FST0r },
710 { X86::DIV_Fp32 , X86::DIV_FST0r },
711 { X86::DIV_Fp64 , X86::DIV_FST0r },
712 { X86::DIV_Fp80 , X86::DIV_FST0r },
713 { X86::MUL_Fp32 , X86::MUL_FST0r },
714 { X86::MUL_Fp64 , X86::MUL_FST0r },
715 { X86::MUL_Fp80 , X86::MUL_FST0r },
716 { X86::SUB_Fp32 , X86::SUB_FST0r },
717 { X86::SUB_Fp64 , X86::SUB_FST0r },
718 { X86::SUB_Fp80 , X86::SUB_FST0r },
721 // ReverseST0Table - Map: A = B op C into: ST(0) = ST(i) op ST(0)
722 static const TableEntry ReverseST0Table[] = {
723 { X86::ADD_Fp32 , X86::ADD_FST0r }, // commutative
724 { X86::ADD_Fp64 , X86::ADD_FST0r }, // commutative
725 { X86::ADD_Fp80 , X86::ADD_FST0r }, // commutative
726 { X86::DIV_Fp32 , X86::DIVR_FST0r },
727 { X86::DIV_Fp64 , X86::DIVR_FST0r },
728 { X86::DIV_Fp80 , X86::DIVR_FST0r },
729 { X86::MUL_Fp32 , X86::MUL_FST0r }, // commutative
730 { X86::MUL_Fp64 , X86::MUL_FST0r }, // commutative
731 { X86::MUL_Fp80 , X86::MUL_FST0r }, // commutative
732 { X86::SUB_Fp32 , X86::SUBR_FST0r },
733 { X86::SUB_Fp64 , X86::SUBR_FST0r },
734 { X86::SUB_Fp80 , X86::SUBR_FST0r },
737 // ForwardSTiTable - Map: A = B op C into: ST(i) = ST(0) op ST(i)
738 static const TableEntry ForwardSTiTable[] = {
739 { X86::ADD_Fp32 , X86::ADD_FrST0 }, // commutative
740 { X86::ADD_Fp64 , X86::ADD_FrST0 }, // commutative
741 { X86::ADD_Fp80 , X86::ADD_FrST0 }, // commutative
742 { X86::DIV_Fp32 , X86::DIVR_FrST0 },
743 { X86::DIV_Fp64 , X86::DIVR_FrST0 },
744 { X86::DIV_Fp80 , X86::DIVR_FrST0 },
745 { X86::MUL_Fp32 , X86::MUL_FrST0 }, // commutative
746 { X86::MUL_Fp64 , X86::MUL_FrST0 }, // commutative
747 { X86::MUL_Fp80 , X86::MUL_FrST0 }, // commutative
748 { X86::SUB_Fp32 , X86::SUBR_FrST0 },
749 { X86::SUB_Fp64 , X86::SUBR_FrST0 },
750 { X86::SUB_Fp80 , X86::SUBR_FrST0 },
753 // ReverseSTiTable - Map: A = B op C into: ST(i) = ST(i) op ST(0)
754 static const TableEntry ReverseSTiTable[] = {
755 { X86::ADD_Fp32 , X86::ADD_FrST0 },
756 { X86::ADD_Fp64 , X86::ADD_FrST0 },
757 { X86::ADD_Fp80 , X86::ADD_FrST0 },
758 { X86::DIV_Fp32 , X86::DIV_FrST0 },
759 { X86::DIV_Fp64 , X86::DIV_FrST0 },
760 { X86::DIV_Fp80 , X86::DIV_FrST0 },
761 { X86::MUL_Fp32 , X86::MUL_FrST0 },
762 { X86::MUL_Fp64 , X86::MUL_FrST0 },
763 { X86::MUL_Fp80 , X86::MUL_FrST0 },
764 { X86::SUB_Fp32 , X86::SUB_FrST0 },
765 { X86::SUB_Fp64 , X86::SUB_FrST0 },
766 { X86::SUB_Fp80 , X86::SUB_FrST0 },
770 /// handleTwoArgFP - Handle instructions like FADD and friends which are virtual
771 /// instructions which need to be simplified and possibly transformed.
773 /// Result: ST(0) = fsub ST(0), ST(i)
774 /// ST(i) = fsub ST(0), ST(i)
775 /// ST(0) = fsubr ST(0), ST(i)
776 /// ST(i) = fsubr ST(0), ST(i)
778 void FPS::handleTwoArgFP(MachineBasicBlock::iterator &I) {
779 ASSERT_SORTED(ForwardST0Table); ASSERT_SORTED(ReverseST0Table);
780 ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable);
781 MachineInstr *MI = I;
783 unsigned NumOperands = MI->getDesc().getNumOperands();
784 assert(NumOperands == 3 && "Illegal TwoArgFP instruction!");
785 unsigned Dest = getFPReg(MI->getOperand(0));
786 unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2));
787 unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1));
788 bool KillsOp0 = MI->killsRegister(X86::FP0+Op0);
789 bool KillsOp1 = MI->killsRegister(X86::FP0+Op1);
791 unsigned TOS = getStackEntry(0);
793 // One of our operands must be on the top of the stack. If neither is yet, we
795 if (Op0 != TOS && Op1 != TOS) { // No operand at TOS?
796 // We can choose to move either operand to the top of the stack. If one of
797 // the operands is killed by this instruction, we want that one so that we
798 // can update right on top of the old version.
800 moveToTop(Op0, I); // Move dead operand to TOS.
802 } else if (KillsOp1) {
806 // All of the operands are live after this instruction executes, so we
807 // cannot update on top of any operand. Because of this, we must
808 // duplicate one of the stack elements to the top. It doesn't matter
809 // which one we pick.
811 duplicateToTop(Op0, Dest, I);
815 } else if (!KillsOp0 && !KillsOp1) {
816 // If we DO have one of our operands at the top of the stack, but we don't
817 // have a dead operand, we must duplicate one of the operands to a new slot
819 duplicateToTop(Op0, Dest, I);
824 // Now we know that one of our operands is on the top of the stack, and at
825 // least one of our operands is killed by this instruction.
826 assert((TOS == Op0 || TOS == Op1) && (KillsOp0 || KillsOp1) &&
827 "Stack conditions not set up right!");
829 // We decide which form to use based on what is on the top of the stack, and
830 // which operand is killed by this instruction.
831 const TableEntry *InstTable;
832 bool isForward = TOS == Op0;
833 bool updateST0 = (TOS == Op0 && !KillsOp1) || (TOS == Op1 && !KillsOp0);
836 InstTable = ForwardST0Table;
838 InstTable = ReverseST0Table;
841 InstTable = ForwardSTiTable;
843 InstTable = ReverseSTiTable;
846 int Opcode = Lookup(InstTable, array_lengthof(ForwardST0Table),
848 assert(Opcode != -1 && "Unknown TwoArgFP pseudo instruction!");
850 // NotTOS - The register which is not on the top of stack...
851 unsigned NotTOS = (TOS == Op0) ? Op1 : Op0;
853 // Replace the old instruction with a new instruction
855 I = BuildMI(*MBB, I, TII->get(Opcode)).addReg(getSTReg(NotTOS));
857 // If both operands are killed, pop one off of the stack in addition to
858 // overwriting the other one.
859 if (KillsOp0 && KillsOp1 && Op0 != Op1) {
860 assert(!updateST0 && "Should have updated other operand!");
861 popStackAfter(I); // Pop the top of stack
864 // Update stack information so that we know the destination register is now on
866 unsigned UpdatedSlot = getSlot(updateST0 ? TOS : NotTOS);
867 assert(UpdatedSlot < StackTop && Dest < 7);
868 Stack[UpdatedSlot] = Dest;
869 RegMap[Dest] = UpdatedSlot;
870 MBB->getParent()->DeleteMachineInstr(MI); // Remove the old instruction
873 /// handleCompareFP - Handle FUCOM and FUCOMI instructions, which have two FP
874 /// register arguments and no explicit destinations.
876 void FPS::handleCompareFP(MachineBasicBlock::iterator &I) {
877 ASSERT_SORTED(ForwardST0Table); ASSERT_SORTED(ReverseST0Table);
878 ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable);
879 MachineInstr *MI = I;
881 unsigned NumOperands = MI->getDesc().getNumOperands();
882 assert(NumOperands == 2 && "Illegal FUCOM* instruction!");
883 unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2));
884 unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1));
885 bool KillsOp0 = MI->killsRegister(X86::FP0+Op0);
886 bool KillsOp1 = MI->killsRegister(X86::FP0+Op1);
888 // Make sure the first operand is on the top of stack, the other one can be
892 // Change from the pseudo instruction to the concrete instruction.
893 MI->getOperand(0).setReg(getSTReg(Op1));
894 MI->RemoveOperand(1);
895 MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode())));
897 // If any of the operands are killed by this instruction, free them.
898 if (KillsOp0) freeStackSlotAfter(I, Op0);
899 if (KillsOp1 && Op0 != Op1) freeStackSlotAfter(I, Op1);
902 /// handleCondMovFP - Handle two address conditional move instructions. These
903 /// instructions move a st(i) register to st(0) iff a condition is true. These
904 /// instructions require that the first operand is at the top of the stack, but
905 /// otherwise don't modify the stack at all.
906 void FPS::handleCondMovFP(MachineBasicBlock::iterator &I) {
907 MachineInstr *MI = I;
909 unsigned Op0 = getFPReg(MI->getOperand(0));
910 unsigned Op1 = getFPReg(MI->getOperand(2));
911 bool KillsOp1 = MI->killsRegister(X86::FP0+Op1);
913 // The first operand *must* be on the top of the stack.
916 // Change the second operand to the stack register that the operand is in.
917 // Change from the pseudo instruction to the concrete instruction.
918 MI->RemoveOperand(0);
919 MI->RemoveOperand(1);
920 MI->getOperand(0).setReg(getSTReg(Op1));
921 MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode())));
923 // If we kill the second operand, make sure to pop it from the stack.
924 if (Op0 != Op1 && KillsOp1) {
925 // Get this value off of the register stack.
926 freeStackSlotAfter(I, Op1);
931 /// handleSpecialFP - Handle special instructions which behave unlike other
932 /// floating point instructions. This is primarily intended for use by pseudo
935 void FPS::handleSpecialFP(MachineBasicBlock::iterator &I) {
936 MachineInstr *MI = I;
937 switch (MI->getOpcode()) {
938 default: assert(0 && "Unknown SpecialFP instruction!");
939 case X86::FpGET_ST0_32:// Appears immediately after a call returning FP type!
940 case X86::FpGET_ST0_64:// Appears immediately after a call returning FP type!
941 case X86::FpGET_ST0_80:// Appears immediately after a call returning FP type!
942 assert(StackTop == 0 && "Stack should be empty after a call!");
943 pushReg(getFPReg(MI->getOperand(0)));
945 case X86::FpGET_ST1_32:// Appears immediately after a call returning FP type!
946 case X86::FpGET_ST1_64:// Appears immediately after a call returning FP type!
947 case X86::FpGET_ST1_80:{// Appears immediately after a call returning FP type!
948 // FpGET_ST1 should occur right after a FpGET_ST0 for a call or inline asm.
949 // The pattern we expect is:
954 // At this point, we've pushed FP1 on the top of stack, so it should be
955 // present if it isn't dead. If it was dead, we already emitted a pop to
956 // remove it from the stack and StackTop = 0.
958 // Push FP4 as top of stack next.
959 pushReg(getFPReg(MI->getOperand(0)));
961 // If StackTop was 0 before we pushed our operand, then ST(0) must have been
962 // dead. In this case, the ST(1) value is the only thing that is live, so
963 // it should be on the TOS (after the pop that was emitted) and is. Just
964 // continue in this case.
968 // Because pushReg just pushed ST(1) as TOS, we now have to swap the two top
969 // elements so that our accounting is correct.
970 unsigned RegOnTop = getStackEntry(0);
971 unsigned RegNo = getStackEntry(1);
973 // Swap the slots the regs are in.
974 std::swap(RegMap[RegNo], RegMap[RegOnTop]);
976 // Swap stack slot contents.
977 assert(RegMap[RegOnTop] < StackTop);
978 std::swap(Stack[RegMap[RegOnTop]], Stack[StackTop-1]);
981 case X86::FpSET_ST0_32:
982 case X86::FpSET_ST0_64:
983 case X86::FpSET_ST0_80:
984 assert(StackTop == 1 && "Stack should have one element on it to return!");
985 --StackTop; // "Forget" we have something on the top of stack!
987 case X86::MOV_Fp3232:
988 case X86::MOV_Fp3264:
989 case X86::MOV_Fp6432:
990 case X86::MOV_Fp6464:
991 case X86::MOV_Fp3280:
992 case X86::MOV_Fp6480:
993 case X86::MOV_Fp8032:
994 case X86::MOV_Fp8064:
995 case X86::MOV_Fp8080: {
996 unsigned SrcReg = getFPReg(MI->getOperand(1));
997 unsigned DestReg = getFPReg(MI->getOperand(0));
999 if (MI->killsRegister(X86::FP0+SrcReg)) {
1000 // If the input operand is killed, we can just change the owner of the
1001 // incoming stack slot into the result.
1002 unsigned Slot = getSlot(SrcReg);
1003 assert(Slot < 7 && DestReg < 7 && "FpMOV operands invalid!");
1004 Stack[Slot] = DestReg;
1005 RegMap[DestReg] = Slot;
1008 // For FMOV we just duplicate the specified value to a new stack slot.
1009 // This could be made better, but would require substantial changes.
1010 duplicateToTop(SrcReg, DestReg, I);
1014 case TargetInstrInfo::INLINEASM: {
1015 // The inline asm MachineInstr currently only *uses* FP registers for the
1016 // 'f' constraint. These should be turned into the current ST(x) register
1017 // in the machine instr. Also, any kills should be explicitly popped after
1020 unsigned NumKills = 0;
1021 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1022 MachineOperand &Op = MI->getOperand(i);
1023 if (!Op.isRegister() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
1025 assert(Op.isUse() && "Only handle inline asm uses right now");
1027 unsigned FPReg = getFPReg(Op);
1028 Op.setReg(getSTReg(FPReg));
1030 // If we kill this operand, make sure to pop it from the stack after the
1031 // asm. We just remember it for now, and pop them all off at the end in
1034 Kills[NumKills++] = FPReg;
1037 // If this asm kills any FP registers (is the last use of them) we must
1038 // explicitly emit pop instructions for them. Do this now after the asm has
1039 // executed so that the ST(x) numbers are not off (which would happen if we
1040 // did this inline with operand rewriting).
1042 // Note: this might be a non-optimal pop sequence. We might be able to do
1043 // better by trying to pop in stack order or something.
1044 MachineBasicBlock::iterator InsertPt = MI;
1046 freeStackSlotAfter(InsertPt, Kills[--NumKills]);
1048 // Don't delete the inline asm!
1054 // If RET has an FP register use operand, pass the first one in ST(0) and
1055 // the second one in ST(1).
1056 if (isStackEmpty()) return; // Quick check to see if any are possible.
1058 // Find the register operands.
1059 unsigned FirstFPRegOp = ~0U, SecondFPRegOp = ~0U;
1061 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1062 MachineOperand &Op = MI->getOperand(i);
1063 if (!Op.isRegister() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
1065 // FP Register uses must be kills unless there are two uses of the same
1066 // register, in which case only one will be a kill.
1067 assert(Op.isUse() &&
1068 (Op.isKill() || // Marked kill.
1069 getFPReg(Op) == FirstFPRegOp || // Second instance.
1070 MI->killsRegister(Op.getReg())) && // Later use is marked kill.
1071 "Ret only defs operands, and values aren't live beyond it");
1073 if (FirstFPRegOp == ~0U)
1074 FirstFPRegOp = getFPReg(Op);
1076 assert(SecondFPRegOp == ~0U && "More than two fp operands!");
1077 SecondFPRegOp = getFPReg(Op);
1080 // Remove the operand so that later passes don't see it.
1081 MI->RemoveOperand(i);
1085 // There are only four possibilities here:
1086 // 1) we are returning a single FP value. In this case, it has to be in
1087 // ST(0) already, so just declare success by removing the value from the
1089 if (SecondFPRegOp == ~0U) {
1090 // Assert that the top of stack contains the right FP register.
1091 assert(StackTop == 1 && FirstFPRegOp == getStackEntry(0) &&
1092 "Top of stack not the right register for RET!");
1094 // Ok, everything is good, mark the value as not being on the stack
1095 // anymore so that our assertion about the stack being empty at end of
1096 // block doesn't fire.
1101 // Otherwise, we are returning two values:
1102 // 2) If returning the same value for both, we only have one thing in the FP
1103 // stack. Consider: RET FP1, FP1
1104 if (StackTop == 1) {
1105 assert(FirstFPRegOp == SecondFPRegOp && FirstFPRegOp == getStackEntry(0)&&
1106 "Stack misconfiguration for RET!");
1108 // Duplicate the TOS so that we return it twice. Just pick some other FPx
1109 // register to hold it.
1110 unsigned NewReg = (FirstFPRegOp+1)%7;
1111 duplicateToTop(FirstFPRegOp, NewReg, MI);
1112 FirstFPRegOp = NewReg;
1115 /// Okay we know we have two different FPx operands now:
1116 assert(StackTop == 2 && "Must have two values live!");
1118 /// 3) If SecondFPRegOp is currently in ST(0) and FirstFPRegOp is currently
1119 /// in ST(1). In this case, emit an fxch.
1120 if (getStackEntry(0) == SecondFPRegOp) {
1121 assert(getStackEntry(1) == FirstFPRegOp && "Unknown regs live");
1122 moveToTop(FirstFPRegOp, MI);
1125 /// 4) Finally, FirstFPRegOp must be in ST(0) and SecondFPRegOp must be in
1126 /// ST(1). Just remove both from our understanding of the stack and return.
1127 assert(getStackEntry(0) == FirstFPRegOp && "Unknown regs live");
1128 assert(getStackEntry(1) == SecondFPRegOp && "Unknown regs live");
1133 I = MBB->erase(I); // Remove the pseudo instruction