1 //===-- X86FloatingPoint.cpp - Floating point Reg -> Stack converter ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the pass which converts floating point instructions from
11 // virtual registers into register stack instructions. This pass uses live
12 // variable information to indicate where the FPn registers are used and their
15 // This pass is hampered by the lack of decent CFG manipulation routines for
16 // machine code. In particular, this wants to be able to split critical edges
17 // as necessary, traverse the machine basic block CFG in depth-first order, and
18 // allow there to be multiple machine basic blocks for each LLVM basicblock
19 // (needed for critical edge splitting).
21 // In particular, this pass currently barfs on critical edges. Because of this,
22 // it requires the instruction selector to insert FP_REG_KILL instructions on
23 // the exits of any basic block that has critical edges going from it, or which
24 // branch to a critical basic block.
26 // FIXME: this is not implemented yet. The stackifier pass only works on local
29 //===----------------------------------------------------------------------===//
31 #define DEBUG_TYPE "x86-codegen"
33 #include "X86InstrInfo.h"
34 #include "llvm/CodeGen/MachineFunctionPass.h"
35 #include "llvm/CodeGen/MachineInstrBuilder.h"
36 #include "llvm/CodeGen/MachineRegisterInfo.h"
37 #include "llvm/CodeGen/Passes.h"
38 #include "llvm/Target/TargetInstrInfo.h"
39 #include "llvm/Target/TargetMachine.h"
40 #include "llvm/Support/Debug.h"
41 #include "llvm/Support/Compiler.h"
42 #include "llvm/ADT/DepthFirstIterator.h"
43 #include "llvm/ADT/SmallVector.h"
44 #include "llvm/ADT/Statistic.h"
45 #include "llvm/ADT/STLExtras.h"
50 STATISTIC(NumFXCH, "Number of fxch instructions inserted");
51 STATISTIC(NumFP , "Number of floating point instructions");
54 struct VISIBILITY_HIDDEN FPS : public MachineFunctionPass {
56 FPS() : MachineFunctionPass((intptr_t)&ID) {}
58 virtual bool runOnMachineFunction(MachineFunction &MF);
60 virtual const char *getPassName() const { return "X86 FP Stackifier"; }
63 const TargetInstrInfo *TII; // Machine instruction info.
64 MachineBasicBlock *MBB; // Current basic block
65 unsigned Stack[8]; // FP<n> Registers in each stack slot...
66 unsigned RegMap[8]; // Track which stack slot contains each register
67 unsigned StackTop; // The current top of the FP stack.
69 void dumpStack() const {
70 cerr << "Stack contents:";
71 for (unsigned i = 0; i != StackTop; ++i) {
72 cerr << " FP" << Stack[i];
73 assert(RegMap[Stack[i]] == i && "Stack[] doesn't match RegMap[]!");
78 // getSlot - Return the stack slot number a particular register number is
80 unsigned getSlot(unsigned RegNo) const {
81 assert(RegNo < 8 && "Regno out of range!");
85 // getStackEntry - Return the X86::FP<n> register in register ST(i)
86 unsigned getStackEntry(unsigned STi) const {
87 assert(STi < StackTop && "Access past stack top!");
88 return Stack[StackTop-1-STi];
91 // getSTReg - Return the X86::ST(i) register which contains the specified
93 unsigned getSTReg(unsigned RegNo) const {
94 return StackTop - 1 - getSlot(RegNo) + llvm::X86::ST0;
97 // pushReg - Push the specified FP<n> register onto the stack
98 void pushReg(unsigned Reg) {
99 assert(Reg < 8 && "Register number out of range!");
100 assert(StackTop < 8 && "Stack overflow!");
101 Stack[StackTop] = Reg;
102 RegMap[Reg] = StackTop++;
105 bool isAtTop(unsigned RegNo) const { return getSlot(RegNo) == StackTop-1; }
106 void moveToTop(unsigned RegNo, MachineBasicBlock::iterator &I) {
107 if (!isAtTop(RegNo)) {
108 unsigned STReg = getSTReg(RegNo);
109 unsigned RegOnTop = getStackEntry(0);
111 // Swap the slots the regs are in
112 std::swap(RegMap[RegNo], RegMap[RegOnTop]);
114 // Swap stack slot contents
115 assert(RegMap[RegOnTop] < StackTop);
116 std::swap(Stack[RegMap[RegOnTop]], Stack[StackTop-1]);
118 // Emit an fxch to update the runtime processors version of the state
119 BuildMI(*MBB, I, TII->get(X86::XCH_F)).addReg(STReg);
124 void duplicateToTop(unsigned RegNo, unsigned AsReg, MachineInstr *I) {
125 unsigned STReg = getSTReg(RegNo);
126 pushReg(AsReg); // New register on top of stack
128 BuildMI(*MBB, I, TII->get(X86::LD_Frr)).addReg(STReg);
131 // popStackAfter - Pop the current value off of the top of the FP stack
132 // after the specified instruction.
133 void popStackAfter(MachineBasicBlock::iterator &I);
135 // freeStackSlotAfter - Free the specified register from the register stack,
136 // so that it is no longer in a register. If the register is currently at
137 // the top of the stack, we just pop the current instruction, otherwise we
138 // store the current top-of-stack into the specified slot, then pop the top
140 void freeStackSlotAfter(MachineBasicBlock::iterator &I, unsigned Reg);
142 bool processBasicBlock(MachineFunction &MF, MachineBasicBlock &MBB);
144 void handleZeroArgFP(MachineBasicBlock::iterator &I);
145 void handleOneArgFP(MachineBasicBlock::iterator &I);
146 void handleOneArgFPRW(MachineBasicBlock::iterator &I);
147 void handleTwoArgFP(MachineBasicBlock::iterator &I);
148 void handleCompareFP(MachineBasicBlock::iterator &I);
149 void handleCondMovFP(MachineBasicBlock::iterator &I);
150 void handleSpecialFP(MachineBasicBlock::iterator &I);
155 FunctionPass *llvm::createX86FloatingPointStackifierPass() { return new FPS(); }
157 /// KillsRegister - Return true if the specified instruction kills (is the last
158 /// use of) the specified register. Note that this routine does not check for
159 /// kills of subregisters.
160 static bool KillsRegister(MachineInstr *MI, unsigned Reg) {
161 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
162 MachineOperand &MO = MI->getOperand(i);
163 if (MO.isRegister() && MO.isKill() && MO.getReg() == Reg)
169 /// getFPReg - Return the X86::FPx register number for the specified operand.
170 /// For example, this returns 3 for X86::FP3.
171 static unsigned getFPReg(const MachineOperand &MO) {
172 assert(MO.isRegister() && "Expected an FP register!");
173 unsigned Reg = MO.getReg();
174 assert(Reg >= X86::FP0 && Reg <= X86::FP6 && "Expected FP register!");
175 return Reg - X86::FP0;
179 /// runOnMachineFunction - Loop over all of the basic blocks, transforming FP
180 /// register references into FP stack references.
182 bool FPS::runOnMachineFunction(MachineFunction &MF) {
183 // We only need to run this pass if there are any FP registers used in this
184 // function. If it is all integer, there is nothing for us to do!
185 bool FPIsUsed = false;
187 assert(X86::FP6 == X86::FP0+6 && "Register enums aren't sorted right!");
188 for (unsigned i = 0; i <= 6; ++i)
189 if (MF.getRegInfo().isPhysRegUsed(X86::FP0+i)) {
195 if (!FPIsUsed) return false;
197 TII = MF.getTarget().getInstrInfo();
200 // Process the function in depth first order so that we process at least one
201 // of the predecessors for every reachable block in the function.
202 std::set<MachineBasicBlock*> Processed;
203 MachineBasicBlock *Entry = MF.begin();
205 bool Changed = false;
206 for (df_ext_iterator<MachineBasicBlock*, std::set<MachineBasicBlock*> >
207 I = df_ext_begin(Entry, Processed), E = df_ext_end(Entry, Processed);
209 Changed |= processBasicBlock(MF, **I);
214 /// processBasicBlock - Loop over all of the instructions in the basic block,
215 /// transforming FP instructions into their stack form.
217 bool FPS::processBasicBlock(MachineFunction &MF, MachineBasicBlock &BB) {
218 bool Changed = false;
221 for (MachineBasicBlock::iterator I = BB.begin(); I != BB.end(); ++I) {
222 MachineInstr *MI = I;
223 unsigned Flags = MI->getDesc().TSFlags;
224 if ((Flags & X86II::FPTypeMask) == X86II::NotFP)
225 continue; // Efficiently ignore non-fp insts!
227 MachineInstr *PrevMI = 0;
231 ++NumFP; // Keep track of # of pseudo instrs
232 DOUT << "\nFPInst:\t" << *MI;
234 // Get dead variables list now because the MI pointer may be deleted as part
236 SmallVector<unsigned, 8> DeadRegs;
237 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
238 const MachineOperand &MO = MI->getOperand(i);
239 if (MO.isRegister() && MO.isDead())
240 DeadRegs.push_back(MO.getReg());
243 switch (Flags & X86II::FPTypeMask) {
244 case X86II::ZeroArgFP: handleZeroArgFP(I); break;
245 case X86II::OneArgFP: handleOneArgFP(I); break; // fstp ST(0)
246 case X86II::OneArgFPRW: handleOneArgFPRW(I); break; // ST(0) = fsqrt(ST(0))
247 case X86II::TwoArgFP: handleTwoArgFP(I); break;
248 case X86II::CompareFP: handleCompareFP(I); break;
249 case X86II::CondMovFP: handleCondMovFP(I); break;
250 case X86II::SpecialFP: handleSpecialFP(I); break;
251 default: assert(0 && "Unknown FP Type!");
254 // Check to see if any of the values defined by this instruction are dead
255 // after definition. If so, pop them.
256 for (unsigned i = 0, e = DeadRegs.size(); i != e; ++i) {
257 unsigned Reg = DeadRegs[i];
258 if (Reg >= X86::FP0 && Reg <= X86::FP6) {
259 DOUT << "Register FP#" << Reg-X86::FP0 << " is dead!\n";
260 freeStackSlotAfter(I, Reg-X86::FP0);
264 // Print out all of the instructions expanded to if -debug
266 MachineBasicBlock::iterator PrevI(PrevMI);
268 cerr << "Just deleted pseudo instruction\n";
270 MachineBasicBlock::iterator Start = I;
271 // Rewind to first instruction newly inserted.
272 while (Start != BB.begin() && prior(Start) != PrevI) --Start;
273 cerr << "Inserted instructions:\n\t";
274 Start->print(*cerr.stream(), &MF.getTarget());
275 while (++Start != next(I)) {}
283 assert(StackTop == 0 && "Stack not empty at end of basic block?");
287 //===----------------------------------------------------------------------===//
288 // Efficient Lookup Table Support
289 //===----------------------------------------------------------------------===//
295 bool operator<(const TableEntry &TE) const { return from < TE.from; }
296 friend bool operator<(const TableEntry &TE, unsigned V) {
299 friend bool operator<(unsigned V, const TableEntry &TE) {
305 static bool TableIsSorted(const TableEntry *Table, unsigned NumEntries) {
306 for (unsigned i = 0; i != NumEntries-1; ++i)
307 if (!(Table[i] < Table[i+1])) return false;
311 static int Lookup(const TableEntry *Table, unsigned N, unsigned Opcode) {
312 const TableEntry *I = std::lower_bound(Table, Table+N, Opcode);
313 if (I != Table+N && I->from == Opcode)
319 #define ASSERT_SORTED(TABLE)
321 #define ASSERT_SORTED(TABLE) \
322 { static bool TABLE##Checked = false; \
323 if (!TABLE##Checked) { \
324 assert(TableIsSorted(TABLE, array_lengthof(TABLE)) && \
325 "All lookup tables must be sorted for efficient access!"); \
326 TABLE##Checked = true; \
331 //===----------------------------------------------------------------------===//
332 // Register File -> Register Stack Mapping Methods
333 //===----------------------------------------------------------------------===//
335 // OpcodeTable - Sorted map of register instructions to their stack version.
336 // The first element is an register file pseudo instruction, the second is the
337 // concrete X86 instruction which uses the register stack.
339 static const TableEntry OpcodeTable[] = {
340 { X86::ABS_Fp32 , X86::ABS_F },
341 { X86::ABS_Fp64 , X86::ABS_F },
342 { X86::ABS_Fp80 , X86::ABS_F },
343 { X86::ADD_Fp32m , X86::ADD_F32m },
344 { X86::ADD_Fp64m , X86::ADD_F64m },
345 { X86::ADD_Fp64m32 , X86::ADD_F32m },
346 { X86::ADD_Fp80m32 , X86::ADD_F32m },
347 { X86::ADD_Fp80m64 , X86::ADD_F64m },
348 { X86::ADD_FpI16m32 , X86::ADD_FI16m },
349 { X86::ADD_FpI16m64 , X86::ADD_FI16m },
350 { X86::ADD_FpI16m80 , X86::ADD_FI16m },
351 { X86::ADD_FpI32m32 , X86::ADD_FI32m },
352 { X86::ADD_FpI32m64 , X86::ADD_FI32m },
353 { X86::ADD_FpI32m80 , X86::ADD_FI32m },
354 { X86::CHS_Fp32 , X86::CHS_F },
355 { X86::CHS_Fp64 , X86::CHS_F },
356 { X86::CHS_Fp80 , X86::CHS_F },
357 { X86::CMOVBE_Fp32 , X86::CMOVBE_F },
358 { X86::CMOVBE_Fp64 , X86::CMOVBE_F },
359 { X86::CMOVBE_Fp80 , X86::CMOVBE_F },
360 { X86::CMOVB_Fp32 , X86::CMOVB_F },
361 { X86::CMOVB_Fp64 , X86::CMOVB_F },
362 { X86::CMOVB_Fp80 , X86::CMOVB_F },
363 { X86::CMOVE_Fp32 , X86::CMOVE_F },
364 { X86::CMOVE_Fp64 , X86::CMOVE_F },
365 { X86::CMOVE_Fp80 , X86::CMOVE_F },
366 { X86::CMOVNBE_Fp32 , X86::CMOVNBE_F },
367 { X86::CMOVNBE_Fp64 , X86::CMOVNBE_F },
368 { X86::CMOVNBE_Fp80 , X86::CMOVNBE_F },
369 { X86::CMOVNB_Fp32 , X86::CMOVNB_F },
370 { X86::CMOVNB_Fp64 , X86::CMOVNB_F },
371 { X86::CMOVNB_Fp80 , X86::CMOVNB_F },
372 { X86::CMOVNE_Fp32 , X86::CMOVNE_F },
373 { X86::CMOVNE_Fp64 , X86::CMOVNE_F },
374 { X86::CMOVNE_Fp80 , X86::CMOVNE_F },
375 { X86::CMOVNP_Fp32 , X86::CMOVNP_F },
376 { X86::CMOVNP_Fp64 , X86::CMOVNP_F },
377 { X86::CMOVNP_Fp80 , X86::CMOVNP_F },
378 { X86::CMOVP_Fp32 , X86::CMOVP_F },
379 { X86::CMOVP_Fp64 , X86::CMOVP_F },
380 { X86::CMOVP_Fp80 , X86::CMOVP_F },
381 { X86::COS_Fp32 , X86::COS_F },
382 { X86::COS_Fp64 , X86::COS_F },
383 { X86::COS_Fp80 , X86::COS_F },
384 { X86::DIVR_Fp32m , X86::DIVR_F32m },
385 { X86::DIVR_Fp64m , X86::DIVR_F64m },
386 { X86::DIVR_Fp64m32 , X86::DIVR_F32m },
387 { X86::DIVR_Fp80m32 , X86::DIVR_F32m },
388 { X86::DIVR_Fp80m64 , X86::DIVR_F64m },
389 { X86::DIVR_FpI16m32, X86::DIVR_FI16m},
390 { X86::DIVR_FpI16m64, X86::DIVR_FI16m},
391 { X86::DIVR_FpI16m80, X86::DIVR_FI16m},
392 { X86::DIVR_FpI32m32, X86::DIVR_FI32m},
393 { X86::DIVR_FpI32m64, X86::DIVR_FI32m},
394 { X86::DIVR_FpI32m80, X86::DIVR_FI32m},
395 { X86::DIV_Fp32m , X86::DIV_F32m },
396 { X86::DIV_Fp64m , X86::DIV_F64m },
397 { X86::DIV_Fp64m32 , X86::DIV_F32m },
398 { X86::DIV_Fp80m32 , X86::DIV_F32m },
399 { X86::DIV_Fp80m64 , X86::DIV_F64m },
400 { X86::DIV_FpI16m32 , X86::DIV_FI16m },
401 { X86::DIV_FpI16m64 , X86::DIV_FI16m },
402 { X86::DIV_FpI16m80 , X86::DIV_FI16m },
403 { X86::DIV_FpI32m32 , X86::DIV_FI32m },
404 { X86::DIV_FpI32m64 , X86::DIV_FI32m },
405 { X86::DIV_FpI32m80 , X86::DIV_FI32m },
406 { X86::ILD_Fp16m32 , X86::ILD_F16m },
407 { X86::ILD_Fp16m64 , X86::ILD_F16m },
408 { X86::ILD_Fp16m80 , X86::ILD_F16m },
409 { X86::ILD_Fp32m32 , X86::ILD_F32m },
410 { X86::ILD_Fp32m64 , X86::ILD_F32m },
411 { X86::ILD_Fp32m80 , X86::ILD_F32m },
412 { X86::ILD_Fp64m32 , X86::ILD_F64m },
413 { X86::ILD_Fp64m64 , X86::ILD_F64m },
414 { X86::ILD_Fp64m80 , X86::ILD_F64m },
415 { X86::ISTT_Fp16m32 , X86::ISTT_FP16m},
416 { X86::ISTT_Fp16m64 , X86::ISTT_FP16m},
417 { X86::ISTT_Fp16m80 , X86::ISTT_FP16m},
418 { X86::ISTT_Fp32m32 , X86::ISTT_FP32m},
419 { X86::ISTT_Fp32m64 , X86::ISTT_FP32m},
420 { X86::ISTT_Fp32m80 , X86::ISTT_FP32m},
421 { X86::ISTT_Fp64m32 , X86::ISTT_FP64m},
422 { X86::ISTT_Fp64m64 , X86::ISTT_FP64m},
423 { X86::ISTT_Fp64m80 , X86::ISTT_FP64m},
424 { X86::IST_Fp16m32 , X86::IST_F16m },
425 { X86::IST_Fp16m64 , X86::IST_F16m },
426 { X86::IST_Fp16m80 , X86::IST_F16m },
427 { X86::IST_Fp32m32 , X86::IST_F32m },
428 { X86::IST_Fp32m64 , X86::IST_F32m },
429 { X86::IST_Fp32m80 , X86::IST_F32m },
430 { X86::IST_Fp64m32 , X86::IST_FP64m },
431 { X86::IST_Fp64m64 , X86::IST_FP64m },
432 { X86::IST_Fp64m80 , X86::IST_FP64m },
433 { X86::LD_Fp032 , X86::LD_F0 },
434 { X86::LD_Fp064 , X86::LD_F0 },
435 { X86::LD_Fp080 , X86::LD_F0 },
436 { X86::LD_Fp132 , X86::LD_F1 },
437 { X86::LD_Fp164 , X86::LD_F1 },
438 { X86::LD_Fp180 , X86::LD_F1 },
439 { X86::LD_Fp32m , X86::LD_F32m },
440 { X86::LD_Fp32m64 , X86::LD_F32m },
441 { X86::LD_Fp32m80 , X86::LD_F32m },
442 { X86::LD_Fp64m , X86::LD_F64m },
443 { X86::LD_Fp64m80 , X86::LD_F64m },
444 { X86::LD_Fp80m , X86::LD_F80m },
445 { X86::MUL_Fp32m , X86::MUL_F32m },
446 { X86::MUL_Fp64m , X86::MUL_F64m },
447 { X86::MUL_Fp64m32 , X86::MUL_F32m },
448 { X86::MUL_Fp80m32 , X86::MUL_F32m },
449 { X86::MUL_Fp80m64 , X86::MUL_F64m },
450 { X86::MUL_FpI16m32 , X86::MUL_FI16m },
451 { X86::MUL_FpI16m64 , X86::MUL_FI16m },
452 { X86::MUL_FpI16m80 , X86::MUL_FI16m },
453 { X86::MUL_FpI32m32 , X86::MUL_FI32m },
454 { X86::MUL_FpI32m64 , X86::MUL_FI32m },
455 { X86::MUL_FpI32m80 , X86::MUL_FI32m },
456 { X86::SIN_Fp32 , X86::SIN_F },
457 { X86::SIN_Fp64 , X86::SIN_F },
458 { X86::SIN_Fp80 , X86::SIN_F },
459 { X86::SQRT_Fp32 , X86::SQRT_F },
460 { X86::SQRT_Fp64 , X86::SQRT_F },
461 { X86::SQRT_Fp80 , X86::SQRT_F },
462 { X86::ST_Fp32m , X86::ST_F32m },
463 { X86::ST_Fp64m , X86::ST_F64m },
464 { X86::ST_Fp64m32 , X86::ST_F32m },
465 { X86::ST_Fp80m32 , X86::ST_F32m },
466 { X86::ST_Fp80m64 , X86::ST_F64m },
467 { X86::ST_FpP80m , X86::ST_FP80m },
468 { X86::SUBR_Fp32m , X86::SUBR_F32m },
469 { X86::SUBR_Fp64m , X86::SUBR_F64m },
470 { X86::SUBR_Fp64m32 , X86::SUBR_F32m },
471 { X86::SUBR_Fp80m32 , X86::SUBR_F32m },
472 { X86::SUBR_Fp80m64 , X86::SUBR_F64m },
473 { X86::SUBR_FpI16m32, X86::SUBR_FI16m},
474 { X86::SUBR_FpI16m64, X86::SUBR_FI16m},
475 { X86::SUBR_FpI16m80, X86::SUBR_FI16m},
476 { X86::SUBR_FpI32m32, X86::SUBR_FI32m},
477 { X86::SUBR_FpI32m64, X86::SUBR_FI32m},
478 { X86::SUBR_FpI32m80, X86::SUBR_FI32m},
479 { X86::SUB_Fp32m , X86::SUB_F32m },
480 { X86::SUB_Fp64m , X86::SUB_F64m },
481 { X86::SUB_Fp64m32 , X86::SUB_F32m },
482 { X86::SUB_Fp80m32 , X86::SUB_F32m },
483 { X86::SUB_Fp80m64 , X86::SUB_F64m },
484 { X86::SUB_FpI16m32 , X86::SUB_FI16m },
485 { X86::SUB_FpI16m64 , X86::SUB_FI16m },
486 { X86::SUB_FpI16m80 , X86::SUB_FI16m },
487 { X86::SUB_FpI32m32 , X86::SUB_FI32m },
488 { X86::SUB_FpI32m64 , X86::SUB_FI32m },
489 { X86::SUB_FpI32m80 , X86::SUB_FI32m },
490 { X86::TST_Fp32 , X86::TST_F },
491 { X86::TST_Fp64 , X86::TST_F },
492 { X86::TST_Fp80 , X86::TST_F },
493 { X86::UCOM_FpIr32 , X86::UCOM_FIr },
494 { X86::UCOM_FpIr64 , X86::UCOM_FIr },
495 { X86::UCOM_FpIr80 , X86::UCOM_FIr },
496 { X86::UCOM_Fpr32 , X86::UCOM_Fr },
497 { X86::UCOM_Fpr64 , X86::UCOM_Fr },
498 { X86::UCOM_Fpr80 , X86::UCOM_Fr },
501 static unsigned getConcreteOpcode(unsigned Opcode) {
502 ASSERT_SORTED(OpcodeTable);
503 int Opc = Lookup(OpcodeTable, array_lengthof(OpcodeTable), Opcode);
504 assert(Opc != -1 && "FP Stack instruction not in OpcodeTable!");
508 //===----------------------------------------------------------------------===//
510 //===----------------------------------------------------------------------===//
512 // PopTable - Sorted map of instructions to their popping version. The first
513 // element is an instruction, the second is the version which pops.
515 static const TableEntry PopTable[] = {
516 { X86::ADD_FrST0 , X86::ADD_FPrST0 },
518 { X86::DIVR_FrST0, X86::DIVR_FPrST0 },
519 { X86::DIV_FrST0 , X86::DIV_FPrST0 },
521 { X86::IST_F16m , X86::IST_FP16m },
522 { X86::IST_F32m , X86::IST_FP32m },
524 { X86::MUL_FrST0 , X86::MUL_FPrST0 },
526 { X86::ST_F32m , X86::ST_FP32m },
527 { X86::ST_F64m , X86::ST_FP64m },
528 { X86::ST_Frr , X86::ST_FPrr },
530 { X86::SUBR_FrST0, X86::SUBR_FPrST0 },
531 { X86::SUB_FrST0 , X86::SUB_FPrST0 },
533 { X86::UCOM_FIr , X86::UCOM_FIPr },
535 { X86::UCOM_FPr , X86::UCOM_FPPr },
536 { X86::UCOM_Fr , X86::UCOM_FPr },
539 /// popStackAfter - Pop the current value off of the top of the FP stack after
540 /// the specified instruction. This attempts to be sneaky and combine the pop
541 /// into the instruction itself if possible. The iterator is left pointing to
542 /// the last instruction, be it a new pop instruction inserted, or the old
543 /// instruction if it was modified in place.
545 void FPS::popStackAfter(MachineBasicBlock::iterator &I) {
546 ASSERT_SORTED(PopTable);
547 assert(StackTop > 0 && "Cannot pop empty stack!");
548 RegMap[Stack[--StackTop]] = ~0; // Update state
550 // Check to see if there is a popping version of this instruction...
551 int Opcode = Lookup(PopTable, array_lengthof(PopTable), I->getOpcode());
553 I->setDesc(TII->get(Opcode));
554 if (Opcode == X86::UCOM_FPPr)
556 } else { // Insert an explicit pop
557 I = BuildMI(*MBB, ++I, TII->get(X86::ST_FPrr)).addReg(X86::ST0);
561 /// freeStackSlotAfter - Free the specified register from the register stack, so
562 /// that it is no longer in a register. If the register is currently at the top
563 /// of the stack, we just pop the current instruction, otherwise we store the
564 /// current top-of-stack into the specified slot, then pop the top of stack.
565 void FPS::freeStackSlotAfter(MachineBasicBlock::iterator &I, unsigned FPRegNo) {
566 if (getStackEntry(0) == FPRegNo) { // already at the top of stack? easy.
571 // Otherwise, store the top of stack into the dead slot, killing the operand
572 // without having to add in an explicit xchg then pop.
574 unsigned STReg = getSTReg(FPRegNo);
575 unsigned OldSlot = getSlot(FPRegNo);
576 unsigned TopReg = Stack[StackTop-1];
577 Stack[OldSlot] = TopReg;
578 RegMap[TopReg] = OldSlot;
579 RegMap[FPRegNo] = ~0;
580 Stack[--StackTop] = ~0;
581 I = BuildMI(*MBB, ++I, TII->get(X86::ST_FPrr)).addReg(STReg);
585 //===----------------------------------------------------------------------===//
586 // Instruction transformation implementation
587 //===----------------------------------------------------------------------===//
589 /// handleZeroArgFP - ST(0) = fld0 ST(0) = flds <mem>
591 void FPS::handleZeroArgFP(MachineBasicBlock::iterator &I) {
592 MachineInstr *MI = I;
593 unsigned DestReg = getFPReg(MI->getOperand(0));
595 // Change from the pseudo instruction to the concrete instruction.
596 MI->RemoveOperand(0); // Remove the explicit ST(0) operand
597 MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode())));
599 // Result gets pushed on the stack.
603 /// handleOneArgFP - fst <mem>, ST(0)
605 void FPS::handleOneArgFP(MachineBasicBlock::iterator &I) {
606 MachineInstr *MI = I;
607 unsigned NumOps = MI->getDesc().getNumOperands();
608 assert((NumOps == 5 || NumOps == 1) &&
609 "Can only handle fst* & ftst instructions!");
611 // Is this the last use of the source register?
612 unsigned Reg = getFPReg(MI->getOperand(NumOps-1));
613 bool KillsSrc = KillsRegister(MI, X86::FP0+Reg);
615 // FISTP64m is strange because there isn't a non-popping versions.
616 // If we have one _and_ we don't want to pop the operand, duplicate the value
617 // on the stack instead of moving it. This ensure that popping the value is
619 // Ditto FISTTP16m, FISTTP32m, FISTTP64m, ST_FpP80m.
622 (MI->getOpcode() == X86::IST_Fp64m32 ||
623 MI->getOpcode() == X86::ISTT_Fp16m32 ||
624 MI->getOpcode() == X86::ISTT_Fp32m32 ||
625 MI->getOpcode() == X86::ISTT_Fp64m32 ||
626 MI->getOpcode() == X86::IST_Fp64m64 ||
627 MI->getOpcode() == X86::ISTT_Fp16m64 ||
628 MI->getOpcode() == X86::ISTT_Fp32m64 ||
629 MI->getOpcode() == X86::ISTT_Fp64m64 ||
630 MI->getOpcode() == X86::IST_Fp64m80 ||
631 MI->getOpcode() == X86::ISTT_Fp16m80 ||
632 MI->getOpcode() == X86::ISTT_Fp32m80 ||
633 MI->getOpcode() == X86::ISTT_Fp64m80 ||
634 MI->getOpcode() == X86::ST_FpP80m)) {
635 duplicateToTop(Reg, 7 /*temp register*/, I);
637 moveToTop(Reg, I); // Move to the top of the stack...
640 // Convert from the pseudo instruction to the concrete instruction.
641 MI->RemoveOperand(NumOps-1); // Remove explicit ST(0) operand
642 MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode())));
644 if (MI->getOpcode() == X86::IST_FP64m ||
645 MI->getOpcode() == X86::ISTT_FP16m ||
646 MI->getOpcode() == X86::ISTT_FP32m ||
647 MI->getOpcode() == X86::ISTT_FP64m ||
648 MI->getOpcode() == X86::ST_FP80m) {
649 assert(StackTop > 0 && "Stack empty??");
651 } else if (KillsSrc) { // Last use of operand?
657 /// handleOneArgFPRW: Handle instructions that read from the top of stack and
658 /// replace the value with a newly computed value. These instructions may have
659 /// non-fp operands after their FP operands.
663 /// R1 = fadd R2, [mem]
665 void FPS::handleOneArgFPRW(MachineBasicBlock::iterator &I) {
666 MachineInstr *MI = I;
667 unsigned NumOps = MI->getDesc().getNumOperands();
668 assert(NumOps >= 2 && "FPRW instructions must have 2 ops!!");
670 // Is this the last use of the source register?
671 unsigned Reg = getFPReg(MI->getOperand(1));
672 bool KillsSrc = KillsRegister(MI, X86::FP0+Reg);
675 // If this is the last use of the source register, just make sure it's on
676 // the top of the stack.
678 assert(StackTop > 0 && "Stack cannot be empty!");
680 pushReg(getFPReg(MI->getOperand(0)));
682 // If this is not the last use of the source register, _copy_ it to the top
684 duplicateToTop(Reg, getFPReg(MI->getOperand(0)), I);
687 // Change from the pseudo instruction to the concrete instruction.
688 MI->RemoveOperand(1); // Drop the source operand.
689 MI->RemoveOperand(0); // Drop the destination operand.
690 MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode())));
694 //===----------------------------------------------------------------------===//
695 // Define tables of various ways to map pseudo instructions
698 // ForwardST0Table - Map: A = B op C into: ST(0) = ST(0) op ST(i)
699 static const TableEntry ForwardST0Table[] = {
700 { X86::ADD_Fp32 , X86::ADD_FST0r },
701 { X86::ADD_Fp64 , X86::ADD_FST0r },
702 { X86::ADD_Fp80 , X86::ADD_FST0r },
703 { X86::DIV_Fp32 , X86::DIV_FST0r },
704 { X86::DIV_Fp64 , X86::DIV_FST0r },
705 { X86::DIV_Fp80 , X86::DIV_FST0r },
706 { X86::MUL_Fp32 , X86::MUL_FST0r },
707 { X86::MUL_Fp64 , X86::MUL_FST0r },
708 { X86::MUL_Fp80 , X86::MUL_FST0r },
709 { X86::SUB_Fp32 , X86::SUB_FST0r },
710 { X86::SUB_Fp64 , X86::SUB_FST0r },
711 { X86::SUB_Fp80 , X86::SUB_FST0r },
714 // ReverseST0Table - Map: A = B op C into: ST(0) = ST(i) op ST(0)
715 static const TableEntry ReverseST0Table[] = {
716 { X86::ADD_Fp32 , X86::ADD_FST0r }, // commutative
717 { X86::ADD_Fp64 , X86::ADD_FST0r }, // commutative
718 { X86::ADD_Fp80 , X86::ADD_FST0r }, // commutative
719 { X86::DIV_Fp32 , X86::DIVR_FST0r },
720 { X86::DIV_Fp64 , X86::DIVR_FST0r },
721 { X86::DIV_Fp80 , X86::DIVR_FST0r },
722 { X86::MUL_Fp32 , X86::MUL_FST0r }, // commutative
723 { X86::MUL_Fp64 , X86::MUL_FST0r }, // commutative
724 { X86::MUL_Fp80 , X86::MUL_FST0r }, // commutative
725 { X86::SUB_Fp32 , X86::SUBR_FST0r },
726 { X86::SUB_Fp64 , X86::SUBR_FST0r },
727 { X86::SUB_Fp80 , X86::SUBR_FST0r },
730 // ForwardSTiTable - Map: A = B op C into: ST(i) = ST(0) op ST(i)
731 static const TableEntry ForwardSTiTable[] = {
732 { X86::ADD_Fp32 , X86::ADD_FrST0 }, // commutative
733 { X86::ADD_Fp64 , X86::ADD_FrST0 }, // commutative
734 { X86::ADD_Fp80 , X86::ADD_FrST0 }, // commutative
735 { X86::DIV_Fp32 , X86::DIVR_FrST0 },
736 { X86::DIV_Fp64 , X86::DIVR_FrST0 },
737 { X86::DIV_Fp80 , X86::DIVR_FrST0 },
738 { X86::MUL_Fp32 , X86::MUL_FrST0 }, // commutative
739 { X86::MUL_Fp64 , X86::MUL_FrST0 }, // commutative
740 { X86::MUL_Fp80 , X86::MUL_FrST0 }, // commutative
741 { X86::SUB_Fp32 , X86::SUBR_FrST0 },
742 { X86::SUB_Fp64 , X86::SUBR_FrST0 },
743 { X86::SUB_Fp80 , X86::SUBR_FrST0 },
746 // ReverseSTiTable - Map: A = B op C into: ST(i) = ST(i) op ST(0)
747 static const TableEntry ReverseSTiTable[] = {
748 { X86::ADD_Fp32 , X86::ADD_FrST0 },
749 { X86::ADD_Fp64 , X86::ADD_FrST0 },
750 { X86::ADD_Fp80 , X86::ADD_FrST0 },
751 { X86::DIV_Fp32 , X86::DIV_FrST0 },
752 { X86::DIV_Fp64 , X86::DIV_FrST0 },
753 { X86::DIV_Fp80 , X86::DIV_FrST0 },
754 { X86::MUL_Fp32 , X86::MUL_FrST0 },
755 { X86::MUL_Fp64 , X86::MUL_FrST0 },
756 { X86::MUL_Fp80 , X86::MUL_FrST0 },
757 { X86::SUB_Fp32 , X86::SUB_FrST0 },
758 { X86::SUB_Fp64 , X86::SUB_FrST0 },
759 { X86::SUB_Fp80 , X86::SUB_FrST0 },
763 /// handleTwoArgFP - Handle instructions like FADD and friends which are virtual
764 /// instructions which need to be simplified and possibly transformed.
766 /// Result: ST(0) = fsub ST(0), ST(i)
767 /// ST(i) = fsub ST(0), ST(i)
768 /// ST(0) = fsubr ST(0), ST(i)
769 /// ST(i) = fsubr ST(0), ST(i)
771 void FPS::handleTwoArgFP(MachineBasicBlock::iterator &I) {
772 ASSERT_SORTED(ForwardST0Table); ASSERT_SORTED(ReverseST0Table);
773 ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable);
774 MachineInstr *MI = I;
776 unsigned NumOperands = MI->getDesc().getNumOperands();
777 assert(NumOperands == 3 && "Illegal TwoArgFP instruction!");
778 unsigned Dest = getFPReg(MI->getOperand(0));
779 unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2));
780 unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1));
781 bool KillsOp0 = KillsRegister(MI, X86::FP0+Op0);
782 bool KillsOp1 = KillsRegister(MI, X86::FP0+Op1);
784 unsigned TOS = getStackEntry(0);
786 // One of our operands must be on the top of the stack. If neither is yet, we
788 if (Op0 != TOS && Op1 != TOS) { // No operand at TOS?
789 // We can choose to move either operand to the top of the stack. If one of
790 // the operands is killed by this instruction, we want that one so that we
791 // can update right on top of the old version.
793 moveToTop(Op0, I); // Move dead operand to TOS.
795 } else if (KillsOp1) {
799 // All of the operands are live after this instruction executes, so we
800 // cannot update on top of any operand. Because of this, we must
801 // duplicate one of the stack elements to the top. It doesn't matter
802 // which one we pick.
804 duplicateToTop(Op0, Dest, I);
808 } else if (!KillsOp0 && !KillsOp1) {
809 // If we DO have one of our operands at the top of the stack, but we don't
810 // have a dead operand, we must duplicate one of the operands to a new slot
812 duplicateToTop(Op0, Dest, I);
817 // Now we know that one of our operands is on the top of the stack, and at
818 // least one of our operands is killed by this instruction.
819 assert((TOS == Op0 || TOS == Op1) && (KillsOp0 || KillsOp1) &&
820 "Stack conditions not set up right!");
822 // We decide which form to use based on what is on the top of the stack, and
823 // which operand is killed by this instruction.
824 const TableEntry *InstTable;
825 bool isForward = TOS == Op0;
826 bool updateST0 = (TOS == Op0 && !KillsOp1) || (TOS == Op1 && !KillsOp0);
829 InstTable = ForwardST0Table;
831 InstTable = ReverseST0Table;
834 InstTable = ForwardSTiTable;
836 InstTable = ReverseSTiTable;
839 int Opcode = Lookup(InstTable, array_lengthof(ForwardST0Table),
841 assert(Opcode != -1 && "Unknown TwoArgFP pseudo instruction!");
843 // NotTOS - The register which is not on the top of stack...
844 unsigned NotTOS = (TOS == Op0) ? Op1 : Op0;
846 // Replace the old instruction with a new instruction
848 I = BuildMI(*MBB, I, TII->get(Opcode)).addReg(getSTReg(NotTOS));
850 // If both operands are killed, pop one off of the stack in addition to
851 // overwriting the other one.
852 if (KillsOp0 && KillsOp1 && Op0 != Op1) {
853 assert(!updateST0 && "Should have updated other operand!");
854 popStackAfter(I); // Pop the top of stack
857 // Update stack information so that we know the destination register is now on
859 unsigned UpdatedSlot = getSlot(updateST0 ? TOS : NotTOS);
860 assert(UpdatedSlot < StackTop && Dest < 7);
861 Stack[UpdatedSlot] = Dest;
862 RegMap[Dest] = UpdatedSlot;
863 delete MI; // Remove the old instruction
866 /// handleCompareFP - Handle FUCOM and FUCOMI instructions, which have two FP
867 /// register arguments and no explicit destinations.
869 void FPS::handleCompareFP(MachineBasicBlock::iterator &I) {
870 ASSERT_SORTED(ForwardST0Table); ASSERT_SORTED(ReverseST0Table);
871 ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable);
872 MachineInstr *MI = I;
874 unsigned NumOperands = MI->getDesc().getNumOperands();
875 assert(NumOperands == 2 && "Illegal FUCOM* instruction!");
876 unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2));
877 unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1));
878 bool KillsOp0 = KillsRegister(MI, X86::FP0+Op0);
879 bool KillsOp1 = KillsRegister(MI, X86::FP0+Op1);
881 // Make sure the first operand is on the top of stack, the other one can be
885 // Change from the pseudo instruction to the concrete instruction.
886 MI->getOperand(0).setReg(getSTReg(Op1));
887 MI->RemoveOperand(1);
888 MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode())));
890 // If any of the operands are killed by this instruction, free them.
891 if (KillsOp0) freeStackSlotAfter(I, Op0);
892 if (KillsOp1 && Op0 != Op1) freeStackSlotAfter(I, Op1);
895 /// handleCondMovFP - Handle two address conditional move instructions. These
896 /// instructions move a st(i) register to st(0) iff a condition is true. These
897 /// instructions require that the first operand is at the top of the stack, but
898 /// otherwise don't modify the stack at all.
899 void FPS::handleCondMovFP(MachineBasicBlock::iterator &I) {
900 MachineInstr *MI = I;
902 unsigned Op0 = getFPReg(MI->getOperand(0));
903 unsigned Op1 = getFPReg(MI->getOperand(2));
904 bool KillsOp1 = KillsRegister(MI, X86::FP0+Op1);
906 // The first operand *must* be on the top of the stack.
909 // Change the second operand to the stack register that the operand is in.
910 // Change from the pseudo instruction to the concrete instruction.
911 MI->RemoveOperand(0);
912 MI->RemoveOperand(1);
913 MI->getOperand(0).setReg(getSTReg(Op1));
914 MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode())));
916 // If we kill the second operand, make sure to pop it from the stack.
917 if (Op0 != Op1 && KillsOp1) {
918 // Get this value off of the register stack.
919 freeStackSlotAfter(I, Op1);
924 /// handleSpecialFP - Handle special instructions which behave unlike other
925 /// floating point instructions. This is primarily intended for use by pseudo
928 void FPS::handleSpecialFP(MachineBasicBlock::iterator &I) {
929 MachineInstr *MI = I;
930 switch (MI->getOpcode()) {
931 default: assert(0 && "Unknown SpecialFP instruction!");
932 case X86::FpGETRESULT32: // Appears immediately after a call returning FP type!
933 case X86::FpGETRESULT64: // Appears immediately after a call returning FP type!
934 case X86::FpGETRESULT80:
935 assert(StackTop == 0 && "Stack should be empty after a call!");
936 pushReg(getFPReg(MI->getOperand(0)));
938 case X86::FpSETRESULT32:
939 case X86::FpSETRESULT64:
940 case X86::FpSETRESULT80:
941 assert(StackTop == 1 && "Stack should have one element on it to return!");
942 --StackTop; // "Forget" we have something on the top of stack!
944 case X86::MOV_Fp3232:
945 case X86::MOV_Fp3264:
946 case X86::MOV_Fp6432:
947 case X86::MOV_Fp6464:
948 case X86::MOV_Fp3280:
949 case X86::MOV_Fp6480:
950 case X86::MOV_Fp8032:
951 case X86::MOV_Fp8064:
952 case X86::MOV_Fp8080: {
953 unsigned SrcReg = getFPReg(MI->getOperand(1));
954 unsigned DestReg = getFPReg(MI->getOperand(0));
956 if (KillsRegister(MI, X86::FP0+SrcReg)) {
957 // If the input operand is killed, we can just change the owner of the
958 // incoming stack slot into the result.
959 unsigned Slot = getSlot(SrcReg);
960 assert(Slot < 7 && DestReg < 7 && "FpMOV operands invalid!");
961 Stack[Slot] = DestReg;
962 RegMap[DestReg] = Slot;
965 // For FMOV we just duplicate the specified value to a new stack slot.
966 // This could be made better, but would require substantial changes.
967 duplicateToTop(SrcReg, DestReg, I);
973 I = MBB->erase(I); // Remove the pseudo instruction