1 //===-- X86FastISel.cpp - X86 FastISel implementation ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the X86-specific support for the FastISel class. Much
11 // of the target-specific code is generated by tablegen in the file
12 // X86GenFastISel.inc, which is #included here.
14 //===----------------------------------------------------------------------===//
17 #include "X86InstrBuilder.h"
18 #include "X86ISelLowering.h"
19 #include "X86RegisterInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/DerivedTypes.h"
24 #include "llvm/GlobalVariable.h"
25 #include "llvm/Instructions.h"
26 #include "llvm/IntrinsicInst.h"
27 #include "llvm/CodeGen/FastISel.h"
28 #include "llvm/CodeGen/MachineConstantPool.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/Support/CallSite.h"
32 #include "llvm/Support/GetElementPtrTypeIterator.h"
33 #include "llvm/Target/TargetOptions.h"
38 class X86FastISel : public FastISel {
39 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
40 /// make the right decision when generating code for different targets.
41 const X86Subtarget *Subtarget;
43 /// StackPtr - Register used as the stack pointer.
47 /// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87
48 /// floating point ops.
49 /// When SSE is available, use it for f32 operations.
50 /// When SSE2 is available, use it for f64 operations.
55 explicit X86FastISel(MachineFunction &mf,
56 MachineModuleInfo *mmi,
58 DenseMap<const Value *, unsigned> &vm,
59 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
60 DenseMap<const AllocaInst *, int> &am
62 , SmallSet<Instruction*, 8> &cil
65 : FastISel(mf, mmi, dw, vm, bm, am
70 Subtarget = &TM.getSubtarget<X86Subtarget>();
71 StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
72 X86ScalarSSEf64 = Subtarget->hasSSE2();
73 X86ScalarSSEf32 = Subtarget->hasSSE1();
76 virtual bool TargetSelectInstruction(Instruction *I);
78 #include "X86GenFastISel.inc"
81 bool X86FastEmitCompare(Value *LHS, Value *RHS, MVT VT);
83 bool X86FastEmitLoad(MVT VT, const X86AddressMode &AM, unsigned &RR);
85 bool X86FastEmitStore(MVT VT, Value *Val,
86 const X86AddressMode &AM);
87 bool X86FastEmitStore(MVT VT, unsigned Val,
88 const X86AddressMode &AM);
90 bool X86FastEmitExtend(ISD::NodeType Opc, MVT DstVT, unsigned Src, MVT SrcVT,
93 bool X86SelectAddress(Value *V, X86AddressMode &AM, bool isCall);
95 bool X86SelectLoad(Instruction *I);
97 bool X86SelectStore(Instruction *I);
99 bool X86SelectCmp(Instruction *I);
101 bool X86SelectZExt(Instruction *I);
103 bool X86SelectBranch(Instruction *I);
105 bool X86SelectShift(Instruction *I);
107 bool X86SelectSelect(Instruction *I);
109 bool X86SelectTrunc(Instruction *I);
111 bool X86SelectFPExt(Instruction *I);
112 bool X86SelectFPTrunc(Instruction *I);
114 bool X86SelectExtractValue(Instruction *I);
116 bool X86VisitIntrinsicCall(IntrinsicInst &I);
117 bool X86SelectCall(Instruction *I);
119 CCAssignFn *CCAssignFnForCall(unsigned CC, bool isTailCall = false);
121 const X86InstrInfo *getInstrInfo() const {
122 return getTargetMachine()->getInstrInfo();
124 const X86TargetMachine *getTargetMachine() const {
125 return static_cast<const X86TargetMachine *>(&TM);
128 unsigned TargetMaterializeConstant(Constant *C);
130 unsigned TargetMaterializeAlloca(AllocaInst *C);
132 /// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is
133 /// computed in an SSE register, not on the X87 floating point stack.
134 bool isScalarFPTypeInSSEReg(MVT VT) const {
135 return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
136 (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
139 bool isTypeLegal(const Type *Ty, MVT &VT, bool AllowI1 = false);
142 } // end anonymous namespace.
144 bool X86FastISel::isTypeLegal(const Type *Ty, MVT &VT, bool AllowI1) {
145 VT = TLI.getValueType(Ty, /*HandleUnknown=*/true);
146 if (VT == MVT::Other || !VT.isSimple())
147 // Unhandled type. Halt "fast" selection and bail.
150 // For now, require SSE/SSE2 for performing floating-point operations,
151 // since x87 requires additional work.
152 if (VT == MVT::f64 && !X86ScalarSSEf64)
154 if (VT == MVT::f32 && !X86ScalarSSEf32)
156 // Similarly, no f80 support yet.
159 // We only handle legal types. For example, on x86-32 the instruction
160 // selector contains all of the 64-bit instructions from x86-64,
161 // under the assumption that i64 won't be used if the target doesn't
163 return (AllowI1 && VT == MVT::i1) || TLI.isTypeLegal(VT);
166 #include "X86GenCallingConv.inc"
168 /// CCAssignFnForCall - Selects the correct CCAssignFn for a given calling
170 CCAssignFn *X86FastISel::CCAssignFnForCall(unsigned CC, bool isTaillCall) {
171 if (Subtarget->is64Bit()) {
172 if (Subtarget->isTargetWin64())
173 return CC_X86_Win64_C;
178 if (CC == CallingConv::X86_FastCall)
179 return CC_X86_32_FastCall;
180 else if (CC == CallingConv::Fast)
181 return CC_X86_32_FastCC;
186 /// X86FastEmitLoad - Emit a machine instruction to load a value of type VT.
187 /// The address is either pre-computed, i.e. Ptr, or a GlobalAddress, i.e. GV.
188 /// Return true and the result register by reference if it is possible.
189 bool X86FastISel::X86FastEmitLoad(MVT VT, const X86AddressMode &AM,
190 unsigned &ResultReg) {
191 // Get opcode and regclass of the output for the given load instruction.
193 const TargetRegisterClass *RC = NULL;
194 switch (VT.getSimpleVT()) {
195 default: return false;
198 RC = X86::GR8RegisterClass;
202 RC = X86::GR16RegisterClass;
206 RC = X86::GR32RegisterClass;
209 // Must be in x86-64 mode.
211 RC = X86::GR64RegisterClass;
214 if (Subtarget->hasSSE1()) {
216 RC = X86::FR32RegisterClass;
219 RC = X86::RFP32RegisterClass;
223 if (Subtarget->hasSSE2()) {
225 RC = X86::FR64RegisterClass;
228 RC = X86::RFP64RegisterClass;
232 // No f80 support yet.
236 ResultReg = createResultReg(RC);
237 addFullAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), AM);
241 /// X86FastEmitStore - Emit a machine instruction to store a value Val of
242 /// type VT. The address is either pre-computed, consisted of a base ptr, Ptr
243 /// and a displacement offset, or a GlobalAddress,
244 /// i.e. V. Return true if it is possible.
246 X86FastISel::X86FastEmitStore(MVT VT, unsigned Val,
247 const X86AddressMode &AM) {
248 // Get opcode and regclass of the output for the given store instruction.
250 switch (VT.getSimpleVT()) {
251 case MVT::f80: // No f80 support yet.
252 default: return false;
253 case MVT::i8: Opc = X86::MOV8mr; break;
254 case MVT::i16: Opc = X86::MOV16mr; break;
255 case MVT::i32: Opc = X86::MOV32mr; break;
256 case MVT::i64: Opc = X86::MOV64mr; break; // Must be in x86-64 mode.
258 Opc = Subtarget->hasSSE1() ? X86::MOVSSmr : X86::ST_Fp32m;
261 Opc = Subtarget->hasSSE2() ? X86::MOVSDmr : X86::ST_Fp64m;
265 addFullAddress(BuildMI(MBB, DL, TII.get(Opc)), AM).addReg(Val);
269 bool X86FastISel::X86FastEmitStore(MVT VT, Value *Val,
270 const X86AddressMode &AM) {
271 // Handle 'null' like i32/i64 0.
272 if (isa<ConstantPointerNull>(Val))
273 Val = Constant::getNullValue(TD.getIntPtrType());
275 // If this is a store of a simple constant, fold the constant into the store.
276 if (ConstantInt *CI = dyn_cast<ConstantInt>(Val)) {
278 switch (VT.getSimpleVT()) {
280 case MVT::i8: Opc = X86::MOV8mi; break;
281 case MVT::i16: Opc = X86::MOV16mi; break;
282 case MVT::i32: Opc = X86::MOV32mi; break;
284 // Must be a 32-bit sign extended value.
285 if ((int)CI->getSExtValue() == CI->getSExtValue())
286 Opc = X86::MOV64mi32;
291 addFullAddress(BuildMI(MBB, DL, TII.get(Opc)), AM)
292 .addImm(CI->getSExtValue());
297 unsigned ValReg = getRegForValue(Val);
301 return X86FastEmitStore(VT, ValReg, AM);
304 /// X86FastEmitExtend - Emit a machine instruction to extend a value Src of
305 /// type SrcVT to type DstVT using the specified extension opcode Opc (e.g.
306 /// ISD::SIGN_EXTEND).
307 bool X86FastISel::X86FastEmitExtend(ISD::NodeType Opc, MVT DstVT,
308 unsigned Src, MVT SrcVT,
309 unsigned &ResultReg) {
310 unsigned RR = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc, Src);
319 /// X86SelectAddress - Attempt to fill in an address from the given value.
321 bool X86FastISel::X86SelectAddress(Value *V, X86AddressMode &AM, bool isCall) {
323 unsigned Opcode = Instruction::UserOp1;
324 if (Instruction *I = dyn_cast<Instruction>(V)) {
325 Opcode = I->getOpcode();
327 } else if (ConstantExpr *C = dyn_cast<ConstantExpr>(V)) {
328 Opcode = C->getOpcode();
334 case Instruction::BitCast:
335 // Look past bitcasts.
336 return X86SelectAddress(U->getOperand(0), AM, isCall);
338 case Instruction::IntToPtr:
339 // Look past no-op inttoptrs.
340 if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
341 return X86SelectAddress(U->getOperand(0), AM, isCall);
344 case Instruction::PtrToInt:
345 // Look past no-op ptrtoints.
346 if (TLI.getValueType(U->getType()) == TLI.getPointerTy())
347 return X86SelectAddress(U->getOperand(0), AM, isCall);
350 case Instruction::Alloca: {
352 // Do static allocas.
353 const AllocaInst *A = cast<AllocaInst>(V);
354 DenseMap<const AllocaInst*, int>::iterator SI = StaticAllocaMap.find(A);
355 if (SI != StaticAllocaMap.end()) {
356 AM.BaseType = X86AddressMode::FrameIndexBase;
357 AM.Base.FrameIndex = SI->second;
363 case Instruction::Add: {
365 // Adds of constants are common and easy enough.
366 if (ConstantInt *CI = dyn_cast<ConstantInt>(U->getOperand(1))) {
367 uint64_t Disp = (int32_t)AM.Disp + (uint64_t)CI->getSExtValue();
368 // They have to fit in the 32-bit signed displacement field though.
370 AM.Disp = (uint32_t)Disp;
371 return X86SelectAddress(U->getOperand(0), AM, isCall);
377 case Instruction::GetElementPtr: {
379 // Pattern-match simple GEPs.
380 uint64_t Disp = (int32_t)AM.Disp;
381 unsigned IndexReg = AM.IndexReg;
382 unsigned Scale = AM.Scale;
383 gep_type_iterator GTI = gep_type_begin(U);
384 // Iterate through the indices, folding what we can. Constants can be
385 // folded, and one dynamic index can be handled, if the scale is supported.
386 for (User::op_iterator i = U->op_begin() + 1, e = U->op_end();
387 i != e; ++i, ++GTI) {
389 if (const StructType *STy = dyn_cast<StructType>(*GTI)) {
390 const StructLayout *SL = TD.getStructLayout(STy);
391 unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
392 Disp += SL->getElementOffset(Idx);
394 uint64_t S = TD.getTypeAllocSize(GTI.getIndexedType());
395 if (ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
396 // Constant-offset addressing.
397 Disp += CI->getSExtValue() * S;
398 } else if (IndexReg == 0 &&
399 (!AM.GV || !Subtarget->isPICStyleRIPRel()) &&
400 (S == 1 || S == 2 || S == 4 || S == 8)) {
401 // Scaled-index addressing.
403 IndexReg = getRegForGEPIndex(Op);
408 goto unsupported_gep;
411 // Check for displacement overflow.
414 // Ok, the GEP indices were covered by constant-offset and scaled-index
415 // addressing. Update the address state and move on to examining the base.
416 AM.IndexReg = IndexReg;
418 AM.Disp = (uint32_t)Disp;
419 return X86SelectAddress(U->getOperand(0), AM, isCall);
421 // Ok, the GEP indices weren't all covered.
426 // Handle constant address.
427 if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
428 // Can't handle alternate code models yet.
429 if (TM.getCodeModel() != CodeModel::Default &&
430 TM.getCodeModel() != CodeModel::Small)
433 // RIP-relative addresses can't have additional register operands.
434 if (Subtarget->isPICStyleRIPRel() &&
435 (AM.Base.Reg != 0 || AM.IndexReg != 0))
438 // Can't handle TLS yet.
439 if (GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV))
440 if (GVar->isThreadLocal())
443 // Set up the basic address.
447 TM.getRelocationModel() == Reloc::PIC_ &&
448 !Subtarget->is64Bit())
449 AM.Base.Reg = getInstrInfo()->getGlobalBaseReg(&MF);
451 // Emit an extra load if the ABI requires it.
452 if (Subtarget->GVRequiresExtraLoad(GV, TM, isCall)) {
453 // Check to see if we've already materialized this
454 // value in a register in this block.
455 DenseMap<const Value *, unsigned>::iterator I = LocalValueMap.find(V);
456 if (I != LocalValueMap.end() && I->second != 0) {
457 AM.Base.Reg = I->second;
462 // Issue load from stub.
464 const TargetRegisterClass *RC = NULL;
465 X86AddressMode StubAM;
466 StubAM.Base.Reg = AM.Base.Reg;
469 if (TLI.getPointerTy() == MVT::i32) {
471 RC = X86::GR32RegisterClass;
473 if (Subtarget->isPICStyleGOT() &&
474 TM.getRelocationModel() == Reloc::PIC_)
475 StubAM.GVOpFlags = X86II::MO_GOT;
479 RC = X86::GR64RegisterClass;
481 if (TM.getRelocationModel() != Reloc::Static)
482 StubAM.GVOpFlags = X86II::MO_GOTPCREL;
485 unsigned ResultReg = createResultReg(RC);
486 addFullAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), StubAM);
488 // Now construct the final address. Note that the Disp, Scale,
489 // and Index values may already be set here.
490 AM.Base.Reg = ResultReg;
493 // Prevent loading GV stub multiple times in same MBB.
494 LocalValueMap[V] = AM.Base.Reg;
495 } else if (Subtarget->isPICStyleRIPRel()) {
496 // Use rip-relative addressing if we can.
497 AM.Base.Reg = X86::RIP;
503 // If all else fails, try to materialize the value in a register.
504 if (!AM.GV || !Subtarget->isPICStyleRIPRel()) {
505 if (AM.Base.Reg == 0) {
506 AM.Base.Reg = getRegForValue(V);
507 return AM.Base.Reg != 0;
509 if (AM.IndexReg == 0) {
510 assert(AM.Scale == 1 && "Scale with no index!");
511 AM.IndexReg = getRegForValue(V);
512 return AM.IndexReg != 0;
519 /// X86SelectStore - Select and emit code to implement store instructions.
520 bool X86FastISel::X86SelectStore(Instruction* I) {
522 if (!isTypeLegal(I->getOperand(0)->getType(), VT))
526 if (!X86SelectAddress(I->getOperand(1), AM, false))
529 return X86FastEmitStore(VT, I->getOperand(0), AM);
532 /// X86SelectLoad - Select and emit code to implement load instructions.
534 bool X86FastISel::X86SelectLoad(Instruction *I) {
536 if (!isTypeLegal(I->getType(), VT))
540 if (!X86SelectAddress(I->getOperand(0), AM, false))
543 unsigned ResultReg = 0;
544 if (X86FastEmitLoad(VT, AM, ResultReg)) {
545 UpdateValueMap(I, ResultReg);
551 static unsigned X86ChooseCmpOpcode(MVT VT) {
552 switch (VT.getSimpleVT()) {
554 case MVT::i8: return X86::CMP8rr;
555 case MVT::i16: return X86::CMP16rr;
556 case MVT::i32: return X86::CMP32rr;
557 case MVT::i64: return X86::CMP64rr;
558 case MVT::f32: return X86::UCOMISSrr;
559 case MVT::f64: return X86::UCOMISDrr;
563 /// X86ChooseCmpImmediateOpcode - If we have a comparison with RHS as the RHS
564 /// of the comparison, return an opcode that works for the compare (e.g.
565 /// CMP32ri) otherwise return 0.
566 static unsigned X86ChooseCmpImmediateOpcode(MVT VT, ConstantInt *RHSC) {
567 switch (VT.getSimpleVT()) {
568 // Otherwise, we can't fold the immediate into this comparison.
570 case MVT::i8: return X86::CMP8ri;
571 case MVT::i16: return X86::CMP16ri;
572 case MVT::i32: return X86::CMP32ri;
574 // 64-bit comparisons are only valid if the immediate fits in a 32-bit sext
576 if ((int)RHSC->getSExtValue() == RHSC->getSExtValue())
577 return X86::CMP64ri32;
582 bool X86FastISel::X86FastEmitCompare(Value *Op0, Value *Op1, MVT VT) {
583 unsigned Op0Reg = getRegForValue(Op0);
584 if (Op0Reg == 0) return false;
586 // Handle 'null' like i32/i64 0.
587 if (isa<ConstantPointerNull>(Op1))
588 Op1 = Constant::getNullValue(TD.getIntPtrType());
590 // We have two options: compare with register or immediate. If the RHS of
591 // the compare is an immediate that we can fold into this compare, use
592 // CMPri, otherwise use CMPrr.
593 if (ConstantInt *Op1C = dyn_cast<ConstantInt>(Op1)) {
594 if (unsigned CompareImmOpc = X86ChooseCmpImmediateOpcode(VT, Op1C)) {
595 BuildMI(MBB, DL, TII.get(CompareImmOpc)).addReg(Op0Reg)
596 .addImm(Op1C->getSExtValue());
601 unsigned CompareOpc = X86ChooseCmpOpcode(VT);
602 if (CompareOpc == 0) return false;
604 unsigned Op1Reg = getRegForValue(Op1);
605 if (Op1Reg == 0) return false;
606 BuildMI(MBB, DL, TII.get(CompareOpc)).addReg(Op0Reg).addReg(Op1Reg);
611 bool X86FastISel::X86SelectCmp(Instruction *I) {
612 CmpInst *CI = cast<CmpInst>(I);
615 if (!isTypeLegal(I->getOperand(0)->getType(), VT))
618 unsigned ResultReg = createResultReg(&X86::GR8RegClass);
620 bool SwapArgs; // false -> compare Op0, Op1. true -> compare Op1, Op0.
621 switch (CI->getPredicate()) {
622 case CmpInst::FCMP_OEQ: {
623 if (!X86FastEmitCompare(CI->getOperand(0), CI->getOperand(1), VT))
626 unsigned EReg = createResultReg(&X86::GR8RegClass);
627 unsigned NPReg = createResultReg(&X86::GR8RegClass);
628 BuildMI(MBB, DL, TII.get(X86::SETEr), EReg);
629 BuildMI(MBB, DL, TII.get(X86::SETNPr), NPReg);
631 TII.get(X86::AND8rr), ResultReg).addReg(NPReg).addReg(EReg);
632 UpdateValueMap(I, ResultReg);
635 case CmpInst::FCMP_UNE: {
636 if (!X86FastEmitCompare(CI->getOperand(0), CI->getOperand(1), VT))
639 unsigned NEReg = createResultReg(&X86::GR8RegClass);
640 unsigned PReg = createResultReg(&X86::GR8RegClass);
641 BuildMI(MBB, DL, TII.get(X86::SETNEr), NEReg);
642 BuildMI(MBB, DL, TII.get(X86::SETPr), PReg);
643 BuildMI(MBB, DL, TII.get(X86::OR8rr), ResultReg).addReg(PReg).addReg(NEReg);
644 UpdateValueMap(I, ResultReg);
647 case CmpInst::FCMP_OGT: SwapArgs = false; SetCCOpc = X86::SETAr; break;
648 case CmpInst::FCMP_OGE: SwapArgs = false; SetCCOpc = X86::SETAEr; break;
649 case CmpInst::FCMP_OLT: SwapArgs = true; SetCCOpc = X86::SETAr; break;
650 case CmpInst::FCMP_OLE: SwapArgs = true; SetCCOpc = X86::SETAEr; break;
651 case CmpInst::FCMP_ONE: SwapArgs = false; SetCCOpc = X86::SETNEr; break;
652 case CmpInst::FCMP_ORD: SwapArgs = false; SetCCOpc = X86::SETNPr; break;
653 case CmpInst::FCMP_UNO: SwapArgs = false; SetCCOpc = X86::SETPr; break;
654 case CmpInst::FCMP_UEQ: SwapArgs = false; SetCCOpc = X86::SETEr; break;
655 case CmpInst::FCMP_UGT: SwapArgs = true; SetCCOpc = X86::SETBr; break;
656 case CmpInst::FCMP_UGE: SwapArgs = true; SetCCOpc = X86::SETBEr; break;
657 case CmpInst::FCMP_ULT: SwapArgs = false; SetCCOpc = X86::SETBr; break;
658 case CmpInst::FCMP_ULE: SwapArgs = false; SetCCOpc = X86::SETBEr; break;
660 case CmpInst::ICMP_EQ: SwapArgs = false; SetCCOpc = X86::SETEr; break;
661 case CmpInst::ICMP_NE: SwapArgs = false; SetCCOpc = X86::SETNEr; break;
662 case CmpInst::ICMP_UGT: SwapArgs = false; SetCCOpc = X86::SETAr; break;
663 case CmpInst::ICMP_UGE: SwapArgs = false; SetCCOpc = X86::SETAEr; break;
664 case CmpInst::ICMP_ULT: SwapArgs = false; SetCCOpc = X86::SETBr; break;
665 case CmpInst::ICMP_ULE: SwapArgs = false; SetCCOpc = X86::SETBEr; break;
666 case CmpInst::ICMP_SGT: SwapArgs = false; SetCCOpc = X86::SETGr; break;
667 case CmpInst::ICMP_SGE: SwapArgs = false; SetCCOpc = X86::SETGEr; break;
668 case CmpInst::ICMP_SLT: SwapArgs = false; SetCCOpc = X86::SETLr; break;
669 case CmpInst::ICMP_SLE: SwapArgs = false; SetCCOpc = X86::SETLEr; break;
674 Value *Op0 = CI->getOperand(0), *Op1 = CI->getOperand(1);
678 // Emit a compare of Op0/Op1.
679 if (!X86FastEmitCompare(Op0, Op1, VT))
682 BuildMI(MBB, DL, TII.get(SetCCOpc), ResultReg);
683 UpdateValueMap(I, ResultReg);
687 bool X86FastISel::X86SelectZExt(Instruction *I) {
688 // Handle zero-extension from i1 to i8, which is common.
689 if (I->getType() == Type::Int8Ty &&
690 I->getOperand(0)->getType() == Type::Int1Ty) {
691 unsigned ResultReg = getRegForValue(I->getOperand(0));
692 if (ResultReg == 0) return false;
693 // Set the high bits to zero.
694 ResultReg = FastEmitZExtFromI1(MVT::i8, ResultReg);
695 if (ResultReg == 0) return false;
696 UpdateValueMap(I, ResultReg);
704 bool X86FastISel::X86SelectBranch(Instruction *I) {
705 // Unconditional branches are selected by tablegen-generated code.
706 // Handle a conditional branch.
707 BranchInst *BI = cast<BranchInst>(I);
708 MachineBasicBlock *TrueMBB = MBBMap[BI->getSuccessor(0)];
709 MachineBasicBlock *FalseMBB = MBBMap[BI->getSuccessor(1)];
711 // Fold the common case of a conditional branch with a comparison.
712 if (CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
713 if (CI->hasOneUse()) {
714 MVT VT = TLI.getValueType(CI->getOperand(0)->getType());
716 // Try to take advantage of fallthrough opportunities.
717 CmpInst::Predicate Predicate = CI->getPredicate();
718 if (MBB->isLayoutSuccessor(TrueMBB)) {
719 std::swap(TrueMBB, FalseMBB);
720 Predicate = CmpInst::getInversePredicate(Predicate);
723 bool SwapArgs; // false -> compare Op0, Op1. true -> compare Op1, Op0.
724 unsigned BranchOpc; // Opcode to jump on, e.g. "X86::JA"
727 case CmpInst::FCMP_OEQ:
728 std::swap(TrueMBB, FalseMBB);
729 Predicate = CmpInst::FCMP_UNE;
731 case CmpInst::FCMP_UNE: SwapArgs = false; BranchOpc = X86::JNE; break;
732 case CmpInst::FCMP_OGT: SwapArgs = false; BranchOpc = X86::JA; break;
733 case CmpInst::FCMP_OGE: SwapArgs = false; BranchOpc = X86::JAE; break;
734 case CmpInst::FCMP_OLT: SwapArgs = true; BranchOpc = X86::JA; break;
735 case CmpInst::FCMP_OLE: SwapArgs = true; BranchOpc = X86::JAE; break;
736 case CmpInst::FCMP_ONE: SwapArgs = false; BranchOpc = X86::JNE; break;
737 case CmpInst::FCMP_ORD: SwapArgs = false; BranchOpc = X86::JNP; break;
738 case CmpInst::FCMP_UNO: SwapArgs = false; BranchOpc = X86::JP; break;
739 case CmpInst::FCMP_UEQ: SwapArgs = false; BranchOpc = X86::JE; break;
740 case CmpInst::FCMP_UGT: SwapArgs = true; BranchOpc = X86::JB; break;
741 case CmpInst::FCMP_UGE: SwapArgs = true; BranchOpc = X86::JBE; break;
742 case CmpInst::FCMP_ULT: SwapArgs = false; BranchOpc = X86::JB; break;
743 case CmpInst::FCMP_ULE: SwapArgs = false; BranchOpc = X86::JBE; break;
745 case CmpInst::ICMP_EQ: SwapArgs = false; BranchOpc = X86::JE; break;
746 case CmpInst::ICMP_NE: SwapArgs = false; BranchOpc = X86::JNE; break;
747 case CmpInst::ICMP_UGT: SwapArgs = false; BranchOpc = X86::JA; break;
748 case CmpInst::ICMP_UGE: SwapArgs = false; BranchOpc = X86::JAE; break;
749 case CmpInst::ICMP_ULT: SwapArgs = false; BranchOpc = X86::JB; break;
750 case CmpInst::ICMP_ULE: SwapArgs = false; BranchOpc = X86::JBE; break;
751 case CmpInst::ICMP_SGT: SwapArgs = false; BranchOpc = X86::JG; break;
752 case CmpInst::ICMP_SGE: SwapArgs = false; BranchOpc = X86::JGE; break;
753 case CmpInst::ICMP_SLT: SwapArgs = false; BranchOpc = X86::JL; break;
754 case CmpInst::ICMP_SLE: SwapArgs = false; BranchOpc = X86::JLE; break;
759 Value *Op0 = CI->getOperand(0), *Op1 = CI->getOperand(1);
763 // Emit a compare of the LHS and RHS, setting the flags.
764 if (!X86FastEmitCompare(Op0, Op1, VT))
767 BuildMI(MBB, DL, TII.get(BranchOpc)).addMBB(TrueMBB);
769 if (Predicate == CmpInst::FCMP_UNE) {
770 // X86 requires a second branch to handle UNE (and OEQ,
771 // which is mapped to UNE above).
772 BuildMI(MBB, DL, TII.get(X86::JP)).addMBB(TrueMBB);
775 FastEmitBranch(FalseMBB);
776 MBB->addSuccessor(TrueMBB);
779 } else if (ExtractValueInst *EI =
780 dyn_cast<ExtractValueInst>(BI->getCondition())) {
781 // Check to see if the branch instruction is from an "arithmetic with
782 // overflow" intrinsic. The main way these intrinsics are used is:
784 // %t = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %v1, i32 %v2)
785 // %sum = extractvalue { i32, i1 } %t, 0
786 // %obit = extractvalue { i32, i1 } %t, 1
787 // br i1 %obit, label %overflow, label %normal
789 // The %sum and %obit are converted in an ADD and a SETO/SETB before
790 // reaching the branch. Therefore, we search backwards through the MBB
791 // looking for the SETO/SETB instruction. If an instruction modifies the
792 // EFLAGS register before we reach the SETO/SETB instruction, then we can't
793 // convert the branch into a JO/JB instruction.
794 if (IntrinsicInst *CI = dyn_cast<IntrinsicInst>(EI->getAggregateOperand())){
795 if (CI->getIntrinsicID() == Intrinsic::sadd_with_overflow ||
796 CI->getIntrinsicID() == Intrinsic::uadd_with_overflow) {
797 const MachineInstr *SetMI = 0;
798 unsigned Reg = lookUpRegForValue(EI);
800 for (MachineBasicBlock::const_reverse_iterator
801 RI = MBB->rbegin(), RE = MBB->rend(); RI != RE; ++RI) {
802 const MachineInstr &MI = *RI;
804 if (MI.modifiesRegister(Reg)) {
805 unsigned Src, Dst, SrcSR, DstSR;
807 if (getInstrInfo()->isMoveInstr(MI, Src, Dst, SrcSR, DstSR)) {
816 const TargetInstrDesc &TID = MI.getDesc();
817 if (TID.hasUnmodeledSideEffects() ||
818 TID.hasImplicitDefOfPhysReg(X86::EFLAGS))
823 unsigned OpCode = SetMI->getOpcode();
825 if (OpCode == X86::SETOr || OpCode == X86::SETBr) {
826 BuildMI(MBB, DL, TII.get(OpCode == X86::SETOr ? X86::JO : X86::JB))
828 FastEmitBranch(FalseMBB);
829 MBB->addSuccessor(TrueMBB);
837 // Otherwise do a clumsy setcc and re-test it.
838 unsigned OpReg = getRegForValue(BI->getCondition());
839 if (OpReg == 0) return false;
841 BuildMI(MBB, DL, TII.get(X86::TEST8rr)).addReg(OpReg).addReg(OpReg);
842 BuildMI(MBB, DL, TII.get(X86::JNE)).addMBB(TrueMBB);
843 FastEmitBranch(FalseMBB);
844 MBB->addSuccessor(TrueMBB);
848 bool X86FastISel::X86SelectShift(Instruction *I) {
849 unsigned CReg = 0, OpReg = 0, OpImm = 0;
850 const TargetRegisterClass *RC = NULL;
851 if (I->getType() == Type::Int8Ty) {
853 RC = &X86::GR8RegClass;
854 switch (I->getOpcode()) {
855 case Instruction::LShr: OpReg = X86::SHR8rCL; OpImm = X86::SHR8ri; break;
856 case Instruction::AShr: OpReg = X86::SAR8rCL; OpImm = X86::SAR8ri; break;
857 case Instruction::Shl: OpReg = X86::SHL8rCL; OpImm = X86::SHL8ri; break;
858 default: return false;
860 } else if (I->getType() == Type::Int16Ty) {
862 RC = &X86::GR16RegClass;
863 switch (I->getOpcode()) {
864 case Instruction::LShr: OpReg = X86::SHR16rCL; OpImm = X86::SHR16ri; break;
865 case Instruction::AShr: OpReg = X86::SAR16rCL; OpImm = X86::SAR16ri; break;
866 case Instruction::Shl: OpReg = X86::SHL16rCL; OpImm = X86::SHL16ri; break;
867 default: return false;
869 } else if (I->getType() == Type::Int32Ty) {
871 RC = &X86::GR32RegClass;
872 switch (I->getOpcode()) {
873 case Instruction::LShr: OpReg = X86::SHR32rCL; OpImm = X86::SHR32ri; break;
874 case Instruction::AShr: OpReg = X86::SAR32rCL; OpImm = X86::SAR32ri; break;
875 case Instruction::Shl: OpReg = X86::SHL32rCL; OpImm = X86::SHL32ri; break;
876 default: return false;
878 } else if (I->getType() == Type::Int64Ty) {
880 RC = &X86::GR64RegClass;
881 switch (I->getOpcode()) {
882 case Instruction::LShr: OpReg = X86::SHR64rCL; OpImm = X86::SHR64ri; break;
883 case Instruction::AShr: OpReg = X86::SAR64rCL; OpImm = X86::SAR64ri; break;
884 case Instruction::Shl: OpReg = X86::SHL64rCL; OpImm = X86::SHL64ri; break;
885 default: return false;
891 MVT VT = TLI.getValueType(I->getType(), /*HandleUnknown=*/true);
892 if (VT == MVT::Other || !isTypeLegal(I->getType(), VT))
895 unsigned Op0Reg = getRegForValue(I->getOperand(0));
896 if (Op0Reg == 0) return false;
898 // Fold immediate in shl(x,3).
899 if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) {
900 unsigned ResultReg = createResultReg(RC);
901 BuildMI(MBB, DL, TII.get(OpImm),
902 ResultReg).addReg(Op0Reg).addImm(CI->getZExtValue() & 0xff);
903 UpdateValueMap(I, ResultReg);
907 unsigned Op1Reg = getRegForValue(I->getOperand(1));
908 if (Op1Reg == 0) return false;
909 TII.copyRegToReg(*MBB, MBB->end(), CReg, Op1Reg, RC, RC);
911 // The shift instruction uses X86::CL. If we defined a super-register
912 // of X86::CL, emit an EXTRACT_SUBREG to precisely describe what
915 BuildMI(MBB, DL, TII.get(TargetInstrInfo::EXTRACT_SUBREG), X86::CL)
916 .addReg(CReg).addImm(X86::SUBREG_8BIT);
918 unsigned ResultReg = createResultReg(RC);
919 BuildMI(MBB, DL, TII.get(OpReg), ResultReg).addReg(Op0Reg);
920 UpdateValueMap(I, ResultReg);
924 bool X86FastISel::X86SelectSelect(Instruction *I) {
925 MVT VT = TLI.getValueType(I->getType(), /*HandleUnknown=*/true);
926 if (VT == MVT::Other || !isTypeLegal(I->getType(), VT))
930 const TargetRegisterClass *RC = NULL;
931 if (VT.getSimpleVT() == MVT::i16) {
932 Opc = X86::CMOVE16rr;
933 RC = &X86::GR16RegClass;
934 } else if (VT.getSimpleVT() == MVT::i32) {
935 Opc = X86::CMOVE32rr;
936 RC = &X86::GR32RegClass;
937 } else if (VT.getSimpleVT() == MVT::i64) {
938 Opc = X86::CMOVE64rr;
939 RC = &X86::GR64RegClass;
944 unsigned Op0Reg = getRegForValue(I->getOperand(0));
945 if (Op0Reg == 0) return false;
946 unsigned Op1Reg = getRegForValue(I->getOperand(1));
947 if (Op1Reg == 0) return false;
948 unsigned Op2Reg = getRegForValue(I->getOperand(2));
949 if (Op2Reg == 0) return false;
951 BuildMI(MBB, DL, TII.get(X86::TEST8rr)).addReg(Op0Reg).addReg(Op0Reg);
952 unsigned ResultReg = createResultReg(RC);
953 BuildMI(MBB, DL, TII.get(Opc), ResultReg).addReg(Op1Reg).addReg(Op2Reg);
954 UpdateValueMap(I, ResultReg);
958 bool X86FastISel::X86SelectFPExt(Instruction *I) {
959 // fpext from float to double.
960 if (Subtarget->hasSSE2() && I->getType() == Type::DoubleTy) {
961 Value *V = I->getOperand(0);
962 if (V->getType() == Type::FloatTy) {
963 unsigned OpReg = getRegForValue(V);
964 if (OpReg == 0) return false;
965 unsigned ResultReg = createResultReg(X86::FR64RegisterClass);
966 BuildMI(MBB, DL, TII.get(X86::CVTSS2SDrr), ResultReg).addReg(OpReg);
967 UpdateValueMap(I, ResultReg);
975 bool X86FastISel::X86SelectFPTrunc(Instruction *I) {
976 if (Subtarget->hasSSE2()) {
977 if (I->getType() == Type::FloatTy) {
978 Value *V = I->getOperand(0);
979 if (V->getType() == Type::DoubleTy) {
980 unsigned OpReg = getRegForValue(V);
981 if (OpReg == 0) return false;
982 unsigned ResultReg = createResultReg(X86::FR32RegisterClass);
983 BuildMI(MBB, DL, TII.get(X86::CVTSD2SSrr), ResultReg).addReg(OpReg);
984 UpdateValueMap(I, ResultReg);
993 bool X86FastISel::X86SelectTrunc(Instruction *I) {
994 if (Subtarget->is64Bit())
995 // All other cases should be handled by the tblgen generated code.
997 MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
998 MVT DstVT = TLI.getValueType(I->getType());
1000 // This code only handles truncation to byte right now.
1001 if (DstVT != MVT::i8 && DstVT != MVT::i1)
1002 // All other cases should be handled by the tblgen generated code.
1004 if (SrcVT != MVT::i16 && SrcVT != MVT::i32)
1005 // All other cases should be handled by the tblgen generated code.
1008 unsigned InputReg = getRegForValue(I->getOperand(0));
1010 // Unhandled operand. Halt "fast" selection and bail.
1013 // First issue a copy to GR16_ABCD or GR32_ABCD.
1014 unsigned CopyOpc = (SrcVT == MVT::i16) ? X86::MOV16rr : X86::MOV32rr;
1015 const TargetRegisterClass *CopyRC = (SrcVT == MVT::i16)
1016 ? X86::GR16_ABCDRegisterClass : X86::GR32_ABCDRegisterClass;
1017 unsigned CopyReg = createResultReg(CopyRC);
1018 BuildMI(MBB, DL, TII.get(CopyOpc), CopyReg).addReg(InputReg);
1020 // Then issue an extract_subreg.
1021 unsigned ResultReg = FastEmitInst_extractsubreg(MVT::i8,
1022 CopyReg, X86::SUBREG_8BIT);
1026 UpdateValueMap(I, ResultReg);
1030 bool X86FastISel::X86SelectExtractValue(Instruction *I) {
1031 ExtractValueInst *EI = cast<ExtractValueInst>(I);
1032 Value *Agg = EI->getAggregateOperand();
1034 if (IntrinsicInst *CI = dyn_cast<IntrinsicInst>(Agg)) {
1035 switch (CI->getIntrinsicID()) {
1037 case Intrinsic::sadd_with_overflow:
1038 case Intrinsic::uadd_with_overflow:
1039 // Cheat a little. We know that the registers for "add" and "seto" are
1040 // allocated sequentially. However, we only keep track of the register
1041 // for "add" in the value map. Use extractvalue's index to get the
1042 // correct register for "seto".
1043 UpdateValueMap(I, lookUpRegForValue(Agg) + *EI->idx_begin());
1051 bool X86FastISel::X86VisitIntrinsicCall(IntrinsicInst &I) {
1052 // FIXME: Handle more intrinsics.
1053 switch (I.getIntrinsicID()) {
1054 default: return false;
1055 case Intrinsic::sadd_with_overflow:
1056 case Intrinsic::uadd_with_overflow: {
1057 // Replace "add with overflow" intrinsics with an "add" instruction followed
1058 // by a seto/setc instruction. Later on, when the "extractvalue"
1059 // instructions are encountered, we use the fact that two registers were
1060 // created sequentially to get the correct registers for the "sum" and the
1062 const Function *Callee = I.getCalledFunction();
1064 cast<StructType>(Callee->getReturnType())->getTypeAtIndex(unsigned(0));
1067 if (!isTypeLegal(RetTy, VT))
1070 Value *Op1 = I.getOperand(1);
1071 Value *Op2 = I.getOperand(2);
1072 unsigned Reg1 = getRegForValue(Op1);
1073 unsigned Reg2 = getRegForValue(Op2);
1075 if (Reg1 == 0 || Reg2 == 0)
1076 // FIXME: Handle values *not* in registers.
1082 else if (VT == MVT::i64)
1087 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
1088 BuildMI(MBB, DL, TII.get(OpC), ResultReg).addReg(Reg1).addReg(Reg2);
1089 unsigned DestReg1 = UpdateValueMap(&I, ResultReg);
1091 // If the add with overflow is an intra-block value then we just want to
1092 // create temporaries for it like normal. If it is a cross-block value then
1093 // UpdateValueMap will return the cross-block register used. Since we
1094 // *really* want the value to be live in the register pair known by
1095 // UpdateValueMap, we have to use DestReg1+1 as the destination register in
1096 // the cross block case. In the non-cross-block case, we should just make
1097 // another register for the value.
1098 if (DestReg1 != ResultReg)
1099 ResultReg = DestReg1+1;
1101 ResultReg = createResultReg(TLI.getRegClassFor(MVT::i8));
1103 unsigned Opc = X86::SETBr;
1104 if (I.getIntrinsicID() == Intrinsic::sadd_with_overflow)
1106 BuildMI(MBB, DL, TII.get(Opc), ResultReg);
1112 bool X86FastISel::X86SelectCall(Instruction *I) {
1113 CallInst *CI = cast<CallInst>(I);
1114 Value *Callee = I->getOperand(0);
1116 // Can't handle inline asm yet.
1117 if (isa<InlineAsm>(Callee))
1120 // Handle intrinsic calls.
1121 if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(CI))
1122 return X86VisitIntrinsicCall(*II);
1124 // Handle only C and fastcc calling conventions for now.
1126 unsigned CC = CS.getCallingConv();
1127 if (CC != CallingConv::C &&
1128 CC != CallingConv::Fast &&
1129 CC != CallingConv::X86_FastCall)
1132 // On X86, -tailcallopt changes the fastcc ABI. FastISel doesn't
1133 // handle this for now.
1134 if (CC == CallingConv::Fast && PerformTailCallOpt)
1137 // Let SDISel handle vararg functions.
1138 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
1139 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
1140 if (FTy->isVarArg())
1143 // Handle *simple* calls for now.
1144 const Type *RetTy = CS.getType();
1146 if (RetTy == Type::VoidTy)
1147 RetVT = MVT::isVoid;
1148 else if (!isTypeLegal(RetTy, RetVT, true))
1151 // Materialize callee address in a register. FIXME: GV address can be
1152 // handled with a CALLpcrel32 instead.
1153 X86AddressMode CalleeAM;
1154 if (!X86SelectAddress(Callee, CalleeAM, true))
1156 unsigned CalleeOp = 0;
1157 GlobalValue *GV = 0;
1158 if (CalleeAM.GV != 0) {
1160 } else if (CalleeAM.Base.Reg != 0) {
1161 CalleeOp = CalleeAM.Base.Reg;
1165 // Allow calls which produce i1 results.
1166 bool AndToI1 = false;
1167 if (RetVT == MVT::i1) {
1172 // Deal with call operands first.
1173 SmallVector<Value*, 8> ArgVals;
1174 SmallVector<unsigned, 8> Args;
1175 SmallVector<MVT, 8> ArgVTs;
1176 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
1177 Args.reserve(CS.arg_size());
1178 ArgVals.reserve(CS.arg_size());
1179 ArgVTs.reserve(CS.arg_size());
1180 ArgFlags.reserve(CS.arg_size());
1181 for (CallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
1183 unsigned Arg = getRegForValue(*i);
1186 ISD::ArgFlagsTy Flags;
1187 unsigned AttrInd = i - CS.arg_begin() + 1;
1188 if (CS.paramHasAttr(AttrInd, Attribute::SExt))
1190 if (CS.paramHasAttr(AttrInd, Attribute::ZExt))
1193 // FIXME: Only handle *easy* calls for now.
1194 if (CS.paramHasAttr(AttrInd, Attribute::InReg) ||
1195 CS.paramHasAttr(AttrInd, Attribute::StructRet) ||
1196 CS.paramHasAttr(AttrInd, Attribute::Nest) ||
1197 CS.paramHasAttr(AttrInd, Attribute::ByVal))
1200 const Type *ArgTy = (*i)->getType();
1202 if (!isTypeLegal(ArgTy, ArgVT))
1204 unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
1205 Flags.setOrigAlign(OriginalAlignment);
1207 Args.push_back(Arg);
1208 ArgVals.push_back(*i);
1209 ArgVTs.push_back(ArgVT);
1210 ArgFlags.push_back(Flags);
1213 // Analyze operands of the call, assigning locations to each operand.
1214 SmallVector<CCValAssign, 16> ArgLocs;
1215 CCState CCInfo(CC, false, TM, ArgLocs);
1216 CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, CCAssignFnForCall(CC));
1218 // Get a count of how many bytes are to be pushed on the stack.
1219 unsigned NumBytes = CCInfo.getNextStackOffset();
1221 // Issue CALLSEQ_START
1222 unsigned AdjStackDown = TM.getRegisterInfo()->getCallFrameSetupOpcode();
1223 BuildMI(MBB, DL, TII.get(AdjStackDown)).addImm(NumBytes);
1225 // Process argument: walk the register/memloc assignments, inserting
1227 SmallVector<unsigned, 4> RegArgs;
1228 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1229 CCValAssign &VA = ArgLocs[i];
1230 unsigned Arg = Args[VA.getValNo()];
1231 MVT ArgVT = ArgVTs[VA.getValNo()];
1233 // Promote the value if needed.
1234 switch (VA.getLocInfo()) {
1235 default: assert(0 && "Unknown loc info!");
1236 case CCValAssign::Full: break;
1237 case CCValAssign::SExt: {
1238 bool Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(),
1240 assert(Emitted && "Failed to emit a sext!"); Emitted=Emitted;
1242 ArgVT = VA.getLocVT();
1245 case CCValAssign::ZExt: {
1246 bool Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(),
1248 assert(Emitted && "Failed to emit a zext!"); Emitted=Emitted;
1250 ArgVT = VA.getLocVT();
1253 case CCValAssign::AExt: {
1254 bool Emitted = X86FastEmitExtend(ISD::ANY_EXTEND, VA.getLocVT(),
1257 Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(),
1260 Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(),
1263 assert(Emitted && "Failed to emit a aext!"); Emitted=Emitted;
1264 ArgVT = VA.getLocVT();
1269 if (VA.isRegLoc()) {
1270 TargetRegisterClass* RC = TLI.getRegClassFor(ArgVT);
1271 bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), VA.getLocReg(),
1273 assert(Emitted && "Failed to emit a copy instruction!"); Emitted=Emitted;
1275 RegArgs.push_back(VA.getLocReg());
1277 unsigned LocMemOffset = VA.getLocMemOffset();
1279 AM.Base.Reg = StackPtr;
1280 AM.Disp = LocMemOffset;
1281 Value *ArgVal = ArgVals[VA.getValNo()];
1283 // If this is a really simple value, emit this with the Value* version of
1284 // X86FastEmitStore. If it isn't simple, we don't want to do this, as it
1285 // can cause us to reevaluate the argument.
1286 if (isa<ConstantInt>(ArgVal) || isa<ConstantPointerNull>(ArgVal))
1287 X86FastEmitStore(ArgVT, ArgVal, AM);
1289 X86FastEmitStore(ArgVT, Arg, AM);
1293 // ELF / PIC requires GOT in the EBX register before function calls via PLT
1295 if (!Subtarget->is64Bit() &&
1296 TM.getRelocationModel() == Reloc::PIC_ &&
1297 Subtarget->isPICStyleGOT()) {
1298 TargetRegisterClass *RC = X86::GR32RegisterClass;
1299 unsigned Base = getInstrInfo()->getGlobalBaseReg(&MF);
1300 bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), X86::EBX, Base, RC, RC);
1301 assert(Emitted && "Failed to emit a copy instruction!"); Emitted=Emitted;
1306 unsigned CallOpc = CalleeOp
1307 ? (Subtarget->is64Bit() ? X86::CALL64r : X86::CALL32r)
1308 : (Subtarget->is64Bit() ? X86::CALL64pcrel32 : X86::CALLpcrel32);
1309 MachineInstrBuilder MIB = CalleeOp
1310 ? BuildMI(MBB, DL, TII.get(CallOpc)).addReg(CalleeOp)
1311 : BuildMI(MBB, DL, TII.get(CallOpc)).addGlobalAddress(GV);
1313 // Add an implicit use GOT pointer in EBX.
1314 if (!Subtarget->is64Bit() &&
1315 TM.getRelocationModel() == Reloc::PIC_ &&
1316 Subtarget->isPICStyleGOT())
1317 MIB.addReg(X86::EBX);
1319 // Add implicit physical register uses to the call.
1320 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
1321 MIB.addReg(RegArgs[i]);
1323 // Issue CALLSEQ_END
1324 unsigned AdjStackUp = TM.getRegisterInfo()->getCallFrameDestroyOpcode();
1325 BuildMI(MBB, DL, TII.get(AdjStackUp)).addImm(NumBytes).addImm(0);
1327 // Now handle call return value (if any).
1328 if (RetVT.getSimpleVT() != MVT::isVoid) {
1329 SmallVector<CCValAssign, 16> RVLocs;
1330 CCState CCInfo(CC, false, TM, RVLocs);
1331 CCInfo.AnalyzeCallResult(RetVT, RetCC_X86);
1333 // Copy all of the result registers out of their specified physreg.
1334 assert(RVLocs.size() == 1 && "Can't handle multi-value calls!");
1335 MVT CopyVT = RVLocs[0].getValVT();
1336 TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT);
1337 TargetRegisterClass *SrcRC = DstRC;
1339 // If this is a call to a function that returns an fp value on the x87 fp
1340 // stack, but where we prefer to use the value in xmm registers, copy it
1341 // out as F80 and use a truncate to move it from fp stack reg to xmm reg.
1342 if ((RVLocs[0].getLocReg() == X86::ST0 ||
1343 RVLocs[0].getLocReg() == X86::ST1) &&
1344 isScalarFPTypeInSSEReg(RVLocs[0].getValVT())) {
1346 SrcRC = X86::RSTRegisterClass;
1347 DstRC = X86::RFP80RegisterClass;
1350 unsigned ResultReg = createResultReg(DstRC);
1351 bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
1352 RVLocs[0].getLocReg(), DstRC, SrcRC);
1353 assert(Emitted && "Failed to emit a copy instruction!"); Emitted=Emitted;
1355 if (CopyVT != RVLocs[0].getValVT()) {
1356 // Round the F80 the right size, which also moves to the appropriate xmm
1357 // register. This is accomplished by storing the F80 value in memory and
1358 // then loading it back. Ewww...
1359 MVT ResVT = RVLocs[0].getValVT();
1360 unsigned Opc = ResVT == MVT::f32 ? X86::ST_Fp80m32 : X86::ST_Fp80m64;
1361 unsigned MemSize = ResVT.getSizeInBits()/8;
1362 int FI = MFI.CreateStackObject(MemSize, MemSize);
1363 addFrameReference(BuildMI(MBB, DL, TII.get(Opc)), FI).addReg(ResultReg);
1364 DstRC = ResVT == MVT::f32
1365 ? X86::FR32RegisterClass : X86::FR64RegisterClass;
1366 Opc = ResVT == MVT::f32 ? X86::MOVSSrm : X86::MOVSDrm;
1367 ResultReg = createResultReg(DstRC);
1368 addFrameReference(BuildMI(MBB, DL, TII.get(Opc), ResultReg), FI);
1372 // Mask out all but lowest bit for some call which produces an i1.
1373 unsigned AndResult = createResultReg(X86::GR8RegisterClass);
1375 TII.get(X86::AND8ri), AndResult).addReg(ResultReg).addImm(1);
1376 ResultReg = AndResult;
1379 UpdateValueMap(I, ResultReg);
1387 X86FastISel::TargetSelectInstruction(Instruction *I) {
1388 switch (I->getOpcode()) {
1390 case Instruction::Load:
1391 return X86SelectLoad(I);
1392 case Instruction::Store:
1393 return X86SelectStore(I);
1394 case Instruction::ICmp:
1395 case Instruction::FCmp:
1396 return X86SelectCmp(I);
1397 case Instruction::ZExt:
1398 return X86SelectZExt(I);
1399 case Instruction::Br:
1400 return X86SelectBranch(I);
1401 case Instruction::Call:
1402 return X86SelectCall(I);
1403 case Instruction::LShr:
1404 case Instruction::AShr:
1405 case Instruction::Shl:
1406 return X86SelectShift(I);
1407 case Instruction::Select:
1408 return X86SelectSelect(I);
1409 case Instruction::Trunc:
1410 return X86SelectTrunc(I);
1411 case Instruction::FPExt:
1412 return X86SelectFPExt(I);
1413 case Instruction::FPTrunc:
1414 return X86SelectFPTrunc(I);
1415 case Instruction::ExtractValue:
1416 return X86SelectExtractValue(I);
1417 case Instruction::IntToPtr: // Deliberate fall-through.
1418 case Instruction::PtrToInt: {
1419 MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
1420 MVT DstVT = TLI.getValueType(I->getType());
1421 if (DstVT.bitsGT(SrcVT))
1422 return X86SelectZExt(I);
1423 if (DstVT.bitsLT(SrcVT))
1424 return X86SelectTrunc(I);
1425 unsigned Reg = getRegForValue(I->getOperand(0));
1426 if (Reg == 0) return false;
1427 UpdateValueMap(I, Reg);
1435 unsigned X86FastISel::TargetMaterializeConstant(Constant *C) {
1437 if (!isTypeLegal(C->getType(), VT))
1440 // Get opcode and regclass of the output for the given load instruction.
1442 const TargetRegisterClass *RC = NULL;
1443 switch (VT.getSimpleVT()) {
1444 default: return false;
1447 RC = X86::GR8RegisterClass;
1451 RC = X86::GR16RegisterClass;
1455 RC = X86::GR32RegisterClass;
1458 // Must be in x86-64 mode.
1460 RC = X86::GR64RegisterClass;
1463 if (Subtarget->hasSSE1()) {
1465 RC = X86::FR32RegisterClass;
1467 Opc = X86::LD_Fp32m;
1468 RC = X86::RFP32RegisterClass;
1472 if (Subtarget->hasSSE2()) {
1474 RC = X86::FR64RegisterClass;
1476 Opc = X86::LD_Fp64m;
1477 RC = X86::RFP64RegisterClass;
1481 // No f80 support yet.
1485 // Materialize addresses with LEA instructions.
1486 if (isa<GlobalValue>(C)) {
1488 if (X86SelectAddress(C, AM, false)) {
1489 if (TLI.getPointerTy() == MVT::i32)
1493 unsigned ResultReg = createResultReg(RC);
1494 addLeaAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), AM);
1500 // MachineConstantPool wants an explicit alignment.
1501 unsigned Align = TD.getPrefTypeAlignment(C->getType());
1503 // Alignment of vector types. FIXME!
1504 Align = TD.getTypeAllocSize(C->getType());
1507 // x86-32 PIC requires a PIC base register for constant pools.
1508 unsigned PICBase = 0;
1509 unsigned char OpFlag = 0;
1510 if (TM.getRelocationModel() == Reloc::PIC_) {
1511 if (Subtarget->isPICStyleStub()) {
1512 OpFlag = X86II::MO_PIC_BASE_OFFSET;
1513 PICBase = getInstrInfo()->getGlobalBaseReg(&MF);
1514 } else if (Subtarget->isPICStyleGOT()) {
1515 OpFlag = X86II::MO_GOTOFF;
1516 PICBase = getInstrInfo()->getGlobalBaseReg(&MF);
1517 } else if (Subtarget->isPICStyleRIPRel() &&
1518 TM.getCodeModel() == CodeModel::Small)
1522 // Create the load from the constant pool.
1523 unsigned MCPOffset = MCP.getConstantPoolIndex(C, Align);
1524 unsigned ResultReg = createResultReg(RC);
1525 addConstantPoolReference(BuildMI(MBB, DL, TII.get(Opc), ResultReg),
1526 MCPOffset, PICBase, OpFlag);
1531 unsigned X86FastISel::TargetMaterializeAlloca(AllocaInst *C) {
1532 // Fail on dynamic allocas. At this point, getRegForValue has already
1533 // checked its CSE maps, so if we're here trying to handle a dynamic
1534 // alloca, we're not going to succeed. X86SelectAddress has a
1535 // check for dynamic allocas, because it's called directly from
1536 // various places, but TargetMaterializeAlloca also needs a check
1537 // in order to avoid recursion between getRegForValue,
1538 // X86SelectAddrss, and TargetMaterializeAlloca.
1539 if (!StaticAllocaMap.count(C))
1543 if (!X86SelectAddress(C, AM, false))
1545 unsigned Opc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
1546 TargetRegisterClass* RC = TLI.getRegClassFor(TLI.getPointerTy());
1547 unsigned ResultReg = createResultReg(RC);
1548 addLeaAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), AM);
1553 llvm::FastISel *X86::createFastISel(MachineFunction &mf,
1554 MachineModuleInfo *mmi,
1556 DenseMap<const Value *, unsigned> &vm,
1557 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
1558 DenseMap<const AllocaInst *, int> &am
1560 , SmallSet<Instruction*, 8> &cil
1563 return new X86FastISel(mf, mmi, dw, vm, bm, am