1 //===-- X86FastISel.cpp - X86 FastISel implementation ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the X86-specific support for the FastISel class. Much
11 // of the target-specific code is generated by tablegen in the file
12 // X86GenFastISel.inc, which is #included here.
14 //===----------------------------------------------------------------------===//
17 #include "X86InstrBuilder.h"
18 #include "X86ISelLowering.h"
19 #include "X86RegisterInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/DerivedTypes.h"
24 #include "llvm/Instructions.h"
25 #include "llvm/Intrinsics.h"
26 #include "llvm/CodeGen/FastISel.h"
27 #include "llvm/CodeGen/MachineConstantPool.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/Support/CallSite.h"
31 #include "llvm/Support/GetElementPtrTypeIterator.h"
35 class X86FastISel : public FastISel {
36 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
37 /// make the right decision when generating code for different targets.
38 const X86Subtarget *Subtarget;
40 /// StackPtr - Register used as the stack pointer.
44 /// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87
45 /// floating point ops.
46 /// When SSE is available, use it for f32 operations.
47 /// When SSE2 is available, use it for f64 operations.
52 explicit X86FastISel(MachineFunction &mf,
53 MachineModuleInfo *mmi,
54 DenseMap<const Value *, unsigned> &vm,
55 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
56 DenseMap<const AllocaInst *, int> &am
58 , SmallSet<Instruction*, 8> &cil
61 : FastISel(mf, mmi, vm, bm, am
66 Subtarget = &TM.getSubtarget<X86Subtarget>();
67 StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
68 X86ScalarSSEf64 = Subtarget->hasSSE2();
69 X86ScalarSSEf32 = Subtarget->hasSSE1();
72 virtual bool TargetSelectInstruction(Instruction *I);
74 #include "X86GenFastISel.inc"
77 bool X86FastEmitCompare(Value *LHS, Value *RHS, MVT VT);
79 bool X86FastEmitLoad(MVT VT, const X86AddressMode &AM, unsigned &RR);
81 bool X86FastEmitStore(MVT VT, Value *Val,
82 const X86AddressMode &AM);
83 bool X86FastEmitStore(MVT VT, unsigned Val,
84 const X86AddressMode &AM);
86 bool X86FastEmitExtend(ISD::NodeType Opc, MVT DstVT, unsigned Src, MVT SrcVT,
89 bool X86SelectAddress(Value *V, X86AddressMode &AM, bool isCall);
91 bool X86SelectLoad(Instruction *I);
93 bool X86SelectStore(Instruction *I);
95 bool X86SelectCmp(Instruction *I);
97 bool X86SelectZExt(Instruction *I);
99 bool X86SelectBranch(Instruction *I);
101 bool X86SelectShift(Instruction *I);
103 bool X86SelectSelect(Instruction *I);
105 bool X86SelectTrunc(Instruction *I);
107 bool X86SelectFPExt(Instruction *I);
108 bool X86SelectFPTrunc(Instruction *I);
110 bool X86SelectExtractValue(Instruction *I);
112 bool X86VisitIntrinsicCall(CallInst &I, unsigned Intrinsic);
113 bool X86SelectCall(Instruction *I);
115 CCAssignFn *CCAssignFnForCall(unsigned CC, bool isTailCall = false);
117 const X86InstrInfo *getInstrInfo() const {
118 return getTargetMachine()->getInstrInfo();
120 const X86TargetMachine *getTargetMachine() const {
121 return static_cast<const X86TargetMachine *>(&TM);
124 unsigned TargetMaterializeConstant(Constant *C);
126 unsigned TargetMaterializeAlloca(AllocaInst *C);
128 /// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is
129 /// computed in an SSE register, not on the X87 floating point stack.
130 bool isScalarFPTypeInSSEReg(MVT VT) const {
131 return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
132 (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
135 bool isTypeLegal(const Type *Ty, MVT &VT, bool AllowI1 = false);
138 bool X86FastISel::isTypeLegal(const Type *Ty, MVT &VT, bool AllowI1) {
139 VT = TLI.getValueType(Ty, /*HandleUnknown=*/true);
140 if (VT == MVT::Other || !VT.isSimple())
141 // Unhandled type. Halt "fast" selection and bail.
144 // For now, require SSE/SSE2 for performing floating-point operations,
145 // since x87 requires additional work.
146 if (VT == MVT::f64 && !X86ScalarSSEf64)
148 if (VT == MVT::f32 && !X86ScalarSSEf32)
150 // Similarly, no f80 support yet.
153 // We only handle legal types. For example, on x86-32 the instruction
154 // selector contains all of the 64-bit instructions from x86-64,
155 // under the assumption that i64 won't be used if the target doesn't
157 return (AllowI1 && VT == MVT::i1) || TLI.isTypeLegal(VT);
160 #include "X86GenCallingConv.inc"
162 /// CCAssignFnForCall - Selects the correct CCAssignFn for a given calling
164 CCAssignFn *X86FastISel::CCAssignFnForCall(unsigned CC, bool isTaillCall) {
165 if (Subtarget->is64Bit()) {
166 if (Subtarget->isTargetWin64())
167 return CC_X86_Win64_C;
168 else if (CC == CallingConv::Fast && isTaillCall)
169 return CC_X86_64_TailCall;
174 if (CC == CallingConv::X86_FastCall)
175 return CC_X86_32_FastCall;
176 else if (CC == CallingConv::Fast)
177 return CC_X86_32_FastCC;
182 /// X86FastEmitLoad - Emit a machine instruction to load a value of type VT.
183 /// The address is either pre-computed, i.e. Ptr, or a GlobalAddress, i.e. GV.
184 /// Return true and the result register by reference if it is possible.
185 bool X86FastISel::X86FastEmitLoad(MVT VT, const X86AddressMode &AM,
186 unsigned &ResultReg) {
187 // Get opcode and regclass of the output for the given load instruction.
189 const TargetRegisterClass *RC = NULL;
190 switch (VT.getSimpleVT()) {
191 default: return false;
194 RC = X86::GR8RegisterClass;
198 RC = X86::GR16RegisterClass;
202 RC = X86::GR32RegisterClass;
205 // Must be in x86-64 mode.
207 RC = X86::GR64RegisterClass;
210 if (Subtarget->hasSSE1()) {
212 RC = X86::FR32RegisterClass;
215 RC = X86::RFP32RegisterClass;
219 if (Subtarget->hasSSE2()) {
221 RC = X86::FR64RegisterClass;
224 RC = X86::RFP64RegisterClass;
228 // No f80 support yet.
232 ResultReg = createResultReg(RC);
233 addFullAddress(BuildMI(MBB, TII.get(Opc), ResultReg), AM);
237 /// X86FastEmitStore - Emit a machine instruction to store a value Val of
238 /// type VT. The address is either pre-computed, consisted of a base ptr, Ptr
239 /// and a displacement offset, or a GlobalAddress,
240 /// i.e. V. Return true if it is possible.
242 X86FastISel::X86FastEmitStore(MVT VT, unsigned Val,
243 const X86AddressMode &AM) {
244 // Get opcode and regclass of the output for the given store instruction.
246 switch (VT.getSimpleVT()) {
247 case MVT::f80: // No f80 support yet.
248 default: return false;
249 case MVT::i8: Opc = X86::MOV8mr; break;
250 case MVT::i16: Opc = X86::MOV16mr; break;
251 case MVT::i32: Opc = X86::MOV32mr; break;
252 case MVT::i64: Opc = X86::MOV64mr; break; // Must be in x86-64 mode.
254 Opc = Subtarget->hasSSE1() ? X86::MOVSSmr : X86::ST_Fp32m;
257 Opc = Subtarget->hasSSE2() ? X86::MOVSDmr : X86::ST_Fp64m;
261 addFullAddress(BuildMI(MBB, TII.get(Opc)), AM).addReg(Val);
265 bool X86FastISel::X86FastEmitStore(MVT VT, Value *Val,
266 const X86AddressMode &AM) {
267 // Handle 'null' like i32/i64 0.
268 if (isa<ConstantPointerNull>(Val))
269 Val = Constant::getNullValue(TD.getIntPtrType());
271 // If this is a store of a simple constant, fold the constant into the store.
272 if (ConstantInt *CI = dyn_cast<ConstantInt>(Val)) {
274 switch (VT.getSimpleVT()) {
276 case MVT::i8: Opc = X86::MOV8mi; break;
277 case MVT::i16: Opc = X86::MOV16mi; break;
278 case MVT::i32: Opc = X86::MOV32mi; break;
280 // Must be a 32-bit sign extended value.
281 if ((int)CI->getSExtValue() == CI->getSExtValue())
282 Opc = X86::MOV64mi32;
287 addFullAddress(BuildMI(MBB, TII.get(Opc)), AM).addImm(CI->getSExtValue());
292 unsigned ValReg = getRegForValue(Val);
296 return X86FastEmitStore(VT, ValReg, AM);
299 /// X86FastEmitExtend - Emit a machine instruction to extend a value Src of
300 /// type SrcVT to type DstVT using the specified extension opcode Opc (e.g.
301 /// ISD::SIGN_EXTEND).
302 bool X86FastISel::X86FastEmitExtend(ISD::NodeType Opc, MVT DstVT,
303 unsigned Src, MVT SrcVT,
304 unsigned &ResultReg) {
305 unsigned RR = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc, Src);
314 /// X86SelectAddress - Attempt to fill in an address from the given value.
316 bool X86FastISel::X86SelectAddress(Value *V, X86AddressMode &AM, bool isCall) {
318 unsigned Opcode = Instruction::UserOp1;
319 if (Instruction *I = dyn_cast<Instruction>(V)) {
320 Opcode = I->getOpcode();
322 } else if (ConstantExpr *C = dyn_cast<ConstantExpr>(V)) {
323 Opcode = C->getOpcode();
329 case Instruction::BitCast:
330 // Look past bitcasts.
331 return X86SelectAddress(U->getOperand(0), AM, isCall);
333 case Instruction::IntToPtr:
334 // Look past no-op inttoptrs.
335 if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
336 return X86SelectAddress(U->getOperand(0), AM, isCall);
339 case Instruction::PtrToInt:
340 // Look past no-op ptrtoints.
341 if (TLI.getValueType(U->getType()) == TLI.getPointerTy())
342 return X86SelectAddress(U->getOperand(0), AM, isCall);
345 case Instruction::Alloca: {
347 // Do static allocas.
348 const AllocaInst *A = cast<AllocaInst>(V);
349 DenseMap<const AllocaInst*, int>::iterator SI = StaticAllocaMap.find(A);
350 if (SI != StaticAllocaMap.end()) {
351 AM.BaseType = X86AddressMode::FrameIndexBase;
352 AM.Base.FrameIndex = SI->second;
358 case Instruction::Add: {
360 // Adds of constants are common and easy enough.
361 if (ConstantInt *CI = dyn_cast<ConstantInt>(U->getOperand(1))) {
362 uint64_t Disp = (int32_t)AM.Disp + (uint64_t)CI->getSExtValue();
363 // They have to fit in the 32-bit signed displacement field though.
365 AM.Disp = (uint32_t)Disp;
366 return X86SelectAddress(U->getOperand(0), AM, isCall);
372 case Instruction::GetElementPtr: {
374 // Pattern-match simple GEPs.
375 uint64_t Disp = (int32_t)AM.Disp;
376 unsigned IndexReg = AM.IndexReg;
377 unsigned Scale = AM.Scale;
378 gep_type_iterator GTI = gep_type_begin(U);
379 // Iterate through the indices, folding what we can. Constants can be
380 // folded, and one dynamic index can be handled, if the scale is supported.
381 for (User::op_iterator i = U->op_begin() + 1, e = U->op_end();
382 i != e; ++i, ++GTI) {
384 if (const StructType *STy = dyn_cast<StructType>(*GTI)) {
385 const StructLayout *SL = TD.getStructLayout(STy);
386 unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
387 Disp += SL->getElementOffset(Idx);
389 uint64_t S = TD.getABITypeSize(GTI.getIndexedType());
390 if (ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
391 // Constant-offset addressing.
392 Disp += CI->getSExtValue() * S;
393 } else if (IndexReg == 0 &&
395 !getTargetMachine()->symbolicAddressesAreRIPRel()) &&
396 (S == 1 || S == 2 || S == 4 || S == 8)) {
397 // Scaled-index addressing.
399 IndexReg = getRegForGEPIndex(Op);
404 goto unsupported_gep;
407 // Check for displacement overflow.
410 // Ok, the GEP indices were covered by constant-offset and scaled-index
411 // addressing. Update the address state and move on to examining the base.
412 AM.IndexReg = IndexReg;
414 AM.Disp = (uint32_t)Disp;
415 return X86SelectAddress(U->getOperand(0), AM, isCall);
417 // Ok, the GEP indices weren't all covered.
422 // Handle constant address.
423 if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
424 // Can't handle alternate code models yet.
425 if (TM.getCodeModel() != CodeModel::Default &&
426 TM.getCodeModel() != CodeModel::Small)
429 // RIP-relative addresses can't have additional register operands.
430 if (getTargetMachine()->symbolicAddressesAreRIPRel() &&
431 (AM.Base.Reg != 0 || AM.IndexReg != 0))
434 // Set up the basic address.
437 TM.getRelocationModel() == Reloc::PIC_ &&
438 !Subtarget->is64Bit())
439 AM.Base.Reg = getInstrInfo()->getGlobalBaseReg(&MF);
441 // Emit an extra load if the ABI requires it.
442 if (Subtarget->GVRequiresExtraLoad(GV, TM, isCall)) {
443 // Check to see if we've already materialized this
444 // value in a register in this block.
445 if (unsigned Reg = LocalValueMap[V]) {
450 // Issue load from stub if necessary.
452 const TargetRegisterClass *RC = NULL;
453 if (TLI.getPointerTy() == MVT::i32) {
455 RC = X86::GR32RegisterClass;
458 RC = X86::GR64RegisterClass;
461 X86AddressMode StubAM;
462 StubAM.Base.Reg = AM.Base.Reg;
464 unsigned ResultReg = createResultReg(RC);
465 addFullAddress(BuildMI(MBB, TII.get(Opc), ResultReg), StubAM);
467 // Now construct the final address. Note that the Disp, Scale,
468 // and Index values may already be set here.
469 AM.Base.Reg = ResultReg;
472 // Prevent loading GV stub multiple times in same MBB.
473 LocalValueMap[V] = AM.Base.Reg;
478 // If all else fails, try to materialize the value in a register.
479 if (!AM.GV || !getTargetMachine()->symbolicAddressesAreRIPRel()) {
480 if (AM.Base.Reg == 0) {
481 AM.Base.Reg = getRegForValue(V);
482 return AM.Base.Reg != 0;
484 if (AM.IndexReg == 0) {
485 assert(AM.Scale == 1 && "Scale with no index!");
486 AM.IndexReg = getRegForValue(V);
487 return AM.IndexReg != 0;
494 /// X86SelectStore - Select and emit code to implement store instructions.
495 bool X86FastISel::X86SelectStore(Instruction* I) {
497 if (!isTypeLegal(I->getOperand(0)->getType(), VT))
501 if (!X86SelectAddress(I->getOperand(1), AM, false))
504 return X86FastEmitStore(VT, I->getOperand(0), AM);
507 /// X86SelectLoad - Select and emit code to implement load instructions.
509 bool X86FastISel::X86SelectLoad(Instruction *I) {
511 if (!isTypeLegal(I->getType(), VT))
515 if (!X86SelectAddress(I->getOperand(0), AM, false))
518 unsigned ResultReg = 0;
519 if (X86FastEmitLoad(VT, AM, ResultReg)) {
520 UpdateValueMap(I, ResultReg);
526 static unsigned X86ChooseCmpOpcode(MVT VT) {
527 switch (VT.getSimpleVT()) {
529 case MVT::i8: return X86::CMP8rr;
530 case MVT::i16: return X86::CMP16rr;
531 case MVT::i32: return X86::CMP32rr;
532 case MVT::i64: return X86::CMP64rr;
533 case MVT::f32: return X86::UCOMISSrr;
534 case MVT::f64: return X86::UCOMISDrr;
538 /// X86ChooseCmpImmediateOpcode - If we have a comparison with RHS as the RHS
539 /// of the comparison, return an opcode that works for the compare (e.g.
540 /// CMP32ri) otherwise return 0.
541 static unsigned X86ChooseCmpImmediateOpcode(MVT VT, ConstantInt *RHSC) {
542 switch (VT.getSimpleVT()) {
543 // Otherwise, we can't fold the immediate into this comparison.
545 case MVT::i8: return X86::CMP8ri;
546 case MVT::i16: return X86::CMP16ri;
547 case MVT::i32: return X86::CMP32ri;
549 // 64-bit comparisons are only valid if the immediate fits in a 32-bit sext
551 if ((int)RHSC->getSExtValue() == RHSC->getSExtValue())
552 return X86::CMP64ri32;
557 bool X86FastISel::X86FastEmitCompare(Value *Op0, Value *Op1, MVT VT) {
558 unsigned Op0Reg = getRegForValue(Op0);
559 if (Op0Reg == 0) return false;
561 // Handle 'null' like i32/i64 0.
562 if (isa<ConstantPointerNull>(Op1))
563 Op1 = Constant::getNullValue(TD.getIntPtrType());
565 // We have two options: compare with register or immediate. If the RHS of
566 // the compare is an immediate that we can fold into this compare, use
567 // CMPri, otherwise use CMPrr.
568 if (ConstantInt *Op1C = dyn_cast<ConstantInt>(Op1)) {
569 if (unsigned CompareImmOpc = X86ChooseCmpImmediateOpcode(VT, Op1C)) {
570 BuildMI(MBB, TII.get(CompareImmOpc)).addReg(Op0Reg)
571 .addImm(Op1C->getSExtValue());
576 unsigned CompareOpc = X86ChooseCmpOpcode(VT);
577 if (CompareOpc == 0) return false;
579 unsigned Op1Reg = getRegForValue(Op1);
580 if (Op1Reg == 0) return false;
581 BuildMI(MBB, TII.get(CompareOpc)).addReg(Op0Reg).addReg(Op1Reg);
586 bool X86FastISel::X86SelectCmp(Instruction *I) {
587 CmpInst *CI = cast<CmpInst>(I);
590 if (!isTypeLegal(I->getOperand(0)->getType(), VT))
593 unsigned ResultReg = createResultReg(&X86::GR8RegClass);
595 bool SwapArgs; // false -> compare Op0, Op1. true -> compare Op1, Op0.
596 switch (CI->getPredicate()) {
597 case CmpInst::FCMP_OEQ: {
598 if (!X86FastEmitCompare(CI->getOperand(0), CI->getOperand(1), VT))
601 unsigned EReg = createResultReg(&X86::GR8RegClass);
602 unsigned NPReg = createResultReg(&X86::GR8RegClass);
603 BuildMI(MBB, TII.get(X86::SETEr), EReg);
604 BuildMI(MBB, TII.get(X86::SETNPr), NPReg);
605 BuildMI(MBB, TII.get(X86::AND8rr), ResultReg).addReg(NPReg).addReg(EReg);
606 UpdateValueMap(I, ResultReg);
609 case CmpInst::FCMP_UNE: {
610 if (!X86FastEmitCompare(CI->getOperand(0), CI->getOperand(1), VT))
613 unsigned NEReg = createResultReg(&X86::GR8RegClass);
614 unsigned PReg = createResultReg(&X86::GR8RegClass);
615 BuildMI(MBB, TII.get(X86::SETNEr), NEReg);
616 BuildMI(MBB, TII.get(X86::SETPr), PReg);
617 BuildMI(MBB, TII.get(X86::OR8rr), ResultReg).addReg(PReg).addReg(NEReg);
618 UpdateValueMap(I, ResultReg);
621 case CmpInst::FCMP_OGT: SwapArgs = false; SetCCOpc = X86::SETAr; break;
622 case CmpInst::FCMP_OGE: SwapArgs = false; SetCCOpc = X86::SETAEr; break;
623 case CmpInst::FCMP_OLT: SwapArgs = true; SetCCOpc = X86::SETAr; break;
624 case CmpInst::FCMP_OLE: SwapArgs = true; SetCCOpc = X86::SETAEr; break;
625 case CmpInst::FCMP_ONE: SwapArgs = false; SetCCOpc = X86::SETNEr; break;
626 case CmpInst::FCMP_ORD: SwapArgs = false; SetCCOpc = X86::SETNPr; break;
627 case CmpInst::FCMP_UNO: SwapArgs = false; SetCCOpc = X86::SETPr; break;
628 case CmpInst::FCMP_UEQ: SwapArgs = false; SetCCOpc = X86::SETEr; break;
629 case CmpInst::FCMP_UGT: SwapArgs = true; SetCCOpc = X86::SETBr; break;
630 case CmpInst::FCMP_UGE: SwapArgs = true; SetCCOpc = X86::SETBEr; break;
631 case CmpInst::FCMP_ULT: SwapArgs = false; SetCCOpc = X86::SETBr; break;
632 case CmpInst::FCMP_ULE: SwapArgs = false; SetCCOpc = X86::SETBEr; break;
634 case CmpInst::ICMP_EQ: SwapArgs = false; SetCCOpc = X86::SETEr; break;
635 case CmpInst::ICMP_NE: SwapArgs = false; SetCCOpc = X86::SETNEr; break;
636 case CmpInst::ICMP_UGT: SwapArgs = false; SetCCOpc = X86::SETAr; break;
637 case CmpInst::ICMP_UGE: SwapArgs = false; SetCCOpc = X86::SETAEr; break;
638 case CmpInst::ICMP_ULT: SwapArgs = false; SetCCOpc = X86::SETBr; break;
639 case CmpInst::ICMP_ULE: SwapArgs = false; SetCCOpc = X86::SETBEr; break;
640 case CmpInst::ICMP_SGT: SwapArgs = false; SetCCOpc = X86::SETGr; break;
641 case CmpInst::ICMP_SGE: SwapArgs = false; SetCCOpc = X86::SETGEr; break;
642 case CmpInst::ICMP_SLT: SwapArgs = false; SetCCOpc = X86::SETLr; break;
643 case CmpInst::ICMP_SLE: SwapArgs = false; SetCCOpc = X86::SETLEr; break;
648 Value *Op0 = CI->getOperand(0), *Op1 = CI->getOperand(1);
652 // Emit a compare of Op0/Op1.
653 if (!X86FastEmitCompare(Op0, Op1, VT))
656 BuildMI(MBB, TII.get(SetCCOpc), ResultReg);
657 UpdateValueMap(I, ResultReg);
661 bool X86FastISel::X86SelectZExt(Instruction *I) {
662 // Special-case hack: The only i1 values we know how to produce currently
663 // set the upper bits of an i8 value to zero.
664 if (I->getType() == Type::Int8Ty &&
665 I->getOperand(0)->getType() == Type::Int1Ty) {
666 unsigned ResultReg = getRegForValue(I->getOperand(0));
667 if (ResultReg == 0) return false;
668 UpdateValueMap(I, ResultReg);
676 bool X86FastISel::X86SelectBranch(Instruction *I) {
677 // Unconditional branches are selected by tablegen-generated code.
678 // Handle a conditional branch.
679 BranchInst *BI = cast<BranchInst>(I);
680 MachineBasicBlock *TrueMBB = MBBMap[BI->getSuccessor(0)];
681 MachineBasicBlock *FalseMBB = MBBMap[BI->getSuccessor(1)];
683 // Fold the common case of a conditional branch with a comparison.
684 if (CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
685 if (CI->hasOneUse()) {
686 MVT VT = TLI.getValueType(CI->getOperand(0)->getType());
688 // Try to take advantage of fallthrough opportunities.
689 CmpInst::Predicate Predicate = CI->getPredicate();
690 if (MBB->isLayoutSuccessor(TrueMBB)) {
691 std::swap(TrueMBB, FalseMBB);
692 Predicate = CmpInst::getInversePredicate(Predicate);
695 bool SwapArgs; // false -> compare Op0, Op1. true -> compare Op1, Op0.
696 unsigned BranchOpc; // Opcode to jump on, e.g. "X86::JA"
699 case CmpInst::FCMP_OEQ:
700 std::swap(TrueMBB, FalseMBB);
701 Predicate = CmpInst::FCMP_UNE;
703 case CmpInst::FCMP_UNE: SwapArgs = false; BranchOpc = X86::JNE; break;
704 case CmpInst::FCMP_OGT: SwapArgs = false; BranchOpc = X86::JA; break;
705 case CmpInst::FCMP_OGE: SwapArgs = false; BranchOpc = X86::JAE; break;
706 case CmpInst::FCMP_OLT: SwapArgs = true; BranchOpc = X86::JA; break;
707 case CmpInst::FCMP_OLE: SwapArgs = true; BranchOpc = X86::JAE; break;
708 case CmpInst::FCMP_ONE: SwapArgs = false; BranchOpc = X86::JNE; break;
709 case CmpInst::FCMP_ORD: SwapArgs = false; BranchOpc = X86::JNP; break;
710 case CmpInst::FCMP_UNO: SwapArgs = false; BranchOpc = X86::JP; break;
711 case CmpInst::FCMP_UEQ: SwapArgs = false; BranchOpc = X86::JE; break;
712 case CmpInst::FCMP_UGT: SwapArgs = true; BranchOpc = X86::JB; break;
713 case CmpInst::FCMP_UGE: SwapArgs = true; BranchOpc = X86::JBE; break;
714 case CmpInst::FCMP_ULT: SwapArgs = false; BranchOpc = X86::JB; break;
715 case CmpInst::FCMP_ULE: SwapArgs = false; BranchOpc = X86::JBE; break;
717 case CmpInst::ICMP_EQ: SwapArgs = false; BranchOpc = X86::JE; break;
718 case CmpInst::ICMP_NE: SwapArgs = false; BranchOpc = X86::JNE; break;
719 case CmpInst::ICMP_UGT: SwapArgs = false; BranchOpc = X86::JA; break;
720 case CmpInst::ICMP_UGE: SwapArgs = false; BranchOpc = X86::JAE; break;
721 case CmpInst::ICMP_ULT: SwapArgs = false; BranchOpc = X86::JB; break;
722 case CmpInst::ICMP_ULE: SwapArgs = false; BranchOpc = X86::JBE; break;
723 case CmpInst::ICMP_SGT: SwapArgs = false; BranchOpc = X86::JG; break;
724 case CmpInst::ICMP_SGE: SwapArgs = false; BranchOpc = X86::JGE; break;
725 case CmpInst::ICMP_SLT: SwapArgs = false; BranchOpc = X86::JL; break;
726 case CmpInst::ICMP_SLE: SwapArgs = false; BranchOpc = X86::JLE; break;
731 Value *Op0 = CI->getOperand(0), *Op1 = CI->getOperand(1);
735 // Emit a compare of the LHS and RHS, setting the flags.
736 if (!X86FastEmitCompare(Op0, Op1, VT))
739 BuildMI(MBB, TII.get(BranchOpc)).addMBB(TrueMBB);
741 if (Predicate == CmpInst::FCMP_UNE) {
742 // X86 requires a second branch to handle UNE (and OEQ,
743 // which is mapped to UNE above).
744 BuildMI(MBB, TII.get(X86::JP)).addMBB(TrueMBB);
747 FastEmitBranch(FalseMBB);
748 MBB->addSuccessor(TrueMBB);
751 } else if (ExtractValueInst *EI =
752 dyn_cast<ExtractValueInst>(BI->getCondition())) {
753 // Check to see if the branch instruction is from an "arithmetic with
754 // overflow" intrinsic. The main way these intrinsics are used is:
756 // %t = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %v1, i32 %v2)
757 // %sum = extractvalue { i32, i1 } %t, 0
758 // %obit = extractvalue { i32, i1 } %t, 1
759 // br i1 %obit, label %overflow, label %normal
761 // The %sum and %obit are converted in an ADD and a SETO/SETC before
762 // reaching the branch. Therefore, we search backwards through the MBB
763 // looking for the SETO/SETC instruction. If an instruction modifies the
764 // EFLAGS register before we reach the SETO/SETC instruction, then we can't
765 // convert the branch into a JO/JC instruction.
767 Value *Agg = EI->getAggregateOperand();
769 if (CallInst *CI = dyn_cast<CallInst>(Agg)) {
770 Function *F = CI->getCalledFunction();
772 if (F && F->isDeclaration()) {
773 switch (F->getIntrinsicID()) {
775 case Intrinsic::sadd_with_overflow:
776 case Intrinsic::uadd_with_overflow: {
777 const MachineInstr *SetMI = 0;
778 unsigned Reg = lookUpRegForValue(EI);
780 for (MachineBasicBlock::const_reverse_iterator
781 RI = MBB->rbegin(), RE = MBB->rend(); RI != RE; ++RI) {
782 const MachineInstr &MI = *RI;
784 if (MI.modifiesRegister(Reg)) {
787 if (getInstrInfo()->isMoveInstr(MI, Src, Dst)) {
796 const TargetInstrDesc &TID = MI.getDesc();
797 const unsigned *ImpDefs = TID.getImplicitDefs();
799 if (TID.hasUnmodeledSideEffects()) break;
801 bool ModifiesEFlags = false;
804 for (unsigned u = 0; ImpDefs[u]; ++u)
805 if (ImpDefs[u] == X86::EFLAGS) {
806 ModifiesEFlags = true;
811 if (ModifiesEFlags) break;
815 unsigned OpCode = SetMI->getOpcode();
817 if (OpCode == X86::SETOr || OpCode == X86::SETCr) {
818 BuildMI(MBB, TII.get((OpCode == X86::SETOr) ?
819 X86::JO : X86::JC)).addMBB(TrueMBB);
820 FastEmitBranch(FalseMBB);
821 MBB->addSuccessor(TrueMBB);
831 // Otherwise do a clumsy setcc and re-test it.
832 unsigned OpReg = getRegForValue(BI->getCondition());
833 if (OpReg == 0) return false;
835 BuildMI(MBB, TII.get(X86::TEST8rr)).addReg(OpReg).addReg(OpReg);
836 BuildMI(MBB, TII.get(X86::JNE)).addMBB(TrueMBB);
837 FastEmitBranch(FalseMBB);
838 MBB->addSuccessor(TrueMBB);
842 bool X86FastISel::X86SelectShift(Instruction *I) {
843 unsigned CReg = 0, OpReg = 0, OpImm = 0;
844 const TargetRegisterClass *RC = NULL;
845 if (I->getType() == Type::Int8Ty) {
847 RC = &X86::GR8RegClass;
848 switch (I->getOpcode()) {
849 case Instruction::LShr: OpReg = X86::SHR8rCL; OpImm = X86::SHR8ri; break;
850 case Instruction::AShr: OpReg = X86::SAR8rCL; OpImm = X86::SAR8ri; break;
851 case Instruction::Shl: OpReg = X86::SHL8rCL; OpImm = X86::SHL8ri; break;
852 default: return false;
854 } else if (I->getType() == Type::Int16Ty) {
856 RC = &X86::GR16RegClass;
857 switch (I->getOpcode()) {
858 case Instruction::LShr: OpReg = X86::SHR16rCL; OpImm = X86::SHR16ri; break;
859 case Instruction::AShr: OpReg = X86::SAR16rCL; OpImm = X86::SAR16ri; break;
860 case Instruction::Shl: OpReg = X86::SHL16rCL; OpImm = X86::SHL16ri; break;
861 default: return false;
863 } else if (I->getType() == Type::Int32Ty) {
865 RC = &X86::GR32RegClass;
866 switch (I->getOpcode()) {
867 case Instruction::LShr: OpReg = X86::SHR32rCL; OpImm = X86::SHR32ri; break;
868 case Instruction::AShr: OpReg = X86::SAR32rCL; OpImm = X86::SAR32ri; break;
869 case Instruction::Shl: OpReg = X86::SHL32rCL; OpImm = X86::SHL32ri; break;
870 default: return false;
872 } else if (I->getType() == Type::Int64Ty) {
874 RC = &X86::GR64RegClass;
875 switch (I->getOpcode()) {
876 case Instruction::LShr: OpReg = X86::SHR64rCL; OpImm = X86::SHR64ri; break;
877 case Instruction::AShr: OpReg = X86::SAR64rCL; OpImm = X86::SAR64ri; break;
878 case Instruction::Shl: OpReg = X86::SHL64rCL; OpImm = X86::SHL64ri; break;
879 default: return false;
885 MVT VT = TLI.getValueType(I->getType(), /*HandleUnknown=*/true);
886 if (VT == MVT::Other || !isTypeLegal(I->getType(), VT))
889 unsigned Op0Reg = getRegForValue(I->getOperand(0));
890 if (Op0Reg == 0) return false;
892 // Fold immediate in shl(x,3).
893 if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) {
894 unsigned ResultReg = createResultReg(RC);
895 BuildMI(MBB, TII.get(OpImm),
896 ResultReg).addReg(Op0Reg).addImm(CI->getZExtValue() & 0xff);
897 UpdateValueMap(I, ResultReg);
901 unsigned Op1Reg = getRegForValue(I->getOperand(1));
902 if (Op1Reg == 0) return false;
903 TII.copyRegToReg(*MBB, MBB->end(), CReg, Op1Reg, RC, RC);
905 // The shift instruction uses X86::CL. If we defined a super-register
906 // of X86::CL, emit an EXTRACT_SUBREG to precisely describe what
909 BuildMI(MBB, TII.get(TargetInstrInfo::EXTRACT_SUBREG), X86::CL)
910 .addReg(CReg).addImm(X86::SUBREG_8BIT);
912 unsigned ResultReg = createResultReg(RC);
913 BuildMI(MBB, TII.get(OpReg), ResultReg).addReg(Op0Reg);
914 UpdateValueMap(I, ResultReg);
918 bool X86FastISel::X86SelectSelect(Instruction *I) {
919 MVT VT = TLI.getValueType(I->getType(), /*HandleUnknown=*/true);
920 if (VT == MVT::Other || !isTypeLegal(I->getType(), VT))
924 const TargetRegisterClass *RC = NULL;
925 if (VT.getSimpleVT() == MVT::i16) {
926 Opc = X86::CMOVE16rr;
927 RC = &X86::GR16RegClass;
928 } else if (VT.getSimpleVT() == MVT::i32) {
929 Opc = X86::CMOVE32rr;
930 RC = &X86::GR32RegClass;
931 } else if (VT.getSimpleVT() == MVT::i64) {
932 Opc = X86::CMOVE64rr;
933 RC = &X86::GR64RegClass;
938 unsigned Op0Reg = getRegForValue(I->getOperand(0));
939 if (Op0Reg == 0) return false;
940 unsigned Op1Reg = getRegForValue(I->getOperand(1));
941 if (Op1Reg == 0) return false;
942 unsigned Op2Reg = getRegForValue(I->getOperand(2));
943 if (Op2Reg == 0) return false;
945 BuildMI(MBB, TII.get(X86::TEST8rr)).addReg(Op0Reg).addReg(Op0Reg);
946 unsigned ResultReg = createResultReg(RC);
947 BuildMI(MBB, TII.get(Opc), ResultReg).addReg(Op1Reg).addReg(Op2Reg);
948 UpdateValueMap(I, ResultReg);
952 bool X86FastISel::X86SelectFPExt(Instruction *I) {
953 // fpext from float to double.
954 if (Subtarget->hasSSE2() && I->getType() == Type::DoubleTy) {
955 Value *V = I->getOperand(0);
956 if (V->getType() == Type::FloatTy) {
957 unsigned OpReg = getRegForValue(V);
958 if (OpReg == 0) return false;
959 unsigned ResultReg = createResultReg(X86::FR64RegisterClass);
960 BuildMI(MBB, TII.get(X86::CVTSS2SDrr), ResultReg).addReg(OpReg);
961 UpdateValueMap(I, ResultReg);
969 bool X86FastISel::X86SelectFPTrunc(Instruction *I) {
970 if (Subtarget->hasSSE2()) {
971 if (I->getType() == Type::FloatTy) {
972 Value *V = I->getOperand(0);
973 if (V->getType() == Type::DoubleTy) {
974 unsigned OpReg = getRegForValue(V);
975 if (OpReg == 0) return false;
976 unsigned ResultReg = createResultReg(X86::FR32RegisterClass);
977 BuildMI(MBB, TII.get(X86::CVTSD2SSrr), ResultReg).addReg(OpReg);
978 UpdateValueMap(I, ResultReg);
987 bool X86FastISel::X86SelectTrunc(Instruction *I) {
988 if (Subtarget->is64Bit())
989 // All other cases should be handled by the tblgen generated code.
991 MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
992 MVT DstVT = TLI.getValueType(I->getType());
993 if (DstVT != MVT::i8)
994 // All other cases should be handled by the tblgen generated code.
996 if (SrcVT != MVT::i16 && SrcVT != MVT::i32)
997 // All other cases should be handled by the tblgen generated code.
1000 unsigned InputReg = getRegForValue(I->getOperand(0));
1002 // Unhandled operand. Halt "fast" selection and bail.
1005 // First issue a copy to GR16_ or GR32_.
1006 unsigned CopyOpc = (SrcVT == MVT::i16) ? X86::MOV16to16_ : X86::MOV32to32_;
1007 const TargetRegisterClass *CopyRC = (SrcVT == MVT::i16)
1008 ? X86::GR16_RegisterClass : X86::GR32_RegisterClass;
1009 unsigned CopyReg = createResultReg(CopyRC);
1010 BuildMI(MBB, TII.get(CopyOpc), CopyReg).addReg(InputReg);
1012 // Then issue an extract_subreg.
1013 unsigned ResultReg = FastEmitInst_extractsubreg(CopyReg, X86::SUBREG_8BIT);
1017 UpdateValueMap(I, ResultReg);
1021 bool X86FastISel::X86SelectExtractValue(Instruction *I) {
1022 ExtractValueInst *EI = cast<ExtractValueInst>(I);
1023 Value *Agg = EI->getAggregateOperand();
1025 if (CallInst *CI = dyn_cast<CallInst>(Agg)) {
1026 Function *F = CI->getCalledFunction();
1028 if (F && F->isDeclaration()) {
1029 switch (F->getIntrinsicID()) {
1031 case Intrinsic::sadd_with_overflow:
1032 case Intrinsic::uadd_with_overflow:
1033 // Cheat a little. We know that the registers for "add" and "seto" are
1034 // allocated sequentially. However, we only keep track of the register
1035 // for "add" in the value map. Use extractvalue's index to get the
1036 // correct register for "seto".
1037 UpdateValueMap(I, lookUpRegForValue(Agg) + *EI->idx_begin());
1046 bool X86FastISel::X86VisitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
1047 // FIXME: Handle more intrinsics.
1048 switch (Intrinsic) {
1049 default: return false;
1050 case Intrinsic::sadd_with_overflow:
1051 case Intrinsic::uadd_with_overflow: {
1052 // Replace "add with overflow" intrinsics with an "add" instruction followed
1053 // by a seto/setc instruction. Later on, when the "extractvalue"
1054 // instructions are encountered, we use the fact that two registers were
1055 // created sequentially to get the correct registers for the "sum" and the
1058 const Function *Callee = I.getCalledFunction();
1060 cast<StructType>(Callee->getReturnType())->getTypeAtIndex(unsigned(0));
1062 if (!isTypeLegal(RetTy, VT))
1065 Value *Op1 = I.getOperand(1);
1066 Value *Op2 = I.getOperand(2);
1067 unsigned Reg1 = getRegForValue(Op1);
1068 unsigned Reg2 = getRegForValue(Op2);
1070 if (Reg1 == 0 || Reg2 == 0)
1071 // FIXME: Handle values *not* in registers.
1078 else if (VT == MVT::i64)
1083 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
1084 BuildMI(MBB, TII.get(OpC), ResultReg).addReg(Reg1).addReg(Reg2);
1085 UpdateValueMap(&I, ResultReg);
1087 ResultReg = createResultReg(TLI.getRegClassFor(MVT::i8));
1088 BuildMI(MBB, TII.get((Intrinsic == Intrinsic::sadd_with_overflow) ?
1089 X86::SETOr : X86::SETCr), ResultReg);
1095 bool X86FastISel::X86SelectCall(Instruction *I) {
1096 CallInst *CI = cast<CallInst>(I);
1097 Value *Callee = I->getOperand(0);
1099 // Can't handle inline asm yet.
1100 if (isa<InlineAsm>(Callee))
1103 // Handle intrinsic calls.
1104 if (Function *F = CI->getCalledFunction())
1105 if (F->isDeclaration())
1106 if (unsigned IID = F->getIntrinsicID())
1107 return X86VisitIntrinsicCall(*CI, IID);
1109 // Handle only C and fastcc calling conventions for now.
1111 unsigned CC = CS.getCallingConv();
1112 if (CC != CallingConv::C &&
1113 CC != CallingConv::Fast &&
1114 CC != CallingConv::X86_FastCall)
1117 // Let SDISel handle vararg functions.
1118 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
1119 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
1120 if (FTy->isVarArg())
1123 // Handle *simple* calls for now.
1124 const Type *RetTy = CS.getType();
1126 if (RetTy == Type::VoidTy)
1127 RetVT = MVT::isVoid;
1128 else if (!isTypeLegal(RetTy, RetVT, true))
1131 // Materialize callee address in a register. FIXME: GV address can be
1132 // handled with a CALLpcrel32 instead.
1133 X86AddressMode CalleeAM;
1134 if (!X86SelectAddress(Callee, CalleeAM, true))
1136 unsigned CalleeOp = 0;
1137 GlobalValue *GV = 0;
1138 if (CalleeAM.Base.Reg != 0) {
1139 assert(CalleeAM.GV == 0);
1140 CalleeOp = CalleeAM.Base.Reg;
1141 } else if (CalleeAM.GV != 0) {
1142 assert(CalleeAM.GV != 0);
1147 // Allow calls which produce i1 results.
1148 bool AndToI1 = false;
1149 if (RetVT == MVT::i1) {
1154 // Deal with call operands first.
1155 SmallVector<Value*, 8> ArgVals;
1156 SmallVector<unsigned, 8> Args;
1157 SmallVector<MVT, 8> ArgVTs;
1158 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
1159 Args.reserve(CS.arg_size());
1160 ArgVals.reserve(CS.arg_size());
1161 ArgVTs.reserve(CS.arg_size());
1162 ArgFlags.reserve(CS.arg_size());
1163 for (CallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
1165 unsigned Arg = getRegForValue(*i);
1168 ISD::ArgFlagsTy Flags;
1169 unsigned AttrInd = i - CS.arg_begin() + 1;
1170 if (CS.paramHasAttr(AttrInd, Attribute::SExt))
1172 if (CS.paramHasAttr(AttrInd, Attribute::ZExt))
1175 // FIXME: Only handle *easy* calls for now.
1176 if (CS.paramHasAttr(AttrInd, Attribute::InReg) ||
1177 CS.paramHasAttr(AttrInd, Attribute::StructRet) ||
1178 CS.paramHasAttr(AttrInd, Attribute::Nest) ||
1179 CS.paramHasAttr(AttrInd, Attribute::ByVal))
1182 const Type *ArgTy = (*i)->getType();
1184 if (!isTypeLegal(ArgTy, ArgVT))
1186 unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
1187 Flags.setOrigAlign(OriginalAlignment);
1189 Args.push_back(Arg);
1190 ArgVals.push_back(*i);
1191 ArgVTs.push_back(ArgVT);
1192 ArgFlags.push_back(Flags);
1195 // Analyze operands of the call, assigning locations to each operand.
1196 SmallVector<CCValAssign, 16> ArgLocs;
1197 CCState CCInfo(CC, false, TM, ArgLocs);
1198 CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, CCAssignFnForCall(CC));
1200 // Get a count of how many bytes are to be pushed on the stack.
1201 unsigned NumBytes = CCInfo.getNextStackOffset();
1203 // Issue CALLSEQ_START
1204 unsigned AdjStackDown = TM.getRegisterInfo()->getCallFrameSetupOpcode();
1205 BuildMI(MBB, TII.get(AdjStackDown)).addImm(NumBytes);
1207 // Process argument: walk the register/memloc assignments, inserting
1209 SmallVector<unsigned, 4> RegArgs;
1210 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1211 CCValAssign &VA = ArgLocs[i];
1212 unsigned Arg = Args[VA.getValNo()];
1213 MVT ArgVT = ArgVTs[VA.getValNo()];
1215 // Promote the value if needed.
1216 switch (VA.getLocInfo()) {
1217 default: assert(0 && "Unknown loc info!");
1218 case CCValAssign::Full: break;
1219 case CCValAssign::SExt: {
1220 bool Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(),
1222 assert(Emitted && "Failed to emit a sext!"); Emitted=Emitted;
1224 ArgVT = VA.getLocVT();
1227 case CCValAssign::ZExt: {
1228 bool Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(),
1230 assert(Emitted && "Failed to emit a zext!"); Emitted=Emitted;
1232 ArgVT = VA.getLocVT();
1235 case CCValAssign::AExt: {
1236 bool Emitted = X86FastEmitExtend(ISD::ANY_EXTEND, VA.getLocVT(),
1239 Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(),
1242 Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(),
1245 assert(Emitted && "Failed to emit a aext!"); Emitted=Emitted;
1246 ArgVT = VA.getLocVT();
1251 if (VA.isRegLoc()) {
1252 TargetRegisterClass* RC = TLI.getRegClassFor(ArgVT);
1253 bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), VA.getLocReg(),
1255 assert(Emitted && "Failed to emit a copy instruction!"); Emitted=Emitted;
1257 RegArgs.push_back(VA.getLocReg());
1259 unsigned LocMemOffset = VA.getLocMemOffset();
1261 AM.Base.Reg = StackPtr;
1262 AM.Disp = LocMemOffset;
1263 Value *ArgVal = ArgVals[VA.getValNo()];
1265 // If this is a really simple value, emit this with the Value* version of
1266 // X86FastEmitStore. If it isn't simple, we don't want to do this, as it
1267 // can cause us to reevaluate the argument.
1268 if (isa<ConstantInt>(ArgVal) || isa<ConstantPointerNull>(ArgVal))
1269 X86FastEmitStore(ArgVT, ArgVal, AM);
1271 X86FastEmitStore(ArgVT, Arg, AM);
1275 // ELF / PIC requires GOT in the EBX register before function calls via PLT
1277 if (!Subtarget->is64Bit() &&
1278 TM.getRelocationModel() == Reloc::PIC_ &&
1279 Subtarget->isPICStyleGOT()) {
1280 TargetRegisterClass *RC = X86::GR32RegisterClass;
1281 unsigned Base = getInstrInfo()->getGlobalBaseReg(&MF);
1282 bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), X86::EBX, Base, RC, RC);
1283 assert(Emitted && "Failed to emit a copy instruction!"); Emitted=Emitted;
1288 unsigned CallOpc = CalleeOp
1289 ? (Subtarget->is64Bit() ? X86::CALL64r : X86::CALL32r)
1290 : (Subtarget->is64Bit() ? X86::CALL64pcrel32 : X86::CALLpcrel32);
1291 MachineInstrBuilder MIB = CalleeOp
1292 ? BuildMI(MBB, TII.get(CallOpc)).addReg(CalleeOp)
1293 : BuildMI(MBB, TII.get(CallOpc)).addGlobalAddress(GV);
1295 // Add an implicit use GOT pointer in EBX.
1296 if (!Subtarget->is64Bit() &&
1297 TM.getRelocationModel() == Reloc::PIC_ &&
1298 Subtarget->isPICStyleGOT())
1299 MIB.addReg(X86::EBX);
1301 // Add implicit physical register uses to the call.
1302 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
1303 MIB.addReg(RegArgs[i]);
1305 // Issue CALLSEQ_END
1306 unsigned AdjStackUp = TM.getRegisterInfo()->getCallFrameDestroyOpcode();
1307 BuildMI(MBB, TII.get(AdjStackUp)).addImm(NumBytes).addImm(0);
1309 // Now handle call return value (if any).
1310 if (RetVT.getSimpleVT() != MVT::isVoid) {
1311 SmallVector<CCValAssign, 16> RVLocs;
1312 CCState CCInfo(CC, false, TM, RVLocs);
1313 CCInfo.AnalyzeCallResult(RetVT, RetCC_X86);
1315 // Copy all of the result registers out of their specified physreg.
1316 assert(RVLocs.size() == 1 && "Can't handle multi-value calls!");
1317 MVT CopyVT = RVLocs[0].getValVT();
1318 TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT);
1319 TargetRegisterClass *SrcRC = DstRC;
1321 // If this is a call to a function that returns an fp value on the x87 fp
1322 // stack, but where we prefer to use the value in xmm registers, copy it
1323 // out as F80 and use a truncate to move it from fp stack reg to xmm reg.
1324 if ((RVLocs[0].getLocReg() == X86::ST0 ||
1325 RVLocs[0].getLocReg() == X86::ST1) &&
1326 isScalarFPTypeInSSEReg(RVLocs[0].getValVT())) {
1328 SrcRC = X86::RSTRegisterClass;
1329 DstRC = X86::RFP80RegisterClass;
1332 unsigned ResultReg = createResultReg(DstRC);
1333 bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
1334 RVLocs[0].getLocReg(), DstRC, SrcRC);
1335 assert(Emitted && "Failed to emit a copy instruction!"); Emitted=Emitted;
1337 if (CopyVT != RVLocs[0].getValVT()) {
1338 // Round the F80 the right size, which also moves to the appropriate xmm
1339 // register. This is accomplished by storing the F80 value in memory and
1340 // then loading it back. Ewww...
1341 MVT ResVT = RVLocs[0].getValVT();
1342 unsigned Opc = ResVT == MVT::f32 ? X86::ST_Fp80m32 : X86::ST_Fp80m64;
1343 unsigned MemSize = ResVT.getSizeInBits()/8;
1344 int FI = MFI.CreateStackObject(MemSize, MemSize);
1345 addFrameReference(BuildMI(MBB, TII.get(Opc)), FI).addReg(ResultReg);
1346 DstRC = ResVT == MVT::f32
1347 ? X86::FR32RegisterClass : X86::FR64RegisterClass;
1348 Opc = ResVT == MVT::f32 ? X86::MOVSSrm : X86::MOVSDrm;
1349 ResultReg = createResultReg(DstRC);
1350 addFrameReference(BuildMI(MBB, TII.get(Opc), ResultReg), FI);
1354 // Mask out all but lowest bit for some call which produces an i1.
1355 unsigned AndResult = createResultReg(X86::GR8RegisterClass);
1356 BuildMI(MBB, TII.get(X86::AND8ri), AndResult).addReg(ResultReg).addImm(1);
1357 ResultReg = AndResult;
1360 UpdateValueMap(I, ResultReg);
1368 X86FastISel::TargetSelectInstruction(Instruction *I) {
1369 switch (I->getOpcode()) {
1371 case Instruction::Load:
1372 return X86SelectLoad(I);
1373 case Instruction::Store:
1374 return X86SelectStore(I);
1375 case Instruction::ICmp:
1376 case Instruction::FCmp:
1377 return X86SelectCmp(I);
1378 case Instruction::ZExt:
1379 return X86SelectZExt(I);
1380 case Instruction::Br:
1381 return X86SelectBranch(I);
1382 case Instruction::Call:
1383 return X86SelectCall(I);
1384 case Instruction::LShr:
1385 case Instruction::AShr:
1386 case Instruction::Shl:
1387 return X86SelectShift(I);
1388 case Instruction::Select:
1389 return X86SelectSelect(I);
1390 case Instruction::Trunc:
1391 return X86SelectTrunc(I);
1392 case Instruction::FPExt:
1393 return X86SelectFPExt(I);
1394 case Instruction::FPTrunc:
1395 return X86SelectFPTrunc(I);
1396 case Instruction::ExtractValue:
1397 return X86SelectExtractValue(I);
1403 unsigned X86FastISel::TargetMaterializeConstant(Constant *C) {
1405 if (!isTypeLegal(C->getType(), VT))
1408 // Get opcode and regclass of the output for the given load instruction.
1410 const TargetRegisterClass *RC = NULL;
1411 switch (VT.getSimpleVT()) {
1412 default: return false;
1415 RC = X86::GR8RegisterClass;
1419 RC = X86::GR16RegisterClass;
1423 RC = X86::GR32RegisterClass;
1426 // Must be in x86-64 mode.
1428 RC = X86::GR64RegisterClass;
1431 if (Subtarget->hasSSE1()) {
1433 RC = X86::FR32RegisterClass;
1435 Opc = X86::LD_Fp32m;
1436 RC = X86::RFP32RegisterClass;
1440 if (Subtarget->hasSSE2()) {
1442 RC = X86::FR64RegisterClass;
1444 Opc = X86::LD_Fp64m;
1445 RC = X86::RFP64RegisterClass;
1449 // No f80 support yet.
1453 // Materialize addresses with LEA instructions.
1454 if (isa<GlobalValue>(C)) {
1456 if (X86SelectAddress(C, AM, false)) {
1457 if (TLI.getPointerTy() == MVT::i32)
1461 unsigned ResultReg = createResultReg(RC);
1462 addFullAddress(BuildMI(MBB, TII.get(Opc), ResultReg), AM);
1468 // MachineConstantPool wants an explicit alignment.
1469 unsigned Align = TD.getPreferredTypeAlignmentShift(C->getType());
1471 // Alignment of vector types. FIXME!
1472 Align = TD.getABITypeSize(C->getType());
1473 Align = Log2_64(Align);
1476 // x86-32 PIC requires a PIC base register for constant pools.
1477 unsigned PICBase = 0;
1478 if (TM.getRelocationModel() == Reloc::PIC_ &&
1479 !Subtarget->is64Bit())
1480 PICBase = getInstrInfo()->getGlobalBaseReg(&MF);
1482 // Create the load from the constant pool.
1483 unsigned MCPOffset = MCP.getConstantPoolIndex(C, Align);
1484 unsigned ResultReg = createResultReg(RC);
1485 addConstantPoolReference(BuildMI(MBB, TII.get(Opc), ResultReg), MCPOffset,
1491 unsigned X86FastISel::TargetMaterializeAlloca(AllocaInst *C) {
1492 // Fail on dynamic allocas. At this point, getRegForValue has already
1493 // checked its CSE maps, so if we're here trying to handle a dynamic
1494 // alloca, we're not going to succeed. X86SelectAddress has a
1495 // check for dynamic allocas, because it's called directly from
1496 // various places, but TargetMaterializeAlloca also needs a check
1497 // in order to avoid recursion between getRegForValue,
1498 // X86SelectAddrss, and TargetMaterializeAlloca.
1499 if (!StaticAllocaMap.count(C))
1503 if (!X86SelectAddress(C, AM, false))
1505 unsigned Opc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
1506 TargetRegisterClass* RC = TLI.getRegClassFor(TLI.getPointerTy());
1507 unsigned ResultReg = createResultReg(RC);
1508 addFullAddress(BuildMI(MBB, TII.get(Opc), ResultReg), AM);
1513 llvm::FastISel *X86::createFastISel(MachineFunction &mf,
1514 MachineModuleInfo *mmi,
1515 DenseMap<const Value *, unsigned> &vm,
1516 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
1517 DenseMap<const AllocaInst *, int> &am
1519 , SmallSet<Instruction*, 8> &cil
1522 return new X86FastISel(mf, mmi, vm, bm, am