1 //===-- X86FastISel.cpp - X86 FastISel implementation ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the X86-specific support for the FastISel class. Much
11 // of the target-specific code is generated by tablegen in the file
12 // X86GenFastISel.inc, which is #included here.
14 //===----------------------------------------------------------------------===//
17 #include "X86InstrBuilder.h"
18 #include "X86RegisterInfo.h"
19 #include "X86Subtarget.h"
20 #include "X86TargetMachine.h"
21 #include "llvm/CallingConv.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/Instructions.h"
25 #include "llvm/IntrinsicInst.h"
26 #include "llvm/CodeGen/FastISel.h"
27 #include "llvm/CodeGen/MachineConstantPool.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/Support/CallSite.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/Support/GetElementPtrTypeIterator.h"
33 #include "llvm/Target/TargetOptions.h"
38 class X86FastISel : public FastISel {
39 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
40 /// make the right decision when generating code for different targets.
41 const X86Subtarget *Subtarget;
43 /// StackPtr - Register used as the stack pointer.
47 /// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87
48 /// floating point ops.
49 /// When SSE is available, use it for f32 operations.
50 /// When SSE2 is available, use it for f64 operations.
55 explicit X86FastISel(MachineFunction &mf,
56 DenseMap<const Value *, unsigned> &vm,
57 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
58 DenseMap<const AllocaInst *, int> &am,
59 std::vector<std::pair<MachineInstr*, unsigned> > &pn
61 , SmallSet<const Instruction *, 8> &cil
64 : FastISel(mf, vm, bm, am, pn
69 Subtarget = &TM.getSubtarget<X86Subtarget>();
70 StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
71 X86ScalarSSEf64 = Subtarget->hasSSE2();
72 X86ScalarSSEf32 = Subtarget->hasSSE1();
75 virtual bool TargetSelectInstruction(const Instruction *I);
77 #include "X86GenFastISel.inc"
80 bool X86FastEmitCompare(const Value *LHS, const Value *RHS, EVT VT);
82 bool X86FastEmitLoad(EVT VT, const X86AddressMode &AM, unsigned &RR);
84 bool X86FastEmitStore(EVT VT, const Value *Val,
85 const X86AddressMode &AM);
86 bool X86FastEmitStore(EVT VT, unsigned Val,
87 const X86AddressMode &AM);
89 bool X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT,
92 bool X86SelectAddress(const Value *V, X86AddressMode &AM);
93 bool X86SelectCallAddress(const Value *V, X86AddressMode &AM);
95 bool X86SelectLoad(const Instruction *I);
97 bool X86SelectStore(const Instruction *I);
99 bool X86SelectCmp(const Instruction *I);
101 bool X86SelectZExt(const Instruction *I);
103 bool X86SelectBranch(const Instruction *I);
105 bool X86SelectShift(const Instruction *I);
107 bool X86SelectSelect(const Instruction *I);
109 bool X86SelectTrunc(const Instruction *I);
111 bool X86SelectFPExt(const Instruction *I);
112 bool X86SelectFPTrunc(const Instruction *I);
114 bool X86SelectExtractValue(const Instruction *I);
116 bool X86VisitIntrinsicCall(const IntrinsicInst &I);
117 bool X86SelectCall(const Instruction *I);
119 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool isTailCall = false);
121 const X86InstrInfo *getInstrInfo() const {
122 return getTargetMachine()->getInstrInfo();
124 const X86TargetMachine *getTargetMachine() const {
125 return static_cast<const X86TargetMachine *>(&TM);
128 unsigned TargetMaterializeConstant(const Constant *C);
130 unsigned TargetMaterializeAlloca(const AllocaInst *C);
132 /// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is
133 /// computed in an SSE register, not on the X87 floating point stack.
134 bool isScalarFPTypeInSSEReg(EVT VT) const {
135 return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
136 (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
139 bool isTypeLegal(const Type *Ty, EVT &VT, bool AllowI1 = false);
142 } // end anonymous namespace.
144 bool X86FastISel::isTypeLegal(const Type *Ty, EVT &VT, bool AllowI1) {
145 VT = TLI.getValueType(Ty, /*HandleUnknown=*/true);
146 if (VT == MVT::Other || !VT.isSimple())
147 // Unhandled type. Halt "fast" selection and bail.
150 // For now, require SSE/SSE2 for performing floating-point operations,
151 // since x87 requires additional work.
152 if (VT == MVT::f64 && !X86ScalarSSEf64)
154 if (VT == MVT::f32 && !X86ScalarSSEf32)
156 // Similarly, no f80 support yet.
159 // We only handle legal types. For example, on x86-32 the instruction
160 // selector contains all of the 64-bit instructions from x86-64,
161 // under the assumption that i64 won't be used if the target doesn't
163 return (AllowI1 && VT == MVT::i1) || TLI.isTypeLegal(VT);
166 #include "X86GenCallingConv.inc"
168 /// CCAssignFnForCall - Selects the correct CCAssignFn for a given calling
170 CCAssignFn *X86FastISel::CCAssignFnForCall(CallingConv::ID CC,
172 if (Subtarget->is64Bit()) {
173 if (CC == CallingConv::GHC)
174 return CC_X86_64_GHC;
175 else if (Subtarget->isTargetWin64())
176 return CC_X86_Win64_C;
181 if (CC == CallingConv::X86_FastCall)
182 return CC_X86_32_FastCall;
183 else if (CC == CallingConv::X86_ThisCall)
184 return CC_X86_32_ThisCall;
185 else if (CC == CallingConv::Fast)
186 return CC_X86_32_FastCC;
187 else if (CC == CallingConv::GHC)
188 return CC_X86_32_GHC;
193 /// X86FastEmitLoad - Emit a machine instruction to load a value of type VT.
194 /// The address is either pre-computed, i.e. Ptr, or a GlobalAddress, i.e. GV.
195 /// Return true and the result register by reference if it is possible.
196 bool X86FastISel::X86FastEmitLoad(EVT VT, const X86AddressMode &AM,
197 unsigned &ResultReg) {
198 // Get opcode and regclass of the output for the given load instruction.
200 const TargetRegisterClass *RC = NULL;
201 switch (VT.getSimpleVT().SimpleTy) {
202 default: return false;
206 RC = X86::GR8RegisterClass;
210 RC = X86::GR16RegisterClass;
214 RC = X86::GR32RegisterClass;
217 // Must be in x86-64 mode.
219 RC = X86::GR64RegisterClass;
222 if (Subtarget->hasSSE1()) {
224 RC = X86::FR32RegisterClass;
227 RC = X86::RFP32RegisterClass;
231 if (Subtarget->hasSSE2()) {
233 RC = X86::FR64RegisterClass;
236 RC = X86::RFP64RegisterClass;
240 // No f80 support yet.
244 ResultReg = createResultReg(RC);
245 addFullAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), AM);
249 /// X86FastEmitStore - Emit a machine instruction to store a value Val of
250 /// type VT. The address is either pre-computed, consisted of a base ptr, Ptr
251 /// and a displacement offset, or a GlobalAddress,
252 /// i.e. V. Return true if it is possible.
254 X86FastISel::X86FastEmitStore(EVT VT, unsigned Val,
255 const X86AddressMode &AM) {
256 // Get opcode and regclass of the output for the given store instruction.
258 switch (VT.getSimpleVT().SimpleTy) {
259 case MVT::f80: // No f80 support yet.
260 default: return false;
262 // Mask out all but lowest bit.
263 unsigned AndResult = createResultReg(X86::GR8RegisterClass);
265 TII.get(X86::AND8ri), AndResult).addReg(Val).addImm(1);
268 // FALLTHROUGH, handling i1 as i8.
269 case MVT::i8: Opc = X86::MOV8mr; break;
270 case MVT::i16: Opc = X86::MOV16mr; break;
271 case MVT::i32: Opc = X86::MOV32mr; break;
272 case MVT::i64: Opc = X86::MOV64mr; break; // Must be in x86-64 mode.
274 Opc = Subtarget->hasSSE1() ? X86::MOVSSmr : X86::ST_Fp32m;
277 Opc = Subtarget->hasSSE2() ? X86::MOVSDmr : X86::ST_Fp64m;
281 addFullAddress(BuildMI(MBB, DL, TII.get(Opc)), AM).addReg(Val);
285 bool X86FastISel::X86FastEmitStore(EVT VT, const Value *Val,
286 const X86AddressMode &AM) {
287 // Handle 'null' like i32/i64 0.
288 if (isa<ConstantPointerNull>(Val))
289 Val = Constant::getNullValue(TD.getIntPtrType(Val->getContext()));
291 // If this is a store of a simple constant, fold the constant into the store.
292 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Val)) {
295 switch (VT.getSimpleVT().SimpleTy) {
297 case MVT::i1: Signed = false; // FALLTHROUGH to handle as i8.
298 case MVT::i8: Opc = X86::MOV8mi; break;
299 case MVT::i16: Opc = X86::MOV16mi; break;
300 case MVT::i32: Opc = X86::MOV32mi; break;
302 // Must be a 32-bit sign extended value.
303 if ((int)CI->getSExtValue() == CI->getSExtValue())
304 Opc = X86::MOV64mi32;
309 addFullAddress(BuildMI(MBB, DL, TII.get(Opc)), AM)
310 .addImm(Signed ? (uint64_t) CI->getSExtValue() :
316 unsigned ValReg = getRegForValue(Val);
320 return X86FastEmitStore(VT, ValReg, AM);
323 /// X86FastEmitExtend - Emit a machine instruction to extend a value Src of
324 /// type SrcVT to type DstVT using the specified extension opcode Opc (e.g.
325 /// ISD::SIGN_EXTEND).
326 bool X86FastISel::X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT,
327 unsigned Src, EVT SrcVT,
328 unsigned &ResultReg) {
329 unsigned RR = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc,
330 Src, /*TODO: Kill=*/false);
339 /// X86SelectAddress - Attempt to fill in an address from the given value.
341 bool X86FastISel::X86SelectAddress(const Value *V, X86AddressMode &AM) {
342 const User *U = NULL;
343 unsigned Opcode = Instruction::UserOp1;
344 if (const Instruction *I = dyn_cast<Instruction>(V)) {
345 // Don't walk into other basic blocks; it's possible we haven't
346 // visited them yet, so the instructions may not yet be assigned
347 // virtual registers.
348 if (MBBMap[I->getParent()] != MBB)
351 Opcode = I->getOpcode();
353 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(V)) {
354 Opcode = C->getOpcode();
358 if (const PointerType *Ty = dyn_cast<PointerType>(V->getType()))
359 if (Ty->getAddressSpace() > 255)
360 // Fast instruction selection doesn't support the special
366 case Instruction::BitCast:
367 // Look past bitcasts.
368 return X86SelectAddress(U->getOperand(0), AM);
370 case Instruction::IntToPtr:
371 // Look past no-op inttoptrs.
372 if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
373 return X86SelectAddress(U->getOperand(0), AM);
376 case Instruction::PtrToInt:
377 // Look past no-op ptrtoints.
378 if (TLI.getValueType(U->getType()) == TLI.getPointerTy())
379 return X86SelectAddress(U->getOperand(0), AM);
382 case Instruction::Alloca: {
383 // Do static allocas.
384 const AllocaInst *A = cast<AllocaInst>(V);
385 DenseMap<const AllocaInst*, int>::iterator SI = StaticAllocaMap.find(A);
386 if (SI != StaticAllocaMap.end()) {
387 AM.BaseType = X86AddressMode::FrameIndexBase;
388 AM.Base.FrameIndex = SI->second;
394 case Instruction::Add: {
395 // Adds of constants are common and easy enough.
396 if (const ConstantInt *CI = dyn_cast<ConstantInt>(U->getOperand(1))) {
397 uint64_t Disp = (int32_t)AM.Disp + (uint64_t)CI->getSExtValue();
398 // They have to fit in the 32-bit signed displacement field though.
399 if (isInt<32>(Disp)) {
400 AM.Disp = (uint32_t)Disp;
401 return X86SelectAddress(U->getOperand(0), AM);
407 case Instruction::GetElementPtr: {
408 X86AddressMode SavedAM = AM;
410 // Pattern-match simple GEPs.
411 uint64_t Disp = (int32_t)AM.Disp;
412 unsigned IndexReg = AM.IndexReg;
413 unsigned Scale = AM.Scale;
414 gep_type_iterator GTI = gep_type_begin(U);
415 // Iterate through the indices, folding what we can. Constants can be
416 // folded, and one dynamic index can be handled, if the scale is supported.
417 for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end();
418 i != e; ++i, ++GTI) {
419 const Value *Op = *i;
420 if (const StructType *STy = dyn_cast<StructType>(*GTI)) {
421 const StructLayout *SL = TD.getStructLayout(STy);
422 unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
423 Disp += SL->getElementOffset(Idx);
425 uint64_t S = TD.getTypeAllocSize(GTI.getIndexedType());
426 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
427 // Constant-offset addressing.
428 Disp += CI->getSExtValue() * S;
429 } else if (IndexReg == 0 &&
430 (!AM.GV || !Subtarget->isPICStyleRIPRel()) &&
431 (S == 1 || S == 2 || S == 4 || S == 8)) {
432 // Scaled-index addressing.
434 IndexReg = getRegForGEPIndex(Op).first;
439 goto unsupported_gep;
442 // Check for displacement overflow.
443 if (!isInt<32>(Disp))
445 // Ok, the GEP indices were covered by constant-offset and scaled-index
446 // addressing. Update the address state and move on to examining the base.
447 AM.IndexReg = IndexReg;
449 AM.Disp = (uint32_t)Disp;
450 if (X86SelectAddress(U->getOperand(0), AM))
453 // If we couldn't merge the sub value into this addr mode, revert back to
454 // our address and just match the value instead of completely failing.
458 // Ok, the GEP indices weren't all covered.
463 // Handle constant address.
464 if (const GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
465 // Can't handle alternate code models yet.
466 if (TM.getCodeModel() != CodeModel::Small)
469 // RIP-relative addresses can't have additional register operands.
470 if (Subtarget->isPICStyleRIPRel() &&
471 (AM.Base.Reg != 0 || AM.IndexReg != 0))
474 // Can't handle TLS yet.
475 if (const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV))
476 if (GVar->isThreadLocal())
479 // Okay, we've committed to selecting this global. Set up the basic address.
482 // Allow the subtarget to classify the global.
483 unsigned char GVFlags = Subtarget->ClassifyGlobalReference(GV, TM);
485 // If this reference is relative to the pic base, set it now.
486 if (isGlobalRelativeToPICBase(GVFlags)) {
487 // FIXME: How do we know Base.Reg is free??
488 AM.Base.Reg = getInstrInfo()->getGlobalBaseReg(&MF);
491 // Unless the ABI requires an extra load, return a direct reference to
493 if (!isGlobalStubReference(GVFlags)) {
494 if (Subtarget->isPICStyleRIPRel()) {
495 // Use rip-relative addressing if we can. Above we verified that the
496 // base and index registers are unused.
497 assert(AM.Base.Reg == 0 && AM.IndexReg == 0);
498 AM.Base.Reg = X86::RIP;
500 AM.GVOpFlags = GVFlags;
504 // Ok, we need to do a load from a stub. If we've already loaded from this
505 // stub, reuse the loaded pointer, otherwise emit the load now.
506 DenseMap<const Value*, unsigned>::iterator I = LocalValueMap.find(V);
508 if (I != LocalValueMap.end() && I->second != 0) {
511 // Issue load from stub.
513 const TargetRegisterClass *RC = NULL;
514 X86AddressMode StubAM;
515 StubAM.Base.Reg = AM.Base.Reg;
517 StubAM.GVOpFlags = GVFlags;
519 if (TLI.getPointerTy() == MVT::i64) {
521 RC = X86::GR64RegisterClass;
523 if (Subtarget->isPICStyleRIPRel())
524 StubAM.Base.Reg = X86::RIP;
527 RC = X86::GR32RegisterClass;
530 LoadReg = createResultReg(RC);
531 addFullAddress(BuildMI(MBB, DL, TII.get(Opc), LoadReg), StubAM);
533 // Prevent loading GV stub multiple times in same MBB.
534 LocalValueMap[V] = LoadReg;
537 // Now construct the final address. Note that the Disp, Scale,
538 // and Index values may already be set here.
539 AM.Base.Reg = LoadReg;
544 // If all else fails, try to materialize the value in a register.
545 if (!AM.GV || !Subtarget->isPICStyleRIPRel()) {
546 if (AM.Base.Reg == 0) {
547 AM.Base.Reg = getRegForValue(V);
548 return AM.Base.Reg != 0;
550 if (AM.IndexReg == 0) {
551 assert(AM.Scale == 1 && "Scale with no index!");
552 AM.IndexReg = getRegForValue(V);
553 return AM.IndexReg != 0;
560 /// X86SelectCallAddress - Attempt to fill in an address from the given value.
562 bool X86FastISel::X86SelectCallAddress(const Value *V, X86AddressMode &AM) {
563 const User *U = NULL;
564 unsigned Opcode = Instruction::UserOp1;
565 if (const Instruction *I = dyn_cast<Instruction>(V)) {
566 Opcode = I->getOpcode();
568 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(V)) {
569 Opcode = C->getOpcode();
575 case Instruction::BitCast:
576 // Look past bitcasts.
577 return X86SelectCallAddress(U->getOperand(0), AM);
579 case Instruction::IntToPtr:
580 // Look past no-op inttoptrs.
581 if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
582 return X86SelectCallAddress(U->getOperand(0), AM);
585 case Instruction::PtrToInt:
586 // Look past no-op ptrtoints.
587 if (TLI.getValueType(U->getType()) == TLI.getPointerTy())
588 return X86SelectCallAddress(U->getOperand(0), AM);
592 // Handle constant address.
593 if (const GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
594 // Can't handle alternate code models yet.
595 if (TM.getCodeModel() != CodeModel::Small)
598 // RIP-relative addresses can't have additional register operands.
599 if (Subtarget->isPICStyleRIPRel() &&
600 (AM.Base.Reg != 0 || AM.IndexReg != 0))
603 // Can't handle TLS or DLLImport.
604 if (const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV))
605 if (GVar->isThreadLocal() || GVar->hasDLLImportLinkage())
608 // Okay, we've committed to selecting this global. Set up the basic address.
611 // No ABI requires an extra load for anything other than DLLImport, which
612 // we rejected above. Return a direct reference to the global.
613 if (Subtarget->isPICStyleRIPRel()) {
614 // Use rip-relative addressing if we can. Above we verified that the
615 // base and index registers are unused.
616 assert(AM.Base.Reg == 0 && AM.IndexReg == 0);
617 AM.Base.Reg = X86::RIP;
618 } else if (Subtarget->isPICStyleStubPIC()) {
619 AM.GVOpFlags = X86II::MO_PIC_BASE_OFFSET;
620 } else if (Subtarget->isPICStyleGOT()) {
621 AM.GVOpFlags = X86II::MO_GOTOFF;
627 // If all else fails, try to materialize the value in a register.
628 if (!AM.GV || !Subtarget->isPICStyleRIPRel()) {
629 if (AM.Base.Reg == 0) {
630 AM.Base.Reg = getRegForValue(V);
631 return AM.Base.Reg != 0;
633 if (AM.IndexReg == 0) {
634 assert(AM.Scale == 1 && "Scale with no index!");
635 AM.IndexReg = getRegForValue(V);
636 return AM.IndexReg != 0;
644 /// X86SelectStore - Select and emit code to implement store instructions.
645 bool X86FastISel::X86SelectStore(const Instruction *I) {
647 if (!isTypeLegal(I->getOperand(0)->getType(), VT, /*AllowI1=*/true))
651 if (!X86SelectAddress(I->getOperand(1), AM))
654 return X86FastEmitStore(VT, I->getOperand(0), AM);
657 /// X86SelectLoad - Select and emit code to implement load instructions.
659 bool X86FastISel::X86SelectLoad(const Instruction *I) {
661 if (!isTypeLegal(I->getType(), VT, /*AllowI1=*/true))
665 if (!X86SelectAddress(I->getOperand(0), AM))
668 unsigned ResultReg = 0;
669 if (X86FastEmitLoad(VT, AM, ResultReg)) {
670 UpdateValueMap(I, ResultReg);
676 static unsigned X86ChooseCmpOpcode(EVT VT) {
677 switch (VT.getSimpleVT().SimpleTy) {
679 case MVT::i8: return X86::CMP8rr;
680 case MVT::i16: return X86::CMP16rr;
681 case MVT::i32: return X86::CMP32rr;
682 case MVT::i64: return X86::CMP64rr;
683 case MVT::f32: return X86::UCOMISSrr;
684 case MVT::f64: return X86::UCOMISDrr;
688 /// X86ChooseCmpImmediateOpcode - If we have a comparison with RHS as the RHS
689 /// of the comparison, return an opcode that works for the compare (e.g.
690 /// CMP32ri) otherwise return 0.
691 static unsigned X86ChooseCmpImmediateOpcode(EVT VT, const ConstantInt *RHSC) {
692 switch (VT.getSimpleVT().SimpleTy) {
693 // Otherwise, we can't fold the immediate into this comparison.
695 case MVT::i8: return X86::CMP8ri;
696 case MVT::i16: return X86::CMP16ri;
697 case MVT::i32: return X86::CMP32ri;
699 // 64-bit comparisons are only valid if the immediate fits in a 32-bit sext
701 if ((int)RHSC->getSExtValue() == RHSC->getSExtValue())
702 return X86::CMP64ri32;
707 bool X86FastISel::X86FastEmitCompare(const Value *Op0, const Value *Op1,
709 unsigned Op0Reg = getRegForValue(Op0);
710 if (Op0Reg == 0) return false;
712 // Handle 'null' like i32/i64 0.
713 if (isa<ConstantPointerNull>(Op1))
714 Op1 = Constant::getNullValue(TD.getIntPtrType(Op0->getContext()));
716 // We have two options: compare with register or immediate. If the RHS of
717 // the compare is an immediate that we can fold into this compare, use
718 // CMPri, otherwise use CMPrr.
719 if (const ConstantInt *Op1C = dyn_cast<ConstantInt>(Op1)) {
720 if (unsigned CompareImmOpc = X86ChooseCmpImmediateOpcode(VT, Op1C)) {
721 BuildMI(MBB, DL, TII.get(CompareImmOpc)).addReg(Op0Reg)
722 .addImm(Op1C->getSExtValue());
727 unsigned CompareOpc = X86ChooseCmpOpcode(VT);
728 if (CompareOpc == 0) return false;
730 unsigned Op1Reg = getRegForValue(Op1);
731 if (Op1Reg == 0) return false;
732 BuildMI(MBB, DL, TII.get(CompareOpc)).addReg(Op0Reg).addReg(Op1Reg);
737 bool X86FastISel::X86SelectCmp(const Instruction *I) {
738 const CmpInst *CI = cast<CmpInst>(I);
741 if (!isTypeLegal(I->getOperand(0)->getType(), VT))
744 unsigned ResultReg = createResultReg(&X86::GR8RegClass);
746 bool SwapArgs; // false -> compare Op0, Op1. true -> compare Op1, Op0.
747 switch (CI->getPredicate()) {
748 case CmpInst::FCMP_OEQ: {
749 if (!X86FastEmitCompare(CI->getOperand(0), CI->getOperand(1), VT))
752 unsigned EReg = createResultReg(&X86::GR8RegClass);
753 unsigned NPReg = createResultReg(&X86::GR8RegClass);
754 BuildMI(MBB, DL, TII.get(X86::SETEr), EReg);
755 BuildMI(MBB, DL, TII.get(X86::SETNPr), NPReg);
757 TII.get(X86::AND8rr), ResultReg).addReg(NPReg).addReg(EReg);
758 UpdateValueMap(I, ResultReg);
761 case CmpInst::FCMP_UNE: {
762 if (!X86FastEmitCompare(CI->getOperand(0), CI->getOperand(1), VT))
765 unsigned NEReg = createResultReg(&X86::GR8RegClass);
766 unsigned PReg = createResultReg(&X86::GR8RegClass);
767 BuildMI(MBB, DL, TII.get(X86::SETNEr), NEReg);
768 BuildMI(MBB, DL, TII.get(X86::SETPr), PReg);
769 BuildMI(MBB, DL, TII.get(X86::OR8rr), ResultReg).addReg(PReg).addReg(NEReg);
770 UpdateValueMap(I, ResultReg);
773 case CmpInst::FCMP_OGT: SwapArgs = false; SetCCOpc = X86::SETAr; break;
774 case CmpInst::FCMP_OGE: SwapArgs = false; SetCCOpc = X86::SETAEr; break;
775 case CmpInst::FCMP_OLT: SwapArgs = true; SetCCOpc = X86::SETAr; break;
776 case CmpInst::FCMP_OLE: SwapArgs = true; SetCCOpc = X86::SETAEr; break;
777 case CmpInst::FCMP_ONE: SwapArgs = false; SetCCOpc = X86::SETNEr; break;
778 case CmpInst::FCMP_ORD: SwapArgs = false; SetCCOpc = X86::SETNPr; break;
779 case CmpInst::FCMP_UNO: SwapArgs = false; SetCCOpc = X86::SETPr; break;
780 case CmpInst::FCMP_UEQ: SwapArgs = false; SetCCOpc = X86::SETEr; break;
781 case CmpInst::FCMP_UGT: SwapArgs = true; SetCCOpc = X86::SETBr; break;
782 case CmpInst::FCMP_UGE: SwapArgs = true; SetCCOpc = X86::SETBEr; break;
783 case CmpInst::FCMP_ULT: SwapArgs = false; SetCCOpc = X86::SETBr; break;
784 case CmpInst::FCMP_ULE: SwapArgs = false; SetCCOpc = X86::SETBEr; break;
786 case CmpInst::ICMP_EQ: SwapArgs = false; SetCCOpc = X86::SETEr; break;
787 case CmpInst::ICMP_NE: SwapArgs = false; SetCCOpc = X86::SETNEr; break;
788 case CmpInst::ICMP_UGT: SwapArgs = false; SetCCOpc = X86::SETAr; break;
789 case CmpInst::ICMP_UGE: SwapArgs = false; SetCCOpc = X86::SETAEr; break;
790 case CmpInst::ICMP_ULT: SwapArgs = false; SetCCOpc = X86::SETBr; break;
791 case CmpInst::ICMP_ULE: SwapArgs = false; SetCCOpc = X86::SETBEr; break;
792 case CmpInst::ICMP_SGT: SwapArgs = false; SetCCOpc = X86::SETGr; break;
793 case CmpInst::ICMP_SGE: SwapArgs = false; SetCCOpc = X86::SETGEr; break;
794 case CmpInst::ICMP_SLT: SwapArgs = false; SetCCOpc = X86::SETLr; break;
795 case CmpInst::ICMP_SLE: SwapArgs = false; SetCCOpc = X86::SETLEr; break;
800 const Value *Op0 = CI->getOperand(0), *Op1 = CI->getOperand(1);
804 // Emit a compare of Op0/Op1.
805 if (!X86FastEmitCompare(Op0, Op1, VT))
808 BuildMI(MBB, DL, TII.get(SetCCOpc), ResultReg);
809 UpdateValueMap(I, ResultReg);
813 bool X86FastISel::X86SelectZExt(const Instruction *I) {
814 // Handle zero-extension from i1 to i8, which is common.
815 if (I->getType()->isIntegerTy(8) &&
816 I->getOperand(0)->getType()->isIntegerTy(1)) {
817 unsigned ResultReg = getRegForValue(I->getOperand(0));
818 if (ResultReg == 0) return false;
819 // Set the high bits to zero.
820 ResultReg = FastEmitZExtFromI1(MVT::i8, ResultReg, /*TODO: Kill=*/false);
821 if (ResultReg == 0) return false;
822 UpdateValueMap(I, ResultReg);
830 bool X86FastISel::X86SelectBranch(const Instruction *I) {
831 // Unconditional branches are selected by tablegen-generated code.
832 // Handle a conditional branch.
833 const BranchInst *BI = cast<BranchInst>(I);
834 MachineBasicBlock *TrueMBB = MBBMap[BI->getSuccessor(0)];
835 MachineBasicBlock *FalseMBB = MBBMap[BI->getSuccessor(1)];
837 // Fold the common case of a conditional branch with a comparison.
838 if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
839 if (CI->hasOneUse()) {
840 EVT VT = TLI.getValueType(CI->getOperand(0)->getType());
842 // Try to take advantage of fallthrough opportunities.
843 CmpInst::Predicate Predicate = CI->getPredicate();
844 if (MBB->isLayoutSuccessor(TrueMBB)) {
845 std::swap(TrueMBB, FalseMBB);
846 Predicate = CmpInst::getInversePredicate(Predicate);
849 bool SwapArgs; // false -> compare Op0, Op1. true -> compare Op1, Op0.
850 unsigned BranchOpc; // Opcode to jump on, e.g. "X86::JA"
853 case CmpInst::FCMP_OEQ:
854 std::swap(TrueMBB, FalseMBB);
855 Predicate = CmpInst::FCMP_UNE;
857 case CmpInst::FCMP_UNE: SwapArgs = false; BranchOpc = X86::JNE_4; break;
858 case CmpInst::FCMP_OGT: SwapArgs = false; BranchOpc = X86::JA_4; break;
859 case CmpInst::FCMP_OGE: SwapArgs = false; BranchOpc = X86::JAE_4; break;
860 case CmpInst::FCMP_OLT: SwapArgs = true; BranchOpc = X86::JA_4; break;
861 case CmpInst::FCMP_OLE: SwapArgs = true; BranchOpc = X86::JAE_4; break;
862 case CmpInst::FCMP_ONE: SwapArgs = false; BranchOpc = X86::JNE_4; break;
863 case CmpInst::FCMP_ORD: SwapArgs = false; BranchOpc = X86::JNP_4; break;
864 case CmpInst::FCMP_UNO: SwapArgs = false; BranchOpc = X86::JP_4; break;
865 case CmpInst::FCMP_UEQ: SwapArgs = false; BranchOpc = X86::JE_4; break;
866 case CmpInst::FCMP_UGT: SwapArgs = true; BranchOpc = X86::JB_4; break;
867 case CmpInst::FCMP_UGE: SwapArgs = true; BranchOpc = X86::JBE_4; break;
868 case CmpInst::FCMP_ULT: SwapArgs = false; BranchOpc = X86::JB_4; break;
869 case CmpInst::FCMP_ULE: SwapArgs = false; BranchOpc = X86::JBE_4; break;
871 case CmpInst::ICMP_EQ: SwapArgs = false; BranchOpc = X86::JE_4; break;
872 case CmpInst::ICMP_NE: SwapArgs = false; BranchOpc = X86::JNE_4; break;
873 case CmpInst::ICMP_UGT: SwapArgs = false; BranchOpc = X86::JA_4; break;
874 case CmpInst::ICMP_UGE: SwapArgs = false; BranchOpc = X86::JAE_4; break;
875 case CmpInst::ICMP_ULT: SwapArgs = false; BranchOpc = X86::JB_4; break;
876 case CmpInst::ICMP_ULE: SwapArgs = false; BranchOpc = X86::JBE_4; break;
877 case CmpInst::ICMP_SGT: SwapArgs = false; BranchOpc = X86::JG_4; break;
878 case CmpInst::ICMP_SGE: SwapArgs = false; BranchOpc = X86::JGE_4; break;
879 case CmpInst::ICMP_SLT: SwapArgs = false; BranchOpc = X86::JL_4; break;
880 case CmpInst::ICMP_SLE: SwapArgs = false; BranchOpc = X86::JLE_4; break;
885 const Value *Op0 = CI->getOperand(0), *Op1 = CI->getOperand(1);
889 // Emit a compare of the LHS and RHS, setting the flags.
890 if (!X86FastEmitCompare(Op0, Op1, VT))
893 BuildMI(MBB, DL, TII.get(BranchOpc)).addMBB(TrueMBB);
895 if (Predicate == CmpInst::FCMP_UNE) {
896 // X86 requires a second branch to handle UNE (and OEQ,
897 // which is mapped to UNE above).
898 BuildMI(MBB, DL, TII.get(X86::JP_4)).addMBB(TrueMBB);
901 FastEmitBranch(FalseMBB, DL);
902 MBB->addSuccessor(TrueMBB);
905 } else if (ExtractValueInst *EI =
906 dyn_cast<ExtractValueInst>(BI->getCondition())) {
907 // Check to see if the branch instruction is from an "arithmetic with
908 // overflow" intrinsic. The main way these intrinsics are used is:
910 // %t = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %v1, i32 %v2)
911 // %sum = extractvalue { i32, i1 } %t, 0
912 // %obit = extractvalue { i32, i1 } %t, 1
913 // br i1 %obit, label %overflow, label %normal
915 // The %sum and %obit are converted in an ADD and a SETO/SETB before
916 // reaching the branch. Therefore, we search backwards through the MBB
917 // looking for the SETO/SETB instruction. If an instruction modifies the
918 // EFLAGS register before we reach the SETO/SETB instruction, then we can't
919 // convert the branch into a JO/JB instruction.
920 if (const IntrinsicInst *CI =
921 dyn_cast<IntrinsicInst>(EI->getAggregateOperand())){
922 if (CI->getIntrinsicID() == Intrinsic::sadd_with_overflow ||
923 CI->getIntrinsicID() == Intrinsic::uadd_with_overflow) {
924 const MachineInstr *SetMI = 0;
925 unsigned Reg = lookUpRegForValue(EI);
927 for (MachineBasicBlock::const_reverse_iterator
928 RI = MBB->rbegin(), RE = MBB->rend(); RI != RE; ++RI) {
929 const MachineInstr &MI = *RI;
931 if (MI.definesRegister(Reg)) {
932 unsigned Src, Dst, SrcSR, DstSR;
934 if (getInstrInfo()->isMoveInstr(MI, Src, Dst, SrcSR, DstSR)) {
943 const TargetInstrDesc &TID = MI.getDesc();
944 if (TID.hasUnmodeledSideEffects() ||
945 TID.hasImplicitDefOfPhysReg(X86::EFLAGS))
950 unsigned OpCode = SetMI->getOpcode();
952 if (OpCode == X86::SETOr || OpCode == X86::SETBr) {
953 BuildMI(MBB, DL, TII.get(OpCode == X86::SETOr ?
954 X86::JO_4 : X86::JB_4))
956 FastEmitBranch(FalseMBB, DL);
957 MBB->addSuccessor(TrueMBB);
965 // Otherwise do a clumsy setcc and re-test it.
966 unsigned OpReg = getRegForValue(BI->getCondition());
967 if (OpReg == 0) return false;
969 BuildMI(MBB, DL, TII.get(X86::TEST8rr)).addReg(OpReg).addReg(OpReg);
970 BuildMI(MBB, DL, TII.get(X86::JNE_4)).addMBB(TrueMBB);
971 FastEmitBranch(FalseMBB, DL);
972 MBB->addSuccessor(TrueMBB);
976 bool X86FastISel::X86SelectShift(const Instruction *I) {
977 unsigned CReg = 0, OpReg = 0, OpImm = 0;
978 const TargetRegisterClass *RC = NULL;
979 if (I->getType()->isIntegerTy(8)) {
981 RC = &X86::GR8RegClass;
982 switch (I->getOpcode()) {
983 case Instruction::LShr: OpReg = X86::SHR8rCL; OpImm = X86::SHR8ri; break;
984 case Instruction::AShr: OpReg = X86::SAR8rCL; OpImm = X86::SAR8ri; break;
985 case Instruction::Shl: OpReg = X86::SHL8rCL; OpImm = X86::SHL8ri; break;
986 default: return false;
988 } else if (I->getType()->isIntegerTy(16)) {
990 RC = &X86::GR16RegClass;
991 switch (I->getOpcode()) {
992 case Instruction::LShr: OpReg = X86::SHR16rCL; OpImm = X86::SHR16ri; break;
993 case Instruction::AShr: OpReg = X86::SAR16rCL; OpImm = X86::SAR16ri; break;
994 case Instruction::Shl: OpReg = X86::SHL16rCL; OpImm = X86::SHL16ri; break;
995 default: return false;
997 } else if (I->getType()->isIntegerTy(32)) {
999 RC = &X86::GR32RegClass;
1000 switch (I->getOpcode()) {
1001 case Instruction::LShr: OpReg = X86::SHR32rCL; OpImm = X86::SHR32ri; break;
1002 case Instruction::AShr: OpReg = X86::SAR32rCL; OpImm = X86::SAR32ri; break;
1003 case Instruction::Shl: OpReg = X86::SHL32rCL; OpImm = X86::SHL32ri; break;
1004 default: return false;
1006 } else if (I->getType()->isIntegerTy(64)) {
1008 RC = &X86::GR64RegClass;
1009 switch (I->getOpcode()) {
1010 case Instruction::LShr: OpReg = X86::SHR64rCL; OpImm = X86::SHR64ri; break;
1011 case Instruction::AShr: OpReg = X86::SAR64rCL; OpImm = X86::SAR64ri; break;
1012 case Instruction::Shl: OpReg = X86::SHL64rCL; OpImm = X86::SHL64ri; break;
1013 default: return false;
1019 EVT VT = TLI.getValueType(I->getType(), /*HandleUnknown=*/true);
1020 if (VT == MVT::Other || !isTypeLegal(I->getType(), VT))
1023 unsigned Op0Reg = getRegForValue(I->getOperand(0));
1024 if (Op0Reg == 0) return false;
1026 // Fold immediate in shl(x,3).
1027 if (const ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) {
1028 unsigned ResultReg = createResultReg(RC);
1029 BuildMI(MBB, DL, TII.get(OpImm),
1030 ResultReg).addReg(Op0Reg).addImm(CI->getZExtValue() & 0xff);
1031 UpdateValueMap(I, ResultReg);
1035 unsigned Op1Reg = getRegForValue(I->getOperand(1));
1036 if (Op1Reg == 0) return false;
1037 TII.copyRegToReg(*MBB, MBB->end(), CReg, Op1Reg, RC, RC, DL);
1039 // The shift instruction uses X86::CL. If we defined a super-register
1040 // of X86::CL, emit an EXTRACT_SUBREG to precisely describe what
1041 // we're doing here.
1042 if (CReg != X86::CL)
1043 BuildMI(MBB, DL, TII.get(TargetOpcode::EXTRACT_SUBREG), X86::CL)
1044 .addReg(CReg).addImm(X86::sub_8bit);
1046 unsigned ResultReg = createResultReg(RC);
1047 BuildMI(MBB, DL, TII.get(OpReg), ResultReg).addReg(Op0Reg);
1048 UpdateValueMap(I, ResultReg);
1052 bool X86FastISel::X86SelectSelect(const Instruction *I) {
1053 EVT VT = TLI.getValueType(I->getType(), /*HandleUnknown=*/true);
1054 if (VT == MVT::Other || !isTypeLegal(I->getType(), VT))
1058 const TargetRegisterClass *RC = NULL;
1059 if (VT.getSimpleVT() == MVT::i16) {
1060 Opc = X86::CMOVE16rr;
1061 RC = &X86::GR16RegClass;
1062 } else if (VT.getSimpleVT() == MVT::i32) {
1063 Opc = X86::CMOVE32rr;
1064 RC = &X86::GR32RegClass;
1065 } else if (VT.getSimpleVT() == MVT::i64) {
1066 Opc = X86::CMOVE64rr;
1067 RC = &X86::GR64RegClass;
1072 unsigned Op0Reg = getRegForValue(I->getOperand(0));
1073 if (Op0Reg == 0) return false;
1074 unsigned Op1Reg = getRegForValue(I->getOperand(1));
1075 if (Op1Reg == 0) return false;
1076 unsigned Op2Reg = getRegForValue(I->getOperand(2));
1077 if (Op2Reg == 0) return false;
1079 BuildMI(MBB, DL, TII.get(X86::TEST8rr)).addReg(Op0Reg).addReg(Op0Reg);
1080 unsigned ResultReg = createResultReg(RC);
1081 BuildMI(MBB, DL, TII.get(Opc), ResultReg).addReg(Op1Reg).addReg(Op2Reg);
1082 UpdateValueMap(I, ResultReg);
1086 bool X86FastISel::X86SelectFPExt(const Instruction *I) {
1087 // fpext from float to double.
1088 if (Subtarget->hasSSE2() &&
1089 I->getType()->isDoubleTy()) {
1090 const Value *V = I->getOperand(0);
1091 if (V->getType()->isFloatTy()) {
1092 unsigned OpReg = getRegForValue(V);
1093 if (OpReg == 0) return false;
1094 unsigned ResultReg = createResultReg(X86::FR64RegisterClass);
1095 BuildMI(MBB, DL, TII.get(X86::CVTSS2SDrr), ResultReg).addReg(OpReg);
1096 UpdateValueMap(I, ResultReg);
1104 bool X86FastISel::X86SelectFPTrunc(const Instruction *I) {
1105 if (Subtarget->hasSSE2()) {
1106 if (I->getType()->isFloatTy()) {
1107 const Value *V = I->getOperand(0);
1108 if (V->getType()->isDoubleTy()) {
1109 unsigned OpReg = getRegForValue(V);
1110 if (OpReg == 0) return false;
1111 unsigned ResultReg = createResultReg(X86::FR32RegisterClass);
1112 BuildMI(MBB, DL, TII.get(X86::CVTSD2SSrr), ResultReg).addReg(OpReg);
1113 UpdateValueMap(I, ResultReg);
1122 bool X86FastISel::X86SelectTrunc(const Instruction *I) {
1123 if (Subtarget->is64Bit())
1124 // All other cases should be handled by the tblgen generated code.
1126 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
1127 EVT DstVT = TLI.getValueType(I->getType());
1129 // This code only handles truncation to byte right now.
1130 if (DstVT != MVT::i8 && DstVT != MVT::i1)
1131 // All other cases should be handled by the tblgen generated code.
1133 if (SrcVT != MVT::i16 && SrcVT != MVT::i32)
1134 // All other cases should be handled by the tblgen generated code.
1137 unsigned InputReg = getRegForValue(I->getOperand(0));
1139 // Unhandled operand. Halt "fast" selection and bail.
1142 // First issue a copy to GR16_ABCD or GR32_ABCD.
1143 unsigned CopyOpc = (SrcVT == MVT::i16) ? X86::MOV16rr : X86::MOV32rr;
1144 const TargetRegisterClass *CopyRC = (SrcVT == MVT::i16)
1145 ? X86::GR16_ABCDRegisterClass : X86::GR32_ABCDRegisterClass;
1146 unsigned CopyReg = createResultReg(CopyRC);
1147 BuildMI(MBB, DL, TII.get(CopyOpc), CopyReg).addReg(InputReg);
1149 // Then issue an extract_subreg.
1150 unsigned ResultReg = FastEmitInst_extractsubreg(MVT::i8,
1151 CopyReg, /*Kill=*/true,
1156 UpdateValueMap(I, ResultReg);
1160 bool X86FastISel::X86SelectExtractValue(const Instruction *I) {
1161 const ExtractValueInst *EI = cast<ExtractValueInst>(I);
1162 const Value *Agg = EI->getAggregateOperand();
1164 if (const IntrinsicInst *CI = dyn_cast<IntrinsicInst>(Agg)) {
1165 switch (CI->getIntrinsicID()) {
1167 case Intrinsic::sadd_with_overflow:
1168 case Intrinsic::uadd_with_overflow:
1169 // Cheat a little. We know that the registers for "add" and "seto" are
1170 // allocated sequentially. However, we only keep track of the register
1171 // for "add" in the value map. Use extractvalue's index to get the
1172 // correct register for "seto".
1173 UpdateValueMap(I, lookUpRegForValue(Agg) + *EI->idx_begin());
1181 bool X86FastISel::X86VisitIntrinsicCall(const IntrinsicInst &I) {
1182 // FIXME: Handle more intrinsics.
1183 switch (I.getIntrinsicID()) {
1184 default: return false;
1185 case Intrinsic::stackprotector: {
1186 // Emit code inline code to store the stack guard onto the stack.
1187 EVT PtrTy = TLI.getPointerTy();
1189 const Value *Op1 = I.getOperand(1); // The guard's value.
1190 const AllocaInst *Slot = cast<AllocaInst>(I.getOperand(2));
1192 // Grab the frame index.
1194 if (!X86SelectAddress(Slot, AM)) return false;
1196 if (!X86FastEmitStore(PtrTy, Op1, AM)) return false;
1200 case Intrinsic::objectsize: {
1201 ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(2));
1202 const Type *Ty = I.getCalledFunction()->getReturnType();
1204 assert(CI && "Non-constant type in Intrinsic::objectsize?");
1207 if (!isTypeLegal(Ty, VT))
1213 else if (VT == MVT::i64)
1218 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
1219 BuildMI(MBB, DL, TII.get(OpC), ResultReg).
1220 addImm(CI->isZero() ? -1ULL : 0);
1221 UpdateValueMap(&I, ResultReg);
1224 case Intrinsic::dbg_declare: {
1225 const DbgDeclareInst *DI = cast<DbgDeclareInst>(&I);
1227 assert(DI->getAddress() && "Null address should be checked earlier!");
1228 if (!X86SelectAddress(DI->getAddress(), AM))
1230 const TargetInstrDesc &II = TII.get(TargetOpcode::DBG_VALUE);
1231 // FIXME may need to add RegState::Debug to any registers produced,
1232 // although ESP/EBP should be the only ones at the moment.
1233 addFullAddress(BuildMI(MBB, DL, II), AM).addImm(0).
1234 addMetadata(DI->getVariable());
1237 case Intrinsic::trap: {
1238 BuildMI(MBB, DL, TII.get(X86::TRAP));
1241 case Intrinsic::sadd_with_overflow:
1242 case Intrinsic::uadd_with_overflow: {
1243 // Replace "add with overflow" intrinsics with an "add" instruction followed
1244 // by a seto/setc instruction. Later on, when the "extractvalue"
1245 // instructions are encountered, we use the fact that two registers were
1246 // created sequentially to get the correct registers for the "sum" and the
1248 const Function *Callee = I.getCalledFunction();
1250 cast<StructType>(Callee->getReturnType())->getTypeAtIndex(unsigned(0));
1253 if (!isTypeLegal(RetTy, VT))
1256 const Value *Op1 = I.getOperand(1);
1257 const Value *Op2 = I.getOperand(2);
1258 unsigned Reg1 = getRegForValue(Op1);
1259 unsigned Reg2 = getRegForValue(Op2);
1261 if (Reg1 == 0 || Reg2 == 0)
1262 // FIXME: Handle values *not* in registers.
1268 else if (VT == MVT::i64)
1273 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
1274 BuildMI(MBB, DL, TII.get(OpC), ResultReg).addReg(Reg1).addReg(Reg2);
1275 unsigned DestReg1 = UpdateValueMap(&I, ResultReg);
1277 // If the add with overflow is an intra-block value then we just want to
1278 // create temporaries for it like normal. If it is a cross-block value then
1279 // UpdateValueMap will return the cross-block register used. Since we
1280 // *really* want the value to be live in the register pair known by
1281 // UpdateValueMap, we have to use DestReg1+1 as the destination register in
1282 // the cross block case. In the non-cross-block case, we should just make
1283 // another register for the value.
1284 if (DestReg1 != ResultReg)
1285 ResultReg = DestReg1+1;
1287 ResultReg = createResultReg(TLI.getRegClassFor(MVT::i8));
1289 unsigned Opc = X86::SETBr;
1290 if (I.getIntrinsicID() == Intrinsic::sadd_with_overflow)
1292 BuildMI(MBB, DL, TII.get(Opc), ResultReg);
1298 bool X86FastISel::X86SelectCall(const Instruction *I) {
1299 const CallInst *CI = cast<CallInst>(I);
1300 const Value *Callee = I->getOperand(0);
1302 // Can't handle inline asm yet.
1303 if (isa<InlineAsm>(Callee))
1306 // Handle intrinsic calls.
1307 if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(CI))
1308 return X86VisitIntrinsicCall(*II);
1310 // Handle only C and fastcc calling conventions for now.
1311 ImmutableCallSite CS(CI);
1312 CallingConv::ID CC = CS.getCallingConv();
1313 if (CC != CallingConv::C &&
1314 CC != CallingConv::Fast &&
1315 CC != CallingConv::X86_FastCall)
1318 // fastcc with -tailcallopt is intended to provide a guaranteed
1319 // tail call optimization. Fastisel doesn't know how to do that.
1320 if (CC == CallingConv::Fast && GuaranteedTailCallOpt)
1323 // Let SDISel handle vararg functions.
1324 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
1325 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
1326 if (FTy->isVarArg())
1329 // Fast-isel doesn't know about callee-pop yet.
1330 if (Subtarget->IsCalleePop(FTy->isVarArg(), CC))
1333 // Handle *simple* calls for now.
1334 const Type *RetTy = CS.getType();
1336 if (RetTy->isVoidTy())
1337 RetVT = MVT::isVoid;
1338 else if (!isTypeLegal(RetTy, RetVT, true))
1341 // Materialize callee address in a register. FIXME: GV address can be
1342 // handled with a CALLpcrel32 instead.
1343 X86AddressMode CalleeAM;
1344 if (!X86SelectCallAddress(Callee, CalleeAM))
1346 unsigned CalleeOp = 0;
1347 const GlobalValue *GV = 0;
1348 if (CalleeAM.GV != 0) {
1350 } else if (CalleeAM.Base.Reg != 0) {
1351 CalleeOp = CalleeAM.Base.Reg;
1355 // Allow calls which produce i1 results.
1356 bool AndToI1 = false;
1357 if (RetVT == MVT::i1) {
1362 // Deal with call operands first.
1363 SmallVector<const Value *, 8> ArgVals;
1364 SmallVector<unsigned, 8> Args;
1365 SmallVector<EVT, 8> ArgVTs;
1366 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
1367 Args.reserve(CS.arg_size());
1368 ArgVals.reserve(CS.arg_size());
1369 ArgVTs.reserve(CS.arg_size());
1370 ArgFlags.reserve(CS.arg_size());
1371 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
1373 unsigned Arg = getRegForValue(*i);
1376 ISD::ArgFlagsTy Flags;
1377 unsigned AttrInd = i - CS.arg_begin() + 1;
1378 if (CS.paramHasAttr(AttrInd, Attribute::SExt))
1380 if (CS.paramHasAttr(AttrInd, Attribute::ZExt))
1383 // FIXME: Only handle *easy* calls for now.
1384 if (CS.paramHasAttr(AttrInd, Attribute::InReg) ||
1385 CS.paramHasAttr(AttrInd, Attribute::StructRet) ||
1386 CS.paramHasAttr(AttrInd, Attribute::Nest) ||
1387 CS.paramHasAttr(AttrInd, Attribute::ByVal))
1390 const Type *ArgTy = (*i)->getType();
1392 if (!isTypeLegal(ArgTy, ArgVT))
1394 unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
1395 Flags.setOrigAlign(OriginalAlignment);
1397 Args.push_back(Arg);
1398 ArgVals.push_back(*i);
1399 ArgVTs.push_back(ArgVT);
1400 ArgFlags.push_back(Flags);
1403 // Analyze operands of the call, assigning locations to each operand.
1404 SmallVector<CCValAssign, 16> ArgLocs;
1405 CCState CCInfo(CC, false, TM, ArgLocs, I->getParent()->getContext());
1407 // Allocate shadow area for Win64
1408 if (Subtarget->isTargetWin64()) {
1409 CCInfo.AllocateStack(32, 8);
1412 CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, CCAssignFnForCall(CC));
1414 // Get a count of how many bytes are to be pushed on the stack.
1415 unsigned NumBytes = CCInfo.getNextStackOffset();
1417 // Issue CALLSEQ_START
1418 unsigned AdjStackDown = TM.getRegisterInfo()->getCallFrameSetupOpcode();
1419 BuildMI(MBB, DL, TII.get(AdjStackDown)).addImm(NumBytes);
1421 // Process argument: walk the register/memloc assignments, inserting
1423 SmallVector<unsigned, 4> RegArgs;
1424 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1425 CCValAssign &VA = ArgLocs[i];
1426 unsigned Arg = Args[VA.getValNo()];
1427 EVT ArgVT = ArgVTs[VA.getValNo()];
1429 // Promote the value if needed.
1430 switch (VA.getLocInfo()) {
1431 default: llvm_unreachable("Unknown loc info!");
1432 case CCValAssign::Full: break;
1433 case CCValAssign::SExt: {
1434 bool Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(),
1436 assert(Emitted && "Failed to emit a sext!"); Emitted=Emitted;
1438 ArgVT = VA.getLocVT();
1441 case CCValAssign::ZExt: {
1442 bool Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(),
1444 assert(Emitted && "Failed to emit a zext!"); Emitted=Emitted;
1446 ArgVT = VA.getLocVT();
1449 case CCValAssign::AExt: {
1450 bool Emitted = X86FastEmitExtend(ISD::ANY_EXTEND, VA.getLocVT(),
1453 Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(),
1456 Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(),
1459 assert(Emitted && "Failed to emit a aext!"); Emitted=Emitted;
1460 ArgVT = VA.getLocVT();
1463 case CCValAssign::BCvt: {
1464 unsigned BC = FastEmit_r(ArgVT.getSimpleVT(), VA.getLocVT().getSimpleVT(),
1465 ISD::BIT_CONVERT, Arg, /*TODO: Kill=*/false);
1466 assert(BC != 0 && "Failed to emit a bitcast!");
1468 ArgVT = VA.getLocVT();
1473 if (VA.isRegLoc()) {
1474 TargetRegisterClass* RC = TLI.getRegClassFor(ArgVT);
1475 bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), VA.getLocReg(),
1477 assert(Emitted && "Failed to emit a copy instruction!"); Emitted=Emitted;
1479 RegArgs.push_back(VA.getLocReg());
1481 unsigned LocMemOffset = VA.getLocMemOffset();
1483 AM.Base.Reg = StackPtr;
1484 AM.Disp = LocMemOffset;
1485 const Value *ArgVal = ArgVals[VA.getValNo()];
1487 // If this is a really simple value, emit this with the Value* version of
1488 // X86FastEmitStore. If it isn't simple, we don't want to do this, as it
1489 // can cause us to reevaluate the argument.
1490 if (isa<ConstantInt>(ArgVal) || isa<ConstantPointerNull>(ArgVal))
1491 X86FastEmitStore(ArgVT, ArgVal, AM);
1493 X86FastEmitStore(ArgVT, Arg, AM);
1497 // ELF / PIC requires GOT in the EBX register before function calls via PLT
1499 if (Subtarget->isPICStyleGOT()) {
1500 TargetRegisterClass *RC = X86::GR32RegisterClass;
1501 unsigned Base = getInstrInfo()->getGlobalBaseReg(&MF);
1502 bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), X86::EBX, Base, RC, RC,
1504 assert(Emitted && "Failed to emit a copy instruction!"); Emitted=Emitted;
1509 MachineInstrBuilder MIB;
1511 // Register-indirect call.
1512 unsigned CallOpc = Subtarget->is64Bit() ? X86::CALL64r : X86::CALL32r;
1513 MIB = BuildMI(MBB, DL, TII.get(CallOpc)).addReg(CalleeOp);
1517 assert(GV && "Not a direct call");
1519 Subtarget->is64Bit() ? X86::CALL64pcrel32 : X86::CALLpcrel32;
1521 // See if we need any target-specific flags on the GV operand.
1522 unsigned char OpFlags = 0;
1524 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
1525 // external symbols most go through the PLT in PIC mode. If the symbol
1526 // has hidden or protected visibility, or if it is static or local, then
1527 // we don't need to use the PLT - we can directly call it.
1528 if (Subtarget->isTargetELF() &&
1529 TM.getRelocationModel() == Reloc::PIC_ &&
1530 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
1531 OpFlags = X86II::MO_PLT;
1532 } else if (Subtarget->isPICStyleStubAny() &&
1533 (GV->isDeclaration() || GV->isWeakForLinker()) &&
1534 Subtarget->getDarwinVers() < 9) {
1535 // PC-relative references to external symbols should go through $stub,
1536 // unless we're building with the leopard linker or later, which
1537 // automatically synthesizes these stubs.
1538 OpFlags = X86II::MO_DARWIN_STUB;
1542 MIB = BuildMI(MBB, DL, TII.get(CallOpc)).addGlobalAddress(GV, 0, OpFlags);
1545 // Add an implicit use GOT pointer in EBX.
1546 if (Subtarget->isPICStyleGOT())
1547 MIB.addReg(X86::EBX);
1549 // Add implicit physical register uses to the call.
1550 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
1551 MIB.addReg(RegArgs[i]);
1553 // Issue CALLSEQ_END
1554 unsigned AdjStackUp = TM.getRegisterInfo()->getCallFrameDestroyOpcode();
1555 BuildMI(MBB, DL, TII.get(AdjStackUp)).addImm(NumBytes).addImm(0);
1557 // Now handle call return value (if any).
1558 if (RetVT.getSimpleVT().SimpleTy != MVT::isVoid) {
1559 SmallVector<CCValAssign, 16> RVLocs;
1560 CCState CCInfo(CC, false, TM, RVLocs, I->getParent()->getContext());
1561 CCInfo.AnalyzeCallResult(RetVT, RetCC_X86);
1563 // Copy all of the result registers out of their specified physreg.
1564 assert(RVLocs.size() == 1 && "Can't handle multi-value calls!");
1565 EVT CopyVT = RVLocs[0].getValVT();
1566 TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT);
1567 TargetRegisterClass *SrcRC = DstRC;
1569 // If this is a call to a function that returns an fp value on the x87 fp
1570 // stack, but where we prefer to use the value in xmm registers, copy it
1571 // out as F80 and use a truncate to move it from fp stack reg to xmm reg.
1572 if ((RVLocs[0].getLocReg() == X86::ST0 ||
1573 RVLocs[0].getLocReg() == X86::ST1) &&
1574 isScalarFPTypeInSSEReg(RVLocs[0].getValVT())) {
1576 SrcRC = X86::RSTRegisterClass;
1577 DstRC = X86::RFP80RegisterClass;
1580 unsigned ResultReg = createResultReg(DstRC);
1581 bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
1582 RVLocs[0].getLocReg(), DstRC, SrcRC, DL);
1583 assert(Emitted && "Failed to emit a copy instruction!"); Emitted=Emitted;
1585 if (CopyVT != RVLocs[0].getValVT()) {
1586 // Round the F80 the right size, which also moves to the appropriate xmm
1587 // register. This is accomplished by storing the F80 value in memory and
1588 // then loading it back. Ewww...
1589 EVT ResVT = RVLocs[0].getValVT();
1590 unsigned Opc = ResVT == MVT::f32 ? X86::ST_Fp80m32 : X86::ST_Fp80m64;
1591 unsigned MemSize = ResVT.getSizeInBits()/8;
1592 int FI = MFI.CreateStackObject(MemSize, MemSize, false);
1593 addFrameReference(BuildMI(MBB, DL, TII.get(Opc)), FI).addReg(ResultReg);
1594 DstRC = ResVT == MVT::f32
1595 ? X86::FR32RegisterClass : X86::FR64RegisterClass;
1596 Opc = ResVT == MVT::f32 ? X86::MOVSSrm : X86::MOVSDrm;
1597 ResultReg = createResultReg(DstRC);
1598 addFrameReference(BuildMI(MBB, DL, TII.get(Opc), ResultReg), FI);
1602 // Mask out all but lowest bit for some call which produces an i1.
1603 unsigned AndResult = createResultReg(X86::GR8RegisterClass);
1605 TII.get(X86::AND8ri), AndResult).addReg(ResultReg).addImm(1);
1606 ResultReg = AndResult;
1609 UpdateValueMap(I, ResultReg);
1617 X86FastISel::TargetSelectInstruction(const Instruction *I) {
1618 switch (I->getOpcode()) {
1620 case Instruction::Load:
1621 return X86SelectLoad(I);
1622 case Instruction::Store:
1623 return X86SelectStore(I);
1624 case Instruction::ICmp:
1625 case Instruction::FCmp:
1626 return X86SelectCmp(I);
1627 case Instruction::ZExt:
1628 return X86SelectZExt(I);
1629 case Instruction::Br:
1630 return X86SelectBranch(I);
1631 case Instruction::Call:
1632 return X86SelectCall(I);
1633 case Instruction::LShr:
1634 case Instruction::AShr:
1635 case Instruction::Shl:
1636 return X86SelectShift(I);
1637 case Instruction::Select:
1638 return X86SelectSelect(I);
1639 case Instruction::Trunc:
1640 return X86SelectTrunc(I);
1641 case Instruction::FPExt:
1642 return X86SelectFPExt(I);
1643 case Instruction::FPTrunc:
1644 return X86SelectFPTrunc(I);
1645 case Instruction::ExtractValue:
1646 return X86SelectExtractValue(I);
1647 case Instruction::IntToPtr: // Deliberate fall-through.
1648 case Instruction::PtrToInt: {
1649 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
1650 EVT DstVT = TLI.getValueType(I->getType());
1651 if (DstVT.bitsGT(SrcVT))
1652 return X86SelectZExt(I);
1653 if (DstVT.bitsLT(SrcVT))
1654 return X86SelectTrunc(I);
1655 unsigned Reg = getRegForValue(I->getOperand(0));
1656 if (Reg == 0) return false;
1657 UpdateValueMap(I, Reg);
1665 unsigned X86FastISel::TargetMaterializeConstant(const Constant *C) {
1667 if (!isTypeLegal(C->getType(), VT))
1670 // Get opcode and regclass of the output for the given load instruction.
1672 const TargetRegisterClass *RC = NULL;
1673 switch (VT.getSimpleVT().SimpleTy) {
1674 default: return false;
1677 RC = X86::GR8RegisterClass;
1681 RC = X86::GR16RegisterClass;
1685 RC = X86::GR32RegisterClass;
1688 // Must be in x86-64 mode.
1690 RC = X86::GR64RegisterClass;
1693 if (Subtarget->hasSSE1()) {
1695 RC = X86::FR32RegisterClass;
1697 Opc = X86::LD_Fp32m;
1698 RC = X86::RFP32RegisterClass;
1702 if (Subtarget->hasSSE2()) {
1704 RC = X86::FR64RegisterClass;
1706 Opc = X86::LD_Fp64m;
1707 RC = X86::RFP64RegisterClass;
1711 // No f80 support yet.
1715 // Materialize addresses with LEA instructions.
1716 if (isa<GlobalValue>(C)) {
1718 if (X86SelectAddress(C, AM)) {
1719 if (TLI.getPointerTy() == MVT::i32)
1723 unsigned ResultReg = createResultReg(RC);
1724 addLeaAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), AM);
1730 // MachineConstantPool wants an explicit alignment.
1731 unsigned Align = TD.getPrefTypeAlignment(C->getType());
1733 // Alignment of vector types. FIXME!
1734 Align = TD.getTypeAllocSize(C->getType());
1737 // x86-32 PIC requires a PIC base register for constant pools.
1738 unsigned PICBase = 0;
1739 unsigned char OpFlag = 0;
1740 if (Subtarget->isPICStyleStubPIC()) { // Not dynamic-no-pic
1741 OpFlag = X86II::MO_PIC_BASE_OFFSET;
1742 PICBase = getInstrInfo()->getGlobalBaseReg(&MF);
1743 } else if (Subtarget->isPICStyleGOT()) {
1744 OpFlag = X86II::MO_GOTOFF;
1745 PICBase = getInstrInfo()->getGlobalBaseReg(&MF);
1746 } else if (Subtarget->isPICStyleRIPRel() &&
1747 TM.getCodeModel() == CodeModel::Small) {
1751 // Create the load from the constant pool.
1752 unsigned MCPOffset = MCP.getConstantPoolIndex(C, Align);
1753 unsigned ResultReg = createResultReg(RC);
1754 addConstantPoolReference(BuildMI(MBB, DL, TII.get(Opc), ResultReg),
1755 MCPOffset, PICBase, OpFlag);
1760 unsigned X86FastISel::TargetMaterializeAlloca(const AllocaInst *C) {
1761 // Fail on dynamic allocas. At this point, getRegForValue has already
1762 // checked its CSE maps, so if we're here trying to handle a dynamic
1763 // alloca, we're not going to succeed. X86SelectAddress has a
1764 // check for dynamic allocas, because it's called directly from
1765 // various places, but TargetMaterializeAlloca also needs a check
1766 // in order to avoid recursion between getRegForValue,
1767 // X86SelectAddrss, and TargetMaterializeAlloca.
1768 if (!StaticAllocaMap.count(C))
1772 if (!X86SelectAddress(C, AM))
1774 unsigned Opc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
1775 TargetRegisterClass* RC = TLI.getRegClassFor(TLI.getPointerTy());
1776 unsigned ResultReg = createResultReg(RC);
1777 addLeaAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), AM);
1782 llvm::FastISel *X86::createFastISel(MachineFunction &mf,
1783 DenseMap<const Value *, unsigned> &vm,
1784 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
1785 DenseMap<const AllocaInst *, int> &am,
1786 std::vector<std::pair<MachineInstr*, unsigned> > &pn
1788 , SmallSet<const Instruction *, 8> &cil
1791 return new X86FastISel(mf, vm, bm, am, pn