1 //===-- X86/X86CodeEmitter.cpp - Convert X86 code to machine code ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the pass that transforms the X86 machine instructions into
11 // relocatable machine code.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-emitter"
16 #include "X86InstrInfo.h"
17 #include "X86JITInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "X86Relocations.h"
22 #include "llvm/PassManager.h"
23 #include "llvm/CodeGen/MachineCodeEmitter.h"
24 #include "llvm/CodeGen/JITCodeEmitter.h"
25 #include "llvm/CodeGen/ObjectCodeEmitter.h"
26 #include "llvm/CodeGen/MachineFunctionPass.h"
27 #include "llvm/CodeGen/MachineInstr.h"
28 #include "llvm/CodeGen/MachineModuleInfo.h"
29 #include "llvm/CodeGen/Passes.h"
30 #include "llvm/Function.h"
31 #include "llvm/ADT/Statistic.h"
32 #include "llvm/MC/MCCodeEmitter.h"
33 #include "llvm/MC/MCExpr.h"
34 #include "llvm/MC/MCInst.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/raw_ostream.h"
38 #include "llvm/Target/TargetOptions.h"
41 STATISTIC(NumEmitted, "Number of machine instructions emitted");
44 template<class CodeEmitter>
45 class Emitter : public MachineFunctionPass {
46 const X86InstrInfo *II;
50 intptr_t PICBaseOffset;
55 explicit Emitter(X86TargetMachine &tm, CodeEmitter &mce)
56 : MachineFunctionPass(&ID), II(0), TD(0), TM(tm),
57 MCE(mce), PICBaseOffset(0), Is64BitMode(false),
58 IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
59 Emitter(X86TargetMachine &tm, CodeEmitter &mce,
60 const X86InstrInfo &ii, const TargetData &td, bool is64)
61 : MachineFunctionPass(&ID), II(&ii), TD(&td), TM(tm),
62 MCE(mce), PICBaseOffset(0), Is64BitMode(is64),
63 IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
65 bool runOnMachineFunction(MachineFunction &MF);
67 virtual const char *getPassName() const {
68 return "X86 Machine Code Emitter";
71 void emitInstruction(const MachineInstr &MI,
72 const TargetInstrDesc *Desc);
74 void getAnalysisUsage(AnalysisUsage &AU) const {
76 AU.addRequired<MachineModuleInfo>();
77 MachineFunctionPass::getAnalysisUsage(AU);
81 void emitPCRelativeBlockAddress(MachineBasicBlock *MBB);
82 void emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
83 intptr_t Disp = 0, intptr_t PCAdj = 0,
84 bool NeedStub = false, bool Indirect = false);
85 void emitExternalSymbolAddress(const char *ES, unsigned Reloc);
86 void emitConstPoolAddress(unsigned CPI, unsigned Reloc, intptr_t Disp = 0,
88 void emitJumpTableAddress(unsigned JTI, unsigned Reloc,
91 void emitDisplacementField(const MachineOperand *RelocOp, int DispVal,
92 intptr_t Adj = 0, bool IsPCRel = true);
94 void emitRegModRMByte(unsigned ModRMReg, unsigned RegOpcodeField);
95 void emitRegModRMByte(unsigned RegOpcodeField);
96 void emitSIBByte(unsigned SS, unsigned Index, unsigned Base);
97 void emitConstant(uint64_t Val, unsigned Size);
99 void emitMemModRMByte(const MachineInstr &MI,
100 unsigned Op, unsigned RegOpcodeField,
103 unsigned getX86RegNum(unsigned RegNo) const;
106 template<class CodeEmitter>
107 char Emitter<CodeEmitter>::ID = 0;
108 } // end anonymous namespace.
110 /// createX86CodeEmitterPass - Return a pass that emits the collected X86 code
111 /// to the specified templated MachineCodeEmitter object.
113 FunctionPass *llvm::createX86CodeEmitterPass(X86TargetMachine &TM,
114 MachineCodeEmitter &MCE) {
115 return new Emitter<MachineCodeEmitter>(TM, MCE);
117 FunctionPass *llvm::createX86JITCodeEmitterPass(X86TargetMachine &TM,
118 JITCodeEmitter &JCE) {
119 return new Emitter<JITCodeEmitter>(TM, JCE);
121 FunctionPass *llvm::createX86ObjectCodeEmitterPass(X86TargetMachine &TM,
122 ObjectCodeEmitter &OCE) {
123 return new Emitter<ObjectCodeEmitter>(TM, OCE);
126 template<class CodeEmitter>
127 bool Emitter<CodeEmitter>::runOnMachineFunction(MachineFunction &MF) {
129 MCE.setModuleInfo(&getAnalysis<MachineModuleInfo>());
131 II = TM.getInstrInfo();
132 TD = TM.getTargetData();
133 Is64BitMode = TM.getSubtarget<X86Subtarget>().is64Bit();
134 IsPIC = TM.getRelocationModel() == Reloc::PIC_;
137 DEBUG(errs() << "JITTing function '"
138 << MF.getFunction()->getName() << "'\n");
139 MCE.startFunction(MF);
140 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
142 MCE.StartMachineBasicBlock(MBB);
143 for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
145 const TargetInstrDesc &Desc = I->getDesc();
146 emitInstruction(*I, &Desc);
147 // MOVPC32r is basically a call plus a pop instruction.
148 if (Desc.getOpcode() == X86::MOVPC32r)
149 emitInstruction(*I, &II->get(X86::POP32r));
150 NumEmitted++; // Keep track of the # of mi's emitted
153 } while (MCE.finishFunction(MF));
158 /// emitPCRelativeBlockAddress - This method keeps track of the information
159 /// necessary to resolve the address of this block later and emits a dummy
162 template<class CodeEmitter>
163 void Emitter<CodeEmitter>::emitPCRelativeBlockAddress(MachineBasicBlock *MBB) {
164 // Remember where this reference was and where it is to so we can
165 // deal with it later.
166 MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
167 X86::reloc_pcrel_word, MBB));
171 /// emitGlobalAddress - Emit the specified address to the code stream assuming
172 /// this is part of a "take the address of a global" instruction.
174 template<class CodeEmitter>
175 void Emitter<CodeEmitter>::emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
176 intptr_t Disp /* = 0 */,
177 intptr_t PCAdj /* = 0 */,
178 bool NeedStub /* = false */,
179 bool Indirect /* = false */) {
180 intptr_t RelocCST = Disp;
181 if (Reloc == X86::reloc_picrel_word)
182 RelocCST = PICBaseOffset;
183 else if (Reloc == X86::reloc_pcrel_word)
185 MachineRelocation MR = Indirect
186 ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc,
187 GV, RelocCST, NeedStub)
188 : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
189 GV, RelocCST, NeedStub);
190 MCE.addRelocation(MR);
191 // The relocated value will be added to the displacement
192 if (Reloc == X86::reloc_absolute_dword)
193 MCE.emitDWordLE(Disp);
195 MCE.emitWordLE((int32_t)Disp);
198 /// emitExternalSymbolAddress - Arrange for the address of an external symbol to
199 /// be emitted to the current location in the function, and allow it to be PC
201 template<class CodeEmitter>
202 void Emitter<CodeEmitter>::emitExternalSymbolAddress(const char *ES,
204 intptr_t RelocCST = (Reloc == X86::reloc_picrel_word) ? PICBaseOffset : 0;
205 MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
206 Reloc, ES, RelocCST));
207 if (Reloc == X86::reloc_absolute_dword)
213 /// emitConstPoolAddress - Arrange for the address of an constant pool
214 /// to be emitted to the current location in the function, and allow it to be PC
216 template<class CodeEmitter>
217 void Emitter<CodeEmitter>::emitConstPoolAddress(unsigned CPI, unsigned Reloc,
218 intptr_t Disp /* = 0 */,
219 intptr_t PCAdj /* = 0 */) {
220 intptr_t RelocCST = 0;
221 if (Reloc == X86::reloc_picrel_word)
222 RelocCST = PICBaseOffset;
223 else if (Reloc == X86::reloc_pcrel_word)
225 MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
226 Reloc, CPI, RelocCST));
227 // The relocated value will be added to the displacement
228 if (Reloc == X86::reloc_absolute_dword)
229 MCE.emitDWordLE(Disp);
231 MCE.emitWordLE((int32_t)Disp);
234 /// emitJumpTableAddress - Arrange for the address of a jump table to
235 /// be emitted to the current location in the function, and allow it to be PC
237 template<class CodeEmitter>
238 void Emitter<CodeEmitter>::emitJumpTableAddress(unsigned JTI, unsigned Reloc,
239 intptr_t PCAdj /* = 0 */) {
240 intptr_t RelocCST = 0;
241 if (Reloc == X86::reloc_picrel_word)
242 RelocCST = PICBaseOffset;
243 else if (Reloc == X86::reloc_pcrel_word)
245 MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
246 Reloc, JTI, RelocCST));
247 // The relocated value will be added to the displacement
248 if (Reloc == X86::reloc_absolute_dword)
254 template<class CodeEmitter>
255 unsigned Emitter<CodeEmitter>::getX86RegNum(unsigned RegNo) const {
256 return II->getRegisterInfo().getX86RegNum(RegNo);
259 inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
261 assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
262 return RM | (RegOpcode << 3) | (Mod << 6);
265 template<class CodeEmitter>
266 void Emitter<CodeEmitter>::emitRegModRMByte(unsigned ModRMReg,
267 unsigned RegOpcodeFld){
268 MCE.emitByte(ModRMByte(3, RegOpcodeFld, getX86RegNum(ModRMReg)));
271 template<class CodeEmitter>
272 void Emitter<CodeEmitter>::emitRegModRMByte(unsigned RegOpcodeFld) {
273 MCE.emitByte(ModRMByte(3, RegOpcodeFld, 0));
276 template<class CodeEmitter>
277 void Emitter<CodeEmitter>::emitSIBByte(unsigned SS,
280 // SIB byte is in the same format as the ModRMByte...
281 MCE.emitByte(ModRMByte(SS, Index, Base));
284 template<class CodeEmitter>
285 void Emitter<CodeEmitter>::emitConstant(uint64_t Val, unsigned Size) {
286 // Output the constant in little endian byte order...
287 for (unsigned i = 0; i != Size; ++i) {
288 MCE.emitByte(Val & 255);
293 /// isDisp8 - Return true if this signed displacement fits in a 8-bit
294 /// sign-extended field.
295 static bool isDisp8(int Value) {
296 return Value == (signed char)Value;
299 static bool gvNeedsNonLazyPtr(const MachineOperand &GVOp,
300 const TargetMachine &TM) {
301 // For Darwin-64, simulate the linktime GOT by using the same non-lazy-pointer
302 // mechanism as 32-bit mode.
303 if (TM.getSubtarget<X86Subtarget>().is64Bit() &&
304 !TM.getSubtarget<X86Subtarget>().isTargetDarwin())
307 // Return true if this is a reference to a stub containing the address of the
308 // global, not the global itself.
309 return isGlobalStubReference(GVOp.getTargetFlags());
312 template<class CodeEmitter>
313 void Emitter<CodeEmitter>::emitDisplacementField(const MachineOperand *RelocOp,
315 intptr_t Adj /* = 0 */,
316 bool IsPCRel /* = true */) {
317 // If this is a simple integer displacement that doesn't require a relocation,
320 emitConstant(DispVal, 4);
324 // Otherwise, this is something that requires a relocation. Emit it as such
326 unsigned RelocType = Is64BitMode ?
327 (IsPCRel ? X86::reloc_pcrel_word : X86::reloc_absolute_word_sext)
328 : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
329 if (RelocOp->isGlobal()) {
330 // In 64-bit static small code model, we could potentially emit absolute.
331 // But it's probably not beneficial. If the MCE supports using RIP directly
332 // do it, otherwise fallback to absolute (this is determined by IsPCRel).
333 // 89 05 00 00 00 00 mov %eax,0(%rip) # PC-relative
334 // 89 04 25 00 00 00 00 mov %eax,0x0 # Absolute
335 bool NeedStub = isa<Function>(RelocOp->getGlobal());
336 bool Indirect = gvNeedsNonLazyPtr(*RelocOp, TM);
337 emitGlobalAddress(RelocOp->getGlobal(), RelocType, RelocOp->getOffset(),
338 Adj, NeedStub, Indirect);
339 } else if (RelocOp->isSymbol()) {
340 emitExternalSymbolAddress(RelocOp->getSymbolName(), RelocType);
341 } else if (RelocOp->isCPI()) {
342 emitConstPoolAddress(RelocOp->getIndex(), RelocType,
343 RelocOp->getOffset(), Adj);
345 assert(RelocOp->isJTI() && "Unexpected machine operand!");
346 emitJumpTableAddress(RelocOp->getIndex(), RelocType, Adj);
350 template<class CodeEmitter>
351 void Emitter<CodeEmitter>::emitMemModRMByte(const MachineInstr &MI,
352 unsigned Op,unsigned RegOpcodeField,
354 const MachineOperand &Op3 = MI.getOperand(Op+3);
356 const MachineOperand *DispForReloc = 0;
358 // Figure out what sort of displacement we have to handle here.
359 if (Op3.isGlobal()) {
361 } else if (Op3.isSymbol()) {
363 } else if (Op3.isCPI()) {
364 if (!MCE.earlyResolveAddresses() || Is64BitMode || IsPIC) {
367 DispVal += MCE.getConstantPoolEntryAddress(Op3.getIndex());
368 DispVal += Op3.getOffset();
370 } else if (Op3.isJTI()) {
371 if (!MCE.earlyResolveAddresses() || Is64BitMode || IsPIC) {
374 DispVal += MCE.getJumpTableEntryAddress(Op3.getIndex());
377 DispVal = Op3.getImm();
380 const MachineOperand &Base = MI.getOperand(Op);
381 const MachineOperand &Scale = MI.getOperand(Op+1);
382 const MachineOperand &IndexReg = MI.getOperand(Op+2);
384 unsigned BaseReg = Base.getReg();
386 // Indicate that the displacement will use an pcrel or absolute reference
387 // by default. MCEs able to resolve addresses on-the-fly use pcrel by default
388 // while others, unless explicit asked to use RIP, use absolute references.
389 bool IsPCRel = MCE.earlyResolveAddresses() ? true : false;
391 // Is a SIB byte needed?
392 // If no BaseReg, issue a RIP relative instruction only if the MCE can
393 // resolve addresses on-the-fly, otherwise use SIB (Intel Manual 2A, table
394 // 2-7) and absolute references.
395 if ((!Is64BitMode || DispForReloc || BaseReg != 0) &&
396 IndexReg.getReg() == 0 &&
397 ((BaseReg == 0 && MCE.earlyResolveAddresses()) || BaseReg == X86::RIP ||
398 (BaseReg != 0 && getX86RegNum(BaseReg) != N86::ESP))) {
399 if (BaseReg == 0 || BaseReg == X86::RIP) { // Just a displacement?
400 // Emit special case [disp32] encoding
401 MCE.emitByte(ModRMByte(0, RegOpcodeField, 5));
402 emitDisplacementField(DispForReloc, DispVal, PCAdj, true);
404 unsigned BaseRegNo = getX86RegNum(BaseReg);
405 if (!DispForReloc && DispVal == 0 && BaseRegNo != N86::EBP) {
406 // Emit simple indirect register encoding... [EAX] f.e.
407 MCE.emitByte(ModRMByte(0, RegOpcodeField, BaseRegNo));
408 } else if (!DispForReloc && isDisp8(DispVal)) {
409 // Emit the disp8 encoding... [REG+disp8]
410 MCE.emitByte(ModRMByte(1, RegOpcodeField, BaseRegNo));
411 emitConstant(DispVal, 1);
413 // Emit the most general non-SIB encoding: [REG+disp32]
414 MCE.emitByte(ModRMByte(2, RegOpcodeField, BaseRegNo));
415 emitDisplacementField(DispForReloc, DispVal, PCAdj, IsPCRel);
419 } else { // We need a SIB byte, so start by outputting the ModR/M byte first
420 assert(IndexReg.getReg() != X86::ESP &&
421 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
423 bool ForceDisp32 = false;
424 bool ForceDisp8 = false;
426 // If there is no base register, we emit the special case SIB byte with
427 // MOD=0, BASE=5, to JUST get the index, scale, and displacement.
428 MCE.emitByte(ModRMByte(0, RegOpcodeField, 4));
430 } else if (DispForReloc) {
431 // Emit the normal disp32 encoding.
432 MCE.emitByte(ModRMByte(2, RegOpcodeField, 4));
434 } else if (DispVal == 0 && getX86RegNum(BaseReg) != N86::EBP) {
435 // Emit no displacement ModR/M byte
436 MCE.emitByte(ModRMByte(0, RegOpcodeField, 4));
437 } else if (isDisp8(DispVal)) {
438 // Emit the disp8 encoding...
439 MCE.emitByte(ModRMByte(1, RegOpcodeField, 4));
440 ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP
442 // Emit the normal disp32 encoding...
443 MCE.emitByte(ModRMByte(2, RegOpcodeField, 4));
446 // Calculate what the SS field value should be...
447 static const unsigned SSTable[] = { ~0, 0, 1, ~0, 2, ~0, ~0, ~0, 3 };
448 unsigned SS = SSTable[Scale.getImm()];
451 // Handle the SIB byte for the case where there is no base, see Intel
452 // Manual 2A, table 2-7. The displacement has already been output.
454 if (IndexReg.getReg())
455 IndexRegNo = getX86RegNum(IndexReg.getReg());
456 else // Examples: [ESP+1*<noreg>+4] or [scaled idx]+disp32 (MOD=0,BASE=5)
458 emitSIBByte(SS, IndexRegNo, 5);
460 unsigned BaseRegNo = getX86RegNum(BaseReg);
462 if (IndexReg.getReg())
463 IndexRegNo = getX86RegNum(IndexReg.getReg());
465 IndexRegNo = 4; // For example [ESP+1*<noreg>+4]
466 emitSIBByte(SS, IndexRegNo, BaseRegNo);
469 // Do we need to output a displacement?
471 emitConstant(DispVal, 1);
472 } else if (DispVal != 0 || ForceDisp32) {
473 emitDisplacementField(DispForReloc, DispVal, PCAdj, IsPCRel);
478 template<class CodeEmitter>
479 void Emitter<CodeEmitter>::emitInstruction(const MachineInstr &MI,
480 const TargetInstrDesc *Desc) {
483 MCE.processDebugLoc(MI.getDebugLoc(), true);
485 unsigned Opcode = Desc->Opcode;
487 // Emit the lock opcode prefix as needed.
488 if (Desc->TSFlags & X86II::LOCK)
491 // Emit segment override opcode prefix as needed.
492 switch (Desc->TSFlags & X86II::SegOvrMask) {
499 default: llvm_unreachable("Invalid segment!");
500 case 0: break; // No segment override!
503 // Emit the repeat opcode prefix as needed.
504 if ((Desc->TSFlags & X86II::Op0Mask) == X86II::REP)
507 // Emit the operand size opcode prefix as needed.
508 if (Desc->TSFlags & X86II::OpSize)
511 // Emit the address size opcode prefix as needed.
512 if (Desc->TSFlags & X86II::AdSize)
515 bool Need0FPrefix = false;
516 switch (Desc->TSFlags & X86II::Op0Mask) {
517 case X86II::TB: // Two-byte opcode prefix
518 case X86II::T8: // 0F 38
519 case X86II::TA: // 0F 3A
522 case X86II::TF: // F2 0F 38
526 case X86II::REP: break; // already handled.
527 case X86II::XS: // F3 0F
531 case X86II::XD: // F2 0F
535 case X86II::D8: case X86II::D9: case X86II::DA: case X86II::DB:
536 case X86II::DC: case X86II::DD: case X86II::DE: case X86II::DF:
538 (((Desc->TSFlags & X86II::Op0Mask)-X86II::D8)
539 >> X86II::Op0Shift));
540 break; // Two-byte opcode prefix
541 default: llvm_unreachable("Invalid prefix!");
542 case 0: break; // No prefix!
545 // Handle REX prefix.
547 if (unsigned REX = X86InstrInfo::determineREX(MI))
548 MCE.emitByte(0x40 | REX);
551 // 0x0F escape code must be emitted just before the opcode.
555 switch (Desc->TSFlags & X86II::Op0Mask) {
556 case X86II::TF: // F2 0F 38
557 case X86II::T8: // 0F 38
560 case X86II::TA: // 0F 3A
565 // If this is a two-address instruction, skip one of the register operands.
566 unsigned NumOps = Desc->getNumOperands();
568 if (NumOps > 1 && Desc->getOperandConstraint(1, TOI::TIED_TO) != -1)
570 else if (NumOps > 2 && Desc->getOperandConstraint(NumOps-1, TOI::TIED_TO)== 0)
571 // Skip the last source operand that is tied_to the dest reg. e.g. LXADD32
574 unsigned char BaseOpcode = II->getBaseOpcodeFor(Desc);
575 switch (Desc->TSFlags & X86II::FormMask) {
577 llvm_unreachable("Unknown FormMask value in X86 MachineCodeEmitter!");
579 // Remember the current PC offset, this is the PIC relocation
583 llvm_unreachable("psuedo instructions should be removed before code"
586 case TargetInstrInfo::INLINEASM:
587 // We allow inline assembler nodes with empty bodies - they can
588 // implicitly define registers, which is ok for JIT.
589 if (MI.getOperand(0).getSymbolName()[0])
590 llvm_report_error("JIT does not support inline asm!");
592 case TargetInstrInfo::DBG_LABEL:
593 case TargetInstrInfo::EH_LABEL:
594 case TargetInstrInfo::GC_LABEL:
595 MCE.emitLabel(MI.getOperand(0).getImm());
597 case TargetInstrInfo::IMPLICIT_DEF:
598 case TargetInstrInfo::KILL:
600 case X86::FP_REG_KILL:
602 case X86::MOVPC32r: {
603 // This emits the "call" portion of this pseudo instruction.
604 MCE.emitByte(BaseOpcode);
605 emitConstant(0, X86InstrInfo::sizeOfImm(Desc));
606 // Remember PIC base.
607 PICBaseOffset = (intptr_t) MCE.getCurrentPCOffset();
608 X86JITInfo *JTI = TM.getJITInfo();
609 JTI->setPICBase(MCE.getCurrentPCValue());
615 case X86II::RawFrm: {
616 MCE.emitByte(BaseOpcode);
621 const MachineOperand &MO = MI.getOperand(CurOp++);
623 DEBUG(errs() << "RawFrm CurOp " << CurOp << "\n");
624 DEBUG(errs() << "isMBB " << MO.isMBB() << "\n");
625 DEBUG(errs() << "isGlobal " << MO.isGlobal() << "\n");
626 DEBUG(errs() << "isSymbol " << MO.isSymbol() << "\n");
627 DEBUG(errs() << "isImm " << MO.isImm() << "\n");
630 emitPCRelativeBlockAddress(MO.getMBB());
635 // Assume undefined functions may be outside the Small codespace.
638 (TM.getCodeModel() == CodeModel::Large ||
639 TM.getSubtarget<X86Subtarget>().isTargetDarwin())) ||
640 Opcode == X86::TAILJMPd;
641 emitGlobalAddress(MO.getGlobal(), X86::reloc_pcrel_word,
642 MO.getOffset(), 0, NeedStub);
647 emitExternalSymbolAddress(MO.getSymbolName(), X86::reloc_pcrel_word);
651 assert(MO.isImm() && "Unknown RawFrm operand!");
652 if (Opcode == X86::CALLpcrel32 || Opcode == X86::CALL64pcrel32) {
653 // Fix up immediate operand for pc relative calls.
654 intptr_t Imm = (intptr_t)MO.getImm();
655 Imm = Imm - MCE.getCurrentPCValue() - 4;
656 emitConstant(Imm, X86InstrInfo::sizeOfImm(Desc));
658 emitConstant(MO.getImm(), X86InstrInfo::sizeOfImm(Desc));
662 case X86II::AddRegFrm: {
663 MCE.emitByte(BaseOpcode + getX86RegNum(MI.getOperand(CurOp++).getReg()));
668 const MachineOperand &MO1 = MI.getOperand(CurOp++);
669 unsigned Size = X86InstrInfo::sizeOfImm(Desc);
671 emitConstant(MO1.getImm(), Size);
675 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
676 : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
677 if (Opcode == X86::MOV64ri64i32)
678 rt = X86::reloc_absolute_word; // FIXME: add X86II flag?
679 // This should not occur on Darwin for relocatable objects.
680 if (Opcode == X86::MOV64ri)
681 rt = X86::reloc_absolute_dword; // FIXME: add X86II flag?
682 if (MO1.isGlobal()) {
683 bool NeedStub = isa<Function>(MO1.getGlobal());
684 bool Indirect = gvNeedsNonLazyPtr(MO1, TM);
685 emitGlobalAddress(MO1.getGlobal(), rt, MO1.getOffset(), 0,
687 } else if (MO1.isSymbol())
688 emitExternalSymbolAddress(MO1.getSymbolName(), rt);
689 else if (MO1.isCPI())
690 emitConstPoolAddress(MO1.getIndex(), rt);
691 else if (MO1.isJTI())
692 emitJumpTableAddress(MO1.getIndex(), rt);
696 case X86II::MRMDestReg: {
697 MCE.emitByte(BaseOpcode);
698 emitRegModRMByte(MI.getOperand(CurOp).getReg(),
699 getX86RegNum(MI.getOperand(CurOp+1).getReg()));
702 emitConstant(MI.getOperand(CurOp++).getImm(),
703 X86InstrInfo::sizeOfImm(Desc));
706 case X86II::MRMDestMem: {
707 MCE.emitByte(BaseOpcode);
708 emitMemModRMByte(MI, CurOp,
709 getX86RegNum(MI.getOperand(CurOp + X86AddrNumOperands)
711 CurOp += X86AddrNumOperands + 1;
713 emitConstant(MI.getOperand(CurOp++).getImm(),
714 X86InstrInfo::sizeOfImm(Desc));
718 case X86II::MRMSrcReg:
719 MCE.emitByte(BaseOpcode);
720 emitRegModRMByte(MI.getOperand(CurOp+1).getReg(),
721 getX86RegNum(MI.getOperand(CurOp).getReg()));
724 emitConstant(MI.getOperand(CurOp++).getImm(),
725 X86InstrInfo::sizeOfImm(Desc));
728 case X86II::MRMSrcMem: {
729 // FIXME: Maybe lea should have its own form?
731 if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r ||
732 Opcode == X86::LEA16r || Opcode == X86::LEA32r)
733 AddrOperands = X86AddrNumOperands - 1; // No segment register
735 AddrOperands = X86AddrNumOperands;
737 intptr_t PCAdj = (CurOp + AddrOperands + 1 != NumOps) ?
738 X86InstrInfo::sizeOfImm(Desc) : 0;
740 MCE.emitByte(BaseOpcode);
741 emitMemModRMByte(MI, CurOp+1, getX86RegNum(MI.getOperand(CurOp).getReg()),
743 CurOp += AddrOperands + 1;
745 emitConstant(MI.getOperand(CurOp++).getImm(),
746 X86InstrInfo::sizeOfImm(Desc));
750 case X86II::MRM0r: case X86II::MRM1r:
751 case X86II::MRM2r: case X86II::MRM3r:
752 case X86II::MRM4r: case X86II::MRM5r:
753 case X86II::MRM6r: case X86II::MRM7r: {
754 MCE.emitByte(BaseOpcode);
756 // Special handling of lfence, mfence, monitor, and mwait.
757 if (Desc->getOpcode() == X86::LFENCE ||
758 Desc->getOpcode() == X86::MFENCE ||
759 Desc->getOpcode() == X86::MONITOR ||
760 Desc->getOpcode() == X86::MWAIT) {
761 emitRegModRMByte((Desc->TSFlags & X86II::FormMask)-X86II::MRM0r);
763 switch (Desc->getOpcode()) {
773 emitRegModRMByte(MI.getOperand(CurOp++).getReg(),
774 (Desc->TSFlags & X86II::FormMask)-X86II::MRM0r);
780 const MachineOperand &MO1 = MI.getOperand(CurOp++);
781 unsigned Size = X86InstrInfo::sizeOfImm(Desc);
783 emitConstant(MO1.getImm(), Size);
787 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
788 : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
789 if (Opcode == X86::MOV64ri32)
790 rt = X86::reloc_absolute_word_sext; // FIXME: add X86II flag?
791 if (MO1.isGlobal()) {
792 bool NeedStub = isa<Function>(MO1.getGlobal());
793 bool Indirect = gvNeedsNonLazyPtr(MO1, TM);
794 emitGlobalAddress(MO1.getGlobal(), rt, MO1.getOffset(), 0,
796 } else if (MO1.isSymbol())
797 emitExternalSymbolAddress(MO1.getSymbolName(), rt);
798 else if (MO1.isCPI())
799 emitConstPoolAddress(MO1.getIndex(), rt);
800 else if (MO1.isJTI())
801 emitJumpTableAddress(MO1.getIndex(), rt);
805 case X86II::MRM0m: case X86II::MRM1m:
806 case X86II::MRM2m: case X86II::MRM3m:
807 case X86II::MRM4m: case X86II::MRM5m:
808 case X86II::MRM6m: case X86II::MRM7m: {
809 intptr_t PCAdj = (CurOp + X86AddrNumOperands != NumOps) ?
810 (MI.getOperand(CurOp+X86AddrNumOperands).isImm() ?
811 X86InstrInfo::sizeOfImm(Desc) : 4) : 0;
813 MCE.emitByte(BaseOpcode);
814 emitMemModRMByte(MI, CurOp, (Desc->TSFlags & X86II::FormMask)-X86II::MRM0m,
816 CurOp += X86AddrNumOperands;
821 const MachineOperand &MO = MI.getOperand(CurOp++);
822 unsigned Size = X86InstrInfo::sizeOfImm(Desc);
824 emitConstant(MO.getImm(), Size);
828 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
829 : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
830 if (Opcode == X86::MOV64mi32)
831 rt = X86::reloc_absolute_word_sext; // FIXME: add X86II flag?
833 bool NeedStub = isa<Function>(MO.getGlobal());
834 bool Indirect = gvNeedsNonLazyPtr(MO, TM);
835 emitGlobalAddress(MO.getGlobal(), rt, MO.getOffset(), 0,
837 } else if (MO.isSymbol())
838 emitExternalSymbolAddress(MO.getSymbolName(), rt);
840 emitConstPoolAddress(MO.getIndex(), rt);
842 emitJumpTableAddress(MO.getIndex(), rt);
846 case X86II::MRMInitReg:
847 MCE.emitByte(BaseOpcode);
848 // Duplicate register, used by things like MOV8r0 (aka xor reg,reg).
849 emitRegModRMByte(MI.getOperand(CurOp).getReg(),
850 getX86RegNum(MI.getOperand(CurOp).getReg()));
855 if (!Desc->isVariadic() && CurOp != NumOps) {
857 errs() << "Cannot encode all operands of: " << MI << "\n";
862 MCE.processDebugLoc(MI.getDebugLoc(), false);
865 // Adapt the Emitter / CodeEmitter interfaces to MCCodeEmitter.
867 // FIXME: This is a total hack designed to allow work on llvm-mc to proceed
868 // without being blocked on various cleanups needed to support a clean interface
869 // to instruction encoding.
873 #include "llvm/DerivedTypes.h"
876 class MCSingleInstructionCodeEmitter : public MachineCodeEmitter {
880 MCSingleInstructionCodeEmitter() { reset(); }
884 BufferEnd = array_endof(Data);
889 return StringRef(reinterpret_cast<char*>(BufferBegin),
890 CurBufferPtr - BufferBegin);
893 virtual void startFunction(MachineFunction &F) {}
894 virtual bool finishFunction(MachineFunction &F) { return false; }
895 virtual void emitLabel(uint64_t LabelID) {}
896 virtual void StartMachineBasicBlock(MachineBasicBlock *MBB) {}
897 virtual bool earlyResolveAddresses() const { return false; }
898 virtual void addRelocation(const MachineRelocation &MR) { }
899 virtual uintptr_t getConstantPoolEntryAddress(unsigned Index) const {
902 virtual uintptr_t getJumpTableEntryAddress(unsigned Index) const {
905 virtual uintptr_t getMachineBasicBlockAddress(MachineBasicBlock *MBB) const {
908 virtual uintptr_t getLabelAddress(uint64_t LabelID) const {
911 virtual void setModuleInfo(MachineModuleInfo* Info) {}
914 class X86MCCodeEmitter : public MCCodeEmitter {
915 X86MCCodeEmitter(const X86MCCodeEmitter &); // DO NOT IMPLEMENT
916 void operator=(const X86MCCodeEmitter &); // DO NOT IMPLEMENT
919 X86TargetMachine &TM;
920 llvm::Function *DummyF;
922 mutable llvm::MachineFunction *DummyMF;
923 llvm::MachineBasicBlock *DummyMBB;
925 MCSingleInstructionCodeEmitter *InstrEmitter;
926 Emitter<MachineCodeEmitter> *Emit;
929 X86MCCodeEmitter(X86TargetMachine &_TM) : TM(_TM) {
930 // Verily, thou shouldst avert thine eyes.
931 const llvm::FunctionType *FTy =
932 FunctionType::get(llvm::Type::getVoidTy(getGlobalContext()), false);
933 DummyF = Function::Create(FTy, GlobalValue::InternalLinkage);
934 DummyTD = new TargetData("");
935 DummyMF = new MachineFunction(DummyF, TM);
936 DummyMBB = DummyMF->CreateMachineBasicBlock();
938 InstrEmitter = new MCSingleInstructionCodeEmitter();
939 Emit = new Emitter<MachineCodeEmitter>(TM, *InstrEmitter,
943 ~X86MCCodeEmitter() {
950 bool AddRegToInstr(const MCInst &MI, MachineInstr *Instr,
951 unsigned Start) const {
952 if (Start + 1 > MI.getNumOperands())
955 const MCOperand &Op = MI.getOperand(Start);
956 if (!Op.isReg()) return false;
958 Instr->addOperand(MachineOperand::CreateReg(Op.getReg(), false));
962 bool AddImmToInstr(const MCInst &MI, MachineInstr *Instr,
963 unsigned Start) const {
964 if (Start + 1 > MI.getNumOperands())
967 const MCOperand &Op = MI.getOperand(Start);
969 Instr->addOperand(MachineOperand::CreateImm(Op.getImm()));
975 const MCExpr *Expr = Op.getExpr();
976 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr)) {
977 Instr->addOperand(MachineOperand::CreateImm(CE->getValue()));
981 // FIXME: Relocation / fixup.
982 Instr->addOperand(MachineOperand::CreateImm(0));
986 bool AddLMemToInstr(const MCInst &MI, MachineInstr *Instr,
987 unsigned Start) const {
988 return (AddRegToInstr(MI, Instr, Start + 0) &&
989 AddImmToInstr(MI, Instr, Start + 1) &&
990 AddRegToInstr(MI, Instr, Start + 2) &&
991 AddImmToInstr(MI, Instr, Start + 3));
994 bool AddMemToInstr(const MCInst &MI, MachineInstr *Instr,
995 unsigned Start) const {
996 return (AddRegToInstr(MI, Instr, Start + 0) &&
997 AddImmToInstr(MI, Instr, Start + 1) &&
998 AddRegToInstr(MI, Instr, Start + 2) &&
999 AddImmToInstr(MI, Instr, Start + 3) &&
1000 AddRegToInstr(MI, Instr, Start + 4));
1003 void EncodeInstruction(const MCInst &MI, raw_ostream &OS) const {
1006 // Convert the MCInst to a MachineInstr so we can (ab)use the regular
1008 const X86InstrInfo &II = *TM.getInstrInfo();
1009 const TargetInstrDesc &Desc = II.get(MI.getOpcode());
1010 MachineInstr *Instr = DummyMF->CreateMachineInstr(Desc, DebugLoc());
1011 DummyMBB->push_back(Instr);
1013 unsigned Opcode = MI.getOpcode();
1014 unsigned NumOps = MI.getNumOperands();
1016 if (NumOps > 1 && Desc.getOperandConstraint(1, TOI::TIED_TO) != -1) {
1017 Instr->addOperand(MachineOperand::CreateReg(0, false));
1019 } else if (NumOps > 2 &&
1020 Desc.getOperandConstraint(NumOps-1, TOI::TIED_TO)== 0)
1021 // Skip the last source operand that is tied_to the dest reg. e.g. LXADD32
1025 switch (Desc.TSFlags & X86II::FormMask) {
1026 case X86II::MRMDestReg:
1027 case X86II::MRMSrcReg:
1028 // Matching doesn't fill this in completely, we have to choose operand 0
1029 // for a tied register.
1030 OK &= AddRegToInstr(MI, Instr, 0); CurOp++;
1031 OK &= AddRegToInstr(MI, Instr, CurOp++);
1033 OK &= AddImmToInstr(MI, Instr, CurOp);
1037 if (CurOp < NumOps) {
1038 // Hack to make branches work.
1039 if (!(Desc.TSFlags & X86II::ImmMask) &&
1040 MI.getOperand(0).isExpr() &&
1041 isa<MCSymbolRefExpr>(MI.getOperand(0).getExpr()))
1042 Instr->addOperand(MachineOperand::CreateMBB(DummyMBB));
1044 OK &= AddImmToInstr(MI, Instr, CurOp);
1048 case X86II::AddRegFrm:
1049 OK &= AddRegToInstr(MI, Instr, CurOp++);
1051 OK &= AddImmToInstr(MI, Instr, CurOp);
1054 case X86II::MRM0r: case X86II::MRM1r:
1055 case X86II::MRM2r: case X86II::MRM3r:
1056 case X86II::MRM4r: case X86II::MRM5r:
1057 case X86II::MRM6r: case X86II::MRM7r:
1058 // Matching doesn't fill this in completely, we have to choose operand 0
1059 // for a tied register.
1060 OK &= AddRegToInstr(MI, Instr, 0); CurOp++;
1062 OK &= AddImmToInstr(MI, Instr, CurOp);
1065 case X86II::MRM0m: case X86II::MRM1m:
1066 case X86II::MRM2m: case X86II::MRM3m:
1067 case X86II::MRM4m: case X86II::MRM5m:
1068 case X86II::MRM6m: case X86II::MRM7m:
1069 OK &= AddMemToInstr(MI, Instr, CurOp); CurOp += 5;
1071 OK &= AddImmToInstr(MI, Instr, CurOp);
1074 case X86II::MRMSrcMem:
1075 OK &= AddRegToInstr(MI, Instr, CurOp++);
1076 if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r ||
1077 Opcode == X86::LEA16r || Opcode == X86::LEA32r)
1078 OK &= AddLMemToInstr(MI, Instr, CurOp);
1080 OK &= AddMemToInstr(MI, Instr, CurOp);
1083 case X86II::MRMDestMem:
1084 OK &= AddMemToInstr(MI, Instr, CurOp); CurOp += 5;
1085 OK &= AddRegToInstr(MI, Instr, CurOp);
1089 case X86II::MRMInitReg:
1096 errs() << "couldn't convert inst '";
1098 errs() << "' to machine instr:\n";
1102 InstrEmitter->reset();
1104 Emit->emitInstruction(*Instr, &Desc);
1105 OS << InstrEmitter->str();
1107 Instr->eraseFromParent();
1112 // Ok, now you can look.
1113 MCCodeEmitter *llvm::createX86MCCodeEmitter(const Target &,
1114 TargetMachine &TM) {
1115 return new X86MCCodeEmitter(static_cast<X86TargetMachine&>(TM));