1 //===-- X86/X86CodeEmitter.cpp - Convert X86 code to machine code ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the pass that transforms the X86 machine instructions into
11 // relocatable machine code.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-emitter"
16 #include "X86InstrInfo.h"
17 #include "X86JITInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "X86Relocations.h"
22 #include "llvm/LLVMContext.h"
23 #include "llvm/PassManager.h"
24 #include "llvm/CodeGen/JITCodeEmitter.h"
25 #include "llvm/CodeGen/MachineFunctionPass.h"
26 #include "llvm/CodeGen/MachineInstr.h"
27 #include "llvm/CodeGen/MachineModuleInfo.h"
28 #include "llvm/CodeGen/Passes.h"
29 #include "llvm/Function.h"
30 #include "llvm/ADT/Statistic.h"
31 #include "llvm/MC/MCCodeEmitter.h"
32 #include "llvm/MC/MCExpr.h"
33 #include "llvm/MC/MCInst.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/ErrorHandling.h"
36 #include "llvm/Support/raw_ostream.h"
37 #include "llvm/Target/TargetOptions.h"
40 STATISTIC(NumEmitted, "Number of machine instructions emitted");
43 template<class CodeEmitter>
44 class Emitter : public MachineFunctionPass {
45 const X86InstrInfo *II;
49 intptr_t PICBaseOffset;
54 explicit Emitter(X86TargetMachine &tm, CodeEmitter &mce)
55 : MachineFunctionPass(&ID), II(0), TD(0), TM(tm),
56 MCE(mce), PICBaseOffset(0), Is64BitMode(false),
57 IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
58 Emitter(X86TargetMachine &tm, CodeEmitter &mce,
59 const X86InstrInfo &ii, const TargetData &td, bool is64)
60 : MachineFunctionPass(&ID), II(&ii), TD(&td), TM(tm),
61 MCE(mce), PICBaseOffset(0), Is64BitMode(is64),
62 IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
64 bool runOnMachineFunction(MachineFunction &MF);
66 virtual const char *getPassName() const {
67 return "X86 Machine Code Emitter";
70 void emitInstruction(const MachineInstr &MI,
71 const TargetInstrDesc *Desc);
73 void getAnalysisUsage(AnalysisUsage &AU) const {
75 AU.addRequired<MachineModuleInfo>();
76 MachineFunctionPass::getAnalysisUsage(AU);
80 void emitPCRelativeBlockAddress(MachineBasicBlock *MBB);
81 void emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
82 intptr_t Disp = 0, intptr_t PCAdj = 0,
83 bool Indirect = false);
84 void emitExternalSymbolAddress(const char *ES, unsigned Reloc);
85 void emitConstPoolAddress(unsigned CPI, unsigned Reloc, intptr_t Disp = 0,
87 void emitJumpTableAddress(unsigned JTI, unsigned Reloc,
90 void emitDisplacementField(const MachineOperand *RelocOp, int DispVal,
91 intptr_t Adj = 0, bool IsPCRel = true);
93 void emitRegModRMByte(unsigned ModRMReg, unsigned RegOpcodeField);
94 void emitRegModRMByte(unsigned RegOpcodeField);
95 void emitSIBByte(unsigned SS, unsigned Index, unsigned Base);
96 void emitConstant(uint64_t Val, unsigned Size);
98 void emitMemModRMByte(const MachineInstr &MI,
99 unsigned Op, unsigned RegOpcodeField,
102 unsigned getX86RegNum(unsigned RegNo) const;
105 template<class CodeEmitter>
106 char Emitter<CodeEmitter>::ID = 0;
107 } // end anonymous namespace.
109 /// createX86CodeEmitterPass - Return a pass that emits the collected X86 code
110 /// to the specified templated MachineCodeEmitter object.
111 FunctionPass *llvm::createX86JITCodeEmitterPass(X86TargetMachine &TM,
112 JITCodeEmitter &JCE) {
113 return new Emitter<JITCodeEmitter>(TM, JCE);
116 template<class CodeEmitter>
117 bool Emitter<CodeEmitter>::runOnMachineFunction(MachineFunction &MF) {
119 MCE.setModuleInfo(&getAnalysis<MachineModuleInfo>());
121 II = TM.getInstrInfo();
122 TD = TM.getTargetData();
123 Is64BitMode = TM.getSubtarget<X86Subtarget>().is64Bit();
124 IsPIC = TM.getRelocationModel() == Reloc::PIC_;
127 DEBUG(dbgs() << "JITTing function '"
128 << MF.getFunction()->getName() << "'\n");
129 MCE.startFunction(MF);
130 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
132 MCE.StartMachineBasicBlock(MBB);
133 for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
135 const TargetInstrDesc &Desc = I->getDesc();
136 emitInstruction(*I, &Desc);
137 // MOVPC32r is basically a call plus a pop instruction.
138 if (Desc.getOpcode() == X86::MOVPC32r)
139 emitInstruction(*I, &II->get(X86::POP32r));
140 NumEmitted++; // Keep track of the # of mi's emitted
143 } while (MCE.finishFunction(MF));
148 /// emitPCRelativeBlockAddress - This method keeps track of the information
149 /// necessary to resolve the address of this block later and emits a dummy
152 template<class CodeEmitter>
153 void Emitter<CodeEmitter>::emitPCRelativeBlockAddress(MachineBasicBlock *MBB) {
154 // Remember where this reference was and where it is to so we can
155 // deal with it later.
156 MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
157 X86::reloc_pcrel_word, MBB));
161 /// emitGlobalAddress - Emit the specified address to the code stream assuming
162 /// this is part of a "take the address of a global" instruction.
164 template<class CodeEmitter>
165 void Emitter<CodeEmitter>::emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
166 intptr_t Disp /* = 0 */,
167 intptr_t PCAdj /* = 0 */,
168 bool Indirect /* = false */) {
169 intptr_t RelocCST = Disp;
170 if (Reloc == X86::reloc_picrel_word)
171 RelocCST = PICBaseOffset;
172 else if (Reloc == X86::reloc_pcrel_word)
174 MachineRelocation MR = Indirect
175 ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc,
177 : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
178 GV, RelocCST, false);
179 MCE.addRelocation(MR);
180 // The relocated value will be added to the displacement
181 if (Reloc == X86::reloc_absolute_dword)
182 MCE.emitDWordLE(Disp);
184 MCE.emitWordLE((int32_t)Disp);
187 /// emitExternalSymbolAddress - Arrange for the address of an external symbol to
188 /// be emitted to the current location in the function, and allow it to be PC
190 template<class CodeEmitter>
191 void Emitter<CodeEmitter>::emitExternalSymbolAddress(const char *ES,
193 intptr_t RelocCST = (Reloc == X86::reloc_picrel_word) ? PICBaseOffset : 0;
195 // X86 never needs stubs because instruction selection will always pick
196 // an instruction sequence that is large enough to hold any address
198 // (see X86ISelLowering.cpp, near 2039: X86TargetLowering::LowerCall)
199 bool NeedStub = false;
200 MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
203 if (Reloc == X86::reloc_absolute_dword)
209 /// emitConstPoolAddress - Arrange for the address of an constant pool
210 /// to be emitted to the current location in the function, and allow it to be PC
212 template<class CodeEmitter>
213 void Emitter<CodeEmitter>::emitConstPoolAddress(unsigned CPI, unsigned Reloc,
214 intptr_t Disp /* = 0 */,
215 intptr_t PCAdj /* = 0 */) {
216 intptr_t RelocCST = 0;
217 if (Reloc == X86::reloc_picrel_word)
218 RelocCST = PICBaseOffset;
219 else if (Reloc == X86::reloc_pcrel_word)
221 MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
222 Reloc, CPI, RelocCST));
223 // The relocated value will be added to the displacement
224 if (Reloc == X86::reloc_absolute_dword)
225 MCE.emitDWordLE(Disp);
227 MCE.emitWordLE((int32_t)Disp);
230 /// emitJumpTableAddress - Arrange for the address of a jump table to
231 /// be emitted to the current location in the function, and allow it to be PC
233 template<class CodeEmitter>
234 void Emitter<CodeEmitter>::emitJumpTableAddress(unsigned JTI, unsigned Reloc,
235 intptr_t PCAdj /* = 0 */) {
236 intptr_t RelocCST = 0;
237 if (Reloc == X86::reloc_picrel_word)
238 RelocCST = PICBaseOffset;
239 else if (Reloc == X86::reloc_pcrel_word)
241 MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
242 Reloc, JTI, RelocCST));
243 // The relocated value will be added to the displacement
244 if (Reloc == X86::reloc_absolute_dword)
250 template<class CodeEmitter>
251 unsigned Emitter<CodeEmitter>::getX86RegNum(unsigned RegNo) const {
252 return X86RegisterInfo::getX86RegNum(RegNo);
255 inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
257 assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
258 return RM | (RegOpcode << 3) | (Mod << 6);
261 template<class CodeEmitter>
262 void Emitter<CodeEmitter>::emitRegModRMByte(unsigned ModRMReg,
263 unsigned RegOpcodeFld){
264 MCE.emitByte(ModRMByte(3, RegOpcodeFld, getX86RegNum(ModRMReg)));
267 template<class CodeEmitter>
268 void Emitter<CodeEmitter>::emitRegModRMByte(unsigned RegOpcodeFld) {
269 MCE.emitByte(ModRMByte(3, RegOpcodeFld, 0));
272 template<class CodeEmitter>
273 void Emitter<CodeEmitter>::emitSIBByte(unsigned SS,
276 // SIB byte is in the same format as the ModRMByte...
277 MCE.emitByte(ModRMByte(SS, Index, Base));
280 template<class CodeEmitter>
281 void Emitter<CodeEmitter>::emitConstant(uint64_t Val, unsigned Size) {
282 // Output the constant in little endian byte order...
283 for (unsigned i = 0; i != Size; ++i) {
284 MCE.emitByte(Val & 255);
289 /// isDisp8 - Return true if this signed displacement fits in a 8-bit
290 /// sign-extended field.
291 static bool isDisp8(int Value) {
292 return Value == (signed char)Value;
295 static bool gvNeedsNonLazyPtr(const MachineOperand &GVOp,
296 const TargetMachine &TM) {
297 // For Darwin-64, simulate the linktime GOT by using the same non-lazy-pointer
298 // mechanism as 32-bit mode.
299 if (TM.getSubtarget<X86Subtarget>().is64Bit() &&
300 !TM.getSubtarget<X86Subtarget>().isTargetDarwin())
303 // Return true if this is a reference to a stub containing the address of the
304 // global, not the global itself.
305 return isGlobalStubReference(GVOp.getTargetFlags());
308 template<class CodeEmitter>
309 void Emitter<CodeEmitter>::emitDisplacementField(const MachineOperand *RelocOp,
311 intptr_t Adj /* = 0 */,
312 bool IsPCRel /* = true */) {
313 // If this is a simple integer displacement that doesn't require a relocation,
316 emitConstant(DispVal, 4);
320 // Otherwise, this is something that requires a relocation. Emit it as such
322 unsigned RelocType = Is64BitMode ?
323 (IsPCRel ? X86::reloc_pcrel_word : X86::reloc_absolute_word_sext)
324 : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
325 if (RelocOp->isGlobal()) {
326 // In 64-bit static small code model, we could potentially emit absolute.
327 // But it's probably not beneficial. If the MCE supports using RIP directly
328 // do it, otherwise fallback to absolute (this is determined by IsPCRel).
329 // 89 05 00 00 00 00 mov %eax,0(%rip) # PC-relative
330 // 89 04 25 00 00 00 00 mov %eax,0x0 # Absolute
331 bool Indirect = gvNeedsNonLazyPtr(*RelocOp, TM);
332 emitGlobalAddress(RelocOp->getGlobal(), RelocType, RelocOp->getOffset(),
334 } else if (RelocOp->isSymbol()) {
335 emitExternalSymbolAddress(RelocOp->getSymbolName(), RelocType);
336 } else if (RelocOp->isCPI()) {
337 emitConstPoolAddress(RelocOp->getIndex(), RelocType,
338 RelocOp->getOffset(), Adj);
340 assert(RelocOp->isJTI() && "Unexpected machine operand!");
341 emitJumpTableAddress(RelocOp->getIndex(), RelocType, Adj);
345 template<class CodeEmitter>
346 void Emitter<CodeEmitter>::emitMemModRMByte(const MachineInstr &MI,
347 unsigned Op,unsigned RegOpcodeField,
349 const MachineOperand &Op3 = MI.getOperand(Op+3);
351 const MachineOperand *DispForReloc = 0;
353 // Figure out what sort of displacement we have to handle here.
354 if (Op3.isGlobal()) {
356 } else if (Op3.isSymbol()) {
358 } else if (Op3.isCPI()) {
359 if (!MCE.earlyResolveAddresses() || Is64BitMode || IsPIC) {
362 DispVal += MCE.getConstantPoolEntryAddress(Op3.getIndex());
363 DispVal += Op3.getOffset();
365 } else if (Op3.isJTI()) {
366 if (!MCE.earlyResolveAddresses() || Is64BitMode || IsPIC) {
369 DispVal += MCE.getJumpTableEntryAddress(Op3.getIndex());
372 DispVal = Op3.getImm();
375 const MachineOperand &Base = MI.getOperand(Op);
376 const MachineOperand &Scale = MI.getOperand(Op+1);
377 const MachineOperand &IndexReg = MI.getOperand(Op+2);
379 unsigned BaseReg = Base.getReg();
381 // Indicate that the displacement will use an pcrel or absolute reference
382 // by default. MCEs able to resolve addresses on-the-fly use pcrel by default
383 // while others, unless explicit asked to use RIP, use absolute references.
384 bool IsPCRel = MCE.earlyResolveAddresses() ? true : false;
386 // Is a SIB byte needed?
387 // If no BaseReg, issue a RIP relative instruction only if the MCE can
388 // resolve addresses on-the-fly, otherwise use SIB (Intel Manual 2A, table
389 // 2-7) and absolute references.
390 if (// The SIB byte must be used if there is an index register.
391 IndexReg.getReg() == 0 &&
392 // The SIB byte must be used if the base is ESP/RSP.
393 BaseReg != X86::ESP && BaseReg != X86::RSP &&
394 // If there is no base register and we're in 64-bit mode, we need a SIB
395 // byte to emit an addr that is just 'disp32' (the non-RIP relative form).
396 (!Is64BitMode || BaseReg != 0)) {
397 if (BaseReg == 0 || // [disp32] in X86-32 mode
398 BaseReg == X86::RIP) { // [disp32+RIP] in X86-64 mode
399 MCE.emitByte(ModRMByte(0, RegOpcodeField, 5));
400 emitDisplacementField(DispForReloc, DispVal, PCAdj, true);
404 unsigned BaseRegNo = getX86RegNum(BaseReg);
405 // If the base is not EBP/ESP and there is no displacement, use simple
406 // indirect register encoding, this handles addresses like [EAX]. The
407 // encoding for [EBP] with no displacement means [disp32] so we handle it
408 // by emitting a displacement of 0 below.
409 if (!DispForReloc && DispVal == 0 && BaseRegNo != N86::EBP) {
410 MCE.emitByte(ModRMByte(0, RegOpcodeField, BaseRegNo));
414 // Otherwise, if the displacement fits in a byte, encode as [REG+disp8].
415 if (!DispForReloc && isDisp8(DispVal)) {
416 MCE.emitByte(ModRMByte(1, RegOpcodeField, BaseRegNo));
417 emitConstant(DispVal, 1);
421 // Otherwise, emit the most general non-SIB encoding: [REG+disp32]
422 MCE.emitByte(ModRMByte(2, RegOpcodeField, BaseRegNo));
423 emitDisplacementField(DispForReloc, DispVal, PCAdj, IsPCRel);
427 // Otherwise we need a SIB byte, so start by outputting the ModR/M byte first.
428 assert(IndexReg.getReg() != X86::ESP &&
429 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
431 bool ForceDisp32 = false;
432 bool ForceDisp8 = false;
434 // If there is no base register, we emit the special case SIB byte with
435 // MOD=0, BASE=4, to JUST get the index, scale, and displacement.
436 MCE.emitByte(ModRMByte(0, RegOpcodeField, 4));
438 } else if (DispForReloc) {
439 // Emit the normal disp32 encoding.
440 MCE.emitByte(ModRMByte(2, RegOpcodeField, 4));
442 } else if (DispVal == 0 && getX86RegNum(BaseReg) != N86::EBP) {
443 // Emit no displacement ModR/M byte
444 MCE.emitByte(ModRMByte(0, RegOpcodeField, 4));
445 } else if (isDisp8(DispVal)) {
446 // Emit the disp8 encoding...
447 MCE.emitByte(ModRMByte(1, RegOpcodeField, 4));
448 ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP
450 // Emit the normal disp32 encoding...
451 MCE.emitByte(ModRMByte(2, RegOpcodeField, 4));
454 // Calculate what the SS field value should be...
455 static const unsigned SSTable[] = { ~0, 0, 1, ~0, 2, ~0, ~0, ~0, 3 };
456 unsigned SS = SSTable[Scale.getImm()];
459 // Handle the SIB byte for the case where there is no base, see Intel
460 // Manual 2A, table 2-7. The displacement has already been output.
462 if (IndexReg.getReg())
463 IndexRegNo = getX86RegNum(IndexReg.getReg());
464 else // Examples: [ESP+1*<noreg>+4] or [scaled idx]+disp32 (MOD=0,BASE=5)
466 emitSIBByte(SS, IndexRegNo, 5);
468 unsigned BaseRegNo = getX86RegNum(BaseReg);
470 if (IndexReg.getReg())
471 IndexRegNo = getX86RegNum(IndexReg.getReg());
473 IndexRegNo = 4; // For example [ESP+1*<noreg>+4]
474 emitSIBByte(SS, IndexRegNo, BaseRegNo);
477 // Do we need to output a displacement?
479 emitConstant(DispVal, 1);
480 } else if (DispVal != 0 || ForceDisp32) {
481 emitDisplacementField(DispForReloc, DispVal, PCAdj, IsPCRel);
485 template<class CodeEmitter>
486 void Emitter<CodeEmitter>::emitInstruction(const MachineInstr &MI,
487 const TargetInstrDesc *Desc) {
490 MCE.processDebugLoc(MI.getDebugLoc(), true);
492 unsigned Opcode = Desc->Opcode;
494 // Emit the lock opcode prefix as needed.
495 if (Desc->TSFlags & X86II::LOCK)
498 // Emit segment override opcode prefix as needed.
499 switch (Desc->TSFlags & X86II::SegOvrMask) {
506 default: llvm_unreachable("Invalid segment!");
507 case 0: break; // No segment override!
510 // Emit the repeat opcode prefix as needed.
511 if ((Desc->TSFlags & X86II::Op0Mask) == X86II::REP)
514 // Emit the operand size opcode prefix as needed.
515 if (Desc->TSFlags & X86II::OpSize)
518 // Emit the address size opcode prefix as needed.
519 if (Desc->TSFlags & X86II::AdSize)
522 bool Need0FPrefix = false;
523 switch (Desc->TSFlags & X86II::Op0Mask) {
524 case X86II::TB: // Two-byte opcode prefix
525 case X86II::T8: // 0F 38
526 case X86II::TA: // 0F 3A
529 case X86II::TF: // F2 0F 38
533 case X86II::REP: break; // already handled.
534 case X86II::XS: // F3 0F
538 case X86II::XD: // F2 0F
542 case X86II::D8: case X86II::D9: case X86II::DA: case X86II::DB:
543 case X86II::DC: case X86II::DD: case X86II::DE: case X86II::DF:
545 (((Desc->TSFlags & X86II::Op0Mask)-X86II::D8)
546 >> X86II::Op0Shift));
547 break; // Two-byte opcode prefix
548 default: llvm_unreachable("Invalid prefix!");
549 case 0: break; // No prefix!
552 // Handle REX prefix.
554 if (unsigned REX = X86InstrInfo::determineREX(MI))
555 MCE.emitByte(0x40 | REX);
558 // 0x0F escape code must be emitted just before the opcode.
562 switch (Desc->TSFlags & X86II::Op0Mask) {
563 case X86II::TF: // F2 0F 38
564 case X86II::T8: // 0F 38
567 case X86II::TA: // 0F 3A
572 // If this is a two-address instruction, skip one of the register operands.
573 unsigned NumOps = Desc->getNumOperands();
575 if (NumOps > 1 && Desc->getOperandConstraint(1, TOI::TIED_TO) != -1)
577 else if (NumOps > 2 && Desc->getOperandConstraint(NumOps-1, TOI::TIED_TO)== 0)
578 // Skip the last source operand that is tied_to the dest reg. e.g. LXADD32
581 unsigned char BaseOpcode = X86II::getBaseOpcodeFor(Desc->TSFlags);
582 switch (Desc->TSFlags & X86II::FormMask) {
584 llvm_unreachable("Unknown FormMask value in X86 MachineCodeEmitter!");
586 // Remember the current PC offset, this is the PIC relocation
590 llvm_unreachable("psuedo instructions should be removed before code"
593 case TargetOpcode::INLINEASM:
594 // We allow inline assembler nodes with empty bodies - they can
595 // implicitly define registers, which is ok for JIT.
596 if (MI.getOperand(0).getSymbolName()[0])
597 llvm_report_error("JIT does not support inline asm!");
599 case TargetOpcode::DBG_LABEL:
600 case TargetOpcode::EH_LABEL:
601 case TargetOpcode::GC_LABEL:
602 MCE.emitLabel(MI.getOperand(0).getImm());
604 case TargetOpcode::IMPLICIT_DEF:
605 case TargetOpcode::KILL:
606 case X86::FP_REG_KILL:
608 case X86::MOVPC32r: {
609 // This emits the "call" portion of this pseudo instruction.
610 MCE.emitByte(BaseOpcode);
611 emitConstant(0, X86II::getSizeOfImm(Desc->TSFlags));
612 // Remember PIC base.
613 PICBaseOffset = (intptr_t) MCE.getCurrentPCOffset();
614 X86JITInfo *JTI = TM.getJITInfo();
615 JTI->setPICBase(MCE.getCurrentPCValue());
621 case X86II::RawFrm: {
622 MCE.emitByte(BaseOpcode);
627 const MachineOperand &MO = MI.getOperand(CurOp++);
629 DEBUG(dbgs() << "RawFrm CurOp " << CurOp << "\n");
630 DEBUG(dbgs() << "isMBB " << MO.isMBB() << "\n");
631 DEBUG(dbgs() << "isGlobal " << MO.isGlobal() << "\n");
632 DEBUG(dbgs() << "isSymbol " << MO.isSymbol() << "\n");
633 DEBUG(dbgs() << "isImm " << MO.isImm() << "\n");
636 emitPCRelativeBlockAddress(MO.getMBB());
641 emitGlobalAddress(MO.getGlobal(), X86::reloc_pcrel_word,
647 emitExternalSymbolAddress(MO.getSymbolName(), X86::reloc_pcrel_word);
651 assert(MO.isImm() && "Unknown RawFrm operand!");
652 if (Opcode == X86::CALLpcrel32 || Opcode == X86::CALL64pcrel32) {
653 // Fix up immediate operand for pc relative calls.
654 intptr_t Imm = (intptr_t)MO.getImm();
655 Imm = Imm - MCE.getCurrentPCValue() - 4;
656 emitConstant(Imm, X86II::getSizeOfImm(Desc->TSFlags));
658 emitConstant(MO.getImm(), X86II::getSizeOfImm(Desc->TSFlags));
662 case X86II::AddRegFrm: {
663 MCE.emitByte(BaseOpcode + getX86RegNum(MI.getOperand(CurOp++).getReg()));
668 const MachineOperand &MO1 = MI.getOperand(CurOp++);
669 unsigned Size = X86II::getSizeOfImm(Desc->TSFlags);
671 emitConstant(MO1.getImm(), Size);
675 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
676 : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
677 if (Opcode == X86::MOV64ri64i32)
678 rt = X86::reloc_absolute_word; // FIXME: add X86II flag?
679 // This should not occur on Darwin for relocatable objects.
680 if (Opcode == X86::MOV64ri)
681 rt = X86::reloc_absolute_dword; // FIXME: add X86II flag?
682 if (MO1.isGlobal()) {
683 bool Indirect = gvNeedsNonLazyPtr(MO1, TM);
684 emitGlobalAddress(MO1.getGlobal(), rt, MO1.getOffset(), 0,
686 } else if (MO1.isSymbol())
687 emitExternalSymbolAddress(MO1.getSymbolName(), rt);
688 else if (MO1.isCPI())
689 emitConstPoolAddress(MO1.getIndex(), rt);
690 else if (MO1.isJTI())
691 emitJumpTableAddress(MO1.getIndex(), rt);
695 case X86II::MRMDestReg: {
696 MCE.emitByte(BaseOpcode);
697 emitRegModRMByte(MI.getOperand(CurOp).getReg(),
698 getX86RegNum(MI.getOperand(CurOp+1).getReg()));
701 emitConstant(MI.getOperand(CurOp++).getImm(),
702 X86II::getSizeOfImm(Desc->TSFlags));
705 case X86II::MRMDestMem: {
706 MCE.emitByte(BaseOpcode);
707 emitMemModRMByte(MI, CurOp,
708 getX86RegNum(MI.getOperand(CurOp + X86AddrNumOperands)
710 CurOp += X86AddrNumOperands + 1;
712 emitConstant(MI.getOperand(CurOp++).getImm(),
713 X86II::getSizeOfImm(Desc->TSFlags));
717 case X86II::MRMSrcReg:
718 MCE.emitByte(BaseOpcode);
719 emitRegModRMByte(MI.getOperand(CurOp+1).getReg(),
720 getX86RegNum(MI.getOperand(CurOp).getReg()));
723 emitConstant(MI.getOperand(CurOp++).getImm(),
724 X86II::getSizeOfImm(Desc->TSFlags));
727 case X86II::MRMSrcMem: {
728 // FIXME: Maybe lea should have its own form?
730 if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r ||
731 Opcode == X86::LEA16r || Opcode == X86::LEA32r)
732 AddrOperands = X86AddrNumOperands - 1; // No segment register
734 AddrOperands = X86AddrNumOperands;
736 intptr_t PCAdj = (CurOp + AddrOperands + 1 != NumOps) ?
737 X86II::getSizeOfImm(Desc->TSFlags) : 0;
739 MCE.emitByte(BaseOpcode);
740 emitMemModRMByte(MI, CurOp+1, getX86RegNum(MI.getOperand(CurOp).getReg()),
742 CurOp += AddrOperands + 1;
744 emitConstant(MI.getOperand(CurOp++).getImm(),
745 X86II::getSizeOfImm(Desc->TSFlags));
749 case X86II::MRM0r: case X86II::MRM1r:
750 case X86II::MRM2r: case X86II::MRM3r:
751 case X86II::MRM4r: case X86II::MRM5r:
752 case X86II::MRM6r: case X86II::MRM7r: {
753 MCE.emitByte(BaseOpcode);
755 // Special handling of lfence, mfence, monitor, and mwait.
756 if (Desc->getOpcode() == X86::LFENCE ||
757 Desc->getOpcode() == X86::MFENCE ||
758 Desc->getOpcode() == X86::MONITOR ||
759 Desc->getOpcode() == X86::MWAIT) {
760 emitRegModRMByte((Desc->TSFlags & X86II::FormMask)-X86II::MRM0r);
762 switch (Desc->getOpcode()) {
772 emitRegModRMByte(MI.getOperand(CurOp++).getReg(),
773 (Desc->TSFlags & X86II::FormMask)-X86II::MRM0r);
779 const MachineOperand &MO1 = MI.getOperand(CurOp++);
780 unsigned Size = X86II::getSizeOfImm(Desc->TSFlags);
782 emitConstant(MO1.getImm(), Size);
786 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
787 : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
788 if (Opcode == X86::MOV64ri32)
789 rt = X86::reloc_absolute_word_sext; // FIXME: add X86II flag?
790 if (MO1.isGlobal()) {
791 bool Indirect = gvNeedsNonLazyPtr(MO1, TM);
792 emitGlobalAddress(MO1.getGlobal(), rt, MO1.getOffset(), 0,
794 } else if (MO1.isSymbol())
795 emitExternalSymbolAddress(MO1.getSymbolName(), rt);
796 else if (MO1.isCPI())
797 emitConstPoolAddress(MO1.getIndex(), rt);
798 else if (MO1.isJTI())
799 emitJumpTableAddress(MO1.getIndex(), rt);
803 case X86II::MRM0m: case X86II::MRM1m:
804 case X86II::MRM2m: case X86II::MRM3m:
805 case X86II::MRM4m: case X86II::MRM5m:
806 case X86II::MRM6m: case X86II::MRM7m: {
807 intptr_t PCAdj = (CurOp + X86AddrNumOperands != NumOps) ?
808 (MI.getOperand(CurOp+X86AddrNumOperands).isImm() ?
809 X86II::getSizeOfImm(Desc->TSFlags) : 4) : 0;
811 MCE.emitByte(BaseOpcode);
812 emitMemModRMByte(MI, CurOp, (Desc->TSFlags & X86II::FormMask)-X86II::MRM0m,
814 CurOp += X86AddrNumOperands;
819 const MachineOperand &MO = MI.getOperand(CurOp++);
820 unsigned Size = X86II::getSizeOfImm(Desc->TSFlags);
822 emitConstant(MO.getImm(), Size);
826 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
827 : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
828 if (Opcode == X86::MOV64mi32)
829 rt = X86::reloc_absolute_word_sext; // FIXME: add X86II flag?
831 bool Indirect = gvNeedsNonLazyPtr(MO, TM);
832 emitGlobalAddress(MO.getGlobal(), rt, MO.getOffset(), 0,
834 } else if (MO.isSymbol())
835 emitExternalSymbolAddress(MO.getSymbolName(), rt);
837 emitConstPoolAddress(MO.getIndex(), rt);
839 emitJumpTableAddress(MO.getIndex(), rt);
843 case X86II::MRMInitReg:
844 MCE.emitByte(BaseOpcode);
845 // Duplicate register, used by things like MOV8r0 (aka xor reg,reg).
846 emitRegModRMByte(MI.getOperand(CurOp).getReg(),
847 getX86RegNum(MI.getOperand(CurOp).getReg()));
852 if (!Desc->isVariadic() && CurOp != NumOps) {
854 dbgs() << "Cannot encode all operands of: " << MI << "\n";
859 MCE.processDebugLoc(MI.getDebugLoc(), false);
862 // Adapt the Emitter / CodeEmitter interfaces to MCCodeEmitter.
864 // FIXME: This is a total hack designed to allow work on llvm-mc to proceed
865 // without being blocked on various cleanups needed to support a clean interface
866 // to instruction encoding.
870 #include "llvm/DerivedTypes.h"
873 class MCSingleInstructionCodeEmitter : public MachineCodeEmitter {
877 MCSingleInstructionCodeEmitter() { reset(); }
881 BufferEnd = array_endof(Data);
886 return StringRef(reinterpret_cast<char*>(BufferBegin),
887 CurBufferPtr - BufferBegin);
890 virtual void startFunction(MachineFunction &F) {}
891 virtual bool finishFunction(MachineFunction &F) { return false; }
892 virtual void emitLabel(uint64_t LabelID) {}
893 virtual void StartMachineBasicBlock(MachineBasicBlock *MBB) {}
894 virtual bool earlyResolveAddresses() const { return false; }
895 virtual void addRelocation(const MachineRelocation &MR) { }
896 virtual uintptr_t getConstantPoolEntryAddress(unsigned Index) const {
899 virtual uintptr_t getJumpTableEntryAddress(unsigned Index) const {
902 virtual uintptr_t getMachineBasicBlockAddress(MachineBasicBlock *MBB) const {
905 virtual uintptr_t getLabelAddress(uint64_t LabelID) const {
908 virtual void setModuleInfo(MachineModuleInfo* Info) {}
911 class X86MCCodeEmitter : public MCCodeEmitter {
912 X86MCCodeEmitter(const X86MCCodeEmitter &); // DO NOT IMPLEMENT
913 void operator=(const X86MCCodeEmitter &); // DO NOT IMPLEMENT
916 X86TargetMachine &TM;
917 llvm::Function *DummyF;
919 mutable llvm::MachineFunction *DummyMF;
920 llvm::MachineBasicBlock *DummyMBB;
922 MCSingleInstructionCodeEmitter *InstrEmitter;
923 Emitter<MachineCodeEmitter> *Emit;
926 X86MCCodeEmitter(X86TargetMachine &_TM) : TM(_TM) {
927 // Verily, thou shouldst avert thine eyes.
928 const llvm::FunctionType *FTy =
929 FunctionType::get(llvm::Type::getVoidTy(getGlobalContext()), false);
930 DummyF = Function::Create(FTy, GlobalValue::InternalLinkage);
931 DummyTD = new TargetData("");
932 DummyMF = new MachineFunction(DummyF, TM, 0);
933 DummyMBB = DummyMF->CreateMachineBasicBlock();
935 InstrEmitter = new MCSingleInstructionCodeEmitter();
936 Emit = new Emitter<MachineCodeEmitter>(TM, *InstrEmitter,
940 ~X86MCCodeEmitter() {
947 unsigned getNumFixupKinds() const {
951 MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
952 static MCFixupKindInfo Infos[] = {
953 { "reloc_pcrel_word", 0, 4 * 8 },
954 { "reloc_picrel_word", 0, 4 * 8 },
955 { "reloc_absolute_word", 0, 4 * 8 },
956 { "reloc_absolute_word_sext", 0, 4 * 8 },
957 { "reloc_absolute_dword", 0, 8 * 8 }
960 assert(Kind >= FirstTargetFixupKind && Kind < MaxTargetFixupKind &&
962 return Infos[Kind - FirstTargetFixupKind];
965 bool AddRegToInstr(const MCInst &MI, MachineInstr *Instr,
966 unsigned Start) const {
967 if (Start + 1 > MI.getNumOperands())
970 const MCOperand &Op = MI.getOperand(Start);
971 if (!Op.isReg()) return false;
973 Instr->addOperand(MachineOperand::CreateReg(Op.getReg(), false));
977 bool AddImmToInstr(const MCInst &MI, MachineInstr *Instr,
978 unsigned Start) const {
979 if (Start + 1 > MI.getNumOperands())
982 const MCOperand &Op = MI.getOperand(Start);
984 Instr->addOperand(MachineOperand::CreateImm(Op.getImm()));
990 const MCExpr *Expr = Op.getExpr();
991 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr)) {
992 Instr->addOperand(MachineOperand::CreateImm(CE->getValue()));
996 // FIXME: Relocation / fixup.
997 Instr->addOperand(MachineOperand::CreateImm(0));
1001 bool AddLMemToInstr(const MCInst &MI, MachineInstr *Instr,
1002 unsigned Start) const {
1003 return (AddRegToInstr(MI, Instr, Start + 0) &&
1004 AddImmToInstr(MI, Instr, Start + 1) &&
1005 AddRegToInstr(MI, Instr, Start + 2) &&
1006 AddImmToInstr(MI, Instr, Start + 3));
1009 bool AddMemToInstr(const MCInst &MI, MachineInstr *Instr,
1010 unsigned Start) const {
1011 return (AddRegToInstr(MI, Instr, Start + 0) &&
1012 AddImmToInstr(MI, Instr, Start + 1) &&
1013 AddRegToInstr(MI, Instr, Start + 2) &&
1014 AddImmToInstr(MI, Instr, Start + 3) &&
1015 AddRegToInstr(MI, Instr, Start + 4));
1018 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
1019 SmallVectorImpl<MCFixup> &Fixups) const {
1022 // Convert the MCInst to a MachineInstr so we can (ab)use the regular
1024 const X86InstrInfo &II = *TM.getInstrInfo();
1025 const TargetInstrDesc &Desc = II.get(MI.getOpcode());
1026 MachineInstr *Instr = DummyMF->CreateMachineInstr(Desc, DebugLoc());
1027 DummyMBB->push_back(Instr);
1029 unsigned Opcode = MI.getOpcode();
1030 unsigned NumOps = MI.getNumOperands();
1032 bool AddTied = false;
1033 if (NumOps > 1 && Desc.getOperandConstraint(1, TOI::TIED_TO) != -1)
1035 else if (NumOps > 2 &&
1036 Desc.getOperandConstraint(NumOps-1, TOI::TIED_TO)== 0)
1037 // Skip the last source operand that is tied_to the dest reg. e.g. LXADD32
1041 switch (Desc.TSFlags & X86II::FormMask) {
1042 case X86II::MRMDestReg:
1043 case X86II::MRMSrcReg:
1044 // Matching doesn't fill this in completely, we have to choose operand 0
1045 // for a tied register.
1046 OK &= AddRegToInstr(MI, Instr, CurOp++);
1048 OK &= AddRegToInstr(MI, Instr, CurOp++ - 1);
1049 OK &= AddRegToInstr(MI, Instr, CurOp++);
1051 OK &= AddImmToInstr(MI, Instr, CurOp);
1055 if (CurOp < NumOps) {
1056 // Hack to make branches work.
1057 if (!(Desc.TSFlags & X86II::ImmMask) &&
1058 MI.getOperand(0).isExpr() &&
1059 isa<MCSymbolRefExpr>(MI.getOperand(0).getExpr()))
1060 Instr->addOperand(MachineOperand::CreateMBB(DummyMBB));
1062 OK &= AddImmToInstr(MI, Instr, CurOp);
1066 case X86II::AddRegFrm:
1067 // Matching doesn't fill this in completely, we have to choose operand 0
1068 // for a tied register.
1069 OK &= AddRegToInstr(MI, Instr, CurOp++);
1071 OK &= AddRegToInstr(MI, Instr, CurOp++ - 1);
1073 OK &= AddImmToInstr(MI, Instr, CurOp);
1076 case X86II::MRM0r: case X86II::MRM1r:
1077 case X86II::MRM2r: case X86II::MRM3r:
1078 case X86II::MRM4r: case X86II::MRM5r:
1079 case X86II::MRM6r: case X86II::MRM7r:
1080 // Matching doesn't fill this in completely, we have to choose operand 0
1081 // for a tied register.
1082 OK &= AddRegToInstr(MI, Instr, CurOp++);
1084 OK &= AddRegToInstr(MI, Instr, CurOp++ - 1);
1086 OK &= AddImmToInstr(MI, Instr, CurOp);
1089 case X86II::MRM0m: case X86II::MRM1m:
1090 case X86II::MRM2m: case X86II::MRM3m:
1091 case X86II::MRM4m: case X86II::MRM5m:
1092 case X86II::MRM6m: case X86II::MRM7m:
1093 OK &= AddMemToInstr(MI, Instr, CurOp); CurOp += 5;
1095 OK &= AddImmToInstr(MI, Instr, CurOp);
1098 case X86II::MRMSrcMem:
1099 // Matching doesn't fill this in completely, we have to choose operand 0
1100 // for a tied register.
1101 OK &= AddRegToInstr(MI, Instr, CurOp++);
1103 OK &= AddRegToInstr(MI, Instr, CurOp++ - 1);
1104 if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r ||
1105 Opcode == X86::LEA16r || Opcode == X86::LEA32r)
1106 OK &= AddLMemToInstr(MI, Instr, CurOp);
1108 OK &= AddMemToInstr(MI, Instr, CurOp);
1111 case X86II::MRMDestMem:
1112 OK &= AddMemToInstr(MI, Instr, CurOp); CurOp += 5;
1113 OK &= AddRegToInstr(MI, Instr, CurOp);
1117 case X86II::MRMInitReg:
1124 dbgs() << "couldn't convert inst '";
1126 dbgs() << "' to machine instr:\n";
1130 InstrEmitter->reset();
1132 Emit->emitInstruction(*Instr, &Desc);
1133 OS << InstrEmitter->str();
1135 Instr->eraseFromParent();
1140 #include "llvm/Support/CommandLine.h"
1142 static cl::opt<bool> EnableNewEncoder("enable-new-x86-encoder",
1146 // Ok, now you can look.
1147 MCCodeEmitter *llvm::createHeinousX86MCCodeEmitter(const Target &T,
1148 TargetMachine &TM) {
1150 // FIXME: Remove the heinous one when the new one works.
1151 if (EnableNewEncoder) {
1152 if (TM.getTargetData()->getPointerSize() == 4)
1153 return createX86_32MCCodeEmitter(T, TM);
1154 return createX86_64MCCodeEmitter(T, TM);
1157 return new X86MCCodeEmitter(static_cast<X86TargetMachine&>(TM));