1 //===-- X86/X86CodeEmitter.cpp - Convert X86 code to machine code ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the pass that transforms the X86 machine instructions into
11 // relocatable machine code.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-emitter"
16 #include "X86InstrInfo.h"
17 #include "X86JITInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "X86Relocations.h"
22 #include "llvm/LLVMContext.h"
23 #include "llvm/PassManager.h"
24 #include "llvm/CodeGen/JITCodeEmitter.h"
25 #include "llvm/CodeGen/MachineFunctionPass.h"
26 #include "llvm/CodeGen/MachineInstr.h"
27 #include "llvm/CodeGen/MachineModuleInfo.h"
28 #include "llvm/CodeGen/Passes.h"
29 #include "llvm/Function.h"
30 #include "llvm/ADT/Statistic.h"
31 #include "llvm/MC/MCCodeEmitter.h"
32 #include "llvm/MC/MCExpr.h"
33 #include "llvm/MC/MCInst.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/ErrorHandling.h"
36 #include "llvm/Support/raw_ostream.h"
37 #include "llvm/Target/TargetOptions.h"
40 STATISTIC(NumEmitted, "Number of machine instructions emitted");
43 template<class CodeEmitter>
44 class Emitter : public MachineFunctionPass {
45 const X86InstrInfo *II;
49 MachineModuleInfo *MMI;
50 intptr_t PICBaseOffset;
55 explicit Emitter(X86TargetMachine &tm, CodeEmitter &mce)
56 : MachineFunctionPass(&ID), II(0), TD(0), TM(tm),
57 MCE(mce), PICBaseOffset(0), Is64BitMode(false),
58 IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
59 Emitter(X86TargetMachine &tm, CodeEmitter &mce,
60 const X86InstrInfo &ii, const TargetData &td, bool is64)
61 : MachineFunctionPass(&ID), II(&ii), TD(&td), TM(tm),
62 MCE(mce), PICBaseOffset(0), Is64BitMode(is64),
63 IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
65 bool runOnMachineFunction(MachineFunction &MF);
67 virtual const char *getPassName() const {
68 return "X86 Machine Code Emitter";
71 void emitInstruction(const MachineInstr &MI,
72 const TargetInstrDesc *Desc);
74 void getAnalysisUsage(AnalysisUsage &AU) const {
76 AU.addRequired<MachineModuleInfo>();
77 MachineFunctionPass::getAnalysisUsage(AU);
81 void emitPCRelativeBlockAddress(MachineBasicBlock *MBB);
82 void emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
83 intptr_t Disp = 0, intptr_t PCAdj = 0,
84 bool Indirect = false);
85 void emitExternalSymbolAddress(const char *ES, unsigned Reloc);
86 void emitConstPoolAddress(unsigned CPI, unsigned Reloc, intptr_t Disp = 0,
88 void emitJumpTableAddress(unsigned JTI, unsigned Reloc,
91 void emitDisplacementField(const MachineOperand *RelocOp, int DispVal,
92 intptr_t Adj = 0, bool IsPCRel = true);
94 void emitRegModRMByte(unsigned ModRMReg, unsigned RegOpcodeField);
95 void emitRegModRMByte(unsigned RegOpcodeField);
96 void emitSIBByte(unsigned SS, unsigned Index, unsigned Base);
97 void emitConstant(uint64_t Val, unsigned Size);
99 void emitMemModRMByte(const MachineInstr &MI,
100 unsigned Op, unsigned RegOpcodeField,
103 unsigned getX86RegNum(unsigned RegNo) const;
106 template<class CodeEmitter>
107 char Emitter<CodeEmitter>::ID = 0;
108 } // end anonymous namespace.
110 /// createX86CodeEmitterPass - Return a pass that emits the collected X86 code
111 /// to the specified templated MachineCodeEmitter object.
112 FunctionPass *llvm::createX86JITCodeEmitterPass(X86TargetMachine &TM,
113 JITCodeEmitter &JCE) {
114 return new Emitter<JITCodeEmitter>(TM, JCE);
117 template<class CodeEmitter>
118 bool Emitter<CodeEmitter>::runOnMachineFunction(MachineFunction &MF) {
119 MMI = &getAnalysis<MachineModuleInfo>();
120 MCE.setModuleInfo(MMI);
122 II = TM.getInstrInfo();
123 TD = TM.getTargetData();
124 Is64BitMode = TM.getSubtarget<X86Subtarget>().is64Bit();
125 IsPIC = TM.getRelocationModel() == Reloc::PIC_;
128 DEBUG(dbgs() << "JITTing function '"
129 << MF.getFunction()->getName() << "'\n");
130 MCE.startFunction(MF);
131 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
133 MCE.StartMachineBasicBlock(MBB);
134 for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
136 const TargetInstrDesc &Desc = I->getDesc();
137 emitInstruction(*I, &Desc);
138 // MOVPC32r is basically a call plus a pop instruction.
139 if (Desc.getOpcode() == X86::MOVPC32r)
140 emitInstruction(*I, &II->get(X86::POP32r));
141 ++NumEmitted; // Keep track of the # of mi's emitted
144 } while (MCE.finishFunction(MF));
149 /// determineREX - Determine if the MachineInstr has to be encoded with a X86-64
150 /// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand
151 /// size, and 3) use of X86-64 extended registers.
152 static unsigned determineREX(const MachineInstr &MI) {
154 const TargetInstrDesc &Desc = MI.getDesc();
156 // Pseudo instructions do not need REX prefix byte.
157 if ((Desc.TSFlags & X86II::FormMask) == X86II::Pseudo)
159 if (Desc.TSFlags & X86II::REX_W)
162 unsigned NumOps = Desc.getNumOperands();
164 bool isTwoAddr = NumOps > 1 &&
165 Desc.getOperandConstraint(1, TOI::TIED_TO) != -1;
167 // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix.
168 unsigned i = isTwoAddr ? 1 : 0;
169 for (unsigned e = NumOps; i != e; ++i) {
170 const MachineOperand& MO = MI.getOperand(i);
172 unsigned Reg = MO.getReg();
173 if (X86InstrInfo::isX86_64NonExtLowByteReg(Reg))
178 switch (Desc.TSFlags & X86II::FormMask) {
179 case X86II::MRMInitReg:
180 if (X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0)))
181 REX |= (1 << 0) | (1 << 2);
183 case X86II::MRMSrcReg: {
184 if (X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0)))
186 i = isTwoAddr ? 2 : 1;
187 for (unsigned e = NumOps; i != e; ++i) {
188 const MachineOperand& MO = MI.getOperand(i);
189 if (X86InstrInfo::isX86_64ExtendedReg(MO))
194 case X86II::MRMSrcMem: {
195 if (X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0)))
198 i = isTwoAddr ? 2 : 1;
199 for (; i != NumOps; ++i) {
200 const MachineOperand& MO = MI.getOperand(i);
202 if (X86InstrInfo::isX86_64ExtendedReg(MO))
209 case X86II::MRM0m: case X86II::MRM1m:
210 case X86II::MRM2m: case X86II::MRM3m:
211 case X86II::MRM4m: case X86II::MRM5m:
212 case X86II::MRM6m: case X86II::MRM7m:
213 case X86II::MRMDestMem: {
214 unsigned e = (isTwoAddr ? X86::AddrNumOperands+1 : X86::AddrNumOperands);
215 i = isTwoAddr ? 1 : 0;
216 if (NumOps > e && X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(e)))
219 for (; i != e; ++i) {
220 const MachineOperand& MO = MI.getOperand(i);
222 if (X86InstrInfo::isX86_64ExtendedReg(MO))
230 if (X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0)))
232 i = isTwoAddr ? 2 : 1;
233 for (unsigned e = NumOps; i != e; ++i) {
234 const MachineOperand& MO = MI.getOperand(i);
235 if (X86InstrInfo::isX86_64ExtendedReg(MO))
246 /// emitPCRelativeBlockAddress - This method keeps track of the information
247 /// necessary to resolve the address of this block later and emits a dummy
250 template<class CodeEmitter>
251 void Emitter<CodeEmitter>::emitPCRelativeBlockAddress(MachineBasicBlock *MBB) {
252 // Remember where this reference was and where it is to so we can
253 // deal with it later.
254 MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
255 X86::reloc_pcrel_word, MBB));
259 /// emitGlobalAddress - Emit the specified address to the code stream assuming
260 /// this is part of a "take the address of a global" instruction.
262 template<class CodeEmitter>
263 void Emitter<CodeEmitter>::emitGlobalAddress(const GlobalValue *GV,
265 intptr_t Disp /* = 0 */,
266 intptr_t PCAdj /* = 0 */,
267 bool Indirect /* = false */) {
268 intptr_t RelocCST = Disp;
269 if (Reloc == X86::reloc_picrel_word)
270 RelocCST = PICBaseOffset;
271 else if (Reloc == X86::reloc_pcrel_word)
273 MachineRelocation MR = Indirect
274 ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc,
275 const_cast<GlobalValue *>(GV),
277 : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
278 const_cast<GlobalValue *>(GV), RelocCST, false);
279 MCE.addRelocation(MR);
280 // The relocated value will be added to the displacement
281 if (Reloc == X86::reloc_absolute_dword)
282 MCE.emitDWordLE(Disp);
284 MCE.emitWordLE((int32_t)Disp);
287 /// emitExternalSymbolAddress - Arrange for the address of an external symbol to
288 /// be emitted to the current location in the function, and allow it to be PC
290 template<class CodeEmitter>
291 void Emitter<CodeEmitter>::emitExternalSymbolAddress(const char *ES,
293 intptr_t RelocCST = (Reloc == X86::reloc_picrel_word) ? PICBaseOffset : 0;
295 // X86 never needs stubs because instruction selection will always pick
296 // an instruction sequence that is large enough to hold any address
298 // (see X86ISelLowering.cpp, near 2039: X86TargetLowering::LowerCall)
299 bool NeedStub = false;
300 MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
303 if (Reloc == X86::reloc_absolute_dword)
309 /// emitConstPoolAddress - Arrange for the address of an constant pool
310 /// to be emitted to the current location in the function, and allow it to be PC
312 template<class CodeEmitter>
313 void Emitter<CodeEmitter>::emitConstPoolAddress(unsigned CPI, unsigned Reloc,
314 intptr_t Disp /* = 0 */,
315 intptr_t PCAdj /* = 0 */) {
316 intptr_t RelocCST = 0;
317 if (Reloc == X86::reloc_picrel_word)
318 RelocCST = PICBaseOffset;
319 else if (Reloc == X86::reloc_pcrel_word)
321 MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
322 Reloc, CPI, RelocCST));
323 // The relocated value will be added to the displacement
324 if (Reloc == X86::reloc_absolute_dword)
325 MCE.emitDWordLE(Disp);
327 MCE.emitWordLE((int32_t)Disp);
330 /// emitJumpTableAddress - Arrange for the address of a jump table to
331 /// be emitted to the current location in the function, and allow it to be PC
333 template<class CodeEmitter>
334 void Emitter<CodeEmitter>::emitJumpTableAddress(unsigned JTI, unsigned Reloc,
335 intptr_t PCAdj /* = 0 */) {
336 intptr_t RelocCST = 0;
337 if (Reloc == X86::reloc_picrel_word)
338 RelocCST = PICBaseOffset;
339 else if (Reloc == X86::reloc_pcrel_word)
341 MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
342 Reloc, JTI, RelocCST));
343 // The relocated value will be added to the displacement
344 if (Reloc == X86::reloc_absolute_dword)
350 template<class CodeEmitter>
351 unsigned Emitter<CodeEmitter>::getX86RegNum(unsigned RegNo) const {
352 return X86RegisterInfo::getX86RegNum(RegNo);
355 inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
357 assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
358 return RM | (RegOpcode << 3) | (Mod << 6);
361 template<class CodeEmitter>
362 void Emitter<CodeEmitter>::emitRegModRMByte(unsigned ModRMReg,
363 unsigned RegOpcodeFld){
364 MCE.emitByte(ModRMByte(3, RegOpcodeFld, getX86RegNum(ModRMReg)));
367 template<class CodeEmitter>
368 void Emitter<CodeEmitter>::emitRegModRMByte(unsigned RegOpcodeFld) {
369 MCE.emitByte(ModRMByte(3, RegOpcodeFld, 0));
372 template<class CodeEmitter>
373 void Emitter<CodeEmitter>::emitSIBByte(unsigned SS,
376 // SIB byte is in the same format as the ModRMByte...
377 MCE.emitByte(ModRMByte(SS, Index, Base));
380 template<class CodeEmitter>
381 void Emitter<CodeEmitter>::emitConstant(uint64_t Val, unsigned Size) {
382 // Output the constant in little endian byte order...
383 for (unsigned i = 0; i != Size; ++i) {
384 MCE.emitByte(Val & 255);
389 /// isDisp8 - Return true if this signed displacement fits in a 8-bit
390 /// sign-extended field.
391 static bool isDisp8(int Value) {
392 return Value == (signed char)Value;
395 static bool gvNeedsNonLazyPtr(const MachineOperand &GVOp,
396 const TargetMachine &TM) {
397 // For Darwin-64, simulate the linktime GOT by using the same non-lazy-pointer
398 // mechanism as 32-bit mode.
399 if (TM.getSubtarget<X86Subtarget>().is64Bit() &&
400 !TM.getSubtarget<X86Subtarget>().isTargetDarwin())
403 // Return true if this is a reference to a stub containing the address of the
404 // global, not the global itself.
405 return isGlobalStubReference(GVOp.getTargetFlags());
408 template<class CodeEmitter>
409 void Emitter<CodeEmitter>::emitDisplacementField(const MachineOperand *RelocOp,
411 intptr_t Adj /* = 0 */,
412 bool IsPCRel /* = true */) {
413 // If this is a simple integer displacement that doesn't require a relocation,
416 emitConstant(DispVal, 4);
420 // Otherwise, this is something that requires a relocation. Emit it as such
422 unsigned RelocType = Is64BitMode ?
423 (IsPCRel ? X86::reloc_pcrel_word : X86::reloc_absolute_word_sext)
424 : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
425 if (RelocOp->isGlobal()) {
426 // In 64-bit static small code model, we could potentially emit absolute.
427 // But it's probably not beneficial. If the MCE supports using RIP directly
428 // do it, otherwise fallback to absolute (this is determined by IsPCRel).
429 // 89 05 00 00 00 00 mov %eax,0(%rip) # PC-relative
430 // 89 04 25 00 00 00 00 mov %eax,0x0 # Absolute
431 bool Indirect = gvNeedsNonLazyPtr(*RelocOp, TM);
432 emitGlobalAddress(RelocOp->getGlobal(), RelocType, RelocOp->getOffset(),
434 } else if (RelocOp->isSymbol()) {
435 emitExternalSymbolAddress(RelocOp->getSymbolName(), RelocType);
436 } else if (RelocOp->isCPI()) {
437 emitConstPoolAddress(RelocOp->getIndex(), RelocType,
438 RelocOp->getOffset(), Adj);
440 assert(RelocOp->isJTI() && "Unexpected machine operand!");
441 emitJumpTableAddress(RelocOp->getIndex(), RelocType, Adj);
445 template<class CodeEmitter>
446 void Emitter<CodeEmitter>::emitMemModRMByte(const MachineInstr &MI,
447 unsigned Op,unsigned RegOpcodeField,
449 const MachineOperand &Op3 = MI.getOperand(Op+3);
451 const MachineOperand *DispForReloc = 0;
453 // Figure out what sort of displacement we have to handle here.
454 if (Op3.isGlobal()) {
456 } else if (Op3.isSymbol()) {
458 } else if (Op3.isCPI()) {
459 if (!MCE.earlyResolveAddresses() || Is64BitMode || IsPIC) {
462 DispVal += MCE.getConstantPoolEntryAddress(Op3.getIndex());
463 DispVal += Op3.getOffset();
465 } else if (Op3.isJTI()) {
466 if (!MCE.earlyResolveAddresses() || Is64BitMode || IsPIC) {
469 DispVal += MCE.getJumpTableEntryAddress(Op3.getIndex());
472 DispVal = Op3.getImm();
475 const MachineOperand &Base = MI.getOperand(Op);
476 const MachineOperand &Scale = MI.getOperand(Op+1);
477 const MachineOperand &IndexReg = MI.getOperand(Op+2);
479 unsigned BaseReg = Base.getReg();
481 // Handle %rip relative addressing.
482 if (BaseReg == X86::RIP ||
483 (Is64BitMode && DispForReloc)) { // [disp32+RIP] in X86-64 mode
484 assert(IndexReg.getReg() == 0 && Is64BitMode &&
485 "Invalid rip-relative address");
486 MCE.emitByte(ModRMByte(0, RegOpcodeField, 5));
487 emitDisplacementField(DispForReloc, DispVal, PCAdj, true);
491 // Indicate that the displacement will use an pcrel or absolute reference
492 // by default. MCEs able to resolve addresses on-the-fly use pcrel by default
493 // while others, unless explicit asked to use RIP, use absolute references.
494 bool IsPCRel = MCE.earlyResolveAddresses() ? true : false;
496 // Is a SIB byte needed?
497 // If no BaseReg, issue a RIP relative instruction only if the MCE can
498 // resolve addresses on-the-fly, otherwise use SIB (Intel Manual 2A, table
499 // 2-7) and absolute references.
500 unsigned BaseRegNo = -1U;
501 if (BaseReg != 0 && BaseReg != X86::RIP)
502 BaseRegNo = getX86RegNum(BaseReg);
504 if (// The SIB byte must be used if there is an index register.
505 IndexReg.getReg() == 0 &&
506 // The SIB byte must be used if the base is ESP/RSP/R12, all of which
507 // encode to an R/M value of 4, which indicates that a SIB byte is
509 BaseRegNo != N86::ESP &&
510 // If there is no base register and we're in 64-bit mode, we need a SIB
511 // byte to emit an addr that is just 'disp32' (the non-RIP relative form).
512 (!Is64BitMode || BaseReg != 0)) {
513 if (BaseReg == 0 || // [disp32] in X86-32 mode
514 BaseReg == X86::RIP) { // [disp32+RIP] in X86-64 mode
515 MCE.emitByte(ModRMByte(0, RegOpcodeField, 5));
516 emitDisplacementField(DispForReloc, DispVal, PCAdj, true);
520 // If the base is not EBP/ESP and there is no displacement, use simple
521 // indirect register encoding, this handles addresses like [EAX]. The
522 // encoding for [EBP] with no displacement means [disp32] so we handle it
523 // by emitting a displacement of 0 below.
524 if (!DispForReloc && DispVal == 0 && BaseRegNo != N86::EBP) {
525 MCE.emitByte(ModRMByte(0, RegOpcodeField, BaseRegNo));
529 // Otherwise, if the displacement fits in a byte, encode as [REG+disp8].
530 if (!DispForReloc && isDisp8(DispVal)) {
531 MCE.emitByte(ModRMByte(1, RegOpcodeField, BaseRegNo));
532 emitConstant(DispVal, 1);
536 // Otherwise, emit the most general non-SIB encoding: [REG+disp32]
537 MCE.emitByte(ModRMByte(2, RegOpcodeField, BaseRegNo));
538 emitDisplacementField(DispForReloc, DispVal, PCAdj, IsPCRel);
542 // Otherwise we need a SIB byte, so start by outputting the ModR/M byte first.
543 assert(IndexReg.getReg() != X86::ESP &&
544 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
546 bool ForceDisp32 = false;
547 bool ForceDisp8 = false;
549 // If there is no base register, we emit the special case SIB byte with
550 // MOD=0, BASE=4, to JUST get the index, scale, and displacement.
551 MCE.emitByte(ModRMByte(0, RegOpcodeField, 4));
553 } else if (DispForReloc) {
554 // Emit the normal disp32 encoding.
555 MCE.emitByte(ModRMByte(2, RegOpcodeField, 4));
557 } else if (DispVal == 0 && BaseRegNo != N86::EBP) {
558 // Emit no displacement ModR/M byte
559 MCE.emitByte(ModRMByte(0, RegOpcodeField, 4));
560 } else if (isDisp8(DispVal)) {
561 // Emit the disp8 encoding...
562 MCE.emitByte(ModRMByte(1, RegOpcodeField, 4));
563 ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP
565 // Emit the normal disp32 encoding...
566 MCE.emitByte(ModRMByte(2, RegOpcodeField, 4));
569 // Calculate what the SS field value should be...
570 static const unsigned SSTable[] = { ~0, 0, 1, ~0, 2, ~0, ~0, ~0, 3 };
571 unsigned SS = SSTable[Scale.getImm()];
574 // Handle the SIB byte for the case where there is no base, see Intel
575 // Manual 2A, table 2-7. The displacement has already been output.
577 if (IndexReg.getReg())
578 IndexRegNo = getX86RegNum(IndexReg.getReg());
579 else // Examples: [ESP+1*<noreg>+4] or [scaled idx]+disp32 (MOD=0,BASE=5)
581 emitSIBByte(SS, IndexRegNo, 5);
583 unsigned BaseRegNo = getX86RegNum(BaseReg);
585 if (IndexReg.getReg())
586 IndexRegNo = getX86RegNum(IndexReg.getReg());
588 IndexRegNo = 4; // For example [ESP+1*<noreg>+4]
589 emitSIBByte(SS, IndexRegNo, BaseRegNo);
592 // Do we need to output a displacement?
594 emitConstant(DispVal, 1);
595 } else if (DispVal != 0 || ForceDisp32) {
596 emitDisplacementField(DispForReloc, DispVal, PCAdj, IsPCRel);
600 template<class CodeEmitter>
601 void Emitter<CodeEmitter>::emitInstruction(const MachineInstr &MI,
602 const TargetInstrDesc *Desc) {
605 MCE.processDebugLoc(MI.getDebugLoc(), true);
607 unsigned Opcode = Desc->Opcode;
609 // Emit the lock opcode prefix as needed.
610 if (Desc->TSFlags & X86II::LOCK)
613 // Emit segment override opcode prefix as needed.
614 switch (Desc->TSFlags & X86II::SegOvrMask) {
621 default: llvm_unreachable("Invalid segment!");
622 case 0: break; // No segment override!
625 // Emit the repeat opcode prefix as needed.
626 if ((Desc->TSFlags & X86II::Op0Mask) == X86II::REP)
629 // Emit the operand size opcode prefix as needed.
630 if (Desc->TSFlags & X86II::OpSize)
633 // Emit the address size opcode prefix as needed.
634 if (Desc->TSFlags & X86II::AdSize)
637 bool Need0FPrefix = false;
638 switch (Desc->TSFlags & X86II::Op0Mask) {
639 case X86II::TB: // Two-byte opcode prefix
640 case X86II::T8: // 0F 38
641 case X86II::TA: // 0F 3A
644 case X86II::TF: // F2 0F 38
648 case X86II::REP: break; // already handled.
649 case X86II::XS: // F3 0F
653 case X86II::XD: // F2 0F
657 case X86II::D8: case X86II::D9: case X86II::DA: case X86II::DB:
658 case X86II::DC: case X86II::DD: case X86II::DE: case X86II::DF:
660 (((Desc->TSFlags & X86II::Op0Mask)-X86II::D8)
661 >> X86II::Op0Shift));
662 break; // Two-byte opcode prefix
663 default: llvm_unreachable("Invalid prefix!");
664 case 0: break; // No prefix!
667 // Handle REX prefix.
669 if (unsigned REX = determineREX(MI))
670 MCE.emitByte(0x40 | REX);
673 // 0x0F escape code must be emitted just before the opcode.
677 switch (Desc->TSFlags & X86II::Op0Mask) {
678 case X86II::TF: // F2 0F 38
679 case X86II::T8: // 0F 38
682 case X86II::TA: // 0F 3A
687 // If this is a two-address instruction, skip one of the register operands.
688 unsigned NumOps = Desc->getNumOperands();
690 if (NumOps > 1 && Desc->getOperandConstraint(1, TOI::TIED_TO) != -1)
692 else if (NumOps > 2 && Desc->getOperandConstraint(NumOps-1, TOI::TIED_TO)== 0)
693 // Skip the last source operand that is tied_to the dest reg. e.g. LXADD32
696 unsigned char BaseOpcode = X86II::getBaseOpcodeFor(Desc->TSFlags);
697 switch (Desc->TSFlags & X86II::FormMask) {
699 llvm_unreachable("Unknown FormMask value in X86 MachineCodeEmitter!");
701 // Remember the current PC offset, this is the PIC relocation
705 llvm_unreachable("psuedo instructions should be removed before code"
708 case TargetOpcode::INLINEASM:
709 // We allow inline assembler nodes with empty bodies - they can
710 // implicitly define registers, which is ok for JIT.
711 if (MI.getOperand(0).getSymbolName()[0])
712 report_fatal_error("JIT does not support inline asm!");
714 case TargetOpcode::PROLOG_LABEL:
715 case TargetOpcode::GC_LABEL:
716 case TargetOpcode::EH_LABEL:
717 MCE.emitLabel(MI.getOperand(0).getMCSymbol());
720 case TargetOpcode::IMPLICIT_DEF:
721 case TargetOpcode::KILL:
723 case X86::MOVPC32r: {
724 // This emits the "call" portion of this pseudo instruction.
725 MCE.emitByte(BaseOpcode);
726 emitConstant(0, X86II::getSizeOfImm(Desc->TSFlags));
727 // Remember PIC base.
728 PICBaseOffset = (intptr_t) MCE.getCurrentPCOffset();
729 X86JITInfo *JTI = TM.getJITInfo();
730 JTI->setPICBase(MCE.getCurrentPCValue());
736 case X86II::RawFrm: {
737 MCE.emitByte(BaseOpcode);
742 const MachineOperand &MO = MI.getOperand(CurOp++);
744 DEBUG(dbgs() << "RawFrm CurOp " << CurOp << "\n");
745 DEBUG(dbgs() << "isMBB " << MO.isMBB() << "\n");
746 DEBUG(dbgs() << "isGlobal " << MO.isGlobal() << "\n");
747 DEBUG(dbgs() << "isSymbol " << MO.isSymbol() << "\n");
748 DEBUG(dbgs() << "isImm " << MO.isImm() << "\n");
751 emitPCRelativeBlockAddress(MO.getMBB());
756 emitGlobalAddress(MO.getGlobal(), X86::reloc_pcrel_word,
762 emitExternalSymbolAddress(MO.getSymbolName(), X86::reloc_pcrel_word);
766 // FIXME: Only used by hackish MCCodeEmitter, remove when dead.
768 emitJumpTableAddress(MO.getIndex(), X86::reloc_pcrel_word);
772 assert(MO.isImm() && "Unknown RawFrm operand!");
773 if (Opcode == X86::CALLpcrel32 || Opcode == X86::CALL64pcrel32) {
774 // Fix up immediate operand for pc relative calls.
775 intptr_t Imm = (intptr_t)MO.getImm();
776 Imm = Imm - MCE.getCurrentPCValue() - 4;
777 emitConstant(Imm, X86II::getSizeOfImm(Desc->TSFlags));
779 emitConstant(MO.getImm(), X86II::getSizeOfImm(Desc->TSFlags));
783 case X86II::AddRegFrm: {
784 MCE.emitByte(BaseOpcode + getX86RegNum(MI.getOperand(CurOp++).getReg()));
789 const MachineOperand &MO1 = MI.getOperand(CurOp++);
790 unsigned Size = X86II::getSizeOfImm(Desc->TSFlags);
792 emitConstant(MO1.getImm(), Size);
796 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
797 : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
798 if (Opcode == X86::MOV64ri64i32)
799 rt = X86::reloc_absolute_word; // FIXME: add X86II flag?
800 // This should not occur on Darwin for relocatable objects.
801 if (Opcode == X86::MOV64ri)
802 rt = X86::reloc_absolute_dword; // FIXME: add X86II flag?
803 if (MO1.isGlobal()) {
804 bool Indirect = gvNeedsNonLazyPtr(MO1, TM);
805 emitGlobalAddress(MO1.getGlobal(), rt, MO1.getOffset(), 0,
807 } else if (MO1.isSymbol())
808 emitExternalSymbolAddress(MO1.getSymbolName(), rt);
809 else if (MO1.isCPI())
810 emitConstPoolAddress(MO1.getIndex(), rt);
811 else if (MO1.isJTI())
812 emitJumpTableAddress(MO1.getIndex(), rt);
816 case X86II::MRMDestReg: {
817 MCE.emitByte(BaseOpcode);
818 emitRegModRMByte(MI.getOperand(CurOp).getReg(),
819 getX86RegNum(MI.getOperand(CurOp+1).getReg()));
822 emitConstant(MI.getOperand(CurOp++).getImm(),
823 X86II::getSizeOfImm(Desc->TSFlags));
826 case X86II::MRMDestMem: {
827 MCE.emitByte(BaseOpcode);
828 emitMemModRMByte(MI, CurOp,
829 getX86RegNum(MI.getOperand(CurOp + X86::AddrNumOperands)
831 CurOp += X86::AddrNumOperands + 1;
833 emitConstant(MI.getOperand(CurOp++).getImm(),
834 X86II::getSizeOfImm(Desc->TSFlags));
838 case X86II::MRMSrcReg:
839 MCE.emitByte(BaseOpcode);
840 emitRegModRMByte(MI.getOperand(CurOp+1).getReg(),
841 getX86RegNum(MI.getOperand(CurOp).getReg()));
844 emitConstant(MI.getOperand(CurOp++).getImm(),
845 X86II::getSizeOfImm(Desc->TSFlags));
848 case X86II::MRMSrcMem: {
849 int AddrOperands = X86::AddrNumOperands;
851 intptr_t PCAdj = (CurOp + AddrOperands + 1 != NumOps) ?
852 X86II::getSizeOfImm(Desc->TSFlags) : 0;
854 MCE.emitByte(BaseOpcode);
855 emitMemModRMByte(MI, CurOp+1, getX86RegNum(MI.getOperand(CurOp).getReg()),
857 CurOp += AddrOperands + 1;
859 emitConstant(MI.getOperand(CurOp++).getImm(),
860 X86II::getSizeOfImm(Desc->TSFlags));
864 case X86II::MRM0r: case X86II::MRM1r:
865 case X86II::MRM2r: case X86II::MRM3r:
866 case X86II::MRM4r: case X86II::MRM5r:
867 case X86II::MRM6r: case X86II::MRM7r: {
868 MCE.emitByte(BaseOpcode);
869 emitRegModRMByte(MI.getOperand(CurOp++).getReg(),
870 (Desc->TSFlags & X86II::FormMask)-X86II::MRM0r);
875 const MachineOperand &MO1 = MI.getOperand(CurOp++);
876 unsigned Size = X86II::getSizeOfImm(Desc->TSFlags);
878 emitConstant(MO1.getImm(), Size);
882 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
883 : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
884 if (Opcode == X86::MOV64ri32)
885 rt = X86::reloc_absolute_word_sext; // FIXME: add X86II flag?
886 if (MO1.isGlobal()) {
887 bool Indirect = gvNeedsNonLazyPtr(MO1, TM);
888 emitGlobalAddress(MO1.getGlobal(), rt, MO1.getOffset(), 0,
890 } else if (MO1.isSymbol())
891 emitExternalSymbolAddress(MO1.getSymbolName(), rt);
892 else if (MO1.isCPI())
893 emitConstPoolAddress(MO1.getIndex(), rt);
894 else if (MO1.isJTI())
895 emitJumpTableAddress(MO1.getIndex(), rt);
899 case X86II::MRM0m: case X86II::MRM1m:
900 case X86II::MRM2m: case X86II::MRM3m:
901 case X86II::MRM4m: case X86II::MRM5m:
902 case X86II::MRM6m: case X86II::MRM7m: {
903 intptr_t PCAdj = (CurOp + X86::AddrNumOperands != NumOps) ?
904 (MI.getOperand(CurOp+X86::AddrNumOperands).isImm() ?
905 X86II::getSizeOfImm(Desc->TSFlags) : 4) : 0;
907 MCE.emitByte(BaseOpcode);
908 emitMemModRMByte(MI, CurOp, (Desc->TSFlags & X86II::FormMask)-X86II::MRM0m,
910 CurOp += X86::AddrNumOperands;
915 const MachineOperand &MO = MI.getOperand(CurOp++);
916 unsigned Size = X86II::getSizeOfImm(Desc->TSFlags);
918 emitConstant(MO.getImm(), Size);
922 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
923 : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
924 if (Opcode == X86::MOV64mi32)
925 rt = X86::reloc_absolute_word_sext; // FIXME: add X86II flag?
927 bool Indirect = gvNeedsNonLazyPtr(MO, TM);
928 emitGlobalAddress(MO.getGlobal(), rt, MO.getOffset(), 0,
930 } else if (MO.isSymbol())
931 emitExternalSymbolAddress(MO.getSymbolName(), rt);
933 emitConstPoolAddress(MO.getIndex(), rt);
935 emitJumpTableAddress(MO.getIndex(), rt);
939 case X86II::MRMInitReg:
940 MCE.emitByte(BaseOpcode);
941 // Duplicate register, used by things like MOV8r0 (aka xor reg,reg).
942 emitRegModRMByte(MI.getOperand(CurOp).getReg(),
943 getX86RegNum(MI.getOperand(CurOp).getReg()));
948 MCE.emitByte(BaseOpcode);
952 MCE.emitByte(BaseOpcode);
956 MCE.emitByte(BaseOpcode);
960 MCE.emitByte(BaseOpcode);
964 MCE.emitByte(BaseOpcode);
969 if (!Desc->isVariadic() && CurOp != NumOps) {
971 dbgs() << "Cannot encode all operands of: " << MI << "\n";
976 MCE.processDebugLoc(MI.getDebugLoc(), false);