1 //===-- X86CallingConv.td - Calling Conventions X86 32/64 --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This describes the calling conventions for the X86-32 and X86-64
13 //===----------------------------------------------------------------------===//
15 /// CCIfSubtarget - Match if the current subtarget has a feature F.
16 class CCIfSubtarget<string F, CCAction A>
17 : CCIf<!strconcat("static_cast<const X86Subtarget&>"
18 "(State.getMachineFunction().getSubtarget()).", F),
21 //===----------------------------------------------------------------------===//
22 // Return Value Calling Conventions
23 //===----------------------------------------------------------------------===//
25 // Return-value conventions common to all X86 CC's.
26 def RetCC_X86Common : CallingConv<[
27 // Scalar values are returned in AX first, then DX. For i8, the ABI
28 // requires the values to be in AL and AH, however this code uses AL and DL
29 // instead. This is because using AH for the second register conflicts with
30 // the way LLVM does multiple return values -- a return of {i16,i8} would end
31 // up in AX and AH, which overlap. Front-ends wishing to conform to the ABI
32 // for functions that return two i8 values are currently expected to pack the
33 // values into an i16 (which uses AX, and thus AL:AH).
35 // For code that doesn't care about the ABI, we allow returning more than two
36 // integer values in registers.
37 CCIfType<[i8] , CCAssignToReg<[AL, DL, CL]>>,
38 CCIfType<[i16], CCAssignToReg<[AX, DX, CX]>>,
39 CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>,
40 CCIfType<[i64], CCAssignToReg<[RAX, RDX, RCX]>>,
42 // Vector types are returned in XMM0 and XMM1, when they fit. XMM2 and XMM3
43 // can only be used by ABI non-compliant code. If the target doesn't have XMM
44 // registers, it won't have vector types.
45 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
46 CCAssignToReg<[XMM0,XMM1,XMM2,XMM3]>>,
48 // 256-bit vectors are returned in YMM0 and XMM1, when they fit. YMM2 and YMM3
49 // can only be used by ABI non-compliant code. This vector type is only
50 // supported while using the AVX target feature.
51 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
52 CCAssignToReg<[YMM0,YMM1,YMM2,YMM3]>>,
54 // 512-bit vectors are returned in ZMM0 and ZMM1, when they fit. ZMM2 and ZMM3
55 // can only be used by ABI non-compliant code. This vector type is only
56 // supported while using the AVX-512 target feature.
57 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
58 CCAssignToReg<[ZMM0,ZMM1,ZMM2,ZMM3]>>,
60 // MMX vector types are always returned in MM0. If the target doesn't have
61 // MM0, it doesn't support these vector types.
62 CCIfType<[x86mmx], CCAssignToReg<[MM0]>>,
64 // Long double types are always returned in FP0 (even with SSE).
65 CCIfType<[f80], CCAssignToReg<[FP0, FP1]>>
68 // X86-32 C return-value convention.
69 def RetCC_X86_32_C : CallingConv<[
70 // The X86-32 calling convention returns FP values in FP0, unless marked
71 // with "inreg" (used here to distinguish one kind of reg from another,
72 // weirdly; this is really the sse-regparm calling convention) in which
73 // case they use XMM0, otherwise it is the same as the common X86 calling
75 CCIfInReg<CCIfSubtarget<"hasSSE2()",
76 CCIfType<[f32, f64], CCAssignToReg<[XMM0,XMM1,XMM2]>>>>,
77 CCIfType<[f32,f64], CCAssignToReg<[FP0, FP1]>>,
78 CCDelegateTo<RetCC_X86Common>
81 // X86-32 FastCC return-value convention.
82 def RetCC_X86_32_Fast : CallingConv<[
83 // The X86-32 fastcc returns 1, 2, or 3 FP values in XMM0-2 if the target has
85 // This can happen when a float, 2 x float, or 3 x float vector is split by
86 // target lowering, and is returned in 1-3 sse regs.
87 CCIfType<[f32], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>,
88 CCIfType<[f64], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>,
90 // For integers, ECX can be used as an extra return register
91 CCIfType<[i8], CCAssignToReg<[AL, DL, CL]>>,
92 CCIfType<[i16], CCAssignToReg<[AX, DX, CX]>>,
93 CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>,
95 // Otherwise, it is the same as the common X86 calling convention.
96 CCDelegateTo<RetCC_X86Common>
99 // Intel_OCL_BI return-value convention.
100 def RetCC_Intel_OCL_BI : CallingConv<[
101 // Vector types are returned in XMM0,XMM1,XMMM2 and XMM3.
102 CCIfType<[f32, f64, v4i32, v2i64, v4f32, v2f64],
103 CCAssignToReg<[XMM0,XMM1,XMM2,XMM3]>>,
105 // 256-bit FP vectors
106 // No more than 4 registers
107 CCIfType<[v8f32, v4f64, v8i32, v4i64],
108 CCAssignToReg<[YMM0,YMM1,YMM2,YMM3]>>,
110 // 512-bit FP vectors
111 CCIfType<[v16f32, v8f64, v16i32, v8i64],
112 CCAssignToReg<[ZMM0,ZMM1,ZMM2,ZMM3]>>,
114 // i32, i64 in the standard way
115 CCDelegateTo<RetCC_X86Common>
118 // X86-32 HiPE return-value convention.
119 def RetCC_X86_32_HiPE : CallingConv<[
120 // Promote all types to i32
121 CCIfType<[i8, i16], CCPromoteToType<i32>>,
123 // Return: HP, P, VAL1, VAL2
124 CCIfType<[i32], CCAssignToReg<[ESI, EBP, EAX, EDX]>>
127 // X86-64 C return-value convention.
128 def RetCC_X86_64_C : CallingConv<[
129 // The X86-64 calling convention always returns FP values in XMM0.
130 CCIfType<[f32], CCAssignToReg<[XMM0, XMM1]>>,
131 CCIfType<[f64], CCAssignToReg<[XMM0, XMM1]>>,
133 // MMX vector types are always returned in XMM0.
134 CCIfType<[x86mmx], CCAssignToReg<[XMM0, XMM1]>>,
135 CCDelegateTo<RetCC_X86Common>
138 // X86-Win64 C return-value convention.
139 def RetCC_X86_Win64_C : CallingConv<[
140 // The X86-Win64 calling convention always returns __m64 values in RAX.
141 CCIfType<[x86mmx], CCBitConvertToType<i64>>,
143 // Otherwise, everything is the same as 'normal' X86-64 C CC.
144 CCDelegateTo<RetCC_X86_64_C>
147 // X86-64 HiPE return-value convention.
148 def RetCC_X86_64_HiPE : CallingConv<[
149 // Promote all types to i64
150 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
152 // Return: HP, P, VAL1, VAL2
153 CCIfType<[i64], CCAssignToReg<[R15, RBP, RAX, RDX]>>
156 // X86-64 WebKit_JS return-value convention.
157 def RetCC_X86_64_WebKit_JS : CallingConv<[
158 // Promote all types to i64
159 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
162 CCIfType<[i64], CCAssignToReg<[RAX]>>
165 // X86-64 AnyReg return-value convention. No explicit register is specified for
166 // the return-value. The register allocator is allowed and expected to choose
167 // any free register.
169 // This calling convention is currently only supported by the stackmap and
170 // patchpoint intrinsics. All other uses will result in an assert on Debug
171 // builds. On Release builds we fallback to the X86 C calling convention.
172 def RetCC_X86_64_AnyReg : CallingConv<[
173 CCCustom<"CC_X86_AnyReg_Error">
176 // This is the root return-value convention for the X86-32 backend.
177 def RetCC_X86_32 : CallingConv<[
178 // If FastCC, use RetCC_X86_32_Fast.
179 CCIfCC<"CallingConv::Fast", CCDelegateTo<RetCC_X86_32_Fast>>,
180 // If HiPE, use RetCC_X86_32_HiPE.
181 CCIfCC<"CallingConv::HiPE", CCDelegateTo<RetCC_X86_32_HiPE>>,
183 // Otherwise, use RetCC_X86_32_C.
184 CCDelegateTo<RetCC_X86_32_C>
187 // This is the root return-value convention for the X86-64 backend.
188 def RetCC_X86_64 : CallingConv<[
189 // HiPE uses RetCC_X86_64_HiPE
190 CCIfCC<"CallingConv::HiPE", CCDelegateTo<RetCC_X86_64_HiPE>>,
192 // Handle JavaScript calls.
193 CCIfCC<"CallingConv::WebKit_JS", CCDelegateTo<RetCC_X86_64_WebKit_JS>>,
194 CCIfCC<"CallingConv::AnyReg", CCDelegateTo<RetCC_X86_64_AnyReg>>,
196 // Handle explicit CC selection
197 CCIfCC<"CallingConv::X86_64_Win64", CCDelegateTo<RetCC_X86_Win64_C>>,
198 CCIfCC<"CallingConv::X86_64_SysV", CCDelegateTo<RetCC_X86_64_C>>,
200 // Mingw64 and native Win64 use Win64 CC
201 CCIfSubtarget<"isTargetWin64()", CCDelegateTo<RetCC_X86_Win64_C>>,
203 // Otherwise, drop to normal X86-64 CC
204 CCDelegateTo<RetCC_X86_64_C>
207 // This is the return-value convention used for the entire X86 backend.
208 def RetCC_X86 : CallingConv<[
210 // Check if this is the Intel OpenCL built-ins calling convention
211 CCIfCC<"CallingConv::Intel_OCL_BI", CCDelegateTo<RetCC_Intel_OCL_BI>>,
213 CCIfSubtarget<"is64Bit()", CCDelegateTo<RetCC_X86_64>>,
214 CCDelegateTo<RetCC_X86_32>
217 //===----------------------------------------------------------------------===//
218 // X86-64 Argument Calling Conventions
219 //===----------------------------------------------------------------------===//
221 def CC_X86_64_C : CallingConv<[
222 // Handles byval parameters.
223 CCIfByVal<CCPassByVal<8, 8>>,
225 // Promote i8/i16 arguments to i32.
226 CCIfType<[i8, i16], CCPromoteToType<i32>>,
228 // The 'nest' parameter, if any, is passed in R10.
229 CCIfNest<CCIfSubtarget<"isTarget64BitILP32()", CCAssignToReg<[R10D]>>>,
230 CCIfNest<CCAssignToReg<[R10]>>,
232 // The first 6 integer arguments are passed in integer registers.
233 CCIfType<[i32], CCAssignToReg<[EDI, ESI, EDX, ECX, R8D, R9D]>>,
234 CCIfType<[i64], CCAssignToReg<[RDI, RSI, RDX, RCX, R8 , R9 ]>>,
236 // The first 8 MMX vector arguments are passed in XMM registers on Darwin.
238 CCIfSubtarget<"isTargetDarwin()",
239 CCIfSubtarget<"hasSSE2()",
240 CCPromoteToType<v2i64>>>>,
242 // The first 8 FP/Vector arguments are passed in XMM registers.
243 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
244 CCIfSubtarget<"hasSSE1()",
245 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>>>,
247 // The first 8 256-bit vector arguments are passed in YMM registers, unless
248 // this is a vararg function.
249 // FIXME: This isn't precisely correct; the x86-64 ABI document says that
250 // fixed arguments to vararg functions are supposed to be passed in
251 // registers. Actually modeling that would be a lot of work, though.
252 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
253 CCIfSubtarget<"hasFp256()",
254 CCAssignToReg<[YMM0, YMM1, YMM2, YMM3,
255 YMM4, YMM5, YMM6, YMM7]>>>>,
257 // The first 8 512-bit vector arguments are passed in ZMM registers.
258 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
259 CCIfSubtarget<"hasAVX512()",
260 CCAssignToReg<[ZMM0, ZMM1, ZMM2, ZMM3, ZMM4, ZMM5, ZMM6, ZMM7]>>>>,
262 // Integer/FP values get stored in stack slots that are 8 bytes in size and
263 // 8-byte aligned if there are no more registers to hold them.
264 CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>,
266 // Long doubles get stack slots whose size and alignment depends on the
268 CCIfType<[f80], CCAssignToStack<0, 0>>,
270 // Vectors get 16-byte stack slots that are 16-byte aligned.
271 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>,
273 // 256-bit vectors get 32-byte stack slots that are 32-byte aligned.
274 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
275 CCAssignToStack<32, 32>>,
277 // 512-bit vectors get 64-byte stack slots that are 64-byte aligned.
278 CCIfType<[v16i32, v8i64, v16f32, v8f64],
279 CCAssignToStack<64, 64>>
282 // Calling convention used on Win64
283 def CC_X86_Win64_C : CallingConv<[
284 // FIXME: Handle byval stuff.
285 // FIXME: Handle varargs.
287 // Promote i8/i16 arguments to i32.
288 CCIfType<[i8, i16], CCPromoteToType<i32>>,
290 // The 'nest' parameter, if any, is passed in R10.
291 CCIfNest<CCAssignToReg<[R10]>>,
293 // 128 bit vectors are passed by pointer
294 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCPassIndirect<i64>>,
297 // 256 bit vectors are passed by pointer
298 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], CCPassIndirect<i64>>,
300 // 512 bit vectors are passed by pointer
301 CCIfType<[v16i32, v16f32, v8f64, v8i64], CCPassIndirect<i64>>,
303 // The first 4 MMX vector arguments are passed in GPRs.
304 CCIfType<[x86mmx], CCBitConvertToType<i64>>,
306 // The first 4 integer arguments are passed in integer registers.
307 CCIfType<[i32], CCAssignToRegWithShadow<[ECX , EDX , R8D , R9D ],
308 [XMM0, XMM1, XMM2, XMM3]>>,
310 // Do not pass the sret argument in RCX, the Win64 thiscall calling
311 // convention requires "this" to be passed in RCX.
312 CCIfCC<"CallingConv::X86_ThisCall",
313 CCIfSRet<CCIfType<[i64], CCAssignToRegWithShadow<[RDX , R8 , R9 ],
314 [XMM1, XMM2, XMM3]>>>>,
316 CCIfType<[i64], CCAssignToRegWithShadow<[RCX , RDX , R8 , R9 ],
317 [XMM0, XMM1, XMM2, XMM3]>>,
319 // The first 4 FP/Vector arguments are passed in XMM registers.
320 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
321 CCAssignToRegWithShadow<[XMM0, XMM1, XMM2, XMM3],
322 [RCX , RDX , R8 , R9 ]>>,
324 // Integer/FP values get stored in stack slots that are 8 bytes in size and
325 // 8-byte aligned if there are no more registers to hold them.
326 CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>,
328 // Long doubles get stack slots whose size and alignment depends on the
330 CCIfType<[f80], CCAssignToStack<0, 0>>
333 def CC_X86_64_GHC : CallingConv<[
334 // Promote i8/i16/i32 arguments to i64.
335 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
337 // Pass in STG registers: Base, Sp, Hp, R1, R2, R3, R4, R5, R6, SpLim
339 CCAssignToReg<[R13, RBP, R12, RBX, R14, RSI, RDI, R8, R9, R15]>>,
341 // Pass in STG registers: F1, F2, F3, F4, D1, D2
342 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
343 CCIfSubtarget<"hasSSE1()",
344 CCAssignToReg<[XMM1, XMM2, XMM3, XMM4, XMM5, XMM6]>>>
347 def CC_X86_64_HiPE : CallingConv<[
348 // Promote i8/i16/i32 arguments to i64.
349 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
351 // Pass in VM's registers: HP, P, ARG0, ARG1, ARG2, ARG3
352 CCIfType<[i64], CCAssignToReg<[R15, RBP, RSI, RDX, RCX, R8]>>,
354 // Integer/FP values get stored in stack slots that are 8 bytes in size and
355 // 8-byte aligned if there are no more registers to hold them.
356 CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>
359 def CC_X86_64_WebKit_JS : CallingConv<[
360 // Promote i8/i16 arguments to i32.
361 CCIfType<[i8, i16], CCPromoteToType<i32>>,
363 // Only the first integer argument is passed in register.
364 CCIfType<[i32], CCAssignToReg<[EAX]>>,
365 CCIfType<[i64], CCAssignToReg<[RAX]>>,
367 // The remaining integer arguments are passed on the stack. 32bit integer and
368 // floating-point arguments are aligned to 4 byte and stored in 4 byte slots.
369 // 64bit integer and floating-point arguments are aligned to 8 byte and stored
370 // in 8 byte stack slots.
371 CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
372 CCIfType<[i64, f64], CCAssignToStack<8, 8>>
375 // No explicit register is specified for the AnyReg calling convention. The
376 // register allocator may assign the arguments to any free register.
378 // This calling convention is currently only supported by the stackmap and
379 // patchpoint intrinsics. All other uses will result in an assert on Debug
380 // builds. On Release builds we fallback to the X86 C calling convention.
381 def CC_X86_64_AnyReg : CallingConv<[
382 CCCustom<"CC_X86_AnyReg_Error">
385 //===----------------------------------------------------------------------===//
386 // X86 C Calling Convention
387 //===----------------------------------------------------------------------===//
389 /// CC_X86_32_Common - In all X86-32 calling conventions, extra integers and FP
390 /// values are spilled on the stack, and the first 4 vector values go in XMM
392 def CC_X86_32_Common : CallingConv<[
393 // Handles byval parameters.
394 CCIfByVal<CCPassByVal<4, 4>>,
396 // The first 3 float or double arguments, if marked 'inreg' and if the call
397 // is not a vararg call and if SSE2 is available, are passed in SSE registers.
398 CCIfNotVarArg<CCIfInReg<CCIfType<[f32,f64],
399 CCIfSubtarget<"hasSSE2()",
400 CCAssignToReg<[XMM0,XMM1,XMM2]>>>>>,
402 // The first 3 __m64 vector arguments are passed in mmx registers if the
403 // call is not a vararg call.
404 CCIfNotVarArg<CCIfType<[x86mmx],
405 CCAssignToReg<[MM0, MM1, MM2]>>>,
407 // Integer/Float values get stored in stack slots that are 4 bytes in
408 // size and 4-byte aligned.
409 CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
411 // Doubles get 8-byte slots that are 4-byte aligned.
412 CCIfType<[f64], CCAssignToStack<8, 4>>,
414 // Long doubles get slots whose size depends on the subtarget.
415 CCIfType<[f80], CCAssignToStack<0, 4>>,
417 // The first 4 SSE vector arguments are passed in XMM registers.
418 CCIfNotVarArg<CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
419 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>>,
421 // The first 4 AVX 256-bit vector arguments are passed in YMM registers.
422 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
423 CCIfSubtarget<"hasFp256()",
424 CCAssignToReg<[YMM0, YMM1, YMM2, YMM3]>>>>,
426 // Other SSE vectors get 16-byte stack slots that are 16-byte aligned.
427 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>,
429 // 256-bit AVX vectors get 32-byte stack slots that are 32-byte aligned.
430 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
431 CCAssignToStack<32, 32>>,
433 // __m64 vectors get 8-byte stack slots that are 4-byte aligned. They are
434 // passed in the parameter area.
435 CCIfType<[x86mmx], CCAssignToStack<8, 4>>]>;
437 def CC_X86_32_C : CallingConv<[
438 // Promote i8/i16 arguments to i32.
439 CCIfType<[i8, i16], CCPromoteToType<i32>>,
441 // The 'nest' parameter, if any, is passed in ECX.
442 CCIfNest<CCAssignToReg<[ECX]>>,
444 // The first 3 integer arguments, if marked 'inreg' and if the call is not
445 // a vararg call, are passed in integer registers.
446 CCIfNotVarArg<CCIfInReg<CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>>>,
448 // Otherwise, same as everything else.
449 CCDelegateTo<CC_X86_32_Common>
452 def CC_X86_32_FastCall : CallingConv<[
453 // Promote i8/i16 arguments to i32.
454 CCIfType<[i8, i16], CCPromoteToType<i32>>,
456 // The 'nest' parameter, if any, is passed in EAX.
457 CCIfNest<CCAssignToReg<[EAX]>>,
459 // The first 2 integer arguments are passed in ECX/EDX
460 CCIfInReg<CCIfType<[i32], CCAssignToReg<[ECX, EDX]>>>,
462 // Otherwise, same as everything else.
463 CCDelegateTo<CC_X86_32_Common>
466 def CC_X86_32_ThisCall_Common : CallingConv<[
467 // The first integer argument is passed in ECX
468 CCIfType<[i32], CCAssignToReg<[ECX]>>,
470 // Otherwise, same as everything else.
471 CCDelegateTo<CC_X86_32_Common>
474 def CC_X86_32_ThisCall_Mingw : CallingConv<[
475 // Promote i8/i16 arguments to i32.
476 CCIfType<[i8, i16], CCPromoteToType<i32>>,
478 CCDelegateTo<CC_X86_32_ThisCall_Common>
481 def CC_X86_32_ThisCall_Win : CallingConv<[
482 // Promote i8/i16 arguments to i32.
483 CCIfType<[i8, i16], CCPromoteToType<i32>>,
485 // Pass sret arguments indirectly through stack.
486 CCIfSRet<CCAssignToStack<4, 4>>,
488 CCDelegateTo<CC_X86_32_ThisCall_Common>
491 def CC_X86_32_ThisCall : CallingConv<[
492 CCIfSubtarget<"isTargetCygMing()", CCDelegateTo<CC_X86_32_ThisCall_Mingw>>,
493 CCDelegateTo<CC_X86_32_ThisCall_Win>
496 def CC_X86_32_FastCC : CallingConv<[
497 // Handles byval parameters. Note that we can't rely on the delegation
498 // to CC_X86_32_Common for this because that happens after code that
499 // puts arguments in registers.
500 CCIfByVal<CCPassByVal<4, 4>>,
502 // Promote i8/i16 arguments to i32.
503 CCIfType<[i8, i16], CCPromoteToType<i32>>,
505 // The 'nest' parameter, if any, is passed in EAX.
506 CCIfNest<CCAssignToReg<[EAX]>>,
508 // The first 2 integer arguments are passed in ECX/EDX
509 CCIfType<[i32], CCAssignToReg<[ECX, EDX]>>,
511 // The first 3 float or double arguments, if the call is not a vararg
512 // call and if SSE2 is available, are passed in SSE registers.
513 CCIfNotVarArg<CCIfType<[f32,f64],
514 CCIfSubtarget<"hasSSE2()",
515 CCAssignToReg<[XMM0,XMM1,XMM2]>>>>,
517 // Doubles get 8-byte slots that are 8-byte aligned.
518 CCIfType<[f64], CCAssignToStack<8, 8>>,
520 // Otherwise, same as everything else.
521 CCDelegateTo<CC_X86_32_Common>
524 def CC_X86_32_GHC : CallingConv<[
525 // Promote i8/i16 arguments to i32.
526 CCIfType<[i8, i16], CCPromoteToType<i32>>,
528 // Pass in STG registers: Base, Sp, Hp, R1
529 CCIfType<[i32], CCAssignToReg<[EBX, EBP, EDI, ESI]>>
532 def CC_X86_32_HiPE : CallingConv<[
533 // Promote i8/i16 arguments to i32.
534 CCIfType<[i8, i16], CCPromoteToType<i32>>,
536 // Pass in VM's registers: HP, P, ARG0, ARG1, ARG2
537 CCIfType<[i32], CCAssignToReg<[ESI, EBP, EAX, EDX, ECX]>>,
539 // Integer/Float values get stored in stack slots that are 4 bytes in
540 // size and 4-byte aligned.
541 CCIfType<[i32, f32], CCAssignToStack<4, 4>>
544 // X86-64 Intel OpenCL built-ins calling convention.
545 def CC_Intel_OCL_BI : CallingConv<[
547 CCIfType<[i32], CCIfSubtarget<"isTargetWin64()", CCAssignToReg<[ECX, EDX, R8D, R9D]>>>,
548 CCIfType<[i64], CCIfSubtarget<"isTargetWin64()", CCAssignToReg<[RCX, RDX, R8, R9 ]>>>,
550 CCIfType<[i32], CCIfSubtarget<"is64Bit()", CCAssignToReg<[EDI, ESI, EDX, ECX]>>>,
551 CCIfType<[i64], CCIfSubtarget<"is64Bit()", CCAssignToReg<[RDI, RSI, RDX, RCX]>>>,
553 CCIfType<[i32], CCAssignToStack<4, 4>>,
555 // The SSE vector arguments are passed in XMM registers.
556 CCIfType<[f32, f64, v4i32, v2i64, v4f32, v2f64],
557 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>,
559 // The 256-bit vector arguments are passed in YMM registers.
560 CCIfType<[v8f32, v4f64, v8i32, v4i64],
561 CCAssignToReg<[YMM0, YMM1, YMM2, YMM3]>>,
563 // The 512-bit vector arguments are passed in ZMM registers.
564 CCIfType<[v16f32, v8f64, v16i32, v8i64],
565 CCAssignToReg<[ZMM0, ZMM1, ZMM2, ZMM3]>>,
567 CCIfSubtarget<"isTargetWin64()", CCDelegateTo<CC_X86_Win64_C>>,
568 CCIfSubtarget<"is64Bit()", CCDelegateTo<CC_X86_64_C>>,
569 CCDelegateTo<CC_X86_32_C>
572 //===----------------------------------------------------------------------===//
573 // X86 Root Argument Calling Conventions
574 //===----------------------------------------------------------------------===//
576 // This is the root argument convention for the X86-32 backend.
577 def CC_X86_32 : CallingConv<[
578 CCIfCC<"CallingConv::X86_FastCall", CCDelegateTo<CC_X86_32_FastCall>>,
579 CCIfCC<"CallingConv::X86_ThisCall", CCDelegateTo<CC_X86_32_ThisCall>>,
580 CCIfCC<"CallingConv::Fast", CCDelegateTo<CC_X86_32_FastCC>>,
581 CCIfCC<"CallingConv::GHC", CCDelegateTo<CC_X86_32_GHC>>,
582 CCIfCC<"CallingConv::HiPE", CCDelegateTo<CC_X86_32_HiPE>>,
584 // Otherwise, drop to normal X86-32 CC
585 CCDelegateTo<CC_X86_32_C>
588 // This is the root argument convention for the X86-64 backend.
589 def CC_X86_64 : CallingConv<[
590 CCIfCC<"CallingConv::GHC", CCDelegateTo<CC_X86_64_GHC>>,
591 CCIfCC<"CallingConv::HiPE", CCDelegateTo<CC_X86_64_HiPE>>,
592 CCIfCC<"CallingConv::WebKit_JS", CCDelegateTo<CC_X86_64_WebKit_JS>>,
593 CCIfCC<"CallingConv::AnyReg", CCDelegateTo<CC_X86_64_AnyReg>>,
594 CCIfCC<"CallingConv::X86_64_Win64", CCDelegateTo<CC_X86_Win64_C>>,
595 CCIfCC<"CallingConv::X86_64_SysV", CCDelegateTo<CC_X86_64_C>>,
597 // Mingw64 and native Win64 use Win64 CC
598 CCIfSubtarget<"isTargetWin64()", CCDelegateTo<CC_X86_Win64_C>>,
600 // Otherwise, drop to normal X86-64 CC
601 CCDelegateTo<CC_X86_64_C>
604 // This is the argument convention used for the entire X86 backend.
605 def CC_X86 : CallingConv<[
606 CCIfCC<"CallingConv::Intel_OCL_BI", CCDelegateTo<CC_Intel_OCL_BI>>,
607 CCIfSubtarget<"is64Bit()", CCDelegateTo<CC_X86_64>>,
608 CCDelegateTo<CC_X86_32>
611 //===----------------------------------------------------------------------===//
612 // Callee-saved Registers.
613 //===----------------------------------------------------------------------===//
615 def CSR_NoRegs : CalleeSavedRegs<(add)>;
617 def CSR_32 : CalleeSavedRegs<(add ESI, EDI, EBX, EBP)>;
618 def CSR_64 : CalleeSavedRegs<(add RBX, R12, R13, R14, R15, RBP)>;
620 def CSR_32EHRet : CalleeSavedRegs<(add EAX, EDX, CSR_32)>;
621 def CSR_64EHRet : CalleeSavedRegs<(add RAX, RDX, CSR_64)>;
623 def CSR_Win64 : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, R12, R13, R14, R15,
624 (sequence "XMM%u", 6, 15))>;
626 // All GPRs - except r11
627 def CSR_64_RT_MostRegs : CalleeSavedRegs<(add CSR_64, RAX, RCX, RDX, RSI, RDI,
630 // All registers - except r11
631 def CSR_64_RT_AllRegs : CalleeSavedRegs<(add CSR_64_RT_MostRegs,
632 (sequence "XMM%u", 0, 15))>;
633 def CSR_64_RT_AllRegs_AVX : CalleeSavedRegs<(add CSR_64_RT_MostRegs,
634 (sequence "YMM%u", 0, 15))>;
636 def CSR_64_MostRegs : CalleeSavedRegs<(add RBX, RCX, RDX, RSI, RDI, R8, R9, R10,
637 R11, R12, R13, R14, R15, RBP,
638 (sequence "XMM%u", 0, 15))>;
640 def CSR_64_AllRegs : CalleeSavedRegs<(add CSR_64_MostRegs, RAX, RSP,
641 (sequence "XMM%u", 16, 31))>;
642 def CSR_64_AllRegs_AVX : CalleeSavedRegs<(sub (add CSR_64_MostRegs, RAX, RSP,
643 (sequence "YMM%u", 0, 31)),
644 (sequence "XMM%u", 0, 15))>;
646 // Standard C + YMM6-15
647 def CSR_Win64_Intel_OCL_BI_AVX : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, R12,
649 (sequence "YMM%u", 6, 15))>;
651 def CSR_Win64_Intel_OCL_BI_AVX512 : CalleeSavedRegs<(add RBX, RBP, RDI, RSI,
653 (sequence "ZMM%u", 6, 21),
655 //Standard C + XMM 8-15
656 def CSR_64_Intel_OCL_BI : CalleeSavedRegs<(add CSR_64,
657 (sequence "XMM%u", 8, 15))>;
659 //Standard C + YMM 8-15
660 def CSR_64_Intel_OCL_BI_AVX : CalleeSavedRegs<(add CSR_64,
661 (sequence "YMM%u", 8, 15))>;
663 def CSR_64_Intel_OCL_BI_AVX512 : CalleeSavedRegs<(add RBX, RDI, RSI, R14, R15,
664 (sequence "ZMM%u", 16, 31),