1 //===-- X86/Printer.cpp - Convert X86 code to human readable rep. ---------===//
3 // This file contains a printer that converts from our internal representation
4 // of LLVM code to a nice human readable form that is suitable for debuggging.
6 //===----------------------------------------------------------------------===//
9 #include "X86InstrInfo.h"
10 #include "llvm/Pass.h"
11 #include "llvm/Function.h"
12 #include "llvm/Target/TargetMachine.h"
13 #include "llvm/CodeGen/MachineFunction.h"
14 #include "llvm/CodeGen/MachineInstr.h"
15 #include "Support/Statistic.h"
18 struct Printer : public FunctionPass {
22 Printer(TargetMachine &tm, std::ostream &o) : TM(tm), O(o) {}
24 bool runOnFunction(Function &F);
28 /// createX86CodePrinterPass - Print out the specified machine code function to
29 /// the specified stream. This function should work regardless of whether or
30 /// not the function is in SSA form or not.
32 Pass *createX86CodePrinterPass(TargetMachine &TM, std::ostream &O) {
33 return new Printer(TM, O);
37 /// runOnFunction - This uses the X86InstructionInfo::print method
38 /// to print assembly for each instruction.
39 bool Printer::runOnFunction (Function & F)
41 static unsigned bbnumber = 0;
42 MachineFunction & MF = MachineFunction::get (&F);
43 const MachineInstrInfo & MII = TM.getInstrInfo ();
45 O << "; x86 printing only sorta implemented so far!\n";
47 // Print out labels for the function.
48 O << "\t.globl\t" << F.getName () << "\n";
49 O << "\t.type\t" << F.getName () << ", @function\n";
50 O << F.getName () << ":\n";
52 // Print out code for the function.
53 for (MachineFunction::const_iterator bb_i = MF.begin (), bb_e = MF.end ();
56 // Print a label for the basic block.
57 O << ".BB" << bbnumber++ << ":\n";
58 for (MachineBasicBlock::const_iterator i_i = bb_i->begin (), i_e =
59 bb_i->end (); i_i != i_e; ++i_i)
61 // Print the assembly for the instruction.
63 MII.print(*i_i, O, TM);
67 // We didn't modify anything.
71 static void printOp(std::ostream &O, const MachineOperand &MO,
72 const MRegisterInfo &RI) {
73 switch (MO.getType()) {
74 case MachineOperand::MO_VirtualRegister:
75 case MachineOperand::MO_MachineRegister:
76 if (MO.getReg() < MRegisterInfo::FirstVirtualRegister)
77 O << RI.get(MO.getReg()).Name;
79 O << "%reg" << MO.getReg();
83 O << "<unknown op ty>"; return;
87 static inline void toHexDigit(std::ostream &O, unsigned char V) {
89 O << (char)('A'+V-10);
94 static std::ostream &toHex(std::ostream &O, unsigned char V) {
95 toHexDigit(O, V >> 4);
96 toHexDigit(O, V & 0xF);
101 static bool isReg(const MachineOperand &MO) {
102 return MO.getType()==MachineOperand::MO_VirtualRegister ||
103 MO.getType()==MachineOperand::MO_MachineRegister;
107 // getX86RegNum - This function maps LLVM register identifiers to their X86
108 // specific numbering, which is used in various places encoding instructions.
110 static unsigned getX86RegNum(unsigned RegNo) {
112 case X86::EAX: case X86::AX: case X86::AL: return 0;
113 case X86::ECX: case X86::CX: case X86::CL: return 1;
114 case X86::EDX: case X86::DX: case X86::DL: return 2;
115 case X86::EBX: case X86::BX: case X86::BL: return 3;
116 case X86::ESP: case X86::SP: case X86::AH: return 4;
117 case X86::EBP: case X86::BP: case X86::CH: return 5;
118 case X86::ESI: case X86::SI: case X86::DH: return 6;
119 case X86::EDI: case X86::DI: case X86::BH: return 7;
121 assert(RegNo >= MRegisterInfo::FirstVirtualRegister &&
122 "Unknown physical register!");
123 DEBUG(std::cerr << "Register allocator hasn't allocated " << RegNo
124 << " correctly yet!\n");
129 inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
131 assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
132 return RM | (RegOpcode << 3) | (Mod << 6);
135 static unsigned char regModRMByte(unsigned ModRMReg, unsigned RegOpcodeField) {
136 return ModRMByte(3, RegOpcodeField, getX86RegNum(ModRMReg));
140 // print - Print out an x86 instruction in intel syntax
141 void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
142 const TargetMachine &TM) const {
143 unsigned Opcode = MI->getOpcode();
144 const MachineInstrDescriptor &Desc = get(Opcode);
146 // Print instruction prefixes if neccesary
148 if (Desc.TSFlags & X86II::OpSize) O << "66 "; // Operand size...
149 if (Desc.TSFlags & X86II::TB) O << "0F "; // Two-byte opcode prefix
151 switch (Desc.TSFlags & X86II::FormMask) {
152 case X86II::OtherFrm:
154 O << "-"; MI->print(O, TM);
157 toHex(O, getBaseOpcodeFor(Opcode)) << "\t\t";
158 O << getName(MI->getOpCode()) << " ";
160 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
162 printOp(O, MI->getOperand(i), RI);
168 case X86II::AddRegFrm:
169 O << "\t\t-"; MI->print(O, TM); break;
171 case X86II::MRMDestReg: {
172 // There are two acceptable forms of MRMDestReg instructions, those with 3
175 // 3 Operands: in this form, the first two registers (the destination, and
176 // the first operand) should be the same, post register allocation. The 3rd
177 // operand is an additional input. This should be for things like add
180 // 2 Operands: this is for things like mov that do not read a second input
182 assert(isReg(MI->getOperand(0)) &&
183 (MI->getNumOperands() == 2 ||
184 (MI->getNumOperands() == 3 && isReg(MI->getOperand(1)))) &&
185 isReg(MI->getOperand(MI->getNumOperands()-1))
186 && "Bad format for MRMDestReg!");
187 if (MI->getNumOperands() == 3 &&
188 MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
191 toHex(O, getBaseOpcodeFor(Opcode)) << " ";
192 unsigned ModRMReg = MI->getOperand(0).getReg();
193 unsigned ExtraReg = MI->getOperand(MI->getNumOperands()-1).getReg();
194 toHex(O, regModRMByte(ModRMReg, getX86RegNum(ExtraReg)));
197 O << getName(MI->getOpCode()) << " ";
198 printOp(O, MI->getOperand(0), RI);
200 printOp(O, MI->getOperand(MI->getNumOperands()-1), RI);
204 case X86II::MRMSrcReg: {
205 // There is a two forms that are acceptable for MRMSrcReg instructions,
206 // those with 3 and 2 operands:
208 // 3 Operands: in this form, the last register (the second input) is the
209 // ModR/M input. The first two operands should be the same, post register
210 // allocation. This is for things like: add r32, r/m32
212 // 2 Operands: this is for things like mov that do not read a second input
214 assert(isReg(MI->getOperand(0)) &&
215 isReg(MI->getOperand(1)) &&
216 (MI->getNumOperands() == 2 ||
217 (MI->getNumOperands() == 3 && isReg(MI->getOperand(2))))
218 && "Bad format for MRMDestReg!");
219 if (MI->getNumOperands() == 3 &&
220 MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
223 toHex(O, getBaseOpcodeFor(Opcode)) << " ";
224 unsigned ModRMReg = MI->getOperand(MI->getNumOperands()-1).getReg();
225 unsigned ExtraReg = MI->getOperand(0).getReg();
226 toHex(O, regModRMByte(ModRMReg, getX86RegNum(ExtraReg)));
229 O << getName(MI->getOpCode()) << " ";
230 printOp(O, MI->getOperand(0), RI);
232 printOp(O, MI->getOperand(MI->getNumOperands()-1), RI);
236 case X86II::MRMDestMem:
237 case X86II::MRMSrcMem:
239 O << "\t\t-"; MI->print(O, TM); break;