1 //===-- X86AsmBackend.cpp - X86 Assembler Backend -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "llvm/Target/TargetAsmBackend.h"
12 #include "X86FixupKinds.h"
13 #include "llvm/ADT/Twine.h"
14 #include "llvm/MC/MCAssembler.h"
15 #include "llvm/MC/MCExpr.h"
16 #include "llvm/MC/MCObjectFormat.h"
17 #include "llvm/MC/MCObjectWriter.h"
18 #include "llvm/MC/MCSectionCOFF.h"
19 #include "llvm/MC/MCSectionELF.h"
20 #include "llvm/MC/MCSectionMachO.h"
21 #include "llvm/Object/MachOFormat.h"
22 #include "llvm/Support/ELF.h"
23 #include "llvm/Support/ErrorHandling.h"
24 #include "llvm/Support/raw_ostream.h"
25 #include "llvm/Target/TargetRegistry.h"
26 #include "llvm/Target/TargetAsmBackend.h"
29 static unsigned getFixupKindLog2Size(unsigned Kind) {
31 default: assert(0 && "invalid fixup kind!");
33 case FK_Data_1: return 0;
35 case FK_Data_2: return 1;
37 case X86::reloc_riprel_4byte:
38 case X86::reloc_riprel_4byte_movq_load:
39 case X86::reloc_signed_4byte:
40 case X86::reloc_global_offset_table:
41 case FK_Data_4: return 2;
42 case FK_Data_8: return 3;
47 class X86AsmBackend : public TargetAsmBackend {
49 X86AsmBackend(const Target &T)
50 : TargetAsmBackend() {}
52 void ApplyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
53 uint64_t Value) const {
54 unsigned Size = 1 << getFixupKindLog2Size(Fixup.getKind());
56 assert(Fixup.getOffset() + Size <= DataSize &&
57 "Invalid fixup offset!");
58 for (unsigned i = 0; i != Size; ++i)
59 Data[Fixup.getOffset() + i] = uint8_t(Value >> (i * 8));
62 bool MayNeedRelaxation(const MCInst &Inst) const;
64 void RelaxInstruction(const MCInst &Inst, MCInst &Res) const;
66 bool WriteNopData(uint64_t Count, MCObjectWriter *OW) const;
68 } // end anonymous namespace
70 static unsigned getRelaxedOpcodeBranch(unsigned Op) {
75 case X86::JAE_1: return X86::JAE_4;
76 case X86::JA_1: return X86::JA_4;
77 case X86::JBE_1: return X86::JBE_4;
78 case X86::JB_1: return X86::JB_4;
79 case X86::JE_1: return X86::JE_4;
80 case X86::JGE_1: return X86::JGE_4;
81 case X86::JG_1: return X86::JG_4;
82 case X86::JLE_1: return X86::JLE_4;
83 case X86::JL_1: return X86::JL_4;
84 case X86::JMP_1: return X86::JMP_4;
85 case X86::JNE_1: return X86::JNE_4;
86 case X86::JNO_1: return X86::JNO_4;
87 case X86::JNP_1: return X86::JNP_4;
88 case X86::JNS_1: return X86::JNS_4;
89 case X86::JO_1: return X86::JO_4;
90 case X86::JP_1: return X86::JP_4;
91 case X86::JS_1: return X86::JS_4;
95 static unsigned getRelaxedOpcodeArith(unsigned Op) {
101 case X86::IMUL16rri8: return X86::IMUL16rri;
102 case X86::IMUL16rmi8: return X86::IMUL16rmi;
103 case X86::IMUL32rri8: return X86::IMUL32rri;
104 case X86::IMUL32rmi8: return X86::IMUL32rmi;
105 case X86::IMUL64rri8: return X86::IMUL64rri32;
106 case X86::IMUL64rmi8: return X86::IMUL64rmi32;
109 case X86::AND16ri8: return X86::AND16ri;
110 case X86::AND16mi8: return X86::AND16mi;
111 case X86::AND32ri8: return X86::AND32ri;
112 case X86::AND32mi8: return X86::AND32mi;
113 case X86::AND64ri8: return X86::AND64ri32;
114 case X86::AND64mi8: return X86::AND64mi32;
117 case X86::OR16ri8: return X86::OR16ri;
118 case X86::OR16mi8: return X86::OR16mi;
119 case X86::OR32ri8: return X86::OR32ri;
120 case X86::OR32mi8: return X86::OR32mi;
121 case X86::OR64ri8: return X86::OR64ri32;
122 case X86::OR64mi8: return X86::OR64mi32;
125 case X86::XOR16ri8: return X86::XOR16ri;
126 case X86::XOR16mi8: return X86::XOR16mi;
127 case X86::XOR32ri8: return X86::XOR32ri;
128 case X86::XOR32mi8: return X86::XOR32mi;
129 case X86::XOR64ri8: return X86::XOR64ri32;
130 case X86::XOR64mi8: return X86::XOR64mi32;
133 case X86::ADD16ri8: return X86::ADD16ri;
134 case X86::ADD16mi8: return X86::ADD16mi;
135 case X86::ADD32ri8: return X86::ADD32ri;
136 case X86::ADD32mi8: return X86::ADD32mi;
137 case X86::ADD64ri8: return X86::ADD64ri32;
138 case X86::ADD64mi8: return X86::ADD64mi32;
141 case X86::SUB16ri8: return X86::SUB16ri;
142 case X86::SUB16mi8: return X86::SUB16mi;
143 case X86::SUB32ri8: return X86::SUB32ri;
144 case X86::SUB32mi8: return X86::SUB32mi;
145 case X86::SUB64ri8: return X86::SUB64ri32;
146 case X86::SUB64mi8: return X86::SUB64mi32;
149 case X86::CMP16ri8: return X86::CMP16ri;
150 case X86::CMP16mi8: return X86::CMP16mi;
151 case X86::CMP32ri8: return X86::CMP32ri;
152 case X86::CMP32mi8: return X86::CMP32mi;
153 case X86::CMP64ri8: return X86::CMP64ri32;
154 case X86::CMP64mi8: return X86::CMP64mi32;
158 static unsigned getRelaxedOpcode(unsigned Op) {
159 unsigned R = getRelaxedOpcodeArith(Op);
162 return getRelaxedOpcodeBranch(Op);
165 bool X86AsmBackend::MayNeedRelaxation(const MCInst &Inst) const {
166 // Branches can always be relaxed.
167 if (getRelaxedOpcodeBranch(Inst.getOpcode()) != Inst.getOpcode())
170 // Check if this instruction is ever relaxable.
171 if (getRelaxedOpcodeArith(Inst.getOpcode()) == Inst.getOpcode())
175 // Check if it has an expression and is not RIP relative.
178 for (unsigned i = 0; i < Inst.getNumOperands(); ++i) {
179 const MCOperand &Op = Inst.getOperand(i);
183 if (Op.isReg() && Op.getReg() == X86::RIP)
187 // FIXME: Why exactly do we need the !hasRIP? Is it just a limitation on
188 // how we do relaxations?
189 return hasExp && !hasRIP;
192 // FIXME: Can tblgen help at all here to verify there aren't other instructions
194 void X86AsmBackend::RelaxInstruction(const MCInst &Inst, MCInst &Res) const {
195 // The only relaxations X86 does is from a 1byte pcrel to a 4byte pcrel.
196 unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode());
198 if (RelaxedOp == Inst.getOpcode()) {
199 SmallString<256> Tmp;
200 raw_svector_ostream OS(Tmp);
201 Inst.dump_pretty(OS);
203 report_fatal_error("unexpected instruction to relax: " + OS.str());
207 Res.setOpcode(RelaxedOp);
210 /// WriteNopData - Write optimal nops to the output file for the \arg Count
211 /// bytes. This returns the number of bytes written. It may return 0 if
212 /// the \arg Count is more than the maximum optimal nops.
213 bool X86AsmBackend::WriteNopData(uint64_t Count, MCObjectWriter *OW) const {
214 static const uint8_t Nops[10][10] = {
222 {0x0f, 0x1f, 0x40, 0x00},
223 // nopl 0(%[re]ax,%[re]ax,1)
224 {0x0f, 0x1f, 0x44, 0x00, 0x00},
225 // nopw 0(%[re]ax,%[re]ax,1)
226 {0x66, 0x0f, 0x1f, 0x44, 0x00, 0x00},
228 {0x0f, 0x1f, 0x80, 0x00, 0x00, 0x00, 0x00},
229 // nopl 0L(%[re]ax,%[re]ax,1)
230 {0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
231 // nopw 0L(%[re]ax,%[re]ax,1)
232 {0x66, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
233 // nopw %cs:0L(%[re]ax,%[re]ax,1)
234 {0x66, 0x2e, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
237 // Write an optimal sequence for the first 15 bytes.
238 const uint64_t OptimalCount = (Count < 16) ? Count : 15;
239 const uint64_t Prefixes = OptimalCount <= 10 ? 0 : OptimalCount - 10;
240 for (uint64_t i = 0, e = Prefixes; i != e; i++)
242 const uint64_t Rest = OptimalCount - Prefixes;
243 for (uint64_t i = 0, e = Rest; i != e; i++)
244 OW->Write8(Nops[Rest - 1][i]);
246 // Finish with single byte nops.
247 for (uint64_t i = OptimalCount, e = Count; i != e; ++i)
256 class ELFX86AsmBackend : public X86AsmBackend {
257 MCELFObjectFormat Format;
260 Triple::OSType OSType;
261 ELFX86AsmBackend(const Target &T, Triple::OSType _OSType)
262 : X86AsmBackend(T), OSType(_OSType) {
263 HasScatteredSymbols = true;
264 HasReliableSymbolDifference = true;
267 virtual const MCObjectFormat &getObjectFormat() const {
271 virtual bool doesSectionRequireSymbols(const MCSection &Section) const {
272 const MCSectionELF &ES = static_cast<const MCSectionELF&>(Section);
273 return ES.getFlags() & MCSectionELF::SHF_MERGE;
277 class ELFX86_32AsmBackend : public ELFX86AsmBackend {
279 ELFX86_32AsmBackend(const Target &T, Triple::OSType OSType)
280 : ELFX86AsmBackend(T, OSType) {}
282 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
283 return createELFObjectWriter(OS, /*Is64Bit=*/false,
285 /*IsLittleEndian=*/true,
286 /*HasRelocationAddend=*/false);
290 class ELFX86_64AsmBackend : public ELFX86AsmBackend {
292 ELFX86_64AsmBackend(const Target &T, Triple::OSType OSType)
293 : ELFX86AsmBackend(T, OSType) {}
295 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
296 return createELFObjectWriter(OS, /*Is64Bit=*/true,
297 OSType, ELF::EM_X86_64,
298 /*IsLittleEndian=*/true,
299 /*HasRelocationAddend=*/true);
303 class WindowsX86AsmBackend : public X86AsmBackend {
305 MCCOFFObjectFormat Format;
308 WindowsX86AsmBackend(const Target &T, bool is64Bit)
311 HasScatteredSymbols = true;
314 virtual const MCObjectFormat &getObjectFormat() const {
318 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
319 return createWinCOFFObjectWriter(OS, Is64Bit);
323 class DarwinX86AsmBackend : public X86AsmBackend {
324 MCMachOObjectFormat Format;
327 DarwinX86AsmBackend(const Target &T)
329 HasScatteredSymbols = true;
332 virtual const MCObjectFormat &getObjectFormat() const {
337 class DarwinX86_32AsmBackend : public DarwinX86AsmBackend {
339 DarwinX86_32AsmBackend(const Target &T)
340 : DarwinX86AsmBackend(T) {}
342 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
343 return createMachObjectWriter(OS, /*Is64Bit=*/false,
344 object::mach::CTM_i386,
345 object::mach::CSX86_ALL,
346 /*IsLittleEndian=*/true);
350 class DarwinX86_64AsmBackend : public DarwinX86AsmBackend {
352 DarwinX86_64AsmBackend(const Target &T)
353 : DarwinX86AsmBackend(T) {
354 HasReliableSymbolDifference = true;
357 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
358 return createMachObjectWriter(OS, /*Is64Bit=*/true,
359 object::mach::CTM_x86_64,
360 object::mach::CSX86_ALL,
361 /*IsLittleEndian=*/true);
364 virtual bool doesSectionRequireSymbols(const MCSection &Section) const {
365 // Temporary labels in the string literals sections require symbols. The
366 // issue is that the x86_64 relocation format does not allow symbol +
367 // offset, and so the linker does not have enough information to resolve the
368 // access to the appropriate atom unless an external relocation is used. For
369 // non-cstring sections, we expect the compiler to use a non-temporary label
370 // for anything that could have an addend pointing outside the symbol.
372 // See <rdar://problem/4765733>.
373 const MCSectionMachO &SMO = static_cast<const MCSectionMachO&>(Section);
374 return SMO.getType() == MCSectionMachO::S_CSTRING_LITERALS;
377 virtual bool isSectionAtomizable(const MCSection &Section) const {
378 const MCSectionMachO &SMO = static_cast<const MCSectionMachO&>(Section);
379 // Fixed sized data sections are uniqued, they cannot be diced into atoms.
380 switch (SMO.getType()) {
384 case MCSectionMachO::S_4BYTE_LITERALS:
385 case MCSectionMachO::S_8BYTE_LITERALS:
386 case MCSectionMachO::S_16BYTE_LITERALS:
387 case MCSectionMachO::S_LITERAL_POINTERS:
388 case MCSectionMachO::S_NON_LAZY_SYMBOL_POINTERS:
389 case MCSectionMachO::S_LAZY_SYMBOL_POINTERS:
390 case MCSectionMachO::S_MOD_INIT_FUNC_POINTERS:
391 case MCSectionMachO::S_MOD_TERM_FUNC_POINTERS:
392 case MCSectionMachO::S_INTERPOSING:
398 } // end anonymous namespace
400 TargetAsmBackend *llvm::createX86_32AsmBackend(const Target &T,
401 const std::string &TT) {
402 switch (Triple(TT).getOS()) {
404 return new DarwinX86_32AsmBackend(T);
405 case Triple::MinGW32:
408 return new WindowsX86AsmBackend(T, false);
410 return new ELFX86_32AsmBackend(T, Triple(TT).getOS());
414 TargetAsmBackend *llvm::createX86_64AsmBackend(const Target &T,
415 const std::string &TT) {
416 switch (Triple(TT).getOS()) {
418 return new DarwinX86_64AsmBackend(T);
419 case Triple::MinGW64:
422 return new WindowsX86AsmBackend(T, true);
424 return new ELFX86_64AsmBackend(T, Triple(TT).getOS());