1 //===-- X86AsmBackend.cpp - X86 Assembler Backend -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "llvm/Target/TargetAsmBackend.h"
12 #include "X86FixupKinds.h"
13 #include "llvm/ADT/Twine.h"
14 #include "llvm/MC/MCAssembler.h"
15 #include "llvm/MC/MCExpr.h"
16 #include "llvm/MC/MCFixupKindInfo.h"
17 #include "llvm/MC/MCMachObjectWriter.h"
18 #include "llvm/MC/MCObjectFormat.h"
19 #include "llvm/MC/MCObjectWriter.h"
20 #include "llvm/MC/MCSectionCOFF.h"
21 #include "llvm/MC/MCSectionELF.h"
22 #include "llvm/MC/MCSectionMachO.h"
23 #include "llvm/Object/MachOFormat.h"
24 #include "llvm/Support/ELF.h"
25 #include "llvm/Support/ErrorHandling.h"
26 #include "llvm/Support/raw_ostream.h"
27 #include "llvm/Target/TargetRegistry.h"
28 #include "llvm/Target/TargetAsmBackend.h"
31 static unsigned getFixupKindLog2Size(unsigned Kind) {
33 default: assert(0 && "invalid fixup kind!");
35 case FK_Data_1: return 0;
37 case FK_Data_2: return 1;
39 case X86::reloc_riprel_4byte:
40 case X86::reloc_riprel_4byte_movq_load:
41 case X86::reloc_signed_4byte:
42 case X86::reloc_global_offset_table:
43 case FK_Data_4: return 2;
44 case FK_Data_8: return 3;
49 class X86MachObjectWriter : public MCMachObjectTargetWriter {
51 X86MachObjectWriter(bool Is64Bit, uint32_t CPUType,
53 : MCMachObjectTargetWriter(Is64Bit, CPUType, CPUSubtype) {}
56 class X86AsmBackend : public TargetAsmBackend {
58 X86AsmBackend(const Target &T)
59 : TargetAsmBackend() {}
61 unsigned getNumFixupKinds() const {
62 return X86::NumTargetFixupKinds;
65 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
66 const static MCFixupKindInfo Infos[X86::NumTargetFixupKinds] = {
67 { "reloc_riprel_4byte", 0, 4 * 8, MCFixupKindInfo::FKF_IsPCRel },
68 { "reloc_riprel_4byte_movq_load", 0, 4 * 8, MCFixupKindInfo::FKF_IsPCRel},
69 { "reloc_signed_4byte", 0, 4 * 8, 0},
70 { "reloc_global_offset_table", 0, 4 * 8, 0}
73 if (Kind < FirstTargetFixupKind)
74 return TargetAsmBackend::getFixupKindInfo(Kind);
76 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
78 return Infos[Kind - FirstTargetFixupKind];
81 void ApplyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
82 uint64_t Value) const {
83 unsigned Size = 1 << getFixupKindLog2Size(Fixup.getKind());
85 assert(Fixup.getOffset() + Size <= DataSize &&
86 "Invalid fixup offset!");
87 for (unsigned i = 0; i != Size; ++i)
88 Data[Fixup.getOffset() + i] = uint8_t(Value >> (i * 8));
91 bool MayNeedRelaxation(const MCInst &Inst) const;
93 void RelaxInstruction(const MCInst &Inst, MCInst &Res) const;
95 bool WriteNopData(uint64_t Count, MCObjectWriter *OW) const;
97 } // end anonymous namespace
99 static unsigned getRelaxedOpcodeBranch(unsigned Op) {
104 case X86::JAE_1: return X86::JAE_4;
105 case X86::JA_1: return X86::JA_4;
106 case X86::JBE_1: return X86::JBE_4;
107 case X86::JB_1: return X86::JB_4;
108 case X86::JE_1: return X86::JE_4;
109 case X86::JGE_1: return X86::JGE_4;
110 case X86::JG_1: return X86::JG_4;
111 case X86::JLE_1: return X86::JLE_4;
112 case X86::JL_1: return X86::JL_4;
113 case X86::JMP_1: return X86::JMP_4;
114 case X86::JNE_1: return X86::JNE_4;
115 case X86::JNO_1: return X86::JNO_4;
116 case X86::JNP_1: return X86::JNP_4;
117 case X86::JNS_1: return X86::JNS_4;
118 case X86::JO_1: return X86::JO_4;
119 case X86::JP_1: return X86::JP_4;
120 case X86::JS_1: return X86::JS_4;
124 static unsigned getRelaxedOpcodeArith(unsigned Op) {
130 case X86::IMUL16rri8: return X86::IMUL16rri;
131 case X86::IMUL16rmi8: return X86::IMUL16rmi;
132 case X86::IMUL32rri8: return X86::IMUL32rri;
133 case X86::IMUL32rmi8: return X86::IMUL32rmi;
134 case X86::IMUL64rri8: return X86::IMUL64rri32;
135 case X86::IMUL64rmi8: return X86::IMUL64rmi32;
138 case X86::AND16ri8: return X86::AND16ri;
139 case X86::AND16mi8: return X86::AND16mi;
140 case X86::AND32ri8: return X86::AND32ri;
141 case X86::AND32mi8: return X86::AND32mi;
142 case X86::AND64ri8: return X86::AND64ri32;
143 case X86::AND64mi8: return X86::AND64mi32;
146 case X86::OR16ri8: return X86::OR16ri;
147 case X86::OR16mi8: return X86::OR16mi;
148 case X86::OR32ri8: return X86::OR32ri;
149 case X86::OR32mi8: return X86::OR32mi;
150 case X86::OR64ri8: return X86::OR64ri32;
151 case X86::OR64mi8: return X86::OR64mi32;
154 case X86::XOR16ri8: return X86::XOR16ri;
155 case X86::XOR16mi8: return X86::XOR16mi;
156 case X86::XOR32ri8: return X86::XOR32ri;
157 case X86::XOR32mi8: return X86::XOR32mi;
158 case X86::XOR64ri8: return X86::XOR64ri32;
159 case X86::XOR64mi8: return X86::XOR64mi32;
162 case X86::ADD16ri8: return X86::ADD16ri;
163 case X86::ADD16mi8: return X86::ADD16mi;
164 case X86::ADD32ri8: return X86::ADD32ri;
165 case X86::ADD32mi8: return X86::ADD32mi;
166 case X86::ADD64ri8: return X86::ADD64ri32;
167 case X86::ADD64mi8: return X86::ADD64mi32;
170 case X86::SUB16ri8: return X86::SUB16ri;
171 case X86::SUB16mi8: return X86::SUB16mi;
172 case X86::SUB32ri8: return X86::SUB32ri;
173 case X86::SUB32mi8: return X86::SUB32mi;
174 case X86::SUB64ri8: return X86::SUB64ri32;
175 case X86::SUB64mi8: return X86::SUB64mi32;
178 case X86::CMP16ri8: return X86::CMP16ri;
179 case X86::CMP16mi8: return X86::CMP16mi;
180 case X86::CMP32ri8: return X86::CMP32ri;
181 case X86::CMP32mi8: return X86::CMP32mi;
182 case X86::CMP64ri8: return X86::CMP64ri32;
183 case X86::CMP64mi8: return X86::CMP64mi32;
187 static unsigned getRelaxedOpcode(unsigned Op) {
188 unsigned R = getRelaxedOpcodeArith(Op);
191 return getRelaxedOpcodeBranch(Op);
194 bool X86AsmBackend::MayNeedRelaxation(const MCInst &Inst) const {
195 // Branches can always be relaxed.
196 if (getRelaxedOpcodeBranch(Inst.getOpcode()) != Inst.getOpcode())
199 // Check if this instruction is ever relaxable.
200 if (getRelaxedOpcodeArith(Inst.getOpcode()) == Inst.getOpcode())
204 // Check if it has an expression and is not RIP relative.
207 for (unsigned i = 0; i < Inst.getNumOperands(); ++i) {
208 const MCOperand &Op = Inst.getOperand(i);
212 if (Op.isReg() && Op.getReg() == X86::RIP)
216 // FIXME: Why exactly do we need the !hasRIP? Is it just a limitation on
217 // how we do relaxations?
218 return hasExp && !hasRIP;
221 // FIXME: Can tblgen help at all here to verify there aren't other instructions
223 void X86AsmBackend::RelaxInstruction(const MCInst &Inst, MCInst &Res) const {
224 // The only relaxations X86 does is from a 1byte pcrel to a 4byte pcrel.
225 unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode());
227 if (RelaxedOp == Inst.getOpcode()) {
228 SmallString<256> Tmp;
229 raw_svector_ostream OS(Tmp);
230 Inst.dump_pretty(OS);
232 report_fatal_error("unexpected instruction to relax: " + OS.str());
236 Res.setOpcode(RelaxedOp);
239 /// WriteNopData - Write optimal nops to the output file for the \arg Count
240 /// bytes. This returns the number of bytes written. It may return 0 if
241 /// the \arg Count is more than the maximum optimal nops.
242 bool X86AsmBackend::WriteNopData(uint64_t Count, MCObjectWriter *OW) const {
243 static const uint8_t Nops[10][10] = {
251 {0x0f, 0x1f, 0x40, 0x00},
252 // nopl 0(%[re]ax,%[re]ax,1)
253 {0x0f, 0x1f, 0x44, 0x00, 0x00},
254 // nopw 0(%[re]ax,%[re]ax,1)
255 {0x66, 0x0f, 0x1f, 0x44, 0x00, 0x00},
257 {0x0f, 0x1f, 0x80, 0x00, 0x00, 0x00, 0x00},
258 // nopl 0L(%[re]ax,%[re]ax,1)
259 {0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
260 // nopw 0L(%[re]ax,%[re]ax,1)
261 {0x66, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
262 // nopw %cs:0L(%[re]ax,%[re]ax,1)
263 {0x66, 0x2e, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
266 // Write an optimal sequence for the first 15 bytes.
267 const uint64_t OptimalCount = (Count < 16) ? Count : 15;
268 const uint64_t Prefixes = OptimalCount <= 10 ? 0 : OptimalCount - 10;
269 for (uint64_t i = 0, e = Prefixes; i != e; i++)
271 const uint64_t Rest = OptimalCount - Prefixes;
272 for (uint64_t i = 0, e = Rest; i != e; i++)
273 OW->Write8(Nops[Rest - 1][i]);
275 // Finish with single byte nops.
276 for (uint64_t i = OptimalCount, e = Count; i != e; ++i)
285 class ELFX86AsmBackend : public X86AsmBackend {
286 MCELFObjectFormat Format;
289 Triple::OSType OSType;
290 ELFX86AsmBackend(const Target &T, Triple::OSType _OSType)
291 : X86AsmBackend(T), OSType(_OSType) {
292 HasScatteredSymbols = true;
293 HasReliableSymbolDifference = true;
296 virtual const MCObjectFormat &getObjectFormat() const {
300 virtual bool doesSectionRequireSymbols(const MCSection &Section) const {
301 const MCSectionELF &ES = static_cast<const MCSectionELF&>(Section);
302 return ES.getFlags() & MCSectionELF::SHF_MERGE;
306 class ELFX86_32AsmBackend : public ELFX86AsmBackend {
308 ELFX86_32AsmBackend(const Target &T, Triple::OSType OSType)
309 : ELFX86AsmBackend(T, OSType) {}
311 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
312 return createELFObjectWriter(OS, /*Is64Bit=*/false,
314 /*IsLittleEndian=*/true,
315 /*HasRelocationAddend=*/false);
319 class ELFX86_64AsmBackend : public ELFX86AsmBackend {
321 ELFX86_64AsmBackend(const Target &T, Triple::OSType OSType)
322 : ELFX86AsmBackend(T, OSType) {}
324 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
325 return createELFObjectWriter(OS, /*Is64Bit=*/true,
326 OSType, ELF::EM_X86_64,
327 /*IsLittleEndian=*/true,
328 /*HasRelocationAddend=*/true);
332 class WindowsX86AsmBackend : public X86AsmBackend {
334 MCCOFFObjectFormat Format;
337 WindowsX86AsmBackend(const Target &T, bool is64Bit)
340 HasScatteredSymbols = true;
343 virtual const MCObjectFormat &getObjectFormat() const {
347 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
348 return createWinCOFFObjectWriter(OS, Is64Bit);
352 class DarwinX86AsmBackend : public X86AsmBackend {
353 MCMachOObjectFormat Format;
356 DarwinX86AsmBackend(const Target &T)
358 HasScatteredSymbols = true;
361 virtual const MCObjectFormat &getObjectFormat() const {
366 class DarwinX86_32AsmBackend : public DarwinX86AsmBackend {
368 DarwinX86_32AsmBackend(const Target &T)
369 : DarwinX86AsmBackend(T) {}
371 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
372 return createMachObjectWriter(new X86MachObjectWriter(
374 object::mach::CTM_i386,
375 object::mach::CSX86_ALL),
376 OS, /*IsLittleEndian=*/true);
380 class DarwinX86_64AsmBackend : public DarwinX86AsmBackend {
382 DarwinX86_64AsmBackend(const Target &T)
383 : DarwinX86AsmBackend(T) {
384 HasReliableSymbolDifference = true;
387 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
388 return createMachObjectWriter(new X86MachObjectWriter(
390 object::mach::CTM_x86_64,
391 object::mach::CSX86_ALL),
392 OS, /*IsLittleEndian=*/true);
395 virtual bool doesSectionRequireSymbols(const MCSection &Section) const {
396 // Temporary labels in the string literals sections require symbols. The
397 // issue is that the x86_64 relocation format does not allow symbol +
398 // offset, and so the linker does not have enough information to resolve the
399 // access to the appropriate atom unless an external relocation is used. For
400 // non-cstring sections, we expect the compiler to use a non-temporary label
401 // for anything that could have an addend pointing outside the symbol.
403 // See <rdar://problem/4765733>.
404 const MCSectionMachO &SMO = static_cast<const MCSectionMachO&>(Section);
405 return SMO.getType() == MCSectionMachO::S_CSTRING_LITERALS;
408 virtual bool isSectionAtomizable(const MCSection &Section) const {
409 const MCSectionMachO &SMO = static_cast<const MCSectionMachO&>(Section);
410 // Fixed sized data sections are uniqued, they cannot be diced into atoms.
411 switch (SMO.getType()) {
415 case MCSectionMachO::S_4BYTE_LITERALS:
416 case MCSectionMachO::S_8BYTE_LITERALS:
417 case MCSectionMachO::S_16BYTE_LITERALS:
418 case MCSectionMachO::S_LITERAL_POINTERS:
419 case MCSectionMachO::S_NON_LAZY_SYMBOL_POINTERS:
420 case MCSectionMachO::S_LAZY_SYMBOL_POINTERS:
421 case MCSectionMachO::S_MOD_INIT_FUNC_POINTERS:
422 case MCSectionMachO::S_MOD_TERM_FUNC_POINTERS:
423 case MCSectionMachO::S_INTERPOSING:
429 } // end anonymous namespace
431 TargetAsmBackend *llvm::createX86_32AsmBackend(const Target &T,
432 const std::string &TT) {
433 switch (Triple(TT).getOS()) {
435 return new DarwinX86_32AsmBackend(T);
436 case Triple::MinGW32:
439 return new WindowsX86AsmBackend(T, false);
441 return new ELFX86_32AsmBackend(T, Triple(TT).getOS());
445 TargetAsmBackend *llvm::createX86_64AsmBackend(const Target &T,
446 const std::string &TT) {
447 switch (Triple(TT).getOS()) {
449 return new DarwinX86_64AsmBackend(T);
450 case Triple::MinGW64:
453 return new WindowsX86AsmBackend(T, true);
455 return new ELFX86_64AsmBackend(T, Triple(TT).getOS());