1 //===-- X86AsmBackend.cpp - X86 Assembler Backend -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "llvm/Target/TargetAsmBackend.h"
12 #include "X86FixupKinds.h"
13 #include "llvm/ADT/Twine.h"
14 #include "llvm/MC/MCAssembler.h"
15 #include "llvm/MC/MCExpr.h"
16 #include "llvm/MC/MCObjectFormat.h"
17 #include "llvm/MC/MCObjectWriter.h"
18 #include "llvm/MC/MCSectionCOFF.h"
19 #include "llvm/MC/MCSectionELF.h"
20 #include "llvm/MC/MCSectionMachO.h"
21 #include "llvm/Support/ELF.h"
22 #include "llvm/Support/MachO.h"
23 #include "llvm/Support/ErrorHandling.h"
24 #include "llvm/Support/raw_ostream.h"
25 #include "llvm/Target/TargetRegistry.h"
26 #include "llvm/Target/TargetAsmBackend.h"
30 static unsigned getFixupKindLog2Size(unsigned Kind) {
32 default: assert(0 && "invalid fixup kind!");
33 case X86::reloc_pcrel_1byte:
34 case FK_Data_1: return 0;
35 case X86::reloc_pcrel_2byte:
36 case FK_Data_2: return 1;
37 case X86::reloc_pcrel_4byte:
38 case X86::reloc_riprel_4byte:
39 case X86::reloc_riprel_4byte_movq_load:
40 case X86::reloc_signed_4byte:
41 case X86::reloc_global_offset_table:
42 case FK_Data_4: return 2;
43 case FK_Data_8: return 3;
48 class X86AsmBackend : public TargetAsmBackend {
50 X86AsmBackend(const Target &T)
51 : TargetAsmBackend(T) {}
53 void ApplyFixup(const MCFixup &Fixup, MCDataFragment &DF,
54 uint64_t Value) const {
55 unsigned Size = 1 << getFixupKindLog2Size(Fixup.getKind());
57 assert(Fixup.getOffset() + Size <= DF.getContents().size() &&
58 "Invalid fixup offset!");
59 for (unsigned i = 0; i != Size; ++i)
60 DF.getContents()[Fixup.getOffset() + i] = uint8_t(Value >> (i * 8));
63 bool MayNeedRelaxation(const MCInst &Inst) const;
65 void RelaxInstruction(const MCInst &Inst, MCInst &Res) const;
67 bool WriteNopData(uint64_t Count, MCObjectWriter *OW) const;
69 } // end anonymous namespace
71 static unsigned getRelaxedOpcodeBranch(unsigned Op) {
76 case X86::JAE_1: return X86::JAE_4;
77 case X86::JA_1: return X86::JA_4;
78 case X86::JBE_1: return X86::JBE_4;
79 case X86::JB_1: return X86::JB_4;
80 case X86::JE_1: return X86::JE_4;
81 case X86::JGE_1: return X86::JGE_4;
82 case X86::JG_1: return X86::JG_4;
83 case X86::JLE_1: return X86::JLE_4;
84 case X86::JL_1: return X86::JL_4;
85 case X86::JMP_1: return X86::JMP_4;
86 case X86::JNE_1: return X86::JNE_4;
87 case X86::JNO_1: return X86::JNO_4;
88 case X86::JNP_1: return X86::JNP_4;
89 case X86::JNS_1: return X86::JNS_4;
90 case X86::JO_1: return X86::JO_4;
91 case X86::JP_1: return X86::JP_4;
92 case X86::JS_1: return X86::JS_4;
96 static unsigned getRelaxedOpcodeArith(unsigned Op) {
102 case X86::IMUL16rri8: return X86::IMUL16rri;
103 case X86::IMUL16rmi8: return X86::IMUL16rmi;
104 case X86::IMUL32rri8: return X86::IMUL32rri;
105 case X86::IMUL32rmi8: return X86::IMUL32rmi;
106 case X86::IMUL64rri8: return X86::IMUL64rri32;
107 case X86::IMUL64rmi8: return X86::IMUL64rmi32;
110 case X86::AND16ri8: return X86::AND16ri;
111 case X86::AND16mi8: return X86::AND16mi;
112 case X86::AND32ri8: return X86::AND32ri;
113 case X86::AND32mi8: return X86::AND32mi;
114 case X86::AND64ri8: return X86::AND64ri32;
115 case X86::AND64mi8: return X86::AND64mi32;
118 case X86::OR16ri8: return X86::OR16ri;
119 case X86::OR16mi8: return X86::OR16mi;
120 case X86::OR32ri8: return X86::OR32ri;
121 case X86::OR32mi8: return X86::OR32mi;
122 case X86::OR64ri8: return X86::OR64ri32;
123 case X86::OR64mi8: return X86::OR64mi32;
126 case X86::XOR16ri8: return X86::XOR16ri;
127 case X86::XOR16mi8: return X86::XOR16mi;
128 case X86::XOR32ri8: return X86::XOR32ri;
129 case X86::XOR32mi8: return X86::XOR32mi;
130 case X86::XOR64ri8: return X86::XOR64ri32;
131 case X86::XOR64mi8: return X86::XOR64mi32;
134 case X86::ADD16ri8: return X86::ADD16ri;
135 case X86::ADD16mi8: return X86::ADD16mi;
136 case X86::ADD32ri8: return X86::ADD32ri;
137 case X86::ADD32mi8: return X86::ADD32mi;
138 case X86::ADD64ri8: return X86::ADD64ri32;
139 case X86::ADD64mi8: return X86::ADD64mi32;
142 case X86::SUB16ri8: return X86::SUB16ri;
143 case X86::SUB16mi8: return X86::SUB16mi;
144 case X86::SUB32ri8: return X86::SUB32ri;
145 case X86::SUB32mi8: return X86::SUB32mi;
146 case X86::SUB64ri8: return X86::SUB64ri32;
147 case X86::SUB64mi8: return X86::SUB64mi32;
150 case X86::CMP16ri8: return X86::CMP16ri;
151 case X86::CMP16mi8: return X86::CMP16mi;
152 case X86::CMP32ri8: return X86::CMP32ri;
153 case X86::CMP32mi8: return X86::CMP32mi;
154 case X86::CMP64ri8: return X86::CMP64ri32;
155 case X86::CMP64mi8: return X86::CMP64mi32;
159 static unsigned getRelaxedOpcode(unsigned Op) {
160 unsigned R = getRelaxedOpcodeArith(Op);
163 return getRelaxedOpcodeBranch(Op);
166 bool X86AsmBackend::MayNeedRelaxation(const MCInst &Inst) const {
167 // Branches can always be relaxed.
168 if (getRelaxedOpcodeBranch(Inst.getOpcode()) != Inst.getOpcode())
171 // Check if this instruction is ever relaxable.
172 if (getRelaxedOpcodeArith(Inst.getOpcode()) == Inst.getOpcode())
176 // Check if it has an expression and is not RIP relative.
179 for (unsigned i = 0; i < Inst.getNumOperands(); ++i) {
180 const MCOperand &Op = Inst.getOperand(i);
184 if (Op.isReg() && Op.getReg() == X86::RIP)
188 // FIXME: Why exactly do we need the !hasRIP? Is it just a limitation on
189 // how we do relaxations?
190 return hasExp && !hasRIP;
193 // FIXME: Can tblgen help at all here to verify there aren't other instructions
195 void X86AsmBackend::RelaxInstruction(const MCInst &Inst, MCInst &Res) const {
196 // The only relaxations X86 does is from a 1byte pcrel to a 4byte pcrel.
197 unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode());
199 if (RelaxedOp == Inst.getOpcode()) {
200 SmallString<256> Tmp;
201 raw_svector_ostream OS(Tmp);
202 Inst.dump_pretty(OS);
204 report_fatal_error("unexpected instruction to relax: " + OS.str());
208 Res.setOpcode(RelaxedOp);
211 /// WriteNopData - Write optimal nops to the output file for the \arg Count
212 /// bytes. This returns the number of bytes written. It may return 0 if
213 /// the \arg Count is more than the maximum optimal nops.
215 /// FIXME this is X86 32-bit specific and should move to a better place.
216 bool X86AsmBackend::WriteNopData(uint64_t Count, MCObjectWriter *OW) const {
217 static const uint8_t Nops[16][16] = {
225 {0x0f, 0x1f, 0x40, 0x00},
226 // nopl 0(%[re]ax,%[re]ax,1)
227 {0x0f, 0x1f, 0x44, 0x00, 0x00},
228 // nopw 0(%[re]ax,%[re]ax,1)
229 {0x66, 0x0f, 0x1f, 0x44, 0x00, 0x00},
231 {0x0f, 0x1f, 0x80, 0x00, 0x00, 0x00, 0x00},
232 // nopl 0L(%[re]ax,%[re]ax,1)
233 {0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
234 // nopw 0L(%[re]ax,%[re]ax,1)
235 {0x66, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
236 // nopw %cs:0L(%[re]ax,%[re]ax,1)
237 {0x66, 0x2e, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
238 // nopw %cs:0L(%[re]ax,%[re]ax,1)
239 {0x66, 0x66, 0x2e, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
240 // nopw 0(%[re]ax,%[re]ax,1)
241 // nopw 0(%[re]ax,%[re]ax,1)
242 {0x66, 0x0f, 0x1f, 0x44, 0x00, 0x00,
243 0x66, 0x0f, 0x1f, 0x44, 0x00, 0x00},
244 // nopw 0(%[re]ax,%[re]ax,1)
245 // nopl 0L(%[re]ax) */
246 {0x66, 0x0f, 0x1f, 0x44, 0x00, 0x00,
247 0x0f, 0x1f, 0x80, 0x00, 0x00, 0x00, 0x00},
250 {0x0f, 0x1f, 0x80, 0x00, 0x00, 0x00, 0x00,
251 0x0f, 0x1f, 0x80, 0x00, 0x00, 0x00, 0x00},
253 // nopl 0L(%[re]ax,%[re]ax,1)
254 {0x0f, 0x1f, 0x80, 0x00, 0x00, 0x00, 0x00,
255 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00}
258 // Write an optimal sequence for the first 15 bytes.
259 uint64_t OptimalCount = (Count < 16) ? Count : 15;
260 for (uint64_t i = 0, e = OptimalCount; i != e; i++)
261 OW->Write8(Nops[OptimalCount - 1][i]);
263 // Finish with single byte nops.
264 for (uint64_t i = OptimalCount, e = Count; i != e; ++i)
273 class ELFX86AsmBackend : public X86AsmBackend {
274 MCELFObjectFormat Format;
277 Triple::OSType OSType;
278 ELFX86AsmBackend(const Target &T, Triple::OSType _OSType)
279 : X86AsmBackend(T), OSType(_OSType) {
280 HasScatteredSymbols = true;
281 HasReliableSymbolDifference = true;
284 virtual const MCObjectFormat &getObjectFormat() const {
288 virtual bool doesSectionRequireSymbols(const MCSection &Section) const {
289 const MCSectionELF &ES = static_cast<const MCSectionELF&>(Section);
290 return ES.getFlags() & MCSectionELF::SHF_MERGE;
293 bool isVirtualSection(const MCSection &Section) const {
294 const MCSectionELF &SE = static_cast<const MCSectionELF&>(Section);
295 return SE.getType() == MCSectionELF::SHT_NOBITS;
299 class ELFX86_32AsmBackend : public ELFX86AsmBackend {
301 ELFX86_32AsmBackend(const Target &T, Triple::OSType OSType)
302 : ELFX86AsmBackend(T, OSType) {}
304 unsigned getPointerSize() const {
308 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
309 return createELFObjectWriter(OS, /*Is64Bit=*/false,
311 /*IsLittleEndian=*/true,
312 /*HasRelocationAddend=*/false);
316 class ELFX86_64AsmBackend : public ELFX86AsmBackend {
318 ELFX86_64AsmBackend(const Target &T, Triple::OSType OSType)
319 : ELFX86AsmBackend(T, OSType) {}
321 unsigned getPointerSize() const {
325 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
326 return createELFObjectWriter(OS, /*Is64Bit=*/true,
327 OSType, ELF::EM_X86_64,
328 /*IsLittleEndian=*/true,
329 /*HasRelocationAddend=*/true);
333 class WindowsX86AsmBackend : public X86AsmBackend {
335 MCCOFFObjectFormat Format;
338 WindowsX86AsmBackend(const Target &T, bool is64Bit)
341 HasScatteredSymbols = true;
344 virtual const MCObjectFormat &getObjectFormat() const {
348 unsigned getPointerSize() const {
355 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
356 return createWinCOFFObjectWriter(OS, Is64Bit);
359 bool isVirtualSection(const MCSection &Section) const {
360 const MCSectionCOFF &SE = static_cast<const MCSectionCOFF&>(Section);
361 return SE.getCharacteristics() & COFF::IMAGE_SCN_CNT_UNINITIALIZED_DATA;
365 class DarwinX86AsmBackend : public X86AsmBackend {
366 MCMachOObjectFormat Format;
369 DarwinX86AsmBackend(const Target &T)
371 HasScatteredSymbols = true;
374 virtual const MCObjectFormat &getObjectFormat() const {
378 bool isVirtualSection(const MCSection &Section) const {
379 const MCSectionMachO &SMO = static_cast<const MCSectionMachO&>(Section);
380 return (SMO.getType() == MCSectionMachO::S_ZEROFILL ||
381 SMO.getType() == MCSectionMachO::S_GB_ZEROFILL ||
382 SMO.getType() == MCSectionMachO::S_THREAD_LOCAL_ZEROFILL);
386 class DarwinX86_32AsmBackend : public DarwinX86AsmBackend {
388 DarwinX86_32AsmBackend(const Target &T)
389 : DarwinX86AsmBackend(T) {}
391 unsigned getPointerSize() const {
395 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
396 return createMachObjectWriter(OS, /*Is64Bit=*/false, MachO::CPUTypeI386,
397 MachO::CPUSubType_I386_ALL,
398 /*IsLittleEndian=*/true);
402 class DarwinX86_64AsmBackend : public DarwinX86AsmBackend {
404 DarwinX86_64AsmBackend(const Target &T)
405 : DarwinX86AsmBackend(T) {
406 HasReliableSymbolDifference = true;
409 unsigned getPointerSize() const {
413 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
414 return createMachObjectWriter(OS, /*Is64Bit=*/true, MachO::CPUTypeX86_64,
415 MachO::CPUSubType_I386_ALL,
416 /*IsLittleEndian=*/true);
419 virtual bool doesSectionRequireSymbols(const MCSection &Section) const {
420 // Temporary labels in the string literals sections require symbols. The
421 // issue is that the x86_64 relocation format does not allow symbol +
422 // offset, and so the linker does not have enough information to resolve the
423 // access to the appropriate atom unless an external relocation is used. For
424 // non-cstring sections, we expect the compiler to use a non-temporary label
425 // for anything that could have an addend pointing outside the symbol.
427 // See <rdar://problem/4765733>.
428 const MCSectionMachO &SMO = static_cast<const MCSectionMachO&>(Section);
429 return SMO.getType() == MCSectionMachO::S_CSTRING_LITERALS;
432 virtual bool isSectionAtomizable(const MCSection &Section) const {
433 const MCSectionMachO &SMO = static_cast<const MCSectionMachO&>(Section);
434 // Fixed sized data sections are uniqued, they cannot be diced into atoms.
435 switch (SMO.getType()) {
439 case MCSectionMachO::S_4BYTE_LITERALS:
440 case MCSectionMachO::S_8BYTE_LITERALS:
441 case MCSectionMachO::S_16BYTE_LITERALS:
442 case MCSectionMachO::S_LITERAL_POINTERS:
443 case MCSectionMachO::S_NON_LAZY_SYMBOL_POINTERS:
444 case MCSectionMachO::S_LAZY_SYMBOL_POINTERS:
445 case MCSectionMachO::S_MOD_INIT_FUNC_POINTERS:
446 case MCSectionMachO::S_MOD_TERM_FUNC_POINTERS:
447 case MCSectionMachO::S_INTERPOSING:
453 } // end anonymous namespace
455 TargetAsmBackend *llvm::createX86_32AsmBackend(const Target &T,
456 const std::string &TT) {
457 switch (Triple(TT).getOS()) {
459 return new DarwinX86_32AsmBackend(T);
460 case Triple::MinGW32:
463 return new WindowsX86AsmBackend(T, false);
465 return new ELFX86_32AsmBackend(T, Triple(TT).getOS());
469 TargetAsmBackend *llvm::createX86_64AsmBackend(const Target &T,
470 const std::string &TT) {
471 switch (Triple(TT).getOS()) {
473 return new DarwinX86_64AsmBackend(T);
474 case Triple::MinGW64:
477 return new WindowsX86AsmBackend(T, true);
479 return new ELFX86_64AsmBackend(T, Triple(TT).getOS());