1 //===-- X86AsmBackend.cpp - X86 Assembler Backend -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "llvm/Target/TargetAsmBackend.h"
12 #include "X86FixupKinds.h"
13 #include "llvm/ADT/Twine.h"
14 #include "llvm/MC/MCAssembler.h"
15 #include "llvm/MC/MCExpr.h"
16 #include "llvm/MC/MCObjectWriter.h"
17 #include "llvm/MC/MCSectionCOFF.h"
18 #include "llvm/MC/MCSectionELF.h"
19 #include "llvm/MC/MCSectionMachO.h"
20 #include "llvm/MC/MachObjectWriter.h"
21 #include "llvm/Support/ErrorHandling.h"
22 #include "llvm/Support/raw_ostream.h"
23 #include "llvm/Target/TargetRegistry.h"
24 #include "llvm/Target/TargetAsmBackend.h"
28 static unsigned getFixupKindLog2Size(unsigned Kind) {
30 default: assert(0 && "invalid fixup kind!");
31 case X86::reloc_pcrel_1byte:
32 case FK_Data_1: return 0;
33 case X86::reloc_pcrel_2byte:
34 case FK_Data_2: return 1;
35 case X86::reloc_pcrel_4byte:
36 case X86::reloc_riprel_4byte:
37 case X86::reloc_riprel_4byte_movq_load:
38 case FK_Data_4: return 2;
39 case FK_Data_8: return 3;
44 class X86AsmBackend : public TargetAsmBackend {
46 X86AsmBackend(const Target &T)
47 : TargetAsmBackend(T) {}
49 void ApplyFixup(const MCFixup &Fixup, MCDataFragment &DF,
50 uint64_t Value) const {
51 unsigned Size = 1 << getFixupKindLog2Size(Fixup.getKind());
53 assert(Fixup.getOffset() + Size <= DF.getContents().size() &&
54 "Invalid fixup offset!");
55 for (unsigned i = 0; i != Size; ++i)
56 DF.getContents()[Fixup.getOffset() + i] = uint8_t(Value >> (i * 8));
59 bool MayNeedRelaxation(const MCInst &Inst) const;
61 void RelaxInstruction(const MCInst &Inst, MCInst &Res) const;
63 bool WriteNopData(uint64_t Count, MCObjectWriter *OW) const;
65 } // end anonymous namespace
67 static unsigned getRelaxedOpcode(unsigned Op) {
72 case X86::JAE_1: return X86::JAE_4;
73 case X86::JA_1: return X86::JA_4;
74 case X86::JBE_1: return X86::JBE_4;
75 case X86::JB_1: return X86::JB_4;
76 case X86::JE_1: return X86::JE_4;
77 case X86::JGE_1: return X86::JGE_4;
78 case X86::JG_1: return X86::JG_4;
79 case X86::JLE_1: return X86::JLE_4;
80 case X86::JL_1: return X86::JL_4;
81 case X86::JMP_1: return X86::JMP_4;
82 case X86::JNE_1: return X86::JNE_4;
83 case X86::JNO_1: return X86::JNO_4;
84 case X86::JNP_1: return X86::JNP_4;
85 case X86::JNS_1: return X86::JNS_4;
86 case X86::JO_1: return X86::JO_4;
87 case X86::JP_1: return X86::JP_4;
88 case X86::JS_1: return X86::JS_4;
92 bool X86AsmBackend::MayNeedRelaxation(const MCInst &Inst) const {
93 // Check if this instruction is ever relaxable.
94 if (getRelaxedOpcode(Inst.getOpcode()) == Inst.getOpcode())
97 // If so, just assume it can be relaxed. Once we support relaxing more complex
98 // instructions we should check that the instruction actually has symbolic
99 // operands before doing this, but we need to be careful about things like
104 // FIXME: Can tblgen help at all here to verify there aren't other instructions
106 void X86AsmBackend::RelaxInstruction(const MCInst &Inst, MCInst &Res) const {
107 // The only relaxations X86 does is from a 1byte pcrel to a 4byte pcrel.
108 unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode());
110 if (RelaxedOp == Inst.getOpcode()) {
111 SmallString<256> Tmp;
112 raw_svector_ostream OS(Tmp);
113 Inst.dump_pretty(OS);
115 report_fatal_error("unexpected instruction to relax: " + OS.str());
119 Res.setOpcode(RelaxedOp);
122 /// WriteNopData - Write optimal nops to the output file for the \arg Count
123 /// bytes. This returns the number of bytes written. It may return 0 if
124 /// the \arg Count is more than the maximum optimal nops.
126 /// FIXME this is X86 32-bit specific and should move to a better place.
127 bool X86AsmBackend::WriteNopData(uint64_t Count, MCObjectWriter *OW) const {
128 static const uint8_t Nops[16][16] = {
136 {0x0f, 0x1f, 0x40, 0x00},
137 // nopl 0(%[re]ax,%[re]ax,1)
138 {0x0f, 0x1f, 0x44, 0x00, 0x00},
139 // nopw 0(%[re]ax,%[re]ax,1)
140 {0x66, 0x0f, 0x1f, 0x44, 0x00, 0x00},
142 {0x0f, 0x1f, 0x80, 0x00, 0x00, 0x00, 0x00},
143 // nopl 0L(%[re]ax,%[re]ax,1)
144 {0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
145 // nopw 0L(%[re]ax,%[re]ax,1)
146 {0x66, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
147 // nopw %cs:0L(%[re]ax,%[re]ax,1)
148 {0x66, 0x2e, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
149 // nopl 0(%[re]ax,%[re]ax,1)
150 // nopw 0(%[re]ax,%[re]ax,1)
151 {0x0f, 0x1f, 0x44, 0x00, 0x00,
152 0x66, 0x0f, 0x1f, 0x44, 0x00, 0x00},
153 // nopw 0(%[re]ax,%[re]ax,1)
154 // nopw 0(%[re]ax,%[re]ax,1)
155 {0x66, 0x0f, 0x1f, 0x44, 0x00, 0x00,
156 0x66, 0x0f, 0x1f, 0x44, 0x00, 0x00},
157 // nopw 0(%[re]ax,%[re]ax,1)
158 // nopl 0L(%[re]ax) */
159 {0x66, 0x0f, 0x1f, 0x44, 0x00, 0x00,
160 0x0f, 0x1f, 0x80, 0x00, 0x00, 0x00, 0x00},
163 {0x0f, 0x1f, 0x80, 0x00, 0x00, 0x00, 0x00,
164 0x0f, 0x1f, 0x80, 0x00, 0x00, 0x00, 0x00},
166 // nopl 0L(%[re]ax,%[re]ax,1)
167 {0x0f, 0x1f, 0x80, 0x00, 0x00, 0x00, 0x00,
168 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00}
171 // Write an optimal sequence for the first 15 bytes.
172 uint64_t OptimalCount = (Count < 16) ? Count : 15;
173 for (uint64_t i = 0, e = OptimalCount; i != e; i++)
174 OW->Write8(Nops[OptimalCount - 1][i]);
176 // Finish with single byte nops.
177 for (uint64_t i = OptimalCount, e = Count; i != e; ++i)
186 class ELFX86AsmBackend : public X86AsmBackend {
188 ELFX86AsmBackend(const Target &T)
190 HasAbsolutizedSet = true;
191 HasScatteredSymbols = true;
194 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
198 bool isVirtualSection(const MCSection &Section) const {
199 const MCSectionELF &SE = static_cast<const MCSectionELF&>(Section);
200 return SE.getType() == MCSectionELF::SHT_NOBITS;;
204 class ELFX86_32AsmBackend : public ELFX86AsmBackend {
206 ELFX86_32AsmBackend(const Target &T)
207 : ELFX86AsmBackend(T) {}
210 class ELFX86_64AsmBackend : public ELFX86AsmBackend {
212 ELFX86_64AsmBackend(const Target &T)
213 : ELFX86AsmBackend(T) {}
216 class WindowsX86AsmBackend : public X86AsmBackend {
218 WindowsX86AsmBackend(const Target &T)
220 HasScatteredSymbols = true;
223 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
224 return createWinCOFFObjectWriter (OS);
227 bool isVirtualSection(const MCSection &Section) const {
228 const MCSectionCOFF &SE = static_cast<const MCSectionCOFF&>(Section);
229 return SE.getCharacteristics() & COFF::IMAGE_SCN_CNT_UNINITIALIZED_DATA;
233 class DarwinX86AsmBackend : public X86AsmBackend {
235 DarwinX86AsmBackend(const Target &T)
237 HasAbsolutizedSet = true;
238 HasScatteredSymbols = true;
241 bool isVirtualSection(const MCSection &Section) const {
242 const MCSectionMachO &SMO = static_cast<const MCSectionMachO&>(Section);
243 return (SMO.getType() == MCSectionMachO::S_ZEROFILL ||
244 SMO.getType() == MCSectionMachO::S_GB_ZEROFILL ||
245 SMO.getType() == MCSectionMachO::S_THREAD_LOCAL_ZEROFILL);
249 class DarwinX86_32AsmBackend : public DarwinX86AsmBackend {
251 DarwinX86_32AsmBackend(const Target &T)
252 : DarwinX86AsmBackend(T) {}
254 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
255 return new MachObjectWriter(OS, /*Is64Bit=*/false);
259 class DarwinX86_64AsmBackend : public DarwinX86AsmBackend {
261 DarwinX86_64AsmBackend(const Target &T)
262 : DarwinX86AsmBackend(T) {
263 HasReliableSymbolDifference = true;
266 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
267 return new MachObjectWriter(OS, /*Is64Bit=*/true);
270 virtual bool doesSectionRequireSymbols(const MCSection &Section) const {
271 // Temporary labels in the string literals sections require symbols. The
272 // issue is that the x86_64 relocation format does not allow symbol +
273 // offset, and so the linker does not have enough information to resolve the
274 // access to the appropriate atom unless an external relocation is used. For
275 // non-cstring sections, we expect the compiler to use a non-temporary label
276 // for anything that could have an addend pointing outside the symbol.
278 // See <rdar://problem/4765733>.
279 const MCSectionMachO &SMO = static_cast<const MCSectionMachO&>(Section);
280 return SMO.getType() == MCSectionMachO::S_CSTRING_LITERALS;
283 virtual bool isSectionAtomizable(const MCSection &Section) const {
284 const MCSectionMachO &SMO = static_cast<const MCSectionMachO&>(Section);
285 // Fixed sized data sections are uniqued, they cannot be diced into atoms.
286 switch (SMO.getType()) {
290 case MCSectionMachO::S_4BYTE_LITERALS:
291 case MCSectionMachO::S_8BYTE_LITERALS:
292 case MCSectionMachO::S_16BYTE_LITERALS:
293 case MCSectionMachO::S_LITERAL_POINTERS:
294 case MCSectionMachO::S_NON_LAZY_SYMBOL_POINTERS:
295 case MCSectionMachO::S_LAZY_SYMBOL_POINTERS:
296 case MCSectionMachO::S_MOD_INIT_FUNC_POINTERS:
297 case MCSectionMachO::S_MOD_TERM_FUNC_POINTERS:
298 case MCSectionMachO::S_INTERPOSING:
304 } // end anonymous namespace
306 TargetAsmBackend *llvm::createX86_32AsmBackend(const Target &T,
307 const std::string &TT) {
308 switch (Triple(TT).getOS()) {
310 return new DarwinX86_32AsmBackend(T);
311 case Triple::MinGW32:
314 return new WindowsX86AsmBackend(T);
316 return new ELFX86_32AsmBackend(T);
320 TargetAsmBackend *llvm::createX86_64AsmBackend(const Target &T,
321 const std::string &TT) {
322 switch (Triple(TT).getOS()) {
324 return new DarwinX86_64AsmBackend(T);
326 return new ELFX86_64AsmBackend(T);