1 //===-- X86.td - Target definition file for the Intel X86 --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This is a target description file for the Intel i386 architecture, referred
11 // to here as the "X86" architecture.
13 //===----------------------------------------------------------------------===//
15 // Get the target-independent interfaces which we are implementing...
17 include "llvm/Target/Target.td"
19 //===----------------------------------------------------------------------===//
20 // X86 Subtarget state
23 def Mode64Bit : SubtargetFeature<"64bit-mode", "In64BitMode", "true",
24 "64-bit mode (x86_64)">;
26 //===----------------------------------------------------------------------===//
27 // X86 Subtarget features
28 //===----------------------------------------------------------------------===//
30 def FeatureCMOV : SubtargetFeature<"cmov","HasCMov", "true",
31 "Enable conditional move instructions">;
33 def FeaturePOPCNT : SubtargetFeature<"popcnt", "HasPOPCNT", "true",
34 "Support POPCNT instruction">;
37 def FeatureMMX : SubtargetFeature<"mmx","X86SSELevel", "MMX",
38 "Enable MMX instructions">;
39 def FeatureSSE1 : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
40 "Enable SSE instructions",
41 // SSE codegen depends on cmovs, and all
42 // SSE1+ processors support them.
43 [FeatureMMX, FeatureCMOV]>;
44 def FeatureSSE2 : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",
45 "Enable SSE2 instructions",
47 def FeatureSSE3 : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
48 "Enable SSE3 instructions",
50 def FeatureSSSE3 : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3",
51 "Enable SSSE3 instructions",
53 def FeatureSSE41 : SubtargetFeature<"sse41", "X86SSELevel", "SSE41",
54 "Enable SSE 4.1 instructions",
56 def FeatureSSE42 : SubtargetFeature<"sse42", "X86SSELevel", "SSE42",
57 "Enable SSE 4.2 instructions",
59 def Feature3DNow : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
60 "Enable 3DNow! instructions",
62 def Feature3DNowA : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
63 "Enable 3DNow! Athlon instructions",
65 // All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied
66 // feature, because SSE2 can be disabled (e.g. for compiling OS kernels)
67 // without disabling 64-bit mode.
68 def Feature64Bit : SubtargetFeature<"64bit", "HasX86_64", "true",
69 "Support 64-bit instructions",
71 def FeatureCMPXCHG16B : SubtargetFeature<"cmpxchg16b", "HasCmpxchg16b", "true",
72 "64-bit with cmpxchg16b",
74 def FeatureSlowBTMem : SubtargetFeature<"slow-bt-mem", "IsBTMemSlow", "true",
75 "Bit testing of memory is slow">;
76 def FeatureFastUAMem : SubtargetFeature<"fast-unaligned-mem",
77 "IsUAMemFast", "true",
78 "Fast unaligned memory access">;
79 def FeatureSSE4A : SubtargetFeature<"sse4a", "HasSSE4A", "true",
80 "Support SSE 4a instructions",
83 def FeatureAVX : SubtargetFeature<"avx", "X86SSELevel", "AVX",
84 "Enable AVX instructions",
86 def FeatureAVX2 : SubtargetFeature<"avx2", "X86SSELevel", "AVX2",
87 "Enable AVX2 instructions",
89 def FeatureAVX512 : SubtargetFeature<"avx-512", "X86SSELevel", "AVX512",
90 "Enable AVX-512 instructions",
92 def FeatureERI : SubtargetFeature<"avx-512-eri", "HasERI", "true",
93 "Enable AVX-512 Exponential and Reciprocal Instructions">;
94 def FeatureCDI : SubtargetFeature<"avx-512-cdi", "HasCDI", "true",
95 "Enable AVX-512 Conflict Detection Instructions">;
96 def FeaturePFI : SubtargetFeature<"avx-512-pfi", "HasPFI", "true",
97 "Enable AVX-512 PreFetch Instructions">;
99 def FeaturePCLMUL : SubtargetFeature<"pclmul", "HasPCLMUL", "true",
100 "Enable packed carry-less multiplication instructions",
102 def FeatureFMA : SubtargetFeature<"fma", "HasFMA", "true",
103 "Enable three-operand fused multiple-add",
105 def FeatureFMA4 : SubtargetFeature<"fma4", "HasFMA4", "true",
106 "Enable four-operand fused multiple-add",
107 [FeatureAVX, FeatureSSE4A]>;
108 def FeatureXOP : SubtargetFeature<"xop", "HasXOP", "true",
109 "Enable XOP instructions",
111 def FeatureVectorUAMem : SubtargetFeature<"vector-unaligned-mem",
112 "HasVectorUAMem", "true",
113 "Allow unaligned memory operands on vector/SIMD instructions">;
114 def FeatureAES : SubtargetFeature<"aes", "HasAES", "true",
115 "Enable AES instructions",
117 def FeatureMOVBE : SubtargetFeature<"movbe", "HasMOVBE", "true",
118 "Support MOVBE instruction">;
119 def FeatureRDRAND : SubtargetFeature<"rdrand", "HasRDRAND", "true",
120 "Support RDRAND instruction">;
121 def FeatureF16C : SubtargetFeature<"f16c", "HasF16C", "true",
122 "Support 16-bit floating point conversion instructions">;
123 def FeatureFSGSBase : SubtargetFeature<"fsgsbase", "HasFSGSBase", "true",
124 "Support FS/GS Base instructions">;
125 def FeatureLZCNT : SubtargetFeature<"lzcnt", "HasLZCNT", "true",
126 "Support LZCNT instruction">;
127 def FeatureBMI : SubtargetFeature<"bmi", "HasBMI", "true",
128 "Support BMI instructions">;
129 def FeatureBMI2 : SubtargetFeature<"bmi2", "HasBMI2", "true",
130 "Support BMI2 instructions">;
131 def FeatureRTM : SubtargetFeature<"rtm", "HasRTM", "true",
132 "Support RTM instructions">;
133 def FeatureHLE : SubtargetFeature<"hle", "HasHLE", "true",
135 def FeatureADX : SubtargetFeature<"adx", "HasADX", "true",
136 "Support ADX instructions">;
137 def FeaturePRFCHW : SubtargetFeature<"prfchw", "HasPRFCHW", "true",
138 "Support PRFCHW instructions">;
139 def FeatureRDSEED : SubtargetFeature<"rdseed", "HasRDSEED", "true",
140 "Support RDSEED instruction">;
141 def FeatureLeaForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true",
142 "Use LEA for adjusting the stack pointer">;
143 def FeatureSlowDivide : SubtargetFeature<"idiv-to-divb",
144 "HasSlowDivide", "true",
145 "Use small divide for positive values less than 256">;
146 def FeaturePadShortFunctions : SubtargetFeature<"pad-short-functions",
147 "PadShortFunctions", "true",
148 "Pad short functions">;
149 def FeatureCallRegIndirect : SubtargetFeature<"call-reg-indirect",
150 "CallRegIndirect", "true",
151 "Call register indirect">;
152 def FeatureLEAUsesAG : SubtargetFeature<"lea-uses-ag", "LEAUsesAG", "true",
153 "LEA instruction needs inputs at AG stage">;
155 //===----------------------------------------------------------------------===//
156 // X86 processors supported.
157 //===----------------------------------------------------------------------===//
159 include "X86Schedule.td"
161 def ProcIntelAtom : SubtargetFeature<"atom", "X86ProcFamily", "IntelAtom",
162 "Intel Atom processors">;
164 class Proc<string Name, list<SubtargetFeature> Features>
165 : ProcessorModel<Name, GenericModel, Features>;
167 def : Proc<"generic", []>;
168 def : Proc<"i386", []>;
169 def : Proc<"i486", []>;
170 def : Proc<"i586", []>;
171 def : Proc<"pentium", []>;
172 def : Proc<"pentium-mmx", [FeatureMMX]>;
173 def : Proc<"i686", []>;
174 def : Proc<"pentiumpro", [FeatureCMOV]>;
175 def : Proc<"pentium2", [FeatureMMX, FeatureCMOV]>;
176 def : Proc<"pentium3", [FeatureSSE1]>;
177 def : Proc<"pentium3m", [FeatureSSE1, FeatureSlowBTMem]>;
178 def : Proc<"pentium-m", [FeatureSSE2, FeatureSlowBTMem]>;
179 def : Proc<"pentium4", [FeatureSSE2]>;
180 def : Proc<"pentium4m", [FeatureSSE2, FeatureSlowBTMem]>;
181 def : Proc<"x86-64", [FeatureSSE2, Feature64Bit, FeatureSlowBTMem,
184 def : ProcessorModel<"yonah", SandyBridgeModel,
185 [FeatureSSE3, FeatureSlowBTMem]>;
188 def : Proc<"prescott", [FeatureSSE3, FeatureSlowBTMem]>;
189 def : Proc<"nocona", [FeatureSSE3, FeatureCMPXCHG16B, FeatureSlowBTMem]>;
191 // Intel Core 2 Solo/Duo.
192 def : ProcessorModel<"core2", SandyBridgeModel,
193 [FeatureSSSE3, FeatureCMPXCHG16B, FeatureSlowBTMem]>;
194 def : ProcessorModel<"penryn", SandyBridgeModel,
195 [FeatureSSE41, FeatureCMPXCHG16B, FeatureSlowBTMem]>;
198 def : ProcessorModel<"atom", AtomModel,
199 [ProcIntelAtom, FeatureSSSE3, FeatureCMPXCHG16B,
200 FeatureMOVBE, FeatureSlowBTMem, FeatureLeaForSP,
202 FeatureCallRegIndirect,
204 FeaturePadShortFunctions]>;
206 // "Arrandale" along with corei3 and corei5
207 def : ProcessorModel<"corei7", SandyBridgeModel,
208 [FeatureSSE42, FeatureCMPXCHG16B, FeatureSlowBTMem,
209 FeatureFastUAMem, FeaturePOPCNT, FeatureAES]>;
211 def : ProcessorModel<"nehalem", SandyBridgeModel,
212 [FeatureSSE42, FeatureCMPXCHG16B, FeatureSlowBTMem,
213 FeatureFastUAMem, FeaturePOPCNT]>;
214 // Westmere is a similar machine to nehalem with some additional features.
215 // Westmere is the corei3/i5/i7 path from nehalem to sandybridge
216 def : ProcessorModel<"westmere", SandyBridgeModel,
217 [FeatureSSE42, FeatureCMPXCHG16B, FeatureSlowBTMem,
218 FeatureFastUAMem, FeaturePOPCNT, FeatureAES,
221 // SSE is not listed here since llvm treats AVX as a reimplementation of SSE,
222 // rather than a superset.
223 def : ProcessorModel<"corei7-avx", SandyBridgeModel,
224 [FeatureAVX, FeatureCMPXCHG16B, FeatureFastUAMem,
225 FeaturePOPCNT, FeatureAES, FeaturePCLMUL]>;
227 def : ProcessorModel<"core-avx-i", SandyBridgeModel,
228 [FeatureAVX, FeatureCMPXCHG16B, FeatureFastUAMem,
229 FeaturePOPCNT, FeatureAES, FeaturePCLMUL, FeatureRDRAND,
230 FeatureF16C, FeatureFSGSBase]>;
233 def : ProcessorModel<"core-avx2", HaswellModel,
234 [FeatureAVX2, FeatureCMPXCHG16B, FeatureFastUAMem,
235 FeaturePOPCNT, FeatureAES, FeaturePCLMUL, FeatureRDRAND,
236 FeatureF16C, FeatureFSGSBase, FeatureMOVBE, FeatureLZCNT,
237 FeatureBMI, FeatureBMI2, FeatureFMA, FeatureRTM,
241 // FIXME: define KNL model
242 def : ProcessorModel<"knl", HaswellModel,
243 [FeatureAVX512, FeatureERI, FeatureCDI, FeaturePFI,
244 FeatureCMPXCHG16B, FeatureFastUAMem, FeaturePOPCNT,
245 FeatureAES, FeaturePCLMUL, FeatureRDRAND, FeatureF16C,
246 FeatureFSGSBase, FeatureMOVBE, FeatureLZCNT, FeatureBMI,
247 FeatureBMI2, FeatureFMA, FeatureRTM, FeatureHLE]>;
249 def : Proc<"k6", [FeatureMMX]>;
250 def : Proc<"k6-2", [Feature3DNow]>;
251 def : Proc<"k6-3", [Feature3DNow]>;
252 def : Proc<"athlon", [Feature3DNowA, FeatureSlowBTMem]>;
253 def : Proc<"athlon-tbird", [Feature3DNowA, FeatureSlowBTMem]>;
254 def : Proc<"athlon-4", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem]>;
255 def : Proc<"athlon-xp", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem]>;
256 def : Proc<"athlon-mp", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem]>;
257 def : Proc<"k8", [FeatureSSE2, Feature3DNowA, Feature64Bit,
259 def : Proc<"opteron", [FeatureSSE2, Feature3DNowA, Feature64Bit,
261 def : Proc<"athlon64", [FeatureSSE2, Feature3DNowA, Feature64Bit,
263 def : Proc<"athlon-fx", [FeatureSSE2, Feature3DNowA, Feature64Bit,
265 def : Proc<"k8-sse3", [FeatureSSE3, Feature3DNowA, FeatureCMPXCHG16B,
267 def : Proc<"opteron-sse3", [FeatureSSE3, Feature3DNowA, FeatureCMPXCHG16B,
269 def : Proc<"athlon64-sse3", [FeatureSSE3, Feature3DNowA, FeatureCMPXCHG16B,
271 def : Proc<"amdfam10", [FeatureSSE4A,
272 Feature3DNowA, FeatureCMPXCHG16B, FeatureLZCNT,
273 FeaturePOPCNT, FeatureSlowBTMem]>;
275 def : Proc<"btver1", [FeatureSSSE3, FeatureSSE4A, FeatureCMPXCHG16B,
276 FeatureLZCNT, FeaturePOPCNT]>;
278 def : Proc<"btver2", [FeatureAVX, FeatureSSE4A, FeatureCMPXCHG16B,
279 FeatureAES, FeaturePCLMUL, FeatureBMI,
280 FeatureF16C, FeatureMOVBE, FeatureLZCNT,
283 def : Proc<"bdver1", [FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B,
284 FeatureAES, FeaturePCLMUL,
285 FeatureLZCNT, FeaturePOPCNT]>;
287 def : Proc<"bdver2", [FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B,
288 FeatureAES, FeaturePCLMUL,
289 FeatureF16C, FeatureLZCNT,
290 FeaturePOPCNT, FeatureBMI, FeatureFMA]>;
291 def : Proc<"geode", [Feature3DNowA]>;
293 def : Proc<"winchip-c6", [FeatureMMX]>;
294 def : Proc<"winchip2", [Feature3DNow]>;
295 def : Proc<"c3", [Feature3DNow]>;
296 def : Proc<"c3-2", [FeatureSSE1]>;
298 //===----------------------------------------------------------------------===//
299 // Register File Description
300 //===----------------------------------------------------------------------===//
302 include "X86RegisterInfo.td"
304 //===----------------------------------------------------------------------===//
305 // Instruction Descriptions
306 //===----------------------------------------------------------------------===//
308 include "X86InstrInfo.td"
310 def X86InstrInfo : InstrInfo;
312 //===----------------------------------------------------------------------===//
313 // Calling Conventions
314 //===----------------------------------------------------------------------===//
316 include "X86CallingConv.td"
319 //===----------------------------------------------------------------------===//
321 //===----------------------------------------------------------------------===//
323 def ATTAsmParser : AsmParser {
324 string AsmParserClassName = "AsmParser";
327 def ATTAsmParserVariant : AsmParserVariant {
333 // Discard comments in assembly strings.
334 string CommentDelimiter = "#";
336 // Recognize hard coded registers.
337 string RegisterPrefix = "%";
340 def IntelAsmParserVariant : AsmParserVariant {
344 string Name = "intel";
346 // Discard comments in assembly strings.
347 string CommentDelimiter = ";";
349 // Recognize hard coded registers.
350 string RegisterPrefix = "";
353 //===----------------------------------------------------------------------===//
355 //===----------------------------------------------------------------------===//
357 // The X86 target supports two different syntaxes for emitting machine code.
358 // This is controlled by the -x86-asm-syntax={att|intel}
359 def ATTAsmWriter : AsmWriter {
360 string AsmWriterClassName = "ATTInstPrinter";
362 bit isMCAsmWriter = 1;
364 def IntelAsmWriter : AsmWriter {
365 string AsmWriterClassName = "IntelInstPrinter";
367 bit isMCAsmWriter = 1;
371 // Information about the instructions...
372 let InstructionSet = X86InstrInfo;
373 let AssemblyParsers = [ATTAsmParser];
374 let AssemblyParserVariants = [ATTAsmParserVariant, IntelAsmParserVariant];
375 let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];