lib/Target/X86/X86.td

   1 //===-- X86.td - Target definition file for the Intel X86 --*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This is a target description file for the Intel i386 architecture, referred
  11 // to here as the "X86" architecture.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 // Get the target-independent interfaces which we are implementing...
  16 //
  17 include "llvm/Target/Target.td"
  18
  19 //===----------------------------------------------------------------------===//
  20 // X86 Subtarget state
  21 //
  22
  23 def Mode64Bit : SubtargetFeature<"64bit-mode", "In64BitMode", "true",
  24                                   "64-bit mode (x86_64)">;
  25 def Mode32Bit : SubtargetFeature<"32bit-mode", "In32BitMode", "true",
  26                                   "32-bit mode (80386)">;
  27 def Mode16Bit : SubtargetFeature<"16bit-mode", "In16BitMode", "true",
  28                                   "16-bit mode (i8086)">;
  29
  30 //===----------------------------------------------------------------------===//
  31 // X86 Subtarget features
  32 //===----------------------------------------------------------------------===//
  33
  34 def FeatureCMOV    : SubtargetFeature<"cmov","HasCMov", "true",
  35                                       "Enable conditional move instructions">;
  36
  37 def FeaturePOPCNT   : SubtargetFeature<"popcnt", "HasPOPCNT", "true",
  38                                        "Support POPCNT instruction">;
  39
  40
  41 def FeatureMMX     : SubtargetFeature<"mmx","X86SSELevel", "MMX",
  42                                       "Enable MMX instructions">;
  43 def FeatureSSE1    : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
  44                                       "Enable SSE instructions",
  45                                       // SSE codegen depends on cmovs, and all
  46                                       // SSE1+ processors support them.
  47                                       [FeatureMMX, FeatureCMOV]>;
  48 def FeatureSSE2    : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",
  49                                       "Enable SSE2 instructions",
  50                                       [FeatureSSE1]>;
  51 def FeatureSSE3    : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
  52                                       "Enable SSE3 instructions",
  53                                       [FeatureSSE2]>;
  54 def FeatureSSSE3   : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3",
  55                                       "Enable SSSE3 instructions",
  56                                       [FeatureSSE3]>;
  57 def FeatureSSE41   : SubtargetFeature<"sse4.1", "X86SSELevel", "SSE41",
  58                                       "Enable SSE 4.1 instructions",
  59                                       [FeatureSSSE3]>;
  60 def FeatureSSE42   : SubtargetFeature<"sse4.2", "X86SSELevel", "SSE42",
  61                                       "Enable SSE 4.2 instructions",
  62                                       [FeatureSSE41]>;
  63 def Feature3DNow   : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
  64                                       "Enable 3DNow! instructions",
  65                                       [FeatureMMX]>;
  66 def Feature3DNowA  : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
  67                                       "Enable 3DNow! Athlon instructions",
  68                                       [Feature3DNow]>;
  69 // All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied
  70 // feature, because SSE2 can be disabled (e.g. for compiling OS kernels)
  71 // without disabling 64-bit mode.
  72 def Feature64Bit   : SubtargetFeature<"64bit", "HasX86_64", "true",
  73                                       "Support 64-bit instructions",
  74                                       [FeatureCMOV]>;
  75 def FeatureCMPXCHG16B : SubtargetFeature<"cx16", "HasCmpxchg16b", "true",
  76                                       "64-bit with cmpxchg16b",
  77                                       [Feature64Bit]>;
  78 def FeatureSlowBTMem : SubtargetFeature<"slow-bt-mem", "IsBTMemSlow", "true",
  79                                        "Bit testing of memory is slow">;
  80 def FeatureSlowSHLD : SubtargetFeature<"slow-shld", "IsSHLDSlow", "true",
  81                                        "SHLD instruction is slow">;
  82 // FIXME: This is a 16-byte (SSE/AVX) feature; we should rename it to make that
  83 // explicit. Also, it seems this would be the default state for most chips
  84 // going forward, so it would probably be better to negate the logic and
  85 // match the 32-byte "slow mem" feature below.
  86 def FeatureFastUAMem : SubtargetFeature<"fast-unaligned-mem",
  87                                         "IsUAMemFast", "true",
  88                                         "Fast unaligned memory access">;
  89 def FeatureSlowUAMem32 : SubtargetFeature<"slow-unaligned-mem-32",
  90                             "IsUAMem32Slow", "true",
  91                             "Slow unaligned 32-byte memory access">;
  92 def FeatureSSE4A   : SubtargetFeature<"sse4a", "HasSSE4A", "true",
  93                                       "Support SSE 4a instructions",
  94                                       [FeatureSSE3]>;
  95
  96 def FeatureAVX     : SubtargetFeature<"avx", "X86SSELevel", "AVX",
  97                                       "Enable AVX instructions",
  98                                       [FeatureSSE42]>;
  99 def FeatureAVX2    : SubtargetFeature<"avx2", "X86SSELevel", "AVX2",
 100                                       "Enable AVX2 instructions",
 101                                       [FeatureAVX]>;
 102 def FeatureAVX512   : SubtargetFeature<"avx512f", "X86SSELevel", "AVX512F",
 103                                       "Enable AVX-512 instructions",
 104                                       [FeatureAVX2]>;
 105 def FeatureERI      : SubtargetFeature<"avx512er", "HasERI", "true",
 106                       "Enable AVX-512 Exponential and Reciprocal Instructions",
 107                                       [FeatureAVX512]>;
 108 def FeatureCDI      : SubtargetFeature<"avx512cd", "HasCDI", "true",
 109                       "Enable AVX-512 Conflict Detection Instructions",
 110                                       [FeatureAVX512]>;
 111 def FeaturePFI      : SubtargetFeature<"avx512pf", "HasPFI", "true",
 112                       "Enable AVX-512 PreFetch Instructions",
 113                                       [FeatureAVX512]>;
 114 def FeatureDQI     : SubtargetFeature<"avx512dq", "HasDQI", "true",
 115                       "Enable AVX-512 Doubleword and Quadword Instructions",
 116                                       [FeatureAVX512]>;
 117 def FeatureBWI     : SubtargetFeature<"avx512bw", "HasBWI", "true",
 118                       "Enable AVX-512 Byte and Word Instructions",
 119                                       [FeatureAVX512]>;
 120 def FeatureVLX     : SubtargetFeature<"avx512vl", "HasVLX", "true",
 121                       "Enable AVX-512 Vector Length eXtensions",
 122                                       [FeatureAVX512]>;
 123 def FeaturePCLMUL  : SubtargetFeature<"pclmul", "HasPCLMUL", "true",
 124                          "Enable packed carry-less multiplication instructions",
 125                                [FeatureSSE2]>;
 126 def FeatureFMA     : SubtargetFeature<"fma", "HasFMA", "true",
 127                                       "Enable three-operand fused multiple-add",
 128                                       [FeatureAVX]>;
 129 def FeatureFMA4    : SubtargetFeature<"fma4", "HasFMA4", "true",
 130                                       "Enable four-operand fused multiple-add",
 131                                       [FeatureAVX, FeatureSSE4A]>;
 132 def FeatureXOP     : SubtargetFeature<"xop", "HasXOP", "true",
 133                                       "Enable XOP instructions",
 134                                       [FeatureFMA4]>;
 135 def FeatureVectorUAMem : SubtargetFeature<"vector-unaligned-mem",
 136                                           "HasVectorUAMem", "true",
 137                  "Allow unaligned memory operands on vector/SIMD instructions">;
 138 def FeatureAES     : SubtargetFeature<"aes", "HasAES", "true",
 139                                       "Enable AES instructions",
 140                                       [FeatureSSE2]>;
 141 def FeatureTBM     : SubtargetFeature<"tbm", "HasTBM", "true",
 142                                       "Enable TBM instructions">;
 143 def FeatureMOVBE   : SubtargetFeature<"movbe", "HasMOVBE", "true",
 144                                       "Support MOVBE instruction">;
 145 def FeatureRDRAND  : SubtargetFeature<"rdrnd", "HasRDRAND", "true",
 146                                       "Support RDRAND instruction">;
 147 def FeatureF16C    : SubtargetFeature<"f16c", "HasF16C", "true",
 148                        "Support 16-bit floating point conversion instructions",
 149                        [FeatureAVX]>;
 150 def FeatureFSGSBase : SubtargetFeature<"fsgsbase", "HasFSGSBase", "true",
 151                                        "Support FS/GS Base instructions">;
 152 def FeatureLZCNT   : SubtargetFeature<"lzcnt", "HasLZCNT", "true",
 153                                       "Support LZCNT instruction">;
 154 def FeatureBMI     : SubtargetFeature<"bmi", "HasBMI", "true",
 155                                       "Support BMI instructions">;
 156 def FeatureBMI2    : SubtargetFeature<"bmi2", "HasBMI2", "true",
 157                                       "Support BMI2 instructions">;
 158 def FeatureRTM     : SubtargetFeature<"rtm", "HasRTM", "true",
 159                                       "Support RTM instructions">;
 160 def FeatureHLE     : SubtargetFeature<"hle", "HasHLE", "true",
 161                                       "Support HLE">;
 162 def FeatureADX     : SubtargetFeature<"adx", "HasADX", "true",
 163                                       "Support ADX instructions">;
 164 def FeatureSHA     : SubtargetFeature<"sha", "HasSHA", "true",
 165                                       "Enable SHA instructions",
 166                                       [FeatureSSE2]>;
 167 def FeatureSGX     : SubtargetFeature<"sgx", "HasSGX", "true",
 168                                       "Support SGX instructions">;
 169 def FeaturePRFCHW  : SubtargetFeature<"prfchw", "HasPRFCHW", "true",
 170                                       "Support PRFCHW instructions">;
 171 def FeatureRDSEED  : SubtargetFeature<"rdseed", "HasRDSEED", "true",
 172                                       "Support RDSEED instruction">;
 173 def FeatureSMAP    : SubtargetFeature<"smap", "HasSMAP", "true",
 174                                       "Support SMAP instructions">;
 175 def FeatureLeaForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true",
 176                                      "Use LEA for adjusting the stack pointer">;
 177 def FeatureSlowDivide32 : SubtargetFeature<"idivl-to-divb",
 178                                      "HasSlowDivide32", "true",
 179                                      "Use 8-bit divide for positive values less than 256">;
 180 def FeatureSlowDivide64 : SubtargetFeature<"idivq-to-divw",
 181                                      "HasSlowDivide64", "true",
 182                                      "Use 16-bit divide for positive values less than 65536">;
 183 def FeaturePadShortFunctions : SubtargetFeature<"pad-short-functions",
 184                                      "PadShortFunctions", "true",
 185                                      "Pad short functions">;
 186 def FeatureCallRegIndirect : SubtargetFeature<"call-reg-indirect",
 187                                      "CallRegIndirect", "true",
 188                                      "Call register indirect">;
 189 def FeatureLEAUsesAG : SubtargetFeature<"lea-uses-ag", "LEAUsesAG", "true",
 190                                    "LEA instruction needs inputs at AG stage">;
 191 def FeatureSlowLEA : SubtargetFeature<"slow-lea", "SlowLEA", "true",
 192                                    "LEA instruction with certain arguments is slow">;
 193 def FeatureSlowIncDec : SubtargetFeature<"slow-incdec", "SlowIncDec", "true",
 194                                    "INC and DEC instructions are slower than ADD and SUB">;
 195 def FeatureUseSqrtEst : SubtargetFeature<"use-sqrt-est", "UseSqrtEst", "true",
 196                             "Use RSQRT* to optimize square root calculations">;
 197 def FeatureUseRecipEst : SubtargetFeature<"use-recip-est", "UseReciprocalEst",
 198                           "true", "Use RCP* to optimize division calculations">;
 199
 200 //===----------------------------------------------------------------------===//
 201 // X86 processors supported.
 202 //===----------------------------------------------------------------------===//
 203
 204 include "X86Schedule.td"
 205
 206 def ProcIntelAtom : SubtargetFeature<"atom", "X86ProcFamily", "IntelAtom",
 207                     "Intel Atom processors">;
 208 def ProcIntelSLM  : SubtargetFeature<"slm", "X86ProcFamily", "IntelSLM",
 209                     "Intel Silvermont processors">;
 210
 211 class Proc<string Name, list<SubtargetFeature> Features>
 212  : ProcessorModel<Name, GenericModel, Features>;
 213
 214 def : Proc<"generic",         []>;
 215 def : Proc<"i386",            []>;
 216 def : Proc<"i486",            []>;
 217 def : Proc<"i586",            []>;
 218 def : Proc<"pentium",         []>;
 219 def : Proc<"pentium-mmx",     [FeatureMMX]>;
 220 def : Proc<"i686",            []>;
 221 def : Proc<"pentiumpro",      [FeatureCMOV]>;
 222 def : Proc<"pentium2",        [FeatureMMX, FeatureCMOV]>;
 223 def : Proc<"pentium3",        [FeatureSSE1]>;
 224 def : Proc<"pentium3m",       [FeatureSSE1, FeatureSlowBTMem]>;
 225 def : Proc<"pentium-m",       [FeatureSSE2, FeatureSlowBTMem]>;
 226 def : Proc<"pentium4",        [FeatureSSE2]>;
 227 def : Proc<"pentium4m",       [FeatureSSE2, FeatureSlowBTMem]>;
 228
 229 // Intel Core Duo.
 230 def : ProcessorModel<"yonah", SandyBridgeModel,
 231                      [FeatureSSE3, FeatureSlowBTMem]>;
 232
 233 // NetBurst.
 234 def : Proc<"prescott", [FeatureSSE3, FeatureSlowBTMem]>;
 235 def : Proc<"nocona",   [FeatureSSE3, FeatureCMPXCHG16B, FeatureSlowBTMem]>;
 236
 237 // Intel Core 2 Solo/Duo.
 238 def : ProcessorModel<"core2", SandyBridgeModel,
 239                      [FeatureSSSE3, FeatureCMPXCHG16B, FeatureSlowBTMem]>;
 240 def : ProcessorModel<"penryn", SandyBridgeModel,
 241                      [FeatureSSE41, FeatureCMPXCHG16B, FeatureSlowBTMem]>;
 242
 243 // Atom CPUs.
 244 class BonnellProc<string Name> : ProcessorModel<Name, AtomModel, [
 245                                    ProcIntelAtom,
 246                                    FeatureSSSE3,
 247                                    FeatureCMPXCHG16B,
 248                                    FeatureMOVBE,
 249                                    FeatureSlowBTMem,
 250                                    FeatureLeaForSP,
 251                                    FeatureSlowDivide32,
 252                                    FeatureSlowDivide64,
 253                                    FeatureCallRegIndirect,
 254                                    FeatureLEAUsesAG,
 255                                    FeaturePadShortFunctions
 256                                  ]>;
 257 def : BonnellProc<"bonnell">;
 258 def : BonnellProc<"atom">; // Pin the generic name to the baseline.
 259
 260 class SilvermontProc<string Name> : ProcessorModel<Name, SLMModel, [
 261                                       ProcIntelSLM,
 262                                       FeatureSSE42,
 263                                       FeatureCMPXCHG16B,
 264                                       FeatureMOVBE,
 265                                       FeaturePOPCNT,
 266                                       FeaturePCLMUL,
 267                                       FeatureAES,
 268                                       FeatureSlowDivide64,
 269                                       FeatureCallRegIndirect,
 270                                       FeaturePRFCHW,
 271                                       FeatureSlowLEA,
 272                                       FeatureSlowIncDec,
 273                                       FeatureSlowBTMem,
 274                                       FeatureFastUAMem
 275                                     ]>;
 276 def : SilvermontProc<"silvermont">;
 277 def : SilvermontProc<"slm">; // Legacy alias.
 278
 279 // "Arrandale" along with corei3 and corei5
 280 class NehalemProc<string Name, list<SubtargetFeature> AdditionalFeatures>
 281     : ProcessorModel<Name, SandyBridgeModel, !listconcat([
 282                                                            FeatureSSE42,
 283                                                            FeatureCMPXCHG16B,
 284                                                            FeatureSlowBTMem,
 285                                                            FeatureFastUAMem,
 286                                                            FeaturePOPCNT
 287                                                          ],
 288                                                          AdditionalFeatures)>;
 289 def : NehalemProc<"nehalem", []>;
 290 def : NehalemProc<"corei7", [FeatureAES]>;
 291
 292 // Westmere is a similar machine to nehalem with some additional features.
 293 // Westmere is the corei3/i5/i7 path from nehalem to sandybridge
 294 class WestmereProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
 295                                     FeatureSSE42,
 296                                     FeatureCMPXCHG16B,
 297                                     FeatureSlowBTMem,
 298                                     FeatureFastUAMem,
 299                                     FeaturePOPCNT,
 300                                     FeatureAES,
 301                                     FeaturePCLMUL
 302                                   ]>;
 303 def : WestmereProc<"westmere">;
 304
 305 // SSE is not listed here since llvm treats AVX as a reimplementation of SSE,
 306 // rather than a superset.
 307 class SandyBridgeProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
 308                                        FeatureAVX,
 309                                        FeatureCMPXCHG16B,
 310                                        FeatureFastUAMem,
 311                                        FeatureSlowUAMem32,
 312                                        FeaturePOPCNT,
 313                                        FeatureAES,
 314                                        FeaturePCLMUL
 315                                      ]>;
 316 def : SandyBridgeProc<"sandybridge">;
 317 def : SandyBridgeProc<"corei7-avx">; // Legacy alias.
 318
 319 class IvyBridgeProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
 320                                      FeatureAVX,
 321                                      FeatureCMPXCHG16B,
 322                                      FeatureFastUAMem,
 323                                      FeatureSlowUAMem32,
 324                                      FeaturePOPCNT,
 325                                      FeatureAES,
 326                                      FeaturePCLMUL,
 327                                      FeatureRDRAND,
 328                                      FeatureF16C,
 329                                      FeatureFSGSBase
 330                                    ]>;
 331 def : IvyBridgeProc<"ivybridge">;
 332 def : IvyBridgeProc<"core-avx-i">; // Legacy alias.
 333
 334 class HaswellProc<string Name> : ProcessorModel<Name, HaswellModel, [
 335                                    FeatureAVX2,
 336                                    FeatureCMPXCHG16B,
 337                                    FeatureFastUAMem,
 338                                    FeaturePOPCNT,
 339                                    FeatureAES,
 340                                    FeaturePCLMUL,
 341                                    FeatureRDRAND,
 342                                    FeatureF16C,
 343                                    FeatureFSGSBase,
 344                                    FeatureMOVBE,
 345                                    FeatureLZCNT,
 346                                    FeatureBMI,
 347                                    FeatureBMI2,
 348                                    FeatureFMA,
 349                                    FeatureRTM,
 350                                    FeatureHLE,
 351                                    FeatureSlowIncDec
 352                                  ]>;
 353 def : HaswellProc<"haswell">;
 354 def : HaswellProc<"core-avx2">; // Legacy alias.
 355
 356 class BroadwellProc<string Name> : ProcessorModel<Name, HaswellModel, [
 357                                      FeatureAVX2,
 358                                      FeatureCMPXCHG16B,
 359                                      FeatureFastUAMem,
 360                                      FeaturePOPCNT,
 361                                      FeatureAES,
 362                                      FeaturePCLMUL,
 363                                      FeatureRDRAND,
 364                                      FeatureF16C,
 365                                      FeatureFSGSBase,
 366                                      FeatureMOVBE,
 367                                      FeatureLZCNT,
 368                                      FeatureBMI,
 369                                      FeatureBMI2,
 370                                      FeatureFMA,
 371                                      FeatureRTM,
 372                                      FeatureHLE,
 373                                      FeatureADX,
 374                                      FeatureRDSEED,
 375                                      FeatureSMAP,
 376                                      FeatureSlowIncDec
 377                                    ]>;
 378 def : BroadwellProc<"broadwell">;
 379
 380 // FIXME: define KNL model
 381 class KnightsLandingProc<string Name> : ProcessorModel<Name, HaswellModel,
 382                      [FeatureAVX512, FeatureERI, FeatureCDI, FeaturePFI,
 383                       FeatureCMPXCHG16B, FeatureFastUAMem, FeaturePOPCNT,
 384                       FeatureAES, FeaturePCLMUL, FeatureRDRAND, FeatureF16C,
 385                       FeatureFSGSBase, FeatureMOVBE, FeatureLZCNT, FeatureBMI,
 386                       FeatureBMI2, FeatureFMA, FeatureRTM, FeatureHLE,
 387                       FeatureSlowIncDec]>;
 388 def : KnightsLandingProc<"knl">;
 389
 390 // FIXME: define SKX model
 391 class SkylakeProc<string Name> : ProcessorModel<Name, HaswellModel,
 392                      [FeatureAVX512, FeatureCDI,
 393                       FeatureDQI, FeatureBWI, FeatureVLX,
 394                       FeatureCMPXCHG16B, FeatureFastUAMem, FeaturePOPCNT,
 395                       FeatureAES, FeaturePCLMUL, FeatureRDRAND, FeatureF16C,
 396                       FeatureFSGSBase, FeatureMOVBE, FeatureLZCNT, FeatureBMI,
 397                       FeatureBMI2, FeatureFMA, FeatureRTM, FeatureHLE,
 398                       FeatureSlowIncDec, FeatureSGX]>;
 399 def : SkylakeProc<"skylake">;
 400 def : SkylakeProc<"skx">; // Legacy alias.
 401
 402
 403 // AMD CPUs.
 404
 405 def : Proc<"k6",              [FeatureMMX]>;
 406 def : Proc<"k6-2",            [Feature3DNow]>;
 407 def : Proc<"k6-3",            [Feature3DNow]>;
 408 def : Proc<"athlon",          [Feature3DNowA, FeatureSlowBTMem,
 409                                FeatureSlowSHLD]>;
 410 def : Proc<"athlon-tbird",    [Feature3DNowA, FeatureSlowBTMem,
 411                                FeatureSlowSHLD]>;
 412 def : Proc<"athlon-4",        [FeatureSSE1,   Feature3DNowA, FeatureSlowBTMem,
 413                                FeatureSlowSHLD]>;
 414 def : Proc<"athlon-xp",       [FeatureSSE1,   Feature3DNowA, FeatureSlowBTMem,
 415                                FeatureSlowSHLD]>;
 416 def : Proc<"athlon-mp",       [FeatureSSE1,   Feature3DNowA, FeatureSlowBTMem,
 417                                FeatureSlowSHLD]>;
 418 def : Proc<"k8",              [FeatureSSE2,   Feature3DNowA, Feature64Bit,
 419                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 420 def : Proc<"opteron",         [FeatureSSE2,   Feature3DNowA, Feature64Bit,
 421                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 422 def : Proc<"athlon64",        [FeatureSSE2,   Feature3DNowA, Feature64Bit,
 423                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 424 def : Proc<"athlon-fx",       [FeatureSSE2,   Feature3DNowA, Feature64Bit,
 425                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 426 def : Proc<"k8-sse3",         [FeatureSSE3,   Feature3DNowA, FeatureCMPXCHG16B,
 427                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 428 def : Proc<"opteron-sse3",    [FeatureSSE3,   Feature3DNowA, FeatureCMPXCHG16B,
 429                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 430 def : Proc<"athlon64-sse3",   [FeatureSSE3,   Feature3DNowA, FeatureCMPXCHG16B,
 431                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 432 def : Proc<"amdfam10",        [FeatureSSE4A,
 433                                Feature3DNowA, FeatureCMPXCHG16B, FeatureLZCNT,
 434                                FeaturePOPCNT, FeatureSlowBTMem,
 435                                FeatureSlowSHLD]>;
 436 def : Proc<"barcelona",       [FeatureSSE4A,
 437                                Feature3DNowA, FeatureCMPXCHG16B, FeatureLZCNT,
 438                                FeaturePOPCNT, FeatureSlowBTMem,
 439                                FeatureSlowSHLD]>;
 440 // Bobcat
 441 def : Proc<"btver1",          [FeatureSSSE3, FeatureSSE4A, FeatureCMPXCHG16B,
 442                                FeaturePRFCHW, FeatureLZCNT, FeaturePOPCNT,
 443                                FeatureSlowSHLD]>;
 444
 445 // Jaguar
 446 def : ProcessorModel<"btver2", BtVer2Model,
 447                      [FeatureAVX, FeatureSSE4A, FeatureCMPXCHG16B,
 448                       FeaturePRFCHW, FeatureAES, FeaturePCLMUL,
 449                       FeatureBMI, FeatureF16C, FeatureMOVBE,
 450                       FeatureLZCNT, FeaturePOPCNT, FeatureFastUAMem,
 451                       FeatureSlowSHLD, FeatureUseSqrtEst, FeatureUseRecipEst]>;
 452
 453 // TODO: We should probably add 'FeatureFastUAMem' to all of the AMD chips.
 454
 455 // Bulldozer
 456 def : Proc<"bdver1",          [FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B,
 457                                FeatureAES, FeaturePRFCHW, FeaturePCLMUL,
 458                                FeatureAVX, FeatureSSE4A, FeatureLZCNT,
 459                                FeaturePOPCNT, FeatureSlowSHLD]>;
 460 // Piledriver
 461 def : Proc<"bdver2",          [FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B,
 462                                FeatureAES, FeaturePRFCHW, FeaturePCLMUL,
 463                                FeatureAVX, FeatureSSE4A, FeatureF16C,
 464                                FeatureLZCNT, FeaturePOPCNT, FeatureBMI,
 465                                FeatureTBM, FeatureFMA, FeatureSlowSHLD]>;
 466
 467 // Steamroller
 468 def : Proc<"bdver3",          [FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B,
 469                                FeatureAES, FeaturePRFCHW, FeaturePCLMUL,
 470                                FeatureAVX, FeatureSSE4A, FeatureF16C,
 471                                FeatureLZCNT, FeaturePOPCNT, FeatureBMI,
 472                                FeatureTBM, FeatureFMA, FeatureSlowSHLD,
 473                                FeatureFSGSBase]>;
 474
 475 // Excavator
 476 def : Proc<"bdver4",          [FeatureAVX2, FeatureXOP, FeatureFMA4,
 477                                FeatureCMPXCHG16B, FeatureAES, FeaturePRFCHW,
 478                                FeaturePCLMUL, FeatureF16C, FeatureLZCNT,
 479                                FeaturePOPCNT, FeatureBMI, FeatureBMI2,
 480                                FeatureTBM, FeatureFMA, FeatureSSE4A,
 481                                FeatureFSGSBase]>;
 482
 483 def : Proc<"geode",           [Feature3DNowA]>;
 484
 485 def : Proc<"winchip-c6",      [FeatureMMX]>;
 486 def : Proc<"winchip2",        [Feature3DNow]>;
 487 def : Proc<"c3",              [Feature3DNow]>;
 488 def : Proc<"c3-2",            [FeatureSSE1]>;
 489
 490 // We also provide a generic 64-bit specific x86 processor model which tries to
 491 // be good for modern chips without enabling instruction set encodings past the
 492 // basic SSE2 and 64-bit ones. It disables slow things from any mainstream and
 493 // modern 64-bit x86 chip, and enables features that are generally beneficial.
 494 //
 495 // We currently use the Sandy Bridge model as the default scheduling model as
 496 // we use it across Nehalem, Westmere, Sandy Bridge, and Ivy Bridge which
 497 // covers a huge swath of x86 processors. If there are specific scheduling
 498 // knobs which need to be tuned differently for AMD chips, we might consider
 499 // forming a common base for them.
 500 def : ProcessorModel<"x86-64", SandyBridgeModel,
 501                      [FeatureSSE2, Feature64Bit, FeatureSlowBTMem,
 502                       FeatureFastUAMem]>;
 503
 504 //===----------------------------------------------------------------------===//
 505 // Register File Description
 506 //===----------------------------------------------------------------------===//
 507
 508 include "X86RegisterInfo.td"
 509
 510 //===----------------------------------------------------------------------===//
 511 // Instruction Descriptions
 512 //===----------------------------------------------------------------------===//
 513
 514 include "X86InstrInfo.td"
 515
 516 def X86InstrInfo : InstrInfo;
 517
 518 //===----------------------------------------------------------------------===//
 519 // Calling Conventions
 520 //===----------------------------------------------------------------------===//
 521
 522 include "X86CallingConv.td"
 523
 524
 525 //===----------------------------------------------------------------------===//
 526 // Assembly Parser
 527 //===----------------------------------------------------------------------===//
 528
 529 def ATTAsmParser : AsmParser {
 530   string AsmParserClassName = "AsmParser";
 531 }
 532
 533 def ATTAsmParserVariant : AsmParserVariant {
 534   int Variant = 0;
 535
 536   // Variant name.
 537   string Name = "att";
 538
 539   // Discard comments in assembly strings.
 540   string CommentDelimiter = "#";
 541
 542   // Recognize hard coded registers.
 543   string RegisterPrefix = "%";
 544 }
 545
 546 def IntelAsmParserVariant : AsmParserVariant {
 547   int Variant = 1;
 548
 549   // Variant name.
 550   string Name = "intel";
 551
 552   // Discard comments in assembly strings.
 553   string CommentDelimiter = ";";
 554
 555   // Recognize hard coded registers.
 556   string RegisterPrefix = "";
 557 }
 558
 559 //===----------------------------------------------------------------------===//
 560 // Assembly Printers
 561 //===----------------------------------------------------------------------===//
 562
 563 // The X86 target supports two different syntaxes for emitting machine code.
 564 // This is controlled by the -x86-asm-syntax={att|intel}
 565 def ATTAsmWriter : AsmWriter {
 566   string AsmWriterClassName  = "ATTInstPrinter";
 567   int Variant = 0;
 568 }
 569 def IntelAsmWriter : AsmWriter {
 570   string AsmWriterClassName  = "IntelInstPrinter";
 571   int Variant = 1;
 572 }
 573
 574 def X86 : Target {
 575   // Information about the instructions...
 576   let InstructionSet = X86InstrInfo;
 577   let AssemblyParsers = [ATTAsmParser];
 578   let AssemblyParserVariants = [ATTAsmParserVariant, IntelAsmParserVariant];
 579   let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];
 580 }