lib/Target/X86/X86.td

   1 //===-- X86.td - Target definition file for the Intel X86 --*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This is a target description file for the Intel i386 architecture, referred
  11 // to here as the "X86" architecture.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 // Get the target-independent interfaces which we are implementing...
  16 //
  17 include "llvm/Target/Target.td"
  18
  19 //===----------------------------------------------------------------------===//
  20 // X86 Subtarget state
  21 //
  22
  23 def Mode64Bit : SubtargetFeature<"64bit-mode", "In64BitMode", "true",
  24                                   "64-bit mode (x86_64)">;
  25 def Mode32Bit : SubtargetFeature<"32bit-mode", "In32BitMode", "true",
  26                                   "32-bit mode (80386)">;
  27 def Mode16Bit : SubtargetFeature<"16bit-mode", "In16BitMode", "true",
  28                                   "16-bit mode (i8086)">;
  29
  30 //===----------------------------------------------------------------------===//
  31 // X86 Subtarget features
  32 //===----------------------------------------------------------------------===//
  33
  34 def FeatureCMOV    : SubtargetFeature<"cmov","HasCMov", "true",
  35                                       "Enable conditional move instructions">;
  36
  37 def FeaturePOPCNT   : SubtargetFeature<"popcnt", "HasPOPCNT", "true",
  38                                        "Support POPCNT instruction">;
  39
  40
  41 def FeatureMMX     : SubtargetFeature<"mmx","X86SSELevel", "MMX",
  42                                       "Enable MMX instructions">;
  43 def FeatureSSE1    : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
  44                                       "Enable SSE instructions",
  45                                       // SSE codegen depends on cmovs, and all
  46                                       // SSE1+ processors support them.
  47                                       [FeatureMMX, FeatureCMOV]>;
  48 def FeatureSSE2    : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",
  49                                       "Enable SSE2 instructions",
  50                                       [FeatureSSE1]>;
  51 def FeatureSSE3    : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
  52                                       "Enable SSE3 instructions",
  53                                       [FeatureSSE2]>;
  54 def FeatureSSSE3   : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3",
  55                                       "Enable SSSE3 instructions",
  56                                       [FeatureSSE3]>;
  57 def FeatureSSE41   : SubtargetFeature<"sse4.1", "X86SSELevel", "SSE41",
  58                                       "Enable SSE 4.1 instructions",
  59                                       [FeatureSSSE3]>;
  60 def FeatureSSE42   : SubtargetFeature<"sse4.2", "X86SSELevel", "SSE42",
  61                                       "Enable SSE 4.2 instructions",
  62                                       [FeatureSSE41]>;
  63 def Feature3DNow   : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
  64                                       "Enable 3DNow! instructions",
  65                                       [FeatureMMX]>;
  66 def Feature3DNowA  : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
  67                                       "Enable 3DNow! Athlon instructions",
  68                                       [Feature3DNow]>;
  69 // All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied
  70 // feature, because SSE2 can be disabled (e.g. for compiling OS kernels)
  71 // without disabling 64-bit mode.
  72 def Feature64Bit   : SubtargetFeature<"64bit", "HasX86_64", "true",
  73                                       "Support 64-bit instructions",
  74                                       [FeatureCMOV]>;
  75 def FeatureCMPXCHG16B : SubtargetFeature<"cx16", "HasCmpxchg16b", "true",
  76                                       "64-bit with cmpxchg16b",
  77                                       [Feature64Bit]>;
  78 def FeatureSlowBTMem : SubtargetFeature<"slow-bt-mem", "IsBTMemSlow", "true",
  79                                        "Bit testing of memory is slow">;
  80 def FeatureSlowSHLD : SubtargetFeature<"slow-shld", "IsSHLDSlow", "true",
  81                                        "SHLD instruction is slow">;
  82 // FIXME: This is a 16-byte (SSE/AVX) feature; we should rename it to make that
  83 // explicit. Also, it seems this would be the default state for most chips
  84 // going forward, so it would probably be better to negate the logic and
  85 // match the 32-byte "slow mem" feature below.
  86 def FeatureFastUAMem : SubtargetFeature<"fast-unaligned-mem",
  87                                         "IsUAMemFast", "true",
  88                                         "Fast unaligned memory access">;
  89 def FeatureSlowUAMem32 : SubtargetFeature<"slow-unaligned-mem-32",
  90                             "IsUAMem32Slow", "true",
  91                             "Slow unaligned 32-byte memory access">;
  92 def FeatureSSE4A   : SubtargetFeature<"sse4a", "HasSSE4A", "true",
  93                                       "Support SSE 4a instructions",
  94                                       [FeatureSSE3]>;
  95
  96 def FeatureAVX     : SubtargetFeature<"avx", "X86SSELevel", "AVX",
  97                                       "Enable AVX instructions",
  98                                       [FeatureSSE42]>;
  99 def FeatureAVX2    : SubtargetFeature<"avx2", "X86SSELevel", "AVX2",
 100                                       "Enable AVX2 instructions",
 101                                       [FeatureAVX]>;
 102 def FeatureAVX512   : SubtargetFeature<"avx512f", "X86SSELevel", "AVX512F",
 103                                       "Enable AVX-512 instructions",
 104                                       [FeatureAVX2]>;
 105 def FeatureERI      : SubtargetFeature<"avx512er", "HasERI", "true",
 106                       "Enable AVX-512 Exponential and Reciprocal Instructions",
 107                                       [FeatureAVX512]>;
 108 def FeatureCDI      : SubtargetFeature<"avx512cd", "HasCDI", "true",
 109                       "Enable AVX-512 Conflict Detection Instructions",
 110                                       [FeatureAVX512]>;
 111 def FeaturePFI      : SubtargetFeature<"avx512pf", "HasPFI", "true",
 112                       "Enable AVX-512 PreFetch Instructions",
 113                                       [FeatureAVX512]>;
 114 def FeatureDQI     : SubtargetFeature<"avx512dq", "HasDQI", "true",
 115                       "Enable AVX-512 Doubleword and Quadword Instructions",
 116                                       [FeatureAVX512]>;
 117 def FeatureBWI     : SubtargetFeature<"avx512bw", "HasBWI", "true",
 118                       "Enable AVX-512 Byte and Word Instructions",
 119                                       [FeatureAVX512]>;
 120 def FeatureVLX     : SubtargetFeature<"avx512vl", "HasVLX", "true",
 121                       "Enable AVX-512 Vector Length eXtensions",
 122                                       [FeatureAVX512]>;
 123 def FeaturePCLMUL  : SubtargetFeature<"pclmul", "HasPCLMUL", "true",
 124                          "Enable packed carry-less multiplication instructions",
 125                                [FeatureSSE2]>;
 126 def FeatureFMA     : SubtargetFeature<"fma", "HasFMA", "true",
 127                                       "Enable three-operand fused multiple-add",
 128                                       [FeatureAVX]>;
 129 def FeatureFMA4    : SubtargetFeature<"fma4", "HasFMA4", "true",
 130                                       "Enable four-operand fused multiple-add",
 131                                       [FeatureAVX, FeatureSSE4A]>;
 132 def FeatureXOP     : SubtargetFeature<"xop", "HasXOP", "true",
 133                                       "Enable XOP instructions",
 134                                       [FeatureFMA4]>;
 135 def FeatureSSEUnalignedMem : SubtargetFeature<"sse-unaligned-mem",
 136                                           "HasSSEUnalignedMem", "true",
 137                       "Allow unaligned memory operands with SSE instructions">;
 138 def FeatureAES     : SubtargetFeature<"aes", "HasAES", "true",
 139                                       "Enable AES instructions",
 140                                       [FeatureSSE2]>;
 141 def FeatureTBM     : SubtargetFeature<"tbm", "HasTBM", "true",
 142                                       "Enable TBM instructions">;
 143 def FeatureMOVBE   : SubtargetFeature<"movbe", "HasMOVBE", "true",
 144                                       "Support MOVBE instruction">;
 145 def FeatureRDRAND  : SubtargetFeature<"rdrnd", "HasRDRAND", "true",
 146                                       "Support RDRAND instruction">;
 147 def FeatureF16C    : SubtargetFeature<"f16c", "HasF16C", "true",
 148                        "Support 16-bit floating point conversion instructions",
 149                        [FeatureAVX]>;
 150 def FeatureFSGSBase : SubtargetFeature<"fsgsbase", "HasFSGSBase", "true",
 151                                        "Support FS/GS Base instructions">;
 152 def FeatureLZCNT   : SubtargetFeature<"lzcnt", "HasLZCNT", "true",
 153                                       "Support LZCNT instruction">;
 154 def FeatureBMI     : SubtargetFeature<"bmi", "HasBMI", "true",
 155                                       "Support BMI instructions">;
 156 def FeatureBMI2    : SubtargetFeature<"bmi2", "HasBMI2", "true",
 157                                       "Support BMI2 instructions">;
 158 def FeatureRTM     : SubtargetFeature<"rtm", "HasRTM", "true",
 159                                       "Support RTM instructions">;
 160 def FeatureHLE     : SubtargetFeature<"hle", "HasHLE", "true",
 161                                       "Support HLE">;
 162 def FeatureADX     : SubtargetFeature<"adx", "HasADX", "true",
 163                                       "Support ADX instructions">;
 164 def FeatureSHA     : SubtargetFeature<"sha", "HasSHA", "true",
 165                                       "Enable SHA instructions",
 166                                       [FeatureSSE2]>;
 167 def FeaturePRFCHW  : SubtargetFeature<"prfchw", "HasPRFCHW", "true",
 168                                       "Support PRFCHW instructions">;
 169 def FeatureRDSEED  : SubtargetFeature<"rdseed", "HasRDSEED", "true",
 170                                       "Support RDSEED instruction">;
 171 def FeatureLeaForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true",
 172                                      "Use LEA for adjusting the stack pointer">;
 173 def FeatureSlowDivide32 : SubtargetFeature<"idivl-to-divb",
 174                                      "HasSlowDivide32", "true",
 175                                      "Use 8-bit divide for positive values less than 256">;
 176 def FeatureSlowDivide64 : SubtargetFeature<"idivq-to-divw",
 177                                      "HasSlowDivide64", "true",
 178                                      "Use 16-bit divide for positive values less than 65536">;
 179 def FeaturePadShortFunctions : SubtargetFeature<"pad-short-functions",
 180                                      "PadShortFunctions", "true",
 181                                      "Pad short functions">;
 182 def FeatureCallRegIndirect : SubtargetFeature<"call-reg-indirect",
 183                                      "CallRegIndirect", "true",
 184                                      "Call register indirect">;
 185 def FeatureLEAUsesAG : SubtargetFeature<"lea-uses-ag", "LEAUsesAG", "true",
 186                                    "LEA instruction needs inputs at AG stage">;
 187 def FeatureSlowLEA : SubtargetFeature<"slow-lea", "SlowLEA", "true",
 188                                    "LEA instruction with certain arguments is slow">;
 189 def FeatureSlowIncDec : SubtargetFeature<"slow-incdec", "SlowIncDec", "true",
 190                                    "INC and DEC instructions are slower than ADD and SUB">;
 191 def FeatureUseSqrtEst : SubtargetFeature<"use-sqrt-est", "UseSqrtEst", "true",
 192                             "Use RSQRT* to optimize square root calculations">;
 193 def FeatureUseRecipEst : SubtargetFeature<"use-recip-est", "UseReciprocalEst",
 194                           "true", "Use RCP* to optimize division calculations">;
 195
 196 //===----------------------------------------------------------------------===//
 197 // X86 processors supported.
 198 //===----------------------------------------------------------------------===//
 199
 200 include "X86Schedule.td"
 201
 202 def ProcIntelAtom : SubtargetFeature<"atom", "X86ProcFamily", "IntelAtom",
 203                     "Intel Atom processors">;
 204 def ProcIntelSLM  : SubtargetFeature<"slm", "X86ProcFamily", "IntelSLM",
 205                     "Intel Silvermont processors">;
 206
 207 class Proc<string Name, list<SubtargetFeature> Features>
 208  : ProcessorModel<Name, GenericModel, Features>;
 209
 210 def : Proc<"generic",         []>;
 211 def : Proc<"i386",            []>;
 212 def : Proc<"i486",            []>;
 213 def : Proc<"i586",            []>;
 214 def : Proc<"pentium",         []>;
 215 def : Proc<"pentium-mmx",     [FeatureMMX]>;
 216 def : Proc<"i686",            []>;
 217 def : Proc<"pentiumpro",      [FeatureCMOV]>;
 218 def : Proc<"pentium2",        [FeatureMMX, FeatureCMOV]>;
 219 def : Proc<"pentium3",        [FeatureSSE1]>;
 220 def : Proc<"pentium3m",       [FeatureSSE1, FeatureSlowBTMem]>;
 221 def : Proc<"pentium-m",       [FeatureSSE2, FeatureSlowBTMem]>;
 222 def : Proc<"pentium4",        [FeatureSSE2]>;
 223 def : Proc<"pentium4m",       [FeatureSSE2, FeatureSlowBTMem]>;
 224
 225 // Intel Core Duo.
 226 def : ProcessorModel<"yonah", SandyBridgeModel,
 227                      [FeatureSSE3, FeatureSlowBTMem]>;
 228
 229 // NetBurst.
 230 def : Proc<"prescott", [FeatureSSE3, FeatureSlowBTMem]>;
 231 def : Proc<"nocona",   [FeatureSSE3, FeatureCMPXCHG16B, FeatureSlowBTMem]>;
 232
 233 // Intel Core 2 Solo/Duo.
 234 def : ProcessorModel<"core2", SandyBridgeModel,
 235                      [FeatureSSSE3, FeatureCMPXCHG16B, FeatureSlowBTMem]>;
 236 def : ProcessorModel<"penryn", SandyBridgeModel,
 237                      [FeatureSSE41, FeatureCMPXCHG16B, FeatureSlowBTMem]>;
 238
 239 // Atom CPUs.
 240 class BonnellProc<string Name> : ProcessorModel<Name, AtomModel, [
 241                                    ProcIntelAtom,
 242                                    FeatureSSSE3,
 243                                    FeatureCMPXCHG16B,
 244                                    FeatureMOVBE,
 245                                    FeatureSlowBTMem,
 246                                    FeatureLeaForSP,
 247                                    FeatureSlowDivide32,
 248                                    FeatureSlowDivide64,
 249                                    FeatureCallRegIndirect,
 250                                    FeatureLEAUsesAG,
 251                                    FeaturePadShortFunctions
 252                                  ]>;
 253 def : BonnellProc<"bonnell">;
 254 def : BonnellProc<"atom">; // Pin the generic name to the baseline.
 255
 256 class SilvermontProc<string Name> : ProcessorModel<Name, SLMModel, [
 257                                       ProcIntelSLM,
 258                                       FeatureSSE42,
 259                                       FeatureCMPXCHG16B,
 260                                       FeatureMOVBE,
 261                                       FeaturePOPCNT,
 262                                       FeaturePCLMUL,
 263                                       FeatureAES,
 264                                       FeatureSlowDivide64,
 265                                       FeatureCallRegIndirect,
 266                                       FeaturePRFCHW,
 267                                       FeatureSlowLEA,
 268                                       FeatureSlowIncDec,
 269                                       FeatureSlowBTMem,
 270                                       FeatureFastUAMem
 271                                     ]>;
 272 def : SilvermontProc<"silvermont">;
 273 def : SilvermontProc<"slm">; // Legacy alias.
 274
 275 // "Arrandale" along with corei3 and corei5
 276 class NehalemProc<string Name, list<SubtargetFeature> AdditionalFeatures>
 277     : ProcessorModel<Name, SandyBridgeModel, !listconcat([
 278                                                            FeatureSSE42,
 279                                                            FeatureCMPXCHG16B,
 280                                                            FeatureSlowBTMem,
 281                                                            FeatureFastUAMem,
 282                                                            FeaturePOPCNT
 283                                                          ],
 284                                                          AdditionalFeatures)>;
 285 def : NehalemProc<"nehalem", []>;
 286 def : NehalemProc<"corei7", [FeatureAES]>;
 287
 288 // Westmere is a similar machine to nehalem with some additional features.
 289 // Westmere is the corei3/i5/i7 path from nehalem to sandybridge
 290 class WestmereProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
 291                                     FeatureSSE42,
 292                                     FeatureCMPXCHG16B,
 293                                     FeatureSlowBTMem,
 294                                     FeatureFastUAMem,
 295                                     FeaturePOPCNT,
 296                                     FeatureAES,
 297                                     FeaturePCLMUL
 298                                   ]>;
 299 def : WestmereProc<"westmere">;
 300
 301 // SSE is not listed here since llvm treats AVX as a reimplementation of SSE,
 302 // rather than a superset.
 303 class SandyBridgeProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
 304                                        FeatureAVX,
 305                                        FeatureCMPXCHG16B,
 306                                        FeatureFastUAMem,
 307                                        FeatureSlowUAMem32,
 308                                        FeaturePOPCNT,
 309                                        FeatureAES,
 310                                        FeaturePCLMUL
 311                                      ]>;
 312 def : SandyBridgeProc<"sandybridge">;
 313 def : SandyBridgeProc<"corei7-avx">; // Legacy alias.
 314
 315 class IvyBridgeProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
 316                                      FeatureAVX,
 317                                      FeatureCMPXCHG16B,
 318                                      FeatureFastUAMem,
 319                                      FeatureSlowUAMem32,
 320                                      FeaturePOPCNT,
 321                                      FeatureAES,
 322                                      FeaturePCLMUL,
 323                                      FeatureRDRAND,
 324                                      FeatureF16C,
 325                                      FeatureFSGSBase
 326                                    ]>;
 327 def : IvyBridgeProc<"ivybridge">;
 328 def : IvyBridgeProc<"core-avx-i">; // Legacy alias.
 329
 330 class HaswellProc<string Name> : ProcessorModel<Name, HaswellModel, [
 331                                    FeatureAVX2,
 332                                    FeatureCMPXCHG16B,
 333                                    FeatureFastUAMem,
 334                                    FeaturePOPCNT,
 335                                    FeatureAES,
 336                                    FeaturePCLMUL,
 337                                    FeatureRDRAND,
 338                                    FeatureF16C,
 339                                    FeatureFSGSBase,
 340                                    FeatureMOVBE,
 341                                    FeatureLZCNT,
 342                                    FeatureBMI,
 343                                    FeatureBMI2,
 344                                    FeatureFMA,
 345                                    FeatureRTM,
 346                                    FeatureHLE,
 347                                    FeatureSlowIncDec
 348                                  ]>;
 349 def : HaswellProc<"haswell">;
 350 def : HaswellProc<"core-avx2">; // Legacy alias.
 351
 352 class BroadwellProc<string Name> : ProcessorModel<Name, HaswellModel, [
 353                                      FeatureAVX2,
 354                                      FeatureCMPXCHG16B,
 355                                      FeatureFastUAMem,
 356                                      FeaturePOPCNT,
 357                                      FeatureAES,
 358                                      FeaturePCLMUL,
 359                                      FeatureRDRAND,
 360                                      FeatureF16C,
 361                                      FeatureFSGSBase,
 362                                      FeatureMOVBE,
 363                                      FeatureLZCNT,
 364                                      FeatureBMI,
 365                                      FeatureBMI2,
 366                                      FeatureFMA,
 367                                      FeatureRTM,
 368                                      FeatureHLE,
 369                                      FeatureADX,
 370                                      FeatureRDSEED,
 371                                      FeatureSlowIncDec
 372                                    ]>;
 373 def : BroadwellProc<"broadwell">;
 374
 375 // FIXME: define KNL model
 376 class KnightsLandingProc<string Name> : ProcessorModel<Name, HaswellModel,
 377                      [FeatureAVX512, FeatureERI, FeatureCDI, FeaturePFI,
 378                       FeatureCMPXCHG16B, FeatureFastUAMem, FeaturePOPCNT,
 379                       FeatureAES, FeaturePCLMUL, FeatureRDRAND, FeatureF16C,
 380                       FeatureFSGSBase, FeatureMOVBE, FeatureLZCNT, FeatureBMI,
 381                       FeatureBMI2, FeatureFMA, FeatureRTM, FeatureHLE,
 382                       FeatureSlowIncDec]>;
 383 def : KnightsLandingProc<"knl">;
 384
 385 // FIXME: define SKX model
 386 class SkylakeProc<string Name> : ProcessorModel<Name, HaswellModel,
 387                      [FeatureAVX512, FeatureCDI,
 388                       FeatureDQI, FeatureBWI, FeatureVLX,
 389                       FeatureCMPXCHG16B, FeatureFastUAMem, FeaturePOPCNT,
 390                       FeatureAES, FeaturePCLMUL, FeatureRDRAND, FeatureF16C,
 391                       FeatureFSGSBase, FeatureMOVBE, FeatureLZCNT, FeatureBMI,
 392                       FeatureBMI2, FeatureFMA, FeatureRTM, FeatureHLE,
 393                       FeatureSlowIncDec]>;
 394 def : SkylakeProc<"skylake">;
 395 def : SkylakeProc<"skx">; // Legacy alias.
 396
 397
 398 // AMD CPUs.
 399
 400 def : Proc<"k6",              [FeatureMMX]>;
 401 def : Proc<"k6-2",            [Feature3DNow]>;
 402 def : Proc<"k6-3",            [Feature3DNow]>;
 403 def : Proc<"athlon",          [Feature3DNowA, FeatureSlowBTMem,
 404                                FeatureSlowSHLD]>;
 405 def : Proc<"athlon-tbird",    [Feature3DNowA, FeatureSlowBTMem,
 406                                FeatureSlowSHLD]>;
 407 def : Proc<"athlon-4",        [FeatureSSE1,   Feature3DNowA, FeatureSlowBTMem,
 408                                FeatureSlowSHLD]>;
 409 def : Proc<"athlon-xp",       [FeatureSSE1,   Feature3DNowA, FeatureSlowBTMem,
 410                                FeatureSlowSHLD]>;
 411 def : Proc<"athlon-mp",       [FeatureSSE1,   Feature3DNowA, FeatureSlowBTMem,
 412                                FeatureSlowSHLD]>;
 413 def : Proc<"k8",              [FeatureSSE2,   Feature3DNowA, Feature64Bit,
 414                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 415 def : Proc<"opteron",         [FeatureSSE2,   Feature3DNowA, Feature64Bit,
 416                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 417 def : Proc<"athlon64",        [FeatureSSE2,   Feature3DNowA, Feature64Bit,
 418                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 419 def : Proc<"athlon-fx",       [FeatureSSE2,   Feature3DNowA, Feature64Bit,
 420                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 421 def : Proc<"k8-sse3",         [FeatureSSE3,   Feature3DNowA, FeatureCMPXCHG16B,
 422                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 423 def : Proc<"opteron-sse3",    [FeatureSSE3,   Feature3DNowA, FeatureCMPXCHG16B,
 424                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 425 def : Proc<"athlon64-sse3",   [FeatureSSE3,   Feature3DNowA, FeatureCMPXCHG16B,
 426                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 427 def : Proc<"amdfam10",        [FeatureSSE4A,
 428                                Feature3DNowA, FeatureCMPXCHG16B, FeatureLZCNT,
 429                                FeaturePOPCNT, FeatureSlowBTMem,
 430                                FeatureSlowSHLD]>;
 431 def : Proc<"barcelona",       [FeatureSSE4A,
 432                                Feature3DNowA, FeatureCMPXCHG16B, FeatureLZCNT,
 433                                FeaturePOPCNT, FeatureSlowBTMem,
 434                                FeatureSlowSHLD]>;
 435 // Bobcat
 436 def : Proc<"btver1",          [FeatureSSSE3, FeatureSSE4A, FeatureCMPXCHG16B,
 437                                FeaturePRFCHW, FeatureLZCNT, FeaturePOPCNT,
 438                                FeatureSlowSHLD]>;
 439
 440 // Jaguar
 441 def : ProcessorModel<"btver2", BtVer2Model,
 442                      [FeatureAVX, FeatureSSE4A, FeatureCMPXCHG16B,
 443                       FeaturePRFCHW, FeatureAES, FeaturePCLMUL,
 444                       FeatureBMI, FeatureF16C, FeatureMOVBE,
 445                       FeatureLZCNT, FeaturePOPCNT, FeatureFastUAMem,
 446                       FeatureSlowSHLD, FeatureUseSqrtEst, FeatureUseRecipEst]>;
 447
 448 // TODO: We should probably add 'FeatureFastUAMem' to all of the AMD chips.
 449
 450 // Bulldozer
 451 def : Proc<"bdver1",          [FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B,
 452                                FeatureAES, FeaturePRFCHW, FeaturePCLMUL,
 453                                FeatureAVX, FeatureSSE4A, FeatureLZCNT,
 454                                FeaturePOPCNT, FeatureSlowSHLD]>;
 455 // Piledriver
 456 def : Proc<"bdver2",          [FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B,
 457                                FeatureAES, FeaturePRFCHW, FeaturePCLMUL,
 458                                FeatureAVX, FeatureSSE4A, FeatureF16C,
 459                                FeatureLZCNT, FeaturePOPCNT, FeatureBMI,
 460                                FeatureTBM, FeatureFMA, FeatureSlowSHLD]>;
 461
 462 // Steamroller
 463 def : Proc<"bdver3",          [FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B,
 464                                FeatureAES, FeaturePRFCHW, FeaturePCLMUL,
 465                                FeatureAVX, FeatureSSE4A, FeatureF16C,
 466                                FeatureLZCNT, FeaturePOPCNT, FeatureBMI,
 467                                FeatureTBM, FeatureFMA, FeatureSlowSHLD,
 468                                FeatureFSGSBase]>;
 469
 470 // Excavator
 471 def : Proc<"bdver4",          [FeatureAVX2, FeatureXOP, FeatureFMA4,
 472                                FeatureCMPXCHG16B, FeatureAES, FeaturePRFCHW,
 473                                FeaturePCLMUL, FeatureF16C, FeatureLZCNT,
 474                                FeaturePOPCNT, FeatureBMI, FeatureBMI2,
 475                                FeatureTBM, FeatureFMA, FeatureSSE4A,
 476                                FeatureFSGSBase]>;
 477
 478 def : Proc<"geode",           [Feature3DNowA]>;
 479
 480 def : Proc<"winchip-c6",      [FeatureMMX]>;
 481 def : Proc<"winchip2",        [Feature3DNow]>;
 482 def : Proc<"c3",              [Feature3DNow]>;
 483 def : Proc<"c3-2",            [FeatureSSE1]>;
 484
 485 // We also provide a generic 64-bit specific x86 processor model which tries to
 486 // be good for modern chips without enabling instruction set encodings past the
 487 // basic SSE2 and 64-bit ones. It disables slow things from any mainstream and
 488 // modern 64-bit x86 chip, and enables features that are generally beneficial.
 489 //
 490 // We currently use the Sandy Bridge model as the default scheduling model as
 491 // we use it across Nehalem, Westmere, Sandy Bridge, and Ivy Bridge which
 492 // covers a huge swath of x86 processors. If there are specific scheduling
 493 // knobs which need to be tuned differently for AMD chips, we might consider
 494 // forming a common base for them.
 495 def : ProcessorModel<"x86-64", SandyBridgeModel,
 496                      [FeatureSSE2, Feature64Bit, FeatureSlowBTMem,
 497                       FeatureFastUAMem]>;
 498
 499 //===----------------------------------------------------------------------===//
 500 // Register File Description
 501 //===----------------------------------------------------------------------===//
 502
 503 include "X86RegisterInfo.td"
 504
 505 //===----------------------------------------------------------------------===//
 506 // Instruction Descriptions
 507 //===----------------------------------------------------------------------===//
 508
 509 include "X86InstrInfo.td"
 510
 511 def X86InstrInfo : InstrInfo;
 512
 513 //===----------------------------------------------------------------------===//
 514 // Calling Conventions
 515 //===----------------------------------------------------------------------===//
 516
 517 include "X86CallingConv.td"
 518
 519
 520 //===----------------------------------------------------------------------===//
 521 // Assembly Parser
 522 //===----------------------------------------------------------------------===//
 523
 524 def ATTAsmParser : AsmParser {
 525   string AsmParserClassName = "AsmParser";
 526 }
 527
 528 def ATTAsmParserVariant : AsmParserVariant {
 529   int Variant = 0;
 530
 531   // Variant name.
 532   string Name = "att";
 533
 534   // Discard comments in assembly strings.
 535   string CommentDelimiter = "#";
 536
 537   // Recognize hard coded registers.
 538   string RegisterPrefix = "%";
 539 }
 540
 541 def IntelAsmParserVariant : AsmParserVariant {
 542   int Variant = 1;
 543
 544   // Variant name.
 545   string Name = "intel";
 546
 547   // Discard comments in assembly strings.
 548   string CommentDelimiter = ";";
 549
 550   // Recognize hard coded registers.
 551   string RegisterPrefix = "";
 552 }
 553
 554 //===----------------------------------------------------------------------===//
 555 // Assembly Printers
 556 //===----------------------------------------------------------------------===//
 557
 558 // The X86 target supports two different syntaxes for emitting machine code.
 559 // This is controlled by the -x86-asm-syntax={att|intel}
 560 def ATTAsmWriter : AsmWriter {
 561   string AsmWriterClassName  = "ATTInstPrinter";
 562   int Variant = 0;
 563 }
 564 def IntelAsmWriter : AsmWriter {
 565   string AsmWriterClassName  = "IntelInstPrinter";
 566   int Variant = 1;
 567 }
 568
 569 def X86 : Target {
 570   // Information about the instructions...
 571   let InstructionSet = X86InstrInfo;
 572   let AssemblyParsers = [ATTAsmParser];
 573   let AssemblyParserVariants = [ATTAsmParserVariant, IntelAsmParserVariant];
 574   let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];
 575 }