lib/Target/X86/X86.td

   1 //===-- X86.td - Target definition file for the Intel X86 --*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This is a target description file for the Intel i386 architecture, referred
  11 // to here as the "X86" architecture.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 // Get the target-independent interfaces which we are implementing...
  16 //
  17 include "llvm/Target/Target.td"
  18
  19 //===----------------------------------------------------------------------===//
  20 // X86 Subtarget state
  21 //
  22
  23 def Mode64Bit : SubtargetFeature<"64bit-mode", "In64BitMode", "true",
  24                                   "64-bit mode (x86_64)">;
  25 def Mode32Bit : SubtargetFeature<"32bit-mode", "In32BitMode", "true",
  26                                   "32-bit mode (80386)">;
  27 def Mode16Bit : SubtargetFeature<"16bit-mode", "In16BitMode", "true",
  28                                   "16-bit mode (i8086)">;
  29
  30 //===----------------------------------------------------------------------===//
  31 // X86 Subtarget features
  32 //===----------------------------------------------------------------------===//
  33
  34 def FeatureCMOV    : SubtargetFeature<"cmov","HasCMov", "true",
  35                                       "Enable conditional move instructions">;
  36
  37 def FeaturePOPCNT   : SubtargetFeature<"popcnt", "HasPOPCNT", "true",
  38                                        "Support POPCNT instruction">;
  39
  40
  41 def FeatureMMX     : SubtargetFeature<"mmx","X86SSELevel", "MMX",
  42                                       "Enable MMX instructions">;
  43 def FeatureSSE1    : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
  44                                       "Enable SSE instructions",
  45                                       // SSE codegen depends on cmovs, and all
  46                                       // SSE1+ processors support them.
  47                                       [FeatureMMX, FeatureCMOV]>;
  48 def FeatureSSE2    : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",
  49                                       "Enable SSE2 instructions",
  50                                       [FeatureSSE1]>;
  51 def FeatureSSE3    : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
  52                                       "Enable SSE3 instructions",
  53                                       [FeatureSSE2]>;
  54 def FeatureSSSE3   : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3",
  55                                       "Enable SSSE3 instructions",
  56                                       [FeatureSSE3]>;
  57 def FeatureSSE41   : SubtargetFeature<"sse4.1", "X86SSELevel", "SSE41",
  58                                       "Enable SSE 4.1 instructions",
  59                                       [FeatureSSSE3]>;
  60 def FeatureSSE42   : SubtargetFeature<"sse4.2", "X86SSELevel", "SSE42",
  61                                       "Enable SSE 4.2 instructions",
  62                                       [FeatureSSE41]>;
  63 def Feature3DNow   : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
  64                                       "Enable 3DNow! instructions",
  65                                       [FeatureMMX]>;
  66 def Feature3DNowA  : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
  67                                       "Enable 3DNow! Athlon instructions",
  68                                       [Feature3DNow]>;
  69 // All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied
  70 // feature, because SSE2 can be disabled (e.g. for compiling OS kernels)
  71 // without disabling 64-bit mode.
  72 def Feature64Bit   : SubtargetFeature<"64bit", "HasX86_64", "true",
  73                                       "Support 64-bit instructions",
  74                                       [FeatureCMOV]>;
  75 def FeatureCMPXCHG16B : SubtargetFeature<"cx16", "HasCmpxchg16b", "true",
  76                                       "64-bit with cmpxchg16b",
  77                                       [Feature64Bit]>;
  78 def FeatureSlowBTMem : SubtargetFeature<"slow-bt-mem", "IsBTMemSlow", "true",
  79                                        "Bit testing of memory is slow">;
  80 def FeatureSlowSHLD : SubtargetFeature<"slow-shld", "IsSHLDSlow", "true",
  81                                        "SHLD instruction is slow">;
  82 // FIXME: This is a 16-byte (SSE/AVX) feature; we should rename it to make that
  83 // explicit. Also, it seems this would be the default state for most chips
  84 // going forward, so it would probably be better to negate the logic and
  85 // match the 32-byte "slow mem" feature below.
  86 def FeatureFastUAMem : SubtargetFeature<"fast-unaligned-mem",
  87                                         "IsUAMemFast", "true",
  88                                         "Fast unaligned memory access">;
  89 def FeatureSlowUAMem32 : SubtargetFeature<"slow-unaligned-mem-32",
  90                             "IsUAMem32Slow", "true",
  91                             "Slow unaligned 32-byte memory access">;
  92 def FeatureSSE4A   : SubtargetFeature<"sse4a", "HasSSE4A", "true",
  93                                       "Support SSE 4a instructions",
  94                                       [FeatureSSE3]>;
  95
  96 def FeatureAVX     : SubtargetFeature<"avx", "X86SSELevel", "AVX",
  97                                       "Enable AVX instructions",
  98                                       [FeatureSSE42]>;
  99 def FeatureAVX2    : SubtargetFeature<"avx2", "X86SSELevel", "AVX2",
 100                                       "Enable AVX2 instructions",
 101                                       [FeatureAVX]>;
 102 def FeatureAVX512   : SubtargetFeature<"avx512f", "X86SSELevel", "AVX512F",
 103                                       "Enable AVX-512 instructions",
 104                                       [FeatureAVX2]>;
 105 def FeatureERI      : SubtargetFeature<"avx512er", "HasERI", "true",
 106                       "Enable AVX-512 Exponential and Reciprocal Instructions",
 107                                       [FeatureAVX512]>;
 108 def FeatureCDI      : SubtargetFeature<"avx512cd", "HasCDI", "true",
 109                       "Enable AVX-512 Conflict Detection Instructions",
 110                                       [FeatureAVX512]>;
 111 def FeaturePFI      : SubtargetFeature<"avx512pf", "HasPFI", "true",
 112                       "Enable AVX-512 PreFetch Instructions",
 113                                       [FeatureAVX512]>;
 114 def FeatureDQI     : SubtargetFeature<"avx512dq", "HasDQI", "true",
 115                       "Enable AVX-512 Doubleword and Quadword Instructions",
 116                                       [FeatureAVX512]>;
 117 def FeatureBWI     : SubtargetFeature<"avx512bw", "HasBWI", "true",
 118                       "Enable AVX-512 Byte and Word Instructions",
 119                                       [FeatureAVX512]>;
 120 def FeatureVLX     : SubtargetFeature<"avx512vl", "HasVLX", "true",
 121                       "Enable AVX-512 Vector Length eXtensions",
 122                                       [FeatureAVX512]>;
 123 def FeaturePCLMUL  : SubtargetFeature<"pclmul", "HasPCLMUL", "true",
 124                          "Enable packed carry-less multiplication instructions",
 125                                [FeatureSSE2]>;
 126 def FeatureFMA     : SubtargetFeature<"fma", "HasFMA", "true",
 127                                       "Enable three-operand fused multiple-add",
 128                                       [FeatureAVX]>;
 129 def FeatureFMA4    : SubtargetFeature<"fma4", "HasFMA4", "true",
 130                                       "Enable four-operand fused multiple-add",
 131                                       [FeatureAVX, FeatureSSE4A]>;
 132 def FeatureXOP     : SubtargetFeature<"xop", "HasXOP", "true",
 133                                       "Enable XOP instructions",
 134                                       [FeatureFMA4]>;
 135 def FeatureSSEUnalignedMem : SubtargetFeature<"sse-unaligned-mem",
 136                                           "HasSSEUnalignedMem", "true",
 137                       "Allow unaligned memory operands with SSE instructions">;
 138 def FeatureAES     : SubtargetFeature<"aes", "HasAES", "true",
 139                                       "Enable AES instructions",
 140                                       [FeatureSSE2]>;
 141 def FeatureTBM     : SubtargetFeature<"tbm", "HasTBM", "true",
 142                                       "Enable TBM instructions">;
 143 def FeatureMOVBE   : SubtargetFeature<"movbe", "HasMOVBE", "true",
 144                                       "Support MOVBE instruction">;
 145 def FeatureRDRAND  : SubtargetFeature<"rdrnd", "HasRDRAND", "true",
 146                                       "Support RDRAND instruction">;
 147 def FeatureF16C    : SubtargetFeature<"f16c", "HasF16C", "true",
 148                        "Support 16-bit floating point conversion instructions",
 149                        [FeatureAVX]>;
 150 def FeatureFSGSBase : SubtargetFeature<"fsgsbase", "HasFSGSBase", "true",
 151                                        "Support FS/GS Base instructions">;
 152 def FeatureLZCNT   : SubtargetFeature<"lzcnt", "HasLZCNT", "true",
 153                                       "Support LZCNT instruction">;
 154 def FeatureBMI     : SubtargetFeature<"bmi", "HasBMI", "true",
 155                                       "Support BMI instructions">;
 156 def FeatureBMI2    : SubtargetFeature<"bmi2", "HasBMI2", "true",
 157                                       "Support BMI2 instructions">;
 158 def FeatureRTM     : SubtargetFeature<"rtm", "HasRTM", "true",
 159                                       "Support RTM instructions">;
 160 def FeatureHLE     : SubtargetFeature<"hle", "HasHLE", "true",
 161                                       "Support HLE">;
 162 def FeatureADX     : SubtargetFeature<"adx", "HasADX", "true",
 163                                       "Support ADX instructions">;
 164 def FeatureSHA     : SubtargetFeature<"sha", "HasSHA", "true",
 165                                       "Enable SHA instructions",
 166                                       [FeatureSSE2]>;
 167 def FeaturePRFCHW  : SubtargetFeature<"prfchw", "HasPRFCHW", "true",
 168                                       "Support PRFCHW instructions">;
 169 def FeatureRDSEED  : SubtargetFeature<"rdseed", "HasRDSEED", "true",
 170                                       "Support RDSEED instruction">;
 171 def FeatureLeaForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true",
 172                                      "Use LEA for adjusting the stack pointer">;
 173 def FeatureSlowDivide32 : SubtargetFeature<"idivl-to-divb",
 174                                      "HasSlowDivide32", "true",
 175                                      "Use 8-bit divide for positive values less than 256">;
 176 def FeatureSlowDivide64 : SubtargetFeature<"idivq-to-divw",
 177                                      "HasSlowDivide64", "true",
 178                                      "Use 16-bit divide for positive values less than 65536">;
 179 def FeaturePadShortFunctions : SubtargetFeature<"pad-short-functions",
 180                                      "PadShortFunctions", "true",
 181                                      "Pad short functions">;
 182 def FeatureCallRegIndirect : SubtargetFeature<"call-reg-indirect",
 183                                      "CallRegIndirect", "true",
 184                                      "Call register indirect">;
 185 def FeatureLEAUsesAG : SubtargetFeature<"lea-uses-ag", "LEAUsesAG", "true",
 186                                    "LEA instruction needs inputs at AG stage">;
 187 def FeatureSlowLEA : SubtargetFeature<"slow-lea", "SlowLEA", "true",
 188                                    "LEA instruction with certain arguments is slow">;
 189 def FeatureSlowIncDec : SubtargetFeature<"slow-incdec", "SlowIncDec", "true",
 190                                    "INC and DEC instructions are slower than ADD and SUB">;
 191 def FeatureUseSqrtEst : SubtargetFeature<"use-sqrt-est", "UseSqrtEst", "true",
 192                             "Use RSQRT* to optimize square root calculations">;
 193 def FeatureUseRecipEst : SubtargetFeature<"use-recip-est", "UseReciprocalEst",
 194                           "true", "Use RCP* to optimize division calculations">;
 195 def FeatureSoftFloat
 196     : SubtargetFeature<"soft-float", "UseSoftFloat", "true",
 197                        "Use software floating point features.">;
 198
 199 //===----------------------------------------------------------------------===//
 200 // X86 processors supported.
 201 //===----------------------------------------------------------------------===//
 202
 203 include "X86Schedule.td"
 204
 205 def ProcIntelAtom : SubtargetFeature<"atom", "X86ProcFamily", "IntelAtom",
 206                     "Intel Atom processors">;
 207 def ProcIntelSLM  : SubtargetFeature<"slm", "X86ProcFamily", "IntelSLM",
 208                     "Intel Silvermont processors">;
 209
 210 class Proc<string Name, list<SubtargetFeature> Features>
 211  : ProcessorModel<Name, GenericModel, Features>;
 212
 213 def : Proc<"generic",         []>;
 214 def : Proc<"i386",            []>;
 215 def : Proc<"i486",            []>;
 216 def : Proc<"i586",            []>;
 217 def : Proc<"pentium",         []>;
 218 def : Proc<"pentium-mmx",     [FeatureMMX]>;
 219 def : Proc<"i686",            []>;
 220 def : Proc<"pentiumpro",      [FeatureCMOV]>;
 221 def : Proc<"pentium2",        [FeatureMMX, FeatureCMOV]>;
 222 def : Proc<"pentium3",        [FeatureSSE1]>;
 223 def : Proc<"pentium3m",       [FeatureSSE1, FeatureSlowBTMem]>;
 224 def : Proc<"pentium-m",       [FeatureSSE2, FeatureSlowBTMem]>;
 225 def : Proc<"pentium4",        [FeatureSSE2]>;
 226 def : Proc<"pentium4m",       [FeatureSSE2, FeatureSlowBTMem]>;
 227
 228 // Intel Core Duo.
 229 def : ProcessorModel<"yonah", SandyBridgeModel,
 230                      [FeatureSSE3, FeatureSlowBTMem]>;
 231
 232 // NetBurst.
 233 def : Proc<"prescott", [FeatureSSE3, FeatureSlowBTMem]>;
 234 def : Proc<"nocona",   [FeatureSSE3, FeatureCMPXCHG16B, FeatureSlowBTMem]>;
 235
 236 // Intel Core 2 Solo/Duo.
 237 def : ProcessorModel<"core2", SandyBridgeModel,
 238                      [FeatureSSSE3, FeatureCMPXCHG16B, FeatureSlowBTMem]>;
 239 def : ProcessorModel<"penryn", SandyBridgeModel,
 240                      [FeatureSSE41, FeatureCMPXCHG16B, FeatureSlowBTMem]>;
 241
 242 // Atom CPUs.
 243 class BonnellProc<string Name> : ProcessorModel<Name, AtomModel, [
 244                                    ProcIntelAtom,
 245                                    FeatureSSSE3,
 246                                    FeatureCMPXCHG16B,
 247                                    FeatureMOVBE,
 248                                    FeatureSlowBTMem,
 249                                    FeatureLeaForSP,
 250                                    FeatureSlowDivide32,
 251                                    FeatureSlowDivide64,
 252                                    FeatureCallRegIndirect,
 253                                    FeatureLEAUsesAG,
 254                                    FeaturePadShortFunctions
 255                                  ]>;
 256 def : BonnellProc<"bonnell">;
 257 def : BonnellProc<"atom">; // Pin the generic name to the baseline.
 258
 259 class SilvermontProc<string Name> : ProcessorModel<Name, SLMModel, [
 260                                       ProcIntelSLM,
 261                                       FeatureSSE42,
 262                                       FeatureCMPXCHG16B,
 263                                       FeatureMOVBE,
 264                                       FeaturePOPCNT,
 265                                       FeaturePCLMUL,
 266                                       FeatureAES,
 267                                       FeatureSlowDivide64,
 268                                       FeatureCallRegIndirect,
 269                                       FeaturePRFCHW,
 270                                       FeatureSlowLEA,
 271                                       FeatureSlowIncDec,
 272                                       FeatureSlowBTMem,
 273                                       FeatureFastUAMem
 274                                     ]>;
 275 def : SilvermontProc<"silvermont">;
 276 def : SilvermontProc<"slm">; // Legacy alias.
 277
 278 // "Arrandale" along with corei3 and corei5
 279 class NehalemProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
 280                                    FeatureSSE42,
 281                                    FeatureCMPXCHG16B,
 282                                    FeatureSlowBTMem,
 283                                    FeatureFastUAMem,
 284                                    FeaturePOPCNT
 285                                  ]>;
 286 def : NehalemProc<"nehalem">;
 287 def : NehalemProc<"corei7">;
 288
 289 // Westmere is a similar machine to nehalem with some additional features.
 290 // Westmere is the corei3/i5/i7 path from nehalem to sandybridge
 291 class WestmereProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
 292                                     FeatureSSE42,
 293                                     FeatureCMPXCHG16B,
 294                                     FeatureSlowBTMem,
 295                                     FeatureFastUAMem,
 296                                     FeaturePOPCNT,
 297                                     FeatureAES,
 298                                     FeaturePCLMUL
 299                                   ]>;
 300 def : WestmereProc<"westmere">;
 301
 302 // SSE is not listed here since llvm treats AVX as a reimplementation of SSE,
 303 // rather than a superset.
 304 class SandyBridgeProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
 305                                        FeatureAVX,
 306                                        FeatureCMPXCHG16B,
 307                                        FeatureFastUAMem,
 308                                        FeatureSlowUAMem32,
 309                                        FeaturePOPCNT,
 310                                        FeatureAES,
 311                                        FeaturePCLMUL
 312                                      ]>;
 313 def : SandyBridgeProc<"sandybridge">;
 314 def : SandyBridgeProc<"corei7-avx">; // Legacy alias.
 315
 316 class IvyBridgeProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
 317                                      FeatureAVX,
 318                                      FeatureCMPXCHG16B,
 319                                      FeatureFastUAMem,
 320                                      FeatureSlowUAMem32,
 321                                      FeaturePOPCNT,
 322                                      FeatureAES,
 323                                      FeaturePCLMUL,
 324                                      FeatureRDRAND,
 325                                      FeatureF16C,
 326                                      FeatureFSGSBase
 327                                    ]>;
 328 def : IvyBridgeProc<"ivybridge">;
 329 def : IvyBridgeProc<"core-avx-i">; // Legacy alias.
 330
 331 class HaswellProc<string Name> : ProcessorModel<Name, HaswellModel, [
 332                                    FeatureAVX2,
 333                                    FeatureCMPXCHG16B,
 334                                    FeatureFastUAMem,
 335                                    FeaturePOPCNT,
 336                                    FeatureAES,
 337                                    FeaturePCLMUL,
 338                                    FeatureRDRAND,
 339                                    FeatureF16C,
 340                                    FeatureFSGSBase,
 341                                    FeatureMOVBE,
 342                                    FeatureLZCNT,
 343                                    FeatureBMI,
 344                                    FeatureBMI2,
 345                                    FeatureFMA,
 346                                    FeatureRTM,
 347                                    FeatureHLE,
 348                                    FeatureSlowIncDec
 349                                  ]>;
 350 def : HaswellProc<"haswell">;
 351 def : HaswellProc<"core-avx2">; // Legacy alias.
 352
 353 class BroadwellProc<string Name> : ProcessorModel<Name, HaswellModel, [
 354                                      FeatureAVX2,
 355                                      FeatureCMPXCHG16B,
 356                                      FeatureFastUAMem,
 357                                      FeaturePOPCNT,
 358                                      FeatureAES,
 359                                      FeaturePCLMUL,
 360                                      FeatureRDRAND,
 361                                      FeatureF16C,
 362                                      FeatureFSGSBase,
 363                                      FeatureMOVBE,
 364                                      FeatureLZCNT,
 365                                      FeatureBMI,
 366                                      FeatureBMI2,
 367                                      FeatureFMA,
 368                                      FeatureRTM,
 369                                      FeatureHLE,
 370                                      FeatureADX,
 371                                      FeatureRDSEED,
 372                                      FeatureSlowIncDec
 373                                    ]>;
 374 def : BroadwellProc<"broadwell">;
 375
 376 // FIXME: define KNL model
 377 class KnightsLandingProc<string Name> : ProcessorModel<Name, HaswellModel,
 378                      [FeatureAVX512, FeatureERI, FeatureCDI, FeaturePFI,
 379                       FeatureCMPXCHG16B, FeatureFastUAMem, FeaturePOPCNT,
 380                       FeatureAES, FeaturePCLMUL, FeatureRDRAND, FeatureF16C,
 381                       FeatureFSGSBase, FeatureMOVBE, FeatureLZCNT, FeatureBMI,
 382                       FeatureBMI2, FeatureFMA, FeatureRTM, FeatureHLE,
 383                       FeatureSlowIncDec]>;
 384 def : KnightsLandingProc<"knl">;
 385
 386 // FIXME: define SKX model
 387 class SkylakeProc<string Name> : ProcessorModel<Name, HaswellModel,
 388                      [FeatureAVX512, FeatureCDI,
 389                       FeatureDQI, FeatureBWI, FeatureVLX,
 390                       FeatureCMPXCHG16B, FeatureFastUAMem, FeaturePOPCNT,
 391                       FeatureAES, FeaturePCLMUL, FeatureRDRAND, FeatureF16C,
 392                       FeatureFSGSBase, FeatureMOVBE, FeatureLZCNT, FeatureBMI,
 393                       FeatureBMI2, FeatureFMA, FeatureRTM, FeatureHLE,
 394                       FeatureSlowIncDec]>;
 395 def : SkylakeProc<"skylake">;
 396 def : SkylakeProc<"skx">; // Legacy alias.
 397
 398
 399 // AMD CPUs.
 400
 401 def : Proc<"k6",              [FeatureMMX]>;
 402 def : Proc<"k6-2",            [Feature3DNow]>;
 403 def : Proc<"k6-3",            [Feature3DNow]>;
 404 def : Proc<"athlon",          [Feature3DNowA, FeatureSlowBTMem,
 405                                FeatureSlowSHLD]>;
 406 def : Proc<"athlon-tbird",    [Feature3DNowA, FeatureSlowBTMem,
 407                                FeatureSlowSHLD]>;
 408 def : Proc<"athlon-4",        [FeatureSSE1,   Feature3DNowA, FeatureSlowBTMem,
 409                                FeatureSlowSHLD]>;
 410 def : Proc<"athlon-xp",       [FeatureSSE1,   Feature3DNowA, FeatureSlowBTMem,
 411                                FeatureSlowSHLD]>;
 412 def : Proc<"athlon-mp",       [FeatureSSE1,   Feature3DNowA, FeatureSlowBTMem,
 413                                FeatureSlowSHLD]>;
 414 def : Proc<"k8",              [FeatureSSE2,   Feature3DNowA, Feature64Bit,
 415                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 416 def : Proc<"opteron",         [FeatureSSE2,   Feature3DNowA, Feature64Bit,
 417                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 418 def : Proc<"athlon64",        [FeatureSSE2,   Feature3DNowA, Feature64Bit,
 419                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 420 def : Proc<"athlon-fx",       [FeatureSSE2,   Feature3DNowA, Feature64Bit,
 421                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 422 def : Proc<"k8-sse3",         [FeatureSSE3,   Feature3DNowA, FeatureCMPXCHG16B,
 423                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 424 def : Proc<"opteron-sse3",    [FeatureSSE3,   Feature3DNowA, FeatureCMPXCHG16B,
 425                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 426 def : Proc<"athlon64-sse3",   [FeatureSSE3,   Feature3DNowA, FeatureCMPXCHG16B,
 427                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 428 def : Proc<"amdfam10",        [FeatureSSE4A,
 429                                Feature3DNowA, FeatureCMPXCHG16B, FeatureLZCNT,
 430                                FeaturePOPCNT, FeatureSlowBTMem,
 431                                FeatureSlowSHLD]>;
 432 def : Proc<"barcelona",       [FeatureSSE4A,
 433                                Feature3DNowA, FeatureCMPXCHG16B, FeatureLZCNT,
 434                                FeaturePOPCNT, FeatureSlowBTMem,
 435                                FeatureSlowSHLD]>;
 436 // Bobcat
 437 def : Proc<"btver1",          [FeatureSSSE3, FeatureSSE4A, FeatureCMPXCHG16B,
 438                                FeaturePRFCHW, FeatureLZCNT, FeaturePOPCNT,
 439                                FeatureSlowSHLD]>;
 440
 441 // Jaguar
 442 def : ProcessorModel<"btver2", BtVer2Model,
 443                      [FeatureAVX, FeatureSSE4A, FeatureCMPXCHG16B,
 444                       FeaturePRFCHW, FeatureAES, FeaturePCLMUL,
 445                       FeatureBMI, FeatureF16C, FeatureMOVBE,
 446                       FeatureLZCNT, FeaturePOPCNT, FeatureFastUAMem,
 447                       FeatureSlowSHLD, FeatureUseSqrtEst, FeatureUseRecipEst]>;
 448
 449 // TODO: We should probably add 'FeatureFastUAMem' to all of the AMD chips.
 450
 451 // Bulldozer
 452 def : Proc<"bdver1",          [FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B,
 453                                FeatureAES, FeaturePRFCHW, FeaturePCLMUL,
 454                                FeatureAVX, FeatureSSE4A, FeatureLZCNT,
 455                                FeaturePOPCNT, FeatureSlowSHLD]>;
 456 // Piledriver
 457 def : Proc<"bdver2",          [FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B,
 458                                FeatureAES, FeaturePRFCHW, FeaturePCLMUL,
 459                                FeatureAVX, FeatureSSE4A, FeatureF16C,
 460                                FeatureLZCNT, FeaturePOPCNT, FeatureBMI,
 461                                FeatureTBM, FeatureFMA, FeatureSlowSHLD]>;
 462
 463 // Steamroller
 464 def : Proc<"bdver3",          [FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B,
 465                                FeatureAES, FeaturePRFCHW, FeaturePCLMUL,
 466                                FeatureAVX, FeatureSSE4A, FeatureF16C,
 467                                FeatureLZCNT, FeaturePOPCNT, FeatureBMI,
 468                                FeatureTBM, FeatureFMA, FeatureSlowSHLD,
 469                                FeatureFSGSBase]>;
 470
 471 // Excavator
 472 def : Proc<"bdver4",          [FeatureAVX2, FeatureXOP, FeatureFMA4,
 473                                FeatureCMPXCHG16B, FeatureAES, FeaturePRFCHW,
 474                                FeaturePCLMUL, FeatureF16C, FeatureLZCNT,
 475                                FeaturePOPCNT, FeatureBMI, FeatureBMI2,
 476                                FeatureTBM, FeatureFMA, FeatureSSE4A,
 477                                FeatureFSGSBase]>;
 478
 479 def : Proc<"geode",           [Feature3DNowA]>;
 480
 481 def : Proc<"winchip-c6",      [FeatureMMX]>;
 482 def : Proc<"winchip2",        [Feature3DNow]>;
 483 def : Proc<"c3",              [Feature3DNow]>;
 484 def : Proc<"c3-2",            [FeatureSSE1]>;
 485
 486 // We also provide a generic 64-bit specific x86 processor model which tries to
 487 // be good for modern chips without enabling instruction set encodings past the
 488 // basic SSE2 and 64-bit ones. It disables slow things from any mainstream and
 489 // modern 64-bit x86 chip, and enables features that are generally beneficial.
 490 //
 491 // We currently use the Sandy Bridge model as the default scheduling model as
 492 // we use it across Nehalem, Westmere, Sandy Bridge, and Ivy Bridge which
 493 // covers a huge swath of x86 processors. If there are specific scheduling
 494 // knobs which need to be tuned differently for AMD chips, we might consider
 495 // forming a common base for them.
 496 def : ProcessorModel<"x86-64", SandyBridgeModel,
 497                      [FeatureSSE2, Feature64Bit, FeatureSlowBTMem,
 498                       FeatureFastUAMem]>;
 499
 500 //===----------------------------------------------------------------------===//
 501 // Register File Description
 502 //===----------------------------------------------------------------------===//
 503
 504 include "X86RegisterInfo.td"
 505
 506 //===----------------------------------------------------------------------===//
 507 // Instruction Descriptions
 508 //===----------------------------------------------------------------------===//
 509
 510 include "X86InstrInfo.td"
 511
 512 def X86InstrInfo : InstrInfo;
 513
 514 //===----------------------------------------------------------------------===//
 515 // Calling Conventions
 516 //===----------------------------------------------------------------------===//
 517
 518 include "X86CallingConv.td"
 519
 520
 521 //===----------------------------------------------------------------------===//
 522 // Assembly Parser
 523 //===----------------------------------------------------------------------===//
 524
 525 def ATTAsmParser : AsmParser {
 526   string AsmParserClassName = "AsmParser";
 527 }
 528
 529 def ATTAsmParserVariant : AsmParserVariant {
 530   int Variant = 0;
 531
 532   // Variant name.
 533   string Name = "att";
 534
 535   // Discard comments in assembly strings.
 536   string CommentDelimiter = "#";
 537
 538   // Recognize hard coded registers.
 539   string RegisterPrefix = "%";
 540 }
 541
 542 def IntelAsmParserVariant : AsmParserVariant {
 543   int Variant = 1;
 544
 545   // Variant name.
 546   string Name = "intel";
 547
 548   // Discard comments in assembly strings.
 549   string CommentDelimiter = ";";
 550
 551   // Recognize hard coded registers.
 552   string RegisterPrefix = "";
 553 }
 554
 555 //===----------------------------------------------------------------------===//
 556 // Assembly Printers
 557 //===----------------------------------------------------------------------===//
 558
 559 // The X86 target supports two different syntaxes for emitting machine code.
 560 // This is controlled by the -x86-asm-syntax={att|intel}
 561 def ATTAsmWriter : AsmWriter {
 562   string AsmWriterClassName  = "ATTInstPrinter";
 563   int Variant = 0;
 564 }
 565 def IntelAsmWriter : AsmWriter {
 566   string AsmWriterClassName  = "IntelInstPrinter";
 567   int Variant = 1;
 568 }
 569
 570 def X86 : Target {
 571   // Information about the instructions...
 572   let InstructionSet = X86InstrInfo;
 573   let AssemblyParsers = [ATTAsmParser];
 574   let AssemblyParserVariants = [ATTAsmParserVariant, IntelAsmParserVariant];
 575   let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];
 576 }