lib/Target/X86/X86.td

   1 //===- X86.td - Target definition file for the Intel X86 ---*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This is a target description file for the Intel i386 architecture, referred to
  11 // here as the "X86" architecture.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 // Get the target-independent interfaces which we are implementing...
  16 //
  17 include "llvm/Target/Target.td"
  18
  19 //===----------------------------------------------------------------------===//
  20 // X86 Subtarget features.
  21 //===----------------------------------------------------------------------===//
  22
  23 def FeatureCMOV    : SubtargetFeature<"cmov","HasCMov", "true",
  24                                       "Enable conditional move instructions">;
  25
  26 def FeaturePOPCNT   : SubtargetFeature<"popcnt", "HasPOPCNT", "true",
  27                                        "Support POPCNT instruction">;
  28
  29
  30 def FeatureMMX     : SubtargetFeature<"mmx","X86SSELevel", "MMX",
  31                                       "Enable MMX instructions">;
  32 def FeatureSSE1    : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
  33                                       "Enable SSE instructions",
  34                                       // SSE codegen depends on cmovs, and all
  35                                       // SSE1+ processors support them.
  36                                       [FeatureMMX, FeatureCMOV]>;
  37 def FeatureSSE2    : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",
  38                                       "Enable SSE2 instructions",
  39                                       [FeatureSSE1]>;
  40 def FeatureSSE3    : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
  41                                       "Enable SSE3 instructions",
  42                                       [FeatureSSE2]>;
  43 def FeatureSSSE3   : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3",
  44                                       "Enable SSSE3 instructions",
  45                                       [FeatureSSE3]>;
  46 def FeatureSSE41   : SubtargetFeature<"sse41", "X86SSELevel", "SSE41",
  47                                       "Enable SSE 4.1 instructions",
  48                                       [FeatureSSSE3]>;
  49 def FeatureSSE42   : SubtargetFeature<"sse42", "X86SSELevel", "SSE42",
  50                                       "Enable SSE 4.2 instructions",
  51                                       [FeatureSSE41, FeaturePOPCNT]>;
  52 def Feature3DNow   : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
  53                                       "Enable 3DNow! instructions",
  54                                       [FeatureMMX]>;
  55 def Feature3DNowA  : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
  56                                       "Enable 3DNow! Athlon instructions",
  57                                       [Feature3DNow]>;
  58 // All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied
  59 // feature, because SSE2 can be disabled (e.g. for compiling OS kernels)
  60 // without disabling 64-bit mode.
  61 def Feature64Bit   : SubtargetFeature<"64bit", "HasX86_64", "true",
  62                                       "Support 64-bit instructions",
  63                                       [FeatureCMOV]>;
  64 def FeatureSlowBTMem : SubtargetFeature<"slow-bt-mem", "IsBTMemSlow", "true",
  65                                        "Bit testing of memory is slow">;
  66 def FeatureFastUAMem : SubtargetFeature<"fast-unaligned-mem",
  67                                         "IsUAMemFast", "true",
  68                                         "Fast unaligned memory access">;
  69 def FeatureSSE4A   : SubtargetFeature<"sse4a", "HasSSE4A", "true",
  70                                       "Support SSE 4a instructions",
  71                                       [FeaturePOPCNT]>;
  72
  73 def FeatureAVX     : SubtargetFeature<"avx", "HasAVX", "true",
  74                                       "Enable AVX instructions">;
  75 def FeatureCLMUL   : SubtargetFeature<"clmul", "HasCLMUL", "true",
  76                                "Enable carry-less multiplication instructions">;
  77 def FeatureFMA3    : SubtargetFeature<"fma3", "HasFMA3", "true",
  78                                      "Enable three-operand fused multiple-add">;
  79 def FeatureFMA4    : SubtargetFeature<"fma4", "HasFMA4", "true",
  80                                       "Enable four-operand fused multiple-add">;
  81 def FeatureVectorUAMem : SubtargetFeature<"vector-unaligned-mem",
  82                                           "HasVectorUAMem", "true",
  83                  "Allow unaligned memory operands on vector/SIMD instructions">;
  84 def FeatureAES     : SubtargetFeature<"aes", "HasAES", "true",
  85                                       "Enable AES instructions">;
  86
  87 //===----------------------------------------------------------------------===//
  88 // X86 processors supported.
  89 //===----------------------------------------------------------------------===//
  90
  91 class Proc<string Name, list<SubtargetFeature> Features>
  92  : Processor<Name, NoItineraries, Features>;
  93
  94 def : Proc<"generic",         []>;
  95 def : Proc<"i386",            []>;
  96 def : Proc<"i486",            []>;
  97 def : Proc<"i586",            []>;
  98 def : Proc<"pentium",         []>;
  99 def : Proc<"pentium-mmx",     [FeatureMMX]>;
 100 def : Proc<"i686",            []>;
 101 def : Proc<"pentiumpro",      [FeatureCMOV]>;
 102 def : Proc<"pentium2",        [FeatureMMX, FeatureCMOV]>;
 103 def : Proc<"pentium3",        [FeatureSSE1]>;
 104 def : Proc<"pentium-m",       [FeatureSSE2, FeatureSlowBTMem]>;
 105 def : Proc<"pentium4",        [FeatureSSE2]>;
 106 def : Proc<"x86-64",          [FeatureSSE2,   Feature64Bit, FeatureSlowBTMem]>;
 107 def : Proc<"yonah",           [FeatureSSE3, FeatureSlowBTMem]>;
 108 def : Proc<"prescott",        [FeatureSSE3, FeatureSlowBTMem]>;
 109 def : Proc<"nocona",          [FeatureSSE3,   Feature64Bit, FeatureSlowBTMem]>;
 110 def : Proc<"core2",           [FeatureSSSE3,  Feature64Bit, FeatureSlowBTMem]>;
 111 def : Proc<"penryn",          [FeatureSSE41,  Feature64Bit, FeatureSlowBTMem]>;
 112 def : Proc<"atom",            [FeatureSSE3,   Feature64Bit, FeatureSlowBTMem]>;
 113 // "Arrandale" along with corei3 and corei5
 114 def : Proc<"corei7",          [FeatureSSE42,  Feature64Bit, FeatureSlowBTMem,
 115                                FeatureFastUAMem, FeatureAES]>;
 116 def : Proc<"nehalem",         [FeatureSSE42,  Feature64Bit, FeatureSlowBTMem,
 117                                FeatureFastUAMem]>;
 118 // Westmere is a similar machine to nehalem with some additional features.
 119 // Westmere is the corei3/i5/i7 path from nehalem to sandybridge
 120 def : Proc<"westmere",        [FeatureSSE42,  Feature64Bit, FeatureSlowBTMem,
 121                                FeatureFastUAMem, FeatureAES, FeatureCLMUL]>;
 122 // SSE is not listed here since llvm treats AVX as a reimplementation of SSE,
 123 // rather than a superset.
 124 // FIXME: Disabling AVX for now since it's not ready.
 125 def : Proc<"sandybridge",     [FeatureSSE42, Feature64Bit,
 126                                FeatureAES, FeatureCLMUL]>;
 127
 128 def : Proc<"k6",              [FeatureMMX]>;
 129 def : Proc<"k6-2",            [Feature3DNow]>;
 130 def : Proc<"k6-3",            [Feature3DNow]>;
 131 def : Proc<"athlon",          [Feature3DNowA, FeatureSlowBTMem]>;
 132 def : Proc<"athlon-tbird",    [Feature3DNowA, FeatureSlowBTMem]>;
 133 def : Proc<"athlon-4",        [FeatureSSE1,   Feature3DNowA, FeatureSlowBTMem]>;
 134 def : Proc<"athlon-xp",       [FeatureSSE1,   Feature3DNowA, FeatureSlowBTMem]>;
 135 def : Proc<"athlon-mp",       [FeatureSSE1,   Feature3DNowA, FeatureSlowBTMem]>;
 136 def : Proc<"k8",              [FeatureSSE2,   Feature3DNowA, Feature64Bit,
 137                                FeatureSlowBTMem]>;
 138 def : Proc<"opteron",         [FeatureSSE2,   Feature3DNowA, Feature64Bit,
 139                                FeatureSlowBTMem]>;
 140 def : Proc<"athlon64",        [FeatureSSE2,   Feature3DNowA, Feature64Bit,
 141                                FeatureSlowBTMem]>;
 142 def : Proc<"athlon-fx",       [FeatureSSE2,   Feature3DNowA, Feature64Bit,
 143                                FeatureSlowBTMem]>;
 144 def : Proc<"k8-sse3",         [FeatureSSE3,   Feature3DNowA, Feature64Bit,
 145                                FeatureSlowBTMem]>;
 146 def : Proc<"opteron-sse3",    [FeatureSSE3,   Feature3DNowA, Feature64Bit,
 147                                FeatureSlowBTMem]>;
 148 def : Proc<"athlon64-sse3",   [FeatureSSE3,   Feature3DNowA, Feature64Bit,
 149                                FeatureSlowBTMem]>;
 150 def : Proc<"amdfam10",        [FeatureSSE3,   FeatureSSE4A,
 151                                Feature3DNowA, Feature64Bit, FeatureSlowBTMem]>;
 152 def : Proc<"barcelona",       [FeatureSSE3,   FeatureSSE4A,
 153                                Feature3DNowA, Feature64Bit, FeatureSlowBTMem]>;
 154 def : Proc<"istanbul",        [Feature3DNowA, Feature64Bit, FeatureSSE4A,
 155                                Feature3DNowA]>;
 156 def : Proc<"shanghai",        [Feature3DNowA, Feature64Bit, FeatureSSE4A,
 157                                Feature3DNowA]>;
 158
 159 def : Proc<"winchip-c6",      [FeatureMMX]>;
 160 def : Proc<"winchip2",        [Feature3DNow]>;
 161 def : Proc<"c3",              [Feature3DNow]>;
 162 def : Proc<"c3-2",            [FeatureSSE1]>;
 163
 164 //===----------------------------------------------------------------------===//
 165 // Register File Description
 166 //===----------------------------------------------------------------------===//
 167
 168 include "X86RegisterInfo.td"
 169
 170 //===----------------------------------------------------------------------===//
 171 // Instruction Descriptions
 172 //===----------------------------------------------------------------------===//
 173
 174 include "X86InstrInfo.td"
 175
 176 def X86InstrInfo : InstrInfo;
 177
 178 //===----------------------------------------------------------------------===//
 179 // Calling Conventions
 180 //===----------------------------------------------------------------------===//
 181
 182 include "X86CallingConv.td"
 183
 184
 185 //===----------------------------------------------------------------------===//
 186 // Assembly Parser
 187 //===----------------------------------------------------------------------===//
 188
 189 // Currently the X86 assembly parser only supports ATT syntax.
 190 def ATTAsmParser : AsmParser {
 191   string AsmParserClassName = "ATTAsmParser";
 192   int Variant = 0;
 193
 194   // Discard comments in assembly strings.
 195   string CommentDelimiter = "#";
 196
 197   // Recognize hard coded registers.
 198   string RegisterPrefix = "%";
 199 }
 200
 201 //===----------------------------------------------------------------------===//
 202 // Assembly Printers
 203 //===----------------------------------------------------------------------===//
 204
 205 // The X86 target supports two different syntaxes for emitting machine code.
 206 // This is controlled by the -x86-asm-syntax={att|intel}
 207 def ATTAsmWriter : AsmWriter {
 208   string AsmWriterClassName  = "ATTInstPrinter";
 209   int Variant = 0;
 210   bit isMCAsmWriter = 1;
 211 }
 212 def IntelAsmWriter : AsmWriter {
 213   string AsmWriterClassName  = "IntelInstPrinter";
 214   int Variant = 1;
 215   bit isMCAsmWriter = 1;
 216 }
 217
 218 def X86 : Target {
 219   // Information about the instructions...
 220   let InstructionSet = X86InstrInfo;
 221
 222   let AssemblyParsers = [ATTAsmParser];
 223
 224   let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];
 225 }