lib/Target/X86/X86.td

   1 //===- X86.td - Target definition file for the Intel X86 ---*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This is a target description file for the Intel i386 architecture, refered to
  11 // here as the "X86" architecture.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 // Get the target-independent interfaces which we are implementing...
  16 //
  17 include "llvm/Target/Target.td"
  18
  19 //===----------------------------------------------------------------------===//
  20 // X86 Subtarget features.
  21 //===----------------------------------------------------------------------===//
  22
  23 def FeatureCMOV    : SubtargetFeature<"cmov","HasCMov", "true",
  24                                       "Enable conditional move instructions">;
  25
  26
  27 def FeatureMMX     : SubtargetFeature<"mmx","X86SSELevel", "MMX",
  28                                       "Enable MMX instructions">;
  29 def FeatureSSE1    : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
  30                                       "Enable SSE instructions",
  31                                       // SSE codegen depends on cmovs, and all
  32                                       // SSE1+ processors support them.
  33                                       [FeatureMMX, FeatureCMOV]>;
  34 def FeatureSSE2    : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",
  35                                       "Enable SSE2 instructions",
  36                                       [FeatureSSE1]>;
  37 def FeatureSSE3    : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
  38                                       "Enable SSE3 instructions",
  39                                       [FeatureSSE2]>;
  40 def FeatureSSSE3   : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3",
  41                                       "Enable SSSE3 instructions",
  42                                       [FeatureSSE3]>;
  43 def FeatureSSE41   : SubtargetFeature<"sse41", "X86SSELevel", "SSE41",
  44                                       "Enable SSE 4.1 instructions",
  45                                       [FeatureSSSE3]>;
  46 def FeatureSSE42   : SubtargetFeature<"sse42", "X86SSELevel", "SSE42",
  47                                       "Enable SSE 4.2 instructions",
  48                                       [FeatureSSE41]>;
  49 def Feature3DNow   : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
  50                                       "Enable 3DNow! instructions">;
  51 def Feature3DNowA  : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
  52                                       "Enable 3DNow! Athlon instructions",
  53                                       [Feature3DNow]>;
  54 // All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied
  55 // feature, because SSE2 can be disabled (e.g. for compiling OS kernels)
  56 // without disabling 64-bit mode.
  57 def Feature64Bit   : SubtargetFeature<"64bit", "HasX86_64", "true",
  58                                       "Support 64-bit instructions",
  59                                       [FeatureCMOV]>;
  60 def FeatureSlowBTMem : SubtargetFeature<"slow-bt-mem", "IsBTMemSlow", "true",
  61                                        "Bit testing of memory is slow">;
  62 def FeatureSSE4A   : SubtargetFeature<"sse4a", "HasSSE4A", "true",
  63                                       "Support SSE 4a instructions">;
  64
  65 def FeatureAVX     : SubtargetFeature<"avx", "HasAVX", "true",
  66                                       "Enable AVX instructions">;
  67 def FeatureFMA3    : SubtargetFeature<"fma3", "HasFMA3", "true",
  68                                      "Enable three-operand fused multiple-add">;
  69 def FeatureFMA4    : SubtargetFeature<"fma4", "HasFMA4", "true",
  70                                       "Enable four-operand fused multiple-add">;
  71 def FeatureVectorUAMem : SubtargetFeature<"vector-unaligned-mem",
  72                                           "HasVectorUAMem", "true",
  73                  "Allow unaligned memory operands on vector/SIMD instructions">;
  74
  75 //===----------------------------------------------------------------------===//
  76 // X86 processors supported.
  77 //===----------------------------------------------------------------------===//
  78
  79 class Proc<string Name, list<SubtargetFeature> Features>
  80  : Processor<Name, NoItineraries, Features>;
  81
  82 def : Proc<"generic",         []>;
  83 def : Proc<"i386",            []>;
  84 def : Proc<"i486",            []>;
  85 def : Proc<"i586",            []>;
  86 def : Proc<"pentium",         []>;
  87 def : Proc<"pentium-mmx",     [FeatureMMX]>;
  88 def : Proc<"i686",            []>;
  89 def : Proc<"pentiumpro",      [FeatureCMOV]>;
  90 def : Proc<"pentium2",        [FeatureMMX, FeatureCMOV]>;
  91 def : Proc<"pentium3",        [FeatureSSE1]>;
  92 def : Proc<"pentium-m",       [FeatureSSE2, FeatureSlowBTMem]>;
  93 def : Proc<"pentium4",        [FeatureSSE2]>;
  94 def : Proc<"x86-64",          [FeatureSSE2,   Feature64Bit, FeatureSlowBTMem]>;
  95 def : Proc<"yonah",           [FeatureSSE3, FeatureSlowBTMem]>;
  96 def : Proc<"prescott",        [FeatureSSE3, FeatureSlowBTMem]>;
  97 def : Proc<"nocona",          [FeatureSSE3,   Feature64Bit, FeatureSlowBTMem]>;
  98 def : Proc<"core2",           [FeatureSSSE3,  Feature64Bit, FeatureSlowBTMem]>;
  99 def : Proc<"penryn",          [FeatureSSE41,  Feature64Bit, FeatureSlowBTMem]>;
 100 def : Proc<"atom",            [FeatureSSE3,   Feature64Bit, FeatureSlowBTMem]>;
 101 def : Proc<"corei7",          [FeatureSSE42,  Feature64Bit, FeatureSlowBTMem]>;
 102 def : Proc<"nehalem",         [FeatureSSE42,  Feature64Bit, FeatureSlowBTMem]>;
 103 // Sandy Bridge does not have FMA
 104 def : Proc<"sandybridge",     [FeatureSSE42,  FeatureAVX,   Feature64Bit]>;
 105
 106 def : Proc<"k6",              [FeatureMMX]>;
 107 def : Proc<"k6-2",            [FeatureMMX,    Feature3DNow]>;
 108 def : Proc<"k6-3",            [FeatureMMX,    Feature3DNow]>;
 109 def : Proc<"athlon",          [FeatureMMX,    Feature3DNowA, FeatureSlowBTMem]>;
 110 def : Proc<"athlon-tbird",    [FeatureMMX,    Feature3DNowA, FeatureSlowBTMem]>;
 111 def : Proc<"athlon-4",        [FeatureSSE1,   Feature3DNowA, FeatureSlowBTMem]>;
 112 def : Proc<"athlon-xp",       [FeatureSSE1,   Feature3DNowA, FeatureSlowBTMem]>;
 113 def : Proc<"athlon-mp",       [FeatureSSE1,   Feature3DNowA, FeatureSlowBTMem]>;
 114 def : Proc<"k8",              [FeatureSSE2,   Feature3DNowA, Feature64Bit,
 115                                FeatureSlowBTMem]>;
 116 def : Proc<"opteron",         [FeatureSSE2,   Feature3DNowA, Feature64Bit,
 117                                FeatureSlowBTMem]>;
 118 def : Proc<"athlon64",        [FeatureSSE2,   Feature3DNowA, Feature64Bit,
 119                                FeatureSlowBTMem]>;
 120 def : Proc<"athlon-fx",       [FeatureSSE2,   Feature3DNowA, Feature64Bit,
 121                                FeatureSlowBTMem]>;
 122 def : Proc<"k8-sse3",         [FeatureSSE3,   Feature3DNowA, Feature64Bit,
 123                                FeatureSlowBTMem]>;
 124 def : Proc<"opteron-sse3",    [FeatureSSE3,   Feature3DNowA, Feature64Bit,
 125                                FeatureSlowBTMem]>;
 126 def : Proc<"athlon64-sse3",   [FeatureSSE3,   Feature3DNowA, Feature64Bit,
 127                                FeatureSlowBTMem]>;
 128 def : Proc<"amdfam10",        [FeatureSSE3,   FeatureSSE4A,
 129                                Feature3DNowA, Feature64Bit, FeatureSlowBTMem]>;
 130 def : Proc<"barcelona",       [FeatureSSE3,   FeatureSSE4A,
 131                                Feature3DNowA, Feature64Bit, FeatureSlowBTMem]>;
 132 def : Proc<"istanbul",        [Feature3DNowA, Feature64Bit, FeatureSSE4A,
 133                                Feature3DNowA]>;
 134 def : Proc<"shanghai",        [Feature3DNowA, Feature64Bit, FeatureSSE4A,
 135                                Feature3DNowA]>;
 136
 137 def : Proc<"winchip-c6",      [FeatureMMX]>;
 138 def : Proc<"winchip2",        [FeatureMMX, Feature3DNow]>;
 139 def : Proc<"c3",              [FeatureMMX, Feature3DNow]>;
 140 def : Proc<"c3-2",            [FeatureSSE1]>;
 141
 142 //===----------------------------------------------------------------------===//
 143 // Register File Description
 144 //===----------------------------------------------------------------------===//
 145
 146 include "X86RegisterInfo.td"
 147
 148 //===----------------------------------------------------------------------===//
 149 // Instruction Descriptions
 150 //===----------------------------------------------------------------------===//
 151
 152 include "X86InstrInfo.td"
 153
 154 def X86InstrInfo : InstrInfo {
 155
 156   // Define how we want to layout our TargetSpecific information field... This
 157   // should be kept up-to-date with the fields in the X86InstrInfo.h file.
 158   let TSFlagsFields = ["FormBits",
 159                        "hasOpSizePrefix",
 160                        "hasAdSizePrefix",
 161                        "Prefix",
 162                        "hasREX_WPrefix",
 163                        "ImmT.Value",
 164                        "FPForm.Value",
 165                        "hasLockPrefix",
 166                        "SegOvrBits",
 167                        "ExeDomain.Value",
 168                        "Opcode"];
 169   let TSFlagsShifts = [0,
 170                        6,
 171                        7,
 172                        8,
 173                        12,
 174                        13,
 175                        16,
 176                        19,
 177                        20,
 178                        22,
 179                        24];
 180 }
 181
 182 //===----------------------------------------------------------------------===//
 183 // Calling Conventions
 184 //===----------------------------------------------------------------------===//
 185
 186 include "X86CallingConv.td"
 187
 188
 189 //===----------------------------------------------------------------------===//
 190 // Assembly Printers
 191 //===----------------------------------------------------------------------===//
 192
 193 // Currently the X86 assembly parser only supports ATT syntax.
 194 def ATTAsmParser : AsmParser {
 195   string AsmParserClassName  = "ATTAsmParser";
 196   string AsmParserInstCleanup  = "InstructionCleanup";
 197   int Variant = 0;
 198
 199   // Discard comments in assembly strings.
 200   string CommentDelimiter = "#";
 201
 202   // Recognize hard coded registers.
 203   string RegisterPrefix = "%";
 204 }
 205
 206 // The X86 target supports two different syntaxes for emitting machine code.
 207 // This is controlled by the -x86-asm-syntax={att|intel}
 208 def ATTAsmWriter : AsmWriter {
 209   string AsmWriterClassName  = "ATTInstPrinter";
 210   int Variant = 0;
 211 }
 212 def IntelAsmWriter : AsmWriter {
 213   string AsmWriterClassName  = "IntelInstPrinter";
 214   int Variant = 1;
 215 }
 216
 217 def X86 : Target {
 218   // Information about the instructions...
 219   let InstructionSet = X86InstrInfo;
 220
 221   let AssemblyParsers = [ATTAsmParser];
 222
 223   let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];
 224 }