lib/Target/X86/X86.td

   1 //===- X86.td - Target definition file for the Intel X86 ---*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This is a target description file for the Intel i386 architecture, referred to
  11 // here as the "X86" architecture.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 // Get the target-independent interfaces which we are implementing...
  16 //
  17 include "llvm/Target/Target.td"
  18
  19 //===----------------------------------------------------------------------===//
  20 // X86 Subtarget state.
  21 //
  22
  23 def Mode64Bit : SubtargetFeature<"64bit-mode", "In64BitMode", "true",
  24                                   "64-bit mode (x86_64)">;
  25
  26 //===----------------------------------------------------------------------===//
  27 // X86 Subtarget features.
  28 //===----------------------------------------------------------------------===//
  29
  30 def FeatureCMOV    : SubtargetFeature<"cmov","HasCMov", "true",
  31                                       "Enable conditional move instructions">;
  32
  33 def FeaturePOPCNT   : SubtargetFeature<"popcnt", "HasPOPCNT", "true",
  34                                        "Support POPCNT instruction">;
  35
  36
  37 def FeatureMMX     : SubtargetFeature<"mmx","X86SSELevel", "MMX",
  38                                       "Enable MMX instructions">;
  39 def FeatureSSE1    : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
  40                                       "Enable SSE instructions",
  41                                       // SSE codegen depends on cmovs, and all
  42                                       // SSE1+ processors support them.
  43                                       [FeatureMMX, FeatureCMOV]>;
  44 def FeatureSSE2    : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",
  45                                       "Enable SSE2 instructions",
  46                                       [FeatureSSE1]>;
  47 def FeatureSSE3    : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
  48                                       "Enable SSE3 instructions",
  49                                       [FeatureSSE2]>;
  50 def FeatureSSSE3   : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3",
  51                                       "Enable SSSE3 instructions",
  52                                       [FeatureSSE3]>;
  53 def FeatureSSE41   : SubtargetFeature<"sse41", "X86SSELevel", "SSE41",
  54                                       "Enable SSE 4.1 instructions",
  55                                       [FeatureSSSE3]>;
  56 def FeatureSSE42   : SubtargetFeature<"sse42", "X86SSELevel", "SSE42",
  57                                       "Enable SSE 4.2 instructions",
  58                                       [FeatureSSE41, FeaturePOPCNT]>;
  59 def Feature3DNow   : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
  60                                       "Enable 3DNow! instructions",
  61                                       [FeatureMMX]>;
  62 def Feature3DNowA  : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
  63                                       "Enable 3DNow! Athlon instructions",
  64                                       [Feature3DNow]>;
  65 // All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied
  66 // feature, because SSE2 can be disabled (e.g. for compiling OS kernels)
  67 // without disabling 64-bit mode.
  68 def Feature64Bit   : SubtargetFeature<"64bit", "HasX86_64", "true",
  69                                       "Support 64-bit instructions",
  70                                       [FeatureCMOV]>;
  71 def FeatureCMPXCHG16B : SubtargetFeature<"cmpxchg16b", "HasCmpxchg16b", "true",
  72                                       "64-bit with cmpxchg16b",
  73                                       [Feature64Bit]>;
  74 def FeatureSlowBTMem : SubtargetFeature<"slow-bt-mem", "IsBTMemSlow", "true",
  75                                        "Bit testing of memory is slow">;
  76 def FeatureFastUAMem : SubtargetFeature<"fast-unaligned-mem",
  77                                         "IsUAMemFast", "true",
  78                                         "Fast unaligned memory access">;
  79 def FeatureSSE4A   : SubtargetFeature<"sse4a", "HasSSE4A", "true",
  80                                       "Support SSE 4a instructions",
  81                                       [FeaturePOPCNT]>;
  82
  83 def FeatureAVX     : SubtargetFeature<"avx", "HasAVX", "true",
  84                                       "Enable AVX instructions">;
  85 def FeatureCLMUL   : SubtargetFeature<"clmul", "HasCLMUL", "true",
  86                                "Enable carry-less multiplication instructions">;
  87 def FeatureFMA3    : SubtargetFeature<"fma3", "HasFMA3", "true",
  88                                      "Enable three-operand fused multiple-add">;
  89 def FeatureFMA4    : SubtargetFeature<"fma4", "HasFMA4", "true",
  90                                       "Enable four-operand fused multiple-add">;
  91 def FeatureVectorUAMem : SubtargetFeature<"vector-unaligned-mem",
  92                                           "HasVectorUAMem", "true",
  93                  "Allow unaligned memory operands on vector/SIMD instructions">;
  94 def FeatureAES     : SubtargetFeature<"aes", "HasAES", "true",
  95                                       "Enable AES instructions">;
  96
  97 //===----------------------------------------------------------------------===//
  98 // X86 processors supported.
  99 //===----------------------------------------------------------------------===//
 100
 101 class Proc<string Name, list<SubtargetFeature> Features>
 102  : Processor<Name, NoItineraries, Features>;
 103
 104 def : Proc<"generic",         []>;
 105 def : Proc<"i386",            []>;
 106 def : Proc<"i486",            []>;
 107 def : Proc<"i586",            []>;
 108 def : Proc<"pentium",         []>;
 109 def : Proc<"pentium-mmx",     [FeatureMMX]>;
 110 def : Proc<"i686",            []>;
 111 def : Proc<"pentiumpro",      [FeatureCMOV]>;
 112 def : Proc<"pentium2",        [FeatureMMX, FeatureCMOV]>;
 113 def : Proc<"pentium3",        [FeatureSSE1]>;
 114 def : Proc<"pentium3m",       [FeatureSSE1, FeatureSlowBTMem]>;
 115 def : Proc<"pentium-m",       [FeatureSSE2, FeatureSlowBTMem]>;
 116 def : Proc<"pentium4",        [FeatureSSE2]>;
 117 def : Proc<"pentium4m",       [FeatureSSE2, FeatureSlowBTMem]>;
 118 def : Proc<"x86-64",          [FeatureSSE2, Feature64Bit, FeatureSlowBTMem]>;
 119 def : Proc<"yonah",           [FeatureSSE3, FeatureSlowBTMem]>;
 120 def : Proc<"prescott",        [FeatureSSE3, FeatureSlowBTMem]>;
 121 def : Proc<"nocona",          [FeatureSSE3, FeatureCMPXCHG16B,
 122                                FeatureSlowBTMem]>;
 123 def : Proc<"core2",           [FeatureSSSE3, FeatureCMPXCHG16B,
 124                                FeatureSlowBTMem]>;
 125 def : Proc<"penryn",          [FeatureSSE41, FeatureCMPXCHG16B,
 126                                FeatureSlowBTMem]>;
 127 def : Proc<"atom",            [FeatureSSE3,  FeatureCMPXCHG16B,
 128                                FeatureSlowBTMem]>;
 129 // "Arrandale" along with corei3 and corei5
 130 def : Proc<"corei7",          [FeatureSSE42, FeatureCMPXCHG16B,
 131                                FeatureSlowBTMem, FeatureFastUAMem, FeatureAES]>;
 132 def : Proc<"nehalem",         [FeatureSSE42,  FeatureCMPXCHG16B,
 133                                FeatureSlowBTMem, FeatureFastUAMem]>;
 134 // Westmere is a similar machine to nehalem with some additional features.
 135 // Westmere is the corei3/i5/i7 path from nehalem to sandybridge
 136 def : Proc<"westmere",        [FeatureSSE42, FeatureCMPXCHG16B,
 137                                FeatureSlowBTMem, FeatureFastUAMem, FeatureAES,
 138                                FeatureCLMUL]>;
 139 // SSE is not listed here since llvm treats AVX as a reimplementation of SSE,
 140 // rather than a superset.
 141 // FIXME: Disabling AVX for now since it's not ready.
 142 def : Proc<"corei7-avx",      [FeatureSSE42, FeatureCMPXCHG16B,
 143                                FeatureAES, FeatureCLMUL]>;
 144
 145 def : Proc<"k6",              [FeatureMMX]>;
 146 def : Proc<"k6-2",            [Feature3DNow]>;
 147 def : Proc<"k6-3",            [Feature3DNow]>;
 148 def : Proc<"athlon",          [Feature3DNowA, FeatureSlowBTMem]>;
 149 def : Proc<"athlon-tbird",    [Feature3DNowA, FeatureSlowBTMem]>;
 150 def : Proc<"athlon-4",        [FeatureSSE1,   Feature3DNowA, FeatureSlowBTMem]>;
 151 def : Proc<"athlon-xp",       [FeatureSSE1,   Feature3DNowA, FeatureSlowBTMem]>;
 152 def : Proc<"athlon-mp",       [FeatureSSE1,   Feature3DNowA, FeatureSlowBTMem]>;
 153 def : Proc<"k8",              [FeatureSSE2,   Feature3DNowA, Feature64Bit,
 154                                FeatureSlowBTMem]>;
 155 def : Proc<"opteron",         [FeatureSSE2,   Feature3DNowA, Feature64Bit,
 156                                FeatureSlowBTMem]>;
 157 def : Proc<"athlon64",        [FeatureSSE2,   Feature3DNowA, Feature64Bit,
 158                                FeatureSlowBTMem]>;
 159 def : Proc<"athlon-fx",       [FeatureSSE2,   Feature3DNowA, Feature64Bit,
 160                                FeatureSlowBTMem]>;
 161 def : Proc<"k8-sse3",         [FeatureSSE3,   Feature3DNowA, FeatureCMPXCHG16B,
 162                                FeatureSlowBTMem]>;
 163 def : Proc<"opteron-sse3",    [FeatureSSE3,   Feature3DNowA, FeatureCMPXCHG16B,
 164                                FeatureSlowBTMem]>;
 165 def : Proc<"athlon64-sse3",   [FeatureSSE3,   Feature3DNowA, FeatureCMPXCHG16B,
 166                                FeatureSlowBTMem]>;
 167 def : Proc<"amdfam10",        [FeatureSSE3,   FeatureSSE4A,
 168                                Feature3DNowA, FeatureCMPXCHG16B,
 169                                FeatureSlowBTMem]>;
 170 def : Proc<"barcelona",       [FeatureSSE3,   FeatureSSE4A,
 171                                Feature3DNowA, FeatureCMPXCHG16B,
 172                                FeatureSlowBTMem]>;
 173 def : Proc<"istanbul",        [Feature3DNowA, FeatureCMPXCHG16B,
 174                                FeatureSSE4A, Feature3DNowA]>;
 175 def : Proc<"shanghai",        [Feature3DNowA, FeatureCMPXCHG16B, FeatureSSE4A,
 176                                Feature3DNowA]>;
 177
 178 def : Proc<"winchip-c6",      [FeatureMMX]>;
 179 def : Proc<"winchip2",        [Feature3DNow]>;
 180 def : Proc<"c3",              [Feature3DNow]>;
 181 def : Proc<"c3-2",            [FeatureSSE1]>;
 182
 183 //===----------------------------------------------------------------------===//
 184 // Register File Description
 185 //===----------------------------------------------------------------------===//
 186
 187 include "X86RegisterInfo.td"
 188
 189 //===----------------------------------------------------------------------===//
 190 // Instruction Descriptions
 191 //===----------------------------------------------------------------------===//
 192
 193 include "X86InstrInfo.td"
 194
 195 def X86InstrInfo : InstrInfo;
 196
 197 //===----------------------------------------------------------------------===//
 198 // Calling Conventions
 199 //===----------------------------------------------------------------------===//
 200
 201 include "X86CallingConv.td"
 202
 203
 204 //===----------------------------------------------------------------------===//
 205 // Assembly Parser
 206 //===----------------------------------------------------------------------===//
 207
 208 // Currently the X86 assembly parser only supports ATT syntax.
 209 def ATTAsmParser : AsmParser {
 210   string AsmParserClassName = "ATTAsmParser";
 211   int Variant = 0;
 212
 213   // Discard comments in assembly strings.
 214   string CommentDelimiter = "#";
 215
 216   // Recognize hard coded registers.
 217   string RegisterPrefix = "%";
 218 }
 219
 220 //===----------------------------------------------------------------------===//
 221 // Assembly Printers
 222 //===----------------------------------------------------------------------===//
 223
 224 // The X86 target supports two different syntaxes for emitting machine code.
 225 // This is controlled by the -x86-asm-syntax={att|intel}
 226 def ATTAsmWriter : AsmWriter {
 227   string AsmWriterClassName  = "ATTInstPrinter";
 228   int Variant = 0;
 229   bit isMCAsmWriter = 1;
 230 }
 231 def IntelAsmWriter : AsmWriter {
 232   string AsmWriterClassName  = "IntelInstPrinter";
 233   int Variant = 1;
 234   bit isMCAsmWriter = 1;
 235 }
 236
 237 def X86 : Target {
 238   // Information about the instructions...
 239   let InstructionSet = X86InstrInfo;
 240
 241   let AssemblyParsers = [ATTAsmParser];
 242
 243   let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];
 244 }