1 //===- X86.td - Target definition file for the Intel X86 ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This is a target description file for the Intel i386 architecture, refered to
11 // here as the "X86" architecture.
13 //===----------------------------------------------------------------------===//
15 // Get the target-independent interfaces which we are implementing...
17 include "llvm/Target/Target.td"
19 //===----------------------------------------------------------------------===//
20 // X86 Subtarget features.
21 //===----------------------------------------------------------------------===//
23 def FeatureCMOV : SubtargetFeature<"cmov","HasCMov", "true",
24 "Enable conditional move instructions">;
26 def FeatureMMX : SubtargetFeature<"mmx","X86SSELevel", "MMX",
27 "Enable MMX instructions">;
28 def FeatureSSE1 : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
29 "Enable SSE instructions",
30 // SSE codegen depends on cmovs, and all
31 // SSE1+ processors support them.
32 [FeatureMMX, FeatureCMOV]>;
33 def FeatureSSE2 : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",
34 "Enable SSE2 instructions",
36 def FeatureSSE3 : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
37 "Enable SSE3 instructions",
39 def FeatureSSSE3 : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3",
40 "Enable SSSE3 instructions",
42 def FeatureSSE41 : SubtargetFeature<"sse41", "X86SSELevel", "SSE41",
43 "Enable SSE 4.1 instructions",
45 def FeatureSSE42 : SubtargetFeature<"sse42", "X86SSELevel", "SSE42",
46 "Enable SSE 4.2 instructions",
48 def Feature3DNow : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
49 "Enable 3DNow! instructions">;
50 def Feature3DNowA : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
51 "Enable 3DNow! Athlon instructions",
53 // All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied
54 // feature, because SSE2 can be disabled (e.g. for compiling OS kernels)
55 // without disabling 64-bit mode.
56 def Feature64Bit : SubtargetFeature<"64bit", "HasX86_64", "true",
57 "Support 64-bit instructions">;
58 def FeatureSlowBTMem : SubtargetFeature<"slow-bt-mem", "IsBTMemSlow", "true",
59 "Bit testing of memory is slow">;
60 def FeatureBreakSSEDep : SubtargetFeature<"break-sse-dep", "BreakSSEDep","true",
61 "Should break SSE partial update dep with load / xorps">;
62 def FeatureSSE4A : SubtargetFeature<"sse4a", "HasSSE4A", "true",
63 "Support SSE 4a instructions">;
65 def FeatureAVX : SubtargetFeature<"avx", "HasAVX", "true",
66 "Enable AVX instructions">;
67 def FeatureFMA3 : SubtargetFeature<"fma3", "HasFMA3", "true",
68 "Enable three-operand fused multiple-add">;
69 def FeatureFMA4 : SubtargetFeature<"fma4", "HasFMA4", "true",
70 "Enable four-operand fused multiple-add">;
72 //===----------------------------------------------------------------------===//
73 // X86 processors supported.
74 //===----------------------------------------------------------------------===//
76 class Proc<string Name, list<SubtargetFeature> Features>
77 : Processor<Name, NoItineraries, Features>;
79 def : Proc<"generic", []>;
80 def : Proc<"i386", []>;
81 def : Proc<"i486", []>;
82 def : Proc<"i586", []>;
83 def : Proc<"pentium", []>;
84 def : Proc<"pentium-mmx", [FeatureMMX]>;
85 def : Proc<"i686", []>;
86 def : Proc<"pentiumpro", [FeatureCMOV]>;
87 def : Proc<"pentium2", [FeatureMMX, FeatureCMOV]>;
88 def : Proc<"pentium3", [FeatureSSE1]>;
89 def : Proc<"pentium-m", [FeatureSSE2, FeatureSlowBTMem]>;
90 def : Proc<"pentium4", [FeatureSSE2]>;
91 def : Proc<"x86-64", [FeatureSSE2, Feature64Bit, FeatureSlowBTMem,
93 def : Proc<"yonah", [FeatureSSE3, FeatureSlowBTMem,
95 def : Proc<"prescott", [FeatureSSE3, FeatureSlowBTMem,
97 def : Proc<"nocona", [FeatureSSE3, Feature64Bit, FeatureSlowBTMem,
99 def : Proc<"core2", [FeatureSSSE3, Feature64Bit, FeatureSlowBTMem,
100 FeatureBreakSSEDep]>;
101 def : Proc<"penryn", [FeatureSSE41, Feature64Bit, FeatureSlowBTMem,
102 FeatureBreakSSEDep]>;
103 def : Proc<"atom", [FeatureSSE3, Feature64Bit, FeatureSlowBTMem,
104 FeatureBreakSSEDep]>;
105 def : Proc<"corei7", [FeatureSSE42, Feature64Bit, FeatureSlowBTMem,
106 FeatureBreakSSEDep]>;
107 def : Proc<"nehalem", [FeatureSSE42, Feature64Bit, FeatureSlowBTMem,
108 FeatureBreakSSEDep]>;
109 // Sandy Bridge does not have FMA
110 def : Proc<"sandybridge", [FeatureSSE42, FeatureAVX, Feature64Bit,
111 FeatureBreakSSEDep]>;
113 def : Proc<"k6", [FeatureMMX]>;
114 def : Proc<"k6-2", [FeatureMMX, Feature3DNow]>;
115 def : Proc<"k6-3", [FeatureMMX, Feature3DNow]>;
116 def : Proc<"athlon", [FeatureMMX, Feature3DNowA, FeatureSlowBTMem]>;
117 def : Proc<"athlon-tbird", [FeatureMMX, Feature3DNowA, FeatureSlowBTMem]>;
118 def : Proc<"athlon-4", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem]>;
119 def : Proc<"athlon-xp", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem]>;
120 def : Proc<"athlon-mp", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem]>;
121 def : Proc<"k8", [FeatureSSE2, Feature3DNowA, Feature64Bit,
123 def : Proc<"opteron", [FeatureSSE2, Feature3DNowA, Feature64Bit,
125 def : Proc<"athlon64", [FeatureSSE2, Feature3DNowA, Feature64Bit,
127 def : Proc<"athlon-fx", [FeatureSSE2, Feature3DNowA, Feature64Bit,
129 def : Proc<"k8-sse3", [FeatureSSE3, Feature3DNowA, Feature64Bit,
131 def : Proc<"opteron-sse3", [FeatureSSE3, Feature3DNowA, Feature64Bit,
133 def : Proc<"athlon64-sse3", [FeatureSSE3, Feature3DNowA, Feature64Bit,
135 def : Proc<"amdfam10", [FeatureSSE3, FeatureSSE4A,
136 Feature3DNowA, Feature64Bit, FeatureSlowBTMem]>;
137 def : Proc<"barcelona", [FeatureSSE3, FeatureSSE4A,
138 Feature3DNowA, Feature64Bit, FeatureSlowBTMem]>;
139 def : Proc<"istanbul", [Feature3DNowA, Feature64Bit, FeatureSSE4A,
141 def : Proc<"shanghai", [Feature3DNowA, Feature64Bit, FeatureSSE4A,
144 def : Proc<"winchip-c6", [FeatureMMX]>;
145 def : Proc<"winchip2", [FeatureMMX, Feature3DNow]>;
146 def : Proc<"c3", [FeatureMMX, Feature3DNow]>;
147 def : Proc<"c3-2", [FeatureSSE1]>;
149 //===----------------------------------------------------------------------===//
150 // Register File Description
151 //===----------------------------------------------------------------------===//
153 include "X86RegisterInfo.td"
155 //===----------------------------------------------------------------------===//
156 // Instruction Descriptions
157 //===----------------------------------------------------------------------===//
159 include "X86InstrInfo.td"
161 def X86InstrInfo : InstrInfo {
163 // Define how we want to layout our TargetSpecific information field... This
164 // should be kept up-to-date with the fields in the X86InstrInfo.h file.
165 let TSFlagsFields = ["FormBits",
175 let TSFlagsShifts = [0,
187 //===----------------------------------------------------------------------===//
188 // Calling Conventions
189 //===----------------------------------------------------------------------===//
191 include "X86CallingConv.td"
194 //===----------------------------------------------------------------------===//
196 //===----------------------------------------------------------------------===//
198 // Currently the X86 assembly parser only supports ATT syntax.
199 def ATTAsmParser : AsmParser {
200 string AsmParserClassName = "ATTAsmParser";
203 // Discard comments in assembly strings.
204 string CommentDelimiter = "#";
206 // Recognize hard coded registers.
207 string RegisterPrefix = "%";
210 // The X86 target supports two different syntaxes for emitting machine code.
211 // This is controlled by the -x86-asm-syntax={att|intel}
212 def ATTAsmWriter : AsmWriter {
213 string AsmWriterClassName = "ATTInstPrinter";
216 def IntelAsmWriter : AsmWriter {
217 string AsmWriterClassName = "IntelInstPrinter";
222 // Information about the instructions...
223 let InstructionSet = X86InstrInfo;
225 let AssemblyParsers = [ATTAsmParser];
227 let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];