1 //===-- X86.td - Target definition file for the Intel X86 --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This is a target description file for the Intel i386 architecture, referred
11 // to here as the "X86" architecture.
13 //===----------------------------------------------------------------------===//
15 // Get the target-independent interfaces which we are implementing...
17 include "llvm/Target/Target.td"
19 //===----------------------------------------------------------------------===//
20 // X86 Subtarget state
23 def Mode64Bit : SubtargetFeature<"64bit-mode", "In64BitMode", "true",
24 "64-bit mode (x86_64)">;
25 def Mode32Bit : SubtargetFeature<"32bit-mode", "In32BitMode", "true",
26 "32-bit mode (80386)">;
27 def Mode16Bit : SubtargetFeature<"16bit-mode", "In16BitMode", "true",
28 "16-bit mode (i8086)">;
30 //===----------------------------------------------------------------------===//
31 // X86 Subtarget features
32 //===----------------------------------------------------------------------===//
34 def FeatureCMOV : SubtargetFeature<"cmov","HasCMov", "true",
35 "Enable conditional move instructions">;
37 def FeaturePOPCNT : SubtargetFeature<"popcnt", "HasPOPCNT", "true",
38 "Support POPCNT instruction">;
40 def FeatureXSAVE : SubtargetFeature<"xsave", "HasXSAVE", "true",
41 "Support xsave instructions">;
43 def FeatureXSAVEOPT: SubtargetFeature<"xsaveopt", "HasXSAVEOPT", "true",
44 "Support xsaveopt instructions">;
46 def FeatureXSAVEC : SubtargetFeature<"xsavec", "HasXSAVEC", "true",
47 "Support xsavec instructions">;
49 def FeatureXSAVES : SubtargetFeature<"xsaves", "HasXSAVES", "true",
50 "Support xsaves instructions">;
52 // The MMX subtarget feature is separate from the rest of the SSE features
53 // because it's important (for odd compatibility reasons) to be able to
54 // turn it off explicitly while allowing SSE+ to be on.
55 def FeatureMMX : SubtargetFeature<"mmx","HasMMX", "true",
56 "Enable MMX instructions">;
58 def FeatureSSE1 : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
59 "Enable SSE instructions",
60 // SSE codegen depends on cmovs, and all
61 // SSE1+ processors support them.
63 def FeatureSSE2 : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",
64 "Enable SSE2 instructions",
66 def FeatureSSE3 : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
67 "Enable SSE3 instructions",
69 def FeatureSSSE3 : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3",
70 "Enable SSSE3 instructions",
72 def FeatureSSE41 : SubtargetFeature<"sse4.1", "X86SSELevel", "SSE41",
73 "Enable SSE 4.1 instructions",
75 def FeatureSSE42 : SubtargetFeature<"sse4.2", "X86SSELevel", "SSE42",
76 "Enable SSE 4.2 instructions",
78 def Feature3DNow : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
79 "Enable 3DNow! instructions",
81 def Feature3DNowA : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
82 "Enable 3DNow! Athlon instructions",
84 // All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied
85 // feature, because SSE2 can be disabled (e.g. for compiling OS kernels)
86 // without disabling 64-bit mode.
87 def Feature64Bit : SubtargetFeature<"64bit", "HasX86_64", "true",
88 "Support 64-bit instructions",
90 def FeatureCMPXCHG16B : SubtargetFeature<"cx16", "HasCmpxchg16b", "true",
91 "64-bit with cmpxchg16b",
93 def FeatureSlowBTMem : SubtargetFeature<"slow-bt-mem", "IsBTMemSlow", "true",
94 "Bit testing of memory is slow">;
95 def FeatureSlowSHLD : SubtargetFeature<"slow-shld", "IsSHLDSlow", "true",
96 "SHLD instruction is slow">;
97 // FIXME: This should not apply to CPUs that do not have SSE.
98 def FeatureSlowUAMem16 : SubtargetFeature<"slow-unaligned-mem-16",
99 "IsUAMem16Slow", "true",
100 "Slow unaligned 16-byte memory access">;
101 def FeatureSlowUAMem32 : SubtargetFeature<"slow-unaligned-mem-32",
102 "IsUAMem32Slow", "true",
103 "Slow unaligned 32-byte memory access">;
104 def FeatureSSE4A : SubtargetFeature<"sse4a", "HasSSE4A", "true",
105 "Support SSE 4a instructions",
108 def FeatureAVX : SubtargetFeature<"avx", "X86SSELevel", "AVX",
109 "Enable AVX instructions",
111 def FeatureAVX2 : SubtargetFeature<"avx2", "X86SSELevel", "AVX2",
112 "Enable AVX2 instructions",
114 def FeatureAVX512 : SubtargetFeature<"avx512f", "X86SSELevel", "AVX512F",
115 "Enable AVX-512 instructions",
117 def FeatureERI : SubtargetFeature<"avx512er", "HasERI", "true",
118 "Enable AVX-512 Exponential and Reciprocal Instructions",
120 def FeatureCDI : SubtargetFeature<"avx512cd", "HasCDI", "true",
121 "Enable AVX-512 Conflict Detection Instructions",
123 def FeaturePFI : SubtargetFeature<"avx512pf", "HasPFI", "true",
124 "Enable AVX-512 PreFetch Instructions",
126 def FeatureDQI : SubtargetFeature<"avx512dq", "HasDQI", "true",
127 "Enable AVX-512 Doubleword and Quadword Instructions",
129 def FeatureBWI : SubtargetFeature<"avx512bw", "HasBWI", "true",
130 "Enable AVX-512 Byte and Word Instructions",
132 def FeatureVLX : SubtargetFeature<"avx512vl", "HasVLX", "true",
133 "Enable AVX-512 Vector Length eXtensions",
135 def FeaturePCLMUL : SubtargetFeature<"pclmul", "HasPCLMUL", "true",
136 "Enable packed carry-less multiplication instructions",
138 def FeatureFMA : SubtargetFeature<"fma", "HasFMA", "true",
139 "Enable three-operand fused multiple-add",
141 def FeatureFMA4 : SubtargetFeature<"fma4", "HasFMA4", "true",
142 "Enable four-operand fused multiple-add",
143 [FeatureAVX, FeatureSSE4A]>;
144 def FeatureXOP : SubtargetFeature<"xop", "HasXOP", "true",
145 "Enable XOP instructions",
147 def FeatureSSEUnalignedMem : SubtargetFeature<"sse-unaligned-mem",
148 "HasSSEUnalignedMem", "true",
149 "Allow unaligned memory operands with SSE instructions">;
150 def FeatureAES : SubtargetFeature<"aes", "HasAES", "true",
151 "Enable AES instructions",
153 def FeatureTBM : SubtargetFeature<"tbm", "HasTBM", "true",
154 "Enable TBM instructions">;
155 def FeatureMOVBE : SubtargetFeature<"movbe", "HasMOVBE", "true",
156 "Support MOVBE instruction">;
157 def FeatureRDRAND : SubtargetFeature<"rdrnd", "HasRDRAND", "true",
158 "Support RDRAND instruction">;
159 def FeatureF16C : SubtargetFeature<"f16c", "HasF16C", "true",
160 "Support 16-bit floating point conversion instructions",
162 def FeatureFSGSBase : SubtargetFeature<"fsgsbase", "HasFSGSBase", "true",
163 "Support FS/GS Base instructions">;
164 def FeatureLZCNT : SubtargetFeature<"lzcnt", "HasLZCNT", "true",
165 "Support LZCNT instruction">;
166 def FeatureBMI : SubtargetFeature<"bmi", "HasBMI", "true",
167 "Support BMI instructions">;
168 def FeatureBMI2 : SubtargetFeature<"bmi2", "HasBMI2", "true",
169 "Support BMI2 instructions">;
170 def FeatureRTM : SubtargetFeature<"rtm", "HasRTM", "true",
171 "Support RTM instructions">;
172 def FeatureHLE : SubtargetFeature<"hle", "HasHLE", "true",
174 def FeatureADX : SubtargetFeature<"adx", "HasADX", "true",
175 "Support ADX instructions">;
176 def FeatureSHA : SubtargetFeature<"sha", "HasSHA", "true",
177 "Enable SHA instructions",
179 def FeaturePRFCHW : SubtargetFeature<"prfchw", "HasPRFCHW", "true",
180 "Support PRFCHW instructions">;
181 def FeatureRDSEED : SubtargetFeature<"rdseed", "HasRDSEED", "true",
182 "Support RDSEED instruction">;
183 def FeatureMPX : SubtargetFeature<"mpx", "HasMPX", "true",
184 "Support MPX instructions">;
185 def FeatureLEAForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true",
186 "Use LEA for adjusting the stack pointer">;
187 def FeatureSlowDivide32 : SubtargetFeature<"idivl-to-divb",
188 "HasSlowDivide32", "true",
189 "Use 8-bit divide for positive values less than 256">;
190 def FeatureSlowDivide64 : SubtargetFeature<"idivq-to-divw",
191 "HasSlowDivide64", "true",
192 "Use 16-bit divide for positive values less than 65536">;
193 def FeaturePadShortFunctions : SubtargetFeature<"pad-short-functions",
194 "PadShortFunctions", "true",
195 "Pad short functions">;
196 // TODO: This feature ought to be renamed.
197 // What it really refers to are CPUs for which certain instructions
198 // (which ones besides the example below?) are microcoded.
199 // The best examples of this are the memory forms of CALL and PUSH
200 // instructions, which should be avoided in favor of a MOV + register CALL/PUSH.
201 def FeatureCallRegIndirect : SubtargetFeature<"call-reg-indirect",
202 "CallRegIndirect", "true",
203 "Call register indirect">;
204 def FeatureLEAUsesAG : SubtargetFeature<"lea-uses-ag", "LEAUsesAG", "true",
205 "LEA instruction needs inputs at AG stage">;
206 def FeatureSlowLEA : SubtargetFeature<"slow-lea", "SlowLEA", "true",
207 "LEA instruction with certain arguments is slow">;
208 def FeatureSlowIncDec : SubtargetFeature<"slow-incdec", "SlowIncDec", "true",
209 "INC and DEC instructions are slower than ADD and SUB">;
211 : SubtargetFeature<"soft-float", "UseSoftFloat", "true",
212 "Use software floating point features.">;
214 //===----------------------------------------------------------------------===//
215 // X86 processors supported.
216 //===----------------------------------------------------------------------===//
218 include "X86Schedule.td"
220 def ProcIntelAtom : SubtargetFeature<"atom", "X86ProcFamily", "IntelAtom",
221 "Intel Atom processors">;
222 def ProcIntelSLM : SubtargetFeature<"slm", "X86ProcFamily", "IntelSLM",
223 "Intel Silvermont processors">;
225 class Proc<string Name, list<SubtargetFeature> Features>
226 : ProcessorModel<Name, GenericModel, Features>;
228 def : Proc<"generic", [FeatureSlowUAMem16]>;
229 def : Proc<"i386", [FeatureSlowUAMem16]>;
230 def : Proc<"i486", [FeatureSlowUAMem16]>;
231 def : Proc<"i586", [FeatureSlowUAMem16]>;
232 def : Proc<"pentium", [FeatureSlowUAMem16]>;
233 def : Proc<"pentium-mmx", [FeatureSlowUAMem16, FeatureMMX]>;
234 def : Proc<"i686", [FeatureSlowUAMem16]>;
235 def : Proc<"pentiumpro", [FeatureSlowUAMem16, FeatureCMOV]>;
236 def : Proc<"pentium2", [FeatureSlowUAMem16, FeatureMMX, FeatureCMOV]>;
237 def : Proc<"pentium3", [FeatureSlowUAMem16, FeatureMMX, FeatureSSE1]>;
238 def : Proc<"pentium3m", [FeatureSlowUAMem16, FeatureMMX, FeatureSSE1,
240 def : Proc<"pentium-m", [FeatureSlowUAMem16, FeatureMMX, FeatureSSE2,
242 def : Proc<"pentium4", [FeatureSlowUAMem16, FeatureMMX, FeatureSSE2]>;
243 def : Proc<"pentium4m", [FeatureSlowUAMem16, FeatureMMX, FeatureSSE2,
247 def : ProcessorModel<
248 "yonah", SandyBridgeModel,
249 [ FeatureSlowUAMem16, FeatureMMX, FeatureSSE3, FeatureSlowBTMem ]>;
252 def : Proc<"prescott",
253 [ FeatureSlowUAMem16, FeatureMMX, FeatureSSE3, FeatureSlowBTMem ]>;
254 def : Proc<"nocona", [
262 // Intel Core 2 Solo/Duo.
263 def : ProcessorModel<"core2", SandyBridgeModel, [
270 def : ProcessorModel<"penryn", SandyBridgeModel, [
279 class BonnellProc<string Name> : ProcessorModel<Name, AtomModel, [
290 FeatureCallRegIndirect,
292 FeaturePadShortFunctions
294 def : BonnellProc<"bonnell">;
295 def : BonnellProc<"atom">; // Pin the generic name to the baseline.
297 class SilvermontProc<string Name> : ProcessorModel<Name, SLMModel, [
307 FeatureCallRegIndirect,
313 def : SilvermontProc<"silvermont">;
314 def : SilvermontProc<"slm">; // Legacy alias.
316 // "Arrandale" along with corei3 and corei5
317 class NehalemProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
324 def : NehalemProc<"nehalem">;
325 def : NehalemProc<"corei7">;
327 // Westmere is a similar machine to nehalem with some additional features.
328 // Westmere is the corei3/i5/i7 path from nehalem to sandybridge
329 class WestmereProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
338 def : WestmereProc<"westmere">;
340 // SSE is not listed here since llvm treats AVX as a reimplementation of SSE,
341 // rather than a superset.
342 class SandyBridgeProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
354 def : SandyBridgeProc<"sandybridge">;
355 def : SandyBridgeProc<"corei7-avx">; // Legacy alias.
357 class IvyBridgeProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
372 def : IvyBridgeProc<"ivybridge">;
373 def : IvyBridgeProc<"core-avx-i">; // Legacy alias.
375 class HaswellProc<string Name> : ProcessorModel<Name, HaswellModel, [
397 def : HaswellProc<"haswell">;
398 def : HaswellProc<"core-avx2">; // Legacy alias.
400 class BroadwellProc<string Name> : ProcessorModel<Name, HaswellModel, [
424 def : BroadwellProc<"broadwell">;
426 // FIXME: define KNL model
427 class KnightsLandingProc<string Name> : ProcessorModel<Name, HaswellModel, [
452 def : KnightsLandingProc<"knl">;
454 // FIXME: define SKX model
455 class SkylakeProc<string Name> : ProcessorModel<Name, HaswellModel, [
486 def : SkylakeProc<"skylake">;
487 def : SkylakeProc<"skx">; // Legacy alias.
492 def : Proc<"k6", [FeatureSlowUAMem16, FeatureMMX]>;
493 def : Proc<"k6-2", [FeatureSlowUAMem16, Feature3DNow]>;
494 def : Proc<"k6-3", [FeatureSlowUAMem16, Feature3DNow]>;
495 def : Proc<"athlon", [FeatureSlowUAMem16, Feature3DNowA,
496 FeatureSlowBTMem, FeatureSlowSHLD]>;
497 def : Proc<"athlon-tbird", [FeatureSlowUAMem16, Feature3DNowA,
498 FeatureSlowBTMem, FeatureSlowSHLD]>;
499 def : Proc<"athlon-4", [FeatureSlowUAMem16, FeatureSSE1, Feature3DNowA,
500 FeatureSlowBTMem, FeatureSlowSHLD]>;
501 def : Proc<"athlon-xp", [FeatureSlowUAMem16, FeatureSSE1, Feature3DNowA,
502 FeatureSlowBTMem, FeatureSlowSHLD]>;
503 def : Proc<"athlon-mp", [FeatureSlowUAMem16, FeatureSSE1, Feature3DNowA,
504 FeatureSlowBTMem, FeatureSlowSHLD]>;
505 def : Proc<"k8", [FeatureSlowUAMem16, FeatureSSE2, Feature3DNowA,
506 Feature64Bit, FeatureSlowBTMem,
508 def : Proc<"opteron", [FeatureSlowUAMem16, FeatureSSE2, Feature3DNowA,
509 Feature64Bit, FeatureSlowBTMem,
511 def : Proc<"athlon64", [FeatureSlowUAMem16, FeatureSSE2, Feature3DNowA,
512 Feature64Bit, FeatureSlowBTMem,
514 def : Proc<"athlon-fx", [FeatureSlowUAMem16, FeatureSSE2, Feature3DNowA,
515 Feature64Bit, FeatureSlowBTMem,
517 def : Proc<"k8-sse3", [FeatureSlowUAMem16, FeatureSSE3, Feature3DNowA,
518 FeatureCMPXCHG16B, FeatureSlowBTMem,
520 def : Proc<"opteron-sse3", [FeatureSlowUAMem16, FeatureSSE3, Feature3DNowA,
521 FeatureCMPXCHG16B, FeatureSlowBTMem,
523 def : Proc<"athlon64-sse3", [FeatureSlowUAMem16, FeatureSSE3, Feature3DNowA,
524 FeatureCMPXCHG16B, FeatureSlowBTMem,
526 def : Proc<"amdfam10", [FeatureSSE4A,
527 Feature3DNowA, FeatureCMPXCHG16B, FeatureLZCNT,
528 FeaturePOPCNT, FeatureSlowBTMem,
530 def : Proc<"barcelona", [FeatureSSE4A,
531 Feature3DNowA, FeatureCMPXCHG16B, FeatureLZCNT,
532 FeaturePOPCNT, FeatureSlowBTMem,
536 def : Proc<"btver1", [
549 def : ProcessorModel<"btver2", BtVer2Model, [
568 def : Proc<"bdver1", [
584 def : Proc<"bdver2", [
605 def : Proc<"bdver3", [
628 def : Proc<"bdver4", [
649 def : Proc<"geode", [FeatureSlowUAMem16, Feature3DNowA]>;
651 def : Proc<"winchip-c6", [FeatureSlowUAMem16, FeatureMMX]>;
652 def : Proc<"winchip2", [FeatureSlowUAMem16, Feature3DNow]>;
653 def : Proc<"c3", [FeatureSlowUAMem16, Feature3DNow]>;
654 def : Proc<"c3-2", [ FeatureSlowUAMem16, FeatureMMX, FeatureSSE1 ]>;
656 // We also provide a generic 64-bit specific x86 processor model which tries to
657 // be good for modern chips without enabling instruction set encodings past the
658 // basic SSE2 and 64-bit ones. It disables slow things from any mainstream and
659 // modern 64-bit x86 chip, and enables features that are generally beneficial.
661 // We currently use the Sandy Bridge model as the default scheduling model as
662 // we use it across Nehalem, Westmere, Sandy Bridge, and Ivy Bridge which
663 // covers a huge swath of x86 processors. If there are specific scheduling
664 // knobs which need to be tuned differently for AMD chips, we might consider
665 // forming a common base for them.
666 def : ProcessorModel<
667 "x86-64", SandyBridgeModel,
668 [ FeatureMMX, FeatureSSE2, Feature64Bit, FeatureSlowBTMem ]>;
670 //===----------------------------------------------------------------------===//
671 // Register File Description
672 //===----------------------------------------------------------------------===//
674 include "X86RegisterInfo.td"
676 //===----------------------------------------------------------------------===//
677 // Instruction Descriptions
678 //===----------------------------------------------------------------------===//
680 include "X86InstrInfo.td"
682 def X86InstrInfo : InstrInfo;
684 //===----------------------------------------------------------------------===//
685 // Calling Conventions
686 //===----------------------------------------------------------------------===//
688 include "X86CallingConv.td"
691 //===----------------------------------------------------------------------===//
693 //===----------------------------------------------------------------------===//
695 def ATTAsmParser : AsmParser {
696 string AsmParserClassName = "AsmParser";
699 def ATTAsmParserVariant : AsmParserVariant {
705 // Discard comments in assembly strings.
706 string CommentDelimiter = "#";
708 // Recognize hard coded registers.
709 string RegisterPrefix = "%";
712 def IntelAsmParserVariant : AsmParserVariant {
716 string Name = "intel";
718 // Discard comments in assembly strings.
719 string CommentDelimiter = ";";
721 // Recognize hard coded registers.
722 string RegisterPrefix = "";
725 //===----------------------------------------------------------------------===//
727 //===----------------------------------------------------------------------===//
729 // The X86 target supports two different syntaxes for emitting machine code.
730 // This is controlled by the -x86-asm-syntax={att|intel}
731 def ATTAsmWriter : AsmWriter {
732 string AsmWriterClassName = "ATTInstPrinter";
735 def IntelAsmWriter : AsmWriter {
736 string AsmWriterClassName = "IntelInstPrinter";
741 // Information about the instructions...
742 let InstructionSet = X86InstrInfo;
743 let AssemblyParsers = [ATTAsmParser];
744 let AssemblyParserVariants = [ATTAsmParserVariant, IntelAsmParserVariant];
745 let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];