1 //===- X86.td - Target definition file for the Intel X86 ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This is a target description file for the Intel i386 architecture, referred
11 // to here as the "X86" architecture.
13 //===----------------------------------------------------------------------===//
15 // Get the target-independent interfaces which we are implementing...
17 include "llvm/Target/Target.td"
19 //===----------------------------------------------------------------------===//
20 // X86 Subtarget state.
23 def Mode64Bit : SubtargetFeature<"64bit-mode", "In64BitMode", "true",
24 "64-bit mode (x86_64)">;
26 //===----------------------------------------------------------------------===//
27 // X86 Subtarget features.
28 //===----------------------------------------------------------------------===//
30 def FeatureCMOV : SubtargetFeature<"cmov","HasCMov", "true",
31 "Enable conditional move instructions">;
33 def FeaturePOPCNT : SubtargetFeature<"popcnt", "HasPOPCNT", "true",
34 "Support POPCNT instruction">;
37 def FeatureMMX : SubtargetFeature<"mmx","X86SSELevel", "MMX",
38 "Enable MMX instructions">;
39 def FeatureSSE1 : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
40 "Enable SSE instructions",
41 // SSE codegen depends on cmovs, and all
42 // SSE1+ processors support them.
43 [FeatureMMX, FeatureCMOV]>;
44 def FeatureSSE2 : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",
45 "Enable SSE2 instructions",
47 def FeatureSSE3 : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
48 "Enable SSE3 instructions",
50 def FeatureSSSE3 : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3",
51 "Enable SSSE3 instructions",
53 def FeatureSSE41 : SubtargetFeature<"sse41", "X86SSELevel", "SSE41",
54 "Enable SSE 4.1 instructions",
56 def FeatureSSE42 : SubtargetFeature<"sse42", "X86SSELevel", "SSE42",
57 "Enable SSE 4.2 instructions",
59 def Feature3DNow : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
60 "Enable 3DNow! instructions",
62 def Feature3DNowA : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
63 "Enable 3DNow! Athlon instructions",
65 // All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied
66 // feature, because SSE2 can be disabled (e.g. for compiling OS kernels)
67 // without disabling 64-bit mode.
68 def Feature64Bit : SubtargetFeature<"64bit", "HasX86_64", "true",
69 "Support 64-bit instructions",
71 def FeatureCMPXCHG16B : SubtargetFeature<"cmpxchg16b", "HasCmpxchg16b", "true",
72 "64-bit with cmpxchg16b",
74 def FeatureSlowBTMem : SubtargetFeature<"slow-bt-mem", "IsBTMemSlow", "true",
75 "Bit testing of memory is slow">;
76 def FeatureFastUAMem : SubtargetFeature<"fast-unaligned-mem",
77 "IsUAMemFast", "true",
78 "Fast unaligned memory access">;
79 def FeatureSSE4A : SubtargetFeature<"sse4a", "HasSSE4A", "true",
80 "Support SSE 4a instructions",
83 def FeatureAVX : SubtargetFeature<"avx", "X86SSELevel", "AVX",
84 "Enable AVX instructions",
86 def FeatureAVX2 : SubtargetFeature<"avx2", "X86SSELevel", "AVX2",
87 "Enable AVX2 instructions",
89 def FeatureCLMUL : SubtargetFeature<"clmul", "HasCLMUL", "true",
90 "Enable carry-less multiplication instructions">;
91 def FeatureFMA3 : SubtargetFeature<"fma3", "HasFMA3", "true",
92 "Enable three-operand fused multiple-add",
94 def FeatureFMA4 : SubtargetFeature<"fma4", "HasFMA4", "true",
95 "Enable four-operand fused multiple-add",
97 def FeatureXOP : SubtargetFeature<"xop", "HasXOP", "true",
98 "Enable XOP instructions">;
99 def FeatureVectorUAMem : SubtargetFeature<"vector-unaligned-mem",
100 "HasVectorUAMem", "true",
101 "Allow unaligned memory operands on vector/SIMD instructions">;
102 def FeatureAES : SubtargetFeature<"aes", "HasAES", "true",
103 "Enable AES instructions">;
104 def FeatureMOVBE : SubtargetFeature<"movbe", "HasMOVBE", "true",
105 "Support MOVBE instruction">;
106 def FeatureRDRAND : SubtargetFeature<"rdrand", "HasRDRAND", "true",
107 "Support RDRAND instruction">;
108 def FeatureF16C : SubtargetFeature<"f16c", "HasF16C", "true",
109 "Support 16-bit floating point conversion instructions">;
110 def FeatureFSGSBase : SubtargetFeature<"fsgsbase", "HasFSGSBase", "true",
111 "Support FS/GS Base instructions">;
112 def FeatureLZCNT : SubtargetFeature<"lzcnt", "HasLZCNT", "true",
113 "Support LZCNT instruction">;
114 def FeatureBMI : SubtargetFeature<"bmi", "HasBMI", "true",
115 "Support BMI instructions">;
116 def FeatureBMI2 : SubtargetFeature<"bmi2", "HasBMI2", "true",
117 "Support BMI2 instructions">;
119 //===----------------------------------------------------------------------===//
120 // X86 processors supported.
121 //===----------------------------------------------------------------------===//
123 class Proc<string Name, list<SubtargetFeature> Features>
124 : Processor<Name, NoItineraries, Features>;
126 def : Proc<"generic", []>;
127 def : Proc<"i386", []>;
128 def : Proc<"i486", []>;
129 def : Proc<"i586", []>;
130 def : Proc<"pentium", []>;
131 def : Proc<"pentium-mmx", [FeatureMMX]>;
132 def : Proc<"i686", []>;
133 def : Proc<"pentiumpro", [FeatureCMOV]>;
134 def : Proc<"pentium2", [FeatureMMX, FeatureCMOV]>;
135 def : Proc<"pentium3", [FeatureSSE1]>;
136 def : Proc<"pentium3m", [FeatureSSE1, FeatureSlowBTMem]>;
137 def : Proc<"pentium-m", [FeatureSSE2, FeatureSlowBTMem]>;
138 def : Proc<"pentium4", [FeatureSSE2]>;
139 def : Proc<"pentium4m", [FeatureSSE2, FeatureSlowBTMem]>;
140 def : Proc<"x86-64", [FeatureSSE2, Feature64Bit, FeatureSlowBTMem]>;
141 def : Proc<"yonah", [FeatureSSE3, FeatureSlowBTMem]>;
142 def : Proc<"prescott", [FeatureSSE3, FeatureSlowBTMem]>;
143 def : Proc<"nocona", [FeatureSSE3, FeatureCMPXCHG16B,
145 def : Proc<"core2", [FeatureSSSE3, FeatureCMPXCHG16B,
147 def : Proc<"penryn", [FeatureSSE41, FeatureCMPXCHG16B,
149 def : Proc<"atom", [FeatureSSE3, FeatureCMPXCHG16B, FeatureMOVBE,
151 // "Arrandale" along with corei3 and corei5
152 def : Proc<"corei7", [FeatureSSE42, FeatureCMPXCHG16B,
153 FeatureSlowBTMem, FeatureFastUAMem,
154 FeaturePOPCNT, FeatureAES]>;
155 def : Proc<"nehalem", [FeatureSSE42, FeatureCMPXCHG16B,
156 FeatureSlowBTMem, FeatureFastUAMem,
158 // Westmere is a similar machine to nehalem with some additional features.
159 // Westmere is the corei3/i5/i7 path from nehalem to sandybridge
160 def : Proc<"westmere", [FeatureSSE42, FeatureCMPXCHG16B,
161 FeatureSlowBTMem, FeatureFastUAMem,
162 FeaturePOPCNT, FeatureAES, FeatureCLMUL]>;
164 // SSE is not listed here since llvm treats AVX as a reimplementation of SSE,
165 // rather than a superset.
166 // FIXME: Disabling AVX for now since it's not ready.
167 def : Proc<"corei7-avx", [FeatureSSE42, FeatureCMPXCHG16B, FeaturePOPCNT,
168 FeatureAES, FeatureCLMUL]>;
170 def : Proc<"core-avx-i", [FeatureSSE42, FeatureCMPXCHG16B, FeaturePOPCNT,
171 FeatureAES, FeatureCLMUL,
172 FeatureRDRAND, FeatureF16C, FeatureFSGSBase]>;
175 // FIXME: Disabling AVX/AVX2/FMA3 for now since it's not ready.
176 def : Proc<"core-avx2", [FeatureSSE42, FeatureCMPXCHG16B, FeaturePOPCNT,
177 FeatureAES, FeatureCLMUL, FeatureRDRAND,
178 FeatureF16C, FeatureFSGSBase,
179 FeatureMOVBE, FeatureLZCNT, FeatureBMI,
182 def : Proc<"k6", [FeatureMMX]>;
183 def : Proc<"k6-2", [Feature3DNow]>;
184 def : Proc<"k6-3", [Feature3DNow]>;
185 def : Proc<"athlon", [Feature3DNowA, FeatureSlowBTMem]>;
186 def : Proc<"athlon-tbird", [Feature3DNowA, FeatureSlowBTMem]>;
187 def : Proc<"athlon-4", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem]>;
188 def : Proc<"athlon-xp", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem]>;
189 def : Proc<"athlon-mp", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem]>;
190 def : Proc<"k8", [FeatureSSE2, Feature3DNowA, Feature64Bit,
192 def : Proc<"opteron", [FeatureSSE2, Feature3DNowA, Feature64Bit,
194 def : Proc<"athlon64", [FeatureSSE2, Feature3DNowA, Feature64Bit,
196 def : Proc<"athlon-fx", [FeatureSSE2, Feature3DNowA, Feature64Bit,
198 def : Proc<"k8-sse3", [FeatureSSE3, Feature3DNowA, FeatureCMPXCHG16B,
200 def : Proc<"opteron-sse3", [FeatureSSE3, Feature3DNowA, FeatureCMPXCHG16B,
202 def : Proc<"athlon64-sse3", [FeatureSSE3, Feature3DNowA, FeatureCMPXCHG16B,
204 def : Proc<"amdfam10", [FeatureSSE3, FeatureSSE4A,
205 Feature3DNowA, FeatureCMPXCHG16B, FeatureLZCNT,
206 FeaturePOPCNT, FeatureSlowBTMem]>;
208 def : Proc<"btver1", [FeatureSSSE3, FeatureSSE4A, FeatureCMPXCHG16B,
209 FeatureLZCNT, FeaturePOPCNT]>;
210 // FIXME: Disabling AVX/FMA4 for now since it's not ready.
212 def : Proc<"bdver1", [FeatureSSE42, FeatureSSE4A, FeatureCMPXCHG16B,
213 FeatureAES, FeatureCLMUL,
214 FeatureXOP, FeatureLZCNT, FeaturePOPCNT]>;
215 // Enhanced Bulldozer
216 def : Proc<"bdver2", [FeatureSSE42, FeatureSSE4A, FeatureCMPXCHG16B,
217 FeatureAES, FeatureCLMUL,
218 FeatureXOP, FeatureF16C, FeatureLZCNT,
219 FeaturePOPCNT, FeatureBMI]>;
221 def : Proc<"winchip-c6", [FeatureMMX]>;
222 def : Proc<"winchip2", [Feature3DNow]>;
223 def : Proc<"c3", [Feature3DNow]>;
224 def : Proc<"c3-2", [FeatureSSE1]>;
226 //===----------------------------------------------------------------------===//
227 // Register File Description
228 //===----------------------------------------------------------------------===//
230 include "X86RegisterInfo.td"
232 //===----------------------------------------------------------------------===//
233 // Instruction Descriptions
234 //===----------------------------------------------------------------------===//
236 include "X86InstrInfo.td"
238 def X86InstrInfo : InstrInfo;
240 //===----------------------------------------------------------------------===//
241 // Calling Conventions
242 //===----------------------------------------------------------------------===//
244 include "X86CallingConv.td"
247 //===----------------------------------------------------------------------===//
249 //===----------------------------------------------------------------------===//
251 // Currently the X86 assembly parser only supports ATT syntax.
252 def ATTAsmParser : AsmParser {
253 string AsmParserClassName = "ATTAsmParser";
256 def ATTAsmParserVariant : AsmParserVariant {
259 // Discard comments in assembly strings.
260 string CommentDelimiter = "#";
262 // Recognize hard coded registers.
263 string RegisterPrefix = "%";
266 def IntelAsmParserVariant : AsmParserVariant {
269 // Discard comments in assembly strings.
270 string CommentDelimiter = ";";
272 // Recognize hard coded registers.
273 string RegisterPrefix = "";
276 //===----------------------------------------------------------------------===//
278 //===----------------------------------------------------------------------===//
280 // The X86 target supports two different syntaxes for emitting machine code.
281 // This is controlled by the -x86-asm-syntax={att|intel}
282 def ATTAsmWriter : AsmWriter {
283 string AsmWriterClassName = "ATTInstPrinter";
285 bit isMCAsmWriter = 1;
287 def IntelAsmWriter : AsmWriter {
288 string AsmWriterClassName = "IntelInstPrinter";
290 bit isMCAsmWriter = 1;
294 // Information about the instructions...
295 let InstructionSet = X86InstrInfo;
296 let AssemblyParsers = [ATTAsmParser];
297 let AssemblyParserVariants = [ATTAsmParserVariant, IntelAsmParserVariant];
298 let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];