1 //===-- X86.td - Target definition file for the Intel X86 --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This is a target description file for the Intel i386 architecture, referred
11 // to here as the "X86" architecture.
13 //===----------------------------------------------------------------------===//
15 // Get the target-independent interfaces which we are implementing...
17 include "llvm/Target/Target.td"
19 //===----------------------------------------------------------------------===//
20 // X86 Subtarget state
23 def Mode64Bit : SubtargetFeature<"64bit-mode", "In64BitMode", "true",
24 "64-bit mode (x86_64)">;
25 def Mode32Bit : SubtargetFeature<"32bit-mode", "In32BitMode", "true",
26 "32-bit mode (80386)">;
27 def Mode16Bit : SubtargetFeature<"16bit-mode", "In16BitMode", "true",
28 "16-bit mode (i8086)">;
30 //===----------------------------------------------------------------------===//
31 // X86 Subtarget features
32 //===----------------------------------------------------------------------===//
34 def FeatureCMOV : SubtargetFeature<"cmov","HasCMov", "true",
35 "Enable conditional move instructions">;
37 def FeaturePOPCNT : SubtargetFeature<"popcnt", "HasPOPCNT", "true",
38 "Support POPCNT instruction">;
40 def FeatureFXSR : SubtargetFeature<"fxsr", "HasFXSR", "true",
41 "Support fxsave/fxrestore instructions">;
43 def FeatureXSAVE : SubtargetFeature<"xsave", "HasXSAVE", "true",
44 "Support xsave instructions">;
46 def FeatureXSAVEOPT: SubtargetFeature<"xsaveopt", "HasXSAVEOPT", "true",
47 "Support xsaveopt instructions">;
49 def FeatureXSAVEC : SubtargetFeature<"xsavec", "HasXSAVEC", "true",
50 "Support xsavec instructions">;
52 def FeatureXSAVES : SubtargetFeature<"xsaves", "HasXSAVES", "true",
53 "Support xsaves instructions">;
55 // The MMX subtarget feature is separate from the rest of the SSE features
56 // because it's important (for odd compatibility reasons) to be able to
57 // turn it off explicitly while allowing SSE+ to be on.
58 def FeatureMMX : SubtargetFeature<"mmx","HasMMX", "true",
59 "Enable MMX instructions">;
61 def FeatureSSE1 : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
62 "Enable SSE instructions",
63 // SSE codegen depends on cmovs, and all
64 // SSE1+ processors support them.
66 def FeatureSSE2 : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",
67 "Enable SSE2 instructions",
69 def FeatureSSE3 : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
70 "Enable SSE3 instructions",
72 def FeatureSSSE3 : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3",
73 "Enable SSSE3 instructions",
75 def FeatureSSE41 : SubtargetFeature<"sse4.1", "X86SSELevel", "SSE41",
76 "Enable SSE 4.1 instructions",
78 def FeatureSSE42 : SubtargetFeature<"sse4.2", "X86SSELevel", "SSE42",
79 "Enable SSE 4.2 instructions",
81 def Feature3DNow : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
82 "Enable 3DNow! instructions",
84 def Feature3DNowA : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
85 "Enable 3DNow! Athlon instructions",
87 // All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied
88 // feature, because SSE2 can be disabled (e.g. for compiling OS kernels)
89 // without disabling 64-bit mode.
90 def Feature64Bit : SubtargetFeature<"64bit", "HasX86_64", "true",
91 "Support 64-bit instructions",
93 def FeatureCMPXCHG16B : SubtargetFeature<"cx16", "HasCmpxchg16b", "true",
94 "64-bit with cmpxchg16b",
96 def FeatureSlowBTMem : SubtargetFeature<"slow-bt-mem", "IsBTMemSlow", "true",
97 "Bit testing of memory is slow">;
98 def FeatureSlowSHLD : SubtargetFeature<"slow-shld", "IsSHLDSlow", "true",
99 "SHLD instruction is slow">;
100 // FIXME: This should not apply to CPUs that do not have SSE.
101 def FeatureSlowUAMem16 : SubtargetFeature<"slow-unaligned-mem-16",
102 "IsUAMem16Slow", "true",
103 "Slow unaligned 16-byte memory access">;
104 def FeatureSlowUAMem32 : SubtargetFeature<"slow-unaligned-mem-32",
105 "IsUAMem32Slow", "true",
106 "Slow unaligned 32-byte memory access">;
107 def FeatureSSE4A : SubtargetFeature<"sse4a", "HasSSE4A", "true",
108 "Support SSE 4a instructions",
111 def FeatureAVX : SubtargetFeature<"avx", "X86SSELevel", "AVX",
112 "Enable AVX instructions",
114 def FeatureAVX2 : SubtargetFeature<"avx2", "X86SSELevel", "AVX2",
115 "Enable AVX2 instructions",
117 def FeatureAVX512 : SubtargetFeature<"avx512f", "X86SSELevel", "AVX512F",
118 "Enable AVX-512 instructions",
120 def FeatureERI : SubtargetFeature<"avx512er", "HasERI", "true",
121 "Enable AVX-512 Exponential and Reciprocal Instructions",
123 def FeatureCDI : SubtargetFeature<"avx512cd", "HasCDI", "true",
124 "Enable AVX-512 Conflict Detection Instructions",
126 def FeaturePFI : SubtargetFeature<"avx512pf", "HasPFI", "true",
127 "Enable AVX-512 PreFetch Instructions",
129 def FeatureDQI : SubtargetFeature<"avx512dq", "HasDQI", "true",
130 "Enable AVX-512 Doubleword and Quadword Instructions",
132 def FeatureBWI : SubtargetFeature<"avx512bw", "HasBWI", "true",
133 "Enable AVX-512 Byte and Word Instructions",
135 def FeatureVLX : SubtargetFeature<"avx512vl", "HasVLX", "true",
136 "Enable AVX-512 Vector Length eXtensions",
138 def FeaturePCLMUL : SubtargetFeature<"pclmul", "HasPCLMUL", "true",
139 "Enable packed carry-less multiplication instructions",
141 def FeatureFMA : SubtargetFeature<"fma", "HasFMA", "true",
142 "Enable three-operand fused multiple-add",
144 def FeatureFMA4 : SubtargetFeature<"fma4", "HasFMA4", "true",
145 "Enable four-operand fused multiple-add",
146 [FeatureAVX, FeatureSSE4A]>;
147 def FeatureXOP : SubtargetFeature<"xop", "HasXOP", "true",
148 "Enable XOP instructions",
150 def FeatureSSEUnalignedMem : SubtargetFeature<"sse-unaligned-mem",
151 "HasSSEUnalignedMem", "true",
152 "Allow unaligned memory operands with SSE instructions">;
153 def FeatureAES : SubtargetFeature<"aes", "HasAES", "true",
154 "Enable AES instructions",
156 def FeatureTBM : SubtargetFeature<"tbm", "HasTBM", "true",
157 "Enable TBM instructions">;
158 def FeatureMOVBE : SubtargetFeature<"movbe", "HasMOVBE", "true",
159 "Support MOVBE instruction">;
160 def FeatureRDRAND : SubtargetFeature<"rdrnd", "HasRDRAND", "true",
161 "Support RDRAND instruction">;
162 def FeatureF16C : SubtargetFeature<"f16c", "HasF16C", "true",
163 "Support 16-bit floating point conversion instructions",
165 def FeatureFSGSBase : SubtargetFeature<"fsgsbase", "HasFSGSBase", "true",
166 "Support FS/GS Base instructions">;
167 def FeatureLZCNT : SubtargetFeature<"lzcnt", "HasLZCNT", "true",
168 "Support LZCNT instruction">;
169 def FeatureBMI : SubtargetFeature<"bmi", "HasBMI", "true",
170 "Support BMI instructions">;
171 def FeatureBMI2 : SubtargetFeature<"bmi2", "HasBMI2", "true",
172 "Support BMI2 instructions">;
173 def FeatureRTM : SubtargetFeature<"rtm", "HasRTM", "true",
174 "Support RTM instructions">;
175 def FeatureHLE : SubtargetFeature<"hle", "HasHLE", "true",
177 def FeatureADX : SubtargetFeature<"adx", "HasADX", "true",
178 "Support ADX instructions">;
179 def FeatureSHA : SubtargetFeature<"sha", "HasSHA", "true",
180 "Enable SHA instructions",
182 def FeaturePRFCHW : SubtargetFeature<"prfchw", "HasPRFCHW", "true",
183 "Support PRFCHW instructions">;
184 def FeatureRDSEED : SubtargetFeature<"rdseed", "HasRDSEED", "true",
185 "Support RDSEED instruction">;
186 def FeatureMPX : SubtargetFeature<"mpx", "HasMPX", "true",
187 "Support MPX instructions">;
188 def FeatureLEAForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true",
189 "Use LEA for adjusting the stack pointer">;
190 def FeatureSlowDivide32 : SubtargetFeature<"idivl-to-divb",
191 "HasSlowDivide32", "true",
192 "Use 8-bit divide for positive values less than 256">;
193 def FeatureSlowDivide64 : SubtargetFeature<"idivq-to-divw",
194 "HasSlowDivide64", "true",
195 "Use 16-bit divide for positive values less than 65536">;
196 def FeaturePadShortFunctions : SubtargetFeature<"pad-short-functions",
197 "PadShortFunctions", "true",
198 "Pad short functions">;
199 // TODO: This feature ought to be renamed.
200 // What it really refers to are CPUs for which certain instructions
201 // (which ones besides the example below?) are microcoded.
202 // The best examples of this are the memory forms of CALL and PUSH
203 // instructions, which should be avoided in favor of a MOV + register CALL/PUSH.
204 def FeatureCallRegIndirect : SubtargetFeature<"call-reg-indirect",
205 "CallRegIndirect", "true",
206 "Call register indirect">;
207 def FeatureLEAUsesAG : SubtargetFeature<"lea-uses-ag", "LEAUsesAG", "true",
208 "LEA instruction needs inputs at AG stage">;
209 def FeatureSlowLEA : SubtargetFeature<"slow-lea", "SlowLEA", "true",
210 "LEA instruction with certain arguments is slow">;
211 def FeatureSlowIncDec : SubtargetFeature<"slow-incdec", "SlowIncDec", "true",
212 "INC and DEC instructions are slower than ADD and SUB">;
214 : SubtargetFeature<"soft-float", "UseSoftFloat", "true",
215 "Use software floating point features.">;
217 //===----------------------------------------------------------------------===//
218 // X86 processors supported.
219 //===----------------------------------------------------------------------===//
221 include "X86Schedule.td"
223 def ProcIntelAtom : SubtargetFeature<"atom", "X86ProcFamily", "IntelAtom",
224 "Intel Atom processors">;
225 def ProcIntelSLM : SubtargetFeature<"slm", "X86ProcFamily", "IntelSLM",
226 "Intel Silvermont processors">;
228 class Proc<string Name, list<SubtargetFeature> Features>
229 : ProcessorModel<Name, GenericModel, Features>;
231 def : Proc<"generic", [FeatureSlowUAMem16]>;
232 def : Proc<"i386", [FeatureSlowUAMem16]>;
233 def : Proc<"i486", [FeatureSlowUAMem16]>;
234 def : Proc<"i586", [FeatureSlowUAMem16]>;
235 def : Proc<"pentium", [FeatureSlowUAMem16]>;
236 def : Proc<"pentium-mmx", [FeatureSlowUAMem16, FeatureMMX]>;
237 def : Proc<"i686", [FeatureSlowUAMem16]>;
238 def : Proc<"pentiumpro", [FeatureSlowUAMem16, FeatureCMOV]>;
239 def : Proc<"pentium2", [FeatureSlowUAMem16, FeatureMMX, FeatureCMOV,
241 def : Proc<"pentium3", [FeatureSlowUAMem16, FeatureMMX, FeatureSSE1,
243 def : Proc<"pentium3m", [FeatureSlowUAMem16, FeatureMMX, FeatureSSE1,
244 FeatureFXSR, FeatureSlowBTMem]>;
245 def : Proc<"pentium-m", [FeatureSlowUAMem16, FeatureMMX, FeatureSSE2,
246 FeatureFXSR, FeatureSlowBTMem]>;
247 def : Proc<"pentium4", [FeatureSlowUAMem16, FeatureMMX, FeatureSSE2,
249 def : Proc<"pentium4m", [FeatureSlowUAMem16, FeatureMMX, FeatureSSE2,
250 FeatureFXSR, FeatureSlowBTMem]>;
253 def : ProcessorModel<"yonah", SandyBridgeModel,
254 [FeatureSlowUAMem16, FeatureMMX, FeatureSSE3, FeatureFXSR,
258 def : Proc<"prescott",
259 [FeatureSlowUAMem16, FeatureMMX, FeatureSSE3, FeatureFXSR,
261 def : Proc<"nocona", [
270 // Intel Core 2 Solo/Duo.
271 def : ProcessorModel<"core2", SandyBridgeModel, [
279 def : ProcessorModel<"penryn", SandyBridgeModel, [
289 class BonnellProc<string Name> : ProcessorModel<Name, AtomModel, [
301 FeatureCallRegIndirect,
303 FeaturePadShortFunctions
305 def : BonnellProc<"bonnell">;
306 def : BonnellProc<"atom">; // Pin the generic name to the baseline.
308 class SilvermontProc<string Name> : ProcessorModel<Name, SLMModel, [
319 FeatureCallRegIndirect,
325 def : SilvermontProc<"silvermont">;
326 def : SilvermontProc<"slm">; // Legacy alias.
328 // "Arrandale" along with corei3 and corei5
329 class NehalemProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
337 def : NehalemProc<"nehalem">;
338 def : NehalemProc<"corei7">;
340 // Westmere is a similar machine to nehalem with some additional features.
341 // Westmere is the corei3/i5/i7 path from nehalem to sandybridge
342 class WestmereProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
352 def : WestmereProc<"westmere">;
354 // SSE is not listed here since llvm treats AVX as a reimplementation of SSE,
355 // rather than a superset.
356 class SandyBridgeProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
369 def : SandyBridgeProc<"sandybridge">;
370 def : SandyBridgeProc<"corei7-avx">; // Legacy alias.
372 class IvyBridgeProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
388 def : IvyBridgeProc<"ivybridge">;
389 def : IvyBridgeProc<"core-avx-i">; // Legacy alias.
391 class HaswellProc<string Name> : ProcessorModel<Name, HaswellModel, [
414 def : HaswellProc<"haswell">;
415 def : HaswellProc<"core-avx2">; // Legacy alias.
417 class BroadwellProc<string Name> : ProcessorModel<Name, HaswellModel, [
442 def : BroadwellProc<"broadwell">;
444 // FIXME: define KNL model
445 class KnightsLandingProc<string Name> : ProcessorModel<Name, HaswellModel, [
471 def : KnightsLandingProc<"knl">;
473 // FIXME: define SKX model
474 class SkylakeProc<string Name> : ProcessorModel<Name, HaswellModel, [
506 def : SkylakeProc<"skylake">;
507 def : SkylakeProc<"skx">; // Legacy alias.
512 def : Proc<"k6", [FeatureSlowUAMem16, FeatureMMX]>;
513 def : Proc<"k6-2", [FeatureSlowUAMem16, Feature3DNow]>;
514 def : Proc<"k6-3", [FeatureSlowUAMem16, Feature3DNow]>;
515 def : Proc<"athlon", [FeatureSlowUAMem16, Feature3DNowA,
516 FeatureSlowBTMem, FeatureSlowSHLD]>;
517 def : Proc<"athlon-tbird", [FeatureSlowUAMem16, Feature3DNowA,
518 FeatureSlowBTMem, FeatureSlowSHLD]>;
519 def : Proc<"athlon-4", [FeatureSlowUAMem16, FeatureSSE1, Feature3DNowA,
520 FeatureFXSR, FeatureSlowBTMem, FeatureSlowSHLD]>;
521 def : Proc<"athlon-xp", [FeatureSlowUAMem16, FeatureSSE1, Feature3DNowA,
522 FeatureFXSR, FeatureSlowBTMem, FeatureSlowSHLD]>;
523 def : Proc<"athlon-mp", [FeatureSlowUAMem16, FeatureSSE1, Feature3DNowA,
524 FeatureFXSR, FeatureSlowBTMem, FeatureSlowSHLD]>;
525 def : Proc<"k8", [FeatureSlowUAMem16, FeatureSSE2, Feature3DNowA,
526 FeatureFXSR, Feature64Bit, FeatureSlowBTMem,
528 def : Proc<"opteron", [FeatureSlowUAMem16, FeatureSSE2, Feature3DNowA,
529 FeatureFXSR, Feature64Bit, FeatureSlowBTMem,
531 def : Proc<"athlon64", [FeatureSlowUAMem16, FeatureSSE2, Feature3DNowA,
532 FeatureFXSR, Feature64Bit, FeatureSlowBTMem,
534 def : Proc<"athlon-fx", [FeatureSlowUAMem16, FeatureSSE2, Feature3DNowA,
535 FeatureFXSR, Feature64Bit, FeatureSlowBTMem,
537 def : Proc<"k8-sse3", [FeatureSlowUAMem16, FeatureSSE3, Feature3DNowA,
538 FeatureFXSR, FeatureCMPXCHG16B, FeatureSlowBTMem,
540 def : Proc<"opteron-sse3", [FeatureSlowUAMem16, FeatureSSE3, Feature3DNowA,
541 FeatureFXSR, FeatureCMPXCHG16B, FeatureSlowBTMem,
543 def : Proc<"athlon64-sse3", [FeatureSlowUAMem16, FeatureSSE3, Feature3DNowA,
544 FeatureFXSR, FeatureCMPXCHG16B, FeatureSlowBTMem,
546 def : Proc<"amdfam10", [FeatureSSE4A, Feature3DNowA, FeatureFXSR,
547 FeatureCMPXCHG16B, FeatureLZCNT, FeaturePOPCNT,
548 FeatureSlowBTMem, FeatureSlowSHLD]>;
549 def : Proc<"barcelona", [FeatureSSE4A, Feature3DNowA, FeatureFXSR,
550 FeatureCMPXCHG16B, FeatureLZCNT, FeaturePOPCNT,
551 FeatureSlowBTMem, FeatureSlowSHLD]>;
554 def : Proc<"btver1", [
568 def : ProcessorModel<"btver2", BtVer2Model, [
588 def : Proc<"bdver1", [
605 def : Proc<"bdver2", [
627 def : Proc<"bdver3", [
651 def : Proc<"bdver4", [
673 def : Proc<"geode", [FeatureSlowUAMem16, Feature3DNowA]>;
675 def : Proc<"winchip-c6", [FeatureSlowUAMem16, FeatureMMX]>;
676 def : Proc<"winchip2", [FeatureSlowUAMem16, Feature3DNow]>;
677 def : Proc<"c3", [FeatureSlowUAMem16, Feature3DNow]>;
678 def : Proc<"c3-2", [FeatureSlowUAMem16, FeatureMMX, FeatureSSE1, FeatureFXSR]>;
680 // We also provide a generic 64-bit specific x86 processor model which tries to
681 // be good for modern chips without enabling instruction set encodings past the
682 // basic SSE2 and 64-bit ones. It disables slow things from any mainstream and
683 // modern 64-bit x86 chip, and enables features that are generally beneficial.
685 // We currently use the Sandy Bridge model as the default scheduling model as
686 // we use it across Nehalem, Westmere, Sandy Bridge, and Ivy Bridge which
687 // covers a huge swath of x86 processors. If there are specific scheduling
688 // knobs which need to be tuned differently for AMD chips, we might consider
689 // forming a common base for them.
690 def : ProcessorModel<"x86-64", SandyBridgeModel,
691 [FeatureMMX, FeatureSSE2, FeatureFXSR, Feature64Bit,
694 //===----------------------------------------------------------------------===//
695 // Register File Description
696 //===----------------------------------------------------------------------===//
698 include "X86RegisterInfo.td"
700 //===----------------------------------------------------------------------===//
701 // Instruction Descriptions
702 //===----------------------------------------------------------------------===//
704 include "X86InstrInfo.td"
706 def X86InstrInfo : InstrInfo;
708 //===----------------------------------------------------------------------===//
709 // Calling Conventions
710 //===----------------------------------------------------------------------===//
712 include "X86CallingConv.td"
715 //===----------------------------------------------------------------------===//
717 //===----------------------------------------------------------------------===//
719 def ATTAsmParser : AsmParser {
720 string AsmParserClassName = "AsmParser";
723 def ATTAsmParserVariant : AsmParserVariant {
729 // Discard comments in assembly strings.
730 string CommentDelimiter = "#";
732 // Recognize hard coded registers.
733 string RegisterPrefix = "%";
736 def IntelAsmParserVariant : AsmParserVariant {
740 string Name = "intel";
742 // Discard comments in assembly strings.
743 string CommentDelimiter = ";";
745 // Recognize hard coded registers.
746 string RegisterPrefix = "";
749 //===----------------------------------------------------------------------===//
751 //===----------------------------------------------------------------------===//
753 // The X86 target supports two different syntaxes for emitting machine code.
754 // This is controlled by the -x86-asm-syntax={att|intel}
755 def ATTAsmWriter : AsmWriter {
756 string AsmWriterClassName = "ATTInstPrinter";
759 def IntelAsmWriter : AsmWriter {
760 string AsmWriterClassName = "IntelInstPrinter";
765 // Information about the instructions...
766 let InstructionSet = X86InstrInfo;
767 let AssemblyParsers = [ATTAsmParser];
768 let AssemblyParserVariants = [ATTAsmParserVariant, IntelAsmParserVariant];
769 let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];