1 //===---------------------------------------------------------------------===//
2 // Random ideas for the X86 backend.
3 //===---------------------------------------------------------------------===//
6 - Support for SSE4: http://www.intel.com/software/penryn
7 http://softwarecommunity.intel.com/isn/Downloads/Intel%20SSE4%20Programming%20Reference.pdf
11 //===---------------------------------------------------------------------===//
13 CodeGen/X86/lea-3.ll:test3 should be a single LEA, not a shift/move. The X86
14 backend knows how to three-addressify this shift, but it appears the register
15 allocator isn't even asking it to do so in this case. We should investigate
16 why this isn't happening, it could have significant impact on other important
17 cases for X86 as well.
19 //===---------------------------------------------------------------------===//
21 This should be one DIV/IDIV instruction, not a libcall:
23 unsigned test(unsigned long long X, unsigned Y) {
27 This can be done trivially with a custom legalizer. What about overflow
28 though? http://gcc.gnu.org/bugzilla/show_bug.cgi?id=14224
30 //===---------------------------------------------------------------------===//
32 Improvements to the multiply -> shift/add algorithm:
33 http://gcc.gnu.org/ml/gcc-patches/2004-08/msg01590.html
35 //===---------------------------------------------------------------------===//
37 Improve code like this (occurs fairly frequently, e.g. in LLVM):
38 long long foo(int x) { return 1LL << x; }
40 http://gcc.gnu.org/ml/gcc-patches/2004-09/msg01109.html
41 http://gcc.gnu.org/ml/gcc-patches/2004-09/msg01128.html
42 http://gcc.gnu.org/ml/gcc-patches/2004-09/msg01136.html
44 Another useful one would be ~0ULL >> X and ~0ULL << X.
46 One better solution for 1LL << x is:
55 But that requires good 8-bit subreg support.
57 64-bit shifts (in general) expand to really bad code. Instead of using
58 cmovs, we should expand to a conditional branch like GCC produces.
60 //===---------------------------------------------------------------------===//
63 _Bool f(_Bool a) { return a!=1; }
70 //===---------------------------------------------------------------------===//
74 1. Dynamic programming based approach when compile time if not an
76 2. Code duplication (addressing mode) during isel.
77 3. Other ideas from "Register-Sensitive Selection, Duplication, and
78 Sequencing of Instructions".
79 4. Scheduling for reduced register pressure. E.g. "Minimum Register
80 Instruction Sequence Problem: Revisiting Optimal Code Generation for DAGs"
81 and other related papers.
82 http://citeseer.ist.psu.edu/govindarajan01minimum.html
84 //===---------------------------------------------------------------------===//
86 Should we promote i16 to i32 to avoid partial register update stalls?
88 //===---------------------------------------------------------------------===//
90 Leave any_extend as pseudo instruction and hint to register
91 allocator. Delay codegen until post register allocation.
93 //===---------------------------------------------------------------------===//
95 Count leading zeros and count trailing zeros:
97 int clz(int X) { return __builtin_clz(X); }
98 int ctz(int X) { return __builtin_ctz(X); }
100 $ gcc t.c -S -o - -O3 -fomit-frame-pointer -masm=intel
102 bsr %eax, DWORD PTR [%esp+4]
106 bsf %eax, DWORD PTR [%esp+4]
109 however, check that these are defined for 0 and 32. Our intrinsics are, GCC's
112 Another example (use predsimplify to eliminate a select):
114 int foo (unsigned long j) {
116 return __builtin_ffs (j) - 1;
121 //===---------------------------------------------------------------------===//
123 It appears icc use push for parameter passing. Need to investigate.
125 //===---------------------------------------------------------------------===//
127 Only use inc/neg/not instructions on processors where they are faster than
128 add/sub/xor. They are slower on the P4 due to only updating some processor
131 //===---------------------------------------------------------------------===//
133 The instruction selector sometimes misses folding a load into a compare. The
134 pattern is written as (cmp reg, (load p)). Because the compare isn't
135 commutative, it is not matched with the load on both sides. The dag combiner
136 should be made smart enough to cannonicalize the load into the RHS of a compare
137 when it can invert the result of the compare for free.
139 //===---------------------------------------------------------------------===//
141 How about intrinsics? An example is:
142 *res = _mm_mulhi_epu16(*A, _mm_mul_epu32(*B, *C));
145 pmuludq (%eax), %xmm0
150 The transformation probably requires a X86 specific pass or a DAG combiner
151 target specific hook.
153 //===---------------------------------------------------------------------===//
155 In many cases, LLVM generates code like this:
164 on some processors (which ones?), it is more efficient to do this:
173 Doing this correctly is tricky though, as the xor clobbers the flags.
175 //===---------------------------------------------------------------------===//
177 We should generate bts/btr/etc instructions on targets where they are cheap or
178 when codesize is important. e.g., for:
180 void setbit(int *target, int bit) {
181 *target |= (1 << bit);
183 void clearbit(int *target, int bit) {
184 *target &= ~(1 << bit);
187 //===---------------------------------------------------------------------===//
189 Instead of the following for memset char*, 1, 10:
191 movl $16843009, 4(%edx)
192 movl $16843009, (%edx)
195 It might be better to generate
202 when we can spare a register. It reduces code size.
204 //===---------------------------------------------------------------------===//
206 Evaluate what the best way to codegen sdiv X, (2^C) is. For X/8, we currently
223 GCC knows several different ways to codegen it, one of which is this:
233 which is probably slower, but it's interesting at least :)
235 //===---------------------------------------------------------------------===//
237 The first BB of this code:
241 %V = call bool %foo()
242 br bool %V, label %T, label %F
259 It would be better to emit "cmp %al, 1" than a xor and test.
261 //===---------------------------------------------------------------------===//
263 We are currently lowering large (1MB+) memmove/memcpy to rep/stosl and rep/movsl
264 We should leave these as libcalls for everything over a much lower threshold,
265 since libc is hand tuned for medium and large mem ops (avoiding RFO for large
266 stores, TLB preheating, etc)
268 //===---------------------------------------------------------------------===//
270 Optimize this into something reasonable:
271 x * copysign(1.0, y) * copysign(1.0, z)
273 //===---------------------------------------------------------------------===//
275 Optimize copysign(x, *y) to use an integer load from y.
277 //===---------------------------------------------------------------------===//
279 %X = weak global int 0
282 %N = cast int %N to uint
283 %tmp.24 = setgt int %N, 0
284 br bool %tmp.24, label %no_exit, label %return
287 %indvar = phi uint [ 0, %entry ], [ %indvar.next, %no_exit ]
288 %i.0.0 = cast uint %indvar to int
289 volatile store int %i.0.0, int* %X
290 %indvar.next = add uint %indvar, 1
291 %exitcond = seteq uint %indvar.next, %N
292 br bool %exitcond, label %return, label %no_exit
306 jl LBB_foo_4 # return
307 LBB_foo_1: # no_exit.preheader
310 movl L_X$non_lazy_ptr, %edx
314 jne LBB_foo_2 # no_exit
315 LBB_foo_3: # return.loopexit
319 We should hoist "movl L_X$non_lazy_ptr, %edx" out of the loop after
320 remateralization is implemented. This can be accomplished with 1) a target
321 dependent LICM pass or 2) makeing SelectDAG represent the whole function.
323 //===---------------------------------------------------------------------===//
325 The following tests perform worse with LSR:
327 lambda, siod, optimizer-eval, ackermann, hash2, nestedloop, strcat, and Treesor.
329 //===---------------------------------------------------------------------===//
331 We are generating far worse code than gcc:
337 for (i = 0; i < N; i++) { X = i; Y = i*4; }
340 LBB1_1: #bb.preheader
344 movl L_X$non_lazy_ptr, %esi
348 movl L_Y$non_lazy_ptr, %edi
358 movl L_X$non_lazy_ptr-"L00000000001$pb"(%ebx), %esi
359 movl L_Y$non_lazy_ptr-"L00000000001$pb"(%ebx), %ecx
362 leal 0(,%edx,4), %eax
370 1. Lack of post regalloc LICM.
371 2. LSR unable to reused IV for a different type (i16 vs. i32) even though
372 the cast would be free.
374 //===---------------------------------------------------------------------===//
376 Teach the coalescer to coalesce vregs of different register classes. e.g. FR32 /
379 //===---------------------------------------------------------------------===//
387 Obviously it would have been better for the first mov (or any op) to store
388 directly %esp[0] if there are no other uses.
390 //===---------------------------------------------------------------------===//
392 Adding to the list of cmp / test poor codegen issues:
394 int test(__m128 *A, __m128 *B) {
395 if (_mm_comige_ss(*A, *B))
415 Note the setae, movzbl, cmpl, cmove can be replaced with a single cmovae. There
416 are a number of issues. 1) We are introducing a setcc between the result of the
417 intrisic call and select. 2) The intrinsic is expected to produce a i32 value
418 so a any extend (which becomes a zero extend) is added.
420 We probably need some kind of target DAG combine hook to fix this.
422 //===---------------------------------------------------------------------===//
424 We generate significantly worse code for this than GCC:
425 http://gcc.gnu.org/bugzilla/show_bug.cgi?id=21150
426 http://gcc.gnu.org/bugzilla/attachment.cgi?id=8701
428 There is also one case we do worse on PPC.
430 //===---------------------------------------------------------------------===//
432 If shorter, we should use things like:
437 The former can also be used when the two-addressy nature of the 'and' would
438 require a copy to be inserted (in X86InstrInfo::convertToThreeAddress).
440 //===---------------------------------------------------------------------===//
444 typedef struct pair { float A, B; } pair;
445 void pairtest(pair P, float *FP) {
449 We currently generate this code with llvmgcc4:
461 we should be able to generate:
469 The issue is that llvmgcc4 is forcing the struct to memory, then passing it as
470 integer chunks. It does this so that structs like {short,short} are passed in
471 a single 32-bit integer stack slot. We should handle the safe cases above much
472 nicer, while still handling the hard cases.
474 While true in general, in this specific case we could do better by promoting
475 load int + bitcast to float -> load fload. This basically needs alignment info,
476 the code is already implemented (but disabled) in dag combine).
478 //===---------------------------------------------------------------------===//
480 Another instruction selector deficiency:
483 %tmp = load int (int)** %foo
484 %tmp = tail call int %tmp( int 3 )
490 movl L_foo$non_lazy_ptr, %eax
496 The current isel scheme will not allow the load to be folded in the call since
497 the load's chain result is read by the callseq_start.
499 //===---------------------------------------------------------------------===//
509 imull $3, 4(%esp), %eax
511 Perhaps this is what we really should generate is? Is imull three or four
512 cycles? Note: ICC generates this:
514 leal (%eax,%eax,2), %eax
516 The current instruction priority is based on pattern complexity. The former is
517 more "complex" because it folds a load so the latter will not be emitted.
519 Perhaps we should use AddedComplexity to give LEA32r a higher priority? We
520 should always try to match LEA first since the LEA matching code does some
521 estimate to determine whether the match is profitable.
523 However, if we care more about code size, then imull is better. It's two bytes
524 shorter than movl + leal.
526 //===---------------------------------------------------------------------===//
528 Implement CTTZ, CTLZ with bsf and bsr. GCC produces:
530 int ctz_(unsigned X) { return __builtin_ctz(X); }
531 int clz_(unsigned X) { return __builtin_clz(X); }
532 int ffs_(unsigned X) { return __builtin_ffs(X); }
548 //===---------------------------------------------------------------------===//
550 It appears gcc place string data with linkonce linkage in
551 .section __TEXT,__const_coal,coalesced instead of
552 .section __DATA,__const_coal,coalesced.
553 Take a look at darwin.h, there are other Darwin assembler directives that we
556 //===---------------------------------------------------------------------===//
558 int %foo(int* %a, int %t) {
562 cond_true: ; preds = %cond_true, %entry
563 %x.0.0 = phi int [ 0, %entry ], [ %tmp9, %cond_true ]
564 %t_addr.0.0 = phi int [ %t, %entry ], [ %tmp7, %cond_true ]
565 %tmp2 = getelementptr int* %a, int %x.0.0
566 %tmp3 = load int* %tmp2 ; <int> [#uses=1]
567 %tmp5 = add int %t_addr.0.0, %x.0.0 ; <int> [#uses=1]
568 %tmp7 = add int %tmp5, %tmp3 ; <int> [#uses=2]
569 %tmp9 = add int %x.0.0, 1 ; <int> [#uses=2]
570 %tmp = setgt int %tmp9, 39 ; <bool> [#uses=1]
571 br bool %tmp, label %bb12, label %cond_true
573 bb12: ; preds = %cond_true
577 is pessimized by -loop-reduce and -indvars
579 //===---------------------------------------------------------------------===//
581 u32 to float conversion improvement:
583 float uint32_2_float( unsigned u ) {
584 float fl = (int) (u & 0xffff);
585 float fh = (int) (u >> 16);
590 00000000 subl $0x04,%esp
591 00000003 movl 0x08(%esp,1),%eax
592 00000007 movl %eax,%ecx
593 00000009 shrl $0x10,%ecx
594 0000000c cvtsi2ss %ecx,%xmm0
595 00000010 andl $0x0000ffff,%eax
596 00000015 cvtsi2ss %eax,%xmm1
597 00000019 mulss 0x00000078,%xmm0
598 00000021 addss %xmm1,%xmm0
599 00000025 movss %xmm0,(%esp,1)
600 0000002a flds (%esp,1)
601 0000002d addl $0x04,%esp
604 //===---------------------------------------------------------------------===//
606 When using fastcc abi, align stack slot of argument of type double on 8 byte
607 boundary to improve performance.
609 //===---------------------------------------------------------------------===//
613 int f(int a, int b) {
614 if (a == 4 || a == 6)
626 //===---------------------------------------------------------------------===//
628 GCC's ix86_expand_int_movcc function (in i386.c) has a ton of interesting
629 simplifications for integer "x cmp y ? a : b". For example, instead of:
632 void f(int X, int Y) {
658 //===---------------------------------------------------------------------===//
660 Currently we don't have elimination of redundant stack manipulations. Consider
665 call fastcc void %test1( )
666 call fastcc void %test2( sbyte* cast (void ()* %test1 to sbyte*) )
670 declare fastcc void %test1()
672 declare fastcc void %test2(sbyte*)
675 This currently compiles to:
685 The add\sub pair is really unneeded here.
687 //===---------------------------------------------------------------------===//
689 We currently compile sign_extend_inreg into two shifts:
692 return (long)(signed char)X;
709 //===---------------------------------------------------------------------===//
711 Consider the expansion of:
713 uint %test3(uint %X) {
714 %tmp1 = rem uint %X, 255
718 Currently it compiles to:
721 movl $2155905153, %ecx
727 This could be "reassociated" into:
729 movl $2155905153, %eax
733 to avoid the copy. In fact, the existing two-address stuff would do this
734 except that mul isn't a commutative 2-addr instruction. I guess this has
735 to be done at isel time based on the #uses to mul?
737 //===---------------------------------------------------------------------===//
739 Make sure the instruction which starts a loop does not cross a cacheline
740 boundary. This requires knowning the exact length of each machine instruction.
741 That is somewhat complicated, but doable. Example 256.bzip2:
743 In the new trace, the hot loop has an instruction which crosses a cacheline
744 boundary. In addition to potential cache misses, this can't help decoding as I
745 imagine there has to be some kind of complicated decoder reset and realignment
746 to grab the bytes from the next cacheline.
748 532 532 0x3cfc movb (1809(%esp, %esi), %bl <<<--- spans 2 64 byte lines
749 942 942 0x3d03 movl %dh, (1809(%esp, %esi)
750 937 937 0x3d0a incl %esi
751 3 3 0x3d0b cmpb %bl, %dl
752 27 27 0x3d0d jnz 0x000062db <main+11707>
754 //===---------------------------------------------------------------------===//
756 In c99 mode, the preprocessor doesn't like assembly comments like #TRUNCATE.
758 //===---------------------------------------------------------------------===//
760 This could be a single 16-bit load.
763 if ((p[0] == 1) & (p[1] == 2)) return 1;
767 //===---------------------------------------------------------------------===//
769 We should inline lrintf and probably other libc functions.
771 //===---------------------------------------------------------------------===//
773 Start using the flags more. For example, compile:
775 int add_zf(int *x, int y, int a, int b) {
799 int add_zf(int *x, int y, int a, int b) {
823 //===---------------------------------------------------------------------===//
827 int foo(double X) { return isnan(X); }
838 the pxor is not needed, we could compare the value against itself.
840 //===---------------------------------------------------------------------===//
842 These two functions have identical effects:
844 unsigned int f(unsigned int i, unsigned int n) {++i; if (i == n) ++i; return i;}
845 unsigned int f2(unsigned int i, unsigned int n) {++i; i += i == n; return i;}
847 We currently compile them to:
855 jne LBB1_2 #UnifiedReturnBlock
859 LBB1_2: #UnifiedReturnBlock
869 leal 1(%ecx,%eax), %eax
872 both of which are inferior to GCC's:
890 //===---------------------------------------------------------------------===//
898 is currently compiled to:
909 It would be better to produce:
918 This can be applied to any no-return function call that takes no arguments etc.
919 Alternatively, the stack save/restore logic could be shrink-wrapped, producing
930 Both are useful in different situations. Finally, it could be shrink-wrapped
931 and tail called, like this:
938 pop %eax # realign stack.
941 Though this probably isn't worth it.
943 //===---------------------------------------------------------------------===//
945 We need to teach the codegen to convert two-address INC instructions to LEA
946 when the flags are dead (likewise dec). For example, on X86-64, compile:
948 int foo(int A, int B) {
967 ;; X's live range extends beyond the shift, so the register allocator
968 ;; cannot coalesce it with Y. Because of this, a copy needs to be
969 ;; emitted before the shift to save the register value before it is
970 ;; clobbered. However, this copy is not needed if the register
971 ;; allocator turns the shift into an LEA. This also occurs for ADD.
973 ; Check that the shift gets turned into an LEA.
974 ; RUN: llvm-upgrade < %s | llvm-as | llc -march=x86 -x86-asm-syntax=intel | \
975 ; RUN: not grep {mov E.X, E.X}
977 %G = external global int
979 int %test1(int %X, int %Y) {
981 volatile store int %Y, int* %G
982 volatile store int %Z, int* %G
987 %Z = add int %X, 1 ;; inc
988 volatile store int %Z, int* %G
992 //===---------------------------------------------------------------------===//
995 #include <xmmintrin.h>
996 unsigned test(float f) {
997 return _mm_cvtsi128_si32( (__m128i) _mm_set_ss( f ));
1002 movss 4(%esp), %xmm0
1006 it should compile to a move from the stack slot directly into eax. DAGCombine
1007 has this xform, but it is currently disabled until the alignment fields of
1008 the load/store nodes are trustworthy.
1010 //===---------------------------------------------------------------------===//
1012 Sometimes it is better to codegen subtractions from a constant (e.g. 7-x) with
1013 a neg instead of a sub instruction. Consider:
1015 int test(char X) { return 7-X; }
1017 we currently produce:
1020 movsbl 4(%esp), %ecx
1024 We would use one fewer register if codegen'd as:
1026 movsbl 4(%esp), %eax
1031 Note that this isn't beneficial if the load can be folded into the sub. In
1032 this case, we want a sub:
1034 int test(int X) { return 7-X; }
1040 //===---------------------------------------------------------------------===//
1045 We get an implicit def on the undef side. If the phi is spilled, we then get:
1049 It should be possible to teach the x86 backend to "fold" the store into the
1050 implicitdef, which just deletes the implicit def.
1052 These instructions should go away:
1054 movaps %xmm1, 192(%esp)
1055 movaps %xmm1, 224(%esp)
1056 movaps %xmm1, 176(%esp)
1058 //===---------------------------------------------------------------------===//
1060 This is a "commutable two-address" register coallescing deficiency:
1062 define <4 x float> @test1(<4 x float> %V) {
1064 %tmp8 = shufflevector <4 x float> %V, <4 x float> undef,
1065 <4 x i32> < i32 3, i32 2, i32 1, i32 0 >
1066 %add = add <4 x float> %tmp8, %V
1067 ret <4 x float> %add
1073 pshufd $27, %xmm0, %xmm1
1081 pshufd $27, %xmm0, %xmm1
1085 //===---------------------------------------------------------------------===//
1087 Leaf functions that require one 4-byte spill slot have a prolog like this:
1093 and an epilog like this:
1098 It would be smaller, and potentially faster, to push eax on entry and to
1099 pop into a dummy register instead of using addl/subl of esp. Just don't pop
1100 into any return registers :)
1102 //===---------------------------------------------------------------------===//
1104 The X86 backend should fold (branch (or (setcc, setcc))) into multiple
1105 branches. We generate really poor code for:
1107 double testf(double a) {
1108 return a == 0.0 ? 0.0 : (a > 0.0 ? 1.0 : -1.0);
1111 For example, the entry BB is:
1116 movsd 24(%esp), %xmm1
1117 ucomisd %xmm0, %xmm1
1121 jne LBB1_5 # UnifiedReturnBlock
1125 it would be better to replace the last four instructions with:
1131 We also codegen the inner ?: into a diamond:
1133 cvtss2sd LCPI1_0(%rip), %xmm2
1134 cvtss2sd LCPI1_1(%rip), %xmm3
1135 ucomisd %xmm1, %xmm0
1136 ja LBB1_3 # cond_true
1143 We should sink the load into xmm3 into the LBB1_2 block. This should
1144 be pretty easy, and will nuke all the copies.
1146 //===---------------------------------------------------------------------===//
1149 #include <algorithm>
1150 inline std::pair<unsigned, bool> full_add(unsigned a, unsigned b)
1151 { return std::make_pair(a + b, a + b < a); }
1152 bool no_overflow(unsigned a, unsigned b)
1153 { return !full_add(a, b).second; }
1173 //===---------------------------------------------------------------------===//
1175 Re-materialize MOV32r0 etc. with xor instead of changing them to moves if the
1176 condition register is dead. xor reg reg is shorter than mov reg, #0.
1178 //===---------------------------------------------------------------------===//
1180 We aren't matching RMW instructions aggressively
1181 enough. Here's a reduced testcase (more in PR1160):
1183 define void @test(i32* %huge_ptr, i32* %target_ptr) {
1184 %A = load i32* %huge_ptr ; <i32> [#uses=1]
1185 %B = load i32* %target_ptr ; <i32> [#uses=1]
1186 %C = or i32 %A, %B ; <i32> [#uses=1]
1187 store i32 %C, i32* %target_ptr
1191 $ llvm-as < t.ll | llc -march=x86-64
1199 That should be something like:
1206 //===---------------------------------------------------------------------===//
1210 bb114.preheader: ; preds = %cond_next94
1211 %tmp231232 = sext i16 %tmp62 to i32 ; <i32> [#uses=1]
1212 %tmp233 = sub i32 32, %tmp231232 ; <i32> [#uses=1]
1213 %tmp245246 = sext i16 %tmp65 to i32 ; <i32> [#uses=1]
1214 %tmp252253 = sext i16 %tmp68 to i32 ; <i32> [#uses=1]
1215 %tmp254 = sub i32 32, %tmp252253 ; <i32> [#uses=1]
1216 %tmp553554 = bitcast i16* %tmp37 to i8* ; <i8*> [#uses=2]
1217 %tmp583584 = sext i16 %tmp98 to i32 ; <i32> [#uses=1]
1218 %tmp585 = sub i32 32, %tmp583584 ; <i32> [#uses=1]
1219 %tmp614615 = sext i16 %tmp101 to i32 ; <i32> [#uses=1]
1220 %tmp621622 = sext i16 %tmp104 to i32 ; <i32> [#uses=1]
1221 %tmp623 = sub i32 32, %tmp621622 ; <i32> [#uses=1]
1226 LBB3_5: # bb114.preheader
1227 movswl -68(%ebp), %eax
1229 movl %ecx, -80(%ebp)
1230 subl %eax, -80(%ebp)
1231 movswl -52(%ebp), %eax
1232 movl %ecx, -84(%ebp)
1233 subl %eax, -84(%ebp)
1234 movswl -70(%ebp), %eax
1235 movl %ecx, -88(%ebp)
1236 subl %eax, -88(%ebp)
1237 movswl -50(%ebp), %eax
1239 movl %ecx, -76(%ebp)
1240 movswl -42(%ebp), %eax
1241 movl %eax, -92(%ebp)
1242 movswl -66(%ebp), %eax
1243 movl %eax, -96(%ebp)
1246 This appears to be bad because the RA is not folding the store to the stack
1247 slot into the movl. The above instructions could be:
1252 This seems like a cross between remat and spill folding.
1254 This has redundant subtractions of %eax from a stack slot. However, %ecx doesn't
1255 change, so we could simply subtract %eax from %ecx first and then use %ecx (or
1258 //===---------------------------------------------------------------------===//
1262 cond_next603: ; preds = %bb493, %cond_true336, %cond_next599
1263 %v.21050.1 = phi i32 [ %v.21050.0, %cond_next599 ], [ %tmp344, %cond_true336 ], [ %v.2, %bb493 ] ; <i32> [#uses=1]
1264 %maxz.21051.1 = phi i32 [ %maxz.21051.0, %cond_next599 ], [ 0, %cond_true336 ], [ %maxz.2, %bb493 ] ; <i32> [#uses=2]
1265 %cnt.01055.1 = phi i32 [ %cnt.01055.0, %cond_next599 ], [ 0, %cond_true336 ], [ %cnt.0, %bb493 ] ; <i32> [#uses=2]
1266 %byteptr.9 = phi i8* [ %byteptr.12, %cond_next599 ], [ %byteptr.0, %cond_true336 ], [ %byteptr.10, %bb493 ] ; <i8*> [#uses=9]
1267 %bitptr.6 = phi i32 [ %tmp5571104.1, %cond_next599 ], [ %tmp4921049, %cond_true336 ], [ %bitptr.7, %bb493 ] ; <i32> [#uses=4]
1268 %source.5 = phi i32 [ %tmp602, %cond_next599 ], [ %source.0, %cond_true336 ], [ %source.6, %bb493 ] ; <i32> [#uses=7]
1269 %tmp606 = getelementptr %struct.const_tables* @tables, i32 0, i32 0, i32 %cnt.01055.1 ; <i8*> [#uses=1]
1270 %tmp607 = load i8* %tmp606, align 1 ; <i8> [#uses=1]
1274 LBB4_70: # cond_next603
1275 movl -20(%ebp), %esi
1276 movl L_tables$non_lazy_ptr-"L4$pb"(%esi), %esi
1278 However, ICC caches this information before the loop and produces this:
1280 movl 88(%esp), %eax #481.12
1282 //===---------------------------------------------------------------------===//
1286 %tmp659 = icmp slt i16 %tmp654, 0 ; <i1> [#uses=1]
1287 br i1 %tmp659, label %cond_true662, label %cond_next715
1293 jns LBB4_109 # cond_next715
1295 Shark tells us that using %cx in the testw instruction is sub-optimal. It
1296 suggests using the 32-bit register (which is what ICC uses).
1298 //===---------------------------------------------------------------------===//
1300 rdar://5506677 - We compile this:
1302 define i32 @foo(double %x) {
1303 %x14 = bitcast double %x to i64 ; <i64> [#uses=1]
1304 %tmp713 = trunc i64 %x14 to i32 ; <i32> [#uses=1]
1305 %tmp8 = and i32 %tmp713, 2147483647 ; <i32> [#uses=1]
1315 movl $2147483647, %eax
1321 It would be much better to eliminate the fldl/fstpl by folding the bitcast
1322 into the load SDNode. That would give us:
1325 movl $2147483647, %eax
1329 //===---------------------------------------------------------------------===//
1333 void compare (long long foo) {
1334 if (foo < 4294967297LL)
1351 je LBB1_2 # cond_true
1353 (also really horrible code on ppc). This is due to the expand code for 64-bit
1354 compares. GCC produces multiple branches, which is much nicer:
1370 //===---------------------------------------------------------------------===//
1371 Tail call optimization improvements: Tail call optimization currently
1372 pushes all arguments on the top of the stack (their normal place if
1373 that was a not tail call optimized functiong call ) before moving them
1374 to actual stack slot. this is done to prevent overwriting of paramters
1375 (see example below) that might be used, since the arguments of the
1376 callee overwrites callers arguments.
1380 int callee(int32, int64);
1381 int caller(int32 arg1, int32 arg2) {
1382 int64 local = arg2 * 2;
1383 return callee(arg2, (int64)local);
1386 [arg1] [!arg2 no longer valid since we moved local onto it]
1390 moving arg1 onto the stack slot of callee function would overwrite
1393 Possible optimizations:
1395 - only push those arguments to the top of the stack that are actual
1396 parameters of the caller function and have no local value in the
1399 in above example local does not need to be pushed onto the top of
1400 the stack as it is definitetly not a caller's function parameter
1402 - analyse the actual parameters of the callee to see which would
1403 overwrite a caller paramter which is used by the callee and only
1404 push them onto the top of the stack
1406 int callee (int32 arg1, int32 arg2);
1407 int caller (int32 arg1, int32 arg2) {
1408 return callee(arg1,arg2);
1411 here we don't need to write any variables to the top of the stack
1412 since they don't overwrite each other
1414 int callee (int32 arg1, int32 arg2);
1415 int caller (int32 arg1, int32 arg2) {
1416 return callee(arg2,arg1);
1419 here we need to push the arguments because they overwrite each other
1422 code for lowering directly onto callers arguments:
1423 + SmallVector<std::pair<unsigned, SDOperand>, 8> RegsToPass;
1424 + SmallVector<SDOperand, 8> MemOpChains;
1426 + SDOperand FramePtr;
1430 + // Walk the register/memloc assignments, inserting copies/loads.
1431 + for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1432 + CCValAssign &VA = ArgLocs[i];
1433 + SDOperand Arg = Op.getOperand(5+2*VA.getValNo());
1437 + if (VA.isRegLoc()) {
1438 + RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1440 + assert(VA.isMemLoc());
1441 + // create frame index
1442 + int32_t Offset = VA.getLocMemOffset()+FPDiff;
1443 + uint32_t OpSize = (MVT::getSizeInBits(VA.getLocVT())+7)/8;
1444 + FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset);
1445 + FIN = DAG.getFrameIndex(FI, MVT::i32);
1446 + // store relative to framepointer
1447 + MemOpChains.push_back(DAG.getStore(Chain, Arg, FIN, NULL, 0));
1450 //===---------------------------------------------------------------------===//