1 //===-- X86MCTargetDesc.cpp - X86 Target Descriptions -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file provides X86 specific target descriptions.
12 //===----------------------------------------------------------------------===//
14 #include "X86MCTargetDesc.h"
15 #include "X86MCAsmInfo.h"
16 #include "InstPrinter/X86ATTInstPrinter.h"
17 #include "InstPrinter/X86IntelInstPrinter.h"
18 #include "llvm/MC/MachineLocation.h"
19 #include "llvm/MC/MCCodeGenInfo.h"
20 #include "llvm/MC/MCInstrAnalysis.h"
21 #include "llvm/MC/MCInstrInfo.h"
22 #include "llvm/MC/MCRegisterInfo.h"
23 #include "llvm/MC/MCStreamer.h"
24 #include "llvm/MC/MCSubtargetInfo.h"
25 #include "llvm/ADT/Triple.h"
26 #include "llvm/Support/Host.h"
27 #include "llvm/Support/TargetRegistry.h"
29 #define GET_REGINFO_MC_DESC
30 #include "X86GenRegisterInfo.inc"
32 #define GET_INSTRINFO_MC_DESC
33 #include "X86GenInstrInfo.inc"
35 #define GET_SUBTARGETINFO_MC_DESC
36 #include "X86GenSubtargetInfo.inc"
41 std::string X86_MC::ParseX86Triple(StringRef TT) {
44 if (TheTriple.getArch() == Triple::x86_64)
48 if (TheTriple.getOS() == Triple::NativeClient)
55 /// GetCpuIDAndInfo - Execute the specified cpuid and return the 4 values in the
56 /// specified arguments. If we can't run cpuid on the host, return true.
57 bool X86_MC::GetCpuIDAndInfo(unsigned value, unsigned *rEAX,
58 unsigned *rEBX, unsigned *rECX, unsigned *rEDX) {
59 #if defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
61 // gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually.
62 asm ("movq\t%%rbx, %%rsi\n\t"
64 "xchgq\t%%rbx, %%rsi\n\t"
71 #elif defined(_MSC_VER)
73 __cpuid(registers, value);
80 #elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
82 asm ("movl\t%%ebx, %%esi\n\t"
84 "xchgl\t%%ebx, %%esi\n\t"
91 #elif defined(_MSC_VER)
96 mov dword ptr [esi],eax
98 mov dword ptr [esi],ebx
100 mov dword ptr [esi],ecx
102 mov dword ptr [esi],edx
110 /// GetCpuIDAndInfoEx - Execute the specified cpuid with subleaf and return the
111 /// 4 values in the specified arguments. If we can't run cpuid on the host,
113 bool X86_MC::GetCpuIDAndInfoEx(unsigned value, unsigned subleaf, unsigned *rEAX,
114 unsigned *rEBX, unsigned *rECX, unsigned *rEDX) {
115 #if defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
116 #if defined(__GNUC__)
117 // gcc desn't know cpuid would clobber ebx/rbx. Preseve it manually.
118 asm ("movq\t%%rbx, %%rsi\n\t"
120 "xchgq\t%%rbx, %%rsi\n\t"
128 #elif defined(_MSC_VER)
129 // can't use __cpuidex because it isn't available in all supported versions
136 mov dword ptr [rsi],eax
138 mov dword ptr [rsi],ebx
140 mov dword ptr [rsi],ecx
142 mov dword ptr [rsi],edx
146 #elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
147 #if defined(__GNUC__)
148 asm ("movl\t%%ebx, %%esi\n\t"
150 "xchgl\t%%ebx, %%esi\n\t"
158 #elif defined(_MSC_VER)
164 mov dword ptr [esi],eax
166 mov dword ptr [esi],ebx
168 mov dword ptr [esi],ecx
170 mov dword ptr [esi],edx
178 void X86_MC::DetectFamilyModel(unsigned EAX, unsigned &Family,
180 Family = (EAX >> 8) & 0xf; // Bits 8 - 11
181 Model = (EAX >> 4) & 0xf; // Bits 4 - 7
182 if (Family == 6 || Family == 0xf) {
184 // Examine extended family ID if family ID is F.
185 Family += (EAX >> 20) & 0xff; // Bits 20 - 27
186 // Examine extended model ID if family ID is 6 or F.
187 Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19
191 unsigned X86_MC::getDwarfRegFlavour(StringRef TT, bool isEH) {
192 Triple TheTriple(TT);
193 if (TheTriple.getArch() == Triple::x86_64)
194 return DWARFFlavour::X86_64;
196 if (TheTriple.isOSDarwin())
197 return isEH ? DWARFFlavour::X86_32_DarwinEH : DWARFFlavour::X86_32_Generic;
198 if (TheTriple.getOS() == Triple::MinGW32 ||
199 TheTriple.getOS() == Triple::Cygwin)
200 // Unsupported by now, just quick fallback
201 return DWARFFlavour::X86_32_Generic;
202 return DWARFFlavour::X86_32_Generic;
205 /// getX86RegNum - This function maps LLVM register identifiers to their X86
206 /// specific numbering, which is used in various places encoding instructions.
207 unsigned X86_MC::getX86RegNum(unsigned RegNo) {
209 case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
210 case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
211 case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
212 case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
213 case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
215 case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
217 case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
219 case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
222 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
224 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
226 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
228 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
230 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
232 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
234 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
236 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
239 case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
240 case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
241 return RegNo-X86::ST0;
243 case X86::XMM0: case X86::XMM8:
244 case X86::YMM0: case X86::YMM8: case X86::MM0:
246 case X86::XMM1: case X86::XMM9:
247 case X86::YMM1: case X86::YMM9: case X86::MM1:
249 case X86::XMM2: case X86::XMM10:
250 case X86::YMM2: case X86::YMM10: case X86::MM2:
252 case X86::XMM3: case X86::XMM11:
253 case X86::YMM3: case X86::YMM11: case X86::MM3:
255 case X86::XMM4: case X86::XMM12:
256 case X86::YMM4: case X86::YMM12: case X86::MM4:
258 case X86::XMM5: case X86::XMM13:
259 case X86::YMM5: case X86::YMM13: case X86::MM5:
261 case X86::XMM6: case X86::XMM14:
262 case X86::YMM6: case X86::YMM14: case X86::MM6:
264 case X86::XMM7: case X86::XMM15:
265 case X86::YMM7: case X86::YMM15: case X86::MM7:
268 case X86::ES: return 0;
269 case X86::CS: return 1;
270 case X86::SS: return 2;
271 case X86::DS: return 3;
272 case X86::FS: return 4;
273 case X86::GS: return 5;
275 case X86::CR0: case X86::CR8 : case X86::DR0: return 0;
276 case X86::CR1: case X86::CR9 : case X86::DR1: return 1;
277 case X86::CR2: case X86::CR10: case X86::DR2: return 2;
278 case X86::CR3: case X86::CR11: case X86::DR3: return 3;
279 case X86::CR4: case X86::CR12: case X86::DR4: return 4;
280 case X86::CR5: case X86::CR13: case X86::DR5: return 5;
281 case X86::CR6: case X86::CR14: case X86::DR6: return 6;
282 case X86::CR7: case X86::CR15: case X86::DR7: return 7;
284 // Pseudo index registers are equivalent to a "none"
285 // scaled index (See Intel Manual 2A, table 2-3)
291 assert((int(RegNo) > 0) && "Unknown physical register!");
296 void X86_MC::InitLLVM2SEHRegisterMapping(MCRegisterInfo *MRI) {
297 // FIXME: TableGen these.
298 for (unsigned Reg = X86::NoRegister+1; Reg < X86::NUM_TARGET_REGS; ++Reg) {
299 int SEH = X86_MC::getX86RegNum(Reg);
301 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
302 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
303 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
304 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
305 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
306 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
307 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
308 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
309 case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11:
310 case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15:
311 case X86::YMM8: case X86::YMM9: case X86::YMM10: case X86::YMM11:
312 case X86::YMM12: case X86::YMM13: case X86::YMM14: case X86::YMM15:
316 MRI->mapLLVMRegToSEHReg(Reg, SEH);
320 MCSubtargetInfo *X86_MC::createX86MCSubtargetInfo(StringRef TT, StringRef CPU,
322 std::string ArchFS = X86_MC::ParseX86Triple(TT);
325 ArchFS = ArchFS + "," + FS.str();
330 std::string CPUName = CPU;
331 if (CPUName.empty()) {
332 #if defined (__x86_64__) || defined(__i386__)
333 CPUName = sys::getHostCPUName();
339 MCSubtargetInfo *X = new MCSubtargetInfo();
340 InitX86MCSubtargetInfo(X, TT, CPUName, ArchFS);
344 static MCInstrInfo *createX86MCInstrInfo() {
345 MCInstrInfo *X = new MCInstrInfo();
346 InitX86MCInstrInfo(X);
350 static MCRegisterInfo *createX86MCRegisterInfo(StringRef TT) {
351 Triple TheTriple(TT);
352 unsigned RA = (TheTriple.getArch() == Triple::x86_64)
353 ? X86::RIP // Should have dwarf #16.
354 : X86::EIP; // Should have dwarf #8.
356 MCRegisterInfo *X = new MCRegisterInfo();
357 InitX86MCRegisterInfo(X, RA,
358 X86_MC::getDwarfRegFlavour(TT, false),
359 X86_MC::getDwarfRegFlavour(TT, true));
360 X86_MC::InitLLVM2SEHRegisterMapping(X);
364 static MCAsmInfo *createX86MCAsmInfo(const Target &T, StringRef TT) {
365 Triple TheTriple(TT);
366 bool is64Bit = TheTriple.getArch() == Triple::x86_64;
369 if (TheTriple.isOSDarwin() || TheTriple.getEnvironment() == Triple::MachO) {
371 MAI = new X86_64MCAsmInfoDarwin(TheTriple);
373 MAI = new X86MCAsmInfoDarwin(TheTriple);
374 } else if (TheTriple.isOSWindows()) {
375 MAI = new X86MCAsmInfoCOFF(TheTriple);
377 MAI = new X86ELFMCAsmInfo(TheTriple);
380 // Initialize initial frame state.
381 // Calculate amount of bytes used for return address storing
382 int stackGrowth = is64Bit ? -8 : -4;
384 // Initial state of the frame pointer is esp+stackGrowth.
385 MachineLocation Dst(MachineLocation::VirtualFP);
386 MachineLocation Src(is64Bit ? X86::RSP : X86::ESP, stackGrowth);
387 MAI->addInitialFrameState(0, Dst, Src);
389 // Add return address to move list
390 MachineLocation CSDst(is64Bit ? X86::RSP : X86::ESP, stackGrowth);
391 MachineLocation CSSrc(is64Bit ? X86::RIP : X86::EIP);
392 MAI->addInitialFrameState(0, CSDst, CSSrc);
397 static MCCodeGenInfo *createX86MCCodeGenInfo(StringRef TT, Reloc::Model RM,
398 CodeModel::Model CM) {
399 MCCodeGenInfo *X = new MCCodeGenInfo();
402 bool is64Bit = T.getArch() == Triple::x86_64;
404 if (RM == Reloc::Default) {
405 // Darwin defaults to PIC in 64 bit mode and dynamic-no-pic in 32 bit mode.
406 // Win64 requires rip-rel addressing, thus we force it to PIC. Otherwise we
407 // use static relocation model by default.
408 if (T.isOSDarwin()) {
412 RM = Reloc::DynamicNoPIC;
413 } else if (T.isOSWindows() && is64Bit)
419 // ELF and X86-64 don't have a distinct DynamicNoPIC model. DynamicNoPIC
420 // is defined as a model for code which may be used in static or dynamic
421 // executables but not necessarily a shared library. On X86-32 we just
422 // compile in -static mode, in x86-64 we use PIC.
423 if (RM == Reloc::DynamicNoPIC) {
426 else if (!T.isOSDarwin())
430 // If we are on Darwin, disallow static relocation model in X86-64 mode, since
431 // the Mach-O file format doesn't support it.
432 if (RM == Reloc::Static && T.isOSDarwin() && is64Bit)
435 // For static codegen, if we're not already set, use Small codegen.
436 if (CM == CodeModel::Default)
437 CM = CodeModel::Small;
438 else if (CM == CodeModel::JITDefault)
439 // 64-bit JIT places everything in the same buffer except external funcs.
440 CM = is64Bit ? CodeModel::Large : CodeModel::Small;
442 X->InitMCCodeGenInfo(RM, CM);
446 static MCStreamer *createMCStreamer(const Target &T, StringRef TT,
447 MCContext &Ctx, MCAsmBackend &MAB,
449 MCCodeEmitter *_Emitter,
452 Triple TheTriple(TT);
454 if (TheTriple.isOSDarwin() || TheTriple.getEnvironment() == Triple::MachO)
455 return createMachOStreamer(Ctx, MAB, _OS, _Emitter, RelaxAll);
457 if (TheTriple.isOSWindows())
458 return createWinCOFFStreamer(Ctx, MAB, *_Emitter, _OS, RelaxAll);
460 return createELFStreamer(Ctx, MAB, _OS, _Emitter, RelaxAll, NoExecStack);
463 static MCInstPrinter *createX86MCInstPrinter(const Target &T,
464 unsigned SyntaxVariant,
465 const MCAsmInfo &MAI,
466 const MCSubtargetInfo &STI) {
467 if (SyntaxVariant == 0)
468 return new X86ATTInstPrinter(MAI);
469 if (SyntaxVariant == 1)
470 return new X86IntelInstPrinter(MAI);
474 static MCInstrAnalysis *createX86MCInstrAnalysis(const MCInstrInfo *Info) {
475 return new MCInstrAnalysis(Info);
478 // Force static initialization.
479 extern "C" void LLVMInitializeX86TargetMC() {
480 // Register the MC asm info.
481 RegisterMCAsmInfoFn A(TheX86_32Target, createX86MCAsmInfo);
482 RegisterMCAsmInfoFn B(TheX86_64Target, createX86MCAsmInfo);
484 // Register the MC codegen info.
485 RegisterMCCodeGenInfoFn C(TheX86_32Target, createX86MCCodeGenInfo);
486 RegisterMCCodeGenInfoFn D(TheX86_64Target, createX86MCCodeGenInfo);
488 // Register the MC instruction info.
489 TargetRegistry::RegisterMCInstrInfo(TheX86_32Target, createX86MCInstrInfo);
490 TargetRegistry::RegisterMCInstrInfo(TheX86_64Target, createX86MCInstrInfo);
492 // Register the MC register info.
493 TargetRegistry::RegisterMCRegInfo(TheX86_32Target, createX86MCRegisterInfo);
494 TargetRegistry::RegisterMCRegInfo(TheX86_64Target, createX86MCRegisterInfo);
496 // Register the MC subtarget info.
497 TargetRegistry::RegisterMCSubtargetInfo(TheX86_32Target,
498 X86_MC::createX86MCSubtargetInfo);
499 TargetRegistry::RegisterMCSubtargetInfo(TheX86_64Target,
500 X86_MC::createX86MCSubtargetInfo);
502 // Register the MC instruction analyzer.
503 TargetRegistry::RegisterMCInstrAnalysis(TheX86_32Target,
504 createX86MCInstrAnalysis);
505 TargetRegistry::RegisterMCInstrAnalysis(TheX86_64Target,
506 createX86MCInstrAnalysis);
508 // Register the code emitter.
509 TargetRegistry::RegisterMCCodeEmitter(TheX86_32Target,
510 createX86MCCodeEmitter);
511 TargetRegistry::RegisterMCCodeEmitter(TheX86_64Target,
512 createX86MCCodeEmitter);
514 // Register the asm backend.
515 TargetRegistry::RegisterMCAsmBackend(TheX86_32Target,
516 createX86_32AsmBackend);
517 TargetRegistry::RegisterMCAsmBackend(TheX86_64Target,
518 createX86_64AsmBackend);
520 // Register the object streamer.
521 TargetRegistry::RegisterMCObjectStreamer(TheX86_32Target,
523 TargetRegistry::RegisterMCObjectStreamer(TheX86_64Target,
526 // Register the MCInstPrinter.
527 TargetRegistry::RegisterMCInstPrinter(TheX86_32Target,
528 createX86MCInstPrinter);
529 TargetRegistry::RegisterMCInstPrinter(TheX86_64Target,
530 createX86MCInstPrinter);