1 //===-- X86MCTargetDesc.cpp - X86 Target Descriptions ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file provides X86 specific target descriptions.
12 //===----------------------------------------------------------------------===//
14 #include "X86MCTargetDesc.h"
15 #include "InstPrinter/X86ATTInstPrinter.h"
16 #include "InstPrinter/X86IntelInstPrinter.h"
17 #include "X86MCAsmInfo.h"
18 #include "llvm/ADT/Triple.h"
19 #include "llvm/MC/MCCodeGenInfo.h"
20 #include "llvm/MC/MCInstrAnalysis.h"
21 #include "llvm/MC/MCInstrInfo.h"
22 #include "llvm/MC/MCRegisterInfo.h"
23 #include "llvm/MC/MCStreamer.h"
24 #include "llvm/MC/MCSubtargetInfo.h"
25 #include "llvm/MC/MachineLocation.h"
26 #include "llvm/Support/ErrorHandling.h"
27 #include "llvm/Support/Host.h"
28 #include "llvm/Support/TargetRegistry.h"
36 #define GET_REGINFO_MC_DESC
37 #include "X86GenRegisterInfo.inc"
39 #define GET_INSTRINFO_MC_DESC
40 #include "X86GenInstrInfo.inc"
42 #define GET_SUBTARGETINFO_MC_DESC
43 #include "X86GenSubtargetInfo.inc"
45 std::string X86_MC::ParseX86Triple(StringRef TT) {
48 if (TheTriple.getArch() == Triple::x86_64)
49 FS = "+64bit-mode,-32bit-mode,-16bit-mode";
50 else if (TheTriple.getEnvironment() != Triple::CODE16)
51 FS = "-64bit-mode,+32bit-mode,-16bit-mode";
53 FS = "-64bit-mode,-32bit-mode,+16bit-mode";
58 /// GetCpuIDAndInfo - Execute the specified cpuid and return the 4 values in the
59 /// specified arguments. If we can't run cpuid on the host, return true.
60 bool X86_MC::GetCpuIDAndInfo(unsigned value, unsigned *rEAX,
61 unsigned *rEBX, unsigned *rECX, unsigned *rEDX) {
62 #if defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
64 // gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually.
65 asm ("movq\t%%rbx, %%rsi\n\t"
67 "xchgq\t%%rbx, %%rsi\n\t"
74 #elif defined(_MSC_VER)
76 __cpuid(registers, value);
85 #elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
87 asm ("movl\t%%ebx, %%esi\n\t"
89 "xchgl\t%%ebx, %%esi\n\t"
96 #elif defined(_MSC_VER)
101 mov dword ptr [esi],eax
103 mov dword ptr [esi],ebx
105 mov dword ptr [esi],ecx
107 mov dword ptr [esi],edx
118 /// GetCpuIDAndInfoEx - Execute the specified cpuid with subleaf and return the
119 /// 4 values in the specified arguments. If we can't run cpuid on the host,
121 bool X86_MC::GetCpuIDAndInfoEx(unsigned value, unsigned subleaf, unsigned *rEAX,
122 unsigned *rEBX, unsigned *rECX, unsigned *rEDX) {
123 #if defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
124 #if defined(__GNUC__)
125 // gcc desn't know cpuid would clobber ebx/rbx. Preseve it manually.
126 asm ("movq\t%%rbx, %%rsi\n\t"
128 "xchgq\t%%rbx, %%rsi\n\t"
136 #elif defined(_MSC_VER)
138 __cpuidex(registers, value, subleaf);
139 *rEAX = registers[0];
140 *rEBX = registers[1];
141 *rECX = registers[2];
142 *rEDX = registers[3];
147 #elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
148 #if defined(__GNUC__)
149 asm ("movl\t%%ebx, %%esi\n\t"
151 "xchgl\t%%ebx, %%esi\n\t"
159 #elif defined(_MSC_VER)
165 mov dword ptr [esi],eax
167 mov dword ptr [esi],ebx
169 mov dword ptr [esi],ecx
171 mov dword ptr [esi],edx
182 void X86_MC::DetectFamilyModel(unsigned EAX, unsigned &Family,
184 Family = (EAX >> 8) & 0xf; // Bits 8 - 11
185 Model = (EAX >> 4) & 0xf; // Bits 4 - 7
186 if (Family == 6 || Family == 0xf) {
188 // Examine extended family ID if family ID is F.
189 Family += (EAX >> 20) & 0xff; // Bits 20 - 27
190 // Examine extended model ID if family ID is 6 or F.
191 Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19
195 unsigned X86_MC::getDwarfRegFlavour(Triple TT, bool isEH) {
196 if (TT.getArch() == Triple::x86_64)
197 return DWARFFlavour::X86_64;
200 return isEH ? DWARFFlavour::X86_32_DarwinEH : DWARFFlavour::X86_32_Generic;
201 if (TT.isOSCygMing())
202 // Unsupported by now, just quick fallback
203 return DWARFFlavour::X86_32_Generic;
204 return DWARFFlavour::X86_32_Generic;
207 void X86_MC::InitLLVM2SEHRegisterMapping(MCRegisterInfo *MRI) {
208 // FIXME: TableGen these.
209 for (unsigned Reg = X86::NoRegister+1; Reg < X86::NUM_TARGET_REGS; ++Reg) {
210 unsigned SEH = MRI->getEncodingValue(Reg);
211 MRI->mapLLVMRegToSEHReg(Reg, SEH);
215 MCSubtargetInfo *X86_MC::createX86MCSubtargetInfo(StringRef TT, StringRef CPU,
217 std::string ArchFS = X86_MC::ParseX86Triple(TT);
220 ArchFS = ArchFS + "," + FS.str();
225 std::string CPUName = CPU;
229 MCSubtargetInfo *X = new MCSubtargetInfo();
230 InitX86MCSubtargetInfo(X, TT, CPUName, ArchFS);
234 static MCInstrInfo *createX86MCInstrInfo() {
235 MCInstrInfo *X = new MCInstrInfo();
236 InitX86MCInstrInfo(X);
240 static MCRegisterInfo *createX86MCRegisterInfo(StringRef TT) {
241 Triple TheTriple(TT);
242 unsigned RA = (TheTriple.getArch() == Triple::x86_64)
243 ? X86::RIP // Should have dwarf #16.
244 : X86::EIP; // Should have dwarf #8.
246 MCRegisterInfo *X = new MCRegisterInfo();
247 InitX86MCRegisterInfo(X, RA,
248 X86_MC::getDwarfRegFlavour(TheTriple, false),
249 X86_MC::getDwarfRegFlavour(TheTriple, true),
251 X86_MC::InitLLVM2SEHRegisterMapping(X);
255 static MCAsmInfo *createX86MCAsmInfo(const MCRegisterInfo &MRI, StringRef TT) {
256 Triple TheTriple(TT);
257 bool is64Bit = TheTriple.getArch() == Triple::x86_64;
260 if (TheTriple.isOSBinFormatMachO()) {
262 MAI = new X86_64MCAsmInfoDarwin(TheTriple);
264 MAI = new X86MCAsmInfoDarwin(TheTriple);
265 } else if (TheTriple.isOSBinFormatELF()) {
266 // Force the use of an ELF container.
267 MAI = new X86ELFMCAsmInfo(TheTriple);
268 } else if (TheTriple.isWindowsMSVCEnvironment()) {
269 MAI = new X86MCAsmInfoMicrosoft(TheTriple);
270 } else if (TheTriple.isOSCygMing() ||
271 TheTriple.isWindowsItaniumEnvironment()) {
272 MAI = new X86MCAsmInfoGNUCOFF(TheTriple);
274 // The default is ELF.
275 MAI = new X86ELFMCAsmInfo(TheTriple);
278 // Initialize initial frame state.
279 // Calculate amount of bytes used for return address storing
280 int stackGrowth = is64Bit ? -8 : -4;
282 // Initial state of the frame pointer is esp+stackGrowth.
283 unsigned StackPtr = is64Bit ? X86::RSP : X86::ESP;
284 MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(
285 nullptr, MRI.getDwarfRegNum(StackPtr, true), -stackGrowth);
286 MAI->addInitialFrameState(Inst);
288 // Add return address to move list
289 unsigned InstPtr = is64Bit ? X86::RIP : X86::EIP;
290 MCCFIInstruction Inst2 = MCCFIInstruction::createOffset(
291 nullptr, MRI.getDwarfRegNum(InstPtr, true), stackGrowth);
292 MAI->addInitialFrameState(Inst2);
297 static MCCodeGenInfo *createX86MCCodeGenInfo(StringRef TT, Reloc::Model RM,
299 CodeGenOpt::Level OL) {
300 MCCodeGenInfo *X = new MCCodeGenInfo();
303 bool is64Bit = T.getArch() == Triple::x86_64;
305 if (RM == Reloc::Default) {
306 // Darwin defaults to PIC in 64 bit mode and dynamic-no-pic in 32 bit mode.
307 // Win64 requires rip-rel addressing, thus we force it to PIC. Otherwise we
308 // use static relocation model by default.
309 if (T.isOSDarwin()) {
313 RM = Reloc::DynamicNoPIC;
314 } else if (T.isOSWindows() && is64Bit)
320 // ELF and X86-64 don't have a distinct DynamicNoPIC model. DynamicNoPIC
321 // is defined as a model for code which may be used in static or dynamic
322 // executables but not necessarily a shared library. On X86-32 we just
323 // compile in -static mode, in x86-64 we use PIC.
324 if (RM == Reloc::DynamicNoPIC) {
327 else if (!T.isOSDarwin())
331 // If we are on Darwin, disallow static relocation model in X86-64 mode, since
332 // the Mach-O file format doesn't support it.
333 if (RM == Reloc::Static && T.isOSDarwin() && is64Bit)
336 // For static codegen, if we're not already set, use Small codegen.
337 if (CM == CodeModel::Default)
338 CM = CodeModel::Small;
339 else if (CM == CodeModel::JITDefault)
340 // 64-bit JIT places everything in the same buffer except external funcs.
341 CM = is64Bit ? CodeModel::Large : CodeModel::Small;
343 X->InitMCCodeGenInfo(RM, CM, OL);
347 static MCStreamer *createMCStreamer(const Target &T, StringRef TT,
348 MCContext &Ctx, MCAsmBackend &MAB,
349 raw_ostream &OS, MCCodeEmitter *Emitter,
350 const MCSubtargetInfo &STI, bool RelaxAll) {
351 Triple TheTriple(TT);
353 switch (TheTriple.getObjectFormat()) {
354 default: llvm_unreachable("unsupported object format");
356 return createMachOStreamer(Ctx, MAB, OS, Emitter, RelaxAll);
358 assert(TheTriple.isOSWindows() && "only Windows COFF is supported");
359 return createX86WinCOFFStreamer(Ctx, MAB, Emitter, OS, RelaxAll);
361 return createELFStreamer(Ctx, MAB, OS, Emitter, RelaxAll);
365 static MCInstPrinter *createX86MCInstPrinter(const Target &T,
366 unsigned SyntaxVariant,
367 const MCAsmInfo &MAI,
368 const MCInstrInfo &MII,
369 const MCRegisterInfo &MRI,
370 const MCSubtargetInfo &STI) {
371 if (SyntaxVariant == 0)
372 return new X86ATTInstPrinter(MAI, MII, MRI, STI);
373 if (SyntaxVariant == 1)
374 return new X86IntelInstPrinter(MAI, MII, MRI);
378 static MCRelocationInfo *createX86MCRelocationInfo(StringRef TT,
380 Triple TheTriple(TT);
381 if (TheTriple.isOSBinFormatMachO() && TheTriple.getArch() == Triple::x86_64)
382 return createX86_64MachORelocationInfo(Ctx);
383 else if (TheTriple.isOSBinFormatELF())
384 return createX86_64ELFRelocationInfo(Ctx);
385 // Default to the stock relocation info.
386 return llvm::createMCRelocationInfo(TT, Ctx);
389 static MCInstrAnalysis *createX86MCInstrAnalysis(const MCInstrInfo *Info) {
390 return new MCInstrAnalysis(Info);
393 // Force static initialization.
394 extern "C" void LLVMInitializeX86TargetMC() {
395 // Register the MC asm info.
396 RegisterMCAsmInfoFn A(TheX86_32Target, createX86MCAsmInfo);
397 RegisterMCAsmInfoFn B(TheX86_64Target, createX86MCAsmInfo);
399 // Register the MC codegen info.
400 RegisterMCCodeGenInfoFn C(TheX86_32Target, createX86MCCodeGenInfo);
401 RegisterMCCodeGenInfoFn D(TheX86_64Target, createX86MCCodeGenInfo);
403 // Register the MC instruction info.
404 TargetRegistry::RegisterMCInstrInfo(TheX86_32Target, createX86MCInstrInfo);
405 TargetRegistry::RegisterMCInstrInfo(TheX86_64Target, createX86MCInstrInfo);
407 // Register the MC register info.
408 TargetRegistry::RegisterMCRegInfo(TheX86_32Target, createX86MCRegisterInfo);
409 TargetRegistry::RegisterMCRegInfo(TheX86_64Target, createX86MCRegisterInfo);
411 // Register the MC subtarget info.
412 TargetRegistry::RegisterMCSubtargetInfo(TheX86_32Target,
413 X86_MC::createX86MCSubtargetInfo);
414 TargetRegistry::RegisterMCSubtargetInfo(TheX86_64Target,
415 X86_MC::createX86MCSubtargetInfo);
417 // Register the MC instruction analyzer.
418 TargetRegistry::RegisterMCInstrAnalysis(TheX86_32Target,
419 createX86MCInstrAnalysis);
420 TargetRegistry::RegisterMCInstrAnalysis(TheX86_64Target,
421 createX86MCInstrAnalysis);
423 // Register the code emitter.
424 TargetRegistry::RegisterMCCodeEmitter(TheX86_32Target,
425 createX86MCCodeEmitter);
426 TargetRegistry::RegisterMCCodeEmitter(TheX86_64Target,
427 createX86MCCodeEmitter);
429 // Register the asm backend.
430 TargetRegistry::RegisterMCAsmBackend(TheX86_32Target,
431 createX86_32AsmBackend);
432 TargetRegistry::RegisterMCAsmBackend(TheX86_64Target,
433 createX86_64AsmBackend);
435 // Register the object streamer.
436 TargetRegistry::RegisterMCObjectStreamer(TheX86_32Target,
438 TargetRegistry::RegisterMCObjectStreamer(TheX86_64Target,
441 // Register the MCInstPrinter.
442 TargetRegistry::RegisterMCInstPrinter(TheX86_32Target,
443 createX86MCInstPrinter);
444 TargetRegistry::RegisterMCInstPrinter(TheX86_64Target,
445 createX86MCInstPrinter);
447 // Register the MC relocation info.
448 TargetRegistry::RegisterMCRelocationInfo(TheX86_32Target,
449 createX86MCRelocationInfo);
450 TargetRegistry::RegisterMCRelocationInfo(TheX86_64Target,
451 createX86MCRelocationInfo);